diff --git a/.clang-format b/.clang-format
index 1cc151e2adcc..6a3de86ab27a 100644
--- a/.clang-format
+++ b/.clang-format
@@ -481,6 +481,7 @@ ForEachMacros:
   - 'genradix_for_each'
   - 'genradix_for_each_from'
   - 'genradix_for_each_reverse'
+  - 'guard'
   - 'hash_for_each'
   - 'hash_for_each_possible'
   - 'hash_for_each_possible_rcu'
@@ -674,6 +675,7 @@ ForEachMacros:
   - 'rq_list_for_each'
   - 'rq_list_for_each_safe'
   - 'sample_read_group__for_each'
+  - 'scoped_guard'
   - 'scsi_for_each_prot_sg'
   - 'scsi_for_each_sg'
   - 'sctp_for_each_hentry'
diff --git a/.mailmap b/.mailmap
index 34acd34bbf9b..8a3204280eb2 100644
--- a/.mailmap
+++ b/.mailmap
@@ -207,6 +207,7 @@ Claudiu Beznea <claudiu.beznea@tuxon.dev> <claudiu.beznea@microchip.com>
 Colin Ian King <colin.i.king@gmail.com> <colin.king@canonical.com>
 Corey Minyard <minyard@acm.org>
 Damian Hobson-Garcia <dhobsong@igel.co.jp>
+Dan Carpenter <error27@gmail.com> <dan.carpenter@linaro.org>
 Dan Carpenter <error27@gmail.com> <dan.carpenter@oracle.com>
 Dan Williams <djbw@kernel.org> <dan.j.williams@intel.com>
 Daniel Borkmann <daniel@iogearbox.net> <danborkmann@googlemail.com>
@@ -495,6 +496,7 @@ Leon Romanovsky <leon@kernel.org> <leon@leon.nu>
 Leon Romanovsky <leon@kernel.org> <leonro@mellanox.com>
 Leon Romanovsky <leon@kernel.org> <leonro@nvidia.com>
 Leo Yan <leo.yan@linux.dev> <leo.yan@linaro.org>
+Liam R. Howlett <liam@infradead.org> <Liam.Howlett@oracle.com>
 Liam Mark <quic_lmark@quicinc.com> <lmark@codeaurora.org>
 Linas Vepstas <linas@austin.ibm.com>
 Linus Lüssing <linus.luessing@c0d3.blue> <linus.luessing@ascom.ch>
@@ -505,6 +507,8 @@ Linus Walleij <linusw@kernel.org> <linus.walleij@stericsson.com>
 Linus Walleij <linusw@kernel.org> <linus.walleij@linaro.org>
 Linus Walleij <linusw@kernel.org> <triad@df.lth.se>
 <linux-hardening@vger.kernel.org> <kernel-hardening@lists.openwall.com>
+Li Wang <li.wang@linux.dev> <liwang@redhat.com>
+Li Wang <li.wang@linux.dev> <wangli.ahau@gmail.com>
 Li Yang <leoyang.li@nxp.com> <leoli@freescale.com>
 Li Yang <leoyang.li@nxp.com> <leo@zh-kernel.org>
 Lior David <quic_liord@quicinc.com> <liord@codeaurora.org>
@@ -687,6 +691,7 @@ Punit Agrawal <punitagrawal@gmail.com> <punit.agrawal@arm.com>
 Puranjay Mohan <puranjay@kernel.org> <puranjay12@gmail.com>
 Qais Yousef <qyousef@layalina.io> <qais.yousef@imgtec.com>
 Qais Yousef <qyousef@layalina.io> <qais.yousef@arm.com>
+Qi Zheng <qi.zheng@linux.dev> <zhengqi.arch@bytedance.com>
 Quentin Monnet <qmo@kernel.org> <quentin.monnet@netronome.com>
 Quentin Monnet <qmo@kernel.org> <quentin@isovalent.com>
 Quentin Perret <qperret@qperret.net> <quentin.perret@arm.com>
diff --git a/Documentation/admin-guide/index.rst b/Documentation/admin-guide/index.rst
index cd28dfe91b06..37456e08fe43 100644
--- a/Documentation/admin-guide/index.rst
+++ b/Documentation/admin-guide/index.rst
@@ -73,6 +73,7 @@ problems and bugs in particular.
    ramoops
    dynamic-debug-howto
    init
+   kallsyms-lineinfo
    kdump/index
    perf/index
    pstore-blk
diff --git a/Documentation/admin-guide/kallsyms-lineinfo.rst b/Documentation/admin-guide/kallsyms-lineinfo.rst
new file mode 100644
index 000000000000..dd264830c8d5
--- /dev/null
+++ b/Documentation/admin-guide/kallsyms-lineinfo.rst
@@ -0,0 +1,97 @@
+.. SPDX-License-Identifier: GPL-2.0
+
+====================================
+Kallsyms Source Line Info (LINEINFO)
+====================================
+
+Overview
+========
+
+``CONFIG_KALLSYMS_LINEINFO`` embeds DWARF-derived source file and line number
+mappings into the kernel image so that stack traces include
+``(file.c:123)`` annotations next to each symbol.  This makes it significantly
+easier to pinpoint the exact source location during debugging, without needing
+to manually cross-reference addresses with ``addr2line``.
+
+Enabling the Feature
+====================
+
+Enable the following kernel configuration options::
+
+    CONFIG_KALLSYMS=y
+    CONFIG_DEBUG_INFO=y
+    CONFIG_KALLSYMS_LINEINFO=y
+
+Build dependency: the host tool ``scripts/gen_lineinfo`` requires ``libdw``
+from elfutils.  Install the development package:
+
+- Debian/Ubuntu: ``apt install libdw-dev``
+- Fedora/RHEL: ``dnf install elfutils-devel``
+- Arch Linux: ``pacman -S elfutils``
+
+Example Output
+==============
+
+Without ``CONFIG_KALLSYMS_LINEINFO``::
+
+    Call Trace:
+     <TASK>
+     dump_stack_lvl+0x5d/0x80
+     do_syscall_64+0x82/0x190
+     entry_SYSCALL_64_after_hwframe+0x76/0x7e
+
+With ``CONFIG_KALLSYMS_LINEINFO``::
+
+    Call Trace:
+     <TASK>
+     dump_stack_lvl+0x5d/0x80 (lib/dump_stack.c:123)
+     do_syscall_64+0x82/0x190 (arch/x86/entry/common.c:52)
+     entry_SYSCALL_64_after_hwframe+0x76/0x7e
+
+Note that assembly routines (such as ``entry_SYSCALL_64_after_hwframe``) are
+not annotated because they lack DWARF debug information.
+
+Module Support
+==============
+
+``CONFIG_KALLSYMS_LINEINFO_MODULES`` extends the feature to loadable kernel
+modules.  When enabled, each ``.ko`` is post-processed at build time to embed
+a ``.mod_lineinfo`` section containing the same kind of address-to-source
+mapping.
+
+Enable in addition to the base options::
+
+    CONFIG_MODULES=y
+    CONFIG_KALLSYMS_LINEINFO_MODULES=y
+
+Stack traces from module code will then include annotations::
+
+    my_driver_func+0x30/0x100 [my_driver] (drivers/foo/bar.c:123)
+
+The ``.mod_lineinfo`` section is loaded into read-only module memory alongside
+the module text.  No additional runtime memory allocation is required; the data
+is freed when the module is unloaded.
+
+Memory Overhead
+===============
+
+The vmlinux lineinfo tables are stored in ``.rodata`` and typically add
+approximately 10-15 MiB to the kernel image for a standard configuration
+(~4.6 million DWARF line entries, ~2-3 bytes per entry after delta
+compression).
+
+Per-module lineinfo adds approximately 2-3 bytes per DWARF line entry to each
+``.ko`` file.
+
+Known Limitations
+=================
+
+- **4 GiB offset limit**: Address offsets from ``_text`` (vmlinux) or
+  ``.text`` base (modules) are stored as 32-bit values.  Entries beyond
+  4 GiB are skipped at build time with a warning.
+- **65535 file limit**: Source file IDs are stored as 16-bit values.  Builds
+  with more than 65535 unique source files will fail with an error.
+- **No assembly annotations**: Functions implemented in assembly that lack
+  DWARF ``.debug_line`` data are not annotated.
+- **No init text**: For modules, functions in ``.init.text`` are not annotated
+  because that memory is freed after module initialization.
diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt
index 4d0f545fb3ec..41c657cd362c 100644
--- a/Documentation/admin-guide/kernel-parameters.txt
+++ b/Documentation/admin-guide/kernel-parameters.txt
@@ -7888,6 +7888,22 @@ Kernel parameters
 			first trust source as a backend which is initialized
 			successfully during iteration.
 
+	trusted.debug=	[KEYS]
+			Format: <bool>
+			Enable trusted keys debug traces at runtime when
+			CONFIG_TRUSTED_KEYS_DEBUG=y.
+
+			To make the traces visible after enabling the option,
+			use trusted.dyndbg='+p' as needed. By convention,
+			the subsystem uses pr_debug() for these traces.
+
+			SAFETY: The traces can leak sensitive data, so be
+			cautious before enabling this. They remain inactive
+			unless this parameter is set this option to  a true
+			value.
+
+			Default: false
+
 	trusted.rng=	[KEYS]
 			Format: <string>
 			The RNG used to generate key material for trusted keys.
diff --git a/Documentation/admin-guide/sysctl/kernel.rst b/Documentation/admin-guide/sysctl/kernel.rst
index c6994e55d141..f9c972a8e152 100644
--- a/Documentation/admin-guide/sysctl/kernel.rst
+++ b/Documentation/admin-guide/sysctl/kernel.rst
@@ -170,6 +170,7 @@ core_pattern
 	%d		dump mode, matches ``PR_SET_DUMPABLE`` and
 			``/proc/sys/fs/suid_dumpable``
 	%s		signal number
+	%n		signal code
 	%t		UNIX time of dump
 	%h		hostname
 	%e		executable filename (may be shortened, could be changed by prctl etc)
diff --git a/Documentation/atomic_t.txt b/Documentation/atomic_t.txt
index bee3b1bca9a7..0e53f6ccb558 100644
--- a/Documentation/atomic_t.txt
+++ b/Documentation/atomic_t.txt
@@ -16,6 +16,10 @@ Non-RMW ops:
   atomic_read(), atomic_set()
   atomic_read_acquire(), atomic_set_release()
 
+Non-RMW, non-atomic_t ops:
+
+  atomic_cond_read_{relaxed,acquire}()
+  atomic_cond_read_{relaxed,acquire}_timeout()
 
 RMW atomic operations:
 
@@ -79,11 +83,11 @@ SEMANTICS
 
 Non-RMW ops:
 
-The non-RMW ops are (typically) regular LOADs and STOREs and are canonically
-implemented using READ_ONCE(), WRITE_ONCE(), smp_load_acquire() and
-smp_store_release() respectively. Therefore, if you find yourself only using
-the Non-RMW operations of atomic_t, you do not in fact need atomic_t at all
-and are doing it wrong.
+The non-RMW ops are (typically) regular, or conditional LOADs and STOREs and
+are canonically implemented using READ_ONCE(), WRITE_ONCE(),
+smp_load_acquire() and smp_store_release() respectively. Therefore, if you
+find yourself only using the Non-RMW operations of atomic_t, you do not in
+fact need atomic_t at all and are doing it wrong.
 
 A note for the implementation of atomic_set{}() is that it must not break the
 atomicity of the RMW ops. That is:
diff --git a/Documentation/block/biovecs.rst b/Documentation/block/biovecs.rst
index 11126ed6f40f..b9dc0c9dbee4 100644
--- a/Documentation/block/biovecs.rst
+++ b/Documentation/block/biovecs.rst
@@ -135,6 +135,7 @@ Usage of helpers:
 	bio_first_bvec_all()
 	bio_first_page_all()
 	bio_first_folio_all()
+	bio_last_bvec_all()
 
 * The following helpers iterate over single-page segment. The passed 'struct
   bio_vec' will contain a single-page IO vector during the iteration::
diff --git a/Documentation/dev-tools/checkpatch.rst b/Documentation/dev-tools/checkpatch.rst
index dccede68698c..6139a08c34cd 100644
--- a/Documentation/dev-tools/checkpatch.rst
+++ b/Documentation/dev-tools/checkpatch.rst
@@ -184,6 +184,13 @@ Available options:
    Override checking of perl version.  Runtime errors may be encountered after
    enabling this flag if the perl version does not meet the minimum specified.
 
+ - --spdx-cxx-comments
+
+   Don't force C comments ``/* */`` for SPDX license (required by old
+   toolchains), allow also C++ comments ``//``.
+
+   NOTE: it should *not* be used for Linux mainline.
+
  - --codespell
 
    Use the codespell dictionary for checking spelling errors.
@@ -210,6 +217,13 @@ Available options:
 
    Display the help text.
 
+Configuration file
+==================
+
+Default configuration options can be stored in ``.checkpatch.conf``, search
+path: ``.:$HOME:.scripts`` or in a directory specified by ``$CHECKPATCH_CONFIG_DIR``
+environment variable (falling back to the default search path).
+
 Message Levels
 ==============
 
diff --git a/Documentation/devicetree/bindings/input/touchscreen/st,stmfts.yaml b/Documentation/devicetree/bindings/input/touchscreen/st,stmfts.yaml
index 12256ae7df90..64c4f24ea3dd 100644
--- a/Documentation/devicetree/bindings/input/touchscreen/st,stmfts.yaml
+++ b/Documentation/devicetree/bindings/input/touchscreen/st,stmfts.yaml
@@ -40,6 +40,10 @@ properties:
   vdd-supply:
     description: Power supply
 
+  reset-gpios:
+    description: Reset GPIO (active-low)
+    maxItems: 1
+
 required:
   - compatible
   - reg
diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
index e0267223887e..639bbeb1f6bd 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
@@ -71,6 +71,7 @@ properties:
       - items:
           - enum:
               - allwinner,sun20i-d1-plic
+              - canaan,k230-plic
               - sophgo,cv1800b-plic
               - sophgo,cv1812h-plic
               - sophgo,sg2002-plic
diff --git a/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml b/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml
index 7c4d6170491d..f5c584cf2146 100644
--- a/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml
+++ b/Documentation/devicetree/bindings/mailbox/qcom-ipcc.yaml
@@ -24,6 +24,7 @@ properties:
   compatible:
     items:
       - enum:
+          - qcom,eliza-ipcc
           - qcom,glymur-ipcc
           - qcom,kaanapali-ipcc
           - qcom,milos-ipcc
diff --git a/Documentation/devicetree/bindings/regulator/mt6360-regulator.yaml b/Documentation/devicetree/bindings/regulator/mt6360-regulator.yaml
index 9c879bc3c360..cbb74e8e875d 100644
--- a/Documentation/devicetree/bindings/regulator/mt6360-regulator.yaml
+++ b/Documentation/devicetree/bindings/regulator/mt6360-regulator.yaml
@@ -17,6 +17,10 @@ properties:
   compatible:
     const: mediatek,mt6360-regulator
 
+  BUCK1_VIN-supply:
+    description: Input supply phandle(s) for BUCK1
+  BUCK2_VIN-supply:
+    description: Input supply phandle(s) for BUCK2
   LDO_VIN1-supply:
     description: Input supply phandle(s) for LDO1/2/3
   LDO_VIN2-supply:
diff --git a/Documentation/devicetree/bindings/riscv/canaan.yaml b/Documentation/devicetree/bindings/riscv/canaan.yaml
index 41fd11f70a49..f9854ff43ac6 100644
--- a/Documentation/devicetree/bindings/riscv/canaan.yaml
+++ b/Documentation/devicetree/bindings/riscv/canaan.yaml
@@ -10,7 +10,7 @@ maintainers:
   - Damien Le Moal <dlemoal@kernel.org>
 
 description:
-  Canaan Kendryte K210 SoC-based boards
+  Canaan Kendryte SoC-based boards
 
 properties:
   $nodename:
@@ -42,6 +42,12 @@ properties:
       - items:
           - const: canaan,kendryte-k210
 
+      - items:
+          - enum:
+              - canaan,canmv-k230
+              - canaan,k230-usip-lp3-evb
+          - const: canaan,kendryte-k230
+
 additionalProperties: true
 
 ...
diff --git a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-irqmux.yaml b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-irqmux.yaml
index 51164772724f..419b32e2df93 100644
--- a/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-irqmux.yaml
+++ b/Documentation/devicetree/bindings/soc/microchip/microchip,mpfs-irqmux.yaml
@@ -26,7 +26,11 @@ description: |
 
 properties:
   compatible:
-    const: microchip,mpfs-irqmux
+    oneOf:
+      - items:
+          - const: microchip,pic64gx-irqmux
+          - const: microchip,mpfs-irqmux
+      - const: microchip,mpfs-irqmux
 
   reg:
     maxItems: 1
diff --git a/Documentation/devicetree/bindings/timer/fsl,imxgpt.yaml b/Documentation/devicetree/bindings/timer/fsl,imxgpt.yaml
index 9898dc7ea97b..6d41fb120379 100644
--- a/Documentation/devicetree/bindings/timer/fsl,imxgpt.yaml
+++ b/Documentation/devicetree/bindings/timer/fsl,imxgpt.yaml
@@ -14,6 +14,7 @@ properties:
     oneOf:
       - const: fsl,imx1-gpt
       - const: fsl,imx21-gpt
+      - const: fsl,imx25-epit
       - items:
           - const: fsl,imx27-gpt
           - const: fsl,imx21-gpt
diff --git a/Documentation/devicetree/bindings/timer/renesas,rz-mtu3.yaml b/Documentation/devicetree/bindings/timer/renesas,rz-mtu3.yaml
index 3ad10c5b66ba..ecff2912d812 100644
--- a/Documentation/devicetree/bindings/timer/renesas,rz-mtu3.yaml
+++ b/Documentation/devicetree/bindings/timer/renesas,rz-mtu3.yaml
@@ -112,6 +112,8 @@ properties:
           - renesas,r9a07g043-mtu3  # RZ/{G2UL,Five}
           - renesas,r9a07g044-mtu3  # RZ/G2{L,LC}
           - renesas,r9a07g054-mtu3  # RZ/V2L
+          - renesas,r9a09g077-mtu3  # RZ/T2H
+          - renesas,r9a09g087-mtu3  # RZ/N2H
       - const: renesas,rz-mtu3
 
   reg:
@@ -162,7 +164,6 @@ properties:
       - description: MTU8.TGRC input capture/compare match
       - description: MTU8.TGRD input capture/compare match
       - description: MTU8.TCNT overflow
-      - description: MTU8.TCNT underflow
 
   interrupt-names:
     items:
@@ -209,7 +210,6 @@ properties:
       - const: tgic8
       - const: tgid8
       - const: tciv8
-      - const: tciu8
 
   clocks:
     maxItems: 1
@@ -233,7 +233,22 @@ required:
   - interrupt-names
   - clocks
   - power-domains
-  - resets
+
+allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - renesas,r9a07g043-mtu3
+              - renesas,r9a07g044-mtu3
+              - renesas,r9a07g054-mtu3
+    then:
+      required:
+        - resets
+    else:
+      properties:
+        resets: false
 
 additionalProperties: false
 
@@ -287,8 +302,7 @@ examples:
                    <GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
                    <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>,
                    <GIC_SPI 211 IRQ_TYPE_EDGE_RISING>,
-                   <GIC_SPI 212 IRQ_TYPE_EDGE_RISING>,
-                   <GIC_SPI 213 IRQ_TYPE_EDGE_RISING>;
+                   <GIC_SPI 212 IRQ_TYPE_EDGE_RISING>;
       interrupt-names = "tgia0", "tgib0", "tgic0", "tgid0", "tciv0", "tgie0",
                         "tgif0",
                         "tgia1", "tgib1", "tciv1", "tciu1",
@@ -298,7 +312,7 @@ examples:
                         "tgiu5", "tgiv5", "tgiw5",
                         "tgia6", "tgib6", "tgic6", "tgid6", "tciv6",
                         "tgia7", "tgib7", "tgic7", "tgid7", "tciv7",
-                        "tgia8", "tgib8", "tgic8", "tgid8", "tciv8", "tciu8";
+                        "tgia8", "tgib8", "tgic8", "tgid8", "tciv8";
       clocks = <&cpg CPG_MOD R9A07G044_MTU_X_MCK_MTU3>;
       power-domains = <&cpg>;
       resets = <&cpg R9A07G044_MTU_X_PRESET_MTU3>;
diff --git a/Documentation/devicetree/bindings/timer/sifive,clint.yaml b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
index 3c16b260db04..a0ba8b572b21 100644
--- a/Documentation/devicetree/bindings/timer/sifive,clint.yaml
+++ b/Documentation/devicetree/bindings/timer/sifive,clint.yaml
@@ -38,6 +38,7 @@ properties:
               - starfive,jh7100-clint   # StarFive JH7100
               - starfive,jh7110-clint   # StarFive JH7110
               - starfive,jh8100-clint   # StarFive JH8100
+              - starfive,jhb100-clint   # StarFive JHB100
               - tenstorrent,blackhole-clint # Tenstorrent Blackhole
           - const: sifive,clint0        # SiFive CLINT v0 IP block
       - items:
@@ -49,6 +50,7 @@ properties:
       - items:
           - enum:
               - allwinner,sun20i-d1-clint
+              - canaan,k230-clint
               - sophgo,cv1800b-clint
               - sophgo,cv1812h-clint
               - sophgo,sg2002-clint
@@ -72,22 +74,6 @@ properties:
     minItems: 1
     maxItems: 4095
 
-  sifive,fine-ctr-bits:
-    maximum: 15
-    description: The width in bits of the fine counter.
-
-if:
-  properties:
-    compatible:
-      contains:
-        const: sifive,clint2
-then:
-  required:
-    - sifive,fine-ctr-bits
-else:
-  properties:
-    sifive,fine-ctr-bits: false
-
 additionalProperties: false
 
 required:
diff --git a/Documentation/gpu/amdgpu/amdgpu-glossary.rst b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
index 033167025fcc..d553dd599c96 100644
--- a/Documentation/gpu/amdgpu/amdgpu-glossary.rst
+++ b/Documentation/gpu/amdgpu/amdgpu-glossary.rst
@@ -233,8 +233,15 @@ we have a dedicated glossary for Display Core at
     TC
       Texture Cache
 
+    TCC
+      Texture Cache per Channel - L2 cache attached to the memory channels.
+      May be used when shader cores are accessing memory.
+      Despite "Texture" in the name, this is used by any kind of memory access.
+      TCCs may be mapped to TCPs, depending on the architecture.
+
     TCP (AMDGPU)
-      Texture Cache per Pipe. Even though the name "Texture" is part of this
+      Texture Cache per Pipe - L1 cache attached to each CU.
+      Even though the name "Texture" is part of this
       acronym, the TCP represents the path to memory shaders; i.e., it is not
       related to texture. The name is a leftover from older designs where shader
       stages had different cache designs; it refers to the L1 cache in older
diff --git a/Documentation/gpu/drm-ras.rst b/Documentation/gpu/drm-ras.rst
index 70b246a78fc8..4636e68f5678 100644
--- a/Documentation/gpu/drm-ras.rst
+++ b/Documentation/gpu/drm-ras.rst
@@ -52,6 +52,8 @@ User space tools can:
   as a parameter.
 * Query specific error counter values with the ``get-error-counter`` command, using both
   ``node-id`` and ``error-id`` as parameters.
+* Clear specific error counters with the ``clear-error-counter`` command, using both
+  ``node-id`` and ``error-id`` as parameters.
 
 YAML-based Interface
 --------------------
@@ -101,3 +103,9 @@ Example: Query an error counter for a given node
     sudo ynl --family drm_ras --do get-error-counter --json '{"node-id":0, "error-id":1}'
     {'error-id': 1, 'error-name': 'error_name1', 'error-value': 0}
 
+Example: Clear an error counter for a given node
+
+.. code-block:: bash
+
+    sudo ynl --family drm_ras --do clear-error-counter --json '{"node-id":0, "error-id":1}'
+    None
diff --git a/Documentation/gpu/xe/index.rst b/Documentation/gpu/xe/index.rst
index bc432c95d1a3..874ffcb6da3a 100644
--- a/Documentation/gpu/xe/index.rst
+++ b/Documentation/gpu/xe/index.rst
@@ -29,3 +29,4 @@ DG2, etc is provided to prototype the driver.
    xe_device
    xe-drm-usage-stats.rst
    xe_configfs
+   xe_gt_stats
diff --git a/Documentation/gpu/xe/xe_gt_stats.rst b/Documentation/gpu/xe/xe_gt_stats.rst
new file mode 100644
index 000000000000..5ff806abaddb
--- /dev/null
+++ b/Documentation/gpu/xe/xe_gt_stats.rst
@@ -0,0 +1,11 @@
+.. SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+================
+Xe GT Statistics
+================
+
+.. kernel-doc:: drivers/gpu/drm/xe/xe_gt_stats.c
+   :doc: Xe GT Statistics
+
+.. kernel-doc:: drivers/gpu/drm/xe/xe_gt_stats_types.h
+   :internal:
diff --git a/Documentation/netlink/specs/drm_ras.yaml b/Documentation/netlink/specs/drm_ras.yaml
index 79af25dac3c5..e113056f8c01 100644
--- a/Documentation/netlink/specs/drm_ras.yaml
+++ b/Documentation/netlink/specs/drm_ras.yaml
@@ -99,7 +99,7 @@ operations:
       flags: [admin-perm]
       do:
         request:
-          attributes:
+          attributes: &id-attrs
             - node-id
             - error-id
         reply:
@@ -113,3 +113,14 @@ operations:
             - node-id
         reply:
           attributes: *errorinfo
+    -
+      name: clear-error-counter
+      doc: >-
+           Clear error counter for a given node.
+           The request includes the error-id and node-id of the
+           counter to be cleared.
+      attribute-set: error-counter-attrs
+      flags: [admin-perm]
+      do:
+        request:
+          attributes: *id-attrs
diff --git a/Documentation/netlink/specs/nfsd.yaml b/Documentation/netlink/specs/nfsd.yaml
index 8ab43c8253b2..25497b533185 100644
--- a/Documentation/netlink/specs/nfsd.yaml
+++ b/Documentation/netlink/specs/nfsd.yaml
@@ -6,7 +6,51 @@ uapi-header: linux/nfsd_netlink.h
 
 doc: NFSD configuration over generic netlink.
 
+definitions:
+  -
+    type: flags
+    name: cache-type
+    entries: [svc_export, expkey]
+  -
+    type: flags
+    name: export-flags
+    doc: These flags are ordered to match the NFSEXP_* flags in include/linux/nfsd/export.h
+    entries:
+      - readonly
+      - insecure-port
+      - rootsquash
+      - allsquash
+      - async
+      - gathered-writes
+      - noreaddirplus
+      - security-label
+      - sign-fh
+      - nohide
+      - nosubtreecheck
+      - noauthnlm
+      - msnfs
+      - fsid
+      - crossmount
+      - noacl
+      - v4root
+      - pnfs
+  -
+    type: flags
+    name: xprtsec-mode
+    doc: These flags are ordered to match the NFSEXP_XPRTSEC_* flags in include/linux/nfsd/export.h
+    entries:
+      - none
+      - tls
+      - mtls
+
 attribute-sets:
+  -
+    name: cache-notify
+    attributes:
+      -
+        name: cache-type
+        type: u32
+        enum: cache-type
   -
     name: rpc-status
     attributes:
@@ -132,6 +176,131 @@ attribute-sets:
       -
         name: npools
         type: u32
+  -
+    name: fslocation
+    attributes:
+      -
+        name: host
+        type: string
+      -
+        name: path
+        type: string
+  -
+    name: fslocations
+    attributes:
+      -
+        name: location
+        type: nest
+        nested-attributes: fslocation
+        multi-attr: true
+  -
+    name: auth-flavor
+    attributes:
+      -
+        name: pseudoflavor
+        type: u32
+      -
+        name: flags
+        type: u32
+        enum: export-flags
+        enum-as-flags: true
+  -
+    name: svc-export
+    attributes:
+      -
+        name: seqno
+        type: u64
+      -
+        name: client
+        type: string
+      -
+        name: path
+        type: string
+      -
+        name: negative
+        type: flag
+      -
+        name: expiry
+        type: u64
+      -
+        name: anon-uid
+        type: u32
+      -
+        name: anon-gid
+        type: u32
+      -
+        name: fslocations
+        type: nest
+        nested-attributes: fslocations
+      -
+        name: uuid
+        type: binary
+      -
+        name: secinfo
+        type: nest
+        nested-attributes: auth-flavor
+        multi-attr: true
+      -
+        name: xprtsec
+        type: u32
+        enum: xprtsec-mode
+        multi-attr: true
+      -
+        name: flags
+        type: u32
+        enum: export-flags
+        enum-as-flags: true
+      -
+        name: fsid
+        type: s32
+  -
+    name: svc-export-reqs
+    attributes:
+      -
+        name: requests
+        type: nest
+        nested-attributes: svc-export
+        multi-attr: true
+  -
+    name: expkey
+    attributes:
+      -
+        name: seqno
+        type: u64
+      -
+        name: client
+        type: string
+      -
+        name: fsidtype
+        type: u8
+      -
+        name: fsid
+        type: binary
+      -
+        name: negative
+        type: flag
+      -
+        name: expiry
+        type: u64
+      -
+        name: path
+        type: string
+  -
+    name: expkey-reqs
+    attributes:
+      -
+        name: requests
+        type: nest
+        nested-attributes: expkey
+        multi-attr: true
+  -
+    name: cache-flush
+    attributes:
+      -
+        name: mask
+        type: u32
+        enum: cache-type
+        enum-as-flags: true
 
 operations:
   list:
@@ -233,3 +402,63 @@ operations:
           attributes:
             - mode
             - npools
+    -
+      name: cache-notify
+      doc: Notification that there are cache requests that need servicing
+      attribute-set: cache-notify
+      mcgrp: exportd
+      event:
+        attributes:
+          - cache-type
+    -
+      name: svc-export-get-reqs
+      doc: Dump all pending svc_export requests
+      attribute-set: svc-export-reqs
+      flags: [admin-perm]
+      dump:
+          reply:
+            attributes:
+              - requests
+    -
+      name: svc-export-set-reqs
+      doc: Respond to one or more svc_export requests
+      attribute-set: svc-export-reqs
+      flags: [admin-perm]
+      do:
+          request:
+            attributes:
+              - requests
+    -
+      name: expkey-get-reqs
+      doc: Dump all pending expkey requests
+      attribute-set: expkey-reqs
+      flags: [admin-perm]
+      dump:
+          reply:
+            attributes:
+              - requests
+    -
+      name: expkey-set-reqs
+      doc: Respond to one or more expkey requests
+      attribute-set: expkey-reqs
+      flags: [admin-perm]
+      do:
+          request:
+            attributes:
+              - requests
+    -
+      name: cache-flush
+      doc: Flush nfsd caches (svc_export and/or expkey)
+      attribute-set: cache-flush
+      flags: [admin-perm]
+      do:
+        request:
+          attributes:
+            - mask
+
+mcast-groups:
+  list:
+    -
+      name: none
+    -
+      name: exportd
diff --git a/Documentation/netlink/specs/sunrpc_cache.yaml b/Documentation/netlink/specs/sunrpc_cache.yaml
new file mode 100644
index 000000000000..f22ff22b9418
--- /dev/null
+++ b/Documentation/netlink/specs/sunrpc_cache.yaml
@@ -0,0 +1,149 @@
+# SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause)
+---
+name: sunrpc
+protocol: genetlink
+uapi-header: linux/sunrpc_netlink.h
+
+doc: SUNRPC cache upcall support over generic netlink.
+
+definitions:
+  -
+    type: flags
+    name: cache-type
+    entries: [ip_map, unix_gid]
+
+attribute-sets:
+  -
+    name: cache-notify
+    attributes:
+      -
+        name: cache-type
+        type: u32
+        enum: cache-type
+  -
+    name: ip-map
+    attributes:
+      -
+        name: seqno
+        type: u64
+      -
+        name: class
+        type: string
+      -
+        name: addr
+        type: string
+      -
+        name: domain
+        type: string
+      -
+        name: negative
+        type: flag
+      -
+        name: expiry
+        type: u64
+  -
+    name: ip-map-reqs
+    attributes:
+      -
+        name: requests
+        type: nest
+        nested-attributes: ip-map
+        multi-attr: true
+  -
+    name: unix-gid
+    attributes:
+      -
+        name: seqno
+        type: u64
+      -
+        name: uid
+        type: u32
+      -
+        name: gids
+        type: u32
+        multi-attr: true
+      -
+        name: negative
+        type: flag
+      -
+        name: expiry
+        type: u64
+  -
+    name: unix-gid-reqs
+    attributes:
+      -
+        name: requests
+        type: nest
+        nested-attributes: unix-gid
+        multi-attr: true
+  -
+    name: cache-flush
+    attributes:
+      -
+        name: mask
+        type: u32
+        enum: cache-type
+        enum-as-flags: true
+
+operations:
+  list:
+    -
+      name: cache-notify
+      doc: Notification that there are cache requests that need servicing
+      attribute-set: cache-notify
+      mcgrp: exportd
+      event:
+        attributes:
+          - cache-type
+    -
+      name: ip-map-get-reqs
+      doc: Dump all pending ip_map requests
+      attribute-set: ip-map-reqs
+      flags: [admin-perm]
+      dump:
+          reply:
+            attributes:
+              - requests
+    -
+      name: ip-map-set-reqs
+      doc: Respond to one or more ip_map requests
+      attribute-set: ip-map-reqs
+      flags: [admin-perm]
+      do:
+          request:
+            attributes:
+              - requests
+    -
+      name: unix-gid-get-reqs
+      doc: Dump all pending unix_gid requests
+      attribute-set: unix-gid-reqs
+      flags: [admin-perm]
+      dump:
+          reply:
+            attributes:
+              - requests
+    -
+      name: unix-gid-set-reqs
+      doc: Respond to one or more unix_gid requests
+      attribute-set: unix-gid-reqs
+      flags: [admin-perm]
+      do:
+          request:
+            attributes:
+              - requests
+    -
+      name: cache-flush
+      doc: Flush sunrpc caches (ip_map and/or unix_gid)
+      attribute-set: cache-flush
+      flags: [admin-perm]
+      do:
+        request:
+          attributes:
+            - mask
+
+mcast-groups:
+  list:
+    -
+      name: none
+    -
+      name: exportd
diff --git a/Documentation/scheduler/sched-ext.rst b/Documentation/scheduler/sched-ext.rst
index 03d595d178ea..c4f59c08d8a4 100644
--- a/Documentation/scheduler/sched-ext.rst
+++ b/Documentation/scheduler/sched-ext.rst
@@ -339,6 +339,11 @@ The following briefly shows how a waking task is scheduled and executed.
      leaves (e.g., when ``ops.dispatch()`` moves it to a terminal DSQ, or
      on property change / sleep).
 
+   Note that ``ops.enqueue()`` can be called multiple times in a row without
+   an intervening call to ``ops.dequeue()``. This can happen, for example,
+   when a task on a user-created DSQ is re-enqueued using
+   ``scx_bpf_dsq_reenq()``. The task stays in BPF custody the entire time.
+
    When a task leaves BPF scheduler custody, ``ops.dequeue()`` is invoked.
    The dequeue can happen for different reasons, distinguished by flags:
 
@@ -503,7 +508,7 @@ Where to Look
     custom DSQ.
 
   * ``scx_qmap[.bpf].c``: A multi-level FIFO scheduler supporting five
-    levels of priority implemented with ``BPF_MAP_TYPE_QUEUE``.
+    levels of priority implemented with arena-backed doubly-linked lists.
 
   * ``scx_central[.bpf].c``: A central FIFO scheduler where all scheduling
     decisions are made on one CPU, demonstrating ``LOCAL_ON`` dispatching,
diff --git a/MAINTAINERS b/MAINTAINERS
index 2fb1c75afd16..c871acf2179c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -8193,10 +8193,9 @@ F:	include/uapi/drm/nouveau_drm.h
 CORE DRIVER FOR NVIDIA GPUS [RUST]
 M:	Danilo Krummrich <dakr@kernel.org>
 M:	Alexandre Courbot <acourbot@nvidia.com>
-L:	nouveau@lists.freedesktop.org
+L:	nova-gpu@lists.linux.dev
 S:	Supported
 W:	https://rust-for-linux.com/nova-gpu-driver
-Q:	https://patchwork.freedesktop.org/project/nouveau/
 B:	https://gitlab.freedesktop.org/drm/nova/-/issues
 C:	irc://irc.oftc.net/nouveau
 T:	git https://gitlab.freedesktop.org/drm/rust/kernel.git drm-rust-next
@@ -8205,10 +8204,9 @@ F:	drivers/gpu/nova-core/
 
 DRM DRIVER FOR NVIDIA GPUS [RUST]
 M:	Danilo Krummrich <dakr@kernel.org>
-L:	nouveau@lists.freedesktop.org
+L:	nova-gpu@lists.linux.dev
 S:	Supported
 W:	https://rust-for-linux.com/nova-gpu-driver
-Q:	https://patchwork.freedesktop.org/project/nouveau/
 B:	https://gitlab.freedesktop.org/drm/nova/-/issues
 C:	irc://irc.oftc.net/nouveau
 T:	git https://gitlab.freedesktop.org/drm/rust/kernel.git drm-rust-next
@@ -9853,7 +9851,7 @@ F:	include/uapi/scsi/fc/
 
 FILE LOCKING (flock() and fcntl()/lockf())
 M:	Jeff Layton <jlayton@kernel.org>
-M:	Chuck Lever <chuck.lever@oracle.com>
+M:	Chuck Lever <cel@kernel.org>
 R:	Alexander Aring <alex.aring@gmail.com>
 L:	linux-fsdevel@vger.kernel.org
 S:	Maintained
@@ -9894,7 +9892,7 @@ F:	init/do_mounts*
 F:	init/*initramfs*
 
 FILESYSTEMS [EXPORTFS]
-M:	Chuck Lever <chuck.lever@oracle.com>
+M:	Chuck Lever <cel@kernel.org>
 M:	Jeff Layton <jlayton@kernel.org>
 R:	Amir Goldstein <amir73il@gmail.com>
 L:	linux-fsdevel@vger.kernel.org
@@ -11242,7 +11240,7 @@ Q:	http://patchwork.linuxtv.org/project/linux-media/list/
 F:	drivers/media/usb/hackrf/
 
 HANDSHAKE UPCALL FOR TRANSPORT LAYER SECURITY
-M:	Chuck Lever <chuck.lever@oracle.com>
+M:	Chuck Lever <cel@kernel.org>
 L:	kernel-tls-handshake@lists.linux.dev
 L:	netdev@vger.kernel.org
 S:	Maintained
@@ -13793,6 +13791,15 @@ S:	Maintained
 F:	Documentation/hwmon/k8temp.rst
 F:	drivers/hwmon/k8temp.c
 
+KALLSYMS LINEINFO
+M:	Sasha Levin <sashal@kernel.org>
+S:	Maintained
+F:	Documentation/admin-guide/kallsyms-lineinfo.rst
+F:	include/linux/mod_lineinfo.h
+F:	lib/tests/lineinfo_kunit.c
+F:	scripts/gen-mod-lineinfo.sh
+F:	scripts/gen_lineinfo.c
+
 KASAN
 M:	Andrey Ryabinin <ryabinin.a.a@gmail.com>
 R:	Alexander Potapenko <glider@google.com>
@@ -13860,7 +13867,6 @@ M:	Pratyush Yadav <pratyush@kernel.org>
 R:	Dave Young <ruirui.yang@linux.dev>
 L:	kexec@lists.infradead.org
 S:	Maintained
-W:	http://lse.sourceforge.net/kdump/
 F:	Documentation/admin-guide/kdump/
 F:	fs/proc/vmcore.c
 F:	include/linux/crash_core.h
@@ -13937,7 +13943,7 @@ S:	Odd Fixes
 W:	http://kernelnewbies.org/KernelJanitors
 
 KERNEL NFSD, SUNRPC, AND LOCKD SERVERS
-M:	Chuck Lever <chuck.lever@oracle.com>
+M:	Chuck Lever <cel@kernel.org>
 M:	Jeff Layton <jlayton@kernel.org>
 R:	NeilBrown <neil@brown.name>
 R:	Olga Kornievskaia <okorniev@redhat.com>
@@ -15252,7 +15258,7 @@ M:	Andrea Cervesato <andrea.cervesato@suse.com>
 M:	Cyril Hrubis <chrubis@suse.cz>
 M:	Jan Stancek <jstancek@redhat.com>
 M:	Petr Vorel <pvorel@suse.cz>
-M:	Li Wang <liwang@redhat.com>
+M:	Li Wang <li.wang@linux.dev>
 M:	Yang Xu <xuyang2018.jy@fujitsu.com>
 M:	Xiao Yang <yangx.jy@fujitsu.com>
 L:	ltp@lists.linux.it (subscribers-only)
@@ -15399,7 +15405,7 @@ F:	include/net/netns/mctp.h
 F:	net/mctp/
 
 MAPLE TREE
-M:	Liam R. Howlett <Liam.Howlett@oracle.com>
+M:	Liam R. Howlett <liam@infradead.org>
 R:	Alice Ryhl <aliceryhl@google.com>
 R:	Andrew Ballance <andrewjballance@gmail.com>
 L:	maple-tree@lists.infradead.org
@@ -16759,7 +16765,7 @@ MEMORY MANAGEMENT - CORE
 M:	Andrew Morton <akpm@linux-foundation.org>
 M:	David Hildenbrand <david@kernel.org>
 R:	Lorenzo Stoakes <ljs@kernel.org>
-R:	Liam R. Howlett <Liam.Howlett@oracle.com>
+R:	Liam R. Howlett <liam@infradead.org>
 R:	Vlastimil Babka <vbabka@kernel.org>
 R:	Mike Rapoport <rppt@kernel.org>
 R:	Suren Baghdasaryan <surenb@google.com>
@@ -16805,7 +16811,7 @@ F:	mm/sparse.c
 F:	mm/util.c
 F:	mm/vmpressure.c
 F:	mm/vmstat.c
-N:	include/linux/page[-_]*
+N:	include\/linux\/page[-_][a-zA-Z]*
 
 MEMORY MANAGEMENT - EXECMEM
 M:	Andrew Morton <akpm@linux-foundation.org>
@@ -16895,7 +16901,7 @@ MEMORY MANAGEMENT - MISC
 M:	Andrew Morton <akpm@linux-foundation.org>
 M:	David Hildenbrand <david@kernel.org>
 R:	Lorenzo Stoakes <ljs@kernel.org>
-R:	Liam R. Howlett <Liam.Howlett@oracle.com>
+R:	Liam R. Howlett <liam@infradead.org>
 R:	Vlastimil Babka <vbabka@kernel.org>
 R:	Mike Rapoport <rppt@kernel.org>
 R:	Suren Baghdasaryan <surenb@google.com>
@@ -16962,6 +16968,7 @@ S:	Maintained
 F:	include/linux/compaction.h
 F:	include/linux/gfp.h
 F:	include/linux/page-isolation.h
+F:	include/linux/pageblock-flags.h
 F:	mm/compaction.c
 F:	mm/debug_page_alloc.c
 F:	mm/debug_page_ref.c
@@ -16983,7 +16990,7 @@ M:	Andrew Morton <akpm@linux-foundation.org>
 M:	Johannes Weiner <hannes@cmpxchg.org>
 R:	David Hildenbrand <david@kernel.org>
 R:	Michal Hocko <mhocko@kernel.org>
-R:	Qi Zheng <zhengqi.arch@bytedance.com>
+R:	Qi Zheng <qi.zheng@linux.dev>
 R:	Shakeel Butt <shakeel.butt@linux.dev>
 R:	Lorenzo Stoakes <ljs@kernel.org>
 L:	linux-mm@kvack.org
@@ -16996,7 +17003,7 @@ M:	Andrew Morton <akpm@linux-foundation.org>
 M:	David Hildenbrand <david@kernel.org>
 M:	Lorenzo Stoakes <ljs@kernel.org>
 R:	Rik van Riel <riel@surriel.com>
-R:	Liam R. Howlett <Liam.Howlett@oracle.com>
+R:	Liam R. Howlett <liam@infradead.org>
 R:	Vlastimil Babka <vbabka@kernel.org>
 R:	Harry Yoo <harry@kernel.org>
 R:	Jann Horn <jannh@google.com>
@@ -17043,7 +17050,7 @@ M:	David Hildenbrand <david@kernel.org>
 M:	Lorenzo Stoakes <ljs@kernel.org>
 R:	Zi Yan <ziy@nvidia.com>
 R:	Baolin Wang <baolin.wang@linux.alibaba.com>
-R:	Liam R. Howlett <Liam.Howlett@oracle.com>
+R:	Liam R. Howlett <liam@infradead.org>
 R:	Nico Pache <npache@redhat.com>
 R:	Ryan Roberts <ryan.roberts@arm.com>
 R:	Dev Jain <dev.jain@arm.com>
@@ -17081,7 +17088,7 @@ F:	tools/testing/selftests/mm/uffd-*.[ch]
 MEMORY MANAGEMENT - RUST
 M:	Alice Ryhl <aliceryhl@google.com>
 R:	Lorenzo Stoakes <ljs@kernel.org>
-R:	Liam R. Howlett <Liam.Howlett@oracle.com>
+R:	Liam R. Howlett <liam@infradead.org>
 L:	linux-mm@kvack.org
 L:	rust-for-linux@vger.kernel.org
 S:	Maintained
@@ -17095,7 +17102,7 @@ F:	rust/kernel/page.rs
 
 MEMORY MAPPING
 M:	Andrew Morton <akpm@linux-foundation.org>
-M:	Liam R. Howlett <Liam.Howlett@oracle.com>
+M:	Liam R. Howlett <liam@infradead.org>
 M:	Lorenzo Stoakes <ljs@kernel.org>
 R:	Vlastimil Babka <vbabka@kernel.org>
 R:	Jann Horn <jannh@google.com>
@@ -17127,7 +17134,7 @@ F:	tools/testing/vma/
 MEMORY MAPPING - LOCKING
 M:	Andrew Morton <akpm@linux-foundation.org>
 M:	Suren Baghdasaryan <surenb@google.com>
-M:	Liam R. Howlett <Liam.Howlett@oracle.com>
+M:	Liam R. Howlett <liam@infradead.org>
 M:	Lorenzo Stoakes <ljs@kernel.org>
 R:	Vlastimil Babka <vbabka@kernel.org>
 R:	Shakeel Butt <shakeel.butt@linux.dev>
@@ -17142,7 +17149,7 @@ F:	mm/mmap_lock.c
 
 MEMORY MAPPING - MADVISE (MEMORY ADVICE)
 M:	Andrew Morton <akpm@linux-foundation.org>
-M:	Liam R. Howlett <Liam.Howlett@oracle.com>
+M:	Liam R. Howlett <liam@infradead.org>
 M:	Lorenzo Stoakes <ljs@kernel.org>
 M:	David Hildenbrand <david@kernel.org>
 R:	Vlastimil Babka <vbabka@kernel.org>
@@ -23369,7 +23376,7 @@ RUST [ALLOC]
 M:	Danilo Krummrich <dakr@kernel.org>
 R:	Lorenzo Stoakes <ljs@kernel.org>
 R:	Vlastimil Babka <vbabka@kernel.org>
-R:	Liam R. Howlett <Liam.Howlett@oracle.com>
+R:	Liam R. Howlett <liam@infradead.org>
 R:	Uladzislau Rezki <urezki@gmail.com>
 L:	rust-for-linux@vger.kernel.org
 S:	Maintained
@@ -24314,7 +24321,7 @@ F:	include/media/i2c/rj54n1cb0c.h
 SHRINKER
 M:	Andrew Morton <akpm@linux-foundation.org>
 M:	Dave Chinner <david@fromorbit.com>
-R:	Qi Zheng <zhengqi.arch@bytedance.com>
+R:	Qi Zheng <qi.zheng@linux.dev>
 R:	Roman Gushchin <roman.gushchin@linux.dev>
 R:	Muchun Song <muchun.song@linux.dev>
 L:	linux-mm@kvack.org
diff --git a/Makefile b/Makefile
index e27c91ea56fc..9028e4e60b24 100644
--- a/Makefile
+++ b/Makefile
@@ -826,7 +826,7 @@ all: vmlinux
 
 CFLAGS_GCOV	:= -fprofile-arcs -ftest-coverage
 ifdef CONFIG_CC_IS_GCC
-CFLAGS_GCOV	+= -fno-tree-loop-im
+CFLAGS_GCOV	+= -fno-tree-loop-im -fprofile-update=prefer-atomic
 endif
 export CFLAGS_GCOV
 
diff --git a/Next/SHA1s b/Next/SHA1s
new file mode 100644
index 000000000000..a6e507b86ab1
--- /dev/null
+++ b/Next/SHA1s
@@ -0,0 +1,422 @@
+Name		SHA1
+----		----
+origin		254f49634ee16a731174d2ae34bc50bd5f45e731
+ext4-fixes	981fcc5674e67158d24d23e841523eccba19d0e7
+vfs-brauner-fixes	ac8777cc36224b4705d2c6efb10c56135d479b21
+fscrypt-current	254f49634ee16a731174d2ae34bc50bd5f45e731
+fsverity-current	254f49634ee16a731174d2ae34bc50bd5f45e731
+btrfs-fixes	1b29979c0f6a930f361da0832d5ceff3fb2cfccb
+vfs-fixes	49c5d168a3a8f4eb27d44a2a22b7e8a856ca601f
+erofs-fixes	2d8c7edcb661812249469f4a5b62e9339118846f
+nfsd-fixes	b0bf14546bcefa4ea49f5efcd7db2a99f0cabde9
+v9fs-fixes	028ef9c96e96197026887c0f092424679298aae8
+overlayfs-fixes	1f6ee9be92f8df85a8c9a5a78c20fd39c0c21a95
+fscrypt		254f49634ee16a731174d2ae34bc50bd5f45e731
+btrfs		6bf684b8823552b99c86bf791b22f622934ee771
+ceph		29e2da94997846a528336fbbfbc61535b5a5cacd
+cifs		0cbc300257d9b399491909806777f504ec687c1d
+configfs	6363844fdbbb76afe1d44d678fe0746390204a5f
+ecryptfs	eb5e768eaf7c5f6274319e2894ceebf0f3cb5750
+dlm		2c3a0b730012ef87aaaf35243e1fbe9880666f7c
+erofs		a5242d37c83abe86df95c6941e2ace9f9055ffcb
+exfat		dc0e16d2f56a6f8de32ebcd66f927f1767ff27e3
+ext3		936274f2565d8f565dd7fb0d496b3228792dae17
+ext4		981fcc5674e67158d24d23e841523eccba19d0e7
+f2fs		cb8ff3ead9a3fc43727980be58c7099506f65261
+fsverity	254f49634ee16a731174d2ae34bc50bd5f45e731
+fuse		ea2ff881bb8edfb7318a6c757b50d41ad501f29b
+gfs2		4da0dd95be3b0321bf9687fb1a3c2fed3319c032
+jfs		dad98c5b2a05ef744af4c884c97066a3c8cdad61
+ksmbd		254f49634ee16a731174d2ae34bc50bd5f45e731
+nfs		e6614b88d59d110ee1a80ed0826e34f24dd35c96
+nfs-anna	4529e0015432977af3ecc3b9f940fc2a1ef1b265
+nfsd		a60fafb3f6892738703ec0f0603cd42bee209efa
+ntfs		fe5be34f5770f8e77fbd4e666ddaf15da10f23a6
+ntfs3		819bd270abf9de3b7f306e233054b85a07c47820
+orangefs	e61bc5e4d87433c8759e7dc92bb640ef71a8970c
+overlayfs	1f6ee9be92f8df85a8c9a5a78c20fd39c0c21a95
+ubifs		11efa98bcc0d00271e8f66c7c940c284f973f39d
+v9fs		8fc518e489c1386fd0cf7f4256d055960ed6a2e4
+v9fs-ericvh	028ef9c96e96197026887c0f092424679298aae8
+xfs		2ffc6900d5c3a7cd59becda2aa67581d9bd3858e
+zonefs		a42938e80357a13f8b8592111e63f2e33a919863
+vfs-brauner	8ee708daac8a2ccf7019a5ef6ee1bec2937f0823
+vfs		e82ff9b6cb767fc823d5e461034f32388c4092a2
+mm-hotfixes	ba24da38a519dfcff8cce3f3f2726d7b159a4d75
+fs-current	983de4a4f819178a8d347d6670a45a672cd5b3d4
+kbuild-current	75f7c47ccd78c947cf1b6ddb18ea453ff0555716
+clang-fixes	4f96b7c68a9904e01049ef610d701b382dca9574
+arc-current	7aaa8047eafd0bd628065b15757d9b48c5f9c07d
+arm-current	75f9a484e817adea211c73f89ed938a2b2f90953
+arm64-fixes	54ac9ff8f1196afc49d644a1625e0af1c9fcf7f5
+arm-soc-fixes	3e2444044d160e33ec2b139d1e4f9691bb9d9bac
+davinci-current	6de23f81a5e08be8fbf5e8d7e9febc72a5b5f27f
+drivers-memory-fixes	6de23f81a5e08be8fbf5e8d7e9febc72a5b5f27f
+sophgo-fixes	19272b37aa4f83ca52bdf9c16d5d81bdd1354494
+sophgo-soc-fixes	0af2f6be1b4281385b618cb86ad946eded089ac8
+m68k-current	cb39cf99d88e8f2c68a41fb3bb01c4f40a8fcc30
+powerpc-fixes	328335a79487ec38d6b0e1aa807785b0f75e594d
+s390-fixes	c8d46f17c2fc7d25c18e60c008928aecab26184d
+net		254f49634ee16a731174d2ae34bc50bd5f45e731
+bpf		b5c111f4967ba4fdecdd318923ec7b081e9ef95f
+ipsec		ec54093e6a8f87e800bb6aa15eb7fc1e33faa524
+netfilter	d40831b016b4986e70d20d0ad14e6a0c62318986
+ipvs		9351edf65cb6ba10564f9c81e3c52cf97f4b2a81
+wireless	d65b175cfac64ee65506eea7fa573d291a9694ca
+ath		1f5ffc672165ff851063a5fd044b727ab2517ae3
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+wpan		8ce4f287524c74a118b0af1eebd4b24a8efca57a
+rdma-fixes	028ef9c96e96197026887c0f092424679298aae8
+sound-current	2724fbc90e5c133fbbd030e72fe8a3869a20df08
+sound-asoc-fixes	c7ecb6a61908c2604dda6e42da66724d256de7b9
+regmap-fixes	4b7774eeab8d66c22f02f5c120602df154a87e12
+regulator-fixes	fb71a29c2455688592dae8cc7af0244948925bad
+spi-fixes	7643978722aac3a012783ce12dc534eba7c51698
+pci-current	40286d6379aacfcc053253ef78dc78b09addffda
+driver-core.current	254f49634ee16a731174d2ae34bc50bd5f45e731
+tty.current	27d128c1cff64c3b8012cc56dd5a1391bb4f1821
+usb.current	27d128c1cff64c3b8012cc56dd5a1391bb4f1821
+usb-serial-fixes	591cd656a1bf5ea94a222af5ef2ee76df029c1d2
+phy		7aaa8047eafd0bd628065b15757d9b48c5f9c07d
+staging.current	27d128c1cff64c3b8012cc56dd5a1391bb4f1821
+iio-fixes	51e7665ab81f02adc80a1219c260ee678e9c6eb8
+counter-current	2932095c114b98cbb40ccf34fc00d613cb17cead
+char-misc.current	27d128c1cff64c3b8012cc56dd5a1391bb4f1821
+soundwire-fixes	6de23f81a5e08be8fbf5e8d7e9febc72a5b5f27f
+thunderbolt-fixes	254f49634ee16a731174d2ae34bc50bd5f45e731
+input-current	6cdc46b38cf146ce81d4831b6472dbf7731849a2
+crypto-current	5db6ef9847717329f12c5ea8aba7e9f588a980c0
+libcrypto-fixes	254f49634ee16a731174d2ae34bc50bd5f45e731
+vfio-fixes	e98137f0a874ab36d0946de4707aa48cb7137d1c
+kselftest-fixes	6de23f81a5e08be8fbf5e8d7e9febc72a5b5f27f
+dmaengine-fixes	7aaa8047eafd0bd628065b15757d9b48c5f9c07d
+backlight-fixes	8f0b4cce4481fb22653697cced8d0d04027cb1e8
+mtd-fixes	b9465b04de4b90228de03db9a1e0d56b00814366
+mfd-fixes	aa6e63373d91f82628b20f6fae7ffe9b97b568a5
+v4l-dvb-fixes	fb2d7bd146fa70d7bd10b6c0bbeff7e3db7c6c57
+reset-fixes	9797524ef2b69c6b187b55bd844eb72a8c1cbd99
+mips-fixes	591cd656a1bf5ea94a222af5ef2ee76df029c1d2
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+kvms390-fixes	16d990a15491cf76cd6eef0846e1b4100e63261a
+kvm-arm-fixes	4ce98bf0865c349e7026ad9c14f48da264920953
+hwmon-fixes	254f49634ee16a731174d2ae34bc50bd5f45e731
+nvdimm-fixes	a8aec14230322ed8f1e8042b6d656c1631d41163
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+drivers-x86-fixes	254f49634ee16a731174d2ae34bc50bd5f45e731
+samsung-krzk-fixes	6de23f81a5e08be8fbf5e8d7e9febc72a5b5f27f
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+devicetree-fixes	81122fba08fa3ccafab6ed272a5c6f2203923a7e
+dt-krzk-fixes	6de23f81a5e08be8fbf5e8d7e9febc72a5b5f27f
+scsi-fixes	98f69975d4c0434ca2e6e8cfa1d8d51647a20593
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+mmc-fixes	8f4d20a710225ec7a565f6a0459862d3b1f32330
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+hyperv-fixes	16cbec24897624051b324aa3a85859c38ca65fde
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+fpga-fixes	19272b37aa4f83ca52bdf9c16d5d81bdd1354494
+spdx		27d128c1cff64c3b8012cc56dd5a1391bb4f1821
+gpio-brgl-fixes	e31eee4a961077d60ef2362507240c6743c1c2ae
+gpio-intel-fixes	254f49634ee16a731174d2ae34bc50bd5f45e731
+pinctrl-intel-fixes	254f49634ee16a731174d2ae34bc50bd5f45e731
+auxdisplay-fixes	254f49634ee16a731174d2ae34bc50bd5f45e731
+kunit-fixes	8b8f1d5e350acdf972b6b02e225d9e14c600f7ad
+memblock-fixes	afd218bb1dd8b4d2ba99a84cfa71524da6dbab35
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+battery-fixes	8f0b4cce4481fb22653697cced8d0d04027cb1e8
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+i2c-host-fixes	39ed7d89b973329cc5c764b65ba6302b17b1907e
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+liveupdate-fixes	028ef9c96e96197026887c0f092424679298aae8
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+mm-nonmm-unstable	7ef437c556709730745fe18338d3bdbf273a583e
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+nocache-cleanup	809b997a5ce945ab470f70c187048fe4f5df20bf
+alpha		d58041d2c63e09a1c9083e0e9f4151e487c4e16a
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+fsl		c99d8ac7b355cbbdbb3f4d8b9a9b46de05a6fee9
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+spacemit	254f49634ee16a731174d2ae34bc50bd5f45e731
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diff --git a/Next/Trees b/Next/Trees
new file mode 100644
index 000000000000..3fbda26c374f
--- /dev/null
+++ b/Next/Trees
@@ -0,0 +1,422 @@
+Trees included into this release:
+
+Name		Url
+----		---
+origin		https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git#master
+ext4-fixes	https://git.kernel.org/pub/scm/linux/kernel/git/tytso/ext4.git#fixes
+vfs-brauner-fixes	https://git.kernel.org/pub/scm/linux/kernel/git/vfs/vfs.git#vfs.fixes
+fscrypt-current	https://git.kernel.org/pub/scm/fs/fscrypt/linux.git#for-current
+fsverity-current	https://git.kernel.org/pub/scm/fs/fsverity/linux.git#for-current
+btrfs-fixes	https://git.kernel.org/pub/scm/linux/kernel/git/kdave/linux.git#next-fixes
+vfs-fixes	https://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs.git#fixes
+erofs-fixes	https://git.kernel.org/pub/scm/linux/kernel/git/xiang/erofs.git#fixes
+nfsd-fixes	https://git.kernel.org/pub/scm/linux/kernel/git/cel/linux#nfsd-fixes
+v9fs-fixes	https://git.kernel.org/pub/scm/linux/kernel/git/ericvh/v9fs.git#fixes/next
+overlayfs-fixes	https://git.kernel.org/pub/scm/linux/kernel/git/overlayfs/vfs.git#ovl-fixes
+fscrypt		https://git.kernel.org/pub/scm/fs/fscrypt/linux.git#for-next
+btrfs		https://git.kernel.org/pub/scm/linux/kernel/git/kdave/linux.git#for-next
+ceph		https://github.com/ceph/ceph-client.git#master
+cifs		git://git.samba.org/sfrench/cifs-2.6.git#for-next
+configfs	https://git.kernel.org/pub/scm/linux/kernel/git/a.hindborg/linux.git#configfs-next
+ecryptfs	https://git.kernel.org/pub/scm/linux/kernel/git/tyhicks/ecryptfs.git#next
+dlm		https://git.kernel.org/pub/scm/linux/kernel/git/teigland/linux-dlm.git#next
+erofs		https://git.kernel.org/pub/scm/linux/kernel/git/xiang/erofs.git#dev
+exfat		https://git.kernel.org/pub/scm/linux/kernel/git/linkinjeon/exfat.git#dev
+ext3		https://git.kernel.org/pub/scm/linux/kernel/git/jack/linux-fs.git#for_next
+ext4		https://git.kernel.org/pub/scm/linux/kernel/git/tytso/ext4.git#dev
+f2fs		https://git.kernel.org/pub/scm/linux/kernel/git/jaegeuk/f2fs.git#dev
+fsverity	https://git.kernel.org/pub/scm/fs/fsverity/linux.git#for-next
+fuse		https://git.kernel.org/pub/scm/linux/kernel/git/mszeredi/fuse.git#for-next
+gfs2		https://git.kernel.org/pub/scm/linux/kernel/git/gfs2/linux-gfs2.git#for-next
+jfs		https://github.com/kleikamp/linux-shaggy.git#jfs-next
+ksmbd		https://github.com/smfrench/smb3-kernel.git#ksmbd-for-next
+nfs		git://git.linux-nfs.org/projects/trondmy/nfs-2.6.git#linux-next
+nfs-anna	git://git.linux-nfs.org/projects/anna/linux-nfs.git#linux-next
+nfsd		https://git.kernel.org/pub/scm/linux/kernel/git/cel/linux#nfsd-next
+ntfs		https://git.kernel.org/pub/scm/linux/kernel/git/linkinjeon/ntfs.git#ntfs-next
+ntfs3		https://github.com/Paragon-Software-Group/linux-ntfs3.git#master
+orangefs	https://git.kernel.org/pub/scm/linux/kernel/git/hubcap/linux.git#for-next
+overlayfs	https://git.kernel.org/pub/scm/linux/kernel/git/overlayfs/vfs.git#overlayfs-next
+ubifs		https://git.kernel.org/pub/scm/linux/kernel/git/rw/ubifs.git#next
+v9fs		https://github.com/martinetd/linux#9p-next
+v9fs-ericvh	https://git.kernel.org/pub/scm/linux/kernel/git/ericvh/v9fs.git#ericvh/for-next
+xfs		https://git.kernel.org/pub/scm/fs/xfs/xfs-linux.git#for-next
+zonefs		https://git.kernel.org/pub/scm/linux/kernel/git/dlemoal/zonefs.git#for-next
+vfs-brauner	https://git.kernel.org/pub/scm/linux/kernel/git/vfs/vfs.git#vfs.all
+vfs		https://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs.git#for-next
+mm-hotfixes	https://git.kernel.org/pub/scm/linux/kernel/git/akpm/mm#mm-hotfixes-unstable
+kbuild-current	https://git.kernel.org/pub/scm/linux/kernel/git/kbuild/linux.git#kbuild-fixes-for-next
+clang-fixes	https://git.kernel.org/pub/scm/linux/kernel/git/nathan/linux.git#clang-fixes-for-next
+arc-current	https://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc.git#for-curr
+arm-current	https://git.kernel.org/pub/scm/linux/kernel/git/rmk/linux.git#fixes
+arm64-fixes	https://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux#for-next/fixes
+arm-soc-fixes	https://git.kernel.org/pub/scm/linux/kernel/git/soc/soc.git#arm/fixes
+davinci-current	https://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux.git#davinci/for-current
+drivers-memory-fixes	https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl.git#fixes
+sophgo-fixes	https://github.com/sophgo/linux.git#fixes
+sophgo-soc-fixes	https://github.com/sophgo/linux.git#soc-fixes
+m68k-current	https://git.kernel.org/pub/scm/linux/kernel/git/geert/linux-m68k.git#for-linus
+powerpc-fixes	https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git#fixes
+s390-fixes	https://git.kernel.org/pub/scm/linux/kernel/git/s390/linux.git#fixes
+net		https://git.kernel.org/pub/scm/linux/kernel/git/netdev/net.git#main
+bpf		https://git.kernel.org/pub/scm/linux/kernel/git/bpf/bpf.git/#master
+ipsec		https://git.kernel.org/pub/scm/linux/kernel/git/klassert/ipsec.git#master
+netfilter	https://git.kernel.org/pub/scm/linux/kernel/git/netfilter/nf.git#main
+ipvs		https://git.kernel.org/pub/scm/linux/kernel/git/horms/ipvs.git#main
+wireless	https://git.kernel.org/pub/scm/linux/kernel/git/wireless/wireless.git#for-next
+ath		https://git.kernel.org/pub/scm/linux/kernel/git/ath/ath.git#for-current
+iwlwifi		https://git.kernel.org/pub/scm/linux/kernel/git/iwlwifi/iwlwifi-next.git#fixes
+wpan		https://git.kernel.org/pub/scm/linux/kernel/git/wpan/wpan.git#master
+rdma-fixes	https://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdma.git#for-rc
+sound-current	https://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound.git#for-linus
+sound-asoc-fixes	https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git#for-linus
+regmap-fixes	https://git.kernel.org/pub/scm/linux/kernel/git/broonie/regmap.git#for-linus
+regulator-fixes	https://git.kernel.org/pub/scm/linux/kernel/git/broonie/regulator.git#for-linus
+spi-fixes	https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git#for-linus
+pci-current	https://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git#for-linus
+driver-core.current	https://git.kernel.org/pub/scm/linux/kernel/git/driver-core/driver-core.git#driver-core-linus
+tty.current	https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty.git#tty-linus
+usb.current	https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb.git#usb-linus
+usb-serial-fixes	https://git.kernel.org/pub/scm/linux/kernel/git/johan/usb-serial.git#usb-linus
+phy		https://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy.git#fixes
+staging.current	https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging.git#staging-linus
+iio-fixes	https://git.kernel.org/pub/scm/linux/kernel/git/jic23/iio.git#fixes-togreg
+counter-current	https://git.kernel.org/pub/scm/linux/kernel/git/wbg/counter.git#counter-current
+char-misc.current	https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc.git#char-misc-linus
+soundwire-fixes	https://git.kernel.org/pub/scm/linux/kernel/git/vkoul/soundwire.git#fixes
+thunderbolt-fixes	https://git.kernel.org/pub/scm/linux/kernel/git/westeri/thunderbolt.git#fixes
+input-current	https://git.kernel.org/pub/scm/linux/kernel/git/dtor/input.git#for-linus
+crypto-current	https://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6.git#master
+libcrypto-fixes	https://git.kernel.org/pub/scm/linux/kernel/git/ebiggers/linux.git#libcrypto-fixes
+vfio-fixes	https://github.com/awilliam/linux-vfio.git#for-linus
+kselftest-fixes	https://git.kernel.org/pub/scm/linux/kernel/git/shuah/linux-kselftest.git#fixes
+dmaengine-fixes	https://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine.git#fixes
+backlight-fixes	https://git.kernel.org/pub/scm/linux/kernel/git/lee/backlight.git#for-backlight-fixes
+mtd-fixes	https://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git#mtd/fixes
+mfd-fixes	https://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd.git#for-mfd-fixes
+v4l-dvb-fixes	git://linuxtv.org/media-ci/media-pending.git#fixes
+reset-fixes	https://git.pengutronix.de/git/pza/linux#reset/fixes
+mips-fixes	https://git.kernel.org/pub/scm/linux/kernel/git/mips/linux.git#mips-fixes
+at91-fixes	https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux.git#at91-fixes
+omap-fixes	https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap.git#fixes
+kvm-fixes	git://git.kernel.org/pub/scm/virt/kvm/kvm.git#master
+kvms390-fixes	https://git.kernel.org/pub/scm/linux/kernel/git/kvms390/linux.git#master
+kvm-arm-fixes	https://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm.git#fixes
+hwmon-fixes	https://git.kernel.org/pub/scm/linux/kernel/git/groeck/linux-staging.git#hwmon
+nvdimm-fixes	https://git.kernel.org/pub/scm/linux/kernel/git/nvdimm/nvdimm.git#libnvdimm-fixes
+cxl-fixes	https://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl.git#fixes
+dma-mapping-fixes	https://git.kernel.org/pub/scm/linux/kernel/git/mszyprowski/linux.git#dma-mapping-fixes
+drivers-x86-fixes	https://git.kernel.org/pub/scm/linux/kernel/git/pdx86/platform-drivers-x86.git#fixes
+samsung-krzk-fixes	https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux.git#fixes
+pinctrl-samsung-fixes	https://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung.git#fixes
+devicetree-fixes	https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git#dt/linus
+dt-krzk-fixes	https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt.git#fixes
+scsi-fixes	https://git.kernel.org/pub/scm/linux/kernel/git/mkp/scsi.git#fixes
+drm-fixes	https://gitlab.freedesktop.org/drm/kernel.git#drm-fixes
+drm-intel-fixes	https://gitlab.freedesktop.org/drm/i915/kernel.git#for-linux-next-fixes
+mmc-fixes	https://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc.git#fixes
+rtc-fixes	https://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux.git#rtc-fixes
+gnss-fixes	https://git.kernel.org/pub/scm/linux/kernel/git/johan/gnss.git#gnss-linus
+hyperv-fixes	https://git.kernel.org/pub/scm/linux/kernel/git/hyperv/linux.git#hyperv-fixes
+risc-v-fixes	https://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git#fixes
+riscv-dt-fixes	https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git#riscv-dt-fixes
+riscv-soc-fixes	https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git#riscv-soc-fixes
+fpga-fixes	https://git.kernel.org/pub/scm/linux/kernel/git/fpga/linux-fpga.git#fixes
+spdx		https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/spdx.git#spdx-linus
+gpio-brgl-fixes	https://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux.git#gpio/for-current
+gpio-intel-fixes	https://git.kernel.org/pub/scm/linux/kernel/git/andy/linux-gpio-intel.git#fixes
+pinctrl-intel-fixes	https://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel.git#fixes
+auxdisplay-fixes	https://git.kernel.org/pub/scm/linux/kernel/git/andy/linux-auxdisplay.git#fixes
+kunit-fixes	https://git.kernel.org/pub/scm/linux/kernel/git/shuah/linux-kselftest.git#kunit-fixes
+memblock-fixes	https://git.kernel.org/pub/scm/linux/kernel/git/rppt/memblock.git#fixes
+renesas-fixes	https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git#fixes
+perf-current	https://git.kernel.org/pub/scm/linux/kernel/git/perf/perf-tools.git#perf-tools
+efi-fixes	https://git.kernel.org/pub/scm/linux/kernel/git/efi/efi.git#urgent
+battery-fixes	https://git.kernel.org/pub/scm/linux/kernel/git/sre/linux-power-supply.git#fixes
+iommufd-fixes	https://git.kernel.org/pub/scm/linux/kernel/git/jgg/iommufd.git#for-rc
+rust-fixes	https://github.com/Rust-for-Linux/linux.git#rust-fixes
+w1-fixes	https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-w1.git#fixes
+pmdomain-fixes	https://git.kernel.org/pub/scm/linux/kernel/git/ulfh/linux-pm.git#fixes
+i2c-host-fixes	https://git.kernel.org/pub/scm/linux/kernel/git/andi.shyti/linux.git#i2c/i2c-host-fixes
+i2c-rust-fixes	https://github.com/ikrtn/rust-for-linux#rust-i2c-fixes
+sparc-fixes	https://git.kernel.org/pub/scm/linux/kernel/git/alarsson/linux-sparc.git#for-linus
+clk-fixes	https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git#clk-fixes
+thead-clk-fixes	https://git.kernel.org/pub/scm/linux/kernel/git/fustini/linux.git#thead-clk-fixes
+tenstorrent-clk-fixes	https://git.kernel.org/pub/scm/linux/kernel/git/tenstorrent/linux.git#tenstorrent-clk-fixes
+pwrseq-fixes	https://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux.git#pwrseq/for-current
+thead-dt-fixes	https://git.kernel.org/pub/scm/linux/kernel/git/fustini/linux.git#thead-dt-fixes
+ftrace-fixes	https://git.kernel.org/pub/scm/linux/kernel/git/trace/linux-trace.git#ftrace/fixes
+ring-buffer-fixes	https://git.kernel.org/pub/scm/linux/kernel/git/trace/linux-trace.git#ring-buffer/fixes
+trace-fixes	https://git.kernel.org/pub/scm/linux/kernel/git/trace/linux-trace.git#trace/fixes
+tracefs-fixes	https://git.kernel.org/pub/scm/linux/kernel/git/trace/linux-trace.git#tracefs/fixes
+spacemit-fixes	https://github.com/spacemit-com/linux#fixes
+tip-fixes	https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git#tip/urgent
+slab-fixes	https://git.kernel.org/pub/scm/linux/kernel/git/vbabka/slab.git#slab/for-next-fixes
+kexec-fixes	https://git.kernel.org/pub/scm/linux/kernel/git/liveupdate/linux.git#kexec-fixes
+liveupdate-fixes	https://git.kernel.org/pub/scm/linux/kernel/git/liveupdate/linux.git#fixes
+drm-msm-fixes	https://gitlab.freedesktop.org/drm/msm.git#msm-fixes
+uml-fixes	https://git.kernel.org/pub/scm/linux/kernel/git/uml/linux.git#fixes
+fwctl-fixes	https://git.kernel.org/pub/scm/linux/kernel/git/fwctl/fwctl.git#for-rc
+devsec-tsm-fixes	https://git.kernel.org/pub/scm/linux/kernel/git/devsec/tsm.git#fixes
+drm-rust-fixes	https://gitlab.freedesktop.org/drm/rust/kernel.git#drm-rust-fixes
+tenstorrent-dt-fixes	https://git.kernel.org/pub/scm/linux/kernel/git/tenstorrent/linux.git#tenstorrent-dt-fixes
+drm-misc-fixes	https://gitlab.freedesktop.org/drm/misc/kernel.git#for-linux-next-fixes
+rust		https://github.com/Rust-for-Linux/linux.git#rust-next
+rust-interop	https://github.com/Rust-for-Linux/linux.git#interop-next
+rust-alloc	https://github.com/Rust-for-Linux/linux.git#alloc-next
+rust-io		https://github.com/Rust-for-Linux/linux.git#io-next
+rust-pin-init	https://github.com/Rust-for-Linux/linux.git#pin-init-next
+rust-timekeeping	https://github.com/Rust-for-Linux/linux.git#timekeeping-next
+rust-xarray	https://github.com/Rust-for-Linux/linux.git#xarray-next
+rust-analyzer	https://github.com/Rust-for-Linux/linux.git#rust-analyzer-next
+mm-stable	https://git.kernel.org/pub/scm/linux/kernel/git/akpm/mm#mm-stable
+mm-nonmm-stable	https://git.kernel.org/pub/scm/linux/kernel/git/akpm/mm#mm-nonmm-stable
+mm-unstable	https://git.kernel.org/pub/scm/linux/kernel/git/akpm/mm#mm-unstable
+mm-nonmm-unstable	https://git.kernel.org/pub/scm/linux/kernel/git/akpm/mm#mm-nonmm-unstable
+kbuild		https://git.kernel.org/pub/scm/linux/kernel/git/kbuild/linux.git#kbuild-for-next
+clang-format	https://github.com/ojeda/linux.git#clang-format
+perf		https://git.kernel.org/pub/scm/linux/kernel/git/perf/perf-tools-next.git#perf-tools-next
+compiler-attributes	https://github.com/ojeda/linux.git#compiler-attributes
+dma-mapping	https://git.kernel.org/pub/scm/linux/kernel/git/mszyprowski/linux.git#dma-mapping-for-next
+asm-generic	https://git.kernel.org/pub/scm/linux/kernel/git/arnd/asm-generic#master
+nocache-cleanup	https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git#nocache-cleanup
+alpha		https://git.kernel.org/pub/scm/linux/kernel/git/mattst88/alpha.git#alpha-next
+arm		https://git.kernel.org/pub/scm/linux/kernel/git/rmk/linux.git#for-next
+arm64		https://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux#for-next/core
+arm-perf	https://git.kernel.org/pub/scm/linux/kernel/git/will/linux.git#for-next/perf
+arm-soc		https://git.kernel.org/pub/scm/linux/kernel/git/soc/soc.git#for-next
+amlogic		https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux.git#for-next
+asahi-soc	https://github.com/AsahiLinux/linux.git#asahi-soc/for-next
+at91		https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux.git#at91-next
+bmc		https://git.kernel.org/pub/scm/linux/kernel/git/bmc/linux.git#for-next
+broadcom	https://github.com/Broadcom/stblinux.git#next
+cix		https://git.kernel.org/pub/scm/linux/kernel/git/peter.chen/cix.git#for-next
+davinci		https://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux.git#davinci/for-next
+drivers-memory	https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl.git#for-next
+fsl		https://git.kernel.org/pub/scm/linux/kernel/git/chleroy/linux.git#soc_fsl
+imx-mxs		https://git.kernel.org/pub/scm/linux/kernel/git/frank.li/linux.git#for-next
+mediatek	https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux.git#for-next
+mvebu		https://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu.git#for-next
+omap		https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap.git#for-next
+qcom		https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux.git#for-next
+renesas		https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git#next
+reset		https://git.pengutronix.de/git/pza/linux#reset/next
+rockchip	https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git#for-next
+samsung-krzk	https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux.git#for-next
+scmi		https://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux.git#for-linux-next
+sophgo		https://github.com/sophgo/linux.git#for-next
+sophgo-soc	https://github.com/sophgo/linux.git#soc-for-next
+spacemit	https://github.com/spacemit-com/linux#for-next
+stm32		https://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32.git#stm32-next
+sunxi		https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux.git#sunxi/for-next
+tee		https://git.kernel.org/pub/scm/linux/kernel/git/jenswi/linux-tee.git#next
+tegra		https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux.git#for-next
+tenstorrent-dt	https://git.kernel.org/pub/scm/linux/kernel/git/tenstorrent/linux.git#tenstorrent-dt-for-next
+thead-dt	https://git.kernel.org/pub/scm/linux/kernel/git/fustini/linux.git#thead-dt-for-next
+ti		https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux.git#ti-next
+xilinx		https://github.com/Xilinx/linux-xlnx.git#for-next
+socfpga		https://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux.git#for-next
+clk		https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git#clk-next
+clk-imx		https://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux.git#for-next
+clk-renesas	https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git#renesas-clk
+thead-clk	https://git.kernel.org/pub/scm/linux/kernel/git/fustini/linux.git#thead-clk-for-next
+tenstorrent-clk	https://git.kernel.org/pub/scm/linux/kernel/git/tenstorrent/linux.git#tenstorrent-clk-for-next
+csky		https://github.com/c-sky/csky-linux.git#linux-next
+loongarch	https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson.git#loongarch-next
+m68k		https://git.kernel.org/pub/scm/linux/kernel/git/geert/linux-m68k.git#for-next
+m68knommu	https://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu.git#for-next
+microblaze	git://git.monstr.eu/linux-2.6-microblaze.git#next
+mips		https://git.kernel.org/pub/scm/linux/kernel/git/mips/linux.git#mips-next
+openrisc	https://github.com/openrisc/linux.git#for-next
+parisc-hd	https://git.kernel.org/pub/scm/linux/kernel/git/deller/parisc-linux.git#for-next
+powerpc		https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git#next
+risc-v		https://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git#for-next
+riscv-dt	https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git#riscv-dt-for-next
+riscv-soc	https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git#riscv-soc-for-next
+s390		https://git.kernel.org/pub/scm/linux/kernel/git/s390/linux.git#for-next
+sh		https://git.kernel.org/pub/scm/linux/kernel/git/glaubitz/sh-linux.git#for-next
+sparc		https://git.kernel.org/pub/scm/linux/kernel/git/alarsson/linux-sparc.git#for-next
+uml		https://git.kernel.org/pub/scm/linux/kernel/git/uml/linux.git#next
+xtensa		https://github.com/jcmvbkbc/linux-xtensa.git#xtensa-for-next
+printk		https://git.kernel.org/pub/scm/linux/kernel/git/printk/linux.git#for-next
+pci		https://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git#next
+pstore		https://git.kernel.org/pub/scm/linux/kernel/git/kees/linux.git#for-next/pstore
+hid		https://git.kernel.org/pub/scm/linux/kernel/git/hid/hid.git#for-next
+i2c		https://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux.git#i2c/for-next
+i2c-host	https://git.kernel.org/pub/scm/linux/kernel/git/andi.shyti/linux.git#i2c/i2c-host
+i2c-rust	https://github.com/ikrtn/rust-for-linux#rust-i2c-next
+i3c		https://git.kernel.org/pub/scm/linux/kernel/git/i3c/linux.git#i3c/next
+dmi		https://git.kernel.org/pub/scm/linux/kernel/git/jdelvare/staging.git#dmi-for-next
+hwmon-staging	https://git.kernel.org/pub/scm/linux/kernel/git/groeck/linux-staging.git#hwmon-next
+jc_docs		git://git.lwn.net/linux.git#docs-next
+v4l-dvb		git://linuxtv.org/media-ci/media-pending.git#next
+v4l-dvb-next	git://linuxtv.org/mchehab/media-next.git#master
+pm		https://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm.git#linux-next
+cpufreq-arm	https://git.kernel.org/pub/scm/linux/kernel/git/vireshk/pm.git#cpufreq/arm/linux-next
+cpupower	https://git.kernel.org/pub/scm/linux/kernel/git/shuah/linux.git#cpupower
+devfreq		https://git.kernel.org/pub/scm/linux/kernel/git/chanwoo/linux.git#devfreq-next
+pmdomain	https://git.kernel.org/pub/scm/linux/kernel/git/ulfh/linux-pm.git#next
+opp		https://git.kernel.org/pub/scm/linux/kernel/git/vireshk/pm.git#opp/linux-next
+thermal		https://git.kernel.org/pub/scm/linux/kernel/git/thermal/linux.git#thermal/linux-next
+rdma		https://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdma.git#for-next
+net-next	https://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next.git#main
+bpf-next	https://git.kernel.org/pub/scm/linux/kernel/git/bpf/bpf-next.git#for-next
+ipsec-next	https://git.kernel.org/pub/scm/linux/kernel/git/klassert/ipsec-next.git#master
+mlx5-next	https://git.kernel.org/pub/scm/linux/kernel/git/mellanox/linux.git#mlx5-next
+netfilter-next	https://git.kernel.org/pub/scm/linux/kernel/git/netfilter/nf-next.git#main
+ipvs-next	https://git.kernel.org/pub/scm/linux/kernel/git/horms/ipvs-next.git#main
+bluetooth	https://git.kernel.org/pub/scm/linux/kernel/git/bluetooth/bluetooth-next.git#master
+wireless-next	https://git.kernel.org/pub/scm/linux/kernel/git/wireless/wireless-next.git#for-next
+ath-next	https://git.kernel.org/pub/scm/linux/kernel/git/ath/ath.git#for-next
+iwlwifi-next	https://git.kernel.org/pub/scm/linux/kernel/git/iwlwifi/iwlwifi-next.git#next
+wpan-next	https://git.kernel.org/pub/scm/linux/kernel/git/wpan/wpan-next.git#master
+wpan-staging	https://git.kernel.org/pub/scm/linux/kernel/git/wpan/wpan-next.git#staging
+mtd		https://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git#mtd/next
+nand		https://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git#nand/next
+spi-nor		https://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git#spi-nor/next
+crypto		https://git.kernel.org/pub/scm/linux/kernel/git/herbert/cryptodev-2.6.git#master
+libcrypto	https://git.kernel.org/pub/scm/linux/kernel/git/ebiggers/linux.git#libcrypto-next
+drm		https://gitlab.freedesktop.org/drm/kernel.git#drm-next
+drm-exynos	https://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos.git#for-linux-next
+drm-misc	https://gitlab.freedesktop.org/drm/misc/kernel.git#for-linux-next
+amdgpu		https://gitlab.freedesktop.org/agd5f/linux.git#drm-next
+drm-intel	https://gitlab.freedesktop.org/drm/i915/kernel.git#for-linux-next
+drm-msm		https://gitlab.freedesktop.org/drm/msm.git#msm-next
+drm-msm-lumag	https://gitlab.freedesktop.org/lumag/msm.git#msm-next-lumag
+drm-xe		https://gitlab.freedesktop.org/drm/xe/kernel.git#drm-xe-next
+etnaviv		https://git.pengutronix.de/git/lst/linux#etnaviv/next
+drm-rust	https://gitlab.freedesktop.org/drm/rust/kernel.git#drm-rust-next
+drm-nova	https://gitlab.freedesktop.org/drm/nova.git#nova-next
+fbdev		https://git.kernel.org/pub/scm/linux/kernel/git/deller/linux-fbdev.git#for-next
+regmap		https://git.kernel.org/pub/scm/linux/kernel/git/broonie/regmap.git#for-next
+sound		https://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound.git#for-next
+ieee1394	https://git.kernel.org/pub/scm/linux/kernel/git/ieee1394/linux1394.git#for-next
+sound-asoc	https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git#for-next
+modules		https://git.kernel.org/pub/scm/linux/kernel/git/modules/linux.git#modules-next
+input		https://git.kernel.org/pub/scm/linux/kernel/git/dtor/input.git#next
+block		https://git.kernel.org/pub/scm/linux/kernel/git/axboe/linux.git#for-next
+device-mapper	https://git.kernel.org/pub/scm/linux/kernel/git/device-mapper/linux-dm.git#for-next
+libata		https://git.kernel.org/pub/scm/linux/kernel/git/libata/linux#for-next
+pcmcia		https://git.kernel.org/pub/scm/linux/kernel/git/brodo/linux.git#pcmcia-next
+mmc		https://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc.git#next
+mfd		https://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd.git#for-mfd-next
+backlight	https://git.kernel.org/pub/scm/linux/kernel/git/lee/backlight.git#for-backlight-next
+battery		https://git.kernel.org/pub/scm/linux/kernel/git/sre/linux-power-supply.git#for-next
+regulator	https://git.kernel.org/pub/scm/linux/kernel/git/broonie/regulator.git#for-next
+security	https://git.kernel.org/pub/scm/linux/kernel/git/pcmoore/lsm.git#next
+apparmor	https://git.kernel.org/pub/scm/linux/kernel/git/jj/linux-apparmor#apparmor-next
+integrity	https://git.kernel.org/pub/scm/linux/kernel/git/zohar/linux-integrity#next-integrity
+selinux		https://git.kernel.org/pub/scm/linux/kernel/git/pcmoore/selinux.git#next
+smack		https://github.com/cschaufler/smack-next#next
+tomoyo		git://git.code.sf.net/p/tomoyo/tomoyo.git#master
+tpmdd-tpm	https://git.kernel.org/pub/scm/linux/kernel/git/jarkko/linux-tpmdd.git#for-next-tpm
+tpmdd-keys	https://git.kernel.org/pub/scm/linux/kernel/git/jarkko/linux-tpmdd.git#for-next-keys
+watchdog	git://www.linux-watchdog.org/linux-watchdog-next.git#master
+iommu		https://git.kernel.org/pub/scm/linux/kernel/git/iommu/linux.git#next
+audit		https://git.kernel.org/pub/scm/linux/kernel/git/pcmoore/audit.git#next
+devicetree	https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git#for-next
+dt-krzk		https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt.git#for-next
+mailbox		https://git.kernel.org/pub/scm/linux/kernel/git/jassibrar/mailbox.git#for-next
+spi		https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git#for-next
+tip		https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git#master
+kexec		https://git.kernel.org/pub/scm/linux/kernel/git/liveupdate/linux.git#kexec-next
+liveupdate	https://git.kernel.org/pub/scm/linux/kernel/git/liveupdate/linux.git#next
+clockevents	https://git.kernel.org/pub/scm/linux/kernel/git/daniel.lezcano/linux.git#timers/drivers/next
+edac		https://git.kernel.org/pub/scm/linux/kernel/git/ras/ras.git#edac-for-next
+ftrace		https://git.kernel.org/pub/scm/linux/kernel/git/trace/linux-trace.git#for-next
+rcu		https://git.kernel.org/pub/scm/linux/kernel/git/rcu/linux#next
+paulmck		https://git.kernel.org/pub/scm/linux/kernel/git/paulmck/linux-rcu.git#non-rcu/next
+kvm		git://git.kernel.org/pub/scm/virt/kvm/kvm.git#next
+kvm-arm		https://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm.git#next
+kvms390		https://git.kernel.org/pub/scm/linux/kernel/git/kvms390/linux.git#next
+kvm-ppc		https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git#topic/ppc-kvm
+kvm-riscv	https://github.com/kvm-riscv/linux.git#riscv_kvm_next
+kvm-x86		https://github.com/kvm-x86/linux.git#next
+xen-tip		https://git.kernel.org/pub/scm/linux/kernel/git/xen/tip.git#linux-next
+percpu		https://git.kernel.org/pub/scm/linux/kernel/git/dennis/percpu.git#for-next
+workqueues	https://git.kernel.org/pub/scm/linux/kernel/git/tj/wq.git#for-next
+sched-ext	https://git.kernel.org/pub/scm/linux/kernel/git/tj/sched_ext.git#for-next
+drivers-x86	https://git.kernel.org/pub/scm/linux/kernel/git/pdx86/platform-drivers-x86.git#for-next
+chrome-platform	https://git.kernel.org/pub/scm/linux/kernel/git/chrome-platform/linux.git#for-next
+chrome-platform-firmware	https://git.kernel.org/pub/scm/linux/kernel/git/chrome-platform/linux.git#for-firmware-next
+hsi		https://git.kernel.org/pub/scm/linux/kernel/git/sre/linux-hsi.git#for-next
+leds-lj		https://git.kernel.org/pub/scm/linux/kernel/git/lee/leds.git#for-leds-next
+ipmi		https://github.com/cminyard/linux-ipmi.git#for-next
+driver-core	https://git.kernel.org/pub/scm/linux/kernel/git/driver-core/driver-core.git#driver-core-next
+usb		https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb.git#usb-next
+thunderbolt	https://git.kernel.org/pub/scm/linux/kernel/git/westeri/thunderbolt.git#next
+usb-serial	https://git.kernel.org/pub/scm/linux/kernel/git/johan/usb-serial.git#usb-next
+tty		https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty.git#tty-next
+char-misc	https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc.git#char-misc-next
+coresight	https://git.kernel.org/pub/scm/linux/kernel/git/coresight/linux.git#next
+fastrpc		https://git.kernel.org/pub/scm/linux/kernel/git/srini/fastrpc.git#for-next
+fpga		https://git.kernel.org/pub/scm/linux/kernel/git/fpga/linux-fpga.git#for-next
+icc		https://git.kernel.org/pub/scm/linux/kernel/git/djakov/icc.git#icc-next
+iio		https://git.kernel.org/pub/scm/linux/kernel/git/jic23/iio.git#togreg
+phy-next	https://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy.git#next
+soundwire	https://git.kernel.org/pub/scm/linux/kernel/git/vkoul/soundwire.git#next
+extcon		https://git.kernel.org/pub/scm/linux/kernel/git/chanwoo/extcon.git#extcon-next
+gnss		https://git.kernel.org/pub/scm/linux/kernel/git/johan/gnss.git#gnss-next
+vfio		https://github.com/awilliam/linux-vfio.git#next
+w1		https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-w1.git#for-next
+spmi		https://git.kernel.org/pub/scm/linux/kernel/git/sboyd/spmi.git#spmi-next
+staging		https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging.git#staging-next
+counter-next	https://git.kernel.org/pub/scm/linux/kernel/git/wbg/counter.git#counter-next
+mux		https://gitlab.com/peda-linux/mux.git#for-next
+dmaengine	https://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine.git#next
+cgroup		https://git.kernel.org/pub/scm/linux/kernel/git/tj/cgroup.git#for-next
+scsi		https://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi.git#for-next
+scsi-mkp	https://git.kernel.org/pub/scm/linux/kernel/git/mkp/scsi.git#for-next
+vhost		https://git.kernel.org/pub/scm/linux/kernel/git/mst/vhost.git#linux-next
+rpmsg		https://git.kernel.org/pub/scm/linux/kernel/git/remoteproc/linux.git#for-next
+gpio-brgl	https://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux.git#gpio/for-next
+gpio-intel	https://git.kernel.org/pub/scm/linux/kernel/git/andy/linux-gpio-intel.git#for-next
+pinctrl		https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git#for-next
+pinctrl-intel	https://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel.git#for-next
+pinctrl-renesas	https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git#renesas-pinctrl
+pinctrl-samsung	https://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung.git#for-next
+pwm		https://git.kernel.org/pub/scm/linux/kernel/git/ukleinek/linux.git#pwm/for-next
+ktest		https://git.kernel.org/pub/scm/linux/kernel/git/rostedt/linux-ktest.git#for-next
+kselftest	https://git.kernel.org/pub/scm/linux/kernel/git/shuah/linux-kselftest.git#next
+kunit		https://git.kernel.org/pub/scm/linux/kernel/git/shuah/linux-kselftest.git#test
+kunit-next	https://git.kernel.org/pub/scm/linux/kernel/git/shuah/linux-kselftest.git#kunit
+livepatching	https://git.kernel.org/pub/scm/linux/kernel/git/livepatching/livepatching.git#for-next
+rtc		https://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux.git#rtc-next
+nvdimm		https://git.kernel.org/pub/scm/linux/kernel/git/nvdimm/nvdimm.git#libnvdimm-for-next
+at24		https://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux.git#at24/for-next
+ntb		https://github.com/jonmason/ntb.git#ntb-next
+seccomp		https://git.kernel.org/pub/scm/linux/kernel/git/kees/linux.git#for-next/seccomp
+slimbus		https://git.kernel.org/pub/scm/linux/kernel/git/srini/slimbus.git#for-next
+nvmem		https://git.kernel.org/pub/scm/linux/kernel/git/srini/nvmem.git#for-next
+hyperv		https://git.kernel.org/pub/scm/linux/kernel/git/hyperv/linux.git#hyperv-next
+auxdisplay	https://git.kernel.org/pub/scm/linux/kernel/git/andy/linux-auxdisplay.git#for-next
+kgdb		https://git.kernel.org/pub/scm/linux/kernel/git/danielt/linux.git#kgdb/for-next
+hmm		https://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdma.git#hmm
+cfi		https://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git#cfi/next
+mhi		https://git.kernel.org/pub/scm/linux/kernel/git/mani/mhi.git#mhi-next
+memblock	https://git.kernel.org/pub/scm/linux/kernel/git/rppt/memblock.git#for-next
+cxl		https://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl.git#next
+zstd		https://github.com/terrelln/linux.git#zstd-next
+efi		https://git.kernel.org/pub/scm/linux/kernel/git/efi/efi.git#next
+unicode		https://git.kernel.org/pub/scm/linux/kernel/git/krisman/unicode.git#for-next
+slab		https://git.kernel.org/pub/scm/linux/kernel/git/vbabka/slab.git#slab/for-next
+random		https://git.kernel.org/pub/scm/linux/kernel/git/crng/random.git#master
+landlock	https://git.kernel.org/pub/scm/linux/kernel/git/mic/linux.git#next
+sysctl		https://git.kernel.org/pub/scm/linux/kernel/git/sysctl/sysctl.git#sysctl-next
+execve		https://git.kernel.org/pub/scm/linux/kernel/git/kees/linux.git#for-next/execve
+bitmap		https://github.com/norov/linux.git#bitmap-for-next
+hte		https://git.kernel.org/pub/scm/linux/kernel/git/pateldipen1984/linux.git#for-next
+kspp		https://git.kernel.org/pub/scm/linux/kernel/git/kees/linux.git#for-next/kspp
+nolibc		https://git.kernel.org/pub/scm/linux/kernel/git/nolibc/linux-nolibc.git#for-next
+iommufd		https://git.kernel.org/pub/scm/linux/kernel/git/jgg/iommufd.git#for-next
+turbostat	https://git.kernel.org/pub/scm/linux/kernel/git/lenb/linux.git#next
+pwrseq		https://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux.git#pwrseq/for-next
+capabilities-next	https://git.kernel.org/pub/scm/linux/kernel/git/sergeh/linux.git#caps-next
+ipe		https://git.kernel.org/pub/scm/linux/kernel/git/wufan/ipe.git#next
+kcsan		https://git.kernel.org/pub/scm/linux/kernel/git/melver/linux.git#next
+crc		https://git.kernel.org/pub/scm/linux/kernel/git/ebiggers/linux.git#crc-next
+keys-next	https://git.kernel.org/pub/scm/linux/kernel/git/dhowells/linux-fs.git#keys-next
+fwctl		https://git.kernel.org/pub/scm/linux/kernel/git/fwctl/fwctl.git#for-next
+devsec-tsm	https://git.kernel.org/pub/scm/linux/kernel/git/devsec/tsm.git#next
+hisilicon	https://github.com/hisilicon/linux-hisi.git#for-next
+kthread		https://git.kernel.org/pub/scm/linux/kernel/git/frederic/linux-dynticks.git#for-next
diff --git a/Next/merge.log b/Next/merge.log
new file mode 100644
index 000000000000..d8ba3335fcfd
--- /dev/null
+++ b/Next/merge.log
@@ -0,0 +1,4214 @@
+$ date -R
+Mon, 27 Apr 2026 09:40:39 +0200
+$ git checkout master
+Already on 'master'
+$ git reset --hard stable
+HEAD is now at dd6c438c3e64 Merge tag 'vfs-7.1-rc1.fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/vfs/vfs
+Merging origin/master (254f49634ee1 Linux 7.1-rc1)
+$ git merge -m Merge branch 'master' of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git origin/master
+Updating dd6c438c3e64..254f49634ee1
+Fast-forward (no commit created; -m option ignored)
+ .mailmap                                           |    1 +
+ CREDITS                                            |    5 +
+ Documentation/.renames.txt                         |    6 -
+ Documentation/ABI/stable/sysfs-driver-speakup      |    4 +-
+ .../ABI/testing/sysfs-bus-coresight-devices-tpdm   |   10 +
+ Documentation/ABI/testing/sysfs-bus-iio            |    2 +-
+ Documentation/admin-guide/kernel-parameters.txt    |   18 -
+ .../devicetree/bindings/extcon/extcon-ptn5150.yaml |    3 +
+ .../devicetree/bindings/iio/accel/adi,adxl372.yaml |    9 +-
+ .../bindings/iio/accel/bosch,bma255.yaml           |   38 +-
+ .../devicetree/bindings/iio/adc/adi,ad4030.yaml    |   64 +
+ .../devicetree/bindings/iio/adc/adi,ad4080.yaml    |    3 +
+ .../devicetree/bindings/iio/adc/adi,ad7380.yaml    |   23 +
+ .../bindings/iio/adc/amlogic,meson-saradc.yaml     |    4 +
+ .../devicetree/bindings/iio/adc/lltc,ltc2497.yaml  |    7 +
+ .../bindings/iio/adc/motorola,cpcap-adc.yaml       |    1 +
+ .../bindings/iio/adc/qcom,spmi-adc5-gen3.yaml      |  151 +
+ .../bindings/iio/adc/qcom,spmi-vadc-common.yaml    |   84 +
+ .../bindings/iio/adc/qcom,spmi-vadc.yaml           |   78 +-
+ .../bindings/iio/amplifiers/adi,ad8366.yaml        |  101 +
+ .../devicetree/bindings/iio/dac/lltc,ltc2632.yaml  |   57 +-
+ .../devicetree/bindings/iio/dac/maxim,ds4424.yaml  |   42 +-
+ .../devicetree/bindings/iio/dac/ti,dac7612.yaml    |    2 +-
+ .../bindings/iio/gyroscope/bosch,bmg160.yaml       |   12 +-
+ .../bindings/iio/light/vishay,vcnl4000.yaml        |   31 +-
+ .../iio/magnetometer/bosch,bmc150_magn.yaml        |   14 +-
+ .../bindings/iio/proximity/st,vl53l0x.yaml         |   22 +-
+ .../bindings/iio/proximity/tyhx,hx9023s.yaml       |    4 +
+ .../bindings/interconnect/qcom,glymur-rpmh.yaml    |  136 +-
+ .../bindings/interconnect/qcom,msm8974.yaml        |   28 +-
+ .../bindings/interconnect/qcom,osm-l3.yaml         |    1 +
+ .../bindings/interconnect/qcom,qcs615-rpmh.yaml    |   23 +
+ .../bindings/interconnect/qcom,qcs8300-rpmh.yaml   |   63 +
+ .../devicetree/bindings/mfd/qcom,spmi-pmic.yaml    |    1 +
+ .../devicetree/bindings/misc/qcom,fastrpc.yaml     |   11 +-
+ .../devicetree/bindings/misc/ti,fpc202.yaml        |   21 +
+ .../bindings/nvmem/layouts/kontron,sl28-vpd.yaml   |    7 +-
+ .../devicetree/bindings/nvmem/qcom,qfprom.yaml     |    1 +
+ .../devicetree/bindings/nvmem/rockchip,otp.yaml    |   83 +-
+ .../devicetree/bindings/rtc/isil,isl12026.txt      |   28 -
+ .../devicetree/bindings/rtc/isil,isl12026.yaml     |   59 +
+ .../bindings/rtc/microchip,mpfs-rtc.yaml           |    3 +
+ .../bindings/rtc/microcrystal,rv3028.yaml          |    2 +
+ .../devicetree/bindings/rtc/olpc-xo1-rtc.txt       |    5 -
+ .../devicetree/bindings/rtc/sprd,sc2731-rtc.yaml   |    7 +-
+ .../devicetree/bindings/rtc/trivial-rtc.yaml       |    2 +
+ .../devicetree/bindings/sound/ti,tas2781.yaml      |    7 +-
+ Documentation/devicetree/bindings/spi/fsl,spi.yaml |    6 +-
+ .../features/vm/ioremap_prot/arch-support.txt      |    2 +-
+ Documentation/iio/ad4030.rst                       |   39 +
+ Documentation/iio/ad7191.rst                       |    6 +-
+ Documentation/iio/adxl345.rst                      |   89 +-
+ Documentation/isdn/credits.rst                     |   73 -
+ Documentation/isdn/index.rst                       |   14 -
+ Documentation/isdn/interface_capi.rst              |  336 --
+ Documentation/isdn/m_isdn.rst                      |    9 -
+ Documentation/networking/6pack.rst                 |  191 -
+ Documentation/networking/ax25.rst                  |   17 -
+ Documentation/networking/caif/caif.rst             |  138 -
+ Documentation/networking/caif/index.rst            |   12 -
+ Documentation/networking/caif/linux_caif.rst       |  195 -
+ .../networking/device_drivers/atm/fore200e.rst     |   66 -
+ .../networking/device_drivers/atm/index.rst        |    2 -
+ .../networking/device_drivers/atm/iphase.rst       |  193 -
+ .../device_drivers/ethernet/3com/3c509.rst         |  249 -
+ .../networking/device_drivers/ethernet/index.rst   |    2 -
+ .../device_drivers/ethernet/smsc/smc9.rst          |   48 -
+ .../networking/device_drivers/hamradio/baycom.rst  |  174 -
+ .../networking/device_drivers/hamradio/index.rst   |   12 -
+ .../device_drivers/hamradio/z8530drv.rst           |  686 ---
+ Documentation/networking/device_drivers/index.rst  |    1 -
+ Documentation/networking/index.rst                 |    3 -
+ Documentation/process/license-rules.rst            |    7 +-
+ Documentation/staging/magic-number.rst             |    3 -
+ Documentation/subsystem-apis.rst                   |    1 -
+ .../translations/it_IT/staging/magic-number.rst    |    3 -
+ .../translations/sp_SP/process/magic-number.rst    |    3 -
+ .../translations/zh_CN/networking/index.rst        |    1 -
+ .../translations/zh_CN/process/magic-number.rst    |    3 -
+ .../translations/zh_TW/process/magic-number.rst    |    3 -
+ MAINTAINERS                                        |  166 +-
+ Makefile                                           |    6 +-
+ arch/alpha/configs/defconfig                       |    1 -
+ arch/arm/Kconfig                                   |    1 +
+ arch/arm/configs/ixp4xx_defconfig                  |    4 -
+ arch/arm/configs/neponset_defconfig                |    1 -
+ arch/arm/configs/u8500_defconfig                   |    1 -
+ arch/arm/kernel/module-plts.c                      |   12 +
+ arch/arm/mm/fault.c                                |  158 +-
+ arch/arm/mm/fault.h                                |   42 +-
+ arch/arm/mm/flush.c                                |    4 +-
+ arch/loongarch/Kconfig                             |  120 +-
+ arch/loongarch/Makefile                            |   23 +-
+ arch/loongarch/boot/Makefile                       |    6 +
+ arch/loongarch/include/asm/cacheflush.h            |   16 +-
+ arch/loongarch/include/asm/cpu-features.h          |    1 +
+ arch/loongarch/include/asm/cpu.h                   |   64 +-
+ arch/loongarch/include/asm/fixmap.h                |   14 +
+ arch/loongarch/include/asm/highmem.h               |   43 +
+ arch/loongarch/include/asm/inst.h                  |   10 +
+ arch/loongarch/include/asm/irq_work.h              |    2 +-
+ arch/loongarch/include/asm/jump_label.h            |    2 +
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+ include/linux/mISDNhw.h                            |  192 -
+ include/linux/mISDNif.h                            |  603 ---
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+ include/linux/yam.h                                |   67 -
+ include/net/9p/9p.h                                |   38 +-
+ include/net/Space.h                                |    5 -
+ include/net/atmclip.h                              |   53 -
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+ include/net/netrom.h                               |  273 -
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+ net/atm/clip.c                                     |  960 ----
+ net/atm/ioctl.c                                    |   14 -
+ net/atm/lec.c                                      | 2274 --------
+ net/atm/lec.h                                      |  155 -
+ net/atm/lec_arpc.h                                 |   97 -
+ net/atm/mpc.c                                      | 1538 ------
+ net/atm/mpc.h                                      |   65 -
+ net/atm/mpoa_caches.c                              |  565 --
+ net/atm/mpoa_caches.h                              |   99 -
+ net/atm/mpoa_proc.c                                |  307 --
+ net/atm/proc.c                                     |   11 -
+ net/ax25/Kconfig                                   |  108 -
+ net/ax25/Makefile                                  |   12 -
+ net/ax25/af_ax25.c                                 | 2089 --------
+ net/ax25/ax25_addr.c                               |  303 --
+ net/ax25/ax25_dev.c                                |  200 -
+ net/ax25/ax25_ds_in.c                              |  298 --
+ net/ax25/ax25_ds_subr.c                            |  204 -
+ net/ax25/ax25_ds_timer.c                           |  235 -
+ net/ax25/ax25_iface.c                              |  214 -
+ net/ax25/ax25_in.c                                 |  455 --
+ net/ax25/ax25_ip.c                                 |  247 -
+ net/ax25/ax25_out.c                                |  398 --
+ net/ax25/ax25_route.c                              |  416 --
+ net/ax25/ax25_std_in.c                             |  443 --
+ net/ax25/ax25_std_subr.c                           |   83 -
+ net/ax25/ax25_std_timer.c                          |  175 -
+ net/ax25/ax25_subr.c                               |  296 --
+ net/ax25/ax25_timer.c                              |  224 -
+ net/ax25/ax25_uid.c                                |  204 -
+ net/ax25/sysctl_net_ax25.c                         |  181 -
+ net/bluetooth/Kconfig                              |    3 -
+ net/bluetooth/Makefile                             |    1 -
+ net/bluetooth/cmtp/Kconfig                         |   12 -
+ net/bluetooth/cmtp/Makefile                        |    8 -
+ net/bluetooth/cmtp/capi.c                          |  579 --
+ net/bluetooth/cmtp/cmtp.h                          |  129 -
+ net/bluetooth/cmtp/core.c                          |  519 --
+ net/bluetooth/cmtp/sock.c                          |  271 -
+ net/bridge/br.c                                    |    7 -
+ net/bridge/br_fdb.c                                |   29 -
+ net/bridge/br_private.h                            |    4 -
+ net/caif/Kconfig                                   |   54 -
+ net/caif/Makefile                                  |   16 -
+ net/caif/caif_dev.c                                |  586 ---
+ net/caif/caif_socket.c                             | 1114 ----
+ net/caif/caif_usb.c                                |  216 -
+ net/caif/cfcnfg.c                                  |  612 ---
+ net/caif/cfctrl.c                                  |  631 ---
+ net/caif/cfdbgl.c                                  |   55 -
+ net/caif/cfdgml.c                                  |  113 -
+ net/caif/cffrml.c                                  |  204 -
+ net/caif/cfmuxl.c                                  |  267 -
+ net/caif/cfpkt_skbuff.c                            |  373 --
+ net/caif/cfrfml.c                                  |  299 --
+ net/caif/cfserl.c                                  |  192 -
+ net/caif/cfsrvl.c                                  |  224 -
+ net/caif/cfutill.c                                 |  104 -
+ net/caif/cfveil.c                                  |  101 -
+ net/caif/cfvidl.c                                  |   65 -
+ net/caif/chnl_net.c                                |  531 --
+ net/ceph/auth.c                                    |    4 +-
+ net/ceph/crush/mapper.c                            |    7 +-
+ net/ceph/messenger.c                               |    4 +-
+ net/ceph/messenger_v2.c                            |   13 +-
+ net/ceph/mon_client.c                              |    2 +
+ net/core/dev.c                                     |    7 -
+ net/ipv4/arp.c                                     |    1 -
+ net/netrom/Makefile                                |   10 -
+ net/netrom/af_netrom.c                             | 1536 ------
+ net/netrom/nr_dev.c                                |  178 -
+ net/netrom/nr_in.c                                 |  301 --
+ net/netrom/nr_loopback.c                           |   73 -
+ net/netrom/nr_out.c                                |  272 -
+ net/netrom/nr_route.c                              |  989 ----
+ net/netrom/nr_subr.c                               |  280 -
+ net/netrom/nr_timer.c                              |  249 -
+ net/netrom/sysctl_net_netrom.c                     |  156 -
+ net/rose/Makefile                                  |   10 -
+ net/rose/af_rose.c                                 | 1687 ------
+ net/rose/rose_dev.c                                |  141 -
+ net/rose/rose_in.c                                 |  301 --
+ net/rose/rose_link.c                               |  289 -
+ net/rose/rose_loopback.c                           |  133 -
+ net/rose/rose_out.c                                |  122 -
+ net/rose/rose_route.c                              | 1333 -----
+ net/rose/rose_subr.c                               |  556 --
+ net/rose/rose_timer.c                              |  227 -
+ net/rose/sysctl_net_rose.c                         |  125 -
+ net/sunrpc/xprt.c                                  |   16 +
+ net/sunrpc/xprtrdma/frwr_ops.c                     |  177 +-
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+ net/sunrpc/xprtrdma/verbs.c                        |   19 +-
+ net/sunrpc/xprtrdma/xprt_rdma.h                    |   43 +-
+ rust/kernel/alloc/kvec.rs                          |  216 +-
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+ sound/hda/common/hda_controller.h                  |    4 -
+ sound/hda/controllers/intel.c                      |   58 +-
+ sound/pci/als4000.c                                |   44 +-
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+ tools/power/x86/turbostat/turbostat.c              |  231 +-
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+ 1113 files changed, 19454 insertions(+), 145125 deletions(-)
+ create mode 100644 Documentation/devicetree/bindings/iio/adc/qcom,spmi-adc5-gen3.yaml
+ create mode 100644 Documentation/devicetree/bindings/iio/adc/qcom,spmi-vadc-common.yaml
+ create mode 100644 Documentation/devicetree/bindings/iio/amplifiers/adi,ad8366.yaml
+ delete mode 100644 Documentation/devicetree/bindings/rtc/isil,isl12026.txt
+ create mode 100644 Documentation/devicetree/bindings/rtc/isil,isl12026.yaml
+ delete mode 100644 Documentation/devicetree/bindings/rtc/olpc-xo1-rtc.txt
+ delete mode 100644 Documentation/isdn/credits.rst
+ delete mode 100644 Documentation/isdn/index.rst
+ delete mode 100644 Documentation/isdn/interface_capi.rst
+ delete mode 100644 Documentation/isdn/m_isdn.rst
+ delete mode 100644 Documentation/networking/6pack.rst
+ delete mode 100644 Documentation/networking/ax25.rst
+ delete mode 100644 Documentation/networking/caif/caif.rst
+ delete mode 100644 Documentation/networking/caif/index.rst
+ delete mode 100644 Documentation/networking/caif/linux_caif.rst
+ delete mode 100644 Documentation/networking/device_drivers/atm/fore200e.rst
+ delete mode 100644 Documentation/networking/device_drivers/atm/iphase.rst
+ delete mode 100644 Documentation/networking/device_drivers/ethernet/3com/3c509.rst
+ delete mode 100644 Documentation/networking/device_drivers/ethernet/smsc/smc9.rst
+ delete mode 100644 Documentation/networking/device_drivers/hamradio/baycom.rst
+ delete mode 100644 Documentation/networking/device_drivers/hamradio/index.rst
+ delete mode 100644 Documentation/networking/device_drivers/hamradio/z8530drv.rst
+ create mode 100644 arch/loongarch/include/asm/highmem.h
+ create mode 100644 arch/loongarch/mm/highmem.c
+ delete mode 100644 arch/riscv/include/asm/xip_fixup.h
+ create mode 100644 arch/riscv/kernel/vdso_cfi/.gitignore
+ create mode 100644 arch/riscv/lib/strchr.S
+ create mode 100644 arch/riscv/lib/strnlen.S
+ create mode 100644 arch/riscv/lib/strrchr.S
+ delete mode 100644 drivers/atm/.gitignore
+ delete mode 100644 drivers/atm/adummy.c
+ delete mode 100644 drivers/atm/atmtcp.c
+ delete mode 100644 drivers/atm/eni.c
+ delete mode 100644 drivers/atm/eni.h
+ delete mode 100644 drivers/atm/fore200e.c
+ delete mode 100644 drivers/atm/fore200e.h
+ delete mode 100644 drivers/atm/he.c
+ delete mode 100644 drivers/atm/he.h
+ delete mode 100644 drivers/atm/idt77105.c
+ delete mode 100644 drivers/atm/idt77105.h
+ delete mode 100644 drivers/atm/idt77252.c
+ delete mode 100644 drivers/atm/idt77252.h
+ delete mode 100644 drivers/atm/idt77252_tables.h
+ delete mode 100644 drivers/atm/iphase.c
+ delete mode 100644 drivers/atm/iphase.h
+ delete mode 100644 drivers/atm/lanai.c
+ delete mode 100644 drivers/atm/midway.h
+ delete mode 100644 drivers/atm/nicstar.c
+ delete mode 100644 drivers/atm/nicstar.h
+ delete mode 100644 drivers/atm/nicstarmac.c
+ delete mode 100644 drivers/atm/nicstarmac.copyright
+ delete mode 100644 drivers/atm/suni.c
+ delete mode 100644 drivers/atm/suni.h
+ delete mode 100644 drivers/atm/tonga.h
+ delete mode 100644 drivers/atm/zeprom.h
+ create mode 100644 drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn42.c
+ create mode 100644 drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_dcn42.h
+ create mode 100644 drivers/iio/adc/qcom-spmi-adc5-gen3.c
+ create mode 100644 drivers/iio/proximity/vl53l1x-i2c.c
+ create mode 100644 drivers/interconnect/qcom/eliza.c
+ delete mode 100644 drivers/isdn/Kconfig
+ delete mode 100644 drivers/isdn/Makefile
+ delete mode 100644 drivers/isdn/capi/Kconfig
+ delete mode 100644 drivers/isdn/capi/Makefile
+ delete mode 100644 drivers/isdn/capi/capi.c
+ delete mode 100644 drivers/isdn/capi/capiutil.c
+ delete mode 100644 drivers/isdn/capi/kcapi.c
+ delete mode 100644 drivers/isdn/capi/kcapi.h
+ delete mode 100644 drivers/isdn/capi/kcapi_proc.c
+ delete mode 100644 drivers/isdn/hardware/Makefile
+ delete mode 100644 drivers/isdn/hardware/mISDN/Kconfig
+ delete mode 100644 drivers/isdn/hardware/mISDN/Makefile
+ delete mode 100644 drivers/isdn/hardware/mISDN/avmfritz.c
+ delete mode 100644 drivers/isdn/hardware/mISDN/hfc_multi.h
+ delete mode 100644 drivers/isdn/hardware/mISDN/hfc_multi_8xx.h
+ delete mode 100644 drivers/isdn/hardware/mISDN/hfc_pci.h
+ delete mode 100644 drivers/isdn/hardware/mISDN/hfcmulti.c
+ delete mode 100644 drivers/isdn/hardware/mISDN/hfcpci.c
+ delete mode 100644 drivers/isdn/hardware/mISDN/hfcsusb.c
+ delete mode 100644 drivers/isdn/hardware/mISDN/hfcsusb.h
+ delete mode 100644 drivers/isdn/hardware/mISDN/iohelper.h
+ delete mode 100644 drivers/isdn/hardware/mISDN/ipac.h
+ delete mode 100644 drivers/isdn/hardware/mISDN/isar.h
+ delete mode 100644 drivers/isdn/hardware/mISDN/isdnhdlc.c
+ delete mode 100644 drivers/isdn/hardware/mISDN/isdnhdlc.h
+ delete mode 100644 drivers/isdn/hardware/mISDN/mISDNinfineon.c
+ delete mode 100644 drivers/isdn/hardware/mISDN/mISDNipac.c
+ delete mode 100644 drivers/isdn/hardware/mISDN/mISDNisar.c
+ delete mode 100644 drivers/isdn/hardware/mISDN/netjet.c
+ delete mode 100644 drivers/isdn/hardware/mISDN/netjet.h
+ delete mode 100644 drivers/isdn/hardware/mISDN/speedfax.c
+ delete mode 100644 drivers/isdn/hardware/mISDN/w6692.c
+ delete mode 100644 drivers/isdn/hardware/mISDN/w6692.h
+ delete mode 100644 drivers/isdn/mISDN/Kconfig
+ delete mode 100644 drivers/isdn/mISDN/Makefile
+ delete mode 100644 drivers/isdn/mISDN/clock.c
+ delete mode 100644 drivers/isdn/mISDN/core.c
+ delete mode 100644 drivers/isdn/mISDN/core.h
+ delete mode 100644 drivers/isdn/mISDN/dsp.h
+ delete mode 100644 drivers/isdn/mISDN/dsp_audio.c
+ delete mode 100644 drivers/isdn/mISDN/dsp_biquad.h
+ delete mode 100644 drivers/isdn/mISDN/dsp_blowfish.c
+ delete mode 100644 drivers/isdn/mISDN/dsp_cmx.c
+ delete mode 100644 drivers/isdn/mISDN/dsp_core.c
+ delete mode 100644 drivers/isdn/mISDN/dsp_dtmf.c
+ delete mode 100644 drivers/isdn/mISDN/dsp_ecdis.h
+ delete mode 100644 drivers/isdn/mISDN/dsp_hwec.c
+ delete mode 100644 drivers/isdn/mISDN/dsp_hwec.h
+ delete mode 100644 drivers/isdn/mISDN/dsp_pipeline.c
+ delete mode 100644 drivers/isdn/mISDN/dsp_tones.c
+ delete mode 100644 drivers/isdn/mISDN/fsm.c
+ delete mode 100644 drivers/isdn/mISDN/fsm.h
+ delete mode 100644 drivers/isdn/mISDN/hwchannel.c
+ delete mode 100644 drivers/isdn/mISDN/l1oip.h
+ delete mode 100644 drivers/isdn/mISDN/l1oip_codec.c
+ delete mode 100644 drivers/isdn/mISDN/l1oip_core.c
+ delete mode 100644 drivers/isdn/mISDN/layer1.c
+ delete mode 100644 drivers/isdn/mISDN/layer1.h
+ delete mode 100644 drivers/isdn/mISDN/layer2.c
+ delete mode 100644 drivers/isdn/mISDN/layer2.h
+ delete mode 100644 drivers/isdn/mISDN/socket.c
+ delete mode 100644 drivers/isdn/mISDN/stack.c
+ delete mode 100644 drivers/isdn/mISDN/tei.c
+ delete mode 100644 drivers/isdn/mISDN/timerdev.c
+ create mode 100644 drivers/misc/mei/pci-csc.c
+ delete mode 100644 drivers/net/caif/Kconfig
+ delete mode 100644 drivers/net/caif/Makefile
+ delete mode 100644 drivers/net/caif/caif_serial.c
+ delete mode 100644 drivers/net/caif/caif_virtio.c
+ delete mode 100644 drivers/net/ethernet/3com/3c509.c
+ delete mode 100644 drivers/net/ethernet/3com/3c515.c
+ delete mode 100644 drivers/net/ethernet/3com/3c574_cs.c
+ delete mode 100644 drivers/net/ethernet/3com/3c589_cs.c
+ delete mode 100644 drivers/net/ethernet/8390/axnet_cs.c
+ delete mode 100644 drivers/net/ethernet/8390/smc-ultra.c
+ delete mode 100644 drivers/net/ethernet/8390/wd.c
+ delete mode 100644 drivers/net/ethernet/amd/lance.c
+ delete mode 100644 drivers/net/ethernet/amd/nmclan_cs.c
+ delete mode 100644 drivers/net/ethernet/fujitsu/Kconfig
+ delete mode 100644 drivers/net/ethernet/fujitsu/Makefile
+ delete mode 100644 drivers/net/ethernet/fujitsu/fmvj18x_cs.c
+ delete mode 100644 drivers/net/ethernet/packetengines/Kconfig
+ delete mode 100644 drivers/net/ethernet/packetengines/Makefile
+ delete mode 100644 drivers/net/ethernet/packetengines/hamachi.c
+ delete mode 100644 drivers/net/ethernet/packetengines/yellowfin.c
+ delete mode 100644 drivers/net/ethernet/smsc/smc9194.c
+ delete mode 100644 drivers/net/ethernet/smsc/smc91c92_cs.c
+ delete mode 100644 drivers/net/hamradio/6pack.c
+ delete mode 100644 drivers/net/hamradio/Kconfig
+ delete mode 100644 drivers/net/hamradio/Makefile
+ delete mode 100644 drivers/net/hamradio/baycom_epp.c
+ delete mode 100644 drivers/net/hamradio/baycom_par.c
+ delete mode 100644 drivers/net/hamradio/baycom_ser_fdx.c
+ delete mode 100644 drivers/net/hamradio/baycom_ser_hdx.c
+ delete mode 100644 drivers/net/hamradio/bpqether.c
+ delete mode 100644 drivers/net/hamradio/hdlcdrv.c
+ delete mode 100644 drivers/net/hamradio/mkiss.c
+ delete mode 100644 drivers/net/hamradio/scc.c
+ delete mode 100644 drivers/net/hamradio/yam.c
+ delete mode 100644 drivers/net/hamradio/z8530.h
+ create mode 100644 fs/ceph/subvolume_metrics.c
+ create mode 100644 fs/ceph/subvolume_metrics.h
+ delete mode 100644 include/linux/hdlcdrv.h
+ create mode 100644 include/linux/iio/adc/qcom-adc5-gen3-common.h
+ delete mode 100644 include/linux/isdn/capilli.h
+ delete mode 100644 include/linux/isdn/capiutil.h
+ delete mode 100644 include/linux/kernelcapi.h
+ delete mode 100644 include/linux/mISDNdsp.h
+ delete mode 100644 include/linux/mISDNhw.h
+ delete mode 100644 include/linux/mISDNif.h
+ delete mode 100644 include/linux/scc.h
+ delete mode 100644 include/linux/virtio_caif.h
+ delete mode 100644 include/linux/yam.h
+ delete mode 100644 include/net/atmclip.h
+ delete mode 100644 include/net/caif/caif_dev.h
+ delete mode 100644 include/net/caif/caif_device.h
+ delete mode 100644 include/net/caif/caif_layer.h
+ delete mode 100644 include/net/caif/cfcnfg.h
+ delete mode 100644 include/net/caif/cfctrl.h
+ delete mode 100644 include/net/caif/cffrml.h
+ delete mode 100644 include/net/caif/cfmuxl.h
+ delete mode 100644 include/net/caif/cfpkt.h
+ delete mode 100644 include/net/caif/cfserl.h
+ delete mode 100644 include/net/caif/cfsrvl.h
+ delete mode 100644 include/net/netrom.h
+ delete mode 100644 include/uapi/linux/baycom.h
+ delete mode 100644 include/uapi/linux/caif/caif_socket.h
+ delete mode 100644 include/uapi/linux/caif/if_caif.h
+ delete mode 100644 include/uapi/linux/capi.h
+ delete mode 100644 include/uapi/linux/hdlcdrv.h
+ delete mode 100644 include/uapi/linux/isdn/capicmd.h
+ delete mode 100644 include/uapi/linux/kernelcapi.h
+ delete mode 100644 include/uapi/linux/netrom.h
+ delete mode 100644 include/uapi/linux/rose.h
+ delete mode 100644 include/uapi/linux/scc.h
+ delete mode 100644 net/atm/clip.c
+ delete mode 100644 net/atm/lec.c
+ delete mode 100644 net/atm/lec.h
+ delete mode 100644 net/atm/lec_arpc.h
+ delete mode 100644 net/atm/mpc.c
+ delete mode 100644 net/atm/mpc.h
+ delete mode 100644 net/atm/mpoa_caches.c
+ delete mode 100644 net/atm/mpoa_caches.h
+ delete mode 100644 net/atm/mpoa_proc.c
+ delete mode 100644 net/ax25/Kconfig
+ delete mode 100644 net/ax25/Makefile
+ delete mode 100644 net/ax25/af_ax25.c
+ delete mode 100644 net/ax25/ax25_addr.c
+ delete mode 100644 net/ax25/ax25_dev.c
+ delete mode 100644 net/ax25/ax25_ds_in.c
+ delete mode 100644 net/ax25/ax25_ds_subr.c
+ delete mode 100644 net/ax25/ax25_ds_timer.c
+ delete mode 100644 net/ax25/ax25_iface.c
+ delete mode 100644 net/ax25/ax25_in.c
+ delete mode 100644 net/ax25/ax25_ip.c
+ delete mode 100644 net/ax25/ax25_out.c
+ delete mode 100644 net/ax25/ax25_route.c
+ delete mode 100644 net/ax25/ax25_std_in.c
+ delete mode 100644 net/ax25/ax25_std_subr.c
+ delete mode 100644 net/ax25/ax25_std_timer.c
+ delete mode 100644 net/ax25/ax25_subr.c
+ delete mode 100644 net/ax25/ax25_timer.c
+ delete mode 100644 net/ax25/ax25_uid.c
+ delete mode 100644 net/ax25/sysctl_net_ax25.c
+ delete mode 100644 net/bluetooth/cmtp/Kconfig
+ delete mode 100644 net/bluetooth/cmtp/Makefile
+ delete mode 100644 net/bluetooth/cmtp/capi.c
+ delete mode 100644 net/bluetooth/cmtp/cmtp.h
+ delete mode 100644 net/bluetooth/cmtp/core.c
+ delete mode 100644 net/bluetooth/cmtp/sock.c
+ delete mode 100644 net/caif/Kconfig
+ delete mode 100644 net/caif/Makefile
+ delete mode 100644 net/caif/caif_dev.c
+ delete mode 100644 net/caif/caif_socket.c
+ delete mode 100644 net/caif/caif_usb.c
+ delete mode 100644 net/caif/cfcnfg.c
+ delete mode 100644 net/caif/cfctrl.c
+ delete mode 100644 net/caif/cfdbgl.c
+ delete mode 100644 net/caif/cfdgml.c
+ delete mode 100644 net/caif/cffrml.c
+ delete mode 100644 net/caif/cfmuxl.c
+ delete mode 100644 net/caif/cfpkt_skbuff.c
+ delete mode 100644 net/caif/cfrfml.c
+ delete mode 100644 net/caif/cfserl.c
+ delete mode 100644 net/caif/cfsrvl.c
+ delete mode 100644 net/caif/cfutill.c
+ delete mode 100644 net/caif/cfveil.c
+ delete mode 100644 net/caif/cfvidl.c
+ delete mode 100644 net/caif/chnl_net.c
+ delete mode 100644 net/netrom/Makefile
+ delete mode 100644 net/netrom/af_netrom.c
+ delete mode 100644 net/netrom/nr_dev.c
+ delete mode 100644 net/netrom/nr_in.c
+ delete mode 100644 net/netrom/nr_loopback.c
+ delete mode 100644 net/netrom/nr_out.c
+ delete mode 100644 net/netrom/nr_route.c
+ delete mode 100644 net/netrom/nr_subr.c
+ delete mode 100644 net/netrom/nr_timer.c
+ delete mode 100644 net/netrom/sysctl_net_netrom.c
+ delete mode 100644 net/rose/Makefile
+ delete mode 100644 net/rose/af_rose.c
+ delete mode 100644 net/rose/rose_dev.c
+ delete mode 100644 net/rose/rose_in.c
+ delete mode 100644 net/rose/rose_link.c
+ delete mode 100644 net/rose/rose_loopback.c
+ delete mode 100644 net/rose/rose_out.c
+ delete mode 100644 net/rose/rose_route.c
+ delete mode 100644 net/rose/rose_subr.c
+ delete mode 100644 net/rose/rose_timer.c
+ delete mode 100644 net/rose/sysctl_net_rose.c
+ create mode 100755 tools/testing/selftests/ublk/test_integrity_03.sh
+Merging ext4-fixes/fixes (981fcc5674e6 jbd2: fix deadlock in jbd2_journal_cancel_revoke())
+$ git merge -m Merge branch 'fixes' of https://git.kernel.org/pub/scm/linux/kernel/git/tytso/ext4.git ext4-fixes/fixes
+Already up to date.
+Merging vfs-brauner-fixes/vfs.fixes (ac8777cc3622 Merge patch series "eventpoll: fix ep_remove() UAF and follow-up cleanup")
+$ git merge -m Merge branch 'vfs.fixes' of https://git.kernel.org/pub/scm/linux/kernel/git/vfs/vfs.git vfs-brauner-fixes/vfs.fixes
+Already up to date.
+Merging fscrypt-current/for-current (254f49634ee1 Linux 7.1-rc1)
+$ git merge -m Merge branch 'for-current' of https://git.kernel.org/pub/scm/fs/fscrypt/linux.git fscrypt-current/for-current
+Already up to date.
+Merging fsverity-current/for-current (254f49634ee1 Linux 7.1-rc1)
+$ git merge -m Merge branch 'for-current' of https://git.kernel.org/pub/scm/fs/fsverity/linux.git fsverity-current/for-current
+Already up to date.
+Merging btrfs-fixes/next-fixes (1b29979c0f6a Merge branch 'misc-7.1' into next-fixes)
+$ git merge -m Merge branch 'next-fixes' of https://git.kernel.org/pub/scm/linux/kernel/git/kdave/linux.git btrfs-fixes/next-fixes
+Auto-merging fs/btrfs/extent_io.c
+Merge made by the 'ort' strategy.
+ fs/btrfs/extent_io.c        | 14 +++++++++--
+ fs/btrfs/extent_io.h        |  3 ++-
+ fs/btrfs/free-space-tree.c  | 18 +++++++++++---
+ fs/btrfs/inode.c            |  4 +++-
+ fs/btrfs/ioctl.c            |  7 +++---
+ fs/btrfs/raid-stripe-tree.c | 57 +++++++++++++++++++++++++++++++++++----------
+ fs/btrfs/relocation.c       | 30 +++++++++++++++++++-----
+ 7 files changed, 104 insertions(+), 29 deletions(-)
+Merging vfs-fixes/fixes (49c5d168a3a8 udf: fix nls leak on udf_fill_super() failure)
+$ git merge -m Merge branch 'fixes' of https://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs.git vfs-fixes/fixes
+Auto-merging fs/udf/super.c
+Merge made by the 'ort' strategy.
+ fs/udf/super.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+Merging erofs-fixes/fixes (2d8c7edcb661 erofs: unify lcn as u64 for 32-bit platforms)
+$ git merge -m Merge branch 'fixes' of https://git.kernel.org/pub/scm/linux/kernel/git/xiang/erofs.git erofs-fixes/fixes
+Already up to date.
+Merging nfsd-fixes/nfsd-fixes (b0bf14546bce nfsd: fix GET_DIR_DELEGATION when VFS leases are disabled)
+$ git merge -m Merge branch 'nfsd-fixes' of https://git.kernel.org/pub/scm/linux/kernel/git/cel/linux nfsd-fixes/nfsd-fixes
+Merge made by the 'ort' strategy.
+ fs/nfsd/nfs4proc.c | 4 ----
+ 1 file changed, 4 deletions(-)
+Merging v9fs-fixes/fixes/next (028ef9c96e96 Linux 7.0)
+$ git merge -m Merge branch 'fixes/next' of https://git.kernel.org/pub/scm/linux/kernel/git/ericvh/v9fs.git v9fs-fixes/fixes/next
+Already up to date.
+Merging overlayfs-fixes/ovl-fixes (1f6ee9be92f8 ovl: make fsync after metadata copy-up opt-in mount option)
+$ git merge -m Merge branch 'ovl-fixes' of https://git.kernel.org/pub/scm/linux/kernel/git/overlayfs/vfs.git overlayfs-fixes/ovl-fixes
+Already up to date.
+Merging fscrypt/for-next (254f49634ee1 Linux 7.1-rc1)
+$ git merge -m Merge branch 'for-next' of https://git.kernel.org/pub/scm/fs/fscrypt/linux.git fscrypt/for-next
+Already up to date.
+Merging btrfs/for-next (6bf684b88235 Merge branch 'for-next-next-v7.0-20260408' into for-next-20260408)
+$ git merge -m Merge branch 'for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/kdave/linux.git btrfs/for-next
+Merge made by the 'ort' strategy.
+Merging ceph/master (29e2da949978 libceph: Fix unnecessarily high ceph_decode_need() for uniform bucket)
+$ git merge -m Merge branch 'master' of https://github.com/ceph/ceph-client.git ceph/master
+Merge made by the 'ort' strategy.
+ net/ceph/crush/crush.c | 6 +-----
+ net/ceph/osdmap.c      | 7 +++++--
+ 2 files changed, 6 insertions(+), 7 deletions(-)
+Merging cifs/for-next (0cbc300257d9 smb/client: remove unused smb3_parse_opt())
+$ git merge -m Merge branch 'for-next' of git://git.samba.org/sfrench/cifs-2.6.git cifs/for-next
+Merge made by the 'ort' strategy.
+ fs/smb/client/cifsproto.h  |  1 -
+ fs/smb/client/fs_context.c | 31 -------------------------------
+ 2 files changed, 32 deletions(-)
+Merging configfs/configfs-next (6363844fdbbb samples: configfs: Constify struct configfs_item_operations and configfs_group_operations)
+$ git merge -m Merge branch 'configfs-next' of https://git.kernel.org/pub/scm/linux/kernel/git/a.hindborg/linux.git configfs/configfs-next
+Already up to date.
+Merging ecryptfs/next (eb5e768eaf7c ecryptfs: remove redundant variable found_auth_tok)
+$ git merge -m Merge branch 'next' of https://git.kernel.org/pub/scm/linux/kernel/git/tyhicks/ecryptfs.git ecryptfs/next
+Merge made by the 'ort' strategy.
+ fs/ecryptfs/keystore.c | 16 +++++-----------
+ 1 file changed, 5 insertions(+), 11 deletions(-)
+Merging dlm/next (2c3a0b730012 dlm: Avoid -Wflex-array-member-not-at-end warning)
+$ git merge -m Merge branch 'next' of https://git.kernel.org/pub/scm/linux/kernel/git/teigland/linux-dlm.git dlm/next
+Already up to date.
+Merging erofs/dev (a5242d37c83a erofs: error out obviously illegal extents in advance)
+$ git merge -m Merge branch 'dev' of https://git.kernel.org/pub/scm/linux/kernel/git/xiang/erofs.git erofs/dev
+Already up to date.
+Merging exfat/dev (dc0e16d2f56a exfat: fix potential use-after-free in exfat_find_dir_entry())
+$ git merge -m Merge branch 'dev' of https://git.kernel.org/pub/scm/linux/kernel/git/linkinjeon/exfat.git exfat/dev
+Merge made by the 'ort' strategy.
+ fs/exfat/dir.c |  4 +++-
+ fs/exfat/nls.c | 19 +++++++++++++------
+ 2 files changed, 16 insertions(+), 7 deletions(-)
+Merging ext3/for_next (936274f2565d Pull udf crc fix.)
+$ git merge -m Merge branch 'for_next' of https://git.kernel.org/pub/scm/linux/kernel/git/jack/linux-fs.git ext3/for_next
+Auto-merging fs/notify/fsnotify.c
+Merge made by the 'ort' strategy.
+ fs/isofs/export.c                |  2 +-
+ fs/isofs/namei.c                 | 11 ++------
+ fs/isofs/rock.c                  |  9 +++++++
+ fs/notify/fanotify/fanotify.c    |  2 +-
+ fs/notify/fsnotify.c             |  2 +-
+ fs/notify/mark.c                 | 57 +++++++++++++++++++++++++++++++++-------
+ fs/udf/misc.c                    |  8 ++++--
+ include/linux/fsnotify_backend.h |  1 +
+ 8 files changed, 68 insertions(+), 24 deletions(-)
+Merging ext4/dev (981fcc5674e6 jbd2: fix deadlock in jbd2_journal_cancel_revoke())
+$ git merge -m Merge branch 'dev' of https://git.kernel.org/pub/scm/linux/kernel/git/tytso/ext4.git ext4/dev
+Already up to date.
+Merging f2fs/dev (cb8ff3ead9a3 f2fs: add page-order information for large folio reads in iostat)
+$ git merge -m Merge branch 'dev' of https://git.kernel.org/pub/scm/linux/kernel/git/jaegeuk/f2fs.git f2fs/dev
+Already up to date.
+Merging fsverity/for-next (254f49634ee1 Linux 7.1-rc1)
+$ git merge -m Merge branch 'for-next' of https://git.kernel.org/pub/scm/fs/fsverity/linux.git fsverity/for-next
+Already up to date.
+Merging fuse/for-next (ea2ff881bb8e fuse: reduce attributes invalidated on directory change)
+$ git merge -m Merge branch 'for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/mszeredi/fuse.git fuse/for-next
+Auto-merging fs/fuse/file.c
+Auto-merging fs/fuse/inode.c
+Merge made by the 'ort' strategy.
+ fs/fuse/Makefile      |    3 +-
+ fs/fuse/args.h        |   65 +++
+ fs/fuse/backing.c     |    1 +
+ fs/fuse/control.c     |   16 +-
+ fs/fuse/cuse.c        |   28 +-
+ fs/fuse/dev.c         | 1253 ++++++++++++++++++-------------------------------
+ fs/fuse/dev.h         |  110 +++++
+ fs/fuse/dev_uring.c   |  143 +++---
+ fs/fuse/dev_uring_i.h |   39 +-
+ fs/fuse/dir.c         |   12 +-
+ fs/fuse/file.c        |  146 +-----
+ fs/fuse/fuse_dev_i.h  |  350 +++++++++++++-
+ fs/fuse/fuse_i.h      |  860 +++++++++++----------------------
+ fs/fuse/fuse_trace.h  |    4 +-
+ fs/fuse/inode.c       |  255 ++--------
+ fs/fuse/notify.c      |  434 +++++++++++++++++
+ fs/fuse/poll.c        |  141 ++++++
+ fs/fuse/req.c         |   99 ++++
+ fs/fuse/req_timeout.c |  148 ++++++
+ fs/fuse/sysctl.c      |    1 +
+ fs/fuse/sysctl.h      |    9 +
+ fs/fuse/virtio_fs.c   |   21 +-
+ 22 files changed, 2288 insertions(+), 1850 deletions(-)
+ create mode 100644 fs/fuse/args.h
+ create mode 100644 fs/fuse/dev.h
+ create mode 100644 fs/fuse/notify.c
+ create mode 100644 fs/fuse/poll.c
+ create mode 100644 fs/fuse/req.c
+ create mode 100644 fs/fuse/req_timeout.c
+ create mode 100644 fs/fuse/sysctl.h
+Merging gfs2/for-next (4da0dd95be3b Merge tag 'gfs2-for-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/gfs2/linux-gfs2)
+$ git merge -m Merge branch 'for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/gfs2/linux-gfs2.git gfs2/for-next
+Already up to date.
+Merging jfs/jfs-next (dad98c5b2a05 jfs: avoid -Wtautological-constant-out-of-range-compare warning again)
+$ git merge -m Merge branch 'jfs-next' of https://github.com/kleikamp/linux-shaggy.git jfs/jfs-next
+Already up to date.
+Merging ksmbd/ksmbd-for-next (254f49634ee1 Linux 7.1-rc1)
+$ git merge -m Merge branch 'ksmbd-for-next' of https://github.com/smfrench/smb3-kernel.git ksmbd/ksmbd-for-next
+Already up to date.
+Merging nfs/linux-next (e6614b88d59d NFS: Fix RCU dereference of cl_xprt in nfs_compare_super_address)
+$ git merge -m Merge branch 'linux-next' of git://git.linux-nfs.org/projects/trondmy/nfs-2.6.git nfs/linux-next
+Already up to date.
+Merging nfs-anna/linux-next (4529e0015432 NFS: Fix NFS KConfig typos)
+$ git merge -m Merge branch 'linux-next' of git://git.linux-nfs.org/projects/anna/linux-nfs.git nfs-anna/linux-next
+Already up to date.
+Merging nfsd/nfsd-next (a60fafb3f689 NFSD: Update my maintainer email addresses)
+$ git merge -m Merge branch 'nfsd-next' of https://git.kernel.org/pub/scm/linux/kernel/git/cel/linux nfsd/nfsd-next
+Merge made by the 'ort' strategy.
+ Documentation/netlink/specs/nfsd.yaml         | 229 +++++++++
+ Documentation/netlink/specs/sunrpc_cache.yaml | 149 ++++++
+ MAINTAINERS                                   |   8 +-
+ fs/nfs/dns_resolve.c                          |   2 +-
+ fs/nfsd/export.c                              | 713 +++++++++++++++++++++++++-
+ fs/nfsd/netlink.c                             |  93 ++++
+ fs/nfsd/netlink.h                             |  18 +
+ fs/nfsd/nfs4idmap.c                           |   4 +-
+ fs/nfsd/nfs4state.c                           |   9 +-
+ fs/nfsd/nfsctl.c                              |  79 +++
+ fs/nfsd/nfsd.h                                |  17 +-
+ include/linux/sunrpc/cache.h                  |  15 +-
+ include/uapi/linux/nfsd_netlink.h             | 132 +++++
+ include/uapi/linux/sunrpc_netlink.h           |  84 +++
+ net/sunrpc/Makefile                           |   2 +-
+ net/sunrpc/auth_gss/svcauth_gss.c             |   2 +-
+ net/sunrpc/cache.c                            | 127 ++++-
+ net/sunrpc/netlink.c                          |  97 ++++
+ net/sunrpc/netlink.h                          |  35 ++
+ net/sunrpc/sunrpc_syms.c                      |  10 +
+ net/sunrpc/svc_xprt.c                         |  46 +-
+ net/sunrpc/svcauth_unix.c                     | 516 ++++++++++++++++++-
+ 22 files changed, 2335 insertions(+), 52 deletions(-)
+ create mode 100644 Documentation/netlink/specs/sunrpc_cache.yaml
+ create mode 100644 include/uapi/linux/sunrpc_netlink.h
+ create mode 100644 net/sunrpc/netlink.c
+ create mode 100644 net/sunrpc/netlink.h
+Merging ntfs/ntfs-next (fe5be34f5770 ntfs: fix WSL symlink target leak on reparse failure)
+$ git merge -m Merge branch 'ntfs-next' of https://git.kernel.org/pub/scm/linux/kernel/git/linkinjeon/ntfs.git ntfs/ntfs-next
+Merge made by the 'ort' strategy.
+ fs/ntfs/dir.c     | 13 ++++++++++---
+ fs/ntfs/index.c   | 17 +++++++++++++----
+ fs/ntfs/reparse.c |  5 +++--
+ 3 files changed, 26 insertions(+), 9 deletions(-)
+$ git am -3 ../patches/0001-ntfs-Fix-up-mm-merge.patch
+Applying: ntfs: Fix up mm merge
+Using index info to reconstruct a base tree...
+M	fs/ntfs/file.c
+Falling back to patching base and 3-way merge...
+Auto-merging fs/ntfs/file.c
+CONFLICT (content): Merge conflict in fs/ntfs/file.c
+Recorded preimage for 'fs/ntfs/file.c'
+error: Failed to merge in the changes.
+hint: Use 'git am --show-current-patch=diff' to see the failed patch
+hint: When you have resolved this problem, run "git am --continue".
+hint: If you prefer to skip this patch, run "git am --skip" instead.
+hint: To restore the original branch and stop patching, run "git am --abort".
+hint: Disable this message with "git config set advice.mergeConflict false"
+Patch failed at 0001 ntfs: Fix up mm merge
+Merging ntfs3/master (819bd270abf9 fs/ntfs3: fix Smatch warnings)
+$ git merge -m Merge branch 'master' of https://github.com/Paragon-Software-Group/linux-ntfs3.git ntfs3/master
+Already up to date.
+$ git am -3 ../patches/0001-ntfs3-Fix-merge-issue-with-ntfs3.patch
+Applying: ntfs3: Fix merge issue with ntfs3
+Using index info to reconstruct a base tree...
+M	fs/ntfs3/inode.c
+Falling back to patching base and 3-way merge...
+Auto-merging fs/ntfs3/inode.c
+No changes -- Patch already applied.
+Merging orangefs/for-next (e61bc5e4d874    bufmap: manage as folios, V2.)
+$ git merge -m Merge branch 'for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/hubcap/linux.git orangefs/for-next
+Already up to date.
+Merging overlayfs/overlayfs-next (1f6ee9be92f8 ovl: make fsync after metadata copy-up opt-in mount option)
+$ git merge -m Merge branch 'overlayfs-next' of https://git.kernel.org/pub/scm/linux/kernel/git/overlayfs/vfs.git overlayfs/overlayfs-next
+Already up to date.
+Merging ubifs/next (11efa98bcc0d ubi: ubi.h: fix kernel-doc warnings)
+$ git merge -m Merge branch 'next' of https://git.kernel.org/pub/scm/linux/kernel/git/rw/ubifs.git ubifs/next
+Auto-merging drivers/mtd/ubi/ubi.h
+Merge made by the 'ort' strategy.
+ drivers/mtd/ubi/ubi.h | 9 ++++++---
+ 1 file changed, 6 insertions(+), 3 deletions(-)
+Merging v9fs/9p-next (8fc518e489c1 9p/trans_xen: replace simple_strto* with kstrtouint)
+$ git merge -m Merge branch '9p-next' of https://github.com/martinetd/linux v9fs/9p-next
+Already up to date.
+Merging v9fs-ericvh/ericvh/for-next (028ef9c96e96 Linux 7.0)
+$ git merge -m Merge branch 'ericvh/for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/ericvh/v9fs.git v9fs-ericvh/ericvh/for-next
+Already up to date.
+Merging xfs/for-next (2ffc6900d5c3 xfs: fix number of GC bvecs)
+$ git merge -m Merge branch 'for-next' of https://git.kernel.org/pub/scm/fs/xfs/xfs-linux.git xfs/for-next
+Already up to date.
+Merging zonefs/for-next (a42938e80357 zonefs: correct some spelling mistakes)
+$ git merge -m Merge branch 'for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/dlemoal/zonefs.git zonefs/for-next
+Already up to date.
+Merging vfs-brauner/vfs.all (8ee708daac8a Merge branch 'kernel-7.1.misc' into vfs.all)
+$ git merge -m Merge branch 'vfs.all' of https://git.kernel.org/pub/scm/linux/kernel/git/vfs/vfs.git vfs-brauner/vfs.all
+Auto-merging fs/aio.c
+Auto-merging fs/fs-writeback.c
+Auto-merging fs/netfs/buffered_write.c
+Auto-merging include/uapi/linux/sched.h
+Auto-merging kernel/fork.c
+CONFLICT (content): Merge conflict in kernel/fork.c
+Auto-merging kernel/nsproxy.c
+CONFLICT (content): Merge conflict in kernel/nsproxy.c
+Resolved 'kernel/fork.c' using previous resolution.
+Resolved 'kernel/nsproxy.c' using previous resolution.
+Automatic merge failed; fix conflicts and then commit the result.
+$ git commit --no-edit -v -a
+[fs-next 31fb623220d9] Merge branch 'vfs.all' of https://git.kernel.org/pub/scm/linux/kernel/git/vfs/vfs.git
+$ git diff -M --stat --summary HEAD^..
+ fs/netfs/buffered_read.c     |  9 +++++---
+ fs/netfs/buffered_write.c    | 51 ++++++++++++++++++++++++++++----------------
+ fs/netfs/iterator.c          | 13 ++++++++---
+ fs/netfs/misc.c              |  8 +++++--
+ fs/netfs/read_retry.c        | 11 ++++++++--
+ include/trace/events/netfs.h |  5 +++++
+ kernel/nsproxy.c             |  2 +-
+ 7 files changed, 70 insertions(+), 29 deletions(-)
+$ git am -3 ../patches/0001-ntfs-Fixup-merge-issue-with-vfs.all-changes.patch
+Applying: ntfs: Fixup merge issue with vfs.all changes
+Using index info to reconstruct a base tree...
+M	fs/ntfs/mft.c
+Falling back to patching base and 3-way merge...
+Auto-merging fs/ntfs/mft.c
+No changes -- Patch already applied.
+Merging vfs/for-next (e82ff9b6cb76 Merge branches 'work.coda' and 'work.dcache-busy-wait' into for-next)
+$ git merge -m Merge branch 'for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs.git vfs/for-next
+Merge made by the 'ort' strategy.
+Merging mm-hotfixes/mm-hotfixes-unstable (ba24da38a519 mm/hugetlb: restore reservation on error in hugetlb_mfill_atomic_pte() resubmission path)
+$ git merge -m Merge branch 'mm-hotfixes-unstable' of https://git.kernel.org/pub/scm/linux/kernel/git/akpm/mm mm-hotfixes/mm-hotfixes-unstable
+Auto-merging .mailmap
+Auto-merging MAINTAINERS
+Auto-merging drivers/dax/bus.c
+Merge made by the 'ort' strategy.
+ .mailmap                           |  5 +++
+ MAINTAINERS                        | 30 +++++++-------
+ arch/arm64/include/asm/page.h      |  2 +-
+ arch/arm64/mm/fault.c              | 11 +++--
+ drivers/base/memory.c              |  8 +++-
+ drivers/dax/bus.c                  |  7 ++--
+ include/linux/gfp_types.h          | 10 ++---
+ include/linux/highmem.h            |  7 ++--
+ include/linux/maple_tree.h         |  2 +-
+ include/linux/mm.h                 |  2 +-
+ include/trace/events/damon.h       |  2 +-
+ kernel/liveupdate/kexec_handover.c | 21 ++++++----
+ kernel/liveupdate/luo_session.c    | 15 ++++---
+ lib/maple_tree.c                   |  2 +-
+ lib/test_maple_tree.c              |  4 +-
+ lib/tests/kunit_iov_iter.c         | 10 ++---
+ mm/damon/lru_sort.c                | 85 ++++++++++++++++++++++++--------------
+ mm/damon/reclaim.c                 | 85 ++++++++++++++++++++++++--------------
+ mm/damon/stat.c                    | 30 +++++++++-----
+ mm/damon/sysfs-schemes.c           | 25 ++++++++++-
+ mm/hugetlb.c                       |  1 +
+ mm/hugetlb_cma.c                   |  1 +
+ mm/memory_hotplug.c                |  1 +
+ mm/migrate_device.c                |  3 +-
+ mm/page-writeback.c                | 16 +++----
+ mm/page_alloc.c                    |  8 ++--
+ mm/userfaultfd.c                   | 12 +++++-
+ mm/util.c                          | 26 ++++++++----
+ mm/vma.c                           |  3 +-
+ mm/vmalloc.c                       |  2 +-
+ tools/testing/radix-tree/maple.c   |  2 +-
+ tools/testing/selftests/mm/config  |  1 +
+ tools/testing/vma/include/dup.h    |  2 +-
+ tools/testing/vma/include/stubs.h  |  3 +-
+ 34 files changed, 284 insertions(+), 160 deletions(-)
+Merging fs-current (983de4a4f819 Merge branch 'nfsd-fixes' of https://git.kernel.org/pub/scm/linux/kernel/git/cel/linux)
+$ git merge -m Merge branch 'fs-current' of linux-next fs-current
+Merge made by the 'ort' strategy.
+ fs/btrfs/extent_io.c        | 14 +++++++++--
+ fs/btrfs/extent_io.h        |  3 ++-
+ fs/btrfs/free-space-tree.c  | 18 +++++++++++---
+ fs/btrfs/inode.c            |  4 +++-
+ fs/btrfs/ioctl.c            |  7 +++---
+ fs/btrfs/raid-stripe-tree.c | 57 +++++++++++++++++++++++++++++++++++----------
+ fs/btrfs/relocation.c       | 30 +++++++++++++++++++-----
+ fs/nfsd/nfs4proc.c          |  4 ----
+ fs/udf/super.c              |  2 +-
+ 9 files changed, 105 insertions(+), 34 deletions(-)
+Merging kbuild-current/kbuild-fixes-for-next (75f7c47ccd78 kbuild: Never respect CONFIG_WERROR / W=e to fixdep)
+$ git merge -m Merge branch 'kbuild-fixes-for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/kbuild/linux.git kbuild-current/kbuild-fixes-for-next
+Already up to date.
+Merging clang-fixes/clang-fixes-for-next (4f96b7c68a99 extract-cert: Wrap key_pass with '#ifdef USE_PKCS11_ENGINE')
+$ git merge -m Merge branch 'clang-fixes-for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/nathan/linux.git clang-fixes/clang-fixes-for-next
+Already up to date.
+Merging arc-current/for-curr (7aaa8047eafd Linux 7.0-rc6)
+$ git merge -m Merge branch 'for-curr' of https://git.kernel.org/pub/scm/linux/kernel/git/vgupta/arc.git arc-current/for-curr
+Already up to date.
+Merging arm-current/fixes (75f9a484e817 ARM: 9472/1: fix race condition on PG_dcache_clean in __sync_icache_dcache())
+$ git merge -m Merge branch 'fixes' of https://git.kernel.org/pub/scm/linux/kernel/git/rmk/linux.git arm-current/fixes
+Already up to date.
+Merging arm64-fixes/for-next/fixes (54ac9ff8f119 arm64: Use static call trampolines when kCFI is enabled)
+$ git merge -m Merge branch 'for-next/fixes' of https://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux arm64-fixes/for-next/fixes
+Already up to date.
+Merging arm-soc-fixes/arm/fixes (3e2444044d16 Merge tag 'mvebu-fixes-7.0-1' of https://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu into arm/fixes)
+$ git merge -m Merge branch 'arm/fixes' of https://git.kernel.org/pub/scm/linux/kernel/git/soc/soc.git arm-soc-fixes/arm/fixes
+Already up to date.
+Merging davinci-current/davinci/for-current (6de23f81a5e0 Linux 7.0-rc1)
+$ git merge -m Merge branch 'davinci/for-current' of https://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux.git davinci-current/davinci/for-current
+Already up to date.
+Merging drivers-memory-fixes/fixes (6de23f81a5e0 Linux 7.0-rc1)
+$ git merge -m Merge branch 'fixes' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl.git drivers-memory-fixes/fixes
+Already up to date.
+Merging sophgo-fixes/fixes (19272b37aa4f Linux 6.16-rc1)
+$ git merge -m Merge branch 'fixes' of https://github.com/sophgo/linux.git sophgo-fixes/fixes
+Already up to date.
+Merging sophgo-soc-fixes/soc-fixes (0af2f6be1b42 Linux 6.15-rc1)
+$ git merge -m Merge branch 'soc-fixes' of https://github.com/sophgo/linux.git sophgo-soc-fixes/soc-fixes
+Already up to date.
+Merging m68k-current/for-linus (cb39cf99d88e m68k: sun3: Replace vsprintf() with bounded vsnprintf())
+$ git merge -m Merge branch 'for-linus' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/linux-m68k.git m68k-current/for-linus
+Already up to date.
+Merging powerpc-fixes/fixes (328335a79487 powerpc/powernv/iommu: iommu incorrectly bypass DMA APIs)
+$ git merge -m Merge branch 'fixes' of https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git powerpc-fixes/fixes
+Already up to date.
+Merging s390-fixes/fixes (c8d46f17c2fc s390/zcrypt: Fix memory leak with CCA cards used as accelerator)
+$ git merge -m Merge branch 'fixes' of https://git.kernel.org/pub/scm/linux/kernel/git/s390/linux.git s390-fixes/fixes
+Already up to date.
+Merging net/main (254f49634ee1 Linux 7.1-rc1)
+$ git merge -m Merge branch 'main' of https://git.kernel.org/pub/scm/linux/kernel/git/netdev/net.git net/main
+Already up to date.
+Merging bpf/master (b5c111f4967b bpf: Fix sk_local_storage diag dumping uninitialized special fields)
+$ git merge -m Merge branch 'master' of https://git.kernel.org/pub/scm/linux/kernel/git/bpf/bpf.git/ bpf/master
+Auto-merging net/core/filter.c
+Merge made by the 'ort' strategy.
+ include/linux/bpf.h                                |  1 +
+ net/core/bpf_sk_storage.c                          | 14 ++++----
+ net/core/filter.c                                  | 32 ++++++++++++++++++
+ net/core/sock_map.c                                | 39 ++++++++++++++--------
+ net/ipv4/bpf_tcp_ca.c                              |  2 +-
+ .../testing/selftests/bpf/prog_tests/bpf_tcp_ca.c  |  4 +++
+ .../selftests/bpf/prog_tests/tcp_hdr_options.c     |  4 +++
+ tools/testing/selftests/bpf/progs/bpf_cubic.c      | 14 ++++++++
+ .../bpf/progs/test_misc_tcp_hdr_options.c          | 15 ++++++++-
+ 9 files changed, 103 insertions(+), 22 deletions(-)
+Merging ipsec/master (ec54093e6a8f xfrm: ah: account for ESN high bits in async callbacks)
+$ git merge -m Merge branch 'master' of https://git.kernel.org/pub/scm/linux/kernel/git/klassert/ipsec.git ipsec/master
+Merge made by the 'ort' strategy.
+ net/ipv4/ah4.c            | 14 ++++++++++++--
+ net/ipv6/ah6.c            | 14 ++++++++++++--
+ net/ipv6/xfrm6_protocol.c |  4 +++-
+ 3 files changed, 27 insertions(+), 5 deletions(-)
+Merging netfilter/main (d40831b016b4 Merge branch 'mptcp-sync-the-msk-sndbuf-at-accept-time')
+$ git merge -m Merge branch 'main' of https://git.kernel.org/pub/scm/linux/kernel/git/netfilter/nf.git netfilter/main
+Already up to date.
+Merging ipvs/main (9351edf65cb6 Merge branch 'bnxt_en-bug-fixes')
+$ git merge -m Merge branch 'main' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/ipvs.git ipvs/main
+Already up to date.
+Merging wireless/for-next (d65b175cfac6 Merge tag 'wireless-2026-04-08' of https://git.kernel.org/pub/scm/linux/kernel/git/wireless/wireless)
+$ git merge -m Merge branch 'for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/wireless/wireless.git wireless/for-next
+Already up to date.
+Merging ath/for-current (1f5ffc672165 Fix mismerge of the arm64 / timer-core interrupt handling changes)
+$ git merge -m Merge branch 'for-current' of https://git.kernel.org/pub/scm/linux/kernel/git/ath/ath.git ath/for-current
+Already up to date.
+Merging iwlwifi/fixes (687a95d204e7 wifi: iwlwifi: mld: correctly set wifi generation data)
+$ git merge -m Merge branch 'fixes' of https://git.kernel.org/pub/scm/linux/kernel/git/iwlwifi/iwlwifi-next.git iwlwifi/fixes
+Already up to date.
+Merging wpan/master (8ce4f287524c net: libwx: fix firmware mailbox abnormal return)
+$ git merge -m Merge branch 'master' of https://git.kernel.org/pub/scm/linux/kernel/git/wpan/wpan.git wpan/master
+Already up to date.
+Merging rdma-fixes/for-rc (028ef9c96e96 Linux 7.0)
+$ git merge -m Merge branch 'for-rc' of https://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdma.git rdma-fixes/for-rc
+Already up to date.
+Merging sound-current/for-linus (2724fbc90e5c Revert "ALSA: pcmtest: fix reference leak on failed device registration")
+$ git merge -m Merge branch 'for-linus' of https://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound.git sound-current/for-linus
+Already up to date.
+Merging sound-asoc-fixes/for-linus (c7ecb6a61908 ASoC: tas2770: Fix order of operations for temperature calculation)
+$ git merge -m Merge branch 'for-linus' of https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git sound-asoc-fixes/for-linus
+Merge made by the 'ort' strategy.
+ sound/soc/amd/acp/acp-legacy-mach.c |  2 +-
+ sound/soc/amd/acp/acp-mach-common.c | 22 +++++++++++++++++++---
+ sound/soc/amd/acp/acp-mach.h        |  4 ++++
+ sound/soc/amd/acp/acp-sof-mach.c    |  2 +-
+ sound/soc/codecs/tas2764.c          |  1 +
+ sound/soc/codecs/tas2770.c          |  4 ++--
+ sound/soc/sof/intel/hda.c           |  3 ++-
+ 7 files changed, 30 insertions(+), 8 deletions(-)
+Merging regmap-fixes/for-linus (4b7774eeab8d regmap: sdw-mbq: Fix spelling mistake "undeferable" -> "undeferrable")
+$ git merge -m Merge branch 'for-linus' of https://git.kernel.org/pub/scm/linux/kernel/git/broonie/regmap.git regmap-fixes/for-linus
+Merge made by the 'ort' strategy.
+ drivers/base/regmap/regmap-sdw-mbq.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+Merging regulator-fixes/for-linus (fb71a29c2455 Merge remote-tracking branch 'regulator/for-7.0' into regulator-linus)
+$ git merge -m Merge branch 'for-linus' of https://git.kernel.org/pub/scm/linux/kernel/git/broonie/regulator.git regulator-fixes/for-linus
+Merge made by the 'ort' strategy.
+Merging spi-fixes/for-linus (7643978722aa spi: rockchip: Drop unused and broken CR0 macros)
+$ git merge -m Merge branch 'for-linus' of https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git spi-fixes/for-linus
+Merge made by the 'ort' strategy.
+ drivers/spi/spi-rockchip.c   | 6 ++----
+ drivers/spi/spi-rzv2h-rspi.c | 2 +-
+ 2 files changed, 3 insertions(+), 5 deletions(-)
+Merging pci-current/for-linus (40286d6379aa Merge tag 'pci-v7.1-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci)
+$ git merge -m Merge branch 'for-linus' of https://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git pci-current/for-linus
+Already up to date.
+Merging driver-core.current/driver-core-linus (254f49634ee1 Linux 7.1-rc1)
+$ git merge -m Merge branch 'driver-core-linus' of https://git.kernel.org/pub/scm/linux/kernel/git/driver-core/driver-core.git driver-core.current/driver-core-linus
+Already up to date.
+Merging tty.current/tty-linus (27d128c1cff6 Merge tag 'trace-ring-buffer-v7.1-3' of git://git.kernel.org/pub/scm/linux/kernel/git/trace/linux-trace)
+$ git merge -m Merge branch 'tty-linus' of https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty.git tty.current/tty-linus
+Already up to date.
+Merging usb.current/usb-linus (27d128c1cff6 Merge tag 'trace-ring-buffer-v7.1-3' of git://git.kernel.org/pub/scm/linux/kernel/git/trace/linux-trace)
+$ git merge -m Merge branch 'usb-linus' of https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb.git usb.current/usb-linus
+Already up to date.
+Merging usb-serial-fixes/usb-linus (591cd656a1bf Linux 7.0-rc7)
+$ git merge -m Merge branch 'usb-linus' of https://git.kernel.org/pub/scm/linux/kernel/git/johan/usb-serial.git usb-serial-fixes/usb-linus
+Already up to date.
+Merging phy/fixes (7aaa8047eafd Linux 7.0-rc6)
+$ git merge -m Merge branch 'fixes' of https://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy.git phy/fixes
+Already up to date.
+Merging staging.current/staging-linus (27d128c1cff6 Merge tag 'trace-ring-buffer-v7.1-3' of git://git.kernel.org/pub/scm/linux/kernel/git/trace/linux-trace)
+$ git merge -m Merge branch 'staging-linus' of https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging.git staging.current/staging-linus
+Already up to date.
+Merging iio-fixes/fixes-togreg (51e7665ab81f iio: chemical: mhz19b: reject oversized serial replies)
+$ git merge -m Merge branch 'fixes-togreg' of https://git.kernel.org/pub/scm/linux/kernel/git/jic23/iio.git iio-fixes/fixes-togreg
+Merge made by the 'ort' strategy.
+ drivers/iio/adc/xilinx-xadc-core.c | 11 +++++++++--
+ drivers/iio/chemical/mhz19b.c      | 17 +++++++++++++++++
+ 2 files changed, 26 insertions(+), 2 deletions(-)
+Merging counter-current/counter-current (2932095c114b counter: rz-mtu3-cnt: do not use struct rz_mtu3_channel's dev member)
+$ git merge -m Merge branch 'counter-current' of https://git.kernel.org/pub/scm/linux/kernel/git/wbg/counter.git counter-current/counter-current
+Already up to date.
+Merging char-misc.current/char-misc-linus (27d128c1cff6 Merge tag 'trace-ring-buffer-v7.1-3' of git://git.kernel.org/pub/scm/linux/kernel/git/trace/linux-trace)
+$ git merge -m Merge branch 'char-misc-linus' of https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc.git char-misc.current/char-misc-linus
+Already up to date.
+Merging soundwire-fixes/fixes (6de23f81a5e0 Linux 7.0-rc1)
+$ git merge -m Merge branch 'fixes' of https://git.kernel.org/pub/scm/linux/kernel/git/vkoul/soundwire.git soundwire-fixes/fixes
+Already up to date.
+Merging thunderbolt-fixes/fixes (254f49634ee1 Linux 7.1-rc1)
+$ git merge -m Merge branch 'fixes' of https://git.kernel.org/pub/scm/linux/kernel/git/westeri/thunderbolt.git thunderbolt-fixes/fixes
+Already up to date.
+Merging input-current/for-linus (6cdc46b38cf1 Input: xpad - fix out-of-bounds access for Share button)
+$ git merge -m Merge branch 'for-linus' of https://git.kernel.org/pub/scm/linux/kernel/git/dtor/input.git input-current/for-linus
+Merge made by the 'ort' strategy.
+ drivers/input/joystick/xpad.c              | 8 ++++----
+ drivers/input/mouse/elan_i2c_core.c        | 3 +++
+ drivers/input/mouse/elan_i2c_i2c.c         | 2 +-
+ drivers/input/touchscreen/usbtouchscreen.c | 5 +++++
+ 4 files changed, 13 insertions(+), 5 deletions(-)
+Merging crypto-current/master (5db6ef984771 crypto: authencesn - reject short ahash digests during instance creation)
+$ git merge -m Merge branch 'master' of https://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6.git crypto-current/master
+Merge made by the 'ort' strategy.
+ crypto/authencesn.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+Merging libcrypto-fixes/libcrypto-fixes (254f49634ee1 Linux 7.1-rc1)
+$ git merge -m Merge branch 'libcrypto-fixes' of https://git.kernel.org/pub/scm/linux/kernel/git/ebiggers/linux.git libcrypto-fixes/libcrypto-fixes
+Already up to date.
+Merging vfio-fixes/for-linus (e98137f0a874 vfio/pci: Fix double free in dma-buf feature)
+$ git merge -m Merge branch 'for-linus' of https://github.com/awilliam/linux-vfio.git vfio-fixes/for-linus
+Already up to date.
+Merging kselftest-fixes/fixes (6de23f81a5e0 Linux 7.0-rc1)
+$ git merge -m Merge branch 'fixes' of https://git.kernel.org/pub/scm/linux/kernel/git/shuah/linux-kselftest.git kselftest-fixes/fixes
+Already up to date.
+Merging dmaengine-fixes/fixes (7aaa8047eafd Linux 7.0-rc6)
+$ git merge -m Merge branch 'fixes' of https://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine.git dmaengine-fixes/fixes
+Already up to date.
+Merging backlight-fixes/for-backlight-fixes (8f0b4cce4481 Linux 6.19-rc1)
+$ git merge -m Merge branch 'for-backlight-fixes' of https://git.kernel.org/pub/scm/linux/kernel/git/lee/backlight.git backlight-fixes/for-backlight-fixes
+Already up to date.
+Merging mtd-fixes/mtd/fixes (b9465b04de4b mtd: rawnand: pl353: make sure optimal timings are applied)
+$ git merge -m Merge branch 'mtd/fixes' of https://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git mtd-fixes/mtd/fixes
+Already up to date.
+Merging mfd-fixes/for-mfd-fixes (aa6e63373d91 mfd: ls2kbmc: Use PCI API instead of direct accesses)
+$ git merge -m Merge branch 'for-mfd-fixes' of https://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd.git mfd-fixes/for-mfd-fixes
+Merge made by the 'ort' strategy.
+Merging v4l-dvb-fixes/fixes (fb2d7bd146fa Merge remote-tracking branch 'media-pending/fixes' into HEAD)
+$ git merge -m Merge branch 'fixes' of git://linuxtv.org/media-ci/media-pending.git v4l-dvb-fixes/fixes
+Merge made by the 'ort' strategy.
+Merging reset-fixes/reset/fixes (9797524ef2b6 reset: amlogic: t7: Fix null reset ops)
+$ git merge -m Merge branch 'reset/fixes' of https://git.pengutronix.de/git/pza/linux reset-fixes/reset/fixes
+Already up to date.
+Merging mips-fixes/mips-fixes (591cd656a1bf Linux 7.0-rc7)
+$ git merge -m Merge branch 'mips-fixes' of https://git.kernel.org/pub/scm/linux/kernel/git/mips/linux.git mips-fixes/mips-fixes
+Already up to date.
+Merging at91-fixes/at91-fixes (907150bbe566 ARM: dts: microchip: sam9x7: fix gpio-lines count for pioB)
+$ git merge -m Merge branch 'at91-fixes' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux.git at91-fixes/at91-fixes
+Already up to date.
+Merging omap-fixes/fixes (6de23f81a5e0 Linux 7.0-rc1)
+$ git merge -m Merge branch 'fixes' of https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap.git omap-fixes/fixes
+Already up to date.
+Merging kvm-fixes/master (028ef9c96e96 Linux 7.0)
+$ git merge -m Merge branch 'master' of git://git.kernel.org/pub/scm/virt/kvm/kvm.git kvm-fixes/master
+Already up to date.
+Merging kvms390-fixes/master (16d990a15491 KVM: s390: pci: fix GAIT table indexing due to double-scaling pointer arithmetic)
+$ git merge -m Merge branch 'master' of https://git.kernel.org/pub/scm/linux/kernel/git/kvms390/linux.git kvms390-fixes/master
+Auto-merging arch/s390/kvm/interrupt.c
+Merge made by the 'ort' strategy.
+ arch/s390/kvm/interrupt.c | 3 +--
+ arch/s390/kvm/pci.c       | 6 ++----
+ 2 files changed, 3 insertions(+), 6 deletions(-)
+Merging kvm-arm-fixes/fixes (4ce98bf0865c KVM: arm64: Wake-up from WFI when iqrchip is in userspace)
+$ git merge -m Merge branch 'fixes' of https://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm.git kvm-arm-fixes/fixes
+Merge made by the 'ort' strategy.
+ arch/arm64/include/asm/kvm_asm.h   | 28 ++++++++++++++++++----------
+ arch/arm64/include/asm/kvm_host.h  |  5 +----
+ arch/arm64/kvm/arm.c               |  4 ++++
+ arch/arm64/kvm/config.c            | 23 ++++++++++++++++-------
+ arch/arm64/kvm/hyp/nvhe/hyp-main.c | 30 +++++++++++++++++-------------
+ arch/arm64/kvm/hyp/nvhe/pkvm.c     | 38 +++++++++++++++++++++++++-------------
+ arch/arm64/kvm/hyp/nvhe/setup.c    |  8 ++++----
+ arch/arm64/kvm/vgic/vgic-mmio-v2.c |  2 +-
+ arch/arm64/kvm/vgic/vgic-mmio-v3.c |  2 +-
+ 9 files changed, 87 insertions(+), 53 deletions(-)
+Merging hwmon-fixes/hwmon (254f49634ee1 Linux 7.1-rc1)
+$ git merge -m Merge branch 'hwmon' of https://git.kernel.org/pub/scm/linux/kernel/git/groeck/linux-staging.git hwmon-fixes/hwmon
+Already up to date.
+Merging nvdimm-fixes/libnvdimm-fixes (a8aec1423032 nvdimm/bus: Fix potential use after free in asynchronous initialization)
+$ git merge -m Merge branch 'libnvdimm-fixes' of https://git.kernel.org/pub/scm/linux/kernel/git/nvdimm/nvdimm.git nvdimm-fixes/libnvdimm-fixes
+Already up to date.
+Merging cxl-fixes/fixes (be5c5280cf2b cxl: Adjust the startup priority of cxl_pmem to be higher than that of cxl_acpi)
+$ git merge -m Merge branch 'fixes' of https://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl.git cxl-fixes/fixes
+Already up to date.
+Merging dma-mapping-fixes/dma-mapping-fixes (3d48c9fd78dd dma-debug: suppress cacheline overlap warning when arch has no DMA alignment requirement)
+$ git merge -m Merge branch 'dma-mapping-fixes' of https://git.kernel.org/pub/scm/linux/kernel/git/mszyprowski/linux.git dma-mapping-fixes/dma-mapping-fixes
+Already up to date.
+Merging drivers-x86-fixes/fixes (254f49634ee1 Linux 7.1-rc1)
+$ git merge -m Merge branch 'fixes' of https://git.kernel.org/pub/scm/linux/kernel/git/pdx86/platform-drivers-x86.git drivers-x86-fixes/fixes
+Already up to date.
+Merging samsung-krzk-fixes/fixes (6de23f81a5e0 Linux 7.0-rc1)
+$ git merge -m Merge branch 'fixes' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux.git samsung-krzk-fixes/fixes
+Already up to date.
+Merging pinctrl-samsung-fixes/fixes (6de23f81a5e0 Linux 7.0-rc1)
+$ git merge -m Merge branch 'fixes' of https://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung.git pinctrl-samsung-fixes/fixes
+Already up to date.
+Merging devicetree-fixes/dt/linus (81122fba08fa of: fix reference count leak in of_alias_scan())
+$ git merge -m Merge branch 'dt/linus' of https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git devicetree-fixes/dt/linus
+Already up to date.
+Merging dt-krzk-fixes/fixes (6de23f81a5e0 Linux 7.0-rc1)
+$ git merge -m Merge branch 'fixes' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt.git dt-krzk-fixes/fixes
+Already up to date.
+Merging scsi-fixes/fixes (98f69975d4c0 Merge branch '7.1/scsi-queue' into 7.1/scsi-fixes)
+$ git merge -m Merge branch 'fixes' of https://git.kernel.org/pub/scm/linux/kernel/git/mkp/scsi.git scsi-fixes/fixes
+Merge made by the 'ort' strategy.
+ drivers/scsi/device_handler/scsi_dh_alua.c |  2 +-
+ drivers/scsi/hisi_sas/hisi_sas_v3_hw.c     |  2 +-
+ drivers/scsi/mpt3sas/mpt3sas_scsih.c       | 14 +++++++++++++-
+ drivers/scsi/pmcraid.h                     |  2 +-
+ drivers/scsi/sg.c                          |  2 +-
+ drivers/scsi/smartpqi/smartpqi_init.c      |  1 +
+ drivers/target/iscsi/iscsi_target.c        | 22 ++++++++++++++++++----
+ drivers/target/target_core_configfs.c      |  2 +-
+ drivers/ufs/core/ufshcd.c                  | 30 ++++++++++++++++++++++++++++--
+ include/ufs/unipro.h                       |  5 +++++
+ 10 files changed, 70 insertions(+), 12 deletions(-)
+Merging drm-fixes/drm-fixes (56d0a0b38faa Merge tag 'drm-misc-fixes-2026-04-23' of https://gitlab.freedesktop.org/drm/misc/kernel into drm-fixes)
+$ git merge -m Merge branch 'drm-fixes' of https://gitlab.freedesktop.org/drm/kernel.git drm-fixes/drm-fixes
+Already up to date.
+Merging drm-intel-fixes/for-linux-next-fixes (028ef9c96e96 Linux 7.0)
+$ git merge -m Merge branch 'for-linux-next-fixes' of https://gitlab.freedesktop.org/drm/i915/kernel.git drm-intel-fixes/for-linux-next-fixes
+Already up to date.
+Merging mmc-fixes/fixes (8f4d20a71022 mmc: vub300: fix use-after-free on disconnect)
+$ git merge -m Merge branch 'fixes' of https://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc.git mmc-fixes/fixes
+Already up to date.
+Merging rtc-fixes/rtc-fixes (6de23f81a5e0 Linux 7.0-rc1)
+$ git merge -m Merge branch 'rtc-fixes' of https://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux.git rtc-fixes/rtc-fixes
+Already up to date.
+Merging gnss-fixes/gnss-linus (f338e7738378 Linux 7.0-rc4)
+$ git merge -m Merge branch 'gnss-linus' of https://git.kernel.org/pub/scm/linux/kernel/git/johan/gnss.git gnss-fixes/gnss-linus
+Already up to date.
+Merging hyperv-fixes/hyperv-fixes (16cbec248976 mshv: Fix infinite fault loop on permission-denied GPA intercepts)
+$ git merge -m Merge branch 'hyperv-fixes' of https://git.kernel.org/pub/scm/linux/kernel/git/hyperv/linux.git hyperv-fixes/hyperv-fixes
+Already up to date.
+Merging risc-v-fixes/fixes (70d39025809b riscv: Define __riscv_copy_{,vec_}{words,bytes}_unaligned() using SYM_TYPED_FUNC_START)
+$ git merge -m Merge branch 'fixes' of https://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git risc-v-fixes/fixes
+Merge made by the 'ort' strategy.
+ arch/riscv/kernel/copy-unaligned.S     | 5 +++--
+ arch/riscv/kernel/vec-copy-unaligned.S | 5 +++--
+ 2 files changed, 6 insertions(+), 4 deletions(-)
+Merging riscv-dt-fixes/riscv-dt-fixes (305f2865bd03 riscv: dts: starfive: jh7110-common: fix jh7110 SoC boot from SD-card.)
+$ git merge -m Merge branch 'riscv-dt-fixes' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git riscv-dt-fixes/riscv-dt-fixes
+Merge made by the 'ort' strategy.
+ arch/riscv/boot/dts/starfive/jh7110-common.dtsi           | 1 +
+ arch/riscv/boot/dts/starfive/jh7110-milkv-marscm-lite.dts | 2 +-
+ 2 files changed, 2 insertions(+), 1 deletion(-)
+Merging riscv-soc-fixes/riscv-soc-fixes (c7596f9001e2 firmware: microchip: fail auto-update probe if no flash found)
+$ git merge -m Merge branch 'riscv-soc-fixes' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git riscv-soc-fixes/riscv-soc-fixes
+Already up to date.
+Merging fpga-fixes/fixes (19272b37aa4f Linux 6.16-rc1)
+$ git merge -m Merge branch 'fixes' of https://git.kernel.org/pub/scm/linux/kernel/git/fpga/linux-fpga.git fpga-fixes/fixes
+Already up to date.
+Merging spdx/spdx-linus (27d128c1cff6 Merge tag 'trace-ring-buffer-v7.1-3' of git://git.kernel.org/pub/scm/linux/kernel/git/trace/linux-trace)
+$ git merge -m Merge branch 'spdx-linus' of https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/spdx.git spdx/spdx-linus
+Already up to date.
+Merging gpio-brgl-fixes/gpio/for-current (e31eee4a9610 gpio: aspeed: fix AST2700 debounce selector bit definitions)
+$ git merge -m Merge branch 'gpio/for-current' of https://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux.git gpio-brgl-fixes/gpio/for-current
+Already up to date.
+Merging gpio-intel-fixes/fixes (254f49634ee1 Linux 7.1-rc1)
+$ git merge -m Merge branch 'fixes' of https://git.kernel.org/pub/scm/linux/kernel/git/andy/linux-gpio-intel.git gpio-intel-fixes/fixes
+Already up to date.
+Merging pinctrl-intel-fixes/fixes (254f49634ee1 Linux 7.1-rc1)
+$ git merge -m Merge branch 'fixes' of https://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel.git pinctrl-intel-fixes/fixes
+Already up to date.
+Merging auxdisplay-fixes/fixes (254f49634ee1 Linux 7.1-rc1)
+$ git merge -m Merge branch 'fixes' of https://git.kernel.org/pub/scm/linux/kernel/git/andy/linux-auxdisplay.git auxdisplay-fixes/fixes
+Already up to date.
+Merging kunit-fixes/kunit-fixes (8b8f1d5e350a kunit: Add documentation of --list_suites)
+$ git merge -m Merge branch 'kunit-fixes' of https://git.kernel.org/pub/scm/linux/kernel/git/shuah/linux-kselftest.git kunit-fixes/kunit-fixes
+Already up to date.
+Merging memblock-fixes/fixes (afd218bb1dd8 mm/fake-numa: fix under-allocation detection in uniform split)
+$ git merge -m Merge branch 'fixes' of https://git.kernel.org/pub/scm/linux/kernel/git/rppt/memblock.git memblock-fixes/fixes
+Merge made by the 'ort' strategy.
+ mm/numa_emulation.c | 17 +++++++++++++----
+ 1 file changed, 13 insertions(+), 4 deletions(-)
+Merging renesas-fixes/fixes (7e8aec50597b Merge branch 'renesas-pinctrl-fixes-for-v7.0' into renesas-fixes)
+$ git merge -m Merge branch 'fixes' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git renesas-fixes/fixes
+Merge made by the 'ort' strategy.
+Merging perf-current/perf-tools (9a683fe0a00d Merge tag 'v7.0-rc6' into perf-tools)
+$ git merge -m Merge branch 'perf-tools' of https://git.kernel.org/pub/scm/linux/kernel/git/perf/perf-tools.git perf-current/perf-tools
+Already up to date.
+Merging efi-fixes/urgent (5241c2ca33bb firmware: efi: Never declare sysfb_primary_display on x86)
+$ git merge -m Merge branch 'urgent' of https://git.kernel.org/pub/scm/linux/kernel/git/efi/efi.git efi-fixes/urgent
+Already up to date.
+Merging battery-fixes/fixes (8f0b4cce4481 Linux 6.19-rc1)
+$ git merge -m Merge branch 'fixes' of https://git.kernel.org/pub/scm/linux/kernel/git/sre/linux-power-supply.git battery-fixes/fixes
+Already up to date.
+Merging iommufd-fixes/for-rc (11439c4635ed Linux 7.0-rc2)
+$ git merge -m Merge branch 'for-rc' of https://git.kernel.org/pub/scm/linux/kernel/git/jgg/iommufd.git iommufd-fixes/for-rc
+Already up to date.
+Merging rust-fixes/rust-fixes (254f49634ee1 Linux 7.1-rc1)
+$ git merge -m Merge branch 'rust-fixes' of https://github.com/Rust-for-Linux/linux.git rust-fixes/rust-fixes
+Already up to date.
+Merging w1-fixes/fixes (6de23f81a5e0 Linux 7.0-rc1)
+$ git merge -m Merge branch 'fixes' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-w1.git w1-fixes/fixes
+Already up to date.
+Merging pmdomain-fixes/fixes (c2812c0cb909 MAINTAINERS, mailmap: Change Ulf Hansson's email)
+$ git merge -m Merge branch 'fixes' of https://git.kernel.org/pub/scm/linux/kernel/git/ulfh/linux-pm.git pmdomain-fixes/fixes
+Already up to date.
+Merging i2c-host-fixes/i2c/i2c-host-fixes (39ed7d89b973 i2c: imx: zero-initialize dma_slave_config for eDMA)
+$ git merge -m Merge branch 'i2c/i2c-host-fixes' of https://git.kernel.org/pub/scm/linux/kernel/git/andi.shyti/linux.git i2c-host-fixes/i2c/i2c-host-fixes
+Already up to date.
+Merging i2c-rust-fixes/rust-i2c-fixes (7ca6d1cfec80 Merge tag 'powerpc-7.0-4' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux)
+$ git merge -m Merge branch 'rust-i2c-fixes' of https://github.com/ikrtn/rust-for-linux i2c-rust-fixes/rust-i2c-fixes
+Already up to date.
+Merging sparc-fixes/for-linus (8f0b4cce4481 Linux 6.19-rc1)
+$ git merge -m Merge branch 'for-linus' of https://git.kernel.org/pub/scm/linux/kernel/git/alarsson/linux-sparc.git sparc-fixes/for-linus
+Already up to date.
+Merging clk-fixes/clk-fixes (cc8f74d3011e Merge tag 'qcom-clk-fixes-for-7.0' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into clk-fixes)
+$ git merge -m Merge branch 'clk-fixes' of https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk-fixes/clk-fixes
+Already up to date.
+Merging thead-clk-fixes/thead-clk-fixes (8f0b4cce4481 Linux 6.19-rc1)
+$ git merge -m Merge branch 'thead-clk-fixes' of https://git.kernel.org/pub/scm/linux/kernel/git/fustini/linux.git thead-clk-fixes/thead-clk-fixes
+Already up to date.
+Merging tenstorrent-clk-fixes/tenstorrent-clk-fixes (6de23f81a5e0 Linux 7.0-rc1)
+$ git merge -m Merge branch 'tenstorrent-clk-fixes' of https://git.kernel.org/pub/scm/linux/kernel/git/tenstorrent/linux.git tenstorrent-clk-fixes/tenstorrent-clk-fixes
+Already up to date.
+Merging pwrseq-fixes/pwrseq/for-current (f338e7738378 Linux 7.0-rc4)
+$ git merge -m Merge branch 'pwrseq/for-current' of https://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux.git pwrseq-fixes/pwrseq/for-current
+Already up to date.
+Merging thead-dt-fixes/thead-dt-fixes (6de23f81a5e0 Linux 7.0-rc1)
+$ git merge -m Merge branch 'thead-dt-fixes' of https://git.kernel.org/pub/scm/linux/kernel/git/fustini/linux.git thead-dt-fixes/thead-dt-fixes
+Already up to date.
+Merging ftrace-fixes/ftrace/fixes (1650a1b6cb1a fgraph: Check ftrace_pids_enabled on registration for early filtering)
+$ git merge -m Merge branch 'ftrace/fixes' of https://git.kernel.org/pub/scm/linux/kernel/git/trace/linux-trace.git ftrace-fixes/ftrace/fixes
+Already up to date.
+Merging ring-buffer-fixes/ring-buffer/fixes (92d5a606721f ring-buffer: Do not double count the reader_page)
+$ git merge -m Merge branch 'ring-buffer/fixes' of https://git.kernel.org/pub/scm/linux/kernel/git/trace/linux-trace.git ring-buffer-fixes/ring-buffer/fixes
+Already up to date.
+Merging trace-fixes/trace/fixes (250ab25391ed tracing: Drain deferred trigger frees if kthread creation fails)
+$ git merge -m Merge branch 'trace/fixes' of https://git.kernel.org/pub/scm/linux/kernel/git/trace/linux-trace.git trace-fixes/trace/fixes
+Already up to date.
+Merging tracefs-fixes/tracefs/fixes (07004a8c4b57 eventfs: Hold eventfs_mutex and SRCU when remount walks events)
+$ git merge -m Merge branch 'tracefs/fixes' of https://git.kernel.org/pub/scm/linux/kernel/git/trace/linux-trace.git tracefs-fixes/tracefs/fixes
+Already up to date.
+Merging spacemit-fixes/fixes (254f49634ee1 Linux 7.1-rc1)
+$ git merge -m Merge branch 'fixes' of https://github.com/spacemit-com/linux spacemit-fixes/fixes
+Already up to date.
+Merging tip-fixes/tip/urgent (27d128c1cff6 Merge tag 'trace-ring-buffer-v7.1-3' of git://git.kernel.org/pub/scm/linux/kernel/git/trace/linux-trace)
+$ git merge -m Merge branch 'tip/urgent' of https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git tip-fixes/tip/urgent
+Already up to date.
+Merging slab-fixes/slab/for-next-fixes (082a6d03a2d6 slub: fix data loss and overflow in krealloc())
+$ git merge -m Merge branch 'slab/for-next-fixes' of https://git.kernel.org/pub/scm/linux/kernel/git/vbabka/slab.git slab-fixes/slab/for-next-fixes
+Already up to date.
+Merging kexec-fixes/kexec-fixes (028ef9c96e96 Linux 7.0)
+$ git merge -m Merge branch 'kexec-fixes' of https://git.kernel.org/pub/scm/linux/kernel/git/liveupdate/linux.git kexec-fixes/kexec-fixes
+Already up to date.
+Merging liveupdate-fixes/fixes (028ef9c96e96 Linux 7.0)
+$ git merge -m Merge branch 'fixes' of https://git.kernel.org/pub/scm/linux/kernel/git/liveupdate/linux.git liveupdate-fixes/fixes
+Already up to date.
+Merging drm-msm-fixes/msm-fixes (a972d1b864e8 drm/msm: Use of_get_available_child_by_name())
+$ git merge -m Merge branch 'msm-fixes' of https://gitlab.freedesktop.org/drm/msm.git drm-msm-fixes/msm-fixes
+Already up to date.
+Merging uml-fixes/fixes (065c4e67cc2c Merge tag 'uml-for-7.1-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/uml/linux)
+$ git merge -m Merge branch 'fixes' of https://git.kernel.org/pub/scm/linux/kernel/git/uml/linux.git uml-fixes/fixes
+Already up to date.
+Merging fwctl-fixes/for-rc (11439c4635ed Linux 7.0-rc2)
+$ git merge -m Merge branch 'for-rc' of https://git.kernel.org/pub/scm/linux/kernel/git/fwctl/fwctl.git fwctl-fixes/for-rc
+Already up to date.
+Merging devsec-tsm-fixes/fixes (c3fd16c3b98e virt: tdx-guest: Fix handling of host controlled 'quote' buffer length)
+$ git merge -m Merge branch 'fixes' of https://git.kernel.org/pub/scm/linux/kernel/git/devsec/tsm.git devsec-tsm-fixes/fixes
+Already up to date.
+Merging drm-rust-fixes/drm-rust-fixes (254f49634ee1 Linux 7.1-rc1)
+$ git merge -m Merge branch 'drm-rust-fixes' of https://gitlab.freedesktop.org/drm/rust/kernel.git drm-rust-fixes/drm-rust-fixes
+Already up to date.
+Merging tenstorrent-dt-fixes/tenstorrent-dt-fixes (6de23f81a5e0 Linux 7.0-rc1)
+$ git merge -m Merge branch 'tenstorrent-dt-fixes' of https://git.kernel.org/pub/scm/linux/kernel/git/tenstorrent/linux.git tenstorrent-dt-fixes/tenstorrent-dt-fixes
+Already up to date.
+Merging drm-misc-fixes/for-linux-next-fixes (d13e855ee923 Merge drm/drm-fixes into drm-misc-fixes)
+$ git merge -m Merge branch 'for-linux-next-fixes' of https://gitlab.freedesktop.org/drm/misc/kernel.git drm-misc-fixes/for-linux-next-fixes
+Auto-merging include/linux/dma-buf.h
+Merge made by the 'ort' strategy.
+ include/linux/dma-buf.h | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+Merging rust/rust-next (254f49634ee1 Linux 7.1-rc1)
+$ git merge -m Merge branch 'rust-next' of https://github.com/Rust-for-Linux/linux.git rust/rust-next
+Already up to date.
+Merging rust-interop/interop-next (05f7e89ab973 Linux 6.19)
+$ git merge -m Merge branch 'interop-next' of https://github.com/Rust-for-Linux/linux.git rust-interop/interop-next
+Already up to date.
+Merging rust-alloc/alloc-next (254f49634ee1 Linux 7.1-rc1)
+$ git merge -m Merge branch 'alloc-next' of https://github.com/Rust-for-Linux/linux.git rust-alloc/alloc-next
+Already up to date.
+Merging rust-io/io-next (86731a2a651e Linux 6.16-rc3)
+$ git merge -m Merge branch 'io-next' of https://github.com/Rust-for-Linux/linux.git rust-io/io-next
+Already up to date.
+Merging rust-pin-init/pin-init-next (09808839c7aa rust: pin-init: replace `addr_of_mut!` with `&raw mut`)
+$ git merge -m Merge branch 'pin-init-next' of https://github.com/Rust-for-Linux/linux.git rust-pin-init/pin-init-next
+Already up to date.
+Merging rust-timekeeping/timekeeping-next (ddb1444d3335 hrtimer: add usage examples to documentation)
+$ git merge -m Merge branch 'timekeeping-next' of https://github.com/Rust-for-Linux/linux.git rust-timekeeping/timekeeping-next
+Already up to date.
+Merging rust-xarray/xarray-next (c455f19bbe61 rust: xarray: add __rust_helper to helpers)
+$ git merge -m Merge branch 'xarray-next' of https://github.com/Rust-for-Linux/linux.git rust-xarray/xarray-next
+Already up to date.
+Merging rust-analyzer/rust-analyzer-next (3418d862679a Merge tag 'rust-analyzer-v7.1' of https://github.com/Rust-for-Linux/linux into rust-next)
+$ git merge -m Merge branch 'rust-analyzer-next' of https://github.com/Rust-for-Linux/linux.git rust-analyzer/rust-analyzer-next
+Already up to date.
+Merging mm-stable/mm-stable (a5d1079c28a5 Merge tag 'ntfs3_for_7.1' of https://github.com/Paragon-Software-Group/linux-ntfs3)
+$ git merge -m Merge branch 'mm-stable' of https://git.kernel.org/pub/scm/linux/kernel/git/akpm/mm mm-stable/mm-stable
+Already up to date.
+Merging mm-nonmm-stable/mm-nonmm-stable (a5d1079c28a5 Merge tag 'ntfs3_for_7.1' of https://github.com/Paragon-Software-Group/linux-ntfs3)
+$ git merge -m Merge branch 'mm-nonmm-stable' of https://git.kernel.org/pub/scm/linux/kernel/git/akpm/mm mm-nonmm-stable/mm-nonmm-stable
+Already up to date.
+Merging mm-unstable/mm-unstable (a2ddbfd1af0f mm/swap: remove redundant swap device reference in alloc/free)
+$ git merge -m Merge branch 'mm-unstable' of https://git.kernel.org/pub/scm/linux/kernel/git/akpm/mm mm-unstable/mm-unstable
+Merge made by the 'ort' strategy.
+ include/linux/swap.h |   5 +-
+ kernel/power/swap.c  |   2 +-
+ kernel/power/user.c  |  15 +++-
+ mm/swapfile.c        | 205 +++++++++++++++++++++++++++++++++++++++------------
+ 4 files changed, 173 insertions(+), 54 deletions(-)
+Merging mm-nonmm-unstable/mm-nonmm-unstable (7ef437c55670 lib/tests: extend cmdline KUnit with next_arg() tests)
+$ git merge -m Merge branch 'mm-nonmm-unstable' of https://git.kernel.org/pub/scm/linux/kernel/git/akpm/mm mm-nonmm-unstable/mm-nonmm-unstable
+Auto-merging MAINTAINERS
+Auto-merging Makefile
+Auto-merging arch/arm64/Kconfig
+Auto-merging lib/Kconfig.debug
+Auto-merging lib/tests/Makefile
+Auto-merging mm/Kconfig
+Auto-merging scripts/checkpatch.pl
+Merge made by the 'ort' strategy.
+ .clang-format                                      |   2 +
+ Documentation/admin-guide/index.rst                |   1 +
+ Documentation/admin-guide/kallsyms-lineinfo.rst    |  97 +++
+ Documentation/admin-guide/sysctl/kernel.rst        |   1 +
+ Documentation/atomic_t.txt                         |  14 +-
+ Documentation/dev-tools/checkpatch.rst             |  14 +
+ MAINTAINERS                                        |   9 +
+ Makefile                                           |   2 +-
+ arch/arm64/Kconfig                                 |   3 +
+ arch/arm64/include/asm/barrier.h                   |  23 +
+ arch/arm64/include/asm/cmpxchg.h                   |  62 +-
+ arch/arm64/include/asm/delay-const.h               |  27 +
+ arch/arm64/include/asm/rqspinlock.h                |  85 ---
+ arch/arm64/lib/delay.c                             |  17 +-
+ arch/riscv/kernel/image-vars.h                     |   9 +
+ certs/Kconfig                                      |  14 +-
+ drivers/clocksource/arm_arch_timer.c               |   2 +
+ drivers/cpuidle/poll_state.c                       |  21 +-
+ drivers/soc/qcom/rpmh-rsc.c                        |   8 +-
+ fs/Kconfig                                         |   6 +-
+ fs/coredump.c                                      |   5 +
+ fs/fat/fat_test.c                                  |  33 +
+ fs/ocfs2/quota_local.c                             |   2 +-
+ fs/proc/base.c                                     |  63 +-
+ fs/proc/generic.c                                  |  10 +-
+ include/asm-generic/barrier.h                      |  95 +++
+ include/linux/atomic.h                             |  10 +
+ include/linux/atomic/atomic-long.h                 |  18 +-
+ include/linux/codetag.h                            |   3 +-
+ include/linux/init.h                               |   2 +-
+ include/linux/kallsyms.h                           |  17 +-
+ include/linux/mod_lineinfo.h                       | 243 ++++++
+ include/linux/module.h                             |   5 +
+ include/linux/sched/idle.h                         |  29 +
+ init/Kconfig                                       |  59 +-
+ kernel/bpf/rqspinlock.c                            |  77 +-
+ kernel/fork.c                                      |  11 +-
+ kernel/kallsyms.c                                  |  58 ++
+ kernel/kallsyms_internal.h                         |  11 +
+ kernel/module/kallsyms.c                           |  80 ++
+ kernel/module/main.c                               |   3 +
+ kernel/taskstats.c                                 |  62 +-
+ lib/Kconfig                                        |   2 +-
+ lib/Kconfig.debug                                  |  20 +
+ lib/alloc_tag.c                                    |   8 +-
+ lib/base64.c                                       |   5 +-
+ lib/cmdline.c                                      |  30 +-
+ lib/codetag.c                                      |  12 +-
+ lib/idr.c                                          |  55 +-
+ lib/kstrtox.c                                      |  37 +-
+ lib/seq_buf.c                                      |   1 +
+ lib/test-kstrtox.c                                 |   6 +
+ lib/test_ida.c                                     |  14 +
+ lib/tests/Makefile                                 |   4 +
+ lib/tests/barrier-timeout-test.c                   | 125 +++
+ lib/tests/cmdline_kunit.c                          | 118 +++
+ lib/tests/lineinfo_kunit.c                         | 813 ++++++++++++++++++++
+ lib/tests/seq_buf_kunit.c                          |  34 +
+ lib/tests/string_helpers_kunit.c                   |  15 +-
+ mm/Kconfig                                         |   4 +-
+ scripts/.gitignore                                 |   1 +
+ scripts/Makefile                                   |   3 +
+ scripts/Makefile.modfinal                          |   6 +
+ scripts/atomic/gen-atomic-long.sh                  |  16 +-
+ scripts/checkpatch.pl                              |  47 +-
+ scripts/empty_lineinfo.S                           |  38 +
+ scripts/gen-mod-lineinfo.sh                        |  48 ++
+ scripts/gen_lineinfo.c                             | 848 +++++++++++++++++++++
+ scripts/get_maintainer.pl                          |  71 +-
+ scripts/kallsyms.c                                 |  17 +
+ scripts/link-vmlinux.sh                            |  43 +-
+ tools/accounting/getdelays.c                       |   8 +-
+ tools/testing/selftests/acct/.gitignore            |   3 +-
+ tools/testing/selftests/acct/Makefile              |   7 +-
+ .../selftests/acct/taskstats_fill_stats_tgid.c     | 375 +++++++++
+ tools/testing/selftests/filelock/.gitignore        |   1 +
+ tools/testing/selftests/filelock/ofdlocks.c        |  94 +--
+ 77 files changed, 3796 insertions(+), 446 deletions(-)
+ create mode 100644 Documentation/admin-guide/kallsyms-lineinfo.rst
+ create mode 100644 arch/arm64/include/asm/delay-const.h
+ create mode 100644 include/linux/mod_lineinfo.h
+ create mode 100644 lib/tests/barrier-timeout-test.c
+ create mode 100644 lib/tests/lineinfo_kunit.c
+ create mode 100644 scripts/empty_lineinfo.S
+ create mode 100755 scripts/gen-mod-lineinfo.sh
+ create mode 100644 scripts/gen_lineinfo.c
+ create mode 100644 tools/testing/selftests/acct/taskstats_fill_stats_tgid.c
+ create mode 100644 tools/testing/selftests/filelock/.gitignore
+Merging kbuild/kbuild-for-next (254f49634ee1 Linux 7.1-rc1)
+$ git merge -m Merge branch 'kbuild-for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/kbuild/linux.git kbuild/kbuild-for-next
+Already up to date.
+Merging clang-format/clang-format (8f0b4cce4481 Linux 6.19-rc1)
+$ git merge -m Merge branch 'clang-format' of https://github.com/ojeda/linux.git clang-format/clang-format
+Already up to date.
+Merging perf/perf-tools-next (841dbf4871c5 perf loongarch: Fix build failure with CONFIG_LIBDW_DWARF_UNWIND)
+$ git merge -m Merge branch 'perf-tools-next' of https://git.kernel.org/pub/scm/linux/kernel/git/perf/perf-tools-next.git perf/perf-tools-next
+Already up to date.
+Merging compiler-attributes/compiler-attributes (8f0b4cce4481 Linux 6.19-rc1)
+$ git merge -m Merge branch 'compiler-attributes' of https://github.com/ojeda/linux.git compiler-attributes/compiler-attributes
+Already up to date.
+Merging dma-mapping/dma-mapping-for-next (15818b2cd42d dma-buf: heaps: system: document system_cc_shared heap)
+$ git merge -m Merge branch 'dma-mapping-for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/mszyprowski/linux.git dma-mapping/dma-mapping-for-next
+Already up to date.
+Merging asm-generic/master (adbbd9714f80 scripts: headers_install.sh: Remove config leak ignore machinery)
+$ git merge -m Merge branch 'master' of https://git.kernel.org/pub/scm/linux/kernel/git/arnd/asm-generic asm-generic/master
+Already up to date.
+Merging nocache-cleanup/nocache-cleanup (809b997a5ce9 x86-64/arm64/powerpc: clean up and rename __copy_from_user_flushcache)
+$ git merge -m Merge branch 'nocache-cleanup' of https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git nocache-cleanup/nocache-cleanup
+Already up to date.
+Merging alpha/alpha-next (d58041d2c63e MAINTAINERS: Add Magnus Lindholm as maintainer for alpha port)
+$ git merge -m Merge branch 'alpha-next' of https://git.kernel.org/pub/scm/linux/kernel/git/mattst88/alpha.git alpha/alpha-next
+Already up to date.
+Merging arm/for-next (c6e61c06d606 ARM: 9463/1: Allow to enable RT)
+$ git merge -m Merge branch 'for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/rmk/linux.git arm/for-next
+Already up to date.
+Merging arm64/for-next/core (858fbd7248bd Merge branch 'for-next/c1-pro-erratum-4193714' into for-next/core)
+$ git merge -m Merge branch 'for-next/core' of https://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux arm64/for-next/core
+Already up to date.
+Merging arm-perf/for-next/perf (47f06ebbe8da perf/arm-cmn: Fix resource_size_t printk specifier in arm_cmn_init_dtc())
+$ git merge -m Merge branch 'for-next/perf' of https://git.kernel.org/pub/scm/linux/kernel/git/will/linux.git arm-perf/for-next/perf
+Already up to date.
+Merging arm-soc/for-next (65e1752b3f5b soc: document merges)
+$ git merge -m Merge branch 'for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/soc/soc.git arm-soc/for-next
+Merge made by the 'ort' strategy.
+ arch/arm/arm-soc-for-next-contents.txt | 23 +++++++++++++++++++++++
+ 1 file changed, 23 insertions(+)
+ create mode 100644 arch/arm/arm-soc-for-next-contents.txt
+Merging amlogic/for-next (8b379d5e9eb7 Merge branch 'v7.2/arm64-dt' into for-next)
+$ git merge -m Merge branch 'for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/amlogic/linux.git amlogic/for-next
+Merge made by the 'ort' strategy.
+ .../dts/amlogic/amlogic-t7-a311d2-khadas-vim4.dts  | 199 +++++++++
+ arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi        | 464 +++++++++++++++++++++
+ .../dts/amlogic/meson-gxl-s905d-phicomm-n1.dts     |  15 +
+ .../dts/amlogic/meson-s4-s905y4-khadas-vim1s.dts   |  81 ++++
+ arch/arm64/boot/dts/amlogic/meson-s4.dtsi          |  45 ++
+ 5 files changed, 804 insertions(+)
+Merging asahi-soc/asahi-soc/for-next (d31647c698f6 Merge branch 'apple-soc/drivers-6.20' into asahi-soc/for-next)
+$ git merge -m Merge branch 'asahi-soc/for-next' of https://github.com/AsahiLinux/linux.git asahi-soc/asahi-soc/for-next
+Merge made by the 'ort' strategy.
+Merging at91/at91-next (c96e60ae720a Merge branch 'at91-dt' into at91-next)
+$ git merge -m Merge branch 'at91-next' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux.git at91/at91-next
+Merge made by the 'ort' strategy.
+Merging bmc/for-next (cd44dc5ead30 Merge branches 'aspeed/arm/dt', 'aspeed/fixes/drivers' and 'nuvoton/arm64/dt' into for-next)
+$ git merge -m Merge branch 'for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/bmc/linux.git bmc/for-next
+Merge made by the 'ort' strategy.
+ drivers/soc/aspeed/Kconfig | 1 -
+ 1 file changed, 1 deletion(-)
+Merging broadcom/next (ddfdca13def5 Merge branch 'devicetree-arm64/next' into next)
+$ git merge -m Merge branch 'next' of https://github.com/Broadcom/stblinux.git broadcom/next
+Merge made by the 'ort' strategy.
+Merging cix/for-next (517d8fc52f3c arm64: defconfig: Enable CIX Sky1 pinctrl, PCIe host, and Cadence GPIO)
+$ git merge -m Merge branch 'for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/peter.chen/cix.git cix/for-next
+Auto-merging arch/arm64/configs/defconfig
+Merge made by the 'ort' strategy.
+ arch/arm64/configs/defconfig | 3 +++
+ 1 file changed, 3 insertions(+)
+Merging davinci/davinci/for-next (6de23f81a5e0 Linux 7.0-rc1)
+$ git merge -m Merge branch 'davinci/for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux.git davinci/davinci/for-next
+Already up to date.
+Merging drivers-memory/for-next (82169065ffb0 memory: tegra: Add MC error logging support for Tegra264)
+$ git merge -m Merge branch 'for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl.git drivers-memory/for-next
+Already up to date.
+Merging fsl/soc_fsl (c99d8ac7b355 bus: fsl-mc: wait for the MC firmware to complete its boot)
+$ git merge -m Merge branch 'soc_fsl' of https://git.kernel.org/pub/scm/linux/kernel/git/chleroy/linux.git fsl/soc_fsl
+Merge made by the 'ort' strategy.
+ drivers/base/platform-msi.c                 |   4 -
+ drivers/bus/fsl-mc/dprc-driver.c            |  14 +--
+ drivers/bus/fsl-mc/fsl-mc-bus.c             |  50 ++++++++-
+ drivers/bus/fsl-mc/fsl-mc-msi.c             | 166 +++++----------------------
+ drivers/bus/fsl-mc/fsl-mc-private.h         |   2 +-
+ drivers/irqchip/Kconfig                     |   6 -
+ drivers/irqchip/Makefile                    |   1 -
+ drivers/irqchip/irq-gic-its-msi-parent.c    |   7 +-
+ drivers/irqchip/irq-gic-v3-its-fsl-mc-msi.c | 168 ----------------------------
+ drivers/soc/fsl/qe/qe.c                     |   3 +
+ drivers/soc/fsl/qe/qe_ports_ic.c            |  23 ++--
+ include/linux/fsl/mc.h                      |   6 +-
+ include/linux/irqdomain_defs.h              |   1 -
+ include/uapi/linux/fsl_hypervisor.h         |   4 +-
+ 14 files changed, 106 insertions(+), 349 deletions(-)
+ delete mode 100644 drivers/irqchip/irq-gic-v3-its-fsl-mc-msi.c
+Merging imx-mxs/for-next (06856fe10891 Merge branches 'imx/bindings', 'imx/dt', 'imx/dt64', 'imx/fixes' and 'imx/soc' into for-next)
+$ git merge -m Merge branch 'for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/frank.li/linux.git imx-mxs/for-next
+Merge made by the 'ort' strategy.
+Merging mediatek/for-next (e6490a169f6d Merge branch 'v7.0-next/dts64' into for-next)
+$ git merge -m Merge branch 'for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/mediatek/linux.git mediatek/for-next
+Merge made by the 'ort' strategy.
+Merging mvebu/for-next (ae4fe907b770 Merge branch 'mvebu/dt64' into mvebu/for-next)
+$ git merge -m Merge branch 'for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu.git mvebu/for-next
+Merge made by the 'ort' strategy.
+Merging omap/for-next (7889b194a15e Merge branch 'omap-for-v7.1/soc' into tmp/omap-next-20260331.171532)
+$ git merge -m Merge branch 'for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap.git omap/for-next
+Merge made by the 'ort' strategy.
+Merging qcom/for-next (254f49634ee1 Linux 7.1-rc1)
+$ git merge -m Merge branch 'for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux.git qcom/for-next
+Already up to date.
+Merging renesas/next (1ba26dfafb4d Merge branch 'renesas-dts-for-v7.1' into renesas-next)
+$ git merge -m Merge branch 'next' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git renesas/next
+Merge made by the 'ort' strategy.
+Merging reset/reset/next (d373605cd514 Merge tag 'reset-fixes-for-v7.0-2' into reset/next)
+$ git merge -m Merge branch 'reset/next' of https://git.pengutronix.de/git/pza/linux reset/reset/next
+Already up to date.
+Merging rockchip/for-next (9772d92b403f Merge branch 'v7.1-armsoc/dts64' into for-next)
+$ git merge -m Merge branch 'for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git rockchip/for-next
+Merge made by the 'ort' strategy.
+ arch/arm64/boot/dts/rockchip/rk3576.dtsi      |  6 +++---
+ arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 12 ++++++------
+ 2 files changed, 9 insertions(+), 9 deletions(-)
+Merging samsung-krzk/for-next (909d9996904b Merge branch 'next/clk' into for-next)
+$ git merge -m Merge branch 'for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux.git samsung-krzk/for-next
+Merge made by the 'ort' strategy.
+Merging scmi/for-linux-next (20d83b0a39f6 Merge branches 'for-next/scmi/updates' and 'for-next/ffa/fixes' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into for-linux-next)
+$ git merge -m Merge branch 'for-linux-next' of https://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux.git scmi/for-linux-next
+Merge made by the 'ort' strategy.
+ drivers/clk/clk-scmi.c                             |  48 +---
+ drivers/firmware/arm_scmi/base.c                   |  10 +-
+ drivers/firmware/arm_scmi/clock.c                  | 319 ++++++++++++++++-----
+ drivers/firmware/arm_scmi/common.h                 |   2 +-
+ drivers/firmware/arm_scmi/driver.c                 |  98 ++++---
+ drivers/firmware/arm_scmi/protocols.h              |  13 +-
+ drivers/firmware/arm_scmi/quirks.c                 |  15 +-
+ .../firmware/arm_scmi/vendors/imx/imx-sm-misc.c    |  86 ++++++
+ drivers/firmware/imx/sm-misc.c                     |  73 +++++
+ include/linux/scmi_imx_protocol.h                  |  14 +
+ include/linux/scmi_protocol.h                      |  35 ++-
+ 11 files changed, 534 insertions(+), 179 deletions(-)
+Merging sophgo/for-next (9aa6068586a9 Merge branch 'dt/riscv' into for-next)
+$ git merge -m Merge branch 'for-next' of https://github.com/sophgo/linux.git sophgo/for-next
+Merge made by the 'ort' strategy.
+ arch/riscv/boot/dts/sophgo/cv180x.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+Merging sophgo-soc/soc-for-next (c8754c7deab4 soc: sophgo: cv1800: rtcsys: New driver (handling RTC only))
+$ git merge -m Merge branch 'soc-for-next' of https://github.com/sophgo/linux.git sophgo-soc/soc-for-next
+Already up to date.
+Merging spacemit/for-next (254f49634ee1 Linux 7.1-rc1)
+$ git merge -m Merge branch 'for-next' of https://github.com/spacemit-com/linux spacemit/for-next
+Already up to date.
+Merging stm32/stm32-next (515aa8b11884 arm64: defconfig: Enable STMicroelectronics STM32 display support)
+$ git merge -m Merge branch 'stm32-next' of https://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32.git stm32/stm32-next
+Auto-merging MAINTAINERS
+Auto-merging arch/arm64/configs/defconfig
+Auto-merging drivers/bus/Kconfig
+Auto-merging drivers/bus/Makefile
+Merge made by the 'ort' strategy.
+Merging sunxi/sunxi/for-next (254f49634ee1 Linux 7.1-rc1)
+$ git merge -m Merge branch 'sunxi/for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux.git sunxi/sunxi/for-next
+Already up to date.
+Merging tee/next (68ab55bcc5f5 Merge branch 'tee_for_v7.1' into next)
+$ git merge -m Merge branch 'next' of https://git.kernel.org/pub/scm/linux/kernel/git/jenswi/linux-tee.git tee/next
+Merge made by the 'ort' strategy.
+ drivers/tee/optee/supp.c | 107 ++++++++++++++++++++++++++++++++---------------
+ 1 file changed, 74 insertions(+), 33 deletions(-)
+Merging tegra/for-next (aea8e82c39d0 Merge branch for-7.1/arm64/defconfig into for-next)
+$ git merge -m Merge branch 'for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux.git tegra/for-next
+Auto-merging Documentation/devicetree/bindings/arm/tegra.yaml
+Auto-merging arch/arm64/boot/dts/nvidia/tegra264.dtsi
+CONFLICT (content): Merge conflict in arch/arm64/boot/dts/nvidia/tegra264.dtsi
+Resolved 'arch/arm64/boot/dts/nvidia/tegra264.dtsi' using previous resolution.
+Automatic merge failed; fix conflicts and then commit the result.
+$ git commit --no-edit -v -a
+[master ea8f5000c711] Merge branch 'for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux.git
+$ git diff -M --stat --summary HEAD^..
+
+Merging tenstorrent-dt/tenstorrent-dt-for-next (ad3cb8132313 riscv: dts: tenstorrent: Add PMU node to blackhole for Linux perf support)
+$ git merge -m Merge branch 'tenstorrent-dt-for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/tenstorrent/linux.git tenstorrent-dt/tenstorrent-dt-for-next
+Merge made by the 'ort' strategy.
+ arch/riscv/boot/dts/tenstorrent/blackhole.dtsi | 48 ++++++++++++++++++++++++++
+ 1 file changed, 48 insertions(+)
+Merging thead-dt/thead-dt-for-next (74ec3d52c003 riscv: dts: thead: beaglev-ahead: enable HDMI output)
+$ git merge -m Merge branch 'thead-dt-for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/fustini/linux.git thead-dt/thead-dt-for-next
+Already up to date.
+Merging ti/ti-next (5a679ea0a7c0 Merge branch 'ti-k3-dts-next' into ti-next)
+$ git merge -m Merge branch 'ti-next' of https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux.git ti/ti-next
+Merge made by the 'ort' strategy.
+Merging xilinx/for-next (edacbf64eedd soc: xilinx: Shutdown and free rx mailbox channel)
+$ git merge -m Merge branch 'for-next' of https://github.com/Xilinx/linux-xlnx.git xilinx/for-next
+Merge made by the 'ort' strategy.
+ drivers/soc/xilinx/zynqmp_power.c | 47 +++++++++++++++++----------------------
+ 1 file changed, 20 insertions(+), 27 deletions(-)
+Merging socfpga/for-next (9d29bcefcdbe arm64: dts: intel: agilex5: Drop CPU masks from GICv3 PPI interrupts)
+$ git merge -m Merge branch 'for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux.git socfpga/for-next
+Merge made by the 'ort' strategy.
+Merging clk/clk-next (522567362b63 clk: bcm: rpi: Mark VEC clock as CLK_IGNORE_UNUSED)
+$ git merge -m Merge branch 'clk-next' of https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk/clk-next
+Already up to date.
+Merging clk-imx/for-next (d16f57caa787 clk: imx8mq: Correct the CSI PHY sels)
+$ git merge -m Merge branch 'for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/abelvesa/linux.git clk-imx/for-next
+Already up to date.
+Merging clk-renesas/renesas-clk (77894661c00a clk: renesas: Add support for RZ/G3L SoC)
+$ git merge -m Merge branch 'renesas-clk' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git clk-renesas/renesas-clk
+Already up to date.
+Merging thead-clk/thead-clk-for-next (baf4fc7c03bd clk: thead: th1520-ap: Support CPU frequency scaling)
+$ git merge -m Merge branch 'thead-clk-for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/fustini/linux.git thead-clk/thead-clk-for-next
+Already up to date.
+Merging tenstorrent-clk/tenstorrent-clk-for-next (23c8ebc95284 clk: tenstorrent: Add Atlantis clock controller driver)
+$ git merge -m Merge branch 'tenstorrent-clk-for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/tenstorrent/linux.git tenstorrent-clk/tenstorrent-clk-for-next
+Already up to date.
+Merging csky/linux-next (817d21578d51 csky: Remove compile warning for CONFIG_SMP)
+$ git merge -m Merge branch 'linux-next' of https://github.com/c-sky/csky-linux.git csky/linux-next
+Already up to date.
+Merging loongarch/loongarch-next (7939f96f26e9 selftests/bpf: Enable CAN_USE_LOAD_ACQ_STORE_REL for LoongArch)
+$ git merge -m Merge branch 'loongarch-next' of https://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson.git loongarch/loongarch-next
+Already up to date.
+Merging m68k/for-next (56f295853f38 m68k: virt: Switch to qemu-virt-ctrl driver)
+$ git merge -m Merge branch 'for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/linux-m68k.git m68k/for-next
+Already up to date.
+Merging m68knommu/for-next (c94727deb107 m68k: update boards company name)
+$ git merge -m Merge branch 'for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/gerg/m68knommu.git m68knommu/for-next
+Merge made by the 'ort' strategy.
+ arch/m68k/Kconfig.machine           |  8 ++++----
+ arch/m68k/coldfire/amcore.c         |  4 ++--
+ arch/m68k/coldfire/stmark2.c        |  4 ++--
+ arch/m68k/configs/stmark2_defconfig | 33 ++++++++++++++++++++-------------
+ 4 files changed, 28 insertions(+), 21 deletions(-)
+Merging microblaze/next (6de23f81a5e0 Linux 7.0-rc1)
+$ git merge -m Merge branch 'next' of git://git.monstr.eu/linux-2.6-microblaze.git microblaze/next
+Already up to date.
+Merging mips/mips-next (15513eefac7c MIPS/mtd: Handle READY GPIO in generic NAND platform data)
+$ git merge -m Merge branch 'mips-next' of https://git.kernel.org/pub/scm/linux/kernel/git/mips/linux.git mips/mips-next
+Already up to date.
+Merging openrisc/for-next (0dfffa5479d6 openrisc: define arch-specific version of nop())
+$ git merge -m Merge branch 'for-next' of https://github.com/openrisc/linux.git openrisc/for-next
+Already up to date.
+Merging parisc-hd/for-next (24e49eb63a32 Revert "parisc: led: fix reference leak on failed device registration")
+$ git merge -m Merge branch 'for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/deller/parisc-linux.git parisc-hd/for-next
+Merge made by the 'ort' strategy.
+ drivers/parisc/led.c | 6 ++----
+ 1 file changed, 2 insertions(+), 4 deletions(-)
+Merging powerpc/next (b80777aef570 mailmap: Add entry for Andrew Donnellan)
+$ git merge -m Merge branch 'next' of https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git powerpc/next
+Already up to date.
+Merging risc-v/for-next (9b3a2be84803 riscv: Remove support for XIP kernel)
+$ git merge -m Merge branch 'for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux.git risc-v/for-next
+Already up to date.
+Merging riscv-dt/riscv-dt-for-next (ae488e2669f3 riscv: dts: microchip: sort pic64gx i2c nodes alphanumerically)
+$ git merge -m Merge branch 'riscv-dt-for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git riscv-dt/riscv-dt-for-next
+Merge made by the 'ort' strategy.
+ .../boot/dts/microchip/pic64gx-curiosity-kit.dts   | 63 +++++++++++++---------
+ arch/riscv/boot/dts/microchip/pic64gx.dtsi         | 40 +++++++++++---
+ 2 files changed, 70 insertions(+), 33 deletions(-)
+Merging riscv-soc/riscv-soc-for-next (b5865650b209 Merge branch 'riscv-soc-drivers-for-next' into riscv-soc-for-next)
+$ git merge -m Merge branch 'riscv-soc-for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git riscv-soc/riscv-soc-for-next
+Auto-merging Documentation/devicetree/bindings/timer/sifive,clint.yaml
+Merge made by the 'ort' strategy.
+ .../interrupt-controller/sifive,plic-1.0.0.yaml    |   1 +
+ .../devicetree/bindings/riscv/canaan.yaml          |   8 +-
+ .../soc/microchip/microchip,mpfs-irqmux.yaml       |   6 +-
+ .../devicetree/bindings/timer/sifive,clint.yaml    |   1 +
+ arch/riscv/boot/dts/canaan/Makefile                |   2 +
+ arch/riscv/boot/dts/canaan/k230-canmv.dts          | 332 +++++++++++++++++++++
+ arch/riscv/boot/dts/canaan/k230-evb.dts            |  28 ++
+ arch/riscv/boot/dts/canaan/k230-pinctrl.h          |  18 ++
+ arch/riscv/boot/dts/canaan/k230.dtsi               | 157 ++++++++++
+ 9 files changed, 551 insertions(+), 2 deletions(-)
+ create mode 100644 arch/riscv/boot/dts/canaan/k230-canmv.dts
+ create mode 100644 arch/riscv/boot/dts/canaan/k230-evb.dts
+ create mode 100644 arch/riscv/boot/dts/canaan/k230-pinctrl.h
+ create mode 100644 arch/riscv/boot/dts/canaan/k230.dtsi
+Merging s390/for-next (c3e8a8ef58bd Merge branch 'features' into for-next)
+$ git merge -m Merge branch 'for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/s390/linux.git s390/for-next
+Merge made by the 'ort' strategy.
+Merging sh/for-next (647b43f65357 sh: Drop CONFIG_FIRMWARE_EDID from defconfig files)
+$ git merge -m Merge branch 'for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/glaubitz/sh-linux.git sh/for-next
+Already up to date.
+Merging sparc/for-next (d844152d85cf sparc: remove unused variable strtab)
+$ git merge -m Merge branch 'for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/alarsson/linux-sparc.git sparc/for-next
+Already up to date.
+Merging uml/next (065c4e67cc2c Merge tag 'uml-for-7.1-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/uml/linux)
+$ git merge -m Merge branch 'next' of https://git.kernel.org/pub/scm/linux/kernel/git/uml/linux.git uml/next
+Already up to date.
+Merging xtensa/xtensa-for-next (aa5903b47d4b xtensa: uapi: Reuse asm-generic ucontext.h)
+$ git merge -m Merge branch 'xtensa-for-next' of https://github.com/jcmvbkbc/linux-xtensa.git xtensa/xtensa-for-next
+Already up to date.
+Merging fs-next (633153240336 Merge branch 'for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs.git)
+$ git merge -m Merge branch 'fs-next' of linux-next fs-next
+Auto-merging MAINTAINERS
+Merge made by the 'ort' strategy.
+ Documentation/netlink/specs/nfsd.yaml         |  229 +++++
+ Documentation/netlink/specs/sunrpc_cache.yaml |  149 +++
+ MAINTAINERS                                   |    8 +-
+ drivers/mtd/ubi/ubi.h                         |    9 +-
+ fs/ecryptfs/keystore.c                        |   16 +-
+ fs/exfat/dir.c                                |    4 +-
+ fs/exfat/nls.c                                |   19 +-
+ fs/fuse/Makefile                              |    3 +-
+ fs/fuse/args.h                                |   65 ++
+ fs/fuse/backing.c                             |    1 +
+ fs/fuse/control.c                             |   16 +-
+ fs/fuse/cuse.c                                |   28 +-
+ fs/fuse/dev.c                                 | 1253 +++++++++----------------
+ fs/fuse/dev.h                                 |  110 +++
+ fs/fuse/dev_uring.c                           |  143 ++-
+ fs/fuse/dev_uring_i.h                         |   39 +-
+ fs/fuse/dir.c                                 |   12 +-
+ fs/fuse/file.c                                |  146 +--
+ fs/fuse/fuse_dev_i.h                          |  350 ++++++-
+ fs/fuse/fuse_i.h                              |  860 ++++++-----------
+ fs/fuse/fuse_trace.h                          |    4 +-
+ fs/fuse/inode.c                               |  255 +----
+ fs/fuse/notify.c                              |  434 +++++++++
+ fs/fuse/poll.c                                |  141 +++
+ fs/fuse/req.c                                 |   99 ++
+ fs/fuse/req_timeout.c                         |  148 +++
+ fs/fuse/sysctl.c                              |    1 +
+ fs/fuse/sysctl.h                              |    9 +
+ fs/fuse/virtio_fs.c                           |   21 +-
+ fs/isofs/export.c                             |    2 +-
+ fs/isofs/namei.c                              |   11 +-
+ fs/isofs/rock.c                               |    9 +
+ fs/netfs/buffered_read.c                      |    9 +-
+ fs/netfs/buffered_write.c                     |   51 +-
+ fs/netfs/iterator.c                           |   13 +-
+ fs/netfs/misc.c                               |    8 +-
+ fs/netfs/read_retry.c                         |   11 +-
+ fs/nfs/dns_resolve.c                          |    2 +-
+ fs/nfsd/export.c                              |  713 +++++++++++++-
+ fs/nfsd/netlink.c                             |   93 ++
+ fs/nfsd/netlink.h                             |   18 +
+ fs/nfsd/nfs4idmap.c                           |    4 +-
+ fs/nfsd/nfs4state.c                           |    9 +-
+ fs/nfsd/nfsctl.c                              |   79 ++
+ fs/nfsd/nfsd.h                                |   17 +-
+ fs/notify/fanotify/fanotify.c                 |    2 +-
+ fs/notify/fsnotify.c                          |    2 +-
+ fs/notify/mark.c                              |   57 +-
+ fs/ntfs/dir.c                                 |   13 +-
+ fs/ntfs/index.c                               |   17 +-
+ fs/ntfs/reparse.c                             |    5 +-
+ fs/smb/client/cifsproto.h                     |    1 -
+ fs/smb/client/fs_context.c                    |   31 -
+ fs/udf/misc.c                                 |    8 +-
+ include/linux/fsnotify_backend.h              |    1 +
+ include/linux/sunrpc/cache.h                  |   15 +-
+ include/trace/events/netfs.h                  |    5 +
+ include/uapi/linux/nfsd_netlink.h             |  132 +++
+ include/uapi/linux/sunrpc_netlink.h           |   84 ++
+ kernel/nsproxy.c                              |    2 +-
+ net/ceph/crush/crush.c                        |    6 +-
+ net/ceph/osdmap.c                             |    7 +-
+ net/sunrpc/Makefile                           |    2 +-
+ net/sunrpc/auth_gss/svcauth_gss.c             |    2 +-
+ net/sunrpc/cache.c                            |  127 ++-
+ net/sunrpc/netlink.c                          |   97 ++
+ net/sunrpc/netlink.h                          |   35 +
+ net/sunrpc/sunrpc_syms.c                      |   10 +
+ net/sunrpc/svc_xprt.c                         |   46 +-
+ net/sunrpc/svcauth_unix.c                     |  516 +++++++++-
+ 70 files changed, 4820 insertions(+), 2024 deletions(-)
+ create mode 100644 Documentation/netlink/specs/sunrpc_cache.yaml
+ create mode 100644 fs/fuse/args.h
+ create mode 100644 fs/fuse/dev.h
+ create mode 100644 fs/fuse/notify.c
+ create mode 100644 fs/fuse/poll.c
+ create mode 100644 fs/fuse/req.c
+ create mode 100644 fs/fuse/req_timeout.c
+ create mode 100644 fs/fuse/sysctl.h
+ create mode 100644 include/uapi/linux/sunrpc_netlink.h
+ create mode 100644 net/sunrpc/netlink.c
+ create mode 100644 net/sunrpc/netlink.h
+$ git am -3 ../patches/0001-ntfs-Fix-up-mm-merge.patch
+Applying: ntfs: Fix up mm merge
+Using index info to reconstruct a base tree...
+M	fs/ntfs/file.c
+Falling back to patching base and 3-way merge...
+Auto-merging fs/ntfs/file.c
+CONFLICT (content): Merge conflict in fs/ntfs/file.c
+Recorded preimage for 'fs/ntfs/file.c'
+error: Failed to merge in the changes.
+hint: Use 'git am --show-current-patch=diff' to see the failed patch
+hint: When you have resolved this problem, run "git am --continue".
+hint: If you prefer to skip this patch, run "git am --skip" instead.
+hint: To restore the original branch and stop patching, run "git am --abort".
+hint: Disable this message with "git config set advice.mergeConflict false"
+Patch failed at 0001 ntfs: Fix up mm merge
+Merging printk/for-next (7b6fb2472fcb Merge branch 'for-7.1-printf-kunit-build' into for-next)
+$ git merge -m Merge branch 'for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/printk/linux.git printk/for-next
+Merge made by the 'ort' strategy.
+Merging pci/next (40286d6379aa Merge tag 'pci-v7.1-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci)
+$ git merge -m Merge branch 'next' of https://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git pci/next
+Already up to date.
+Merging pstore/for-next/pstore (24b8f8dcb9a1 pstore/ftrace: Factor KASLR offset in the core kernel instruction addresses)
+$ git merge -m Merge branch 'for-next/pstore' of https://git.kernel.org/pub/scm/linux/kernel/git/kees/linux.git pstore/for-next/pstore
+Already up to date.
+Merging hid/for-next (7df6572f1cb3 Merge branch 'for-7.1/core-v2' into for-next)
+$ git merge -m Merge branch 'for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/hid/hid.git hid/for-next
+Merge made by the 'ort' strategy.
+Merging i2c/i2c/for-next (4a1817466394 Merge branch 'i2c/for-mergewindow' into i2c/for-next)
+$ git merge -m Merge branch 'i2c/for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/wsa/linux.git i2c/i2c/for-next
+Merge made by the 'ort' strategy.
+Merging i2c-host/i2c/i2c-host (e43f2df330a1 i2c: usbio: Add ACPI device-id for NVL platforms)
+$ git merge -m Merge branch 'i2c/i2c-host' of https://git.kernel.org/pub/scm/linux/kernel/git/andi.shyti/linux.git i2c-host/i2c/i2c-host
+Already up to date.
+Merging i2c-rust/rust-i2c-next (b388d1f9a51d MAINTAINERS: add Rust I2C tree and update Igor Korotin's email)
+$ git merge -m Merge branch 'rust-i2c-next' of https://github.com/ikrtn/rust-for-linux i2c-rust/rust-i2c-next
+Auto-merging .mailmap
+Auto-merging MAINTAINERS
+Merge made by the 'ort' strategy.
+Merging i3c/i3c/next (d35a6db887ee i3c: mipi-i3c-hci: fix IBI payload length calculation for final status)
+$ git merge -m Merge branch 'i3c/next' of https://git.kernel.org/pub/scm/linux/kernel/git/i3c/linux.git i3c/i3c/next
+Already up to date.
+Merging dmi/dmi-for-next (1afafbaf749d firmware/dmi: Include product_family info to modalias)
+$ git merge -m Merge branch 'dmi-for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/jdelvare/staging.git dmi/dmi-for-next
+Already up to date.
+Merging hwmon-staging/hwmon-next (254f49634ee1 Linux 7.1-rc1)
+$ git merge -m Merge branch 'hwmon-next' of https://git.kernel.org/pub/scm/linux/kernel/git/groeck/linux-staging.git hwmon-staging/hwmon-next
+Already up to date.
+Merging jc_docs/docs-next (40a3f6c5e260 Documentation: core-api: real-time: correct spelling)
+$ git merge -m Merge branch 'docs-next' of git://git.lwn.net/linux.git jc_docs/docs-next
+Already up to date.
+Merging v4l-dvb/next (4fbeef21f538 Revert "media: cx231xx: add USB ID 2040:8360 for Hauppauge WinTV-HVR-935")
+$ git merge -m Merge branch 'next' of git://linuxtv.org/media-ci/media-pending.git v4l-dvb/next
+Already up to date.
+Merging v4l-dvb-next/master (adc218676eef Linux 6.12)
+$ git merge -m Merge branch 'master' of git://linuxtv.org/mchehab/media-next.git v4l-dvb-next/master
+Already up to date.
+Merging pm/linux-next (0baea1c4d826 Merge branch 'fixes' into linux-next)
+$ git merge -m Merge branch 'linux-next' of https://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm.git pm/linux-next
+Merge made by the 'ort' strategy.
+Merging cpufreq-arm/cpufreq/arm/linux-next (8655a4e35cda cpufreq: tegra194: remove COMPILE_TEST)
+$ git merge -m Merge branch 'cpufreq/arm/linux-next' of https://git.kernel.org/pub/scm/linux/kernel/git/vireshk/pm.git cpufreq-arm/cpufreq/arm/linux-next
+Already up to date.
+Merging cpupower/cpupower (2fd3b83cacfb cpupower: remove extern declarations in cmd functions)
+$ git merge -m Merge branch 'cpupower' of https://git.kernel.org/pub/scm/linux/kernel/git/shuah/linux.git cpupower/cpupower
+Already up to date.
+Merging devfreq/devfreq-next (cd905830ea61 PM / devfreq: tegra30-devfreq: add support for Tegra114)
+$ git merge -m Merge branch 'devfreq-next' of https://git.kernel.org/pub/scm/linux/kernel/git/chanwoo/linux.git devfreq/devfreq-next
+Already up to date.
+Merging pmdomain/next (596ca99cf04f pmdomain: qcom: rpmhpd: Add power domains for Hawi SoC)
+$ git merge -m Merge branch 'next' of https://git.kernel.org/pub/scm/linux/kernel/git/ulfh/linux-pm.git pmdomain/next
+Already up to date.
+Merging opp/opp/linux-next (3d2398f44a2d OPP: Move break out of scoped_guard in dev_pm_opp_xlate_required_opp())
+$ git merge -m Merge branch 'opp/linux-next' of https://git.kernel.org/pub/scm/linux/kernel/git/vireshk/pm.git opp/opp/linux-next
+Already up to date.
+Merging thermal/thermal/linux-next (bf746e2a41ef thermal: renesas: rzg3e: Remove stale @trim_offset kernel-doc entry)
+$ git merge -m Merge branch 'thermal/linux-next' of https://git.kernel.org/pub/scm/linux/kernel/git/thermal/linux.git thermal/thermal/linux-next
+Already up to date.
+Merging rdma/for-next (9091e3b59f2b RDMA/core: Fix user CQ creation for drivers without create_cq)
+$ git merge -m Merge branch 'for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdma.git rdma/for-next
+Already up to date.
+Merging net-next/main (254f49634ee1 Linux 7.1-rc1)
+$ git merge -m Merge branch 'main' of https://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next.git net-next/main
+Already up to date.
+$ git am -3 ../patches/0001-net-mlx5e-Fix-up-merge.patch
+Applying: net/mlx5e: Fix up merge
+Using index info to reconstruct a base tree...
+M	drivers/net/ethernet/mellanox/mlx5/core/en/xsk/setup.c
+Falling back to patching base and 3-way merge...
+No changes -- Patch already applied.
+$ git am -3 ../patches/0001-net-Fix-up-mismerge-due-to-missing-cast-enum-skb_dro.patch
+Applying: net: Fix up mismerge due to missing cast (enum skb_drop_reason)
+Using index info to reconstruct a base tree...
+M	include/net/sch_generic.h
+Falling back to patching base and 3-way merge...
+No changes -- Patch already applied.
+$ git am -3 ../patches/0001-io_uring-Fix-up-build-for-net-Slightly-simplify-net_.patch
+Applying: io_uring: Fix up build for "net: Slightly simplify net_mp_{open,close}_rxq"
+Using index info to reconstruct a base tree...
+M	io_uring/zcrx.c
+Falling back to patching base and 3-way merge...
+Auto-merging io_uring/zcrx.c
+No changes -- Patch already applied.
+Merging bpf-next/for-next (7c8d208d816d Merge branch 'introduce-arena-library-and-runtime')
+$ git merge -m Merge branch 'for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/bpf/bpf-next.git bpf-next/for-next
+Auto-merging include/linux/bpf.h
+Merge made by the 'ort' strategy.
+ Documentation/bpf/btf.rst                          |    6 +-
+ arch/s390/net/bpf_jit_comp.c                       |   37 +
+ drivers/net/ethernet/netronome/nfp/bpf/verifier.c  |    8 +-
+ fs/bpf_fs_kfuncs.c                                 |    2 +-
+ fs/verity/measure.c                                |    4 +-
+ include/linux/bpf.h                                |   63 +-
+ include/linux/bpf_verifier.h                       |   72 +-
+ include/linux/btf.h                                |    4 +-
+ include/linux/cnum.h                               |   80 +
+ include/linux/filter.h                             |    5 +-
+ include/linux/trace_events.h                       |    6 +
+ include/trace/bpf_probe.h                          |    2 -
+ include/uapi/linux/btf.h                           |   26 +-
+ kernel/bpf/Makefile                                |    2 +-
+ kernel/bpf/btf.c                                   |   29 +-
+ kernel/bpf/cnum.c                                  |  120 +
+ kernel/bpf/cnum_defs.h                             |  230 ++
+ kernel/bpf/core.c                                  |    4 +-
+ kernel/bpf/helpers.c                               |   36 +-
+ kernel/bpf/log.c                                   |   24 +-
+ kernel/bpf/states.c                                |   16 +-
+ kernel/bpf/syscall.c                               |    5 +
+ kernel/bpf/verifier.c                              | 2318 ++++++++------------
+ kernel/events/core.c                               |    9 +
+ kernel/trace/bpf_trace.c                           |   70 +-
+ kernel/trace/trace_syscalls.c                      |  108 +-
+ lib/test_bpf.c                                     |  363 ++-
+ net/bpf/test_run.c                                 |   65 +-
+ tools/bpf/bpftool/btf.c                            |   17 +-
+ tools/bpf/bpftool/btf_dumper.c                     |    4 +-
+ tools/bpf/bpftool/gen.c                            |   16 +-
+ tools/include/uapi/linux/btf.h                     |   26 +-
+ tools/lib/bpf/btf.c                                |   54 +-
+ tools/lib/bpf/btf.h                                |    2 +-
+ tools/lib/bpf/btf_dump.c                           |   24 +-
+ tools/lib/bpf/libbpf.c                             |   97 +-
+ tools/lib/bpf/relo_core.c                          |   16 +-
+ tools/testing/selftests/bpf/.gitignore             |    1 -
+ tools/testing/selftests/bpf/Makefile               |   56 +-
+ tools/testing/selftests/bpf/bpf_arena_alloc.h      |    2 +-
+ tools/testing/selftests/bpf/bpf_arena_list.h       |    2 +-
+ tools/testing/selftests/bpf/bpf_arena_strsearch.h  |    2 +-
+ tools/testing/selftests/bpf/bpf_experimental.h     |   84 +-
+ tools/testing/selftests/bpf/bpf_kfuncs.h           |    8 +-
+ tools/testing/selftests/bpf/default.profraw        |  Bin 0 -> 160 bytes
+ tools/testing/selftests/bpf/libarena/Makefile      |   94 +
+ .../bpf/{ => libarena/include}/bpf_arena_common.h  |    0
+ .../include}/bpf_arena_spin_lock.h                 |   11 +-
+ .../bpf/{ => libarena/include}/bpf_atomic.h        |    4 +-
+ .../selftests/bpf/libarena/include/bpf_may_goto.h  |   84 +
+ .../selftests/bpf/libarena/include/libarena/asan.h |  103 +
+ .../bpf/libarena/include/libarena/buddy.h          |   92 +
+ .../bpf/libarena/include/libarena/common.h         |   94 +
+ .../bpf/libarena/include/libarena/userspace.h      |  132 ++
+ .../bpf/libarena/selftests/st_asan_buddy.bpf.c     |  258 +++
+ .../bpf/libarena/selftests/st_asan_common.h        |   52 +
+ .../bpf/libarena/selftests/st_buddy.bpf.c          |  209 ++
+ .../bpf/libarena/selftests/test_progs_compat.h     |   15 +
+ .../testing/selftests/bpf/libarena/src/asan.bpf.c  |  553 +++++
+ .../testing/selftests/bpf/libarena/src/buddy.bpf.c |  903 ++++++++
+ .../selftests/bpf/libarena/src/common.bpf.c        |   52 +
+ .../selftests/bpf/prog_tests/arena_spin_lock.c     |    7 -
+ tools/testing/selftests/bpf/prog_tests/bpf_nf.c    |   22 +-
+ tools/testing/selftests/bpf/prog_tests/btf.c       |    8 +-
+ .../selftests/bpf/prog_tests/btf_dedup_split.c     |   51 +-
+ tools/testing/selftests/bpf/prog_tests/btf_dump.c  |    4 +-
+ tools/testing/selftests/bpf/prog_tests/cb_refs.c   |    2 +-
+ .../selftests/bpf/prog_tests/cgrp_local_storage.c  |   15 +-
+ .../testing/selftests/bpf/prog_tests/ctx_rewrite.c |   17 +-
+ .../testing/selftests/bpf/prog_tests/file_reader.c |   22 +-
+ .../testing/selftests/bpf/prog_tests/kfunc_call.c  |    2 +-
+ tools/testing/selftests/bpf/prog_tests/libarena.c  |   66 +
+ .../selftests/bpf/prog_tests/libarena_asan.c       |   93 +
+ .../testing/selftests/bpf/prog_tests/linked_list.c |    4 +-
+ .../testing/selftests/bpf/prog_tests/reg_bounds.c  |   90 +-
+ .../bpf/prog_tests/sleepable_tracepoints.c         |  142 ++
+ .../selftests/bpf/prog_tests/task_local_storage.c  |    1 +
+ tools/testing/selftests/bpf/progs/arena_atomics.c  |    2 +-
+ .../testing/selftests/bpf/progs/arena_spin_lock.c  |    2 +-
+ .../selftests/bpf/progs/cgrp_kfunc_failure.c       |   14 +-
+ .../selftests/bpf/progs/cgrp_ls_sleepable.c        |   18 +
+ .../selftests/bpf/progs/compute_live_registers.c   |    2 +-
+ .../testing/selftests/bpf/progs/cpumask_failure.c  |   10 +-
+ .../testing/selftests/bpf/progs/cpumask_success.c  |    2 +-
+ tools/testing/selftests/bpf/progs/dynptr_fail.c    |   22 +-
+ tools/testing/selftests/bpf/progs/dynptr_success.c |    6 +-
+ .../testing/selftests/bpf/progs/file_reader_fail.c |    4 +-
+ tools/testing/selftests/bpf/progs/irq.c            |    4 +-
+ tools/testing/selftests/bpf/progs/iters.c          |    6 +-
+ .../selftests/bpf/progs/iters_state_safety.c       |   14 +-
+ tools/testing/selftests/bpf/progs/iters_testmod.c  |    4 +-
+ .../selftests/bpf/progs/iters_testmod_seq.c        |    4 +-
+ tools/testing/selftests/bpf/progs/lpm_trie_bench.c |    2 +-
+ tools/testing/selftests/bpf/progs/map_kptr_fail.c  |    2 +-
+ .../selftests/bpf/progs/percpu_alloc_fail.c        |    4 +-
+ tools/testing/selftests/bpf/progs/rbtree_fail.c    |    6 +-
+ .../selftests/bpf/progs/refcounted_kptr_fail.c     |    2 +-
+ tools/testing/selftests/bpf/progs/stream.c         |    2 +-
+ tools/testing/selftests/bpf/progs/stream_fail.c    |    2 +-
+ .../selftests/bpf/progs/task_kfunc_failure.c       |   18 +-
+ .../selftests/bpf/progs/task_local_storage.c       |   19 +
+ tools/testing/selftests/bpf/progs/task_work_fail.c |    6 +-
+ .../testing/selftests/bpf/progs/test_bpf_nf_fail.c |    8 +-
+ .../selftests/bpf/progs/test_kfunc_dynptr_param.c  |   11 +-
+ .../bpf/progs/test_kfunc_param_nullable.c          |    2 +-
+ .../bpf/progs/test_sleepable_tracepoints.c         |  112 +
+ .../bpf/progs/test_sleepable_tracepoints_fail.c    |   18 +
+ .../testing/selftests/bpf/progs/test_tunnel_kern.c |   13 +-
+ tools/testing/selftests/bpf/progs/verifier_arena.c |    2 +-
+ .../selftests/bpf/progs/verifier_arena_globals1.c  |    2 +-
+ .../selftests/bpf/progs/verifier_arena_globals2.c  |    2 +-
+ .../selftests/bpf/progs/verifier_arena_large.c     |    2 +-
+ .../selftests/bpf/progs/verifier_bits_iter.c       |    4 +-
+ .../testing/selftests/bpf/progs/verifier_bounds.c  |   89 +-
+ .../selftests/bpf/progs/verifier_bpf_fastcall.c    |   24 +-
+ tools/testing/selftests/bpf/progs/verifier_ldsx.c  |    2 +-
+ .../selftests/bpf/progs/verifier_may_goto_1.c      |   12 +-
+ .../selftests/bpf/progs/verifier_ref_tracking.c    |    6 +-
+ tools/testing/selftests/bpf/progs/verifier_sdiv.c  |   64 +-
+ .../testing/selftests/bpf/progs/verifier_subreg.c  |    6 +-
+ .../selftests/bpf/progs/verifier_vfs_reject.c      |    8 +-
+ tools/testing/selftests/bpf/progs/wq_failures.c    |    2 +-
+ tools/testing/selftests/bpf/progs/xdp_flowtable.c  |    7 +-
+ tools/testing/selftests/bpf/progs/xdping_kern.c    |  183 --
+ tools/testing/selftests/bpf/test_loader.c          |   51 +-
+ tools/testing/selftests/bpf/test_progs.c           |    2 +-
+ tools/testing/selftests/bpf/test_progs.h           |    2 +
+ tools/testing/selftests/bpf/test_xdping.sh         |  103 -
+ tools/testing/selftests/bpf/uprobe_multi.c         |    4 +-
+ tools/testing/selftests/bpf/verifier/calls.c       |   14 +-
+ tools/testing/selftests/bpf/verifier/sleepable.c   |   17 +-
+ tools/testing/selftests/bpf/xdping.c               |  254 ---
+ tools/testing/selftests/bpf/xdping.h               |   13 -
+ 133 files changed, 5773 insertions(+), 2770 deletions(-)
+ create mode 100644 include/linux/cnum.h
+ create mode 100644 kernel/bpf/cnum.c
+ create mode 100644 kernel/bpf/cnum_defs.h
+ create mode 100644 tools/testing/selftests/bpf/default.profraw
+ create mode 100644 tools/testing/selftests/bpf/libarena/Makefile
+ rename tools/testing/selftests/bpf/{ => libarena/include}/bpf_arena_common.h (100%)
+ rename tools/testing/selftests/bpf/{progs => libarena/include}/bpf_arena_spin_lock.h (98%)
+ rename tools/testing/selftests/bpf/{ => libarena/include}/bpf_atomic.h (98%)
+ create mode 100644 tools/testing/selftests/bpf/libarena/include/bpf_may_goto.h
+ create mode 100644 tools/testing/selftests/bpf/libarena/include/libarena/asan.h
+ create mode 100644 tools/testing/selftests/bpf/libarena/include/libarena/buddy.h
+ create mode 100644 tools/testing/selftests/bpf/libarena/include/libarena/common.h
+ create mode 100644 tools/testing/selftests/bpf/libarena/include/libarena/userspace.h
+ create mode 100644 tools/testing/selftests/bpf/libarena/selftests/st_asan_buddy.bpf.c
+ create mode 100644 tools/testing/selftests/bpf/libarena/selftests/st_asan_common.h
+ create mode 100644 tools/testing/selftests/bpf/libarena/selftests/st_buddy.bpf.c
+ create mode 100644 tools/testing/selftests/bpf/libarena/selftests/test_progs_compat.h
+ create mode 100644 tools/testing/selftests/bpf/libarena/src/asan.bpf.c
+ create mode 100644 tools/testing/selftests/bpf/libarena/src/buddy.bpf.c
+ create mode 100644 tools/testing/selftests/bpf/libarena/src/common.bpf.c
+ create mode 100644 tools/testing/selftests/bpf/prog_tests/libarena.c
+ create mode 100644 tools/testing/selftests/bpf/prog_tests/libarena_asan.c
+ create mode 100644 tools/testing/selftests/bpf/prog_tests/sleepable_tracepoints.c
+ create mode 100644 tools/testing/selftests/bpf/progs/test_sleepable_tracepoints.c
+ create mode 100644 tools/testing/selftests/bpf/progs/test_sleepable_tracepoints_fail.c
+ delete mode 100644 tools/testing/selftests/bpf/progs/xdping_kern.c
+ delete mode 100755 tools/testing/selftests/bpf/test_xdping.sh
+ delete mode 100644 tools/testing/selftests/bpf/xdping.c
+ delete mode 100644 tools/testing/selftests/bpf/xdping.h
+$ git reset --hard HEAD^
+HEAD is now at 3813b0465af2 Merge branch 'linux-next' of https://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm.git
+Merging next-20260424 version of bpf-next
+$ git merge -m next-20260424/bpf-next 7c528b364bd8b2e5629aab1d84898c52c2085187
+Merge made by the 'ort' strategy.
+ tools/lib/bpf/libbpf.c                                |  9 ++++++++-
+ .../selftests/bpf/prog_tests/cgrp_local_storage.c     | 15 +++++++++++++--
+ .../selftests/bpf/prog_tests/task_local_storage.c     |  1 +
+ tools/testing/selftests/bpf/progs/cgrp_ls_sleepable.c | 18 ++++++++++++++++++
+ .../testing/selftests/bpf/progs/task_local_storage.c  | 19 +++++++++++++++++++
+ 5 files changed, 59 insertions(+), 3 deletions(-)
+$ git am -3 ../patches/0001-perf-Fixup-for-btf_vlan-API-change.patch
+Applying: perf: Fixup for btf_vlan() API change
+$ git reset HEAD^
+Unstaged changes after reset:
+M	tools/perf/builtin-trace.c
+M	tools/perf/util/btf.c
+$ git add -A .
+$ git commit -v -a --amend
+[master 5433b4bd449c] next-20260424/bpf-next
+ Date: Mon Apr 27 13:28:04 2026 +0200
+Merging ipsec-next/master (05d42dc8ab92 xfrm: Drop support for HMAC-RIPEMD-160)
+$ git merge -m Merge branch 'master' of https://git.kernel.org/pub/scm/linux/kernel/git/klassert/ipsec-next.git ipsec-next/master
+Already up to date.
+Merging mlx5-next/mlx5-next (a1bac8b70ede net/mlx5: Add icm_mng_function_id_mode cap bit)
+$ git merge -m Merge branch 'mlx5-next' of https://git.kernel.org/pub/scm/linux/kernel/git/mellanox/linux.git mlx5-next/mlx5-next
+Already up to date.
+Merging netfilter-next/main (3f3a2aefbc66 iavf: fix kernel-doc comment style in iavf_ethtool.c)
+$ git merge -m Merge branch 'main' of https://git.kernel.org/pub/scm/linux/kernel/git/netfilter/nf-next.git netfilter-next/main
+Already up to date.
+Merging ipvs-next/main (9229cb5a941c fbnic: Set Relaxed Ordering PCIe TLP attributes for DMA engines)
+$ git merge -m Merge branch 'main' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/ipvs-next.git ipvs-next/main
+Already up to date.
+Merging bluetooth/master (516a3ab44299 Bluetooth: btusb: Add Realtek RTL8922AE VID/PID 0bda/d923)
+$ git merge -m Merge branch 'master' of https://git.kernel.org/pub/scm/linux/kernel/git/bluetooth/bluetooth-next.git bluetooth/master
+Merge made by the 'ort' strategy.
+ drivers/bluetooth/Kconfig        |   2 +-
+ drivers/bluetooth/btintel.c      |  10 +-
+ drivers/bluetooth/btintel.h      |   7 ++
+ drivers/bluetooth/btintel_pcie.c | 216 +++++++++++++++++++++++++++++++++------
+ drivers/bluetooth/btintel_pcie.h |   9 +-
+ drivers/bluetooth/btmtk.c        |  38 ++++++-
+ drivers/bluetooth/btmtk.h        |   7 ++
+ drivers/bluetooth/btusb.c        |  11 ++
+ drivers/bluetooth/hci_ath.c      |   3 +
+ drivers/bluetooth/hci_bcsp.c     |   3 +
+ drivers/bluetooth/hci_h4.c       |   3 +
+ drivers/bluetooth/hci_h5.c       |   3 +
+ drivers/bluetooth/virtio_bt.c    |  39 +++++--
+ include/net/bluetooth/hci_core.h |   2 +-
+ net/bluetooth/6lowpan.c          |  25 ++++-
+ net/bluetooth/bnep/core.c        |  13 ++-
+ net/bluetooth/hci_conn.c         | 124 ++++++++++++++++++----
+ net/bluetooth/hci_event.c        |  29 +++++-
+ net/bluetooth/iso.c              |  56 +++++-----
+ net/bluetooth/l2cap_core.c       |  14 +--
+ net/bluetooth/l2cap_sock.c       |   9 ++
+ net/bluetooth/rfcomm/core.c      |   7 +-
+ net/bluetooth/sco.c              |  62 +++++++----
+ 23 files changed, 554 insertions(+), 138 deletions(-)
+Merging wireless-next/for-next (fa489a77e326 wifi: cfg80211: Explicitly include <linux/export.h> in michael-mic.c)
+$ git merge -m Merge branch 'for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/wireless/wireless-next.git wireless-next/for-next
+Already up to date.
+Merging ath-next/for-next (929298742bb5 Merge tag 'ath-next-20260408' of git://git.kernel.org/pub/scm/linux/kernel/git/ath/ath)
+$ git merge -m Merge branch 'for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/ath/ath.git ath-next/for-next
+Already up to date.
+Merging iwlwifi-next/next (709503c4a210 wifi: iwlwifi: mvm: fix race condition in PTP removal)
+$ git merge -m Merge branch 'next' of https://git.kernel.org/pub/scm/linux/kernel/git/iwlwifi/iwlwifi-next.git iwlwifi-next/next
+Merge made by the 'ort' strategy.
+ drivers/net/wireless/intel/iwlwifi/mld/ptp.c | 2 +-
+ drivers/net/wireless/intel/iwlwifi/mvm/ptp.c | 2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+Merging wpan-next/master (1dd9291eb903 ieee802154: Remove WARN_ON() in cfg802154_pernet_exit())
+$ git merge -m Merge branch 'master' of https://git.kernel.org/pub/scm/linux/kernel/git/wpan/wpan-next.git wpan-next/master
+Merge made by the 'ort' strategy.
+ net/ieee802154/core.c | 49 ++++++++++++++++++++++++++++---------------------
+ 1 file changed, 28 insertions(+), 21 deletions(-)
+Merging wpan-staging/staging (1dd9291eb903 ieee802154: Remove WARN_ON() in cfg802154_pernet_exit())
+$ git merge -m Merge branch 'staging' of https://git.kernel.org/pub/scm/linux/kernel/git/wpan/wpan-next.git wpan-staging/staging
+Already up to date.
+Merging mtd/mtd/next (b2a4fe0960ae Merge tag 'nand/for-7.1' into mtd/next)
+$ git merge -m Merge branch 'mtd/next' of https://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git mtd/mtd/next
+Already up to date.
+Merging nand/nand/next (7866ce992cf0 mtd: spinand: winbond: Declare the QE bit on W25NxxJW)
+$ git merge -m Merge branch 'nand/next' of https://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git nand/nand/next
+Already up to date.
+Merging spi-nor/spi-nor/next (cf6788aed0cd mtd: spi-nor: micron-st: Enable die erase support for MT35XU02GCBA)
+$ git merge -m Merge branch 'spi-nor/next' of https://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git spi-nor/spi-nor/next
+Already up to date.
+Merging crypto/master (8879a3c110cb crypto: af_alg - use sock_kmemdup in alg_setkey_by_key_serial)
+$ git merge -m Merge branch 'master' of https://git.kernel.org/pub/scm/linux/kernel/git/herbert/cryptodev-2.6.git crypto/master
+Already up to date.
+Merging libcrypto/libcrypto-next (254f49634ee1 Linux 7.1-rc1)
+$ git merge -m Merge branch 'libcrypto-next' of https://git.kernel.org/pub/scm/linux/kernel/git/ebiggers/linux.git libcrypto/libcrypto-next
+Already up to date.
+Merging drm/drm-next (254f49634ee1 Linux 7.1-rc1)
+$ git merge -m Merge branch 'drm-next' of https://gitlab.freedesktop.org/drm/kernel.git drm/drm-next
+Already up to date.
+Merging drm-exynos/for-linux-next (3a8660878839 Linux 6.18-rc1)
+$ git merge -m Merge branch 'for-linux-next' of https://git.kernel.org/pub/scm/linux/kernel/git/daeinki/drm-exynos.git drm-exynos/for-linux-next
+Already up to date.
+Merging drm-misc/for-linux-next (f6c73e7156b5 drm: rcar-du: Fix crash when no CMM is available)
+$ git merge -m Merge branch 'for-linux-next' of https://gitlab.freedesktop.org/drm/misc/kernel.git drm-misc/for-linux-next
+Already up to date.
+Merging amdgpu/drm-next (ba82f2b9c12a drm/amdgpu: Add node_id-to-die-name decoding for ih v7_1)
+$ git merge -m Merge branch 'drm-next' of https://gitlab.freedesktop.org/agd5f/linux.git amdgpu/drm-next
+Auto-merging drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+Auto-merging drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+Auto-merging drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+Auto-merging drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+Auto-merging drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_ism.c
+Auto-merging drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+Merge made by the 'ort' strategy.
+ Documentation/gpu/amdgpu/amdgpu-glossary.rst       |     9 +-
+ drivers/gpu/drm/amd/amdgpu/Makefile                |     2 +-
+ drivers/gpu/drm/amd/amdgpu/amdgpu.h                |     2 +
+ drivers/gpu/drm/amd/amdgpu/amdgpu_cper.c           |    12 +-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_device.c         |    22 +-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c      |    29 +
+ drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h      |     2 +
+ drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c            |     6 +-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c            |    25 +-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c            |    12 +-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h             |     6 +
+ drivers/gpu/drm/amd/amdgpu/amdgpu_imu.h            |     1 -
+ drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c            |    57 +-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c            |    71 +-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h            |    13 +
+ drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h           |     4 -
+ drivers/gpu/drm/amd/amdgpu/amdgpu_object.c         |    18 +-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c            |     9 +-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c     |     2 +-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c            |   331 +-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h            |    20 +-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c          |     3 +-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c           |   123 +-
+ drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c             |    17 +-
+ drivers/gpu/drm/amd/amdgpu/cik_sdma.c              |    13 +-
+ drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c             |     5 +
+ drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c             |     5 +
+ drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c             |     5 +
+ drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c             |    99 +-
+ drivers/gpu/drm/amd/amdgpu/gfx_v12_1_pkt.h         |   415 +-
+ drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c              |    66 +
+ drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c              |     7 +-
+ drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c              |     6 +-
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c              |     6 +-
+ drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c            |     6 +-
+ drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c             |     6 +-
+ drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c             |    13 +
+ drivers/gpu/drm/amd/amdgpu/ih_v7_0.c               |    40 +-
+ drivers/gpu/drm/amd/amdgpu/imu_v12_1.c             |    12 +-
+ drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c             |     2 +-
+ drivers/gpu/drm/amd/amdgpu/mes_v12_1.c             |    78 +-
+ drivers/gpu/drm/amd/amdgpu/nbio_v6_3_2.c           |   369 +
+ drivers/gpu/drm/amd/amdgpu/nbio_v6_3_2.h           |    31 +
+ drivers/gpu/drm/amd/amdgpu/psp_v15_0_8.c           |     1 +
+ drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c             |     8 +-
+ drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c             |     8 +-
+ drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c             |    17 +-
+ drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c           |    12 +-
+ drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c             |    11 +-
+ drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c             |    14 +-
+ drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c             |     5 +-
+ drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c             |     5 +-
+ drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c             |    12 +-
+ drivers/gpu/drm/amd/amdgpu/si_dma.c                |    12 +-
+ drivers/gpu/drm/amd/amdgpu/soc_v1_0.c              |    13 +-
+ drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c              |    10 +
+ drivers/gpu/drm/amd/amdkfd/kfd_chardev.c           |    26 +-
+ .../amd/amdkfd/kfd_device_queue_manager_v12_1.c    |    19 +-
+ drivers/gpu/drm/amd/amdkfd/kfd_migrate.c           |     3 +-
+ drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c |     6 +-
+ drivers/gpu/drm/amd/amdkfd/kfd_priv.h              |     6 +-
+ drivers/gpu/drm/amd/amdkfd/kfd_svm.c               |    11 +
+ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c  |   346 +-
+ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h  |    10 +
+ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c  |    36 +-
+ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c |    70 +-
+ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.h |     5 +-
+ .../drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c  |    60 +-
+ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_ism.c  |    26 +-
+ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c  |   244 +-
+ .../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.h  |    13 +-
+ .../drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c   |   143 +-
+ .../drm/amd/display/amdgpu_dm/amdgpu_dm_replay.h   |    28 +-
+ .../drm/amd/display/amdgpu_dm/amdgpu_dm_services.c |    27 +
+ .../gpu/drm/amd/display/dc/basics/custom_float.c   |     2 +-
+ drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c  |     2 +-
+ drivers/gpu/drm/amd/display/dc/bios/bios_parser.c  |    17 +-
+ drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c |    21 +-
+ .../gpu/drm/amd/display/dc/bios/command_table.c    |    12 +-
+ .../gpu/drm/amd/display/dc/bios/command_table2.c   |     4 +-
+ .../amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c |     6 +-
+ .../drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c  |    12 +-
+ .../amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c   |    39 +-
+ .../drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c |    13 +-
+ .../amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c   |    14 +-
+ .../amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c |    14 +-
+ .../amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c |    15 +-
+ .../amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c |    15 +-
+ .../amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c   |    43 +-
+ .../amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c   |    16 +-
+ .../amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c |    40 +-
+ .../amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c   |    22 +-
+ .../drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c   |     1 -
+ drivers/gpu/drm/amd/display/dc/core/dc.c           |   206 +-
+ .../gpu/drm/amd/display/dc/core/dc_hw_sequencer.c  |   565 +-
+ drivers/gpu/drm/amd/display/dc/core/dc_resource.c  |    66 +-
+ drivers/gpu/drm/amd/display/dc/core/dc_stream.c    |    26 +-
+ drivers/gpu/drm/amd/display/dc/core/dc_surface.c   |     2 +-
+ drivers/gpu/drm/amd/display/dc/dc.h                |    17 +-
+ drivers/gpu/drm/amd/display/dc/dc_bios_types.h     |     3 +-
+ drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c       |   137 +-
+ drivers/gpu/drm/amd/display/dc/dc_fused_io.c       |     6 +-
+ drivers/gpu/drm/amd/display/dc/dc_helper.c         |    12 +-
+ drivers/gpu/drm/amd/display/dc/dc_stream.h         |    38 +-
+ drivers/gpu/drm/amd/display/dc/dc_types.h          |    30 +
+ .../gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c |     4 +-
+ .../drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c   |    20 +-
+ .../gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c |     2 +
+ drivers/gpu/drm/amd/display/dc/dce/dce_aux.c       |     4 +-
+ .../gpu/drm/amd/display/dc/dce/dce_clock_source.c  |    24 +-
+ drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c    |     2 +-
+ drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c    |    16 +-
+ .../gpu/drm/amd/display/dc/dce/dce_panel_cntl.c    |     4 +-
+ drivers/gpu/drm/amd/display/dc/dce/dce_transform.c |     8 +-
+ drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c  |    14 +-
+ drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c      |    12 +-
+ drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c   |    23 +-
+ .../amd/display/dc/dce80/dce80_timing_generator.c  |     2 +-
+ .../gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c |     4 +-
+ .../gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.c  |    16 +-
+ .../dc/dio/dcn401/dcn401_dio_stream_encoder.c      |     2 +-
+ .../display/dc/dio/dcn42/dcn42_dio_link_encoder.h  |     2 -
+ .../dc/dio/dcn42/dcn42_dio_stream_encoder.c        |     4 +-
+ .../gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c   |     5 +-
+ .../gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c   |     7 +-
+ .../gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c   |     2 +-
+ .../gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c   |    37 +-
+ drivers/gpu/drm/amd/display/dc/dml2_0/README.md    |    31 +
+ .../drm/amd/display/dc/dml2_0/display_mode_core.c  |    14 +-
+ .../drm/amd/display/dc/dml2_0/display_mode_util.c  |    20 +-
+ .../dc/dml2_0/dml21/dml21_translation_helper.c     |    15 +-
+ .../drm/amd/display/dc/dml2_0/dml21/dml21_utils.c  |     2 +-
+ .../display/dc/dml2_0/dml21/inc/dml_top_types.h    |     1 -
+ .../dml2_0/dml21/src/dml2_core/dml2_core_factory.c |     1 -
+ .../dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_factory.c |     1 -
+ .../dml2_0/dml21/src/dml2_mcg/dml2_mcg_factory.c   |     1 -
+ .../dml2_0/dml21/src/dml2_pmo/dml2_pmo_factory.c   |     3 +-
+ .../dml21/src/dml2_top/dml2_top_interfaces.c       |     1 -
+ .../drm/amd/display/dc/dml2_0/dml2_mall_phantom.c  |   105 +-
+ .../gpu/drm/amd/display/dc/dml2_0/dml2_policy.c    |     6 +-
+ .../display/dc/dml2_0/dml2_translation_helper.c    |     4 +-
+ drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c |    40 +-
+ .../gpu/drm/amd/display/dc/dpp/dcn42/dcn42_dpp.c   |     6 +-
+ .../gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c   |    16 +-
+ drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c   |    33 +-
+ drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c       |     2 +-
+ drivers/gpu/drm/amd/display/dc/gpio/hw_generic.c   |     2 +-
+ drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.c      |     2 +-
+ drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.h      |     9 +
+ drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c       |     2 +-
+ .../drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c |    16 +-
+ .../drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c |    28 +-
+ .../drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.h |     3 +
+ .../drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c |    12 +-
+ .../drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c |    12 +-
+ .../drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c |    12 +-
+ .../gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c |     4 +-
+ .../gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c |     4 +-
+ .../gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c |     4 +-
+ .../drm/amd/display/dc/hwss/dce110/dce110_hwseq.c  |   127 +-
+ .../drm/amd/display/dc/hwss/dce120/dce120_hwseq.c  |    12 +-
+ .../drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c    |    12 +-
+ .../drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c    |    13 +-
+ .../drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c    |     8 +-
+ .../drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c    |    16 +-
+ .../drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c  |     4 +-
+ .../drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c    |     4 +-
+ .../drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c    |     6 +-
+ .../drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c  |    18 +-
+ drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h |   138 +
+ drivers/gpu/drm/amd/display/dc/inc/bw_fixed.h      |     2 +-
+ .../amd/display/dc/irq/dce110/irq_service_dce110.c |     2 +-
+ .../amd/display/dc/link/accessories/link_dp_cts.c  |    37 +-
+ .../amd/display/dc/link/hwss/link_hwss_hpo_dp.c    |     4 +-
+ .../gpu/drm/amd/display/dc/link/link_detection.c   |     4 +-
+ drivers/gpu/drm/amd/display/dc/link/link_dpms.c    |    16 +-
+ drivers/gpu/drm/amd/display/dc/link/link_factory.c |     6 +-
+ .../drm/amd/display/dc/link/protocols/link_ddc.c   |     5 +-
+ .../display/dc/link/protocols/link_dp_capability.c |     2 +-
+ .../amd/display/dc/link/protocols/link_dp_dpia.c   |     2 +-
+ .../display/dc/link/protocols/link_dp_dpia_bw.c    |    10 +-
+ .../dc/link/protocols/link_dp_irq_handler.c        |    51 +-
+ .../dc/link/protocols/link_dp_panel_replay.c       |    27 +-
+ .../dc/link/protocols/link_dp_training_8b_10b.c    |    10 +-
+ .../dc/link/protocols/link_edp_panel_control.c     |    41 +-
+ .../amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.c |     4 +-
+ .../amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.c |     4 +-
+ .../gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c |     4 +-
+ .../gpu/drm/amd/display/dc/optc/dcn42/dcn42_optc.h |     1 -
+ .../display/dc/resource/dce110/dce110_resource.c   |     4 +-
+ .../amd/display/dc/resource/dcn10/dcn10_resource.c |     4 +-
+ .../amd/display/dc/resource/dcn20/dcn20_resource.c |    24 +-
+ .../amd/display/dc/resource/dcn21/dcn21_resource.c |     2 +-
+ .../amd/display/dc/resource/dcn30/dcn30_resource.c |    14 +-
+ .../display/dc/resource/dcn301/dcn301_resource.c   |     8 +-
+ .../display/dc/resource/dcn302/dcn302_resource.c   |     4 +-
+ .../display/dc/resource/dcn303/dcn303_resource.c   |     4 +-
+ .../amd/display/dc/resource/dcn31/dcn31_resource.c |     4 +-
+ .../display/dc/resource/dcn314/dcn314_resource.c   |     4 +-
+ .../display/dc/resource/dcn315/dcn315_resource.c   |     4 +-
+ .../display/dc/resource/dcn316/dcn316_resource.c   |     4 +-
+ .../amd/display/dc/resource/dcn32/dcn32_resource.c |    20 +-
+ .../dc/resource/dcn32/dcn32_resource_helpers.c     |     2 +-
+ .../display/dc/resource/dcn321/dcn321_resource.c   |     4 +-
+ .../amd/display/dc/resource/dcn35/dcn35_resource.c |     4 +-
+ .../display/dc/resource/dcn351/dcn351_resource.c   |     4 +-
+ .../amd/display/dc/resource/dcn36/dcn36_resource.c |     4 +-
+ .../display/dc/resource/dcn401/dcn401_resource.c   |     4 +-
+ .../amd/display/dc/resource/dcn42/dcn42_resource.c |     4 +-
+ .../dcn401/dcn401_soc_and_ip_translator.c          |    42 +-
+ .../dcn42/dcn42_soc_and_ip_translator.c            |    14 +-
+ .../gpu/drm/amd/display/modules/inc/mod_power.h    |   415 +
+ .../amd/display/modules/info_packet/info_packet.c  |     2 +-
+ drivers/gpu/drm/amd/display/modules/power/Makefile |     2 +-
+ drivers/gpu/drm/amd/display/modules/power/power.c  |  3024 ++
+ .../drm/amd/display/modules/power/power_helpers.c  |    16 +-
+ drivers/gpu/drm/amd/include/amd_cper.h             |     2 +-
+ .../drm/amd/include/asic_reg/gc/gc_12_1_0_offset.h |   110 +
+ .../amd/include/asic_reg/gc/gc_12_1_0_sh_mask.h    |   455 +
+ .../drm/amd/include/asic_reg/gc/gc_12_1_1_offset.h |   149 +
+ .../amd/include/asic_reg/gc/gc_12_1_1_sh_mask.h    |   377 +
+ .../amd/include/asic_reg/nbio/nbio_6_3_2_offset.h  | 13149 +++++
+ .../amd/include/asic_reg/nbio/nbio_6_3_2_sh_mask.h | 49475 +++++++++++++++++++
+ drivers/gpu/drm/amd/pm/amdgpu_pm.c                 |     6 +-
+ drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c |     1 +
+ .../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c   |     4 +
+ .../gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c   |   215 +-
+ .../gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.h   |    34 +
+ drivers/gpu/drm/radeon/cik.c                       |     2 +-
+ drivers/gpu/drm/radeon/radeon_gem.c                |    13 +-
+ drivers/gpu/drm/radeon/radeon_ring.c               |     4 +-
+ drivers/gpu/drm/radeon/si.c                        |     2 +-
+ 232 files changed, 71302 insertions(+), 2156 deletions(-)
+ create mode 100644 drivers/gpu/drm/amd/amdgpu/nbio_v6_3_2.c
+ create mode 100644 drivers/gpu/drm/amd/amdgpu/nbio_v6_3_2.h
+ create mode 100644 drivers/gpu/drm/amd/display/dc/dml2_0/README.md
+ create mode 100644 drivers/gpu/drm/amd/display/modules/inc/mod_power.h
+ create mode 100644 drivers/gpu/drm/amd/display/modules/power/power.c
+ create mode 100755 drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_1_offset.h
+ create mode 100755 drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_1_sh_mask.h
+ create mode 100644 drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_3_2_offset.h
+ create mode 100644 drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_3_2_sh_mask.h
+$ git am -3 ../patches/0001-drm-fbdev-emulation-restore-drm_fb_helper_gem_is_fb-.patch
+Applying: drm/fbdev-emulation: restore drm_fb_helper_gem_is_fb() dummy
+$ git reset HEAD^
+Unstaged changes after reset:
+M	include/drm/drm_fb_helper.h
+$ git add -A .
+$ git commit -v -a --amend
+[master f9e9fa16e610] Merge branch 'drm-next' of https://gitlab.freedesktop.org/agd5f/linux.git
+ Date: Mon Apr 27 13:52:37 2026 +0200
+Merging drm-intel/for-linux-next (314f6179e370 drm/i915/psr: Init variable to avoid early exit from et alignment loop)
+$ git merge -m Merge branch 'for-linux-next' of https://gitlab.freedesktop.org/drm/i915/kernel.git drm-intel/for-linux-next
+Already up to date.
+Merging drm-msm/msm-next (a972d1b864e8 drm/msm: Use of_get_available_child_by_name())
+$ git merge -m Merge branch 'msm-next' of https://gitlab.freedesktop.org/drm/msm.git drm-msm/msm-next
+Already up to date.
+Merging drm-msm-lumag/msm-next-lumag (a972d1b864e8 drm/msm: Use of_get_available_child_by_name())
+$ git merge -m Merge branch 'msm-next-lumag' of https://gitlab.freedesktop.org/lumag/msm.git drm-msm-lumag/msm-next-lumag
+Already up to date.
+Merging drm-xe/drm-xe-next (4d58d7535e82 drm/xe/uapi: Reject coh_none PAT index for CPU_ADDR_MIRROR)
+$ git merge -m Merge branch 'drm-xe-next' of https://gitlab.freedesktop.org/drm/xe/kernel.git drm-xe/drm-xe-next
+Auto-merging drivers/gpu/drm/i915/display/intel_psr.c
+Auto-merging drivers/gpu/drm/xe/xe_debugfs.c
+Auto-merging drivers/gpu/drm/xe/xe_hw_engine.c
+Auto-merging drivers/gpu/drm/xe/xe_hwmon.c
+Merge made by the 'ort' strategy.
+ Documentation/gpu/drm-ras.rst                      |   8 +
+ Documentation/gpu/xe/index.rst                     |   1 +
+ Documentation/gpu/xe/xe_gt_stats.rst               |  11 +
+ Documentation/netlink/specs/drm_ras.yaml           |  13 +-
+ drivers/gpu/drm/drm_gpusvm.c                       |   5 +
+ drivers/gpu/drm/drm_ras.c                          |  43 ++-
+ drivers/gpu/drm/drm_ras_nl.c                       |  13 +
+ drivers/gpu/drm/drm_ras_nl.h                       |   2 +
+ drivers/gpu/drm/i915/display/intel_cdclk.c         |   2 +-
+ drivers/gpu/drm/i915/display/intel_ddi.c           |   2 +-
+ .../gpu/drm/i915/display/intel_display_device.c    |   2 +-
+ drivers/gpu/drm/i915/display/intel_display_power.c |   2 +-
+ drivers/gpu/drm/i915/display/intel_display_wa.c    |   2 +-
+ drivers/gpu/drm/i915/display/intel_dp_mst.c        |   2 +-
+ drivers/gpu/drm/i915/display/intel_dpll_mgr.c      |   2 +-
+ drivers/gpu/drm/i915/display/intel_fbc.c           |   2 +-
+ drivers/gpu/drm/i915/display/intel_flipq.c         |   2 +-
+ drivers/gpu/drm/i915/display/intel_hdcp.c          |   2 +-
+ drivers/gpu/drm/i915/display/intel_pmdemand.c      |   2 +-
+ drivers/gpu/drm/i915/display/intel_psr.c           |   2 +-
+ drivers/gpu/drm/i915/display/skl_universal_plane.c |   2 +-
+ drivers/gpu/drm/xe/Makefile                        |   3 +
+ drivers/gpu/drm/xe/abi/guc_klvs_abi.h              |   8 +
+ drivers/gpu/drm/xe/abi/xe_sysctrl_abi.h            |  65 ++++
+ .../gpu/drm/xe/compat-i915-headers/intel_step.h    |  13 -
+ drivers/gpu/drm/xe/display/xe_fb_pin.c             |  11 +-
+ drivers/gpu/drm/xe/regs/xe_gt_regs.h               |   7 +-
+ drivers/gpu/drm/xe/regs/xe_pcode_regs.h            |   3 +
+ drivers/gpu/drm/xe/regs/xe_sysctrl_regs.h          |  36 ++
+ .../gpu/drm/xe/tests/xe_gt_sriov_pf_config_kunit.c |  21 +-
+ drivers/gpu/drm/xe/tests/xe_migrate.c              |   3 +-
+ drivers/gpu/drm/xe/tests/xe_pci.c                  |   4 +-
+ drivers/gpu/drm/xe/xe_bo.c                         |  29 +-
+ drivers/gpu/drm/xe/xe_bo_types.h                   |   5 +-
+ drivers/gpu/drm/xe/xe_debugfs.c                    |  43 ++-
+ drivers/gpu/drm/xe/xe_dep_scheduler.h              |   5 +
+ drivers/gpu/drm/xe/xe_devcoredump.c                |   6 +-
+ drivers/gpu/drm/xe/xe_device.c                     |  64 +++-
+ drivers/gpu/drm/xe/xe_device.h                     |   9 +
+ drivers/gpu/drm/xe/xe_device_types.h               |  22 +-
+ drivers/gpu/drm/xe/xe_dma_buf.c                    |  23 +-
+ drivers/gpu/drm/xe/xe_drm_ras.c                    |  35 +-
+ drivers/gpu/drm/xe/xe_drm_ras.h                    |   4 +-
+ drivers/gpu/drm/xe/xe_eu_stall.c                   |   4 +-
+ drivers/gpu/drm/xe/xe_eu_stall.h                   |   4 +-
+ drivers/gpu/drm/xe/xe_exec_queue.c                 |   9 +-
+ drivers/gpu/drm/xe/xe_exec_queue_types.h           |   2 +-
+ drivers/gpu/drm/xe/xe_ggtt.c                       |   8 +-
+ drivers/gpu/drm/xe/xe_gsc.c                        |   2 +-
+ drivers/gpu/drm/xe/xe_gt_sriov_pf.c                |   1 +
+ drivers/gpu/drm/xe/xe_gt_sriov_pf_config.c         | 262 ++++++++++++--
+ drivers/gpu/drm/xe/xe_gt_sriov_pf_config.h         |   2 +
+ drivers/gpu/drm/xe/xe_gt_sriov_pf_policy.c         | 124 ++++---
+ drivers/gpu/drm/xe/xe_gt_sriov_pf_policy.h         |   4 +-
+ drivers/gpu/drm/xe/xe_gt_sriov_pf_types.h          |   1 -
+ drivers/gpu/drm/xe/xe_gt_stats.c                   |  41 +++
+ drivers/gpu/drm/xe/xe_gt_stats_types.h             | 118 ++++++
+ drivers/gpu/drm/xe/xe_gt_types.h                   |   4 +-
+ drivers/gpu/drm/xe/xe_guc.c                        |   8 +
+ drivers/gpu/drm/xe/xe_guc_ads.c                    |   3 +
+ drivers/gpu/drm/xe/xe_guc_capture.h                |   4 +-
+ drivers/gpu/drm/xe/xe_guc_capture_types.h          |   6 +-
+ drivers/gpu/drm/xe/xe_guc_ct.c                     |  38 +-
+ drivers/gpu/drm/xe/xe_guc_ct_types.h               |   8 +-
+ drivers/gpu/drm/xe/xe_guc_fwif.h                   |   4 +-
+ drivers/gpu/drm/xe/xe_guc_pc.c                     |  32 +-
+ drivers/gpu/drm/xe/xe_guc_relay_types.h            |   2 +-
+ drivers/gpu/drm/xe/xe_guc_submit.c                 |  40 +-
+ drivers/gpu/drm/xe/xe_guc_submit_types.h           |   2 +-
+ drivers/gpu/drm/xe/xe_hw_engine.c                  |   3 +
+ drivers/gpu/drm/xe/xe_hw_engine_types.h            |   2 +-
+ drivers/gpu/drm/xe/xe_hw_error.h                   |   4 +-
+ drivers/gpu/drm/xe/xe_hwmon.c                      |  28 +-
+ drivers/gpu/drm/xe/xe_lrc.c                        |   2 +-
+ drivers/gpu/drm/xe/xe_mem_pool.c                   | 403 +++++++++++++++++++++
+ drivers/gpu/drm/xe/xe_mem_pool.h                   |  35 ++
+ drivers/gpu/drm/xe/xe_mem_pool_types.h             |  21 ++
+ drivers/gpu/drm/xe/xe_migrate.c                    |  71 ++--
+ drivers/gpu/drm/xe/xe_migrate.h                    |   4 +-
+ drivers/gpu/drm/xe/xe_nvm.h                        |   4 +-
+ drivers/gpu/drm/xe/xe_oa_types.h                   |   8 +-
+ drivers/gpu/drm/xe/xe_pagefault_types.h            |   4 +-
+ drivers/gpu/drm/xe/xe_pat.c                        |   9 +
+ drivers/gpu/drm/xe/xe_pat.h                        |   8 +
+ drivers/gpu/drm/xe/xe_pci.c                        |  13 +-
+ drivers/gpu/drm/xe/xe_pci_sriov.c                  |   2 +
+ drivers/gpu/drm/xe/xe_pci_types.h                  |   2 +-
+ drivers/gpu/drm/xe/xe_pcode_api.h                  |   8 +-
+ drivers/gpu/drm/xe/xe_pm.c                         |   6 +
+ drivers/gpu/drm/xe/xe_pt.c                         |   3 +-
+ drivers/gpu/drm/xe/xe_pt_types.h                   |   2 +-
+ drivers/gpu/drm/xe/xe_pt_walk.h                    |  14 +-
+ drivers/gpu/drm/xe/xe_pxp.c                        |   6 +
+ drivers/gpu/drm/xe/xe_pxp.h                        |   6 +-
+ drivers/gpu/drm/xe/xe_pxp_debugfs.h                |   6 +-
+ drivers/gpu/drm/xe/xe_pxp_submit.h                 |   6 +-
+ drivers/gpu/drm/xe/xe_pxp_types.h                  |   6 +-
+ drivers/gpu/drm/xe/xe_query.c                      |   7 +
+ drivers/gpu/drm/xe/xe_reg_sr.h                     |   4 +-
+ drivers/gpu/drm/xe/xe_reg_sr_types.h               |   4 +-
+ drivers/gpu/drm/xe/xe_reg_whitelist.c              |   2 +-
+ drivers/gpu/drm/xe/xe_reg_whitelist.h              |   4 +-
+ drivers/gpu/drm/xe/xe_rtp.h                        |   4 +-
+ drivers/gpu/drm/xe/xe_rtp_helpers.h                |   6 +-
+ drivers/gpu/drm/xe/xe_rtp_types.h                  |   4 +-
+ drivers/gpu/drm/xe/xe_sriov_pf.c                   |   6 -
+ drivers/gpu/drm/xe/xe_sriov_pf_helpers.h           |   3 +-
+ drivers/gpu/drm/xe/xe_sriov_pf_provision.c         |  41 +++
+ drivers/gpu/drm/xe/xe_sriov_pf_provision.h         |   1 +
+ drivers/gpu/drm/xe/xe_sriov_pf_types.h             |   3 -
+ drivers/gpu/drm/xe/xe_sriov_vf_ccs.c               |  54 +--
+ drivers/gpu/drm/xe/xe_sriov_vf_ccs_types.h         |   5 +-
+ drivers/gpu/drm/xe/xe_step.c                       |   2 +-
+ drivers/gpu/drm/xe/xe_step.h                       |   4 +-
+ drivers/gpu/drm/xe/xe_step_types.h                 |  61 +---
+ drivers/gpu/drm/xe/xe_svm.c                        |  10 +-
+ drivers/gpu/drm/xe/xe_sysctrl.c                    | 101 ++++++
+ drivers/gpu/drm/xe/xe_sysctrl.h                    |  22 ++
+ drivers/gpu/drm/xe/xe_sysctrl_mailbox.c            | 371 +++++++++++++++++++
+ drivers/gpu/drm/xe/xe_sysctrl_mailbox.h            |  31 ++
+ drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h      |  40 ++
+ drivers/gpu/drm/xe/xe_sysctrl_types.h              |  32 ++
+ drivers/gpu/drm/xe/xe_tlb_inval.c                  |   2 +-
+ drivers/gpu/drm/xe/xe_tuning.c                     |   9 +-
+ drivers/gpu/drm/xe/xe_tuning.h                     |   4 +-
+ drivers/gpu/drm/xe/xe_uc_fw.c                      |  11 +
+ drivers/gpu/drm/xe/xe_uc_fw.h                      |   4 +
+ drivers/gpu/drm/xe/xe_uc_fw_abi.h                  |   4 +-
+ drivers/gpu/drm/xe/xe_vm.c                         |  17 +-
+ drivers/gpu/drm/xe/xe_vm_madvise.c                 |  47 +++
+ drivers/gpu/drm/xe/xe_vm_types.h                   |   3 +-
+ drivers/gpu/drm/xe/xe_vram.c                       |  22 ++
+ drivers/gpu/drm/xe/xe_vram.h                       |   2 +
+ drivers/gpu/drm/xe/xe_wa.c                         |  21 +-
+ drivers/gpu/drm/xe/xe_wa.h                         |   4 +-
+ drivers/gpu/drm/xe/xe_wa_oob.rules                 |   7 +
+ include/drm/drm_ras.h                              |  11 +
+ include/uapi/drm/drm_ras.h                         |   1 +
+ include/uapi/drm/xe_drm.h                          | 206 +++++------
+ 139 files changed, 2598 insertions(+), 559 deletions(-)
+ create mode 100644 Documentation/gpu/xe/xe_gt_stats.rst
+ create mode 100644 drivers/gpu/drm/xe/abi/xe_sysctrl_abi.h
+ delete mode 100644 drivers/gpu/drm/xe/compat-i915-headers/intel_step.h
+ create mode 100644 drivers/gpu/drm/xe/regs/xe_sysctrl_regs.h
+ create mode 100644 drivers/gpu/drm/xe/xe_mem_pool.c
+ create mode 100644 drivers/gpu/drm/xe/xe_mem_pool.h
+ create mode 100644 drivers/gpu/drm/xe/xe_mem_pool_types.h
+ create mode 100644 drivers/gpu/drm/xe/xe_sysctrl.c
+ create mode 100644 drivers/gpu/drm/xe/xe_sysctrl.h
+ create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_mailbox.c
+ create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_mailbox.h
+ create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h
+ create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_types.h
+Merging etnaviv/etnaviv/next (6bde14ba5f7e drm/etnaviv: add optional reset support)
+$ git merge -m Merge branch 'etnaviv/next' of https://git.pengutronix.de/git/lst/linux etnaviv/etnaviv/next
+Already up to date.
+Merging drm-rust/drm-rust-next (15e8bae5d930 MAINTAINERS: nova: update mailing list)
+$ git merge -m Merge branch 'drm-rust-next' of https://gitlab.freedesktop.org/drm/rust/kernel.git drm-rust/drm-rust-next
+Auto-merging MAINTAINERS
+Merge made by the 'ort' strategy.
+ MAINTAINERS                  | 6 ++----
+ rust/kernel/drm/gem/shmem.rs | 6 ++----
+ 2 files changed, 4 insertions(+), 8 deletions(-)
+Merging drm-nova/nova-next (93296e9d9528 gpu: nova-core: vbios: store reference to Device where relevant)
+$ git merge -m Merge branch 'nova-next' of https://gitlab.freedesktop.org/drm/nova.git drm-nova/nova-next
+Already up to date.
+Merging fbdev/for-next (028ef9c96e96 Linux 7.0)
+$ git merge -m Merge branch 'for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/deller/linux-fbdev.git fbdev/for-next
+Already up to date.
+$ git am -3 ../patches/0001-fix-up-for-drm-hyperv-Remove-reference-to-hyperv_fb-.patch
+Applying: fix up for "drm/hyperv: Remove reference to hyperv_fb driver"
+$ git reset HEAD^
+Unstaged changes after reset:
+M	drivers/gpu/drm/hyperv/Kconfig
+$ git add -A .
+$ git commit -v -a --amend
+[master e4624c935228] Merge branch 'drm-rust-next' of https://gitlab.freedesktop.org/drm/rust/kernel.git
+ Date: Mon Apr 27 13:52:43 2026 +0200
+Merging regmap/for-next (4b7774eeab8d regmap: sdw-mbq: Fix spelling mistake "undeferable" -> "undeferrable")
+$ git merge -m Merge branch 'for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/broonie/regmap.git regmap/for-next
+Already up to date.
+Merging sound/for-next (2724fbc90e5c Revert "ALSA: pcmtest: fix reference leak on failed device registration")
+$ git merge -m Merge branch 'for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/tiwai/sound.git sound/for-next
+Already up to date.
+Merging ieee1394/for-next (254f49634ee1 Linux 7.1-rc1)
+$ git merge -m Merge branch 'for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/ieee1394/linux1394.git ieee1394/for-next
+Already up to date.
+Merging sound-asoc/for-next (6c97f0cf368c Merge remote-tracking branch 'asoc/for-7.2' into asoc-next)
+$ git merge -m Merge branch 'for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git sound-asoc/for-next
+Merge made by the 'ort' strategy.
+ sound/soc/apple/mca.c          | 14 +++-----
+ sound/soc/atmel/atmel-classd.c | 41 ++++++++++++----------
+ sound/soc/atmel/mchp-spdifrx.c | 33 +++++++++++-------
+ sound/soc/codecs/tlv320aic3x.c |  7 ++++
+ sound/soc/fsl/fsl_micfil.c     | 79 ++++++++++++++++++++++++++++++++++++++++++
+ sound/soc/fsl/fsl_micfil.h     |  1 +
+ sound/soc/soc-ops.c            |  4 +++
+ 7 files changed, 138 insertions(+), 41 deletions(-)
+Merging modules/modules-next (663385f9155f module: Simplify warning on positive returns from module_init())
+$ git merge -m Merge branch 'modules-next' of https://git.kernel.org/pub/scm/linux/kernel/git/modules/linux.git modules/modules-next
+Already up to date.
+Merging input/next (26b760d0f814 Input: stmfts - fix formatting issues)
+$ git merge -m Merge branch 'next' of https://git.kernel.org/pub/scm/linux/kernel/git/dtor/input.git input/next
+Merge made by the 'ort' strategy.
+ .../bindings/input/touchscreen/st,stmfts.yaml      |   4 +
+ drivers/input/keyboard/lm8323.c                    |   2 +-
+ drivers/input/touchscreen/stmfts.c                 | 160 ++++++++++++++-------
+ 3 files changed, 111 insertions(+), 55 deletions(-)
+Merging block/for-next (bb4f7cb60f6b Merge branch 'block-7.1' into for-next)
+$ git merge -m Merge branch 'for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/axboe/linux.git block/for-next
+Merge made by the 'ort' strategy.
+$ git am -3 ../patches/0001-Revert-block-remove-bio_last_bvec_all.patch
+Applying: Revert "block: remove bio_last_bvec_all"
+$ git reset HEAD^
+Unstaged changes after reset:
+M	Documentation/block/biovecs.rst
+M	include/linux/bio.h
+$ git add -A .
+$ git commit -v -a --amend
+[master f778177c617f] Merge branch 'for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/axboe/linux.git
+ Date: Mon Apr 27 13:52:50 2026 +0200
+Merging device-mapper/for-next (8c0ee19db81f dm cache: fix missing return in invalidate_committed's error path)
+$ git merge -m Merge branch 'for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/device-mapper/linux-dm.git device-mapper/for-next
+Already up to date.
+Merging libata/for-next (8ebf408e7d46 ata: libata-scsi: fix requeue of deferred ATA PASS-THROUGH commands)
+$ git merge -m Merge branch 'for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/libata/linux libata/for-next
+Already up to date.
+Merging pcmcia/pcmcia-next (b3c26ea81ccc pcmcia: remove obsolete host controller drivers)
+$ git merge -m Merge branch 'pcmcia-next' of https://git.kernel.org/pub/scm/linux/kernel/git/brodo/linux.git pcmcia/pcmcia-next
+Already up to date.
+Merging mmc/next (52957cdad30f mmc: sdhci-msm: Fix the wrapped key handling)
+$ git merge -m Merge branch 'next' of https://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc.git mmc/next
+Already up to date.
+Merging mfd/for-mfd-next (caa5a5d44d8a mfd: core: Preserve OF node when ACPI handle is present)
+$ git merge -m Merge branch 'for-mfd-next' of https://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd.git mfd/for-mfd-next
+Already up to date.
+Merging backlight/for-backlight-next (04d8f3fd0b52 backlight: apple_bl: Convert to a platform driver)
+$ git merge -m Merge branch 'for-backlight-next' of https://git.kernel.org/pub/scm/linux/kernel/git/lee/backlight.git backlight/for-backlight-next
+Already up to date.
+Merging battery/for-next (98d68b74ebb9 power: supply: qcom_smbx: allow disabling charging)
+$ git merge -m Merge branch 'for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/sre/linux-power-supply.git battery/for-next
+Already up to date.
+Merging regulator/for-next (c061b678e65d Merge remote-tracking branch 'regulator/for-7.2' into regulator-next)
+$ git merge -m Merge branch 'for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/broonie/regulator.git regulator/for-next
+Merge made by the 'ort' strategy.
+ Documentation/devicetree/bindings/regulator/mt6360-regulator.yaml | 4 ++++
+ 1 file changed, 4 insertions(+)
+Merging security/next (82544d36b172 selinux: fix overlayfs mmap() and mprotect() access checks)
+$ git merge -m Merge branch 'next' of https://git.kernel.org/pub/scm/linux/kernel/git/pcmoore/lsm.git security/next
+Already up to date.
+Merging apparmor/apparmor-next (6de23f81a5e0 Linux 7.0-rc1)
+$ git merge -m Merge branch 'apparmor-next' of https://git.kernel.org/pub/scm/linux/kernel/git/jj/linux-apparmor apparmor/apparmor-next
+Already up to date.
+Merging integrity/next-integrity (82bbd447199f evm: Enforce signatures version 3 with new EVM policy 'bit 3')
+$ git merge -m Merge branch 'next-integrity' of https://git.kernel.org/pub/scm/linux/kernel/git/zohar/linux-integrity integrity/next-integrity
+Already up to date.
+Merging selinux/next (8dc51459ef70 selinux: annotate intentional data race in inode_doinit_with_dentry())
+$ git merge -m Merge branch 'next' of https://git.kernel.org/pub/scm/linux/kernel/git/pcmoore/selinux.git selinux/next
+Already up to date.
+Merging smack/next (b2faddc13112 Smack: Fix error in capability bypass)
+$ git merge -m Merge branch 'next' of https://github.com/cschaufler/smack-next smack/next
+Auto-merging security/smack/smack_lsm.c
+Merge made by the 'ort' strategy.
+ security/smack/smack_lsm.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+Merging tomoyo/master (de8a048f0f6a loop: check lo->lo_backing_file in lo_rw_aio)
+$ git merge -m Merge branch 'master' of git://git.code.sf.net/p/tomoyo/tomoyo.git tomoyo/master
+Auto-merging lib/Kconfig.debug
+Merge made by the 'ort' strategy.
+ drivers/block/loop.c      |  39 +++++++++-
+ include/linux/netdevice.h |  15 ++++
+ include/net/dst.h         |  22 +++++-
+ include/net/sock.h        |   8 +-
+ kernel/locking/lockdep.c  |   2 +
+ kernel/softirq.c          |   4 +
+ kernel/workqueue.c        |  28 +++++++
+ lib/Kconfig.debug         |   7 ++
+ net/bridge/br_nf_core.c   |   1 +
+ net/core/dev.c            | 188 ++++++++++++++++++++++++++++++++++++++++++++++
+ net/core/dst.c            |  85 +++++++++++++++++++++
+ net/core/lock_debug.c     |   1 +
+ net/socket.c              |  32 ++++++--
+ 13 files changed, 419 insertions(+), 13 deletions(-)
+Merging tpmdd-tpm/for-next-tpm (949692da7211 tpm: tpm_tis: stop transmit if retries are exhausted)
+$ git merge -m Merge branch 'for-next-tpm' of https://git.kernel.org/pub/scm/linux/kernel/git/jarkko/linux-tpmdd.git tpmdd-tpm/for-next-tpm
+Already up to date.
+Merging tpmdd-keys/for-next-keys (4fb4ce024d06 KEYS: trusted: Debugging as a feature)
+$ git merge -m Merge branch 'for-next-keys' of https://git.kernel.org/pub/scm/linux/kernel/git/jarkko/linux-tpmdd.git tpmdd-keys/for-next-keys
+Auto-merging Documentation/admin-guide/kernel-parameters.txt
+Merge made by the 'ort' strategy.
+ Documentation/admin-guide/kernel-parameters.txt | 16 +++++++++
+ include/keys/trusted-type.h                     | 21 +++++++-----
+ security/keys/Kconfig                           |  1 -
+ security/keys/trusted-keys/Kconfig              | 23 +++++++++++++
+ security/keys/trusted-keys/trusted_caam.c       |  7 ++--
+ security/keys/trusted-keys/trusted_core.c       |  6 ++++
+ security/keys/trusted-keys/trusted_tpm1.c       | 44 ++++++++++++++-----------
+ 7 files changed, 87 insertions(+), 31 deletions(-)
+Merging watchdog/master (450517fa5aae dt-bindings: watchdog: qcom-wdt: Document Glymur watchdog)
+$ git merge -m Merge branch 'master' of git://www.linux-watchdog.org/linux-watchdog-next.git watchdog/master
+Already up to date.
+Merging iommu/next (f8d5e7066d84 Merge branches 'fixes', 'arm/smmu/updates', 'arm/smmu/bindings', 'riscv', 'intel/vt-d', 'amd/amd-vi' and 'core' into next)
+$ git merge -m Merge branch 'next' of https://git.kernel.org/pub/scm/linux/kernel/git/iommu/linux.git iommu/next
+Already up to date.
+Merging audit/next (360160f75592 audit: handle unknown status requests in audit_receive_msg())
+$ git merge -m Merge branch 'next' of https://git.kernel.org/pub/scm/linux/kernel/git/pcmoore/audit.git audit/next
+Already up to date.
+Merging devicetree/for-next (a74c2e55ab66 dt-bindings: display: panel: panel-simple: Add lg,sw49410 compatible)
+$ git merge -m Merge branch 'for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git devicetree/for-next
+Already up to date.
+Merging dt-krzk/for-next (6de23f81a5e0 Linux 7.0-rc1)
+$ git merge -m Merge branch 'for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-dt.git dt-krzk/for-next
+Already up to date.
+Merging mailbox/for-next (6e937f4e769e mailbox: mailbox-test: make data_ready a per-instance variable)
+$ git merge -m Merge branch 'for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/jassibrar/mailbox.git mailbox/for-next
+Merge made by the 'ort' strategy.
+ .../devicetree/bindings/mailbox/qcom-ipcc.yaml     |  1 +
+ drivers/mailbox/cix-mailbox.c                      |  6 +-
+ drivers/mailbox/exynos-mailbox.c                   |  4 --
+ drivers/mailbox/hi3660-mailbox.c                   |  2 -
+ drivers/mailbox/hi6220-mailbox.c                   | 14 ++--
+ drivers/mailbox/imx-mailbox.c                      |  4 +-
+ drivers/mailbox/mailbox-sti.c                      |  2 -
+ drivers/mailbox/mailbox-test.c                     | 80 +++++++++++++---------
+ drivers/mailbox/mailbox.c                          | 67 +++++++++++-------
+ drivers/mailbox/mailbox.h                          | 12 ----
+ drivers/mailbox/mtk-cmdq-mailbox.c                 | 10 +--
+ drivers/mailbox/mtk-vcp-mailbox.c                  |  2 +-
+ drivers/mailbox/omap-mailbox.c                     |  4 +-
+ drivers/mailbox/pcc.c                              |  2 -
+ drivers/mailbox/rockchip-mailbox.c                 |  9 +--
+ drivers/mailbox/tegra-hsp.c                        |  6 +-
+ include/linux/mailbox_client.h                     |  1 +
+ include/linux/mailbox_controller.h                 | 17 +++--
+ 18 files changed, 124 insertions(+), 119 deletions(-)
+ delete mode 100644 drivers/mailbox/mailbox.h
+Merging spi/for-next (fc46965cca20 Merge remote-tracking branch 'spi/for-7.2' into spi-next)
+$ git merge -m Merge branch 'for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git spi/for-next
+Merge made by the 'ort' strategy.
+ drivers/spi/spi-mpc52xx.c | 26 ++++++++++++++++----------
+ 1 file changed, 16 insertions(+), 10 deletions(-)
+Merging tip/master (a2b8bd083106 Merge branch into tip/master: 'timers/clocksource')
+$ git merge -m Merge branch 'master' of https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git tip/master
+Merge made by the 'ort' strategy.
+ .../devicetree/bindings/timer/fsl,imxgpt.yaml      |  1 +
+ drivers/clocksource/mmio.c                         | 11 +++++++---
+ drivers/clocksource/timer-of.c                     | 24 ++++++++++++----------
+ drivers/clocksource/timer-of.h                     |  5 ++---
+ drivers/clocksource/timer-rtl-otto.c               |  2 +-
+ drivers/clocksource/timer-sun5i.c                  |  3 +++
+ 6 files changed, 28 insertions(+), 18 deletions(-)
+Merging kexec/kexec-next (028ef9c96e96 Linux 7.0)
+$ git merge -m Merge branch 'kexec-next' of https://git.kernel.org/pub/scm/linux/kernel/git/liveupdate/linux.git kexec/kexec-next
+Already up to date.
+Merging liveupdate/next (028ef9c96e96 Linux 7.0)
+$ git merge -m Merge branch 'next' of https://git.kernel.org/pub/scm/linux/kernel/git/liveupdate/linux.git liveupdate/next
+Already up to date.
+Merging clockevents/timers/drivers/next (0712d2137dd8 dt-bindings: timer: Add StarFive JHB100 clint)
+$ git merge -m Merge branch 'timers/drivers/next' of https://git.kernel.org/pub/scm/linux/kernel/git/daniel.lezcano/linux.git clockevents/timers/drivers/next
+Auto-merging Documentation/devicetree/bindings/timer/sifive,clint.yaml
+Merge made by the 'ort' strategy.
+ .../devicetree/bindings/timer/renesas,rz-mtu3.yaml | 26 +++++++++++++++++-----
+ .../devicetree/bindings/timer/sifive,clint.yaml    | 17 +-------------
+ 2 files changed, 21 insertions(+), 22 deletions(-)
+Merging edac/edac-for-next (3d63012017f1 Merge ras/edac-urgent into for-next)
+$ git merge -m Merge branch 'edac-for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/ras/ras.git edac/edac-for-next
+Merge made by the 'ort' strategy.
+Merging ftrace/for-next (0b6bc3dbe632 Merge tag 'trace-latency-v7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/trace/linux-trace)
+$ git merge -m Merge branch 'for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/trace/linux-trace.git ftrace/for-next
+Already up to date.
+Merging rcu/next (ed062c41dfda Merge branch 'rcu-nocb.20260123a')
+$ git merge -m Merge branch 'next' of https://git.kernel.org/pub/scm/linux/kernel/git/rcu/linux rcu/next
+Already up to date.
+Merging paulmck/non-rcu/next (48f7a50c027d stop_machine: Fix the documentation for a NULL cpus argument)
+$ git merge -m Merge branch 'non-rcu/next' of https://git.kernel.org/pub/scm/linux/kernel/git/paulmck/linux-rcu.git paulmck/non-rcu/next
+Already up to date.
+Merging kvm/next (6b802031877a Merge tag 'kvm-s390-next-7.1-1' of https://git.kernel.org/pub/scm/linux/kernel/git/kvms390/linux into HEAD)
+$ git merge -m Merge branch 'next' of git://git.kernel.org/pub/scm/virt/kvm/kvm.git kvm/next
+Already up to date.
+Merging kvm-arm/next (94b4ae79ebb4 Merge branch kvm-arm64/misc-7.1 into kvmarm-master/next)
+$ git merge -m Merge branch 'next' of https://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm.git kvm-arm/next
+Already up to date.
+Merging kvms390/next (9b8e8aad5896 KVM: s390: ucontrol: Fix memslot handling)
+$ git merge -m Merge branch 'next' of https://git.kernel.org/pub/scm/linux/kernel/git/kvms390/linux.git kvms390/next
+Already up to date.
+Merging kvm-ppc/topic/ppc-kvm (f338e7738378 Linux 7.0-rc4)
+$ git merge -m Merge branch 'topic/ppc-kvm' of https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git kvm-ppc/topic/ppc-kvm
+Already up to date.
+Merging kvm-riscv/riscv_kvm_next (ddbf9c76c402 RISC-V: KVM: Fix shift-out-of-bounds in make_xfence_request())
+$ git merge -m Merge branch 'riscv_kvm_next' of https://github.com/kvm-riscv/linux.git kvm-riscv/riscv_kvm_next
+Already up to date.
+Merging kvm-x86/next (85f871f6ba46 Merge branch 'selftests_kernel_types')
+$ git merge -m Merge branch 'next' of https://github.com/kvm-x86/linux.git kvm-x86/next
+Auto-merging tools/testing/selftests/kvm/arm64/set_id_regs.c
+Merge made by the 'ort' strategy.
+ .../selftests/kvm/access_tracking_perf_test.c      |  44 +--
+ tools/testing/selftests/kvm/arch_timer.c           |   6 +-
+ .../testing/selftests/kvm/arm64/aarch32_id_regs.c  |  14 +-
+ tools/testing/selftests/kvm/arm64/arch_timer.c     |   8 +-
+ .../selftests/kvm/arm64/arch_timer_edge_cases.c    | 161 +++++----
+ .../testing/selftests/kvm/arm64/debug-exceptions.c |  72 ++--
+ tools/testing/selftests/kvm/arm64/hypercalls.c     |  24 +-
+ tools/testing/selftests/kvm/arm64/idreg-idst.c     |   4 +-
+ tools/testing/selftests/kvm/arm64/no-vgic.c        |   8 +-
+ .../testing/selftests/kvm/arm64/page_fault_test.c  |  82 ++---
+ tools/testing/selftests/kvm/arm64/psci_test.c      |  26 +-
+ tools/testing/selftests/kvm/arm64/sea_to_user.c    |  41 ++-
+ tools/testing/selftests/kvm/arm64/set_id_regs.c    |  70 ++--
+ tools/testing/selftests/kvm/arm64/smccc_filter.c   |  10 +-
+ tools/testing/selftests/kvm/arm64/vgic_init.c      |  56 +--
+ tools/testing/selftests/kvm/arm64/vgic_irq.c       | 137 ++++----
+ .../testing/selftests/kvm/arm64/vgic_lpi_stress.c  |  20 +-
+ tools/testing/selftests/kvm/arm64/vgic_v5.c        |  10 +-
+ .../selftests/kvm/arm64/vpmu_counter_access.c      |  56 +--
+ tools/testing/selftests/kvm/coalesced_io_test.c    |  38 +--
+ tools/testing/selftests/kvm/demand_paging_test.c   |  10 +-
+ tools/testing/selftests/kvm/dirty_log_perf_test.c  |  14 +-
+ tools/testing/selftests/kvm/dirty_log_test.c       |  82 ++---
+ tools/testing/selftests/kvm/get-reg-list.c         |   2 +-
+ tools/testing/selftests/kvm/guest_memfd_test.c     |  18 +-
+ tools/testing/selftests/kvm/guest_print_test.c     |  22 +-
+ .../testing/selftests/kvm/hardware_disable_test.c  |   6 +-
+ .../selftests/kvm/include/arm64/arch_timer.h       |  30 +-
+ tools/testing/selftests/kvm/include/arm64/delay.h  |   4 +-
+ tools/testing/selftests/kvm/include/arm64/gic.h    |   8 +-
+ .../selftests/kvm/include/arm64/gic_v3_its.h       |   7 +-
+ .../selftests/kvm/include/arm64/processor.h        |  22 +-
+ tools/testing/selftests/kvm/include/arm64/ucall.h  |   4 +-
+ tools/testing/selftests/kvm/include/arm64/vgic.h   |  22 +-
+ tools/testing/selftests/kvm/include/kvm_util.h     | 344 +++++++++----------
+ .../testing/selftests/kvm/include/kvm_util_types.h |   8 +-
+ .../selftests/kvm/include/loongarch/arch_timer.h   |   4 +-
+ .../selftests/kvm/include/loongarch/ucall.h        |   4 +-
+ tools/testing/selftests/kvm/include/memstress.h    |  30 +-
+ .../selftests/kvm/include/riscv/arch_timer.h       |  22 +-
+ .../selftests/kvm/include/riscv/processor.h        |   9 +-
+ tools/testing/selftests/kvm/include/riscv/ucall.h  |   4 +-
+ .../kvm/include/s390/diag318_test_handler.h        |   2 +-
+ .../testing/selftests/kvm/include/s390/facility.h  |   4 +-
+ tools/testing/selftests/kvm/include/s390/ucall.h   |   4 +-
+ tools/testing/selftests/kvm/include/sparsebit.h    |   6 +-
+ tools/testing/selftests/kvm/include/test_util.h    |  40 +--
+ tools/testing/selftests/kvm/include/timer_test.h   |  18 +-
+ tools/testing/selftests/kvm/include/ucall_common.h |  22 +-
+ .../selftests/kvm/include/userfaultfd_util.h       |   6 +-
+ tools/testing/selftests/kvm/include/x86/apic.h     |  22 +-
+ tools/testing/selftests/kvm/include/x86/evmcs.h    |  22 +-
+ tools/testing/selftests/kvm/include/x86/hyperv.h   |  28 +-
+ .../selftests/kvm/include/x86/kvm_util_arch.h      |  36 +-
+ tools/testing/selftests/kvm/include/x86/pmu.h      |   9 +-
+ .../testing/selftests/kvm/include/x86/processor.h  | 292 ++++++++--------
+ tools/testing/selftests/kvm/include/x86/sev.h      |  20 +-
+ tools/testing/selftests/kvm/include/x86/smm.h      |   3 +-
+ tools/testing/selftests/kvm/include/x86/svm_util.h |  12 +-
+ tools/testing/selftests/kvm/include/x86/ucall.h    |   2 +-
+ tools/testing/selftests/kvm/include/x86/vmx.h      |  70 ++--
+ tools/testing/selftests/kvm/kvm_page_table_test.c  |  54 +--
+ tools/testing/selftests/kvm/lib/arm64/gic.c        |   6 +-
+ .../testing/selftests/kvm/lib/arm64/gic_private.h  |  26 +-
+ tools/testing/selftests/kvm/lib/arm64/gic_v3.c     |  90 ++---
+ tools/testing/selftests/kvm/lib/arm64/gic_v3_its.c |  11 +-
+ tools/testing/selftests/kvm/lib/arm64/processor.c  | 163 +++++----
+ tools/testing/selftests/kvm/lib/arm64/ucall.c      |  12 +-
+ tools/testing/selftests/kvm/lib/arm64/vgic.c       |  40 +--
+ tools/testing/selftests/kvm/lib/elf.c              |  17 +-
+ tools/testing/selftests/kvm/lib/guest_modes.c      |   2 +-
+ tools/testing/selftests/kvm/lib/guest_sprintf.c    |  18 +-
+ tools/testing/selftests/kvm/lib/kvm_util.c         | 377 +++++++++------------
+ .../selftests/kvm/lib/loongarch/processor.c        | 110 +++---
+ tools/testing/selftests/kvm/lib/loongarch/ucall.c  |  12 +-
+ tools/testing/selftests/kvm/lib/memstress.c        |  38 +--
+ tools/testing/selftests/kvm/lib/riscv/processor.c  |  91 +++--
+ .../selftests/kvm/lib/s390/diag318_test_handler.c  |  12 +-
+ tools/testing/selftests/kvm/lib/s390/facility.c    |   2 +-
+ tools/testing/selftests/kvm/lib/s390/processor.c   |  65 ++--
+ tools/testing/selftests/kvm/lib/sparsebit.c        |  18 +-
+ tools/testing/selftests/kvm/lib/test_util.c        |  30 +-
+ tools/testing/selftests/kvm/lib/ucall_common.c     |  34 +-
+ tools/testing/selftests/kvm/lib/userfaultfd_util.c |  14 +-
+ tools/testing/selftests/kvm/lib/x86/apic.c         |   2 +-
+ tools/testing/selftests/kvm/lib/x86/hyperv.c       |  14 +-
+ tools/testing/selftests/kvm/lib/x86/memstress.c    |  14 +-
+ tools/testing/selftests/kvm/lib/x86/pmu.c          |   8 +-
+ tools/testing/selftests/kvm/lib/x86/processor.c    | 292 ++++++++--------
+ tools/testing/selftests/kvm/lib/x86/sev.c          |  20 +-
+ tools/testing/selftests/kvm/lib/x86/svm.c          |  16 +-
+ tools/testing/selftests/kvm/lib/x86/ucall.c        |   4 +-
+ tools/testing/selftests/kvm/lib/x86/vmx.c          |  44 +--
+ tools/testing/selftests/kvm/loongarch/arch_timer.c |  28 +-
+ tools/testing/selftests/kvm/loongarch/pmu_test.c   |  10 +-
+ .../kvm/memslot_modification_stress_test.c         |  10 +-
+ tools/testing/selftests/kvm/memslot_perf_test.c    | 164 ++++-----
+ tools/testing/selftests/kvm/mmu_stress_test.c      |  28 +-
+ .../testing/selftests/kvm/pre_fault_memory_test.c  |  12 +-
+ tools/testing/selftests/kvm/riscv/arch_timer.c     |   8 +-
+ tools/testing/selftests/kvm/riscv/ebreak_test.c    |   6 +-
+ tools/testing/selftests/kvm/riscv/get-reg-list.c   |   4 +-
+ tools/testing/selftests/kvm/riscv/sbi_pmu_test.c   |   8 +-
+ tools/testing/selftests/kvm/s390/debug_test.c      |   8 +-
+ tools/testing/selftests/kvm/s390/irq_routing.c     |   2 +-
+ tools/testing/selftests/kvm/s390/memop.c           |  94 ++---
+ tools/testing/selftests/kvm/s390/resets.c          |   6 +-
+ .../selftests/kvm/s390/shared_zeropage_test.c      |   2 +-
+ tools/testing/selftests/kvm/s390/tprot.c           |  24 +-
+ tools/testing/selftests/kvm/s390/ucontrol_test.c   |   8 +-
+ .../testing/selftests/kvm/set_memory_region_test.c |  40 +--
+ tools/testing/selftests/kvm/steal_time.c           |  74 ++--
+ .../selftests/kvm/system_counter_offset_test.c     |  12 +-
+ tools/testing/selftests/kvm/x86/amx_test.c         |  14 +-
+ tools/testing/selftests/kvm/x86/aperfmperf_test.c  |  16 +-
+ .../selftests/kvm/x86/apic_bus_clock_test.c        |  24 +-
+ tools/testing/selftests/kvm/x86/cpuid_test.c       |   6 +-
+ tools/testing/selftests/kvm/x86/debug_regs.c       |   4 +-
+ .../kvm/x86/dirty_log_page_splitting_test.c        |  16 +-
+ .../selftests/kvm/x86/evmcs_smm_controls_test.c    |   6 +-
+ tools/testing/selftests/kvm/x86/fastops_test.c     |  52 +--
+ .../testing/selftests/kvm/x86/feature_msrs_test.c  |  12 +-
+ .../testing/selftests/kvm/x86/fix_hypercall_test.c |  20 +-
+ tools/testing/selftests/kvm/x86/flds_emulation.h   |   6 +-
+ tools/testing/selftests/kvm/x86/hwcr_msr_test.c    |  10 +-
+ tools/testing/selftests/kvm/x86/hyperv_clock.c     |   6 +-
+ tools/testing/selftests/kvm/x86/hyperv_evmcs.c     |  10 +-
+ .../selftests/kvm/x86/hyperv_extended_hypercalls.c |  20 +-
+ tools/testing/selftests/kvm/x86/hyperv_features.c  |  26 +-
+ tools/testing/selftests/kvm/x86/hyperv_ipi.c       |  12 +-
+ tools/testing/selftests/kvm/x86/hyperv_svm_test.c  |  10 +-
+ tools/testing/selftests/kvm/x86/hyperv_tlb_flush.c |  36 +-
+ tools/testing/selftests/kvm/x86/kvm_buslock_test.c |   2 +-
+ tools/testing/selftests/kvm/x86/kvm_clock_test.c   |  14 +-
+ tools/testing/selftests/kvm/x86/kvm_pv_test.c      |  10 +-
+ .../testing/selftests/kvm/x86/monitor_mwait_test.c |   2 +-
+ .../selftests/kvm/x86/nested_close_kvm_test.c      |   2 +-
+ .../selftests/kvm/x86/nested_dirty_log_test.c      |  10 +-
+ .../selftests/kvm/x86/nested_emulation_test.c      |  20 +-
+ .../selftests/kvm/x86/nested_exceptions_test.c     |   6 +-
+ .../selftests/kvm/x86/nested_invalid_cr3_test.c    |   2 +-
+ .../selftests/kvm/x86/nested_set_state_test.c      |   4 +-
+ .../selftests/kvm/x86/nested_tsc_adjust_test.c     |  12 +-
+ .../selftests/kvm/x86/nested_tsc_scaling_test.c    |  24 +-
+ .../selftests/kvm/x86/nested_vmsave_vmload_test.c  |   2 +-
+ .../testing/selftests/kvm/x86/nx_huge_pages_test.c |  18 +-
+ .../testing/selftests/kvm/x86/platform_info_test.c |   6 +-
+ .../testing/selftests/kvm/x86/pmu_counters_test.c  | 109 +++---
+ .../selftests/kvm/x86/pmu_event_filter_test.c      | 102 +++---
+ .../kvm/x86/private_mem_conversions_test.c         |  78 ++---
+ .../selftests/kvm/x86/private_mem_kvm_exits_test.c |  14 +-
+ tools/testing/selftests/kvm/x86/set_boot_cpu_id.c  |   6 +-
+ tools/testing/selftests/kvm/x86/set_sregs_test.c   |   6 +-
+ tools/testing/selftests/kvm/x86/sev_init2_tests.c  |   6 +-
+ tools/testing/selftests/kvm/x86/sev_smoke_test.c   |  22 +-
+ .../kvm/x86/smaller_maxphyaddr_emulation_test.c    |   8 +-
+ tools/testing/selftests/kvm/x86/smm_test.c         |   8 +-
+ tools/testing/selftests/kvm/x86/state_test.c       |  14 +-
+ tools/testing/selftests/kvm/x86/svm_int_ctl_test.c |   2 +-
+ .../selftests/kvm/x86/svm_lbr_nested_state.c       |   2 +-
+ .../selftests/kvm/x86/svm_nested_clear_efer_svme.c |   2 +-
+ .../selftests/kvm/x86/svm_nested_shutdown_test.c   |   2 +-
+ .../kvm/x86/svm_nested_soft_inject_test.c          |  10 +-
+ .../selftests/kvm/x86/svm_nested_vmcb12_gpa.c      |  14 +-
+ tools/testing/selftests/kvm/x86/svm_vmcall_test.c  |   2 +-
+ tools/testing/selftests/kvm/x86/sync_regs_test.c   |   2 +-
+ .../selftests/kvm/x86/triple_fault_event_test.c    |   4 +-
+ tools/testing/selftests/kvm/x86/tsc_msrs_test.c    |   2 +-
+ tools/testing/selftests/kvm/x86/tsc_scaling_sync.c |   4 +-
+ .../selftests/kvm/x86/ucna_injection_test.c        |  45 +--
+ .../testing/selftests/kvm/x86/userspace_io_test.c  |   4 +-
+ .../selftests/kvm/x86/userspace_msr_exit_test.c    |  58 ++--
+ .../selftests/kvm/x86/vmx_apic_access_test.c       |   4 +-
+ .../selftests/kvm/x86/vmx_apicv_updates_test.c     |   4 +-
+ .../kvm/x86/vmx_invalid_nested_guest_state.c       |   2 +-
+ tools/testing/selftests/kvm/x86/vmx_msrs_test.c    |  22 +-
+ .../selftests/kvm/x86/vmx_nested_la57_state_test.c |   4 +-
+ .../testing/selftests/kvm/x86/vmx_pmu_caps_test.c  |  12 +-
+ .../selftests/kvm/x86/vmx_preemption_timer_test.c  |   2 +-
+ tools/testing/selftests/kvm/x86/xapic_ipi_test.c   |  64 ++--
+ tools/testing/selftests/kvm/x86/xapic_state_test.c |  20 +-
+ tools/testing/selftests/kvm/x86/xapic_tpr_test.c   |  24 +-
+ tools/testing/selftests/kvm/x86/xcr0_cpuid_test.c  |   8 +-
+ tools/testing/selftests/kvm/x86/xen_shinfo_test.c  |  22 +-
+ tools/testing/selftests/kvm/x86/xss_msr_test.c     |   2 +-
+ 185 files changed, 2715 insertions(+), 2826 deletions(-)
+Merging xen-tip/linux-next (3f100dd61ad4 xen/grant-table: guard gnttab_suspend/resume with CONFIG_HIBERNATE_CALLBACKS)
+$ git merge -m Merge branch 'linux-next' of https://git.kernel.org/pub/scm/linux/kernel/git/xen/tip.git xen-tip/linux-next
+Already up to date.
+Merging percpu/for-next (8f0b4cce4481 Linux 6.19-rc1)
+$ git merge -m Merge branch 'for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/dennis/percpu.git percpu/for-next
+Already up to date.
+Merging workqueues/for-next (d730905bc3c0 Merge tag 'mips_7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux)
+$ git merge -m Merge branch 'for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/tj/wq.git workqueues/for-next
+Already up to date.
+Merging sched-ext/for-next (bd9ee45f29be Merge branch 'for-7.2' into for-next)
+$ git merge -m Merge branch 'for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/tj/sched_ext.git sched-ext/for-next
+Auto-merging kernel/sched/ext.c
+Merge made by the 'ort' strategy.
+ Documentation/scheduler/sched-ext.rst              |   7 +-
+ include/linux/rhashtable-types.h                   |   5 +
+ include/linux/rhashtable.h                         |   8 +-
+ include/linux/sched/ext.h                          |   9 +
+ kernel/sched/ext.c                                 | 542 ++++++++++++++-----
+ kernel/sched/ext_idle.c                            |  20 +-
+ kernel/sched/ext_idle.h                            |   1 +
+ kernel/sched/ext_internal.h                        |  22 +-
+ lib/rhashtable.c                                   |  36 +-
+ tools/sched_ext/README.md                          |   6 +-
+ tools/sched_ext/include/scx/common.bpf.h           |   5 +
+ tools/sched_ext/include/scx/compat.bpf.h           |   6 +-
+ tools/sched_ext/include/scx/compat.h               |  23 +-
+ tools/sched_ext/scx_central.bpf.c                  |  10 +-
+ tools/sched_ext/scx_cpu0.bpf.c                     |   2 -
+ tools/sched_ext/scx_cpu0.c                         |   2 -
+ tools/sched_ext/scx_flatcg.c                       |  12 +-
+ tools/sched_ext/scx_qmap.bpf.c                     | 583 +++++++++++++--------
+ tools/sched_ext/scx_qmap.c                         |  58 +-
+ tools/sched_ext/scx_qmap.h                         |  73 +++
+ tools/testing/selftests/sched_ext/Makefile         |   1 +
+ .../selftests/sched_ext/non_scx_kfunc_deny.bpf.c   |  39 ++
+ .../selftests/sched_ext/non_scx_kfunc_deny.c       |  47 ++
+ 23 files changed, 1094 insertions(+), 423 deletions(-)
+ create mode 100644 tools/sched_ext/scx_qmap.h
+ create mode 100644 tools/testing/selftests/sched_ext/non_scx_kfunc_deny.bpf.c
+ create mode 100644 tools/testing/selftests/sched_ext/non_scx_kfunc_deny.c
+Merging drivers-x86/for-next (254f49634ee1 Linux 7.1-rc1)
+$ git merge -m Merge branch 'for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/pdx86/platform-drivers-x86.git drivers-x86/for-next
+Already up to date.
+$ git am -3 ../patches/0001-hid-Fix-up-mismerge.patch
+Applying: hid: Fix up mismerge
+$ git reset HEAD^
+Unstaged changes after reset:
+M	drivers/hid/hid-asus.c
+$ git add -A .
+$ git commit -v -a --amend
+[master b6906a84fd70] Merge branch 'for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/tj/sched_ext.git
+ Date: Mon Apr 27 13:53:14 2026 +0200
+Merging chrome-platform/for-next (0fd0fea2525d platform/chrome: cros_kbd_led_backlight: Drop CONFIG_MFD_CROS_EC_DEV ifdeffery)
+$ git merge -m Merge branch 'for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/chrome-platform/linux.git chrome-platform/for-next
+Merge made by the 'ort' strategy.
+ drivers/platform/chrome/cros_ec_sensorhub.c      |  6 ++++-
+ drivers/platform/chrome/cros_ec_sysfs.c          |  5 +++--
+ drivers/platform/chrome/cros_kbd_led_backlight.c | 28 ++++++------------------
+ include/linux/platform_data/cros_ec_proto.h      |  2 ++
+ 4 files changed, 17 insertions(+), 24 deletions(-)
+Merging chrome-platform-firmware/for-firmware-next (254f49634ee1 Linux 7.1-rc1)
+$ git merge -m Merge branch 'for-firmware-next' of https://git.kernel.org/pub/scm/linux/kernel/git/chrome-platform/linux.git chrome-platform-firmware/for-firmware-next
+Already up to date.
+Merging hsi/for-next (df5ead915b19 HSI: omap_ssi_port: remove depends on ARM)
+$ git merge -m Merge branch 'for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/sre/linux-hsi.git hsi/for-next
+Already up to date.
+Merging leds-lj/for-leds-next (7a43ccf85dfe leds: class: Make led_remove_lookup() NULL-aware)
+$ git merge -m Merge branch 'for-leds-next' of https://git.kernel.org/pub/scm/linux/kernel/git/lee/leds.git leds-lj/for-leds-next
+Already up to date.
+Merging ipmi/for-next (7c4b10c9c087 ipmi:kcs: Reduce the number of retries)
+$ git merge -m Merge branch 'for-next' of https://github.com/cminyard/linux-ipmi.git ipmi/for-next
+Merge made by the 'ort' strategy.
+ drivers/char/ipmi/ipmi_kcs_sm.c  |  2 +-
+ drivers/char/ipmi/ipmi_si_intf.c | 39 ++++++++++++++++++++++++++++++++++-----
+ drivers/char/ipmi/ipmi_ssif.c    | 16 ++++++++++++++++
+ 3 files changed, 51 insertions(+), 6 deletions(-)
+Merging driver-core/driver-core-next (254f49634ee1 Linux 7.1-rc1)
+$ git merge -m Merge branch 'driver-core-next' of https://git.kernel.org/pub/scm/linux/kernel/git/driver-core/driver-core.git driver-core/driver-core-next
+Already up to date.
+Merging usb/usb-next (27d128c1cff6 Merge tag 'trace-ring-buffer-v7.1-3' of git://git.kernel.org/pub/scm/linux/kernel/git/trace/linux-trace)
+$ git merge -m Merge branch 'usb-next' of https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/usb.git usb/usb-next
+Already up to date.
+Merging thunderbolt/next (babaad95670d thunderbolt: debugfs: Don't stop reading SB registers if just one fails)
+$ git merge -m Merge branch 'next' of https://git.kernel.org/pub/scm/linux/kernel/git/westeri/thunderbolt.git thunderbolt/next
+Merge made by the 'ort' strategy.
+ drivers/thunderbolt/debugfs.c | 6 ++++--
+ 1 file changed, 4 insertions(+), 2 deletions(-)
+Merging usb-serial/usb-next (37d9c4c055c3 USB: serial: iuu_phoenix: fix iuutool author name)
+$ git merge -m Merge branch 'usb-next' of https://git.kernel.org/pub/scm/linux/kernel/git/johan/usb-serial.git usb-serial/usb-next
+Already up to date.
+Merging tty/tty-next (27d128c1cff6 Merge tag 'trace-ring-buffer-v7.1-3' of git://git.kernel.org/pub/scm/linux/kernel/git/trace/linux-trace)
+$ git merge -m Merge branch 'tty-next' of https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/tty.git tty/tty-next
+Already up to date.
+Merging char-misc/char-misc-next (27d128c1cff6 Merge tag 'trace-ring-buffer-v7.1-3' of git://git.kernel.org/pub/scm/linux/kernel/git/trace/linux-trace)
+$ git merge -m Merge branch 'char-misc-next' of https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc.git char-misc/char-misc-next
+Already up to date.
+Merging coresight/next (971f3474f889 coresight: tpdm: fix invalid MMIO access issue)
+$ git merge -m Merge branch 'next' of https://git.kernel.org/pub/scm/linux/kernel/git/coresight/linux.git coresight/next
+Already up to date.
+Merging fastrpc/for-next (6de23f81a5e0 Linux 7.0-rc1)
+$ git merge -m Merge branch 'for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/srini/fastrpc.git fastrpc/for-next
+Already up to date.
+Merging fpga/for-next (f63ddbcc3299 fpga: m10bmc-sec: switch show_canceled_csk() to using sysfs_emit())
+$ git merge -m Merge branch 'for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/fpga/linux-fpga.git fpga/for-next
+Already up to date.
+Merging icc/icc-next (0436cd305d0b MAINTAINERS: Add interconnect kunit test entry)
+$ git merge -m Merge branch 'icc-next' of https://git.kernel.org/pub/scm/linux/kernel/git/djakov/icc.git icc/icc-next
+Already up to date.
+Merging iio/togreg (d2a4ec19d2a2 Docs: iio: ad7191 Correct clock configuration)
+$ git merge -m Merge branch 'togreg' of https://git.kernel.org/pub/scm/linux/kernel/git/jic23/iio.git iio/togreg
+Already up to date.
+Merging phy-next/next (caf08514bbee dt-bindings: phy: qcom,sc8280xp-qmp-ufs-phy: document the Eliza QMP UFS PHY)
+$ git merge -m Merge branch 'next' of https://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy.git phy-next/next
+Already up to date.
+Merging soundwire/next (b8f2d65fec19 soundwire: intel_auxdevice: Add cs42l49 to wake_capable_list)
+$ git merge -m Merge branch 'next' of https://git.kernel.org/pub/scm/linux/kernel/git/vkoul/soundwire.git soundwire/next
+Already up to date.
+Merging extcon/extcon-next (1bf0ba46d9d2 extcon: usbc-tusb320: Make typec-power-opmode optional)
+$ git merge -m Merge branch 'extcon-next' of https://git.kernel.org/pub/scm/linux/kernel/git/chanwoo/extcon.git extcon/extcon-next
+Already up to date.
+Merging gnss/gnss-next (f338e7738378 Linux 7.0-rc4)
+$ git merge -m Merge branch 'gnss-next' of https://git.kernel.org/pub/scm/linux/kernel/git/johan/gnss.git gnss/gnss-next
+Already up to date.
+Merging vfio/next (30471982cd66 vfio/cdx: Consolidate MSI configured state onto cdx_irqs)
+$ git merge -m Merge branch 'next' of https://github.com/awilliam/linux-vfio.git vfio/next
+Already up to date.
+Merging w1/for-next (6de23f81a5e0 Linux 7.0-rc1)
+$ git merge -m Merge branch 'for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-w1.git w1/for-next
+Already up to date.
+Merging spmi/spmi-next (6de23f81a5e0 Linux 7.0-rc1)
+$ git merge -m Merge branch 'spmi-next' of https://git.kernel.org/pub/scm/linux/kernel/git/sboyd/spmi.git spmi/spmi-next
+Already up to date.
+Merging staging/staging-next (27d128c1cff6 Merge tag 'trace-ring-buffer-v7.1-3' of git://git.kernel.org/pub/scm/linux/kernel/git/trace/linux-trace)
+$ git merge -m Merge branch 'staging-next' of https://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging.git staging/staging-next
+Already up to date.
+Merging counter-next/counter-next (cbf8db23fc58 counter: sysfs: remove double return in counter_sysfs_attr_add())
+$ git merge -m Merge branch 'counter-next' of https://git.kernel.org/pub/scm/linux/kernel/git/wbg/counter.git counter-next/counter-next
+Already up to date.
+Merging mux/for-next (59b723cd2adb Linux 6.12-rc6)
+$ git merge -m Merge branch 'for-next' of https://gitlab.com/peda-linux/mux.git mux/for-next
+Already up to date.
+Merging dmaengine/next (b7560798466a dmaengine: dw-edma: Add non-LL mode)
+$ git merge -m Merge branch 'next' of https://git.kernel.org/pub/scm/linux/kernel/git/vkoul/dmaengine.git dmaengine/next
+Already up to date.
+Merging cgroup/for-next (41cb56f2cf9b Merge branch 'for-7.1-fixes' into for-next)
+$ git merge -m Merge branch 'for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/tj/cgroup.git cgroup/for-next
+Auto-merging kernel/cgroup/cgroup.c
+Merge made by the 'ort' strategy.
+ kernel/cgroup/cgroup.c          |  46 ++++++++++------
+ kernel/cgroup/cpuset-internal.h |   5 ++
+ kernel/cgroup/cpuset.c          |  13 +++--
+ kernel/cgroup/rdma.c            | 118 ++++++++++++++++++++--------------------
+ 4 files changed, 100 insertions(+), 82 deletions(-)
+Merging scsi/for-next (06bc53260985 Merge branch 'misc' into for-next)
+$ git merge -m Merge branch 'for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/jejb/scsi.git scsi/for-next
+Merge made by the 'ort' strategy.
+Merging scsi-mkp/for-next (254f49634ee1 Linux 7.1-rc1)
+$ git merge -m Merge branch 'for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/mkp/scsi.git scsi-mkp/for-next
+Already up to date.
+Merging vhost/linux-next (ebcff9dacaf2 vduse: avoid adding implicit padding)
+$ git merge -m Merge branch 'linux-next' of https://git.kernel.org/pub/scm/linux/kernel/git/mst/vhost.git vhost/linux-next
+Already up to date.
+Merging rpmsg/for-next (6f860d238b44 Merge branches 'hwspinlock-next', 'rpmsg-next', 'rproc-fixes' and 'rproc-next' into for-next)
+$ git merge -m Merge branch 'for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/remoteproc/linux.git rpmsg/for-next
+Merge made by the 'ort' strategy.
+Merging gpio-brgl/gpio/for-next (6d22fcf85e3f gpio: qcom: Unify user-visible "Qualcomm" name)
+$ git merge -m Merge branch 'gpio/for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux.git gpio-brgl/gpio/for-next
+Auto-merging drivers/gpio/Kconfig
+Merge made by the 'ort' strategy.
+ drivers/gpio/Kconfig        | 2 +-
+ drivers/gpio/gpio-pca953x.c | 7 ++-----
+ drivers/gpio/gpio-usbio.c   | 1 +
+ drivers/gpio/gpio-xilinx.c  | 6 ++----
+ 4 files changed, 6 insertions(+), 10 deletions(-)
+Merging gpio-intel/for-next (254f49634ee1 Linux 7.1-rc1)
+$ git merge -m Merge branch 'for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/andy/linux-gpio-intel.git gpio-intel/for-next
+Already up to date.
+Merging pinctrl/for-next (bd7fd288490c Merge branch 'devel' into for-next)
+$ git merge -m Merge branch 'for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl.git pinctrl/for-next
+Merge made by the 'ort' strategy.
+Merging pinctrl-intel/for-next (254f49634ee1 Linux 7.1-rc1)
+$ git merge -m Merge branch 'for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/intel.git pinctrl-intel/for-next
+Already up to date.
+Merging pinctrl-renesas/renesas-pinctrl (3f92867ce3ee pinctrl: renesas: rzg2l: Drop superfluous blank line)
+$ git merge -m Merge branch 'renesas-pinctrl' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers.git pinctrl-renesas/renesas-pinctrl
+Already up to date.
+Merging pinctrl-samsung/for-next (6de23f81a5e0 Linux 7.0-rc1)
+$ git merge -m Merge branch 'for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/pinctrl/samsung.git pinctrl-samsung/for-next
+Already up to date.
+Merging pwm/pwm/for-next (68637b68afcc pwm: atmel-tcb: Cache clock rates and mark chip as atomic)
+$ git merge -m Merge branch 'pwm/for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/ukleinek/linux.git pwm/pwm/for-next
+Already up to date.
+Merging ktest/for-next (932cdaf3e273 ktest: Add logfile to failure directory)
+$ git merge -m Merge branch 'for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/rostedt/linux-ktest.git ktest/for-next
+Already up to date.
+Merging kselftest/next (83ef26f91143 selftests: Fix duplicated test number reporting)
+$ git merge -m Merge branch 'next' of https://git.kernel.org/pub/scm/linux/kernel/git/shuah/linux-kselftest.git kselftest/next
+Already up to date.
+Merging kunit/test (6de23f81a5e0 Linux 7.0-rc1)
+$ git merge -m Merge branch 'test' of https://git.kernel.org/pub/scm/linux/kernel/git/shuah/linux-kselftest.git kunit/test
+Already up to date.
+Merging kunit-next/kunit (8f260b02eeef kunit: tool: Terminate kernel under test on SIGINT)
+$ git merge -m Merge branch 'kunit' of https://git.kernel.org/pub/scm/linux/kernel/git/shuah/linux-kselftest.git kunit-next/kunit
+Already up to date.
+Merging livepatching/for-next (712c0756828b Merge branch 'for-7.1/module-function-test' into for-next)
+$ git merge -m Merge branch 'for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/livepatching/livepatching.git livepatching/for-next
+Merge made by the 'ort' strategy.
+Merging rtc/rtc-next (0fedce7244e4 rtc: abx80x: Disable alarm feature if no interrupt attached)
+$ git merge -m Merge branch 'rtc-next' of https://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux.git rtc/rtc-next
+Already up to date.
+Merging nvdimm/libnvdimm-for-next (45df9111692c dax/fsdev: fix uninitialized kaddr in fsdev_dax_zero_page_range())
+$ git merge -m Merge branch 'libnvdimm-for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/nvdimm/nvdimm.git nvdimm/libnvdimm-for-next
+Already up to date.
+Merging at24/at24/for-next (6de23f81a5e0 Linux 7.0-rc1)
+$ git merge -m Merge branch 'at24/for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux.git at24/at24/for-next
+Already up to date.
+Merging ntb/ntb-next (7b3302c687ca ntb_hw_amd: Fix incorrect debug message in link disable path)
+$ git merge -m Merge branch 'ntb-next' of https://github.com/jonmason/ntb.git ntb/ntb-next
+Merge made by the 'ort' strategy.
+ drivers/ntb/hw/amd/ntb_hw_amd.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+Merging seccomp/for-next/seccomp (41fa04327384 selftests/seccomp: Add hard-coded __NR_uprobe for x86_64)
+$ git merge -m Merge branch 'for-next/seccomp' of https://git.kernel.org/pub/scm/linux/kernel/git/kees/linux.git seccomp/for-next/seccomp
+Already up to date.
+Merging slimbus/for-next (6de23f81a5e0 Linux 7.0-rc1)
+$ git merge -m Merge branch 'for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/srini/slimbus.git slimbus/for-next
+Already up to date.
+Merging nvmem/for-next (8d48419d141c Merge branches 'nvmem-fixes' and 'nvmem-for-7.1' into nvmem-for-next)
+$ git merge -m Merge branch 'for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/srini/nvmem.git nvmem/for-next
+Merge made by the 'ort' strategy.
+Merging hyperv/hyperv-next (5170a82e8921 x86/hyperv: Skip LP/VP creation on kexec)
+$ git merge -m Merge branch 'hyperv-next' of https://git.kernel.org/pub/scm/linux/kernel/git/hyperv/linux.git hyperv/hyperv-next
+Already up to date.
+Merging auxdisplay/for-next (254f49634ee1 Linux 7.1-rc1)
+$ git merge -m Merge branch 'for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/andy/linux-auxdisplay.git auxdisplay/for-next
+Already up to date.
+Merging kgdb/kgdb/for-next (fdbdd0ccb30a kdb: remove redundant check for scancode 0xe0)
+$ git merge -m Merge branch 'kgdb/for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/danielt/linux.git kgdb/kgdb/for-next
+Already up to date.
+Merging hmm/hmm (19272b37aa4f Linux 6.16-rc1)
+$ git merge -m Merge branch 'hmm' of https://git.kernel.org/pub/scm/linux/kernel/git/rdma/rdma.git hmm/hmm
+Already up to date.
+Merging cfi/cfi/next (6de23f81a5e0 Linux 7.0-rc1)
+$ git merge -m Merge branch 'cfi/next' of https://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git cfi/cfi/next
+Already up to date.
+Merging mhi/mhi-next (ac12b852b4ea bus: mhi: host: pci_generic: Add Telit FE912C04 modem support)
+$ git merge -m Merge branch 'mhi-next' of https://git.kernel.org/pub/scm/linux/kernel/git/mani/mhi.git mhi/mhi-next
+Already up to date.
+Merging memblock/for-next (d5759519805c x86/alternative: delay freeing of smp_locks section)
+$ git merge -m Merge branch 'for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/rppt/memblock.git memblock/for-next
+Already up to date.
+Merging cxl/next (6c724ce0ec6e Merge branch 'for-7.1/cxl-misc' into cxl-for-next)
+$ git merge -m Merge branch 'next' of https://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl.git cxl/next
+Already up to date.
+Merging zstd/zstd-next (65d1f5507ed2 zstd: Import upstream v1.5.7)
+$ git merge -m Merge branch 'zstd-next' of https://github.com/terrelln/linux.git zstd/zstd-next
+Already up to date.
+Merging efi/next (48a428215782 efi/capsule-loader: fix incorrect sizeof in phys array reallocation)
+$ git merge -m Merge branch 'next' of https://git.kernel.org/pub/scm/linux/kernel/git/efi/efi.git efi/next
+Already up to date.
+Merging unicode/for-next (bcfee135d584 utf8: Remove unused utf8_normalize)
+$ git merge -m Merge branch 'for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/krisman/unicode.git unicode/for-next
+Auto-merging fs/unicode/utf8-core.c
+Merge made by the 'ort' strategy.
+ fs/unicode/utf8-core.c  | 22 ----------------------
+ include/linux/unicode.h |  3 ---
+ 2 files changed, 25 deletions(-)
+Merging slab/slab/for-next (44e0ebe4accd Merge branch 'slab/for-7.1/misc' into slab/for-next)
+$ git merge -m Merge branch 'slab/for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/vbabka/slab.git slab/slab/for-next
+Already up to date.
+Merging random/master (bb9ff576fdff virt: vmgenid: remap memory as decrypted)
+$ git merge -m Merge branch 'master' of https://git.kernel.org/pub/scm/linux/kernel/git/crng/random.git random/master
+Merge made by the 'ort' strategy.
+ drivers/virt/vmgenid.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+Merging landlock/next (3457a5ccacd3 landlock: Document fallocate(2) as another truncation corner case)
+$ git merge -m Merge branch 'next' of https://git.kernel.org/pub/scm/linux/kernel/git/mic/linux.git landlock/next
+Already up to date.
+Merging sysctl/sysctl-next (f63a9df7e3f9 sysctl: fix uninitialized variable in proc_do_large_bitmap)
+$ git merge -m Merge branch 'sysctl-next' of https://git.kernel.org/pub/scm/linux/kernel/git/sysctl/sysctl.git sysctl/sysctl-next
+Already up to date.
+Merging execve/for-next/execve (9bf092c97b86 sched: update task_struct->comm comment)
+$ git merge -m Merge branch 'for-next/execve' of https://git.kernel.org/pub/scm/linux/kernel/git/kees/linux.git execve/for-next/execve
+Already up to date.
+Merging bitmap/bitmap-for-next (1f5ffc672165 Fix mismerge of the arm64 / timer-core interrupt handling changes)
+$ git merge -m Merge branch 'bitmap-for-next' of https://github.com/norov/linux.git bitmap/bitmap-for-next
+Already up to date.
+Merging hte/for-next (005b25ad1171 hte: tegra194: Add Tegra264 GTE support)
+$ git merge -m Merge branch 'for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/pateldipen1984/linux.git hte/for-next
+Already up to date.
+Merging kspp/for-next/kspp (e0142e0de50a Merge branch 'for-next/hardening' into for-next/kspp)
+$ git merge -m Merge branch 'for-next/kspp' of https://git.kernel.org/pub/scm/linux/kernel/git/kees/linux.git kspp/for-next/kspp
+Merge made by the 'ort' strategy.
+Merging nolibc/for-next (b070dc36291f selftests/nolibc: use gcc 15)
+$ git merge -m Merge branch 'for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/nolibc/linux-nolibc.git nolibc/for-next
+Already up to date.
+Merging iommufd/for-next (8602018b1f17 iommufd: Fix a race with concurrent allocation and unmap)
+$ git merge -m Merge branch 'for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/jgg/iommufd.git iommufd/for-next
+Already up to date.
+Merging turbostat/next (6112da1ea4a7 Merge branches 'turbostat' and 'x86_energy_perf_policy' into power-utilities)
+$ git merge -m Merge branch 'next' of https://git.kernel.org/pub/scm/linux/kernel/git/lenb/linux.git turbostat/next
+Already up to date.
+Merging pwrseq/pwrseq/for-next (b4464d8f313f power: sequencing: pcie-m2: add SERIAL_DEV_BUS dependency)
+$ git merge -m Merge branch 'pwrseq/for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux.git pwrseq/pwrseq/for-next
+Already up to date.
+Merging capabilities-next/caps-next (071588136007 ipc: don't audit capability check in ipc_permissions())
+$ git merge -m Merge branch 'caps-next' of https://git.kernel.org/pub/scm/linux/kernel/git/sergeh/linux.git capabilities-next/caps-next
+Already up to date.
+Merging ipe/next (028ef9c96e96 Linux 7.0)
+$ git merge -m Merge branch 'next' of https://git.kernel.org/pub/scm/linux/kernel/git/wufan/ipe.git ipe/next
+Already up to date.
+Merging kcsan/next (dcb6fa37fd7b Linux 6.18-rc3)
+$ git merge -m Merge branch 'next' of https://git.kernel.org/pub/scm/linux/kernel/git/melver/linux.git kcsan/next
+Already up to date.
+Merging crc/crc-next (254f49634ee1 Linux 7.1-rc1)
+$ git merge -m Merge branch 'crc-next' of https://git.kernel.org/pub/scm/linux/kernel/git/ebiggers/linux.git crc/crc-next
+Already up to date.
+Merging keys-next/keys-next (965e9a2cf23b pkcs7: Change a pr_warn() to pr_warn_once())
+$ git merge -m Merge branch 'keys-next' of https://git.kernel.org/pub/scm/linux/kernel/git/dhowells/linux-fs.git keys-next/keys-next
+Already up to date.
+Merging fwctl/for-next (a55f80233f38 fwctl: Fix class init ordering to avoid NULL pointer dereference on device removal)
+$ git merge -m Merge branch 'for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/fwctl/fwctl.git fwctl/for-next
+Already up to date.
+Merging devsec-tsm/next (3177779ae17d virt: coco: change tsm_class to a const struct)
+$ git merge -m Merge branch 'next' of https://git.kernel.org/pub/scm/linux/kernel/git/devsec/tsm.git devsec-tsm/next
+Already up to date.
+Merging hisilicon/for-next (b419e155e31d Merge branch 'next/dt64' into for-next)
+$ git merge -m Merge branch 'for-next' of https://github.com/hisilicon/linux-hisi.git hisilicon/for-next
+Merge made by the 'ort' strategy.
+Merging kthread/for-next (fa39ec4f89f2 doc: Add housekeeping documentation)
+$ git merge -m Merge branch 'for-next' of https://git.kernel.org/pub/scm/linux/kernel/git/frederic/linux-dynticks.git kthread/for-next
+Already up to date.
diff --git a/arch/arm/arm-soc-for-next-contents.txt b/arch/arm/arm-soc-for-next-contents.txt
new file mode 100644
index 000000000000..637d0bd2c508
--- /dev/null
+++ b/arch/arm/arm-soc-for-next-contents.txt
@@ -0,0 +1,23 @@
+arm/fixes
+	nxp/fixes-2
+		https://git.kernel.org/pub/scm/linux/kernel/git/frank.li/linux tags/imx-fixes-7.0-2nd
+	reset/fixes-3
+		https://git.pengutronix.de/git/pza/linux tags/reset-fixes-for-v7.0-3
+	marvell/fixes
+		https://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu tags/mvebu-fixes-7.0-1
+
+soc/late2
+	arm/fixes
+		Merge branch 'arm/fixes' into soc/late2
+		contains nxp/fixes-2
+		contains reset/fixes-3
+		contains marvell/fixes
+	marvell/dt64
+		https://git.kernel.org/pub/scm/linux/kernel/git/gclement/mvebu tags/mvebu-dt64-7.1-1
+	patch
+		ARM: dts: bcm4709: fix bus range assignment
+		Documentation/process: maintainer-soc: Trim from trivial ask-DT
+		Documentation/process: maintainer-soc: Document purpose of defconfigs
+	apple/fixes
+		https://git.kernel.org/pub/scm/linux/kernel/git/sven/linux tags/apple-soc-fixes-7.0
+
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index fe60738e5943..fa676428ec3f 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -1606,6 +1606,9 @@ config ARCH_SUPPORTS_CRASH_DUMP
 config ARCH_DEFAULT_CRASH_DUMP
 	def_bool y
 
+config ARCH_HAS_CPU_RELAX
+	def_bool y
+
 config ARCH_HAS_GENERIC_CRASHKERNEL_RESERVATION
 	def_bool CRASH_RESERVE
 
diff --git a/arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-khadas-vim4.dts b/arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-khadas-vim4.dts
index f4c953034be3..69d6118ba57e 100644
--- a/arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-khadas-vim4.dts
+++ b/arch/arm64/boot/dts/amlogic/amlogic-t7-a311d2-khadas-vim4.dts
@@ -6,6 +6,8 @@
 /dts-v1/;
 
 #include "amlogic-t7.dtsi"
+#include <dt-bindings/gpio/amlogic,t7-periphs-pinctrl.h>
+#include <dt-bindings/gpio/gpio.h>
 
 / {
 	model = "Khadas VIM4";
@@ -13,6 +15,9 @@ / {
 
 	aliases {
 		serial0 = &uart_a;
+		mmc0 = &sd_emmc_c;
+		mmc1 = &sd_emmc_b;
+		mmc2 = &sd_emmc_a;
 	};
 
 	memory@0 {
@@ -47,6 +52,200 @@ xtal: xtal-clk {
 		#clock-cells = <0>;
 	};
 
+	dc_in: regulator-dc-in {
+		compatible = "regulator-fixed";
+		regulator-name = "DC_IN";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		regulator-always-on;
+	};
+
+	sd_3v3: regulator-sdcard-3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "SD_3V3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vddao_3v3>;
+		gpio = <&gpio GPIOD_11 GPIO_ACTIVE_LOW>;
+		regulator-boot-on;
+		regulator-always-on;
+	};
+
+	sdio_pwrseq: sdio-pwrseq {
+		compatible = "mmc-pwrseq-simple";
+		reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
+		post-power-on-delay-ms = <500>;
+		power-off-delay-us = <200000>;
+		clocks = <&wifi32k>;
+		clock-names = "ext_clock";
+	};
+
+	vcc5v: regulator-vcc-5v {
+		compatible = "regulator-fixed";
+		regulator-name = "VCC5V";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&dc_in>;
+
+		gpio = <&gpio GPIOH_4 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+
+	vcc5v0_usb: regulator-vcc-usb {
+		compatible = "regulator-fixed";
+		regulator-name = "VCC5V0_USB";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&vcc5v>;
+
+		gpio = <&gpio GPIOY_5 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+	};
+
+	vddao_1v8: regulator-vddao-1v8 {
+		compatible = "regulator-fixed";
+		regulator-name = "VDDAO_1V8";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		vin-supply = <&vddao_3v3>;
+		regulator-always-on;
+	};
+
+	vddao_3v3: regulator-vddao-3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "VDDAO_3V3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&dc_in>;
+		regulator-always-on;
+	};
+
+	vddio_1v8: regulator-vddio-1v8 {
+		compatible = "regulator-fixed";
+		regulator-name = "VDDIO_1V8";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <1800000>;
+		vin-supply = <&vddio_3v3>;
+		regulator-always-on;
+	};
+
+	vddio_3v3: regulator-vddio-3v3 {
+		compatible = "regulator-fixed";
+		regulator-name = "VDDIO_3V3";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vddao_3v3>;
+		regulator-always-on;
+	};
+
+	vddio_c: regulator-gpio-c {
+		compatible = "regulator-gpio";
+		regulator-name = "VDDIO_C";
+		regulator-min-microvolt = <1800000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vddio_3v3>;
+		gpios = <&gpio GPIOD_9 GPIO_ACTIVE_HIGH>;
+		states = <1800000 1
+			  3300000 0>;
+	};
+
+	wifi32k: wifi32k {
+		compatible = "pwm-clock";
+		#clock-cells = <0>;
+		clock-frequency = <32768>;
+			pwms = <&pwm_ab 0 30518 0>;
+	};
+};
+
+&pwm_ab {
+	status = "okay";
+	pinctrl-0 = <&pwm_a_pins>;
+	pinctrl-names = "default";
+};
+
+/* SDIO */
+&sd_emmc_a {
+	status = "okay";
+	pinctrl-0 = <&sdio_pins>;
+	pinctrl-1 = <&sdio_clk_gate_pins>;
+	pinctrl-names = "default", "clk-gate";
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	bus-width = <4>;
+	cap-sd-highspeed;
+	sd-uhs-sdr12;
+	sd-uhs-sdr25;
+	sd-uhs-sdr50;
+	sd-uhs-sdr104;
+	cap-sdio-irq;
+	max-frequency = <200000000>;
+	non-removable;
+	disable-wp;
+	no-mmc;
+	no-sd;
+
+	power-domains = <&pwrc PWRC_T7_SDIO_A_ID>;
+
+	keep-power-in-suspend;
+
+	mmc-pwrseq = <&sdio_pwrseq>;
+
+	vmmc-supply = <&vddao_3v3>;
+	vqmmc-supply = <&vddao_1v8>;
+
+	brcmf: wifi@1 {
+		reg = <1>;
+		compatible = "brcm,bcm43752-fmac", "brcm,bcm4329-fmac";
+	};
+};
+
+/* SD card */
+&sd_emmc_b {
+	status = "okay";
+	pinctrl-0 = <&sdcard_pins>;
+	pinctrl-1 = <&sdcard_clk_gate_pins>;
+	pinctrl-names = "default", "clk-gate";
+
+	bus-width = <4>;
+	cap-sd-highspeed;
+	sd-uhs-sdr12;
+	sd-uhs-sdr25;
+	sd-uhs-sdr50;
+	sd-uhs-sdr104;
+	max-frequency = <200000000>;
+	disable-wp;
+	no-sdio;
+	no-mmc;
+
+	power-domains = <&pwrc PWRC_T7_SDIO_B_ID>;
+
+	cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_LOW>;
+	vmmc-supply = <&sd_3v3>;
+	vqmmc-supply = <&vddio_c>;
+};
+
+/* eMMC */
+&sd_emmc_c {
+	status = "okay";
+	pinctrl-0 = <&emmc_ctrl_pins>, <&emmc_data_8b_pins>, <&emmc_ds_pins>;
+	pinctrl-1 = <&emmc_clk_gate_pins>;
+	pinctrl-names = "default", "clk-gate";
+
+	bus-width = <8>;
+	cap-mmc-highspeed;
+	mmc-ddr-1_8v;
+	mmc-hs200-1_8v;
+	max-frequency = <200000000>;
+	disable-wp;
+	non-removable;
+	no-sdio;
+	no-sd;
+
+	power-domains = <&pwrc PWRC_T7_EMMC_ID>;
+
+	vmmc-supply = <&vddio_3v3>;
+	vqmmc-supply = <&vddio_1v8>;
 };
 
 &uart_a {
diff --git a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi
index d523cbc0ed22..7fe72c94ed62 100644
--- a/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi
+++ b/arch/arm64/boot/dts/amlogic/amlogic-t7.dtsi
@@ -6,6 +6,9 @@
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/power/amlogic,t7-pwrc.h>
 #include "amlogic-t7-reset.h"
+#include <dt-bindings/clock/amlogic,t7-scmi.h>
+#include <dt-bindings/clock/amlogic,t7-pll-clkc.h>
+#include <dt-bindings/clock/amlogic,t7-peripherals-clkc.h>
 
 / {
 	interrupt-parent = <&gic>;
@@ -201,6 +204,34 @@ pwrc: power-controller {
 		};
 	};
 
+	sram@f7042000 {
+		compatible = "mmio-sram";
+		reg = <0x0 0xf7042000 0x0 0x100>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges = <0 0x0 0xf7042000 0x100>;
+
+		scmi_shmem: sram@0 {
+			compatible = "arm,scmi-shmem";
+			reg = <0x0 0x100>;
+		};
+	};
+
+	firmware {
+		scmi: scmi {
+			compatible = "arm,scmi-smc";
+			arm,smc-id = <0x820000c1>;
+			shmem = <&scmi_shmem>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			scmi_clk: protocol@14 {
+				reg = <0x14>;
+				#clock-cells = <1>;
+			};
+		};
+	};
+
 	soc {
 		compatible = "simple-bus";
 		#address-cells = <2>;
@@ -226,6 +257,42 @@ apb4: bus@fe000000 {
 			#size-cells = <2>;
 			ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>;
 
+			clkc_periphs: clock-controller@0 {
+				compatible = "amlogic,t7-peripherals-clkc";
+				reg = <0x0 0x0 0x0 0x1c8>;
+				#clock-cells = <1>;
+				clocks = <&xtal>,
+					 <&scmi_clk CLKID_SYS_CLK>,
+					 <&scmi_clk CLKID_FIXED_PLL>,
+					 <&scmi_clk CLKID_FCLK_DIV2>,
+					 <&scmi_clk CLKID_FCLK_DIV2P5>,
+					 <&scmi_clk CLKID_FCLK_DIV3>,
+					 <&scmi_clk CLKID_FCLK_DIV4>,
+					 <&scmi_clk CLKID_FCLK_DIV5>,
+					 <&scmi_clk CLKID_FCLK_DIV7>,
+					 <&hifi CLKID_HIFI_PLL>,
+					 <&gp0 CLKID_GP0_PLL>,
+					 <&gp1 CLKID_GP1_PLL>,
+					 <&mpll CLKID_MPLL1>,
+					 <&mpll CLKID_MPLL2>,
+					 <&mpll CLKID_MPLL3>;
+				clock-names = "xtal",
+					      "sys",
+					      "fix",
+					      "fdiv2",
+					      "fdiv2p5",
+					      "fdiv3",
+					      "fdiv4",
+					      "fdiv5",
+					      "fdiv7",
+					      "hifi",
+					      "gp0",
+					      "gp1",
+					      "mpll1",
+					      "mpll2",
+					      "mpll3";
+			};
+
 			reset: reset-controller@2000 {
 				compatible = "amlogic,t7-reset";
 				reg = <0x0 0x2000 0x0 0x98>;
@@ -252,6 +319,240 @@ gpio: bank@4000 {
 					#gpio-cells = <2>;
 					gpio-ranges = <&periphs_pinctrl 0 0 157>;
 				};
+
+				emmc_ctrl_pins: emmc-ctrl {
+					mux-0 {
+						groups = "emmc_cmd";
+						function = "emmc";
+						bias-pull-up;
+					};
+
+					mux-1 {
+						groups = "emmc_clk";
+						function = "emmc";
+						bias-disable;
+					};
+				};
+
+				emmc_data_4b_pins: emmc-data-4b {
+					mux {
+						groups = "emmc_nand_d0",
+							 "emmc_nand_d1",
+							 "emmc_nand_d2",
+							 "emmc_nand_d3";
+						function = "emmc";
+						bias-pull-up;
+					};
+				};
+
+				emmc_data_8b_pins: emmc-data-8b {
+					mux {
+						groups = "emmc_nand_d0",
+							 "emmc_nand_d1",
+							 "emmc_nand_d2",
+							 "emmc_nand_d3",
+							 "emmc_nand_d4",
+							 "emmc_nand_d5",
+							 "emmc_nand_d6",
+							 "emmc_nand_d7";
+						function = "emmc";
+						bias-pull-up;
+					};
+				};
+
+				emmc_ds_pins: emmc-ds {
+					mux {
+						groups = "emmc_nand_ds";
+						function = "emmc";
+						bias-pull-down;
+					};
+				};
+
+				emmc_clk_gate_pins: emmc-clk-gate {
+					mux {
+						groups = "GPIOB_8";
+						function = "gpio_periphs";
+						bias-pull-down;
+					};
+				};
+
+				pwm_a_pins: pwm-a {
+					mux {
+						groups = "pwm_a";
+						function = "pwm_a";
+						bias-disable;
+					};
+				};
+
+				pwm_ao_a_pins: pwm-ao-a {
+					mux {
+						groups = "pwm_ao_a";
+						function = "pwm_ao_a";
+						bias-disable;
+					};
+				};
+
+				pwm_ao_b_pins: pwm-ao-b {
+					mux {
+						groups = "pwm_ao_b";
+						function = "pwm_ao_b";
+						bias-disable;
+					};
+				};
+
+				pwm_ao_c_pins: pwm-ao-c {
+					mux {
+						groups = "pwm_ao_c";
+						function = "pwm_ao_c";
+						bias-disable;
+					};
+				};
+
+				pwm_ao_c_hiz_pins: pwm-ao-c-hiz {
+					mux {
+						groups = "pwm_ao_c_hiz";
+						function = "pwm_ao_c_hiz";
+						bias-disable;
+					};
+				};
+
+				pwm_ao_d_pins: pwm-ao-d {
+					mux {
+						groups = "pwm_ao_d";
+						function = "pwm_ao_d";
+						bias-disable;
+					};
+				};
+
+				pwm_ao_e_pins: pwm-ao-e {
+					mux {
+						groups = "pwm_ao_e";
+						function = "pwm_ao_e";
+						bias-disable;
+					};
+				};
+
+				pwm_ao_f_pins: pwm-ao-f {
+					mux {
+						groups = "pwm_ao_f";
+						function = "pwm_ao_f";
+						bias-disable;
+					};
+				};
+
+				pwm_ao_g_pins: pwm-ao-g {
+					mux {
+						groups = "pwm_ao_g";
+						function = "pwm_ao_g";
+						bias-disable;
+					};
+				};
+
+				pwm_ao_g_hiz_pins: pwm-ao-g-hiz {
+					mux {
+						groups = "pwm_ao_g_hiz";
+						function = "pwm_ao_g_hiz";
+						bias-disable;
+					};
+				};
+
+				pwm_ao_h_pins: pwm-ao-h {
+					mux {
+						groups = "pwm_ao_h";
+						function = "pwm_ao_h";
+						bias-disable;
+					};
+				};
+
+				pwm_b_pins: pwm-b {
+					mux {
+						groups = "pwm_b";
+						function = "pwm_b";
+						bias-disable;
+					};
+				};
+
+				pwm_c_pins: pwm-c {
+					mux {
+						groups = "pwm_c";
+						function = "pwm_c";
+						bias-disable;
+					};
+				};
+
+				pwm_d_pins: pwm-d {
+					mux {
+						groups = "pwm_d";
+						function = "pwm_d";
+						bias-disable;
+					};
+				};
+
+				pwm_e_pins: pwm-e {
+					mux {
+						groups = "pwm_e";
+						function = "pwm_e";
+						bias-disable;
+					};
+				};
+
+				pwm_f_pins: pwm-f {
+					mux {
+						groups = "pwm_f";
+						function = "pwm_f";
+						bias-disable;
+					};
+				};
+
+				pwm_vs_pins: pwm-vs {
+					mux {
+						groups = "pwm_vs";
+						function = "pwm_vs";
+						bias-disable;
+					};
+				};
+
+				sdcard_pins: sdcard {
+					mux {
+						groups = "sdcard_d0",
+							 "sdcard_d1",
+							 "sdcard_d2",
+							 "sdcard_d3",
+							 "sdcard_clk",
+							 "sdcard_cmd";
+						function = "sdcard";
+						bias-pull-up;
+					};
+				};
+
+				sdcard_clk_gate_pins: sdcard-clk-gate {
+					mux {
+						groups = "GPIOC_4";
+						function = "gpio_periphs";
+						bias-pull-down;
+					};
+				};
+
+				sdio_pins: sdio {
+					mux {
+						groups = "sdio_d0",
+							 "sdio_d1",
+							 "sdio_d2",
+							 "sdio_d3",
+							 "sdio_clk",
+							 "sdio_cmd";
+						function = "sdio";
+						bias-pull-up;
+					};
+				};
+
+				sdio_clk_gate_pins: sdio-clk-gate {
+					mux {
+						groups = "GPIOX_4";
+						function = "gpio_periphs";
+						bias-pull-up;
+					};
+				};
 			};
 
 			gpio_intc: interrupt-controller@4080 {
@@ -271,6 +572,64 @@ uart_a: serial@78000 {
 				status = "disabled";
 			};
 
+			gp0: clock-controller@8080 {
+				compatible = "amlogic,t7-gp0-pll";
+				reg = <0x0 0x8080 0x0 0x20>;
+				clocks = <&scmi_clk CLKID_TOP_PLL_OSC>;
+				clock-names = "in0";
+				#clock-cells = <1>;
+			};
+
+			gp1: clock-controller@80c0 {
+				compatible = "amlogic,t7-gp1-pll";
+				reg = <0x0 0x80c0 0x0 0x14>;
+				clocks = <&scmi_clk CLKID_TOP_PLL_OSC>;
+				clock-names = "in0";
+				#clock-cells = <1>;
+			};
+
+			hifi: clock-controller@8100 {
+				compatible = "amlogic,t7-hifi-pll";
+				reg = <0x0 0x8100 0x0 0x20>;
+				clocks = <&scmi_clk CLKID_TOP_PLL_OSC>;
+				clock-names = "in0";
+				#clock-cells = <1>;
+			};
+
+			pcie: clock-controller@8140 {
+				compatible = "amlogic,t7-pcie-pll";
+				reg = <0x0 0x8140 0x0 0x1c>;
+				clocks = <&scmi_clk CLKID_PCIE_OSC>;
+				clock-names = "in0";
+				#clock-cells = <1>;
+			};
+
+			mpll: clock-controller@8180 {
+				compatible = "amlogic,t7-mpll";
+				reg = <0x0 0x8180 0x0 0x28>;
+				clocks = <&scmi_clk CLKID_FIXED_PLL_DCO>;
+				clock-names = "in0";
+				#clock-cells = <1>;
+			};
+
+			hdmi: clock-controller@81c0 {
+				compatible = "amlogic,t7-hdmi-pll";
+				reg = <0x0 0x81c0 0x0 0x20>;
+				clocks = <&scmi_clk CLKID_HDMI_PLL_OSC>;
+				clock-names = "in0";
+				#clock-cells = <1>;
+			};
+
+			mclk: clock-controller@8300 {
+				compatible = "amlogic,t7-mclk-pll";
+				reg = <0x0 0x8300 0x0 0x18>;
+				clocks = <&scmi_clk CLKID_MCLK_PLL_OSC>,
+					 <&xtal>,
+					 <&scmi_clk CLKID_FCLK_50M>;
+				clock-names = "in0", "in1", "in2";
+				#clock-cells = <1>;
+			};
+
 			sec_ao: ao-secure@10220 {
 				compatible = "amlogic,t7-ao-secure",
 					     "amlogic,meson-gx-ao-secure",
@@ -278,6 +637,111 @@ sec_ao: ao-secure@10220 {
 				reg = <0x0 0x10220 0x0 0x140>;
 				amlogic,has-chip-id;
 			};
+
+			pwm_ao_ef: pwm@30000 {
+				compatible = "amlogic,t7-pwm", "amlogic,meson-s4-pwm";
+				reg = <0x0 0x30000 0x0 0x24>;
+				clocks = <&clkc_periphs CLKID_PWM_AO_E>,
+					 <&clkc_periphs CLKID_PWM_AO_F>;
+				#pwm-cells = <3>;
+				status = "disabled";
+			};
+
+			pwm_ao_gh: pwm@32000 {
+				compatible = "amlogic,t7-pwm", "amlogic,meson-s4-pwm";
+				reg = <0x0 0x32000 0x0 0x24>;
+				clocks = <&clkc_periphs CLKID_PWM_AO_G>,
+					 <&clkc_periphs CLKID_PWM_AO_H>;
+				#pwm-cells = <3>;
+				status = "disabled";
+			};
+
+			pwm_ab: pwm@58000 {
+				compatible = "amlogic,t7-pwm", "amlogic,meson-s4-pwm";
+				reg = <0x0 0x58000 0x0 0x24>;
+				clocks = <&clkc_periphs CLKID_PWM_A>,
+					 <&clkc_periphs CLKID_PWM_B>;
+				#pwm-cells = <3>;
+				status = "disabled";
+			};
+
+			pwm_cd: pwm@5a000 {
+				compatible = "amlogic,t7-pwm", "amlogic,meson-s4-pwm";
+				reg = <0x0 0x5a000 0x0 0x24>;
+				clocks = <&clkc_periphs CLKID_PWM_C>,
+					 <&clkc_periphs CLKID_PWM_D>;
+				#pwm-cells = <3>;
+				status = "disabled";
+			};
+
+			pwm_ef: pwm@5c000 {
+				compatible = "amlogic,t7-pwm", "amlogic,meson-s4-pwm";
+				reg = <0x0 0x5c000 0x0 0x24>;
+				clocks = <&clkc_periphs CLKID_PWM_E>,
+					 <&clkc_periphs CLKID_PWM_F>;
+				#pwm-cells = <3>;
+				status = "disabled";
+			};
+
+			pwm_ao_ab: pwm@5e000 {
+				compatible = "amlogic,t7-pwm", "amlogic,meson-s4-pwm";
+				reg = <0x0 0x5e000 0x0 0x24>;
+				clocks = <&clkc_periphs CLKID_PWM_AO_A>,
+					 <&clkc_periphs CLKID_PWM_AO_B>;
+				#pwm-cells = <3>;
+				status = "disabled";
+			};
+
+			pwm_ao_cd: pwm@60000 {
+				compatible = "amlogic,t7-pwm", "amlogic,meson-s4-pwm";
+				reg = <0x0 0x60000 0x0 0x24>;
+				clocks = <&clkc_periphs CLKID_PWM_AO_C>,
+					 <&clkc_periphs CLKID_PWM_AO_D>;
+				#pwm-cells = <3>;
+				status = "disabled";
+			};
+
+			sd_emmc_a: mmc@88000 {
+				compatible = "amlogic,t7-mmc", "amlogic,meson-axg-mmc";
+				reg = <0x0 0x88000 0x0 0x800>;
+				interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
+				clocks = <&clkc_periphs CLKID_SYS_SD_EMMC_A>,
+					 <&clkc_periphs CLKID_SD_EMMC_A>,
+					 <&scmi_clk CLKID_FCLK_DIV2>;
+				clock-names = "core", "clkin0", "clkin1";
+				resets = <&reset RESET_SD_EMMC_A>;
+				assigned-clocks = <&clkc_periphs CLKID_SD_EMMC_A_SEL>;
+				assigned-clock-parents = <&xtal>;
+				status = "disabled";
+			};
+
+			sd_emmc_b: mmc@8a000 {
+				compatible = "amlogic,t7-mmc", "amlogic,meson-axg-mmc";
+				reg = <0x0 0x8a000 0x0 0x800>;
+				interrupts = <GIC_SPI 177 IRQ_TYPE_EDGE_RISING>;
+				clocks = <&clkc_periphs CLKID_SYS_SD_EMMC_B>,
+					 <&clkc_periphs CLKID_SD_EMMC_B>,
+					 <&scmi_clk CLKID_FCLK_DIV2>;
+				clock-names = "core", "clkin0", "clkin1";
+				resets = <&reset RESET_SD_EMMC_B>;
+				assigned-clocks = <&clkc_periphs CLKID_SD_EMMC_B_SEL>;
+				assigned-clock-parents = <&xtal>;
+				status = "disabled";
+			};
+
+			sd_emmc_c: mmc@8c000 {
+				compatible = "amlogic,t7-mmc", "amlogic,meson-axg-mmc";
+				reg = <0x0 0x8c000 0x0 0x800>;
+				interrupts = <GIC_SPI 178 IRQ_TYPE_EDGE_RISING>;
+				clocks = <&clkc_periphs CLKID_SYS_SD_EMMC_C>,
+					 <&clkc_periphs CLKID_SD_EMMC_C>,
+					 <&scmi_clk CLKID_FCLK_DIV2>;
+				clock-names = "core", "clkin0", "clkin1";
+				resets = <&reset RESET_SD_EMMC_C>;
+				assigned-clocks = <&clkc_periphs CLKID_SD_EMMC_C_SEL>;
+				assigned-clock-parents = <&xtal>;
+				status = "disabled";
+			};
 		};
 
 	};
diff --git a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-phicomm-n1.dts b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-phicomm-n1.dts
index 393d3cb33b9e..dea3a60e8527 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-phicomm-n1.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-gxl-s905d-phicomm-n1.dts
@@ -30,6 +30,21 @@ &cvbs_vdac_port {
 	status = "disabled";
 };
 
+&uart_A {
+	status = "okay";
+	pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
+	pinctrl-names = "default";
+	uart-has-rtscts;
+
+	bluetooth {
+		compatible = "brcm,bcm43438-bt";
+		shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
+		max-speed = <2000000>;
+		clocks = <&wifi32k>;
+		clock-names = "lpo";
+	};
+};
+
 &usb {
 	dr_mode = "host";
 };
diff --git a/arch/arm64/boot/dts/amlogic/meson-s4-s905y4-khadas-vim1s.dts b/arch/arm64/boot/dts/amlogic/meson-s4-s905y4-khadas-vim1s.dts
index 27d0f6134ea9..99d5df71b9cd 100644
--- a/arch/arm64/boot/dts/amlogic/meson-s4-s905y4-khadas-vim1s.dts
+++ b/arch/arm64/boot/dts/amlogic/meson-s4-s905y4-khadas-vim1s.dts
@@ -6,6 +6,8 @@
 /dts-v1/;
 
 #include "meson-s4.dtsi"
+#include <dt-bindings/input/input.h>
+#include <dt-bindings/leds/common.h>
 
 / {
 	model = "Khadas VIM1S";
@@ -18,6 +20,8 @@ aliases {
 		mmc0 = &emmc; /* eMMC */
 		mmc1 = &sd; /* SD card */
 		mmc2 = &sdio; /* SDIO */
+		rtc0 = &rtc;
+		rtc1 = &vrtc;
 		serial0 = &uart_b;
 	};
 
@@ -38,11 +42,48 @@ secmon_reserved: secmon@5000000 {
 		};
 	};
 
+	adc-keys {
+		compatible = "adc-keys";
+		io-channels = <&saradc 0>;
+		io-channel-names = "buttons";
+		keyup-threshold-microvolt = <1710000>;
+		poll-interval = <100>;
+
+		button-function {
+			label = "Function";
+			linux,code = <KEY_FN>;
+			press-threshold-microvolt = <10000>;
+		};
+	};
+
 	emmc_pwrseq: emmc-pwrseq {
 		compatible = "mmc-pwrseq-emmc";
 		reset-gpios = <&gpio GPIOB_9 GPIO_ACTIVE_LOW>;
 	};
 
+	gpio-keys-polled {
+		compatible = "gpio-keys-polled";
+		poll-interval = <100>;
+
+		power-button {
+			label = "power";
+			linux,code = <KEY_POWER>;
+			gpios = <&gpio GPIOD_8 GPIO_ACTIVE_LOW>;
+		};
+	};
+
+	pwm-leds {
+		compatible = "pwm-leds";
+
+		led-1 {
+			color = <LED_COLOR_ID_WHITE>;
+			function = LED_FUNCTION_STATUS;
+			linux,default-trigger = "heartbeat";
+			max-brightness = <255>;
+			pwms = <&pwm_gh 0 30040 0>;
+		};
+	};
+
 	sdio_32k: sdio-32k {
 		compatible = "pwm-clock";
 		#clock-cells = <0>;
@@ -184,10 +225,24 @@ &ethmac {
 	phy-mode = "rmii";
 };
 
+&i2c1 {
+	status = "okay";
+	pinctrl-names = "default";
+	pinctrl-0 = <&i2c1_pins2>;
+	clock-frequency = <100000>;
+
+	rtc: rtc@51 {
+		compatible = "haoyu,hym8563";
+		reg = <0x51>;
+		#clock-cells = <0>;
+	};
+};
+
 &ir {
 	status = "okay";
 	pinctrl-0 = <&remote_pins>;
 	pinctrl-names = "default";
+	linux,rc-map-name = "rc-khadas";
 };
 
 &pwm_ef {
@@ -196,6 +251,12 @@ &pwm_ef {
 	pinctrl-names = "default";
 };
 
+&pwm_gh {
+	status = "okay";
+	pinctrl-0 = <&pwm_g_pins1>;
+	pinctrl-names = "default";
+};
+
 &pwm_ij {
 	status = "okay";
 };
@@ -247,6 +308,11 @@ brcmf: wifi@1 {
 	};
 };
 
+&saradc {
+	status = "okay";
+	vref-supply = <&vddio_ao1v8>;
+};
+
 &spicc0 {
 	status = "okay";
 	pinctrl-names = "default";
@@ -254,6 +320,21 @@ &spicc0 {
 	cs-gpios = <&gpio GPIOX_10 GPIO_ACTIVE_LOW>;
 };
 
+&uart_a {
+	status = "okay";
+	pinctrl-0 = <&uart_a_pins>, <&uart_a_cts_rts_pins>;
+	pinctrl-names = "default";
+	uart-has-rtscts;
+
+	bluetooth {
+		compatible = "brcm,bcm4345c5";
+		shutdown-gpios = <&gpio GPIOX_17 GPIO_ACTIVE_HIGH>;
+		max-speed = <2000000>;
+		clocks = <&sdio_32k>;
+		clock-names = "lpo";
+	};
+};
+
 &uart_b {
 	status = "okay";
 };
diff --git a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi
index dfc0a30a6e61..2a6fbd530836 100644
--- a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi
@@ -59,6 +59,11 @@ psci {
 		method = "smc";
 	};
 
+	vrtc: rtc@fe010288 {
+		compatible = "amlogic,meson-vrtc";
+		reg = <0x0 0xfe010288 0x0 0x4>;
+	};
+
 	xtal: xtal-clk {
 		compatible = "fixed-clock";
 		clock-frequency = <24000000>;
@@ -77,6 +82,20 @@ pwrc: power-controller {
 		};
 	};
 
+	saradc: adc@fe026000 {
+		compatible = "amlogic,meson-s4-saradc",
+			     "amlogic,meson-g12a-saradc";
+		reg = <0x0 0xfe026000 0x0 0x48>;
+		#io-channel-cells = <1>;
+		interrupts = <GIC_SPI 181 IRQ_TYPE_EDGE_RISING>;
+		clocks = <&xtal>,
+			 <&clkc_periphs CLKID_SAR_ADC>,
+			 <&clkc_periphs CLKID_SARADC>,
+			 <&clkc_periphs CLKID_SARADC_SEL>;
+		clock-names = "clkin", "core", "adc_clk", "adc_sel";
+		status = "disabled";
+	};
+
 	soc {
 		compatible = "simple-bus";
 		#address-cells = <2>;
@@ -163,6 +182,22 @@ mux {
 					};
 				};
 
+				uart_a_pins: uart-a-pins {
+					mux {
+						groups = "uart_a_tx",
+						       "uart_a_rx";
+						function = "uart_a";
+					};
+				};
+
+				uart_a_cts_rts_pins: uart-a-cts-rts-pins {
+					mux {
+						groups = "uart_a_cts",
+						       "uart_a_rts";
+						function = "uart_a";
+					};
+				};
+
 				i2c0_pins1: i2c0-pins1 {
 					mux {
 						groups = "i2c0_sda",
@@ -814,6 +849,16 @@ mdio0: mdio {
 			};
 		};
 
+		uart_a: serial@fe078000 {
+			compatible = "amlogic,meson-s4-uart",
+				     "amlogic,meson-ao-uart";
+			reg = <0x0 0xfe078000 0x0 0x18>;
+			interrupts = <GIC_SPI 168 IRQ_TYPE_EDGE_RISING>;
+			clocks = <&xtal>, <&clkc_periphs CLKID_UART_A>, <&xtal>;
+			clock-names = "xtal", "pclk", "baud";
+			status = "disabled";
+		};
+
 		sdio: mmc@fe088000 {
 			compatible = "amlogic,meson-axg-mmc";
 			reg = <0x0 0xfe088000 0x0 0x800>;
diff --git a/arch/arm64/boot/dts/rockchip/rk3576.dtsi b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
index 28175d8200d5..e12a2a0cfb89 100644
--- a/arch/arm64/boot/dts/rockchip/rk3576.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3576.dtsi
@@ -1281,10 +1281,10 @@ gpu: gpu@27800000 {
 
 		vdec: video-codec@27b00000 {
 			compatible = "rockchip,rk3576-vdec";
-			reg = <0x0 0x27b00100 0x0 0x500>,
-			      <0x0 0x27b00000 0x0 0x100>,
+			reg = <0x0 0x27b00000 0x0 0x100>,
+			      <0x0 0x27b00100 0x0 0x500>,
 			      <0x0 0x27b00600 0x0 0x100>;
-			reg-names = "function", "link", "cache";
+			reg-names = "link", "function", "cache";
 			interrupts = <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&cru ACLK_RKVDEC_ROOT>, <&cru HCLK_RKVDEC>,
 				 <&cru ACLK_RKVDEC_ROOT_BAK>, <&cru CLK_RKVDEC_CORE>,
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
index 4fb8888c281c..d4dc057e31f0 100644
--- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi
@@ -1355,10 +1355,10 @@ vepu121_3_mmu: iommu@fdbac800 {
 
 	vdec0: video-codec@fdc38000 {
 		compatible = "rockchip,rk3588-vdec";
-		reg = <0x0 0xfdc38100 0x0 0x500>,
-		      <0x0 0xfdc38000 0x0 0x100>,
+		reg = <0x0 0xfdc38000 0x0 0x100>,
+		      <0x0 0xfdc38100 0x0 0x500>,
 		      <0x0 0xfdc38600 0x0 0x100>;
-		reg-names = "function", "link", "cache";
+		reg-names = "link", "function", "cache";
 		interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH 0>;
 		clocks = <&cru ACLK_RKVDEC0>, <&cru HCLK_RKVDEC0>, <&cru CLK_RKVDEC0_CA>,
 			 <&cru CLK_RKVDEC0_CORE>, <&cru CLK_RKVDEC0_HEVC_CA>;
@@ -1387,10 +1387,10 @@ vdec0_mmu: iommu@fdc38700 {
 
 	vdec1: video-codec@fdc40000 {
 		compatible = "rockchip,rk3588-vdec";
-		reg = <0x0 0xfdc40100 0x0 0x500>,
-		      <0x0 0xfdc40000 0x0 0x100>,
+		reg = <0x0 0xfdc40000 0x0 0x100>,
+		      <0x0 0xfdc40100 0x0 0x500>,
 		      <0x0 0xfdc40600 0x0 0x100>;
-		reg-names = "function", "link", "cache";
+		reg-names = "link", "function", "cache";
 		interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
 		clocks = <&cru ACLK_RKVDEC1>, <&cru HCLK_RKVDEC1>, <&cru CLK_RKVDEC1_CA>,
 			 <&cru CLK_RKVDEC1_CORE>, <&cru CLK_RKVDEC1_HEVC_CA>;
diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index d905a0777f93..dd1ac01ee29b 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -242,6 +242,7 @@ CONFIG_PCIE_XILINX_DMA_PL=y
 CONFIG_PCIE_XILINX_NWL=y
 CONFIG_PCIE_XILINX_CPM=y
 CONFIG_PCI_J721E_HOST=m
+CONFIG_PCI_SKY1_HOST=m
 CONFIG_PCI_IMX6_HOST=y
 CONFIG_PCI_LAYERSCAPE=y
 CONFIG_PCI_HISI=y
@@ -684,6 +685,7 @@ CONFIG_PINCTRL_SDM660=y
 CONFIG_PINCTRL_SDM670=y
 CONFIG_PINCTRL_SDM845=y
 CONFIG_PINCTRL_SDX75=y
+CONFIG_PINCTRL_SKY1=y
 CONFIG_PINCTRL_SM4450=y
 CONFIG_PINCTRL_SM6115=y
 CONFIG_PINCTRL_SM6125=y
@@ -710,6 +712,7 @@ CONFIG_PINCTRL_SM8550_LPASS_LPI=m
 CONFIG_PINCTRL_SM8650_LPASS_LPI=m
 CONFIG_PINCTRL_SOPHGO_SG2000=y
 CONFIG_GPIO_ALTERA=m
+CONFIG_GPIO_CADENCE=m
 CONFIG_GPIO_DAVINCI=y
 CONFIG_GPIO_DWAPB=y
 CONFIG_GPIO_MB86S7X=y
diff --git a/arch/arm64/include/asm/barrier.h b/arch/arm64/include/asm/barrier.h
index 9495c4441a46..fbd71cd4ef4e 100644
--- a/arch/arm64/include/asm/barrier.h
+++ b/arch/arm64/include/asm/barrier.h
@@ -12,6 +12,7 @@
 #include <linux/kasan-checks.h>
 
 #include <asm/alternative-macros.h>
+#include <asm/vdso/processor.h>
 
 #define __nops(n)	".rept	" #n "\nnop\n.endr\n"
 #define nops(n)		asm volatile(__nops(n))
@@ -219,6 +220,28 @@ do {									\
 	(typeof(*ptr))VAL;						\
 })
 
+/* Re-declared here to avoid include dependency. */
+extern bool arch_timer_evtstrm_available(void);
+
+/*
+ * In the common case, cpu_poll_relax() sits waiting in __cmpwait_relaxed()/
+ * __cmpwait_relaxed_timeout() for the ptr value to change.
+ *
+ * Since this period is reasonably long, choose SMP_TIMEOUT_POLL_COUNT
+ * to be 1, so smp_cond_load_{relaxed,acquire}_timeout() does a
+ * time-check in each iteration.
+ */
+#define SMP_TIMEOUT_POLL_COUNT	1
+
+#define cpu_poll_relax(ptr, val, timeout_ns) do {			\
+	if (alternative_has_cap_unlikely(ARM64_HAS_WFXT))		\
+		__cmpwait_relaxed_timeout(ptr, val, timeout_ns);	\
+	else if (arch_timer_evtstrm_available())			\
+		__cmpwait_relaxed(ptr, val);				\
+	else								\
+		cpu_relax();						\
+} while (0)
+
 #include <asm-generic/barrier.h>
 
 #endif	/* __ASSEMBLER__ */
diff --git a/arch/arm64/include/asm/cmpxchg.h b/arch/arm64/include/asm/cmpxchg.h
index 6cf3cd6873f5..9e4cdc9e41d1 100644
--- a/arch/arm64/include/asm/cmpxchg.h
+++ b/arch/arm64/include/asm/cmpxchg.h
@@ -12,6 +12,7 @@
 
 #include <asm/barrier.h>
 #include <asm/lse.h>
+#include <asm/delay-const.h>
 
 /*
  * We need separate acquire parameters for ll/sc and lse, since the full
@@ -212,7 +213,8 @@ __CMPXCHG_GEN(_mb)
 
 #define __CMPWAIT_CASE(w, sfx, sz)					\
 static inline void __cmpwait_case_##sz(volatile void *ptr,		\
-				       unsigned long val)		\
+				       unsigned long val,		\
+				       u64 __maybe_unused timeout_ns)	\
 {									\
 	unsigned long tmp;						\
 									\
@@ -235,20 +237,52 @@ __CMPWAIT_CASE( ,  , 64);
 
 #undef __CMPWAIT_CASE
 
-#define __CMPWAIT_GEN(sfx)						\
-static __always_inline void __cmpwait##sfx(volatile void *ptr,		\
-				  unsigned long val,			\
-				  int size)				\
+#define __CMPWAIT_TIMEOUT_CASE(w, sfx, sz)				\
+static inline void __cmpwait_case_timeout_##sz(volatile void *ptr,	\
+					       unsigned long val,	\
+					       u64 timeout_ns)		\
+{									\
+	unsigned long tmp;						\
+	u64 ecycles = __delay_cycles() +				\
+			NSECS_TO_CYCLES(timeout_ns);			\
+	asm volatile(							\
+	"	sevl\n"							\
+	"	wfe\n"							\
+	"	ldxr" #sfx "\t%" #w "[tmp], %[v]\n"			\
+	"	eor	%" #w "[tmp], %" #w "[tmp], %" #w "[val]\n"	\
+	"	cbnz	%" #w "[tmp], 2f\n"				\
+	"	msr s0_3_c1_c0_0, %[ecycles]\n"				\
+	"2:"								\
+	: [tmp] "=&r" (tmp), [v] "+Q" (*(u##sz *)ptr)			\
+	: [val] "r" (val), [ecycles] "r" (ecycles));			\
+}
+
+__CMPWAIT_TIMEOUT_CASE(w, b, 8);
+__CMPWAIT_TIMEOUT_CASE(w, h, 16);
+__CMPWAIT_TIMEOUT_CASE(w,  , 32);
+__CMPWAIT_TIMEOUT_CASE( ,  , 64);
+
+#undef __CMPWAIT_TIMEOUT_CASE
+
+#define __CMPWAIT_GEN(timeout, sfx)					\
+static __always_inline void __cmpwait##timeout##sfx(volatile void *ptr,	\
+						    unsigned long val,	\
+						    u64 timeout_ns,	\
+						    int size)		\
 {									\
 	switch (size) {							\
 	case 1:								\
-		return __cmpwait_case##sfx##_8(ptr, (u8)val);		\
+		return __cmpwait_case##timeout##sfx##_8(ptr, (u8)val,	\
+							timeout_ns);	\
 	case 2:								\
-		return __cmpwait_case##sfx##_16(ptr, (u16)val);		\
+		return __cmpwait_case##timeout##sfx##_16(ptr, (u16)val,	\
+							 timeout_ns);	\
 	case 4:								\
-		return __cmpwait_case##sfx##_32(ptr, val);		\
+		return __cmpwait_case##timeout##sfx##_32(ptr, val,	\
+							 timeout_ns);	\
 	case 8:								\
-		return __cmpwait_case##sfx##_64(ptr, val);		\
+		return __cmpwait_case##timeout##sfx##_64(ptr, val,	\
+							 timeout_ns);	\
 	default:							\
 		BUILD_BUG();						\
 	}								\
@@ -256,11 +290,15 @@ static __always_inline void __cmpwait##sfx(volatile void *ptr,		\
 	unreachable();							\
 }
 
-__CMPWAIT_GEN()
+__CMPWAIT_GEN(        , )
+__CMPWAIT_GEN(_timeout, )
 
 #undef __CMPWAIT_GEN
 
-#define __cmpwait_relaxed(ptr, val) \
-	__cmpwait((ptr), (unsigned long)(val), sizeof(*(ptr)))
+#define __cmpwait_relaxed_timeout(ptr, val, timeout_ns)			\
+	__cmpwait_timeout((ptr), (unsigned long)(val), timeout_ns, sizeof(*(ptr)))
+
+#define __cmpwait_relaxed(ptr, val)					\
+	__cmpwait((ptr), (unsigned long)(val), 0, sizeof(*(ptr)))
 
 #endif	/* __ASM_CMPXCHG_H */
diff --git a/arch/arm64/include/asm/delay-const.h b/arch/arm64/include/asm/delay-const.h
new file mode 100644
index 000000000000..cb3988ff4e41
--- /dev/null
+++ b/arch/arm64/include/asm/delay-const.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+#ifndef _ASM_DELAY_CONST_H
+#define _ASM_DELAY_CONST_H
+
+#include <asm/param.h>	/* For HZ */
+
+/* 2**32 / 1000000 (rounded up) */
+#define __usecs_to_xloops_mult	0x10C7UL
+
+/* 2**32 / 1000000000 (rounded up) */
+#define __nsecs_to_xloops_mult	0x5UL
+
+extern unsigned long loops_per_jiffy;
+static inline unsigned long xloops_to_cycles(unsigned long xloops)
+{
+	return (xloops * loops_per_jiffy * HZ) >> 32;
+}
+
+#define USECS_TO_CYCLES(time_usecs) \
+	xloops_to_cycles((time_usecs) * __usecs_to_xloops_mult)
+
+#define NSECS_TO_CYCLES(time_nsecs) \
+	xloops_to_cycles((time_nsecs) * __nsecs_to_xloops_mult)
+
+u64 notrace __delay_cycles(void);
+
+#endif	/* _ASM_DELAY_CONST_H */
diff --git a/arch/arm64/include/asm/kvm_asm.h b/arch/arm64/include/asm/kvm_asm.h
index 37414440cee7..043495f7fc78 100644
--- a/arch/arm64/include/asm/kvm_asm.h
+++ b/arch/arm64/include/asm/kvm_asm.h
@@ -50,6 +50,9 @@
 
 #include <linux/mm.h>
 
+#define MARKER(m)				\
+	m, __after_##m = m - 1
+
 enum __kvm_host_smccc_func {
 	/* Hypercalls that are unavailable once pKVM has finalised. */
 	/* __KVM_HOST_SMCCC_FUNC___kvm_hyp_init */
@@ -59,8 +62,10 @@ enum __kvm_host_smccc_func {
 	__KVM_HOST_SMCCC_FUNC___kvm_enable_ssbs,
 	__KVM_HOST_SMCCC_FUNC___vgic_v3_init_lrs,
 	__KVM_HOST_SMCCC_FUNC___vgic_v3_get_gic_config,
+
+	MARKER(__KVM_HOST_SMCCC_FUNC_MIN_PKVM),
+
 	__KVM_HOST_SMCCC_FUNC___pkvm_prot_finalize,
-	__KVM_HOST_SMCCC_FUNC_MIN_PKVM = __KVM_HOST_SMCCC_FUNC___pkvm_prot_finalize,
 
 	/* Hypercalls that are always available and common to [nh]VHE/pKVM. */
 	__KVM_HOST_SMCCC_FUNC___kvm_adjust_pc,
@@ -72,11 +77,20 @@ enum __kvm_host_smccc_func {
 	__KVM_HOST_SMCCC_FUNC___kvm_tlb_flush_vmid_range,
 	__KVM_HOST_SMCCC_FUNC___kvm_flush_cpu_context,
 	__KVM_HOST_SMCCC_FUNC___kvm_timer_set_cntvoff,
+	__KVM_HOST_SMCCC_FUNC___tracing_load,
+	__KVM_HOST_SMCCC_FUNC___tracing_unload,
+	__KVM_HOST_SMCCC_FUNC___tracing_enable,
+	__KVM_HOST_SMCCC_FUNC___tracing_swap_reader,
+	__KVM_HOST_SMCCC_FUNC___tracing_update_clock,
+	__KVM_HOST_SMCCC_FUNC___tracing_reset,
+	__KVM_HOST_SMCCC_FUNC___tracing_enable_event,
+	__KVM_HOST_SMCCC_FUNC___tracing_write_event,
 	__KVM_HOST_SMCCC_FUNC___vgic_v3_save_aprs,
 	__KVM_HOST_SMCCC_FUNC___vgic_v3_restore_vmcr_aprs,
 	__KVM_HOST_SMCCC_FUNC___vgic_v5_save_apr,
 	__KVM_HOST_SMCCC_FUNC___vgic_v5_restore_vmcr_apr,
-	__KVM_HOST_SMCCC_FUNC_MAX_NO_PKVM = __KVM_HOST_SMCCC_FUNC___vgic_v5_restore_vmcr_apr,
+
+	MARKER(__KVM_HOST_SMCCC_FUNC_PKVM_ONLY),
 
 	/* Hypercalls that are available only when pKVM has finalised. */
 	__KVM_HOST_SMCCC_FUNC___pkvm_host_share_hyp,
@@ -100,14 +114,8 @@ enum __kvm_host_smccc_func {
 	__KVM_HOST_SMCCC_FUNC___pkvm_vcpu_load,
 	__KVM_HOST_SMCCC_FUNC___pkvm_vcpu_put,
 	__KVM_HOST_SMCCC_FUNC___pkvm_tlb_flush_vmid,
-	__KVM_HOST_SMCCC_FUNC___tracing_load,
-	__KVM_HOST_SMCCC_FUNC___tracing_unload,
-	__KVM_HOST_SMCCC_FUNC___tracing_enable,
-	__KVM_HOST_SMCCC_FUNC___tracing_swap_reader,
-	__KVM_HOST_SMCCC_FUNC___tracing_update_clock,
-	__KVM_HOST_SMCCC_FUNC___tracing_reset,
-	__KVM_HOST_SMCCC_FUNC___tracing_enable_event,
-	__KVM_HOST_SMCCC_FUNC___tracing_write_event,
+
+	MARKER(__KVM_HOST_SMCCC_FUNC_MAX)
 };
 
 #define DECLARE_KVM_VHE_SYM(sym)	extern char sym[]
diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h
index 851f6171751c..65eead8362e0 100644
--- a/arch/arm64/include/asm/kvm_host.h
+++ b/arch/arm64/include/asm/kvm_host.h
@@ -450,9 +450,6 @@ struct kvm_vcpu_fault_info {
 	r = __VNCR_START__ + ((VNCR_ ## r) / 8),	\
 	__after_##r = __MAX__(__before_##r - 1, r)
 
-#define MARKER(m)				\
-	m, __after_##m = m - 1
-
 enum vcpu_sysreg {
 	__INVALID_SYSREG__,   /* 0 is reserved as an invalid value */
 	MPIDR_EL1,	/* MultiProcessor Affinity Register */
@@ -1548,7 +1545,7 @@ static inline bool __vcpu_has_feature(const struct kvm_arch *ka, int feature)
 #define kvm_vcpu_has_feature(k, f)	__vcpu_has_feature(&(k)->arch, (f))
 #define vcpu_has_feature(v, f)	__vcpu_has_feature(&(v)->kvm->arch, (f))
 
-#define kvm_vcpu_initialized(v) vcpu_get_flag(vcpu, VCPU_INITIALIZED)
+#define kvm_vcpu_initialized(v) vcpu_get_flag(v, VCPU_INITIALIZED)
 
 int kvm_trng_call(struct kvm_vcpu *vcpu);
 #ifdef CONFIG_KVM
diff --git a/arch/arm64/include/asm/page.h b/arch/arm64/include/asm/page.h
index e25d0d18f6d7..58200de8a221 100644
--- a/arch/arm64/include/asm/page.h
+++ b/arch/arm64/include/asm/page.h
@@ -33,7 +33,7 @@ struct folio *vma_alloc_zeroed_movable_folio(struct vm_area_struct *vma,
 						unsigned long vaddr);
 #define vma_alloc_zeroed_movable_folio vma_alloc_zeroed_movable_folio
 
-bool tag_clear_highpages(struct page *to, int numpages);
+bool tag_clear_highpages(struct page *to, int numpages, bool clear_pages);
 #define __HAVE_ARCH_TAG_CLEAR_HIGHPAGES
 
 #define copy_user_page(to, from, vaddr, pg)	copy_page(to, from)
diff --git a/arch/arm64/include/asm/rqspinlock.h b/arch/arm64/include/asm/rqspinlock.h
index 9ea0a74e5892..a385603436e9 100644
--- a/arch/arm64/include/asm/rqspinlock.h
+++ b/arch/arm64/include/asm/rqspinlock.h
@@ -3,91 +3,6 @@
 #define _ASM_RQSPINLOCK_H
 
 #include <asm/barrier.h>
-
-/*
- * Hardcode res_smp_cond_load_acquire implementations for arm64 to a custom
- * version based on [0]. In rqspinlock code, our conditional expression involves
- * checking the value _and_ additionally a timeout. However, on arm64, the
- * WFE-based implementation may never spin again if no stores occur to the
- * locked byte in the lock word. As such, we may be stuck forever if
- * event-stream based unblocking is not available on the platform for WFE spin
- * loops (arch_timer_evtstrm_available).
- *
- * Once support for smp_cond_load_acquire_timewait [0] lands, we can drop this
- * copy-paste.
- *
- * While we rely on the implementation to amortize the cost of sampling
- * cond_expr for us, it will not happen when event stream support is
- * unavailable, time_expr check is amortized. This is not the common case, and
- * it would be difficult to fit our logic in the time_expr_ns >= time_limit_ns
- * comparison, hence just let it be. In case of event-stream, the loop is woken
- * up at microsecond granularity.
- *
- * [0]: https://lore.kernel.org/lkml/20250203214911.898276-1-ankur.a.arora@oracle.com
- */
-
-#ifndef smp_cond_load_acquire_timewait
-
-#define smp_cond_time_check_count	200
-
-#define __smp_cond_load_relaxed_spinwait(ptr, cond_expr, time_expr_ns,	\
-					 time_limit_ns) ({		\
-	typeof(ptr) __PTR = (ptr);					\
-	__unqual_scalar_typeof(*ptr) VAL;				\
-	unsigned int __count = 0;					\
-	for (;;) {							\
-		VAL = READ_ONCE(*__PTR);				\
-		if (cond_expr)						\
-			break;						\
-		cpu_relax();						\
-		if (__count++ < smp_cond_time_check_count)		\
-			continue;					\
-		if ((time_expr_ns) >= (time_limit_ns))			\
-			break;						\
-		__count = 0;						\
-	}								\
-	(typeof(*ptr))VAL;						\
-})
-
-#define __smp_cond_load_acquire_timewait(ptr, cond_expr,		\
-					 time_expr_ns, time_limit_ns)	\
-({									\
-	typeof(ptr) __PTR = (ptr);					\
-	__unqual_scalar_typeof(*ptr) VAL;				\
-	for (;;) {							\
-		VAL = smp_load_acquire(__PTR);				\
-		if (cond_expr)						\
-			break;						\
-		__cmpwait_relaxed(__PTR, VAL);				\
-		if ((time_expr_ns) >= (time_limit_ns))			\
-			break;						\
-	}								\
-	(typeof(*ptr))VAL;						\
-})
-
-#define smp_cond_load_acquire_timewait(ptr, cond_expr,			\
-				      time_expr_ns, time_limit_ns)	\
-({									\
-	__unqual_scalar_typeof(*ptr) _val;				\
-	int __wfe = arch_timer_evtstrm_available();			\
-									\
-	if (likely(__wfe)) {						\
-		_val = __smp_cond_load_acquire_timewait(ptr, cond_expr,	\
-							time_expr_ns,	\
-							time_limit_ns);	\
-	} else {							\
-		_val = __smp_cond_load_relaxed_spinwait(ptr, cond_expr,	\
-							time_expr_ns,	\
-							time_limit_ns);	\
-		smp_acquire__after_ctrl_dep();				\
-	}								\
-	(typeof(*ptr))_val;						\
-})
-
-#endif
-
-#define res_smp_cond_load_acquire(v, c) smp_cond_load_acquire_timewait(v, c, 0, 1)
-
 #include <asm-generic/rqspinlock.h>
 
 #endif /* _ASM_RQSPINLOCK_H */
diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c
index 176cbe8baad3..8bb2c7422cc8 100644
--- a/arch/arm64/kvm/arm.c
+++ b/arch/arm64/kvm/arm.c
@@ -824,6 +824,10 @@ int kvm_arch_vcpu_runnable(struct kvm_vcpu *v)
 {
 	bool irq_lines = *vcpu_hcr(v) & (HCR_VI | HCR_VF | HCR_VSE);
 
+	irq_lines |= (!irqchip_in_kernel(v->kvm) &&
+		      (kvm_timer_should_notify_user(v) ||
+		       kvm_pmu_should_notify_user(v)));
+
 	return ((irq_lines || kvm_vgic_vcpu_pending_irq(v))
 		&& !kvm_arm_vcpu_stopped(v) && !v->arch.pause);
 }
diff --git a/arch/arm64/kvm/config.c b/arch/arm64/kvm/config.c
index f35b8dddd7c1..0622162b089e 100644
--- a/arch/arm64/kvm/config.c
+++ b/arch/arm64/kvm/config.c
@@ -131,7 +131,6 @@ struct reg_feat_map_desc {
 	}
 
 #define FEAT_SPE		ID_AA64DFR0_EL1, PMSVer, IMP
-#define FEAT_SPE_FnE		ID_AA64DFR0_EL1, PMSVer, V1P2
 #define FEAT_BRBE		ID_AA64DFR0_EL1, BRBE, IMP
 #define FEAT_TRC_SR		ID_AA64DFR0_EL1, TraceVer, IMP
 #define FEAT_PMUv3		ID_AA64DFR0_EL1, PMUVer, IMP
@@ -192,7 +191,7 @@ struct reg_feat_map_desc {
 #define FEAT_SRMASK		ID_AA64MMFR4_EL1, SRMASK, IMP
 #define FEAT_PoPS		ID_AA64MMFR4_EL1, PoPS, IMP
 #define FEAT_PFAR		ID_AA64PFR1_EL1, PFAR, IMP
-#define FEAT_Debugv8p9		ID_AA64DFR0_EL1, PMUVer, V3P9
+#define FEAT_Debugv8p9		ID_AA64DFR0_EL1, DebugVer, V8P9
 #define FEAT_PMUv3_SS		ID_AA64DFR0_EL1, PMSS, IMP
 #define FEAT_SEBEP		ID_AA64DFR0_EL1, SEBEP, IMP
 #define FEAT_EBEP		ID_AA64DFR1_EL1, EBEP, IMP
@@ -283,7 +282,7 @@ static bool feat_anerr(struct kvm *kvm)
 static bool feat_sme_smps(struct kvm *kvm)
 {
 	/*
-	 * Revists this if KVM ever supports SME -- this really should
+	 * Revisit this if KVM ever supports SME -- this really should
 	 * look at the guest's view of SMIDR_EL1. Funnily enough, this
 	 * is not captured in the JSON file, but only as a note in the
 	 * ARM ARM.
@@ -295,17 +294,27 @@ static bool feat_sme_smps(struct kvm *kvm)
 static bool feat_spe_fds(struct kvm *kvm)
 {
 	/*
-	 * Revists this if KVM ever supports SPE -- this really should
+	 * Revisit this if KVM ever supports SPE -- this really should
 	 * look at the guest's view of PMSIDR_EL1.
 	 */
 	return (kvm_has_feat(kvm, FEAT_SPEv1p4) &&
 		(read_sysreg_s(SYS_PMSIDR_EL1) & PMSIDR_EL1_FDS));
 }
 
+static bool feat_spe_fne(struct kvm *kvm)
+{
+	/*
+	 * Revisit this if KVM ever supports SPE -- this really should
+	 * look at the guest's view of PMSIDR_EL1.
+	 */
+	return (kvm_has_feat(kvm, FEAT_SPEv1p2) &&
+		(read_sysreg_s(SYS_PMSIDR_EL1) & PMSIDR_EL1_FnE));
+}
+
 static bool feat_trbe_mpam(struct kvm *kvm)
 {
 	/*
-	 * Revists this if KVM ever supports both MPAM and TRBE --
+	 * Revisit this if KVM ever supports both MPAM and TRBE --
 	 * this really should look at the guest's view of TRBIDR_EL1.
 	 */
 	return (kvm_has_feat(kvm, FEAT_TRBE) &&
@@ -537,7 +546,7 @@ static const struct reg_bits_to_feat_map hdfgrtr_feat_map[] = {
 		   HDFGRTR_EL2_PMBPTR_EL1	|
 		   HDFGRTR_EL2_PMBLIMITR_EL1,
 		   FEAT_SPE),
-	NEEDS_FEAT(HDFGRTR_EL2_nPMSNEVFR_EL1, FEAT_SPE_FnE),
+	NEEDS_FEAT(HDFGRTR_EL2_nPMSNEVFR_EL1, feat_spe_fne),
 	NEEDS_FEAT(HDFGRTR_EL2_nBRBDATA		|
 		   HDFGRTR_EL2_nBRBCTL		|
 		   HDFGRTR_EL2_nBRBIDR,
@@ -605,7 +614,7 @@ static const struct reg_bits_to_feat_map hdfgwtr_feat_map[] = {
 		   HDFGWTR_EL2_PMBPTR_EL1	|
 		   HDFGWTR_EL2_PMBLIMITR_EL1,
 		   FEAT_SPE),
-	NEEDS_FEAT(HDFGWTR_EL2_nPMSNEVFR_EL1, FEAT_SPE_FnE),
+	NEEDS_FEAT(HDFGWTR_EL2_nPMSNEVFR_EL1, feat_spe_fne),
 	NEEDS_FEAT(HDFGWTR_EL2_nBRBDATA		|
 		   HDFGWTR_EL2_nBRBCTL,
 		   FEAT_BRBE),
diff --git a/arch/arm64/kvm/hyp/nvhe/hyp-main.c b/arch/arm64/kvm/hyp/nvhe/hyp-main.c
index 73f2e0221e70..06db299c37a8 100644
--- a/arch/arm64/kvm/hyp/nvhe/hyp-main.c
+++ b/arch/arm64/kvm/hyp/nvhe/hyp-main.c
@@ -709,6 +709,14 @@ static const hcall_t host_hcall[] = {
 	HANDLE_FUNC(__kvm_tlb_flush_vmid_range),
 	HANDLE_FUNC(__kvm_flush_cpu_context),
 	HANDLE_FUNC(__kvm_timer_set_cntvoff),
+	HANDLE_FUNC(__tracing_load),
+	HANDLE_FUNC(__tracing_unload),
+	HANDLE_FUNC(__tracing_enable),
+	HANDLE_FUNC(__tracing_swap_reader),
+	HANDLE_FUNC(__tracing_update_clock),
+	HANDLE_FUNC(__tracing_reset),
+	HANDLE_FUNC(__tracing_enable_event),
+	HANDLE_FUNC(__tracing_write_event),
 	HANDLE_FUNC(__vgic_v3_save_aprs),
 	HANDLE_FUNC(__vgic_v3_restore_vmcr_aprs),
 	HANDLE_FUNC(__vgic_v5_save_apr),
@@ -735,22 +743,16 @@ static const hcall_t host_hcall[] = {
 	HANDLE_FUNC(__pkvm_vcpu_load),
 	HANDLE_FUNC(__pkvm_vcpu_put),
 	HANDLE_FUNC(__pkvm_tlb_flush_vmid),
-	HANDLE_FUNC(__tracing_load),
-	HANDLE_FUNC(__tracing_unload),
-	HANDLE_FUNC(__tracing_enable),
-	HANDLE_FUNC(__tracing_swap_reader),
-	HANDLE_FUNC(__tracing_update_clock),
-	HANDLE_FUNC(__tracing_reset),
-	HANDLE_FUNC(__tracing_enable_event),
-	HANDLE_FUNC(__tracing_write_event),
 };
 
 static void handle_host_hcall(struct kvm_cpu_context *host_ctxt)
 {
 	DECLARE_REG(unsigned long, id, host_ctxt, 0);
-	unsigned long hcall_min = 0, hcall_max = -1;
+	unsigned long hcall_min = 0, hcall_max = __KVM_HOST_SMCCC_FUNC_MAX;
 	hcall_t hfn;
 
+	BUILD_BUG_ON(ARRAY_SIZE(host_hcall) != __KVM_HOST_SMCCC_FUNC_MAX);
+
 	/*
 	 * If pKVM has been initialised then reject any calls to the
 	 * early "privileged" hypercalls. Note that we cannot reject
@@ -763,16 +765,14 @@ static void handle_host_hcall(struct kvm_cpu_context *host_ctxt)
 	if (static_branch_unlikely(&kvm_protected_mode_initialized)) {
 		hcall_min = __KVM_HOST_SMCCC_FUNC_MIN_PKVM;
 	} else {
-		hcall_max = __KVM_HOST_SMCCC_FUNC_MAX_NO_PKVM;
+		hcall_max = __KVM_HOST_SMCCC_FUNC_PKVM_ONLY;
 	}
 
 	id &= ~ARM_SMCCC_CALL_HINTS;
 	id -= KVM_HOST_SMCCC_ID(0);
 
-	if (unlikely(id < hcall_min || id > hcall_max ||
-		     id >= ARRAY_SIZE(host_hcall))) {
+	if (unlikely(id < hcall_min || id >= hcall_max))
 		goto inval;
-	}
 
 	hfn = host_hcall[id];
 	if (unlikely(!hfn))
@@ -805,6 +805,10 @@ static void handle_host_smc(struct kvm_cpu_context *host_ctxt)
 	}
 
 	func_id &= ~ARM_SMCCC_CALL_HINTS;
+	if (upper_32_bits(func_id)) {
+		cpu_reg(host_ctxt, 0) = SMCCC_RET_NOT_SUPPORTED;
+		goto exit_skip_instr;
+	}
 
 	handled = kvm_host_psci_handler(host_ctxt, func_id);
 	if (!handled)
diff --git a/arch/arm64/kvm/hyp/nvhe/pkvm.c b/arch/arm64/kvm/hyp/nvhe/pkvm.c
index 7ed96d64d611..e7496eb85628 100644
--- a/arch/arm64/kvm/hyp/nvhe/pkvm.c
+++ b/arch/arm64/kvm/hyp/nvhe/pkvm.c
@@ -266,7 +266,8 @@ struct pkvm_hyp_vcpu *pkvm_load_hyp_vcpu(pkvm_handle_t handle,
 	if (hyp_vm->kvm.created_vcpus <= vcpu_idx)
 		goto unlock;
 
-	hyp_vcpu = hyp_vm->vcpus[vcpu_idx];
+	/* Pairs with smp_store_release() in register_hyp_vcpu(). */
+	hyp_vcpu = smp_load_acquire(&hyp_vm->vcpus[vcpu_idx]);
 	if (!hyp_vcpu)
 		goto unlock;
 
@@ -860,12 +861,30 @@ int __pkvm_init_vm(struct kvm *host_kvm, unsigned long vm_hva,
  *	     the page-aligned size of 'struct pkvm_hyp_vcpu'.
  * Return 0 on success, negative error code on failure.
  */
+static int register_hyp_vcpu(struct pkvm_hyp_vm *hyp_vm,
+			      struct pkvm_hyp_vcpu *hyp_vcpu)
+{
+	unsigned int idx = hyp_vcpu->vcpu.vcpu_idx;
+
+	if (idx >= hyp_vm->kvm.created_vcpus)
+		return -EINVAL;
+
+	if (hyp_vm->vcpus[idx])
+		return -EINVAL;
+
+	/*
+	 * Ensure the hyp_vcpu is initialised before publishing it to
+	 * the vCPU-load path via 'hyp_vm->vcpus[]'.
+	 */
+	smp_store_release(&hyp_vm->vcpus[idx], hyp_vcpu);
+	return 0;
+}
+
 int __pkvm_init_vcpu(pkvm_handle_t handle, struct kvm_vcpu *host_vcpu,
 		     unsigned long vcpu_hva)
 {
 	struct pkvm_hyp_vcpu *hyp_vcpu;
 	struct pkvm_hyp_vm *hyp_vm;
-	unsigned int idx;
 	int ret;
 
 	hyp_vcpu = map_donated_memory(vcpu_hva, sizeof(*hyp_vcpu));
@@ -884,18 +903,11 @@ int __pkvm_init_vcpu(pkvm_handle_t handle, struct kvm_vcpu *host_vcpu,
 	if (ret)
 		goto unlock;
 
-	idx = hyp_vcpu->vcpu.vcpu_idx;
-	if (idx >= hyp_vm->kvm.created_vcpus) {
-		ret = -EINVAL;
-		goto unlock;
-	}
-
-	if (hyp_vm->vcpus[idx]) {
-		ret = -EINVAL;
-		goto unlock;
+	ret = register_hyp_vcpu(hyp_vm, hyp_vcpu);
+	if (ret) {
+		unpin_host_vcpu(host_vcpu);
+		unpin_host_sve_state(hyp_vcpu);
 	}
-
-	hyp_vm->vcpus[idx] = hyp_vcpu;
 unlock:
 	hyp_spin_unlock(&vm_table_lock);
 
diff --git a/arch/arm64/kvm/hyp/nvhe/setup.c b/arch/arm64/kvm/hyp/nvhe/setup.c
index d8e5b563fd3d..d461981616d9 100644
--- a/arch/arm64/kvm/hyp/nvhe/setup.c
+++ b/arch/arm64/kvm/hyp/nvhe/setup.c
@@ -312,15 +312,15 @@ void __noreturn __pkvm_init_finalise(void)
 	};
 	pkvm_pgtable.mm_ops = &pkvm_pgtable_mm_ops;
 
-	ret = fix_host_ownership();
+	ret = fix_hyp_pgtable_refcnt();
 	if (ret)
 		goto out;
 
-	ret = fix_hyp_pgtable_refcnt();
+	ret = hyp_create_fixmap();
 	if (ret)
 		goto out;
 
-	ret = hyp_create_fixmap();
+	ret = fix_host_ownership();
 	if (ret)
 		goto out;
 
diff --git a/arch/arm64/kvm/vgic/vgic-mmio-v2.c b/arch/arm64/kvm/vgic/vgic-mmio-v2.c
index 406845b3117c..0643e333db35 100644
--- a/arch/arm64/kvm/vgic/vgic-mmio-v2.c
+++ b/arch/arm64/kvm/vgic/vgic-mmio-v2.c
@@ -91,7 +91,7 @@ static int vgic_mmio_uaccess_write_v2_misc(struct kvm_vcpu *vcpu,
 		 * migration from old kernels to new kernels with legacy
 		 * userspace.
 		 */
-		reg = FIELD_GET(GICD_IIDR_REVISION_MASK, reg);
+		reg = FIELD_GET(GICD_IIDR_REVISION_MASK, val);
 		switch (reg) {
 		case KVM_VGIC_IMP_REV_2:
 		case KVM_VGIC_IMP_REV_3:
diff --git a/arch/arm64/kvm/vgic/vgic-mmio-v3.c b/arch/arm64/kvm/vgic/vgic-mmio-v3.c
index 89edb84d1ac6..5913a20d8301 100644
--- a/arch/arm64/kvm/vgic/vgic-mmio-v3.c
+++ b/arch/arm64/kvm/vgic/vgic-mmio-v3.c
@@ -194,7 +194,7 @@ static int vgic_mmio_uaccess_write_v3_misc(struct kvm_vcpu *vcpu,
 		if ((reg ^ val) & ~GICD_IIDR_REVISION_MASK)
 			return -EINVAL;
 
-		reg = FIELD_GET(GICD_IIDR_REVISION_MASK, reg);
+		reg = FIELD_GET(GICD_IIDR_REVISION_MASK, val);
 		switch (reg) {
 		case KVM_VGIC_IMP_REV_2:
 		case KVM_VGIC_IMP_REV_3:
diff --git a/arch/arm64/lib/delay.c b/arch/arm64/lib/delay.c
index e278e060e78a..dfb102ce3009 100644
--- a/arch/arm64/lib/delay.c
+++ b/arch/arm64/lib/delay.c
@@ -12,17 +12,11 @@
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/timex.h>
+#include <kunit/visibility.h>
+#include <asm/delay-const.h>
 
 #include <clocksource/arm_arch_timer.h>
 
-#define USECS_TO_CYCLES(time_usecs)			\
-	xloops_to_cycles((time_usecs) * 0x10C7UL)
-
-static inline unsigned long xloops_to_cycles(unsigned long xloops)
-{
-	return (xloops * loops_per_jiffy * HZ) >> 32;
-}
-
 /*
  * Force the use of CNTVCT_EL0 in order to have the same base as WFxT.
  * This avoids some annoying issues when CNTVOFF_EL2 is not reset 0 on a
@@ -32,11 +26,12 @@ static inline unsigned long xloops_to_cycles(unsigned long xloops)
  * Note that userspace cannot change the offset behind our back either,
  * as the vcpu mutex is held as long as KVM_RUN is in progress.
  */
-static cycles_t notrace __delay_cycles(void)
+u64 notrace __delay_cycles(void)
 {
 	guard(preempt_notrace)();
 	return __arch_counter_get_cntvct_stable();
 }
+EXPORT_SYMBOL_IF_KUNIT(__delay_cycles);
 
 void __delay(unsigned long cycles)
 {
@@ -73,12 +68,12 @@ EXPORT_SYMBOL(__const_udelay);
 
 void __udelay(unsigned long usecs)
 {
-	__const_udelay(usecs * 0x10C7UL); /* 2**32 / 1000000 (rounded up) */
+	__const_udelay(usecs * __usecs_to_xloops_mult);
 }
 EXPORT_SYMBOL(__udelay);
 
 void __ndelay(unsigned long nsecs)
 {
-	__const_udelay(nsecs * 0x5UL); /* 2**32 / 1000000000 (rounded up) */
+	__const_udelay(nsecs * __nsecs_to_xloops_mult);
 }
 EXPORT_SYMBOL(__ndelay);
diff --git a/arch/arm64/mm/fault.c b/arch/arm64/mm/fault.c
index 0f3c5c7ca054..739800835920 100644
--- a/arch/arm64/mm/fault.c
+++ b/arch/arm64/mm/fault.c
@@ -1018,7 +1018,7 @@ struct folio *vma_alloc_zeroed_movable_folio(struct vm_area_struct *vma,
 	return vma_alloc_folio(flags, 0, vma, vaddr);
 }
 
-bool tag_clear_highpages(struct page *page, int numpages)
+bool tag_clear_highpages(struct page *page, int numpages, bool clear_pages)
 {
 	/*
 	 * Check if MTE is supported and fall back to clear_highpage().
@@ -1026,13 +1026,16 @@ bool tag_clear_highpages(struct page *page, int numpages)
 	 * post_alloc_hook() will invoke tag_clear_highpages().
 	 */
 	if (!system_supports_mte())
-		return false;
+		return clear_pages;
 
 	/* Newly allocated pages, shouldn't have been tagged yet */
 	for (int i = 0; i < numpages; i++, page++) {
 		WARN_ON_ONCE(!try_page_mte_tagging(page));
-		mte_zero_clear_page_tags(page_address(page));
+		if (clear_pages)
+			mte_zero_clear_page_tags(page_address(page));
+		else
+			mte_clear_page_tags(page_address(page));
 		set_page_mte_tagged(page);
 	}
-	return true;
+	return false;
 }
diff --git a/arch/m68k/Kconfig.machine b/arch/m68k/Kconfig.machine
index 624e6b27f394..cff990c319cb 100644
--- a/arch/m68k/Kconfig.machine
+++ b/arch/m68k/Kconfig.machine
@@ -277,16 +277,16 @@ config M5407C3
 	  Support for the Motorola M5407C3 board.
 
 config AMCORE
-	bool "Sysam AMCORE board support"
+	bool "Kernelspace AMCORE board support"
 	depends on M5307
 	help
-	  Support for the Sysam AMCORE open-hardware generic board.
+	  Support for the Kernelspace AMCORE open-hardware generic board.
 
 config STMARK2
-	bool "Sysam stmark2 board support"
+	bool "Kernelspace stmark2 board support"
 	depends on M5441x
 	help
-	  Support for the Sysam stmark2 open-hardware generic board.
+	  Support for the Kernelspace stmark2 open-hardware generic board.
 
 config FIREBEE
 	bool "FireBee board support"
diff --git a/arch/m68k/coldfire/amcore.c b/arch/m68k/coldfire/amcore.c
index c6cb1a5cc1a5..6531ef62bc01 100644
--- a/arch/m68k/coldfire/amcore.c
+++ b/arch/m68k/coldfire/amcore.c
@@ -1,7 +1,7 @@
 /*
- * amcore.c -- Support for Sysam AMCORE open board
+ * amcore.c -- Support for Kernelspace AMCORE open board
  *
- * (C) Copyright 2016, Angelo Dureghello <angelo@sysam.it>
+ * (C) Copyright 2026, Angelo Dureghello <angelo@kernel-space.org>
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file COPYING in the main directory of this archive
diff --git a/arch/m68k/coldfire/stmark2.c b/arch/m68k/coldfire/stmark2.c
index 036a6ae5f599..85502b81175e 100644
--- a/arch/m68k/coldfire/stmark2.c
+++ b/arch/m68k/coldfire/stmark2.c
@@ -1,7 +1,7 @@
 /*
- * stmark2.c -- Support for Sysam AMCORE open board
+ * stmark2.c -- Support for Kernelspace AMCORE open board
  *
- * (C) Copyright 2017, Angelo Dureghello <angelo@sysam.it>
+ * (C) Copyright 2026, Angelo Dureghello <angelo@kernel-space.org>
  *
  * This file is subject to the terms and conditions of the GNU General Public
  * License.  See the file COPYING in the main directory of this archive
diff --git a/arch/m68k/configs/stmark2_defconfig b/arch/m68k/configs/stmark2_defconfig
index 515d9b208b10..b3fb95f73a95 100644
--- a/arch/m68k/configs/stmark2_defconfig
+++ b/arch/m68k/configs/stmark2_defconfig
@@ -2,16 +2,20 @@ CONFIG_LOCALVERSION="stmark2-001"
 CONFIG_DEFAULT_HOSTNAME="stmark2"
 CONFIG_SYSVIPC=y
 CONFIG_LOG_BUF_SHIFT=14
-CONFIG_NAMESPACES=y
 CONFIG_BLK_DEV_INITRD=y
+# CONFIG_RD_BZIP2 is not set
+# CONFIG_RD_LZMA is not set
+# CONFIG_RD_XZ is not set
+# CONFIG_RD_LZO is not set
+# CONFIG_RD_LZ4 is not set
+# CONFIG_RD_ZSTD is not set
 CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_EXPERT=y
 # CONFIG_FHANDLE is not set
 # CONFIG_AIO is not set
 # CONFIG_ADVISE_SYSCALLS is not set
 # CONFIG_MEMBARRIER is not set
-CONFIG_EXPERT=y
-# CONFIG_VM_EVENT_COUNTERS is not set
-# CONFIG_COMPAT_BRK is not set
+# CONFIG_KALLSYMS is not set
 CONFIG_COLDFIRE=y
 CONFIG_M5441x=y
 CONFIG_CLOCK_FREQ=240000000
@@ -21,10 +25,12 @@ CONFIG_RAMBASE=0x40000000
 CONFIG_RAMSIZE=0x8000000
 CONFIG_VECTORBASE=0x40000000
 CONFIG_KERNELBASE=0x40001000
-# CONFIG_BLK_DEV_BSG is not set
 CONFIG_BINFMT_FLAT=y
 CONFIG_BINFMT_ZFLAT=y
 CONFIG_BINFMT_MISC=y
+# CONFIG_COREDUMP is not set
+# CONFIG_COMPAT_BRK is not set
+# CONFIG_VM_EVENT_COUNTERS is not set
 CONFIG_DEVTMPFS=y
 CONFIG_DEVTMPFS_MOUNT=y
 # CONFIG_ALLOW_DEV_COREDUMP is not set
@@ -47,11 +53,11 @@ CONFIG_MTD_SPI_NOR=y
 # CONFIG_INPUT_MOUSE is not set
 CONFIG_SERIO_LIBPS2=y
 # CONFIG_UNIX98_PTYS is not set
-# CONFIG_DEVMEM is not set
 CONFIG_SERIAL_MCF=y
 CONFIG_SERIAL_MCF_BAUDRATE=115200
 CONFIG_SERIAL_MCF_CONSOLE=y
 # CONFIG_HW_RANDOM is not set
+# CONFIG_DEVMEM is not set
 CONFIG_SPI=y
 CONFIG_SPI_DEBUG=y
 CONFIG_SPI_FSL_DSPI=y
@@ -59,7 +65,7 @@ CONFIG_DEBUG_GPIO=y
 CONFIG_GPIO_SYSFS=y
 CONFIG_GPIO_GENERIC_PLATFORM=y
 # CONFIG_HWMON is not set
-# CONFIG_HID is not set
+# CONFIG_HID_SUPPORT is not set
 # CONFIG_USB_SUPPORT is not set
 CONFIG_MMC=y
 CONFIG_MMC_DEBUG=y
@@ -68,6 +74,8 @@ CONFIG_MMC_SDHCI_PLTFM=y
 CONFIG_MMC_SDHCI_ESDHC_MCF=y
 CONFIG_DMADEVICES=y
 CONFIG_MCF_EDMA=y
+# CONFIG_VIRTIO_MENU is not set
+# CONFIG_VHOST_MENU is not set
 CONFIG_EXT2_FS=y
 CONFIG_EXT2_FS_XATTR=y
 CONFIG_EXT2_FS_POSIX_ACL=y
@@ -79,14 +87,13 @@ CONFIG_EXT4_FS_SECURITY=y
 # CONFIG_DNOTIFY is not set
 # CONFIG_INOTIFY_USER is not set
 CONFIG_OVERLAY_FS=y
-CONFIG_FSCACHE=y
 # CONFIG_PROC_SYSCTL is not set
-CONFIG_CRAMFS=y
 CONFIG_SQUASHFS=y
-CONFIG_ROMFS_FS=y
-# CONFIG_CRYPTO_HW is not set
+CONFIG_XZ_DEC=y
 CONFIG_PRINTK_TIME=y
-# CONFIG_DEBUG_BUGVERBOSE is not set
+CONFIG_DYNAMIC_DEBUG_CORE=y
+# CONFIG_DEBUG_MISC is not set
 # CONFIG_SECTION_MISMATCH_WARN_ONLY is not set
-CONFIG_SLUB_DEBUG_ON=y
+# CONFIG_SLUB_DEBUG is not set
 CONFIG_PANIC_ON_OOPS=y
+# CONFIG_RUNTIME_TESTING_MENU is not set
diff --git a/arch/riscv/boot/dts/canaan/Makefile b/arch/riscv/boot/dts/canaan/Makefile
index 987d1f0c41f0..7d54ea5c6f3d 100644
--- a/arch/riscv/boot/dts/canaan/Makefile
+++ b/arch/riscv/boot/dts/canaan/Makefile
@@ -1,6 +1,8 @@
 # SPDX-License-Identifier: GPL-2.0
 dtb-$(CONFIG_ARCH_CANAAN) += canaan_kd233.dtb
 dtb-$(CONFIG_ARCH_CANAAN) += k210_generic.dtb
+dtb-$(CONFIG_ARCH_CANAAN) += k230-canmv.dtb
+dtb-$(CONFIG_ARCH_CANAAN) += k230-evb.dtb
 dtb-$(CONFIG_ARCH_CANAAN) += sipeed_maix_bit.dtb
 dtb-$(CONFIG_ARCH_CANAAN) += sipeed_maix_dock.dtb
 dtb-$(CONFIG_ARCH_CANAAN) += sipeed_maix_go.dtb
diff --git a/arch/riscv/boot/dts/canaan/k230-canmv.dts b/arch/riscv/boot/dts/canaan/k230-canmv.dts
new file mode 100644
index 000000000000..32ba53d17c00
--- /dev/null
+++ b/arch/riscv/boot/dts/canaan/k230-canmv.dts
@@ -0,0 +1,332 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2024 Yangyu Chen <cyy@cyyself.name>
+ */
+
+#include "k230.dtsi"
+
+/ {
+	model = "Canaan CanMV-K230";
+	compatible = "canaan,canmv-k230", "canaan,kendryte-k230";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	ddr: memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0x20000000>;
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
+
+&pinctrl {
+	jtag_pins: jtag-pins {
+		jtag-tck-cfg {
+			pinmux = <K230_PINMUX(2, 1)>;
+			slew-rate = <0>;
+			drive-strength = <4>;
+			power-source = <K230_MSC_1V8>;
+			input-enable;
+			bias-pull-down;
+			input-schmitt-enable;
+		};
+
+		jtag-tdi-cfg {
+			pinmux = <K230_PINMUX(3, 1)>;
+			slew-rate = <0>;
+			drive-strength = <4>;
+			power-source = <K230_MSC_1V8>;
+			input-enable;
+			bias-disable;
+		};
+
+		jtag-tdo-cfg {
+			pinmux = <K230_PINMUX(4, 1)>;
+			slew-rate = <0>;
+			drive-strength = <4>;
+			power-source = <K230_MSC_1V8>;
+			output-enable;
+			bias-disable;
+		};
+
+		jtag-tms-cfg {
+			pinmux = <K230_PINMUX(5, 1)>;
+			slew-rate = <0>;
+			drive-strength = <4>;
+			power-source = <K230_MSC_1V8>;
+			input-enable;
+			bias-pull-up;
+		};
+	};
+
+	uart2_pins: uart2-pins {
+		uart2-pins-cfg {
+			pinmux = <K230_PINMUX(5, 3)>, /* uart2 txd */
+				 <K230_PINMUX(6, 3)>; /* uart2 rxd */
+			slew-rate = <0>;
+			drive-strength = <4>;
+			power-source = <K230_MSC_1V8>;
+			input-enable;
+			output-enable;
+			bias-disable;
+		};
+	};
+
+	pwm2_pins: pwm2-pins {
+		pwm2-pin-cfg {
+			pinmux = <K230_PINMUX(7, 1)>;
+			slew-rate = <0>;
+			drive-strength = <7>;
+			power-source = <K230_MSC_1V8>;
+			input-enable;
+			output-enable;
+			bias-disable;
+			input-schmitt-enable;
+		};
+	};
+
+	pwm3_pins: pwm3-pins {
+		pwm3-pin-cfg {
+			pinmux = <K230_PINMUX(8, 1)>;
+			slew-rate = <0>;
+			drive-strength = <7>;
+			power-source = <K230_MSC_1V8>;
+			input-enable;
+			output-enable;
+			bias-disable;
+			input-schmitt-enable;
+		};
+	};
+
+	pwm4_pins: pwm4-pins {
+		pwm4-pin-cfg {
+			pinmux = <K230_PINMUX(9, 1)>;
+			slew-rate = <0>;
+			drive-strength = <7>;
+			power-source = <K230_MSC_1V8>;
+			input-enable;
+			output-enable;
+			bias-disable;
+			input-schmitt-enable;
+		};
+	};
+
+	iis_pins: iis-pins {
+		iis-clk-cfg {
+			pinmux = <K230_PINMUX(32, 2)>;
+			slew-rate = <0>;
+			drive-strength = <4>;
+			power-source = <K230_MSC_1V8>;
+			output-enable;
+			bias-disable;
+		};
+
+		iis-ws-cfg {
+			pinmux = <K230_PINMUX(33, 2)>;
+			slew-rate = <0>;
+			drive-strength = <4>;
+			power-source = <K230_MSC_1V8>;
+			output-enable;
+			bias-disable;
+		};
+
+		iis-din0-cfg {
+			pinmux = <K230_PINMUX(34, 2)>;
+			slew-rate = <0>;
+			drive-strength = <4>;
+			power-source = <K230_MSC_1V8>;
+			input-enable;
+			bias-disable;
+		};
+
+		iis-dout0-cfg {
+			pinmux = <K230_PINMUX(35, 2)>;
+			slew-rate = <0>;
+			drive-strength = <4>;
+			power-source = <K230_MSC_1V8>;
+			output-enable;
+			bias-disable;
+		};
+	};
+
+	uart4_pins: uart4-pins {
+		uart4-txd-cfg {
+			pinmux = <K230_PINMUX(36, 4)>;
+			slew-rate = <0>;
+			drive-strength = <7>;
+			power-source = <K230_MSC_1V8>;
+			output-enable;
+			bias-disable;
+			input-schmitt-enable;
+		};
+
+		uart4-rxd-cfg {
+			pinmux = <K230_PINMUX(37, 4)>;
+			slew-rate = <0>;
+			drive-strength = <7>;
+			power-source = <K230_MSC_1V8>;
+			input-enable;
+			bias-disable;
+			input-schmitt-enable;
+		};
+	};
+
+	uart0_pins: uart0-pins {
+		uart0-txd-cfg {
+			pinmux = <K230_PINMUX(38, 1)>;
+			slew-rate = <0>;
+			drive-strength = <7>;
+			power-source = <K230_MSC_1V8>;
+			output-enable;
+			bias-disable;
+			input-schmitt-enable;
+		};
+
+		uart0-rxd-cfg {
+			pinmux = <K230_PINMUX(39, 1)>;
+			slew-rate = <0>;
+			drive-strength = <7>;
+			power-source = <K230_MSC_1V8>;
+			input-enable;
+			bias-disable;
+			input-schmitt-enable;
+		};
+	};
+
+	iic1_pins: iic1-pins {
+		iic1-pins-cfg {
+			pinmux = <K230_PINMUX(40, 2)>, /* iic1 scl */
+				 <K230_PINMUX(41, 2)>; /* iic1 sda */
+			slew-rate = <0>;
+			drive-strength = <7>;
+			power-source = <K230_MSC_1V8>;
+			input-enable;
+			output-enable;
+			bias-pull-up;
+			input-schmitt-enable;
+		};
+	};
+
+	iic3_pins: iic3-pins {
+		iic3-pins-cfg {
+			pinmux = <K230_PINMUX(44, 2)>, /* iic3 scl */
+				 <K230_PINMUX(45, 2)>; /* iic3 sda */
+			slew-rate = <0>;
+			drive-strength = <7>;
+			power-source = <K230_MSC_1V8>;
+			input-enable;
+			output-enable;
+			bias-pull-up;
+			input-schmitt-enable;
+		};
+	};
+
+	iic4_pins: iic4-pins {
+		iic4-pins-cfg {
+			pinmux = <K230_PINMUX(46, 3)>, /* iic4 scl */
+				 <K230_PINMUX(47, 3)>; /* iic4 sda */
+			slew-rate = <0>;
+			drive-strength = <7>;
+			power-source = <K230_MSC_1V8>;
+			input-enable;
+			output-enable;
+			bias-pull-up;
+			input-schmitt-enable;
+		};
+	};
+
+	iic0_pins: iic0-pins {
+		iic0-pins-cfg {
+			pinmux = <K230_PINMUX(48, 3)>, /* iic0 scl */
+				 <K230_PINMUX(49, 3)>; /* iic0 sda */
+			slew-rate = <0>;
+			drive-strength = <7>;
+			power-source = <K230_MSC_1V8>;
+			input-enable;
+			output-enable;
+			bias-pull-up;
+			input-schmitt-enable;
+		};
+	};
+
+	uart3_pins: uart3-pins {
+		uart3-txd-cfg {
+			pinmux = <K230_PINMUX(50, 1)>;
+			slew-rate = <0>;
+			drive-strength = <7>;
+			power-source = <K230_MSC_3V3>;
+			output-enable;
+			bias-disable;
+			input-schmitt-enable;
+		};
+
+		uart3-rxd-cfg {
+			pinmux = <K230_PINMUX(51, 1)>;
+			slew-rate = <0>;
+			drive-strength = <7>;
+			power-source = <K230_MSC_3V3>;
+			input-enable;
+			bias-disable;
+			input-schmitt-enable;
+		};
+	};
+
+	key_pins: key-pins {
+		key-pins-cfg {
+			pinmux = <K230_PINMUX(52, 0)>, /* key0 */
+				 <K230_PINMUX(53, 0)>; /* key1 */
+			slew-rate = <0>;
+			drive-strength = <7>;
+			power-source = <K230_MSC_3V3>;
+			input-enable;
+			output-enable;
+			bias-disable;
+			input-schmitt-enable;
+		};
+	};
+
+	mmc1_pins: mmc1-pins {
+		mmc1-cmd-cfg {
+			pinmux = <K230_PINMUX(54, 2)>;
+			slew-rate = <0>;
+			drive-strength = <7>;
+			power-source = <K230_MSC_3V3>;
+			input-enable;
+			output-enable;
+			bias-pull-up;
+			input-schmitt-enable;
+		};
+
+		mmc1-clk-cfg {
+			pinmux = <K230_PINMUX(55, 2)>;
+			slew-rate = <0>;
+			drive-strength = <7>;
+			power-source = <K230_MSC_3V3>;
+			output-enable;
+			bias-disable;
+			input-schmitt-enable;
+		};
+
+		mmc1-data-cfg {
+			pinmux = <K230_PINMUX(56, 2)>, /* mmc1 data0 */
+				 <K230_PINMUX(57, 2)>, /* mmc1 data1 */
+				 <K230_PINMUX(58, 2)>, /* mmc1 data2 */
+				 <K230_PINMUX(59, 2)>; /* mmc1 data3 */
+			slew-rate = <0>;
+			drive-strength = <7>;
+			power-source = <K230_MSC_3V3>;
+			input-enable;
+			output-enable;
+			bias-pull-up;
+			input-schmitt-enable;
+		};
+	};
+};
diff --git a/arch/riscv/boot/dts/canaan/k230-evb.dts b/arch/riscv/boot/dts/canaan/k230-evb.dts
new file mode 100644
index 000000000000..bfa53f2e2403
--- /dev/null
+++ b/arch/riscv/boot/dts/canaan/k230-evb.dts
@@ -0,0 +1,28 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2024 Yangyu Chen <cyy@cyyself.name>
+ */
+
+#include "k230.dtsi"
+
+/ {
+	model = "Kendryte K230 EVB";
+	compatible = "canaan,k230-usip-lp3-evb", "canaan,kendryte-k230";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	ddr: memory@0 {
+		device_type = "memory";
+		reg = <0x0 0x0 0x0 0x20000000>;
+	};
+};
+
+&uart0 {
+	status = "okay";
+};
diff --git a/arch/riscv/boot/dts/canaan/k230-pinctrl.h b/arch/riscv/boot/dts/canaan/k230-pinctrl.h
new file mode 100644
index 000000000000..63dd999ca55b
--- /dev/null
+++ b/arch/riscv/boot/dts/canaan/k230-pinctrl.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */
+/*
+ * Copyright (C) 2024 Canaan Bright Sight Co. Ltd
+ * Copyright (C) 2024 Ze Huang <18771902331@163.com>
+ */
+
+#ifndef _K230_PINCTRL_H
+#define _K230_PINCTRL_H
+
+#define K230_MSC_3V3 0
+#define K230_MSC_1V8 1
+
+#define BANK_VOLTAGE_DEFAULT       K230_MSC_1V8
+#define BANK_VOLTAGE_IO50_IO61     K230_MSC_3V3
+
+#define K230_PINMUX(pin, mode) (((pin) << 8) | (mode))
+
+#endif /* _K230_PINCTRL_H */
diff --git a/arch/riscv/boot/dts/canaan/k230.dtsi b/arch/riscv/boot/dts/canaan/k230.dtsi
new file mode 100644
index 000000000000..a73b1926ab93
--- /dev/null
+++ b/arch/riscv/boot/dts/canaan/k230.dtsi
@@ -0,0 +1,157 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2024 Yangyu Chen <cyy@cyyself.name>
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/reset/canaan,k230-rst.h>
+#include "k230-pinctrl.h"
+
+/dts-v1/;
+/ {
+	#address-cells = <2>;
+	#size-cells = <2>;
+	compatible = "canaan,kendryte-k230";
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		timebase-frequency = <27000000>;
+
+		cpu@0 {
+			compatible = "thead,c908", "riscv";
+			device_type = "cpu";
+			reg = <0>;
+			riscv,isa = "rv64imafdcbv_zicbom_zicbop_zicboz_zicntr_zicsr_zifencei_zihpm_zfh_zba_zbb_zbc_zbs_zvfh_svpbmt";
+			riscv,isa-base = "rv64i";
+			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "zicbom",
+					       "zicbop", "zicboz", "zicntr", "zicsr", "zifencei",
+					       "zihpm", "zfh", "zba", "zbb", "zbc", "zbs", "zvfh",
+					       "svpbmt";
+			riscv,cbom-block-size = <64>;
+			riscv,cbop-block-size = <64>;
+			riscv,cboz-block-size = <64>;
+			d-cache-block-size = <64>;
+			d-cache-sets = <128>;
+			d-cache-size = <32768>;
+			i-cache-block-size = <64>;
+			i-cache-sets = <128>;
+			i-cache-size = <32768>;
+			next-level-cache = <&l2_cache>;
+			mmu-type = "riscv,sv39";
+
+			cpu0_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#interrupt-cells = <1>;
+			};
+		};
+
+		l2_cache: l2-cache {
+			compatible = "cache";
+			cache-block-size = <64>;
+			cache-level = <2>;
+			cache-size = <262144>;
+			cache-sets = <256>;
+			cache-unified;
+		};
+	};
+
+	apb_clk: apb-clk-clock {
+		compatible = "fixed-clock";
+		clock-frequency = <50000000>;
+		clock-output-names = "apb_clk";
+		#clock-cells = <0>;
+	};
+
+	soc {
+		compatible = "simple-bus";
+		interrupt-parent = <&plic>;
+		#address-cells = <2>;
+		#size-cells = <2>;
+		dma-noncoherent;
+		ranges;
+
+		plic: interrupt-controller@f00000000 {
+			compatible = "canaan,k230-plic", "thead,c900-plic";
+			reg = <0xf 0x00000000 0x0 0x04000000>;
+			interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>;
+			interrupt-controller;
+			#address-cells = <0>;
+			#interrupt-cells = <2>;
+			riscv,ndev = <208>;
+		};
+
+		clint: timer@f04000000 {
+			compatible = "canaan,k230-clint", "thead,c900-clint";
+			reg = <0xf 0x04000000 0x0 0x00010000>;
+			interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>;
+		};
+
+		rst: reset-controller@91101000 {
+			compatible = "canaan,k230-rst";
+			reg = <0x0 0x91101000 0x0 0x1000>;
+			#reset-cells = <1>;
+		};
+
+		pinctrl: pinctrl@91105000 {
+			compatible = "canaan,k230-pinctrl";
+			reg = <0x0 0x91105000 0x0 0x100>;
+		};
+
+		uart0: serial@91400000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x0 0x91400000 0x0 0x1000>;
+			clocks = <&apb_clk>;
+			interrupts = <16 IRQ_TYPE_LEVEL_HIGH>;
+			reg-io-width = <4>;
+			reg-shift = <2>;
+			resets = <&rst RST_UART0>;
+			status = "disabled";
+		};
+
+		uart1: serial@91401000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x0 0x91401000 0x0 0x1000>;
+			clocks = <&apb_clk>;
+			interrupts = <17 IRQ_TYPE_LEVEL_HIGH>;
+			reg-io-width = <4>;
+			reg-shift = <2>;
+			resets = <&rst RST_UART1>;
+			status = "disabled";
+		};
+
+		uart2: serial@91402000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x0 0x91402000 0x0 0x1000>;
+			clocks = <&apb_clk>;
+			interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
+			reg-io-width = <4>;
+			reg-shift = <2>;
+			resets = <&rst RST_UART2>;
+			status = "disabled";
+		};
+
+		uart3: serial@91403000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x0 0x91403000 0x0 0x1000>;
+			clocks = <&apb_clk>;
+			interrupts = <19 IRQ_TYPE_LEVEL_HIGH>;
+			reg-io-width = <4>;
+			reg-shift = <2>;
+			resets = <&rst RST_UART3>;
+			status = "disabled";
+		};
+
+		uart4: serial@91404000 {
+			compatible = "snps,dw-apb-uart";
+			reg = <0x0 0x91404000 0x0 0x1000>;
+			clocks = <&apb_clk>;
+			interrupts = <20 IRQ_TYPE_LEVEL_HIGH>;
+			reg-io-width = <4>;
+			reg-shift = <2>;
+			resets = <&rst RST_UART4>;
+			status = "disabled";
+		};
+	};
+};
diff --git a/arch/riscv/boot/dts/microchip/pic64gx-curiosity-kit.dts b/arch/riscv/boot/dts/microchip/pic64gx-curiosity-kit.dts
index 2f2ccd77af30..ef5bff3093fc 100644
--- a/arch/riscv/boot/dts/microchip/pic64gx-curiosity-kit.dts
+++ b/arch/riscv/boot/dts/microchip/pic64gx-curiosity-kit.dts
@@ -63,10 +63,6 @@ hss: hss-buffer@bfc00000 {
 };
 
 &gpio0 {
-	interrupts = <13>, <14>, <15>, <16>,
-		     <17>, <18>, <19>, <20>,
-		     <21>, <22>, <23>, <24>,
-		     <25>, <26>;
 	status ="okay";
 	gpio-line-names =
 		"", "", "", "", "", "", "", "",
@@ -74,12 +70,6 @@ &gpio0 {
 };
 
 &gpio1 {
-	interrupts = <27>, <28>, <29>, <30>,
-		     <31>, <32>, <33>, <34>,
-		     <35>, <36>, <37>, <38>,
-		     <39>, <40>, <41>, <42>,
-		     <43>, <44>, <45>, <46>,
-		     <47>, <48>, <49>, <50>;
 	status ="okay";
 	gpio-line-names =
 		"", "", "LED1", "LED2", "LED3", "LED4", "LED5", "LED6",
@@ -88,14 +78,6 @@ &gpio1 {
 };
 
 &gpio2 {
-	interrupts = <53>, <53>, <53>, <53>,
-		     <53>, <53>, <53>, <53>,
-		     <53>, <53>, <53>, <53>,
-		     <53>, <53>, <53>, <53>,
-		     <53>, <53>, <53>, <53>,
-		     <53>, <53>, <53>, <53>,
-		     <53>, <53>, <53>, <53>,
-		     <53>, <53>, <53>, <53>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&mdio1_gpio>, <&spi0_gpio>, <&can0_gpio>, <&pcie_gpio>,
 		    <&qspi_gpio>, <&uart3_gpio>, <&uart4_gpio>, <&can1_gpio>;
@@ -107,6 +89,43 @@ &gpio2 {
 		"DIP4", "USR_IO11", "", "", "SWITCH1", "", "", "";
 };
 
+&i2c0 {
+	status = "okay";
+};
+
+&i2c1 {
+	status = "okay";
+};
+
+&irqmux {
+	interrupt-map = <0 &plic 13>, <1 &plic 14>, <2 &plic 15>,
+			<3 &plic 16>, <4 &plic 17>, <5 &plic 18>,
+			<6 &plic 19>, <7 &plic 20>, <8 &plic 21>,
+			<9 &plic 22>, <10 &plic 23>, <11 &plic 24>,
+			<12 &plic 25>, <13 &plic 26>,
+
+			<32 &plic 27>, <33 &plic 28>, <34 &plic 29>,
+			<35 &plic 30>, <36 &plic 31>, <37 &plic 32>,
+			<38 &plic 33>, <39 &plic 34>, <40 &plic 35>,
+			<41 &plic 36>, <42 &plic 37>, <43 &plic 38>,
+			<44 &plic 39>, <45 &plic 40>, <46 &plic 41>,
+			<47 &plic 42>, <48 &plic 43>, <49 &plic 44>,
+			<50 &plic 45>, <51 &plic 46>, <52 &plic 47>,
+			<53 &plic 48>, <54 &plic 49>, <55 &plic 50>,
+
+			<64 &plic 53>, <65 &plic 53>, <66 &plic 53>,
+			<67 &plic 53>, <68 &plic 53>, <69 &plic 53>,
+			<70 &plic 53>, <71 &plic 53>, <72 &plic 53>,
+			<73 &plic 53>, <74 &plic 53>, <75 &plic 53>,
+			<76 &plic 53>, <77 &plic 53>, <78 &plic 53>,
+			<79 &plic 53>, <80 &plic 53>, <81 &plic 53>,
+			<82 &plic 53>, <83 &plic 53>, <84 &plic 53>,
+			<85 &plic 53>, <86 &plic 53>, <87 &plic 53>,
+			<88 &plic 53>, <89 &plic 53>, <90 &plic 53>,
+			<91 &plic 53>, <92 &plic 53>, <93 &plic 53>,
+			<94 &plic 53>, <95 &plic 53>;
+};
+
 &mac0 {
 	status = "okay";
 	phy-mode = "sgmii";
@@ -123,14 +142,6 @@ &mbox {
 	status = "okay";
 };
 
-&i2c0 {
-	status = "okay";
-};
-
-&i2c1 {
-	status = "okay";
-};
-
 &mmc {
 	bus-width = <4>;
 	disable-wp;
diff --git a/arch/riscv/boot/dts/microchip/pic64gx.dtsi b/arch/riscv/boot/dts/microchip/pic64gx.dtsi
index c164d7bc270a..5cf3e3de0e06 100644
--- a/arch/riscv/boot/dts/microchip/pic64gx.dtsi
+++ b/arch/riscv/boot/dts/microchip/pic64gx.dtsi
@@ -295,6 +295,14 @@ mss_top_sysreg: syscon@20002000 {
 			#size-cells = <1>;
 			#reset-cells = <1>;
 
+			irqmux: interrupt-controller@54 {
+				compatible = "microchip,pic64gx-irqmux", "microchip,mpfs-irqmux";
+				reg = <0x54 0x4>;
+				#address-cells = <0>;
+				#interrupt-cells = <1>;
+				interrupt-map-mask = <0x7f>;
+			};
+
 			iomux0: pinctrl@200 {
 				compatible = "microchip,pic64gx-pinctrl-iomux0",
 					     "microchip,mpfs-pinctrl-iomux0";
@@ -459,8 +467,8 @@ mac0: ethernet@20110000 {
 			interrupts = <64>, <65>, <66>, <67>, <68>, <69>;
 			/* Filled in by a bootloader */
 			local-mac-address = [00 00 00 00 00 00];
-			clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>;
-			clock-names = "pclk", "hclk";
+			clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>, <&refclk>;
+			clock-names = "pclk", "hclk", "tsu_clk";
 			resets = <&mss_top_sysreg CLK_MAC0>;
 			status = "disabled";
 		};
@@ -475,8 +483,8 @@ mac1: ethernet@20112000 {
 			interrupts = <70>, <71>, <72>, <73>, <74>, <75>;
 			/* Filled in by a bootloader */
 			local-mac-address = [00 00 00 00 00 00];
-			clocks = <&clkcfg CLK_MAC1>, <&clkcfg CLK_AHB>;
-			clock-names = "pclk", "hclk";
+			clocks = <&clkcfg CLK_MAC0>, <&clkcfg CLK_AHB>, <&refclk>;
+			clock-names = "pclk", "hclk", "tsu_clk";
 			resets = <&mss_top_sysreg CLK_MAC1>;
 			status = "disabled";
 		};
@@ -484,9 +492,13 @@ mac1: ethernet@20112000 {
 		gpio0: gpio@20120000 {
 			compatible = "microchip,pic64gx-gpio", "microchip,mpfs-gpio";
 			reg = <0x0 0x20120000 0x0 0x1000>;
-			interrupt-parent = <&plic>;
+			interrupt-parent = <&irqmux>;
 			interrupt-controller;
 			#interrupt-cells = <1>;
+			interrupts = <0>, <1>, <2>, <3>,
+				     <4>, <5>, <6>, <7>,
+				     <8>, <9>, <10>, <11>,
+				     <12>, <13>;
 			clocks = <&clkcfg CLK_GPIO0>;
 			gpio-controller;
 			#gpio-cells = <2>;
@@ -497,9 +509,15 @@ gpio0: gpio@20120000 {
 		gpio1: gpio@20121000 {
 			compatible = "microchip,pic64gx-gpio", "microchip,mpfs-gpio";
 			reg = <0x0 0x20121000 0x0 0x1000>;
-			interrupt-parent = <&plic>;
+			interrupt-parent = <&irqmux>;
 			interrupt-controller;
 			#interrupt-cells = <1>;
+			interrupts = <32>, <33>, <34>, <35>,
+				     <36>, <37>, <38>, <39>,
+				     <40>, <41>, <42>, <43>,
+				     <44>, <45>, <46>, <47>,
+				     <48>, <49>, <50>, <51>,
+				     <52>, <53>, <54>, <55>;
 			clocks = <&clkcfg CLK_GPIO1>;
 			gpio-controller;
 			#gpio-cells = <2>;
@@ -510,9 +528,17 @@ gpio1: gpio@20121000 {
 		gpio2: gpio@20122000 {
 			compatible = "microchip,pic64gx-gpio", "microchip,mpfs-gpio";
 			reg = <0x0 0x20122000 0x0 0x1000>;
-			interrupt-parent = <&plic>;
+			interrupt-parent = <&irqmux>;
 			interrupt-controller;
 			#interrupt-cells = <1>;
+			interrupts = <64>, <65>, <66>, <67>,
+				     <68>, <69>, <70>, <71>,
+				     <72>, <73>, <74>, <75>,
+				     <76>, <77>, <78>, <79>,
+				     <80>, <81>, <82>, <83>,
+				     <84>, <85>, <86>, <87>,
+				     <88>, <89>, <90>, <91>,
+				     <92>, <93>, <94>, <95>;
 			clocks = <&clkcfg CLK_GPIO2>;
 			gpio-controller;
 			#gpio-cells = <2>;
diff --git a/arch/riscv/boot/dts/sophgo/cv180x.dtsi b/arch/riscv/boot/dts/sophgo/cv180x.dtsi
index 06b0ce5a2db7..8446b4dfe1a1 100644
--- a/arch/riscv/boot/dts/sophgo/cv180x.dtsi
+++ b/arch/riscv/boot/dts/sophgo/cv180x.dtsi
@@ -417,7 +417,7 @@ sdhci1: mmc@4320000 {
 		};
 
 		dmac: dma-controller@4330000 {
-			compatible = "snps,axi-dma-1.01a";
+			compatible = "sophgo,cv1800b-axi-dma";
 			reg = <0x04330000 0x1000>;
 			interrupts = <SOC_PERIPHERAL_IRQ(13) IRQ_TYPE_LEVEL_HIGH>;
 			clocks = <&clk CLK_SDMA_AXI>, <&clk CLK_SDMA_AXI>;
diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
index 8cfe8033305d..11ab9fcee38a 100644
--- a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
@@ -463,6 +463,7 @@ GPOEN_ENABLE,
 			input-disable;
 			input-schmitt-disable;
 			slew-rate = <0>;
+			bootph-pre-ram;
 		};
 
 		mmc-pins {
diff --git a/arch/riscv/boot/dts/starfive/jh7110-milkv-marscm-lite.dts b/arch/riscv/boot/dts/starfive/jh7110-milkv-marscm-lite.dts
index 63aa94d65ab5..566b0bdc2800 100644
--- a/arch/riscv/boot/dts/starfive/jh7110-milkv-marscm-lite.dts
+++ b/arch/riscv/boot/dts/starfive/jh7110-milkv-marscm-lite.dts
@@ -13,7 +13,7 @@ / {
 
 &mmc0 {
 	bus-width = <4>;
-	cd-gpios = <&sysgpio 41 GPIO_ACTIVE_LOW>;
+	broken-cd;
 	disable-wp;
 };
 
diff --git a/arch/riscv/boot/dts/tenstorrent/blackhole.dtsi b/arch/riscv/boot/dts/tenstorrent/blackhole.dtsi
index 6408810d8d80..5f709e45d9b2 100644
--- a/arch/riscv/boot/dts/tenstorrent/blackhole.dtsi
+++ b/arch/riscv/boot/dts/tenstorrent/blackhole.dtsi
@@ -77,6 +77,54 @@ cpu3_intc: interrupt-controller {
 		};
 	};
 
+	pmu {
+		compatible = "riscv,pmu";
+		riscv,event-to-mhpmevent =
+			/* SBI_PMU_HW_CPU_CYCLES -> CPU cycles */
+			<0x00001 0x00000000 0x0001>,
+			/* SBI_PMU_HW_INSTRUCTIONS -> Instructions executed */
+			<0x00002 0x00000000 0x0004>,
+			/* SBI_PMU_HW_CACHE_REFERENCES -> I-cache/ITIM busy | D-cache/DTIM busy */
+			<0x00003 0x00000000 0x1801>,
+			/* SBI_PMU_HW_CACHE_MISSES -> I-cache miss | D-cache miss */
+			<0x00004 0x00000000 0x0302>,
+			/* SBI_PMU_HW_BRANCH_INSTRUCTIONS -> Conditional branch retired */
+			<0x00005 0x00000000 0x4000>,
+			/*
+			 * SBI_PMU_HW_BRANCH_MISSES ->
+			 * Branch direction misprediction | Branch/jump target misprediction
+			 */
+			<0x00006 0x00000000 0x6001>,
+			/* L1D_READ_MISS -> Data cache miss or MMIO access */
+			<0x10001 0x00000000 0x0202>,
+			/* L1D_WRITE_ACCESS -> Data cache write-back */
+			<0x10002 0x00000000 0x0402>,
+			/* L1I_READ_MISS -> Instruction cache miss */
+			<0x10009 0x00000000 0x0102>,
+			/* LL_READ_MISS -> UTLB miss */
+			<0x10011 0x00000000 0x2002>,
+			/* DTLB_READ_MISS -> Data TLB miss */
+			<0x10019 0x00000000 0x1002>,
+			/* ITLB_READ_MISS -> Instruction TLB miss */
+			<0x10021 0x00000000 0x0802>;
+		riscv,event-to-mhpmcounters =
+			<0x00001 0x00001 0x01>,
+			<0x00002 0x00002 0x04>,
+			<0x00003 0x00006 0x78>,
+			<0x10001 0x10002 0x78>,
+			<0x10009 0x10009 0x78>,
+			<0x10011 0x10011 0x78>,
+			<0x10019 0x10019 0x78>,
+			<0x10021 0x10021 0x78>;
+		riscv,raw-event-to-mhpmcounters =
+			/* Class 0: Instruction Commit Events, bits 8-25 variant */
+			<0x0 0x0 0xffffffff 0xfc0000ff 0x78>,
+			/* Class 1: Microarchitectural Events, bits 8-18 variant */
+			<0x0 0x1 0xffffffff 0xfff800ff 0x78>,
+			/* Class 2: Memory System Events, bits 8-13 variant */
+			<0x0 0x2 0xffffffff 0xffffc0ff 0x78>;
+	};
+
 	soc {
 		#address-cells = <2>;
 		#size-cells = <2>;
diff --git a/arch/riscv/kernel/copy-unaligned.S b/arch/riscv/kernel/copy-unaligned.S
index 2b3d9398c113..90f3549621f7 100644
--- a/arch/riscv/kernel/copy-unaligned.S
+++ b/arch/riscv/kernel/copy-unaligned.S
@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0 */
 /* Copyright (C) 2023 Rivos Inc. */
 
+#include <linux/cfi_types.h>
 #include <linux/linkage.h>
 #include <asm/asm.h>
 
@@ -9,7 +10,7 @@
 /* void __riscv_copy_words_unaligned(void *, const void *, size_t) */
 /* Performs a memcpy without aligning buffers, using word loads and stores. */
 /* Note: The size is truncated to a multiple of 8 * SZREG */
-SYM_FUNC_START(__riscv_copy_words_unaligned)
+SYM_TYPED_FUNC_START(__riscv_copy_words_unaligned)
 	andi  a4, a2, ~((8*SZREG)-1)
 	beqz  a4, 2f
 	add   a3, a1, a4
@@ -41,7 +42,7 @@ SYM_FUNC_END(__riscv_copy_words_unaligned)
 /* void __riscv_copy_bytes_unaligned(void *, const void *, size_t) */
 /* Performs a memcpy without aligning buffers, using only byte accesses. */
 /* Note: The size is truncated to a multiple of 8 */
-SYM_FUNC_START(__riscv_copy_bytes_unaligned)
+SYM_TYPED_FUNC_START(__riscv_copy_bytes_unaligned)
 	andi a4, a2, ~(8-1)
 	beqz a4, 2f
 	add  a3, a1, a4
diff --git a/arch/riscv/kernel/image-vars.h b/arch/riscv/kernel/image-vars.h
index 3bd9d06a8b8f..888bb1ddf945 100644
--- a/arch/riscv/kernel/image-vars.h
+++ b/arch/riscv/kernel/image-vars.h
@@ -32,6 +32,15 @@ __efistub___init_text_end	= __init_text_end;
 __efistub_sysfb_primary_display	= sysfb_primary_display;
 #endif
 
+#ifdef CONFIG_CC_IS_GCC
+/*
+ * Double-word integer shifts are used by the library code and so EFI stub as
+ * well. Not needed for clang and please let me know if anyone understands why.
+ */
+PROVIDE(__efistub___lshrdi3    = __lshrdi3);
+PROVIDE(__efistub___ashldi3    = __ashldi3);
+#endif /* CONFIG_CC_IS_GCC */
+
 #endif
 
 #endif /* __RISCV_KERNEL_IMAGE_VARS_H */
diff --git a/arch/riscv/kernel/vec-copy-unaligned.S b/arch/riscv/kernel/vec-copy-unaligned.S
index 7ce4de6f6e69..361039f7b944 100644
--- a/arch/riscv/kernel/vec-copy-unaligned.S
+++ b/arch/riscv/kernel/vec-copy-unaligned.S
@@ -2,6 +2,7 @@
 /* Copyright (C) 2024 Rivos Inc. */
 
 #include <linux/args.h>
+#include <linux/cfi_types.h>
 #include <linux/linkage.h>
 #include <asm/asm.h>
 
@@ -16,7 +17,7 @@
 /* void __riscv_copy_vec_words_unaligned(void *, const void *, size_t) */
 /* Performs a memcpy without aligning buffers, using word loads and stores. */
 /* Note: The size is truncated to a multiple of WORD_EEW */
-SYM_FUNC_START(__riscv_copy_vec_words_unaligned)
+SYM_TYPED_FUNC_START(__riscv_copy_vec_words_unaligned)
 	andi  a4, a2, ~(WORD_EEW-1)
 	beqz  a4, 2f
 	add   a3, a1, a4
@@ -38,7 +39,7 @@ SYM_FUNC_END(__riscv_copy_vec_words_unaligned)
 /* void __riscv_copy_vec_bytes_unaligned(void *, const void *, size_t) */
 /* Performs a memcpy without aligning buffers, using only byte accesses. */
 /* Note: The size is truncated to a multiple of 8 */
-SYM_FUNC_START(__riscv_copy_vec_bytes_unaligned)
+SYM_TYPED_FUNC_START(__riscv_copy_vec_bytes_unaligned)
 	andi a4, a2, ~(8-1)
 	beqz a4, 2f
 	add  a3, a1, a4
diff --git a/arch/s390/kvm/interrupt.c b/arch/s390/kvm/interrupt.c
index 07f59c3b9a7b..3bcdbbbb6891 100644
--- a/arch/s390/kvm/interrupt.c
+++ b/arch/s390/kvm/interrupt.c
@@ -3310,8 +3310,7 @@ static void aen_host_forward(unsigned long si)
 	struct zpci_gaite *gaite;
 	struct kvm *kvm;
 
-	gaite = (struct zpci_gaite *)aift->gait +
-		(si * sizeof(struct zpci_gaite));
+	gaite = aift->gait + si;
 	if (gaite->count == 0)
 		return;
 	if (gaite->aisb != 0)
diff --git a/arch/s390/kvm/pci.c b/arch/s390/kvm/pci.c
index 86d93e8dddae..eed45af1a92d 100644
--- a/arch/s390/kvm/pci.c
+++ b/arch/s390/kvm/pci.c
@@ -290,8 +290,7 @@ static int kvm_s390_pci_aif_enable(struct zpci_dev *zdev, struct zpci_fib *fib,
 				    phys_to_virt(fib->fmt0.aibv));
 
 	spin_lock_irq(&aift->gait_lock);
-	gaite = (struct zpci_gaite *)aift->gait + (zdev->aisb *
-						   sizeof(struct zpci_gaite));
+	gaite = aift->gait + zdev->aisb;
 
 	/* If assist not requested, host will get all alerts */
 	if (assist)
@@ -357,8 +356,7 @@ static int kvm_s390_pci_aif_disable(struct zpci_dev *zdev, bool force)
 	if (zdev->kzdev->fib.fmt0.aibv == 0)
 		goto out;
 	spin_lock_irq(&aift->gait_lock);
-	gaite = (struct zpci_gaite *)aift->gait + (zdev->aisb *
-						   sizeof(struct zpci_gaite));
+	gaite = aift->gait + zdev->aisb;
 	isc = gaite->gisc;
 	gaite->count--;
 	if (gaite->count == 0) {
diff --git a/certs/Kconfig b/certs/Kconfig
index 8e39a80c7abe..9d2bf7fb5b9e 100644
--- a/certs/Kconfig
+++ b/certs/Kconfig
@@ -6,14 +6,14 @@ config MODULE_SIG_KEY
 	default "certs/signing_key.pem"
 	depends on MODULE_SIG || (IMA_APPRAISE_MODSIG && MODULES)
 	help
-         Provide the file name of a private key/certificate in PEM format,
-         or a PKCS#11 URI according to RFC7512. The file should contain, or
-         the URI should identify, both the certificate and its corresponding
-         private key.
-
-         If this option is unchanged from its default "certs/signing_key.pem",
-         then the kernel will automatically generate the private key and
-         certificate as described in Documentation/admin-guide/module-signing.rst
+	 Provide the file name of a private key/certificate in PEM format,
+	 or a PKCS#11 URI according to RFC7512. The file should contain, or
+	 the URI should identify, both the certificate and its corresponding
+	 private key.
+
+	 If this option is unchanged from its default "certs/signing_key.pem",
+	 then the kernel will automatically generate the private key and
+	 certificate as described in Documentation/admin-guide/module-signing.rst
 
 choice
 	prompt "Type of module signing key to be generated"
diff --git a/crypto/authencesn.c b/crypto/authencesn.c
index af3d584e584f..522df41365d8 100644
--- a/crypto/authencesn.c
+++ b/crypto/authencesn.c
@@ -390,6 +390,11 @@ static int crypto_authenc_esn_create(struct crypto_template *tmpl,
 	auth = crypto_spawn_ahash_alg(&ctx->auth);
 	auth_base = &auth->base;
 
+	if (auth->digestsize > 0 && auth->digestsize < 4) {
+		err = -EINVAL;
+		goto err_free_inst;
+	}
+
 	err = crypto_grab_skcipher(&ctx->enc, aead_crypto_instance(inst),
 				   crypto_attr_alg_name(tb[2]), 0, mask);
 	if (err)
diff --git a/drivers/base/memory.c b/drivers/base/memory.c
index f806a683b767..6981b55d582a 100644
--- a/drivers/base/memory.c
+++ b/drivers/base/memory.c
@@ -1230,8 +1230,10 @@ void memblk_nr_poison_inc(unsigned long pfn)
 	const unsigned long block_id = pfn_to_block_id(pfn);
 	struct memory_block *mem = find_memory_block_by_id(block_id);
 
-	if (mem)
+	if (mem) {
 		atomic_long_inc(&mem->nr_hwpoison);
+		put_device(&mem->dev);
+	}
 }
 
 void memblk_nr_poison_sub(unsigned long pfn, long i)
@@ -1239,8 +1241,10 @@ void memblk_nr_poison_sub(unsigned long pfn, long i)
 	const unsigned long block_id = pfn_to_block_id(pfn);
 	struct memory_block *mem = find_memory_block_by_id(block_id);
 
-	if (mem)
+	if (mem) {
 		atomic_long_sub(i, &mem->nr_hwpoison);
+		put_device(&mem->dev);
+	}
 }
 
 static unsigned long memblk_nr_poison(struct memory_block *mem)
diff --git a/drivers/base/platform-msi.c b/drivers/base/platform-msi.c
index 70db08f3ac6f..69eed058eb20 100644
--- a/drivers/base/platform-msi.c
+++ b/drivers/base/platform-msi.c
@@ -61,10 +61,6 @@ static const struct msi_domain_template platform_msi_template = {
  * parent. The parent domain sets up the new domain. The domain has
  * a fixed size of @nvec. The domain is managed by devres and will
  * be removed when the device is removed.
- *
- * Note: For migration purposes this falls back to the original platform_msi code
- *	 up to the point where all platforms have been converted to the MSI
- *	 parent model.
  */
 int platform_device_msi_init_and_alloc_irqs(struct device *dev, unsigned int nvec,
 					    irq_write_msi_msg_t write_msi_msg)
diff --git a/drivers/base/regmap/regmap-sdw-mbq.c b/drivers/base/regmap/regmap-sdw-mbq.c
index 4533fe793c5f..2585933d4946 100644
--- a/drivers/base/regmap/regmap-sdw-mbq.c
+++ b/drivers/base/regmap/regmap-sdw-mbq.c
@@ -172,7 +172,7 @@ static int regmap_sdw_mbq_read(void *context, unsigned int reg, unsigned int *va
 	ret = regmap_sdw_mbq_read_impl(slave, reg, val, mbq_size);
 	if (ret == -ENODATA) {
 		if (!deferrable)
-			dev_warn(dev, "Defer on undeferable control: %x\n", reg);
+			dev_warn(dev, "Defer on undeferrable control: %x\n", reg);
 
 		ret = regmap_sdw_mbq_poll_busy(slave, reg, ctx);
 		if (ret)
diff --git a/drivers/block/loop.c b/drivers/block/loop.c
index 0000913f7efc..3ba06b632aa0 100644
--- a/drivers/block/loop.c
+++ b/drivers/block/loop.c
@@ -74,6 +74,14 @@ struct loop_device {
 	struct gendisk		*lo_disk;
 	struct mutex		lo_mutex;
 	bool			idr_visible;
+
+#ifdef CONFIG_DEBUG_AID_FOR_SYZBOT
+	pid_t clear_pid;
+	char clear_comm[TASK_COMM_LEN];
+	unsigned long clear_jiffies;
+	int clear_nr_entries;
+	unsigned long clear_entries[20];
+#endif
 };
 
 struct loop_cmd {
@@ -94,6 +102,26 @@ static DEFINE_IDR(loop_index_idr);
 static DEFINE_MUTEX(loop_ctl_mutex);
 static DEFINE_MUTEX(loop_validate_mutex);
 
+static struct file *check_file_not_null(struct loop_device *lo)
+{
+	struct file *file = READ_ONCE(lo->lo_backing_file);
+
+#ifdef CONFIG_DEBUG_AID_FOR_SYZBOT
+	if (!file)
+		pr_err("file == NULL\n");
+	else if (IS_ERR(file))
+		pr_err("IS_ERR(file)\n");
+	else
+		return file;
+	if (lo->clear_nr_entries) {
+		pr_err("Last __loop_clr_fd() call was %lu jiffies ago by %s (%d)\n",
+		       jiffies - lo->clear_jiffies, lo->clear_comm, lo->clear_pid);
+		stack_trace_print(lo->clear_entries, lo->clear_nr_entries, 4);
+	}
+#endif
+	return file;
+}
+
 /**
  * loop_global_lock_killable() - take locks for safe loop_validate_file() test
  *
@@ -250,7 +278,7 @@ static int lo_fallocate(struct loop_device *lo, struct request *rq, loff_t pos,
 	 * We use fallocate to manipulate the space mappings used by the image
 	 * a.k.a. discard/zerorange.
 	 */
-	struct file *file = lo->lo_backing_file;
+	struct file *file = check_file_not_null(lo);
 	int ret;
 
 	mode |= FALLOC_FL_KEEP_SIZE;
@@ -345,7 +373,7 @@ static int lo_rw_aio(struct loop_device *lo, struct loop_cmd *cmd,
 	struct bio_vec *bvec;
 	struct request *rq = blk_mq_rq_from_pdu(cmd);
 	struct bio *bio = rq->bio;
-	struct file *file = lo->lo_backing_file;
+	struct file *file = check_file_not_null(lo);
 	struct bio_vec tmp;
 	unsigned int offset;
 	unsigned int nr_bvec;
@@ -1118,6 +1146,13 @@ static void __loop_clr_fd(struct loop_device *lo)
 	struct file *filp;
 	gfp_t gfp = lo->old_gfp_mask;
 
+#ifdef CONFIG_DEBUG_AID_FOR_SYZBOT
+	lo->clear_pid = current->pid;
+	get_task_comm(lo->clear_comm, current);
+	lo->clear_jiffies = jiffies;
+	lo->clear_nr_entries = stack_trace_save(lo->clear_entries,
+						ARRAY_SIZE(lo->clear_entries), 0);
+#endif
 	spin_lock_irq(&lo->lo_lock);
 	filp = lo->lo_backing_file;
 	lo->lo_backing_file = NULL;
diff --git a/drivers/bluetooth/Kconfig b/drivers/bluetooth/Kconfig
index c5d45cf91f88..fc1b37044a9b 100644
--- a/drivers/bluetooth/Kconfig
+++ b/drivers/bluetooth/Kconfig
@@ -502,7 +502,7 @@ config BT_NXPUART
 
 config BT_INTEL_PCIE
 	tristate "Intel HCI PCIe driver"
-	depends on PCI
+	depends on PCI && ACPI
 	select BT_INTEL
 	select FW_LOADER
 	help
diff --git a/drivers/bluetooth/btintel.c b/drivers/bluetooth/btintel.c
index dcaaa4ca02b9..5e9cac090bd8 100644
--- a/drivers/bluetooth/btintel.c
+++ b/drivers/bluetooth/btintel.c
@@ -67,9 +67,10 @@ static struct {
 	u32        fw_build_num;
 } coredump_info;
 
-static const guid_t btintel_guid_dsm =
+const guid_t btintel_guid_dsm =
 	GUID_INIT(0xaa10f4e0, 0x81ac, 0x4233,
 		  0xab, 0xf6, 0x3b, 0x2a, 0xc5, 0x0e, 0x28, 0xd9);
+EXPORT_SYMBOL_GPL(btintel_guid_dsm);
 
 int btintel_check_bdaddr(struct hci_dev *hdev)
 {
@@ -2624,7 +2625,7 @@ static void btintel_set_ppag(struct hci_dev *hdev, struct intel_version_tlv *ver
 	kfree_skb(skb);
 }
 
-static int btintel_acpi_reset_method(struct hci_dev *hdev)
+int btintel_acpi_reset_method(struct hci_dev *hdev)
 {
 	int ret = 0;
 	acpi_status status;
@@ -2632,14 +2633,14 @@ static int btintel_acpi_reset_method(struct hci_dev *hdev)
 	struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
 
 	status = acpi_evaluate_object(ACPI_HANDLE(GET_HCIDEV_DEV(hdev)), "_PRR", NULL, &buffer);
-	if (ACPI_FAILURE(status)) {
+	if (ACPI_FAILURE(status) || !buffer.pointer) {
 		bt_dev_err(hdev, "Failed to run _PRR method");
 		ret = -ENODEV;
 		return ret;
 	}
 	p = buffer.pointer;
 
-	if (p->package.count != 1 || p->type != ACPI_TYPE_PACKAGE) {
+	if (p->type != ACPI_TYPE_PACKAGE || p->package.count != 1) {
 		bt_dev_err(hdev, "Invalid arguments");
 		ret = -EINVAL;
 		goto exit_on_error;
@@ -2663,6 +2664,7 @@ static int btintel_acpi_reset_method(struct hci_dev *hdev)
 	kfree(buffer.pointer);
 	return ret;
 }
+EXPORT_SYMBOL_GPL(btintel_acpi_reset_method);
 
 static void btintel_set_dsm_reset_method(struct hci_dev *hdev,
 					 struct intel_version_tlv *ver_tlv)
diff --git a/drivers/bluetooth/btintel.h b/drivers/bluetooth/btintel.h
index 0e9ca99aaaae..70d812ad36a2 100644
--- a/drivers/bluetooth/btintel.h
+++ b/drivers/bluetooth/btintel.h
@@ -79,6 +79,8 @@ struct intel_tlv {
 #define BTINTEL_HWID_SCP2	0x20	/* Scorpius Peak2 - Nova Lake */
 #define BTINTEL_HWID_BZRIW	0x22	/* BlazarIW - Wildcat Lake */
 
+extern const guid_t btintel_guid_dsm;
+
 struct intel_version_tlv {
 	u32	cnvi_top;
 	u32	cnvr_top;
@@ -289,6 +291,7 @@ int btintel_bootloader_setup_tlv(struct hci_dev *hdev,
 int btintel_shutdown_combined(struct hci_dev *hdev);
 void btintel_hw_error(struct hci_dev *hdev, u8 code);
 void btintel_print_fseq_info(struct hci_dev *hdev);
+int btintel_acpi_reset_method(struct hci_dev *hdev);
 #else
 
 static inline int btintel_check_bdaddr(struct hci_dev *hdev)
@@ -422,4 +425,8 @@ static inline void btintel_hw_error(struct hci_dev *hdev, u8 code)
 static inline void btintel_print_fseq_info(struct hci_dev *hdev)
 {
 }
+static inline int btintel_acpi_reset_method(struct hci_dev *hdev)
+{
+	return -ENODEV;
+}
 #endif
diff --git a/drivers/bluetooth/btintel_pcie.c b/drivers/bluetooth/btintel_pcie.c
index 2f59c0d6f9ec..fda474406003 100644
--- a/drivers/bluetooth/btintel_pcie.c
+++ b/drivers/bluetooth/btintel_pcie.c
@@ -15,6 +15,7 @@
 #include <linux/wait.h>
 #include <linux/delay.h>
 #include <linux/interrupt.h>
+#include <linux/acpi.h>
 
 #include <linux/unaligned.h>
 #include <linux/devcoredump.h>
@@ -102,6 +103,22 @@ enum {
 	BTINTEL_PCIE_D3
 };
 
+enum {
+	BTINTEL_PCIE_DSM_SET_RESET_TIMING = 1,
+	BTINTEL_PCIE_DSM_GET_RESET_TIMING = 2,
+	BTINTEL_PCIE_DSM_BT_PLDR_CONFIG = 3,
+	BTINTEL_PCIE_DSM_GET_RESET_TYPE = 4,
+	BTINTEL_PCIE_DSM_DYNAMIC_PLDR = 5,
+	BTINTEL_PCIE_DSM_GET_RESET_METHOD = 6,
+	BTINTEL_PCIE_DSM_SET_PLDR_DELAY = 7,
+};
+
+enum btintel_dsm_internal_product_reset_mode {
+	BTINTEL_PCIE_DSM_PLDR_MODE_EN_PROD_RESET	= BIT(0),
+	BTINTEL_PCIE_DSM_PLDR_MODE_EN_WIFI_FLR		= BIT(1),
+	BTINTEL_PCIE_DSM_PLDR_MODE_EN_BT_OFF_ON		= BIT(2),
+};
+
 /* Structure for dbgc fragment buffer
  * @buf_addr_lsb: LSB of the buffer's physical address
  * @buf_addr_msb: MSB of the buffer's physical address
@@ -128,11 +145,6 @@ struct btintel_pcie_dbgc_ctxt {
 	struct btintel_pcie_dbgc_ctxt_buf bufs[BTINTEL_PCIE_DBGC_BUFFER_COUNT];
 };
 
-struct btintel_pcie_removal {
-	struct pci_dev *pdev;
-	struct work_struct work;
-};
-
 static LIST_HEAD(btintel_pcie_recovery_list);
 static DEFINE_SPINLOCK(btintel_pcie_recovery_lock);
 
@@ -289,6 +301,9 @@ static inline void btintel_pcie_dump_debug_registers(struct hci_dev *hdev)
 	skb_put_data(skb, buf, strlen(buf));
 	data->boot_stage_cache = reg;
 
+	if (reg & BTINTEL_PCIE_CSR_BOOT_STAGE_DEVICE_WARNING)
+		bt_dev_warn(hdev, "Controller device warning (boot_stage: 0x%8.8x)", reg);
+
 	reg = btintel_pcie_rd_reg32(data, BTINTEL_PCIE_CSR_IPC_STATUS_REG);
 	snprintf(buf, sizeof(buf), "ipc status: 0x%8.8x", reg);
 	skb_put_data(skb, buf, strlen(buf));
@@ -880,8 +895,11 @@ static inline bool btintel_pcie_in_lockdown(struct btintel_pcie_data *data)
 
 static inline bool btintel_pcie_in_error(struct btintel_pcie_data *data)
 {
-	return (data->boot_stage_cache & BTINTEL_PCIE_CSR_BOOT_STAGE_DEVICE_ERR) ||
-		(data->boot_stage_cache & BTINTEL_PCIE_CSR_BOOT_STAGE_ABORT_HANDLER);
+	if (data->boot_stage_cache & BTINTEL_PCIE_CSR_BOOT_STAGE_DEVICE_WARNING)
+		bt_dev_warn(data->hdev, "Controller device warning (boot_stage: 0x%8.8x)",
+			    data->boot_stage_cache);
+
+	return	data->boot_stage_cache & BTINTEL_PCIE_CSR_BOOT_STAGE_ABORT_HANDLER;
 }
 
 static void btintel_pcie_msix_gp1_handler(struct btintel_pcie_data *data)
@@ -914,7 +932,8 @@ static void btintel_pcie_msix_gp0_handler(struct btintel_pcie_data *data)
 		data->img_resp_cache = reg;
 
 	if (btintel_pcie_in_error(data)) {
-		bt_dev_err(data->hdev, "Controller in error state");
+		bt_dev_err(data->hdev, "Controller in error state (boot_stage: 0x%8.8x)",
+			   data->boot_stage_cache);
 		btintel_pcie_dump_debug_registers(data->hdev);
 		return;
 	}
@@ -2266,21 +2285,132 @@ static void btintel_pcie_inc_recovery_count(struct pci_dev *pdev,
 }
 
 static int btintel_pcie_setup_hdev(struct btintel_pcie_data *data);
+static void btintel_pcie_reset(struct hci_dev *hdev);
 
-static void btintel_pcie_removal_work(struct work_struct *wk)
+static int btintel_pcie_acpi_reset_method(struct btintel_pcie_data *data)
 {
-	struct btintel_pcie_removal *removal =
-		container_of(wk, struct btintel_pcie_removal, work);
-	struct pci_dev *pdev = removal->pdev;
-	struct btintel_pcie_data *data;
+	union acpi_object *obj, argv4;
+	acpi_handle handle;
+	int ret;
+	struct pldr_mode {
+		__le16	cmd_type;
+		__le16	cmd_payload;
+	} __packed;
+
+	/* set 1 for _PRR mode
+	 * Product Reset (PLDR Abort flow)
+	 */
+	static const struct pldr_mode mode = {
+		.cmd_type = cpu_to_le16(1),
+		.cmd_payload = cpu_to_le16(BTINTEL_PCIE_DSM_PLDR_MODE_EN_PROD_RESET |
+			       BTINTEL_PCIE_DSM_PLDR_MODE_EN_WIFI_FLR),
+	};
+	struct hci_dev *hdev = data->hdev;
+
+	handle = ACPI_HANDLE(GET_HCIDEV_DEV(data->hdev));
+	if (!handle) {
+		bt_dev_err(data->hdev, "No support for bluetooth device in ACPI firmware");
+		return -EACCES;
+	}
+
+	if (!acpi_has_method(handle, "_PRR")) {
+		bt_dev_err(data->hdev, "No support for _PRR ACPI method, cold boot");
+		return -ENODEV;
+	}
+
+	argv4.buffer.type = ACPI_TYPE_BUFFER;
+	argv4.buffer.length = sizeof(mode);
+	argv4.buffer.pointer = (void *)&mode;
+
+	obj = acpi_evaluate_dsm(handle, &btintel_guid_dsm, 0,
+				BTINTEL_PCIE_DSM_DYNAMIC_PLDR, &argv4);
+	if (!obj) {
+		bt_dev_err(data->hdev, "Failed to call dsm to set reset method");
+		return -EIO;
+	}
+	ACPI_FREE(obj);
+
+	pci_dev_lock(data->pdev);
+	pci_save_state(data->pdev);
+	ret = btintel_acpi_reset_method(hdev);
+	if (ret)
+		bt_dev_err(data->hdev, "ACPI _PRR reset failed (%d), PLDR incomplete",
+			   ret);
+	pci_restore_state(data->pdev);
+	pci_dev_unlock(data->pdev);
+	return ret;
+}
+
+static void btintel_pcie_perform_pldr(struct btintel_pcie_data *data)
+{
+	struct pci_dev *pdev = data->pdev;
+	struct pci_dev *wifi = NULL;
+	struct pci_bus *bus;
+	int ret;
+	/* on integrated we have to look up by ID (same bus) */
+	static const struct pci_device_id wifi_device_ids[] = {
+	#define WIFI_DEV(_id) { PCI_DEVICE(PCI_VENDOR_ID_INTEL, _id) }
+		WIFI_DEV(0xA840), /* LNL */
+		WIFI_DEV(0xE440), /* PTL-P */
+		WIFI_DEV(0xE340), /* PTL-H */
+		WIFI_DEV(0xD340), /* NVL-H */
+		WIFI_DEV(0x6E70), /* NVL-S */
+		WIFI_DEV(0x4D40), /* WCL */
+		WIFI_DEV(0xD240), /* RZL-H */
+		WIFI_DEV(0x6C40), /* RZL-M */
+		{}
+	};
+	struct pci_dev *tmp = NULL;
+
+	bus = pdev->bus;
+	if (!bus)
+		return;
+
+	list_for_each_entry(tmp, &bus->devices, bus_list) {
+		if (pci_match_id(wifi_device_ids, tmp)) {
+			wifi = pci_dev_get(tmp);
+			break;
+		}
+	}
+
+	if (wifi)
+		device_release_driver(&wifi->dev);
+
+	/* Wi-Fi is fully unbound before the reset and fully reprobed after
+	 * the normal PCI probe path handles all state setup from scratch.
+	 * BT needs pci_save_state()/pci_restore_state() because the BT driver
+	 * is still partially attached when the _PRR runs (it hasn't been unbound yet).
+	 * The PCI device needs to remain minimally functional so that
+	 * device_reprobe(&pdev->dev) can work afterward
+	 */
+	ret = btintel_pcie_acpi_reset_method(data);
+
+	if (wifi) {
+		if (device_reprobe(&wifi->dev))
+			BT_ERR("WiFi reprobe failed for BDF:%s", pci_name(wifi));
+		pci_dev_put(wifi);
+	}
+
+	if (!ret) {
+		if (device_reprobe(&pdev->dev))
+			BT_ERR("BT reprobe failed for BDF:%s", pci_name(pdev));
+	}
+}
+
+static void btintel_pcie_reset_work(struct work_struct *wk)
+{
+	struct btintel_pcie_data *data =
+		container_of(wk, struct btintel_pcie_data, reset_work);
+	struct pci_dev *pdev = data->pdev;
 	int err;
 
 	pci_lock_rescan_remove();
 
 	if (!pdev->bus)
-		goto error;
+		goto out;
 
-	data = pci_get_drvdata(pdev);
+	if (!data)
+		goto out;
 
 	btintel_pcie_disable_interrupts(data);
 	btintel_pcie_synchronize_irqs(data);
@@ -2288,12 +2418,21 @@ static void btintel_pcie_removal_work(struct work_struct *wk)
 	flush_work(&data->rx_work);
 
 	bt_dev_dbg(data->hdev, "Release bluetooth interface");
+	if (data->reset_type == BTINTEL_PCIE_IOSF_PRR_PLDR) {
+		/* This function holds pci_lock_rescan_remove(), which acquires
+		 * pci_rescan_remove_lock. This mutex serializes against PCI device
+		 * addition/removal (hotplug), so no device can be added to or
+		 * removed from the bus list while this code runs.
+		 */
+		btintel_pcie_perform_pldr(data);
+		goto out;
+	}
 	btintel_pcie_release_hdev(data);
 
 	err = pci_reset_function(pdev);
 	if (err) {
 		BT_ERR("Failed resetting the pcie device (%d)", err);
-		goto error;
+		goto out;
 	}
 
 	btintel_pcie_enable_interrupts(data);
@@ -2303,7 +2442,7 @@ static void btintel_pcie_removal_work(struct work_struct *wk)
 	if (err) {
 		BT_ERR("Failed to enable bluetooth hardware after reset (%d)",
 		       err);
-		goto error;
+		goto out;
 	}
 
 	btintel_pcie_reset_ia(data);
@@ -2313,17 +2452,15 @@ static void btintel_pcie_removal_work(struct work_struct *wk)
 	err = btintel_pcie_setup_hdev(data);
 	if (err) {
 		BT_ERR("Failed registering hdev (%d)", err);
-		goto error;
+		goto out;
 	}
-error:
+out:
 	pci_dev_put(pdev);
 	pci_unlock_rescan_remove();
-	kfree(removal);
 }
 
 static void btintel_pcie_reset(struct hci_dev *hdev)
 {
-	struct btintel_pcie_removal *removal;
 	struct btintel_pcie_data *data;
 
 	data = hci_get_drvdata(hdev);
@@ -2334,14 +2471,8 @@ static void btintel_pcie_reset(struct hci_dev *hdev)
 	if (test_and_set_bit(BTINTEL_PCIE_RECOVERY_IN_PROGRESS, &data->flags))
 		return;
 
-	removal = kzalloc_obj(*removal, GFP_ATOMIC);
-	if (!removal)
-		return;
-
-	removal->pdev = data->pdev;
-	INIT_WORK(&removal->work, btintel_pcie_removal_work);
-	pci_dev_get(removal->pdev);
-	schedule_work(&removal->work);
+	pci_dev_get(data->pdev);
+	schedule_work(&data->reset_work);
 }
 
 static void btintel_pcie_hw_error(struct hci_dev *hdev, u8 code)
@@ -2351,15 +2482,19 @@ static void btintel_pcie_hw_error(struct hci_dev *hdev, u8 code)
 	struct pci_dev *pdev = dev_data->pdev;
 	time64_t retry_window;
 
-	if (code == 0x13) {
-		bt_dev_err(hdev, "Encountered top exception");
-		return;
-	}
+	btintel_pcie_dump_debug_registers(hdev);
 
 	data = btintel_pcie_get_recovery(pdev, &hdev->dev);
 	if (!data)
 		return;
 
+	if (code == 0x13)
+		dev_data->reset_type = BTINTEL_PCIE_IOSF_PRR_PLDR;
+	else
+		dev_data->reset_type = BTINTEL_PCIE_IOSF_PRR_FLR;
+
+	bt_dev_err(hdev, "Encountered exception err:0x%x triggering: %s", code,
+		   dev_data->reset_type == BTINTEL_PCIE_IOSF_PRR_PLDR ? "PLDR" : "FLR");
 	retry_window = ktime_get_boottime_seconds() - data->last_error;
 
 	if (retry_window < BTINTEL_PCIE_RESET_WINDOW_SECS &&
@@ -2512,10 +2647,14 @@ static int btintel_pcie_probe(struct pci_dev *pdev,
 
 	skb_queue_head_init(&data->rx_skb_q);
 	INIT_WORK(&data->rx_work, btintel_pcie_rx_work);
+	INIT_WORK(&data->reset_work, btintel_pcie_reset_work);
 
 	data->boot_stage_cache = 0x00;
 	data->img_resp_cache = 0x00;
-
+	/* FLR can be invoked by echoing to debugfs path, so explicitly
+	 * initialized
+	 */
+	data->reset_type = BTINTEL_PCIE_IOSF_PRR_FLR;
 	err = btintel_pcie_config_pcie(pdev, data);
 	if (err)
 		goto exit_error;
@@ -2564,6 +2703,14 @@ static void btintel_pcie_remove(struct pci_dev *pdev)
 
 	data = pci_get_drvdata(pdev);
 
+	/* Cancel pending reset work. Skip only when remove() is called from
+	 * within the reset work itself (PLDR device_reprobe path) to avoid
+	 * deadlock. current_work() returns the work_struct of the caller if
+	 * we are in a workqueue context.
+	 */
+	if (current_work() != &data->reset_work)
+		cancel_work_sync(&data->reset_work);
+
 	btintel_pcie_disable_interrupts(data);
 
 	btintel_pcie_synchronize_irqs(data);
@@ -2713,6 +2860,7 @@ static int btintel_pcie_resume(struct device *dev)
 	if (data->pm_sx_event == PM_EVENT_FREEZE ||
 	    data->pm_sx_event == PM_EVENT_HIBERNATE) {
 		set_bit(BTINTEL_PCIE_CORE_HALTED, &data->flags);
+		data->reset_type = BTINTEL_PCIE_IOSF_PRR_FLR;
 		btintel_pcie_reset(data->hdev);
 		return 0;
 	}
diff --git a/drivers/bluetooth/btintel_pcie.h b/drivers/bluetooth/btintel_pcie.h
index 3c7bb708362d..2db85f71b2f8 100644
--- a/drivers/bluetooth/btintel_pcie.h
+++ b/drivers/bluetooth/btintel_pcie.h
@@ -48,7 +48,7 @@
 #define BTINTEL_PCIE_CSR_BOOT_STAGE_OPFW		(BIT(2))
 #define BTINTEL_PCIE_CSR_BOOT_STAGE_ROM_LOCKDOWN	(BIT(10))
 #define BTINTEL_PCIE_CSR_BOOT_STAGE_IML_LOCKDOWN	(BIT(11))
-#define BTINTEL_PCIE_CSR_BOOT_STAGE_DEVICE_ERR		(BIT(12))
+#define BTINTEL_PCIE_CSR_BOOT_STAGE_DEVICE_WARNING	(BIT(12))
 #define BTINTEL_PCIE_CSR_BOOT_STAGE_ABORT_HANDLER	(BIT(13))
 #define BTINTEL_PCIE_CSR_BOOT_STAGE_DEVICE_HALTED	(BIT(14))
 #define BTINTEL_PCIE_CSR_BOOT_STAGE_MAC_ACCESS_ON	(BIT(16))
@@ -144,6 +144,11 @@ enum msix_mbox_int_causes {
 	BTINTEL_PCIE_CSR_MBOX_STATUS_MBOX4 = BIT(3), /* cause MBOX4 */
 };
 
+enum btintel_pcie_reset_type {
+	BTINTEL_PCIE_IOSF_PRR_FLR = 0,
+	BTINTEL_PCIE_IOSF_PRR_PLDR = 1,
+};
+
 #define BTINTEL_PCIE_MSIX_NON_AUTO_CLEAR_CAUSE	BIT(7)
 
 /* Minimum and Maximum number of MSI-X Vector
@@ -500,6 +505,7 @@ struct btintel_pcie_data {
 	struct workqueue_struct	*workqueue;
 	struct sk_buff_head	rx_skb_q;
 	struct work_struct	rx_work;
+	struct work_struct      reset_work;
 
 	struct dma_pool	*dma_pool;
 	dma_addr_t	dma_p_addr;
@@ -511,6 +517,7 @@ struct btintel_pcie_data {
 	struct txq	txq;
 	struct rxq	rxq;
 	u32	alive_intr_ctxt;
+	enum btintel_pcie_reset_type	reset_type;
 	struct btintel_pcie_dbgc	dbgc;
 	struct btintel_pcie_dump_header dmp_hdr;
 	u8	pm_sx_event;
diff --git a/drivers/bluetooth/btmtk.c b/drivers/bluetooth/btmtk.c
index 6fb6ca274808..ab34f1dd42bc 100644
--- a/drivers/bluetooth/btmtk.c
+++ b/drivers/bluetooth/btmtk.c
@@ -695,8 +695,13 @@ static int btmtk_usb_hci_wmt_sync(struct hci_dev *hdev,
 	if (data->evt_skb == NULL)
 		goto err_free_wc;
 
-	/* Parse and handle the return WMT event */
-	wmt_evt = (struct btmtk_hci_wmt_evt *)data->evt_skb->data;
+	wmt_evt = skb_pull_data(data->evt_skb, sizeof(*wmt_evt));
+	if (!wmt_evt) {
+		bt_dev_err(hdev, "WMT event too short (%u bytes)",
+			   data->evt_skb->len);
+		err = -EINVAL;
+		goto err_free_skb;
+	}
 	if (wmt_evt->whdr.op != hdr->op) {
 		bt_dev_err(hdev, "Wrong op received %d expected %d",
 			   wmt_evt->whdr.op, hdr->op);
@@ -712,6 +717,12 @@ static int btmtk_usb_hci_wmt_sync(struct hci_dev *hdev,
 			status = BTMTK_WMT_PATCH_DONE;
 		break;
 	case BTMTK_WMT_FUNC_CTRL:
+		if (!skb_pull_data(data->evt_skb,
+				   sizeof(wmt_evt_funcc->status))) {
+			err = -EINVAL;
+			goto err_free_skb;
+		}
+
 		wmt_evt_funcc = (struct btmtk_hci_wmt_evt_funcc *)wmt_evt;
 		if (be16_to_cpu(wmt_evt_funcc->status) == 0x404)
 			status = BTMTK_WMT_ON_DONE;
@@ -1534,6 +1545,29 @@ int btmtk_usb_shutdown(struct hci_dev *hdev)
 	return 0;
 }
 EXPORT_SYMBOL_GPL(btmtk_usb_shutdown);
+
+int btmtk_recv_event(struct hci_dev *hdev, struct sk_buff *skb)
+{
+	struct hci_event_hdr *hdr = (void *)skb->data;
+	struct hci_ev_cmd_complete *ec;
+
+	if (hdr->evt == HCI_EV_CMD_COMPLETE &&
+	    skb->len >= HCI_EVENT_HDR_SIZE + sizeof(*ec)) {
+		u16 opcode;
+
+		ec = (void *)(skb->data + HCI_EVENT_HDR_SIZE);
+		opcode = __le16_to_cpu(ec->opcode);
+
+		/* Filter vendor opcode */
+		if (opcode == 0xfc5d) {
+			kfree_skb(skb);
+			return 0;
+		}
+	}
+
+	return hci_recv_frame(hdev, skb);
+}
+EXPORT_SYMBOL_GPL(btmtk_recv_event);
 #endif
 
 MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>");
diff --git a/drivers/bluetooth/btmtk.h b/drivers/bluetooth/btmtk.h
index c564aedc0ce0..c83c24897c95 100644
--- a/drivers/bluetooth/btmtk.h
+++ b/drivers/bluetooth/btmtk.h
@@ -220,6 +220,8 @@ int btmtk_usb_suspend(struct hci_dev *hdev);
 int btmtk_usb_setup(struct hci_dev *hdev);
 
 int btmtk_usb_shutdown(struct hci_dev *hdev);
+
+int btmtk_recv_event(struct hci_dev *hdev, struct sk_buff *skb);
 #else
 
 static inline int btmtk_set_bdaddr(struct hci_dev *hdev,
@@ -299,4 +301,9 @@ static inline int btmtk_usb_shutdown(struct hci_dev *hdev)
 {
 	return -EOPNOTSUPP;
 }
+
+static inline int btmtk_recv_event(struct hci_dev *hdev, struct sk_buff *skb)
+{
+	return hci_recv_frame(hdev, skb);
+}
 #endif
diff --git a/drivers/bluetooth/btusb.c b/drivers/bluetooth/btusb.c
index 7f5fce93d984..572091e601f9 100644
--- a/drivers/bluetooth/btusb.c
+++ b/drivers/bluetooth/btusb.c
@@ -601,6 +601,10 @@ static const struct usb_device_id quirks_table[] = {
 	/* Realtek 8922AE Bluetooth devices */
 	{ USB_DEVICE(0x0bda, 0x8922), .driver_info = BTUSB_REALTEK |
 						     BTUSB_WIDEBAND_SPEECH },
+	{ USB_DEVICE(0x0bda, 0xd922), .driver_info = BTUSB_REALTEK |
+						     BTUSB_WIDEBAND_SPEECH },
+	{ USB_DEVICE(0x0bda, 0xd923), .driver_info = BTUSB_REALTEK |
+						     BTUSB_WIDEBAND_SPEECH },
 	{ USB_DEVICE(0x13d3, 0x3617), .driver_info = BTUSB_REALTEK |
 						     BTUSB_WIDEBAND_SPEECH },
 	{ USB_DEVICE(0x13d3, 0x3616), .driver_info = BTUSB_REALTEK |
@@ -723,6 +727,8 @@ static const struct usb_device_id quirks_table[] = {
 						     BTUSB_WIDEBAND_SPEECH },
 	{ USB_DEVICE(0x04ca, 0x38e4), .driver_info = BTUSB_MEDIATEK |
 						     BTUSB_WIDEBAND_SPEECH },
+	{ USB_DEVICE(0x0e8d, 0x223c), .driver_info = BTUSB_MEDIATEK |
+						     BTUSB_WIDEBAND_SPEECH },
 	{ USB_DEVICE(0x13d3, 0x3568), .driver_info = BTUSB_MEDIATEK |
 						     BTUSB_WIDEBAND_SPEECH },
 	{ USB_DEVICE(0x13d3, 0x3584), .driver_info = BTUSB_MEDIATEK |
@@ -773,6 +779,8 @@ static const struct usb_device_id quirks_table[] = {
 						     BTUSB_WIDEBAND_SPEECH },
 	{ USB_DEVICE(0x0489, 0xe151), .driver_info = BTUSB_MEDIATEK |
 						     BTUSB_WIDEBAND_SPEECH },
+	{ USB_DEVICE(0x0e8d, 0x8c38), .driver_info = BTUSB_MEDIATEK |
+						     BTUSB_WIDEBAND_SPEECH },
 	{ USB_DEVICE(0x13d3, 0x3602), .driver_info = BTUSB_MEDIATEK |
 						     BTUSB_WIDEBAND_SPEECH },
 	{ USB_DEVICE(0x13d3, 0x3603), .driver_info = BTUSB_MEDIATEK |
@@ -814,6 +822,8 @@ static const struct usb_device_id quirks_table[] = {
 	{ USB_DEVICE(0x2ff8, 0xb011), .driver_info = BTUSB_REALTEK },
 
 	/* Additional Realtek 8761BUV Bluetooth devices */
+	{ USB_DEVICE(0x2c4e, 0x0115), .driver_info = BTUSB_REALTEK |
+						     BTUSB_WIDEBAND_SPEECH },
 	{ USB_DEVICE(0x2357, 0x0604), .driver_info = BTUSB_REALTEK |
 						     BTUSB_WIDEBAND_SPEECH },
 	{ USB_DEVICE(0x0b05, 0x190e), .driver_info = BTUSB_REALTEK |
@@ -4242,6 +4252,7 @@ static int btusb_probe(struct usb_interface *intf,
 		hci_set_quirk(hdev, HCI_QUIRK_BROKEN_ENHANCED_SETUP_SYNC_CONN);
 		hci_set_quirk(hdev, HCI_QUIRK_NON_PERSISTENT_SETUP);
 		data->recv_acl = btmtk_usb_recv_acl;
+		data->recv_event = btmtk_recv_event;
 		data->suspend = btmtk_usb_suspend;
 		data->resume = btmtk_usb_resume;
 		data->disconnect = btusb_mtk_disconnect;
diff --git a/drivers/bluetooth/hci_ath.c b/drivers/bluetooth/hci_ath.c
index fa679ad0acdf..8201fa7f61e8 100644
--- a/drivers/bluetooth/hci_ath.c
+++ b/drivers/bluetooth/hci_ath.c
@@ -191,6 +191,9 @@ static int ath_recv(struct hci_uart *hu, const void *data, int count)
 {
 	struct ath_struct *ath = hu->priv;
 
+	if (!ath)
+		return -ENODEV;
+
 	ath->rx_skb = h4_recv_buf(hu, ath->rx_skb, data, count,
 				  ath_recv_pkts, ARRAY_SIZE(ath_recv_pkts));
 	if (IS_ERR(ath->rx_skb)) {
diff --git a/drivers/bluetooth/hci_bcsp.c b/drivers/bluetooth/hci_bcsp.c
index b386f91d8b46..db56eead27ce 100644
--- a/drivers/bluetooth/hci_bcsp.c
+++ b/drivers/bluetooth/hci_bcsp.c
@@ -585,6 +585,9 @@ static int bcsp_recv(struct hci_uart *hu, const void *data, int count)
 	if (!test_bit(HCI_UART_REGISTERED, &hu->flags))
 		return -EUNATCH;
 
+	if (!bcsp)
+		return -ENODEV;
+
 	BT_DBG("hu %p count %d rx_state %d rx_count %ld",
 	       hu, count, bcsp->rx_state, bcsp->rx_count);
 
diff --git a/drivers/bluetooth/hci_h4.c b/drivers/bluetooth/hci_h4.c
index a889a66a326f..767372707498 100644
--- a/drivers/bluetooth/hci_h4.c
+++ b/drivers/bluetooth/hci_h4.c
@@ -109,6 +109,9 @@ static int h4_recv(struct hci_uart *hu, const void *data, int count)
 {
 	struct h4_struct *h4 = hu->priv;
 
+	if (!h4)
+		return -ENODEV;
+
 	h4->rx_skb = h4_recv_buf(hu, h4->rx_skb, data, count,
 				 h4_recv_pkts, ARRAY_SIZE(h4_recv_pkts));
 	if (IS_ERR(h4->rx_skb)) {
diff --git a/drivers/bluetooth/hci_h5.c b/drivers/bluetooth/hci_h5.c
index cfdf75dc2847..d35383718212 100644
--- a/drivers/bluetooth/hci_h5.c
+++ b/drivers/bluetooth/hci_h5.c
@@ -587,6 +587,9 @@ static int h5_recv(struct hci_uart *hu, const void *data, int count)
 	struct h5 *h5 = hu->priv;
 	const unsigned char *ptr = data;
 
+	if (!h5)
+		return -ENODEV;
+
 	BT_DBG("%s pending %zu count %d", hu->hdev->name, h5->rx_pending,
 	       count);
 
diff --git a/drivers/bluetooth/virtio_bt.c b/drivers/bluetooth/virtio_bt.c
index 76d61af8a275..140ab55c9fc5 100644
--- a/drivers/bluetooth/virtio_bt.c
+++ b/drivers/bluetooth/virtio_bt.c
@@ -12,6 +12,7 @@
 #include <net/bluetooth/hci_core.h>
 
 #define VERSION "0.1"
+#define VIRTBT_RX_BUF_SIZE 1000
 
 enum {
 	VIRTBT_VQ_TX,
@@ -33,11 +34,11 @@ static int virtbt_add_inbuf(struct virtio_bluetooth *vbt)
 	struct sk_buff *skb;
 	int err;
 
-	skb = alloc_skb(1000, GFP_KERNEL);
+	skb = alloc_skb(VIRTBT_RX_BUF_SIZE, GFP_KERNEL);
 	if (!skb)
 		return -ENOMEM;
 
-	sg_init_one(sg, skb->data, 1000);
+	sg_init_one(sg, skb->data, VIRTBT_RX_BUF_SIZE);
 
 	err = virtqueue_add_inbuf(vq, sg, 1, skb, GFP_KERNEL);
 	if (err < 0) {
@@ -197,6 +198,7 @@ static int virtbt_shutdown_generic(struct hci_dev *hdev)
 
 static void virtbt_rx_handle(struct virtio_bluetooth *vbt, struct sk_buff *skb)
 {
+	size_t min_hdr;
 	__u8 pkt_type;
 
 	pkt_type = *((__u8 *) skb->data);
@@ -204,16 +206,32 @@ static void virtbt_rx_handle(struct virtio_bluetooth *vbt, struct sk_buff *skb)
 
 	switch (pkt_type) {
 	case HCI_EVENT_PKT:
+		min_hdr = sizeof(struct hci_event_hdr);
+		break;
 	case HCI_ACLDATA_PKT:
+		min_hdr = sizeof(struct hci_acl_hdr);
+		break;
 	case HCI_SCODATA_PKT:
+		min_hdr = sizeof(struct hci_sco_hdr);
+		break;
 	case HCI_ISODATA_PKT:
-		hci_skb_pkt_type(skb) = pkt_type;
-		hci_recv_frame(vbt->hdev, skb);
+		min_hdr = sizeof(struct hci_iso_hdr);
 		break;
 	default:
 		kfree_skb(skb);
-		break;
+		return;
+	}
+
+	if (skb->len < min_hdr) {
+		bt_dev_err_ratelimited(vbt->hdev,
+				       "rx pkt_type 0x%02x payload %u < hdr %zu\n",
+				       pkt_type, skb->len, min_hdr);
+		kfree_skb(skb);
+		return;
 	}
+
+	hci_skb_pkt_type(skb) = pkt_type;
+	hci_recv_frame(vbt->hdev, skb);
 }
 
 static void virtbt_rx_work(struct work_struct *work)
@@ -227,8 +245,15 @@ static void virtbt_rx_work(struct work_struct *work)
 	if (!skb)
 		return;
 
-	skb_put(skb, len);
-	virtbt_rx_handle(vbt, skb);
+	if (!len || len > VIRTBT_RX_BUF_SIZE) {
+		bt_dev_err_ratelimited(vbt->hdev,
+				       "rx reply len %u outside [1, %u]\n",
+				       len, VIRTBT_RX_BUF_SIZE);
+		kfree_skb(skb);
+	} else {
+		skb_put(skb, len);
+		virtbt_rx_handle(vbt, skb);
+	}
 
 	if (virtbt_add_inbuf(vbt) < 0)
 		return;
diff --git a/drivers/bus/fsl-mc/dprc-driver.c b/drivers/bus/fsl-mc/dprc-driver.c
index db67442addad..a85706826fa0 100644
--- a/drivers/bus/fsl-mc/dprc-driver.c
+++ b/drivers/bus/fsl-mc/dprc-driver.c
@@ -609,9 +609,8 @@ int dprc_setup(struct fsl_mc_device *mc_dev)
 {
 	struct device *parent_dev = mc_dev->dev.parent;
 	struct fsl_mc_bus *mc_bus = to_fsl_mc_bus(mc_dev);
-	struct irq_domain *mc_msi_domain;
+	struct irq_domain *mc_msi_domain = NULL;
 	bool mc_io_created = false;
-	bool msi_domain_set = false;
 	bool uapi_created = false;
 	u16 major_ver, minor_ver;
 	size_t region_size;
@@ -652,14 +651,12 @@ int dprc_setup(struct fsl_mc_device *mc_dev)
 		uapi_created = true;
 	}
 
-	mc_msi_domain = fsl_mc_find_msi_domain(&mc_dev->dev);
-	if (!mc_msi_domain) {
+	mc_msi_domain = fsl_mc_get_msi_parent(&mc_dev->dev);
+	if (!mc_msi_domain)
 		dev_warn(&mc_dev->dev,
 			 "WARNING: MC bus without interrupt support\n");
-	} else {
+	else
 		dev_set_msi_domain(&mc_dev->dev, mc_msi_domain);
-		msi_domain_set = true;
-	}
 
 	error = dprc_open(mc_dev->mc_io, 0, mc_dev->obj_desc.id,
 			  &mc_dev->mc_handle);
@@ -699,8 +696,7 @@ int dprc_setup(struct fsl_mc_device *mc_dev)
 	(void)dprc_close(mc_dev->mc_io, 0, mc_dev->mc_handle);
 
 error_cleanup_msi_domain:
-	if (msi_domain_set)
-		dev_set_msi_domain(&mc_dev->dev, NULL);
+	dev_set_msi_domain(&mc_dev->dev, NULL);
 
 	if (mc_io_created) {
 		fsl_destroy_mc_io(mc_dev->mc_io);
diff --git a/drivers/bus/fsl-mc/fsl-mc-bus.c b/drivers/bus/fsl-mc/fsl-mc-bus.c
index 221146e4860b..64d75eed0d34 100644
--- a/drivers/bus/fsl-mc/fsl-mc-bus.c
+++ b/drivers/bus/fsl-mc/fsl-mc-bus.c
@@ -66,6 +66,13 @@ struct fsl_mc_addr_translation_range {
 #define GCR1_P1_STOP	BIT(31)
 #define GCR1_P2_STOP	BIT(30)
 
+#define FSL_MC_GSR		0x8
+#define FSL_MC_GSR_BOOT_DONE	BIT(0)
+#define FSL_MC_GSR_MCS_MASK	GENMASK(7, 0)
+#define FSL_MC_GSR_MCS_ERR_MASK	GENMASK(7, 1)
+#define FSL_MC_GSR_BC_MASK	GENMASK(15, 8)
+#define FSL_MC_GSR_BC_SHIFT	8
+
 #define FSL_MC_FAPR	0x28
 #define MC_FAPR_PL	BIT(18)
 #define MC_FAPR_BMT	BIT(17)
@@ -828,14 +835,12 @@ int fsl_mc_device_add(struct fsl_mc_obj_desc *obj_desc,
 	} else {
 		/*
 		 * A non-DPRC object has to be a child of a DPRC, use the
-		 * parent's ICID and interrupt domain.
+		 * parent's ICID.
 		 */
 		mc_dev->icid = parent_mc_dev->icid;
 		mc_dev->dma_mask = FSL_MC_DEFAULT_DMA_MASK;
 		mc_dev->dev.dma_mask = &mc_dev->dma_mask;
 		mc_dev->dev.coherent_dma_mask = mc_dev->dma_mask;
-		dev_set_msi_domain(&mc_dev->dev,
-				   dev_get_msi_domain(&parent_mc_dev->dev));
 	}
 
 	/*
@@ -992,6 +997,41 @@ static int get_mc_addr_translation_ranges(struct device *dev,
 	return 0;
 }
 
+static u32 fsl_mc_read_gsr(struct fsl_mc *mc)
+{
+	return readl(mc->fsl_mc_regs + FSL_MC_GSR);
+}
+
+static int fsl_mc_firmware_check(struct platform_device *pdev)
+{
+	struct fsl_mc *mc = platform_get_drvdata(pdev);
+	u32 gsr, boot_done, boot_code, mcs;
+
+	gsr = fsl_mc_read_gsr(mc);
+	boot_code = (gsr & FSL_MC_GSR_BC_MASK) >> FSL_MC_GSR_BC_SHIFT;
+	if (boot_code == 0xDD) {
+		dev_err(&pdev->dev,
+			"fsl-mc: DPL processing was not started, DPAA2 will not work!\n");
+		return -EOPNOTSUPP;
+	}
+
+	boot_done = gsr & FSL_MC_GSR_BOOT_DONE;
+	if (!boot_done) {
+		dev_dbg(&pdev->dev,
+			"fsl-mc: DPL processing in progress, defer probe\n");
+		return -EPROBE_DEFER;
+	}
+
+	mcs = gsr & FSL_MC_GSR_MCS_MASK;
+	if (mcs & FSL_MC_GSR_MCS_ERR_MASK) {
+		dev_err(&pdev->dev,
+			"fsl-mc: MC boot completed with error 0x%x\n", mcs);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
 /*
  * fsl_mc_bus_probe - callback invoked when the root MC bus is being
  * added
@@ -1056,6 +1096,10 @@ static int fsl_mc_bus_probe(struct platform_device *pdev)
 		       mc->fsl_mc_regs + FSL_MC_GCR1);
 	}
 
+	error = fsl_mc_firmware_check(pdev);
+	if (error)
+		return error;
+
 	/*
 	 * Get physical address of MC portal for the root DPRC:
 	 */
diff --git a/drivers/bus/fsl-mc/fsl-mc-msi.c b/drivers/bus/fsl-mc/fsl-mc-msi.c
index 82cd69f7884c..be38b43803de 100644
--- a/drivers/bus/fsl-mc/fsl-mc-msi.c
+++ b/drivers/bus/fsl-mc/fsl-mc-msi.c
@@ -15,53 +15,16 @@
 
 #include "fsl-mc-private.h"
 
-#ifdef GENERIC_MSI_DOMAIN_OPS
-/*
- * Generate a unique ID identifying the interrupt (only used within the MSI
- * irqdomain.  Combine the icid with the interrupt index.
- */
-static irq_hw_number_t fsl_mc_domain_calc_hwirq(struct fsl_mc_device *dev,
-						struct msi_desc *desc)
-{
-	/*
-	 * Make the base hwirq value for ICID*10000 so it is readable
-	 * as a decimal value in /proc/interrupts.
-	 */
-	return (irq_hw_number_t)(desc->msi_index + (dev->icid * 10000));
-}
-
-static void fsl_mc_msi_set_desc(msi_alloc_info_t *arg,
-				struct msi_desc *desc)
-{
-	arg->desc = desc;
-	arg->hwirq = fsl_mc_domain_calc_hwirq(to_fsl_mc_device(desc->dev),
-					      desc);
-}
-#else
-#define fsl_mc_msi_set_desc NULL
-#endif
-
-static void fsl_mc_msi_update_dom_ops(struct msi_domain_info *info)
+static void fsl_mc_write_msi_msg(struct msi_desc *msi_desc, struct msi_msg *msg)
 {
-	struct msi_domain_ops *ops = info->ops;
-
-	if (!ops)
-		return;
-
-	/*
-	 * set_desc should not be set by the caller
-	 */
-	if (!ops->set_desc)
-		ops->set_desc = fsl_mc_msi_set_desc;
-}
-
-static void __fsl_mc_msi_write_msg(struct fsl_mc_device *mc_bus_dev,
-				   struct fsl_mc_device_irq *mc_dev_irq,
-				   struct msi_desc *msi_desc)
-{
-	int error;
+	struct fsl_mc_device *mc_bus_dev = to_fsl_mc_device(msi_desc->dev);
+	struct fsl_mc_bus *mc_bus = to_fsl_mc_bus(mc_bus_dev);
+	struct fsl_mc_device_irq *mc_dev_irq = &mc_bus->irq_resources[msi_desc->msi_index];
 	struct fsl_mc_device *owner_mc_dev = mc_dev_irq->mc_dev;
 	struct dprc_irq_cfg irq_cfg;
+	int error;
+
+	msi_desc->msg = *msg;
 
 	/*
 	 * msi_desc->msg.address is 0x0 when this function is invoked in
@@ -110,118 +73,27 @@ static void __fsl_mc_msi_write_msg(struct fsl_mc_device *mc_bus_dev,
 	}
 }
 
-/*
- * NOTE: This function is invoked with interrupts disabled
- */
-static void fsl_mc_msi_write_msg(struct irq_data *irq_data,
-				 struct msi_msg *msg)
-{
-	struct msi_desc *msi_desc = irq_data_get_msi_desc(irq_data);
-	struct fsl_mc_device *mc_bus_dev = to_fsl_mc_device(msi_desc->dev);
-	struct fsl_mc_bus *mc_bus = to_fsl_mc_bus(mc_bus_dev);
-	struct fsl_mc_device_irq *mc_dev_irq =
-		&mc_bus->irq_resources[msi_desc->msi_index];
-
-	msi_desc->msg = *msg;
-
-	/*
-	 * Program the MSI (paddr, value) pair in the device:
-	 */
-	__fsl_mc_msi_write_msg(mc_bus_dev, mc_dev_irq, msi_desc);
-}
-
-static void fsl_mc_msi_update_chip_ops(struct msi_domain_info *info)
-{
-	struct irq_chip *chip = info->chip;
-
-	if (!chip)
-		return;
-
-	/*
-	 * irq_write_msi_msg should not be set by the caller
-	 */
-	if (!chip->irq_write_msi_msg)
-		chip->irq_write_msi_msg = fsl_mc_msi_write_msg;
-}
-
-/**
- * fsl_mc_msi_create_irq_domain - Create a fsl-mc MSI interrupt domain
- * @fwnode:	Optional firmware node of the interrupt controller
- * @info:	MSI domain info
- * @parent:	Parent irq domain
- *
- * Updates the domain and chip ops and creates a fsl-mc MSI
- * interrupt domain.
- *
- * Returns:
- * A domain pointer or NULL in case of failure.
- */
-struct irq_domain *fsl_mc_msi_create_irq_domain(struct fwnode_handle *fwnode,
-						struct msi_domain_info *info,
-						struct irq_domain *parent)
-{
-	struct irq_domain *domain;
-
-	if (WARN_ON((info->flags & MSI_FLAG_LEVEL_CAPABLE)))
-		info->flags &= ~MSI_FLAG_LEVEL_CAPABLE;
-	if (info->flags & MSI_FLAG_USE_DEF_DOM_OPS)
-		fsl_mc_msi_update_dom_ops(info);
-	if (info->flags & MSI_FLAG_USE_DEF_CHIP_OPS)
-		fsl_mc_msi_update_chip_ops(info);
-	info->flags |= MSI_FLAG_ALLOC_SIMPLE_MSI_DESCS | MSI_FLAG_FREE_MSI_DESCS;
-
-	domain = msi_create_irq_domain(fwnode, info, parent);
-	if (domain)
-		irq_domain_update_bus_token(domain, DOMAIN_BUS_FSL_MC_MSI);
-
-	return domain;
-}
-
-struct irq_domain *fsl_mc_find_msi_domain(struct device *dev)
+struct irq_domain *fsl_mc_get_msi_parent(struct device *dev)
 {
+	struct fsl_mc_device *mc_dev = to_fsl_mc_device(dev);
 	struct device *root_dprc_dev;
 	struct device *bus_dev;
-	struct irq_domain *msi_domain;
-	struct fsl_mc_device *mc_dev = to_fsl_mc_device(dev);
 
 	fsl_mc_get_root_dprc(dev, &root_dprc_dev);
 	bus_dev = root_dprc_dev->parent;
 
-	if (bus_dev->of_node) {
-		msi_domain = of_msi_map_get_device_domain(dev,
-						  mc_dev->icid,
-						  DOMAIN_BUS_FSL_MC_MSI);
-
-		/*
-		 * if the msi-map property is missing assume that all the
-		 * child containers inherit the domain from the parent
-		 */
-		if (!msi_domain)
-
-			msi_domain = of_msi_get_domain(bus_dev,
-						bus_dev->of_node,
-						DOMAIN_BUS_FSL_MC_MSI);
-	} else {
-		msi_domain = iort_get_device_domain(dev, mc_dev->icid,
-						    DOMAIN_BUS_FSL_MC_MSI);
-	}
-
-	return msi_domain;
+	return (bus_dev->of_node ?
+		of_msi_get_domain(bus_dev, bus_dev->of_node, DOMAIN_BUS_NEXUS) :
+		iort_get_device_domain(bus_dev, mc_dev->icid, DOMAIN_BUS_NEXUS));
 }
 
 int fsl_mc_msi_domain_alloc_irqs(struct device *dev,  unsigned int irq_count)
 {
 	int error = msi_setup_device_data(dev);
-
 	if (error)
 		return error;
 
-	/*
-	 * NOTE: Calling this function will trigger the invocation of the
-	 * its_fsl_mc_msi_prepare() callback
-	 */
-	error = msi_domain_alloc_irqs_range(dev, MSI_DEFAULT_DOMAIN, 0, irq_count - 1);
-
+	error = platform_device_msi_init_and_alloc_irqs(dev, irq_count, fsl_mc_write_msi_msg);
 	if (error)
 		dev_err(dev, "Failed to allocate IRQs\n");
 	return error;
@@ -231,3 +103,15 @@ void fsl_mc_msi_domain_free_irqs(struct device *dev)
 {
 	msi_domain_free_irqs_all(dev, MSI_DEFAULT_DOMAIN);
 }
+
+u32 fsl_mc_get_msi_id(struct device *dev)
+{
+	struct fsl_mc_device *mc_dev = to_fsl_mc_device(dev);
+	struct device *root_dprc_dev;
+
+	fsl_mc_get_root_dprc(dev, &root_dprc_dev);
+
+	return (root_dprc_dev->parent->of_node ?
+		of_msi_xlate(dev, NULL, mc_dev->icid) :
+		iort_msi_map_id(dev, mc_dev->icid));
+}
diff --git a/drivers/bus/fsl-mc/fsl-mc-private.h b/drivers/bus/fsl-mc/fsl-mc-private.h
index beed4c53533d..197edcc8cde4 100644
--- a/drivers/bus/fsl-mc/fsl-mc-private.h
+++ b/drivers/bus/fsl-mc/fsl-mc-private.h
@@ -641,7 +641,7 @@ int fsl_mc_msi_domain_alloc_irqs(struct device *dev,
 
 void fsl_mc_msi_domain_free_irqs(struct device *dev);
 
-struct irq_domain *fsl_mc_find_msi_domain(struct device *dev);
+struct irq_domain *fsl_mc_get_msi_parent(struct device *dev);
 
 int __must_check fsl_create_mc_io(struct device *dev,
 				  phys_addr_t mc_portal_phys_addr,
diff --git a/drivers/char/ipmi/ipmi_kcs_sm.c b/drivers/char/ipmi/ipmi_kcs_sm.c
index efda90dcf5b3..c89055db39e5 100644
--- a/drivers/char/ipmi/ipmi_kcs_sm.c
+++ b/drivers/char/ipmi/ipmi_kcs_sm.c
@@ -102,7 +102,7 @@ enum kcs_states {
 /* Timeouts in microseconds. */
 #define IBF_RETRY_TIMEOUT (5*USEC_PER_SEC)
 #define OBF_RETRY_TIMEOUT (5*USEC_PER_SEC)
-#define MAX_ERROR_RETRIES 10
+#define MAX_ERROR_RETRIES 2
 #define ERROR0_OBF_WAIT_JIFFIES (2*HZ)
 
 struct si_sm_data {
diff --git a/drivers/char/ipmi/ipmi_si_intf.c b/drivers/char/ipmi/ipmi_si_intf.c
index 4a9e9de4d684..e46f4150ceb5 100644
--- a/drivers/char/ipmi/ipmi_si_intf.c
+++ b/drivers/char/ipmi/ipmi_si_intf.c
@@ -168,6 +168,9 @@ struct smi_info {
 			     OEM2_DATA_AVAIL)
 	unsigned char       msg_flags;
 
+	/* When requesting events and messages, don't do it forever. */
+	unsigned int        num_requests_in_a_row;
+
 	/* Does the BMC have an event buffer? */
 	bool		    has_event_buffer;
 
@@ -410,7 +413,10 @@ static void start_getting_msg_queue(struct smi_info *smi_info)
 
 	start_new_msg(smi_info, smi_info->curr_msg->data,
 		      smi_info->curr_msg->data_size);
-	smi_info->si_state = SI_GETTING_MESSAGES;
+	if (smi_info->si_state != SI_GETTING_MESSAGES) {
+	    smi_info->num_requests_in_a_row = 0;
+	    smi_info->si_state = SI_GETTING_MESSAGES;
+	}
 }
 
 static void start_getting_events(struct smi_info *smi_info)
@@ -421,7 +427,10 @@ static void start_getting_events(struct smi_info *smi_info)
 
 	start_new_msg(smi_info, smi_info->curr_msg->data,
 		      smi_info->curr_msg->data_size);
-	smi_info->si_state = SI_GETTING_EVENTS;
+	if (smi_info->si_state != SI_GETTING_EVENTS) {
+	    smi_info->num_requests_in_a_row = 0;
+	    smi_info->si_state = SI_GETTING_EVENTS;
+	}
 }
 
 /*
@@ -487,15 +496,19 @@ static void handle_flags(struct smi_info *smi_info)
 	} else if (smi_info->msg_flags & RECEIVE_MSG_AVAIL) {
 		/* Messages available. */
 		smi_info->curr_msg = alloc_msg_handle_irq(smi_info);
-		if (!smi_info->curr_msg)
+		if (!smi_info->curr_msg) {
+			smi_info->si_state = SI_NORMAL;
 			return;
+		}
 
 		start_getting_msg_queue(smi_info);
 	} else if (smi_info->msg_flags & EVENT_MSG_BUFFER_FULL) {
 		/* Events available. */
 		smi_info->curr_msg = alloc_msg_handle_irq(smi_info);
-		if (!smi_info->curr_msg)
+		if (!smi_info->curr_msg) {
+			smi_info->si_state = SI_NORMAL;
 			return;
+		}
 
 		start_getting_events(smi_info);
 	} else if (smi_info->msg_flags & OEM_DATA_AVAIL &&
@@ -630,7 +643,13 @@ static void handle_transaction_done(struct smi_info *smi_info)
 		 */
 		msg = smi_info->curr_msg;
 		smi_info->curr_msg = NULL;
-		if (msg->rsp[2] != 0) {
+		/*
+		 * It appears some BMCs, with no event data, return no
+		 * data in the message and not a 0x80 error as the
+		 * spec says they should.  Shut down processing if
+		 * the data is not the right length.
+		 */
+		if (msg->rsp[2] != 0 || msg->rsp_size != 19) {
 			/* Error getting event, probably done. */
 			msg->done(msg);
 
@@ -640,6 +659,11 @@ static void handle_transaction_done(struct smi_info *smi_info)
 		} else {
 			smi_inc_stat(smi_info, events);
 
+			smi_info->num_requests_in_a_row++;
+			if (smi_info->num_requests_in_a_row > 10)
+				/* Stop if we do this too many times. */
+				smi_info->msg_flags &= ~EVENT_MSG_BUFFER_FULL;
+
 			/*
 			 * Do this before we deliver the message
 			 * because delivering the message releases the
@@ -678,6 +702,11 @@ static void handle_transaction_done(struct smi_info *smi_info)
 		} else {
 			smi_inc_stat(smi_info, incoming_messages);
 
+			smi_info->num_requests_in_a_row++;
+			if (smi_info->num_requests_in_a_row > 10)
+				/* Stop if we do this too many times. */
+				smi_info->msg_flags &= ~RECEIVE_MSG_AVAIL;
+
 			/*
 			 * Do this before we deliver the message
 			 * because delivering the message releases the
diff --git a/drivers/char/ipmi/ipmi_ssif.c b/drivers/char/ipmi/ipmi_ssif.c
index b49500a1bd36..baf372900b63 100644
--- a/drivers/char/ipmi/ipmi_ssif.c
+++ b/drivers/char/ipmi/ipmi_ssif.c
@@ -225,6 +225,9 @@ struct ssif_info {
 	bool		    has_event_buffer;
 	bool		    supports_alert;
 
+	/* When requesting events and messages, don't do it forever. */
+	unsigned int        num_requests_in_a_row;
+
 	/*
 	 * Used to tell what we should do with alerts.  If we are
 	 * waiting on a response, read the data immediately.
@@ -413,6 +416,7 @@ static void start_event_fetch(struct ssif_info *ssif_info, unsigned long *flags)
 	}
 
 	ssif_info->curr_msg = msg;
+	ssif_info->num_requests_in_a_row = 0;
 	ssif_info->ssif_state = SSIF_GETTING_EVENTS;
 	ipmi_ssif_unlock_cond(ssif_info, flags);
 
@@ -436,6 +440,7 @@ static void start_recv_msg_fetch(struct ssif_info *ssif_info,
 	}
 
 	ssif_info->curr_msg = msg;
+	ssif_info->num_requests_in_a_row = 0;
 	ssif_info->ssif_state = SSIF_GETTING_MESSAGES;
 	ipmi_ssif_unlock_cond(ssif_info, flags);
 
@@ -843,6 +848,11 @@ static void msg_done_handler(struct ssif_info *ssif_info, int result,
 			ssif_info->msg_flags &= ~EVENT_MSG_BUFFER_FULL;
 			handle_flags(ssif_info, flags);
 		} else {
+			ssif_info->num_requests_in_a_row++;
+			if (ssif_info->num_requests_in_a_row > 10)
+				/* Stop if we do this too many times. */
+				ssif_info->msg_flags &= ~EVENT_MSG_BUFFER_FULL;
+
 			handle_flags(ssif_info, flags);
 			ssif_inc_stat(ssif_info, events);
 			deliver_recv_msg(ssif_info, msg);
@@ -876,6 +886,11 @@ static void msg_done_handler(struct ssif_info *ssif_info, int result,
 			ssif_info->msg_flags &= ~RECEIVE_MSG_AVAIL;
 			handle_flags(ssif_info, flags);
 		} else {
+			ssif_info->num_requests_in_a_row++;
+			if (ssif_info->num_requests_in_a_row > 10)
+				/* Stop if we do this too many times. */
+				ssif_info->msg_flags &= ~RECEIVE_MSG_AVAIL;
+
 			ssif_inc_stat(ssif_info, incoming_messages);
 			handle_flags(ssif_info, flags);
 			deliver_recv_msg(ssif_info, msg);
@@ -1886,6 +1901,7 @@ static int ssif_probe(struct i2c_client *client)
 					"kssif%4.4x", thread_num);
 	if (IS_ERR(ssif_info->thread)) {
 		rv = PTR_ERR(ssif_info->thread);
+		ssif_info->thread = NULL;
 		dev_notice(&ssif_info->client->dev,
 			   "Could not start kernel thread: error %d\n",
 			   rv);
diff --git a/drivers/clk/clk-scmi.c b/drivers/clk/clk-scmi.c
index 6b286ea6f121..7c562559ad8b 100644
--- a/drivers/clk/clk-scmi.c
+++ b/drivers/clk/clk-scmi.c
@@ -12,7 +12,6 @@
 #include <linux/of.h>
 #include <linux/module.h>
 #include <linux/scmi_protocol.h>
-#include <asm/div64.h>
 
 #define NOT_ATOMIC	false
 #define ATOMIC		true
@@ -57,35 +56,17 @@ static unsigned long scmi_clk_recalc_rate(struct clk_hw *hw,
 static int scmi_clk_determine_rate(struct clk_hw *hw,
 				   struct clk_rate_request *req)
 {
-	u64 fmin, fmax, ftmp;
+	int ret;
 	struct scmi_clk *clk = to_scmi_clk(hw);
 
 	/*
-	 * We can't figure out what rate it will be, so just return the
-	 * rate back to the caller. scmi_clk_recalc_rate() will be called
-	 * after the rate is set and we'll know what rate the clock is
+	 * If we could not get a better rate scmi_clk_recalc_rate() will be
+	 * called after the rate is set and we'll know what rate the clock is
 	 * running at then.
 	 */
-	if (clk->info->rate_discrete)
-		return 0;
-
-	fmin = clk->info->range.min_rate;
-	fmax = clk->info->range.max_rate;
-	if (req->rate <= fmin) {
-		req->rate = fmin;
-
-		return 0;
-	} else if (req->rate >= fmax) {
-		req->rate = fmax;
-
-		return 0;
-	}
-
-	ftmp = req->rate - fmin;
-	ftmp += clk->info->range.step_size - 1; /* to round up */
-	do_div(ftmp, clk->info->range.step_size);
-
-	req->rate = ftmp * clk->info->range.step_size + fmin;
+	ret = scmi_proto_clk_ops->determine_rate(clk->ph, clk->id, &req->rate);
+	if (ret)
+		return ret;
 
 	return 0;
 }
@@ -221,7 +202,6 @@ static int scmi_clk_ops_init(struct device *dev, struct scmi_clk *sclk,
 			     const struct clk_ops *scmi_ops)
 {
 	int ret;
-	unsigned long min_rate, max_rate;
 
 	struct clk_init_data init = {
 		.flags = CLK_GET_RATE_NOCACHE,
@@ -236,20 +216,8 @@ static int scmi_clk_ops_init(struct device *dev, struct scmi_clk *sclk,
 	if (ret)
 		return ret;
 
-	if (sclk->info->rate_discrete) {
-		int num_rates = sclk->info->list.num_rates;
-
-		if (num_rates <= 0)
-			return -EINVAL;
-
-		min_rate = sclk->info->list.rates[0];
-		max_rate = sclk->info->list.rates[num_rates - 1];
-	} else {
-		min_rate = sclk->info->range.min_rate;
-		max_rate = sclk->info->range.max_rate;
-	}
-
-	clk_hw_set_rate_range(&sclk->hw, min_rate, max_rate);
+	clk_hw_set_rate_range(&sclk->hw, sclk->info->min_rate,
+			      sclk->info->max_rate);
 	return ret;
 }
 
diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c
index 90aeff44a276..1de63e1a2cd2 100644
--- a/drivers/clocksource/arm_arch_timer.c
+++ b/drivers/clocksource/arm_arch_timer.c
@@ -28,6 +28,7 @@
 #include <linux/acpi.h>
 #include <linux/arm-smccc.h>
 #include <linux/ptp_kvm.h>
+#include <kunit/visibility.h>
 
 #include <asm/arch_timer.h>
 #include <asm/virt.h>
@@ -896,6 +897,7 @@ bool arch_timer_evtstrm_available(void)
 	 */
 	return cpumask_test_cpu(raw_smp_processor_id(), &evtstrm_available);
 }
+EXPORT_SYMBOL_IF_KUNIT(arch_timer_evtstrm_available);
 
 static struct arch_timer_kvm_info arch_timer_kvm_info;
 
diff --git a/drivers/clocksource/mmio.c b/drivers/clocksource/mmio.c
index cd5fbf49ac29..0fee8edb837a 100644
--- a/drivers/clocksource/mmio.c
+++ b/drivers/clocksource/mmio.c
@@ -21,21 +21,25 @@ u64 clocksource_mmio_readl_up(struct clocksource *c)
 {
 	return (u64)readl_relaxed(to_mmio_clksrc(c)->reg);
 }
+EXPORT_SYMBOL_GPL(clocksource_mmio_readl_up);
 
 u64 clocksource_mmio_readl_down(struct clocksource *c)
 {
 	return ~(u64)readl_relaxed(to_mmio_clksrc(c)->reg) & c->mask;
 }
+EXPORT_SYMBOL_GPL(clocksource_mmio_readl_down);
 
 u64 clocksource_mmio_readw_up(struct clocksource *c)
 {
 	return (u64)readw_relaxed(to_mmio_clksrc(c)->reg);
 }
+EXPORT_SYMBOL_GPL(clocksource_mmio_readw_up);
 
 u64 clocksource_mmio_readw_down(struct clocksource *c)
 {
 	return ~(u64)readw_relaxed(to_mmio_clksrc(c)->reg) & c->mask;
 }
+EXPORT_SYMBOL_GPL(clocksource_mmio_readw_down);
 
 /**
  * clocksource_mmio_init - Initialize a simple mmio based clocksource
@@ -46,9 +50,9 @@ u64 clocksource_mmio_readw_down(struct clocksource *c)
  * @bits:	Number of valid bits
  * @read:	One of clocksource_mmio_read*() above
  */
-int __init clocksource_mmio_init(void __iomem *base, const char *name,
-	unsigned long hz, int rating, unsigned bits,
-	u64 (*read)(struct clocksource *))
+int clocksource_mmio_init(void __iomem *base, const char *name,
+			  unsigned long hz, int rating, unsigned bits,
+			  u64 (*read)(struct clocksource *))
 {
 	struct clocksource_mmio *cs;
 
@@ -68,3 +72,4 @@ int __init clocksource_mmio_init(void __iomem *base, const char *name,
 
 	return clocksource_register_hz(&cs->clksrc, hz);
 }
+EXPORT_SYMBOL_GPL(clocksource_mmio_init);
diff --git a/drivers/clocksource/timer-of.c b/drivers/clocksource/timer-of.c
index 420202bf76e4..ba63433211b0 100644
--- a/drivers/clocksource/timer-of.c
+++ b/drivers/clocksource/timer-of.c
@@ -19,7 +19,7 @@
  *
  * Free the irq resource
  */
-static __init void timer_of_irq_exit(struct of_timer_irq *of_irq)
+static void timer_of_irq_exit(struct of_timer_irq *of_irq)
 {
 	struct timer_of *to = container_of(of_irq, struct timer_of, of_irq);
 
@@ -41,8 +41,8 @@ static __init void timer_of_irq_exit(struct of_timer_irq *of_irq)
  *
  * Returns 0 on success, < 0 otherwise
  */
-static __init int timer_of_irq_init(struct device_node *np,
-				    struct of_timer_irq *of_irq)
+static int timer_of_irq_init(struct device_node *np,
+			     struct of_timer_irq *of_irq)
 {
 	int ret;
 	struct timer_of *to = container_of(of_irq, struct timer_of, of_irq);
@@ -82,7 +82,7 @@ static __init int timer_of_irq_init(struct device_node *np,
  *
  * Disables and releases the refcount on the clk
  */
-static __init void timer_of_clk_exit(struct of_timer_clk *of_clk)
+static void timer_of_clk_exit(struct of_timer_clk *of_clk)
 {
 	of_clk->rate = 0;
 	clk_disable_unprepare(of_clk->clk);
@@ -98,8 +98,8 @@ static __init void timer_of_clk_exit(struct of_timer_clk *of_clk)
  *
  * Returns 0 on success, < 0 otherwise
  */
-static __init int timer_of_clk_init(struct device_node *np,
-				    struct of_timer_clk *of_clk)
+static int timer_of_clk_init(struct device_node *np,
+			     struct of_timer_clk *of_clk)
 {
 	int ret;
 
@@ -137,13 +137,13 @@ static __init int timer_of_clk_init(struct device_node *np,
 	goto out;
 }
 
-static __init void timer_of_base_exit(struct of_timer_base *of_base)
+static void timer_of_base_exit(struct of_timer_base *of_base)
 {
 	iounmap(of_base->base);
 }
 
-static __init int timer_of_base_init(struct device_node *np,
-				     struct of_timer_base *of_base)
+static  int timer_of_base_init(struct device_node *np,
+			       struct of_timer_base *of_base)
 {
 	of_base->base = of_base->name ?
 		of_io_request_and_map(np, of_base->index, of_base->name) :
@@ -156,7 +156,7 @@ static __init int timer_of_base_init(struct device_node *np,
 	return 0;
 }
 
-int __init timer_of_init(struct device_node *np, struct timer_of *to)
+int timer_of_init(struct device_node *np, struct timer_of *to)
 {
 	int ret = -EINVAL;
 	int flags = 0;
@@ -200,6 +200,7 @@ int __init timer_of_init(struct device_node *np, struct timer_of *to)
 		timer_of_base_exit(&to->of_base);
 	return ret;
 }
+EXPORT_SYMBOL_GPL(timer_of_init);
 
 /**
  * timer_of_cleanup - release timer_of resources
@@ -208,7 +209,7 @@ int __init timer_of_init(struct device_node *np, struct timer_of *to)
  * Release the resources that has been used in timer_of_init().
  * This function should be called in init error cases
  */
-void __init timer_of_cleanup(struct timer_of *to)
+void timer_of_cleanup(struct timer_of *to)
 {
 	if (to->flags & TIMER_OF_IRQ)
 		timer_of_irq_exit(&to->of_irq);
@@ -219,3 +220,4 @@ void __init timer_of_cleanup(struct timer_of *to)
 	if (to->flags & TIMER_OF_BASE)
 		timer_of_base_exit(&to->of_base);
 }
+EXPORT_SYMBOL_GPL(timer_of_cleanup);
diff --git a/drivers/clocksource/timer-of.h b/drivers/clocksource/timer-of.h
index 01a2c6b7db06..74a632b85b47 100644
--- a/drivers/clocksource/timer-of.h
+++ b/drivers/clocksource/timer-of.h
@@ -65,9 +65,8 @@ static inline unsigned long timer_of_period(struct timer_of *to)
 	return to->of_clk.period;
 }
 
-extern int __init timer_of_init(struct device_node *np,
-				struct timer_of *to);
+int timer_of_init(struct device_node *np, struct timer_of *to);
 
-extern void __init timer_of_cleanup(struct timer_of *to);
+void timer_of_cleanup(struct timer_of *to);
 
 #endif
diff --git a/drivers/clocksource/timer-rtl-otto.c b/drivers/clocksource/timer-rtl-otto.c
index 6113d2fdd4de..dd236a7babee 100644
--- a/drivers/clocksource/timer-rtl-otto.c
+++ b/drivers/clocksource/timer-rtl-otto.c
@@ -225,7 +225,7 @@ static int rttm_enable_clocksource(struct clocksource *cs)
 	return 0;
 }
 
-struct rttm_cs rttm_cs = {
+static struct rttm_cs rttm_cs = {
 	.to = {
 		.flags	= TIMER_OF_BASE | TIMER_OF_CLOCK,
 	},
diff --git a/drivers/clocksource/timer-sun5i.c b/drivers/clocksource/timer-sun5i.c
index f827d3f98f60..d7e012992170 100644
--- a/drivers/clocksource/timer-sun5i.c
+++ b/drivers/clocksource/timer-sun5i.c
@@ -286,6 +286,9 @@ static int sun5i_timer_probe(struct platform_device *pdev)
 	}
 
 	rstc = devm_reset_control_get_optional_exclusive(dev, NULL);
+	if (IS_ERR(rstc))
+		return dev_err_probe(dev, PTR_ERR(rstc),
+				     "failed to get reset\n");
 	if (rstc)
 		reset_control_deassert(rstc);
 
diff --git a/drivers/cpuidle/poll_state.c b/drivers/cpuidle/poll_state.c
index c7524e4c522a..7443b3e971ba 100644
--- a/drivers/cpuidle/poll_state.c
+++ b/drivers/cpuidle/poll_state.c
@@ -6,41 +6,22 @@
 #include <linux/cpuidle.h>
 #include <linux/export.h>
 #include <linux/irqflags.h>
-#include <linux/sched.h>
-#include <linux/sched/clock.h>
 #include <linux/sched/idle.h>
 #include <linux/sprintf.h>
 #include <linux/types.h>
 
-#define POLL_IDLE_RELAX_COUNT	200
-
 static int __cpuidle poll_idle(struct cpuidle_device *dev,
 			       struct cpuidle_driver *drv, int index)
 {
-	u64 time_start;
-
-	time_start = local_clock_noinstr();
-
 	dev->poll_time_limit = false;
 
 	raw_local_irq_enable();
 	if (!current_set_polling_and_test()) {
-		unsigned int loop_count = 0;
 		u64 limit;
 
 		limit = cpuidle_poll_time(drv, dev);
 
-		while (!need_resched()) {
-			cpu_relax();
-			if (loop_count++ < POLL_IDLE_RELAX_COUNT)
-				continue;
-
-			loop_count = 0;
-			if (local_clock_noinstr() - time_start > limit) {
-				dev->poll_time_limit = true;
-				break;
-			}
-		}
+		dev->poll_time_limit = !tif_need_resched_relaxed_wait(limit);
 	}
 	raw_local_irq_disable();
 
diff --git a/drivers/dax/bus.c b/drivers/dax/bus.c
index ccfe65004888..492573b47f66 100644
--- a/drivers/dax/bus.c
+++ b/drivers/dax/bus.c
@@ -1485,6 +1485,7 @@ static struct dev_dax *__devm_create_dev_dax(struct dev_dax_data *data)
 	}
 
 	dev = &dev_dax->dev;
+	dev->type = &dev_dax_type;
 	device_initialize(dev);
 	dev_set_name(dev, "dax%d.%d", dax_region->id, dev_dax->id);
 
@@ -1531,7 +1532,6 @@ static struct dev_dax *__devm_create_dev_dax(struct dev_dax_data *data)
 	dev->devt = inode->i_rdev;
 	dev->bus = &dax_bus_type;
 	dev->parent = parent;
-	dev->type = &dev_dax_type;
 
 	rc = device_add(dev);
 	if (rc) {
@@ -1554,14 +1554,13 @@ static struct dev_dax *__devm_create_dev_dax(struct dev_dax_data *data)
 	return dev_dax;
 
 err_alloc_dax:
-	kfree(dev_dax->pgmap);
 err_pgmap:
 	free_dev_dax_ranges(dev_dax);
 err_range:
-	free_dev_dax_id(dev_dax);
+	put_device(dev);
+	return ERR_PTR(rc);
 err_id:
 	kfree(dev_dax);
-
 	return ERR_PTR(rc);
 }
 
diff --git a/drivers/firmware/arm_scmi/base.c b/drivers/firmware/arm_scmi/base.c
index cd1331c2fc40..4df2620e3c5d 100644
--- a/drivers/firmware/arm_scmi/base.c
+++ b/drivers/firmware/arm_scmi/base.c
@@ -69,7 +69,7 @@ static int scmi_base_attributes_get(const struct scmi_protocol_handle *ph)
 	int ret;
 	struct scmi_xfer *t;
 	struct scmi_msg_resp_base_attributes *attr_info;
-	struct scmi_revision_info *rev = ph->get_priv(ph);
+	struct scmi_base_info *rev = ph->get_priv(ph);
 
 	ret = ph->xops->xfer_get_init(ph, PROTOCOL_ATTRIBUTES,
 				      0, sizeof(*attr_info), &t);
@@ -103,7 +103,7 @@ scmi_base_vendor_id_get(const struct scmi_protocol_handle *ph, bool sub_vendor)
 	int ret, size;
 	char *vendor_id;
 	struct scmi_xfer *t;
-	struct scmi_revision_info *rev = ph->get_priv(ph);
+	struct scmi_base_info *rev = ph->get_priv(ph);
 
 	if (sub_vendor) {
 		cmd = BASE_DISCOVER_SUB_VENDOR;
@@ -143,7 +143,7 @@ scmi_base_implementation_version_get(const struct scmi_protocol_handle *ph)
 	int ret;
 	__le32 *impl_ver;
 	struct scmi_xfer *t;
-	struct scmi_revision_info *rev = ph->get_priv(ph);
+	struct scmi_base_info *rev = ph->get_priv(ph);
 
 	ret = ph->xops->xfer_get_init(ph, BASE_DISCOVER_IMPLEMENT_VERSION,
 				      0, sizeof(*impl_ver), &t);
@@ -180,7 +180,7 @@ scmi_base_implementation_list_get(const struct scmi_protocol_handle *ph,
 	__le32 *num_skip, *num_ret;
 	u32 tot_num_ret = 0, loop_num_ret;
 	struct device *dev = ph->dev;
-	struct scmi_revision_info *rev = ph->get_priv(ph);
+	struct scmi_base_info *rev = ph->get_priv(ph);
 
 	ret = ph->xops->xfer_get_init(ph, BASE_DISCOVER_LIST_PROTOCOLS,
 				      sizeof(*num_skip), 0, &t);
@@ -377,7 +377,7 @@ static int scmi_base_protocol_init(const struct scmi_protocol_handle *ph)
 	u8 *prot_imp;
 	char name[SCMI_SHORT_NAME_MAX_SIZE];
 	struct device *dev = ph->dev;
-	struct scmi_revision_info *rev = scmi_revision_area_get(ph);
+	struct scmi_base_info *rev = scmi_revision_area_get(ph);
 
 	rev->major_ver = PROTOCOL_REV_MAJOR(ph->version);
 	rev->minor_ver = PROTOCOL_REV_MINOR(ph->version);
diff --git a/drivers/firmware/arm_scmi/clock.c b/drivers/firmware/arm_scmi/clock.c
index ab36871650a1..ce6f968925af 100644
--- a/drivers/firmware/arm_scmi/clock.c
+++ b/drivers/firmware/arm_scmi/clock.c
@@ -5,6 +5,7 @@
  * Copyright (C) 2018-2022 ARM Ltd.
  */
 
+#include <linux/math64.h>
 #include <linux/module.h>
 #include <linux/limits.h>
 #include <linux/sort.h>
@@ -156,13 +157,26 @@ struct scmi_clock_rate_notify_payld {
 	__le32 rate_high;
 };
 
+struct scmi_clock_desc {
+	u32 id;
+	unsigned int tot_rates;
+	struct scmi_clock_rates r;
+#define	RATE_MIN	0
+#define	RATE_MAX	1
+#define	RATE_STEP	2
+	struct scmi_clock_info info;
+};
+
+#define to_desc(p)	(container_of(p, struct scmi_clock_desc, info))
+
 struct clock_info {
 	int num_clocks;
 	int max_async_req;
 	bool notify_rate_changed_cmd;
 	bool notify_rate_change_requested_cmd;
 	atomic_t cur_async_req;
-	struct scmi_clock_info *clk;
+	struct scmi_clock_desc *clkds;
+#define CLOCK_INFO(c, i)	(&(((c)->clkds + (i))->info))
 	int (*clock_config_set)(const struct scmi_protocol_handle *ph,
 				u32 clk_id, enum clk_state state,
 				enum scmi_clock_oem_config oem_type,
@@ -184,7 +198,7 @@ scmi_clock_domain_lookup(struct clock_info *ci, u32 clk_id)
 	if (clk_id >= ci->num_clocks)
 		return ERR_PTR(-EINVAL);
 
-	return ci->clk + clk_id;
+	return CLOCK_INFO(ci, clk_id);
 }
 
 static int
@@ -225,8 +239,7 @@ scmi_clock_protocol_attributes_get(const struct scmi_protocol_handle *ph,
 
 struct scmi_clk_ipriv {
 	struct device *dev;
-	u32 clk_id;
-	struct scmi_clock_info *clk;
+	struct scmi_clock_desc *clkd;
 };
 
 static void iter_clk_possible_parents_prepare_message(void *message, unsigned int desc_index,
@@ -235,7 +248,7 @@ static void iter_clk_possible_parents_prepare_message(void *message, unsigned in
 	struct scmi_msg_clock_possible_parents *msg = message;
 	const struct scmi_clk_ipriv *p = priv;
 
-	msg->id = cpu_to_le32(p->clk_id);
+	msg->id = cpu_to_le32(p->clkd->id);
 	/* Set the number of OPPs to be skipped/already read */
 	msg->skip_parents = cpu_to_le32(desc_index);
 }
@@ -245,7 +258,6 @@ static int iter_clk_possible_parents_update_state(struct scmi_iterator_state *st
 {
 	const struct scmi_msg_resp_clock_possible_parents *r = response;
 	struct scmi_clk_ipriv *p = priv;
-	struct device *dev = ((struct scmi_clk_ipriv *)p)->dev;
 	u32 flags;
 
 	flags = le32_to_cpu(r->num_parent_flags);
@@ -257,14 +269,15 @@ static int iter_clk_possible_parents_update_state(struct scmi_iterator_state *st
 	 * assume it's returned+remaining on first call.
 	 */
 	if (!st->max_resources) {
-		p->clk->num_parents = st->num_returned + st->num_remaining;
-		p->clk->parents = devm_kcalloc(dev, p->clk->num_parents,
-					       sizeof(*p->clk->parents),
-					       GFP_KERNEL);
-		if (!p->clk->parents) {
-			p->clk->num_parents = 0;
+		int num_parents = st->num_returned + st->num_remaining;
+
+		p->clkd->info.parents = devm_kcalloc(p->dev, num_parents,
+						     sizeof(*p->clkd->info.parents),
+						     GFP_KERNEL);
+		if (!p->clkd->info.parents)
 			return -ENOMEM;
-		}
+
+		/* max_resources is used by the iterators to control bounds */
 		st->max_resources = st->num_returned + st->num_remaining;
 	}
 
@@ -279,29 +292,29 @@ static int iter_clk_possible_parents_process_response(const struct scmi_protocol
 	const struct scmi_msg_resp_clock_possible_parents *r = response;
 	struct scmi_clk_ipriv *p = priv;
 
-	u32 *parent = &p->clk->parents[st->desc_index + st->loop_idx];
+	p->clkd->info.parents[st->desc_index + st->loop_idx] =
+		le32_to_cpu(r->possible_parents[st->loop_idx]);
 
-	*parent = le32_to_cpu(r->possible_parents[st->loop_idx]);
+	/* Count only effectively discovered parents */
+	p->clkd->info.num_parents++;
 
 	return 0;
 }
 
-static int scmi_clock_possible_parents(const struct scmi_protocol_handle *ph, u32 clk_id,
-				       struct scmi_clock_info *clk)
+static int scmi_clock_possible_parents(const struct scmi_protocol_handle *ph,
+				       u32 clk_id, struct clock_info *cinfo)
 {
 	struct scmi_iterator_ops ops = {
 		.prepare_message = iter_clk_possible_parents_prepare_message,
 		.update_state = iter_clk_possible_parents_update_state,
 		.process_response = iter_clk_possible_parents_process_response,
 	};
-
+	struct scmi_clock_desc *clkd = &cinfo->clkds[clk_id];
 	struct scmi_clk_ipriv ppriv = {
-		.clk_id = clk_id,
-		.clk = clk,
+		.clkd = clkd,
 		.dev = ph->dev,
 	};
 	void *iter;
-	int ret;
 
 	iter = ph->hops->iter_response_init(ph, &ops, 0,
 					    CLOCK_POSSIBLE_PARENTS_GET,
@@ -310,9 +323,7 @@ static int scmi_clock_possible_parents(const struct scmi_protocol_handle *ph, u3
 	if (IS_ERR(iter))
 		return PTR_ERR(iter);
 
-	ret = ph->hops->iter_response_run(iter);
-
-	return ret;
+	return ph->hops->iter_response_run(iter);
 }
 
 static int
@@ -351,7 +362,7 @@ static int scmi_clock_attributes_get(const struct scmi_protocol_handle *ph,
 	u32 attributes;
 	struct scmi_xfer *t;
 	struct scmi_msg_resp_clock_attributes *attr;
-	struct scmi_clock_info *clk = cinfo->clk + clk_id;
+	struct scmi_clock_info *clk = CLOCK_INFO(cinfo, clk_id);
 
 	ret = ph->xops->xfer_get_init(ph, CLOCK_ATTRIBUTES,
 				      sizeof(clk_id), sizeof(*attr), &t);
@@ -392,10 +403,16 @@ static int scmi_clock_attributes_get(const struct scmi_protocol_handle *ph,
 		    SUPPORTS_RATE_CHANGE_REQUESTED_NOTIF(attributes))
 			clk->rate_change_requested_notifications = true;
 		if (PROTOCOL_REV_MAJOR(ph->version) >= 0x3) {
-			if (SUPPORTS_PARENT_CLOCK(attributes))
-				scmi_clock_possible_parents(ph, clk_id, clk);
-			if (SUPPORTS_GET_PERMISSIONS(attributes))
-				scmi_clock_get_permissions(ph, clk_id, clk);
+			if (SUPPORTS_PARENT_CLOCK(attributes)) {
+				ret = scmi_clock_possible_parents(ph, clk_id, cinfo);
+				if (ret)
+					return ret;
+			}
+			if (SUPPORTS_GET_PERMISSIONS(attributes)) {
+				ret = scmi_clock_get_permissions(ph, clk_id, clk);
+				if (ret)
+					return ret;
+			}
 			if (SUPPORTS_EXTENDED_CONFIG(attributes))
 				clk->extended_config = true;
 		}
@@ -423,7 +440,7 @@ static void iter_clk_describe_prepare_message(void *message,
 	struct scmi_msg_clock_describe_rates *msg = message;
 	const struct scmi_clk_ipriv *p = priv;
 
-	msg->id = cpu_to_le32(p->clk_id);
+	msg->id = cpu_to_le32(p->clkd->id);
 	/* Set the number of rates to be skipped/already read */
 	msg->rate_index = cpu_to_le32(desc_index);
 }
@@ -456,20 +473,33 @@ iter_clk_describe_update_state(struct scmi_iterator_state *st,
 	flags = le32_to_cpu(r->num_rates_flags);
 	st->num_remaining = NUM_REMAINING(flags);
 	st->num_returned = NUM_RETURNED(flags);
-	p->clk->rate_discrete = RATE_DISCRETE(flags);
+	p->clkd->r.rate_discrete = RATE_DISCRETE(flags);
 
 	/* Warn about out of spec replies ... */
-	if (!p->clk->rate_discrete &&
+	if (!p->clkd->r.rate_discrete &&
 	    (st->num_returned != 3 || st->num_remaining != 0)) {
 		dev_warn(p->dev,
 			 "Out-of-spec CLOCK_DESCRIBE_RATES reply for %s - returned:%d remaining:%d rx_len:%zd\n",
-			 p->clk->name, st->num_returned, st->num_remaining,
+			 p->clkd->info.name, st->num_returned, st->num_remaining,
 			 st->rx_len);
 
 		SCMI_QUIRK(clock_rates_triplet_out_of_spec,
 			   QUIRK_OUT_OF_SPEC_TRIPLET);
 	}
 
+	if (!st->max_resources) {
+		unsigned int tot_rates = st->num_returned + st->num_remaining;
+
+		p->clkd->r.rates = devm_kcalloc(p->dev, tot_rates,
+						sizeof(*p->clkd->r.rates), GFP_KERNEL);
+		if (!p->clkd->r.rates)
+			return -ENOMEM;
+
+		/* max_resources is used by the iterators to control bounds */
+		p->clkd->tot_rates = tot_rates;
+		st->max_resources = tot_rates;
+	}
+
 	return 0;
 }
 
@@ -478,38 +508,20 @@ iter_clk_describe_process_response(const struct scmi_protocol_handle *ph,
 				   const void *response,
 				   struct scmi_iterator_state *st, void *priv)
 {
-	int ret = 0;
 	struct scmi_clk_ipriv *p = priv;
 	const struct scmi_msg_resp_clock_describe_rates *r = response;
 
-	if (!p->clk->rate_discrete) {
-		switch (st->desc_index + st->loop_idx) {
-		case 0:
-			p->clk->range.min_rate = RATE_TO_U64(r->rate[0]);
-			break;
-		case 1:
-			p->clk->range.max_rate = RATE_TO_U64(r->rate[1]);
-			break;
-		case 2:
-			p->clk->range.step_size = RATE_TO_U64(r->rate[2]);
-			break;
-		default:
-			ret = -EINVAL;
-			break;
-		}
-	} else {
-		u64 *rate = &p->clk->list.rates[st->desc_index + st->loop_idx];
+	p->clkd->r.rates[p->clkd->r.num_rates] = RATE_TO_U64(r->rate[st->loop_idx]);
 
-		*rate = RATE_TO_U64(r->rate[st->loop_idx]);
-		p->clk->list.num_rates++;
-	}
+	/* Count only effectively discovered rates */
+	p->clkd->r.num_rates++;
 
-	return ret;
+	return 0;
 }
 
 static int
-scmi_clock_describe_rates_get(const struct scmi_protocol_handle *ph, u32 clk_id,
-			      struct scmi_clock_info *clk)
+scmi_clock_describe_rates_get_full(const struct scmi_protocol_handle *ph,
+				   struct scmi_clock_desc *clkd)
 {
 	int ret;
 	void *iter;
@@ -519,12 +531,16 @@ scmi_clock_describe_rates_get(const struct scmi_protocol_handle *ph, u32 clk_id,
 		.process_response = iter_clk_describe_process_response,
 	};
 	struct scmi_clk_ipriv cpriv = {
-		.clk_id = clk_id,
-		.clk = clk,
+		.clkd = clkd,
 		.dev = ph->dev,
 	};
 
-	iter = ph->hops->iter_response_init(ph, &ops, SCMI_MAX_NUM_RATES,
+	/*
+	 * Using tot_rates as max_resources parameter here so as to trigger
+	 * the dynamic allocation only when strictly needed: when trying a
+	 * full enumeration after a lazy one tot_rates will be non-zero.
+	 */
+	iter = ph->hops->iter_response_init(ph, &ops, clkd->tot_rates,
 					    CLOCK_DESCRIBE_RATES,
 					    sizeof(struct scmi_msg_clock_describe_rates),
 					    &cpriv);
@@ -535,18 +551,99 @@ scmi_clock_describe_rates_get(const struct scmi_protocol_handle *ph, u32 clk_id,
 	if (ret)
 		return ret;
 
-	if (!clk->rate_discrete) {
-		dev_dbg(ph->dev, "Min %llu Max %llu Step %llu Hz\n",
-			clk->range.min_rate, clk->range.max_rate,
-			clk->range.step_size);
-	} else if (clk->list.num_rates) {
-		sort(clk->list.rates, clk->list.num_rates,
-		     sizeof(clk->list.rates[0]), rate_cmp_func, NULL);
+	/* empty set ? */
+	if (!clkd->r.num_rates)
+		return 0;
+
+	if (clkd->r.rate_discrete && PROTOCOL_REV_MAJOR(ph->version) == 0x1)
+		sort(clkd->r.rates, clkd->r.num_rates,
+		     sizeof(clkd->r.rates[0]), rate_cmp_func, NULL);
+
+	return 0;
+}
+
+static int
+scmi_clock_describe_rates_get_lazy(const struct scmi_protocol_handle *ph,
+				   struct scmi_clock_desc *clkd)
+{
+	struct scmi_iterator_ops ops = {
+		.prepare_message = iter_clk_describe_prepare_message,
+		.update_state = iter_clk_describe_update_state,
+		.process_response = iter_clk_describe_process_response,
+	};
+	struct scmi_clk_ipriv cpriv = {
+		.clkd = clkd,
+		.dev = ph->dev,
+	};
+	unsigned int first, last;
+	void *iter;
+	int ret;
+
+	iter = ph->hops->iter_response_init(ph, &ops, 0, CLOCK_DESCRIBE_RATES,
+					    sizeof(struct scmi_msg_clock_describe_rates),
+					    &cpriv);
+	if (IS_ERR(iter))
+		return PTR_ERR(iter);
+
+	/* Try to grab a triplet, so that in case is NON-discrete we are done */
+	first = 0;
+	last = 2;
+	ret = ph->hops->iter_response_run_bound(iter, &first, &last);
+	if (ret)
+		goto out;
+
+	/*
+	 * If discrete and we don't already have it, grab the last value, which
+	 * should be the max
+	 */
+	if (clkd->r.rate_discrete && clkd->tot_rates > clkd->r.num_rates) {
+		first = clkd->tot_rates - 1;
+		last = clkd->tot_rates - 1;
+		ret = ph->hops->iter_response_run_bound(iter, &first, &last);
 	}
 
+out:
+	ph->hops->iter_response_bound_cleanup(iter);
+
 	return ret;
 }
 
+static int
+scmi_clock_describe_rates_get(const struct scmi_protocol_handle *ph,
+			      u32 clk_id, struct clock_info *cinfo)
+{
+	struct scmi_clock_desc *clkd = &cinfo->clkds[clk_id];
+	int ret;
+
+	/*
+	 * Since only after SCMI Clock v1.0 the returned rates are guaranteed to
+	 * be discovered in ascending order, lazy enumeration cannot be use for
+	 * SCMI Clock v1.0 protocol.
+	 */
+	if (PROTOCOL_REV_MAJOR(ph->version) > 0x1)
+		ret = scmi_clock_describe_rates_get_lazy(ph, clkd);
+	else
+		ret = scmi_clock_describe_rates_get_full(ph, clkd);
+
+	if (ret)
+		return ret;
+
+	clkd->info.min_rate = clkd->r.rates[RATE_MIN];
+	if (!clkd->r.rate_discrete) {
+		clkd->info.max_rate = clkd->r.rates[RATE_MAX];
+		dev_dbg(ph->dev, "Min %llu Max %llu Step %llu Hz\n",
+			clkd->r.rates[RATE_MIN], clkd->r.rates[RATE_MAX],
+			clkd->r.rates[RATE_STEP]);
+	} else {
+		clkd->info.max_rate = clkd->r.rates[clkd->r.num_rates - 1];
+		dev_dbg(ph->dev, "Clock:%s DISCRETE:%d -> Min %llu Max %llu\n",
+			clkd->info.name, clkd->r.rate_discrete,
+			clkd->info.min_rate, clkd->info.max_rate);
+	}
+
+	return 0;
+}
+
 static int
 scmi_clock_rate_get(const struct scmi_protocol_handle *ph,
 		    u32 clk_id, u64 *value)
@@ -624,6 +721,75 @@ static int scmi_clock_rate_set(const struct scmi_protocol_handle *ph,
 	return ret;
 }
 
+static int scmi_clock_determine_rate(const struct scmi_protocol_handle *ph,
+				     u32 clk_id, unsigned long *rate)
+{
+	u64 fmin, fmax, ftmp;
+	struct scmi_clock_info *clk;
+	struct scmi_clock_desc *clkd;
+	struct clock_info *ci = ph->get_priv(ph);
+
+	if (!rate)
+		return -EINVAL;
+
+	clk = scmi_clock_domain_lookup(ci, clk_id);
+	if (IS_ERR(clk))
+		return PTR_ERR(clk);
+
+	clkd = to_desc(clk);
+
+	/*
+	 * If we can't figure out what rate it will be, so just return the
+	 * rate back to the caller.
+	 */
+	if (clkd->r.rate_discrete)
+		return 0;
+
+	fmin = clk->min_rate;
+	fmax = clk->max_rate;
+	if (*rate <= fmin) {
+		*rate = fmin;
+		return 0;
+	} else if (*rate >= fmax) {
+		*rate = fmax;
+		return 0;
+	}
+
+	ftmp = *rate - fmin;
+	ftmp += clkd->r.rates[RATE_STEP] - 1; /* to round up */
+	ftmp = div64_ul(ftmp, clkd->r.rates[RATE_STEP]);
+
+	*rate = ftmp * clkd->r.rates[RATE_STEP] + fmin;
+
+	return 0;
+}
+
+static const struct scmi_clock_rates *
+scmi_clock_all_rates_get(const struct scmi_protocol_handle *ph, u32 clk_id)
+{
+	struct clock_info *ci = ph->get_priv(ph);
+	struct scmi_clock_desc *clkd;
+	struct scmi_clock_info *clk;
+
+	clk = scmi_clock_domain_lookup(ci, clk_id);
+	if (IS_ERR(clk) || !clk->name[0])
+		return NULL;
+
+	clkd = to_desc(clk);
+	/* Needs full enumeration ? */
+	if (clkd->r.rate_discrete && clkd->tot_rates != clkd->r.num_rates) {
+		int ret;
+
+		/* rates[] is already allocated BUT we need to re-enumerate */
+		clkd->r.num_rates = 0;
+		ret = scmi_clock_describe_rates_get_full(ph, clkd);
+		if (ret)
+			return NULL;
+	}
+
+	return &clkd->r;
+}
+
 static int
 scmi_clock_config_set(const struct scmi_protocol_handle *ph, u32 clk_id,
 		      enum clk_state state,
@@ -936,6 +1102,8 @@ static const struct scmi_clk_proto_ops clk_proto_ops = {
 	.info_get = scmi_clock_info_get,
 	.rate_get = scmi_clock_rate_get,
 	.rate_set = scmi_clock_rate_set,
+	.determine_rate = scmi_clock_determine_rate,
+	.all_rates_get = scmi_clock_all_rates_get,
 	.enable = scmi_clock_enable,
 	.disable = scmi_clock_disable,
 	.state_get = scmi_clock_state_get,
@@ -1080,17 +1248,20 @@ static int scmi_clock_protocol_init(const struct scmi_protocol_handle *ph)
 	if (ret)
 		return ret;
 
-	cinfo->clk = devm_kcalloc(ph->dev, cinfo->num_clocks,
-				  sizeof(*cinfo->clk), GFP_KERNEL);
-	if (!cinfo->clk)
+	cinfo->clkds = devm_kcalloc(ph->dev, cinfo->num_clocks,
+				    sizeof(*cinfo->clkds), GFP_KERNEL);
+	if (!cinfo->clkds)
 		return -ENOMEM;
 
 	for (clkid = 0; clkid < cinfo->num_clocks; clkid++) {
-		struct scmi_clock_info *clk = cinfo->clk + clkid;
-
+		cinfo->clkds[clkid].id = clkid;
 		ret = scmi_clock_attributes_get(ph, clkid, cinfo);
-		if (!ret)
-			scmi_clock_describe_rates_get(ph, clkid, clk);
+		if (ret)
+			return ret;
+
+		ret = scmi_clock_describe_rates_get(ph, clkid, cinfo);
+		if (ret)
+			return ret;
 	}
 
 	if (PROTOCOL_REV_MAJOR(ph->version) >= 0x3) {
diff --git a/drivers/firmware/arm_scmi/common.h b/drivers/firmware/arm_scmi/common.h
index 7c9617d080a0..07a127dec031 100644
--- a/drivers/firmware/arm_scmi/common.h
+++ b/drivers/firmware/arm_scmi/common.h
@@ -138,7 +138,7 @@ static inline void unpack_scmi_header(u32 msg_hdr, struct scmi_msg_hdr *hdr)
 	xfer_;							\
 })
 
-struct scmi_revision_info *
+struct scmi_base_info *
 scmi_revision_area_get(const struct scmi_protocol_handle *ph);
 void scmi_setup_protocol_implemented(const struct scmi_protocol_handle *ph,
 				     u8 *prot_imp);
diff --git a/drivers/firmware/arm_scmi/driver.c b/drivers/firmware/arm_scmi/driver.c
index f167194f7cf6..3e0d975ec94c 100644
--- a/drivers/firmware/arm_scmi/driver.c
+++ b/drivers/firmware/arm_scmi/driver.c
@@ -17,6 +17,7 @@
 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
 
 #include <linux/bitmap.h>
+#include <linux/cleanup.h>
 #include <linux/debugfs.h>
 #include <linux/device.h>
 #include <linux/export.h>
@@ -133,7 +134,7 @@ struct scmi_protocol_instance {
  *	       usage.
  * @protocols_mtx: A mutex to protect protocols instances initialization.
  * @protocols_imp: List of protocols implemented, currently maximum of
- *		   scmi_revision_info.num_protocols elements allocated by the
+ *		   scmi_base_info.num_protocols elements allocated by the
  *		   base protocol
  * @active_protocols: IDR storing device_nodes for protocols actually defined
  *		      in the DT and confirmed as implemented by fw.
@@ -151,7 +152,7 @@ struct scmi_info {
 	int id;
 	struct device *dev;
 	const struct scmi_desc *desc;
-	struct scmi_revision_info version;
+	struct scmi_base_info version;
 	struct scmi_handle handle;
 	struct scmi_xfers_info tx_minfo;
 	struct scmi_xfers_info rx_minfo;
@@ -265,7 +266,7 @@ scmi_vendor_protocol_lookup(int protocol_id, char *vendor_id,
 }
 
 static const struct scmi_protocol *
-scmi_vendor_protocol_get(int protocol_id, struct scmi_revision_info *version)
+scmi_vendor_protocol_get(int protocol_id, struct scmi_base_info *version)
 {
 	const struct scmi_protocol *proto;
 
@@ -303,7 +304,7 @@ scmi_vendor_protocol_get(int protocol_id, struct scmi_revision_info *version)
 }
 
 static const struct scmi_protocol *
-scmi_protocol_get(int protocol_id, struct scmi_revision_info *version)
+scmi_protocol_get(int protocol_id, struct scmi_base_info *version)
 {
 	const struct scmi_protocol *proto = NULL;
 
@@ -1789,86 +1790,115 @@ static void *scmi_iterator_init(const struct scmi_protocol_handle *ph,
 				size_t tx_size, void *priv)
 {
 	int ret;
-	struct scmi_iterator *i;
 
-	i = devm_kzalloc(ph->dev, sizeof(*i), GFP_KERNEL);
+	struct scmi_iterator *i __free(kfree) = kzalloc(sizeof(*i), GFP_KERNEL);
 	if (!i)
 		return ERR_PTR(-ENOMEM);
 
+	if (!ops || !ph)
+		return ERR_PTR(-EINVAL);
+
 	i->ph = ph;
 	i->ops = ops;
 	i->priv = priv;
 
 	ret = ph->xops->xfer_get_init(ph, msg_id, tx_size, 0, &i->t);
-	if (ret) {
-		devm_kfree(ph->dev, i);
+	if (ret)
 		return ERR_PTR(ret);
-	}
 
 	i->state.max_resources = max_resources;
 	i->msg = i->t->tx.buf;
 	i->resp = i->t->rx.buf;
 
-	return i;
+	return no_free_ptr(i);
 }
 
-static int scmi_iterator_run(void *iter)
+static int __scmi_iterator_run(void *iter, unsigned int *start, unsigned int *end)
 {
-	int ret = -EINVAL;
+	int ret;
 	struct scmi_iterator_ops *iops;
 	const struct scmi_protocol_handle *ph;
 	struct scmi_iterator_state *st;
-	struct scmi_iterator *i = iter;
+	struct scmi_iterator *i;
+	unsigned int n;
 
-	if (!i || !i->ops || !i->ph)
-		return ret;
+	if (!iter)
+		return -EINVAL;
 
+	i = iter;
 	iops = i->ops;
 	ph = i->ph;
 	st = &i->state;
 
+	/* Reinitialize state for next run */
+	st->num_returned = 0;
+	st->num_remaining = 0;
+	st->desc_index = start ? *start : 0;
+
 	do {
 		iops->prepare_message(i->msg, st->desc_index, i->priv);
 		ret = ph->xops->do_xfer(ph, i->t);
 		if (ret)
-			break;
+			return ret;
 
 		st->rx_len = i->t->rx.len;
 		ret = iops->update_state(st, i->resp, i->priv);
 		if (ret)
-			break;
+			return ret;
 
 		if (st->num_returned > st->max_resources - st->desc_index) {
 			dev_err(ph->dev,
 				"No. of resources can't exceed %d\n",
 				st->max_resources);
-			ret = -EINVAL;
-			break;
+			return -EINVAL;
 		}
 
-		for (st->loop_idx = 0; st->loop_idx < st->num_returned;
-		     st->loop_idx++) {
+		if (end)
+			n = min(st->num_returned, *end - st->desc_index + 1);
+		else
+			n = st->num_returned;
+		for (st->loop_idx = 0; st->loop_idx < n; st->loop_idx++) {
 			ret = iops->process_response(ph, i->resp, st, i->priv);
 			if (ret)
-				goto out;
+				return ret;
 		}
 
-		st->desc_index += st->num_returned;
+		st->desc_index += n;
 		ph->xops->reset_rx_to_maxsz(ph, i->t);
 		/*
 		 * check for both returned and remaining to avoid infinite
 		 * loop due to buggy firmware
 		 */
-	} while (st->num_returned && st->num_remaining);
+	} while (st->num_returned && st->num_remaining &&
+		 (!end || (st->desc_index <= min(*end, st->max_resources - 1))));
 
-out:
-	/* Finalize and destroy iterator */
-	ph->xops->xfer_put(ph, i->t);
-	devm_kfree(ph->dev, i);
+	return 0;
+}
+
+static void scmi_iterator_bound_cleanup(void *iter)
+{
+	struct scmi_iterator *i = iter;
+
+	i->ph->xops->xfer_put(i->ph, i->t);
+	kfree(i);
+}
+
+static int scmi_iterator_run(void *iter)
+{
+	int ret;
+
+	ret = __scmi_iterator_run(iter, NULL, NULL);
+	scmi_iterator_bound_cleanup(iter);
 
 	return ret;
 }
 
+static int scmi_iterator_run_bound(void *iter, unsigned int *start,
+				   unsigned int *end)
+{
+	return __scmi_iterator_run(iter, start, end);
+}
+
 struct scmi_msg_get_fc_info {
 	__le32 domain;
 	__le32 message_id;
@@ -2047,6 +2077,8 @@ static const struct scmi_proto_helpers_ops helpers_ops = {
 	.get_max_msg_size = scmi_common_get_max_msg_size,
 	.iter_response_init = scmi_iterator_init,
 	.iter_response_run = scmi_iterator_run,
+	.iter_response_run_bound = scmi_iterator_run_bound,
+	.iter_response_bound_cleanup = scmi_iterator_bound_cleanup,
 	.protocol_msg_check = scmi_protocol_msg_check,
 	.fastchannel_init = scmi_common_fastchannel_init,
 	.fastchannel_db_ring = scmi_common_fastchannel_db_ring,
@@ -2063,7 +2095,7 @@ static const struct scmi_proto_helpers_ops helpers_ops = {
  * Return: A reference to the version memory area associated to the SCMI
  *	   instance underlying this protocol handle.
  */
-struct scmi_revision_info *
+struct scmi_base_info *
 scmi_revision_area_get(const struct scmi_protocol_handle *ph)
 {
 	const struct scmi_protocol_instance *pi = ph_to_pi(ph);
@@ -2376,7 +2408,7 @@ scmi_is_protocol_implemented(const struct scmi_handle *handle, u8 prot_id)
 {
 	int i;
 	struct scmi_info *info = handle_to_scmi_info(handle);
-	struct scmi_revision_info *rev = handle->version;
+	struct scmi_base_info *rev = handle->version;
 
 	if (!info->protocols_imp)
 		return false;
@@ -2552,13 +2584,11 @@ static bool scmi_is_transport_atomic(const struct scmi_handle *handle,
  */
 static struct scmi_handle *scmi_handle_get(struct device *dev)
 {
-	struct list_head *p;
 	struct scmi_info *info;
 	struct scmi_handle *handle = NULL;
 
 	mutex_lock(&scmi_list_mutex);
-	list_for_each(p, &scmi_list) {
-		info = list_entry(p, struct scmi_info, node);
+	list_for_each_entry(info, &scmi_list, node) {
 		if (dev->parent == info->dev) {
 			info->users++;
 			handle = &info->handle;
@@ -3171,7 +3201,7 @@ static const struct scmi_desc *scmi_transport_setup(struct device *dev)
 
 static void scmi_enable_matching_quirks(struct scmi_info *info)
 {
-	struct scmi_revision_info *rev = &info->version;
+	struct scmi_base_info *rev = &info->version;
 
 	dev_dbg(info->dev, "Looking for quirks matching: %s/%s/0x%08X\n",
 		rev->vendor_id, rev->sub_vendor_id, rev->impl_ver);
diff --git a/drivers/firmware/arm_scmi/protocols.h b/drivers/firmware/arm_scmi/protocols.h
index f51245aca259..15ad5162e37a 100644
--- a/drivers/firmware/arm_scmi/protocols.h
+++ b/drivers/firmware/arm_scmi/protocols.h
@@ -259,7 +259,15 @@ struct scmi_fc_info {
  *			multi-part responses using the custom operations
  *			provided in @ops.
  * @iter_response_run: A common helper to trigger the run of a previously
- *		       initialized iterator.
+ *		       initialized iterator. Note that unbound iterators are
+ *		       automatically cleaned up.
+ * @iter_response_run_bound: A common helper to trigger the run of a previously
+ *			     initialized iterator, but only within the
+ *			     specified, optional, @start and @end resource
+ *			     indexes. Note that these bound-iterators need
+ *			     explicit cleanup via @iter_response_bound_cleanup.
+ * @iter_response_bound_cleanup: A common helper to finally release the iterator
+ *				 for bound iterators.
  * @protocol_msg_check: A common helper to check is a specific protocol message
  *			is supported.
  * @fastchannel_init: A common helper used to initialize FC descriptors by
@@ -276,6 +284,9 @@ struct scmi_proto_helpers_ops {
 				    unsigned int max_resources, u8 msg_id,
 				    size_t tx_size, void *priv);
 	int (*iter_response_run)(void *iter);
+	int (*iter_response_run_bound)(void *iter,
+				       unsigned int *start, unsigned int *end);
+	void (*iter_response_bound_cleanup)(void *iter);
 	int (*protocol_msg_check)(const struct scmi_protocol_handle *ph,
 				  u32 message_id, u32 *attributes);
 	void (*fastchannel_init)(const struct scmi_protocol_handle *ph,
diff --git a/drivers/firmware/arm_scmi/quirks.c b/drivers/firmware/arm_scmi/quirks.c
index 03848283c2a0..2b38ba3f59a1 100644
--- a/drivers/firmware/arm_scmi/quirks.c
+++ b/drivers/firmware/arm_scmi/quirks.c
@@ -238,16 +238,15 @@ static int scmi_quirk_range_parse(struct scmi_quirk *quirk)
 	if (sep)
 		*sep = '\0';
 
-	if (sep == first) /* -X */
-		ret = kstrtouint(first + 1, 0, &quirk->end_range);
-	else /* X OR X- OR X-y */
+	if (sep != first) /* X OR X- OR X-y */ {
 		ret = kstrtouint(first, 0, &quirk->start_range);
-	if (ret)
-		return ret;
+		if (ret)
+			return ret;
+	}
 
 	if (!sep)
 		quirk->end_range = quirk->start_range;
-	else if (sep != last) /* x-Y */
+	else if (sep != last) /* -X OR x-Y */
 		ret = kstrtouint(sep + 1, 0, &quirk->end_range);
 
 	if (quirk->start_range > quirk->end_range)
@@ -259,10 +258,8 @@ static int scmi_quirk_range_parse(struct scmi_quirk *quirk)
 void scmi_quirks_initialize(void)
 {
 	struct scmi_quirk *quirk;
-	int i;
 
-	for (i = 0, quirk = scmi_quirks_table[0]; quirk;
-	     i++, quirk = scmi_quirks_table[i]) {
+	for (unsigned int i = 0; (quirk = scmi_quirks_table[i]); i++) {
 		int ret;
 
 		ret = scmi_quirk_range_parse(quirk);
diff --git a/drivers/firmware/arm_scmi/vendors/imx/imx-sm-misc.c b/drivers/firmware/arm_scmi/vendors/imx/imx-sm-misc.c
index 0ada753367ef..637973fb45e6 100644
--- a/drivers/firmware/arm_scmi/vendors/imx/imx-sm-misc.c
+++ b/drivers/firmware/arm_scmi/vendors/imx/imx-sm-misc.c
@@ -27,6 +27,7 @@ enum scmi_imx_misc_protocol_cmd {
 	SCMI_IMX_MISC_CTRL_GET	= 0x4,
 	SCMI_IMX_MISC_DISCOVER_BUILD_INFO = 0x6,
 	SCMI_IMX_MISC_CTRL_NOTIFY = 0x8,
+	SCMI_IMX_MISC_RESET_REASON_GET = 0xA,
 	SCMI_IMX_MISC_CFG_INFO_GET = 0xC,
 	SCMI_IMX_MISC_SYSLOG_GET = 0xD,
 	SCMI_IMX_MISC_BOARD_INFO = 0xE,
@@ -89,6 +90,37 @@ struct scmi_imx_misc_cfg_info_out {
 	u8 cfgname[MISC_MAX_CFGNAME];
 };
 
+struct scmi_imx_misc_reset_reason_in {
+#define MISC_REASON_FLAG_SYSTEM	BIT(0)
+	__le32 flags;
+};
+
+struct scmi_imx_misc_reset_reason_out {
+	/* Boot reason flags */
+#define MISC_BOOT_FLAG_VLD		BIT(31)
+#define MISC_BOOT_FLAG_ORG_VLD		BIT(28)
+#define MISC_BOOT_FLAG_ORIGIN		GENMASK(27, 24)
+#define MISC_BOOT_FLAG_O_SHIFT		24
+#define MISC_BOOT_FLAG_ERR_VLD		BIT(23)
+#define MISC_BOOT_FLAG_ERR_ID		GENMASK(22, 8)
+#define MISC_BOOT_FLAG_E_SHIFT		8
+#define MISC_BOOT_FLAG_REASON		GENMASK(7, 0)
+	__le32 b_flags;
+	/* Shutdown reason flags */
+#define MISC_SHUTDOWN_FLAG_VLD		BIT(31)
+#define MISC_SHUTDOWN_FLAG_EXT_LEN	GENMASK(30, 29)
+#define MISC_SHUTDOWN_FLAG_ORG_VLD	BIT(28)
+#define MISC_SHUTDOWN_FLAG_ORIGIN	GENMASK(27, 24)
+#define MISC_SHUTDOWN_FLAG_O_SHIFT	24
+#define MISC_SHUTDOWN_FLAG_ERR_VLD	BIT(23)
+#define MISC_SHUTDOWN_FLAG_ERR_ID	GENMASK(22, 8)
+#define MISC_SHUTDOWN_FLAG_E_SHIFT	8
+#define MISC_SHUTDOWN_FLAG_REASON	GENMASK(7, 0)
+	__le32 s_flags;
+	/* Array of extended info words */
+	__le32 extinfo[MISC_EXT_INFO_LEN_MAX];
+};
+
 struct scmi_imx_misc_syslog_in {
 	__le32 flags;
 	__le32 index;
@@ -452,11 +484,65 @@ static int scmi_imx_misc_syslog_get(const struct scmi_protocol_handle *ph, u16 *
 	return ph->hops->iter_response_run(iter);
 }
 
+static int scmi_imx_misc_reset_reason(const struct scmi_protocol_handle *ph, bool system,
+				      struct scmi_imx_misc_reset_reason *boot_r,
+				      struct scmi_imx_misc_reset_reason *shut_r,
+				      u32 *extinfo)
+{
+	struct scmi_imx_misc_reset_reason_in *in;
+	struct scmi_imx_misc_reset_reason_out *out;
+	struct scmi_xfer *t;
+	int ret;
+
+	ret = ph->xops->xfer_get_init(ph, SCMI_IMX_MISC_RESET_REASON_GET, sizeof(*in),
+				      sizeof(*out), &t);
+	if (ret)
+		return ret;
+
+	in = t->tx.buf;
+	if (system)
+		in->flags = le32_encode_bits(1, MISC_REASON_FLAG_SYSTEM);
+	else
+		in->flags = cpu_to_le32(0);
+
+	ret = ph->xops->do_xfer(ph, t);
+	if (!ret) {
+		out = t->rx.buf;
+		if (boot_r) {
+			boot_r->valid = le32_get_bits(out->b_flags, MISC_BOOT_FLAG_VLD);
+			boot_r->orig_valid = le32_get_bits(out->b_flags, MISC_BOOT_FLAG_ORG_VLD);
+			boot_r->err_valid = le32_get_bits(out->b_flags, MISC_BOOT_FLAG_ERR_VLD);
+			boot_r->reason = le32_get_bits(out->b_flags, MISC_BOOT_FLAG_REASON);
+			boot_r->origin = le32_get_bits(out->b_flags, MISC_BOOT_FLAG_ORIGIN);
+			boot_r->errid = le32_get_bits(out->b_flags, MISC_BOOT_FLAG_ERR_ID);
+		}
+
+		if (shut_r) {
+			shut_r->valid = le32_get_bits(out->s_flags, MISC_SHUTDOWN_FLAG_VLD);
+			shut_r->orig_valid = le32_get_bits(out->s_flags,
+							   MISC_SHUTDOWN_FLAG_ORG_VLD);
+			shut_r->err_valid = le32_get_bits(out->s_flags,
+							  MISC_SHUTDOWN_FLAG_ERR_VLD);
+			shut_r->reason = le32_get_bits(out->s_flags, MISC_SHUTDOWN_FLAG_REASON);
+			shut_r->origin = le32_get_bits(out->s_flags, MISC_SHUTDOWN_FLAG_ORIGIN);
+			shut_r->errid = le32_get_bits(out->s_flags, MISC_SHUTDOWN_FLAG_ERR_ID);
+		}
+
+		if (extinfo)
+			memcpy_from_le32(extinfo, out->extinfo, MISC_EXT_INFO_LEN_MAX);
+	}
+
+	ph->xops->xfer_put(ph, t);
+
+	return ret;
+}
+
 static const struct scmi_imx_misc_proto_ops scmi_imx_misc_proto_ops = {
 	.misc_ctrl_set = scmi_imx_misc_ctrl_set,
 	.misc_ctrl_get = scmi_imx_misc_ctrl_get,
 	.misc_ctrl_req_notify = scmi_imx_misc_ctrl_notify,
 	.misc_syslog = scmi_imx_misc_syslog_get,
+	.misc_reset_reason = scmi_imx_misc_reset_reason,
 };
 
 static int scmi_imx_misc_protocol_init(const struct scmi_protocol_handle *ph)
diff --git a/drivers/firmware/imx/sm-misc.c b/drivers/firmware/imx/sm-misc.c
index 0a8ada329c9d..16b5ff833d21 100644
--- a/drivers/firmware/imx/sm-misc.c
+++ b/drivers/firmware/imx/sm-misc.c
@@ -18,6 +18,29 @@ static const struct scmi_imx_misc_proto_ops *imx_misc_ctrl_ops;
 static struct scmi_protocol_handle *ph;
 struct notifier_block scmi_imx_misc_ctrl_nb;
 
+static const char * const rst_imx95[] = {
+	"cm33_lockup", "cm33_swreq", "cm7_lockup", "cm7_swreq", "fccu",
+	"jtag_sw", "ele", "tempsense", "wdog1", "wdog2", "wdog3", "wdog4",
+	"wdog5", "jtag", "cm33_exc", "bbm", "sw", "sm_err", "fusa_sreco",
+	"pmic", "unused", "unused", "unused", "unused", "unused", "unused",
+	"unused", "unused", "unused", "unused", "unused", "por",
+};
+
+static const char * const rst_imx94[] = {
+	"cm33_lockup", "cm33_swreq", "cm70_lockup", "cm70_swreq", "fccu",
+	"jtag_sw", "ele", "tempsense", "wdog1", "wdog2", "wdog3", "wdog4",
+	"wdog5", "jtag", "wdog6", "wdog7", "wdog8", "wo_netc", "cm33s_lockup",
+	"cm33s_swreq", "cm71_lockup", "cm71_swreq", "cm33_exc", "bbm", "sw",
+	"sm_err", "fusa_sreco", "pmic", "unused", "unused", "unused", "por",
+};
+
+static const struct of_device_id allowlist[] = {
+	{ .compatible = "fsl,imx952", .data = rst_imx95 },
+	{ .compatible = "fsl,imx95", .data = rst_imx95 },
+	{ .compatible = "fsl,imx94", .data = rst_imx94 },
+	{ /* Sentinel */ }
+};
+
 int scmi_imx_misc_ctrl_set(u32 id, u32 val)
 {
 	if (!ph)
@@ -75,6 +98,54 @@ static void scmi_imx_misc_put(void *p)
 	debugfs_remove((struct dentry *)p);
 }
 
+static int scmi_imx_misc_get_reason(struct scmi_device *sdev)
+{
+	struct scmi_imx_misc_reset_reason boot, shutdown;
+	const char **rst;
+	bool system = true;
+	int ret;
+
+	if (!of_machine_device_match(allowlist))
+		return 0;
+
+	rst = (const char **)of_machine_get_match_data(allowlist);
+
+	ret = imx_misc_ctrl_ops->misc_reset_reason(ph, system, &boot, &shutdown, NULL);
+	if (!ret) {
+		if (boot.valid)
+			dev_info(&sdev->dev, "%s Boot reason: %s, origin: %d, errid: %d\n",
+				 system ? "SYS" : "LM", rst[boot.reason],
+				 boot.orig_valid ? boot.origin : -1,
+				 boot.err_valid ? boot.errid : -1);
+		if (shutdown.valid)
+			dev_info(&sdev->dev, "%s shutdown reason: %s, origin: %d, errid: %d\n",
+				 system ? "SYS" : "LM", rst[shutdown.reason],
+				 shutdown.orig_valid ? shutdown.origin : -1,
+				 shutdown.err_valid ? shutdown.errid : -1);
+	} else {
+		dev_err(&sdev->dev, "Failed to get system reset reason: %d\n", ret);
+	}
+
+	system = false;
+	ret = imx_misc_ctrl_ops->misc_reset_reason(ph, system, &boot, &shutdown, NULL);
+	if (!ret) {
+		if (boot.valid)
+			dev_info(&sdev->dev, "%s Boot reason: %s, origin: %d, errid: %d\n",
+				 system ? "SYS" : "LM", rst[boot.reason],
+				 boot.orig_valid ? boot.origin : -1,
+				 boot.err_valid ? boot.errid : -1);
+		if (shutdown.valid)
+			dev_info(&sdev->dev, "%s shutdown reason: %s, origin: %d, errid: %d\n",
+				 system ? "SYS" : "LM", rst[shutdown.reason],
+				 shutdown.orig_valid ? shutdown.origin : -1,
+				 shutdown.err_valid ? shutdown.errid : -1);
+	} else {
+		dev_err(&sdev->dev, "Failed to get lm reset reason: %d\n", ret);
+	}
+
+	return 0;
+}
+
 static int scmi_imx_misc_ctrl_probe(struct scmi_device *sdev)
 {
 	const struct scmi_handle *handle = sdev->handle;
@@ -133,6 +204,8 @@ static int scmi_imx_misc_ctrl_probe(struct scmi_device *sdev)
 	scmi_imx_dentry = debugfs_create_dir("scmi_imx", NULL);
 	debugfs_create_file("syslog", 0444, scmi_imx_dentry, &sdev->dev, &syslog_fops);
 
+	scmi_imx_misc_get_reason(sdev);
+
 	return devm_add_action_or_reset(&sdev->dev, scmi_imx_misc_put, scmi_imx_dentry);
 }
 
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 020e51e30317..f86e25da964b 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -806,7 +806,7 @@ config GPIO_VISCONTI
 	  Say yes here to support GPIO on Tohisba Visconti.
 
 config GPIO_WCD934X
-	tristate "Qualcomm Technologies Inc WCD9340/WCD9341 GPIO controller driver"
+	tristate "Qualcomm WCD9340/WCD9341 GPIO controller driver"
 	depends on MFD_WCD934X
 	help
          This driver is to support GPIO block found on the Qualcomm Technologies
diff --git a/drivers/gpio/gpio-pca953x.c b/drivers/gpio/gpio-pca953x.c
index 52e96cc5f67b..1fef733fe1f0 100644
--- a/drivers/gpio/gpio-pca953x.c
+++ b/drivers/gpio/gpio-pca953x.c
@@ -877,11 +877,9 @@ static void pca953x_irq_bus_sync_unlock(struct irq_data *d)
 	bitmap_or(irq_mask, chip->irq_trig_fall, chip->irq_trig_raise, gc->ngpio);
 	bitmap_or(irq_mask, irq_mask, chip->irq_trig_level_high, gc->ngpio);
 	bitmap_or(irq_mask, irq_mask, chip->irq_trig_level_low, gc->ngpio);
-	bitmap_complement(reg_direction, reg_direction, gc->ngpio);
-	bitmap_and(irq_mask, irq_mask, reg_direction, gc->ngpio);
 
 	/* Look for any newly setup interrupt */
-	for_each_set_bit(level, irq_mask, gc->ngpio)
+	for_each_andnot_bit(level, irq_mask, reg_direction, gc->ngpio)
 		pca953x_gpio_direction_input(&chip->gpio_chip, level);
 
 	mutex_unlock(&chip->irq_lock);
@@ -1005,8 +1003,7 @@ static bool pca953x_irq_pending(struct pca953x_chip *chip, unsigned long *pendin
 	bitmap_and(cur_stat, cur_stat, chip->irq_mask, gc->ngpio);
 	bitmap_or(pending, pending, cur_stat, gc->ngpio);
 
-	bitmap_complement(cur_stat, new_stat, gc->ngpio);
-	bitmap_and(cur_stat, cur_stat, reg_direction, gc->ngpio);
+	bitmap_andnot(cur_stat, reg_direction, new_stat, gc->ngpio);
 	bitmap_and(old_stat, cur_stat, chip->irq_trig_level_low, gc->ngpio);
 	bitmap_and(old_stat, old_stat, chip->irq_mask, gc->ngpio);
 	bitmap_or(pending, pending, old_stat, gc->ngpio);
diff --git a/drivers/gpio/gpio-usbio.c b/drivers/gpio/gpio-usbio.c
index 34d42c743d5b..489c8ac6299e 100644
--- a/drivers/gpio/gpio-usbio.c
+++ b/drivers/gpio/gpio-usbio.c
@@ -31,6 +31,7 @@ static const struct acpi_device_id usbio_gpio_acpi_hids[] = {
 	{ "INTC10B5" }, /* LNL */
 	{ "INTC10D1" }, /* MTL-CVF */
 	{ "INTC10E2" }, /* PTL */
+	{ "INTC1116" }, /* NVL */
 	{ }
 };
 
diff --git a/drivers/gpio/gpio-xilinx.c b/drivers/gpio/gpio-xilinx.c
index be4b4d730547..532205175827 100644
--- a/drivers/gpio/gpio-xilinx.c
+++ b/drivers/gpio/gpio-xilinx.c
@@ -495,13 +495,11 @@ static void xgpio_irqhandler(struct irq_desc *desc)
 
 	xgpio_read_ch_all(chip, XGPIO_DATA_OFFSET, hw);
 
-	bitmap_complement(rising, chip->last_irq_read, 64);
-	bitmap_and(rising, rising, hw, 64);
+	bitmap_andnot(rising, hw, chip->last_irq_read, 64);
 	bitmap_and(rising, rising, chip->enable, 64);
 	bitmap_and(rising, rising, chip->rising_edge, 64);
 
-	bitmap_complement(falling, hw, 64);
-	bitmap_and(falling, falling, chip->last_irq_read, 64);
+	bitmap_andnot(falling, chip->last_irq_read, hw, 64);
 	bitmap_and(falling, falling, chip->enable, 64);
 	bitmap_and(falling, falling, chip->falling_edge, 64);
 
diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
index db66c6372199..154a60e22c70 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -90,7 +90,7 @@ amdgpu-y += \
 	nbio_v7_2.o hdp_v4_0.o hdp_v5_0.o aldebaran_reg_init.o aldebaran.o soc21.o soc24.o \
 	sienna_cichlid.o smu_v13_0_10.o nbio_v4_3.o hdp_v6_0.o nbio_v7_7.o hdp_v5_2.o lsdma_v6_0.o \
 	nbio_v7_9.o aqua_vanjaram.o nbio_v7_11.o lsdma_v7_0.o hdp_v7_0.o nbif_v6_3_1.o \
-	cyan_skillfish_reg_init.o soc_v1_0.o lsdma_v7_1.o
+	cyan_skillfish_reg_init.o soc_v1_0.o lsdma_v7_1.o nbio_v6_3_2.o
 
 # add DF block
 amdgpu-y += \
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 8bc591deb546..695dac53fe08 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1462,6 +1462,8 @@ ssize_t amdgpu_get_soft_full_reset_mask(struct amdgpu_ring *ring);
 ssize_t amdgpu_show_reset_mask(char *buf, uint32_t supported_reset);
 void amdgpu_sdma_set_vm_pte_scheds(struct amdgpu_device *adev,
 				   const struct amdgpu_vm_pte_funcs *vm_pte_funcs);
+void amdgpu_sdma_set_buffer_funcs_scheds(struct amdgpu_device *adev,
+					 const struct amdgpu_buffer_funcs *buffer_funcs);
 
 /* atpx handler */
 #if defined(CONFIG_VGA_SWITCHEROO)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cper.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cper.c
index 4e6e390854e6..004edc28d0cc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cper.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cper.c
@@ -153,7 +153,7 @@ int amdgpu_cper_entry_fill_fatal_section(struct amdgpu_device *adev,
 		   FATAL_SEC_OFFSET(hdr->sec_cnt, idx));
 
 	amdgpu_cper_entry_fill_section_desc(adev, section_desc, false, false,
-					    CPER_SEV_FATAL, CRASHDUMP, FATAL_SEC_LEN,
+					    CPER_SEV_FATAL_UNCORRECTED, CRASHDUMP, FATAL_SEC_LEN,
 					    FATAL_SEC_OFFSET(hdr->sec_cnt, idx));
 
 	section->body.reg_ctx_type = CPER_CTX_TYPE_CRASH;
@@ -215,7 +215,7 @@ int amdgpu_cper_entry_fill_bad_page_threshold_section(struct amdgpu_device *adev
 		   NONSTD_SEC_OFFSET(hdr->sec_cnt, idx));
 
 	amdgpu_cper_entry_fill_section_desc(adev, section_desc, true, false,
-					    CPER_SEV_FATAL, RUNTIME, NONSTD_SEC_LEN,
+					    CPER_SEV_FATAL_UNCORRECTED, RUNTIME, NONSTD_SEC_LEN,
 					    NONSTD_SEC_OFFSET(hdr->sec_cnt, idx));
 
 	section->hdr.valid_bits.err_info_cnt = 1;
@@ -312,7 +312,7 @@ int amdgpu_cper_generate_ue_record(struct amdgpu_device *adev,
 	reg_data.synd_lo   = lower_32_bits(bank->regs[ACA_REG_IDX_SYND]);
 	reg_data.synd_hi   = upper_32_bits(bank->regs[ACA_REG_IDX_SYND]);
 
-	amdgpu_cper_entry_fill_hdr(adev, fatal, AMDGPU_CPER_TYPE_FATAL, CPER_SEV_FATAL);
+	amdgpu_cper_entry_fill_hdr(adev, fatal, AMDGPU_CPER_TYPE_FATAL, CPER_SEV_FATAL_UNCORRECTED);
 	ret = amdgpu_cper_entry_fill_fatal_section(adev, fatal, 0, reg_data);
 	if (ret)
 		return ret;
@@ -337,7 +337,7 @@ int amdgpu_cper_generate_bp_threshold_record(struct amdgpu_device *adev)
 
 	amdgpu_cper_entry_fill_hdr(adev, bp_threshold,
 				   AMDGPU_CPER_TYPE_BP_THRESHOLD,
-				   CPER_SEV_FATAL);
+				   CPER_SEV_FATAL_UNCORRECTED);
 	ret = amdgpu_cper_entry_fill_bad_page_threshold_section(adev, bp_threshold, 0);
 	if (ret)
 		return ret;
@@ -353,14 +353,14 @@ static enum cper_error_severity amdgpu_aca_err_type_to_cper_sev(struct amdgpu_de
 {
 	switch (aca_err_type) {
 	case ACA_ERROR_TYPE_UE:
-		return CPER_SEV_FATAL;
+		return CPER_SEV_FATAL_UNCORRECTED;
 	case ACA_ERROR_TYPE_CE:
 		return CPER_SEV_NON_FATAL_CORRECTED;
 	case ACA_ERROR_TYPE_DEFERRED:
 		return CPER_SEV_NON_FATAL_UNCORRECTED;
 	default:
 		dev_err(adev->dev, "Unknown ACA error type!\n");
-		return CPER_SEV_FATAL;
+		return CPER_SEV_FATAL_UNCORRECTED;
 	}
 }
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 737ef1ef96a5..7aa604fd9490 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -2460,7 +2460,7 @@ static int amdgpu_device_ip_init(struct amdgpu_device *adev)
 	if (r)
 		goto init_failed;
 
-	amdgpu_ttm_set_buffer_funcs_status(adev, true);
+	amdgpu_ttm_enable_buffer_funcs(adev);
 
 	/* Don't init kfd if whole hive need to be reset during init */
 	if (adev->init_lvl->level != AMDGPU_INIT_LEVEL_MINIMAL_XGMI) {
@@ -2839,8 +2839,12 @@ static int amdgpu_device_ip_fini_early(struct amdgpu_device *adev)
 	 * that checks whether the PSP is running. A solution for those issues
 	 * in the APU is to trigger a GPU reset, but this should be done during
 	 * the unload phase to avoid adding boot latency and screen flicker.
+	 * GFX V11 has GC block as default off IP. Every time AMDGPU driver sends
+	 * a request to PMFW to unload MP1, PMFW will put GC in reset and power down
+	 * the voltage. Hence, skipping reset for APUs with GFX V11 or later.
 	 */
-	if ((adev->flags & AMD_IS_APU) && !adev->gmc.is_app_apu) {
+	if ((adev->flags & AMD_IS_APU) && !adev->gmc.is_app_apu &&
+		amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(11, 0, 0)) {
 		r = amdgpu_asic_reset(adev);
 		if (r)
 			dev_err(adev->dev, "asic reset on %s failed\n", __func__);
@@ -3144,7 +3148,7 @@ static int amdgpu_device_ip_suspend(struct amdgpu_device *adev)
 		amdgpu_virt_request_full_gpu(adev, false);
 	}
 
-	amdgpu_ttm_set_buffer_funcs_status(adev, false);
+	amdgpu_ttm_disable_buffer_funcs(adev);
 
 	r = amdgpu_device_ip_suspend_phase1(adev);
 	if (r)
@@ -3359,7 +3363,7 @@ static int amdgpu_device_ip_resume(struct amdgpu_device *adev)
 
 	r = amdgpu_device_ip_resume_phase2(adev);
 
-	amdgpu_ttm_set_buffer_funcs_status(adev, true);
+	amdgpu_ttm_enable_buffer_funcs(adev);
 
 	if (r)
 		return r;
@@ -3697,7 +3701,7 @@ int amdgpu_device_init(struct amdgpu_device *adev,
 	adev->num_rings = 0;
 	RCU_INIT_POINTER(adev->gang_submit, dma_fence_get_stub());
 	adev->mman.buffer_funcs = NULL;
-	adev->mman.buffer_funcs_ring = NULL;
+	adev->mman.num_buffer_funcs_scheds = 0;
 	adev->vm_manager.vm_pte_funcs = NULL;
 	adev->vm_manager.vm_pte_num_scheds = 0;
 	adev->gmc.gmc_funcs = NULL;
@@ -4210,7 +4214,7 @@ void amdgpu_device_fini_hw(struct amdgpu_device *adev)
 	/* disable ras feature must before hw fini */
 	amdgpu_ras_pre_fini(adev);
 
-	amdgpu_ttm_set_buffer_funcs_status(adev, false);
+	amdgpu_ttm_disable_buffer_funcs(adev);
 
 	/*
 	 * device went through surprise hotplug; we need to destroy topology
@@ -4477,7 +4481,7 @@ int amdgpu_device_suspend(struct drm_device *dev, bool notify_clients)
 	if (r)
 		goto unwind_userq;
 
-	amdgpu_ttm_set_buffer_funcs_status(adev, false);
+	amdgpu_ttm_disable_buffer_funcs(adev);
 
 	amdgpu_fence_driver_hw_fini(adev);
 
@@ -4491,7 +4495,7 @@ int amdgpu_device_suspend(struct drm_device *dev, bool notify_clients)
 	return 0;
 
 unwind_evict:
-	amdgpu_ttm_set_buffer_funcs_status(adev, true);
+	amdgpu_ttm_enable_buffer_funcs(adev);
 	amdgpu_fence_driver_hw_init(adev);
 
 unwind_userq:
@@ -5225,7 +5229,7 @@ int amdgpu_device_reinit_after_reset(struct amdgpu_reset_context *reset_context)
 				if (r)
 					goto out;
 
-				amdgpu_ttm_set_buffer_funcs_status(tmp_adev, true);
+				amdgpu_ttm_enable_buffer_funcs(tmp_adev);
 
 				r = amdgpu_device_ip_resume_phase3(tmp_adev);
 				if (r)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index fcad7daaa41b..57cff29b3002 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -64,6 +64,7 @@
 #include "nbio_v7_2.h"
 #include "nbio_v7_7.h"
 #include "nbif_v6_3_1.h"
+#include "nbio_v6_3_2.h"
 #include "hdp_v5_0.h"
 #include "hdp_v5_2.h"
 #include "hdp_v6_0.h"
@@ -3195,6 +3196,9 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
 		adev->nbio.funcs = &nbif_v6_3_1_funcs;
 		adev->nbio.hdp_flush_reg = &nbif_v6_3_1_hdp_flush_reg;
 		break;
+	case IP_VERSION(6, 3, 2):
+		adev->nbio.funcs = &nbio_v6_3_2_funcs;
+		break;
 	default:
 		break;
 	}
@@ -3418,3 +3422,28 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
 	return 0;
 }
 
+int amdgpu_discovery_get_gc_major_minor_version(struct amdgpu_device *adev,
+						uint16_t *major, uint16_t *minor)
+{
+	uint8_t *discovery_bin = adev->discovery.bin;
+	struct table_info *info;
+	union gc_info *gc_info;
+	u16 offset;
+
+	if (!discovery_bin)
+		return -EINVAL;
+	if (amdgpu_discovery_get_table_info(adev, &info, GC))
+		return -EINVAL;
+
+	offset = le16_to_cpu(info->offset);
+	if (!offset)
+		return -EINVAL;
+
+	gc_info = (union gc_info *)(discovery_bin + offset);
+
+	if (major)
+		*major = le16_to_cpu(gc_info->v1.header.version_major);
+	if (minor)
+		*minor = le16_to_cpu(gc_info->v1.header.version_minor);
+	return 0;
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h
index 0ff1a7923eed..e0010f6a3eda 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.h
@@ -48,6 +48,8 @@ int amdgpu_discovery_get_nps_info(struct amdgpu_device *adev,
 				  uint32_t *nps_type,
 				  struct amdgpu_gmc_memrange *ranges,
 				  int *range_cnt, bool refresh);
+int amdgpu_discovery_get_gc_major_minor_version(struct amdgpu_device *adev,
+						uint16_t *major, uint16_t *minor);
 
 void amdgpu_discovery_dump(struct amdgpu_device *adev, struct drm_printer *p);
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
index e47921e2a9af..46aae3fad4bf 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
@@ -3158,8 +3158,10 @@ static int __init amdgpu_init(void)
 	amdgpu_register_atpx_handler();
 	amdgpu_acpi_detect();
 
-	/* Ignore KFD init failures. Normal when CONFIG_HSA_AMD is not set. */
-	amdgpu_amdkfd_init();
+	/* Ignore KFD init failures when CONFIG_HSA_AMD is not set. */
+	r = amdgpu_amdkfd_init();
+	if (r && r != -ENOENT)
+		goto error_fence;
 
 	if (amdgpu_pp_feature_mask & PP_OVERDRIVE_MASK) {
 		add_taint(TAINT_CPU_OUT_OF_SPEC, LOCKDEP_STILL_OK);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
index 5376035d32fe..9ef80bca4102 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
@@ -27,6 +27,7 @@
  */
 #include <linux/ktime.h>
 #include <linux/module.h>
+#include <linux/overflow.h>
 #include <linux/pagemap.h>
 #include <linux/pci.h>
 #include <linux/dma-buf.h>
@@ -1217,13 +1218,14 @@ int amdgpu_gem_list_handles_ioctl(struct drm_device *dev, void *data,
 	return ret;
 }
 
-static int amdgpu_gem_align_pitch(struct amdgpu_device *adev,
-				  int width,
-				  int cpp,
-				  bool tiled)
+static unsigned int amdgpu_gem_align_pitch(struct amdgpu_device *adev,
+					   unsigned int width,
+					   unsigned int cpp,
+					   bool tiled)
 {
-	int aligned = width;
-	int pitch_mask = 0;
+	unsigned int aligned = width;
+	unsigned int pitch_mask = 0;
+	unsigned int pitch;
 
 	switch (cpp) {
 	case 1:
@@ -1238,9 +1240,12 @@ static int amdgpu_gem_align_pitch(struct amdgpu_device *adev,
 		break;
 	}
 
-	aligned += pitch_mask;
+	if (check_add_overflow(aligned, pitch_mask, &aligned))
+		return 0;
 	aligned &= ~pitch_mask;
-	return aligned * cpp;
+	if (check_mul_overflow(aligned, cpp, &pitch))
+		return 0;
+	return pitch;
 }
 
 int amdgpu_mode_dumb_create(struct drm_file *file_priv,
@@ -1267,8 +1272,12 @@ int amdgpu_mode_dumb_create(struct drm_file *file_priv,
 
 	args->pitch = amdgpu_gem_align_pitch(adev, args->width,
 					     DIV_ROUND_UP(args->bpp, 8), 0);
+	if (!args->pitch)
+		return -EINVAL;
 	args->size = (u64)args->pitch * args->height;
 	args->size = ALIGN(args->size, PAGE_SIZE);
+	if (!args->size)
+		return -EINVAL;
 	domain = amdgpu_bo_get_preferred_domain(adev,
 				amdgpu_display_supported_domains(adev, flags));
 	r = amdgpu_gem_object_create(adev, args->size, 0, domain, flags,
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
index 285e217fba04..f1d9e12ebfc7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
@@ -314,7 +314,10 @@ void amdgpu_gmc_gart_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc,
 		mc->gart_start = max_mc_address - mc->gart_size + 1;
 		break;
 	case AMDGPU_GART_PLACEMENT_LOW:
-		mc->gart_start = 0;
+		if (size_bf >= mc->gart_size)
+			mc->gart_start = 0;
+		else
+			mc->gart_start = ALIGN(mc->fb_end, four_gb);
 		break;
 	case AMDGPU_GART_PLACEMENT_BEST_FIT:
 	default:
@@ -708,12 +711,14 @@ int amdgpu_gmc_allocate_vm_inv_eng(struct amdgpu_device *adev)
 void amdgpu_gmc_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
 			      uint32_t vmhub, uint32_t flush_type)
 {
-	struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
+	struct amdgpu_ring *ring;
 	struct amdgpu_vmhub *hub = &adev->vmhub[vmhub];
 	struct dma_fence *fence;
 	struct amdgpu_job *job;
 	int r;
 
+	ring = to_amdgpu_ring(adev->mman.buffer_funcs_scheds[0]);
+
 	if (!hub->sdma_invalidation_workaround || vmid ||
 	    !adev->mman.buffer_funcs_enabled || !adev->ib_pool_ready ||
 	    !ring->sched.ready) {
@@ -1002,6 +1007,9 @@ void amdgpu_gmc_noretry_set(struct amdgpu_device *adev)
 				gc_ver == IP_VERSION(9, 5, 0) ||
 				gc_ver >= IP_VERSION(10, 3, 0));
 
+	/* For GFX12.1 B0, set xnack (retry) on as default */
+	if (gc_ver == IP_VERSION(12, 1, 0) && (adev->rev_id & 0xf) == 0x1)
+		noretry_default = false;
 	if (!amdgpu_sriov_xnack_support(adev))
 		gmc->noretry = 1;
 	else
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
index f58b6be7fccc..444437c30088 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
@@ -91,6 +91,12 @@ struct amdgpu_ih_funcs {
 	uint64_t (*decode_iv_ts)(struct amdgpu_ih_ring *ih, u32 rptr,
 				 signed int offset);
 	void (*set_rptr)(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih);
+	/* Decode IH cookie node_id into a human-readable die name string.
+	 * Returns buf, or NULL if this IH version does not support node_id decoding.
+	 */
+	const char *(*node_id_to_die_name)(struct amdgpu_device *adev,
+					   unsigned int node_id,
+					   char *buf, size_t size);
 };
 
 #define amdgpu_ih_get_wptr(adev, ih) (adev)->irq.ih_funcs->get_wptr((adev), (ih))
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_imu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_imu.h
index 9c56be725ff3..eb8537558f5f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_imu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_imu.h
@@ -39,7 +39,6 @@ struct amdgpu_imu_funcs {
     int (*switch_compute_partition)(struct amdgpu_device *adev,
 				    int num_xccs_per_xcp,
 				    int compute_partition_mode);
-    void (*init_mcm_addr_lut)(struct amdgpu_device *adev);
 };
 
 struct imu_rlc_ram_golden {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 06efce38f323..71272f40feef 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -873,68 +873,59 @@ int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
 				    ? -EFAULT : 0;
 	}
 	case AMDGPU_INFO_READ_MMR_REG: {
-		int ret = 0;
-		unsigned int n, alloc_size;
-		uint32_t *regs;
 		unsigned int se_num = (info->read_mmr_reg.instance >>
 				   AMDGPU_INFO_MMR_SE_INDEX_SHIFT) &
 				  AMDGPU_INFO_MMR_SE_INDEX_MASK;
 		unsigned int sh_num = (info->read_mmr_reg.instance >>
 				   AMDGPU_INFO_MMR_SH_INDEX_SHIFT) &
 				  AMDGPU_INFO_MMR_SH_INDEX_MASK;
-
-		if (!down_read_trylock(&adev->reset_domain->sem))
-			return -ENOENT;
+		unsigned int alloc_size;
+		uint32_t *regs;
+		int ret;
 
 		/* set full masks if the userspace set all bits
 		 * in the bitfields
 		 */
-		if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK) {
+		if (se_num == AMDGPU_INFO_MMR_SE_INDEX_MASK)
 			se_num = 0xffffffff;
-		} else if (se_num >= AMDGPU_GFX_MAX_SE) {
-			ret = -EINVAL;
-			goto out;
-		}
+		else if (se_num >= AMDGPU_GFX_MAX_SE)
+			return -EINVAL;
 
-		if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK) {
+		if (sh_num == AMDGPU_INFO_MMR_SH_INDEX_MASK)
 			sh_num = 0xffffffff;
-		} else if (sh_num >= AMDGPU_GFX_MAX_SH_PER_SE) {
-			ret = -EINVAL;
-			goto out;
-		}
+		else if (sh_num >= AMDGPU_GFX_MAX_SH_PER_SE)
+			return -EINVAL;
 
-		if (info->read_mmr_reg.count > 128) {
-			ret = -EINVAL;
-			goto out;
-		}
+		if (info->read_mmr_reg.count > 128)
+			return -EINVAL;
 
-		regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs), GFP_KERNEL);
-		if (!regs) {
-			ret = -ENOMEM;
-			goto out;
-		}
+		regs = kmalloc_array(info->read_mmr_reg.count, sizeof(*regs),
+				     GFP_KERNEL);
+		if (!regs)
+			return -ENOMEM;
 
+		down_read(&adev->reset_domain->sem);
 		alloc_size = info->read_mmr_reg.count * sizeof(*regs);
-
 		amdgpu_gfx_off_ctrl(adev, false);
+		ret = 0;
 		for (i = 0; i < info->read_mmr_reg.count; i++) {
 			if (amdgpu_asic_read_register(adev, se_num, sh_num,
 						      info->read_mmr_reg.dword_offset + i,
 						      &regs[i])) {
 				DRM_DEBUG_KMS("unallowed offset %#x\n",
 					      info->read_mmr_reg.dword_offset + i);
-				kfree(regs);
-				amdgpu_gfx_off_ctrl(adev, true);
 				ret = -EFAULT;
-				goto out;
+				break;
 			}
 		}
 		amdgpu_gfx_off_ctrl(adev, true);
-		n = copy_to_user(out, regs, min(size, alloc_size));
-		kfree(regs);
-		ret = (n ? -EFAULT : 0);
-out:
 		up_read(&adev->reset_domain->sem);
+
+		if (!ret) {
+			ret = copy_to_user(out, regs, min(size, alloc_size))
+				? -EFAULT : 0;
+		}
+		kfree(regs);
 		return ret;
 	}
 	case AMDGPU_INFO_DEV_INFO: {
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
index 0d4c77c1b4b5..bdf2561b5404 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
@@ -103,7 +103,7 @@ static inline u32 amdgpu_mes_get_hqd_mask(u32 num_pipe,
 
 int amdgpu_mes_init(struct amdgpu_device *adev)
 {
-	int i, r, num_pipes;
+	int i, r, num_pipes, num_queues = 0;
 	u32 total_vmid_mask, reserved_vmid_mask;
 	int num_xcc = adev->gfx.xcc_mask ? NUM_XCC(adev->gfx.xcc_mask) : 1;
 	u32 gfx_hqd_mask = amdgpu_mes_get_hqd_mask(adev->gfx.me.num_pipe_per_me,
@@ -159,7 +159,8 @@ int amdgpu_mes_init(struct amdgpu_device *adev)
 		adev->mes.compute_hqd_mask[i] = compute_hqd_mask;
 	}
 
-	num_pipes = adev->sdma.num_instances;
+	num_pipes = adev->sdma.num_inst_per_xcc ?
+		adev->sdma.num_inst_per_xcc : adev->sdma.num_instances;
 	if (num_pipes > AMDGPU_MES_MAX_SDMA_PIPES)
 		dev_warn(adev->dev, "more SDMA pipes than supported by MES! (%d vs %d)\n",
 			 num_pipes, AMDGPU_MES_MAX_SDMA_PIPES);
@@ -216,8 +217,27 @@ int amdgpu_mes_init(struct amdgpu_device *adev)
 	if (r)
 		goto error_doorbell;
 
+	if (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(12, 1, 0)) {
+		/* When queue/pipe reset is done in MES instead of in the
+		 * driver, MES passes hung queues information to the driver in
+		 * hung_queue_hqd_info. Calculate required space to store this
+		 * information.
+		 */
+		for (i = 0; i < AMDGPU_MES_MAX_GFX_PIPES; i++)
+			num_queues += hweight32(adev->mes.gfx_hqd_mask[i]);
+
+		for (i = 0; i < AMDGPU_MES_MAX_COMPUTE_PIPES; i++)
+			num_queues += hweight32(adev->mes.compute_hqd_mask[i]);
+
+		for (i = 0; i < AMDGPU_MES_MAX_SDMA_PIPES; i++)
+			num_queues += hweight32(adev->mes.sdma_hqd_mask[i]) * num_xcc;
+
+		adev->mes.hung_queue_hqd_info_offset = num_queues;
+		adev->mes.hung_queue_db_array_size = num_queues * 2;
+	}
+
 	if (adev->mes.hung_queue_db_array_size) {
-		for (i = 0; i < AMDGPU_MAX_MES_PIPES * num_xcc; i++) {
+		for (i = 0; i < AMDGPU_MAX_MES_PIPES; i++) {
 			r = amdgpu_bo_create_kernel(adev,
 						    adev->mes.hung_queue_db_array_size * sizeof(u32),
 						    PAGE_SIZE,
@@ -264,10 +284,10 @@ void amdgpu_mes_fini(struct amdgpu_device *adev)
 			      &adev->mes.event_log_cpu_addr);
 
 	for (i = 0; i < AMDGPU_MAX_MES_PIPES * num_xcc; i++) {
-		amdgpu_bo_free_kernel(&adev->mes.hung_queue_db_array_gpu_obj[i],
-				      &adev->mes.hung_queue_db_array_gpu_addr[i],
-				      &adev->mes.hung_queue_db_array_cpu_addr[i]);
-
+		if (adev->mes.hung_queue_db_array_gpu_obj[i])
+			 amdgpu_bo_free_kernel(&adev->mes.hung_queue_db_array_gpu_obj[i],
+					 &adev->mes.hung_queue_db_array_gpu_addr[i],
+					 &adev->mes.hung_queue_db_array_cpu_addr[i]);
 		if (adev->mes.sch_ctx_ptr[i])
 			amdgpu_device_wb_free(adev, adev->mes.sch_ctx_offs[i]);
 		if (adev->mes.query_status_fence_ptr[i])
@@ -428,7 +448,7 @@ int amdgpu_mes_detect_and_reset_hung_queues(struct amdgpu_device *adev,
 {
 	struct mes_detect_and_reset_queue_input input;
 	u32 *db_array = adev->mes.hung_queue_db_array_cpu_addr[xcc_id];
-	int r, i;
+	int hqd_info_offset = adev->mes.hung_queue_hqd_info_offset, r, i;
 
 	if (!hung_db_num || !hung_db_array)
 		return -EINVAL;
@@ -446,23 +466,30 @@ int amdgpu_mes_detect_and_reset_hung_queues(struct amdgpu_device *adev,
 
 	r = adev->mes.funcs->detect_and_reset_hung_queues(&adev->mes,
 							  &input);
-	if (r) {
-		dev_err(adev->dev, "failed to detect and reset\n");
-	} else {
-		*hung_db_num = 0;
-		for (i = 0; i < adev->mes.hung_queue_hqd_info_offset; i++) {
-			if (db_array[i] != AMDGPU_MES_INVALID_DB_OFFSET) {
-				hung_db_array[i] = db_array[i];
-				*hung_db_num += 1;
-			}
+
+	if (r && detect_only) {
+		dev_err(adev->dev, "Failed to detect hung queues\n");
+		return r;
+	}
+
+	*hung_db_num = 0;
+	/* MES passes hung queues' doorbell to driver */
+	for (i = 0; i < adev->mes.hung_queue_hqd_info_offset; i++) {
+		/* Finding hung queues where db_array[i] is a valid doorbell */
+		if (db_array[i] != AMDGPU_MES_INVALID_DB_OFFSET) {
+			hung_db_array[i] = db_array[i];
+			*hung_db_num += 1;
 		}
+	}
 
-		/*
-		 * TODO: return HQD info for MES scheduled user compute queue reset cases
-		 * stored in hung_db_array hqd info offset to full array size
-		 */
+	if (r && !(*hung_db_num)) {
+		dev_err(adev->dev, "Failed to detect and reset hung queues\n");
+		return r;
 	}
 
+	for (i = hqd_info_offset; i < hqd_info_offset + *hung_db_num; i++)
+		hung_db_array[i] = db_array[i];
+
 	return r;
 }
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
index f80e3aca9c78..cafc5caae822 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
@@ -170,6 +170,19 @@ struct amdgpu_mes {
 	uint64_t            shared_cmd_buf_gpu_addr[AMDGPU_MAX_MES_INST_PIPES];
 };
 
+struct amdgpu_mes_hung_queue_hqd_info {
+	union {
+		struct {
+			u32 queue_type: 3; // queue type
+			u32 pipe_index: 4; // pipe index
+			u32 queue_index: 8; // queue index
+			u32 reserved: 17;
+		};
+
+		u32 bit0_31;
+	};
+};
+
 struct amdgpu_mes_gang {
 	int 				gang_id;
 	int 				priority;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
index 51ab1a332615..8069fc41cc7f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mode.h
@@ -38,7 +38,6 @@
 #include <drm/drm_probe_helper.h>
 #include <linux/i2c.h>
 #include <linux/i2c-algo-bit.h>
-#include <linux/hrtimer.h>
 #include "amdgpu_irq.h"
 
 #include <drm/display/drm_dp_mst_helper.h>
@@ -505,9 +504,6 @@ struct amdgpu_crtc {
 	u32 line_time;
 	u32 lb_vblank_lead_lines;
 	struct drm_display_mode hw_mode;
-	/* for virtual dce */
-	struct hrtimer vblank_timer;
-	enum amdgpu_interrupt_state vsync_timer_enabled;
 
 	int otg_inst;
 	struct drm_pending_vblank_event *event;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index b6aabac39b46..f98bfba59a2c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@ -717,13 +717,17 @@ int amdgpu_bo_create(struct amdgpu_device *adev,
 	    bo->tbo.resource->mem_type == TTM_PL_VRAM) {
 		struct dma_fence *fence;
 
-		r = amdgpu_ttm_clear_buffer(bo, bo->tbo.base.resv, &fence);
+		r = amdgpu_ttm_clear_buffer(amdgpu_ttm_next_clear_entity(adev),
+					    bo, bo->tbo.base.resv, &fence,
+					    true, AMDGPU_KERNEL_JOB_ID_TTM_CLEAR_BUFFER);
 		if (unlikely(r))
 			goto fail_unreserve;
 
-		dma_resv_add_fence(bo->tbo.base.resv, fence,
-				   DMA_RESV_USAGE_KERNEL);
-		dma_fence_put(fence);
+		if (fence) {
+			dma_resv_add_fence(bo->tbo.base.resv, fence,
+					   DMA_RESV_USAGE_KERNEL);
+			dma_fence_put(fence);
+		}
 	}
 	if (!bp->resv)
 		amdgpu_bo_unreserve(bo);
@@ -1325,9 +1329,9 @@ void amdgpu_bo_release_notify(struct ttm_buffer_object *bo)
 	if (r)
 		goto out;
 
-	r = amdgpu_fill_buffer(amdgpu_ttm_next_clear_entity(adev),
-			       abo, 0, &bo->base._resv,
-			       &fence, AMDGPU_KERNEL_JOB_ID_CLEAR_ON_RELEASE);
+	r = amdgpu_ttm_clear_buffer(amdgpu_ttm_next_clear_entity(adev),
+				    abo, &bo->base._resv, &fence,
+				    false, AMDGPU_KERNEL_JOB_ID_CLEAR_ON_RELEASE);
 	if (WARN_ON(r))
 		goto out;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index f0e4d020f4c7..4a64e39fa9cd 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -518,7 +518,7 @@ static int psp_sw_init(struct amdgpu_ip_block *ip_block)
 	}
 
 	ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG,
-				      (amdgpu_sriov_vf(adev) || adev->debug_use_vram_fw_buf) ?
+				      (amdgpu_sriov_vf(adev) || adev->debug_use_vram_fw_buf || adev->gmc.xgmi.connected_to_cpu) ?
 				      AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT,
 				      &psp->fw_pri_bo,
 				      &psp->fw_pri_mc_addr,
@@ -3527,7 +3527,12 @@ int psp_init_toc_microcode(struct psp_context *psp, const char *chip_name)
 	const struct psp_firmware_header_v1_0 *toc_hdr;
 	int err = 0;
 
-	err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, AMDGPU_UCODE_REQUIRED,
+	if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(15, 0, 8) &&
+	    adev->rev_id == 0)
+		err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, AMDGPU_UCODE_REQUIRED,
+				   "amdgpu/%s_toc_1.bin", chip_name);
+	else
+		err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, AMDGPU_UCODE_REQUIRED,
 				   "amdgpu/%s_toc.bin", chip_name);
 	if (err)
 		goto out;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
index cdf4909592d2..0c57fe259894 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.c
@@ -1950,7 +1950,7 @@ void amdgpu_ras_check_bad_page_status(struct amdgpu_device *adev)
 	if (!control || amdgpu_bad_page_threshold == 0)
 		return;
 
-	if (control->ras_num_bad_pages >= ras->bad_page_cnt_threshold) {
+	if (control->ras_num_bad_pages > ras->bad_page_cnt_threshold) {
 		if (amdgpu_dpm_send_rma_reason(adev))
 			dev_warn(adev->dev, "Unable to send out-of-band RMA CPER");
 		else
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index 0dc68fb9d88e..2740de94e93c 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -75,6 +75,9 @@ static int amdgpu_ttm_init_on_chip(struct amdgpu_device *adev,
 				    unsigned int type,
 				    uint64_t size_in_page)
 {
+	if (!size_in_page)
+		return 0;
+
 	return ttm_range_man_init(&adev->mman.bdev, type,
 				  false, size_in_page);
 }
@@ -168,7 +171,7 @@ amdgpu_ttm_job_submit(struct amdgpu_device *adev, struct amdgpu_ttm_buffer_entit
 {
 	struct amdgpu_ring *ring;
 
-	ring = adev->mman.buffer_funcs_ring;
+	ring = to_amdgpu_ring(adev->mman.buffer_funcs_scheds[0]);
 	amdgpu_ring_pad_ib(ring, &job->ibs[0]);
 	WARN_ON(job->ibs[0].length_dw > num_dw);
 
@@ -417,8 +420,8 @@ static int amdgpu_move_blit(struct ttm_buffer_object *bo,
 	if (old_mem->mem_type == TTM_PL_VRAM &&
 	    (abo->flags & AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE)) {
 		struct dma_fence *wipe_fence = NULL;
-		r = amdgpu_fill_buffer(entity, abo, 0, NULL, &wipe_fence,
-				       AMDGPU_KERNEL_JOB_ID_MOVE_BLIT);
+		r = amdgpu_ttm_clear_buffer(entity, abo, NULL, &wipe_fence,
+					    false, AMDGPU_KERNEL_JOB_ID_MOVE_BLIT);
 		if (r) {
 			goto error;
 		} else if (wipe_fence) {
@@ -1560,7 +1563,7 @@ static int amdgpu_ttm_access_memory_sdma(struct ttm_buffer_object *bo,
 	if (!adev->mman.sdma_access_ptr)
 		return -EACCES;
 
-	if (!drm_dev_enter(adev_to_drm(adev), &idx))
+	if (!adev->mman.buffer_funcs_enabled || !drm_dev_enter(adev_to_drm(adev), &idx))
 		return -ENODEV;
 
 	if (write)
@@ -1712,10 +1715,7 @@ static void amdgpu_ttm_init_fw_resv_region(struct amdgpu_device *adev)
 		reserve_size = max(reserve_size, (uint32_t)280 << 20);
 	else if (!adev->bios &&
 		 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(12, 1, 0)) {
-		if (hweight32(adev->aid_mask) == 1)
-			reserve_size = max(reserve_size, (uint32_t)128 << 20);
-		else
-			reserve_size = max(reserve_size, (uint32_t)144 << 20);
+		reserve_size = max(reserve_size, (uint32_t)150 << 20);
 	} else if (!reserve_size)
 		reserve_size = DISCOVERY_TMR_OFFSET;
 
@@ -2098,7 +2098,7 @@ int amdgpu_ttm_init(struct amdgpu_device *adev)
 	}
 
 	/* Change the size here instead of the init above so only lpfn is affected */
-	amdgpu_ttm_set_buffer_funcs_status(adev, false);
+	amdgpu_ttm_disable_buffer_funcs(adev);
 #ifdef CONFIG_64BIT
 #ifdef CONFIG_X86
 	if (adev->gmc.xgmi.connected_to_cpu)
@@ -2278,115 +2278,92 @@ void amdgpu_ttm_fini(struct amdgpu_device *adev)
 }
 
 /**
- * amdgpu_ttm_set_buffer_funcs_status - enable/disable use of buffer functions
+ * amdgpu_ttm_enable_buffer_funcs - enable use of buffer functions
  *
  * @adev: amdgpu_device pointer
- * @enable: true when we can use buffer functions.
  *
- * Enable/disable use of buffer functions during suspend/resume. This should
+ * Enable use of buffer functions during suspend/resume. This should
  * only be called at bootup or when userspace isn't running.
  */
-void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
+void amdgpu_ttm_enable_buffer_funcs(struct amdgpu_device *adev)
 {
 	struct ttm_resource_manager *man = ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM);
 	u32 num_clear_entities, num_move_entities;
-	uint64_t size;
 	int r, i, j;
 
 	if (!adev->mman.initialized || amdgpu_in_reset(adev) ||
-	    adev->mman.buffer_funcs_enabled == enable || adev->gmc.is_app_apu)
+	    adev->mman.buffer_funcs_enabled || adev->gmc.is_app_apu)
 		return;
 
-	if (enable) {
-		struct amdgpu_ring *ring;
-		struct drm_gpu_scheduler *sched;
+	if (!adev->mman.num_buffer_funcs_scheds) {
+		dev_warn(adev->dev, "Not enabling DMA transfers for in kernel use");
+		return;
+	}
 
-		if (!adev->mman.buffer_funcs_ring || !adev->mman.buffer_funcs_ring->sched.ready) {
-			dev_warn(adev->dev, "Not enabling DMA transfers for in kernel use");
-			return;
-		}
+	/* default_entity doesn't need multiple schedulers so pass only 1. */
+	r = amdgpu_ttm_buffer_entity_init(&adev->mman.gtt_mgr,
+						&adev->mman.default_entity,
+						DRM_SCHED_PRIORITY_KERNEL,
+						adev->mman.buffer_funcs_scheds, 1, 0);
+	if (r < 0) {
+		dev_err(adev->dev,
+			"Failed setting up TTM entity (%d)\n", r);
+		return;
+	}
 
-		num_clear_entities = 1;
-		num_move_entities = 1;
-		ring = adev->mman.buffer_funcs_ring;
-		sched = &ring->sched;
-		r = amdgpu_ttm_buffer_entity_init(&adev->mman.gtt_mgr,
-						  &adev->mman.default_entity,
-						  DRM_SCHED_PRIORITY_KERNEL,
-						  &sched, 1, 0);
-		if (r < 0) {
-			dev_err(adev->dev,
-				"Failed setting up TTM entity (%d)\n", r);
-			return;
-		}
+	num_clear_entities = MIN(adev->mman.num_buffer_funcs_scheds, TTM_NUM_MOVE_FENCES);
+	num_move_entities = MIN(adev->mman.num_buffer_funcs_scheds, TTM_NUM_MOVE_FENCES);
 
-		adev->mman.clear_entities = kcalloc(num_clear_entities,
-						    sizeof(struct amdgpu_ttm_buffer_entity),
-						    GFP_KERNEL);
-		atomic_set(&adev->mman.next_clear_entity, 0);
-		if (!adev->mman.clear_entities)
-			goto error_free_default_entity;
+	adev->mman.clear_entities = kcalloc(num_clear_entities,
+						sizeof(struct amdgpu_ttm_buffer_entity),
+						GFP_KERNEL);
+	atomic_set(&adev->mman.next_clear_entity, 0);
+	if (!adev->mman.clear_entities)
+		goto error_free_default_entity;
 
-		adev->mman.num_clear_entities = num_clear_entities;
-
-		for (i = 0; i < num_clear_entities; i++) {
-			r = amdgpu_ttm_buffer_entity_init(
-				&adev->mman.gtt_mgr, &adev->mman.clear_entities[i],
-				DRM_SCHED_PRIORITY_NORMAL, &sched, 1, 1);
-
-			if (r < 0) {
-				for (j = 0; j < i; j++)
-					amdgpu_ttm_buffer_entity_fini(
-						&adev->mman.gtt_mgr, &adev->mman.clear_entities[j]);
-				kfree(adev->mman.clear_entities);
-				adev->mman.num_clear_entities = 0;
-				adev->mman.clear_entities = NULL;
-				goto error_free_default_entity;
-			}
+	adev->mman.num_clear_entities = num_clear_entities;
+
+	for (i = 0; i < num_clear_entities; i++) {
+		r = amdgpu_ttm_buffer_entity_init(
+			&adev->mman.gtt_mgr,
+			&adev->mman.clear_entities[i],
+			DRM_SCHED_PRIORITY_KERNEL,
+			adev->mman.buffer_funcs_scheds,
+			adev->mman.num_buffer_funcs_scheds, 1);
+
+		if (r < 0) {
+			for (j = 0; j < i; j++)
+				amdgpu_ttm_buffer_entity_fini(
+					&adev->mman.gtt_mgr, &adev->mman.clear_entities[j]);
+			adev->mman.num_clear_entities = 0;
+			kfree(adev->mman.clear_entities);
+			goto error_free_default_entity;
 		}
+	}
 
-		adev->mman.num_move_entities = num_move_entities;
-		atomic_set(&adev->mman.next_move_entity, 0);
-		for (i = 0; i < num_move_entities; i++) {
-			r = amdgpu_ttm_buffer_entity_init(
-				&adev->mman.gtt_mgr,
-				&adev->mman.move_entities[i],
-				DRM_SCHED_PRIORITY_NORMAL, &sched, 1, 2);
-
-			if (r < 0) {
-				for (j = 0; j < i; j++)
-					amdgpu_ttm_buffer_entity_fini(
-						&adev->mman.gtt_mgr, &adev->mman.move_entities[j]);
-				adev->mman.num_move_entities = 0;
-				goto error_free_clear_entities;
-			}
+	adev->mman.num_move_entities = num_move_entities;
+	atomic_set(&adev->mman.next_move_entity, 0);
+	for (i = 0; i < num_move_entities; i++) {
+		r = amdgpu_ttm_buffer_entity_init(
+			&adev->mman.gtt_mgr,
+			&adev->mman.move_entities[i],
+			DRM_SCHED_PRIORITY_KERNEL,
+			adev->mman.buffer_funcs_scheds,
+			adev->mman.num_buffer_funcs_scheds, 2);
+
+		if (r < 0) {
+			for (j = 0; j < i; j++)
+				amdgpu_ttm_buffer_entity_fini(
+					&adev->mman.gtt_mgr,
+					&adev->mman.move_entities[j]);
+			adev->mman.num_move_entities = 0;
+			goto error_free_clear_entities;
 		}
-	} else {
-		amdgpu_ttm_buffer_entity_fini(&adev->mman.gtt_mgr,
-					      &adev->mman.default_entity);
-		for (i = 0; i < adev->mman.num_clear_entities; i++)
-			amdgpu_ttm_buffer_entity_fini(&adev->mman.gtt_mgr,
-						      &adev->mman.clear_entities[i]);
-		for (i = 0; i < adev->mman.num_move_entities; i++)
-			amdgpu_ttm_buffer_entity_fini(&adev->mman.gtt_mgr,
-						      &adev->mman.move_entities[i]);
-		/* Drop all the old fences since re-creating the scheduler entities
-		 * will allocate new contexts.
-		 */
-		ttm_resource_manager_cleanup(man);
-		kfree(adev->mman.clear_entities);
-		adev->mman.clear_entities = NULL;
-		adev->mman.num_clear_entities = 0;
-		adev->mman.num_move_entities = 0;
 	}
 
 	/* this just adjusts TTM size idea, which sets lpfn to the correct value */
-	if (enable)
-		size = adev->gmc.real_vram_size;
-	else
-		size = adev->gmc.visible_vram_size;
-	man->size = size;
-	adev->mman.buffer_funcs_enabled = enable;
+	man->size = adev->gmc.real_vram_size;
+	adev->mman.buffer_funcs_enabled = true;
 
 	return;
 
@@ -2402,6 +2379,42 @@ void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev, bool enable)
 				      &adev->mman.default_entity);
 }
 
+/**
+ * amdgpu_ttm_disable_buffer_funcs - disable use of buffer functions
+ *
+ * @adev: amdgpu_device pointer
+ */
+void amdgpu_ttm_disable_buffer_funcs(struct amdgpu_device *adev)
+{
+	struct ttm_resource_manager *man =
+		ttm_manager_type(&adev->mman.bdev, TTM_PL_VRAM);
+	int i;
+
+	if (!adev->mman.buffer_funcs_enabled || amdgpu_in_reset(adev))
+		return;
+
+	amdgpu_ttm_buffer_entity_fini(&adev->mman.gtt_mgr,
+				      &adev->mman.default_entity);
+	for (i = 0; i < adev->mman.num_move_entities; i++)
+		amdgpu_ttm_buffer_entity_fini(&adev->mman.gtt_mgr,
+					      &adev->mman.move_entities[i]);
+	for (i = 0; i < adev->mman.num_clear_entities; i++)
+		amdgpu_ttm_buffer_entity_fini(&adev->mman.gtt_mgr,
+					      &adev->mman.clear_entities[i]);
+	/* Drop all the old fences since re-creating the scheduler entities
+	 * will allocate new contexts.
+	 */
+	ttm_resource_manager_cleanup(man);
+
+	kfree(adev->mman.clear_entities);
+	adev->mman.clear_entities = NULL;
+	adev->mman.num_clear_entities = 0;
+	adev->mman.num_move_entities = 0;
+
+	man->size = adev->gmc.visible_vram_size;
+	adev->mman.buffer_funcs_enabled = false;
+}
+
 static int amdgpu_ttm_prepare_job(struct amdgpu_device *adev,
 				  struct amdgpu_ttm_buffer_entity *entity,
 				  unsigned int num_dw,
@@ -2446,7 +2459,7 @@ int amdgpu_copy_buffer(struct amdgpu_device *adev,
 	unsigned int i;
 	int r;
 
-	ring = adev->mman.buffer_funcs_ring;
+	ring = to_amdgpu_ring(adev->mman.buffer_funcs_scheds[0]);
 
 	if (!ring->sched.ready) {
 		dev_err(adev->dev,
@@ -2521,77 +2534,23 @@ static int amdgpu_ttm_fill_mem(struct amdgpu_device *adev,
 }
 
 /**
- * amdgpu_ttm_clear_buffer - clear memory buffers
- * @bo: amdgpu buffer object
- * @resv: reservation object
- * @fence: dma_fence associated with the operation
- *
- * Clear the memory buffer resource.
+ * amdgpu_ttm_clear_buffer - fill a buffer with 0
+ * @entity: entity to use
+ * @bo: the bo to fill
+ * @resv: fences contained in this reservation will be used as dependencies.
+ * @out_fence: the fence from the last clear will be stored here. It might be
+ *             NULL if no job was run.
+ * @consider_clear_status: true if region reported as cleared by amdgpu_res_cleared()
+ *                         are skipped.
+ * @k_job_id: trace id
  *
- * Returns:
- * 0 for success or a negative error code on failure.
  */
-int amdgpu_ttm_clear_buffer(struct amdgpu_bo *bo,
+int amdgpu_ttm_clear_buffer(struct amdgpu_ttm_buffer_entity *entity,
+			    struct amdgpu_bo *bo,
 			    struct dma_resv *resv,
-			    struct dma_fence **fence)
-{
-	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
-	struct amdgpu_ttm_buffer_entity *entity;
-	struct amdgpu_res_cursor cursor;
-	u64 addr;
-	int r = 0;
-
-	if (!adev->mman.buffer_funcs_enabled)
-		return -EINVAL;
-
-	if (!fence)
-		return -EINVAL;
-	entity = &adev->mman.clear_entities[0];
-	*fence = dma_fence_get_stub();
-
-	amdgpu_res_first(bo->tbo.resource, 0, amdgpu_bo_size(bo), &cursor);
-
-	mutex_lock(&entity->lock);
-	while (cursor.remaining) {
-		struct dma_fence *next = NULL;
-		u64 size;
-
-		if (amdgpu_res_cleared(&cursor)) {
-			amdgpu_res_next(&cursor, cursor.size);
-			continue;
-		}
-
-		/* Never clear more than 256MiB at once to avoid timeouts */
-		size = min(cursor.size, 256ULL << 20);
-
-		r = amdgpu_ttm_map_buffer(entity, &bo->tbo, bo->tbo.resource, &cursor,
-					  0, false, &size, &addr);
-		if (r)
-			goto err;
-
-		r = amdgpu_ttm_fill_mem(adev, entity, 0, addr, size, resv,
-					&next, true,
-					AMDGPU_KERNEL_JOB_ID_TTM_CLEAR_BUFFER);
-		if (r)
-			goto err;
-
-		dma_fence_put(*fence);
-		*fence = next;
-
-		amdgpu_res_next(&cursor, size);
-	}
-err:
-	mutex_unlock(&entity->lock);
-
-	return r;
-}
-
-int amdgpu_fill_buffer(struct amdgpu_ttm_buffer_entity *entity,
-		       struct amdgpu_bo *bo,
-		       uint32_t src_data,
-		       struct dma_resv *resv,
-		       struct dma_fence **f,
-		       u64 k_job_id)
+			    struct dma_fence **out_fence,
+			    bool consider_clear_status,
+			    u64 k_job_id)
 {
 	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 	struct dma_fence *fence = NULL;
@@ -2608,6 +2567,11 @@ int amdgpu_fill_buffer(struct amdgpu_ttm_buffer_entity *entity,
 		struct dma_fence *next;
 		uint64_t cur_size, to;
 
+		if (consider_clear_status && amdgpu_res_cleared(&dst)) {
+			amdgpu_res_next(&dst, dst.size);
+			continue;
+		}
+
 		/* Never fill more than 256MiB at once to avoid timeouts */
 		cur_size = min(dst.size, 256ULL << 20);
 
@@ -2617,7 +2581,7 @@ int amdgpu_fill_buffer(struct amdgpu_ttm_buffer_entity *entity,
 			goto error;
 
 		r = amdgpu_ttm_fill_mem(adev, entity,
-					src_data, to, cur_size, resv,
+					0, to, cur_size, resv,
 					&next, true, k_job_id);
 		if (r)
 			goto error;
@@ -2629,9 +2593,7 @@ int amdgpu_fill_buffer(struct amdgpu_ttm_buffer_entity *entity,
 	}
 error:
 	mutex_unlock(&entity->lock);
-	if (f)
-		*f = dma_fence_get(fence);
-	dma_fence_put(fence);
+	*out_fence = fence;
 	return r;
 }
 
@@ -2679,6 +2641,41 @@ int amdgpu_ttm_evict_resources(struct amdgpu_device *adev, int mem_type)
 	return ttm_resource_manager_evict_all(&adev->mman.bdev, man);
 }
 
+void amdgpu_sdma_set_buffer_funcs_scheds(struct amdgpu_device *adev,
+					 const struct amdgpu_buffer_funcs *buffer_funcs)
+{
+	struct drm_gpu_scheduler *sched;
+	struct amdgpu_vmhub *hub;
+	int i, n;
+
+	adev->mman.buffer_funcs = buffer_funcs;
+
+	for (i = 0, n = 0; i < adev->sdma.num_instances; i++) {
+		if (adev->sdma.has_page_queue)
+			sched = &adev->sdma.instance[i].page.sched;
+		else
+			sched = &adev->sdma.instance[i].ring.sched;
+
+		if (!sched->ready)
+			continue;
+
+		adev->mman.buffer_funcs_scheds[n++] = sched;
+	}
+
+	if (n == 0) {
+		adev->mman.num_buffer_funcs_scheds = 0;
+		drm_warn(&adev->ddev, "No working sdma ring available\n");
+		return;
+	}
+
+	/* Navi1x's workaround requires us to limit to a single SDMA sched
+	 * for ttm.
+	 */
+	hub = &adev->vmhub[AMDGPU_GFXHUB(0)];
+	adev->mman.num_buffer_funcs_scheds = hub->sdma_invalidation_workaround ?
+		1 : n;
+}
+
 #if defined(CONFIG_DEBUG_FS)
 
 static int amdgpu_ttm_page_pool_show(struct seq_file *m, void *unused)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
index f2f23a42b3cc..2d72fa217274 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
@@ -87,7 +87,8 @@ struct amdgpu_mman {
 
 	/* buffer handling */
 	const struct amdgpu_buffer_funcs	*buffer_funcs;
-	struct amdgpu_ring			*buffer_funcs_ring;
+	struct drm_gpu_scheduler		*buffer_funcs_scheds[AMDGPU_MAX_RINGS];
+	u32					num_buffer_funcs_scheds;
 	bool					buffer_funcs_enabled;
 
 	/* @default_entity: for workarounds, has no gart windows */
@@ -184,8 +185,8 @@ void amdgpu_ttm_unmark_vram_reserved(struct amdgpu_device *adev,
 
 int amdgpu_ttm_init(struct amdgpu_device *adev);
 void amdgpu_ttm_fini(struct amdgpu_device *adev);
-void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev,
-					bool enable);
+void amdgpu_ttm_enable_buffer_funcs(struct amdgpu_device *adev);
+void amdgpu_ttm_disable_buffer_funcs(struct amdgpu_device *adev);
 int amdgpu_copy_buffer(struct amdgpu_device *adev,
 		       struct amdgpu_ttm_buffer_entity *entity,
 		       uint64_t src_offset,
@@ -193,15 +194,12 @@ int amdgpu_copy_buffer(struct amdgpu_device *adev,
 		       struct dma_resv *resv,
 		       struct dma_fence **fence,
 		       bool vm_needs_flush, uint32_t copy_flags);
-int amdgpu_ttm_clear_buffer(struct amdgpu_bo *bo,
+int amdgpu_ttm_clear_buffer(struct amdgpu_ttm_buffer_entity *entity,
+			    struct amdgpu_bo *bo,
 			    struct dma_resv *resv,
-			    struct dma_fence **fence);
-int amdgpu_fill_buffer(struct amdgpu_ttm_buffer_entity *entity,
-		       struct amdgpu_bo *bo,
-		       uint32_t src_data,
-		       struct dma_resv *resv,
-		       struct dma_fence **f,
-		       u64 k_job_id);
+			    struct dma_fence **out_fence,
+			    bool consider_clear_status,
+			    u64 k_job_id);
 struct amdgpu_ttm_buffer_entity *amdgpu_ttm_next_clear_entity(struct amdgpu_device *adev);
 
 int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c
index d5abf785ca17..a15ca3e35344 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_userq.c
@@ -1187,7 +1187,7 @@ amdgpu_userq_vm_validate(struct amdgpu_userq_mgr *uq_mgr)
 			bo = range->bo;
 			ret = amdgpu_ttm_tt_get_user_pages(bo, range);
 			if (ret)
-				goto unlock_all;
+				goto free_ranges;
 		}
 
 		invalidated = true;
@@ -1214,6 +1214,7 @@ amdgpu_userq_vm_validate(struct amdgpu_userq_mgr *uq_mgr)
 
 unlock_all:
 	drm_exec_fini(&exec);
+free_ranges:
 	xa_for_each(&xa, tmp_key, range) {
 		if (!range)
 			continue;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
index e54295b56282..9f497e9c65b8 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.c
@@ -5,6 +5,7 @@
 #include <drm/drm_simple_kms_helper.h>
 #include <drm/drm_gem_framebuffer_helper.h>
 #include <drm/drm_vblank.h>
+#include <drm/drm_vblank_helper.h>
 
 #include "amdgpu.h"
 #ifdef CONFIG_DRM_AMDGPU_SI
@@ -42,81 +43,6 @@ static const u32 amdgpu_vkms_formats[] = {
 	DRM_FORMAT_XRGB8888,
 };
 
-static enum hrtimer_restart amdgpu_vkms_vblank_simulate(struct hrtimer *timer)
-{
-	struct amdgpu_crtc *amdgpu_crtc = container_of(timer, struct amdgpu_crtc, vblank_timer);
-	struct drm_crtc *crtc = &amdgpu_crtc->base;
-	struct amdgpu_vkms_output *output = drm_crtc_to_amdgpu_vkms_output(crtc);
-	u64 ret_overrun;
-	bool ret;
-
-	ret_overrun = hrtimer_forward_now(&amdgpu_crtc->vblank_timer,
-					  output->period_ns);
-	if (ret_overrun != 1)
-		drm_warn(amdgpu_crtc->base.dev,
-			 "%s: vblank timer overrun count: %llu\n",
-			 __func__, ret_overrun);
-
-	ret = drm_crtc_handle_vblank(crtc);
-	/* Don't queue timer again when vblank is disabled. */
-	if (!ret)
-		return HRTIMER_NORESTART;
-
-	return HRTIMER_RESTART;
-}
-
-static int amdgpu_vkms_enable_vblank(struct drm_crtc *crtc)
-{
-	struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(crtc);
-	struct amdgpu_vkms_output *out = drm_crtc_to_amdgpu_vkms_output(crtc);
-	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
-
-	drm_calc_timestamping_constants(crtc, &crtc->mode);
-
-	out->period_ns = ktime_set(0, vblank->framedur_ns);
-	hrtimer_start(&amdgpu_crtc->vblank_timer, out->period_ns, HRTIMER_MODE_REL);
-
-	return 0;
-}
-
-static void amdgpu_vkms_disable_vblank(struct drm_crtc *crtc)
-{
-	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
-
-	hrtimer_try_to_cancel(&amdgpu_crtc->vblank_timer);
-}
-
-static bool amdgpu_vkms_get_vblank_timestamp(struct drm_crtc *crtc,
-					     int *max_error,
-					     ktime_t *vblank_time,
-					     bool in_vblank_irq)
-{
-	struct amdgpu_vkms_output *output = drm_crtc_to_amdgpu_vkms_output(crtc);
-	struct drm_vblank_crtc *vblank = drm_crtc_vblank_crtc(crtc);
-	struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
-
-	if (!READ_ONCE(vblank->enabled)) {
-		*vblank_time = ktime_get();
-		return true;
-	}
-
-	*vblank_time = READ_ONCE(amdgpu_crtc->vblank_timer.node.expires);
-
-	if (WARN_ON(*vblank_time == vblank->time))
-		return true;
-
-	/*
-	 * To prevent races we roll the hrtimer forward before we do any
-	 * interrupt processing - this is how real hw works (the interrupt is
-	 * only generated after all the vblank registers are updated) and what
-	 * the vblank core expects. Therefore we need to always correct the
-	 * timestampe by one frame.
-	 */
-	*vblank_time -= output->period_ns;
-
-	return true;
-}
-
 static const struct drm_crtc_funcs amdgpu_vkms_crtc_funcs = {
 	.set_config             = drm_atomic_helper_set_config,
 	.destroy                = drm_crtc_cleanup,
@@ -124,45 +50,11 @@ static const struct drm_crtc_funcs amdgpu_vkms_crtc_funcs = {
 	.reset                  = drm_atomic_helper_crtc_reset,
 	.atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
 	.atomic_destroy_state   = drm_atomic_helper_crtc_destroy_state,
-	.enable_vblank		= amdgpu_vkms_enable_vblank,
-	.disable_vblank		= amdgpu_vkms_disable_vblank,
-	.get_vblank_timestamp	= amdgpu_vkms_get_vblank_timestamp,
+	DRM_CRTC_VBLANK_TIMER_FUNCS,
 };
 
-static void amdgpu_vkms_crtc_atomic_enable(struct drm_crtc *crtc,
-					   struct drm_atomic_state *state)
-{
-	drm_crtc_vblank_on(crtc);
-}
-
-static void amdgpu_vkms_crtc_atomic_disable(struct drm_crtc *crtc,
-					    struct drm_atomic_state *state)
-{
-	drm_crtc_vblank_off(crtc);
-}
-
-static void amdgpu_vkms_crtc_atomic_flush(struct drm_crtc *crtc,
-					  struct drm_atomic_state *state)
-{
-	unsigned long flags;
-	if (crtc->state->event) {
-		spin_lock_irqsave(&crtc->dev->event_lock, flags);
-
-		if (drm_crtc_vblank_get(crtc) != 0)
-			drm_crtc_send_vblank_event(crtc, crtc->state->event);
-		else
-			drm_crtc_arm_vblank_event(crtc, crtc->state->event);
-
-		spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
-
-		crtc->state->event = NULL;
-	}
-}
-
 static const struct drm_crtc_helper_funcs amdgpu_vkms_crtc_helper_funcs = {
-	.atomic_flush	= amdgpu_vkms_crtc_atomic_flush,
-	.atomic_enable	= amdgpu_vkms_crtc_atomic_enable,
-	.atomic_disable	= amdgpu_vkms_crtc_atomic_disable,
+	DRM_CRTC_HELPER_VBLANK_FUNCS,
 };
 
 static int amdgpu_vkms_crtc_init(struct drm_device *dev, struct drm_crtc *crtc,
@@ -187,10 +79,6 @@ static int amdgpu_vkms_crtc_init(struct drm_device *dev, struct drm_crtc *crtc,
 	amdgpu_crtc->pll_id = ATOM_PPLL_INVALID;
 	amdgpu_crtc->encoder = NULL;
 	amdgpu_crtc->connector = NULL;
-	amdgpu_crtc->vsync_timer_enabled = AMDGPU_IRQ_STATE_DISABLE;
-
-	hrtimer_setup(&amdgpu_crtc->vblank_timer, &amdgpu_vkms_vblank_simulate, CLOCK_MONOTONIC,
-		      HRTIMER_MODE_REL);
 
 	return ret;
 }
@@ -538,11 +426,6 @@ static int amdgpu_vkms_sw_init(struct amdgpu_ip_block *ip_block)
 static int amdgpu_vkms_sw_fini(struct amdgpu_ip_block *ip_block)
 {
 	struct amdgpu_device *adev = ip_block->adev;
-	int i = 0;
-
-	for (i = 0; i < adev->mode_info.num_crtc; i++)
-		if (adev->mode_info.crtcs[i])
-			hrtimer_cancel(&adev->mode_info.crtcs[i]->vblank_timer);
 
 	drm_kms_helper_poll_fini(adev_to_drm(adev));
 	drm_mode_config_cleanup(adev_to_drm(adev));
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 115a7b269af3..9ba9de16a27a 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -3023,11 +3023,22 @@ bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid,
 
 	is_compute_context = vm->is_compute_context;
 
-	if (is_compute_context && !svm_range_restore_pages(adev, pasid, vmid,
-	    node_id, addr >> PAGE_SHIFT, ts, write_fault)) {
+	if (is_compute_context) {
+		/* Unreserve root since svm_range_restore_pages might try to reserve it. */
+		/* TODO: rework svm_range_restore_pages so that this isn't necessary. */
 		amdgpu_bo_unreserve(root);
+
+		if (!svm_range_restore_pages(adev, pasid, vmid,
+					     node_id, addr >> PAGE_SHIFT, ts, write_fault)) {
+			amdgpu_bo_unref(&root);
+			return true;
+		}
 		amdgpu_bo_unref(&root);
-		return true;
+
+		/* Re-acquire the VM lock, could be that the VM was freed in between. */
+		vm = amdgpu_vm_lock_by_pasid(adev, &root, pasid);
+		if (!vm)
+			return false;
 	}
 
 	addr /= AMDGPU_GPU_PAGE_SIZE;
diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
index 22780c09177d..120da838ac28 100644
--- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
@@ -939,7 +939,6 @@ static int cik_sdma_early_init(struct amdgpu_ip_block *ip_block)
 
 	cik_sdma_set_ring_funcs(adev);
 	cik_sdma_set_irq_funcs(adev);
-	cik_sdma_set_buffer_funcs(adev);
 	amdgpu_sdma_set_vm_pte_scheds(adev, &cik_sdma_vm_pte_funcs);
 
 	return 0;
@@ -1000,8 +999,15 @@ static int cik_sdma_sw_fini(struct amdgpu_ip_block *ip_block)
 static int cik_sdma_hw_init(struct amdgpu_ip_block *ip_block)
 {
 	struct amdgpu_device *adev = ip_block->adev;
+	int r;
+
+	r = cik_sdma_start(adev);
+	if (r)
+		return r;
+
+	cik_sdma_set_buffer_funcs(adev);
 
-	return cik_sdma_start(adev);
+	return 0;
 }
 
 static int cik_sdma_hw_fini(struct amdgpu_ip_block *ip_block)
@@ -1340,8 +1346,7 @@ static const struct amdgpu_buffer_funcs cik_sdma_buffer_funcs = {
 
 static void cik_sdma_set_buffer_funcs(struct amdgpu_device *adev)
 {
-	adev->mman.buffer_funcs = &cik_sdma_buffer_funcs;
-	adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
+	amdgpu_sdma_set_buffer_funcs_scheds(adev, &cik_sdma_buffer_funcs);
 }
 
 const struct amdgpu_ip_block_version cik_sdma_ip_block =
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 8b60299b73ef..58c69dcb527f 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -7011,6 +7011,11 @@ static int gfx_v10_0_compute_mqd_init(struct amdgpu_device *adev, void *m,
 	tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
 	mqd->cp_hqd_ib_control = tmp;
 
+	tmp = REG_SET_FIELD(0, CP_HQD_QUANTUM, QUANTUM_EN, 1);
+	tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_SCALE, 1);
+	tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_DURATION, 1);
+	mqd->cp_hqd_quantum = tmp;
+
 	/* set static priority for a compute queue/ring */
 	mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority;
 	mqd->cp_hqd_queue_priority = prop->hqd_queue_priority;
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index 8c82e90f871b..837d98947958 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -4417,6 +4417,11 @@ static int gfx_v11_0_compute_mqd_init(struct amdgpu_device *adev, void *m,
 	mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority;
 	mqd->cp_hqd_queue_priority = prop->hqd_queue_priority;
 
+	tmp = REG_SET_FIELD(0, CP_HQD_QUANTUM, QUANTUM_EN, 1);
+	tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_SCALE, 1);
+	tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_DURATION, 1);
+	mqd->cp_hqd_quantum = tmp;
+
 	mqd->cp_hqd_active = prop->hqd_active;
 
 	/* set UQ fenceaddress */
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
index 65c33823a688..60f0c7d6a7a3 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_0.c
@@ -3268,6 +3268,11 @@ static int gfx_v12_0_compute_mqd_init(struct amdgpu_device *adev, void *m,
 	mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority;
 	mqd->cp_hqd_queue_priority = prop->hqd_queue_priority;
 
+	tmp = REG_SET_FIELD(0, CP_HQD_QUANTUM, QUANTUM_EN, 1);
+	tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_SCALE, 1);
+	tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_DURATION, 1);
+	mqd->cp_hqd_quantum = tmp;
+
 	mqd->cp_hqd_active = prop->hqd_active;
 
 	/* set UQ fenceaddress */
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
index 68fd3c04134d..5b5bfc379e9d 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1.c
@@ -61,7 +61,7 @@
 #define regCP_HQD_IB_CONTROL_DEFAULT                                              0x00100000
 
 MODULE_FIRMWARE("amdgpu/gc_12_1_0_mec.bin");
-MODULE_FIRMWARE("amdgpu/gc_12_1_0_rlc.bin");
+MODULE_FIRMWARE("amdgpu/gc_12_1_0_rlc_1.bin");
 
 #define SH_MEM_ALIGNMENT_MODE_UNALIGNED_GFX12_1_0	0x00000001
 #define DEFAULT_SH_MEM_CONFIG \
@@ -243,9 +243,9 @@ static void gfx_v12_1_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
 	amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
 	amdgpu_ring_write(ring,
 			  /* memory (1) or register (0) */
-			  (WAIT_REG_MEM_MEM_SPACE(mem_space) |
-			   WAIT_REG_MEM_OPERATION(opt) | /* wait */
-			   WAIT_REG_MEM_FUNCTION(3)));  /* equal */
+			  (PACKET3_WAIT_REG_MEM__MEM_SPACE(mem_space) |
+			   PACKET3_WAIT_REG_MEM__OPERATION(opt) | /* wait */
+			   PACKET3_WAIT_REG_MEM__FUNCTION(3)));  /* equal */
 
 	if (mem_space)
 		BUG_ON(addr0 & 0x3); /* Dword align */
@@ -335,7 +335,7 @@ static int gfx_v12_1_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 	}
 
 	ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
-	ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
+	ib.ptr[1] = PACKET3_WRITE_DATA__DST_SEL(5) | PACKET3_WRITE_DATA__WR_CONFIRM(1);
 	ib.ptr[2] = lower_32_bits(gpu_addr);
 	ib.ptr[3] = upper_32_bits(gpu_addr);
 	ib.ptr[4] = 0xDEADBEEF;
@@ -409,7 +409,13 @@ static int gfx_v12_1_init_microcode(struct amdgpu_device *adev)
 	amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix));
 
 	if (!amdgpu_sriov_vf(adev)) {
-		err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw,
+		if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(12, 1, 0) &&
+		    adev->rev_id == 0)
+			err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw,
+					   AMDGPU_UCODE_REQUIRED,
+					   "amdgpu/%s_rlc_1.bin", ucode_prefix);
+		else
+			err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw,
 					   AMDGPU_UCODE_REQUIRED,
 					   "amdgpu/%s_rlc.bin", ucode_prefix);
 		if (err)
@@ -712,10 +718,19 @@ static void gfx_v12_1_select_me_pipe_q(struct amdgpu_device *adev,
 	soc_v1_0_grbm_select(adev, me, pipe, q, vm, GET_INST(GC, xcc_id));
 }
 
+#define regGFX_IMU_PARTITION_SWITCH		0x5f8c
+#define regGFX_IMU_PARTITION_SWITCH_BASE_IDX	1
+#define GFX_IMU_PARTITION_SWITCH__TOTAL_XCCS_IN_XCP__SHIFT	0x2
+#define GFX_IMU_PARTITION_SWITCH__TOTAL_XCCS_IN_XCP_MASK		0x0000003CL
+
 static int gfx_v12_1_get_xccs_per_xcp(struct amdgpu_device *adev)
 {
-	/* Fill this in when the interface is ready */
-	return 1;
+	u32 reg_data;
+
+	/* the register data is expected to be the same on all instances */
+	reg_data = RREG32_SOC15(GC, GET_INST(GC, 0), regGFX_IMU_PARTITION_SWITCH);
+
+	return REG_GET_FIELD(reg_data, GFX_IMU_PARTITION_SWITCH, TOTAL_XCCS_IN_XCP);
 }
 
 static int gfx_v12_1_ih_to_xcc_inst(struct amdgpu_device *adev, int ih_node)
@@ -1136,6 +1151,7 @@ static int gfx_v12_1_rlc_backdoor_autoload_enable(struct amdgpu_device *adev)
 
 static int gfx_v12_1_sw_init(struct amdgpu_ip_block *ip_block)
 {
+	uint16_t major_ver, minor_ver;
 	int i, j, k, r, ring_id = 0;
 	unsigned num_compute_rings;
 	int xcc_id, num_xcc;
@@ -1146,6 +1162,15 @@ static int gfx_v12_1_sw_init(struct amdgpu_ip_block *ip_block)
 		adev->gfx.mec.num_mec = 1;
 		adev->gfx.mec.num_pipe_per_mec = 4;
 		adev->gfx.mec.num_queue_per_pipe = 8;
+
+		if (!amdgpu_discovery_get_gc_major_minor_version(
+			    adev, &major_ver, &minor_ver)) {
+			if (major_ver == 1 && minor_ver == 3) {
+				adev->gfx.config.max_cu_per_sh /= 2;
+				dev_dbg(adev->dev, "Halving max_cu_per_sh for GC Discovery table v1:3 %d\n",
+					adev->gfx.config.max_cu_per_sh);
+			}
+		}
 		break;
 	default:
 		adev->gfx.mec.num_mec = 2;
@@ -1450,6 +1475,19 @@ static void gfx_v12_1_get_tcc_info(struct amdgpu_device *adev)
 {
 }
 
+static void gfx_v12_1_xcc_xnack_set_chicken_bits(struct amdgpu_device *adev, int xcc_id)
+{
+	/* NOTE: COMPRESSION_ENABLE is used a chicken bit to enable/disable xcc xnack */
+	mutex_lock(&adev->srbm_mutex);
+	if (!adev->gmc.noretry) {
+		WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id),
+				      TCP_PERFCOUNTER_FILTER, COMPRESSION_ENABLE, 0x1);
+	} else
+		WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id),
+				      TCP_PERFCOUNTER_FILTER, COMPRESSION_ENABLE, 0x0);
+	mutex_unlock(&adev->srbm_mutex);
+}
+
 static void gfx_v12_1_xcc_constants_init(struct amdgpu_device *adev,
 					 int xcc_id)
 {
@@ -1477,6 +1515,8 @@ static void gfx_v12_1_xcc_constants_init(struct amdgpu_device *adev,
 	mutex_unlock(&adev->srbm_mutex);
 
 	gfx_v12_1_xcc_init_compute_vmid(adev, xcc_id);
+	gfx_v12_1_xcc_xnack_set_chicken_bits(adev, xcc_id);
+
 }
 
 static void gfx_v12_1_constants_init(struct amdgpu_device *adev)
@@ -2246,6 +2286,11 @@ static int gfx_v12_1_compute_mqd_init(struct amdgpu_device *adev, void *m,
 	mqd->cp_mqd_stride_size = prop->mqd_stride_size ? prop->mqd_stride_size :
 		AMDGPU_MQD_SIZE_ALIGN(adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size);
 
+	tmp = REG_SET_FIELD(0, CP_HQD_QUANTUM, QUANTUM_EN, 1);
+	tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_SCALE, 1);
+	tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_DURATION, 1);
+	mqd->cp_hqd_quantum = tmp;
+
 	mqd->cp_hqd_active = prop->hqd_active;
 
 	return 0;
@@ -3355,7 +3400,7 @@ static void gfx_v12_1_ring_emit_ib_compute(struct amdgpu_ring *ring,
 					   uint32_t flags)
 {
 	unsigned vmid = AMDGPU_JOB_GET_VMID(job);
-	u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
+	u32 control = PACKET3_INDIRECT_BUFFER__VALID(1) | ib->length_dw | (vmid << 24);
 
 	/* Currently, there is a high possibility to get wave ID mismatch
 	 * between ME and GDS, leading to a hw deadlock, because ME generates
@@ -3391,15 +3436,15 @@ static void gfx_v12_1_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
 
 	/* RELEASE_MEM - flush caches, send int */
 	amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
-	amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ(1) |
-				 PACKET3_RELEASE_MEM_GCR_GLV_WB |
-				 PACKET3_RELEASE_MEM_GCR_GL2_WB |
-				 PACKET3_RELEASE_MEM_GCR_GL2_SCOPE(2) |
-				 PACKET3_RELEASE_MEM_TEMPORAL(3) |
-				 PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
-				 PACKET3_RELEASE_MEM_EVENT_INDEX(5)));
-	amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) |
-				 PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0)));
+	amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM__GCR_SEQ(1) |
+				 PACKET3_RELEASE_MEM__GCR_GLV_WB |
+				 PACKET3_RELEASE_MEM__GCR_GL2_WB |
+				 PACKET3_RELEASE_MEM__GCR_GL2_SCOPE(2) |
+				 PACKET3_RELEASE_MEM__TEMPORAL(3) |
+				 PACKET3_RELEASE_MEM__EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
+				 PACKET3_RELEASE_MEM__EVENT_INDEX(5)));
+	amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM__DATA_SEL(write64bit ? 2 : 1) |
+				 PACKET3_RELEASE_MEM__INT_SEL(int_sel ? 2 : 0)));
 
 	/*
 	 * the address should be Qword aligned if 64bit write, Dword
@@ -3460,7 +3505,7 @@ static void gfx_v12_1_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
 
 	/* write fence seq to the "addr" */
 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
-	amdgpu_ring_write(ring, (WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
+	amdgpu_ring_write(ring, (PACKET3_WRITE_DATA__DST_SEL(5) | PACKET3_WRITE_DATA__WR_CONFIRM(1)));
 	amdgpu_ring_write(ring, lower_32_bits(addr));
 	amdgpu_ring_write(ring, upper_32_bits(addr));
 	amdgpu_ring_write(ring, lower_32_bits(seq));
@@ -3468,7 +3513,7 @@ static void gfx_v12_1_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
 	if (flags & AMDGPU_FENCE_FLAG_INT) {
 		/* set register to trigger INT */
 		amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
-		amdgpu_ring_write(ring, (WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
+		amdgpu_ring_write(ring, (PACKET3_WRITE_DATA__DST_SEL(0) | PACKET3_WRITE_DATA__WR_CONFIRM(1)));
 		amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, GET_INST(GC, 0), regCPC_INT_STATUS));
 		amdgpu_ring_write(ring, 0);
 		amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
@@ -3507,7 +3552,7 @@ static void gfx_v12_1_ring_emit_wreg(struct amdgpu_ring *ring,
 		cmd = (1 << 16); /* no inc addr */
 		break;
 	default:
-		cmd = WR_CONFIRM;
+		cmd = PACKET3_WRITE_DATA__WR_CONFIRM(1);
 		break;
 	}
 	amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
@@ -3819,12 +3864,12 @@ static int gfx_v12_1_rlc_poison_irq(struct amdgpu_device *adev,
 static void gfx_v12_1_emit_mem_sync(struct amdgpu_ring *ring)
 {
 	const unsigned int gcr_cntl =
-			PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) |
-			PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) |
-			PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) |
-			PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) |
-			PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1) |
-			PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_SCOPE(2);
+			PACKET3_ACQUIRE_MEM__GCR_CNTL__GL2_INV(1) |
+			PACKET3_ACQUIRE_MEM__GCR_CNTL__GL2_WB(1) |
+			PACKET3_ACQUIRE_MEM__GCR_CNTL__GLV_INV(1) |
+			PACKET3_ACQUIRE_MEM__GCR_CNTL__GLK_INV(1) |
+			PACKET3_ACQUIRE_MEM__GCR_CNTL__GLI_INV(1) |
+			PACKET3_ACQUIRE_MEM__GCR_CNTL__GL2_SCOPE(2);
 
 	/* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */
 	amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6));
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1_pkt.h b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1_pkt.h
index 21a07530c64d..77b4f6ea532f 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v12_1_pkt.h
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v12_1_pkt.h
@@ -58,11 +58,36 @@
 #define	PACKET3_DISPATCH_DIRECT				0x15
 #define	PACKET3_DISPATCH_INDIRECT			0x16
 #define	PACKET3_ATOMIC_MEM				0x1E
+#define 	PACKET3_ATOMIC_MEM__ATOMIC(x) ((((unsigned)(x)) & 0x7F) << 0)
+#define 	PACKET3_ATOMIC_MEM__COMMAND(x) ((((unsigned)(x)) & 0xF) << 8)
+#define 	PACKET3_ATOMIC_MEM__SCOPE(x) ((((unsigned)(x)) & 0x3) << 23)
+#define 	PACKET3_ATOMIC_MEM__TEMPORAL(x) ((((unsigned)(x)) & 0x3) << 25)
+#define 	PACKET3_ATOMIC_MEM__ADDR_LO(x) (((unsigned)(x)))
+#define 	PACKET3_ATOMIC_MEM__ADDR_HI(x) (((unsigned)(x)))
+#define 	PACKET3_ATOMIC_MEM__SRC_DATA_LO(x) (((unsigned)(x)))
+#define 	PACKET3_ATOMIC_MEM__SRC_DATA_HI(x) (((unsigned)(x)))
+#define 	PACKET3_ATOMIC_MEM__CMP_DATA_LO(x) (((unsigned)(x)))
+#define 	PACKET3_ATOMIC_MEM__CMP_DATA_HI(x) (((unsigned)(x)))
+#define 	PACKET3_ATOMIC_MEM__LOOP_INTERVAL(x) ((((unsigned)(x)) & 0x1FFF) << 0)
+#define 	PACKET3_ATOMIC_MEM__COMMAND__SINGLE_PASS_ATOMIC 0
+#define 	PACKET3_ATOMIC_MEM__COMMAND__LOOP_UNTIL_COMPARE_SATISFIED 1
+#define 	PACKET3_ATOMIC_MEM__COMMAND__WAIT_FOR_WRITE_CONFIRMATION 2
+#define 	PACKET3_ATOMIC_MEM__COMMAND__SEND_AND_CONTINUE 3
+#define 	PACKET3_ATOMIC_MEM__SCOPE__CU 0
+#define 	PACKET3_ATOMIC_MEM__SCOPE__SE 1
+#define 	PACKET3_ATOMIC_MEM__SCOPE__DEVICE 2
+#define 	PACKET3_ATOMIC_MEM__SCOPE__SYSTEM 3
+#define 	PACKET3_ATOMIC_MEM__TEMPORAL__RT 0
+#define 	PACKET3_ATOMIC_MEM__TEMPORAL__NT 1
+#define 	PACKET3_ATOMIC_MEM__TEMPORAL__FW 2
+#define 	PACKET3_ATOMIC_MEM__TEMPORAL__UC 3
 #define	PACKET3_OCCLUSION_QUERY				0x1F
 #define	PACKET3_SET_PREDICATION				0x20
 #define	PACKET3_REG_RMW					0x21
 #define	PACKET3_COND_EXEC				0x22
 #define	PACKET3_PRED_EXEC				0x23
+#define 	PACKET3_PRED_EXEC__EXEC_COUNT(x) ((((unsigned)(x)) & 0x3FFF) << 0)
+#define 	PACKET3_PRED_EXEC__VIRTUALXCCID_SELECT(x) ((((unsigned)(x)) & 0xFF) << 24)
 #define	PACKET3_DRAW_INDIRECT				0x24
 #define	PACKET3_DRAW_INDEX_INDIRECT			0x25
 #define	PACKET3_INDEX_BASE				0x26
@@ -74,7 +99,11 @@
 #define	PACKET3_DRAW_INDEX_MULTI_AUTO			0x30
 #define	PACKET3_DRAW_INDEX_OFFSET_2			0x35
 #define	PACKET3_WRITE_DATA				0x37
-#define		WRITE_DATA_DST_SEL(x)                   (((x) & 0xf) << 8)
+#define 	PACKET3_WRITE_DATA__DST_SEL(x) ((((unsigned)(x)) & 0xF) << 8)
+#define 	PACKET3_WRITE_DATA__DST_SEL__MEM_MAPPED_REGISTER 0
+#define 	PACKET3_WRITE_DATA__DST_SEL__TC_L2 2
+#define 	PACKET3_WRITE_DATA__DST_SEL__MEMORY 5
+#define 	PACKET3_WRITE_DATA__DST_SEL__MEMORY_MAPPED_ADC_PERSISTENT_STATE 6
 		/* 0 - register
 		 * 1 - reserved
 		 * 2 - tc_l2
@@ -83,27 +112,52 @@
 		 * 5 - memory (same as tc_l2)
          * 6 - memory_mapped_adc_persistent_state
 		 */
-#define		WRITE_DATA_SCOPE(x)                     (((x) & 0x3) << 12)
-#define		WRITE_DATA_MODE(x)                      (((x) & 0x3) << 14)
+#define 	PACKET3_WRITE_DATA__SCOPE(x)   ((((unsigned)(x)) & 0x3) << 12)
+#define 	PACKET3_WRITE_DATA__SCOPE__CU 0
+#define 	PACKET3_WRITE_DATA__SCOPE__SE 1
+#define 	PACKET3_WRITE_DATA__SCOPE__DEVICE 2
+#define 	PACKET3_WRITE_DATA__SCOPE__SYSTEM 3
+#define 	PACKET3_WRITE_DATA__MODE(x)    ((((unsigned)(x)) & 0x3) << 14)
+#define 	PACKET3_WRITE_DATA__MODE__LOCAL_XCD 0
+#define 	PACKET3_WRITE_DATA__MODE__REMOTE_OR_LOCAL_AID 1
+#define 	PACKET3_WRITE_DATA__MODE__REMOTE_XCD 2
+#define 	PACKET3_WRITE_DATA__MODE__REMOTE_MID 3
         /* 0 - local xcd
          * 1 - remote/local aid
          * 2 - remote xcd
          * 3 - remote mid
          */
-#define		WRITE_DATA_ADDR_INCR                    (1 << 16)
-#define		WRITE_DATA_MID_DIE_ID(x)                (((x) & 0x3) << 18)
-#define		WR_CONFIRM                              (1 << 20)
-#define		WRITE_DATA_XCD_DIE_ID(x)                (((x) & 0xf) << 21)
-#define		WRITE_DATA_TEMPORAL(x)                  (((x) & 0x3) << 25)
-		/* 0 - rt
-		 * 1 - nt
-         * 2 - ht
-         * 3 - lu
-		 */
-#define		WRITE_DATA_COOP_DISABLE                 (1 << 27)
+#define 	PACKET3_WRITE_DATA__ADDR_INCR(x)  ((((unsigned)(x)) & 0x1) << 16)
+#define 	PACKET3_WRITE_DATA__ADDR_INCR__INCREMENT_ADDRESS 0
+#define 	PACKET3_WRITE_DATA__ADDR_INCR__DO_NOT_INCREMENT_ADDRESS 1
+#define 	PACKET3_WRITE_DATA__MID_DIE_ID(x)       ((((unsigned)(x)) & 0x3) << 18)
+#define 	PACKET3_WRITE_DATA__WR_CONFIRM(x) ((((unsigned)(x)) & 0x1) << 20)
+#define 	PACKET3_WRITE_DATA__WR_CONFIRM__DO_NOT_WAIT_FOR_WRITE_CONFIRMATION 0
+#define 	PACKET3_WRITE_DATA__WR_CONFIRM__WAIT_FOR_WRITE_CONFIRMATION 1
+#define 	PACKET3_WRITE_DATA__XCD_DIE_ID(x) ((((unsigned)(x)) & 0xF) << 21)
+#define 	PACKET3_WRITE_DATA__TEMPORAL(x) ((((unsigned)(x)) & 0x3) << 25)
+#define 	PACKET3_WRITE_DATA__TEMPORAL__RT 0
+#define 	PACKET3_WRITE_DATA__TEMPORAL__NT 1
+#define 	PACKET3_WRITE_DATA__TEMPORAL__HT 2
+#define 	PACKET3_WRITE_DATA__TEMPORAL__LU 3
+#define 	PACKET3_WRITE_DATA__COOP_DISABLE(x)  ((((unsigned)(x)) & 0x1) << 27)
+#define 	PACKET3_WRITE_DATA__COOP_DISABLE__MASTER_AND_SLAVE_COOP 0
+#define 	PACKET3_WRITE_DATA__COOP_DISABLE__MASTER_ONLY 1
+#define 	PACKET3_WRITE_DATA__DST_MMREG_ADDR_LO(x) ((unsigned)(x))
+#define 	PACKET3_WRITE_DATA__DST_MEM_ADDR_LO(x) ((((unsigned)(x)) & 0x3FFFFFFF) << 2)
+#define 	PACKET3_WRITE_DATA__DST_MMREG_ADDR_HI(x) ((((unsigned)(x)) & 0x3FFF) << 0)
+#define 	PACKET3_WRITE_DATA__DST_MEM_ADDR_HI(x) ((unsigned)(x))
+#define 	PACKET3_WRITE_DATA__DATA(x) ((unsigned)(x))
 #define	PACKET3_DRAW_INDEX_INDIRECT_MULTI		0x38
 #define	PACKET3_WAIT_REG_MEM				0x3C
-#define		WAIT_REG_MEM_FUNCTION(x)                (((x) & 0x7) << 0)
+#define		PACKET3_WAIT_REG_MEM__FUNCTION(x) ((((unsigned)(x)) & 0x7) << 0)
+#define		PACKET3_WAIT_REG_MEM__FUNCTION__ALWAYS_PASS 0
+#define		PACKET3_WAIT_REG_MEM__FUNCTION__LESS_THAN_REF_VALUE 1
+#define		PACKET3_WAIT_REG_MEM__FUNCTION__LESS_THAN_EQUAL_TO_THE_REF_VALUE 2
+#define		PACKET3_WAIT_REG_MEM__FUNCTION__EQUAL_TO_THE_REFERENCE_VALUE 3
+#define		PACKET3_WAIT_REG_MEM__FUNCTION__NOT_EQUAL_REFERENCE_VALUE 4
+#define		PACKET3_WAIT_REG_MEM__FUNCTION__GREATER_THAN_OR_EQUAL_REFERENCE_VALUE 5
+#define		PACKET3_WAIT_REG_MEM__FUNCTION__GREATER_THAN_REFERENCE_VALUE 6
 		/* 0 - always
 		 * 1 - <
 		 * 2 - <=
@@ -112,117 +166,222 @@
 		 * 5 - >=
 		 * 6 - >
 		 */
-#define		WAIT_REG_MEM_MEM_SPACE(x)               (((x) & 0x3) << 4)
+#define 	PACKET3_WAIT_REG_MEM__MEM_SPACE(x) ((((unsigned)(x)) & 0x3) << 4)
+#define 	PACKET3_WAIT_REG_MEM__MEM_SPACE__REGISTER_SPACE 0
+#define 	PACKET3_WAIT_REG_MEM__MEM_SPACE__MEMORY_SPACE 1
 		/* 0 - reg
 		 * 1 - mem
 		 */
-#define		WAIT_REG_MEM_OPERATION(x)               (((x) & 0x3) << 6)
+#define		PACKET3_WAIT_REG_MEM__OPERATION(x) ((((unsigned)(x)) & 0x3) << 6)
+#define 	PACKET3_WAIT_REG_MEM__OPERATION__WAIT_REG_MEM 0
+#define 	PACKET3_WAIT_REG_MEM__OPERATION__WR_WAIT_WR_REG 1
+#define 	PACKET3_WAIT_REG_MEM__OPERATION__WAIT_MEM_PREEMPTABLE 3
 		/* 0 - wait_reg_mem
 		 * 1 - wr_wait_wr_reg
+		 * 2 - reserved
+		 * 3 - wait_mem_preemptable
 		 */
-#define		WAIT_REG_MEM_MODE(x)                    (((x) & 0x3) << 10)
+#define		PACKET3_WAIT_REG_MEM__MODE(x)   ((((unsigned)(x)) & 0x3) << 10)
+#define		PACKET3_WAIT_REG_MEM__MODE__LOCAL_XCD   0
+#define		PACKET3_WAIT_REG_MEM__MODE__REMOTE_OR_LOCAL_AID   1
+#define		PACKET3_WAIT_REG_MEM__MODE__REMOTE_XCD   2
+#define		PACKET3_WAIT_REG_MEM__MODE__REMOTE_MID   3
         /* 0 - local xcd
          * 1 - remote/local aid
          * 2 - remote xcd
          * 3 - remote mid
          */
-#define		WAIT_REG_MEM_MID_DIE_ID(x)              (((x) & 0x3) << 12)
-#define		WAIT_REG_MEM_XCD_DIE_ID(x)              (((x) & 0xf) << 14)
-#define		WAIT_REG_MEM_MES_INTR_PIPE(x)           (((x) & 0x3) << 22)
-#define		WAIT_REG_MEM_MES_ACTION(x)              (((x) & 0x1) << 24)
-#define		WAIT_REG_MEM_TEMPORAL(x)                (((x) & 0x3) << 25)
+#define		PACKET3_WAIT_REG_MEM__MID_DIE_ID(x) ((((unsigned)(x)) & 0x3) << 12)
+#define		PACKET3_WAIT_REG_MEM__XCD_DIE_ID(x) ((((unsigned)(x)) & 0xf) << 14)
+#define		PACKET3_WAIT_REG_MEM__MES_INTR_PIPE(x) ((((unsigned)(x)) & 0x3) << 22)
+#define		PACKET3_WAIT_REG_MEM__MES_ACTION(x) ((((unsigned)(x)) & 0x1) << 24)
+#define		PACKET3_WAIT_REG_MEM__TEMPORAL(x)       ((((unsigned)(x)) & 0x3) << 25)
+#define 	PACKET3_WAIT_REG_MEM__TEMPORAL__RT 0
+#define 	PACKET3_WAIT_REG_MEM__TEMPORAL__NT 1
+#define 	PACKET3_WAIT_REG_MEM__TEMPORAL__HT 2
+#define 	PACKET3_WAIT_REG_MEM__TEMPORAL__LU 3
 		/* 0 - rt
 		 * 1 - nt
          * 2 - ht
          * 3 - lu
 		 */
+#define		PACKET3_WAIT_REG_MEM__MEM_POLL_ADDR_LO(x) ((((unsigned)(x)) & 0x3FFFFFFF) << 2)
+#define		PACKET3_WAIT_REG_MEM__REG_POLL_ADDR(x) ((unsigned)(x))
+#define		PACKET3_WAIT_REG_MEM__REG_WRITE_ADDR1(x) ((((unsigned)(x)) & 0x3FFFF) << 0)
+#define		PACKET3_WAIT_REG_MEM__MEM_POLL_ADDR_HI(x) ((unsigned)(x))
+#define		PACKET3_WAIT_REG_MEM__REG_POLL_ADDR_HI(x) ((((unsigned)(x)) & 0x3FFF) << 0)
+#define		PACKET3_WAIT_REG_MEM__REG_WRITE_ADDR2(x) ((((unsigned)(x)) & 0x3FFFF) << 0)
+#define		PACKET3_WAIT_REG_MEM__REFERENCE(x) ((unsigned)(x))
+#define		PACKET3_WAIT_REG_MEM__MASK(x) ((unsigned)(x))
+#define		PACKET3_WAIT_REG_MEM__POLL_INTERVAL(x) ((((unsigned)(x)) & 0xFFFF) << 0)
+#define		PACKET3_WAIT_REG_MEM__OPTIMIZE_ACE_OFFLOAD_MODE(x) ((((unsigned)(x)) & 0x1) << 31)
 #define	PACKET3_INDIRECT_BUFFER				0x3F
-#define		INDIRECT_BUFFER_VALID                   (1 << 23)
-#define		INDIRECT_BUFFER_TEMPORAL(x)             (x) << 28)
-		/* 0 - rt
-		 * 1 - nt
-		 * 2 - ht
-         * 3 - lu
-		 */
+#define 	PACKET3_INDIRECT_BUFFER__IB_BASE_LO(x) ((((unsigned)(x)) & 0x3FFFFFFF) << 2)
+#define 	PACKET3_INDIRECT_BUFFER__IB_BASE_HI(x) ((unsigned)(x))
+#define 	PACKET3_INDIRECT_BUFFER__IB_SIZE(x) ((((unsigned)(x)) & 0xFFFFF) << 0)
+#define 	PACKET3_INDIRECT_BUFFER__CHAIN(x) ((((unsigned)(x)) & 0x1) << 20)
+#define 	PACKET3_INDIRECT_BUFFER__OFFLOAD_POLLING(x) ((((unsigned)(x)) & 0x1) << 21)
+#define 	PACKET3_INDIRECT_BUFFER__VALID(x) ((((unsigned)(x)) & 0x1) << 23)
+#define 	PACKET3_INDIRECT_BUFFER__VMID(x) ((((unsigned)(x)) & 0xF) << 24)
+#define 	PACKET3_INDIRECT_BUFFER__TEMPORAL(x) ((((unsigned)(x)) & 0x3) << 28)
+#define 	PACKET3_INDIRECT_BUFFER__INHERIT_VMID(x) ((((unsigned)(x)) & 0x1) << 30)
+#define 	PACKET3_INDIRECT_BUFFER__PRIV(x) ((((unsigned)(x)) & 0x1) << 31)
+#define 	PACKET3_INDIRECT_BUFFER__TEMPORAL__RT 0
+#define 	PACKET3_INDIRECT_BUFFER__TEMPORAL__NT 1
+#define 	PACKET3_INDIRECT_BUFFER__TEMPORAL__HT 2
+#define 	PACKET3_INDIRECT_BUFFER__TEMPORAL__LU 3
 #define	PACKET3_COND_INDIRECT_BUFFER			0x3F
 #define	PACKET3_COPY_DATA				0x40
-#define		COPY_DATA_SRC_SEL(x)                    (((x) & 0xf) << 0)
-#define		COPY_DATA_DST_SEL(x)                    (((x) & 0xf) << 8)
-#define		COPY_DATA_SRC_SCOPE(x)                  (((x) & 0x3) << 4)
-#define		COPY_DATA_DST_SCOPE(x)                  (((x) & 0x3) << 27)
-#define		COPY_DATA_MODE(x)                       (((x) & 0x3) << 6)
-        /* 0 - local xcd
-         * 1 - remote/local aid
-         * 2 - remote xcd
-         * 3 - remote mid
-         */
-#define		COPY_DATA_SRC_TEMPORAL(x)               (((x) & 0x3) << 13)
-#define		COPY_DATA_DST_TEMPORAL(x)               (((x) & 0x3) << 25)
-		/* 0 - rt
-		 * 1 - nt
-         * 2 - ht
-         * 3 - lu
-		 */
-#define		COPY_DATA_COUNT_SEL                     (1 << 16)
-#define		COPY_DATA_SRC_DST_REMOTE_MODE(x)        (((x)) & 0x1 << 16)
-        /* 0 - src remote
-         * 1 - dst remote
-         */
-#define		COPY_DATA_MID_DIE_ID(x)                 (((x) & 0x3) << 18)
-#define		COPY_DATA_XCD_DIE_ID(x)                 (((x) & 0xf) << 21)
-#define		COPY_DATA_PQ_EXE_STATUS                 (1 << 27)
+#define 	PACKET3_COPY_DATA__SRC_SEL(x) ((((unsigned)(x)) & 0xF) << 0)
+#define		PACKET3_COPY_DATA__SRC_SCOPE(x) ((((unsigned)(x)) & 0x3) << 4)
+#define 	PACKET3_COPY_DATA__MODE(x) ((((unsigned)(x)) & 0x3) << 6)
+#define 	PACKET3_COPY_DATA__DST_SEL(x) ((((unsigned)(x)) & 0xF) << 8)
+#define 	PACKET3_COPY_DATA__SRC_TEMPORAL(x) ((((unsigned)(x)) & 0x3) << 13)
+#define 	PACKET3_COPY_DATA__COUNT_SEL(x) ((((unsigned)(x)) & 0x1) << 16)
+#define 	PACKET3_COPY_DATA__SRC_DST_REMOTE_MODE(x) ((((unsigned)(x)) & 0x1) << 17)
+#define 	PACKET3_COPY_DATA__MID_DIE_ID(x) ((((unsigned)(x)) & 0x3) << 18)
+#define 	PACKET3_COPY_DATA__WR_CONFIRM(x) ((((unsigned)(x)) & 0x1) << 20)
+#define 	PACKET3_COPY_DATA__XCD_DIE_ID(x) ((((unsigned)(x)) & 0xF) << 21)
+#define 	PACKET3_COPY_DATA__DST_TEMPORAL(x) ((((unsigned)(x)) & 0x3) << 25)
+#define		PACKET3_COPY_DATA__DST_SCOPE(x) ((((unsigned)(x)) & 0x3) << 27)
+#define 	PACKET3_COPY_DATA__PQ_EXE_STATUS(x) ((((unsigned)(x)) & 0x1) << 29)
+#define 	PACKET3_COPY_DATA__SRC_REG_OFFSET_LO(x) ((unsigned)(x))
+#define 	PACKET3_COPY_DATA__SRC_32B_ADDR_LO(x) ((((unsigned)(x)) & 0x3FFFFFFF) << 2)
+#define 	PACKET3_COPY_DATA__SRC_64B_ADDR_LO(x) ((((unsigned)(x)) & 0x1FFFFFFF) << 3)
+#define 	PACKET3_COPY_DATA__IMM_DATA(x) ((unsigned)(x))
+#define 	PACKET3_COPY_DATA__SRC_REG_OFFSET_HI(x) ((((unsigned)(x)) & 0x3FFF) << 0)
+#define 	PACKET3_COPY_DATA__SRC_MEMTC_ADDR_HI(x) ((unsigned)(x))
+#define 	PACKET3_COPY_DATA__SRC_IMM_DATA(x) ((unsigned)(x))
+#define 	PACKET3_COPY_DATA__DST_REG_OFFSET_LO(x) ((unsigned)(x))
+#define 	PACKET3_COPY_DATA__DST_32B_ADDR_LO(x) ((((unsigned)(x)) & 0x3FFFFFFF) << 2)
+#define 	PACKET3_COPY_DATA__DST_64B_ADDR_LO(x) ((((unsigned)(x)) & 0x1FFFFFFF) << 3)
+#define 	PACKET3_COPY_DATA__DST_REG_OFFSET_HI(x) ((((unsigned)(x)) & 0x3FFF) << 0)
+#define 	PACKET3_COPY_DATA__DST_ADDR_HI(x) ((unsigned)(x))
+#define 	PACKET3_COPY_DATA__SRC_SEL__MEM_MAPPED_REGISTER 0
+#define 	PACKET3_COPY_DATA__SRC_SEL__TC_L2_OBSOLETE 1
+#define 	PACKET3_COPY_DATA__SRC_SEL__TC_L2 2
+#define 	PACKET3_COPY_DATA__SRC_SEL__PERFCOUNTERS 4
+#define 	PACKET3_COPY_DATA__SRC_SEL__IMMEDIATE_DATA 5
+#define 	PACKET3_COPY_DATA__SRC_SEL__ATOMIC_RETURN_DATA 6
+#define 	PACKET3_COPY_DATA__SRC_SEL__GPU_CLOCK_COUNT 9
+#define 	PACKET3_COPY_DATA__SRC_SEL__SYSTEM_CLOCK_COUNT 10
+#define 	PACKET3_COPY_DATA__SRC_SCOPE__CU 0
+#define 	PACKET3_COPY_DATA__SRC_SCOPE__SE 1
+#define 	PACKET3_COPY_DATA__SRC_SCOPE__DEVICE 2
+#define 	PACKET3_COPY_DATA__SRC_SCOPE__SYSTEM 3
+#define 	PACKET3_COPY_DATA__MODE__LOCAL_XCD 0
+#define 	PACKET3_COPY_DATA__MODE__REMOTE_OR_LOCAL_AID 1
+#define 	PACKET3_COPY_DATA__MODE__REMOTE_XCD 2
+#define 	PACKET3_COPY_DATA__MODE__REMOTE_MID 3
+#define 	PACKET3_COPY_DATA__DST_SEL__MEM_MAPPED_REGISTER 0
+#define 	PACKET3_COPY_DATA__DST_SEL__TC_L2 2
+#define 	PACKET3_COPY_DATA__DST_SEL__PERFCOUNTERS 4
+#define 	PACKET3_COPY_DATA__DST_SEL__TC_L2_OBSOLETE 5
+#define 	PACKET3_COPY_DATA__DST_SEL__MEM_MAPPED_REG_DC 6
+#define 	PACKET3_COPY_DATA__SRC_TEMPORAL__RT 0
+#define 	PACKET3_COPY_DATA__SRC_TEMPORAL__NT 1
+#define 	PACKET3_COPY_DATA__SRC_TEMPORAL__HT 2
+#define 	PACKET3_COPY_DATA__SRC_TEMPORAL__LU 3
+#define 	PACKET3_COPY_DATA__COUNT_SEL__32_BITS_OF_DATA 0
+#define 	PACKET3_COPY_DATA__COUNT_SEL__64_BITS_OF_DATA 1
+#define 	PACKET3_COPY_DATA__SRC_DST_REMOTE_MODE__SRC_IS_REMOTE 0
+#define 	PACKET3_COPY_DATA__SRC_DST_REMOTE_MODE__DST_IS_REMOTE 1
+#define 	PACKET3_COPY_DATA__WR_CONFIRM__DO_NOT_WAIT_FOR_CONFIRMATION 0
+#define 	PACKET3_COPY_DATA__WR_CONFIRM__WAIT_FOR_CONFIRMATION 1
+#define 	PACKET3_COPY_DATA__DST_TEMPORAL__RT 0
+#define 	PACKET3_COPY_DATA__DST_TEMPORAL__NT 1
+#define 	PACKET3_COPY_DATA__DST_TEMPORAL__HT 2
+#define 	PACKET3_COPY_DATA__DST_TEMPORAL__LU 3
+#define 	PACKET3_COPY_DATA__DST_SCOPE__CU 0
+#define 	PACKET3_COPY_DATA__DST_SCOPE__SE 1
+#define 	PACKET3_COPY_DATA__DST_SCOPE__DEVICE 2
+#define 	PACKET3_COPY_DATA__DST_SCOPE__SYSTEM 3
+#define 	PACKET3_COPY_DATA__PQ_EXE_STATUS__DEFAULT 0
+#define 	PACKET3_COPY_DATA__PQ_EXE_STATUS__PHASE_UPDATE 1
 #define	PACKET3_PFP_SYNC_ME				0x42
 #define	PACKET3_COND_WRITE				0x45
 #define	PACKET3_EVENT_WRITE				0x46
-#define		EVENT_TYPE(x)                           ((x) << 0)
-#define		EVENT_INDEX(x)                          ((x) << 8)
-		/* 0 - any non-TS event
-		 * 1 - ZPASS_DONE, PIXEL_PIPE_STAT_*
-		 * 2 - SAMPLE_PIPELINESTAT
-		 * 3 - SAMPLE_STREAMOUTSTAT*
-		 * 4 - *S_PARTIAL_FLUSH
-		 */
+#define		PACKET3_EVENT_WRITE__EVENT_TYPE(x) ((((unsigned)(x)) & 0x3F) << 0)
+#define		PACKET3_EVENT_WRITE__EVENT_INDEX(x) ((((unsigned)(x)) & 0xF) << 8)
+#define		PACKET3_EVENT_WRITE__OFFLOAD_ENABLE(x) ((((unsigned)(x)) & 0x1) << 31)
+#define 	PACKET3_EVENT_WRITE__ADDRESS_LO(x) ((((unsigned)(x)) & 0x1FFFFFFF) << 3)
+#define 	PACKET3_EVENT_WRITE__ADDRESS_HI(x) ((unsigned)(x))
+#define 	PACKET3_EVENT_WRITE__EVENT_INDEX__OTHER 0
+#define 	PACKET3_EVENT_WRITE__EVENT_INDEX__SAMPLE_PIPELINESTAT 2
+#define 	PACKET3_EVENT_WRITE__EVENT_INDEX__CS_PARTIAL_FLUSH 4
+#define	PACKET3_EVENT_WRITE_EOP				0x47
+#define	PACKET3_EVENT_WRITE_EOS				0x48
 #define	PACKET3_RELEASE_MEM				0x49
-#define		PACKET3_RELEASE_MEM_EVENT_TYPE(x)	    ((x) << 0)
-#define		PACKET3_RELEASE_MEM_EVENT_INDEX(x)	    ((x) << 8)
-#define		PACKET3_RELEASE_MEM_GCR_GL2_SCOPE(x)	((x) << 12)
-#define		PACKET3_RELEASE_MEM_GCR_GLV_INV		    (1 << 14)
-#define		PACKET3_RELEASE_MEM_GCR_GL2_US		    (1 << 16)
-#define		PACKET3_RELEASE_MEM_GCR_GL2_RANGE(x)	((x) << 17)
-#define		PACKET3_RELEASE_MEM_GCR_GL2_DISCARD	    (1 << 19)
-#define		PACKET3_RELEASE_MEM_GCR_GL2_INV		    (1 << 20)
-#define		PACKET3_RELEASE_MEM_GCR_GL2_WB		    (1 << 21)
-#define		PACKET3_RELEASE_MEM_GCR_SEQ(x)		    ((x) << 22)
-#define		PACKET3_RELEASE_MEM_GCR_GLV_WB		    (1 << 24)
-#define		PACKET3_RELEASE_MEM_TEMPORAL(x)	        ((x) << 25)
+#define		PACKET3_RELEASE_MEM__EVENT_TYPE(x)  ((((unsigned)(x)) & 0x3F) << 0)
+#define		PACKET3_RELEASE_MEM__WAIT_SYNC(x)  ((((unsigned)(x)) & 0x1) << 7)
+#define		PACKET3_RELEASE_MEM__EVENT_INDEX(x)  ((((unsigned)(x)) & 0xF) << 8)
+#define		PACKET3_RELEASE_MEM__EVENT_INDEX__END_OF_PIPE   5
+#define		PACKET3_RELEASE_MEM__EVENT_INDEX__SHADER_DONE   6
+#define		PACKET3_RELEASE_MEM__GCR_CNTL(x)  ((((unsigned)(x)) & 0x1FFF) << 12)
+#define		PACKET3_RELEASE_MEM__GCR_GL2_SCOPE(x)	((x) << 12)
+#define		PACKET3_RELEASE_MEM__GCR_GLV_INV		    (1 << 14)
+#define		PACKET3_RELEASE_MEM__GCR_GL2_US		    (1 << 16)
+#define		PACKET3_RELEASE_MEM__GCR_GL2_RANGE(x)	((x) << 17)
+#define		PACKET3_RELEASE_MEM__GCR_GL2_DISCARD	    (1 << 19)
+#define		PACKET3_RELEASE_MEM__GCR_GL2_INV		    (1 << 20)
+#define		PACKET3_RELEASE_MEM__GCR_GL2_WB		    (1 << 21)
+#define		PACKET3_RELEASE_MEM__GCR_SEQ(x)		    ((x) << 22)
+#define		PACKET3_RELEASE_MEM__GCR_GLV_WB		    (1 << 24)
+#define		PACKET3_RELEASE_MEM__TEMPORAL(x)    ((((unsigned)(x)) & 0x3) << 25)
+#define		PACKET3_RELEASE_MEM__TEMPORAL__RT   0
+#define		PACKET3_RELEASE_MEM__TEMPORAL__NT   1
+#define		PACKET3_RELEASE_MEM__TEMPORAL__HT   2
+#define		PACKET3_RELEASE_MEM__TEMPORAL__LU   3
 		/* 0 - temporal__release_mem__rt
 		 * 1 - temporal__release_mem__nt
 		 * 2 - temporal__release_mem__ht
 		 * 3 - temporal__release_mem__lu
 		 */
-#define		PACKET3_RELEASE_MEM_PQ_EXE_STATUS		(1 << 28)
-#define		PACKET3_RELEASE_MEM_GCR_GLK_INV		    (1 << 30)
+#define		PACKET3_RELEASE_MEM__PQ_EXE_STATUS(x)    ((((unsigned)(x)) & 0x1) << 28)
+#define		PACKET3_RELEASE_MEM__PQ_EXE_STATUS__DEFAULT 0
+#define		PACKET3_RELEASE_MEM__PQ_EXE_STATUS__PHASE_UPDATE 1
+#define		PACKET3_RELEASE_MEM__GCR_GLK_INV		    (1 << 30)
 
-#define		PACKET3_RELEASE_MEM_DST_SEL(x)		((x) << 16)
-		/* 0 - memory controller
-		 * 1 - TC/L2
-         * 2 - register
-		 */
-#define		PACKET3_RELEASE_MEM_MES_INTR_PIPE(x)    ((x) << 20)
-#define		PACKET3_RELEASE_MEM_MES_ACTION_ID(x)    ((x) << 22)
-#define		PACKET3_RELEASE_MEM_INT_SEL(x)		((x) << 24)
-		/* 0 - none
-		 * 1 - interrupt only (DATA_SEL = 0)
-		 * 2 - interrupt when data write is confirmed
-		 */
-#define		PACKET3_RELEASE_MEM_ADD_DOOREBLL_OFFSET(x)		(1 << 28)
-#define		PACKET3_RELEASE_MEM_DATA_SEL(x)		((x) << 29)
+#define		PACKET3_RELEASE_MEM__DST_SEL(x) ((((unsigned)(x)) & 0x3) << 16)
+#define		PACKET3_RELEASE_MEM__DST_SEL__MEMORY_CONTROLLER 0
+#define		PACKET3_RELEASE_MEM__DST_SEL__TC_L2 1
+#define		PACKET3_RELEASE_MEM__DST_SEL__QUQUE_WRITE_POINTER_REGISTER 2
+#define		PACKET3_RELEASE_MEM__DST_SEL__QUQUE_WRITE_POINTER_POLL_MASK_BIT 3
+#define		PACKET3_RELEASE_MEM__MES_INTR_PIPE(x)    ((((unsigned)(x)) & 0x3) << 20)
+#define		PACKET3_RELEASE_MEM__MES_ACTION_ID(x)    ((((unsigned)(x)) & 0x3) << 22)
+#define		PACKET3_RELEASE_MEM__MES_ACTION_ID__NO_MES_NOTIFICATION  0
+#define		PACKET3_RELEASE_MEM__MES_ACTION_ID__INTERRUPT_AND_FENCE  1
+#define		PACKET3_RELEASE_MEM__MES_ACTION_ID__INTERRUPT_NO_FENCE_THEN_ADDRESS_PAYLOAD  2
+#define		PACKET3_RELEASE_MEM__MES_ACTION_ID__INTERRUPT_AND_ADDRESS_PAYLOAD  3
+#define		PACKET3_RELEASE_MEM__INT_SEL(x)  ((((unsigned)(x)) & 0x7) << 24)
+#define		PACKET3_RELEASE_MEM__INT_SEL__NONE   0
+#define		PACKET3_RELEASE_MEM__INT_SEL__SEND_INTERRUPT_ONLY   1
+#define		PACKET3_RELEASE_MEM__INT_SEL__SEND_INTERRUPT_AFTER_WRITE_CONFIRM   2
+#define		PACKET3_RELEASE_MEM__INT_SEL__SEND_DATA_AND_WRITE_CONFIRM   3
+#define		PACKET3_RELEASE_MEM__INT_SEL__UNCONDITIONALLY_SEND_INT_CTXID   4
+#define		PACKET3_RELEASE_MEM__INT_SEL__UNCONDITIONALLY_SEND_INT_CTXID_BASED_ON_32_BIT_COMPARE   5
+#define		PACKET3_RELEASE_MEM__INT_SEL__UNCONDITIONALLY_SEND_INT_CTXID_BASED_ON_64_BIT_COMPARE   6
+#define		PACKET3_RELEASE_MEM__ADD_DOOREBLL_OFFSET(x)  ((((unsigned)(x)) & 0x1) << 28)
+#define		PACKET3_RELEASE_MEM__DATA_SEL(x)     ((((unsigned)(x)) & 0x7) << 29)
+#define		PACKET3_RELEASE_MEM__DATA_SEL__NONE 0
+#define		PACKET3_RELEASE_MEM__DATA_SEL__SEND_32_BIT_LOW 1
+#define		PACKET3_RELEASE_MEM__DATA_SEL__SEND_64_BIT_DATA 2
+#define		PACKET3_RELEASE_MEM__DATA_SEL__SEND_GPU_CLOCK_COUNTER 3
+#define		PACKET3_RELEASE_MEM__DATA_SEL__SEND_SYSTEM_CLOCK_COUNTER 4
 		/* 0 - discard
 		 * 1 - send low 32bit data
 		 * 2 - send 64bit data
 		 * 3 - send 64bit GPU counter value
 		 * 4 - send 64bit sys counter value
 		 */
+#define		PACKET3_RELEASE_MEM__ADDRESS_LO_32B(x)     ((((unsigned)(x)) & 0x3FFFFFFF) << 2)
+#define		PACKET3_RELEASE_MEM__ADDRESS_LO_64B(x)     ((((unsigned)(x)) & 0x1FFFFFFF) << 3)
+#define		PACKET3_RELEASE_MEM__ADDRESS_HI(x)     ((unsigned)(x))
+#define		PACKET3_RELEASE_MEM__DATA_LO(x)     ((unsigned)(x))
+#define		PACKET3_RELEASE_MEM__CMP_DATA_LO(x)     ((unsigned)(x))
+#define		PACKET3_RELEASE_MEM__DATA_HI(x)     ((unsigned)(x))
+#define		PACKET3_RELEASE_MEM__CMP_DATA_HI(x)     ((unsigned)(x))
+#define		PACKET3_RELEASE_MEM__INT_CTXID(x)     ((unsigned)(x))
 
 #define	PACKET3_PREAMBLE_CNTL				0x4A
 #              define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE     (2 << 28)
@@ -279,58 +438,78 @@
 #              define PACKET3_DMA_DATA_CMD_DIS_WC   (1 << 30)
 #define	PACKET3_CONTEXT_REG_RMW				0x51
 #define	PACKET3_ACQUIRE_MEM				0x58
-/* 1.  HEADER
- * 2.  COHER_CNTL [30:0]
- * 2.1 ENGINE_SEL [31:31]
- * 2.  COHER_SIZE [31:0]
- * 3.  COHER_SIZE_HI [7:0]
- * 4.  COHER_BASE_LO [31:0]
- * 5.  COHER_BASE_HI [23:0]
- * 7.  POLL_INTERVAL [15:0]
- * 8.  GCR_CNTL [18:0]
- */
-#define 	PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(x) ((x) << 0)
+/* 1.  HEADER */
+#define		PACKET3_ACQUIRE_MEM__COHER_SIZE(x) ((unsigned)(x))
+/* 3.  COHER_SIZE [31:0] */
+#define		PACKET3_ACQUIRE_MEM__COHER_SIZE_HI(x) ((((unsigned)(x)) & 0xFF) << 0)
+/* 4.  COHER_SIZE_HI [7:0] */
+#define		PACKET3_ACQUIRE_MEM__COHER_BASE_LO(x) ((unsigned)(x))
+/* 5.  COHER_BASE_LO [31:0] */
+#define		PACKET3_ACQUIRE_MEM__COHER_BASE_HI(x) ((((unsigned)(x)) & 0xFFFFFF) << 0)
+/* 6.  COHER_BASE_HI [23:0] */
+#define		PACKET3_ACQUIRE_MEM__POLL_INTERVAL(x) ((((unsigned)(x)) & 0xFFFF) << 0)
+/* 7.  POLL_INTERVAL [15:0] */
+#define		PACKET3_ACQUIRE_MEM__GCR_CNTL(x) ((((unsigned)(x)) & 0x7FFFF) << 0)
+/* 8.  GCR_CNTL [18:0] */
+#define 	PACKET3_ACQUIRE_MEM__GCR_CNTL__GLI_INV(x) ((x) << 0)
+#define 	PACKET3_ACQUIRE_MEM__GCR_CNTL__GLI_INV__NOP 0
+#define 	PACKET3_ACQUIRE_MEM__GCR_CNTL__GLI_INV__ALL 1
+#define 	PACKET3_ACQUIRE_MEM__GCR_CNTL__GLI_INV__RANGE 2
+#define 	PACKET3_ACQUIRE_MEM__GCR_CNTL__GLI_INV__FIRST_LAST 3
 		/*
 		 * 0:NOP
 		 * 1:ALL
 		 * 2:RANGE
 		 * 3:FIRST_LAST
 		 */
-#define 	PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_RANGE(x) ((x) << 2)
+#define 	PACKET3_ACQUIRE_MEM__GCR_CNTL__GL1_RANGE(x) ((x) << 2)
+#define 	PACKET3_ACQUIRE_MEM__GCR_CNTL__GL1_RANGE__ALL   0
+#define 	PACKET3_ACQUIRE_MEM__GCR_CNTL__GL1_RANGE__RANGE   2
+#define 	PACKET3_ACQUIRE_MEM__GCR_CNTL__GL1_RANGE__FIRST_LAST   3
 		/*
 		 * 0:ALL
 		 * 1:reserved
 		 * 2:RANGE
 		 * 3:FIRST_LAST
 		 */
-#define 	PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_SCOPE(x) ((x) << 4)
+#define 	PACKET3_ACQUIRE_MEM__GCR_CNTL__GL2_SCOPE(x) ((x) << 4)
+#define 	PACKET3_ACQUIRE_MEM__GCR_CNTL__GL2_SCOPE__DEVICE    0
+#define 	PACKET3_ACQUIRE_MEM__GCR_CNTL__GL2_SCOPE__SYSTEM    1
+#define 	PACKET3_ACQUIRE_MEM__GCR_CNTL__GL2_SCOPE__FORCE_ALL    2
         /*
          * 0:Device scope
          * 1:System scope
          * 2:Force INV/WB all
          * 3:Reserved
          */
-#define 	PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_WB(x) ((x) << 6)
-#define 	PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(x) ((x) << 7)
-#define 	PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(x) ((x) << 8)
-#define 	PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_US(x) ((x) << 10)
-#define 	PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_RANGE(x) ((x) << 11)
+#define 	PACKET3_ACQUIRE_MEM__GCR_CNTL__GLV_WB(x) ((x) << 6)
+#define 	PACKET3_ACQUIRE_MEM__GCR_CNTL__GLK_INV(x) ((x) << 7)
+#define 	PACKET3_ACQUIRE_MEM__GCR_CNTL__GLV_INV(x) ((x) << 8)
+#define 	PACKET3_ACQUIRE_MEM__GCR_CNTL__GL2_US(x) ((x) << 10)
+#define 	PACKET3_ACQUIRE_MEM__GCR_CNTL__GL2_RANGE(x) ((x) << 11)
+#define 	PACKET3_ACQUIRE_MEM__GCR_CNTL__GL2_RANGE__ALL   0
+#define 	PACKET3_ACQUIRE_MEM__GCR_CNTL__GL2_RANGE__VOL   1
+#define 	PACKET3_ACQUIRE_MEM__GCR_CNTL__GL2_RANGE__RANGE   2
+#define 	PACKET3_ACQUIRE_MEM__GCR_CNTL__GL2_RANGE__FIRST_LAST   3
 		/*
 		 * 0:ALL
 		 * 1:VOL
 		 * 2:RANGE
 		 * 3:FIRST_LAST
 		 */
-#define 	PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_DISCARD(x)  ((x) << 13)
-#define 	PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(x) ((x) << 14)
-#define 	PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(x) ((x) << 15)
-#define 	PACKET3_ACQUIRE_MEM_GCR_CNTL_SEQ(x) ((x) << 16)
+#define 	PACKET3_ACQUIRE_MEM__GCR_CNTL__GL2_DISCARD(x)  ((x) << 13)
+#define 	PACKET3_ACQUIRE_MEM__GCR_CNTL__GL2_INV(x) ((x) << 14)
+#define 	PACKET3_ACQUIRE_MEM__GCR_CNTL__GL2_WB(x) ((x) << 15)
+#define 	PACKET3_ACQUIRE_MEM__GCR_CNTL__SEQ(x) ((x) << 16)
+#define 	PACKET3_ACQUIRE_MEM__GCR_CNTL__SEQ__PARALLET    0
+#define 	PACKET3_ACQUIRE_MEM__GCR_CNTL__SEQ__FORWARD    1
+#define 	PACKET3_ACQUIRE_MEM__GCR_CNTL__SEQ__REVERSE    2
 		/*
 		 * 0: PARALLEL
 		 * 1: FORWARD
 		 * 2: REVERSE
 		 */
-#define 	PACKET3_ACQUIRE_MEM_GCR_RANGE_IS_PA  (1 << 18)
+#define 	PACKET3_ACQUIRE_MEM__GCR_CNTL__GCR_RANGE_IS_PA  (1 << 18)
 #define	PACKET3_GEN_PDEPTE				0x5B
 #define	PACKET3_PRIME_UTCL2				0x5D
 #define	PACKET3_LOAD_UCONFIG_REG			0x5E
@@ -348,11 +527,19 @@
 #define	PACKET3_SET_SH_REG				0x76
 #define		PACKET3_SET_SH_REG_START			0x00002c00
 #define		PACKET3_SET_SH_REG_END				0x00003000
+#define 	PACKET3_SET_SH_REG__REG_OFFSET(x) ((((unsigned)(x)) & 0xFFFF) << 0)
+#define 	PACKET3_SET_SH_REG__VMID_SHIFT(x) ((((unsigned)(x)) & 0x1F) << 23)
+#define 	PACKET3_SET_SH_REG__INDEX(x) ((((unsigned)(x)) & 0xF) << 28)
+#define 	PACKET3_SET_SH_REG__REG_DATA(x) (((unsigned)(x)))
+#define 	PACKET3_SET_SH_REG__INDEX__DEFAULT 0
+#define 	PACKET3_SET_SH_REG__INDEX__INSERT_VMID 1
 #define	PACKET3_SET_SH_REG_OFFSET			0x77
 #define	PACKET3_SET_QUEUE_REG				0x78
 #define	PACKET3_SET_UCONFIG_REG				0x79
 #define		PACKET3_SET_UCONFIG_REG_START			0x0000c000
 #define		PACKET3_SET_UCONFIG_REG_END			0x0000c400
+#define 	PACKET3_SET_UCONFIG_REG__REG_OFFSET(x) ((((unsigned)(x)) & 0xFFFF) << 0)
+#define 	PACKET3_SET_UCONFIG_REG__REG_DATA(x) (((unsigned)(x)))
 #define	PACKET3_SET_UCONFIG_REG_INDEX			0x7A
 #define	PACKET3_DISPATCH_DRAW_PREAMBLE			0x8C
 #define	PACKET3_DISPATCH_DRAW				0x8D
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
index 73223d97a87f..ac90d8e9d86a 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
@@ -1571,6 +1571,71 @@ static void gfx_v6_0_setup_spi(struct amdgpu_device *adev)
 	mutex_unlock(&adev->grbm_idx_mutex);
 }
 
+/**
+ * gfx_v6_0_setup_tcc() - setup which TCCs are used
+ *
+ * @adev: amdgpu_device pointer
+ *
+ * Verify whether the current GPU has any TCCs disabled,
+ * which can happen when the GPU is harvested and some
+ * memory channels are disabled, reducing the memory bus width.
+ * For example, on the Radeon HD 7870 XT (Tahiti LE).
+ *
+ * If some TCCs are disabled, we need to make sure that
+ * the disabled TCCs are not used, and the remaining TCCs
+ * are used optimally.
+ *
+ * TCP_CHAN_STEER_LO/HI control which TCC is used by TCP channels.
+ * TCP_ADDR_CONFIG.NUM_TCC_BANKS controls how many channels are used.
+ *
+ * For optimal performance:
+ * - Rely on the CHAN_STEER from the golden registers table,
+ *   only skip disabled TCCs but keep the mapping order.
+ * - Limit NUM_TCC_BANKS to number of active TCCs to avoid thrashing,
+ *   which performs better than using the same TCC twice.
+ */
+static void gfx_v6_0_setup_tcc(struct amdgpu_device *adev)
+{
+	u32 i, tcc, tcp_addr_config, num_active_tcc = 0;
+	u64 chan_steer, patched_chan_steer = 0;
+	const u32 num_max_tcc = adev->gfx.config.max_texture_channel_caches;
+	const u32 dis_tcc_mask =
+		amdgpu_gfx_create_bitmask(num_max_tcc) &
+		(REG_GET_FIELD(RREG32(mmCGTS_TCC_DISABLE),
+			       CGTS_TCC_DISABLE, TCC_DISABLE) |
+		 REG_GET_FIELD(RREG32(mmCGTS_USER_TCC_DISABLE),
+			       CGTS_USER_TCC_DISABLE, TCC_DISABLE));
+
+	/* When no TCC is disabled, the golden registers table already has optimal TCC setup */
+	if (!dis_tcc_mask)
+		return;
+
+	/* Each 4-bit nibble contains the index of a TCC used by all TCPs */
+	chan_steer = RREG32(mmTCP_CHAN_STEER_LO) | ((u64)RREG32(mmTCP_CHAN_STEER_HI) << 32ull);
+
+	/* Patch the TCP to TCC mapping to skip disabled TCCs */
+	for (i = 0; i < num_max_tcc; ++i) {
+		tcc = (chan_steer >> (u64)(4 * i)) & 0xf;
+
+		if (!((1 << tcc) & dis_tcc_mask)) {
+			/* Copy enabled TCC indices to the patched register value. */
+			patched_chan_steer |= (u64)tcc << (u64)(4 * num_active_tcc);
+			++num_active_tcc;
+		}
+	}
+
+	WARN_ON(num_active_tcc != num_max_tcc - hweight32(dis_tcc_mask));
+
+	/* Patch number of TCCs used by TCPs */
+	tcp_addr_config = REG_SET_FIELD(RREG32(mmTCP_ADDR_CONFIG),
+					TCP_ADDR_CONFIG, NUM_TCC_BANKS,
+					num_active_tcc - 1);
+
+	WREG32(mmTCP_ADDR_CONFIG, tcp_addr_config);
+	WREG32(mmTCP_CHAN_STEER_HI, upper_32_bits(patched_chan_steer));
+	WREG32(mmTCP_CHAN_STEER_LO, lower_32_bits(patched_chan_steer));
+}
+
 static void gfx_v6_0_config_init(struct amdgpu_device *adev)
 {
 	adev->gfx.config.double_offchip_lds_buf = 0;
@@ -1729,6 +1794,7 @@ static void gfx_v6_0_constants_init(struct amdgpu_device *adev)
 	gfx_v6_0_tiling_mode_table_init(adev);
 
 	gfx_v6_0_setup_rb(adev);
+	gfx_v6_0_setup_tcc(adev);
 
 	gfx_v6_0_setup_spi(adev);
 
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index 2b691452775b..65b8497ad5f0 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -2819,6 +2819,7 @@ static void gfx_v7_0_mqd_init(struct amdgpu_device *adev,
 {
 	u64 hqd_gpu_addr;
 	u64 wb_gpu_addr;
+	u32 tmp;
 
 	/* init the mqd struct */
 	memset(mqd, 0, sizeof(struct cik_mqd));
@@ -2923,7 +2924,11 @@ static void gfx_v7_0_mqd_init(struct amdgpu_device *adev,
 	mqd->cp_hqd_atomic1_preop_lo = RREG32(mmCP_HQD_ATOMIC1_PREOP_LO);
 	mqd->cp_hqd_atomic1_preop_hi = RREG32(mmCP_HQD_ATOMIC1_PREOP_HI);
 	mqd->cp_hqd_pq_rptr = RREG32(mmCP_HQD_PQ_RPTR);
-	mqd->cp_hqd_quantum = RREG32(mmCP_HQD_QUANTUM);
+	tmp = RREG32(mmCP_HQD_QUANTUM);
+	tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_EN, 1);
+	tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_SCALE, 1);
+	tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_DURATION, 10);
+	mqd->cp_hqd_quantum = tmp;
 	mqd->cp_hqd_pipe_priority = RREG32(mmCP_HQD_PIPE_PRIORITY);
 	mqd->cp_hqd_queue_priority = RREG32(mmCP_HQD_QUEUE_PRIORITY);
 	mqd->cp_hqd_iq_rptr = RREG32(mmCP_HQD_IQ_RPTR);
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index a6b4c8f41dc1..130196859ff3 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -4532,7 +4532,11 @@ static int gfx_v8_0_mqd_init(struct amdgpu_ring *ring)
 
 	/* set static priority for a queue/ring */
 	gfx_v8_0_mqd_set_priority(ring, mqd);
-	mqd->cp_hqd_quantum = RREG32(mmCP_HQD_QUANTUM);
+	tmp = RREG32(mmCP_HQD_QUANTUM);
+	tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_EN, 1);
+	tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_SCALE, 1);
+	tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_DURATION, 10);
+	mqd->cp_hqd_quantum = tmp;
 
 	/* map_queues packet doesn't need activate the queue,
 	 * so only kiq need set this field.
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 95be105671ec..2eb32f92a77c 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -3667,7 +3667,11 @@ static int gfx_v9_0_mqd_init(struct amdgpu_ring *ring)
 
 	/* set static priority for a queue/ring */
 	gfx_v9_0_mqd_set_priority(ring, mqd);
-	mqd->cp_hqd_quantum = RREG32_SOC15(GC, 0, mmCP_HQD_QUANTUM);
+	tmp = RREG32_SOC15(GC, 0, mmCP_HQD_QUANTUM);
+	tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_EN, 1);
+	tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_SCALE, 1);
+	tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_DURATION, 1);
+	mqd->cp_hqd_quantum = tmp;
 
 	/* map_queues packet doesn't need activate the queue,
 	 * so only kiq need set this field.
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
index ad4d442e7345..d0b8fb931720 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.c
@@ -1943,7 +1943,11 @@ static int gfx_v9_4_3_xcc_mqd_init(struct amdgpu_ring *ring, int xcc_id)
 
 	/* set static priority for a queue/ring */
 	gfx_v9_4_3_mqd_set_priority(ring, mqd);
-	mqd->cp_hqd_quantum = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_QUANTUM);
+	tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_HQD_QUANTUM);
+	tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_EN, 1);
+	tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_SCALE, 1);
+	tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_DURATION, 1);
+	mqd->cp_hqd_quantum = tmp;
 
 	/* map_queues packet doesn't need activate the queue,
 	 * so only kiq need set this field.
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c
index e10ac9788d13..5bdd4b9b7893 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v12_0.c
@@ -729,8 +729,10 @@ static int gmc_v12_0_mc_init(struct amdgpu_device *adev)
 	int r;
 
 	if (adev->gmc.xgmi.connected_to_cpu)
-		adev->gmc.mc_vram_size =
-			adev->gmc.xgmi.node_segment_size * adev->gmc.xgmi.num_physical_nodes;
+		/* On A+A, manage driver allocation range to the local
+		 * node segment and prevent allocations on remote HBM.
+		 */
+		adev->gmc.mc_vram_size = adev->gmc.xgmi.node_segment_size;
 	else
 		adev->gmc.mc_vram_size =
 			adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL;
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c b/drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c
index 7ea7b9c30bca..855cd29cbffa 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v12_1.c
@@ -112,6 +112,8 @@ static int gmc_v12_1_process_interrupt(struct amdgpu_device *adev,
 	const char *hub_name;
 	int ret, xcc_id = 0;
 	uint32_t status = 0;
+	const char *die_name;
+	char die_name_buf[32];
 	u64 addr;
 
 	node_id = entry->node_id;
@@ -201,6 +203,17 @@ static int gmc_v12_1_process_interrupt(struct amdgpu_device *adev,
 	dev_err(adev->dev, "  in page starting at address 0x%016llx from IH client %d (%s)\n",
 		addr, entry->client_id, soc_v1_0_ih_clientid_name[entry->client_id]);
 
+	if (adev->irq.ih_funcs &&
+	    adev->irq.ih_funcs->node_id_to_die_name) {
+		die_name = adev->irq.ih_funcs->node_id_to_die_name(adev, node_id,
+								   die_name_buf,
+								   sizeof(die_name_buf));
+		if (die_name)
+			dev_err(adev->dev,
+				"  cookie node_id %d fault from die %s\n",
+				node_id, die_name);
+	}
+
 	if (amdgpu_sriov_vf(adev))
 		return 0;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c b/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c
index 1fbe904f4223..6de9e87e04e1 100644
--- a/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/ih_v7_0.c
@@ -798,6 +798,43 @@ static void ih_v7_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64
 	return;
 }
 
+/*
+ * ih_v7_0_node_id_to_die_name - Decode IH cookie node_id to a die name string
+ *
+ * Currently, only applies to IH v7_1. For other IH versions returns NULL.
+ *
+ * IH v7_1 node_id encoding:
+ * node_id[N:3] = MID index
+ * node_id[2:0] = sub-slot: 0=MID, 1=AID, 2-5=AID.XCD, 6-7=RSV
+ */
+static const char *ih_v7_0_node_id_to_die_name(struct amdgpu_device *adev,
+					       unsigned int node_id,
+					       char *buf, size_t size)
+{
+	int mid_id, sub_slot;
+
+	/* Node ID to die name decoding is only defined for IH v7_1 currenlty. */
+	if (amdgpu_ip_version(adev, OSSSYS_HWIP, 0) != IP_VERSION(7, 1, 0))
+		return NULL;
+
+	mid_id = node_id >> 3;
+	sub_slot = node_id & 0x7;
+
+	if (mid_id > 1)
+		return "UNKNOWN";
+
+	if (sub_slot == 0)
+		snprintf(buf, size, "MID%d", mid_id);
+	else if (sub_slot == 1)
+		snprintf(buf, size, "AID%d", mid_id);
+	else if (sub_slot <= 5)
+		snprintf(buf, size, "AID%d.XCD%d", mid_id, sub_slot - 2);
+	else
+		snprintf(buf, size, "RSV");
+
+	return buf;
+}
+
 static const struct amd_ip_funcs ih_v7_0_ip_funcs = {
 	.name = "ih_v7_0",
 	.early_init = ih_v7_0_early_init,
@@ -819,7 +856,8 @@ static const struct amdgpu_ih_funcs ih_v7_0_funcs = {
 	.get_wptr = ih_v7_0_get_wptr,
 	.decode_iv = amdgpu_ih_decode_iv_helper,
 	.decode_iv_ts = amdgpu_ih_decode_iv_ts_helper,
-	.set_rptr = ih_v7_0_set_rptr
+	.set_rptr = ih_v7_0_set_rptr,
+	.node_id_to_die_name = ih_v7_0_node_id_to_die_name,
 };
 
 static void ih_v7_0_set_interrupt_funcs(struct amdgpu_device *adev)
diff --git a/drivers/gpu/drm/amd/amdgpu/imu_v12_1.c b/drivers/gpu/drm/amd/amdgpu/imu_v12_1.c
index 539785a51f69..fe20cf2b9454 100644
--- a/drivers/gpu/drm/amd/amdgpu/imu_v12_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/imu_v12_1.c
@@ -140,27 +140,17 @@ static int imu_v12_1_switch_compute_partition(struct amdgpu_device *adev,
 	int ret;
 
 	if (adev->psp.funcs) {
-		/*TODO: revisit asp interface once it's avaialble */
-		ret = psp_spatial_partition(&adev->psp,
-					    NUM_XCC(adev->gfx.xcc_mask) /
-						    num_xccs_per_xcp);
+		ret = psp_spatial_partition(&adev->psp, compute_partition_mode);
 		if (ret)
 			return ret;
 	}
 
 	adev->gfx.num_xcc_per_xcp = num_xccs_per_xcp;
-
 	return 0;
 }
 
-static void imu_v12_1_init_mcm_addr_lut(struct amdgpu_device *adev)
-{
-	/* todo: fill in when interface is ready */
-}
-
 const struct amdgpu_imu_funcs gfx_v12_1_imu_funcs = {
 	.init_microcode = imu_v12_1_init_microcode,
 	.load_microcode = imu_v12_1_load_microcode,
 	.switch_compute_partition = imu_v12_1_switch_compute_partition,
-	.init_mcm_addr_lut = imu_v12_1_init_mcm_addr_lut,
 };
diff --git a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
index 20983f126b49..fe2b049afac3 100644
--- a/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.c
@@ -149,7 +149,7 @@ static int jpeg_v2_5_sw_init(struct amdgpu_ip_block *ip_block)
 		else
 			ring->vm_hub = AMDGPU_MMHUB0(0);
 		ring->doorbell_index = (adev->doorbell_index.vcn.vcn_ring0_1 << 1) + 1 + 8 * i;
-		sprintf(ring->name, "jpeg_dec_%d", i);
+		snprintf(ring->name, sizeof(ring->name), "jpeg_dec_%d", i);
 		r = amdgpu_ring_init(adev, ring, 512, &adev->jpeg.inst[i].irq,
 				     0, AMDGPU_RING_PRIO_DEFAULT, NULL);
 		if (r)
diff --git a/drivers/gpu/drm/amd/amdgpu/mes_v12_1.c b/drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
index cec801278126..2d8a10d18939 100644
--- a/drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/mes_v12_1.c
@@ -44,6 +44,7 @@ static int mes_v12_1_hw_fini(struct amdgpu_ip_block *ip_block);
 static int mes_v12_1_kiq_hw_init(struct amdgpu_device *adev, uint32_t xcc_id);
 static int mes_v12_1_kiq_hw_fini(struct amdgpu_device *adev, uint32_t xcc_id);
 static int mes_v12_1_self_test(struct amdgpu_device *adev, int xcc_id);
+static int mes_v12_1_setup_coop_mode(struct amdgpu_device *adev, int xcc_id);
 
 #define MES_EOP_SIZE   2048
 
@@ -621,11 +622,15 @@ static int mes_v12_1_set_hw_resources_1(struct amdgpu_mes *mes,
 	mes_set_hw_res_1_pkt.header.dwsize = API_FRAME_SIZE_IN_DWORDS;
 	mes_set_hw_res_1_pkt.mes_kiq_unmap_timeout = 100;
 
-	if (mes->enable_coop_mode && pipe == AMDGPU_MES_SCHED_PIPE) {
+	/* From version 0x74 above, pipe1 support use shared command buffer
+	   to distribute some tasks on individual XCCs*/
+	if (mes->enable_coop_mode &&
+	    ((pipe == AMDGPU_MES_SCHED_PIPE) ||
+	    ((mes->kiq_version & AMDGPU_MES_VERSION_MASK) >= 0x74))) {
 		master_xcc_id = mes->master_xcc_ids[inst];
 		mes_set_hw_res_1_pkt.mes_coop_mode = 1;
 		mes_set_hw_res_1_pkt.coop_sch_shared_mc_addr =
-			mes->shared_cmd_buf_gpu_addr[master_xcc_id];
+			mes->shared_cmd_buf_gpu_addr[master_xcc_id + pipe];
 	}
 
 	return mes_v12_1_submit_pkt_and_poll_completion(mes, xcc_id, pipe,
@@ -633,21 +638,10 @@ static int mes_v12_1_set_hw_resources_1(struct amdgpu_mes *mes,
 			offsetof(union MESAPI_SET_HW_RESOURCES_1, api_status));
 }
 
-static void mes_v12_1_set_gfx_hqd_mask(union MESAPI_SET_HW_RESOURCES *pkt)
-{
-	/*
-	 * GFX V12 has only one GFX pipe, but 8 queues in it.
-	 * GFX pipe 0 queue 0 is being used by Kernel queue.
-	 * Set GFX pipe 0 queue 1-7 for MES scheduling
-	 * mask = 1111 1110b
-	 */
-	pkt->gfx_hqd_mask[0] = 0xFE;
-}
-
 static int mes_v12_1_set_hw_resources(struct amdgpu_mes *mes,
 					int pipe, int xcc_id)
 {
-	int i;
+	int i, status;
 	struct amdgpu_device *adev = mes->adev;
 	union MESAPI_SET_HW_RESOURCES mes_set_hw_res_pkt;
 
@@ -667,7 +661,9 @@ static int mes_v12_1_set_hw_resources(struct amdgpu_mes *mes,
 			mes_set_hw_res_pkt.compute_hqd_mask[i] =
 				mes->compute_hqd_mask[i];
 
-		mes_v12_1_set_gfx_hqd_mask(&mes_set_hw_res_pkt);
+		for (i = 0; i < MAX_GFX_PIPES; i++)
+			mes_set_hw_res_pkt.gfx_hqd_mask[i] =
+				mes->gfx_hqd_mask[i];
 
 		for (i = 0; i < MAX_SDMA_PIPES; i++)
 			mes_set_hw_res_pkt.sdma_hqd_mask[i] =
@@ -715,9 +711,23 @@ static int mes_v12_1_set_hw_resources(struct amdgpu_mes *mes,
 	if (adev->enforce_isolation[0] == AMDGPU_ENFORCE_ISOLATION_ENABLE)
 		mes_set_hw_res_pkt.limit_single_process = 1;
 
-	return mes_v12_1_submit_pkt_and_poll_completion(mes, xcc_id, pipe,
+	status = mes_v12_1_submit_pkt_and_poll_completion(mes, xcc_id, pipe,
 			&mes_set_hw_res_pkt, sizeof(mes_set_hw_res_pkt),
 			offsetof(union MESAPI_SET_HW_RESOURCES, api_status));
+
+	/* get MES scheduler versions */
+	mutex_lock(&adev->srbm_mutex);
+	soc_v1_0_grbm_select(adev, 3, pipe, 0, 0, GET_INST(GC, xcc_id));
+
+	if (pipe == AMDGPU_MES_SCHED_PIPE)
+		adev->mes.sched_version = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_GP3_LO);
+	else if (pipe == AMDGPU_MES_KIQ_PIPE && adev->enable_mes_kiq)
+		adev->mes.kiq_version = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_GP3_LO);
+
+	soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));
+	mutex_unlock(&adev->srbm_mutex);
+
+	return status;
 }
 
 static void mes_v12_1_init_aggregated_doorbell(struct amdgpu_mes *mes,
@@ -1157,9 +1167,6 @@ static int mes_v12_1_allocate_shared_cmd_buf(struct amdgpu_device *adev,
 {
 	int r, inst = MES_PIPE_INST(xcc_id, pipe);
 
-	if (pipe == AMDGPU_MES_KIQ_PIPE)
-		return 0;
-
 	r = amdgpu_bo_create_kernel(adev, PAGE_SIZE, PAGE_SIZE,
 				    AMDGPU_GEM_DOMAIN_VRAM,
 				    &adev->mes.shared_cmd_buf_obj[inst],
@@ -1405,18 +1412,6 @@ static int mes_v12_1_queue_init(struct amdgpu_device *adev,
 		mes_v12_1_queue_init_register(ring, xcc_id);
 	}
 
-	/* get MES scheduler/KIQ versions */
-	mutex_lock(&adev->srbm_mutex);
-	soc_v1_0_grbm_select(adev, 3, pipe, 0, 0, GET_INST(GC, xcc_id));
-
-	if (pipe == AMDGPU_MES_SCHED_PIPE)
-		adev->mes.sched_version = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_GP3_LO);
-	else if (pipe == AMDGPU_MES_KIQ_PIPE && adev->enable_mes_kiq)
-		adev->mes.kiq_version = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MES_GP3_LO);
-
-	soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id));
-	mutex_unlock(&adev->srbm_mutex);
-
 	return 0;
 }
 
@@ -1723,6 +1718,10 @@ static int mes_v12_1_kiq_hw_init(struct amdgpu_device *adev, uint32_t xcc_id)
 		goto failure;
 
 	if (adev->enable_uni_mes) {
+		r = mes_v12_1_setup_coop_mode(adev, xcc_id);
+		if (r)
+			goto failure;
+
 		r = mes_v12_1_set_hw_resources(&adev->mes,
 						 AMDGPU_MES_KIQ_PIPE, xcc_id);
 		if (r)
@@ -1845,9 +1844,6 @@ static int mes_v12_1_xcc_hw_init(struct amdgpu_ip_block *ip_block, int xcc_id)
 		goto failure;
 
 	if (adev->enable_uni_mes) {
-		r = mes_v12_1_setup_coop_mode(adev, xcc_id);
-		if (r)
-			goto failure;
 		mes_v12_1_set_hw_resources_1(&adev->mes,
 					       AMDGPU_MES_SCHED_PIPE, xcc_id);
 	}
@@ -1897,24 +1893,12 @@ static int mes_v12_1_hw_fini(struct amdgpu_ip_block *ip_block)
 
 static int mes_v12_1_suspend(struct amdgpu_ip_block *ip_block)
 {
-	int r;
-
-	r = amdgpu_mes_suspend(ip_block->adev);
-	if (r)
-		return r;
-
 	return mes_v12_1_hw_fini(ip_block);
 }
 
 static int mes_v12_1_resume(struct amdgpu_ip_block *ip_block)
 {
-	int r;
-
-	r = mes_v12_1_hw_init(ip_block);
-	if (r)
-		return r;
-
-	return amdgpu_mes_resume(ip_block->adev);
+	return mes_v12_1_hw_init(ip_block);
 }
 
 static int mes_v12_1_early_init(struct amdgpu_ip_block *ip_block)
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_3_2.c b/drivers/gpu/drm/amd/amdgpu/nbio_v6_3_2.c
new file mode 100644
index 000000000000..5e8f466f23ad
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_3_2.c
@@ -0,0 +1,369 @@
+/*
+ * Copyright 2025 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#include "nbio/nbio_6_3_2_offset.h"
+#include "nbio/nbio_6_3_2_sh_mask.h"
+
+#include "amdgpu.h"
+#include "nbio_v6_3_2.h"
+
+static u32 nbio_v6_3_2_get_pcie_index_offset(struct amdgpu_device *adev)
+{
+	return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_INDEX2);
+}
+
+static u32 nbio_v6_3_2_get_pcie_data_offset(struct amdgpu_device *adev)
+{
+	return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_DATA2);
+}
+
+static u32 nbio_v6_3_2_get_pcie_index_hi_offset(struct amdgpu_device *adev)
+{
+	return SOC15_REG_OFFSET(NBIO, 0, regBIF_BX0_PCIE_INDEX2_HI);
+}
+
+static u32 nbio_v6_3_2_get_rev_id(struct amdgpu_device *adev)
+{
+	u32 tmp;
+
+	/* TODO: RCC_STRAP0_RCC_DEV0_EPF0_STRAP0 is not accessible from
+	 * guest side. It requires bootloader to update specific fields
+	 * in ip discovery table to identify soc revision id.
+	 * Return 0 when the function is called from guest side until
+	 * bootloader change is available.
+	 */
+	if (amdgpu_sriov_vf(adev))
+		return 0;
+
+	tmp = RREG32_SOC15(NBIO, 0, regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0);
+	tmp = REG_GET_FIELD(tmp, RCC_STRAP0_RCC_DEV0_EPF0_STRAP0,
+			    STRAP_ATI_REV_ID_DEV0_F0);
+
+	return tmp;
+}
+
+static void nbio_v6_3_2_mc_access_enable(struct amdgpu_device *adev,
+					 bool enable)
+{
+	if (enable)
+		WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN,
+			BIF_BX0_BIF_FB_EN__FB_READ_EN_MASK | BIF_BX0_BIF_FB_EN__FB_WRITE_EN_MASK);
+	else
+		WREG32_SOC15(NBIO, 0, regBIF_BX0_BIF_FB_EN, 0);
+}
+
+static void nbio_v6_3_2_init_registers(struct amdgpu_device *adev)
+{
+	WREG32_SOC15(NBIO, 0, regXCD_DOORBELL_FENCE_1,
+		(0xff & ~(adev->gfx.xcc_mask)) <<
+		XCD_DOORBELL_FENCE_1__XCD_0_DOORBELL_DISABLE__SHIFT);
+}
+
+static u32 nbio_v6_3_2_get_memsize(struct amdgpu_device *adev)
+{
+	return RREG32_SOC15(NBIO, 0, regRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE);
+}
+
+static void nbio_v6_3_2_enable_doorbell_aperture(struct amdgpu_device *adev,
+						 bool enable)
+{
+	/* Enable to allow doorbell pass thru on pre-silicon bare-metal */
+	WREG32_SOC15(NBIO, 0, regGDC0_DOORBELL_ACCESS_EN_PF, 0xfffff);
+	WREG32_FIELD15_PREREG(NBIO, 0, RCC_DEV0_EPF0_RCC_DOORBELL_APER_EN,
+			BIF_DOORBELL_APER_EN, enable ? 1 : 0);
+}
+
+static void nbio_v6_3_2_enable_doorbell_selfring_aperture(struct amdgpu_device *adev,
+							  bool enable)
+{
+	u32 tmp = 0;
+
+	if (enable) {
+		tmp = REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
+				    DOORBELL_SELFRING_GPA_APER_EN, 1) |
+		      REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
+				    DOORBELL_SELFRING_GPA_APER_MODE, 1) |
+		      REG_SET_FIELD(tmp, BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL,
+				    DOORBELL_SELFRING_GPA_APER_SIZE, 0);
+
+		WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW,
+			     lower_32_bits(adev->doorbell.base));
+		WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH,
+			     upper_32_bits(adev->doorbell.base));
+	}
+
+	WREG32_SOC15(NBIO, 0, regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL, tmp);
+}
+
+static void nbio_v6_3_2_enable_doorbell_interrupt(struct amdgpu_device *adev,
+						  bool enable)
+{
+	WREG32_FIELD15_PREREG(NBIO, 0, BIF_BX0_BIF_DOORBELL_INT_CNTL,
+			      DOORBELL_INTERRUPT_DISABLE, enable ? 0 : 1);
+}
+
+static void nbio_v6_3_2_ih_control(struct amdgpu_device *adev)
+{
+	u32 interrupt_cntl;
+
+	/* setup interrupt control */
+	WREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL2, adev->dummy_page_addr >> 8);
+
+	interrupt_cntl = RREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL);
+	/*
+	 * BIF_BX0_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=0 - dummy read disabled with msi, enabled without msi
+	 * BIF_BX0_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK=1 - dummy read controlled by IH_DUMMY_RD_EN
+	 */
+	interrupt_cntl = REG_SET_FIELD(interrupt_cntl, BIF_BX0_INTERRUPT_CNTL,
+				       IH_DUMMY_RD_OVERRIDE, 0);
+
+	/* BIF_BX0_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK=1 if ring is in non-cacheable memory, e.g., vram */
+	interrupt_cntl = REG_SET_FIELD(interrupt_cntl, BIF_BX0_INTERRUPT_CNTL,
+				       IH_REQ_NONSNOOP_EN, 0);
+
+	WREG32_SOC15(NBIO, 0, regBIF_BX0_INTERRUPT_CNTL, interrupt_cntl);
+}
+
+static void nbio_v6_3_2_ih_doorbell_range(struct amdgpu_device *adev,
+					  bool use_doorbell, int doorbell_index)
+{
+	u32 ih_doorbell_range = 0;
+	u32 ih_doorbell_range1 = 0;
+
+	if (use_doorbell) {
+		ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
+						  GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL,
+						  S2A_DOORBELL_PORT1_ENABLE,
+						  0x1);
+		ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
+						  GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL,
+						  S2A_DOORBELL_PORT1_AWID,
+						  0x0);
+		ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
+						  GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL,
+						  S2A_DOORBELL_PORT1_RANGE_OFFSET,
+						  doorbell_index);
+		ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
+						  GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL,
+						  S2A_DOORBELL_PORT1_RANGE_SIZE,
+						  8);
+		ih_doorbell_range = REG_SET_FIELD(ih_doorbell_range,
+						  GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL,
+						  S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE,
+						  0x0);
+		ih_doorbell_range1 = REG_SET_FIELD(ih_doorbell_range1,
+						   GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL1,
+						   S2A_DOORBELL_PORT1_TARGET_PORT_TYPE,
+						   0x3);
+		ih_doorbell_range1 = REG_SET_FIELD(ih_doorbell_range1,
+						   GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL1,
+						   S2A_DOORBELL_PORT1_TARGET_DIEID,
+						   0x0);
+		ih_doorbell_range1 = REG_SET_FIELD(ih_doorbell_range1,
+						   GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL1,
+						   S2A_DOORBELL_PORT1_TARGET_PORT_ID,
+						   0x0);
+	}
+
+	WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL, ih_doorbell_range);
+	WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL1, ih_doorbell_range1);
+}
+
+static void nbio_v6_3_2_gc_doorbell_init(struct amdgpu_device *adev)
+{
+	WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL, 0x30000007);
+	WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL1, 0x3);
+}
+
+static void nbio_v6_3_2_sdma_doorbell_range(struct amdgpu_device *adev,
+					    int instance, bool use_doorbell,
+					    int doorbell_index,
+					    int doorbell_size)
+{
+	if (instance == 0) {
+		u32 doorbell_range = 0;
+		u32 doorbell_range1 = 0;
+
+		if (use_doorbell) {
+			doorbell_range = REG_SET_FIELD(doorbell_range,
+						       GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL,
+						       S2A_DOORBELL_PORT6_ENABLE,
+						       0x1);
+			doorbell_range = REG_SET_FIELD(doorbell_range,
+						       GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL,
+						       S2A_DOORBELL_PORT6_AWID,
+						       0xe);
+			doorbell_range = REG_SET_FIELD(doorbell_range,
+						       GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL,
+						       S2A_DOORBELL_PORT6_RANGE_OFFSET,
+						       doorbell_index);
+			doorbell_range = REG_SET_FIELD(doorbell_range,
+						       GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL,
+						       S2A_DOORBELL_PORT6_RANGE_SIZE,
+						       doorbell_size);
+			doorbell_range = REG_SET_FIELD(doorbell_range,
+						       GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL,
+						       S2A_DOORBELL_PORT6_AWADDR_31_28_VALUE,
+						       0xe);
+			doorbell_range1 = REG_SET_FIELD(doorbell_range1,
+						        GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL1,
+						        S2A_DOORBELL_PORT6_TARGET_PORT_TYPE,
+						        0x3);
+			doorbell_range1 = REG_SET_FIELD(doorbell_range1,
+						        GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL1,
+						        S2A_DOORBELL_PORT6_TARGET_DIEID,
+						        0x0);
+			doorbell_range1 = REG_SET_FIELD(doorbell_range1,
+						        GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL1,
+						        S2A_DOORBELL_PORT6_TARGET_PORT_ID,
+						        0x0);
+		}
+
+		WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL, doorbell_range);
+		WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL1, doorbell_range1);
+	}
+}
+
+static void nbio_v6_3_2_vcn_doorbell_range(struct amdgpu_device *adev,
+					   bool use_doorbell, int doorbell_index,
+					   int instance)
+{
+	u32 doorbell_range = 0;
+	u32 doorbell_range1 = 0;
+
+	if (use_doorbell) {
+		doorbell_range = REG_SET_FIELD(doorbell_range,
+					       GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL,
+					       S2A_DOORBELL_PORT2_ENABLE,
+					       0x1);
+		doorbell_range = REG_SET_FIELD(doorbell_range,
+					       GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL,
+					       S2A_DOORBELL_PORT2_AWID,
+					       (instance % adev->vcn.num_inst_per_aid) ? 0x7 : 0x4);
+		doorbell_range = REG_SET_FIELD(doorbell_range,
+					       GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL,
+					       S2A_DOORBELL_PORT2_RANGE_OFFSET,
+					       doorbell_index);
+		doorbell_range = REG_SET_FIELD(doorbell_range,
+					       GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL,
+					       S2A_DOORBELL_PORT2_RANGE_SIZE,
+					       8);
+		doorbell_range = REG_SET_FIELD(doorbell_range,
+					       GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL,
+					       S2A_DOORBELL_PORT2_AWADDR_31_28_VALUE,
+					       (instance % adev->vcn.num_inst_per_aid) ? 0x7 : 0x4);
+		doorbell_range1 = REG_SET_FIELD(doorbell_range1,
+						GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL1,
+					        S2A_DOORBELL_PORT2_TARGET_PORT_TYPE,
+					        0x3);
+		doorbell_range1 = REG_SET_FIELD(doorbell_range1,
+						GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL1,
+					        S2A_DOORBELL_PORT2_TARGET_DIEID,
+					        (instance / adev->vcn.num_inst_per_aid) ? 0x3 : 0x0);
+		doorbell_range1 = REG_SET_FIELD(doorbell_range1,
+						GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL1,
+					        S2A_DOORBELL_PORT2_TARGET_PORT_ID,
+					        0x0);
+	}
+
+	switch (instance) {
+	case 0:
+		WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL, doorbell_range);
+		WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL1, doorbell_range1);
+		break;
+	case 1:
+		WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL, doorbell_range);
+		WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL1, doorbell_range1);
+		break;
+	case 2:
+		WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL, doorbell_range);
+		WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL1, doorbell_range1);
+		break;
+	case 3:
+		WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL, doorbell_range);
+		WREG32_SOC15(NBIO, 0, regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL1, doorbell_range1);
+		break;
+	default:
+		dev_err(adev->dev,
+			"amdgpu: invalid vcn instance set when program doorbell range\n");
+		break;
+	}
+}
+
+static int nbio_v6_3_2_get_compute_partition_mode(struct amdgpu_device *adev)
+{
+	u32 tmp, px;
+
+	tmp = RREG32_SOC15(NBIO, 0, regBIF_BX_PF0_PARTITION_COMPUTE_STATUS);
+	px = REG_GET_FIELD(tmp, BIF_BX_PF0_PARTITION_COMPUTE_STATUS,
+			   PARTITION_MODE);
+
+	return px;
+}
+
+static bool nbio_v6_3_2_is_nps_switch_requested(struct amdgpu_device *adev)
+{
+	u32 tmp;
+
+	tmp = RREG32_SOC15(NBIO, 0, regBIF_BX_PF0_PARTITION_MEM_STATUS);
+	tmp = REG_GET_FIELD(tmp, BIF_BX_PF0_PARTITION_MEM_STATUS,
+			    CHANGE_STATUS);
+
+	/* 0x8 - NPS switch requested */
+	return (tmp == 0x8);
+}
+static u32 nbio_v6_3_2_get_memory_partition_mode(struct amdgpu_device *adev,
+						 u32 *supp_modes)
+{
+	u32 tmp;
+
+	tmp = RREG32_SOC15(NBIO, 0, regBIF_BX_PF0_PARTITION_MEM_STATUS);
+	tmp = REG_GET_FIELD(tmp, BIF_BX_PF0_PARTITION_MEM_STATUS, NPS_MODE);
+
+	if (supp_modes) {
+		*supp_modes =
+			RREG32_SOC15(NBIO, 0, regBIF_BX_PF0_PARTITION_MEM_CAP);
+	}
+
+	return ffs(tmp);
+}
+
+const struct amdgpu_nbio_funcs nbio_v6_3_2_funcs = {
+	.get_pcie_index_offset = nbio_v6_3_2_get_pcie_index_offset,
+	.get_pcie_data_offset = nbio_v6_3_2_get_pcie_data_offset,
+	.get_pcie_index_hi_offset = nbio_v6_3_2_get_pcie_index_hi_offset,
+	.get_rev_id = nbio_v6_3_2_get_rev_id,
+	.mc_access_enable = nbio_v6_3_2_mc_access_enable,
+	.get_memsize = nbio_v6_3_2_get_memsize,
+	.enable_doorbell_aperture = nbio_v6_3_2_enable_doorbell_aperture,
+	.enable_doorbell_selfring_aperture = nbio_v6_3_2_enable_doorbell_selfring_aperture,
+	.enable_doorbell_interrupt = nbio_v6_3_2_enable_doorbell_interrupt,
+	.get_compute_partition_mode = nbio_v6_3_2_get_compute_partition_mode,
+	.get_memory_partition_mode = nbio_v6_3_2_get_memory_partition_mode,
+	.is_nps_switch_requested = nbio_v6_3_2_is_nps_switch_requested,
+	.ih_control = nbio_v6_3_2_ih_control,
+	.ih_doorbell_range = nbio_v6_3_2_ih_doorbell_range,
+	.gc_doorbell_init = nbio_v6_3_2_gc_doorbell_init,
+	.sdma_doorbell_range = nbio_v6_3_2_sdma_doorbell_range,
+	.vcn_doorbell_range = nbio_v6_3_2_vcn_doorbell_range,
+	.init_registers = nbio_v6_3_2_init_registers,
+};
diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v6_3_2.h b/drivers/gpu/drm/amd/amdgpu/nbio_v6_3_2.h
new file mode 100644
index 000000000000..bc7f747c88f4
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v6_3_2.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright 2025 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+
+#ifndef __NBIO_V6_3_2_H__
+#define __NBIO_V6_3_2_H__
+
+#include "soc15_common.h"
+
+extern const struct amdgpu_nbio_funcs nbio_v6_3_2_funcs;
+
+#endif
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v15_0_8.c b/drivers/gpu/drm/amd/amdgpu/psp_v15_0_8.c
index b2d7cbd894c0..ec20cd5eb755 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v15_0_8.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v15_0_8.c
@@ -32,6 +32,7 @@
 #include "mp/mp_15_0_8_sh_mask.h"
 
 MODULE_FIRMWARE("amdgpu/psp_15_0_8_toc.bin");
+MODULE_FIRMWARE("amdgpu/psp_15_0_8_toc_1.bin");
 
 static int psp_v15_0_8_init_microcode(struct psp_context *psp)
 {
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
index 0090ace49024..93ec52c1f367 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
@@ -828,7 +828,6 @@ static int sdma_v2_4_early_init(struct amdgpu_ip_block *ip_block)
 		return r;
 
 	sdma_v2_4_set_ring_funcs(adev);
-	sdma_v2_4_set_buffer_funcs(adev);
 	amdgpu_sdma_set_vm_pte_scheds(adev, &sdma_v2_4_vm_pte_funcs);
 	sdma_v2_4_set_irq_funcs(adev);
 
@@ -898,7 +897,9 @@ static int sdma_v2_4_hw_init(struct amdgpu_ip_block *ip_block)
 	if (r)
 		return r;
 
-	return r;
+	sdma_v2_4_set_buffer_funcs(adev);
+
+	return 0;
 }
 
 static int sdma_v2_4_hw_fini(struct amdgpu_ip_block *ip_block)
@@ -1235,8 +1236,7 @@ static const struct amdgpu_buffer_funcs sdma_v2_4_buffer_funcs = {
 
 static void sdma_v2_4_set_buffer_funcs(struct amdgpu_device *adev)
 {
-	adev->mman.buffer_funcs = &sdma_v2_4_buffer_funcs;
-	adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
+	amdgpu_sdma_set_buffer_funcs_scheds(adev, &sdma_v2_4_buffer_funcs);
 }
 
 const struct amdgpu_ip_block_version sdma_v2_4_ip_block = {
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
index 2526d393162a..3fde9be74690 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
@@ -1108,7 +1108,6 @@ static int sdma_v3_0_early_init(struct amdgpu_ip_block *ip_block)
 		return r;
 
 	sdma_v3_0_set_ring_funcs(adev);
-	sdma_v3_0_set_buffer_funcs(adev);
 	amdgpu_sdma_set_vm_pte_scheds(adev, &sdma_v3_0_vm_pte_funcs);
 	sdma_v3_0_set_irq_funcs(adev);
 
@@ -1184,7 +1183,9 @@ static int sdma_v3_0_hw_init(struct amdgpu_ip_block *ip_block)
 	if (r)
 		return r;
 
-	return r;
+	sdma_v3_0_set_buffer_funcs(adev);
+
+	return 0;
 }
 
 static int sdma_v3_0_hw_fini(struct amdgpu_ip_block *ip_block)
@@ -1677,8 +1678,7 @@ static const struct amdgpu_buffer_funcs sdma_v3_0_buffer_funcs = {
 
 static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev)
 {
-	adev->mman.buffer_funcs = &sdma_v3_0_buffer_funcs;
-	adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
+	amdgpu_sdma_set_buffer_funcs_scheds(adev, &sdma_v3_0_buffer_funcs);
 }
 
 const struct amdgpu_ip_block_version sdma_v3_0_ip_block =
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 44f0f23e1148..8a2a4e61867e 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -1775,7 +1775,6 @@ static int sdma_v4_0_early_init(struct amdgpu_ip_block *ip_block)
 		adev->sdma.has_page_queue = true;
 
 	sdma_v4_0_set_ring_funcs(adev);
-	sdma_v4_0_set_buffer_funcs(adev);
 	amdgpu_sdma_set_vm_pte_scheds(adev, &sdma_v4_0_vm_pte_funcs);
 	sdma_v4_0_set_irq_funcs(adev);
 	sdma_v4_0_set_ras_funcs(adev);
@@ -1961,6 +1960,7 @@ static int sdma_v4_0_sw_fini(struct amdgpu_ip_block *ip_block)
 static int sdma_v4_0_hw_init(struct amdgpu_ip_block *ip_block)
 {
 	struct amdgpu_device *adev = ip_block->adev;
+	int r;
 
 	if (adev->flags & AMD_IS_APU)
 		amdgpu_dpm_set_powergating_by_smu(adev, AMD_IP_BLOCK_TYPE_SDMA, false, 0);
@@ -1968,7 +1968,12 @@ static int sdma_v4_0_hw_init(struct amdgpu_ip_block *ip_block)
 	if (!amdgpu_sriov_vf(adev))
 		sdma_v4_0_init_golden_registers(adev);
 
-	return sdma_v4_0_start(adev);
+	r = sdma_v4_0_start(adev);
+	if (r)
+		return r;
+	sdma_v4_0_set_buffer_funcs(adev);
+
+	return 0;
 }
 
 static int sdma_v4_0_hw_fini(struct amdgpu_ip_block *ip_block)
@@ -2626,13 +2631,9 @@ static const struct amdgpu_buffer_funcs sdma_v4_4_buffer_funcs = {
 static void sdma_v4_0_set_buffer_funcs(struct amdgpu_device *adev)
 {
 	if (amdgpu_ip_version(adev, SDMA0_HWIP, 0) >= IP_VERSION(4, 4, 0))
-		adev->mman.buffer_funcs = &sdma_v4_4_buffer_funcs;
-	else
-		adev->mman.buffer_funcs = &sdma_v4_0_buffer_funcs;
-	if (adev->sdma.has_page_queue)
-		adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].page;
+		amdgpu_sdma_set_buffer_funcs_scheds(adev, &sdma_v4_4_buffer_funcs);
 	else
-		adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
+		amdgpu_sdma_set_buffer_funcs_scheds(adev, &sdma_v4_0_buffer_funcs);
 }
 
 static void sdma_v4_0_get_ras_error_count(uint32_t value,
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
index 78bdfed0a7fd..88428b88e00f 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.c
@@ -1368,7 +1368,6 @@ static int sdma_v4_4_2_early_init(struct amdgpu_ip_block *ip_block)
 		adev->sdma.has_page_queue = true;
 
 	sdma_v4_4_2_set_ring_funcs(adev);
-	sdma_v4_4_2_set_buffer_funcs(adev);
 	amdgpu_sdma_set_vm_pte_scheds(adev, &sdma_v4_4_2_vm_pte_funcs);
 	sdma_v4_4_2_set_irq_funcs(adev);
 	sdma_v4_4_2_set_ras_funcs(adev);
@@ -1568,8 +1567,11 @@ static int sdma_v4_4_2_hw_init(struct amdgpu_ip_block *ip_block)
 		sdma_v4_4_2_inst_init_golden_registers(adev, inst_mask);
 
 	r = sdma_v4_4_2_inst_start(adev, inst_mask, false);
+	if (r)
+		return r;
+	sdma_v4_4_2_set_buffer_funcs(adev);
 
-	return r;
+	return 0;
 }
 
 static int sdma_v4_4_2_hw_fini(struct amdgpu_ip_block *ip_block)
@@ -2316,11 +2318,7 @@ static const struct amdgpu_buffer_funcs sdma_v4_4_2_buffer_funcs = {
 
 static void sdma_v4_4_2_set_buffer_funcs(struct amdgpu_device *adev)
 {
-	adev->mman.buffer_funcs = &sdma_v4_4_2_buffer_funcs;
-	if (adev->sdma.has_page_queue)
-		adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].page;
-	else
-		adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
+	amdgpu_sdma_set_buffer_funcs_scheds(adev, &sdma_v4_4_2_buffer_funcs);
 }
 
 /**
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
index 52f4e9e099cb..fa02907217e0 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c
@@ -1373,7 +1373,6 @@ static int sdma_v5_0_early_init(struct amdgpu_ip_block *ip_block)
 		return r;
 
 	sdma_v5_0_set_ring_funcs(adev);
-	sdma_v5_0_set_buffer_funcs(adev);
 	amdgpu_sdma_set_vm_pte_scheds(adev, &sdma_v5_0_vm_pte_funcs);
 	sdma_v5_0_set_irq_funcs(adev);
 	sdma_v5_0_set_mqd_funcs(adev);
@@ -1472,8 +1471,11 @@ static int sdma_v5_0_hw_init(struct amdgpu_ip_block *ip_block)
 	sdma_v5_0_init_golden_registers(adev);
 
 	r = sdma_v5_0_start(adev);
+	if (r)
+		return r;
+	sdma_v5_0_set_buffer_funcs(adev);
 
-	return r;
+	return 0;
 }
 
 static int sdma_v5_0_hw_fini(struct amdgpu_ip_block *ip_block)
@@ -2052,10 +2054,7 @@ static const struct amdgpu_buffer_funcs sdma_v5_0_buffer_funcs = {
 
 static void sdma_v5_0_set_buffer_funcs(struct amdgpu_device *adev)
 {
-	if (adev->mman.buffer_funcs == NULL) {
-		adev->mman.buffer_funcs = &sdma_v5_0_buffer_funcs;
-		adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
-	}
+	amdgpu_sdma_set_buffer_funcs_scheds(adev, &sdma_v5_0_buffer_funcs);
 }
 
 const struct amdgpu_ip_block_version sdma_v5_0_ip_block = {
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
index b4fb90cc8f7d..f6ecbc524c9b 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v5_2.c
@@ -1264,7 +1264,6 @@ static int sdma_v5_2_early_init(struct amdgpu_ip_block *ip_block)
 		return r;
 
 	sdma_v5_2_set_ring_funcs(adev);
-	sdma_v5_2_set_buffer_funcs(adev);
 	amdgpu_sdma_set_vm_pte_scheds(adev, &sdma_v5_2_vm_pte_funcs);
 	sdma_v5_2_set_irq_funcs(adev);
 	sdma_v5_2_set_mqd_funcs(adev);
@@ -1385,8 +1384,14 @@ static int sdma_v5_2_sw_fini(struct amdgpu_ip_block *ip_block)
 static int sdma_v5_2_hw_init(struct amdgpu_ip_block *ip_block)
 {
 	struct amdgpu_device *adev = ip_block->adev;
+	int r;
+
+	r = sdma_v5_2_start(adev);
+	if (r)
+		return r;
+	sdma_v5_2_set_buffer_funcs(adev);
 
-	return sdma_v5_2_start(adev);
+	return 0;
 }
 
 static int sdma_v5_2_hw_fini(struct amdgpu_ip_block *ip_block)
@@ -2056,10 +2061,7 @@ static const struct amdgpu_buffer_funcs sdma_v5_2_buffer_funcs = {
 
 static void sdma_v5_2_set_buffer_funcs(struct amdgpu_device *adev)
 {
-	if (adev->mman.buffer_funcs == NULL) {
-		adev->mman.buffer_funcs = &sdma_v5_2_buffer_funcs;
-		adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
-	}
+	amdgpu_sdma_set_buffer_funcs_scheds(adev, &sdma_v5_2_buffer_funcs);
 }
 
 const struct amdgpu_ip_block_version sdma_v5_2_ip_block = {
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
index 0f530bb8a9a3..de329b76a00c 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
@@ -1313,7 +1313,6 @@ static int sdma_v6_0_early_init(struct amdgpu_ip_block *ip_block)
 		return r;
 
 	sdma_v6_0_set_ring_funcs(adev);
-	sdma_v6_0_set_buffer_funcs(adev);
 	amdgpu_sdma_set_vm_pte_scheds(adev, &sdma_v6_0_vm_pte_funcs);
 	sdma_v6_0_set_irq_funcs(adev);
 	sdma_v6_0_set_mqd_funcs(adev);
@@ -1477,6 +1476,7 @@ static int sdma_v6_0_hw_init(struct amdgpu_ip_block *ip_block)
 	r = sdma_v6_0_start(adev);
 	if (r)
 		return r;
+	sdma_v6_0_set_buffer_funcs(adev);
 
 	return sdma_v6_0_set_userq_trap_interrupts(adev, true);
 }
@@ -1895,8 +1895,7 @@ static const struct amdgpu_buffer_funcs sdma_v6_0_buffer_funcs = {
 
 static void sdma_v6_0_set_buffer_funcs(struct amdgpu_device *adev)
 {
-	adev->mman.buffer_funcs = &sdma_v6_0_buffer_funcs;
-	adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
+	amdgpu_sdma_set_buffer_funcs_scheds(adev, &sdma_v6_0_buffer_funcs);
 }
 
 const struct amdgpu_ip_block_version sdma_v6_0_ip_block = {
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
index 9ed817b69a3b..85d98a0e1bff 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
@@ -1299,7 +1299,6 @@ static int sdma_v7_0_early_init(struct amdgpu_ip_block *ip_block)
 	}
 
 	sdma_v7_0_set_ring_funcs(adev);
-	sdma_v7_0_set_buffer_funcs(adev);
 	amdgpu_sdma_set_vm_pte_scheds(adev, &sdma_v7_0_vm_pte_funcs);
 	sdma_v7_0_set_irq_funcs(adev);
 	sdma_v7_0_set_mqd_funcs(adev);
@@ -1432,6 +1431,7 @@ static int sdma_v7_0_hw_init(struct amdgpu_ip_block *ip_block)
 	r = sdma_v7_0_start(adev);
 	if (r)
 		return r;
+	sdma_v7_0_set_buffer_funcs(adev);
 
 	return sdma_v7_0_set_userq_trap_interrupts(adev, true);
 }
@@ -1845,8 +1845,7 @@ static const struct amdgpu_buffer_funcs sdma_v7_0_buffer_funcs = {
 
 static void sdma_v7_0_set_buffer_funcs(struct amdgpu_device *adev)
 {
-	adev->mman.buffer_funcs = &sdma_v7_0_buffer_funcs;
-	adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
+	amdgpu_sdma_set_buffer_funcs_scheds(adev, &sdma_v7_0_buffer_funcs);
 }
 
 const struct amdgpu_ip_block_version sdma_v7_0_ip_block = {
diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c b/drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c
index 061934a2e93a..e1c0a4ff0e7f 100644
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c
@@ -1287,7 +1287,6 @@ static int sdma_v7_1_early_init(struct amdgpu_ip_block *ip_block)
 	}
 
 	sdma_v7_1_set_ring_funcs(adev);
-	sdma_v7_1_set_buffer_funcs(adev);
 	amdgpu_sdma_set_vm_pte_scheds(adev, &sdma_v7_1_vm_pte_funcs);
 	sdma_v7_1_set_irq_funcs(adev);
 	sdma_v7_1_set_mqd_funcs(adev);
@@ -1386,10 +1385,16 @@ static int sdma_v7_1_hw_init(struct amdgpu_ip_block *ip_block)
 {
 	struct amdgpu_device *adev = ip_block->adev;
 	uint32_t inst_mask;
+	int r;
 
 	inst_mask = GENMASK(adev->sdma.num_instances - 1, 0);
 
-	return sdma_v7_1_inst_start(adev, inst_mask);
+	r = sdma_v7_1_inst_start(adev, inst_mask);
+	if (r)
+		return r;
+	sdma_v7_1_set_buffer_funcs(adev);
+
+	return 0;
 }
 
 static int sdma_v7_1_hw_fini(struct amdgpu_ip_block *ip_block)
@@ -1776,8 +1781,7 @@ static const struct amdgpu_buffer_funcs sdma_v7_1_buffer_funcs = {
 
 static void sdma_v7_1_set_buffer_funcs(struct amdgpu_device *adev)
 {
-	adev->mman.buffer_funcs = &sdma_v7_1_buffer_funcs;
-	adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
+	amdgpu_sdma_set_buffer_funcs_scheds(adev, &sdma_v7_1_buffer_funcs);
 }
 
 const struct amdgpu_ip_block_version sdma_v7_1_ip_block = {
diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c b/drivers/gpu/drm/amd/amdgpu/si_dma.c
index 3e58feb2d5e4..549708075eb4 100644
--- a/drivers/gpu/drm/amd/amdgpu/si_dma.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c
@@ -487,7 +487,6 @@ static int si_dma_early_init(struct amdgpu_ip_block *ip_block)
 	adev->sdma.num_instances = SDMA_MAX_INSTANCE;
 
 	si_dma_set_ring_funcs(adev);
-	si_dma_set_buffer_funcs(adev);
 	amdgpu_sdma_set_vm_pte_scheds(adev, &si_dma_vm_pte_funcs);
 	si_dma_set_irq_funcs(adev);
 
@@ -543,8 +542,14 @@ static int si_dma_sw_fini(struct amdgpu_ip_block *ip_block)
 static int si_dma_hw_init(struct amdgpu_ip_block *ip_block)
 {
 	struct amdgpu_device *adev = ip_block->adev;
+	int r;
 
-	return si_dma_start(adev);
+	r = si_dma_start(adev);
+	if (r)
+		return r;
+	si_dma_set_buffer_funcs(adev);
+
+	return 0;
 }
 
 static int si_dma_hw_fini(struct amdgpu_ip_block *ip_block)
@@ -833,8 +838,7 @@ static const struct amdgpu_buffer_funcs si_dma_buffer_funcs = {
 
 static void si_dma_set_buffer_funcs(struct amdgpu_device *adev)
 {
-	adev->mman.buffer_funcs = &si_dma_buffer_funcs;
-	adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
+	amdgpu_sdma_set_buffer_funcs_scheds(adev, &si_dma_buffer_funcs);
 }
 
 const struct amdgpu_ip_block_version si_dma_ip_block =
diff --git a/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c b/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c
index 709b1669b07b..e88bebd928ef 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc_v1_0.c
@@ -330,6 +330,8 @@ static int soc_v1_0_common_early_init(struct amdgpu_ip_block *ip_block)
 		return -EINVAL;
 	}
 
+	adev->nbio.funcs->init_registers(adev);
+
 	return 0;
 }
 
@@ -737,15 +739,8 @@ static int soc_v1_0_switch_partition_mode(struct amdgpu_xcp_mgr *xcp_mgr,
 
 	num_xcc_per_xcp = __soc_v1_0_get_xcc_per_xcp(xcp_mgr, mode);
 	if (adev->gfx.imu.funcs &&
-	    adev->gfx.imu.funcs->switch_compute_partition) {
-		ret = adev->gfx.imu.funcs->switch_compute_partition(xcp_mgr->adev, num_xcc_per_xcp, mode);
-		if (ret)
-			goto out;
-	}
-	if (adev->gfx.imu.funcs &&
-	    adev->gfx.imu.funcs->init_mcm_addr_lut &&
-	    amdgpu_emu_mode)
-		adev->gfx.imu.funcs->init_mcm_addr_lut(adev);
+	    adev->gfx.imu.funcs->switch_compute_partition)
+		adev->gfx.imu.funcs->switch_compute_partition(xcp_mgr->adev, num_xcc_per_xcp, mode);
 
 	/* Init info about new xcps */
 	*num_xcps = num_xcc / num_xcc_per_xcp;
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c b/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c
index fea576a7f397..efb3fde919ee 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v3_1.c
@@ -242,6 +242,10 @@ static void uvd_v3_1_mc_resume(struct amdgpu_device *adev)
 	uint64_t addr;
 	uint32_t size;
 
+	/* When the keyselect is already set, don't perturb it. */
+	if (RREG32(mmUVD_FW_START))
+		return;
+
 	/* program the VCPU memory controller bits 0-27 */
 	addr = (adev->uvd.inst->gpu_addr + AMDGPU_UVD_FIRMWARE_OFFSET) >> 3;
 	size = AMDGPU_UVD_FIRMWARE_SIZE(adev) >> 3;
@@ -284,6 +288,12 @@ static int uvd_v3_1_fw_validate(struct amdgpu_device *adev)
 	int i;
 	uint32_t keysel = adev->uvd.keyselect;
 
+	if (RREG32(mmUVD_FW_START) & UVD_FW_STATUS__PASS_MASK) {
+		dev_dbg(adev->dev, "UVD keyselect already set: 0x%x (on CPU: 0x%x)\n",
+			RREG32(mmUVD_FW_START), adev->uvd.keyselect);
+		return 0;
+	}
+
 	WREG32(mmUVD_FW_START, keysel);
 
 	for (i = 0; i < 10; ++i) {
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
index 55ea5145a28a..f829d65a79b4 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_chardev.c
@@ -25,6 +25,7 @@
 #include <linux/err.h>
 #include <linux/fs.h>
 #include <linux/file.h>
+#include <linux/overflow.h>
 #include <linux/sched.h>
 #include <linux/slab.h>
 #include <linux/uaccess.h>
@@ -1695,6 +1696,16 @@ static int kfd_ioctl_smi_events(struct file *filep,
 	return kfd_smi_event_open(pdd->dev, &args->anon_fd);
 }
 
+static int kfd_ioctl_svm_validate(void *kdata, unsigned int usize)
+{
+	struct kfd_ioctl_svm_args *args = kdata;
+	size_t expected = struct_size(args, attrs, args->nattr);
+
+	if (expected == SIZE_MAX || usize < expected)
+		return -EINVAL;
+	return 0;
+}
+
 #if IS_ENABLED(CONFIG_HSA_AMD_SVM)
 
 static int kfd_ioctl_set_xnack_mode(struct file *filep,
@@ -3209,7 +3220,11 @@ static int kfd_ioctl_create_process(struct file *filep, struct kfd_process *p, v
 
 #define AMDKFD_IOCTL_DEF(ioctl, _func, _flags) \
 	[_IOC_NR(ioctl)] = {.cmd = ioctl, .func = _func, .flags = _flags, \
-			    .cmd_drv = 0, .name = #ioctl}
+			    .validate = NULL, .cmd_drv = 0, .name = #ioctl}
+
+#define AMDKFD_IOCTL_DEF_V(ioctl, _func, _validate, _flags) \
+	[_IOC_NR(ioctl)] = {.cmd = ioctl, .func = _func, .flags = _flags, \
+			    .validate = _validate, .cmd_drv = 0, .name = #ioctl}
 
 /** Ioctl table */
 static const struct amdkfd_ioctl_desc amdkfd_ioctls[] = {
@@ -3306,7 +3321,8 @@ static const struct amdkfd_ioctl_desc amdkfd_ioctls[] = {
 	AMDKFD_IOCTL_DEF(AMDKFD_IOC_SMI_EVENTS,
 			kfd_ioctl_smi_events, 0),
 
-	AMDKFD_IOCTL_DEF(AMDKFD_IOC_SVM, kfd_ioctl_svm, 0),
+	AMDKFD_IOCTL_DEF_V(AMDKFD_IOC_SVM, kfd_ioctl_svm,
+			   kfd_ioctl_svm_validate, 0),
 
 	AMDKFD_IOCTL_DEF(AMDKFD_IOC_SET_XNACK_MODE,
 			kfd_ioctl_set_xnack_mode, 0),
@@ -3431,6 +3447,12 @@ static long kfd_ioctl(struct file *filep, unsigned int cmd, unsigned long arg)
 		memset(kdata, 0, usize);
 	}
 
+	if (ioctl->validate) {
+		retcode = ioctl->validate(kdata, usize);
+		if (retcode)
+			goto err_i1;
+	}
+
 	retcode = func(filep, process, kdata);
 
 	if (cmd & IOC_OUT)
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v12_1.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v12_1.c
index 9e70a5f8a50b..525989371378 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v12_1.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_v12_1.c
@@ -54,6 +54,7 @@ static int update_qpd_v12_1(struct device_queue_manager *dqm,
 	struct kfd_process_device *pdd;
 	struct amdgpu_device *adev = dqm->dev->adev;
 	struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB(0)];
+	bool xnack_enabled;
 
 	pdd = qpd_to_pdd(qpd);
 	qpd->vm_cntx_cntl = hub->vm_cntx_cntl;
@@ -71,16 +72,18 @@ static int update_qpd_v12_1(struct device_queue_manager *dqm,
 		qpd->sh_mem_ape1_base = 0;
 	}
 
-	if (KFD_SUPPORT_XNACK_PER_PROCESS(dqm->dev)) {
-		if (!pdd->process->xnack_enabled) {
-			qpd->sh_mem_config |= 1 << SH_MEM_CONFIG__RETRY_DISABLE__SHIFT;
-			qpd->vm_cntx_cntl &=
+	xnack_enabled = KFD_SUPPORT_XNACK_PER_PROCESS(dqm->dev) ?
+			pdd->process->xnack_enabled :
+			!pdd->dev->kfd->noretry;
+
+	if (!xnack_enabled) {
+		qpd->sh_mem_config |= 1 << SH_MEM_CONFIG__RETRY_DISABLE__SHIFT;
+		qpd->vm_cntx_cntl &=
 			~(1 << GCVM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT);
-		} else {
-			qpd->sh_mem_config &= ~(1 << SH_MEM_CONFIG__RETRY_DISABLE__SHIFT);
-			qpd->vm_cntx_cntl |=
+	} else {
+		qpd->sh_mem_config &= ~(1 << SH_MEM_CONFIG__RETRY_DISABLE__SHIFT);
+		qpd->vm_cntx_cntl |=
 			(1 << GCVM_CONTEXT0_CNTL__RETRY_PERMISSION_OR_INVALID_PAGE_FAULT__SHIFT);
-		}
 	}
 
 	qpd->sh_mem_bases = compute_sh_mem_bases_64bit(pdd);
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
index 964efa325908..28dc6886c1ff 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_migrate.c
@@ -129,13 +129,14 @@ svm_migrate_copy_memory_gart(struct amdgpu_device *adev, dma_addr_t *sys,
 			     struct dma_fence **mfence)
 {
 	const u64 GTT_MAX_PAGES = AMDGPU_GTT_MAX_TRANSFER_SIZE;
-	struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
+	struct amdgpu_ring *ring;
 	struct amdgpu_ttm_buffer_entity *entity;
 	u64 gart_s, gart_d;
 	struct dma_fence *next;
 	u64 size;
 	int r;
 
+	ring = to_amdgpu_ring(adev->mman.buffer_funcs_scheds[0]);
 	entity = &adev->mman.move_entities[0];
 
 	mutex_lock(&entity->lock);
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c
index c90c0d99b1e3..475589b924e9 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_mqd_manager_v12_1.c
@@ -32,6 +32,10 @@
 #include "amdgpu_amdkfd.h"
 #include "kfd_device_queue_manager.h"
 
+static void update_mqd(struct mqd_manager *mm, void *mqd,
+		       struct queue_properties *q,
+		       struct mqd_update_info *minfo);
+
 static inline struct v12_1_compute_mqd *get_mqd(void *mqd)
 {
 	return (struct v12_1_compute_mqd *)mqd;
@@ -215,7 +219,7 @@ static void init_mqd(struct mqd_manager *mm, void **mqd,
 	*mqd = m;
 	if (gart_addr)
 		*gart_addr = addr;
-	mm->update_mqd(mm, m, q, NULL);
+	update_mqd(mm, m, q, NULL);
 }
 
 static int load_mqd(struct mqd_manager *mm, void *mqd,
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
index 6e333bfa17d6..b7cf59b2699e 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_priv.h
@@ -215,8 +215,7 @@ enum cache_policy {
 	((KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 2)) ||	\
 	 (KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 3)) ||	\
 	 (KFD_GC_VERSION(dev) == IP_VERSION(9, 4, 4)) ||	\
-	 (KFD_GC_VERSION(dev) == IP_VERSION(9, 5, 0)) ||	\
-	 (KFD_GC_VERSION(dev) == IP_VERSION(12, 1, 0)))
+	 (KFD_GC_VERSION(dev) == IP_VERSION(9, 5, 0)))
 
 struct kfd_node;
 
@@ -1047,10 +1046,13 @@ extern struct srcu_struct kfd_processes_srcu;
 typedef int amdkfd_ioctl_t(struct file *filep, struct kfd_process *p,
 				void *data);
 
+typedef int amdkfd_ioctl_validate_t(void *kdata, unsigned int usize);
+
 struct amdkfd_ioctl_desc {
 	unsigned int cmd;
 	int flags;
 	amdkfd_ioctl_t *func;
+	amdkfd_ioctl_validate_t *validate;
 	unsigned int cmd_drv;
 	const char *name;
 };
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
index b120fdb0ef77..38085a0a0f58 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_svm.c
@@ -1366,6 +1366,12 @@ svm_range_unmap_from_gpu(struct amdgpu_device *adev, struct amdgpu_vm *vm,
 
 	pr_debug("CPU[0x%llx 0x%llx] -> GPU[0x%llx 0x%llx]\n", start, last,
 		gpu_start, gpu_end);
+
+	if (!amdgpu_vm_ready(vm)) {
+		pr_debug("VM not ready, canceling unmap\n");
+		return -EINVAL;
+	}
+
 	return amdgpu_vm_update_range(adev, vm, false, true, true, false, NULL, gpu_start,
 				      gpu_end, init_pte_value, 0, 0, NULL, NULL,
 				      fence);
@@ -1443,6 +1449,11 @@ svm_range_map_to_gpu(struct kfd_process_device *pdd, struct svm_range *prange,
 	pr_debug("svms 0x%p [0x%lx 0x%lx] readonly %d\n", prange->svms,
 		 last_start, last_start + npages - 1, readonly);
 
+	if (!amdgpu_vm_ready(vm)) {
+		pr_debug("VM not ready, canceling map\n");
+		return -EINVAL;
+	}
+
 	for (i = offset; i < offset + npages; i++) {
 		uint64_t gpu_start;
 		uint64_t gpu_end;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index e96a12ff2d31..8d690468de02 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -104,6 +104,7 @@
 #include "ivsrcid/dcn/irqsrcs_dcn_1_0.h"
 
 #include "modules/inc/mod_freesync.h"
+#include "modules/inc/mod_power.h"
 #include "modules/power/power_helpers.h"
 
 static_assert(AMDGPU_DMUB_NOTIFICATION_MAX == DMUB_NOTIFICATION_MAX, "AMDGPU_DMUB_NOTIFICATION_MAX mismatch");
@@ -1881,6 +1882,70 @@ static enum dmub_ips_disable_type dm_get_default_ips_mode(
 	return ret;
 }
 
+static int amdgpu_dm_init_power_module(struct amdgpu_display_manager *dm)
+{
+	struct mod_power_init_params init_data[MAX_NUM_EDP];
+
+	if (dm->num_of_edps == 0) {
+		drm_dbg_driver(
+			dm->ddev,
+			"amdgpu: No eDP detected, skip initializing power module\n");
+		return 0;
+	}
+
+	/* Initialize all the power module parameters */
+	for (int i = 0; i < dm->num_of_edps; i++) {
+		init_data[i].allow_psr_smu_optimizations =
+			!!(amdgpu_dc_feature_mask & DC_PSR_ALLOW_SMU_OPT);
+		init_data[i].allow_psr_multi_disp_optimizations =
+			!!(amdgpu_dc_feature_mask & DC_PSR_ALLOW_MULTI_DISP_OPT);
+		/* See dm_late_init */
+		init_data[i].backlight_ramping_override = false;
+		init_data[i].backlight_ramping_start = 0xCCCC;
+		init_data[i].backlight_ramping_reduction = 0xCCCCCCCC;
+		init_data[i].def_varibright_level = 0;
+		init_data[i].abm_config_setting = 0;
+		init_data[i].num_backlight_levels = 101;
+		init_data[i].use_nits_based_brightness = false;
+		init_data[i].panel_max_millinits = 0;
+		init_data[i].panel_min_millinits = 0;
+		init_data[i].disable_fractional_pwm =
+			!(amdgpu_dc_feature_mask & DC_DISABLE_FRACTIONAL_PWM_MASK);
+		init_data[i].use_custom_backlight_caps = false;
+		init_data[i].custom_backlight_caps_config_no = 0;
+		init_data[i].use_linear_backlight_curve = false;
+		init_data[i].def_varibright_enable = 0;
+		init_data[i].varibright_level = 0;
+		/*
+		 * Power module uses 16-bit backlight levels (0xFFFF max) rather
+		 * than 8-bit(0XFF max)
+		 */
+		init_data[i].min_backlight_pwm =
+			dm->backlight_caps[i].min_input_signal * 0x101;
+		init_data[i].max_backlight_pwm =
+			dm->backlight_caps[i].max_input_signal * 0x101;
+		init_data[i].min_abm_backlight =
+			dm->backlight_caps[i].min_input_signal * 0x101;
+
+		/* Min backlight level after ABM reduction,  Don't allow below 1%
+		 * 0xFFFF x 0.01 = 0x28F
+		 */
+		init_data[i].min_abm_backlight = (init_data[i].min_abm_backlight < 0x28F) ?
+			0x28F : init_data[i].min_abm_backlight;
+	}
+
+	dm->power_module = mod_power_create(dm->dc, init_data, dm->num_of_edps);
+	if (!dm->power_module) {
+		drm_err(dm->ddev, "amdgpu: Error allocating memory for power module\n");
+		return -ENOMEM;
+	}
+
+	mod_power_hw_init(dm->power_module);
+	drm_dbg_driver(dm->ddev, "amdgpu: Power module init done\n");
+
+	return 0;
+}
+
 static int amdgpu_dm_init(struct amdgpu_device *adev)
 {
 	struct dc_init_data init_data;
@@ -1898,6 +1963,8 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
 	mutex_init(&adev->dm.dc_lock);
 	mutex_init(&adev->dm.audio_lock);
 
+	spin_lock_init(&adev->dm.dmub_lock);
+
 	if (amdgpu_dm_irq_init(adev)) {
 		drm_err(adev_to_drm(adev), "failed to initialize DM IRQ support.\n");
 		goto error;
@@ -2194,6 +2261,9 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
 		goto error;
 	}
 
+	if (amdgpu_dm_init_power_module(&adev->dm))
+		goto error;
+
 	/* create fake encoders for MST */
 	dm_dp_create_fake_mst_encoders(adev);
 
@@ -2330,6 +2400,10 @@ static void amdgpu_dm_fini(struct amdgpu_device *adev)
 		adev->dm.freesync_module = NULL;
 	}
 
+	if (adev->dm.power_module) {
+		mod_power_destroy(adev->dm.power_module);
+		adev->dm.power_module = NULL;
+	}
 	mutex_destroy(&adev->dm.audio_lock);
 	mutex_destroy(&adev->dm.dc_lock);
 	mutex_destroy(&adev->dm.dpia_aux_lock);
@@ -5050,8 +5124,8 @@ static int amdgpu_dm_mode_config_init(struct amdgpu_device *adev)
 #define AMDGPU_DM_MIN_SPREAD ((AMDGPU_DM_DEFAULT_MAX_BACKLIGHT - AMDGPU_DM_DEFAULT_MIN_BACKLIGHT) / 2)
 #define AUX_BL_DEFAULT_TRANSITION_TIME_MS 50
 
-static void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm,
-					    int bl_idx)
+void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm,
+				     int bl_idx)
 {
 	struct amdgpu_dm_backlight_caps *caps = &dm->backlight_caps[bl_idx];
 
@@ -5213,15 +5287,34 @@ static u32 convert_brightness_to_user(const struct amdgpu_dm_backlight_caps *cap
 				 max - min);
 }
 
+static struct dc_stream_state *dm_find_stream_with_link(
+	struct amdgpu_display_manager *dm,
+	struct dc_link *link)
+{
+	struct dc_state *cur_dc_state = dm->dc->current_state;
+	struct dc_stream_state *stream = NULL;
+	int i;
+
+	for (i = 0; i < cur_dc_state->stream_count; i++) {
+		stream = cur_dc_state->streams[i];
+		if (stream->link == link)
+			return stream;
+	}
+
+	return NULL;
+}
+
 static void amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm,
 					 int bl_idx,
 					 u32 user_brightness)
 {
 	struct amdgpu_dm_backlight_caps *caps;
 	struct dc_link *link;
-	u32 brightness;
-	bool rc, reallow_idle = false;
+	u32 brightness = 0;
+	bool rc = false, reallow_idle = false;
 	struct drm_connector *connector;
+	struct dc_stream_state *stream;
+	unsigned int min, max;
 
 	list_for_each_entry(connector, &dm->ddev->mode_config.connector_list, head) {
 		struct amdgpu_dm_connector *aconnector = to_amdgpu_dm_connector(connector);
@@ -5251,13 +5344,6 @@ static void amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm,
 	if (caps->brightness_mask)
 		brightness |= caps->brightness_mask;
 
-	/* Change brightness based on AUX property */
-	mutex_lock(&dm->dc_lock);
-	if (dm->dc->caps.ips_support && dm->dc->ctx->dmub_srv->idle_allowed) {
-		dc_allow_idle_optimizations(dm->dc, false);
-		reallow_idle = true;
-	}
-
 	if (trace_amdgpu_dm_brightness_enabled()) {
 		trace_amdgpu_dm_brightness(__builtin_return_address(0),
 					   user_brightness,
@@ -5266,22 +5352,45 @@ static void amdgpu_dm_backlight_set_level(struct amdgpu_display_manager *dm,
 					   power_supply_is_system_supplied() > 0);
 	}
 
-	if (caps->aux_support) {
-		rc = dc_link_set_backlight_level_nits(link, true, brightness,
-						      AUX_BL_DEFAULT_TRANSITION_TIME_MS);
-		if (!rc)
-			DRM_DEBUG("DM: Failed to update backlight via AUX on eDP[%d]\n", bl_idx);
-	} else {
-		struct set_backlight_level_params backlight_level_params = { 0 };
+	stream = dm_find_stream_with_link(dm, link);
+	if (!stream)
+		return;
 
-		backlight_level_params.backlight_pwm_u16_16 = brightness;
-		backlight_level_params.transition_time_in_ms = 0;
+	mutex_lock(&dm->dc_lock);
+	if (dm->dc->caps.ips_support && dm->dc->ctx->dmub_srv->idle_allowed) {
+		dc_allow_idle_optimizations(dm->dc, false);
+		reallow_idle = true;
+	}
 
-		rc = dc_link_set_backlight_level(link, &backlight_level_params);
-		if (!rc)
-			DRM_DEBUG("DM: Failed to update backlight on eDP[%d]\n", bl_idx);
+	if (caps->aux_support) {
+		rc = mod_power_set_backlight_nits(dm->power_module, stream, brightness,
+			AUX_BL_DEFAULT_TRANSITION_TIME_MS, false, true);
+	} else {
+		/* power module uses millipercent */
+		get_brightness_range(caps, &min, &max);
+		brightness = DIV_ROUND_CLOSEST(brightness * 100, (max - min)) * 1000;
+		rc = mod_power_set_backlight_percent(dm->power_module, stream,
+						     brightness, 0, false);
 	}
 
+	/*
+	 * Some kms clients create a ramped backlight transition effect
+	 * by rapidly changing the backlight. Yet we must wait on dmcub
+	 * fw to exit psr/replay before programming backlight. To
+	 * prevent lag, keep disable psr/replay and let the next atomic
+	 * flip clear the event.
+	 *
+	 * ToDo: use ISM to handle rapidly backlight change
+	 *
+	 * Rapidly backlight change is similar to rapidly cursor events,
+	 * which is now handled by ISM. ISM can delay the event until system
+	 * is really idle, so we may use ISM to handle backlight change as well.
+	 */
+	amdgpu_dm_psr_set_event(dm, stream, true,
+		psr_event_hw_programming, true);
+	amdgpu_dm_replay_set_event(dm, stream, true,
+		replay_event_hw_programming, true);
+
 	if (dm->dc->caps.ips_support && reallow_idle)
 		dc_allow_idle_optimizations(dm->dc, true);
 
@@ -5499,6 +5608,8 @@ static void setup_backlight_device(struct amdgpu_display_manager *dm,
 
 static void amdgpu_set_panel_orientation(struct drm_connector *connector);
 
+
+
 /*
  * In this architecture, the association
  * connector -> encoder -> crtc
@@ -5740,7 +5851,7 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
 						psr_feature_enabled = false;
 
 				if (psr_feature_enabled) {
-					amdgpu_dm_set_psr_caps(link);
+					amdgpu_dm_set_psr_caps(link, aconnector);
 					drm_info(adev_to_drm(adev), "%s: PSR support %d, DC PSR ver %d, sink PSR ver %d DPCD caps 0x%x su_y_granularity %d\n",
 						 aconnector->base.name,
 						 link->psr_settings.psr_feature_enabled,
@@ -9792,7 +9903,8 @@ static void update_stream_irq_parameters(
 	spin_unlock_irqrestore(&adev_to_drm(adev)->event_lock, flags);
 }
 
-static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state,
+static void amdgpu_dm_handle_vrr_transition(struct amdgpu_display_manager *dm,
+					    struct dm_crtc_state *old_state,
 					    struct dm_crtc_state *new_state)
 {
 	bool old_vrr_active = amdgpu_dm_crtc_vrr_active(old_state);
@@ -9811,6 +9923,13 @@ static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state,
 		WARN_ON(drm_crtc_vblank_get(new_state->base.crtc) != 0);
 		drm_dbg_driver(new_state->base.crtc->dev, "%s: crtc=%u VRR off->on: Get vblank ref\n",
 				 __func__, new_state->base.crtc->base.id);
+
+		scoped_guard(mutex, &dm->dc_lock) {
+			amdgpu_dm_psr_set_event(dm, new_state->stream, true,
+				psr_event_vrr_transition, true);
+			amdgpu_dm_replay_set_event(dm, new_state->stream, true,
+				replay_event_vrr, true);
+		}
 	} else if (old_vrr_active && !new_vrr_active) {
 		/* Transition VRR active -> inactive:
 		 * Allow vblank irq disable again for fixed refresh rate.
@@ -9819,6 +9938,13 @@ static void amdgpu_dm_handle_vrr_transition(struct dm_crtc_state *old_state,
 		drm_crtc_vblank_put(new_state->base.crtc);
 		drm_dbg_driver(new_state->base.crtc->dev, "%s: crtc=%u VRR on->off: Drop vblank ref\n",
 				 __func__, new_state->base.crtc->base.id);
+
+		scoped_guard(mutex, &dm->dc_lock) {
+			amdgpu_dm_psr_set_event(dm, new_state->stream, false,
+				psr_event_vrr_transition, false);
+			amdgpu_dm_replay_set_event(dm, new_state->stream, false,
+				replay_event_vrr, false);
+		}
 	}
 }
 
@@ -9916,7 +10042,8 @@ static void amdgpu_dm_update_cursor(struct drm_plane *plane,
 	}
 }
 
-static void amdgpu_dm_enable_self_refresh(struct amdgpu_crtc *acrtc_attach,
+static void amdgpu_dm_enable_self_refresh(struct amdgpu_display_manager *dm,
+					  struct amdgpu_crtc *acrtc_attach,
 					  const struct dm_crtc_state *acrtc_state,
 					  const u64 current_ts)
 {
@@ -9924,20 +10051,10 @@ static void amdgpu_dm_enable_self_refresh(struct amdgpu_crtc *acrtc_attach,
 	struct replay_settings *pr = &acrtc_state->stream->link->replay_settings;
 	struct amdgpu_dm_connector *aconn =
 		(struct amdgpu_dm_connector *)acrtc_state->stream->dm_stream_context;
-	bool vrr_active = amdgpu_dm_crtc_vrr_active(acrtc_state);
-
-	if (acrtc_state->update_type > UPDATE_TYPE_FAST) {
-		if (pr->config.replay_supported && !pr->replay_feature_enabled)
-			amdgpu_dm_link_setup_replay(acrtc_state->stream->link, aconn);
-		else if (psr->psr_version != DC_PSR_VERSION_UNSUPPORTED &&
-			     !psr->psr_feature_enabled)
-			if (!aconn->disallow_edp_enter_psr)
-				amdgpu_dm_link_setup_psr(acrtc_state->stream);
-	}
 
 	/* Decrement skip count when SR is enabled and we're doing fast updates. */
 	if (acrtc_state->update_type == UPDATE_TYPE_FAST &&
-	    (psr->psr_feature_enabled || pr->config.replay_supported)) {
+	    (psr->psr_feature_enabled || pr->replay_feature_enabled)) {
 		if (aconn->sr_skip_count > 0)
 			aconn->sr_skip_count--;
 
@@ -9952,17 +10069,15 @@ static void amdgpu_dm_enable_self_refresh(struct amdgpu_crtc *acrtc_attach,
 		 * of update events.
 		 * See `amdgpu_dm_crtc_vblank_control_worker()`.
 		 */
-		if (!vrr_active &&
-		    acrtc_attach->dm_irq_params.allow_sr_entry &&
-#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
-		    !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) &&
-#endif
-		    (current_ts - psr->psr_dirty_rects_change_timestamp_ns) > 500000000) {
-			if (pr->replay_feature_enabled && !pr->replay_allow_active)
-				amdgpu_dm_replay_enable(acrtc_state->stream, true);
-			if (psr->psr_version == DC_PSR_VERSION_SU_1 &&
-			    !psr->psr_allow_active && !aconn->disallow_edp_enter_psr)
-				amdgpu_dm_psr_enable(acrtc_state->stream);
+		if (acrtc_attach->dm_irq_params.allow_sr_entry &&
+			(current_ts - psr->psr_dirty_rects_change_timestamp_ns) > 500000000) {
+			amdgpu_dm_psr_set_event(dm, acrtc_state->stream, false,
+				psr_event_hw_programming, false);
+
+			amdgpu_dm_replay_set_event(dm, acrtc_state->stream, true,
+				replay_event_general_ui, true);
+			amdgpu_dm_replay_set_event(dm, acrtc_state->stream, false,
+				replay_event_hw_programming, false);
 		}
 	} else {
 		acrtc_attach->dm_irq_params.allow_sr_entry = false;
@@ -10124,15 +10239,12 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
 			 */
 			if (acrtc_state->stream->link->psr_settings.psr_version >= DC_PSR_VERSION_SU_1 &&
 			    acrtc_attach->dm_irq_params.allow_sr_entry &&
-#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
-			    !amdgpu_dm_crc_window_is_activated(acrtc_state->base.crtc) &&
-#endif
 			    dirty_rects_changed) {
 				mutex_lock(&dm->dc_lock);
 				acrtc_state->stream->link->psr_settings.psr_dirty_rects_change_timestamp_ns =
 				timestamp_ns;
-				if (acrtc_state->stream->link->psr_settings.psr_allow_active)
-					amdgpu_dm_psr_disable(acrtc_state->stream, true);
+				amdgpu_dm_psr_set_event(dm, acrtc_state->stream, true,
+					psr_event_hw_programming, true);
 				mutex_unlock(&dm->dc_lock);
 			}
 		}
@@ -10297,15 +10409,6 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
 		if (acrtc_state->abm_level != dm_old_crtc_state->abm_level)
 			bundle->stream_update.abm_level = &acrtc_state->abm_level;
 
-		mutex_lock(&dm->dc_lock);
-		if ((acrtc_state->update_type > UPDATE_TYPE_FAST) || vrr_active) {
-			if (acrtc_state->stream->link->replay_settings.replay_allow_active)
-				amdgpu_dm_replay_disable(acrtc_state->stream);
-			if (acrtc_state->stream->link->psr_settings.psr_allow_active)
-				amdgpu_dm_psr_disable(acrtc_state->stream, true);
-		}
-		mutex_unlock(&dm->dc_lock);
-
 		/*
 		 * If FreeSync state on the stream has changed then we need to
 		 * re-adjust the min/max bounds now that DC doesn't handle this
@@ -10343,8 +10446,8 @@ static void amdgpu_dm_commit_planes(struct drm_atomic_state *state,
 		if (dm_old_crtc_state->active_planes != acrtc_state->active_planes)
 			dm_update_pflip_irq_state(drm_to_adev(dev),
 						  acrtc_attach);
-
-		amdgpu_dm_enable_self_refresh(acrtc_attach, acrtc_state, timestamp_ns);
+		amdgpu_dm_enable_self_refresh(dm, acrtc_attach, acrtc_state,
+					      timestamp_ns);
 		mutex_unlock(&dm->dc_lock);
 	}
 
@@ -10463,6 +10566,102 @@ static void dm_clear_writeback(struct amdgpu_display_manager *dm,
 	dc_stream_remove_writeback(dm->dc, crtc_state->stream, 0);
 }
 
+/**
+ * amdgpu_dm_mod_power_update_streams - update mod_power stream state on modeset
+ * @state: the drm atomic state
+ * @dm: the display manager to update mod_power on
+ *
+ * Notify mod_power of stream changes on modeset events, and disable PSR/Replay
+ * in preparation for hardware programming. See also
+ * amdgpu_dm_mod_power_setup_streams() for post-modeset mod_power setup.
+ */
+static void amdgpu_dm_mod_power_update_streams(struct drm_atomic_state *state,
+					       struct amdgpu_display_manager *dm)
+{
+	struct dm_crtc_state *dm_old_crtc_state, *dm_new_crtc_state;
+	struct drm_crtc_state *old_crtc_state, *new_crtc_state;
+	struct amdgpu_dm_connector *aconnector;
+	struct drm_crtc *crtc;
+	int i = 0;
+
+	for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
+		dm_old_crtc_state = to_dm_crtc_state(old_crtc_state);
+		dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
+
+		if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
+			continue;
+
+		/*
+		 * Update mod_power on modeset event in preparation for hw
+		 * programming. Always use the old stream, since it would have
+		 * been previously added to mod_power. If old stream is null (on
+		 * crtc enable, for example), mod_power will no-op, which is the
+		 * desried behavior.
+		 */
+		if (old_crtc_state->active) {
+			scoped_guard(mutex, &dm->dc_lock) {
+				amdgpu_dm_psr_set_event(dm, dm_old_crtc_state->stream, true,
+					psr_event_hw_programming, true);
+				amdgpu_dm_replay_set_event(dm, dm_old_crtc_state->stream, true,
+					replay_event_hw_programming, true);
+			}
+		}
+
+		if (new_crtc_state->active) {
+			aconnector = (struct amdgpu_dm_connector *)
+				dm_new_crtc_state->stream->dm_stream_context;
+			if (old_crtc_state->active) {
+				mod_power_replace_stream(dm->power_module,
+					dm_old_crtc_state->stream,
+					dm_new_crtc_state->stream,
+					&aconnector->psr_caps);
+			} else {
+				mod_power_add_stream(dm->power_module,
+					dm_new_crtc_state->stream,
+					&aconnector->psr_caps);
+			}
+		} else if (old_crtc_state->active) {
+			mod_power_remove_stream(dm->power_module,
+				dm_old_crtc_state->stream);
+		}
+	}
+}
+
+/**
+ * amdgpu_dm_mod_power_setup_streams - setup mod_power stream state post modeset
+ * @state: the drm atomic state
+ * @dm: the display manager to update mod_power on
+ *
+ * Notify mod_power of mode_change. This needs to be done after dc_stream
+ * updates have been committed, and VRR parameters have been updated.
+ */
+static void amdgpu_dm_mod_power_setup_streams(struct drm_atomic_state *state,
+					      struct amdgpu_display_manager *dm)
+{
+	struct dm_crtc_state *dm_new_crtc_state;
+	struct drm_crtc_state *new_crtc_state;
+	struct amdgpu_crtc *acrtc;
+	struct drm_crtc *crtc;
+	int i = 0;
+
+	for_each_new_crtc_in_state(state, crtc, new_crtc_state, i) {
+		dm_new_crtc_state = to_dm_crtc_state(new_crtc_state);
+		acrtc = to_amdgpu_crtc(crtc);
+
+		if (!drm_atomic_crtc_needs_modeset(new_crtc_state))
+			continue;
+
+		if (new_crtc_state->active) {
+			amdgpu_dm_link_setup_replay(dm_new_crtc_state->stream,
+					&acrtc->dm_irq_params.vrr_params);
+			mod_power_notify_mode_change(dm->power_module,
+						dm_new_crtc_state->stream,
+						false);
+		}
+	}
+
+}
+
 static void amdgpu_dm_commit_streams(struct drm_atomic_state *state,
 					struct dc_state *dc_state)
 {
@@ -10506,6 +10705,8 @@ static void amdgpu_dm_commit_streams(struct drm_atomic_state *state,
 		acrtc->wb_enabled = false;
 	}
 
+	amdgpu_dm_mod_power_update_streams(state, dm);
+
 	for_each_oldnew_crtc_in_state(state, crtc, old_crtc_state,
 				      new_crtc_state, i) {
 		struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
@@ -10610,13 +10811,10 @@ static void amdgpu_dm_commit_streams(struct drm_atomic_state *state,
 		}
 	} /* for_each_crtc_in_state() */
 
-	/* if there mode set or reset, disable eDP PSR, Replay */
+	/* if there mode set or reset, flush vblank work queue */
 	if (mode_set_reset_required) {
 		if (dm->vblank_control_workqueue)
 			flush_workqueue(dm->vblank_control_workqueue);
-
-		amdgpu_dm_replay_disable_all(dm);
-		amdgpu_dm_psr_disable_all(dm);
 	}
 
 	dm_enable_per_frame_crtc_master_sync(dc_state);
@@ -11089,7 +11287,7 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
 			manage_dm_interrupts(adev, acrtc, dm_new_crtc_state);
 		}
 		/* Handle vrr on->off / off->on transitions */
-		amdgpu_dm_handle_vrr_transition(dm_old_crtc_state, dm_new_crtc_state);
+		amdgpu_dm_handle_vrr_transition(dm, dm_old_crtc_state, dm_new_crtc_state);
 
 #ifdef CONFIG_DEBUG_FS
 		if (new_crtc_state->active &&
@@ -11127,6 +11325,8 @@ static void amdgpu_dm_atomic_commit_tail(struct drm_atomic_state *state)
 #endif
 	}
 
+	amdgpu_dm_mod_power_setup_streams(state, dm);
+
 	for_each_new_crtc_in_state(state, crtc, new_crtc_state, j)
 		if (new_crtc_state->async_flip)
 			wait_for_vblank = false;
@@ -13685,11 +13885,17 @@ int amdgpu_dm_process_dmub_set_config_sync(
 
 bool dm_execute_dmub_cmd(const struct dc_context *ctx, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type)
 {
+	struct amdgpu_device *adev = ctx->driver_context;
+
+	guard(spinlock_irqsave)(&adev->dm.dmub_lock);
 	return dc_dmub_srv_cmd_run(ctx->dmub_srv, cmd, wait_type);
 }
 
 bool dm_execute_dmub_cmd_list(const struct dc_context *ctx, unsigned int count, union dmub_rb_cmd *cmd, enum dm_dmub_wait_type wait_type)
 {
+	struct amdgpu_device *adev = ctx->driver_context;
+
+	guard(spinlock_irqsave)(&adev->dm.dmub_lock);
 	return dc_dmub_srv_cmd_run_list(ctx->dmub_srv, count, cmd, wait_type);
 }
 
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
index 74a8fe1a1999..1e0ccf58cdb8 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
@@ -463,6 +463,13 @@ struct amdgpu_display_manager {
 	 */
 	struct mutex dc_lock;
 
+	/**
+	 * @dmub_lock:
+	 *
+	 * Guards access to DMUB command submission.
+	 */
+	spinlock_t dmub_lock;
+
 	/**
 	 * @audio_lock:
 	 *
@@ -568,6 +575,7 @@ struct amdgpu_display_manager {
 	struct amdgpu_dm_backlight_caps backlight_caps[AMDGPU_DM_MAX_NUM_EDP];
 
 	struct mod_freesync *freesync_module;
+	struct mod_power *power_module;
 	struct hdcp_workqueue *hdcp_workqueue;
 
 	/**
@@ -835,6 +843,7 @@ struct amdgpu_dm_connector {
 	bool force_yuv420_output;
 	bool force_yuv422_output;
 	struct dsc_preferred_settings dsc_settings;
+	struct psr_caps psr_caps;
 	union dp_downstream_port_present mst_downstream_port_present;
 	/* Cached display modes */
 	struct drm_display_mode freesync_vid_base;
@@ -1149,4 +1158,5 @@ int amdgpu_dm_initialize_hdmi_connector(struct amdgpu_dm_connector *aconnector);
 
 void retrieve_dmi_info(struct amdgpu_display_manager *dm);
 
+void amdgpu_dm_update_backlight_caps(struct amdgpu_display_manager *dm, int bl_idx);
 #endif /* __AMDGPU_DM_H__ */
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
index 62573173e2ac..4155984201c6 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c
@@ -503,7 +503,6 @@ int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc *crtc,
 {
 	struct amdgpu_device *adev = drm_to_adev(crtc->dev);
 	struct dc_stream_state *stream_state = dm_crtc_state->stream;
-	struct amdgpu_dm_connector *aconnector = NULL;
 	bool enable = amdgpu_dm_is_valid_crc_source(source);
 	int ret = 0;
 	enum crc_poly_mode crc_poly_mode = CRC_POLY_MODE_16;
@@ -512,21 +511,17 @@ int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc *crtc,
 	if (!stream_state)
 		return -EINVAL;
 
-	/* Get connector from stream */
-	aconnector = (struct amdgpu_dm_connector *)stream_state->dm_stream_context;
-
 	mutex_lock(&adev->dm.dc_lock);
 
-
+	/* Notify power module about CRC window active to disable PSR/Replay
+	 * Power module will check caps internally and skip if not supported
+	 */
 	if (enable) {
-		/* For PSR1, check that the panel has exited PSR */
-		if (stream_state->link->psr_settings.psr_version < DC_PSR_VERSION_SU_1)
-			amdgpu_dm_psr_wait_disable(stream_state);
+		amdgpu_dm_psr_set_event(&adev->dm, stream_state, true,
+			psr_event_crc_window_active, true);
 
-		/* Set flag to disallow enter replay when CRC source is enabled */
-		if (aconnector)
-			aconnector->disallow_edp_enter_replay = true;
-		amdgpu_dm_replay_disable(stream_state);
+		amdgpu_dm_replay_set_event(&adev->dm, stream_state, true,
+			replay_event_crc_window_active, true);
 	}
 
 	/* CRC polynomial selection only support for DCN3.6+ except DCN4.0.1 */
@@ -559,11 +554,15 @@ int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc *crtc,
 	}
 
 	if (!enable) {
-		/* Clear flag to allow enter replay when CRC source is disabled */
-		if (aconnector)
-			aconnector->disallow_edp_enter_replay = false;
-	}
+		/* Notify power module about CRC window inactive to re-enable PSR/Replay
+		 * Power module will check caps internally and skip if not supported
+		 */
+		amdgpu_dm_psr_set_event(&adev->dm, stream_state, false,
+			psr_event_crc_window_active, false);
 
+		amdgpu_dm_replay_set_event(&adev->dm, stream_state, false,
+			replay_event_crc_window_active, false);
+	}
 unlock:
 	mutex_unlock(&adev->dm.dc_lock);
 
@@ -760,10 +759,13 @@ void amdgpu_dm_crtc_handle_crc_irq(struct drm_crtc *crtc)
 	uint32_t crcs[3];
 	unsigned long flags;
 
-	if (crtc == NULL)
+	if (!crtc || !crtc->state || !crtc->dev)
 		return;
 
 	crtc_state = to_dm_crtc_state(crtc->state);
+	if (!crtc_state->stream)
+		return;
+
 	stream_state = crtc_state->stream;
 	acrtc = to_amdgpu_crtc(crtc);
 	drm_dev = crtc->dev;
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
index d69f5a75b685..90a9e27e9d54 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c
@@ -34,6 +34,7 @@
 #include "amdgpu_dm_plane.h"
 #include "amdgpu_dm_trace.h"
 #include "amdgpu_dm_debugfs.h"
+#include "modules/inc/mod_power.h"
 
 #define HPD_DETECTION_PERIOD_uS 2000000
 #define HPD_DETECTION_TIME_uS 100000
@@ -100,68 +101,33 @@ bool amdgpu_dm_crtc_vrr_active(const struct dm_crtc_state *dm_state)
 }
 
 /**
- * amdgpu_dm_crtc_set_panel_sr_feature() - Manage panel self-refresh features.
- * @dm: amdgpu display manager instance.
- * @acrtc: CRTC whose panel self-refresh state is being updated.
- * @stream: DC stream associated with @acrtc.
- * @vblank_enabled: Whether the DRM vblank counter is currently enabled.
- * @allow_sr_entry: Whether entry into self-refresh mode is allowed.
+ * amdgpu_dm_crtc_set_static_screen_optimze() - Toggle static screen optimizations.
  *
- * The DRM vblank counter enable/disable action is used as the trigger to enable
- * or disable various panel self-refresh features:
+ * @dm: display manager
+ * @stream: DC stream state
+ * @sso_enable: desired static screen optimization state
+ * @allow_sr_entry: whether entry into self-refresh mode is allowed
  *
- * Panel Replay and PSR SU
- * - Enable when:
- *   - VRR is disabled
- *   - vblank counter is disabled
- *   - entry is allowed: usermode demonstrates an adequate number of fast
- *     commits
- *   - CRC capture window isn't active
- * - Keep enabled even when vblank counter gets enabled
- *
- * PSR1
- * - Enable condition same as above
- * - Disable when vblank counter is enabled
+ * This function uses the static-screen optimization state as the trigger to
+ * set/clear the Replay and PSR vsync-related events.
  */
-void amdgpu_dm_crtc_set_panel_sr_feature(
+void amdgpu_dm_crtc_set_static_screen_optimze(
 	struct amdgpu_display_manager *dm,
-	struct amdgpu_crtc *acrtc,
 	struct dc_stream_state *stream,
-	bool vblank_enabled, bool allow_sr_entry)
+	bool sso_enable, bool allow_sr_entry)
 {
 	struct dc_link *link = stream->link;
-	bool is_sr_active = (link->replay_settings.replay_allow_active ||
-				 link->psr_settings.psr_allow_active);
-	bool is_crc_window_active = false;
-	bool vrr_active = amdgpu_dm_crtc_vrr_active_irq(acrtc);
-
-#ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
-	is_crc_window_active =
-		amdgpu_dm_crc_window_is_activated(&acrtc->base);
-#endif
+	bool set_vsync_event = !sso_enable;
 
-	if (link->replay_settings.replay_feature_enabled && !vrr_active &&
-		allow_sr_entry && !is_sr_active && !is_crc_window_active) {
-		amdgpu_dm_replay_enable(stream, true);
-	} else if (vblank_enabled) {
-		if (link->psr_settings.psr_version < DC_PSR_VERSION_SU_1 && is_sr_active)
-			amdgpu_dm_psr_disable(stream, false);
-	} else if (link->psr_settings.psr_feature_enabled && !vrr_active &&
-		allow_sr_entry && !is_sr_active && !is_crc_window_active) {
-
-		struct amdgpu_dm_connector *aconn =
-			(struct amdgpu_dm_connector *) stream->dm_stream_context;
-
-		if (!aconn->disallow_edp_enter_psr) {
-			amdgpu_dm_psr_enable(stream);
-			if (dm->idle_workqueue &&
-			    (dm->dc->config.disable_ips == DMUB_IPS_ENABLE) &&
-			    dm->dc->idle_optimizations_allowed &&
-			    dm->idle_workqueue->enable &&
-			    !dm->idle_workqueue->running)
-				schedule_work(&dm->idle_workqueue->work);
-		}
-	}
+	if (!allow_sr_entry)
+		return;
+
+	amdgpu_dm_replay_set_event(dm, stream,
+		set_vsync_event, replay_event_vsync, set_vsync_event);
+
+	if (link->psr_settings.psr_version < DC_PSR_VERSION_SU_1)
+		amdgpu_dm_psr_set_event(dm, stream,
+			set_vsync_event, psr_event_vsync, set_vsync_event);
 }
 
 bool amdgpu_dm_is_headless(struct amdgpu_device *adev)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.h
index 3a8094013a5d..e9fb52f0e66d 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.h
@@ -27,11 +27,10 @@
 #ifndef __AMDGPU_DM_CRTC_H__
 #define __AMDGPU_DM_CRTC_H__
 
-void amdgpu_dm_crtc_set_panel_sr_feature(
+void amdgpu_dm_crtc_set_static_screen_optimze(
 	struct amdgpu_display_manager *dm,
-	struct amdgpu_crtc *acrtc,
 	struct dc_stream_state *stream,
-	bool vblank_enabled, bool allow_sr_entry);
+	bool sso_enable, bool allow_sr_entry);
 
 void amdgpu_dm_crtc_handle_vblank(struct amdgpu_crtc *acrtc);
 
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
index 2409ac72b166..011ae1980f80 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
@@ -33,6 +33,7 @@
 #include "amdgpu_dm.h"
 #include "amdgpu_dm_debugfs.h"
 #include "amdgpu_dm_replay.h"
+#include "amdgpu_dm_psr.h"
 #include "dm_helpers.h"
 #include "dmub/dmub_srv.h"
 #include "resource.h"
@@ -3300,11 +3301,26 @@ static int disallow_edp_enter_psr_get(void *data, u64 *val)
 static int disallow_edp_enter_psr_set(void *data, u64 val)
 {
 	struct amdgpu_dm_connector *aconnector = data;
+	struct dc_link *link = aconnector->dc_link;
+
+	aconnector->disallow_edp_enter_psr = (val != 0);
 
-	aconnector->disallow_edp_enter_psr = val ? true : false;
+	/* eDP PSR enable / disable is happened during mode change in power module.
+	 * Only psr_settings.psr_version is used to decide whether PSR is enabled or not.
+	 * So here we only update psr_version based on debugfs setting.
+	 * If disallow_edp_enter_psr is true, set psr_version to unsupported;
+	 * if disallow_edp_enter_psr is false, set psr_version based on sink capability.
+	 */
+	if (aconnector->disallow_edp_enter_psr)
+		link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED;
+	else if (aconnector->psr_caps.psr_version == 1)
+		link->psr_settings.psr_version = DC_PSR_VERSION_1;
+	else if (aconnector->psr_caps.psr_version == 2)
+		link->psr_settings.psr_version = DC_PSR_VERSION_SU_1;
 	return 0;
 }
 
+
 /* check if kernel disallow eDP enter replay state
  * cat /sys/kernel/debug/dri/0/eDP-X/disallow_edp_enter_replay
  * 0: allow edp enter replay; 1: disallow
@@ -3346,11 +3362,27 @@ static int disallow_edp_enter_replay_get(void *data, u64 *val)
 static int disallow_edp_enter_replay_set(void *data, u64 val)
 {
 	struct amdgpu_dm_connector *aconnector = data;
+	struct dc_link *link = aconnector->dc_link;
+
+	aconnector->disallow_edp_enter_replay = (val != 0);
 
-	aconnector->disallow_edp_enter_replay = val ? true : false;
+	/* eDP replay enable / disable is happened during mode change in power module.
+	 * Only replay_settings.config.replay_supported is used to decide whether
+	 * replay is enabled or not. So here we only update replay_supported based on
+	 * debugfs setting.
+	 * If disallow_edp_enter_replay is true, set replay_supported to false.
+	 * if disallow_edp_enter_replay is false, set replay_supported back based on
+	 * sink replay capability.
+	 */
+	if (aconnector->disallow_edp_enter_replay)
+		link->replay_settings.config.replay_supported = false;
+	else
+		link->replay_settings.config.replay_supported =
+			link->replay_settings.config.replay_cap_support;
 	return 0;
 }
 
+
 static int dmub_trace_mask_set(void *data, u64 val)
 {
 	struct amdgpu_device *adev = data;
@@ -3485,6 +3517,7 @@ DEFINE_DEBUGFS_ATTRIBUTE(disallow_edp_enter_replay_fops,
 
 DEFINE_DEBUGFS_ATTRIBUTE(ips_residency_cntl_fops, ips_residency_cntl_get,
 			   ips_residency_cntl_set, "%llu\n");
+
 DEFINE_SHOW_ATTRIBUTE(current_backlight);
 DEFINE_SHOW_ATTRIBUTE(target_backlight);
 DEFINE_SHOW_ATTRIBUTE(ips_status);
@@ -3855,28 +3888,35 @@ DEFINE_DEBUGFS_ATTRIBUTE(crc_win_y_end_fops, crc_win_y_end_get,
 static int crc_win_update_set(void *data, u64 val)
 {
 	struct drm_crtc *crtc = data;
-	struct amdgpu_crtc *acrtc;
+	struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
 	struct amdgpu_device *adev = drm_to_adev(crtc->dev);
 
 	if (val) {
-		acrtc = to_amdgpu_crtc(crtc);
 		mutex_lock(&adev->dm.dc_lock);
-		/* PSR may write to OTG CRC window control register,
-		 * so close it before starting secure_display.
+		/* PSR Replay may write to OTG CRC window control register,
+		 * so inactive it before starting secure_display by sending disable event.
 		 */
-		amdgpu_dm_psr_disable(acrtc->dm_irq_params.stream, true);
+		amdgpu_dm_psr_set_event(&adev->dm, acrtc->dm_irq_params.stream, true,
+			psr_event_crc_window_active, true);
+		amdgpu_dm_replay_set_event(&adev->dm, acrtc->dm_irq_params.stream, true,
+			replay_event_crc_window_active, true);
 
 		spin_lock_irq(&adev_to_drm(adev)->event_lock);
-
 		acrtc->dm_irq_params.window_param[0].enable = true;
 		acrtc->dm_irq_params.window_param[0].update_win = true;
 		acrtc->dm_irq_params.window_param[0].skip_frame_cnt = 0;
 		acrtc->dm_irq_params.crc_window_activated = true;
-
 		spin_unlock_irq(&adev_to_drm(adev)->event_lock);
 		mutex_unlock(&adev->dm.dc_lock);
+	} else {
+		/* Clear disable events to allow PSR/Replay to active */
+		mutex_lock(&adev->dm.dc_lock);
+		amdgpu_dm_psr_set_event(&adev->dm, acrtc->dm_irq_params.stream, false,
+			psr_event_crc_window_active, false);
+		amdgpu_dm_replay_set_event(&adev->dm, acrtc->dm_irq_params.stream, false,
+			replay_event_crc_window_active, false);
+		mutex_unlock(&adev->dm.dc_lock);
 	}
-
 	return 0;
 }
 
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_ism.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_ism.c
index a64e95860e99..d03ea3bafd46 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_ism.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_ism.c
@@ -291,24 +291,16 @@ static void dm_ism_commit_idle_optimization_state(struct amdgpu_dm_ism *ism,
 	 */
 	if (stream && stream->link) {
 		/*
-		 * If allow_panel_sso is true when disabling vblank, allow
-		 * deeper panel sleep states such as PSR1 and Replay static
-		 * screen optimization.
-		 */
-		if (!vblank_enabled && allow_panel_sso) {
-			amdgpu_dm_crtc_set_panel_sr_feature(
-				dm, acrtc, stream, false,
-				acrtc->dm_irq_params.allow_sr_entry);
-		} else if (vblank_enabled) {
-			/* Make sure to exit SSO on vblank enable */
-			amdgpu_dm_crtc_set_panel_sr_feature(
-				dm, acrtc, stream, true,
-				acrtc->dm_irq_params.allow_sr_entry);
-		}
-		/*
-		 * Else, vblank_enabled == false and allow_panel_sso == false;
-		 * do nothing here.
+		 * If the OS requires vblank events (or vblank is otherwise enabled),
+		 * do not allow static screen optimizations.
+		 *
+		 * Keep ism->allow_static_screen_optimizations unchanged so the
+		 * hysteresis-based decision can be reused once vblank is disabled.
 		 */
+		allow_panel_sso = allow_panel_sso && !vblank_enabled;
+		amdgpu_dm_crtc_set_static_screen_optimze(
+			dm, stream, allow_panel_sso,
+			acrtc->dm_irq_params.allow_sr_entry);
 	}
 
 	/*
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
index 99d6d6c93561..dc5913a6456e 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.c
@@ -58,171 +58,76 @@ static bool link_supports_psrsu(struct dc_link *link)
 	return false;
 }
 
-/*
- * amdgpu_dm_set_psr_caps() - set link psr capabilities
- * @link: link
- *
- */
-void amdgpu_dm_set_psr_caps(struct dc_link *link)
+static void amdgpu_dm_psr_fill_caps(struct dc_link *link, struct psr_caps *caps)
 {
-	if (!(link->connector_signal & SIGNAL_TYPE_EDP)) {
-		link->psr_settings.psr_feature_enabled = false;
-		return;
-	}
-
-	if (link->type == dc_connection_none) {
-		link->psr_settings.psr_feature_enabled = false;
-		return;
-	}
-
-	if (link->dpcd_caps.psr_info.psr_version == 0) {
-		link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED;
-		link->psr_settings.psr_feature_enabled = false;
-
-	} else {
-		unsigned int panel_inst = 0;
-
-		if (link_supports_psrsu(link))
-			link->psr_settings.psr_version = DC_PSR_VERSION_SU_1;
-		else
-			link->psr_settings.psr_version = DC_PSR_VERSION_1;
-
-		link->psr_settings.psr_feature_enabled = true;
-
-		/*disable allow psr/psrsu/replay on eDP1*/
-		if (dc_get_edp_link_panel_inst(link->ctx->dc, link, &panel_inst) && panel_inst == 1) {
-			link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED;
-			link->psr_settings.psr_feature_enabled = false;
-		}
-	}
+	struct dpcd_caps *dpcd_caps = &link->dpcd_caps;
+	unsigned int power_opts = 0;
+
+	if (amdgpu_dc_feature_mask & DC_PSR_ALLOW_SMU_OPT)
+		power_opts |= psr_power_opt_smu_opt_static_screen;
+	power_opts |= psr_power_opt_z10_static_screen;
+
+	if (link->psr_settings.psr_version == DC_PSR_VERSION_1)
+		caps->psr_version = 1;
+	else if (link->psr_settings.psr_version == DC_PSR_VERSION_SU_1)
+		caps->psr_version = 2;
+
+	caps->psr_rfb_setup_time = (6 - dpcd_caps->psr_info.psr_dpcd_caps.bits.PSR_SETUP_TIME) * 55;
+	caps->psr_exit_link_training_required =
+		!dpcd_caps->psr_info.psr_dpcd_caps.bits.LINK_TRAINING_ON_EXIT_NOT_REQUIRED;
+	caps->edp_revision = dpcd_caps->edp_rev;
+	caps->support_ver = dpcd_caps->psr_info.psr_version;
+	caps->su_granularity_required =
+		dpcd_caps->psr_info.psr_dpcd_caps.bits.SU_GRANULARITY_REQUIRED;
+	caps->y_coordinate_required = dpcd_caps->psr_info.psr_dpcd_caps.bits.Y_COORDINATE_REQUIRED;
+	caps->su_y_granularity = dpcd_caps->psr_info.psr2_su_y_granularity_cap;
+	caps->alpm_cap = dpcd_caps->alpm_caps.bits.AUX_WAKE_ALPM_CAP;
+	caps->standby_support = dpcd_caps->alpm_caps.bits.PM_STATE_2A_SUPPORT;
+	caps->rate_control_caps = 0; /* TODO: read in rc caps from aux */
+	caps->psr_power_opt_flag = power_opts;
 }
 
 /*
- * amdgpu_dm_link_setup_psr() - configure psr link
- * @stream: stream state
- *
- * Return: true if success
+ * amdgpu_dm_set_psr_caps() - set link psr capabilities
+ * @link: link
+ * @aconnector: amdgpu_dm_connector
  */
-bool amdgpu_dm_link_setup_psr(struct dc_stream_state *stream)
+bool amdgpu_dm_set_psr_caps(struct dc_link *link, struct amdgpu_dm_connector *aconnector)
 {
-	struct dc_link *link = NULL;
-	struct psr_config psr_config = {0};
-	struct psr_context psr_context = {0};
-	struct dc *dc = NULL;
-	bool ret = false;
+	struct dc *dc;
+	unsigned int panel_inst = 0;
 
-	if (stream == NULL)
+	if (!link || !aconnector)
 		return false;
 
-	link = stream->link;
 	dc = link->ctx->dc;
 
-	if (link->psr_settings.psr_version != DC_PSR_VERSION_UNSUPPORTED) {
-		mod_power_calc_psr_configs(&psr_config, link, stream);
-
-		/* linux DM specific updating for psr config fields */
-		psr_config.allow_smu_optimizations =
-			(amdgpu_dc_feature_mask & DC_PSR_ALLOW_SMU_OPT) &&
-			mod_power_only_edp(dc->current_state, stream);
-		psr_config.allow_multi_disp_optimizations =
-			(amdgpu_dc_feature_mask & DC_PSR_ALLOW_MULTI_DISP_OPT);
-
-		if (link->psr_settings.psr_version == DC_PSR_VERSION_SU_1) {
-			if (!psr_su_set_dsc_slice_height(dc, link, stream, &psr_config))
-				return false;
-		}
-
-		ret = dc_link_setup_psr(link, stream, &psr_config, &psr_context);
-
-	}
-	DRM_DEBUG_DRIVER("PSR link: %d\n",	link->psr_settings.psr_feature_enabled);
-
-	return ret;
-}
-
-/*
- * amdgpu_dm_psr_enable() - enable psr f/w
- * @stream: stream state
- *
- */
-void amdgpu_dm_psr_enable(struct dc_stream_state *stream)
-{
-	struct dc_link *link = stream->link;
-	unsigned int vsync_rate_hz = 0;
-	struct dc_static_screen_params params = {0};
-	/* Calculate number of static frames before generating interrupt to
-	 * enter PSR.
-	 */
-	// Init fail safe of 2 frames static
-	unsigned int num_frames_static = 2;
-	unsigned int power_opt = 0;
-	bool psr_enable = true;
-
-	DRM_DEBUG_DRIVER("Enabling psr...\n");
-
-	vsync_rate_hz = div64_u64(div64_u64((
-			stream->timing.pix_clk_100hz * (uint64_t)100),
-			stream->timing.v_total),
-			stream->timing.h_total);
-
-	/* Round up
-	 * Calculate number of frames such that at least 30 ms of time has
-	 * passed.
-	 */
-	if (vsync_rate_hz != 0) {
-		unsigned int frame_time_microsec = 1000000 / vsync_rate_hz;
-
-		num_frames_static = (30000 / frame_time_microsec) + 1;
-	}
-
-	params.triggers.cursor_update = true;
-	params.triggers.overlay_update = true;
-	params.triggers.surface_update = true;
-	params.num_frames = num_frames_static;
+	/* Reset psr version first */
+	link->psr_settings.psr_version = DC_PSR_VERSION_UNSUPPORTED;
 
-	dc_stream_set_static_screen_params(link->ctx->dc,
-					   &stream, 1,
-					   &params);
+	if (!dc->caps.dmub_caps.psr)
+		return false;
 
-	/*
-	 * Only enable static-screen optimizations for PSR1. For PSR SU, this
-	 * causes vstartup interrupt issues, used by amdgpu_dm to send vblank
-	 * events.
-	 */
-	if (link->psr_settings.psr_version < DC_PSR_VERSION_SU_1)
-		power_opt |= psr_power_opt_z10_static_screen;
+	if (!(link->connector_signal & SIGNAL_TYPE_EDP))
+		return false;
 
-	dc_link_set_psr_allow_active(link, &psr_enable, false, false, &power_opt);
+	if (link->type == dc_connection_none)
+		return false;
 
-	if (link->ctx->dc->caps.ips_support)
-		dc_allow_idle_optimizations(link->ctx->dc, true);
-}
+	if (link->dpcd_caps.psr_info.psr_version == 0)
+		return false;
 
-/*
- * amdgpu_dm_psr_disable() - disable psr f/w
- * @stream:  stream state
- *
- * Return: true if success
- */
-bool amdgpu_dm_psr_disable(struct dc_stream_state *stream, bool wait)
-{
-	bool psr_enable = false;
+	/*disable allow psr/psrsu/replay on eDP1*/
+	if (dc_get_edp_link_panel_inst(link->ctx->dc, link, &panel_inst) && panel_inst == 1)
+		return false;
 
-	DRM_DEBUG_DRIVER("Disabling psr...\n");
+	if (link_supports_psrsu(link))
+		link->psr_settings.psr_version = DC_PSR_VERSION_SU_1;
+	else
+		link->psr_settings.psr_version = DC_PSR_VERSION_1;
 
-	return dc_link_set_psr_allow_active(stream->link, &psr_enable, wait, false, NULL);
-}
-
-/*
- * amdgpu_dm_psr_disable_all() - disable psr f/w for all streams
- * if psr is enabled on any stream
- *
- * Return: true if success
- */
-bool amdgpu_dm_psr_disable_all(struct amdgpu_display_manager *dm)
-{
-	DRM_DEBUG_DRIVER("Disabling psr if psr is enabled on any stream\n");
-	return dc_set_psr_allow_active(dm->dc, false);
+	amdgpu_dm_psr_fill_caps(link, &aconnector->psr_caps);
+	return true;
 }
 
 /*
@@ -250,36 +155,37 @@ bool amdgpu_dm_psr_is_active_allowed(struct amdgpu_display_manager *dm)
 			break;
 		}
 	}
-
 	return allow_active;
 }
 
-/**
- * amdgpu_dm_psr_wait_disable() - Wait for eDP panel to exit PSR
- * @stream: stream state attached to the eDP link
- *
- * Waits for a max of 500ms for the eDP panel to exit PSR.
+/*
+ * amdgpu_dm_psr_set_event() - set or clear PSR event for stream
+ * @dm: pointer to amdgpu_display_manager
+ * @stream: pointer to dc_stream_state
+ * @set_event: true to set event, false to clear event
+ * @event: PSR event type
+ * @wait_for_disable: whether to wait for PSR to be disabled
  *
- * Return: true if panel exited PSR, false otherwise.
+ * Return: true if successful, false otherwise
  */
-bool amdgpu_dm_psr_wait_disable(struct dc_stream_state *stream)
+bool amdgpu_dm_psr_set_event(struct amdgpu_display_manager *dm, struct dc_stream_state *stream,
+		bool set_event, enum psr_event event, bool wait_for_disable)
 {
-	enum dc_psr_state psr_state = PSR_STATE0;
-	struct dc_link *link = stream->link;
-	int retry_count;
+	unsigned int psr_events;
 
-	if (link == NULL)
+	/* Validate all required parameters */
+	if (!stream || !stream->link ||
+		!stream->link->psr_settings.psr_feature_enabled)
 		return false;
 
-	for (retry_count = 0; retry_count <= 1000; retry_count++) {
-		dc_link_get_psr_state(link, &psr_state);
-		if (psr_state == PSR_STATE0)
-			break;
-		udelay(500);
-	}
-
-	if (retry_count == 1000)
+	/* Get current psr events */
+	if (!mod_power_get_psr_event(dm->power_module, stream, &psr_events))
 		return false;
 
-	return true;
+	/* If all events already in desired state, return true. */
+	if ((psr_events & event) == (set_event ? event : 0))
+		return true;
+
+	return mod_power_set_psr_event(dm->power_module, stream,
+				       set_event, event, wait_for_disable);
 }
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.h
index 4fb8626913cf..16d535806ad6 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_psr.h
@@ -28,16 +28,15 @@
 #define AMDGPU_DM_AMDGPU_DM_PSR_H_
 
 #include "amdgpu.h"
+#include "dc.h"
+#include "modules/inc/mod_power.h"
 
 /* the number of pageflips before enabling psr */
 #define AMDGPU_DM_PSR_ENTRY_DELAY 5
 
-void amdgpu_dm_set_psr_caps(struct dc_link *link);
-void amdgpu_dm_psr_enable(struct dc_stream_state *stream);
-bool amdgpu_dm_link_setup_psr(struct dc_stream_state *stream);
-bool amdgpu_dm_psr_disable(struct dc_stream_state *stream, bool wait);
-bool amdgpu_dm_psr_disable_all(struct amdgpu_display_manager *dm);
+bool amdgpu_dm_set_psr_caps(struct dc_link *link, struct amdgpu_dm_connector *aconnector);
 bool amdgpu_dm_psr_is_active_allowed(struct amdgpu_display_manager *dm);
-bool amdgpu_dm_psr_wait_disable(struct dc_stream_state *stream);
-
+bool amdgpu_dm_psr_set_event(struct amdgpu_display_manager *dm,
+		struct dc_stream_state *stream, bool set_event,	enum psr_event event,
+		bool wait_for_disable);
 #endif /* AMDGPU_DM_AMDGPU_DM_PSR_H_ */
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c
index 8c150b001105..297125d1db70 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.c
@@ -27,7 +27,6 @@
 #include "amdgpu_dm_replay.h"
 #include "dc_dmub_srv.h"
 #include "dc.h"
-#include "dm_helpers.h"
 #include "amdgpu_dm.h"
 #include "modules/power/power_helpers.h"
 #include "dmub/inc/dmub_cmd.h"
@@ -99,13 +98,29 @@ bool amdgpu_dm_set_replay_caps(struct dc_link *link, struct amdgpu_dm_connector
 		!dc->ctx->dmub_srv->dmub->feature_caps.replay_supported)
 		return false;
 
+	/* Mark Replay is supported in link and update related attributes
+	 * This flag presents DPCD caps & amd_vsdb caps satisfy replay requirement.
+	 */
+	pr_config.replay_cap_support = true;
+
 	// Mark Replay is supported in pr_config
 	pr_config.replay_supported = true;
 
+	pr_config.replay_enable_option = pr_enable_option_general_ui |
+					 pr_enable_option_static_screen	|
+					 pr_enable_option_static_screen_coasting;
+	pr_config.replay_power_opt_supported = replay_power_opt_smu_opt_static_screen |
+					       replay_power_opt_z10_static_screen;
+	pr_config.replay_smu_opt_supported = false;
+	pr_config.replay_support_fast_resync_in_ultra_sleep_mode =
+		aconnector->max_vfreq >= 2 * aconnector->min_vfreq;
+	pr_config.force_disable_desync_error_check = false;
+
 	debug_flags = (union replay_debug_flags *)&pr_config.debug_flags;
 	debug_flags->u32All = 0;
 	debug_flags->bitfields.visual_confirm =
 		link->ctx->dc->debug.visual_confirm == VISUAL_CONFIRM_REPLAY;
+	debug_flags->bitfields.skip_crtc_disabled = dc->debug.replay_skip_crtc_disabled;
 
 	init_replay_config(link, &pr_config);
 
@@ -113,104 +128,80 @@ bool amdgpu_dm_set_replay_caps(struct dc_link *link, struct amdgpu_dm_connector
 }
 
 /*
- * amdgpu_dm_link_setup_replay() - configure replay link
- * @link: link
- * @aconnector: aconnector
+ * amdgpu_dm_link_setup_replay() - config replay settings
+ * @stream: pointer to dc_stream_state structure
+ * @vrr_params: pointer to mod_vrr_params structure containing VRR parameters
  *
+ * config replay link settings including coasting vtotal calculations.
+ *
+ * Return: true if successful, false if any parameter is invalid or replay not supported
  */
-bool amdgpu_dm_link_setup_replay(struct dc_link *link, struct amdgpu_dm_connector *aconnector)
+bool amdgpu_dm_link_setup_replay(struct dc_stream_state *stream,
+		struct mod_vrr_params *vrr_params)
 {
-	struct replay_config *pr_config;
+	struct dc_link *link;
+	unsigned int static_coasting_vtotal;
+	unsigned int nom_coasting_vtotal;
 
-	if (link == NULL || aconnector == NULL)
+	if (!stream || !stream->link || !vrr_params)
 		return false;
 
-	pr_config = &link->replay_settings.config;
-
-	if (!pr_config->replay_supported)
+	link = stream->link;
+	if (!link->replay_settings.config.replay_supported)
 		return false;
 
-	pr_config->replay_power_opt_supported = 0x11;
-	pr_config->replay_smu_opt_supported = false;
-	pr_config->replay_enable_option |= pr_enable_option_static_screen;
-	pr_config->replay_support_fast_resync_in_ultra_sleep_mode = aconnector->max_vfreq >= 2 * aconnector->min_vfreq;
-	pr_config->replay_timing_sync_supported = false;
+	if (link->replay_settings.replay_feature_enabled)
+		return true;
 
-	if (!pr_config->replay_timing_sync_supported)
-		pr_config->replay_enable_option &= ~pr_enable_option_general_ui;
+	calculate_replay_link_off_frame_count(link, stream->timing.v_total,
+			stream->timing.h_total);
 
-	link->replay_settings.replay_feature_enabled = true;
+	nom_coasting_vtotal = stream->timing.v_total;
+	static_coasting_vtotal = mod_freesync_calc_v_total_from_refresh(stream,
+			vrr_params->min_refresh_in_uhz);
 
+	set_replay_coasting_vtotal(link, PR_COASTING_TYPE_NOM,
+			nom_coasting_vtotal);
+	set_replay_coasting_vtotal(link, PR_COASTING_TYPE_STATIC,
+			static_coasting_vtotal);
 	return true;
 }
 
 /*
- * amdgpu_dm_replay_enable() - enable replay f/w
- * @stream: stream state
+ * amdgpu_dm_replay_set_event() - set or clear replay event for a stream
+ * @dm: pointer to amdgpu_display_manager
+ * @stream: pointer to dc_stream_state
+ * @set_event: true to set event, false to clear event
+ * @event: replay event type to set or clear
+ * @wait_for_disable: whether to wait for replay to be disabled before returning
  *
- * Return: true if success
- */
-bool amdgpu_dm_replay_enable(struct dc_stream_state *stream, bool wait)
-{
-	bool replay_active = true;
-	struct dc_link *link = NULL;
-	struct amdgpu_dm_connector *aconnector = NULL;
-
-	if (stream == NULL)
-		return false;
-
-	/* Check if replay is disabled by connector flag */
-	aconnector = (struct amdgpu_dm_connector *)stream->dm_stream_context;
-	if (!aconnector || aconnector->disallow_edp_enter_replay) {
-		return false;
-	}
-
-	link = stream->link;
-
-	if (link) {
-		link->dc->link_srv->dp_setup_replay(link, stream);
-		link->dc->link_srv->edp_set_coasting_vtotal(link, stream->timing.v_total, 0);
-		DRM_DEBUG_DRIVER("Enabling replay...\n");
-		link->dc->link_srv->edp_set_replay_allow_active(link, &replay_active, wait, false, NULL);
-		return true;
-	}
-
-	return false;
-}
-
-/*
- * amdgpu_dm_replay_disable() - disable replay f/w
- * @stream:  stream state
+ * This function sets or clears a specific replay event for the given stream.
+ * It temporarily disables idle optimizations during the operation to ensure
+ * hardware access is available.
  *
- * Return: true if success
+ * Return: true if successful, false if any parameter is invalid or operation fails
  */
-bool amdgpu_dm_replay_disable(struct dc_stream_state *stream)
+bool amdgpu_dm_replay_set_event(struct amdgpu_display_manager *dm,
+		struct dc_stream_state *stream,
+		bool set_event,
+		enum replay_event event,
+		bool wait_for_disable)
 {
-	bool replay_active = false;
-	struct dc_link *link = NULL;
+	unsigned int replay_events;
 
-	if (stream == NULL)
+	/* Validate all required parameters */
+	if (!stream || !stream->link ||
+		!stream->link->replay_settings.replay_feature_enabled)
 		return false;
 
-	link = stream->link;
+	/* Get current replay events */
+	if (!mod_power_get_replay_event(dm->power_module, stream, &replay_events))
+		return false;
 
-	if (link) {
-		DRM_DEBUG_DRIVER("Disabling replay...\n");
-		link->dc->link_srv->edp_set_replay_allow_active(stream->link, &replay_active, true, false, NULL);
+	/* If all events already in desired state, return true. */
+	if ((replay_events & event) == (set_event ? event : 0))
 		return true;
-	}
-
-	return false;
-}
 
-/*
- * amdgpu_dm_replay_disable_all() - disable replay f/w
- * if replay is enabled on any stream
- *
- * Return: true if success
- */
-bool amdgpu_dm_replay_disable_all(struct amdgpu_display_manager *dm)
-{
-	DRM_DEBUG_DRIVER("Disabling replay if replay is enabled on any stream\n");
-	return dc_set_replay_allow_active(dm->dc, false);
+	return mod_power_set_replay_event(dm->power_module, stream,
+					 set_event, event, wait_for_disable);
 }
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.h
index 73b6c67ae5e7..021bf0255516 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_replay.h
@@ -28,22 +28,16 @@
 #define AMDGPU_DM_AMDGPU_DM_REPLAY_H_
 
 #include "amdgpu.h"
+#include "dc.h"
+#include "modules/inc/mod_power.h"
 
-enum replay_enable_option {
-	pr_enable_option_static_screen = 0x1,
-	pr_enable_option_mpo_video = 0x2,
-	pr_enable_option_full_screen_video = 0x4,
-	pr_enable_option_general_ui = 0x8,
-	pr_enable_option_static_screen_coasting = 0x10000,
-	pr_enable_option_mpo_video_coasting = 0x20000,
-	pr_enable_option_full_screen_video_coasting = 0x40000,
-};
-
-bool amdgpu_dm_link_supports_replay(struct dc_link *link, struct amdgpu_dm_connector *aconnector);
-bool amdgpu_dm_replay_enable(struct dc_stream_state *stream, bool enable);
-bool amdgpu_dm_set_replay_caps(struct dc_link *link, struct amdgpu_dm_connector *aconnector);
-bool amdgpu_dm_link_setup_replay(struct dc_link *link, struct amdgpu_dm_connector *aconnector);
-bool amdgpu_dm_replay_disable(struct dc_stream_state *stream);
-bool amdgpu_dm_replay_disable_all(struct amdgpu_display_manager *dm);
-
+bool amdgpu_dm_link_supports_replay(struct dc_link *link,
+		struct amdgpu_dm_connector *aconnector);
+bool amdgpu_dm_set_replay_caps(struct dc_link *link,
+		struct amdgpu_dm_connector *aconnector);
+bool amdgpu_dm_link_setup_replay(struct dc_stream_state *stream,
+		struct mod_vrr_params *vrr_params);
+bool amdgpu_dm_replay_set_event(struct amdgpu_display_manager *dm,
+		struct dc_stream_state *stream, bool set_event,
+		enum replay_event event, bool wait_for_disable);
 #endif /* AMDGPU_DM_AMDGPU_DM_REPLAY_H_ */
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
index 8550d5e8b753..84dcb573d98f 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_services.c
@@ -62,3 +62,30 @@ void dm_trace_smu_exit(bool success, uint32_t response, struct dc_context *ctx)
 }
 
 /**** power component interfaces ****/
+
+bool dm_query_extended_brightness_caps(struct dc_context *ctx,
+	enum dm_acpi_display_type display, struct dm_acpi_atif_backlight_caps *pCaps)
+{
+	struct amdgpu_device *adev;
+	struct amdgpu_display_manager *dm;
+	int bl_index = (display == AcpiDisplayType_LCD1) ? 0 : 1;
+
+	if (!ctx || !pCaps || !ctx->driver_context)
+		return false;
+
+	adev = (struct amdgpu_device *)ctx->driver_context;
+	dm = &adev->dm;
+
+	amdgpu_dm_update_backlight_caps(dm, bl_index);
+
+	pCaps->num_data_points = dm->backlight_caps[bl_index].data_points;
+	pCaps->max_input_signal = dm->backlight_caps[bl_index].max_input_signal;
+	pCaps->min_input_signal = dm->backlight_caps[bl_index].min_input_signal;
+	pCaps->ac_level_percentage = dm->backlight_caps[bl_index].ac_level;
+	pCaps->dc_level_percentage = dm->backlight_caps[bl_index].dc_level;
+
+	if (pCaps->num_data_points > 0)
+		memcpy(pCaps->data_points, dm->backlight_caps[bl_index].luminance_data,
+			sizeof(struct dm_bl_data_point) * pCaps->num_data_points);
+	return true;
+}
diff --git a/drivers/gpu/drm/amd/display/dc/basics/custom_float.c b/drivers/gpu/drm/amd/display/dc/basics/custom_float.c
index ae05ded9a7f3..d313584335d3 100644
--- a/drivers/gpu/drm/amd/display/dc/basics/custom_float.c
+++ b/drivers/gpu/drm/amd/display/dc/basics/custom_float.c
@@ -90,7 +90,7 @@ static bool build_custom_float(struct fixed31_32 value,
 	    dc_fixpt_lt(dc_fixpt_one, mantiss))
 		mantiss = dc_fixpt_zero;
 	else
-		mantiss = dc_fixpt_shl(mantiss, format->mantissa_bits);
+		mantiss = dc_fixpt_shl(mantiss, (unsigned char)format->mantissa_bits);
 
 	*mantissa = dc_fixpt_floor(mantiss);
 
diff --git a/drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c b/drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
index f37a43f4172e..911b62fb9b2c 100644
--- a/drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/basics/dce_calcs.c
@@ -3077,7 +3077,7 @@ bool bw_calcs(struct dc_context *ctx,
 		}
 		calculate_bandwidth(dceip, vbios, data);
 
-		yclk_lvl = data->y_clk_level;
+		yclk_lvl = (uint8_t)data->y_clk_level;
 
 		calcs_output->nbp_state_change_enable =
 			data->nbp_state_change_enable;
diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
index dd362071a6c9..8d196a00d437 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser.c
@@ -794,17 +794,19 @@ static enum bp_result bios_parser_external_encoder_control(
 
 static enum bp_result bios_parser_dac_load_detection(
 	struct dc_bios *dcb,
-	enum engine_id engine_id)
+	enum engine_id engine_id,
+	struct graphics_object_id ext_enc_id)
 {
 	struct bios_parser *bp = BP_FROM_DCB(dcb);
 	struct dc_context *ctx = dcb->ctx;
 	struct bp_load_detection_parameters bp_params = {0};
+	struct bp_external_encoder_control ext_cntl = {0};
 	enum bp_result bp_result = BP_RESULT_UNSUPPORTED;
 	uint32_t bios_0_scratch;
 	uint32_t device_id_mask = 0;
 
-	bp_params.device_id = get_support_mask_for_device_id(
-		DEVICE_TYPE_CRT, engine_id == ENGINE_ID_DACB ? 2 : 1);
+	bp_params.device_id = (uint16_t)get_support_mask_for_device_id(
+			DEVICE_TYPE_CRT, engine_id == ENGINE_ID_DACB ? 2 : 1);
 
 	if (bp_params.device_id == ATOM_DEVICE_CRT1_SUPPORT)
 		device_id_mask = ATOM_S0_CRT1_MASK;
@@ -824,6 +826,13 @@ static enum bp_result bios_parser_dac_load_detection(
 
 		bp_params.engine_id = engine_id;
 		bp_result = bp->cmd_tbl.dac_load_detection(bp, &bp_params);
+	} else if (ext_enc_id.id) {
+		if (!bp->cmd_tbl.external_encoder_control)
+			return BP_RESULT_UNSUPPORTED;
+
+		ext_cntl.action = EXTERNAL_ENCODER_CONTROL_DAC_LOAD_DETECT;
+		ext_cntl.encoder_id = ext_enc_id;
+		bp_result = bp->cmd_tbl.external_encoder_control(bp, &ext_cntl);
 	}
 
 	if (bp_result != BP_RESULT_OK)
@@ -1382,7 +1391,7 @@ static enum bp_result get_embedded_panel_info_v1_2(
 	info->ss_id = lvds->ucSS_Id;
 
 	{
-		uint8_t rr = le16_to_cpu(lvds->usSupportedRefreshRate);
+		uint16_t rr = le16_to_cpu(lvds->usSupportedRefreshRate);
 		/* Get minimum supported refresh rate*/
 		if (SUPPORTED_LCD_REFRESHRATE_30Hz & rr)
 			info->supported_rr.REFRESH_RATE_30HZ = 1;
diff --git a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
index a1c08e1cc411..1b09a7907cb4 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c
@@ -157,7 +157,7 @@ static uint8_t bios_parser_get_connectors_number(struct dc_bios *dcb)
 
 		break;
 	}
-	return count;
+	return (uint8_t)count;
 }
 
 static struct graphics_object_id bios_parser_get_connector_id(
@@ -401,7 +401,7 @@ static enum bp_result bios_parser_get_i2c_info(struct dc_bios *dcb,
 		return BP_RESULT_BADINPUT;
 
 	if (id.type == OBJECT_TYPE_GENERIC) {
-		dummy_record.i2c_id = id.id;
+		dummy_record.i2c_id = (uint8_t)id.id;
 
 		if (get_gpio_i2c_info(bp, &dummy_record, info) == BP_RESULT_OK)
 			return BP_RESULT_OK;
@@ -1228,7 +1228,7 @@ static enum bp_result get_disp_caps_v4_1(
 	if (!disp_cntl_tbl)
 		return BP_RESULT_BADBIOSTABLE;
 
-	*dce_caps = disp_cntl_tbl->display_caps;
+	*dce_caps = (uint8_t)disp_cntl_tbl->display_caps;
 
 	return result;
 }
@@ -1252,7 +1252,7 @@ static enum bp_result get_disp_caps_v4_2(
 	if (!disp_cntl_tbl)
 		return BP_RESULT_BADBIOSTABLE;
 
-	*dce_caps = disp_cntl_tbl->display_caps;
+	*dce_caps = (uint8_t)disp_cntl_tbl->display_caps;
 
 	return result;
 }
@@ -1276,7 +1276,7 @@ static enum bp_result get_disp_caps_v4_3(
 	if (!disp_cntl_tbl)
 		return BP_RESULT_BADBIOSTABLE;
 
-	*dce_caps = disp_cntl_tbl->display_caps;
+	*dce_caps = (uint8_t)disp_cntl_tbl->display_caps;
 
 	return result;
 }
@@ -1300,7 +1300,7 @@ static enum bp_result get_disp_caps_v4_4(
 	if (!disp_cntl_tbl)
 		return BP_RESULT_BADBIOSTABLE;
 
-	*dce_caps = disp_cntl_tbl->display_caps;
+	*dce_caps = (uint8_t)disp_cntl_tbl->display_caps;
 
 	return result;
 }
@@ -1324,7 +1324,7 @@ static enum bp_result get_disp_caps_v4_5(
 	if (!disp_cntl_tbl)
 		return BP_RESULT_BADBIOSTABLE;
 
-	*dce_caps = disp_cntl_tbl->display_caps;
+	*dce_caps = (uint8_t)disp_cntl_tbl->display_caps;
 
 	return result;
 }
@@ -2585,7 +2585,7 @@ static enum bp_result get_integrated_info_v11(
 		info->ext_disp_conn_info.path[i].channel_mapping.raw =
 			info_v11->extdispconninfo.path[i].channelmapping;
 		info->ext_disp_conn_info.path[i].caps =
-				le16_to_cpu(info_v11->extdispconninfo.path[i].caps);
+				(unsigned short)le16_to_cpu(info_v11->extdispconninfo.path[i].caps);
 	}
 	info->ext_disp_conn_info.checksum =
 	info_v11->extdispconninfo.checksum;
@@ -2790,7 +2790,7 @@ static enum bp_result get_integrated_info_v2_1(
 		info->ext_disp_conn_info.path[i].channel_mapping.raw =
 			info_v2_1->extdispconninfo.path[i].channelmapping;
 		info->ext_disp_conn_info.path[i].caps =
-				le16_to_cpu(info_v2_1->extdispconninfo.path[i].caps);
+				(unsigned short)le16_to_cpu(info_v2_1->extdispconninfo.path[i].caps);
 	}
 
 	info->ext_disp_conn_info.checksum =
@@ -2954,7 +2954,7 @@ static enum bp_result get_integrated_info_v2_2(
 		info->ext_disp_conn_info.path[i].channel_mapping.raw =
 			info_v2_2->extdispconninfo.path[i].channelmapping;
 		info->ext_disp_conn_info.path[i].caps =
-				le16_to_cpu(info_v2_2->extdispconninfo.path[i].caps);
+				(unsigned short)le16_to_cpu(info_v2_2->extdispconninfo.path[i].caps);
 	}
 
 	info->ext_disp_conn_info.checksum =
@@ -2977,6 +2977,7 @@ static enum bp_result get_integrated_info_v2_2(
 	info->edp1_info.edp_panel_bpc =
 		info_v2_2->edp1_info.edp_panel_bpc;
 	info->edp1_info.edp_bootup_bl_level =
+		info_v2_2->edp1_info.edp_bootup_bl_level;
 
 	info->edp2_info.edp_backlight_pwm_hz =
 	le16_to_cpu(info_v2_2->edp2_info.edp_backlight_pwm_hz);
diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table.c b/drivers/gpu/drm/amd/display/dc/bios/command_table.c
index f6e22dcecf29..0df84394a325 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/command_table.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/command_table.c
@@ -1521,8 +1521,8 @@ static enum bp_result adjust_display_pll_v2(
 
 		if (pixel_clock_10KHz_in != 0) {
 			bp_params->adjusted_pixel_clock =
-					div_u64(pixel_clk * pixel_clk_10_khz_out,
-							pixel_clock_10KHz_in);
+					(uint32_t)div_u64(pixel_clk * pixel_clk_10_khz_out,
+							  pixel_clock_10KHz_in);
 		} else {
 			bp_params->adjusted_pixel_clock = 0;
 			BREAK_TO_DEBUGGER();
@@ -1571,8 +1571,8 @@ static enum bp_result adjust_display_pll_v3(
 
 		if (pixel_clk_10_kHz_in != 0) {
 			bp_params->adjusted_pixel_clock =
-					div_u64(pixel_clk * pixel_clk_10_khz_out,
-							pixel_clk_10_kHz_in);
+					(uint32_t)div_u64(pixel_clk * pixel_clk_10_khz_out,
+							  pixel_clk_10_kHz_in);
 		} else {
 			bp_params->adjusted_pixel_clock = 0;
 			BREAK_TO_DEBUGGER();
@@ -2662,8 +2662,8 @@ static enum bp_result set_dce_clock_v2_1(
 			!cmd->dc_clock_type_to_atom(bp_params->clock_type, &atom_clock_type))
 		return BP_RESULT_BADINPUT;
 
-	params.asParam.ucDCEClkSrc  = atom_pll_id;
-	params.asParam.ucDCEClkType = atom_clock_type;
+	params.asParam.ucDCEClkSrc = (uint8_t)atom_pll_id;
+	params.asParam.ucDCEClkType = (uint8_t)atom_clock_type;
 
 	if (bp_params->clock_type == DCECLOCK_TYPE_DPREFCLK) {
 		if (bp_params->flags.USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK)
diff --git a/drivers/gpu/drm/amd/display/dc/bios/command_table2.c b/drivers/gpu/drm/amd/display/dc/bios/command_table2.c
index 17ef515c6c69..88625daf5378 100644
--- a/drivers/gpu/drm/amd/display/dc/bios/command_table2.c
+++ b/drivers/gpu/drm/amd/display/dc/bios/command_table2.c
@@ -929,8 +929,8 @@ static enum bp_result set_dce_clock_v2_1(
 					&atom_clock_type))
 		return BP_RESULT_BADINPUT;
 
-	params.param.dceclksrc  = atom_pll_id;
-	params.param.dceclktype = atom_clock_type;
+	params.param.dceclksrc = (uint8_t)atom_pll_id;
+	params.param.dceclktype = (uint8_t)atom_clock_type;
 
 	if (bp_params->clock_type == DCECLOCK_TYPE_DPREFCLK) {
 		if (bp_params->flags.USE_GENLOCK_AS_SOURCE_FOR_DPREFCLK)
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
index cd4c45516616..13296c6ec08f 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/dce110_clk_mgr.c
@@ -127,7 +127,7 @@ void dce110_fill_display_configs(
 	pp_display_cfg->avail_mclk_switch_time_us = dce110_get_min_vblank_time_us(context);
 	pp_display_cfg->disp_clk_khz = dc->clk_mgr->clks.dispclk_khz;
 	pp_display_cfg->avail_mclk_switch_time_in_disp_active_us = 0;
-	pp_display_cfg->crtc_index = dc->res_pool->res_cap->num_timing_generator;
+	pp_display_cfg->crtc_index = (uint8_t)dc->res_pool->res_cap->num_timing_generator;
 
 	for (j = 0; j < context->stream_count; j++) {
 		int k;
@@ -151,7 +151,7 @@ void dce110_fill_display_configs(
 
 		num_cfgs++;
 		cfg->signal = pipe_ctx->stream->signal;
-		cfg->pipe_idx = pipe_ctx->stream_res.tg->inst;
+		cfg->pipe_idx = (uint8_t)pipe_ctx->stream_res.tg->inst;
 		cfg->src_height = stream->src.height;
 		cfg->src_width = stream->src.width;
 		cfg->ddi_channel_mapping =
@@ -189,7 +189,7 @@ void dce110_fill_display_configs(
 		pp_display_cfg->line_time_in_us = 0;
 	}
 
-	pp_display_cfg->display_count = num_cfgs;
+	pp_display_cfg->display_count = (uint8_t)num_cfgs;
 }
 
 void dce11_pplib_apply_display_requirements(
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
index 09e83097a623..df06e5cd27aa 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c
@@ -462,8 +462,10 @@ static void build_watermark_ranges(struct clk_bw_params *bw_params, struct pp_sm
 		if (!bw_params->wm_table.entries[i].valid)
 			continue;
 
-		ranges->reader_wm_sets[num_valid_sets].wm_inst = bw_params->wm_table.entries[i].wm_inst;
-		ranges->reader_wm_sets[num_valid_sets].wm_type = bw_params->wm_table.entries[i].wm_type;
+		ranges->reader_wm_sets[num_valid_sets].wm_inst =
+			(uint8_t)bw_params->wm_table.entries[i].wm_inst;
+		ranges->reader_wm_sets[num_valid_sets].wm_type =
+			(uint8_t)bw_params->wm_table.entries[i].wm_type;
 		/* We will not select WM based on fclk, so leave it as unconstrained */
 		ranges->reader_wm_sets[num_valid_sets].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
 		ranges->reader_wm_sets[num_valid_sets].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
@@ -474,9 +476,11 @@ static void build_watermark_ranges(struct clk_bw_params *bw_params, struct pp_sm
 				ranges->reader_wm_sets[num_valid_sets].min_drain_clk_mhz = 0;
 			else {
 				/* add 1 to make it non-overlapping with next lvl */
-				ranges->reader_wm_sets[num_valid_sets].min_drain_clk_mhz = bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1;
+				ranges->reader_wm_sets[num_valid_sets].min_drain_clk_mhz =
+					(uint16_t)(bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1);
 			}
-			ranges->reader_wm_sets[num_valid_sets].max_drain_clk_mhz = bw_params->clk_table.entries[i].dcfclk_mhz;
+			ranges->reader_wm_sets[num_valid_sets].max_drain_clk_mhz =
+				(uint16_t)bw_params->clk_table.entries[i].dcfclk_mhz;
 
 		} else {
 			/* unconstrained for memory retraining */
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c
index dcec9d0f8c34..92bc355883d5 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn30/dcn30_clk_mgr.c
@@ -78,9 +78,9 @@ static const struct clk_mgr_mask clk_mgr_mask = {
 
 
 /* Query SMU for all clock states for a particular clock */
-static void dcn3_init_single_clock(struct clk_mgr_internal *clk_mgr, uint32_t clk, unsigned int *entry_0, unsigned int *num_levels)
+static void dcn3_init_single_clock(struct clk_mgr_internal *clk_mgr, uint32_t clk, unsigned int *entry_0, uint8_t *num_levels)
 {
-	unsigned int i;
+	uint8_t i;
 	char *entry_i = (char *)entry_0;
 	uint32_t ret = dcn30_smu_get_dpm_freq_by_index(clk_mgr, clk, 0xFF);
 
@@ -109,7 +109,7 @@ static void dcn3_build_wm_range_table(struct clk_mgr_internal *clk_mgr)
 void dcn3_init_clocks(struct clk_mgr *clk_mgr_base)
 {
 	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
-	unsigned int num_levels;
+	uint8_t num_levels;
 
 	memset(&(clk_mgr_base->clks), 0, sizeof(struct dc_clocks));
 	clk_mgr_base->clks.p_state_change_support = true;
@@ -234,7 +234,7 @@ static void dcn3_update_clocks(struct clk_mgr *clk_mgr_base,
 
 	if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz)) {
 		clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
-		dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DCEFCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz));
+		dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DCEFCLK, (uint16_t)khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz));
 	}
 
 	if (should_set_clock(safe_to_lower, new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) {
@@ -265,10 +265,11 @@ static void dcn3_update_clocks(struct clk_mgr *clk_mgr_base,
 			if (dc->clk_mgr->dc_mode_softmax_enabled &&
 				new_clocks->dramclk_khz <= dc->clk_mgr->bw_params->dc_mode_softmax_memclk * 1000)
 				dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
-					dc->clk_mgr->bw_params->dc_mode_softmax_memclk);
+					(uint16_t)dc->clk_mgr->bw_params->dc_mode_softmax_memclk);
 			else
 				dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
-					clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].memclk_mhz);
+					(uint16_t)clk_mgr_base->bw_params->clk_table.entries[
+						clk_mgr_base->bw_params->clk_table.num_entries - 1].memclk_mhz);
 		}
 	}
 
@@ -281,20 +282,20 @@ static void dcn3_update_clocks(struct clk_mgr *clk_mgr_base,
 	/* set UCLK to requested value if P-State switching is supported, or to re-enable P-State switching */
 	if (clk_mgr_base->clks.p_state_change_support &&
 			(update_uclk || !clk_mgr_base->clks.prev_p_state_change_support))
-		dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz));
+		dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, (uint16_t)khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz));
 
 	if (should_set_clock(safe_to_lower, new_clocks->dppclk_khz, clk_mgr_base->clks.dppclk_khz)) {
 		if (clk_mgr_base->clks.dppclk_khz > new_clocks->dppclk_khz)
 			dpp_clock_lowered = true;
 
 		clk_mgr_base->clks.dppclk_khz = new_clocks->dppclk_khz;
-		dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_PIXCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dppclk_khz));
+		dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_PIXCLK, (uint16_t)khz_to_mhz_ceil(clk_mgr_base->clks.dppclk_khz));
 		update_dppclk = true;
 	}
 
 	if (should_set_clock(safe_to_lower, new_clocks->dispclk_khz, clk_mgr_base->clks.dispclk_khz)) {
 		clk_mgr_base->clks.dispclk_khz = new_clocks->dispclk_khz;
-		dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DISPCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dispclk_khz));
+		dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DISPCLK, (uint16_t)khz_to_mhz_ceil(clk_mgr_base->clks.dispclk_khz));
 		update_dispclk = true;
 	}
 
@@ -323,7 +324,7 @@ static void dcn3_update_clocks(struct clk_mgr *clk_mgr_base,
 
 static void dcn3_notify_wm_ranges(struct clk_mgr *clk_mgr_base)
 {
-	unsigned int i;
+	uint8_t i;
 	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
 	WatermarksExternal_t *table = (WatermarksExternal_t *) clk_mgr->wm_range_table;
 
@@ -363,13 +364,14 @@ static void dcn3_set_hard_min_memclk(struct clk_mgr *clk_mgr_base, bool current_
 	if (current_mode) {
 		if (clk_mgr_base->clks.p_state_change_support)
 			dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
-					khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz));
+					(uint16_t)khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz));
 		else
 			dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
-					clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].memclk_mhz);
+					(uint16_t)clk_mgr_base->bw_params->clk_table.entries[
+							clk_mgr_base->bw_params->clk_table.num_entries - 1].memclk_mhz);
 	} else {
 		dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
-				clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz);
+				(uint16_t)clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz);
 	}
 }
 
@@ -382,7 +384,8 @@ static void dcn3_set_hard_max_memclk(struct clk_mgr *clk_mgr_base)
 		return;
 
 	dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK,
-			clk_mgr_base->bw_params->clk_table.entries[clk_mgr_base->bw_params->clk_table.num_entries - 1].memclk_mhz);
+			(uint16_t)clk_mgr_base->bw_params->clk_table.entries[
+				clk_mgr_base->bw_params->clk_table.num_entries - 1].memclk_mhz);
 }
 
 static void dcn3_set_max_memclk(struct clk_mgr *clk_mgr_base, unsigned int memclk_mhz)
@@ -392,7 +395,7 @@ static void dcn3_set_max_memclk(struct clk_mgr *clk_mgr_base, unsigned int memcl
 	if (!clk_mgr->smu_present)
 		return;
 
-	dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK, memclk_mhz);
+	dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK, (uint16_t)memclk_mhz);
 }
 static void dcn3_set_min_memclk(struct clk_mgr *clk_mgr_base, unsigned int memclk_mhz)
 {
@@ -400,14 +403,14 @@ static void dcn3_set_min_memclk(struct clk_mgr *clk_mgr_base, unsigned int memcl
 
 	if (!clk_mgr->smu_present)
 		return;
-	dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, memclk_mhz);
+	dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, (uint16_t)memclk_mhz);
 }
 
 /* Get current memclk states, update bounding box */
 static void dcn3_get_memclk_states_from_smu(struct clk_mgr *clk_mgr_base)
 {
 	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
-	unsigned int num_levels;
+	uint8_t num_levels;
 
 	if (!clk_mgr->smu_present)
 		return;
@@ -480,7 +483,7 @@ static void dcn30_notify_link_rate_change(struct clk_mgr *clk_mgr_base, struct d
 
 	if (max_phyclk_req != clk_mgr_base->clks.phyclk_khz) {
 		clk_mgr_base->clks.phyclk_khz = max_phyclk_req;
-		dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_PHYCLK, khz_to_mhz_ceil(clk_mgr_base->clks.phyclk_khz));
+		dcn30_smu_set_hard_min_by_freq(clk_mgr, PPCLK_PHYCLK, (uint16_t)khz_to_mhz_ceil(clk_mgr_base->clks.phyclk_khz));
 	}
 }
 
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c
index 57ba7bc4d16e..70f6f0913f13 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/vg_clk_mgr.c
@@ -385,7 +385,7 @@ static void vg_init_clocks(struct clk_mgr *clk_mgr)
 
 static void vg_build_watermark_ranges(struct clk_bw_params *bw_params, struct watermarks *table)
 {
-	int i, num_valid_sets;
+	uint8_t i, num_valid_sets;
 
 	num_valid_sets = 0;
 
@@ -394,8 +394,11 @@ static void vg_build_watermark_ranges(struct clk_bw_params *bw_params, struct wa
 		if (!bw_params->wm_table.entries[i].valid)
 			continue;
 
-		table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst;
-		table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type;
+
+		table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting =
+			(uint8_t)bw_params->wm_table.entries[i].wm_inst;
+		table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType =
+			(uint8_t)bw_params->wm_table.entries[i].wm_type;
 		/* We will not select WM based on fclk, so leave it as unconstrained */
 		table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
 		table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
@@ -406,10 +409,10 @@ static void vg_build_watermark_ranges(struct clk_bw_params *bw_params, struct wa
 			else {
 				/* add 1 to make it non-overlapping with next lvl */
 				table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk =
-						bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1;
+						(uint16_t)(bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1);
 			}
 			table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk =
-					bw_params->clk_table.entries[i].dcfclk_mhz;
+					(uint16_t)bw_params->clk_table.entries[i].dcfclk_mhz;
 
 		} else {
 			/* unconstrained for memory retraining */
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
index 89fc482947ef..68a121dbb489 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn31/dcn31_clk_mgr.c
@@ -114,7 +114,7 @@ static int dcn31_get_active_display_cnt_wa(
 static void dcn31_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, bool disable)
 {
 	struct dc *dc = clk_mgr_base->ctx->dc;
-	int i;
+	uint8_t i;
 
 	for (i = 0; i < dc->res_pool->pipe_count; ++i) {
 		struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
@@ -424,7 +424,7 @@ static struct dcn31_watermarks dummy_wms = { 0 };
 
 static void dcn31_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn31_watermarks *table)
 {
-	int i, num_valid_sets;
+	uint8_t i, num_valid_sets;
 
 	num_valid_sets = 0;
 
@@ -433,8 +433,10 @@ static void dcn31_build_watermark_ranges(struct clk_bw_params *bw_params, struct
 		if (!bw_params->wm_table.entries[i].valid)
 			continue;
 
-		table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst;
-		table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type;
+		table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting =
+			(uint8_t)bw_params->wm_table.entries[i].wm_inst;
+		table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType =
+			(uint8_t)bw_params->wm_table.entries[i].wm_type;
 		/* We will not select WM based on fclk, so leave it as unconstrained */
 		table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
 		table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
@@ -445,10 +447,10 @@ static void dcn31_build_watermark_ranges(struct clk_bw_params *bw_params, struct
 			else {
 				/* add 1 to make it non-overlapping with next lvl */
 				table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk =
-						bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1;
+						(uint16_t)(bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1);
 			}
 			table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk =
-					bw_params->clk_table.entries[i].dcfclk_mhz;
+					(uint16_t)bw_params->clk_table.entries[i].dcfclk_mhz;
 
 		} else {
 			/* unconstrained for memory retraining */
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c
index b08a70a2f571..0d5892266112 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn314/dcn314_clk_mgr.c
@@ -149,7 +149,7 @@ static void dcn314_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state
 				  bool safe_to_lower, bool disable)
 {
 	struct dc *dc = clk_mgr_base->ctx->dc;
-	int i;
+	uint8_t i;
 
 	for (i = 0; i < dc->res_pool->pipe_count; ++i) {
 		struct pipe_ctx *pipe = safe_to_lower
@@ -495,7 +495,7 @@ static struct dcn314_ss_info_table ss_info_table = {
 
 static void dcn314_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn314_watermarks *table)
 {
-	int i, num_valid_sets;
+	uint8_t i, num_valid_sets;
 
 	num_valid_sets = 0;
 
@@ -504,8 +504,10 @@ static void dcn314_build_watermark_ranges(struct clk_bw_params *bw_params, struc
 		if (!bw_params->wm_table.entries[i].valid)
 			continue;
 
-		table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst;
-		table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type;
+		table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting =
+			(uint8_t)bw_params->wm_table.entries[i].wm_inst;
+		table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType =
+			(uint8_t)bw_params->wm_table.entries[i].wm_type;
 		/* We will not select WM based on fclk, so leave it as unconstrained */
 		table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
 		table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
@@ -516,10 +518,10 @@ static void dcn314_build_watermark_ranges(struct clk_bw_params *bw_params, struc
 			else {
 				/* add 1 to make it non-overlapping with next lvl */
 				table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk =
-						bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1;
+						(uint16_t)(bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1);
 			}
 			table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk =
-					bw_params->clk_table.entries[i].dcfclk_mhz;
+					(uint16_t)bw_params->clk_table.entries[i].dcfclk_mhz;
 
 		} else {
 			/* unconstrained for memory retraining */
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
index 3a651c1a866d..ef184f28e426 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn315/dcn315_clk_mgr.c
@@ -100,7 +100,7 @@ static bool should_disable_otg(struct pipe_ctx *pipe)
 static void dcn315_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context, bool disable)
 {
 	struct dc *dc = clk_mgr_base->ctx->dc;
-	int i;
+	uint8_t i;
 
 	for (i = 0; i < dc->res_pool->pipe_count; ++i) {
 		struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
@@ -384,7 +384,7 @@ static struct dcn315_watermarks dummy_wms = { 0 };
 
 static void dcn315_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn315_watermarks *table)
 {
-	int i, num_valid_sets;
+	uint8_t i, num_valid_sets;
 
 	num_valid_sets = 0;
 
@@ -393,8 +393,11 @@ static void dcn315_build_watermark_ranges(struct clk_bw_params *bw_params, struc
 		if (!bw_params->wm_table.entries[i].valid)
 			continue;
 
-		table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst;
-		table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type;
+
+		table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting =
+			(uint8_t)bw_params->wm_table.entries[i].wm_inst;
+		table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType =
+			(uint8_t)bw_params->wm_table.entries[i].wm_type;
 		/* We will not select WM based on fclk, so leave it as unconstrained */
 		table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
 		table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
@@ -405,10 +408,10 @@ static void dcn315_build_watermark_ranges(struct clk_bw_params *bw_params, struc
 			else {
 				/* add 1 to make it non-overlapping with next lvl */
 				table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk =
-						bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1;
+						(uint16_t)(bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1);
 			}
 			table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk =
-					bw_params->clk_table.entries[i].dcfclk_mhz;
+					(uint16_t)bw_params->clk_table.entries[i].dcfclk_mhz;
 
 		} else {
 			/* unconstrained for memory retraining */
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c
index e9d492d8c8d4..aa8f2a5edc21 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn316/dcn316_clk_mgr.c
@@ -103,7 +103,7 @@ static void dcn316_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state
 		bool safe_to_lower, bool disable)
 {
 	struct dc *dc = clk_mgr_base->ctx->dc;
-	int i;
+	uint8_t i;
 
 	for (i = 0; i < dc->res_pool->pipe_count; ++i) {
 		struct pipe_ctx *pipe = safe_to_lower
@@ -350,7 +350,7 @@ static struct dcn316_watermarks dummy_wms = { 0 };
 
 static void dcn316_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn316_watermarks *table)
 {
-	int i, num_valid_sets;
+	uint8_t i, num_valid_sets;
 
 	num_valid_sets = 0;
 
@@ -359,8 +359,11 @@ static void dcn316_build_watermark_ranges(struct clk_bw_params *bw_params, struc
 		if (!bw_params->wm_table.entries[i].valid)
 			continue;
 
-		table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst;
-		table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type;
+
+		table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting =
+			(uint8_t)bw_params->wm_table.entries[i].wm_inst;
+		table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType =
+			(uint8_t)bw_params->wm_table.entries[i].wm_type;
 		/* We will not select WM based on fclk, so leave it as unconstrained */
 		table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
 		table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
@@ -371,10 +374,10 @@ static void dcn316_build_watermark_ranges(struct clk_bw_params *bw_params, struc
 			else {
 				/* add 1 to make it non-overlapping with next lvl */
 				table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk =
-						bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1;
+						(uint16_t)(bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1);
 			}
 			table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk =
-					bw_params->clk_table.entries[i].dcfclk_mhz;
+					(uint16_t)bw_params->clk_table.entries[i].dcfclk_mhz;
 
 		} else {
 			/* unconstrained for memory retraining */
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
index fda6cade30a8..c27f31250246 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
@@ -132,7 +132,7 @@ static const struct clk_mgr_mask clk_mgr_mask_dcn321 = {
 static void dcn32_init_single_clock(struct clk_mgr_internal *clk_mgr, PPCLK_e clk, unsigned int *entry_0,
 		unsigned int *num_levels)
 {
-	unsigned int i;
+	uint8_t i;
 	char *entry_i = (char *)entry_0;
 
 	uint32_t ret = dcn30_smu_get_dpm_freq_by_index(clk_mgr, clk, 0xFF);
@@ -409,7 +409,7 @@ static void dcn32_update_clocks_update_dentist(
 			 * floored in Mhz to describe the intended clock.
 			 */
 			dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DISPCLK,
-					khz_to_mhz_floor(temp_dispclk_khz));
+					(uint16_t)khz_to_mhz_floor(temp_dispclk_khz));
 
 		if (dc->debug.override_dispclk_programming) {
 			REG_GET(DENTIST_DISPCLK_CNTL,
@@ -456,7 +456,7 @@ static void dcn32_update_clocks_update_dentist(
 		 * floored in Mhz to describe the intended clock.
 		 */
 		dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DISPCLK,
-				khz_to_mhz_floor(clk_mgr->base.clks.dispclk_khz));
+				(uint16_t)khz_to_mhz_floor(clk_mgr->base.clks.dispclk_khz));
 
 	if (dc->debug.override_dispclk_programming) {
 		REG_GET(DENTIST_DISPCLK_CNTL,
@@ -680,7 +680,7 @@ static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base,
 		if (should_set_clock(safe_to_lower, new_clocks->dcfclk_khz, clk_mgr_base->clks.dcfclk_khz) &&
 				!dc->work_arounds.clock_update_disable_mask.dcfclk) {
 			clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
-			dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DCFCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz));
+			dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DCFCLK, (uint16_t)khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz));
 		}
 
 		if (should_set_clock(safe_to_lower, new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz) &&
@@ -715,13 +715,13 @@ static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base,
 					 * frequency.
 					 */
 					if (dc->debug.disable_dc_mode_overwrite) {
-						dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK, dc->clk_mgr->bw_params->max_memclk_mhz);
-						dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, dc->clk_mgr->bw_params->max_memclk_mhz);
+						dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK, (uint16_t)dc->clk_mgr->bw_params->max_memclk_mhz);
+						dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, (uint16_t)dc->clk_mgr->bw_params->max_memclk_mhz);
 					} else
 						dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
-								dc->clk_mgr->bw_params->dc_mode_softmax_memclk);
+								(uint16_t)dc->clk_mgr->bw_params->dc_mode_softmax_memclk);
 				} else {
-					dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, dc->clk_mgr->bw_params->max_memclk_mhz);
+					dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, (uint16_t)dc->clk_mgr->bw_params->max_memclk_mhz);
 				}
 			}
 		}
@@ -755,9 +755,10 @@ static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base,
 				!dc->work_arounds.clock_update_disable_mask.uclk) {
 			if (dc->clk_mgr->dc_mode_softmax_enabled && dc->debug.disable_dc_mode_overwrite)
 				dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK,
-						max((int)dc->clk_mgr->bw_params->dc_mode_softmax_memclk, khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz)));
+						(uint16_t)max((int)dc->clk_mgr->bw_params->dc_mode_softmax_memclk,
+								khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz)));
 
-			dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz));
+			dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, (uint16_t)khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz));
 		}
 
 		if (clk_mgr_base->clks.num_ways != new_clocks->num_ways &&
@@ -783,7 +784,7 @@ static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base,
 			 * floored in Mhz to describe the intended clock.
 			 */
 			dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DPPCLK,
-					khz_to_mhz_floor(clk_mgr_base->clks.dppclk_khz));
+					(uint16_t)khz_to_mhz_floor(clk_mgr_base->clks.dppclk_khz));
 
 		update_dppclk = true;
 	}
@@ -803,7 +804,7 @@ static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base,
 			should_set_clock(safe_to_lower, new_clocks->ref_dtbclk_khz / 1000, clk_mgr_base->clks.ref_dtbclk_khz / 1000)) {
 		/* DCCG requires KHz precision for DTBCLK */
 		clk_mgr_base->clks.ref_dtbclk_khz =
-				dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DTBCLK, khz_to_mhz_ceil(new_clocks->ref_dtbclk_khz));
+				dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DTBCLK, (uint16_t)khz_to_mhz_ceil(new_clocks->ref_dtbclk_khz));
 
 		dcn32_update_clocks_update_dtb_dto(clk_mgr, context, clk_mgr_base->clks.ref_dtbclk_khz);
 	}
@@ -822,7 +823,7 @@ static void dcn32_update_clocks(struct clk_mgr *clk_mgr_base,
 				 * floored in Mhz to describe the intended clock.
 				 */
 				dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_DPPCLK,
-						khz_to_mhz_floor(clk_mgr_base->clks.dppclk_khz));
+						(uint16_t)khz_to_mhz_floor(clk_mgr_base->clks.dppclk_khz));
 		} else {
 			/* if clock is being raised, increase refclk before lowering DTO */
 			if (update_dppclk || update_dispclk)
@@ -968,7 +969,7 @@ static void dcn32_clock_read_ss_info(struct clk_mgr_internal *clk_mgr)
 }
 static void dcn32_notify_wm_ranges(struct clk_mgr *clk_mgr_base)
 {
-	unsigned int i;
+	uint8_t i;
 	struct clk_mgr_internal *clk_mgr = TO_CLK_MGR_INTERNAL(clk_mgr_base);
 	WatermarksExternal_t *table = (WatermarksExternal_t *) clk_mgr->wm_range_table;
 
@@ -1002,13 +1003,13 @@ static void dcn32_set_hard_min_memclk(struct clk_mgr *clk_mgr_base, bool current
 	if (current_mode) {
 		if (clk_mgr_base->clks.p_state_change_support)
 			dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
-					khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz));
+					(uint16_t)khz_to_mhz_ceil(clk_mgr_base->clks.dramclk_khz));
 		else
 			dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
-					clk_mgr_base->bw_params->max_memclk_mhz);
+					(uint16_t)clk_mgr_base->bw_params->max_memclk_mhz);
 	} else {
 		dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK,
-				clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz);
+				(uint16_t)clk_mgr_base->bw_params->clk_table.entries[0].memclk_mhz);
 	}
 }
 
@@ -1020,7 +1021,7 @@ static void dcn32_set_hard_max_memclk(struct clk_mgr *clk_mgr_base)
 	if (!clk_mgr->smu_present)
 		return;
 
-	dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK, clk_mgr_base->bw_params->max_memclk_mhz);
+	dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK, (uint16_t)clk_mgr_base->bw_params->max_memclk_mhz);
 }
 
 /* Get current memclk states, update bounding box */
@@ -1052,7 +1053,7 @@ static void dcn32_get_memclk_states_from_smu(struct clk_mgr *clk_mgr_base)
 
 	clk_mgr_base->bw_params->max_memclk_mhz =
 			clk_mgr_base->bw_params->clk_table.entries[num_entries_per_clk->num_memclk_levels - 1].memclk_mhz;
-	clk_mgr_base->bw_params->clk_table.num_entries = num_levels ? num_levels : 1;
+	clk_mgr_base->bw_params->clk_table.num_entries = (uint8_t)(num_levels ? num_levels : 1);
 
 	if (clk_mgr->dpm_present && !num_levels)
 		clk_mgr->dpm_present = false;
@@ -1109,7 +1110,7 @@ static void dcn32_set_max_memclk(struct clk_mgr *clk_mgr_base, unsigned int memc
 	if (!clk_mgr->smu_present)
 		return;
 
-	dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK, memclk_mhz);
+	dcn30_smu_set_hard_max_by_freq(clk_mgr, PPCLK_UCLK, (uint16_t)memclk_mhz);
 }
 
 static void dcn32_set_min_memclk(struct clk_mgr *clk_mgr_base, unsigned int memclk_mhz)
@@ -1119,7 +1120,7 @@ static void dcn32_set_min_memclk(struct clk_mgr *clk_mgr_base, unsigned int memc
 	if (!clk_mgr->smu_present)
 		return;
 
-	dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, memclk_mhz);
+	dcn32_smu_set_hard_min_by_freq(clk_mgr, PPCLK_UCLK, (uint16_t)memclk_mhz);
 }
 
 static struct clk_mgr_funcs dcn32_funcs = {
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
index 2798088842f4..ddcde2433211 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c
@@ -190,7 +190,7 @@ void dcn35_disable_otg_wa(struct clk_mgr *clk_mgr_base, struct dc_state *context
 		bool safe_to_lower, bool disable)
 {
 	struct dc *dc = clk_mgr_base->ctx->dc;
-	int i;
+	uint8_t i;
 
 	if (dc->ctx->dce_environment == DCE_ENV_DIAG)
 		return;
@@ -332,7 +332,7 @@ static uint8_t get_lowest_dpia_index(const struct dc_link *link)
 			continue;
 
 		if (idx > dc_struct->links[i]->link_index)
-			idx = dc_struct->links[i]->link_index;
+			idx = (uint8_t)dc_struct->links[i]->link_index;
 	}
 
 	return idx;
@@ -863,7 +863,7 @@ static void dcn35_read_ss_info_from_lut(struct clk_mgr_internal *clk_mgr)
 
 static void dcn35_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn35_watermarks *table)
 {
-	int i, num_valid_sets;
+	uint8_t i, num_valid_sets;
 
 	num_valid_sets = 0;
 
@@ -872,8 +872,10 @@ static void dcn35_build_watermark_ranges(struct clk_bw_params *bw_params, struct
 		if (!bw_params->wm_table.entries[i].valid)
 			continue;
 
-		table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst;
-		table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type;
+		table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting =
+			(uint8_t)bw_params->wm_table.entries[i].wm_inst;
+		table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType =
+			(uint8_t)bw_params->wm_table.entries[i].wm_type;
 		/* We will not select WM based on fclk, so leave it as unconstrained */
 		table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
 		table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
@@ -884,10 +886,10 @@ static void dcn35_build_watermark_ranges(struct clk_bw_params *bw_params, struct
 			else {
 				/* add 1 to make it non-overlapping with next lvl */
 				table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk =
-						bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1;
+						(uint16_t)(bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1);
 			}
 			table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk =
-					bw_params->clk_table.entries[i].dcfclk_mhz;
+					(uint16_t)bw_params->clk_table.entries[i].dcfclk_mhz;
 
 		} else {
 			/* unconstrained for memory retraining */
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
index 82c1a55a2271..944e9ad6982a 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn401/dcn401_clk_mgr.c
@@ -174,7 +174,7 @@ static void dcn401_init_single_clock(struct clk_mgr_internal *clk_mgr, PPCLK_e c
 
 	/* if the initial message failed, num_levels will be 0 */
 	for (i = 0; i < *num_levels && i < ARRAY_SIZE(clk_mgr->base.bw_params->clk_table.entries); i++) {
-		*((unsigned int *)entry_i) = (dcn401_smu_get_dpm_freq_by_index(clk_mgr, clk, i) & 0xFFFF);
+		*((unsigned int *)entry_i) = (dcn401_smu_get_dpm_freq_by_index(clk_mgr, clk, (uint8_t)i) & 0xFFFF);
 		entry_i += sizeof(clk_mgr->base.bw_params->clk_table.entries[0]);
 	}
 }
@@ -182,15 +182,15 @@ static void dcn401_init_single_clock(struct clk_mgr_internal *clk_mgr, PPCLK_e c
 static void dcn401_build_wm_range_table(struct clk_mgr *clk_mgr)
 {
 	/* For min clocks use as reported by PM FW and report those as min */
-	uint16_t min_uclk_mhz = clk_mgr->bw_params->clk_table.entries[0].memclk_mhz;
-	uint16_t min_dcfclk_mhz	= clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz;
+	unsigned int min_uclk_mhz = clk_mgr->bw_params->clk_table.entries[0].memclk_mhz;
+	unsigned int min_dcfclk_mhz = clk_mgr->bw_params->clk_table.entries[0].dcfclk_mhz;
 
 	/* Set A - Normal - default values */
 	clk_mgr->bw_params->wm_table.nv_entries[WM_A].valid = true;
 	clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.wm_type = WATERMARKS_CLOCK_RANGE;
-	clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz;
+	clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_dcfclk = (uint16_t)min_dcfclk_mhz;
 	clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_dcfclk = 0xFFFF;
-	clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_uclk = min_uclk_mhz;
+	clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.min_uclk = (uint16_t)min_uclk_mhz;
 	clk_mgr->bw_params->wm_table.nv_entries[WM_A].pmfw_breakdown.max_uclk = 0xFFFF;
 
 	/* Set B - Unused on dcn4 */
@@ -201,9 +201,9 @@ static void dcn401_build_wm_range_table(struct clk_mgr *clk_mgr)
 	if (clk_mgr->ctx->dc->bb_overrides.dummy_clock_change_latency_ns != 0x7FFFFFFF) {
 		clk_mgr->bw_params->wm_table.nv_entries[WM_1A].valid = true;
 		clk_mgr->bw_params->wm_table.nv_entries[WM_1A].pmfw_breakdown.wm_type = WATERMARKS_DUMMY_PSTATE;
-		clk_mgr->bw_params->wm_table.nv_entries[WM_1A].pmfw_breakdown.min_dcfclk = min_dcfclk_mhz;
+		clk_mgr->bw_params->wm_table.nv_entries[WM_1A].pmfw_breakdown.min_dcfclk = (uint16_t)min_dcfclk_mhz;
 		clk_mgr->bw_params->wm_table.nv_entries[WM_1A].pmfw_breakdown.max_dcfclk = 0xFFFF;
-		clk_mgr->bw_params->wm_table.nv_entries[WM_1A].pmfw_breakdown.min_uclk = min_uclk_mhz;
+		clk_mgr->bw_params->wm_table.nv_entries[WM_1A].pmfw_breakdown.min_uclk = (uint16_t)min_uclk_mhz;
 		clk_mgr->bw_params->wm_table.nv_entries[WM_1A].pmfw_breakdown.max_uclk = 0xFFFF;
 	} else {
 		clk_mgr->bw_params->wm_table.nv_entries[WM_1A].valid = false;
@@ -604,10 +604,10 @@ static int dcn401_set_hard_min_by_freq_optimized(struct clk_mgr_internal *clk_mg
 	 * clock returned is less than requested, then we will ceil the
 	 * requested value to mhz and call it again.
 	 */
-	int actual_clk_khz = dcn401_smu_set_hard_min_by_freq(clk_mgr, clk, khz_to_mhz_floor(requested_clk_khz));
+	int actual_clk_khz = dcn401_smu_set_hard_min_by_freq(clk_mgr, clk, (uint16_t)khz_to_mhz_floor(requested_clk_khz));
 
 	if (actual_clk_khz < requested_clk_khz)
-		actual_clk_khz = dcn401_smu_set_hard_min_by_freq(clk_mgr, clk, khz_to_mhz_ceil(requested_clk_khz));
+		actual_clk_khz = dcn401_smu_set_hard_min_by_freq(clk_mgr, clk, (uint16_t)khz_to_mhz_ceil(requested_clk_khz));
 
 	return actual_clk_khz;
 }
@@ -849,7 +849,7 @@ static unsigned int dcn401_build_update_bandwidth_clocks_sequence(
 		clk_mgr_base->clks.dcfclk_khz = new_clocks->dcfclk_khz;
 		if (dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_DCFCLK)) {
 			block_sequence[num_steps].params.update_hardmin_params.ppclk = PPCLK_DCFCLK;
-			block_sequence[num_steps].params.update_hardmin_params.freq_mhz = khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz);
+			block_sequence[num_steps].params.update_hardmin_params.freq_mhz = (uint16_t)khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_khz);
 			block_sequence[num_steps].params.update_hardmin_params.response = NULL;
 			block_sequence[num_steps].func = CLK_MGR401_UPDATE_HARDMIN_PPCLK;
 			num_steps++;
@@ -860,7 +860,7 @@ static unsigned int dcn401_build_update_bandwidth_clocks_sequence(
 	if (should_set_clock(safe_to_lower, new_clocks->dcfclk_deep_sleep_khz, clk_mgr_base->clks.dcfclk_deep_sleep_khz)) {
 		clk_mgr_base->clks.dcfclk_deep_sleep_khz = new_clocks->dcfclk_deep_sleep_khz;
 		if (dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_DCFCLK)) {
-			block_sequence[num_steps].params.update_deep_sleep_dcfclk_params.freq_mhz = khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_deep_sleep_khz);
+			block_sequence[num_steps].params.update_deep_sleep_dcfclk_params.freq_mhz = (uint16_t)khz_to_mhz_ceil(clk_mgr_base->clks.dcfclk_deep_sleep_khz);
 			block_sequence[num_steps].func = CLK_MGR401_UPDATE_DEEP_SLEEP_DCFCLK;
 			num_steps++;
 		}
@@ -984,24 +984,24 @@ static unsigned int dcn401_build_update_bandwidth_clocks_sequence(
 	/* When idle DPM is enabled, need to send active and idle hardmins separately */
 	/* CLK_MGR401_UPDATE_ACTIVE_HARDMINS */
 	if ((update_active_uclk || update_active_fclk) && is_idle_dpm_enabled) {
-		block_sequence[num_steps].params.update_idle_hardmin_params.uclk_mhz = active_uclk_mhz;
-		block_sequence[num_steps].params.update_idle_hardmin_params.fclk_mhz = active_fclk_mhz;
+		block_sequence[num_steps].params.update_idle_hardmin_params.uclk_mhz = (uint16_t)active_uclk_mhz;
+		block_sequence[num_steps].params.update_idle_hardmin_params.fclk_mhz = (uint16_t)active_fclk_mhz;
 		block_sequence[num_steps].func = CLK_MGR401_UPDATE_ACTIVE_HARDMINS;
 		num_steps++;
 	}
 
 	/* CLK_MGR401_UPDATE_IDLE_HARDMINS */
 	if ((update_idle_uclk || update_idle_fclk) && is_idle_dpm_enabled) {
-		block_sequence[num_steps].params.update_idle_hardmin_params.uclk_mhz = idle_uclk_mhz;
-		block_sequence[num_steps].params.update_idle_hardmin_params.fclk_mhz = idle_fclk_mhz;
+		block_sequence[num_steps].params.update_idle_hardmin_params.uclk_mhz = (uint16_t)idle_uclk_mhz;
+		block_sequence[num_steps].params.update_idle_hardmin_params.fclk_mhz = (uint16_t)idle_fclk_mhz;
 		block_sequence[num_steps].func = CLK_MGR401_UPDATE_IDLE_HARDMINS;
 		num_steps++;
 	}
 
 	/* CLK_MGR401_UPDATE_SUBVP_HARDMINS */
 	if ((update_subvp_prefetch_dramclk || update_subvp_prefetch_fclk) && is_df_throttle_opt_enabled) {
-		block_sequence[num_steps].params.update_idle_hardmin_params.uclk_mhz = subvp_prefetch_dramclk_mhz;
-		block_sequence[num_steps].params.update_idle_hardmin_params.fclk_mhz = subvp_prefetch_fclk_mhz;
+		block_sequence[num_steps].params.update_idle_hardmin_params.uclk_mhz = (uint16_t)subvp_prefetch_dramclk_mhz;
+		block_sequence[num_steps].params.update_idle_hardmin_params.fclk_mhz = (uint16_t)subvp_prefetch_fclk_mhz;
 		block_sequence[num_steps].func = CLK_MGR401_UPDATE_SUBVP_HARDMINS;
 		num_steps++;
 	}
@@ -1010,7 +1010,7 @@ static unsigned int dcn401_build_update_bandwidth_clocks_sequence(
 	if (update_active_uclk || update_idle_uclk) {
 		if (!is_idle_dpm_enabled) {
 			block_sequence[num_steps].params.update_hardmin_params.ppclk = PPCLK_UCLK;
-			block_sequence[num_steps].params.update_hardmin_params.freq_mhz = active_uclk_mhz;
+			block_sequence[num_steps].params.update_hardmin_params.freq_mhz = (uint16_t)active_uclk_mhz;
 			block_sequence[num_steps].params.update_hardmin_params.response = NULL;
 			block_sequence[num_steps].func = CLK_MGR401_UPDATE_HARDMIN_PPCLK;
 			num_steps++;
@@ -1123,7 +1123,7 @@ static unsigned int dcn401_build_update_display_clocks_sequence(
 			dcn401_is_ppclk_dpm_enabled(clk_mgr_internal, PPCLK_DTBCLK)) {
 		/* DCCG requires KHz precision for DTBCLK */
 		block_sequence[num_steps].params.update_hardmin_params.ppclk = PPCLK_DTBCLK;
-		block_sequence[num_steps].params.update_hardmin_params.freq_mhz = khz_to_mhz_ceil(new_clocks->ref_dtbclk_khz);
+		block_sequence[num_steps].params.update_hardmin_params.freq_mhz = (uint16_t)khz_to_mhz_ceil(new_clocks->ref_dtbclk_khz);
 		block_sequence[num_steps].params.update_hardmin_params.response = &clk_mgr_base->clks.ref_dtbclk_khz;
 		block_sequence[num_steps].func = CLK_MGR401_UPDATE_HARDMIN_PPCLK;
 		num_steps++;
@@ -1318,7 +1318,7 @@ static void dcn401_notify_wm_ranges(struct clk_mgr *clk_mgr_base)
 	/* collect valid ranges, place in pmfw table */
 	for (i = 0; i < WM_SET_COUNT; i++)
 		if (clk_mgr->base.bw_params->wm_table.nv_entries[i].valid) {
-			table->Watermarks.WatermarkRow[i].WmSetting = i;
+			table->Watermarks.WatermarkRow[i].WmSetting = (uint8_t)i;
 			table->Watermarks.WatermarkRow[i].Flags = clk_mgr->base.bw_params->wm_table.nv_entries[i].pmfw_breakdown.wm_type;
 		}
 	dcn401_smu_set_dram_addr_high(clk_mgr, clk_mgr->wm_range_table_addr >> 32);
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c
index 6a97ce69a562..a0cdaf69056e 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_clk_mgr.c
@@ -634,7 +634,7 @@ static void dcn42_read_ss_info_from_lut(struct clk_mgr_internal *clk_mgr)
 
 void dcn42_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn42_watermarks *table)
 {
-	int i, num_valid_sets;
+	uint8_t i, num_valid_sets;
 
 	num_valid_sets = 0;
 
@@ -643,8 +643,10 @@ void dcn42_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn42_
 		if (!bw_params->wm_table.entries[i].valid)
 			continue;
 
-		table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting = bw_params->wm_table.entries[i].wm_inst;
-		table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType = bw_params->wm_table.entries[i].wm_type;
+		table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmSetting =
+			(uint8_t)bw_params->wm_table.entries[i].wm_inst;
+		table->WatermarkRow[WM_DCFCLK][num_valid_sets].WmType =
+			(uint8_t)bw_params->wm_table.entries[i].wm_type;
 		/* We will not select WM based on fclk, so leave it as unconstrained */
 		table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinClock = 0;
 		table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxClock = 0xFFFF;
@@ -655,10 +657,10 @@ void dcn42_build_watermark_ranges(struct clk_bw_params *bw_params, struct dcn42_
 			else {
 				/* add 1 to make it non-overlapping with next lvl */
 				table->WatermarkRow[WM_DCFCLK][num_valid_sets].MinMclk =
-						bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1;
+						(uint16_t)(bw_params->clk_table.entries[i - 1].dcfclk_mhz + 1);
 			}
 			table->WatermarkRow[WM_DCFCLK][num_valid_sets].MaxMclk =
-					bw_params->clk_table.entries[i].dcfclk_mhz;
+					(uint16_t)bw_params->clk_table.entries[i].dcfclk_mhz;
 
 		} else {
 			/* unconstrained for memory retraining */
@@ -734,9 +736,12 @@ void dcn42_notify_wm_ranges(struct clk_mgr *clk_mgr_base)
 			clk_mgr_dcn42->smu_wm_set.mc_address.low_part);
 	dcn42_smu_transfer_wm_table_dram_2_smu(clk_mgr);
 
-	if (clk_mgr_dcn42->smu_wm_set.wm_set && clk_mgr_dcn42->smu_wm_set.mc_address.quad_part != 0)
+	if (clk_mgr_dcn42->smu_wm_set.wm_set && clk_mgr_dcn42->smu_wm_set.mc_address.quad_part != 0) {
 		dm_helpers_free_gpu_mem(clk_mgr->base.ctx, DC_MEM_ALLOC_TYPE_GART,
 				clk_mgr_dcn42->smu_wm_set.wm_set);
+		clk_mgr_dcn42->smu_wm_set.wm_set = NULL;
+		clk_mgr_dcn42->smu_wm_set.mc_address.quad_part = 0;
+	}
 
 }
 
@@ -1099,7 +1104,10 @@ void dcn42_clk_mgr_destroy(struct clk_mgr_internal *clk_mgr_int)
 {
 	struct clk_mgr_dcn42 *clk_mgr = TO_CLK_MGR_DCN42(clk_mgr_int);
 
-	if (clk_mgr->smu_wm_set.wm_set && clk_mgr->smu_wm_set.mc_address.quad_part != 0)
+	if (clk_mgr->smu_wm_set.wm_set && clk_mgr->smu_wm_set.mc_address.quad_part != 0) {
 		dm_helpers_free_gpu_mem(clk_mgr_int->base.ctx, DC_MEM_ALLOC_TYPE_GART,
 				clk_mgr->smu_wm_set.wm_set);
+		clk_mgr->smu_wm_set.wm_set = NULL;
+		clk_mgr->smu_wm_set.mc_address.quad_part = 0;
+	}
 }
diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c
index c791bb1edb47..6d0012b7d6dc 100644
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn42/dcn42_smu.c
@@ -428,4 +428,3 @@ void dcn42_smu_set_dtbclk(struct clk_mgr_internal *clk_mgr, bool enable)
 			enable);
 	smu_print("%s: smu_set_dtbclk = %d\n", __func__, enable ? 1 : 0);
 }
-
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index 419f894c87b0..c3f9ba454642 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -235,7 +235,7 @@ static bool create_links(
 	 *   variants of the same card.
 	 */
 	for (i = 0; dc->link_count < connectors_num && i < MAX_LINKS; i++) {
-		struct graphics_object_id connector_id = bios->funcs->get_connector_id(bios, i);
+		struct graphics_object_id connector_id = bios->funcs->get_connector_id(bios, (uint8_t)i);
 		struct link_init_data link_init_params = {0};
 		struct dc_link *link;
 
@@ -246,7 +246,7 @@ static bool create_links(
 
 		link_init_params.ctx = dc->ctx;
 		/* next BIOS object table connector */
-		link_init_params.connector_index = i;
+		link_init_params.connector_index = (uint8_t)i;
 		link_init_params.link_index = dc->link_count;
 		link_init_params.dc = dc;
 		link = dc->link_srv->create_link(&link_init_params);
@@ -267,7 +267,7 @@ static bool create_links(
 		struct dc_link *link;
 
 		link_init_params.ctx = dc->ctx;
-		link_init_params.connector_index = i;
+		link_init_params.connector_index = (uint8_t)i;
 		link_init_params.link_index = dc->link_count;
 		link_init_params.dc = dc;
 		link_init_params.is_dpia_link = true;
@@ -659,12 +659,12 @@ bool dc_stream_configure_crc(struct dc *dc, struct dc_stream_state *stream,
 	/* By default, capture the full frame */
 	param.windowa_x_start = 0;
 	param.windowa_y_start = 0;
-	param.windowa_x_end = pipe->stream->timing.h_addressable;
-	param.windowa_y_end = pipe->stream->timing.v_addressable;
+	param.windowa_x_end = (uint16_t)pipe->stream->timing.h_addressable;
+	param.windowa_y_end = (uint16_t)pipe->stream->timing.v_addressable;
 	param.windowb_x_start = 0;
 	param.windowb_y_start = 0;
-	param.windowb_x_end = pipe->stream->timing.h_addressable;
-	param.windowb_y_end = pipe->stream->timing.v_addressable;
+	param.windowb_x_end = (uint16_t)pipe->stream->timing.h_addressable;
+	param.windowb_y_end = (uint16_t)pipe->stream->timing.v_addressable;
 	param.crc_poly_mode = crc_poly_mode;
 
 	if (crc_window) {
@@ -2137,7 +2137,7 @@ static uint8_t get_stream_mask(struct dc *dc, struct dc_state *context)
 			stream_mask |= 1 << i;
 	}
 
-	return stream_mask;
+	return (uint8_t)stream_mask;
 }
 
 void dc_z10_restore(const struct dc *dc)
@@ -2482,7 +2482,7 @@ enum dc_status dc_commit_streams(struct dc *dc, struct dc_commit_streams_params
 		set[i].stream = stream;
 
 		if (status) {
-			set[i].plane_count = status->plane_count;
+			set[i].plane_count = (uint8_t)status->plane_count;
 			for (j = 0; j < status->plane_count; j++)
 				set[i].plane_states[j] = status->plane_states[j];
 		}
@@ -2541,7 +2541,7 @@ enum dc_status dc_commit_streams(struct dc *dc, struct dc_commit_streams_params
 	for (i = 0; i < params->stream_count; i++) {
 		for (j = 0; j < context->stream_count; j++) {
 			if (params->streams[i]->stream_id == context->streams[j]->stream_id)
-				params->streams[i]->out.otg_offset = context->stream_status[j].primary_otg_inst;
+				params->streams[i]->out.otg_offset = (uint8_t)context->stream_status[j].primary_otg_inst;
 
 			if (dc_is_embedded_signal(params->streams[i]->signal)) {
 				struct dc_stream_status *status = dc_state_get_stream_status(context, params->streams[i]);
@@ -2669,7 +2669,7 @@ void dc_post_update_surfaces_to_stream(struct dc *dc)
 		for (i = 0; i < dc->res_pool->pipe_count; i++)
 			if (context->res_ctx.pipe_ctx[i].stream == NULL ||
 					context->res_ctx.pipe_ctx[i].plane_state == NULL) {
-				context->res_ctx.pipe_ctx[i].pipe_idx = i;
+				context->res_ctx.pipe_ctx[i].pipe_idx = (uint8_t)i;
 				dc->hwss.disable_plane(dc, context, &context->res_ctx.pipe_ctx[i]);
 			}
 
@@ -2946,6 +2946,11 @@ static struct surface_update_descriptor det_surface_update(
 		elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM);
 	}
 
+	if (u->cursor_csc_color_matrix) {
+		update_flags->bits.cursor_csc_color_matrix_change = 1;
+		elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM);
+	}
+
 	if (u->coeff_reduction_factor) {
 		update_flags->bits.coeff_reduction_change = 1;
 		elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM);
@@ -3073,7 +3078,7 @@ static struct surface_update_descriptor check_update_surfaces_for_stream(
 			elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL | LOCK_DESCRIPTOR_LINK);
 		}
 
-		if (stream_update->gamut_remap)
+		if (check_config->enable_legacy_fast_update && stream_update->gamut_remap)
 			su_flags->bits.gamut_remap = 1;
 
 		if (stream_update->wb_update)
@@ -3104,6 +3109,29 @@ static struct surface_update_descriptor check_update_surfaces_for_stream(
 			elevate_update_type(&overall_type, UPDATE_TYPE_FULL, LOCK_DESCRIPTOR_GLOBAL);
 
 		// Non-global cases
+
+		if (stream_update->gamut_remap) {
+			su_flags->bits.gamut_remap = 1;
+			elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM);
+		}
+
+		if ((stream_update->hdr_static_metadata && !stream_update->stream->use_dynamic_meta) ||
+				stream_update->vrr_infopacket ||
+				stream_update->vsc_infopacket ||
+				stream_update->vsp_infopacket ||
+				stream_update->hfvsif_infopacket ||
+				stream_update->adaptive_sync_infopacket ||
+				stream_update->vtem_infopacket ||
+				stream_update->avi_infopacket) {
+			su_flags->bits.info_frame = 1;
+			elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM);
+		}
+
+		if (stream_update->hdr_static_metadata && stream_update->stream->use_dynamic_meta) {
+			su_flags->bits.dmdata = 1;
+			elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM);
+		}
+
 		if (stream_update->output_csc_transform) {
 			su_flags->bits.out_csc = 1;
 			elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM);
@@ -3113,6 +3141,26 @@ static struct surface_update_descriptor check_update_surfaces_for_stream(
 			su_flags->bits.out_tf = 1;
 			elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM);
 		}
+
+		if (stream_update->periodic_interrupt) {
+			su_flags->bits.periodic_interrupt = 1;
+			elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM);
+		}
+
+		if (stream_update->dither_option) {
+			su_flags->bits.dither = 1;
+			elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM);
+		}
+
+		if (stream_update->cursor_attributes) {
+			su_flags->bits.cursor_attr = 1;
+			elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM);
+		}
+
+		if (stream_update->cursor_position) {
+			su_flags->bits.cursor_pos = 1;
+			elevate_update_type(&overall_type, UPDATE_TYPE_FAST, LOCK_DESCRIPTOR_STREAM);
+		}
 	}
 
 	for (int i = 0 ; i < surface_count; i++) {
@@ -3170,10 +3218,10 @@ static void copy_surface_update_to_plane(
 		surface->flip_immediate =
 			srf_update->flip_addr->flip_immediate;
 		surface->time.time_elapsed_in_us[surface->time.index] =
-			srf_update->flip_addr->flip_timestamp_in_us -
-				surface->time.prev_update_time_in_us;
+			(unsigned int)(srf_update->flip_addr->flip_timestamp_in_us -
+				surface->time.prev_update_time_in_us);
 		surface->time.prev_update_time_in_us =
-			srf_update->flip_addr->flip_timestamp_in_us;
+			(unsigned int)srf_update->flip_addr->flip_timestamp_in_us;
 		surface->time.index++;
 		if (surface->time.index >= DC_PLANE_UPDATE_TIMES_MAX)
 			surface->time.index = 0;
@@ -3849,27 +3897,34 @@ static void commit_planes_do_stream_update(struct dc *dc,
 				resource_build_test_pattern_params(&context->res_ctx, pipe_ctx);
 			}
 
+			// DPMS should not use partially updated pipe context
+			struct pipe_ctx *dpms_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[j];
+
 			if (stream_update->dpms_off) {
 				if (*stream_update->dpms_off) {
-					dc->link_srv->set_dpms_off(pipe_ctx);
+					dc->link_srv->set_dpms_off(dpms_pipe_ctx);
 					/* for dpms, keep acquired resources*/
-					if (pipe_ctx->stream_res.audio && !dc->debug.az_endpoint_mute_only)
-						pipe_ctx->stream_res.audio->funcs->az_disable(pipe_ctx->stream_res.audio);
+					if (dpms_pipe_ctx->stream_res.audio && !dc->debug.az_endpoint_mute_only) {
+						struct audio *audio = dpms_pipe_ctx->stream_res.audio;
+
+						audio->funcs->az_disable(audio);
+					}
 
 					dc->optimized_required = true;
 
 				} else {
 					if (get_seamless_boot_stream_count(context) == 0)
 						dc->hwss.prepare_bandwidth(dc, dc->current_state);
-					dc->link_srv->set_dpms_on(dc->current_state, pipe_ctx);
+					dc->link_srv->set_dpms_on(dc->current_state, dpms_pipe_ctx);
 				}
-			} else if (pipe_ctx->stream->link->wa_flags.blank_stream_on_ocs_change && stream_update->output_color_space
-					&& !stream->dpms_off && dc_is_dp_signal(pipe_ctx->stream->signal)) {
+			} else if (dpms_pipe_ctx->stream->link->wa_flags.blank_stream_on_ocs_change &&
+					stream_update->output_color_space &&
+					!stream->dpms_off && dc_is_dp_signal(dpms_pipe_ctx->stream->signal)) {
 				/*
 				 * Workaround for firmware issue in some receivers where they don't pick up
 				 * correct output color space unless DP link is disabled/re-enabled
 				 */
-				dc->link_srv->set_dpms_on(dc->current_state, pipe_ctx);
+				dc->link_srv->set_dpms_on(dc->current_state, dpms_pipe_ctx);
 			}
 
 			if (stream_update->abm_level && pipe_ctx->stream_res.abm) {
@@ -3949,7 +4004,7 @@ void dc_dmub_update_dirty_rect(struct dc *dc,
 		else
 			update_dirty_rect->cmd_version = DMUB_CMD_CURSOR_UPDATE_VERSION_1;
 
-		update_dirty_rect->dirty_rect_count = flip_addr->dirty_rect_count;
+		update_dirty_rect->dirty_rect_count = (uint8_t)flip_addr->dirty_rect_count;
 		memcpy(update_dirty_rect->src_dirty_rects, flip_addr->dirty_rects,
 				sizeof(flip_addr->dirty_rects));
 		for (j = 0; j < dc->res_pool->pipe_count; j++) {
@@ -3960,9 +4015,9 @@ void dc_dmub_update_dirty_rect(struct dc *dc,
 			if (pipe_ctx->plane_state != plane_state)
 				continue;
 
-			update_dirty_rect->panel_inst = panel_inst;
-			update_dirty_rect->pipe_idx = j;
-			update_dirty_rect->otg_inst = pipe_ctx->stream_res.tg->inst;
+			update_dirty_rect->panel_inst = (uint8_t)panel_inst;
+			update_dirty_rect->pipe_idx = (uint8_t)j;
+			update_dirty_rect->otg_inst = (uint8_t)pipe_ctx->stream_res.tg->inst;
 			dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_NO_WAIT);
 		}
 	}
@@ -4010,7 +4065,7 @@ static void build_dmub_update_dirty_rect(
 		else
 			update_dirty_rect->cmd_version = DMUB_CMD_CURSOR_UPDATE_VERSION_1;
 
-		update_dirty_rect->dirty_rect_count = flip_addr->dirty_rect_count;
+		update_dirty_rect->dirty_rect_count = (uint8_t)flip_addr->dirty_rect_count;
 		memcpy(update_dirty_rect->src_dirty_rects, flip_addr->dirty_rects,
 				sizeof(flip_addr->dirty_rects));
 		for (j = 0; j < dc->res_pool->pipe_count; j++) {
@@ -4020,9 +4075,9 @@ static void build_dmub_update_dirty_rect(
 				continue;
 			if (pipe_ctx->plane_state != plane_state)
 				continue;
-			update_dirty_rect->panel_inst = panel_inst;
-			update_dirty_rect->pipe_idx = j;
-			update_dirty_rect->otg_inst = pipe_ctx->stream_res.tg->inst;
+			update_dirty_rect->panel_inst = (uint8_t)panel_inst;
+			update_dirty_rect->pipe_idx = (uint8_t)j;
+			update_dirty_rect->otg_inst = (uint8_t)pipe_ctx->stream_res.tg->inst;
 			dc_dmub_cmd[*dmub_cmd_count].dmub_cmd = cmd;
 			dc_dmub_cmd[*dmub_cmd_count].wait_type = DM_DMUB_WAIT_TYPE_NO_WAIT;
 			(*dmub_cmd_count)++;
@@ -4325,7 +4380,7 @@ static void commit_planes_for_stream(struct dc *dc,
 				struct dmub_hw_lock_inst_flags inst_flags = { 0 };
 
 				hw_locks.bits.lock_dig = 1;
-				inst_flags.dig_inst = top_pipe_to_program->stream_res.tg->inst;
+				inst_flags.dig_inst = (uint8_t)top_pipe_to_program->stream_res.tg->inst;
 
 				dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv,
 							true,
@@ -4592,7 +4647,7 @@ static void commit_planes_for_stream(struct dc *dc,
 				struct dmub_hw_lock_inst_flags inst_flags = { 0 };
 
 				hw_locks.bits.lock_dig = 1;
-				inst_flags.dig_inst = top_pipe_to_program->stream_res.tg->inst;
+				inst_flags.dig_inst = (uint8_t)top_pipe_to_program->stream_res.tg->inst;
 
 				dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv,
 							false,
@@ -5109,9 +5164,35 @@ void populate_fast_updates(struct dc_fast_update *fast_update,
 	if (stream_update) {
 		fast_update[0].out_transfer_func = stream_update->out_transfer_func;
 		fast_update[0].output_csc_transform = stream_update->output_csc_transform;
+		fast_update[0].cursor_attributes = stream_update->cursor_attributes;
+		fast_update[0].cursor_position = stream_update->cursor_position;
+		fast_update[0].periodic_interrupt = stream_update->periodic_interrupt;
+		fast_update[0].dither_option = stream_update->dither_option;
+		fast_update[0].gamut_remap = stream_update->gamut_remap;
+		fast_update[0].vrr_infopacket = stream_update->vrr_infopacket;
+		fast_update[0].vsc_infopacket = stream_update->vsc_infopacket;
+		fast_update[0].vsp_infopacket = stream_update->vsp_infopacket;
+		fast_update[0].hfvsif_infopacket = stream_update->hfvsif_infopacket;
+		fast_update[0].vtem_infopacket = stream_update->vtem_infopacket;
+		fast_update[0].adaptive_sync_infopacket = stream_update->adaptive_sync_infopacket;
+		fast_update[0].avi_infopacket = stream_update->avi_infopacket;
+		fast_update[0].hdr_static_metadata = stream_update->hdr_static_metadata;
 	} else {
 		fast_update[0].out_transfer_func = NULL;
 		fast_update[0].output_csc_transform = NULL;
+		fast_update[0].cursor_attributes = NULL;
+		fast_update[0].cursor_position = NULL;
+		fast_update[0].periodic_interrupt = NULL;
+		fast_update[0].dither_option = NULL;
+		fast_update[0].gamut_remap = NULL;
+		fast_update[0].vrr_infopacket = NULL;
+		fast_update[0].vsc_infopacket = NULL;
+		fast_update[0].vsp_infopacket = NULL;
+		fast_update[0].hfvsif_infopacket = NULL;
+		fast_update[0].vtem_infopacket = NULL;
+		fast_update[0].adaptive_sync_infopacket = NULL;
+		fast_update[0].avi_infopacket = NULL;
+		fast_update[0].hdr_static_metadata = NULL;
 	}
 
 	for (i = 0; i < surface_count; i++) {
@@ -5132,7 +5213,20 @@ static bool fast_updates_exist(const struct dc_fast_update *fast_update, int sur
 	int i;
 
 	if (fast_update[0].out_transfer_func ||
-		fast_update[0].output_csc_transform)
+		fast_update[0].output_csc_transform ||
+		fast_update[0].gamut_remap ||
+		fast_update[0].cursor_attributes ||
+		fast_update[0].cursor_position ||
+		fast_update[0].periodic_interrupt ||
+		fast_update[0].dither_option ||
+		fast_update[0].vrr_infopacket ||
+		fast_update[0].vsc_infopacket ||
+		fast_update[0].vsp_infopacket ||
+		fast_update[0].hfvsif_infopacket ||
+		fast_update[0].vtem_infopacket ||
+		fast_update[0].adaptive_sync_infopacket ||
+		fast_update[0].avi_infopacket ||
+		fast_update[0].hdr_static_metadata)
 		return true;
 
 	for (i = 0; i < surface_count; i++) {
@@ -5156,7 +5250,20 @@ bool fast_nonaddr_updates_exist(struct dc_fast_update *fast_update, int surface_
 	int i;
 
 	if (fast_update[0].out_transfer_func ||
-		fast_update[0].output_csc_transform)
+		fast_update[0].output_csc_transform ||
+		fast_update[0].cursor_attributes ||
+		fast_update[0].cursor_position ||
+		fast_update[0].periodic_interrupt ||
+		fast_update[0].dither_option ||
+		fast_update[0].gamut_remap ||
+		fast_update[0].vrr_infopacket ||
+		fast_update[0].vsc_infopacket ||
+		fast_update[0].vsp_infopacket ||
+		fast_update[0].hfvsif_infopacket ||
+		fast_update[0].vtem_infopacket ||
+		fast_update[0].adaptive_sync_infopacket ||
+		fast_update[0].avi_infopacket ||
+		fast_update[0].hdr_static_metadata)
 		return true;
 
 	for (i = 0; i < surface_count; i++) {
@@ -5240,23 +5347,12 @@ static bool full_update_required(
 			(((stream_update->src.height != 0 && stream_update->src.width != 0) ||
 			(stream_update->dst.height != 0 && stream_update->dst.width != 0) ||
 			stream_update->integer_scaling_update) ||
-			stream_update->hdr_static_metadata ||
 			stream_update->abm_level ||
-			stream_update->periodic_interrupt ||
-			stream_update->vrr_infopacket ||
-			stream_update->vsc_infopacket ||
-			stream_update->vsp_infopacket ||
-			stream_update->hfvsif_infopacket ||
-			stream_update->vtem_infopacket ||
-			stream_update->adaptive_sync_infopacket ||
-			stream_update->avi_infopacket ||
 			stream_update->dpms_off ||
 			stream_update->allow_freesync ||
 			stream_update->vrr_active_variable ||
 			stream_update->vrr_active_fixed ||
-			stream_update->gamut_remap ||
 			stream_update->output_color_space ||
-			stream_update->dither_option ||
 			stream_update->wb_update ||
 			stream_update->dsc_config ||
 			stream_update->mst_bw_update ||
@@ -6081,12 +6177,12 @@ bool dc_process_dmub_aux_transfer_async(struct dc *dc,
 	else
 		cmd.dp_aux_access.aux_control.type = AUX_CHANNEL_LEGACY_DDC;
 
-	cmd.dp_aux_access.aux_control.instance = dc->links[link_index]->ddc_hw_inst;
+	cmd.dp_aux_access.aux_control.instance = (uint8_t)dc->links[link_index]->ddc_hw_inst;
 	cmd.dp_aux_access.aux_control.sw_crc_enabled = 0;
 	cmd.dp_aux_access.aux_control.timeout = 0;
 	cmd.dp_aux_access.aux_control.dpaux.address = payload->address;
 	cmd.dp_aux_access.aux_control.dpaux.is_i2c_over_aux = payload->i2c_over_aux;
-	cmd.dp_aux_access.aux_control.dpaux.length = payload->length;
+	cmd.dp_aux_access.aux_control.dpaux.length = (uint8_t)payload->length;
 
 	/* set aux action */
 	if (payload->i2c_over_aux) {
@@ -6152,7 +6248,7 @@ bool dc_smart_power_oled_enable(const struct dc_link *link, bool enable, uint16_
 	}
 
 	if (pipe_ctx)
-		otg_inst = pipe_ctx->stream_res.tg->inst;
+		otg_inst = (uint8_t)pipe_ctx->stream_res.tg->inst;
 
 	// before enable smart power OLED, we need to call set pipe for DMUB to set ABM config
 	if (enable) {
@@ -6169,11 +6265,11 @@ bool dc_smart_power_oled_enable(const struct dc_link *link, bool enable, uint16_
 		sizeof(struct dmub_rb_cmd_smart_power_oled_enable_data) - sizeof(struct dmub_cmd_header);
 	cmd.smart_power_oled_enable.header.ret_status = 1;
 	cmd.smart_power_oled_enable.data.enable = enable;
-	cmd.smart_power_oled_enable.data.panel_inst = panel_inst;
+	cmd.smart_power_oled_enable.data.panel_inst = (uint8_t)panel_inst;
 	cmd.smart_power_oled_enable.data.peak_nits = peak_nits;
 	cmd.smart_power_oled_enable.data.otg_inst = otg_inst;
-	cmd.smart_power_oled_enable.data.digfe_inst = link->link_enc->preferred_engine;
-	cmd.smart_power_oled_enable.data.digbe_inst = link->link_enc->transmitter;
+	cmd.smart_power_oled_enable.data.digfe_inst = (uint8_t)link->link_enc->preferred_engine;
+	cmd.smart_power_oled_enable.data.digbe_inst = (uint8_t)link->link_enc->transmitter;
 
 	cmd.smart_power_oled_enable.data.debugcontrol = debug_control;
 	cmd.smart_power_oled_enable.data.triggerline = triggerline;
@@ -6204,7 +6300,7 @@ bool dc_smart_power_oled_get_max_cll(const struct dc_link *link, unsigned int *p
 	cmd.smart_power_oled_getmaxcll.header.payload_bytes = sizeof(cmd.smart_power_oled_getmaxcll.data);
 	cmd.smart_power_oled_getmaxcll.header.ret_status = 1;
 
-	cmd.smart_power_oled_getmaxcll.data.input.panel_inst = panel_inst;
+	cmd.smart_power_oled_getmaxcll.data.input.panel_inst = (uint8_t)panel_inst;
 
 	// send cmd and wait for reply
 	status = dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY);
@@ -6262,7 +6358,7 @@ bool dc_process_dmub_set_config_async(struct dc *dc,
 	cmd.set_config_access.header.type = DMUB_CMD__DPIA;
 	cmd.set_config_access.header.sub_type = DMUB_CMD__DPIA_SET_CONFIG_ACCESS;
 
-	cmd.set_config_access.set_config_control.instance = dc->links[link_index]->ddc_hw_inst;
+	cmd.set_config_access.set_config_control.instance = (uint8_t)dc->links[link_index]->ddc_hw_inst;
 	cmd.set_config_access.set_config_control.cmd_pkt.msg_type = payload->msg_type;
 	cmd.set_config_access.set_config_control.cmd_pkt.msg_data = payload->msg_data;
 
@@ -6306,7 +6402,7 @@ enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc,
 	cmd.set_mst_alloc_slots.header.type = DMUB_CMD__DPIA;
 	cmd.set_mst_alloc_slots.header.sub_type = DMUB_CMD__DPIA_MST_ALLOC_SLOTS;
 
-	cmd.set_mst_alloc_slots.mst_slots_control.instance = dc->links[link_index]->ddc_hw_inst;
+	cmd.set_mst_alloc_slots.mst_slots_control.instance = (uint8_t)dc->links[link_index]->ddc_hw_inst;
 	cmd.set_mst_alloc_slots.mst_slots_control.mst_alloc_slots = mst_alloc_slots;
 
 	if (!dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY))
@@ -6346,7 +6442,7 @@ void dc_process_dmub_dpia_set_tps_notification(const struct dc *dc, uint32_t lin
 
 	cmd.set_tps_notification.header.type = DMUB_CMD__DPIA;
 	cmd.set_tps_notification.header.sub_type = DMUB_CMD__DPIA_SET_TPS_NOTIFICATION;
-	cmd.set_tps_notification.tps_notification.instance = dc->links[link_index]->ddc_hw_inst;
+	cmd.set_tps_notification.tps_notification.instance = (uint8_t)dc->links[link_index]->ddc_hw_inst;
 	cmd.set_tps_notification.tps_notification.tps = tps;
 
 	dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
index 7333f5905330..a347d3ff5e6e 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
@@ -39,6 +39,8 @@
 #include "abm.h"
 #include "dcn10/dcn10_hubbub.h"
 #include "dce/dmub_hw_lock_mgr.h"
+#include "custom_float.h"
+#include "link_service.h"
 
 #define MAX_NUM_MCACHE 8
 
@@ -345,39 +347,39 @@ void get_surface_visual_confirm_color(
 	switch (pipe_ctx->plane_res.scl_data.format) {
 	case PIXEL_FORMAT_ARGB8888:
 		/* set border color to red */
-		color->color_r_cr = color_value;
+		color->color_r_cr = (uint16_t)color_value;
 		if (pipe_ctx->plane_state->layer_index > 0) {
 			/* set border color to pink */
-			color->color_b_cb = color_value;
-			color->color_g_y = color_value * 0.5;
+			color->color_b_cb = (uint16_t)color_value;
+			color->color_g_y = (uint16_t)(color_value / 2);
 		}
 		break;
 
 	case PIXEL_FORMAT_ARGB2101010:
 		/* set border color to blue */
-		color->color_b_cb = color_value;
+		color->color_b_cb = (uint16_t)color_value;
 		if (pipe_ctx->plane_state->layer_index > 0) {
 			/* set border color to cyan */
-			color->color_g_y = color_value;
+			color->color_g_y = (uint16_t)color_value;
 		}
 		break;
 	case PIXEL_FORMAT_420BPP8:
 		/* set border color to green */
-		color->color_g_y = color_value;
+		color->color_g_y = (uint16_t)color_value;
 		break;
 	case PIXEL_FORMAT_420BPP10:
 		/* set border color to yellow */
-		color->color_g_y = color_value;
-		color->color_r_cr = color_value;
+		color->color_g_y = (uint16_t)color_value;
+		color->color_r_cr = (uint16_t)color_value;
 		break;
 	case PIXEL_FORMAT_FP16:
 		/* set border color to white */
-		color->color_r_cr = color_value;
-		color->color_b_cb = color_value;
-		color->color_g_y = color_value;
+		color->color_r_cr = (uint16_t)color_value;
+		color->color_b_cb = (uint16_t)color_value;
+		color->color_g_y = (uint16_t)color_value;
 		if (pipe_ctx->plane_state->layer_index > 0) {
 			/* set border color to orange */
-			color->color_g_y = 0.22 * color_value;
+			color->color_g_y = (uint16_t)((color_value * 22) / 100);
 			color->color_b_cb = 0;
 		}
 		break;
@@ -403,21 +405,21 @@ void get_hdr_visual_confirm_color(
 	case PIXEL_FORMAT_ARGB2101010:
 		if (top_pipe_ctx->stream->out_transfer_func.tf == TRANSFER_FUNCTION_PQ) {
 			/* HDR10, ARGB2101010 - set border color to red */
-			color->color_r_cr = color_value;
+			color->color_r_cr = (uint16_t)color_value;
 		} else if (top_pipe_ctx->stream->out_transfer_func.tf == TRANSFER_FUNCTION_GAMMA22) {
 			/* FreeSync 2 ARGB2101010 - set border color to pink */
-			color->color_r_cr = color_value;
-			color->color_b_cb = color_value;
+			color->color_r_cr = (uint16_t)color_value;
+			color->color_b_cb = (uint16_t)color_value;
 		} else
 			is_sdr = true;
 		break;
 	case PIXEL_FORMAT_FP16:
 		if (top_pipe_ctx->stream->out_transfer_func.tf == TRANSFER_FUNCTION_PQ) {
 			/* HDR10, FP16 - set border color to blue */
-			color->color_b_cb = color_value;
+			color->color_b_cb = (uint16_t)color_value;
 		} else if (top_pipe_ctx->stream->out_transfer_func.tf == TRANSFER_FUNCTION_GAMMA22) {
 			/* FreeSync 2 HDR - set border color to green */
-			color->color_g_y = color_value;
+			color->color_g_y = (uint16_t)color_value;
 		} else
 			is_sdr = true;
 		break;
@@ -428,9 +430,9 @@ void get_hdr_visual_confirm_color(
 
 	if (is_sdr) {
 		/* SDR - set border color to Gray */
-		color->color_r_cr = color_value/2;
-		color->color_b_cb = color_value/2;
-		color->color_g_y = color_value/2;
+		color->color_r_cr = (uint16_t)(color_value / 2);
+		color->color_b_cb = (uint16_t)(color_value / 2);
+		color->color_g_y = (uint16_t)(color_value / 2);
 	}
 }
 
@@ -454,7 +456,7 @@ void get_smartmux_visual_confirm_color(
 		*color = sm_ver_colors[dc->config.smart_mux_version];
 	} else {
 		/* dGPU driving the eDP - red */
-		color->color_r_cr = color_value;
+		color->color_r_cr = (uint16_t)color_value;
 		color->color_g_y = 0;
 		color->color_b_cb = 0;
 	}
@@ -476,19 +478,19 @@ void get_vabc_visual_confirm_color(
 	if (edp_link) {
 		switch (edp_link->backlight_control_type) {
 		case BACKLIGHT_CONTROL_PWM:
-			color->color_r_cr = color_value;
+			color->color_r_cr = (uint16_t)color_value;
 			color->color_g_y = 0;
 			color->color_b_cb = 0;
 			break;
 		case BACKLIGHT_CONTROL_AMD_AUX:
 			color->color_r_cr = 0;
-			color->color_g_y = color_value;
+			color->color_g_y = (uint16_t)color_value;
 			color->color_b_cb = 0;
 			break;
 		case BACKLIGHT_CONTROL_VESA_AUX:
 			color->color_r_cr = 0;
 			color->color_g_y = 0;
-			color->color_b_cb = color_value;
+			color->color_b_cb = (uint16_t)color_value;
 			break;
 		}
 	} else {
@@ -506,19 +508,19 @@ void get_subvp_visual_confirm_color(
 	if (pipe_ctx) {
 		switch (pipe_ctx->p_state_type) {
 		case P_STATE_SUB_VP:
-			color->color_r_cr = color_value;
+			color->color_r_cr = (uint16_t)color_value;
 			color->color_g_y  = 0;
 			color->color_b_cb = 0;
 			break;
 		case P_STATE_DRR_SUB_VP:
 			color->color_r_cr = 0;
-			color->color_g_y  = color_value;
+			color->color_g_y  = (uint16_t)color_value;
 			color->color_b_cb = 0;
 			break;
 		case P_STATE_V_BLANK_SUB_VP:
 			color->color_r_cr = 0;
 			color->color_g_y  = 0;
-			color->color_b_cb = color_value;
+			color->color_b_cb = (uint16_t)color_value;
 			break;
 		default:
 			break;
@@ -535,34 +537,34 @@ void get_mclk_switch_visual_confirm_color(
 	if (pipe_ctx) {
 		switch (pipe_ctx->p_state_type) {
 		case P_STATE_V_BLANK:
-			color->color_r_cr = color_value;
-			color->color_g_y = color_value;
+			color->color_r_cr = (uint16_t)color_value;
+			color->color_g_y = (uint16_t)color_value;
 			color->color_b_cb = 0;
 			break;
 		case P_STATE_FPO:
 			color->color_r_cr = 0;
-			color->color_g_y  = color_value;
-			color->color_b_cb = color_value;
+			color->color_g_y  = (uint16_t)color_value;
+			color->color_b_cb = (uint16_t)color_value;
 			break;
 		case P_STATE_V_ACTIVE:
-			color->color_r_cr = color_value;
+			color->color_r_cr = (uint16_t)color_value;
 			color->color_g_y  = 0;
-			color->color_b_cb = color_value;
+			color->color_b_cb = (uint16_t)color_value;
 			break;
 		case P_STATE_SUB_VP:
-			color->color_r_cr = color_value;
+			color->color_r_cr = (uint16_t)color_value;
 			color->color_g_y  = 0;
 			color->color_b_cb = 0;
 			break;
 		case P_STATE_DRR_SUB_VP:
 			color->color_r_cr = 0;
-			color->color_g_y  = color_value;
+			color->color_g_y  = (uint16_t)color_value;
 			color->color_b_cb = 0;
 			break;
 		case P_STATE_V_BLANK_SUB_VP:
 			color->color_r_cr = 0;
 			color->color_g_y  = 0;
-			color->color_b_cb = color_value;
+			color->color_b_cb = (uint16_t)color_value;
 			break;
 		default:
 			break;
@@ -577,13 +579,13 @@ void get_cursor_visual_confirm_color(
 	uint32_t color_value = MAX_TG_COLOR_VALUE;
 
 	if (pipe_ctx->stream && pipe_ctx->stream->cursor_position.enable) {
-		color->color_r_cr = color_value;
+		color->color_r_cr = (uint16_t)color_value;
 		color->color_g_y = 0;
 		color->color_b_cb = 0;
 	} else {
 		color->color_r_cr = 0;
 		color->color_g_y = 0;
-		color->color_b_cb = color_value;
+		color->color_b_cb = (uint16_t)color_value;
 	}
 }
 
@@ -721,9 +723,9 @@ void get_fams2_visual_confirm_color(
 	/* driver only handles visual confirm when FAMS2 is disabled */
 	if (!dc_state_is_fams2_in_use(dc, context)) {
 		/* when FAMS2 is disabled, all pipes are grey */
-		color->color_g_y = color_value / 2;
-		color->color_b_cb = color_value / 2;
-		color->color_r_cr = color_value / 2;
+		color->color_g_y = (uint16_t)(color_value / 2);
+		color->color_b_cb = (uint16_t)(color_value / 2);
+		color->color_r_cr = (uint16_t)(color_value / 2);
 	}
 }
 
@@ -789,8 +791,242 @@ void hwss_build_fast_sequence(struct dc *dc,
 		(*num_steps)++;
 	}
 
+	if (dc->hwss.setup_periodic_interrupt && stream->update_flags.bits.periodic_interrupt) {
+		block_sequence[*num_steps].params.setup_periodic_interrupt_params.dc = dc;
+		block_sequence[*num_steps].params.setup_periodic_interrupt_params.pipe_ctx = pipe_ctx;
+		block_sequence[*num_steps].func = HWSS_SETUP_PERIODIC_INTERRUPT;
+		(*num_steps)++;
+	}
+
+	if (stream->update_flags.bits.info_frame) {
+		resource_build_info_frame(pipe_ctx);
+		block_sequence[*num_steps].params.update_info_frame_params.dc = dc;
+		block_sequence[*num_steps].params.update_info_frame_params.pipe_ctx = pipe_ctx;
+		block_sequence[*num_steps].func = HWSS_UPDATE_INFO_FRAME;
+		(*num_steps)++;
+
+		if (dc_is_dp_signal(pipe_ctx->stream->signal)) {
+			block_sequence[*num_steps].params.dp_trace_source_sequence_params.dc = dc;
+			block_sequence[*num_steps].params.dp_trace_source_sequence_params.link = pipe_ctx->stream->link;
+			block_sequence[*num_steps].params.dp_trace_source_sequence_params.dp_test_mode = DPCD_SOURCE_SEQ_AFTER_UPDATE_INFO_FRAME;
+			block_sequence[*num_steps].func = DP_TRACE_SOURCE_SEQUENCE;
+			(*num_steps)++;
+		}
+	}
+
+	if (dc->hwss.set_dmdata_attributes && stream->update_flags.bits.dmdata &&
+			stream->use_dynamic_meta && pipe_ctx->stream->dmdata_address.quad_part != 0) {
+		struct dc_dmdata_attributes attr = { 0 };
+
+		attr.dmdata_mode = DMDATA_HW_MODE;
+		attr.dmdata_size = dc_is_hdmi_signal(pipe_ctx->stream->signal) ? 32 : 36;
+		attr.address.quad_part = pipe_ctx->stream->dmdata_address.quad_part;
+		attr.dmdata_dl_delta = 0;
+		attr.dmdata_qos_mode = 0;
+		attr.dmdata_qos_level = 0;
+		attr.dmdata_repeat = 1; /* always repeat */
+		attr.dmdata_updated = 1;
+		attr.dmdata_sw_data = NULL;
+
+		block_sequence[*num_steps].params.set_dmdata_attributes_params.hubp = pipe_ctx->plane_res.hubp;
+		block_sequence[*num_steps].params.set_dmdata_attributes_params.attr = attr;
+		block_sequence[*num_steps].func = HUBP_SET_DMDATA_ATTRIBUTES;
+		(*num_steps)++;
+	}
+
+	/* Track cursor lock state - separate locks for attribute and position updates */
+	bool enable_cursor_offload = false;
+
+	if ((dc->hwss.set_cursor_attribute && stream->update_flags.bits.cursor_attr) ||
+		(dc->hwss.set_cursor_position && stream->update_flags.bits.cursor_pos))
+		enable_cursor_offload = dc_dmub_srv_is_cursor_offload_enabled(dc);
+
+	/* Cursor attribute updates - separate lock/iterate/unlock */
+	if (dc->hwss.set_cursor_attribute && stream->update_flags.bits.cursor_attr) {
+		struct pipe_ctx *cursor_pipe_to_program = NULL;
+
+		for (i = 0; i < MAX_PIPES; i++) {
+			current_pipe = &context->res_ctx.pipe_ctx[i];
+
+			if (current_pipe->stream != stream)
+				continue;
+
+			if (!cursor_pipe_to_program) {
+				cursor_pipe_to_program = current_pipe;
+
+				if (enable_cursor_offload && dc->hwss.begin_cursor_offload_update) {
+					block_sequence[*num_steps].params.begin_cursor_offload_update_params.dc = dc;
+					block_sequence[*num_steps].params.begin_cursor_offload_update_params.pipe_ctx =
+						current_pipe;
+					block_sequence[*num_steps].func = HWSS_BEGIN_CURSOR_OFFLOAD_UPDATE;
+					(*num_steps)++;
+				} else {
+					block_sequence[*num_steps].params.cursor_lock_params.dc = dc;
+					block_sequence[*num_steps].params.cursor_lock_params.pipe_ctx = current_pipe;
+					block_sequence[*num_steps].params.cursor_lock_params.lock = true;
+					block_sequence[*num_steps].func = HWSS_CURSOR_LOCK;
+					(*num_steps)++;
+
+					if (current_pipe->next_odm_pipe) {
+						block_sequence[*num_steps].params.cursor_lock_params.dc = dc;
+						block_sequence[*num_steps].params.cursor_lock_params.pipe_ctx =
+							current_pipe->next_odm_pipe;
+						block_sequence[*num_steps].params.cursor_lock_params.lock = true;
+						block_sequence[*num_steps].func = HWSS_CURSOR_LOCK;
+						(*num_steps)++;
+					}
+				}
+			}
+
+			block_sequence[*num_steps].params.hubp_set_cursor_attributes_params.hubp =
+				current_pipe->plane_res.hubp;
+			block_sequence[*num_steps].params.hubp_set_cursor_attributes_params.attributes =
+				&current_pipe->stream->cursor_attributes;
+			block_sequence[*num_steps].func = HUBP_SET_CURSOR_ATTRIBUTES;
+			(*num_steps)++;
+
+			block_sequence[*num_steps].params.dpp_set_cursor_attributes_params.dpp =
+				current_pipe->plane_res.dpp;
+			block_sequence[*num_steps].params.dpp_set_cursor_attributes_params.attributes =
+				&current_pipe->stream->cursor_attributes;
+			block_sequence[*num_steps].func = DPP_SET_CURSOR_ATTRIBUTES;
+			(*num_steps)++;
+
+			if (dc->ctx->dmub_srv) {
+				block_sequence[*num_steps].params.send_cursor_info_to_dmu_params.pipe_ctx =
+					current_pipe;
+				block_sequence[*num_steps].params.send_cursor_info_to_dmu_params.pipe_idx =
+					current_pipe->pipe_idx;
+				block_sequence[*num_steps].func = DC_SEND_CURSOR_INFO_TO_DMU;
+				(*num_steps)++;
+			}
+
+			block_sequence[*num_steps].params.set_cursor_sdr_white_level_params.dc = dc;
+			block_sequence[*num_steps].params.set_cursor_sdr_white_level_params.pipe_ctx =
+				current_pipe;
+			block_sequence[*num_steps].func = SET_CURSOR_SDR_WHITE_LEVEL;
+			(*num_steps)++;
+
+			if (enable_cursor_offload && dc->hwss.update_cursor_offload_pipe) {
+				block_sequence[*num_steps].params.update_cursor_offload_pipe_params.dc = dc;
+				block_sequence[*num_steps].params.update_cursor_offload_pipe_params.pipe_ctx =
+					current_pipe;
+				block_sequence[*num_steps].func = HWSS_UPDATE_CURSOR_OFFLOAD_PIPE;
+				(*num_steps)++;
+			}
+		}
+
+		/* Unlock cursor attributes after all pipes have been programmed */
+		if (cursor_pipe_to_program) {
+			if (enable_cursor_offload && dc->hwss.commit_cursor_offload_update) {
+				block_sequence[*num_steps].params.commit_cursor_offload_update_params.dc = dc;
+				block_sequence[*num_steps].params.commit_cursor_offload_update_params.pipe_ctx =
+					cursor_pipe_to_program;
+				block_sequence[*num_steps].func = HWSS_COMMIT_CURSOR_OFFLOAD_UPDATE;
+				(*num_steps)++;
+			} else {
+				block_sequence[*num_steps].params.cursor_lock_params.dc = dc;
+				block_sequence[*num_steps].params.cursor_lock_params.pipe_ctx = cursor_pipe_to_program;
+				block_sequence[*num_steps].params.cursor_lock_params.lock = false;
+				block_sequence[*num_steps].func = HWSS_CURSOR_LOCK;
+				(*num_steps)++;
+
+				if (cursor_pipe_to_program->next_odm_pipe) {
+					block_sequence[*num_steps].params.cursor_lock_params.dc = dc;
+					block_sequence[*num_steps].params.cursor_lock_params.pipe_ctx =
+						cursor_pipe_to_program->next_odm_pipe;
+					block_sequence[*num_steps].params.cursor_lock_params.lock = false;
+					block_sequence[*num_steps].func = HWSS_CURSOR_LOCK;
+					(*num_steps)++;
+				}
+			}
+		}
+	}
+
+	/* Cursor position updates */
+	if (dc->hwss.set_cursor_position && stream->update_flags.bits.cursor_pos) {
+		struct pipe_ctx *cursor_pipe_to_program = NULL;
+
+		for (i = 0; i < MAX_PIPES; i++) {
+			current_pipe = &context->res_ctx.pipe_ctx[i];
+
+			if (current_pipe->stream != stream ||
+					(!current_pipe->plane_res.mi && !current_pipe->plane_res.hubp) ||
+					!current_pipe->plane_state ||
+					(!current_pipe->plane_res.xfm && !current_pipe->plane_res.dpp) ||
+					(!current_pipe->plane_res.ipp && !current_pipe->plane_res.dpp))
+				continue;
+
+			if (!cursor_pipe_to_program) {
+				cursor_pipe_to_program = current_pipe;
+
+				if (enable_cursor_offload && dc->hwss.begin_cursor_offload_update) {
+					block_sequence[*num_steps].params.begin_cursor_offload_update_params.dc = dc;
+					block_sequence[*num_steps].params.begin_cursor_offload_update_params.pipe_ctx =
+						current_pipe;
+					block_sequence[*num_steps].func = HWSS_BEGIN_CURSOR_OFFLOAD_UPDATE;
+					(*num_steps)++;
+				} else {
+					block_sequence[*num_steps].params.cursor_lock_params.dc = dc;
+					block_sequence[*num_steps].params.cursor_lock_params.pipe_ctx = current_pipe;
+					block_sequence[*num_steps].params.cursor_lock_params.lock = true;
+					block_sequence[*num_steps].func = HWSS_CURSOR_LOCK;
+					(*num_steps)++;
+				}
+			}
+
+			block_sequence[*num_steps].params.set_cursor_position_params.dc = dc;
+			block_sequence[*num_steps].params.set_cursor_position_params.pipe_ctx = current_pipe;
+			block_sequence[*num_steps].func = SET_CURSOR_POSITION;
+			(*num_steps)++;
+
+			if (enable_cursor_offload && dc->hwss.update_cursor_offload_pipe) {
+				block_sequence[*num_steps].params.update_cursor_offload_pipe_params.dc = dc;
+				block_sequence[*num_steps].params.update_cursor_offload_pipe_params.pipe_ctx =
+					current_pipe;
+				block_sequence[*num_steps].func = HWSS_UPDATE_CURSOR_OFFLOAD_PIPE;
+				(*num_steps)++;
+			}
+
+			if (dc->ctx->dmub_srv) {
+				block_sequence[*num_steps].params.send_cursor_info_to_dmu_params.pipe_ctx =
+					current_pipe;
+				block_sequence[*num_steps].params.send_cursor_info_to_dmu_params.pipe_idx =
+					current_pipe->pipe_idx;
+				block_sequence[*num_steps].func = DC_SEND_CURSOR_INFO_TO_DMU;
+				(*num_steps)++;
+			}
+		}
+
+		/* Unlock cursor position after all pipes have been programmed */
+		if (cursor_pipe_to_program) {
+			if (enable_cursor_offload && dc->hwss.commit_cursor_offload_update) {
+				block_sequence[*num_steps].params.commit_cursor_offload_update_params.dc = dc;
+				block_sequence[*num_steps].params.commit_cursor_offload_update_params.pipe_ctx =
+					cursor_pipe_to_program;
+				block_sequence[*num_steps].func = HWSS_COMMIT_CURSOR_OFFLOAD_UPDATE;
+				(*num_steps)++;
+			} else {
+				block_sequence[*num_steps].params.cursor_lock_params.dc = dc;
+				block_sequence[*num_steps].params.cursor_lock_params.pipe_ctx = cursor_pipe_to_program;
+				block_sequence[*num_steps].params.cursor_lock_params.lock = false;
+				block_sequence[*num_steps].func = HWSS_CURSOR_LOCK;
+				(*num_steps)++;
+			}
+		}
+	}
+
 	current_pipe = pipe_ctx;
 	while (current_pipe) {
+		if (current_pipe->stream->update_flags.bits.dither) {
+			resource_build_bit_depth_reduction_params(current_pipe->stream, &current_pipe->stream->bit_depth_params);
+			block_sequence[*num_steps].params.opp_program_fmt_params.opp = current_pipe->stream_res.opp;
+			block_sequence[*num_steps].params.opp_program_fmt_params.fmt_bit_depth = &current_pipe->stream->bit_depth_params;
+			block_sequence[*num_steps].params.opp_program_fmt_params.clamping = &current_pipe->stream->clamping;
+			block_sequence[*num_steps].func = OPP_PROGRAM_FMT;
+			(*num_steps)++;
+		}
+
 		current_mpc_pipe = current_pipe;
 		while (current_mpc_pipe) {
 			if (current_mpc_pipe->plane_state) {
@@ -831,7 +1067,9 @@ void hwss_build_fast_sequence(struct dc *dc,
 					(*num_steps)++;
 				}
 
-				if (dc->hwss.program_gamut_remap && current_mpc_pipe->plane_state->update_flags.bits.gamut_remap_change) {
+				if (dc->hwss.program_gamut_remap &&
+						(current_mpc_pipe->plane_state->update_flags.bits.gamut_remap_change ||
+						 current_mpc_pipe->stream->update_flags.bits.gamut_remap)) {
 					block_sequence[*num_steps].params.program_gamut_remap_params.pipe_ctx = current_mpc_pipe;
 					block_sequence[*num_steps].func = DPP_PROGRAM_GAMUT_REMAP;
 					(*num_steps)++;
@@ -856,6 +1094,16 @@ void hwss_build_fast_sequence(struct dc *dc,
 					block_sequence[*num_steps].func = DPP_PROGRAM_CM_HIST;
 					(*num_steps)++;
 				}
+
+				if (current_mpc_pipe->plane_res.dpp &&
+						current_mpc_pipe->plane_res.dpp->funcs->set_cursor_matrix &&
+						current_mpc_pipe->plane_state->update_flags.bits.cursor_csc_color_matrix_change) {
+					block_sequence[*num_steps].params.dpp_set_cursor_matrix_params.dpp = current_mpc_pipe->plane_res.dpp;
+					block_sequence[*num_steps].params.dpp_set_cursor_matrix_params.color_space = current_mpc_pipe->plane_state->color_space;
+					block_sequence[*num_steps].params.dpp_set_cursor_matrix_params.cursor_csc_color_matrix = &current_mpc_pipe->plane_state->cursor_csc_color_matrix;
+					block_sequence[*num_steps].func = DPP_SET_CURSOR_MATRIX;
+					(*num_steps)++;
+				}
 			}
 			if (hws->funcs.set_output_transfer_func && current_mpc_pipe->stream->update_flags.bits.out_tf) {
 				block_sequence[*num_steps].params.set_output_transfer_func_params.dc = dc;
@@ -989,7 +1237,25 @@ void hwss_execute_sequence(struct dc *dc,
 					params->set_input_transfer_func_params.plane_state);
 			break;
 		case DPP_PROGRAM_GAMUT_REMAP:
-			dc->hwss.program_gamut_remap(params->program_gamut_remap_params.pipe_ctx);
+			hwss_program_gamut_remap(params);
+			break;
+		case HUBP_ENABLE_3DLUT_FL:
+			hwss_hubp_enable_3dlut_fl(params);
+			break;
+		case OTG_SETUP_VERTICAL_INTERRUPT:
+			hwss_tg_setup_vertical_interrupt0(params);
+			break;
+		case HWSS_SETUP_PERIODIC_INTERRUPT:
+			hwss_setup_periodic_interrupt(dc, params);
+			break;
+		case HWSS_UPDATE_INFO_FRAME:
+			hwss_update_info_frame(dc, params);
+			break;
+		case DP_TRACE_SOURCE_SEQUENCE:
+			hwss_dp_trace_source_sequence(params);
+			break;
+		case HUBP_SET_DMDATA_ATTRIBUTES:
+			hwss_set_dmdata_attributes(params);
 			break;
 		case DPP_SETUP_DPP:
 			hwss_setup_dpp(params);
@@ -1311,9 +1577,30 @@ void hwss_execute_sequence(struct dc *dc,
 		case ABORT_CURSOR_OFFLOAD_UPDATE:
 			hwss_abort_cursor_offload_update(params);
 			break;
+		case HWSS_CURSOR_LOCK:
+			hwss_cursor_lock(params);
+			break;
+		case HWSS_BEGIN_CURSOR_OFFLOAD_UPDATE:
+			hwss_begin_cursor_offload_update(params);
+			break;
+		case HWSS_COMMIT_CURSOR_OFFLOAD_UPDATE:
+			hwss_commit_cursor_offload_update(params);
+			break;
+		case HWSS_UPDATE_CURSOR_OFFLOAD_PIPE:
+			hwss_update_cursor_offload_pipe(params);
+			break;
+		case DC_SEND_CURSOR_INFO_TO_DMU:
+			hwss_send_cursor_info_to_dmu(params);
+			break;
 		case SET_CURSOR_ATTRIBUTE:
 			hwss_set_cursor_attribute(params);
 			break;
+		case HUBP_SET_CURSOR_ATTRIBUTES:
+			hwss_hubp_set_cursor_attributes(params);
+			break;
+		case DPP_SET_CURSOR_ATTRIBUTES:
+			hwss_dpp_set_cursor_attributes(params);
+			break;
 		case SET_CURSOR_POSITION:
 			hwss_set_cursor_position(params);
 			break;
@@ -1732,6 +2019,21 @@ void hwss_add_tg_set_vtg_params(struct block_sequence_state *seq_state,
 	}
 }
 
+/*
+ * Helper function to add OTG setup vertical interrupt0 to block sequence
+ */
+void hwss_add_vertical_interrupt_setup(struct block_sequence_state *seq_state,
+		struct timing_generator *tg, uint32_t start_line, uint32_t end_line)
+{
+	if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
+		seq_state->steps[*seq_state->num_steps].params.tg_setup_vertical_interrupt0_params.tg = tg;
+		seq_state->steps[*seq_state->num_steps].params.tg_setup_vertical_interrupt0_params.start_line = start_line;
+		seq_state->steps[*seq_state->num_steps].params.tg_setup_vertical_interrupt0_params.end_line = end_line;
+		seq_state->steps[*seq_state->num_steps].func = OTG_SETUP_VERTICAL_INTERRUPT;
+		(*seq_state->num_steps)++;
+	}
+}
+
 /*
  * Helper function to add TG setup vertical interrupt2 to block sequence
  */
@@ -1947,6 +2249,27 @@ void hwss_add_tg_wait_double_buffer_pending(struct block_sequence_state *seq_sta
 	}
 }
 
+void hwss_add_hubp_enable_3dlut_fl(struct block_sequence_state *seq_state,
+		struct hubp *hubp)
+{
+	if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
+		seq_state->steps[*seq_state->num_steps].params.hubp_enable_3dlut_fl_params.hubp = hubp;
+		seq_state->steps[*seq_state->num_steps].func = HUBP_ENABLE_3DLUT_FL;
+		(*seq_state->num_steps)++;
+	}
+}
+
+void hwss_add_set_dmdata_attributes(struct block_sequence_state *seq_state,
+		struct hubp *hubp, struct dc_dmdata_attributes *attr)
+{
+	if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
+		seq_state->steps[*seq_state->num_steps].params.set_dmdata_attributes_params.hubp = hubp;
+		seq_state->steps[*seq_state->num_steps].params.set_dmdata_attributes_params.attr = *attr;
+		seq_state->steps[*seq_state->num_steps].func = HUBP_SET_DMDATA_ATTRIBUTES;
+		(*seq_state->num_steps)++;
+	}
+}
+
 void hwss_program_manual_trigger(union block_sequence_params *params)
 {
 	struct pipe_ctx *pipe_ctx = params->program_manual_trigger_params.pipe_ctx;
@@ -2091,7 +2414,7 @@ void get_surface_tile_visual_confirm_color(
 	switch (bottom_pipe_ctx->plane_state->tiling_info.gfx9.swizzle) {
 	case DC_SW_LINEAR:
 		/* LINEAR Surface - set border color to red */
-		color->color_r_cr = color_value;
+		color->color_r_cr = (uint16_t)color_value;
 		break;
 	default:
 		break;
@@ -2416,6 +2739,59 @@ void hwss_tg_set_vtg_params(union block_sequence_params *params)
 		tg->funcs->set_vtg_params(tg, timing, program_fp2);
 }
 
+void hwss_hubp_enable_3dlut_fl(union block_sequence_params *params)
+{
+	struct hubp *hubp = params->hubp_enable_3dlut_fl_params.hubp;
+
+	if (hubp->funcs->hubp_enable_3dlut_fl)
+		hubp->funcs->hubp_enable_3dlut_fl(hubp, true);
+}
+
+void hwss_update_info_frame(struct dc *dc, union block_sequence_params *params)
+{
+	struct pipe_ctx *pipe_ctx = params->update_info_frame_params.pipe_ctx;
+
+	if (dc->hwss.update_info_frame)
+		dc->hwss.update_info_frame(pipe_ctx);
+}
+
+void hwss_setup_periodic_interrupt(struct dc *dc, union block_sequence_params *params)
+{
+	struct pipe_ctx *pipe_ctx = params->setup_periodic_interrupt_params.pipe_ctx;
+
+	if (dc->hwss.setup_periodic_interrupt)
+		dc->hwss.setup_periodic_interrupt(dc, pipe_ctx);
+}
+
+void hwss_dp_trace_source_sequence(union block_sequence_params *params)
+{
+	struct dc *dc = params->dp_trace_source_sequence_params.dc;
+	struct dc_link *link = params->dp_trace_source_sequence_params.link;
+	uint8_t dp_test_mode = params->dp_trace_source_sequence_params.dp_test_mode;
+
+	if (dc->link_srv->dp_trace_source_sequence)
+		dc->link_srv->dp_trace_source_sequence(link, dp_test_mode);
+}
+
+void hwss_set_dmdata_attributes(union block_sequence_params *params)
+{
+	struct hubp *hubp = params->set_dmdata_attributes_params.hubp;
+	struct dc_dmdata_attributes *attr = &params->set_dmdata_attributes_params.attr;
+
+	if (hubp->funcs->dmdata_set_attributes)
+		hubp->funcs->dmdata_set_attributes(hubp, attr);
+}
+
+void hwss_tg_setup_vertical_interrupt0(union block_sequence_params *params)
+{
+	struct timing_generator *tg = params->tg_setup_vertical_interrupt0_params.tg;
+	uint32_t start_line = params->tg_setup_vertical_interrupt0_params.start_line;
+	uint32_t end_line = params->tg_setup_vertical_interrupt0_params.end_line;
+
+	if (tg->funcs->setup_vertical_interrupt0)
+		tg->funcs->setup_vertical_interrupt0(tg, start_line, end_line);
+}
+
 void hwss_tg_setup_vertical_interrupt2(union block_sequence_params *params)
 {
 	struct timing_generator *tg = params->tg_setup_vertical_interrupt2_params.tg;
@@ -3113,6 +3489,51 @@ void hwss_abort_cursor_offload_update(union block_sequence_params *params)
 		dc->hwss.abort_cursor_offload_update(dc, pipe_ctx);
 }
 
+void hwss_cursor_lock(union block_sequence_params *params)
+{
+	struct dc *dc = params->cursor_lock_params.dc;
+	struct pipe_ctx *pipe_ctx = params->cursor_lock_params.pipe_ctx;
+	bool lock = params->cursor_lock_params.lock;
+
+	if (dc && dc->hwss.cursor_lock)
+		dc->hwss.cursor_lock(dc, pipe_ctx, lock);
+}
+
+void hwss_begin_cursor_offload_update(union block_sequence_params *params)
+{
+	struct dc *dc = params->begin_cursor_offload_update_params.dc;
+	struct pipe_ctx *pipe_ctx = params->begin_cursor_offload_update_params.pipe_ctx;
+
+	if (dc && dc->hwss.begin_cursor_offload_update)
+		dc->hwss.begin_cursor_offload_update(dc, pipe_ctx);
+}
+
+void hwss_commit_cursor_offload_update(union block_sequence_params *params)
+{
+	struct dc *dc = params->commit_cursor_offload_update_params.dc;
+	struct pipe_ctx *pipe_ctx = params->commit_cursor_offload_update_params.pipe_ctx;
+
+	if (dc && dc->hwss.commit_cursor_offload_update)
+		dc->hwss.commit_cursor_offload_update(dc, pipe_ctx);
+}
+
+void hwss_update_cursor_offload_pipe(union block_sequence_params *params)
+{
+	struct dc *dc = params->update_cursor_offload_pipe_params.dc;
+	struct pipe_ctx *pipe_ctx = params->update_cursor_offload_pipe_params.pipe_ctx;
+
+	if (dc && dc->hwss.update_cursor_offload_pipe)
+		dc->hwss.update_cursor_offload_pipe(dc, pipe_ctx);
+}
+
+void hwss_send_cursor_info_to_dmu(union block_sequence_params *params)
+{
+	struct pipe_ctx *pipe_ctx = params->send_cursor_info_to_dmu_params.pipe_ctx;
+	int pipe_idx = params->send_cursor_info_to_dmu_params.pipe_idx;
+
+	dc_send_update_cursor_info_to_dmu(pipe_ctx, pipe_idx);
+}
+
 void hwss_set_cursor_attribute(union block_sequence_params *params)
 {
 	struct dc *dc = params->set_cursor_attribute_params.dc;
@@ -3122,6 +3543,24 @@ void hwss_set_cursor_attribute(union block_sequence_params *params)
 		dc->hwss.set_cursor_attribute(pipe_ctx);
 }
 
+void hwss_hubp_set_cursor_attributes(union block_sequence_params *params)
+{
+	struct hubp *hubp = params->hubp_set_cursor_attributes_params.hubp;
+	const struct dc_cursor_attributes *attributes = params->hubp_set_cursor_attributes_params.attributes;
+
+	if (hubp && hubp->funcs->set_cursor_attributes)
+		hubp->funcs->set_cursor_attributes(hubp, attributes);
+}
+
+void hwss_dpp_set_cursor_attributes(union block_sequence_params *params)
+{
+	struct dpp *dpp = params->dpp_set_cursor_attributes_params.dpp;
+	struct dc_cursor_attributes *attributes = params->dpp_set_cursor_attributes_params.attributes;
+
+	if (dpp && dpp->funcs->set_cursor_attributes)
+		dpp->funcs->set_cursor_attributes(dpp, attributes);
+}
+
 void hwss_set_cursor_position(union block_sequence_params *params)
 {
 	struct dc *dc = params->set_cursor_position_params.dc;
@@ -3140,6 +3579,14 @@ void hwss_set_cursor_sdr_white_level(union block_sequence_params *params)
 		dc->hwss.set_cursor_sdr_white_level(pipe_ctx);
 }
 
+void hwss_program_gamut_remap(union block_sequence_params *params)
+{
+	struct dc *dc = params->program_gamut_remap_params.pipe_ctx->stream->ctx->dc;
+
+	if (dc && dc->hwss.program_gamut_remap)
+		dc->hwss.program_gamut_remap(params->program_gamut_remap_params.pipe_ctx);
+}
+
 void hwss_program_output_csc(union block_sequence_params *params)
 {
 	struct dc *dc = params->program_output_csc_params.dc;
@@ -4009,6 +4456,30 @@ void hwss_add_set_cursor_attribute(struct block_sequence_state *seq_state,
 	}
 }
 
+void hwss_add_hubp_set_cursor_attributes(struct block_sequence_state *seq_state,
+		struct hubp *hubp,
+		const struct dc_cursor_attributes *attributes)
+{
+	if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
+		seq_state->steps[*seq_state->num_steps].func = HUBP_SET_CURSOR_ATTRIBUTES;
+		seq_state->steps[*seq_state->num_steps].params.hubp_set_cursor_attributes_params.hubp = hubp;
+		seq_state->steps[*seq_state->num_steps].params.hubp_set_cursor_attributes_params.attributes = attributes;
+		(*seq_state->num_steps)++;
+	}
+}
+
+void hwss_add_dpp_set_cursor_attributes(struct block_sequence_state *seq_state,
+		struct dpp *dpp,
+		struct dc_cursor_attributes *attributes)
+{
+	if (*seq_state->num_steps < MAX_HWSS_BLOCK_SEQUENCE_SIZE) {
+		seq_state->steps[*seq_state->num_steps].func = DPP_SET_CURSOR_ATTRIBUTES;
+		seq_state->steps[*seq_state->num_steps].params.dpp_set_cursor_attributes_params.dpp = dpp;
+		seq_state->steps[*seq_state->num_steps].params.dpp_set_cursor_attributes_params.attributes = attributes;
+		(*seq_state->num_steps)++;
+	}
+}
+
 void hwss_add_set_cursor_position(struct block_sequence_state *seq_state,
 		struct dc *dc,
 		struct pipe_ctx *pipe_ctx)
@@ -4124,8 +4595,8 @@ void get_refresh_rate_confirm_color(struct pipe_ctx *pipe_ctx, struct tg_color *
 		if (max_refresh_rate - min_refresh_rate)
 			scaling_factor = MAX_TG_COLOR_VALUE * (refresh_rate - min_refresh_rate) / (max_refresh_rate - min_refresh_rate);
 
-		pipe_ctx->visual_confirm_color.color_r_cr = color_value;
-		pipe_ctx->visual_confirm_color.color_g_y = scaling_factor;
-		pipe_ctx->visual_confirm_color.color_b_cb = color_value;
+		pipe_ctx->visual_confirm_color.color_r_cr = (uint16_t)color_value;
+		pipe_ctx->visual_confirm_color.color_g_y = (uint16_t)scaling_factor;
+		pipe_ctx->visual_confirm_color.color_b_cb = (uint16_t)color_value;
 	}
 }
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 05991a10f8bf..1ab76c2d0f72 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -286,34 +286,34 @@ struct resource_pool *dc_create_resource_pool(struct dc  *dc,
 #endif
 	case DCE_VERSION_8_0:
 		res_pool = dce80_create_resource_pool(
-				init_data->num_virtual_links, dc);
+				(uint8_t)init_data->num_virtual_links, dc);
 		break;
 	case DCE_VERSION_8_1:
 		res_pool = dce81_create_resource_pool(
-				init_data->num_virtual_links, dc);
+				(uint8_t)init_data->num_virtual_links, dc);
 		break;
 	case DCE_VERSION_8_3:
 		res_pool = dce83_create_resource_pool(
-				init_data->num_virtual_links, dc);
+				(uint8_t)init_data->num_virtual_links, dc);
 		break;
 	case DCE_VERSION_10_0:
 		res_pool = dce100_create_resource_pool(
-				init_data->num_virtual_links, dc);
+				(uint8_t)init_data->num_virtual_links, dc);
 		break;
 	case DCE_VERSION_11_0:
 		res_pool = dce110_create_resource_pool(
-				init_data->num_virtual_links, dc,
+				(uint8_t)init_data->num_virtual_links, dc,
 				init_data->asic_id);
 		break;
 	case DCE_VERSION_11_2:
 	case DCE_VERSION_11_22:
 		res_pool = dce112_create_resource_pool(
-				init_data->num_virtual_links, dc);
+				(uint8_t)init_data->num_virtual_links, dc);
 		break;
 	case DCE_VERSION_12_0:
 	case DCE_VERSION_12_1:
 		res_pool = dce120_create_resource_pool(
-				init_data->num_virtual_links, dc);
+				(uint8_t)init_data->num_virtual_links, dc);
 		break;
 
 #if defined(CONFIG_DRM_AMD_DC_FP)
@@ -511,7 +511,7 @@ bool resource_construct(
 	pool->hpo_dp_link_enc_count = 0;
 	if (create_funcs->create_hpo_dp_link_encoder) {
 		for (i = 0; i < caps->num_hpo_dp_link_encoder; i++) {
-			pool->hpo_dp_link_enc[i] = create_funcs->create_hpo_dp_link_encoder(i, ctx);
+			pool->hpo_dp_link_enc[i] = create_funcs->create_hpo_dp_link_encoder((uint8_t)i, ctx);
 			if (pool->hpo_dp_link_enc[i] == NULL)
 				DC_ERR("DC: failed to create HPO DP link encoder!\n");
 			pool->hpo_dp_link_enc_count++;
@@ -610,7 +610,7 @@ bool resource_are_vblanks_synchronizable(
 {
 	uint32_t base60_refresh_rates[] = {10, 20, 5};
 	uint8_t i;
-	uint8_t rr_count = ARRAY_SIZE(base60_refresh_rates);
+	uint8_t rr_count = (uint8_t)ARRAY_SIZE(base60_refresh_rates);
 	uint64_t frame_time_diff;
 
 	if (stream1->ctx->dc->config.vblank_alignment_dto_params &&
@@ -1801,7 +1801,7 @@ struct pipe_ctx *resource_find_free_secondary_pipe_legacy(
 		int preferred_pipe_idx = (pool->pipe_count - 1) - primary_pipe->pipe_idx;
 		if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
 			secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
-			secondary_pipe->pipe_idx = preferred_pipe_idx;
+			secondary_pipe->pipe_idx = (uint8_t)preferred_pipe_idx;
 		}
 	}
 
@@ -1813,7 +1813,7 @@ struct pipe_ctx *resource_find_free_secondary_pipe_legacy(
 		for (i = pool->pipe_count - 1; i >= 0; i--) {
 			if (res_ctx->pipe_ctx[i].stream == NULL) {
 				secondary_pipe = &res_ctx->pipe_ctx[i];
-				secondary_pipe->pipe_idx = i;
+				secondary_pipe->pipe_idx = (uint8_t)i;
 				break;
 			}
 		}
@@ -2624,8 +2624,8 @@ static int acquire_first_split_pipe(
 			split_pipe->plane_res.ipp = pool->ipps[i];
 			split_pipe->plane_res.dpp = pool->dpps[i];
 			split_pipe->stream_res.opp = pool->opps[i];
-			split_pipe->plane_res.mpcc_inst = pool->dpps[i]->inst;
-			split_pipe->pipe_idx = i;
+			split_pipe->plane_res.mpcc_inst = (uint8_t)pool->dpps[i]->inst;
+			split_pipe->pipe_idx = (uint8_t)i;
 
 			split_pipe->stream = stream;
 			return i;
@@ -3804,7 +3804,7 @@ static int acquire_resource_from_hw_enabled_state(
 			pipe_ctx->stream_res.opp = pool->opps[id_src[i]];
 
 			if (pool->dpps[id_src[i]]) {
-				pipe_ctx->plane_res.mpcc_inst = pool->dpps[id_src[i]]->inst;
+				pipe_ctx->plane_res.mpcc_inst = (uint8_t)pool->dpps[id_src[i]]->inst;
 
 				if (pool->mpc->funcs->read_mpcc_state) {
 					struct mpcc_state s = {0};
@@ -3823,7 +3823,7 @@ static int acquire_resource_from_hw_enabled_state(
 						pipe_ctx->stream_res.opp->mpc_tree_params.opp_id = s.opp_id;
 				}
 			}
-			pipe_ctx->pipe_idx = id_src[i];
+			pipe_ctx->pipe_idx = (uint8_t)id_src[i];
 
 			if (id_src[i] >= pool->timing_generator_count) {
 				id_src[i] = pool->timing_generator_count - 1;
@@ -3939,7 +3939,7 @@ static bool acquire_otg_master_pipe_for_stream(
 	if (pipe_idx != FREE_PIPE_INDEX_NOT_FOUND) {
 		pipe_ctx = &new_ctx->res_ctx.pipe_ctx[pipe_idx];
 		memset(pipe_ctx, 0, sizeof(*pipe_ctx));
-		pipe_ctx->pipe_idx = pipe_idx;
+		pipe_ctx->pipe_idx = (uint8_t)pipe_idx;
 		pipe_ctx->stream_res.tg = pool->timing_generators[pipe_idx];
 		pipe_ctx->plane_res.mi = pool->mis[pipe_idx];
 		pipe_ctx->plane_res.hubp = pool->hubps[pipe_idx];
@@ -3948,7 +3948,7 @@ static bool acquire_otg_master_pipe_for_stream(
 		pipe_ctx->plane_res.dpp = pool->dpps[pipe_idx];
 		pipe_ctx->stream_res.opp = pool->opps[pipe_idx];
 		if (pool->dpps[pipe_idx])
-			pipe_ctx->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst;
+			pipe_ctx->plane_res.mpcc_inst = (uint8_t)pool->dpps[pipe_idx]->inst;
 
 		if (pipe_idx >= pool->timing_generator_count && pool->timing_generator_count != 0) {
 			int tg_inst = pool->timing_generator_count - 1;
@@ -4497,7 +4497,7 @@ static void patch_gamut_packet_checksum(
 		for (i = 0; i <= gamut_packet->sb[1]; i++)
 			chk_sum += ptr[i];
 
-		gamut_packet->sb[2] = (uint8_t) (0x100 - chk_sum);
+		gamut_packet->sb[2] = (uint8_t)(0x100 - chk_sum);
 	}
 }
 
@@ -4562,7 +4562,7 @@ static void set_avi_info_frame(
 
 	/* Y0_Y1_Y2 : The pixel encoding */
 	/* H14b AVI InfoFrame has extension on Y-field from 2 bits to 3 bits */
-	hdmi_info.bits.Y0_Y1_Y2 = pixel_encoding;
+	hdmi_info.bits.Y0_Y1_Y2 = (uint8_t)pixel_encoding;
 
 	/* A0 = 1 Active Format Information valid */
 	hdmi_info.bits.A0 = ACTIVE_FORMAT_VALID;
@@ -4692,7 +4692,7 @@ static void set_avi_info_frame(
 		}
 	}
 	/* If VIC >= 128, the Source shall use AVI InfoFrame Version 3*/
-	hdmi_info.bits.VIC0_VIC7 = vic;
+	hdmi_info.bits.VIC0_VIC7 = (uint8_t)vic;
 	if (vic >= 128)
 		hdmi_info.bits.header.version = 3;
 	/* If (C1, C0)=(1, 1) and (EC2, EC1, EC0)=(1, 1, 1),
@@ -4710,7 +4710,7 @@ static void set_avi_info_frame(
 
 		hdmi_info.bits.FR0_FR3 = fr_ind & 0xF;
 		hdmi_info.bits.FR4 = (fr_ind >> 4) & 0x1;
-		hdmi_info.bits.RID0_RID5 = rid;
+		hdmi_info.bits.RID0_RID5 = (uint8_t)rid;
 	}
 
 	/* pixel repetition
@@ -4723,11 +4723,11 @@ static void set_avi_info_frame(
 	 * barBottom: Line Number of Start of Bottom Bar.
 	 * barLeft:   Pixel Number of End of Left Bar.
 	 * barRight:  Pixel Number of Start of Right Bar. */
-	hdmi_info.bits.bar_top = stream->timing.v_border_top;
-	hdmi_info.bits.bar_bottom = (stream->timing.v_total
+	hdmi_info.bits.bar_top = (uint16_t)stream->timing.v_border_top;
+	hdmi_info.bits.bar_bottom = (uint16_t)(stream->timing.v_total
 			- stream->timing.v_border_bottom + 1);
-	hdmi_info.bits.bar_left  = stream->timing.h_border_left;
-	hdmi_info.bits.bar_right = (stream->timing.h_total
+	hdmi_info.bits.bar_left  = (uint16_t)stream->timing.h_border_left;
+	hdmi_info.bits.bar_right = (uint16_t)(stream->timing.h_total
 			- stream->timing.h_border_right + 1);
 
     /* Additional Colorimetry Extension
@@ -4746,7 +4746,7 @@ static void set_avi_info_frame(
 		*check_sum += hdmi_info.packet_raw_data.sb[byte_index];
 
 	/* one byte complement */
-	*check_sum = (uint8_t) (0x100 - *check_sum);
+	*check_sum = (uint8_t)(0x100 - *check_sum);
 
 	/* Store in hw_path_mode */
 	info_packet->hb0 = hdmi_info.packet_raw_data.hb0;
@@ -5369,7 +5369,7 @@ bool get_temp_dp_link_res(struct dc_link *link,
 void reset_syncd_pipes_from_disabled_pipes(struct dc *dc,
 		struct dc_state *context)
 {
-	int i, j;
+	uint8_t i, j;
 	struct pipe_ctx *pipe_ctx_old, *pipe_ctx, *pipe_ctx_syncd;
 
 	/* If pipe backend is reset, need to reset pipe syncd status */
@@ -5432,7 +5432,7 @@ void reset_sync_context_for_pipe(const struct dc *dc,
 	struct dc_state *context,
 	uint8_t pipe_idx)
 {
-	int i;
+	uint8_t i;
 	struct pipe_ctx *pipe_ctx_reset;
 
 	/* reset the otg sync context for the pipe and its slave pipes if any */
@@ -5448,7 +5448,7 @@ void reset_sync_context_for_pipe(const struct dc *dc,
 uint8_t resource_transmitter_to_phy_idx(const struct dc *dc, enum transmitter transmitter)
 {
 	/* TODO - get transmitter to phy idx mapping from DMUB */
-	uint8_t phy_idx = transmitter - TRANSMITTER_UNIPHY_A;
+	uint8_t phy_idx = (uint8_t)(transmitter - TRANSMITTER_UNIPHY_A);
 
 	if (dc->ctx->dce_version == DCN_VERSION_3_1 &&
 			dc->ctx->asic_id.hw_internal_rev == YELLOW_CARP_B0) {
@@ -5515,8 +5515,8 @@ const struct link_hwss *get_link_hwss(const struct dc_link *link,
 bool is_h_timing_divisible_by_2(struct dc_stream_state *stream)
 {
 	bool divisible = false;
-	uint16_t h_blank_start = 0;
-	uint16_t h_blank_end = 0;
+	uint32_t h_blank_start = 0;
+	uint32_t h_blank_end = 0;
 
 	if (stream) {
 		h_blank_start = stream->timing.h_total - stream->timing.h_front_porch;
@@ -5570,13 +5570,13 @@ bool dc_resource_acquire_secondary_pipe_for_mpc_odm_legacy(
 	sec_pipe->next_odm_pipe = sec_next;
 	sec_pipe->prev_odm_pipe = sec_prev;
 
-	sec_pipe->pipe_idx = pipe_idx;
+	sec_pipe->pipe_idx = (uint8_t)pipe_idx;
 	sec_pipe->plane_res.mi = pool->mis[pipe_idx];
 	sec_pipe->plane_res.hubp = pool->hubps[pipe_idx];
 	sec_pipe->plane_res.ipp = pool->ipps[pipe_idx];
 	sec_pipe->plane_res.xfm = pool->transforms[pipe_idx];
 	sec_pipe->plane_res.dpp = pool->dpps[pipe_idx];
-	sec_pipe->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst;
+	sec_pipe->plane_res.mpcc_inst = (uint8_t)pool->dpps[pipe_idx]->inst;
 	sec_pipe->stream_res.dsc = NULL;
 	if (odm) {
 		if (!sec_pipe->top_pipe)
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
index e16de323f39c..16ff43b58e00 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
@@ -259,11 +259,17 @@ const struct dc_stream_status *dc_stream_get_status_const(
 	return dc_state_get_stream_status(dc->current_state, stream);
 }
 
+struct dc_link *dc_stream_get_link(
+	const struct dc_stream_state *stream)
+{
+	return stream->link;
+}
+
 void program_cursor_attributes(
 	struct dc *dc,
 	struct dc_stream_state *stream)
 {
-	int i;
+	uint8_t i;
 	struct resource_context *res_ctx;
 	struct pipe_ctx *pipe_to_program = NULL;
 	bool enable_cursor_offload = dc_dmub_srv_is_cursor_offload_enabled(dc);
@@ -410,7 +416,7 @@ void program_cursor_position(
 	struct dc *dc,
 	struct dc_stream_state *stream)
 {
-	int i;
+	uint8_t i;
 	struct resource_context *res_ctx;
 	struct pipe_ctx *pipe_to_program = NULL;
 	bool enable_cursor_offload = dc_dmub_srv_is_cursor_offload_enabled(dc);
@@ -1032,14 +1038,18 @@ static int dc_stream_get_brightness_millinits_linear_interpolation (struct dc_st
 								     int refresh_hz)
 {
 	long long slope = 0;
+	long long y_intercept = 0;
+	long long brightness_millinits = 0;
+
 	if (stream->lumin_data.refresh_rate_hz[index2] != stream->lumin_data.refresh_rate_hz[index1]) {
 		slope = (stream->lumin_data.luminance_millinits[index2] - stream->lumin_data.luminance_millinits[index1]) /
 			    (stream->lumin_data.refresh_rate_hz[index2] - stream->lumin_data.refresh_rate_hz[index1]);
 	}
 
-	int y_intercept = stream->lumin_data.luminance_millinits[index2] - slope * stream->lumin_data.refresh_rate_hz[index2];
+	y_intercept = stream->lumin_data.luminance_millinits[index2] - slope * stream->lumin_data.refresh_rate_hz[index2];
+	brightness_millinits = y_intercept + (long long)refresh_hz * slope;
 
-	return (y_intercept + refresh_hz * slope);
+	return (int)brightness_millinits;
 }
 
 /*
@@ -1051,14 +1061,18 @@ static int dc_stream_get_refresh_hz_linear_interpolation (struct dc_stream_state
 							   int brightness_millinits)
 {
 	long long slope = 1;
+	long long y_intercept = 0;
+	long long refresh_hz = 0;
+
 	if (stream->lumin_data.refresh_rate_hz[index2] != stream->lumin_data.refresh_rate_hz[index1]) {
 		slope = (stream->lumin_data.luminance_millinits[index2] - stream->lumin_data.luminance_millinits[index1]) /
 				(stream->lumin_data.refresh_rate_hz[index2] - stream->lumin_data.refresh_rate_hz[index1]);
 	}
 
-	int y_intercept = stream->lumin_data.luminance_millinits[index2] - slope * stream->lumin_data.refresh_rate_hz[index2];
+	y_intercept = stream->lumin_data.luminance_millinits[index2] - slope * stream->lumin_data.refresh_rate_hz[index2];
+	refresh_hz = div64_s64((brightness_millinits - y_intercept), slope);
 
-	return ((int)div64_s64((brightness_millinits - y_intercept), slope));
+	return (int)refresh_hz;
 }
 
 /*
diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c
index a59b176d8e55..4da841826e73 100644
--- a/drivers/gpu/drm/amd/display/dc/core/dc_surface.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_surface.c
@@ -75,7 +75,7 @@ uint8_t  dc_plane_get_pipe_mask(struct dc_state *dc_state, const struct dc_plane
 		struct pipe_ctx *pipe_ctx = &dc_state->res_ctx.pipe_ctx[i];
 
 		if (pipe_ctx->plane_state == plane_state && pipe_ctx->plane_res.hubp)
-			pipe_mask |= 1 << pipe_ctx->plane_res.hubp->inst;
+			pipe_mask |= (uint8_t)(1 << pipe_ctx->plane_res.hubp->inst);
 	}
 
 	return pipe_mask;
diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index 7f55ba09b191..50ec5acb6c7b 100644
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -63,7 +63,7 @@ struct dcn_dsc_reg_state;
 struct dcn_optc_reg_state;
 struct dcn_dccg_reg_state;
 
-#define DC_VER "3.2.378"
+#define DC_VER "3.2.379"
 
 /**
  * MAX_SURFACES - representative of the upper bound of surfaces that can be piped to a single CRTC
@@ -1485,6 +1485,7 @@ union surface_update_flags {
 		uint32_t pixel_format_change:1;
 		uint32_t plane_size_change:1;
 		uint32_t gamut_remap_change:1;
+		uint32_t cursor_csc_color_matrix_change:1;
 
 		/* Full updates */
 		uint32_t new_plane:1;
@@ -1894,6 +1895,20 @@ struct dc_fast_update {
 #if defined(CONFIG_DRM_AMD_DC_DCN4_2)
 	struct cm_hist_control *cm_hist_control;
 #endif
+	/* stream-level fast updates */
+	const struct colorspace_transform *gamut_remap;
+	const struct dc_cursor_attributes *cursor_attributes;
+	const struct dc_cursor_position *cursor_position;
+	const struct periodic_interrupt_config *periodic_interrupt;
+	const enum dc_dither_option *dither_option;
+	struct dc_info_packet *vrr_infopacket;
+	struct dc_info_packet *vsc_infopacket;
+	struct dc_info_packet *vsp_infopacket;
+	struct dc_info_packet *hfvsif_infopacket;
+	struct dc_info_packet *vtem_infopacket;
+	struct dc_info_packet *adaptive_sync_infopacket;
+	struct dc_info_packet *avi_infopacket;
+	struct dc_info_packet *hdr_static_metadata;
 };
 
 struct dc_surface_update {
diff --git a/drivers/gpu/drm/amd/display/dc/dc_bios_types.h b/drivers/gpu/drm/amd/display/dc/dc_bios_types.h
index 6f96c5cf39fe..526f71616f94 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_bios_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_bios_types.h
@@ -102,7 +102,8 @@ struct dc_vbios_funcs {
 		struct bp_external_encoder_control *cntl);
 	enum bp_result (*dac_load_detection)(
 		struct dc_bios *bios,
-		enum engine_id engine_id);
+		enum engine_id engine_id,
+		struct graphics_object_id ext_enc_id);
 	enum bp_result (*transmitter_control)(
 		struct dc_bios *bios,
 		struct bp_transmitter_control *cntl);
diff --git a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
index 79c8b4cab053..eb713ed23f17 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
+++ b/drivers/gpu/drm/amd/display/dc/dc_dmub_srv.c
@@ -336,7 +336,7 @@ bool dc_dmub_srv_optimized_init_done(struct dc_dmub_srv *dc_dmub_srv)
 		return false;
 	}
 
-	return boot_status.bits.optimized_init_done;
+	return (bool)boot_status.bits.optimized_init_done;
 }
 
 bool dc_dmub_srv_notify_stream_mask(struct dc_dmub_srv *dc_dmub_srv,
@@ -346,7 +346,7 @@ bool dc_dmub_srv_notify_stream_mask(struct dc_dmub_srv *dc_dmub_srv,
 		return false;
 
 	return dc_wake_and_execute_gpint(dc_dmub_srv->ctx, DMUB_GPINT__IDLE_OPT_NOTIFY_STREAM_MASK,
-					 stream_mask, NULL, DM_DMUB_WAIT_TYPE_WAIT);
+				 (uint16_t)stream_mask, NULL, DM_DMUB_WAIT_TYPE_WAIT);
 }
 
 bool dc_dmub_srv_is_restore_required(struct dc_dmub_srv *dc_dmub_srv)
@@ -368,7 +368,7 @@ bool dc_dmub_srv_is_restore_required(struct dc_dmub_srv *dc_dmub_srv)
 		return false;
 	}
 
-	return boot_status.bits.restore_required;
+	return (bool)boot_status.bits.restore_required;
 }
 
 bool dc_dmub_srv_get_dmub_outbox0_msg(const struct dc *dc, struct dmcub_trace_buf_entry *entry)
@@ -415,7 +415,7 @@ void dc_dmub_srv_set_drr_manual_trigger_cmd(struct dc *dc, uint32_t tg_inst)
 static uint8_t dc_dmub_srv_get_pipes_for_stream(struct dc *dc, struct dc_stream_state *stream)
 {
 	uint8_t pipes = 0;
-	int i = 0;
+	uint8_t i = 0;
 
 	for (i = 0; i < MAX_PIPES; i++) {
 		struct pipe_ctx *pipe = &dc->current_state->res_ctx.pipe_ctx[i];
@@ -433,15 +433,15 @@ static void dc_dmub_srv_populate_fams_pipe_info(struct dc *dc, struct dc_state *
 	int j;
 	int pipe_idx = 0;
 
-	fams_pipe_data->pipe_index[pipe_idx++] = head_pipe->plane_res.hubp->inst;
+	fams_pipe_data->pipe_index[pipe_idx++] = (uint8_t)head_pipe->plane_res.hubp->inst;
 	for (j = 0; j < dc->res_pool->pipe_count; j++) {
 		struct pipe_ctx *split_pipe = &context->res_ctx.pipe_ctx[j];
 
 		if (split_pipe->stream == head_pipe->stream && (split_pipe->top_pipe || split_pipe->prev_odm_pipe)) {
-			fams_pipe_data->pipe_index[pipe_idx++] = split_pipe->plane_res.hubp->inst;
+			fams_pipe_data->pipe_index[pipe_idx++] = (uint8_t)split_pipe->plane_res.hubp->inst;
 		}
 	}
-	fams_pipe_data->pipe_count = pipe_idx;
+	fams_pipe_data->pipe_count = (uint8_t)pipe_idx;
 }
 
 bool dc_dmub_srv_p_state_delegate(struct dc *dc, bool should_manage_pstate, struct dc_state *context)
@@ -456,7 +456,7 @@ bool dc_dmub_srv_p_state_delegate(struct dc *dc, bool should_manage_pstate, stru
 	if (dc == NULL)
 		return false;
 
-	visual_confirm_enabled = dc->debug.visual_confirm == VISUAL_CONFIRM_FAMS;
+	visual_confirm_enabled = (uint8_t)(dc->debug.visual_confirm == VISUAL_CONFIRM_FAMS);
 
 	// Format command.
 	cmd.fw_assisted_mclk_switch.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH;
@@ -477,7 +477,8 @@ bool dc_dmub_srv_p_state_delegate(struct dc *dc, bool should_manage_pstate, stru
 			 */
 			stream_status = dc_state_get_stream_status(context, pipe->stream);
 			if (stream_status && !stream_status->fpo_in_use) {
-				cmd.fw_assisted_mclk_switch.config_data.vactive_stretch_margin_us = dc->debug.fpo_vactive_margin_us;
+				cmd.fw_assisted_mclk_switch.config_data.vactive_stretch_margin_us =
+					(uint16_t)dc->debug.fpo_vactive_margin_us;
 				break;
 			}
 		}
@@ -492,11 +493,13 @@ bool dc_dmub_srv_p_state_delegate(struct dc *dc, bool should_manage_pstate, stru
 		stream_status = dc_state_get_stream_status(context, pipe->stream);
 		if (stream_status && stream_status->fpo_in_use) {
 			struct pipe_ctx *pipe = &context->res_ctx.pipe_ctx[i];
-			uint8_t min_refresh_in_hz = (pipe->stream->timing.min_refresh_in_uhz + 999999) / 1000000;
+			uint8_t min_refresh_in_hz;
+
+			min_refresh_in_hz = (uint8_t)((pipe->stream->timing.min_refresh_in_uhz + 999999) / 1000000);
 
 			config_data->pipe_data[k].pix_clk_100hz = pipe->stream->timing.pix_clk_100hz;
 			config_data->pipe_data[k].min_refresh_in_hz = min_refresh_in_hz;
-			config_data->pipe_data[k].max_ramp_step = ramp_up_num_steps;
+			config_data->pipe_data[k].max_ramp_step = (uint8_t)ramp_up_num_steps;
 			config_data->pipe_data[k].pipes = dc_dmub_srv_get_pipes_for_stream(dc, pipe->stream);
 			dc_dmub_srv_populate_fams_pipe_info(dc, context, pipe, &config_data->pipe_data[k]);
 			k++;
@@ -551,7 +554,7 @@ void dc_dmub_srv_get_visual_confirm_color_cmd(struct dc *dc, struct pipe_ctx *pi
 	cmd.visual_confirm_color.header.sub_type = 0;
 	cmd.visual_confirm_color.header.ret_status = 1;
 	cmd.visual_confirm_color.header.payload_bytes = sizeof(struct dmub_cmd_visual_confirm_color_data);
-	cmd.visual_confirm_color.visual_confirm_color_data.visual_confirm_color.panel_inst = panel_inst;
+	cmd.visual_confirm_color.visual_confirm_color_data.visual_confirm_color.panel_inst = (uint16_t)panel_inst;
 
 	// If command was processed, copy feature caps to dmub srv
 	if (dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY) &&
@@ -589,17 +592,17 @@ static void populate_subvp_cmd_drr_info(struct dc *dc,
 	struct dc_crtc_timing *main_timing = &subvp_pipe->stream->timing;
 	struct dc_crtc_timing *phantom_timing;
 	struct dc_crtc_timing *drr_timing = &vblank_pipe->stream->timing;
-	uint16_t drr_frame_us = 0;
-	uint16_t min_drr_supported_us = 0;
-	uint16_t max_drr_supported_us = 0;
-	uint16_t max_drr_vblank_us = 0;
-	uint16_t max_drr_mallregion_us = 0;
-	uint16_t mall_region_us = 0;
-	uint16_t prefetch_us = 0;
-	uint16_t subvp_active_us = 0;
-	uint16_t drr_active_us = 0;
-	uint16_t min_vtotal_supported = 0;
-	uint16_t max_vtotal_supported = 0;
+	uint64_t drr_frame_us = 0;
+	uint64_t min_drr_supported_us = 0;
+	uint64_t max_drr_supported_us = 0;
+	uint64_t max_drr_vblank_us = 0;
+	uint64_t max_drr_mallregion_us = 0;
+	uint64_t mall_region_us = 0;
+	uint64_t prefetch_us = 0;
+	uint64_t subvp_active_us = 0;
+	uint64_t drr_active_us = 0;
+	uint64_t min_vtotal_supported = 0;
+	uint64_t max_vtotal_supported = 0;
 
 	if (!phantom_stream)
 		return;
@@ -639,9 +642,10 @@ static void populate_subvp_cmd_drr_info(struct dc *dc,
 	 */
 	max_vtotal_supported = max_vtotal_supported - dc->caps.subvp_drr_max_vblank_margin_us;
 
-	pipe_data->pipe_config.vblank_data.drr_info.min_vtotal_supported = min_vtotal_supported;
-	pipe_data->pipe_config.vblank_data.drr_info.max_vtotal_supported = max_vtotal_supported;
-	pipe_data->pipe_config.vblank_data.drr_info.drr_vblank_start_margin = dc->caps.subvp_drr_vblank_start_margin_us;
+	pipe_data->pipe_config.vblank_data.drr_info.min_vtotal_supported = (uint16_t)min_vtotal_supported;
+	pipe_data->pipe_config.vblank_data.drr_info.max_vtotal_supported = (uint16_t)max_vtotal_supported;
+	pipe_data->pipe_config.vblank_data.drr_info.drr_vblank_start_margin =
+		(uint16_t)dc->caps.subvp_drr_vblank_start_margin_us;
 }
 
 /**
@@ -686,14 +690,15 @@ static void populate_subvp_cmd_vblank_pipe_info(struct dc *dc,
 
 	pipe_data->mode = VBLANK;
 	pipe_data->pipe_config.vblank_data.pix_clk_100hz = vblank_pipe->stream->timing.pix_clk_100hz;
-	pipe_data->pipe_config.vblank_data.vblank_start = vblank_pipe->stream->timing.v_total -
-							vblank_pipe->stream->timing.v_front_porch;
-	pipe_data->pipe_config.vblank_data.vtotal = vblank_pipe->stream->timing.v_total;
-	pipe_data->pipe_config.vblank_data.htotal = vblank_pipe->stream->timing.h_total;
+	pipe_data->pipe_config.vblank_data.vblank_start = (uint16_t)(vblank_pipe->stream->timing.v_total -
+							vblank_pipe->stream->timing.v_front_porch);
+	pipe_data->pipe_config.vblank_data.vtotal = (uint16_t)vblank_pipe->stream->timing.v_total;
+	pipe_data->pipe_config.vblank_data.htotal = (uint16_t)vblank_pipe->stream->timing.h_total;
 	pipe_data->pipe_config.vblank_data.vblank_pipe_index = vblank_pipe->pipe_idx;
-	pipe_data->pipe_config.vblank_data.vstartup_start = vblank_pipe->pipe_dlg_param.vstartup_start;
+	pipe_data->pipe_config.vblank_data.vstartup_start = (uint16_t)vblank_pipe->pipe_dlg_param.vstartup_start;
 	pipe_data->pipe_config.vblank_data.vblank_end =
-			vblank_pipe->stream->timing.v_total - vblank_pipe->stream->timing.v_front_porch - vblank_pipe->stream->timing.v_addressable;
+			(uint16_t)(vblank_pipe->stream->timing.v_total -
+			vblank_pipe->stream->timing.v_front_porch - vblank_pipe->stream->timing.v_addressable);
 
 	if (vblank_pipe->stream->ignore_msa_timing_param &&
 		(vblank_pipe->stream->allow_freesync || vblank_pipe->stream->vrr_active_variable || vblank_pipe->stream->vrr_active_fixed))
@@ -739,10 +744,10 @@ static void update_subvp_prefetch_end_to_mall_start(struct dc *dc,
 	phantom_timing0 = &phantom_stream0->timing;
 	phantom_timing1 = &phantom_stream1->timing;
 
-	subvp0_prefetch_us = div64_u64(((uint64_t)(phantom_timing0->v_total - phantom_timing0->v_front_porch) *
+	subvp0_prefetch_us = (uint32_t)div64_u64(((uint64_t)(phantom_timing0->v_total - phantom_timing0->v_front_porch) *
 			(uint64_t)phantom_timing0->h_total * 1000000),
 			(((uint64_t)phantom_timing0->pix_clk_100hz * 100) + dc->caps.subvp_prefetch_end_to_mall_start_us));
-	subvp1_prefetch_us = div64_u64(((uint64_t)(phantom_timing1->v_total - phantom_timing1->v_front_porch) *
+	subvp1_prefetch_us = (uint32_t)div64_u64(((uint64_t)(phantom_timing1->v_total - phantom_timing1->v_front_porch) *
 			(uint64_t)phantom_timing1->h_total * 1000000),
 			(((uint64_t)phantom_timing1->pix_clk_100hz * 100) + dc->caps.subvp_prefetch_end_to_mall_start_us));
 
@@ -751,8 +756,8 @@ static void update_subvp_prefetch_end_to_mall_start(struct dc *dc,
 	if (subvp0_prefetch_us > subvp1_prefetch_us) {
 		pipe_data = &cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[1];
 		prefetch_delta_us = subvp0_prefetch_us - subvp1_prefetch_us;
-		pipe_data->pipe_config.subvp_data.prefetch_to_mall_start_lines =
-				div64_u64(((uint64_t)(dc->caps.subvp_prefetch_end_to_mall_start_us + prefetch_delta_us) *
+pipe_data->pipe_config.subvp_data.prefetch_to_mall_start_lines =
+				(uint16_t)div64_u64(((uint64_t)(dc->caps.subvp_prefetch_end_to_mall_start_us + prefetch_delta_us) *
 					((uint64_t)phantom_timing1->pix_clk_100hz * 100) + ((uint64_t)phantom_timing1->h_total * 1000000 - 1)),
 					((uint64_t)phantom_timing1->h_total * 1000000));
 
@@ -760,7 +765,7 @@ static void update_subvp_prefetch_end_to_mall_start(struct dc *dc,
 		pipe_data = &cmd->fw_assisted_mclk_switch_v2.config_data.pipe_data[0];
 		prefetch_delta_us = subvp1_prefetch_us - subvp0_prefetch_us;
 		pipe_data->pipe_config.subvp_data.prefetch_to_mall_start_lines =
-				div64_u64(((uint64_t)(dc->caps.subvp_prefetch_end_to_mall_start_us + prefetch_delta_us) *
+				(uint16_t)div64_u64(((uint64_t)(dc->caps.subvp_prefetch_end_to_mall_start_us + prefetch_delta_us) *
 					((uint64_t)phantom_timing0->pix_clk_100hz * 100) + ((uint64_t)phantom_timing0->h_total * 1000000 - 1)),
 					((uint64_t)phantom_timing0->h_total * 1000000));
 	}
@@ -800,14 +805,14 @@ static void populate_subvp_cmd_pipe_info(struct dc *dc,
 
 	pipe_data->mode = SUBVP;
 	pipe_data->pipe_config.subvp_data.pix_clk_100hz = subvp_pipe->stream->timing.pix_clk_100hz;
-	pipe_data->pipe_config.subvp_data.htotal = subvp_pipe->stream->timing.h_total;
-	pipe_data->pipe_config.subvp_data.vtotal = subvp_pipe->stream->timing.v_total;
+	pipe_data->pipe_config.subvp_data.htotal = (uint16_t)subvp_pipe->stream->timing.h_total;
+	pipe_data->pipe_config.subvp_data.vtotal = (uint16_t)subvp_pipe->stream->timing.v_total;
 	pipe_data->pipe_config.subvp_data.main_vblank_start =
-			main_timing->v_total - main_timing->v_front_porch;
+			(uint16_t)(main_timing->v_total - main_timing->v_front_porch);
 	pipe_data->pipe_config.subvp_data.main_vblank_end =
-			main_timing->v_total - main_timing->v_front_porch - main_timing->v_addressable;
-	pipe_data->pipe_config.subvp_data.mall_region_lines = phantom_timing->v_addressable;
-	pipe_data->pipe_config.subvp_data.main_pipe_index = subvp_pipe->stream_res.tg->inst;
+			(uint16_t)(main_timing->v_total - main_timing->v_front_porch - main_timing->v_addressable);
+	pipe_data->pipe_config.subvp_data.mall_region_lines = (uint16_t)phantom_timing->v_addressable;
+	pipe_data->pipe_config.subvp_data.main_pipe_index = (uint8_t)subvp_pipe->stream_res.tg->inst;
 	pipe_data->pipe_config.subvp_data.is_drr = subvp_pipe->stream->ignore_msa_timing_param &&
 		(subvp_pipe->stream->allow_freesync || subvp_pipe->stream->vrr_active_variable || subvp_pipe->stream->vrr_active_fixed);
 
@@ -822,25 +827,25 @@ static void populate_subvp_cmd_pipe_info(struct dc *dc,
 	reduce_fraction(subvp_pipe->plane_state->src_rect.height, subvp_pipe->plane_state->dst_rect.height,
 			&out_num_plane, &out_den_plane);
 	reduce_fraction(out_num_stream * out_num_plane, out_den_stream * out_den_plane, &out_num, &out_den);
-	pipe_data->pipe_config.subvp_data.scale_factor_numerator = out_num;
-	pipe_data->pipe_config.subvp_data.scale_factor_denominator = out_den;
+	pipe_data->pipe_config.subvp_data.scale_factor_numerator = (uint8_t)out_num;
+	pipe_data->pipe_config.subvp_data.scale_factor_denominator = (uint8_t)out_den;
 
 	// Prefetch lines is equal to VACTIVE + BP + VSYNC
 	pipe_data->pipe_config.subvp_data.prefetch_lines =
-			phantom_timing->v_total - phantom_timing->v_front_porch;
+			(uint16_t)(phantom_timing->v_total - phantom_timing->v_front_porch);
 
 	// Round up
 	pipe_data->pipe_config.subvp_data.prefetch_to_mall_start_lines =
-			div64_u64(((uint64_t)dc->caps.subvp_prefetch_end_to_mall_start_us * ((uint64_t)phantom_timing->pix_clk_100hz * 100) +
+			(uint16_t)div64_u64(((uint64_t)dc->caps.subvp_prefetch_end_to_mall_start_us * ((uint64_t)phantom_timing->pix_clk_100hz * 100) +
 					((uint64_t)phantom_timing->h_total * 1000000 - 1)), ((uint64_t)phantom_timing->h_total * 1000000));
 	pipe_data->pipe_config.subvp_data.processing_delay_lines =
-			div64_u64(((uint64_t)(dc->caps.subvp_fw_processing_delay_us) * ((uint64_t)phantom_timing->pix_clk_100hz * 100) +
+			(uint16_t)div64_u64(((uint64_t)(dc->caps.subvp_fw_processing_delay_us) * ((uint64_t)phantom_timing->pix_clk_100hz * 100) +
 					((uint64_t)phantom_timing->h_total * 1000000 - 1)), ((uint64_t)phantom_timing->h_total * 1000000));
 
 	if (subvp_pipe->bottom_pipe) {
-		pipe_data->pipe_config.subvp_data.main_split_pipe_index = subvp_pipe->bottom_pipe->pipe_idx;
+		pipe_data->pipe_config.subvp_data.main_split_pipe_index = (uint8_t)subvp_pipe->bottom_pipe->pipe_idx;
 	} else if (subvp_pipe->next_odm_pipe) {
-		pipe_data->pipe_config.subvp_data.main_split_pipe_index = subvp_pipe->next_odm_pipe->pipe_idx;
+		pipe_data->pipe_config.subvp_data.main_split_pipe_index = (uint8_t)subvp_pipe->next_odm_pipe->pipe_idx;
 	} else {
 		pipe_data->pipe_config.subvp_data.main_split_pipe_index = 0xF;
 	}
@@ -851,11 +856,11 @@ static void populate_subvp_cmd_pipe_info(struct dc *dc,
 
 		if (resource_is_pipe_type(phantom_pipe, OTG_MASTER) &&
 				phantom_pipe->stream == dc_state_get_paired_subvp_stream(context, subvp_pipe->stream)) {
-			pipe_data->pipe_config.subvp_data.phantom_pipe_index = phantom_pipe->stream_res.tg->inst;
+			pipe_data->pipe_config.subvp_data.phantom_pipe_index = (uint8_t)phantom_pipe->stream_res.tg->inst;
 			if (phantom_pipe->bottom_pipe) {
-				pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = phantom_pipe->bottom_pipe->plane_res.hubp->inst;
+				pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = (uint8_t)phantom_pipe->bottom_pipe->plane_res.hubp->inst;
 			} else if (phantom_pipe->next_odm_pipe) {
-				pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = phantom_pipe->next_odm_pipe->plane_res.hubp->inst;
+				pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = (uint8_t)phantom_pipe->next_odm_pipe->plane_res.hubp->inst;
 			} else {
 				pipe_data->pipe_config.subvp_data.phantom_split_pipe_index = 0xF;
 			}
@@ -933,15 +938,15 @@ void dc_dmub_setup_subvp_dmub_command(struct dc *dc,
 		if (subvp_count == 2) {
 			update_subvp_prefetch_end_to_mall_start(dc, context, &cmd, subvp_pipes);
 		}
-		cmd.fw_assisted_mclk_switch_v2.config_data.pstate_allow_width_us = dc->caps.subvp_pstate_allow_width_us;
-		cmd.fw_assisted_mclk_switch_v2.config_data.vertical_int_margin_us = dc->caps.subvp_vertical_int_margin_us;
+		cmd.fw_assisted_mclk_switch_v2.config_data.pstate_allow_width_us = (uint8_t)dc->caps.subvp_pstate_allow_width_us;
+		cmd.fw_assisted_mclk_switch_v2.config_data.vertical_int_margin_us = (uint8_t)dc->caps.subvp_vertical_int_margin_us;
 
 		// Store the original watermark value for this SubVP config so we can lower it when the
 		// MCLK switch starts
 		wm_val_refclk = context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns *
 				(dc->res_pool->ref_clocks.dchub_ref_clock_inKhz / 1000) / 1000;
 
-		cmd.fw_assisted_mclk_switch_v2.config_data.watermark_a_cache = wm_val_refclk < 0xFFFF ? wm_val_refclk : 0xFFFF;
+		cmd.fw_assisted_mclk_switch_v2.config_data.watermark_a_cache = (uint16_t)(wm_val_refclk < 0xFFFF ? wm_val_refclk : 0xFFFF);
 	}
 
 	dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
@@ -1060,10 +1065,10 @@ static void dc_build_cursor_update_payload0(
 	payload->cursor_rect.width  = hubp->cur_rect.w;
 	payload->cursor_rect.height = hubp->cur_rect.h;
 
-	payload->enable      = hubp->pos.cur_ctl.bits.cur_enable;
+	payload->enable      = (uint8_t)hubp->pos.cur_ctl.bits.cur_enable;
 	payload->pipe_idx    = p_idx;
-	payload->panel_inst  = panel_inst;
-	payload->otg_inst    = pipe_ctx->stream_res.tg->inst;
+	payload->panel_inst  = (uint8_t)panel_inst;
+	payload->otg_inst    = (uint8_t)pipe_ctx->stream_res.tg->inst;
 }
 
 static void dc_build_cursor_position_update_payload0(
@@ -1645,7 +1650,7 @@ bool dc_dmub_srv_should_detect(struct dc_dmub_srv *dc_dmub_srv)
 	if (dc_dmub_srv->dmub->shared_state &&
 	    dc_dmub_srv->dmub->meta_info.feature_bits.bits.shared_state_link_detection) {
 		ips_fw = &dc_dmub_srv->dmub->shared_state[DMUB_SHARED_SHARE_FEATURE__IPS_FW].data.ips_fw;
-		return ips_fw->signals.bits.detection_required;
+		return (bool)ips_fw->signals.bits.detection_required;
 	}
 
 	/* Detection may require reading scratch 0 - exit out of idle prior to the read. */
@@ -1807,7 +1812,7 @@ static void dc_dmub_srv_rb_based_fams2_update_config(struct dc *dc,
 		struct dc_state *context,
 		bool enable)
 {
-	uint8_t num_cmds = 1;
+	uint32_t num_cmds = 1;
 	uint32_t i;
 	union dmub_rb_cmd cmd[2 * MAX_STREAMS + 1];
 	struct dmub_rb_cmd_fams2 *global_cmd = &cmd[0].fams2_config;
@@ -1940,7 +1945,7 @@ void dc_dmub_srv_fams2_drr_update(struct dc *dc,
 
 	cmd.fams2_drr_update.header.type = DMUB_CMD__FW_ASSISTED_MCLK_SWITCH;
 	cmd.fams2_drr_update.header.sub_type = DMUB_CMD__FAMS2_DRR_UPDATE;
-	cmd.fams2_drr_update.dmub_optc_state_req.tg_inst = tg_inst;
+	cmd.fams2_drr_update.dmub_optc_state_req.tg_inst = (uint8_t)tg_inst;
 	cmd.fams2_drr_update.dmub_optc_state_req.v_total_max = vtotal_max;
 	cmd.fams2_drr_update.dmub_optc_state_req.v_total_min = vtotal_min;
 	cmd.fams2_drr_update.dmub_optc_state_req.v_total_mid = vtotal_mid;
@@ -1991,10 +1996,10 @@ void dc_dmub_srv_fams2_passthrough_flip(
 		cmds[num_cmds].fams2_flip.header.multi_cmd_pending = 1;
 
 		/* set topology info */
-		cmds[num_cmds].fams2_flip.flip_info.pipe_mask = dc_plane_get_pipe_mask(state, plane_state);
-		if (stream_status)
-			cmds[num_cmds].fams2_flip.flip_info.otg_inst = stream_status->primary_otg_inst;
-
+		cmds[num_cmds].fams2_flip.flip_info.pipe_mask = (uint8_t)dc_plane_get_pipe_mask(state, plane_state);
+		if (stream_status) {
+			cmds[num_cmds].fams2_flip.flip_info.otg_inst = (uint8_t)stream_status->primary_otg_inst;
+		}
 		cmds[num_cmds].fams2_flip.flip_info.config.bits.is_immediate = plane_state->flip_immediate;
 
 		/* build address info for command */
diff --git a/drivers/gpu/drm/amd/display/dc/dc_fused_io.c b/drivers/gpu/drm/amd/display/dc/dc_fused_io.c
index fee69642fb93..664cb4abf623 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_fused_io.c
+++ b/drivers/gpu/drm/amd/display/dc/dc_fused_io.c
@@ -23,11 +23,11 @@ static bool op_i2c_convert(
 
 	req->type = type;
 	loc->is_aux = false;
-	loc->ddc_line = ddc_line;
+	loc->ddc_line = (uint8_t)ddc_line;
 	loc->over_aux = over_aux;
 	loc->address = op->address;
 	loc->offset = op->offset;
-	loc->length = op->size;
+	loc->length = (uint8_t)op->size;
 	memcpy(req->buffer, op->data, op->size);
 
 	return true;
@@ -84,7 +84,7 @@ static bool atomic_write_poll_read(
 			timeout_us += timeout_per_aux_transaction_us * (io->request.u.aux.length / 16);
 	}
 
-	if (!dm_helpers_execute_fused_io(link->ctx, link, commands, count, timeout_us))
+	if (!dm_helpers_execute_fused_io(link->ctx, link, commands, count, (uint32_t)timeout_us))
 		return false;
 
 	return commands[0].fused_io.request.status == FUSED_REQUEST_STATUS_SUCCESS;
diff --git a/drivers/gpu/drm/amd/display/dc/dc_helper.c b/drivers/gpu/drm/amd/display/dc/dc_helper.c
index 77299767096f..e221384f7611 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_helper.c
+++ b/drivers/gpu/drm/amd/display/dc/dc_helper.c
@@ -122,7 +122,7 @@ static void set_reg_field_values(struct dc_reg_value_masks *field_value_mask,
 		field_value = va_arg(ap, uint32_t);
 
 		set_reg_field_value_masks(field_value_mask,
-				field_value, mask, shift);
+				field_value, mask, (uint8_t)shift);
 		i++;
 	}
 }
@@ -459,7 +459,7 @@ void generic_reg_wait(const struct dc_context *ctx,
 
 		reg_val = dm_read_reg(ctx, addr);
 
-		field_value = get_reg_field_value_ex(reg_val, mask, shift);
+		field_value = get_reg_field_value_ex(reg_val, mask, (uint8_t)shift);
 
 		if (field_value == condition_value) {
 			if (i * delay_between_poll_us > 1000)
@@ -525,7 +525,7 @@ uint32_t generic_indirect_reg_get(const struct dc_context *ctx,
 		mask = va_arg(ap, uint32_t);
 		field_value = va_arg(ap, uint32_t *);
 
-		*field_value = get_reg_field_value_ex(value, mask, shift);
+		*field_value = get_reg_field_value_ex(value, mask, (uint8_t)shift);
 		i++;
 	}
 
@@ -554,7 +554,7 @@ uint32_t generic_indirect_reg_update_ex(const struct dc_context *ctx,
 		mask = va_arg(ap, uint32_t);
 		field_value = va_arg(ap, uint32_t);
 
-		reg_val = set_reg_field_value_ex(reg_val, field_value, mask, shift);
+		reg_val = set_reg_field_value_ex(reg_val, field_value, mask, (uint8_t)shift);
 		i++;
 	}
 
@@ -584,7 +584,7 @@ uint32_t generic_indirect_reg_update_ex_sync(const struct dc_context *ctx,
 		mask = va_arg(ap, uint32_t);
 		field_value = va_arg(ap, uint32_t);
 
-		reg_val = set_reg_field_value_ex(reg_val, field_value, mask, shift);
+		reg_val = set_reg_field_value_ex(reg_val, field_value, mask, (uint8_t)shift);
 		i++;
 	}
 
@@ -615,7 +615,7 @@ uint32_t generic_indirect_reg_get_sync(const struct dc_context *ctx,
 		mask = va_arg(ap, uint32_t);
 		field_value = va_arg(ap, uint32_t *);
 
-		*field_value = get_reg_field_value_ex(value, mask, shift);
+		*field_value = get_reg_field_value_ex(value, mask, (uint8_t)shift);
 		i++;
 	}
 
diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h
index 7c38fa6f8cb1..6a8c1390b85f 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_stream.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h
@@ -64,35 +64,6 @@ struct dc_stream_status {
 	bool fpo_in_use;
 };
 
-enum hubp_dmdata_mode {
-	DMDATA_SW_MODE,
-	DMDATA_HW_MODE
-};
-
-struct dc_dmdata_attributes {
-	/* Specifies whether dynamic meta data will be updated by software
-	 * or has to be fetched by hardware (DMA mode)
-	 */
-	enum hubp_dmdata_mode dmdata_mode;
-	/* Specifies if current dynamic meta data is to be used only for the current frame */
-	bool dmdata_repeat;
-	/* Specifies the size of Dynamic Metadata surface in byte.  Size of 0 means no Dynamic metadata is fetched */
-	uint32_t dmdata_size;
-	/* Specifies if a new dynamic meta data should be fetched for an upcoming frame */
-	bool dmdata_updated;
-	/* If hardware mode is used, the base address where DMDATA surface is located */
-	PHYSICAL_ADDRESS_LOC address;
-	/* Specifies whether QOS level will be provided by TTU or it will come from DMDATA_QOS_LEVEL */
-	bool dmdata_qos_mode;
-	/* If qos_mode = 1, this is the QOS value to be used: */
-	uint32_t dmdata_qos_level;
-	/* Specifies the value in unit of REFCLK cycles to be added to the
-	 * current time to produce the Amortized deadline for Dynamic Metadata chunk request
-	 */
-	uint32_t dmdata_dl_delta;
-	/* An unbounded array of uint32s, represents software dmdata to be loaded */
-	uint32_t *dmdata_sw_data;
-};
 
 struct dc_writeback_info {
 	bool wb_enabled;
@@ -146,6 +117,12 @@ union stream_update_flags {
 		uint32_t fams_changed : 1;
 		uint32_t scaler_sharpener : 1;
 		uint32_t sharpening_required : 1;
+		uint32_t cursor_attr : 1;
+		uint32_t cursor_pos : 1;
+		uint32_t periodic_interrupt : 1;
+		uint32_t info_frame : 1;
+		uint32_t dmdata : 1;
+		uint32_t dither : 1;
 	} bits;
 
 	uint32_t raw;
@@ -517,6 +494,9 @@ struct surface_update_descriptor dc_check_update_surfaces_for_stream(
 		int surface_count,
 		struct dc_stream_update *stream_update);
 
+struct dc_link *dc_stream_get_link(
+	const struct dc_stream_state *dc_stream);
+
 /**
  * Create a new default stream for the requested sink
  */
diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h
index c08d5c005df6..476db257d4ee 100644
--- a/drivers/gpu/drm/amd/display/dc/dc_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_types.h
@@ -790,6 +790,36 @@ struct dc_clock_config {
 	uint32_t current_clock_khz;/*current clock in use*/
 };
 
+enum hubp_dmdata_mode {
+	DMDATA_SW_MODE,
+	DMDATA_HW_MODE
+};
+
+struct dc_dmdata_attributes {
+	/* Specifies whether dynamic meta data will be updated by software
+	 * or has to be fetched by hardware (DMA mode)
+	 */
+	enum hubp_dmdata_mode dmdata_mode;
+	/* Specifies if current dynamic meta data is to be used only for the current frame */
+	bool dmdata_repeat;
+	/* Specifies the size of Dynamic Metadata surface in byte.  Size of 0 means no Dynamic metadata is fetched */
+	uint32_t dmdata_size;
+	/* Specifies if a new dynamic meta data should be fetched for an upcoming frame */
+	bool dmdata_updated;
+	/* If hardware mode is used, the base address where DMDATA surface is located */
+	PHYSICAL_ADDRESS_LOC address;
+	/* Specifies whether QOS level will be provided by TTU or it will come from DMDATA_QOS_LEVEL */
+	bool dmdata_qos_mode;
+	/* If qos_mode = 1, this is the QOS value to be used: */
+	uint32_t dmdata_qos_level;
+	/* Specifies the value in unit of REFCLK cycles to be added to the
+	 * current time to produce the Amortized deadline for Dynamic Metadata chunk request
+	 */
+	uint32_t dmdata_dl_delta;
+	/* An unbounded array of uint32s, represents software dmdata to be loaded */
+	uint32_t *dmdata_sw_data;
+};
+
 struct hw_asic_id {
 	uint32_t chip_id;
 	uint32_t chip_family;
diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
index a72bf413fad6..21dcb812fbf7 100644
--- a/drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
@@ -576,7 +576,7 @@ void dccg31_set_dtbclk_dto(
 
 		// phase / modulo = dtbclk / dtbclk ref
 		modulo = params->ref_dtbclk_khz * 1000;
-		phase = div_u64((((unsigned long long)modulo * req_dtbclk_khz) + params->ref_dtbclk_khz - 1),
+		phase = (uint32_t)div_u64((((unsigned long long)modulo * req_dtbclk_khz) + params->ref_dtbclk_khz - 1),
 				params->ref_dtbclk_khz);
 
 		REG_UPDATE(OTG_PIXEL_RATE_CNTL[params->otg_inst],
@@ -620,7 +620,7 @@ void dccg31_set_audio_dtbclk_dto(
 
 		// phase / modulo = dtbclk / dtbclk ref
 		modulo = params->ref_dtbclk_khz * 1000;
-		phase = div_u64((((unsigned long long)modulo * params->req_audio_dtbclk_khz) + params->ref_dtbclk_khz - 1),
+		phase = (uint32_t)div_u64((((unsigned long long)modulo * params->req_audio_dtbclk_khz) + params->ref_dtbclk_khz - 1),
 			params->ref_dtbclk_khz);
 
 
diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
index 97605a416031..417ed9d0e6bb 100644
--- a/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
@@ -610,11 +610,13 @@ void dccg401_set_dp_dto(
 		 * int = target_pix_rate / reference_clock
 		 * phase = target_pix_rate - int * reference_clock,
 		 * modulo = reference_clock */
-		dto_integer = div_u64(params->pixclk_hz, dto_modulo_hz);
+
+		/* dto_modulo_hz = refclk (~100 MHz), well within uint32_t range */
+		dto_integer = div_u64(params->pixclk_hz, (uint32_t)dto_modulo_hz);
 		dto_phase_hz = params->pixclk_hz - dto_integer * dto_modulo_hz;
 
-		if (dto_phase_hz <= 0 && dto_integer <= 0) {
-			/* negative pixel rate should never happen */
+		if (dto_phase_hz == 0 && dto_integer == 0) {
+			/* zero pixel rate should never happen */
 			BREAK_TO_DEBUGGER();
 			return;
 		}
@@ -656,25 +658,25 @@ void dccg401_set_dp_dto(
 
 		dccg401_set_dtbclk_p_src(dccg, params->clk_src, params->otg_inst);
 
-		REG_WRITE(DP_DTO_PHASE[params->otg_inst], dto_phase_hz);
-		REG_WRITE(DP_DTO_MODULO[params->otg_inst], dto_modulo_hz);
+		REG_WRITE(DP_DTO_PHASE[params->otg_inst], (uint32_t)dto_phase_hz);
+		REG_WRITE(DP_DTO_MODULO[params->otg_inst], (uint32_t)dto_modulo_hz);
 
 		switch (params->otg_inst) {
 		case 0:
 			REG_UPDATE(OTG_PIXEL_RATE_DIV,
-					DPDTO0_INT, dto_integer);
+					DPDTO0_INT, (uint32_t)dto_integer);
 			break;
 		case 1:
 			REG_UPDATE(OTG_PIXEL_RATE_DIV,
-					DPDTO1_INT, dto_integer);
+					DPDTO1_INT, (uint32_t)dto_integer);
 			break;
 		case 2:
 			REG_UPDATE(OTG_PIXEL_RATE_DIV,
-					DPDTO2_INT, dto_integer);
+					DPDTO2_INT, (uint32_t)dto_integer);
 			break;
 		case 3:
 			REG_UPDATE(OTG_PIXEL_RATE_DIV,
-					DPDTO3_INT, dto_integer);
+					DPDTO3_INT, (uint32_t)dto_integer);
 			break;
 		default:
 			BREAK_TO_DEBUGGER();
diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c
index b813310763e5..9612f4498ef6 100644
--- a/drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c
@@ -6,6 +6,7 @@
 #include "core_types.h"
 #include "dcn35/dcn35_dccg.h"
 #include "dcn42_dccg.h"
+#include "dcn20/dcn20_dccg.h"
 
 #define TO_DCN_DCCG(dccg)\
 	container_of(dccg, struct dcn_dccg, base)
@@ -306,6 +307,7 @@ static const struct dccg_funcs dccg42_funcs = {
 	.dccg_root_gate_disable_control = dccg35_root_gate_disable_control,
 	.dccg_read_reg_state = dccg31_read_reg_state,
 	.dccg_enable_global_fgcg = dccg42_enable_global_fgcg,
+	.allow_clock_gating = dccg2_allow_clock_gating
 };
 
 struct dccg *dccg42_create(
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
index 673bb87d2c17..eee58f946fae 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_aux.c
@@ -321,7 +321,7 @@ static int read_channel_reply(struct dce_aux *engine, uint32_t size,
 			uint32_t aux_sw_data_val;
 
 			REG_GET(AUX_SW_DATA, AUX_SW_DATA, &aux_sw_data_val);
-			buffer[i] = aux_sw_data_val;
+			buffer[i] = (uint8_t)aux_sw_data_val;
 			++i;
 		}
 
@@ -375,7 +375,7 @@ static enum aux_return_code_type get_channel_status(
 			(value & AUX_SW_STATUS__AUX_SW_RX_RECV_INVALID_L_MASK))
 			return AUX_RET_ERROR_INVALID_REPLY;
 
-		*returned_bytes = get_reg_field_value(value,
+		*returned_bytes = (uint8_t)get_reg_field_value(value,
 				AUX_SW_STATUS,
 				AUX_SW_REPLY_BYTE_COUNT);
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
index 25c13822fede..ac9eed58c415 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
@@ -162,11 +162,9 @@ static bool calculate_fb_and_fractional_fb_divider(
 	feedback_divider *= (uint64_t)
 			(calc_pll_cs->fract_fb_divider_precision_factor);
 
-	*feedback_divider_param =
-		div_u64_rem(
-			feedback_divider,
-			calc_pll_cs->fract_fb_divider_factor,
-			fract_feedback_divider_param);
+	*feedback_divider_param = (uint32_t)div_u64_rem(
+		feedback_divider, calc_pll_cs->fract_fb_divider_factor,
+		fract_feedback_divider_param);
 
 	if (*feedback_divider_param != 0)
 		return true;
@@ -240,7 +238,7 @@ static bool calc_fb_divider_checking_tolerance(
 		pll_settings->calculated_pix_clk_100hz =
 			actual_calculated_clock_100hz;
 		pll_settings->vco_freq =
-			div_u64((u64)actual_calculated_clock_100hz * post_divider, 10);
+			(uint32_t)div_u64((u64)actual_calculated_clock_100hz * post_divider, 10);
 		return true;
 	}
 	return false;
@@ -440,8 +438,7 @@ static bool pll_adjust_pix_clk(
 	bp_adjust_pixel_clock_params.
 		encoder_object_id = pix_clk_params->encoder_object_id;
 	bp_adjust_pixel_clock_params.signal_type = pix_clk_params->signal_type;
-	bp_adjust_pixel_clock_params.
-		ss_enable = pix_clk_params->flags.ENABLE_SS;
+	bp_adjust_pixel_clock_params.ss_enable = pix_clk_params->flags.ENABLE_SS != 0;
 	bp_result = clk_src->bios->funcs->adjust_pixel_clock(
 			clk_src->bios, &bp_adjust_pixel_clock_params);
 	if (bp_result == BP_RESULT_OK) {
@@ -958,7 +955,7 @@ static bool dce112_program_pix_clk(
 		dce112_program_pixel_clk_resync(clk_src,
 					pix_clk_params->signal_type,
 					pix_clk_params->color_depth,
-					pix_clk_params->flags.SUPPORT_YCBCR420);
+					pix_clk_params->flags.SUPPORT_YCBCR420 != 0);
 
 	return true;
 }
@@ -1059,7 +1056,7 @@ static bool dcn31_program_pix_clk(
 			dce112_program_pixel_clk_resync(clk_src,
 						pix_clk_params->signal_type,
 						pix_clk_params->color_depth,
-						pix_clk_params->flags.SUPPORT_YCBCR420);
+						pix_clk_params->flags.SUPPORT_YCBCR420 != 0);
 	}
 
 	return true;
@@ -1162,7 +1159,7 @@ static bool dcn401_program_pix_clk(
 			dce112_program_pixel_clk_resync(clk_src,
 						pix_clk_params->signal_type,
 						pix_clk_params->color_depth,
-						pix_clk_params->flags.SUPPORT_YCBCR420);
+						pix_clk_params->flags.SUPPORT_YCBCR420 != 0);
 	}
 
 	return true;
@@ -1211,9 +1208,8 @@ static bool get_pixel_clk_frequency_100hz(
 			 */
 			modulo_hz = REG_READ(MODULO[inst]);
 			if (modulo_hz)
-				*pixel_clk_khz = div_u64((uint64_t)clock_hz*
-					dp_dto_ref_khz*10,
-					modulo_hz);
+				*pixel_clk_khz = (unsigned int)div_u64((uint64_t)clock_hz *
+					dp_dto_ref_khz * 10, modulo_hz);
 			else
 				*pixel_clk_khz = 0;
 		} else {
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c
index fe239a96121e..05892ab4529f 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_hw.c
@@ -120,7 +120,7 @@ static void process_channel_reply(
 		uint32_t i2c_data;
 
 		REG_GET(DC_I2C_DATA, DC_I2C_DATA, &i2c_data);
-		*buffer++ = i2c_data;
+		*buffer++ = (uint8_t)i2c_data;
 
 		--length;
 	}
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c
index 52e05b9185f1..e64b3b6bff5c 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_i2c_sw.c
@@ -75,7 +75,7 @@ static void release_engine_dce_sw(
 static bool wait_for_scl_high_sw(
 	struct dc_context *ctx,
 	struct ddc *ddc,
-	uint16_t clock_delay_div_4)
+	uint32_t clock_delay_div_4)
 {
 	(void)ctx;
 	uint32_t scl_retry = 0;
@@ -97,7 +97,7 @@ static bool wait_for_scl_high_sw(
 static bool write_byte_sw(
 	struct dc_context *ctx,
 	struct ddc *ddc_handle,
-	uint16_t clock_delay_div_4,
+	uint32_t clock_delay_div_4,
 	uint8_t byte)
 {
 	int32_t shift = 7;
@@ -154,7 +154,7 @@ static bool write_byte_sw(
 static bool read_byte_sw(
 	struct dc_context *ctx,
 	struct ddc *ddc_handle,
-	uint16_t clock_delay_div_4,
+	uint32_t clock_delay_div_4,
 	uint8_t *byte,
 	bool more)
 {
@@ -214,7 +214,7 @@ static bool read_byte_sw(
 static bool stop_sync_sw(
 	struct dc_context *ctx,
 	struct ddc *ddc_handle,
-	uint16_t clock_delay_div_4)
+	uint32_t clock_delay_div_4)
 {
 	uint32_t retry = 0;
 
@@ -251,7 +251,7 @@ static bool stop_sync_sw(
 static bool i2c_write_sw(
 	struct dc_context *ctx,
 	struct ddc *ddc_handle,
-	uint16_t clock_delay_div_4,
+	uint32_t clock_delay_div_4,
 	uint8_t address,
 	uint32_t length,
 	const uint8_t *data)
@@ -273,7 +273,7 @@ static bool i2c_write_sw(
 static bool i2c_read_sw(
 	struct dc_context *ctx,
 	struct ddc *ddc_handle,
-	uint16_t clock_delay_div_4,
+	uint32_t clock_delay_div_4,
 	uint8_t address,
 	uint32_t length,
 	uint8_t *data)
@@ -298,7 +298,7 @@ static bool i2c_read_sw(
 static bool start_sync_sw(
 	struct dc_context *ctx,
 	struct ddc *ddc_handle,
-	uint16_t clock_delay_div_4)
+	uint32_t clock_delay_div_4)
 {
 	uint32_t retry = 0;
 
@@ -399,7 +399,7 @@ static void dce_i2c_sw_engine_submit_channel_request(struct dce_i2c_sw *engine,
 						     struct i2c_request_transaction_data *req)
 {
 	struct ddc *ddc = engine->ddc;
-	uint16_t clock_delay_div_4 = engine->clock_delay >> 2;
+	uint32_t clock_delay_div_4 = engine->clock_delay >> 2;
 
 	/* send sync (start / repeated start) */
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.c b/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.c
index de31fb1b6819..31a9181c6a2b 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.c
@@ -209,7 +209,7 @@ static void dce_driver_set_backlight(struct panel_cntl *panel_cntl,
 	if (pwm_period_bitcnt == 0)
 		bit_count = 16;
 	else
-		bit_count = pwm_period_bitcnt;
+		bit_count = (uint8_t)pwm_period_bitcnt;
 
 	/* e.g. maskedPwmPeriod = 0x24 when bitCount is 6 */
 	masked_pwm_period = masked_pwm_period & ((1 << bit_count) - 1);
@@ -224,7 +224,7 @@ static void dce_driver_set_backlight(struct panel_cntl *panel_cntl,
 	 * components shift by bitCount then mask 16 bits and add rounding bit
 	 * from MSB of fraction e.g. 0x86F7 = ((0x21BDC0 >> 6) & 0xFFF) + 0
 	 */
-	backlight_16bit = active_duty_cycle >> bit_count;
+	backlight_16bit = (uint32_t)(active_duty_cycle >> bit_count);
 	backlight_16bit &= 0xFFFF;
 	backlight_16bit += (active_duty_cycle >> (bit_count - 1)) & 0x1;
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
index c1448ae47366..d178dcc4306d 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_transform.c
@@ -802,7 +802,7 @@ static void program_bit_depth_reduction(
 
 	ASSERT(depth <= COLOR_DEPTH_121212); /* Invalid clamp bit depth */
 
-	spatial_dither_enable = bit_depth_params->flags.SPATIAL_DITHER_ENABLED;
+	spatial_dither_enable = bit_depth_params->flags.SPATIAL_DITHER_ENABLED != 0;
 	/* Default to 12 bit truncation without rounding */
 	trunc_round_depth = DCP_OUT_TRUNC_ROUND_DEPTH_12BIT;
 	trunc_mode = DCP_OUT_TRUNC_ROUND_MODE_TRUNCATE;
@@ -835,9 +835,9 @@ static void program_bit_depth_reduction(
 		   spatial_dither_enable,
 		   DCP_SPATIAL_DITHER_MODE_A_AA_A,
 		   DCP_SPATIAL_DITHER_DEPTH_30BPP,
-		   bit_depth_params->flags.FRAME_RANDOM,
-		   bit_depth_params->flags.RGB_RANDOM,
-		   bit_depth_params->flags.HIGHPASS_RANDOM);
+		   bit_depth_params->flags.FRAME_RANDOM != 0,
+		   bit_depth_params->flags.RGB_RANDOM != 0,
+		   bit_depth_params->flags.HIGHPASS_RANDOM != 0);
 }
 
 #if defined(CONFIG_DRM_AMD_DC_SI)
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c
index 806b5709c9e7..a3cd04fc44f7 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_abm_lcd.c
@@ -176,7 +176,7 @@ void dmub_abm_init_config(struct abm *abm,
 	cmd.abm_init_config.header.type = DMUB_CMD__ABM;
 	cmd.abm_init_config.header.sub_type = DMUB_CMD__ABM_INIT_CONFIG;
 	cmd.abm_init_config.abm_init_config_data.src.quad_part = dc->dmub_srv->dmub->scratch_mem_fb.gpu_addr;
-	cmd.abm_init_config.abm_init_config_data.bytes = bytes;
+	cmd.abm_init_config.abm_init_config_data.bytes = (uint16_t)bytes;
 	cmd.abm_init_config.abm_init_config_data.version = DMUB_CMD_ABM_CONTROL_VERSION_1;
 	cmd.abm_init_config.abm_init_config_data.panel_mask = panel_mask;
 
@@ -237,7 +237,7 @@ bool dmub_abm_save_restore(
 	cmd.abm_save_restore.header.sub_type = DMUB_CMD__ABM_SAVE_RESTORE;
 
 	cmd.abm_save_restore.abm_init_config_data.src.quad_part = dc->dmub_srv->dmub->scratch_mem_fb.gpu_addr;
-	cmd.abm_save_restore.abm_init_config_data.bytes = bytes;
+	cmd.abm_save_restore.abm_init_config_data.bytes = (uint16_t)bytes;
 	cmd.abm_save_restore.abm_init_config_data.version = DMUB_CMD_ABM_CONTROL_VERSION_1;
 	cmd.abm_save_restore.abm_init_config_data.panel_mask = panel_mask;
 
@@ -265,10 +265,10 @@ bool dmub_abm_set_pipe(struct abm *abm,
 	memset(&cmd, 0, sizeof(cmd));
 	cmd.abm_set_pipe.header.type = DMUB_CMD__ABM;
 	cmd.abm_set_pipe.header.sub_type = DMUB_CMD__ABM_SET_PIPE;
-	cmd.abm_set_pipe.abm_set_pipe_data.otg_inst = otg_inst;
-	cmd.abm_set_pipe.abm_set_pipe_data.pwrseq_inst = pwrseq_inst;
-	cmd.abm_set_pipe.abm_set_pipe_data.set_pipe_option = option;
-	cmd.abm_set_pipe.abm_set_pipe_data.panel_inst = panel_inst;
+	cmd.abm_set_pipe.abm_set_pipe_data.otg_inst = (uint8_t)otg_inst;
+	cmd.abm_set_pipe.abm_set_pipe_data.pwrseq_inst = (uint8_t)pwrseq_inst;
+	cmd.abm_set_pipe.abm_set_pipe_data.set_pipe_option = (uint8_t)option;
+	cmd.abm_set_pipe.abm_set_pipe_data.panel_inst = (uint8_t)panel_inst;
 	cmd.abm_set_pipe.abm_set_pipe_data.ramping_boundary = ramping_boundary;
 	cmd.abm_set_pipe.header.payload_bytes = sizeof(struct dmub_cmd_abm_set_pipe_data);
 
@@ -308,7 +308,7 @@ bool dmub_abm_set_event(struct abm *abm, unsigned int scaling_enable, unsigned i
 	memset(&cmd, 0, sizeof(cmd));
 	cmd.abm_set_event.header.type = DMUB_CMD__ABM;
 	cmd.abm_set_event.header.sub_type = DMUB_CMD__ABM_SET_EVENT;
-	cmd.abm_set_event.abm_set_event_data.vb_scaling_enable = scaling_enable;
+	cmd.abm_set_event.abm_set_event_data.vb_scaling_enable = (uint8_t)scaling_enable;
 	cmd.abm_set_event.abm_set_event_data.vb_scaling_strength_mapping = scaling_strength_map;
 	cmd.abm_set_event.abm_set_event_data.panel_mask = (1<<panel_inst);
 	cmd.abm_set_event.header.payload_bytes = sizeof(struct dmub_cmd_abm_set_event_data);
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
index f94fd007af23..45630c3effe1 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
@@ -341,26 +341,26 @@ static bool dmub_psr_copy_settings(struct dmub_psr *dmub,
 	copy_settings_data->mpcc_inst				= pipe_ctx->plane_res.mpcc_inst;
 
 	if (pipe_ctx->plane_res.dpp)
-		copy_settings_data->dpp_inst			= pipe_ctx->plane_res.dpp->inst;
+		copy_settings_data->dpp_inst			= (uint8_t)pipe_ctx->plane_res.dpp->inst;
 	else
 		copy_settings_data->dpp_inst			= 0;
 	if (pipe_ctx->stream_res.opp)
-		copy_settings_data->opp_inst			= pipe_ctx->stream_res.opp->inst;
+		copy_settings_data->opp_inst			= (uint8_t)pipe_ctx->stream_res.opp->inst;
 	else
 		copy_settings_data->opp_inst			= 0;
 	if (pipe_ctx->stream_res.tg)
-		copy_settings_data->otg_inst			= pipe_ctx->stream_res.tg->inst;
+		copy_settings_data->otg_inst			= (uint8_t)pipe_ctx->stream_res.tg->inst;
 	else
 		copy_settings_data->otg_inst			= 0;
 
 	// Misc
 	copy_settings_data->use_phy_fsm             = link->ctx->dc->debug.psr_power_use_phy_fsm;
-	copy_settings_data->psr_level				= psr_context->psr_level.u32all;
+	copy_settings_data->psr_level				= (uint16_t)psr_context->psr_level.u32all;
 	copy_settings_data->smu_optimizations_en		= psr_context->allow_smu_optimizations;
 	copy_settings_data->multi_disp_optimizations_en	= psr_context->allow_multi_disp_optimizations;
-	copy_settings_data->frame_delay				= psr_context->frame_delay;
+	copy_settings_data->frame_delay				= (uint8_t)psr_context->frame_delay;
 	copy_settings_data->frame_cap_ind			= psr_context->psrFrameCaptureIndicationReq;
-	copy_settings_data->init_sdp_deadline			= psr_context->sdpTransmitLineNumDeadline;
+	copy_settings_data->init_sdp_deadline			= (uint16_t)psr_context->sdpTransmitLineNumDeadline;
 	copy_settings_data->debug.u32All = 0;
 	copy_settings_data->debug.bitfields.visual_confirm	= dc->dc->debug.visual_confirm == VISUAL_CONFIRM_PSR;
 	copy_settings_data->debug.bitfields.use_hw_lock_mgr		= 1;
diff --git a/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c b/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c
index 0af1b8e0a49e..9b50bf1d80fc 100644
--- a/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c
+++ b/drivers/gpu/drm/amd/display/dc/dce/dmub_replay.c
@@ -151,22 +151,23 @@ static bool dmub_replay_copy_settings(struct dmub_replay *dmub,
 	copy_settings_data->digfe_inst				= replay_context->digfe_inst;
 
 	if (pipe_ctx->plane_res.dpp)
-		copy_settings_data->dpp_inst			= pipe_ctx->plane_res.dpp->inst;
+		copy_settings_data->dpp_inst			= (uint8_t)pipe_ctx->plane_res.dpp->inst;
 	else
 		copy_settings_data->dpp_inst			= 0;
+
 	if (pipe_ctx->stream_res.tg)
-		copy_settings_data->otg_inst			= pipe_ctx->stream_res.tg->inst;
+		copy_settings_data->otg_inst			= (uint8_t)pipe_ctx->stream_res.tg->inst;
 	else
 		copy_settings_data->otg_inst			= 0;
 
 	copy_settings_data->dpphy_inst				= link->link_enc->transmitter;
 
 	// Misc
-	copy_settings_data->line_time_in_ns			= replay_context->line_time_in_ns;
-	copy_settings_data->panel_inst				= panel_inst;
-	copy_settings_data->debug.u32All			= link->replay_settings.config.debug_flags;
+	copy_settings_data->line_time_in_ns			= (uint16_t)replay_context->line_time_in_ns;
+	copy_settings_data->panel_inst				= (uint16_t)panel_inst;
+	copy_settings_data->debug.u32All			= (uint16_t)link->replay_settings.config.debug_flags;
 	copy_settings_data->pixel_deviation_per_line		= link->dpcd_caps.pr_info.pixel_deviation_per_line;
-	copy_settings_data->max_deviation_line			= link->dpcd_caps.pr_info.max_deviation_line;
+	copy_settings_data->max_deviation_line			= (uint16_t)link->dpcd_caps.pr_info.max_deviation_line;
 	copy_settings_data->smu_optimizations_en		= link->replay_settings.replay_smu_opt_enable;
 	copy_settings_data->replay_timing_sync_supported = link->replay_settings.config.replay_timing_sync_supported;
 	copy_settings_data->replay_support_fast_resync_in_ultra_sleep_mode = link->replay_settings.config.replay_support_fast_resync_in_ultra_sleep_mode;
@@ -193,13 +194,13 @@ static bool dmub_replay_copy_settings(struct dmub_replay *dmub,
 
 	copy_settings_data->flags.bitfields.alpm_mode = (enum dmub_alpm_mode)link->replay_settings.config.alpm_mode;
 	if (link->replay_settings.config.alpm_mode == DC_ALPM_AUXLESS) {
-		copy_settings_data->auxless_alpm_data.lfps_setup_ns = dc->dc->debug.auxless_alpm_lfps_setup_ns;
-		copy_settings_data->auxless_alpm_data.lfps_period_ns = dc->dc->debug.auxless_alpm_lfps_period_ns;
-		copy_settings_data->auxless_alpm_data.lfps_silence_ns = dc->dc->debug.auxless_alpm_lfps_silence_ns;
+		copy_settings_data->auxless_alpm_data.lfps_setup_ns = (uint16_t)dc->dc->debug.auxless_alpm_lfps_setup_ns;
+		copy_settings_data->auxless_alpm_data.lfps_period_ns = (uint16_t)dc->dc->debug.auxless_alpm_lfps_period_ns;
+		copy_settings_data->auxless_alpm_data.lfps_silence_ns = (uint16_t)dc->dc->debug.auxless_alpm_lfps_silence_ns;
 		copy_settings_data->auxless_alpm_data.lfps_t1_t2_override_us =
-			dc->dc->debug.auxless_alpm_lfps_t1t2_us;
+			(uint16_t)dc->dc->debug.auxless_alpm_lfps_t1t2_us;
 		copy_settings_data->auxless_alpm_data.lfps_t1_t2_offset_us =
-			dc->dc->debug.auxless_alpm_lfps_t1t2_offset_us;
+			(uint16_t)dc->dc->debug.auxless_alpm_lfps_t1t2_offset_us;
 		copy_settings_data->auxless_alpm_data.lttpr_count = link->dc->link_srv->dp_get_lttpr_count(link);
 	}
 
diff --git a/drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c b/drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c
index 53c03364f5d4..20c18ac87998 100644
--- a/drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c
+++ b/drivers/gpu/drm/amd/display/dc/dce80/dce80_timing_generator.c
@@ -98,7 +98,7 @@ static void program_pix_dur(struct timing_generator *tg, uint32_t pix_clk_100hz)
 
 	set_reg_field_value(
 		value,
-		pix_dur,
+		(uint32_t)pix_dur,
 		DPG_PIPE_ARBITRATION_CONTROL1,
 		PIXEL_DURATION);
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
index c702a30563f9..9ffc7fd3212e 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_cm_common.c
@@ -75,8 +75,8 @@ void cm_helper_read_color_matrices(struct dc_context *ctx,
 				csc_c11, &regval0,
 				csc_c12, &regval1);
 
-		regval[2 * i] = regval0;
-		regval[(2 * i) + 1] = regval1;
+		regval[2 * i] = (uint16_t)regval0;
+		regval[(2 * i) + 1] = (uint16_t)regval1;
 
 		i++;
 	}
diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.c
index 6f2a0d5d963b..33a4c07a057c 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_mmhubbub.c
@@ -107,35 +107,35 @@ static void mmhubbub3_config_mcif_buf(struct mcif_wb *mcif_wb,
 	struct dcn30_mmhubbub *mcif_wb30 = TO_DCN30_MMHUBBUB(mcif_wb);
 
 	/* buffer address for packing mode or Luma in planar mode */
-	REG_UPDATE(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB_BUF_1_ADDR_Y, MCIF_ADDR(params->luma_address[0]));
+	REG_UPDATE(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB_BUF_1_ADDR_Y, (uint32_t)MCIF_ADDR(params->luma_address[0]));
 	REG_UPDATE(MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_ADDR_HIGH(params->luma_address[0]));
 
 	/* buffer address for Chroma in planar mode (unused in packing mode) */
-	REG_UPDATE(MCIF_WB_BUF_1_ADDR_C, MCIF_WB_BUF_1_ADDR_C, MCIF_ADDR(params->chroma_address[0]));
+	REG_UPDATE(MCIF_WB_BUF_1_ADDR_C, MCIF_WB_BUF_1_ADDR_C, (uint32_t)MCIF_ADDR(params->chroma_address[0]));
 	REG_UPDATE(MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_ADDR_HIGH(params->chroma_address[0]));
 
 	/* buffer address for packing mode or Luma in planar mode */
-	REG_UPDATE(MCIF_WB_BUF_2_ADDR_Y, MCIF_WB_BUF_2_ADDR_Y, MCIF_ADDR(params->luma_address[1]));
+	REG_UPDATE(MCIF_WB_BUF_2_ADDR_Y, MCIF_WB_BUF_2_ADDR_Y, (uint32_t)MCIF_ADDR(params->luma_address[1]));
 	REG_UPDATE(MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_ADDR_HIGH(params->luma_address[1]));
 
 	/* buffer address for Chroma in planar mode (unused in packing mode) */
-	REG_UPDATE(MCIF_WB_BUF_2_ADDR_C, MCIF_WB_BUF_2_ADDR_C, MCIF_ADDR(params->chroma_address[1]));
+	REG_UPDATE(MCIF_WB_BUF_2_ADDR_C, MCIF_WB_BUF_2_ADDR_C, (uint32_t)MCIF_ADDR(params->chroma_address[1]));
 	REG_UPDATE(MCIF_WB_BUF_2_ADDR_C_HIGH, MCIF_WB_BUF_2_ADDR_C_HIGH, MCIF_ADDR_HIGH(params->chroma_address[1]));
 
 	/* buffer address for packing mode or Luma in planar mode */
-	REG_UPDATE(MCIF_WB_BUF_3_ADDR_Y, MCIF_WB_BUF_3_ADDR_Y, MCIF_ADDR(params->luma_address[2]));
+	REG_UPDATE(MCIF_WB_BUF_3_ADDR_Y, MCIF_WB_BUF_3_ADDR_Y, (uint32_t)MCIF_ADDR(params->luma_address[2]));
 	REG_UPDATE(MCIF_WB_BUF_3_ADDR_Y_HIGH, MCIF_WB_BUF_3_ADDR_Y_HIGH, MCIF_ADDR_HIGH(params->luma_address[2]));
 
 	/* buffer address for Chroma in planar mode (unused in packing mode) */
-	REG_UPDATE(MCIF_WB_BUF_3_ADDR_C, MCIF_WB_BUF_3_ADDR_C, MCIF_ADDR(params->chroma_address[2]));
+	REG_UPDATE(MCIF_WB_BUF_3_ADDR_C, MCIF_WB_BUF_3_ADDR_C, (uint32_t)MCIF_ADDR(params->chroma_address[2]));
 	REG_UPDATE(MCIF_WB_BUF_3_ADDR_C_HIGH, MCIF_WB_BUF_3_ADDR_C_HIGH, MCIF_ADDR_HIGH(params->chroma_address[2]));
 
 	/* buffer address for packing mode or Luma in planar mode */
-	REG_UPDATE(MCIF_WB_BUF_4_ADDR_Y, MCIF_WB_BUF_4_ADDR_Y, MCIF_ADDR(params->luma_address[3]));
+	REG_UPDATE(MCIF_WB_BUF_4_ADDR_Y, MCIF_WB_BUF_4_ADDR_Y, (uint32_t)MCIF_ADDR(params->luma_address[3]));
 	REG_UPDATE(MCIF_WB_BUF_4_ADDR_Y_HIGH, MCIF_WB_BUF_4_ADDR_Y_HIGH, MCIF_ADDR_HIGH(params->luma_address[3]));
 
 	/* buffer address for Chroma in planar mode (unused in packing mode) */
-	REG_UPDATE(MCIF_WB_BUF_4_ADDR_C, MCIF_WB_BUF_4_ADDR_C, MCIF_ADDR(params->chroma_address[3]));
+	REG_UPDATE(MCIF_WB_BUF_4_ADDR_C, MCIF_WB_BUF_4_ADDR_C, (uint32_t)MCIF_ADDR(params->chroma_address[3]));
 	REG_UPDATE(MCIF_WB_BUF_4_ADDR_C_HIGH, MCIF_WB_BUF_4_ADDR_C_HIGH, MCIF_ADDR_HIGH(params->chroma_address[3]));
 
 	/* setup luma & chroma size
diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c
index 2d33ed0c062d..79d0c2896d29 100644
--- a/drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dio/dcn401/dcn401_dio_stream_encoder.c
@@ -43,7 +43,7 @@
 
 #undef FN
 #define FN(reg_name, field_name) \
-	enc1->se_shift->field_name, enc1->se_mask->field_name
+	(uint8_t)enc1->se_shift->field_name, enc1->se_mask->field_name
 
 #define VBI_LINE_0 0
 #define HDMI_CLOCK_CHANNEL_RATE_MORE_340M 340000
diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn42/dcn42_dio_link_encoder.h b/drivers/gpu/drm/amd/display/dc/dio/dcn42/dcn42_dio_link_encoder.h
index 4b5a9594f279..9c607b24ec1c 100644
--- a/drivers/gpu/drm/amd/display/dc/dio/dcn42/dcn42_dio_link_encoder.h
+++ b/drivers/gpu/drm/amd/display/dc/dio/dcn42/dcn42_dio_link_encoder.h
@@ -121,8 +121,6 @@
 	LE_SF(DIO_CLK_CNTL, SYMCLKC_G_HDCP_GATE_DIS, mask_sh),\
 	LE_SF(DIO_CLK_CNTL, SYMCLKD_G_HDCP_GATE_DIS, mask_sh),\
 	LE_SF(DIO_CLK_CNTL, SYMCLKE_G_HDCP_GATE_DIS, mask_sh),\
-	LE_SF(DIO_CLK_CNTL, SYMCLKF_G_HDCP_GATE_DIS, mask_sh),\
-	LE_SF(DIO_CLK_CNTL, SYMCLKG_G_HDCP_GATE_DIS, mask_sh)
 
 void dcn42_link_encoder_construct(
 	struct dcn20_link_encoder *enc20,
diff --git a/drivers/gpu/drm/amd/display/dc/dio/dcn42/dcn42_dio_stream_encoder.c b/drivers/gpu/drm/amd/display/dc/dio/dcn42/dcn42_dio_stream_encoder.c
index 65afbfcaa96b..55ddb9cf8a52 100644
--- a/drivers/gpu/drm/amd/display/dc/dio/dcn42/dcn42_dio_stream_encoder.c
+++ b/drivers/gpu/drm/amd/display/dc/dio/dcn42/dcn42_dio_stream_encoder.c
@@ -23,7 +23,7 @@
 
 #undef FN
 #define FN(reg_name, field_name) \
-	enc1->se_shift->field_name, enc1->se_mask->field_name
+	(uint8_t)enc1->se_shift->field_name, enc1->se_mask->field_name
 
 #define VBI_LINE_0 0
 #define HDMI_CLOCK_CHANNEL_RATE_MORE_340M 340000
@@ -401,7 +401,7 @@ void enc42_se_enable_audio_clock(
 {
 	struct dcn10_stream_encoder *enc1 = DCN10STRENC_FROM_STRENC(enc);
 
-	REG_UPDATE(DIG_FE_AUDIO_CNTL, APG_CLOCK_ENABLE, !!enable);
+	REG_UPDATE(DIG_FE_AUDIO_CNTL, APG_CLOCK_ENABLE, enable);
 }
 
 
diff --git a/drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c b/drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
index 61553e24d53e..a95f94d6c7c3 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/calcs/dcn_calcs.c
@@ -533,13 +533,14 @@ static void split_stream_across_pipes(
 
 	*secondary_pipe = *primary_pipe;
 
-	secondary_pipe->pipe_idx = pipe_idx;
+	secondary_pipe->pipe_idx = (uint8_t)pipe_idx;
 	secondary_pipe->plane_res.mi = pool->mis[secondary_pipe->pipe_idx];
 	secondary_pipe->plane_res.hubp = pool->hubps[secondary_pipe->pipe_idx];
 	secondary_pipe->plane_res.ipp = pool->ipps[secondary_pipe->pipe_idx];
 	secondary_pipe->plane_res.xfm = pool->transforms[secondary_pipe->pipe_idx];
 	secondary_pipe->plane_res.dpp = pool->dpps[secondary_pipe->pipe_idx];
-	secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst;
+	secondary_pipe->plane_res.mpcc_inst =
+			(uint8_t)pool->dpps[secondary_pipe->pipe_idx]->inst;
 	if (primary_pipe->bottom_pipe) {
 		ASSERT(primary_pipe->bottom_pipe != secondary_pipe);
 		secondary_pipe->bottom_pipe = primary_pipe->bottom_pipe;
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
index e82f2d531211..82f50847cbac 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
@@ -1402,11 +1402,12 @@ int dcn20_populate_dml_pipes_from_context(struct dc *dc,
 			timing->h_addressable + timing->h_border_left + timing->h_border_right;
 		pipes[pipe_cnt].pipe.dest.vactive =
 			timing->v_addressable + timing->v_border_top + timing->v_border_bottom;
-		pipes[pipe_cnt].pipe.dest.interlaced = timing->flags.INTERLACE;
+		pipes[pipe_cnt].pipe.dest.interlaced = (unsigned char)timing->flags.INTERLACE;
 		pipes[pipe_cnt].pipe.dest.pixel_rate_mhz = timing->pix_clk_100hz/10000.0;
 		if (timing->timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
 			pipes[pipe_cnt].pipe.dest.pixel_rate_mhz *= 2;
-		pipes[pipe_cnt].pipe.dest.otg_inst = res_ctx->pipe_ctx[i].stream_res.tg->inst;
+		pipes[pipe_cnt].pipe.dest.otg_inst =
+				(unsigned char)res_ctx->pipe_ctx[i].stream_res.tg->inst;
 		pipes[pipe_cnt].dout.dp_lanes = 4;
 		pipes[pipe_cnt].dout.dp_rate = dm_dp_rate_na;
 		pipes[pipe_cnt].dout.is_virtual = 0;
@@ -1879,7 +1880,7 @@ void dcn20_update_bounding_box(struct dc *dc,
 		bb->clock_limits[i].dram_speed_mts = uclk_states[i] * 16 / 1000;
 
 		// FCLK:UCLK ratio is 1.08
-		min_fclk_required_by_uclk = div_u64(((unsigned long long)uclk_states[i]) * 1080,
+		min_fclk_required_by_uclk = (int)div_u64(((unsigned long long)uclk_states[i]) * 1080,
 			1000000);
 
 		bb->clock_limits[i].fabricclk_mhz = (min_fclk_required_by_uclk < min_dcfclk) ?
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c
index 0cdd60869ce1..354641312acc 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn30/dcn30_fpu.c
@@ -662,7 +662,7 @@ void dcn3_fpu_build_wm_range_table(struct clk_mgr *base)
 	double pstate_latency_us = base->ctx->dc->dml.soc.dram_clock_change_latency_us;
 	double sr_exit_time_us = base->ctx->dc->dml.soc.sr_exit_time_us;
 	double sr_enter_plus_exit_time_us = base->ctx->dc->dml.soc.sr_enter_plus_exit_time_us;
-	uint16_t min_uclk_mhz = base->bw_params->clk_table.entries[0].memclk_mhz;
+	uint16_t min_uclk_mhz = (uint16_t)base->bw_params->clk_table.entries[0].memclk_mhz;
 
 	dc_assert_fp_enabled();
 
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
index eb199215d298..f5ddf771e73d 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn32/dcn32_fpu.c
@@ -191,21 +191,24 @@ void dcn32_build_wm_range_table_fpu(struct clk_mgr_internal *clk_mgr)
 	double sr_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_exit_time_us;
 	double sr_enter_plus_exit_time_us = clk_mgr->base.ctx->dc->dml.soc.sr_enter_plus_exit_time_us;
 	/* For min clocks use as reported by PM FW and report those as min */
-	uint16_t min_uclk_mhz			= clk_mgr->base.bw_params->clk_table.entries[0].memclk_mhz;
-	uint16_t min_dcfclk_mhz			= clk_mgr->base.bw_params->clk_table.entries[0].dcfclk_mhz;
+	uint16_t min_uclk_mhz			= (uint16_t)clk_mgr->base.bw_params->clk_table.entries[0].memclk_mhz;
+	uint16_t min_dcfclk_mhz			= (uint16_t)clk_mgr->base.bw_params->clk_table.entries[0].dcfclk_mhz;
 	uint16_t setb_min_uclk_mhz		= min_uclk_mhz;
-	uint16_t dcfclk_mhz_for_the_second_state = clk_mgr->base.ctx->dc->dml.soc.clock_limits[2].dcfclk_mhz;
+	uint16_t dcfclk_mhz_for_the_second_state =
+			(uint16_t)clk_mgr->base.ctx->dc->dml.soc.clock_limits[2].dcfclk_mhz;
 
 	dc_assert_fp_enabled();
 
 	/* For Set B ranges use min clocks state 2 when available, and report those to PM FW */
-	if (dcfclk_mhz_for_the_second_state)
-		clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = dcfclk_mhz_for_the_second_state;
-	else
-		clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk = clk_mgr->base.bw_params->clk_table.entries[0].dcfclk_mhz;
+	if (dcfclk_mhz_for_the_second_state) {
+		clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk =
+				(uint16_t)dcfclk_mhz_for_the_second_state;
+	} else
+		clk_mgr->base.bw_params->wm_table.nv_entries[WM_B].pmfw_breakdown.min_dcfclk =
+				(uint16_t)clk_mgr->base.bw_params->clk_table.entries[0].dcfclk_mhz;
 
 	if (clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz)
-		setb_min_uclk_mhz = clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz;
+		setb_min_uclk_mhz = (uint16_t)clk_mgr->base.bw_params->clk_table.entries[2].memclk_mhz;
 
 	/* Set A - Normal - default values */
 	clk_mgr->base.bw_params->wm_table.nv_entries[WM_A].valid = true;
@@ -901,7 +904,7 @@ static bool subvp_vblank_schedulable(struct dc *dc, struct dc_state *context)
 	struct pipe_ctx *subvp_pipe = NULL;
 	bool found = false;
 	bool schedulable = false;
-	uint32_t i = 0;
+	uint8_t i = 0;
 	uint8_t vblank_index = 0;
 	uint16_t prefetch_us = 0;
 	uint16_t mall_region_us = 0;
@@ -986,7 +989,7 @@ static bool subvp_subvp_admissable(struct dc *dc,
 				struct dc_state *context)
 {
 	bool result = false;
-	uint32_t i;
+	uint8_t i;
 	uint8_t subvp_count = 0;
 	uint32_t min_refresh = subvp_high_refresh_list.min_refresh, max_refresh = 0;
 	uint64_t refresh_rate = 0;
@@ -1779,7 +1782,7 @@ static struct pipe_ctx *dcn32_find_split_pipe(
 
 	if (old_index >= 0 && context->res_ctx.pipe_ctx[old_index].stream == NULL) {
 		pipe = &context->res_ctx.pipe_ctx[old_index];
-		pipe->pipe_idx = old_index;
+		pipe->pipe_idx = (uint8_t)old_index;
 	}
 
 	if (!pipe)
@@ -1788,7 +1791,7 @@ static struct pipe_ctx *dcn32_find_split_pipe(
 					&& dc->current_state->res_ctx.pipe_ctx[i].prev_odm_pipe == NULL) {
 				if (context->res_ctx.pipe_ctx[i].stream == NULL) {
 					pipe = &context->res_ctx.pipe_ctx[i];
-					pipe->pipe_idx = i;
+					pipe->pipe_idx = (uint8_t)i;
 					break;
 				}
 			}
@@ -1803,7 +1806,7 @@ static struct pipe_ctx *dcn32_find_split_pipe(
 		for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) {
 			if (context->res_ctx.pipe_ctx[i].stream == NULL) {
 				pipe = &context->res_ctx.pipe_ctx[i];
-				pipe->pipe_idx = i;
+				pipe->pipe_idx = (uint8_t)i;
 				break;
 			}
 		}
@@ -1846,13 +1849,13 @@ static bool dcn32_split_stream_for_mpc_or_odm(
 
 	*sec_pipe = *pri_pipe;
 
-	sec_pipe->pipe_idx = pipe_idx;
+	sec_pipe->pipe_idx = (uint8_t)pipe_idx;
 	sec_pipe->plane_res.mi = pool->mis[pipe_idx];
 	sec_pipe->plane_res.hubp = pool->hubps[pipe_idx];
 	sec_pipe->plane_res.ipp = pool->ipps[pipe_idx];
 	sec_pipe->plane_res.xfm = pool->transforms[pipe_idx];
 	sec_pipe->plane_res.dpp = pool->dpps[pipe_idx];
-	sec_pipe->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst;
+	sec_pipe->plane_res.mpcc_inst = (uint8_t)pool->dpps[pipe_idx]->inst;
 	sec_pipe->stream_res.dsc = NULL;
 	if (odm) {
 		if (pri_pipe->next_odm_pipe) {
@@ -3365,8 +3368,8 @@ bool dcn32_allow_subvp_with_active_margin(struct pipe_ctx *pipe)
 
 		refresh_rate = (pipe->stream->timing.pix_clk_100hz * (uint64_t)100 +
 			(uint64_t)pipe->stream->timing.v_total * pipe->stream->timing.h_total - (uint64_t)1);
-		refresh_rate = div_u64(refresh_rate, pipe->stream->timing.v_total);
-		refresh_rate = div_u64(refresh_rate, pipe->stream->timing.h_total);
+		refresh_rate = (uint32_t)div_u64(refresh_rate, pipe->stream->timing.v_total);
+		refresh_rate = (uint32_t)div_u64(refresh_rate, pipe->stream->timing.h_total);
 
 		if (refresh_rate >= min_refresh && refresh_rate <= max_refresh &&
 				dcn32_check_native_scaling_for_res(pipe, width, height)) {
diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/README.md b/drivers/gpu/drm/amd/display/dc/dml2_0/README.md
new file mode 100644
index 000000000000..9e8814fbe52f
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/dc/dml2_0/README.md
@@ -0,0 +1,31 @@
+# DML2_0 (Display Mode Library 2.0) repository
+
+## Category to Directory Mapping
+
+```yaml
+directory_categories:
+  app_tools:
+    - dml21/build/
+    - dml21/src/dml2_unit_test/
+    - utils/
+
+  driver_hw_dependent:
+    - dml21/inc/bounding_boxes/
+    - dml21/src/dml2_cga/
+    - dml21/src/dml2_core/
+    - dml21/src/dml2_dpmm/
+    - dml21/src/dml2_mcg/
+    - dml21/src/dml2_pmo/
+    - dml21/src/dml2_standalone_libraries/
+    - dml21/src/dml2_utm_soc_bb/
+
+  driver_hw_independent:
+    - ./
+    - dml21/
+    - dml21/inc/
+    - dml21/src/dml2_top/
+    - dml21/src/inc/
+
+  undefined:
+    - .github/
+```
diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c b/drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
index 698d62fb9cf7..16514f1e4ed9 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_core.c
@@ -1119,10 +1119,10 @@ static dml_bool_t CalculatePrefetchSchedule(struct display_mode_lib_scratch_st *
 	if (p->myPipe->Dppclk == 0.0 || p->myPipe->Dispclk == 0.0)
 		return true;
 
-	*p->DSTXAfterScaler = (dml_uint_t) dml_round(s->DPPCycles * p->myPipe->PixelClock / p->myPipe->Dppclk + s->DISPCLKCycles * p->myPipe->PixelClock / p->myPipe->Dispclk + p->DSCDelay, 1.0);
+	*p->DSTXAfterScaler = (dml_uint_t) dml_round(s->DPPCycles * p->myPipe->PixelClock / p->myPipe->Dppclk + s->DISPCLKCycles * p->myPipe->PixelClock / p->myPipe->Dispclk + p->DSCDelay, true);
 	*p->DSTXAfterScaler = (dml_uint_t) dml_round(*p->DSTXAfterScaler + (p->myPipe->ODMMode != dml_odm_mode_bypass ? 18 : 0) + (p->myPipe->DPPPerSurface - 1) * p->DPP_RECOUT_WIDTH +
 						((p->myPipe->ODMMode == dml_odm_mode_split_1to2 || p->myPipe->ODMMode == dml_odm_mode_mso_1to2) ? (dml_float_t)p->myPipe->HActive / 2.0 : 0) +
-						((p->myPipe->ODMMode == dml_odm_mode_mso_1to4) ? (dml_float_t)p->myPipe->HActive * 3.0 / 4.0 : 0), 1.0);
+						((p->myPipe->ODMMode == dml_odm_mode_mso_1to4) ? (dml_float_t)p->myPipe->HActive * 3.0 / 4.0 : 0), true);
 
 #ifdef __DML_VBA_DEBUG__
 	dml_print("DML::%s: DPPCycles = %u\n", __func__, s->DPPCycles);
@@ -4301,7 +4301,7 @@ static void CalculateSwathAndDETConfiguration(struct display_mode_lib_scratch_st
 
 	*p->compbuf_reserved_space_64b = 2 * p->PixelChunkSizeInKByte * 1024 / 64;
 	if (*p->UnboundedRequestEnabled) {
-		*p->compbuf_reserved_space_64b = dml_max(*p->compbuf_reserved_space_64b,
+		*p->compbuf_reserved_space_64b = (dml_uint_t)dml_max(*p->compbuf_reserved_space_64b,
 				(dml_float_t)(p->ROBBufferSizeInKByte * 1024/64)
 				- (dml_float_t)(RoundedUpSwathSizeBytesY[SurfaceDoingUnboundedRequest] * TTUFIFODEPTH / MAXIMUMCOMPRESSION/64));
 	}
@@ -6178,9 +6178,9 @@ static void CalculateImmediateFlipBandwithSupport(
 
 static dml_uint_t MicroSecToVertLines(dml_uint_t num_us, dml_uint_t h_total, dml_float_t pixel_clock)
 {
-	dml_uint_t lines_time_in_ns = 1000.0 * (h_total * 1000.0) / (pixel_clock * 1000.0);
+	dml_uint_t lines_time_in_ns = (dml_uint_t)(1000.0 * (h_total * 1000.0) / (pixel_clock * 1000.0));
 
-	return dml_ceil(1000.0 * num_us / lines_time_in_ns, 1.0);
+	return (dml_uint_t)dml_ceil(1000.0 * num_us / lines_time_in_ns, 1.0);
 }
 
 /// @brief Calculate the maximum vstartup for mode support and mode programming consideration
@@ -6207,9 +6207,9 @@ static dml_uint_t CalculateMaxVStartup(
 	// + 2 is because
 	// 1 -> VStartup_start should be 1 line before VSync
 	// 1 -> always reserve 1 line between start of VBlank to VStartup signal
-	dml_uint_t vblank_nom_vsync_capped = dml_max(vblank_nom_input,
+	dml_uint_t vblank_nom_vsync_capped = (dml_uint_t)dml_max(vblank_nom_input,
 			timing->VTotal[plane_idx] - timing->VActive[plane_idx] - timing->VFrontPorch[plane_idx] + 2);
-	dml_uint_t vblank_nom_max_allowed_capped = dml_min(vblank_nom_vsync_capped, max_allowed_vblank_nom);
+	dml_uint_t vblank_nom_max_allowed_capped = (dml_uint_t)dml_min(vblank_nom_vsync_capped, max_allowed_vblank_nom);
 	dml_uint_t vblank_avail = (vblank_nom_max_allowed_capped == 0) ?
 			vblank_nom_default_in_line : vblank_nom_max_allowed_capped;
 
diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_util.c b/drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_util.c
index b2fada6c44c3..3939a0d8b835 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_util.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2_0/display_mode_util.c
@@ -80,7 +80,7 @@ static inline float dcn_bw_pow(float a, float exp)
 	/*ASSERT(exp == (int)exp);*/
 	if ((int)exp == 0)
 		return 1;
-	temp = dcn_bw_pow(a, (int)(exp / 2));
+	temp = dcn_bw_pow(a, (float)(exp / 2));
 	if (((int)exp % 2) == 0) {
 		return temp * temp;
 	} else {
@@ -110,7 +110,7 @@ dml_float_t dml_ceil(dml_float_t x, dml_float_t granularity)
 	if (granularity == 0)
 		return 0;
 	//return (dml_float_t) (ceil(x / granularity) * granularity);
-	return (dml_float_t)dcn_bw_ceil2(x, granularity);
+	return (dml_float_t)dcn_bw_ceil2((float)x, (float)granularity);
 }
 
 dml_float_t dml_floor(dml_float_t x, dml_float_t granularity)
@@ -118,7 +118,7 @@ dml_float_t dml_floor(dml_float_t x, dml_float_t granularity)
 	if (granularity == 0)
 	return 0;
 	//return (dml_float_t) (floor(x / granularity) * granularity);
-	return (dml_float_t)dcn_bw_floor2(x, granularity);
+	return (dml_float_t)dcn_bw_floor2((float)x, (float)granularity);
 }
 
 dml_float_t dml_min(dml_float_t x, dml_float_t y)
@@ -168,12 +168,12 @@ dml_float_t dml_max5(dml_float_t a, dml_float_t b, dml_float_t c, dml_float_t d,
 }
 dml_float_t dml_log(dml_float_t x, dml_float_t base)
 {
-	return (dml_float_t) (_log(x) / _log(base));
+	return (dml_float_t) (_log((float)x) / _log((float)base));
 }
 
 dml_float_t dml_log2(dml_float_t x)
 {
-	return (dml_float_t) (_log(x) / _log(2));
+	return (dml_float_t) (_log((float)x) / _log(2.0f));
 }
 
 dml_float_t dml_round(dml_float_t val, dml_bool_t bankers_rounding)
@@ -184,19 +184,19 @@ dml_float_t dml_round(dml_float_t val, dml_bool_t bankers_rounding)
 //	else {
 //		return round(val);
 		double round_pt = 0.5;
-		double ceil = dml_ceil(val, 1);
-		double floor = dml_floor(val, 1);
+	double ceil = dml_ceil(val, 1.0);
+	double floor = dml_floor(val, 1.0);
 
 		if (val - floor >= round_pt)
-			return ceil;
+			return (dml_float_t)ceil;
 		else
-			return floor;
+			return (dml_float_t)floor;
 //	}
 }
 
 dml_float_t dml_pow(dml_float_t base, int exp)
 {
-	return (dml_float_t) dcn_bw_pow(base, exp);
+	return (dml_float_t) dcn_bw_pow((float)base, (float)exp);
 }
 
 dml_uint_t dml_round_to_multiple(dml_uint_t num, dml_uint_t multiple, dml_bool_t up)
diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c
index 476030193f14..d89fd876975e 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_translation_helper.c
@@ -90,6 +90,8 @@ static void populate_dml21_timing_config_from_stream_state(struct dml2_timing_cf
 		struct pipe_ctx *pipe_ctx,
 		struct dml2_context *dml_ctx)
 {
+	const unsigned int min_v_front_porch = (stream->timing.flags.INTERLACE != 0) ? 2 : 1;
+
 	unsigned int hblank_start, vblank_start;
 	uint64_t min_hardware_refresh_in_uhz;
 	uint32_t pix_clk_100hz;
@@ -97,7 +99,8 @@ static void populate_dml21_timing_config_from_stream_state(struct dml2_timing_cf
 	timing->h_active = stream->timing.h_addressable + stream->timing.h_border_left + stream->timing.h_border_right + pipe_ctx->dsc_padding_params.dsc_hactive_padding;
 	timing->v_active = stream->timing.v_addressable + stream->timing.v_border_bottom + stream->timing.v_border_top;
 	timing->h_front_porch = stream->timing.h_front_porch;
-	timing->v_front_porch = stream->timing.v_front_porch;
+	timing->v_front_porch = stream->timing.v_front_porch > min_v_front_porch ?
+			stream->timing.v_front_porch : min_v_front_porch;
 	timing->pixel_clock_khz = stream->timing.pix_clk_100hz / 10;
 	if (pipe_ctx->dsc_padding_params.dsc_hactive_padding != 0)
 		timing->pixel_clock_khz = pipe_ctx->dsc_padding_params.dsc_pix_clk_100hz / 10;
@@ -116,7 +119,7 @@ static void populate_dml21_timing_config_from_stream_state(struct dml2_timing_cf
 	if (hblank_start < stream->timing.h_addressable)
 		timing->h_blank_end = 0;
 
-	vblank_start = stream->timing.v_total - stream->timing.v_front_porch;
+	vblank_start = timing->v_total - timing->v_front_porch;
 
 	timing->v_blank_end = vblank_start - stream->timing.v_addressable
 		- stream->timing.v_border_top - stream->timing.v_border_bottom;
@@ -848,10 +851,10 @@ void dml21_copy_clocks_to_dc_state(struct dml2_context *in_ctx, struct dc_state
 	context->bw_ctx.bw.dcn.clk.socclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4x.socclk_khz;
 	context->bw_ctx.bw.dcn.clk.subvp_prefetch_dramclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4x.svp_prefetch_no_throttle.uclk_khz;
 	context->bw_ctx.bw.dcn.clk.subvp_prefetch_fclk_khz = in_ctx->v21.mode_programming.programming->min_clocks.dcn4x.svp_prefetch_no_throttle.fclk_khz;
-	context->bw_ctx.bw.dcn.clk.stutter_efficiency.base_efficiency = in_ctx->v21.mode_programming.programming->stutter.base_percent_efficiency;
-	context->bw_ctx.bw.dcn.clk.stutter_efficiency.low_power_efficiency = in_ctx->v21.mode_programming.programming->stutter.low_power_percent_efficiency;
-	context->bw_ctx.bw.dcn.clk.stutter_efficiency.z8_stutter_efficiency = in_ctx->v21.mode_programming.programming->informative.power_management.z8.stutter_efficiency;
-	context->bw_ctx.bw.dcn.clk.stutter_efficiency.z8_stutter_period = in_ctx->v21.mode_programming.programming->informative.power_management.z8.stutter_period;
+	context->bw_ctx.bw.dcn.clk.stutter_efficiency.base_efficiency = (uint8_t)in_ctx->v21.mode_programming.programming->stutter.base_percent_efficiency;
+	context->bw_ctx.bw.dcn.clk.stutter_efficiency.low_power_efficiency = (uint8_t)in_ctx->v21.mode_programming.programming->stutter.low_power_percent_efficiency;
+	context->bw_ctx.bw.dcn.clk.stutter_efficiency.z8_stutter_efficiency = (uint8_t)in_ctx->v21.mode_programming.programming->informative.power_management.z8.stutter_efficiency;
+	context->bw_ctx.bw.dcn.clk.stutter_efficiency.z8_stutter_period = (int)in_ctx->v21.mode_programming.programming->informative.power_management.z8.stutter_period;
 	context->bw_ctx.bw.dcn.clk.zstate_support = in_ctx->v21.mode_programming.programming->z8_stutter.supported_in_blank; /*ignore meets_eco since it is not used*/
 }
 
diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c
index 732de97335fa..835fece1d46a 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_utils.c
@@ -267,7 +267,7 @@ static struct dc_stream_state *dml21_add_phantom_stream(struct dml2_context *dml
 	phantom_stream->dst.height = stream_programming->phantom_stream.descriptor.timing.v_active;
 
 	phantom_stream->src.y = 0;
-	phantom_stream->src.height = (double)phantom_stream_descriptor->timing.v_active * (double)main_stream->src.height / (double)main_stream->dst.height;
+	phantom_stream->src.height = (int)((double)phantom_stream_descriptor->timing.v_active * (double)main_stream->src.height / (double)main_stream->dst.height);
 
 	phantom_stream->use_dynamic_meta = false;
 
diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_types.h b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_types.h
index 98b26116cdc1..dff903a103db 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/inc/dml_top_types.h
@@ -19,7 +19,6 @@ enum dml2_project_id {
 	dml2_project_dcn4x_stage1,
 	dml2_project_dcn4x_stage2,
 	dml2_project_dcn4x_stage2_auto_drr_svp,
-	dml2_project_dcn40,
 	dml2_project_dcn42,
 };
 
diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_factory.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_factory.c
index 6cad99c21139..67e307fa4310 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_factory.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/dml2_core_factory.c
@@ -21,7 +21,6 @@ bool dml2_core_create(enum dml2_project_id project_id, struct dml2_core_instance
 	case dml2_project_dcn4x_stage1:
 		result = false;
 		break;
-	case dml2_project_dcn40:
 	case dml2_project_dcn4x_stage2:
 	case dml2_project_dcn4x_stage2_auto_drr_svp:
 		out->initialize = &core_dcn4_initialize;
diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_factory.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_factory.c
index 39965ff2e111..be0517e10104 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_factory.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_dpmm/dml2_dpmm_factory.c
@@ -33,7 +33,6 @@ bool dml2_dpmm_create(enum dml2_project_id project_id, struct dml2_dpmm_instance
 		out->map_watermarks = &dummy_map_watermarks;
 		result = true;
 		break;
-	case dml2_project_dcn40:
 	case dml2_project_dcn4x_stage2:
 		out->map_mode_to_soc_dpm = &dpmm_dcn3_map_mode_to_soc_dpm;
 		out->map_watermarks = &dummy_map_watermarks;
diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_factory.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_factory.c
index fb0b0ac547c7..270283332cc1 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_factory.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_mcg/dml2_mcg_factory.c
@@ -27,7 +27,6 @@ bool dml2_mcg_create(enum dml2_project_id project_id, struct dml2_mcg_instance *
 		out->build_min_clock_table = &dummy_build_min_clock_table;
 		result = true;
 		break;
-	case dml2_project_dcn40:
 	case dml2_project_dcn4x_stage2:
 	case dml2_project_dcn4x_stage2_auto_drr_svp:
 		out->build_min_clock_table = &mcg_dcn4_build_min_clock_table;
diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_factory.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_factory.c
index 83802aac11cd..af2ba7d08a61 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_factory.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_pmo/dml2_pmo_factory.c
@@ -3,8 +3,8 @@
 // Copyright 2024 Advanced Micro Devices, Inc.
 
 #include "dml2_pmo_factory.h"
-#include "dml2_pmo_dcn3.h"
 #include "dml2_pmo_dcn4_fams2.h"
+#include "dml2_pmo_dcn3.h"
 #include "dml2_external_lib_deps.h"
 
 static bool dummy_init_for_stutter(struct dml2_pmo_init_for_stutter_in_out *in_out)
@@ -40,7 +40,6 @@ bool dml2_pmo_create(enum dml2_project_id project_id, struct dml2_pmo_instance *
 		out->optimize_dcc_mcache = pmo_dcn4_fams2_optimize_dcc_mcache;
 		result = true;
 		break;
-	case dml2_project_dcn40:
 	case dml2_project_dcn4x_stage2:
 		out->initialize = pmo_dcn3_initialize;
 
diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_interfaces.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_interfaces.c
index a6c5031f69c1..04860b6790df 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_interfaces.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_top/dml2_top_interfaces.c
@@ -17,7 +17,6 @@ bool dml2_initialize_instance(struct dml2_initialize_instance_in_out *in_out)
 	case dml2_project_dcn4x_stage1:
 	case dml2_project_dcn4x_stage2:
 	case dml2_project_dcn4x_stage2_auto_drr_svp:
-	case dml2_project_dcn40:
 	case dml2_project_dcn42:
 		return dml2_top_soc15_initialize_instance(in_out);
 	case dml2_project_invalid:
diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c
index 9bbe4e058be7..4543a60a0683 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_mall_phantom.c
@@ -244,9 +244,9 @@ static bool assign_subvp_pipe(struct dml2_context *ctx, struct dc_state *context
 			continue;
 
 		// Round up
-		refresh_rate = (pipe->stream->timing.pix_clk_100hz * 100 +
+		refresh_rate = (unsigned int)((pipe->stream->timing.pix_clk_100hz * 100 +
 				pipe->stream->timing.v_total * pipe->stream->timing.h_total - 1)
-				/ (double)(pipe->stream->timing.v_total * pipe->stream->timing.h_total);
+				/ (double)(pipe->stream->timing.v_total * pipe->stream->timing.h_total));
 		/* SubVP pipe candidate requirements:
 		 * - Refresh rate < 120hz
 		 * - Not able to switch in vactive naturally (switching in active means the
@@ -264,8 +264,8 @@ static bool assign_subvp_pipe(struct dml2_context *ctx, struct dc_state *context
 			pipe = &context->res_ctx.pipe_ctx[i];
 			if (num_pipes <= free_pipes) {
 				struct dc_stream_state *stream = pipe->stream;
-				unsigned int frame_us = (stream->timing.v_total * stream->timing.h_total /
-						(double)(stream->timing.pix_clk_100hz * 100)) * 1000000;
+				unsigned int frame_us = (unsigned int)((stream->timing.v_total * stream->timing.h_total /
+						(double)(stream->timing.pix_clk_100hz * 100)) * 1000000);
 				if (frame_us > max_frame_time && !stream->ignore_msa_timing_param) {
 					*index = i;
 					max_frame_time = frame_us;
@@ -382,8 +382,8 @@ static bool subvp_subvp_schedulable(struct dml2_context *ctx, struct dc_state *c
 					phantom->timing.v_addressable;
 
 			// Round up when calculating microschedule time (+ 1 at the end)
-			time_us = (microschedule_lines * phantom->timing.h_total) /
-					(double)(phantom->timing.pix_clk_100hz * 100) * 1000000 +
+			time_us = (uint32_t)((microschedule_lines * phantom->timing.h_total) /
+					(double)(phantom->timing.pix_clk_100hz * 100) * 1000000) +
 					ctx->config.svp_pstate.subvp_prefetch_end_to_mall_start_us +
 					ctx->config.svp_pstate.subvp_fw_processing_delay_us + 1;
 			if (time_us > max_microschedule_us)
@@ -402,16 +402,16 @@ static bool subvp_subvp_schedulable(struct dml2_context *ctx, struct dc_state *c
 	if (index < 2 || !subvp_pipes[0] || !subvp_pipes[1])
 		return false;
 
-	vactive1_us = ((subvp_pipes[0]->stream->timing.v_addressable * subvp_pipes[0]->stream->timing.h_total) /
-			(double)(subvp_pipes[0]->stream->timing.pix_clk_100hz * 100)) * 1000000;
-	vactive2_us = ((subvp_pipes[1]->stream->timing.v_addressable * subvp_pipes[1]->stream->timing.h_total) /
-				(double)(subvp_pipes[1]->stream->timing.pix_clk_100hz * 100)) * 1000000;
-	vblank1_us = (((subvp_pipes[0]->stream->timing.v_total - subvp_pipes[0]->stream->timing.v_addressable) *
+	vactive1_us = (int32_t)(((subvp_pipes[0]->stream->timing.v_addressable * subvp_pipes[0]->stream->timing.h_total) /
+			(double)(subvp_pipes[0]->stream->timing.pix_clk_100hz * 100)) * 1000000);
+	vactive2_us = (int32_t)(((subvp_pipes[1]->stream->timing.v_addressable * subvp_pipes[1]->stream->timing.h_total) /
+				(double)(subvp_pipes[1]->stream->timing.pix_clk_100hz * 100)) * 1000000);
+	vblank1_us = (int32_t)(((subvp_pipes[0]->stream->timing.v_total - subvp_pipes[0]->stream->timing.v_addressable) *
 			subvp_pipes[0]->stream->timing.h_total) /
-			(double)(subvp_pipes[0]->stream->timing.pix_clk_100hz * 100)) * 1000000;
-	vblank2_us = (((subvp_pipes[1]->stream->timing.v_total - subvp_pipes[1]->stream->timing.v_addressable) *
+			(double)(subvp_pipes[0]->stream->timing.pix_clk_100hz * 100) * 1000000);
+	vblank2_us = (int32_t)(((subvp_pipes[1]->stream->timing.v_total - subvp_pipes[1]->stream->timing.v_addressable) *
 			subvp_pipes[1]->stream->timing.h_total) /
-			(double)(subvp_pipes[1]->stream->timing.pix_clk_100hz * 100)) * 1000000;
+			(double)(subvp_pipes[1]->stream->timing.pix_clk_100hz * 100) * 1000000);
 
 	if ((vactive1_us - vblank2_us) / 2 > max_microschedule_us &&
 	    (vactive2_us - vblank1_us) / 2 > max_microschedule_us)
@@ -445,13 +445,13 @@ bool dml2_svp_drr_schedulable(struct dml2_context *ctx, struct dc_state *context
 	struct dc_crtc_timing *main_timing = NULL;
 	struct dc_crtc_timing *phantom_timing = NULL;
 	struct dc_stream_state *phantom_stream;
-	int16_t prefetch_us = 0;
-	int16_t mall_region_us = 0;
-	int16_t drr_frame_us = 0;	// nominal frame time
-	int16_t subvp_active_us = 0;
-	int16_t stretched_drr_us = 0;
-	int16_t drr_stretched_vblank_us = 0;
-	int16_t max_vblank_mallregion = 0;
+	int32_t prefetch_us = 0;
+	int32_t mall_region_us = 0;
+	int32_t drr_frame_us = 0;	// nominal frame time
+	int32_t subvp_active_us = 0;
+	int32_t stretched_drr_us = 0;
+	int32_t drr_stretched_vblank_us = 0;
+	int32_t max_vblank_mallregion = 0;
 
 	// Find SubVP pipe
 	for (i = 0; i < ctx->config.dcn_pipe_count; i++) {
@@ -475,19 +475,19 @@ bool dml2_svp_drr_schedulable(struct dml2_context *ctx, struct dc_state *context
 	phantom_stream = ctx->config.svp_pstate.callbacks.get_paired_subvp_stream(context, pipe->stream);
 	main_timing = &pipe->stream->timing;
 	phantom_timing = &phantom_stream->timing;
-	prefetch_us = (phantom_timing->v_total - phantom_timing->v_front_porch) * phantom_timing->h_total /
+	prefetch_us = (int32_t)((phantom_timing->v_total - phantom_timing->v_front_porch) * phantom_timing->h_total /
 			(double)(phantom_timing->pix_clk_100hz * 100) * 1000000 +
-			ctx->config.svp_pstate.subvp_prefetch_end_to_mall_start_us;
-	subvp_active_us = main_timing->v_addressable * main_timing->h_total /
-			(double)(main_timing->pix_clk_100hz * 100) * 1000000;
-	drr_frame_us = drr_timing->v_total * drr_timing->h_total /
-			(double)(drr_timing->pix_clk_100hz * 100) * 1000000;
+			ctx->config.svp_pstate.subvp_prefetch_end_to_mall_start_us);
+	subvp_active_us = (int32_t)(main_timing->v_addressable * main_timing->h_total /
+			(double)(main_timing->pix_clk_100hz * 100) * 1000000);
+	drr_frame_us = (int32_t)(drr_timing->v_total * drr_timing->h_total /
+			(double)(drr_timing->pix_clk_100hz * 100) * 1000000);
 	// P-State allow width and FW delays already included phantom_timing->v_addressable
-	mall_region_us = phantom_timing->v_addressable * phantom_timing->h_total /
-			(double)(phantom_timing->pix_clk_100hz * 100) * 1000000;
+	mall_region_us = (int32_t)(phantom_timing->v_addressable * phantom_timing->h_total /
+			(double)(phantom_timing->pix_clk_100hz * 100) * 1000000);
 	stretched_drr_us = drr_frame_us + mall_region_us + SUBVP_DRR_MARGIN_US;
-	drr_stretched_vblank_us = (drr_timing->v_total - drr_timing->v_addressable) * drr_timing->h_total /
-			(double)(drr_timing->pix_clk_100hz * 100) * 1000000 + (stretched_drr_us - drr_frame_us);
+	drr_stretched_vblank_us = (int32_t)((drr_timing->v_total - drr_timing->v_addressable) * drr_timing->h_total /
+			(double)(drr_timing->pix_clk_100hz * 100) * 1000000 + (stretched_drr_us - drr_frame_us));
 	max_vblank_mallregion = drr_stretched_vblank_us > mall_region_us ? drr_stretched_vblank_us : mall_region_us;
 
 	/* We consider SubVP + DRR schedulable if the stretched frame duration of the DRR display (i.e. the
@@ -526,12 +526,12 @@ static bool subvp_vblank_schedulable(struct dml2_context *ctx, struct dc_state *
 	bool schedulable = false;
 	uint32_t i = 0;
 	uint8_t vblank_index = 0;
-	uint16_t prefetch_us = 0;
-	uint16_t mall_region_us = 0;
-	uint16_t vblank_frame_us = 0;
-	uint16_t subvp_active_us = 0;
-	uint16_t vblank_blank_us = 0;
-	uint16_t max_vblank_mallregion = 0;
+	uint32_t prefetch_us = 0;
+	uint32_t mall_region_us = 0;
+	uint32_t vblank_frame_us = 0;
+	uint32_t subvp_active_us = 0;
+	uint32_t vblank_blank_us = 0;
+	uint32_t max_vblank_mallregion = 0;
 	struct dc_crtc_timing *main_timing = NULL;
 	struct dc_crtc_timing *phantom_timing = NULL;
 	struct dc_crtc_timing *vblank_timing = NULL;
@@ -581,24 +581,27 @@ static bool subvp_vblank_schedulable(struct dml2_context *ctx, struct dc_state *
 		vblank_timing = &context->res_ctx.pipe_ctx[vblank_index].stream->timing;
 		// Prefetch time is equal to VACTIVE + BP + VSYNC of the phantom pipe
 		// Also include the prefetch end to mallstart delay time
-		prefetch_us = (phantom_timing->v_total - phantom_timing->v_front_porch) * phantom_timing->h_total /
+		prefetch_us = (uint32_t)((phantom_timing->v_total - phantom_timing->v_front_porch) * phantom_timing->h_total /
 				(double)(phantom_timing->pix_clk_100hz * 100) * 1000000 +
-				ctx->config.svp_pstate.subvp_prefetch_end_to_mall_start_us;
+				ctx->config.svp_pstate.subvp_prefetch_end_to_mall_start_us);
 		// P-State allow width and FW delays already included phantom_timing->v_addressable
-		mall_region_us = phantom_timing->v_addressable * phantom_timing->h_total /
-				(double)(phantom_timing->pix_clk_100hz * 100) * 1000000;
-		vblank_frame_us = vblank_timing->v_total * vblank_timing->h_total /
-				(double)(vblank_timing->pix_clk_100hz * 100) * 1000000;
-		vblank_blank_us =  (vblank_timing->v_total - vblank_timing->v_addressable) * vblank_timing->h_total /
-				(double)(vblank_timing->pix_clk_100hz * 100) * 1000000;
-		subvp_active_us = main_timing->v_addressable * main_timing->h_total /
-				(double)(main_timing->pix_clk_100hz * 100) * 1000000;
+		mall_region_us = (uint32_t)(phantom_timing->v_addressable * phantom_timing->h_total /
+				(double)(phantom_timing->pix_clk_100hz * 100) * 1000000);
+		vblank_frame_us = (uint32_t)(vblank_timing->v_total * vblank_timing->h_total /
+				(double)(vblank_timing->pix_clk_100hz * 100) * 1000000);
+		vblank_blank_us = (uint32_t)((vblank_timing->v_total - vblank_timing->v_addressable) * vblank_timing->h_total /
+				(double)(vblank_timing->pix_clk_100hz * 100) * 1000000);
+		subvp_active_us = (uint32_t)(main_timing->v_addressable * main_timing->h_total /
+				(double)(main_timing->pix_clk_100hz * 100) * 1000000);
 		max_vblank_mallregion = vblank_blank_us > mall_region_us ? vblank_blank_us : mall_region_us;
+		const uint64_t required_us = (uint64_t)prefetch_us +
+					     (uint64_t)vblank_frame_us +
+					     (uint64_t)max_vblank_mallregion;
 
 		// Schedulable if VACTIVE region of the SubVP pipe can fit the MALL prefetch, VBLANK frame time,
 		// and the max of (VBLANK blanking time, MALL region)
 		// TODO: Possibly add some margin (i.e. the below conditions should be [...] > X instead of [...] > 0)
-		if (subvp_active_us - prefetch_us - vblank_frame_us - max_vblank_mallregion > 0)
+		if ((uint64_t)subvp_active_us > required_us)
 			schedulable = true;
 	}
 	return schedulable;
@@ -694,10 +697,10 @@ static void set_phantom_stream_timing(struct dml2_context *ctx, struct dc_state
 	}
 
 	// Calculate lines required for pstate allow width and FW processing delays
-	pstate_width_fw_delay_lines = ((double)(ctx->config.svp_pstate.subvp_fw_processing_delay_us +
+	pstate_width_fw_delay_lines = (uint32_t)(((double)(ctx->config.svp_pstate.subvp_fw_processing_delay_us +
 			ctx->config.svp_pstate.subvp_pstate_allow_width_us) / 1000000) *
 			(ref_pipe->stream->timing.pix_clk_100hz * 100) /
-			(double)ref_pipe->stream->timing.h_total;
+			(double)ref_pipe->stream->timing.h_total);
 
 	// DML calculation for MALL region doesn't take into account FW delay
 	// and required pstate allow width for multi-display cases
@@ -712,7 +715,7 @@ static void set_phantom_stream_timing(struct dml2_context *ctx, struct dc_state
 	fp_and_sync_width_time = (phantom_stream->timing.v_front_porch + phantom_stream->timing.v_sync_width) * line_time;
 
 	if ((svp_vstartup * line_time) + fp_and_sync_width_time > cvt_rb_vblank_max) {
-		svp_vstartup = (cvt_rb_vblank_max - fp_and_sync_width_time) / line_time;
+		svp_vstartup = (unsigned int)((cvt_rb_vblank_max - fp_and_sync_width_time) / line_time);
 	}
 
 	// For backporch of phantom pipe, use vstartup of the main pipe
diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_policy.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_policy.c
index ef693f608d59..ab2964811c5b 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_policy.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_policy.c
@@ -123,9 +123,9 @@ int dml2_policy_build_synthetic_soc_states(struct dml2_policy_build_synthetic_so
 	struct dml2_policy_build_synthetic_soc_states_params *p)
 {
 	int i, j;
-	unsigned int min_fclk_mhz = p->in_states->state_array[0].fabricclk_mhz;
-	unsigned int min_dcfclk_mhz = p->in_states->state_array[0].dcfclk_mhz;
-	unsigned int min_socclk_mhz = p->in_states->state_array[0].socclk_mhz;
+	unsigned int min_fclk_mhz = (unsigned int)p->in_states->state_array[0].fabricclk_mhz;
+	unsigned int min_dcfclk_mhz = (unsigned int)p->in_states->state_array[0].dcfclk_mhz;
+	unsigned int min_socclk_mhz = (unsigned int)p->in_states->state_array[0].socclk_mhz;
 
 	int max_dcfclk_mhz = 0, max_dispclk_mhz = 0, max_dppclk_mhz = 0,
 		max_phyclk_mhz = 0, max_dtbclk_mhz = 0, max_fclk_mhz = 0,
diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c
index 8e0997441ee0..0d8ff236c6d0 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_translation_helper.c
@@ -508,11 +508,11 @@ void dml2_init_soc_states(struct dml2_context *dml2, const struct dc *in_dc,
 	/* DCFCLK stas values are project specific */
 	if ((dml2->v20.dml_core_ctx.project == dml_project_dcn32) ||
 		(dml2->v20.dml_core_ctx.project == dml_project_dcn321)) {
-		p->dcfclk_stas_mhz[0] = p->in_states->state_array[0].dcfclk_mhz;
+		p->dcfclk_stas_mhz[0] = (int)p->in_states->state_array[0].dcfclk_mhz;
 		p->dcfclk_stas_mhz[1] = 615;
 		p->dcfclk_stas_mhz[2] = 906;
 		p->dcfclk_stas_mhz[3] = 1324;
-		p->dcfclk_stas_mhz[4] = p->in_states->state_array[1].dcfclk_mhz;
+		p->dcfclk_stas_mhz[4] = (int)p->in_states->state_array[1].dcfclk_mhz;
 	} else if (dml2->v20.dml_core_ctx.project != dml_project_dcn35 &&
 			dml2->v20.dml_core_ctx.project != dml_project_dcn36 &&
 			dml2->v20.dml_core_ctx.project != dml_project_dcn351) {
diff --git a/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c
index 86567e232415..1bc81e26a11f 100644
--- a/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2_0/dml2_utils.c
@@ -333,7 +333,7 @@ void dml2_calculate_rq_and_dlg_params(const struct dc *dc, struct dc_state *cont
 		}
 
 		context->bw_ctx.bw.dcn.compbuf_size_kb -= context->res_ctx.pipe_ctx[dc_pipe_ctx_index].det_buffer_size_kb;
-		context->res_ctx.pipe_ctx[dc_pipe_ctx_index].plane_res.bw.dppclk_khz = dml_get_dppclk_calculated(&context->bw_ctx.dml2->v20.dml_core_ctx, dml_pipe_idx) * 1000;
+		context->res_ctx.pipe_ctx[dc_pipe_ctx_index].plane_res.bw.dppclk_khz = (int)(dml_get_dppclk_calculated(&context->bw_ctx.dml2->v20.dml_core_ctx, dml_pipe_idx) * 1000);
 		if (context->bw_ctx.bw.dcn.clk.dppclk_khz < context->res_ctx.pipe_ctx[dc_pipe_ctx_index].plane_res.bw.dppclk_khz)
 			context->bw_ctx.bw.dcn.clk.dppclk_khz = context->res_ctx.pipe_ctx[dc_pipe_ctx_index].plane_res.bw.dppclk_khz;
 
@@ -362,10 +362,10 @@ void dml2_calculate_rq_and_dlg_params(const struct dc *dc, struct dc_state *cont
 	context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz;
 	context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz;
 
-	context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = in_ctx->v20.dml_core_ctx.states.state_array[in_ctx->v20.scratch.mode_support_params.out_lowest_state_idx].dppclk_mhz
-		* 1000;
-	context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = in_ctx->v20.dml_core_ctx.states.state_array[in_ctx->v20.scratch.mode_support_params.out_lowest_state_idx].dispclk_mhz
-		* 1000;
+	context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = (int)(in_ctx->v20.dml_core_ctx.states.state_array[in_ctx->v20.scratch.mode_support_params.out_lowest_state_idx].dppclk_mhz
+		* 1000);
+	context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = (int)(in_ctx->v20.dml_core_ctx.states.state_array[in_ctx->v20.scratch.mode_support_params.out_lowest_state_idx].dispclk_mhz
+		* 1000);
 
 	if (dc->config.forced_clocks || dc->debug.max_disp_clk) {
 		context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz;
@@ -375,18 +375,18 @@ void dml2_calculate_rq_and_dlg_params(const struct dc *dc, struct dc_state *cont
 
 void dml2_extract_watermark_set(struct dcn_watermarks *watermark, struct display_mode_lib_st *dml_core_ctx)
 {
-	watermark->urgent_ns = dml_get_wm_urgent(dml_core_ctx) * 1000;
-	watermark->cstate_pstate.cstate_enter_plus_exit_ns = dml_get_wm_stutter_enter_exit(dml_core_ctx) * 1000;
-	watermark->cstate_pstate.cstate_exit_ns = dml_get_wm_stutter_exit(dml_core_ctx) * 1000;
-	watermark->cstate_pstate.pstate_change_ns = dml_get_wm_dram_clock_change(dml_core_ctx) * 1000;
-	watermark->pte_meta_urgent_ns = dml_get_wm_memory_trip(dml_core_ctx) * 1000;
-	watermark->frac_urg_bw_nom = dml_get_fraction_of_urgent_bandwidth(dml_core_ctx) * 1000;
-	watermark->frac_urg_bw_flip = dml_get_fraction_of_urgent_bandwidth_imm_flip(dml_core_ctx) * 1000;
-	watermark->urgent_latency_ns = dml_get_urgent_latency(dml_core_ctx) * 1000;
-	watermark->cstate_pstate.fclk_pstate_change_ns = dml_get_wm_fclk_change(dml_core_ctx) * 1000;
-	watermark->usr_retraining_ns = dml_get_wm_usr_retraining(dml_core_ctx) * 1000;
-	watermark->cstate_pstate.cstate_enter_plus_exit_z8_ns = dml_get_wm_z8_stutter_enter_exit(dml_core_ctx) * 1000;
-	watermark->cstate_pstate.cstate_exit_z8_ns = dml_get_wm_z8_stutter(dml_core_ctx) * 1000;
+	watermark->urgent_ns = (uint32_t)(dml_get_wm_urgent(dml_core_ctx) * 1000);
+	watermark->cstate_pstate.cstate_enter_plus_exit_ns = (uint32_t)(dml_get_wm_stutter_enter_exit(dml_core_ctx) * 1000);
+	watermark->cstate_pstate.cstate_exit_ns = (uint32_t)(dml_get_wm_stutter_exit(dml_core_ctx) * 1000);
+	watermark->cstate_pstate.pstate_change_ns = (uint32_t)(dml_get_wm_dram_clock_change(dml_core_ctx) * 1000);
+	watermark->pte_meta_urgent_ns = (uint32_t)(dml_get_wm_memory_trip(dml_core_ctx) * 1000);
+	watermark->frac_urg_bw_nom = (uint32_t)(dml_get_fraction_of_urgent_bandwidth(dml_core_ctx) * 1000);
+	watermark->frac_urg_bw_flip = (uint32_t)(dml_get_fraction_of_urgent_bandwidth_imm_flip(dml_core_ctx) * 1000);
+	watermark->urgent_latency_ns = (uint32_t)(dml_get_urgent_latency(dml_core_ctx) * 1000);
+	watermark->cstate_pstate.fclk_pstate_change_ns = (uint32_t)(dml_get_wm_fclk_change(dml_core_ctx) * 1000);
+	watermark->usr_retraining_ns = (uint32_t)(dml_get_wm_usr_retraining(dml_core_ctx) * 1000);
+	watermark->cstate_pstate.cstate_enter_plus_exit_z8_ns = (uint32_t)(dml_get_wm_z8_stutter_enter_exit(dml_core_ctx) * 1000);
+	watermark->cstate_pstate.cstate_exit_z8_ns = (uint32_t)(dml_get_wm_z8_stutter(dml_core_ctx) * 1000);
 }
 
 unsigned int dml2_calc_max_scaled_time(
@@ -434,9 +434,9 @@ void dml2_extract_writeback_wm(struct dc_state *context, struct display_mode_lib
 		for (j = 0 ; j < 4; j++) {
 			/*current dml only has one set of watermark, need to follow up*/
 			bw_writeback->mcif_wb_arb[i].cli_watermark[j] =
-					dml_get_wm_writeback_urgent(dml_core_ctx) * 1000;
+					(unsigned int)(dml_get_wm_writeback_urgent(dml_core_ctx) * 1000);
 			bw_writeback->mcif_wb_arb[i].pstate_watermark[j] =
-					dml_get_wm_writeback_dram_clock_change(dml_core_ctx) * 1000;
+					(unsigned int)(dml_get_wm_writeback_dram_clock_change(dml_core_ctx) * 1000);
 		}
 		if (context->res_ctx.pipe_ctx[i].stream->phy_pix_clk != 0) {
 			/* time_per_pixel should be in u6.6 format */
@@ -450,7 +450,7 @@ void dml2_extract_writeback_wm(struct dc_state *context, struct display_mode_lib
 					wbif_mode, 	wb_arb_params->cli_watermark[0]);
 		/*not required any more*/
 		bw_writeback->mcif_wb_arb[i].dram_speed_change_duration =
-			dml_get_wm_writeback_dram_clock_change(dml_core_ctx) * 1000;
+			(unsigned int)(dml_get_wm_writeback_dram_clock_change(dml_core_ctx) * 1000);
 
 	}
 }
diff --git a/drivers/gpu/drm/amd/display/dc/dpp/dcn42/dcn42_dpp.c b/drivers/gpu/drm/amd/display/dc/dpp/dcn42/dcn42_dpp.c
index c126fb9d5bfa..b5d7ed5dd511 100644
--- a/drivers/gpu/drm/amd/display/dc/dpp/dcn42/dcn42_dpp.c
+++ b/drivers/gpu/drm/amd/display/dc/dpp/dcn42/dcn42_dpp.c
@@ -269,10 +269,10 @@ static void dpp42_dpp_setup(
 
 		tbl_entry.color_space = input_color_space;
 
-		if (color_space >= COLOR_SPACE_YCBCR601)
-			select = INPUT_CSC_SELECT_ICSC;
-		else
+		if (dpp3_should_bypass_post_csc_for_colorspace(color_space))
 			select = INPUT_CSC_SELECT_BYPASS;
+		else
+			select = INPUT_CSC_SELECT_ICSC;
 
 		dpp3_program_post_csc(dpp_base, color_space, select,
 			&tbl_entry);
diff --git a/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c b/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
index 6e1e759462bf..9c326ad1d3b1 100644
--- a/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
+++ b/drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
@@ -405,20 +405,20 @@ bool dsc_prepare_config(const struct dsc_config *dsc_cfg, struct dsc_reg_values
 	dsc_reg_vals->pixel_format = dsc_dc_pixel_encoding_to_dsc_pixel_format(dsc_cfg->pixel_encoding, dsc_cfg->dc_dsc_cfg.ycbcr422_simple);
 	dsc_reg_vals->num_slices_h = dsc_cfg->dc_dsc_cfg.num_slices_h;
 	dsc_reg_vals->num_slices_v = dsc_cfg->dc_dsc_cfg.num_slices_v;
-	dsc_reg_vals->pps.dsc_version_minor = dsc_cfg->dc_dsc_cfg.version_minor;
-	dsc_reg_vals->pps.pic_width = dsc_cfg->pic_width;
-	dsc_reg_vals->pps.pic_height = dsc_cfg->pic_height;
+	dsc_reg_vals->pps.dsc_version_minor = (u8)dsc_cfg->dc_dsc_cfg.version_minor;
+	dsc_reg_vals->pps.pic_width = (u16)dsc_cfg->pic_width;
+	dsc_reg_vals->pps.pic_height = (u16)dsc_cfg->pic_height;
 	dsc_reg_vals->pps.bits_per_component = dsc_dc_color_depth_to_dsc_bits_per_comp(dsc_cfg->color_depth);
 	dsc_reg_vals->pps.block_pred_enable = dsc_cfg->dc_dsc_cfg.block_pred_enable;
-	dsc_reg_vals->pps.line_buf_depth = dsc_cfg->dc_dsc_cfg.linebuf_depth;
+	dsc_reg_vals->pps.line_buf_depth = (u8)dsc_cfg->dc_dsc_cfg.linebuf_depth;
 	dsc_reg_vals->alternate_ich_encoding_en = dsc_reg_vals->pps.dsc_version_minor == 1 ? 0 : 1;
 	dsc_reg_vals->ich_reset_at_eol = (dsc_cfg->is_odm || dsc_reg_vals->num_slices_h > 1) ? 0xF : 0;
 
 	// Need to find the ceiling value for the slice width
-	dsc_reg_vals->pps.slice_width = (dsc_cfg->pic_width + dsc_cfg->dsc_padding + dsc_cfg->dc_dsc_cfg.num_slices_h - 1) / dsc_cfg->dc_dsc_cfg.num_slices_h;
+	dsc_reg_vals->pps.slice_width = (u16)((dsc_cfg->pic_width + dsc_cfg->dsc_padding + dsc_cfg->dc_dsc_cfg.num_slices_h - 1) / dsc_cfg->dc_dsc_cfg.num_slices_h);
 	// TODO: in addition to validating slice height (pic height must be divisible by slice height),
 	// see what happens when the same condition doesn't apply for slice_width/pic_width.
-	dsc_reg_vals->pps.slice_height = dsc_cfg->pic_height / dsc_cfg->dc_dsc_cfg.num_slices_v;
+	dsc_reg_vals->pps.slice_height = (u16)(dsc_cfg->pic_height / dsc_cfg->dc_dsc_cfg.num_slices_v);
 
 	ASSERT(dsc_reg_vals->pps.slice_height * dsc_cfg->dc_dsc_cfg.num_slices_v == dsc_cfg->pic_height);
 	if (!(dsc_reg_vals->pps.slice_height * dsc_cfg->dc_dsc_cfg.num_slices_v == dsc_cfg->pic_height)) {
@@ -428,9 +428,9 @@ bool dsc_prepare_config(const struct dsc_config *dsc_cfg, struct dsc_reg_values
 
 	dsc_reg_vals->bpp_x32 = dsc_cfg->dc_dsc_cfg.bits_per_pixel << 1;
 	if (dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420 || dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422)
-		dsc_reg_vals->pps.bits_per_pixel = dsc_reg_vals->bpp_x32;
+		dsc_reg_vals->pps.bits_per_pixel = (u16)dsc_reg_vals->bpp_x32;
 	else
-		dsc_reg_vals->pps.bits_per_pixel = dsc_reg_vals->bpp_x32 >> 1;
+		dsc_reg_vals->pps.bits_per_pixel = (u16)(dsc_reg_vals->bpp_x32 >> 1);
 
 	dsc_reg_vals->pps.convert_rgb = dsc_reg_vals->pixel_format == DSC_PIXFMT_RGB ? 1 : 0;
 	dsc_reg_vals->pps.native_422 = (dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422);
diff --git a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c
index 59864130cf83..6c07d9a87bfe 100644
--- a/drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c
+++ b/drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c
@@ -72,27 +72,27 @@ static void copy_rc_to_cfg(struct drm_dsc_config *dsc_cfg, const struct rc_param
 {
 	int i;
 
-	dsc_cfg->rc_quant_incr_limit0   = rc->rc_quant_incr_limit0;
-	dsc_cfg->rc_quant_incr_limit1   = rc->rc_quant_incr_limit1;
-	dsc_cfg->initial_offset         = rc->initial_fullness_offset;
-	dsc_cfg->initial_xmit_delay     = rc->initial_xmit_delay;
-	dsc_cfg->first_line_bpg_offset  = rc->first_line_bpg_offset;
-	dsc_cfg->second_line_bpg_offset = rc->second_line_bpg_offset;
-	dsc_cfg->flatness_min_qp        = rc->flatness_min_qp;
-	dsc_cfg->flatness_max_qp        = rc->flatness_max_qp;
+	dsc_cfg->rc_quant_incr_limit0   = (u8)rc->rc_quant_incr_limit0;
+	dsc_cfg->rc_quant_incr_limit1   = (u8)rc->rc_quant_incr_limit1;
+	dsc_cfg->initial_offset         = (u16)rc->initial_fullness_offset;
+	dsc_cfg->initial_xmit_delay     = (u16)rc->initial_xmit_delay;
+	dsc_cfg->first_line_bpg_offset  = (u8)rc->first_line_bpg_offset;
+	dsc_cfg->second_line_bpg_offset = (u8)rc->second_line_bpg_offset;
+	dsc_cfg->flatness_min_qp        = (u8)rc->flatness_min_qp;
+	dsc_cfg->flatness_max_qp        = (u8)rc->flatness_max_qp;
 	for (i = 0; i < QP_SET_SIZE; ++i) {
-		dsc_cfg->rc_range_params[i].range_min_qp     = rc->qp_min[i];
-		dsc_cfg->rc_range_params[i].range_max_qp     = rc->qp_max[i];
+		dsc_cfg->rc_range_params[i].range_min_qp     = (u8)rc->qp_min[i];
+		dsc_cfg->rc_range_params[i].range_max_qp     = (u8)rc->qp_max[i];
 		/* Truncate 8-bit signed value to 6-bit signed value */
 		dsc_cfg->rc_range_params[i].range_bpg_offset = 0x3f & rc->ofs[i];
 	}
-	dsc_cfg->rc_model_size    = rc->rc_model_size;
-	dsc_cfg->rc_edge_factor   = rc->rc_edge_factor;
-	dsc_cfg->rc_tgt_offset_high = rc->rc_tgt_offset_hi;
-	dsc_cfg->rc_tgt_offset_low = rc->rc_tgt_offset_lo;
+	dsc_cfg->rc_model_size    = (u16)rc->rc_model_size;
+	dsc_cfg->rc_edge_factor   = (u8)rc->rc_edge_factor;
+	dsc_cfg->rc_tgt_offset_high = (u8)rc->rc_tgt_offset_hi;
+	dsc_cfg->rc_tgt_offset_low = (u8)rc->rc_tgt_offset_lo;
 
 	for (i = 0; i < QP_SET_SIZE - 1; ++i)
-		dsc_cfg->rc_buf_thresh[i] = rc->rc_buf_thresh[i];
+		dsc_cfg->rc_buf_thresh[i] = (u16)rc->rc_buf_thresh[i];
 }
 
 int dscc_compute_dsc_parameters(const struct drm_dsc_config *pps,
@@ -103,7 +103,8 @@ int dscc_compute_dsc_parameters(const struct drm_dsc_config *pps,
 	struct drm_dsc_config   dsc_cfg;
 
 	dsc_params->pps = *pps;
-	dsc_params->pps.initial_scale_value = 8 * rc->rc_model_size / (rc->rc_model_size - rc->initial_fullness_offset);
+	dsc_params->pps.initial_scale_value = (u8)(8 * rc->rc_model_size /
+			(rc->rc_model_size - rc->initial_fullness_offset));
 
 	copy_pps_fields(&dsc_cfg, &dsc_params->pps);
 	copy_rc_to_cfg(&dsc_cfg, rc);
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c
index 86d60986d669..a76884a069e8 100644
--- a/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c
+++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c
@@ -36,7 +36,7 @@
 
 #undef FN
 #define FN(reg_name, field_name) \
-	ddc->shifts->field_name, ddc->masks->field_name
+	gpio_reg_shift(ddc->shifts->field_name), ddc->masks->field_name
 
 #define CTX \
 	ddc->base.base.ctx
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_generic.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_generic.c
index 7f137cb96895..5db83920e367 100644
--- a/drivers/gpu/drm/amd/display/dc/gpio/hw_generic.c
+++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_generic.c
@@ -37,7 +37,7 @@
 
 #undef FN
 #define FN(reg_name, field_name) \
-	generic->shifts->field_name, generic->masks->field_name
+	gpio_reg_shift(generic->shifts->field_name), generic->masks->field_name
 
 #define CTX \
 	generic->base.base.ctx
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.c
index f0d400972897..07651dc7e205 100644
--- a/drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.c
+++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.c
@@ -32,7 +32,7 @@
 
 #undef FN
 #define FN(reg_name, field_name) \
-	gpio->regs->field_name ## _shift, gpio->regs->field_name ## _mask
+	gpio_reg_shift(gpio->regs->field_name ## _shift), gpio->regs->field_name ## _mask
 
 #define CTX \
 	gpio->base.ctx
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.h b/drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.h
index bca0cef18ff9..5b551068cdd6 100644
--- a/drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.h
+++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_gpio.h
@@ -141,4 +141,13 @@ enum gpio_result dal_hw_gpio_change_mode(
 void dal_hw_gpio_close(
 	struct hw_gpio_pin *ptr);
 
+/*
+ * Shared helper used by all GPIO register helpers that pass a field shift
+ * (stored as uint32_t) into register functions that expect uint8_t.
+ */
+static inline uint8_t gpio_reg_shift(uint32_t shift)
+{
+	return (uint8_t)shift;
+}
+
 #endif
diff --git a/drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c b/drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c
index 79e107904e21..2cb960e517ae 100644
--- a/drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c
+++ b/drivers/gpu/drm/amd/display/dc/gpio/hw_hpd.c
@@ -35,7 +35,7 @@
 
 #undef FN
 #define FN(reg_name, field_name) \
-	hpd->shifts->field_name, hpd->masks->field_name
+	gpio_reg_shift(hpd->shifts->field_name), hpd->masks->field_name
 
 #define CTX \
 	hpd->base.base.ctx
diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c b/drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c
index 97ef8281a476..d683d0740c13 100644
--- a/drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn10/dcn10_hubbub.c
@@ -638,27 +638,27 @@ void hubbub1_update_dchub(
 				SDPIF_FB_BASE, 0x0FFFF);
 
 		REG_UPDATE(DCHUBBUB_SDPIF_AGP_BASE,
-				SDPIF_AGP_BASE, dh_data->zfb_phys_addr_base >> 22);
+				SDPIF_AGP_BASE, (uint32_t)(dh_data->zfb_phys_addr_base >> 22));
 
 		REG_UPDATE(DCHUBBUB_SDPIF_AGP_BOT,
-				SDPIF_AGP_BOT, dh_data->zfb_mc_base_addr >> 22);
+				SDPIF_AGP_BOT, (uint32_t)(dh_data->zfb_mc_base_addr >> 22));
 
 		REG_UPDATE(DCHUBBUB_SDPIF_AGP_TOP,
-				SDPIF_AGP_TOP, (dh_data->zfb_mc_base_addr +
-						dh_data->zfb_size_in_byte - 1) >> 22);
+				SDPIF_AGP_TOP, (uint32_t)((dh_data->zfb_mc_base_addr +
+						dh_data->zfb_size_in_byte - 1) >> 22));
 		break;
 	case FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL:
 		/*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/
 
 		REG_UPDATE(DCHUBBUB_SDPIF_AGP_BASE,
-				SDPIF_AGP_BASE, dh_data->zfb_phys_addr_base >> 22);
+				SDPIF_AGP_BASE, (uint32_t)(dh_data->zfb_phys_addr_base >> 22));
 
 		REG_UPDATE(DCHUBBUB_SDPIF_AGP_BOT,
-				SDPIF_AGP_BOT, dh_data->zfb_mc_base_addr >> 22);
+				SDPIF_AGP_BOT, (uint32_t)(dh_data->zfb_mc_base_addr >> 22));
 
 		REG_UPDATE(DCHUBBUB_SDPIF_AGP_TOP,
-				SDPIF_AGP_TOP, (dh_data->zfb_mc_base_addr +
-						dh_data->zfb_size_in_byte - 1) >> 22);
+				SDPIF_AGP_TOP, (uint32_t)((dh_data->zfb_mc_base_addr +
+						dh_data->zfb_size_in_byte - 1) >> 22));
 		break;
 	case FRAME_BUFFER_MODE_LOCAL_ONLY:
 		/*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/
diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c b/drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c
index 5c6f7ddafd6b..053a08b6d3a3 100644
--- a/drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.c
@@ -398,17 +398,17 @@ int hubbub2_init_dchub_sys_ctx(struct hubbub *hubbub,
 	struct dcn_vmid_page_table_config phys_config;
 
 	REG_SET(DCN_VM_FB_LOCATION_BASE, 0,
-			FB_BASE, pa_config->system_aperture.fb_base >> 24);
+			FB_BASE, ADDR_HI24(pa_config->system_aperture.fb_base));
 	REG_SET(DCN_VM_FB_LOCATION_TOP, 0,
-			FB_TOP, pa_config->system_aperture.fb_top >> 24);
+			FB_TOP, ADDR_HI24(pa_config->system_aperture.fb_top));
 	REG_SET(DCN_VM_FB_OFFSET, 0,
-			FB_OFFSET, pa_config->system_aperture.fb_offset >> 24);
+			FB_OFFSET, ADDR_HI24(pa_config->system_aperture.fb_offset));
 	REG_SET(DCN_VM_AGP_BOT, 0,
-			AGP_BOT, pa_config->system_aperture.agp_bot >> 24);
+			AGP_BOT, ADDR_HI24(pa_config->system_aperture.agp_bot));
 	REG_SET(DCN_VM_AGP_TOP, 0,
-			AGP_TOP, pa_config->system_aperture.agp_top >> 24);
+			AGP_TOP, ADDR_HI24(pa_config->system_aperture.agp_top));
 	REG_SET(DCN_VM_AGP_BASE, 0,
-			AGP_BASE, pa_config->system_aperture.agp_base >> 24);
+			AGP_BASE, ADDR_HI24(pa_config->system_aperture.agp_base));
 
 	REG_SET(DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB, 0,
 			DCN_VM_PROTECTION_FAULT_DEFAULT_ADDR_MSB, (pa_config->page_table_default_page_addr >> 44) & 0xF);
@@ -447,36 +447,36 @@ void hubbub2_update_dchub(struct hubbub *hubbub,
 
 		/*This field defines the 24 MSBs, bits [47:24] of the 48 bit AGP Base*/
 		REG_UPDATE(DCN_VM_AGP_BASE,
-				AGP_BASE, dh_data->zfb_phys_addr_base >> 24);
+				AGP_BASE, ADDR_HI24(dh_data->zfb_phys_addr_base));
 
 		/*This field defines the bottom range of the AGP aperture and represents the 24*/
 		/*MSBs, bits [47:24] of the 48 address bits*/
 		REG_UPDATE(DCN_VM_AGP_BOT,
-				AGP_BOT, dh_data->zfb_mc_base_addr >> 24);
+				AGP_BOT, ADDR_HI24(dh_data->zfb_mc_base_addr));
 
 		/*This field defines the top range of the AGP aperture and represents the 24*/
 		/*MSBs, bits [47:24] of the 48 address bits*/
 		REG_UPDATE(DCN_VM_AGP_TOP,
-				AGP_TOP, (dh_data->zfb_mc_base_addr +
-						dh_data->zfb_size_in_byte - 1) >> 24);
+				AGP_TOP, ADDR_HI24(dh_data->zfb_mc_base_addr +
+						dh_data->zfb_size_in_byte - 1));
 		break;
 	case FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL:
 		/*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/
 
 		/*This field defines the 24 MSBs, bits [47:24] of the 48 bit AGP Base*/
 		REG_UPDATE(DCN_VM_AGP_BASE,
-				AGP_BASE, dh_data->zfb_phys_addr_base >> 24);
+				AGP_BASE, ADDR_HI24(dh_data->zfb_phys_addr_base));
 
 		/*This field defines the bottom range of the AGP aperture and represents the 24*/
 		/*MSBs, bits [47:24] of the 48 address bits*/
 		REG_UPDATE(DCN_VM_AGP_BOT,
-				AGP_BOT, dh_data->zfb_mc_base_addr >> 24);
+				AGP_BOT, ADDR_HI24(dh_data->zfb_mc_base_addr));
 
 		/*This field defines the top range of the AGP aperture and represents the 24*/
 		/*MSBs, bits [47:24] of the 48 address bits*/
 		REG_UPDATE(DCN_VM_AGP_TOP,
-				AGP_TOP, (dh_data->zfb_mc_base_addr +
-						dh_data->zfb_size_in_byte - 1) >> 24);
+				AGP_TOP, ADDR_HI24(dh_data->zfb_mc_base_addr +
+						dh_data->zfb_size_in_byte - 1));
 		break;
 	case FRAME_BUFFER_MODE_LOCAL_ONLY:
 		/*Should not touch FB LOCATION (should be done by VBIOS)*/
diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.h b/drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.h
index 46d8f5c70750..6223dfaee270 100644
--- a/drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.h
+++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn20/dcn20_hubbub.h
@@ -141,4 +141,7 @@ void hubbub2_wm_read_state(struct hubbub *hubbub,
 void hubbub2_read_state(struct hubbub *hubbub,
 		struct dcn_hubbub_state *hubbub_state);
 
+/* Extract bits [47:24] of a physical address for hardware register fields */
+#define ADDR_HI24(a)  ((uint32_t)((uint64_t)(a) >> 24))
+
 #endif
diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c b/drivers/gpu/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c
index e4496ad203b2..d790d6ee359a 100644
--- a/drivers/gpu/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn21/dcn21_hubbub.c
@@ -111,17 +111,17 @@ int hubbub21_init_dchub(struct hubbub *hubbub,
 	struct dcn_vmid_page_table_config phys_config;
 
 	REG_SET(DCN_VM_FB_LOCATION_BASE, 0,
-			FB_BASE, pa_config->system_aperture.fb_base >> 24);
+			FB_BASE, ADDR_HI24(pa_config->system_aperture.fb_base));
 	REG_SET(DCN_VM_FB_LOCATION_TOP, 0,
-			FB_TOP, pa_config->system_aperture.fb_top >> 24);
+			FB_TOP, ADDR_HI24(pa_config->system_aperture.fb_top));
 	REG_SET(DCN_VM_FB_OFFSET, 0,
-			FB_OFFSET, pa_config->system_aperture.fb_offset >> 24);
+			FB_OFFSET, ADDR_HI24(pa_config->system_aperture.fb_offset));
 	REG_SET(DCN_VM_AGP_BOT, 0,
-			AGP_BOT, pa_config->system_aperture.agp_bot >> 24);
+			AGP_BOT, ADDR_HI24(pa_config->system_aperture.agp_bot));
 	REG_SET(DCN_VM_AGP_TOP, 0,
-			AGP_TOP, pa_config->system_aperture.agp_top >> 24);
+			AGP_TOP, ADDR_HI24(pa_config->system_aperture.agp_top));
 	REG_SET(DCN_VM_AGP_BASE, 0,
-			AGP_BASE, pa_config->system_aperture.agp_base >> 24);
+			AGP_BASE, ADDR_HI24(pa_config->system_aperture.agp_base));
 
 	if (pa_config->gart_config.page_table_start_addr != pa_config->gart_config.page_table_end_addr) {
 		phys_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr >> 12;
diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c b/drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
index 181a93dc46e6..6a7c1bee5747 100644
--- a/drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn30/dcn30_hubbub.c
@@ -68,17 +68,17 @@ int hubbub3_init_dchub_sys_ctx(struct hubbub *hubbub,
 	struct dcn_vmid_page_table_config phys_config;
 
 	REG_SET(DCN_VM_FB_LOCATION_BASE, 0,
-			FB_BASE, pa_config->system_aperture.fb_base >> 24);
+			FB_BASE, ADDR_HI24(pa_config->system_aperture.fb_base));
 	REG_SET(DCN_VM_FB_LOCATION_TOP, 0,
-			FB_TOP, pa_config->system_aperture.fb_top >> 24);
+			FB_TOP, ADDR_HI24(pa_config->system_aperture.fb_top));
 	REG_SET(DCN_VM_FB_OFFSET, 0,
-			FB_OFFSET, pa_config->system_aperture.fb_offset >> 24);
+			FB_OFFSET, ADDR_HI24(pa_config->system_aperture.fb_offset));
 	REG_SET(DCN_VM_AGP_BOT, 0,
-			AGP_BOT, pa_config->system_aperture.agp_bot >> 24);
+			AGP_BOT, ADDR_HI24(pa_config->system_aperture.agp_bot));
 	REG_SET(DCN_VM_AGP_TOP, 0,
-			AGP_TOP, pa_config->system_aperture.agp_top >> 24);
+			AGP_TOP, ADDR_HI24(pa_config->system_aperture.agp_top));
 	REG_SET(DCN_VM_AGP_BASE, 0,
-			AGP_BASE, pa_config->system_aperture.agp_base >> 24);
+			AGP_BASE, ADDR_HI24(pa_config->system_aperture.agp_base));
 
 	if (pa_config->gart_config.page_table_start_addr != pa_config->gart_config.page_table_end_addr) {
 		phys_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr >> 12;
diff --git a/drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c b/drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c
index 3c298192f359..79cb506be5cb 100644
--- a/drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/hubbub/dcn31/dcn31_hubbub.c
@@ -910,17 +910,17 @@ int hubbub31_init_dchub_sys_ctx(struct hubbub *hubbub,
 	struct dcn_vmid_page_table_config phys_config;
 
 	REG_SET(DCN_VM_FB_LOCATION_BASE, 0,
-			FB_BASE, pa_config->system_aperture.fb_base >> 24);
+			FB_BASE, ADDR_HI24(pa_config->system_aperture.fb_base));
 	REG_SET(DCN_VM_FB_LOCATION_TOP, 0,
-			FB_TOP, pa_config->system_aperture.fb_top >> 24);
+			FB_TOP, ADDR_HI24(pa_config->system_aperture.fb_top));
 	REG_SET(DCN_VM_FB_OFFSET, 0,
-			FB_OFFSET, pa_config->system_aperture.fb_offset >> 24);
+			FB_OFFSET, ADDR_HI24(pa_config->system_aperture.fb_offset));
 	REG_SET(DCN_VM_AGP_BOT, 0,
-			AGP_BOT, pa_config->system_aperture.agp_bot >> 24);
+			AGP_BOT, ADDR_HI24(pa_config->system_aperture.agp_bot));
 	REG_SET(DCN_VM_AGP_TOP, 0,
-			AGP_TOP, pa_config->system_aperture.agp_top >> 24);
+			AGP_TOP, ADDR_HI24(pa_config->system_aperture.agp_top));
 	REG_SET(DCN_VM_AGP_BASE, 0,
-			AGP_BASE, pa_config->system_aperture.agp_base >> 24);
+			AGP_BASE, ADDR_HI24(pa_config->system_aperture.agp_base));
 
 	if (pa_config->gart_config.page_table_start_addr != pa_config->gart_config.page_table_end_addr) {
 		phys_config.page_table_start_addr = pa_config->gart_config.page_table_start_addr >> 12;
diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
index ceee5165fd6a..244d4462fa9e 100644
--- a/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn20/dcn20_hubp.c
@@ -68,10 +68,10 @@ void hubp2_set_vm_system_aperture_settings(struct hubp *hubp,
 			DCN_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB, mc_vm_apt_default.low_part);
 
 	REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, 0,
-			MC_VM_SYSTEM_APERTURE_LOW_ADDR, mc_vm_apt_low.quad_part);
+			MC_VM_SYSTEM_APERTURE_LOW_ADDR, mc_vm_apt_low.low_part);
 
 	REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, 0,
-			MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mc_vm_apt_high.quad_part);
+			MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mc_vm_apt_high.low_part);
 
 	REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0,
 			ENABLE_L1_TLB, 1,
diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c
index 08ea0a1b9e7f..67828505939a 100644
--- a/drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn21/dcn21_hubp.c
@@ -238,10 +238,10 @@ static void hubp21_set_vm_system_aperture_settings(struct hubp *hubp,
 	mc_vm_apt_high.quad_part = apt->sys_high.quad_part >> 18;
 
 	REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, 0,
-			MC_VM_SYSTEM_APERTURE_LOW_ADDR, mc_vm_apt_low.quad_part);
+			MC_VM_SYSTEM_APERTURE_LOW_ADDR, mc_vm_apt_low.low_part);
 
 	REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, 0,
-			MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mc_vm_apt_high.quad_part);
+			MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mc_vm_apt_high.low_part);
 
 	REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0,
 			ENABLE_L1_TLB, 1,
diff --git a/drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c b/drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c
index e2708e30eb1b..3e5ae0eae39f 100644
--- a/drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/hubp/dcn30/dcn30_hubp.c
@@ -55,10 +55,10 @@ void hubp3_set_vm_system_aperture_settings(struct hubp *hubp,
 	mc_vm_apt_high.quad_part = apt->sys_high.quad_part >> 18;
 
 	REG_SET(DCN_VM_SYSTEM_APERTURE_LOW_ADDR, 0,
-			MC_VM_SYSTEM_APERTURE_LOW_ADDR, mc_vm_apt_low.quad_part);
+			MC_VM_SYSTEM_APERTURE_LOW_ADDR, mc_vm_apt_low.low_part);
 
 	REG_SET(DCN_VM_SYSTEM_APERTURE_HIGH_ADDR, 0,
-			MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mc_vm_apt_high.quad_part);
+			MC_VM_SYSTEM_APERTURE_HIGH_ADDR, mc_vm_apt_high.low_part);
 
 	REG_SET_2(DCN_VM_MX_L1_TLB_CNTL, 0,
 			ENABLE_L1_TLB, 1,
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
index 5273ca09fe12..e6712cffeb04 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c
@@ -665,16 +665,45 @@ void dce110_update_info_frame(struct pipe_ctx *pipe_ctx)
 }
 
 static void
-dce110_dac_encoder_control(struct pipe_ctx *pipe_ctx, bool enable)
+dce110_external_encoder_control(enum bp_external_encoder_control_action action,
+				struct dc_link *link,
+				struct dc_crtc_timing *timing)
 {
-	struct dc_link *link = pipe_ctx->stream->link;
+	struct dc *dc = link->ctx->dc;
 	struct dc_bios *bios = link->ctx->dc_bios;
-	struct bp_encoder_control encoder_control = {0};
+	const struct dc_link_settings *link_settings = &link->cur_link_settings;
+	enum bp_result bp_result = BP_RESULT_OK;
+	struct bp_external_encoder_control ext_cntl = {
+		.action = action,
+		.connector_obj_id = link->link_enc->connector,
+		.encoder_id = link->ext_enc_id,
+		.lanes_number = link_settings->lane_count,
+		.link_rate = link_settings->link_rate,
+
+		/* Use signal type of the real link encoder, ie. DP */
+		.signal = link->connector_signal,
+
+		/* We don't know the timing yet when executing the SETUP action,
+		 * so use a reasonably high default value. It seems that ENABLE
+		 * can change the actual pixel clock but doesn't work with higher
+		 * pixel clocks than what SETUP was called with.
+		 */
+		.pixel_clock = timing ? timing->pix_clk_100hz / 10 : 300000,
+		.color_depth = timing ? timing->display_color_depth : COLOR_DEPTH_888,
+	};
+	DC_LOGGER_INIT(dc->ctx);
+
+	bp_result = bios->funcs->external_encoder_control(bios, &ext_cntl);
+
+	if (bp_result != BP_RESULT_OK)
+		DC_LOG_ERROR("Failed to execute external encoder action: 0x%x\n", action);
+}
 
-	encoder_control.action = enable ? ENCODER_CONTROL_ENABLE : ENCODER_CONTROL_DISABLE;
-	encoder_control.engine_id = link->link_enc->analog_engine;
-	encoder_control.pixel_clock = pipe_ctx->stream->timing.pix_clk_100hz / 10;
-	bios->funcs->encoder_control(bios, &encoder_control);
+static void
+dce110_prepare_ddc(struct dc_link *link)
+{
+	if (link->ext_enc_id.id)
+		dce110_external_encoder_control(EXTERNAL_ENCODER_CONTROL_DDC_SETUP, link, NULL);
 }
 
 static bool
@@ -684,7 +713,8 @@ dce110_dac_load_detect(struct dc_link *link)
 	struct link_encoder *link_enc = link->link_enc;
 	enum bp_result bp_result;
 
-	bp_result = bios->funcs->dac_load_detection(bios, link_enc->analog_engine);
+	bp_result = bios->funcs->dac_load_detection(
+			bios, link_enc->analog_engine, link->ext_enc_id);
 	return bp_result == BP_RESULT_OK;
 }
 
@@ -700,7 +730,6 @@ void dce110_enable_stream(struct pipe_ctx *pipe_ctx)
 	uint32_t early_control = 0;
 	struct timing_generator *tg = pipe_ctx->stream_res.tg;
 
-	link_hwss->setup_stream_attribute(pipe_ctx);
 	link_hwss->setup_stream_encoder(pipe_ctx);
 
 	dc->hwss.update_info_frame(pipe_ctx);
@@ -719,8 +748,8 @@ void dce110_enable_stream(struct pipe_ctx *pipe_ctx)
 
 	tg->funcs->set_early_control(tg, early_control);
 
-	if (dc_is_rgb_signal(pipe_ctx->stream->signal))
-		dce110_dac_encoder_control(pipe_ctx, true);
+	if (link->ext_enc_id.id)
+		dce110_external_encoder_control(EXTERNAL_ENCODER_CONTROL_ENABLE, link, timing);
 }
 
 static enum bp_result link_transmitter_control(
@@ -858,7 +887,7 @@ void dce110_edp_power_control(
 				DC_LOG_HW_RESUME_S3(
 						"%s: remaining_min_edp_poweroff_time_ms=%llu: begin wait.\n",
 						__func__, remaining_min_edp_poweroff_time_ms);
-				msleep(remaining_min_edp_poweroff_time_ms);
+				msleep((unsigned int)remaining_min_edp_poweroff_time_ms);
 				DC_LOG_HW_RESUME_S3(
 						"%s: remaining_min_edp_poweroff_time_ms=%llu: end wait.\n",
 						__func__, remaining_min_edp_poweroff_time_ms);
@@ -883,7 +912,7 @@ void dce110_edp_power_control(
 		cntl.coherent = false;
 		cntl.lanes_number = LANE_COUNT_FOUR;
 		cntl.hpd_sel = link->link_enc->hpd_source;
-		pwrseq_instance = link->panel_cntl->pwrseq_inst;
+		pwrseq_instance = (uint8_t)link->panel_cntl->pwrseq_inst;
 
 		if (ctx->dc->ctx->dmub_srv &&
 				ctx->dc->debug.dmub_command_table) {
@@ -952,7 +981,7 @@ void dce110_edp_wait_for_T12(
 		t12_duration += link->panel_config.pps.extra_t12_ms; // Add extra T12
 
 		if (time_since_edp_poweroff_ms < t12_duration)
-			msleep(t12_duration - time_since_edp_poweroff_ms);
+			msleep((unsigned int)(t12_duration - time_since_edp_poweroff_ms));
 	}
 }
 /*todo: cloned in stream enc, fix*/
@@ -1021,8 +1050,9 @@ void dce110_edp_backlight_control(
 	 */
 	/* dc_service_sleep_in_milliseconds(50); */
 		/*edp 1.2*/
-	if (link->panel_cntl)
-		pwrseq_instance = link->panel_cntl->pwrseq_inst;
+	if (link->panel_cntl) {
+		pwrseq_instance = (uint8_t)link->panel_cntl->pwrseq_inst;
+	}
 
 	if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_ON) {
 		if (!link->dc->config.edp_no_power_sequencing)
@@ -1219,8 +1249,8 @@ void dce110_disable_stream(struct pipe_ctx *pipe_ctx)
 					       link_enc->transmitter - TRANSMITTER_UNIPHY_A);
 	}
 
-	if (dc_is_rgb_signal(pipe_ctx->stream->signal))
-		dce110_dac_encoder_control(pipe_ctx, false);
+	if (link->ext_enc_id.id)
+		dce110_external_encoder_control(EXTERNAL_ENCODER_CONTROL_DISABLE, link, NULL);
 }
 
 void dce110_unblank_stream(struct pipe_ctx *pipe_ctx,
@@ -1439,11 +1469,11 @@ void build_audio_output(
 	audio_output->crtc_info.pixel_repetition = 1;
 
 	audio_output->crtc_info.interlaced =
-			stream->timing.flags.INTERLACE;
+			(stream->timing.flags.INTERLACE != 0);
 
 	audio_output->crtc_info.refresh_rate =
-		(stream->timing.pix_clk_100hz*100)/
-		(stream->timing.h_total*stream->timing.v_total);
+		(uint16_t)((stream->timing.pix_clk_100hz*100)/
+		(stream->timing.h_total*stream->timing.v_total));
 
 	audio_output->crtc_info.color_depth =
 		stream->timing.display_color_depth;
@@ -1603,22 +1633,6 @@ static enum dc_status dce110_enable_stream_timing(
 
 	return DC_OK;
 }
-static void
-dce110_select_crtc_source(struct pipe_ctx *pipe_ctx)
-{
-	struct dc_link *link = pipe_ctx->stream->link;
-	struct dc_bios *bios = link->ctx->dc_bios;
-	struct bp_crtc_source_select crtc_source_select = {0};
-	enum engine_id engine_id = link->link_enc->preferred_engine;
-
-	if (dc_is_rgb_signal(pipe_ctx->stream->signal))
-		engine_id = link->link_enc->analog_engine;
-	crtc_source_select.controller_id = CONTROLLER_ID_D0 + pipe_ctx->stream_res.tg->inst;
-	crtc_source_select.color_depth = pipe_ctx->stream->timing.display_color_depth;
-	crtc_source_select.engine_id = engine_id;
-	crtc_source_select.sink_signal = pipe_ctx->stream->signal;
-	bios->funcs->select_crtc_source(bios, &crtc_source_select);
-}
 
 enum dc_status dce110_apply_single_controller_ctx_to_hw(
 		struct pipe_ctx *pipe_ctx,
@@ -1639,10 +1653,6 @@ enum dc_status dce110_apply_single_controller_ctx_to_hw(
 		hws->funcs.disable_stream_gating(dc, pipe_ctx);
 	}
 
-	if (pipe_ctx->stream->signal == SIGNAL_TYPE_RGB) {
-		dce110_select_crtc_source(pipe_ctx);
-	}
-
 	if (pipe_ctx->stream_res.audio != NULL) {
 		struct audio_output audio_output = {0};
 
@@ -1722,8 +1732,7 @@ enum dc_status dce110_apply_single_controller_ctx_to_hw(
 		pipe_ctx->stream_res.tg->funcs->set_static_screen_control(
 				pipe_ctx->stream_res.tg, event_triggers, 2);
 
-	if (!dc_is_virtual_signal(pipe_ctx->stream->signal) &&
-		!dc_is_rgb_signal(pipe_ctx->stream->signal))
+	if (!dc_is_virtual_signal(pipe_ctx->stream->signal))
 		pipe_ctx->stream_res.stream_enc->funcs->dig_connect_to_otg(
 			pipe_ctx->stream_res.stream_enc,
 			pipe_ctx->stream_res.tg->inst);
@@ -1839,7 +1848,7 @@ static void power_down_all_hw_blocks(struct dc *dc)
 static void disable_vga_and_power_gate_all_controllers(
 		struct dc *dc)
 {
-	int i;
+	uint8_t i;
 	struct timing_generator *tg;
 	struct dc_context *ctx = dc->ctx;
 
@@ -1869,7 +1878,7 @@ static void get_edp_streams(struct dc_state *context,
 		struct dc_stream_state **edp_streams,
 		int *edp_stream_num)
 {
-	int i;
+	uint8_t i;
 
 	*edp_stream_num = 0;
 	for (i = 0; i < context->stream_count; i++) {
@@ -2115,9 +2124,11 @@ static uint32_t compute_pstate_blackout_duration(
 	const struct dc_stream_state *stream)
 {
 	uint32_t total_dest_line_time_ns;
+	int64_t pstate_blackout_duration_ns64;
 	uint32_t pstate_blackout_duration_ns;
 
-	pstate_blackout_duration_ns = 1000 * blackout_duration.value >> 24;
+	pstate_blackout_duration_ns64 = (1000 * blackout_duration.value) >> 24;
+	pstate_blackout_duration_ns = (uint32_t)pstate_blackout_duration_ns64;
 
 	total_dest_line_time_ns = 1000000UL *
 		(stream->timing.h_total * 10) /
@@ -2574,7 +2585,7 @@ enum dc_status dce110_apply_ctx_to_hw(
 		}
 
 		hws->funcs.enable_display_power_gating(
-				dc, i, dc->ctx->dc_bios,
+				dc, (uint8_t)i, dc->ctx->dc_bios,
 				PIPE_GATING_CONTROL_DISABLE);
 	}
 
@@ -2919,10 +2930,10 @@ static void dce110_init_hw(struct dc *dc)
 		xfm->funcs->transform_reset(xfm);
 
 		hws->funcs.enable_display_power_gating(
-				dc, i, bp,
+				dc, (uint8_t)i, bp,
 				PIPE_GATING_CONTROL_INIT);
 		hws->funcs.enable_display_power_gating(
-				dc, i, bp,
+				dc, (uint8_t)i, bp,
 				PIPE_GATING_CONTROL_DISABLE);
 		hws->funcs.enable_display_pipe_clock_gating(
 			dc->ctx,
@@ -3180,7 +3191,7 @@ static void dce110_power_down_fe(struct dc *dc, struct dc_state *state, struct p
 		return;
 
 	hws->funcs.enable_display_power_gating(
-		dc, fe_idx, dc->ctx->dc_bios, PIPE_GATING_CONTROL_ENABLE);
+		dc, (uint8_t)fe_idx, dc->ctx->dc_bios, PIPE_GATING_CONTROL_ENABLE);
 
 	dc->res_pool->transforms[fe_idx]->funcs->transform_reset(
 				dc->res_pool->transforms[fe_idx]);
@@ -3376,6 +3387,15 @@ void dce110_enable_tmds_link_output(struct dc_link *link,
 	link->phy_state.symclk_state = SYMCLK_ON_TX_ON;
 }
 
+static void dce110_enable_analog_link_output(
+		struct dc_link *link,
+		uint32_t pix_clk_100hz)
+{
+	link->link_enc->funcs->enable_analog_output(
+			link->link_enc,
+			pix_clk_100hz);
+}
+
 void dce110_enable_dp_link_output(
 		struct dc_link *link,
 		const struct link_resource *link_res,
@@ -3423,6 +3443,11 @@ void dce110_enable_dp_link_output(
 		}
 	}
 
+	if (link->ext_enc_id.id) {
+		dce110_external_encoder_control(EXTERNAL_ENCODER_CONTROL_INIT, link, NULL);
+		dce110_external_encoder_control(EXTERNAL_ENCODER_CONTROL_SETUP, link, NULL);
+	}
+
 	if (dc->link_srv->dp_get_encoding_format(link_settings) == DP_8b_10b_ENCODING) {
 		if (dc->clk_mgr->funcs->notify_link_rate_change)
 			dc->clk_mgr->funcs->notify_link_rate_change(dc->clk_mgr, link);
@@ -3513,8 +3538,10 @@ static const struct hw_sequencer_funcs dce110_funcs = {
 	.enable_lvds_link_output = dce110_enable_lvds_link_output,
 	.enable_tmds_link_output = dce110_enable_tmds_link_output,
 	.enable_dp_link_output = dce110_enable_dp_link_output,
+	.enable_analog_link_output = dce110_enable_analog_link_output,
 	.disable_link_output = dce110_disable_link_output,
 	.dac_load_detect = dce110_dac_load_detect,
+	.prepare_ddc = dce110_prepare_ddc,
 };
 
 static const struct hwseq_private_funcs dce110_private_funcs = {
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c
index 0689bbf12ad8..fbe34d1bb39a 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dce120/dce120_hwseq.c
@@ -208,24 +208,24 @@ static void dce120_update_dchub(
 				FB_BASE, 0x0FFFF);
 
 		REG_UPDATE(DCHUB_AGP_BASE,
-				AGP_BASE, dh_data->zfb_phys_addr_base >> 22);
+				AGP_BASE, (uint32_t)(dh_data->zfb_phys_addr_base >> 22));
 
 		REG_UPDATE(DCHUB_AGP_BOT,
-				AGP_BOT, dh_data->zfb_mc_base_addr >> 22);
+				AGP_BOT, (uint32_t)(dh_data->zfb_mc_base_addr >> 22));
 
 		REG_UPDATE(DCHUB_AGP_TOP,
-				AGP_TOP, (dh_data->zfb_mc_base_addr + dh_data->zfb_size_in_byte - 1) >> 22);
+				AGP_TOP, (uint32_t)((dh_data->zfb_mc_base_addr + dh_data->zfb_size_in_byte - 1) >> 22));
 		break;
 	case FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL:
 		/*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/
 		REG_UPDATE(DCHUB_AGP_BASE,
-				AGP_BASE, dh_data->zfb_phys_addr_base >> 22);
+				AGP_BASE, (uint32_t)(dh_data->zfb_phys_addr_base >> 22));
 
 		REG_UPDATE(DCHUB_AGP_BOT,
-				AGP_BOT, dh_data->zfb_mc_base_addr >> 22);
+				AGP_BOT, (uint32_t)(dh_data->zfb_mc_base_addr >> 22));
 
 		REG_UPDATE(DCHUB_AGP_TOP,
-				AGP_TOP, (dh_data->zfb_mc_base_addr + dh_data->zfb_size_in_byte - 1) >> 22);
+				AGP_TOP, (uint32_t)((dh_data->zfb_mc_base_addr + dh_data->zfb_size_in_byte - 1) >> 22));
 		break;
 	case FRAME_BUFFER_MODE_LOCAL_ONLY:
 		/*Should not touch FB LOCATION (done by VBIOS on AsicInit table)*/
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
index 756ce8379538..f35b07e88a39 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
@@ -1574,7 +1574,7 @@ void dcn10_disable_plane(struct dc *dc, struct dc_state *state, struct pipe_ctx
 
 void dcn10_init_pipes(struct dc *dc, struct dc_state *context)
 {
-	int i;
+	uint8_t i;
 	struct dce_hwseq *hws = dc->hwseq;
 	struct hubbub *hubbub = dc->res_pool->hubbub;
 	bool can_apply_seamless_boot = false;
@@ -1677,7 +1677,7 @@ void dcn10_init_pipes(struct dc *dc, struct dc_state *context)
 
 		pipe_ctx->plane_res.hubp = hubp;
 		pipe_ctx->plane_res.dpp = dpp;
-		pipe_ctx->plane_res.mpcc_inst = dpp->inst;
+		pipe_ctx->plane_res.mpcc_inst = (uint8_t)dpp->inst;
 		hubp->mpcc_id = dpp->inst;
 		hubp->opp_id = OPP_ID_INVALID;
 		hubp->power_gated = false;
@@ -2258,7 +2258,7 @@ void dcn10_cursor_lock(struct dc *dc, struct pipe_ctx *pipe, bool lock)
 		struct dmub_hw_lock_inst_flags inst_flags = { 0 };
 
 		hw_locks.bits.lock_cursor = 1;
-		inst_flags.opp_inst = pipe->stream_res.opp->inst;
+		inst_flags.opp_inst = (uint8_t)pipe->stream_res.opp->inst;
 
 		dmub_hw_lock_mgr_cmd(dc->ctx->dmub_srv,
 					lock,
@@ -2383,7 +2383,7 @@ static uint8_t get_clock_divider(struct pipe_ctx *pipe,
 	}
 	clock_divider *= numpipes;
 
-	return clock_divider;
+	return (uint8_t)clock_divider;
 }
 
 static int dcn10_align_pixel_clocks(struct dc *dc, int group_size,
@@ -2458,7 +2458,7 @@ static int dcn10_align_pixel_clocks(struct dc *dc, int group_size,
 				dc->res_pool->dp_clock_source->funcs->override_dp_pix_clk(
 					dc->res_pool->dp_clock_source,
 					grouped_pipes[i]->stream_res.tg->inst,
-					phase[i], modulo[i]);
+					(unsigned int)phase[i], (unsigned int)modulo[i]);
 				dc->res_pool->dp_clock_source->funcs->get_pixel_clk_frequency_100hz(
 					dc->res_pool->dp_clock_source,
 					grouped_pipes[i]->stream_res.tg->inst, &pclk);
@@ -3516,7 +3516,7 @@ void dcn10_config_stereo_parameters(
 			}
 		}
 		flags->RIGHT_EYE_POLARITY =\
-				stream->timing.flags.RIGHT_EYE_3D_POLARITY;
+				(stream->timing.flags.RIGHT_EYE_3D_POLARITY != 0);
 		if (timing_3d_format == TIMING_3D_FORMAT_HW_FRAME_PACKING)
 			flags->FRAME_PACKED = 1;
 	}
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
index 288e4edaa9a2..c2ea0106fdec 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
@@ -235,7 +235,7 @@ void dcn20_setup_gsl_group_as_lock(
 
 		group_idx = find_free_gsl_group(dc);
 		ASSERT(group_idx != 0);
-		pipe_ctx->stream_res.gsl_group = group_idx;
+		pipe_ctx->stream_res.gsl_group = (uint8_t)group_idx;
 
 		/* set gsl group reg field and mark resource used */
 		switch (group_idx) {
@@ -826,7 +826,7 @@ enum dc_status dcn20_enable_stream_timing(
 	unsigned int event_triggers = 0;
 	int opp_cnt = 1;
 	int opp_inst[MAX_PIPES] = {0};
-	bool interlace = stream->timing.flags.INTERLACE;
+	bool interlace = (stream->timing.flags.INTERLACE != 0);
 	int i;
 	struct mpc_dwb_flow_control flow_control;
 	struct mpc *mpc = dc->res_pool->mpc;
@@ -1452,7 +1452,7 @@ void dcn20_pipe_control_lock(
 		struct dmub_hw_lock_inst_flags inst_flags = { 0 };
 
 		hw_locks.bits.lock_pipe = 1;
-		inst_flags.otg_inst =  pipe->stream_res.tg->inst;
+		inst_flags.otg_inst = (uint8_t)pipe->stream_res.tg->inst;
 
 		if (pipe->plane_state != NULL)
 			hw_locks.bits.triple_buffer_lock = pipe->plane_state->triplebuffer_flips;
@@ -2733,7 +2733,8 @@ void dcn20_update_plane_addr(const struct dc *dc, struct pipe_ctx *pipe_ctx)
 	addr_patched = patch_address_for_sbs_tb_stereo(pipe_ctx, &addr);
 
 	// Call Helper to track VMID use
-	vm_helper_mark_vmid_used(dc->vm_helper, plane_state->address.vmid, pipe_ctx->plane_res.hubp->inst);
+	vm_helper_mark_vmid_used(dc->vm_helper, plane_state->address.vmid,
+			(uint8_t)pipe_ctx->plane_res.hubp->inst);
 
 	pipe_ctx->plane_res.hubp->funcs->hubp_program_surface_flip_and_addr(
 			pipe_ctx->plane_res.hubp,
@@ -3126,7 +3127,7 @@ void dcn20_program_dmdata_engine(struct pipe_ctx *pipe_ctx)
 
 void dcn20_fpga_init_hw(struct dc *dc)
 {
-	int i, j;
+	uint8_t i, j;
 	struct dce_hwseq *hws = dc->hwseq;
 	struct resource_pool *res_pool = dc->res_pool;
 	struct dc_state  *context = dc->current_state;
@@ -3199,7 +3200,7 @@ void dcn20_fpga_init_hw(struct dc *dc)
 
 		pipe_ctx->plane_res.hubp = hubp;
 		pipe_ctx->plane_res.dpp = dpp;
-		pipe_ctx->plane_res.mpcc_inst = dpp->inst;
+		pipe_ctx->plane_res.mpcc_inst = (uint8_t)dpp->inst;
 		hubp->mpcc_id = dpp->inst;
 		hubp->opp_id = OPP_ID_INVALID;
 		hubp->power_gated = false;
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c
index 062745389d9a..0988369bd968 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c
@@ -146,10 +146,10 @@ bool dcn21_dmub_abm_set_pipe(struct abm *abm, uint32_t otg_inst,
 	memset(&cmd, 0, sizeof(cmd));
 	cmd.abm_set_pipe.header.type = DMUB_CMD__ABM;
 	cmd.abm_set_pipe.header.sub_type = DMUB_CMD__ABM_SET_PIPE;
-	cmd.abm_set_pipe.abm_set_pipe_data.otg_inst = otg_inst;
-	cmd.abm_set_pipe.abm_set_pipe_data.pwrseq_inst = pwrseq_inst;
-	cmd.abm_set_pipe.abm_set_pipe_data.set_pipe_option = option;
-	cmd.abm_set_pipe.abm_set_pipe_data.panel_inst = panel_inst;
+	cmd.abm_set_pipe.abm_set_pipe_data.otg_inst = (uint8_t)otg_inst;
+	cmd.abm_set_pipe.abm_set_pipe_data.pwrseq_inst = (uint8_t)pwrseq_inst;
+	cmd.abm_set_pipe.abm_set_pipe_data.set_pipe_option = (uint8_t)option;
+	cmd.abm_set_pipe.abm_set_pipe_data.panel_inst = (uint8_t)panel_inst;
 	cmd.abm_set_pipe.abm_set_pipe_data.ramping_boundary = ramping_boundary;
 	cmd.abm_set_pipe.header.payload_bytes = sizeof(struct dmub_cmd_abm_set_pipe_data);
 
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
index 2aa0f1de8103..2705c58a9150 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
@@ -978,7 +978,7 @@ bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable)
 							cursor_cache_enable ? &cursor_attr : NULL)) {
 				unsigned int v_total = stream->adjust.v_total_max ?
 						stream->adjust.v_total_max : stream->timing.v_total;
-				unsigned int refresh_hz = div_u64((unsigned long long) stream->timing.pix_clk_100hz *
+				unsigned int refresh_hz = (unsigned int)div_u64((unsigned long long)stream->timing.pix_clk_100hz *
 						100LL, (v_total * stream->timing.h_total));
 
 				/*
@@ -1006,9 +1006,9 @@ bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable)
 				unsigned int denom = refresh_hz * 6528;
 				unsigned int stutter_period = dc->current_state->perf_params.stutter_period_us;
 
-				tmr_delay = div_u64(((1000000LL + 2 * stutter_period * refresh_hz) *
+				tmr_delay = (uint32_t)(div_u64(((1000000LL + 2 * stutter_period * refresh_hz) *
 						(100LL + dc->debug.mall_additional_timer_percent) + denom - 1),
-						denom) - 64LL;
+						denom) - 64LL);
 
 				/* In some cases the stutter period is really big (tiny modes) in these
 				 * cases MALL cant be enabled, So skip these cases to avoid a ASSERT()
@@ -1030,9 +1030,9 @@ bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable)
 					}
 
 					denom *= 2;
-					tmr_delay = div_u64(((1000000LL + 2 * stutter_period * refresh_hz) *
+					tmr_delay = (uint32_t)(div_u64(((1000000LL + 2 * stutter_period * refresh_hz) *
 							(100LL + dc->debug.mall_additional_timer_percent) + denom - 1),
-							denom) - 64LL;
+							denom) - 64LL);
 				}
 
 				/* Copy HW cursor */
@@ -1062,9 +1062,9 @@ bool dcn30_apply_idle_power_optimizations(struct dc *dc, bool enable)
 					cmd.mall.cursor_copy_src.quad_part = cursor_attr.address.quad_part;
 					cmd.mall.cursor_copy_dst.quad_part =
 							(plane->address.grph.cursor_cache_addr.quad_part + 2047) & ~2047;
-					cmd.mall.cursor_width = cursor_attr.width;
-					cmd.mall.cursor_height = cursor_attr.height;
-					cmd.mall.cursor_pitch = cursor_attr.pitch;
+					cmd.mall.cursor_width = (uint16_t)cursor_attr.width;
+					cmd.mall.cursor_height = (uint16_t)cursor_attr.height;
+					cmd.mall.cursor_pitch = (uint16_t)cursor_attr.pitch;
 
 					dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
 
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
index 858a06b03b57..1e856ee508f1 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn314/dcn314_hwseq.c
@@ -211,7 +211,7 @@ void dcn314_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx
 	if (pipe_ctx->stream_res.dsc) {
 		struct pipe_ctx *current_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx];
 
-		update_dsc_on_stream(pipe_ctx, pipe_ctx->stream->timing.flags.DSC);
+		update_dsc_on_stream(pipe_ctx, pipe_ctx->stream->timing.flags.DSC != 0);
 
 		/* Check if no longer using pipe for ODM, then need to disconnect DSC for that pipe */
 		if (!pipe_ctx->next_odm_pipe && current_pipe_ctx->next_odm_pipe &&
@@ -419,7 +419,7 @@ void dcn314_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc
 			if (dcn314_is_pipe_dig_fifo_on(pipe))
 				continue;
 			pipe->stream_res.tg->funcs->disable_crtc(pipe->stream_res.tg);
-			reset_sync_context_for_pipe(dc, context, i);
+			reset_sync_context_for_pipe(dc, context, (uint8_t)i);
 			otg_disabled[i] = true;
 		}
 	}
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
index b45ceb570a5c..7dbaaf9403f2 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
@@ -1175,7 +1175,7 @@ void dcn32_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *
 	if (pipe_ctx->stream_res.dsc) {
 		struct pipe_ctx *current_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx];
 
-		dcn32_update_dsc_on_stream(pipe_ctx, pipe_ctx->stream->timing.flags.DSC);
+		dcn32_update_dsc_on_stream(pipe_ctx, pipe_ctx->stream->timing.flags.DSC != 0);
 
 		/* Check if no longer using pipe for ODM, then need to disconnect DSC for that pipe */
 		if (!pipe_ctx->next_odm_pipe && current_pipe_ctx->next_odm_pipe &&
@@ -1277,7 +1277,7 @@ void dcn32_resync_fifo_dccg_dio(struct dce_hwseq *hws, struct dc *dc, struct dc_
 		if ((pipe->stream->dpms_off || dc_is_virtual_signal(pipe->stream->signal))
 			&& dc_state_get_pipe_subvp_type(dc_state, pipe) != SUBVP_PHANTOM) {
 			pipe->stream_res.tg->funcs->disable_crtc(pipe->stream_res.tg);
-			reset_sync_context_for_pipe(dc, context, i);
+			reset_sync_context_for_pipe(dc, context, (uint8_t)i);
 			otg_disabled[i] = true;
 		}
 	}
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
index f133b52ea958..894d48fcd7f8 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
@@ -467,7 +467,7 @@ void dcn35_update_odm(struct dc *dc, struct dc_state *context, struct pipe_ctx *
 	if (pipe_ctx->stream_res.dsc) {
 		struct pipe_ctx *current_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[pipe_ctx->pipe_idx];
 
-		update_dsc_on_stream(pipe_ctx, pipe_ctx->stream->timing.flags.DSC);
+		update_dsc_on_stream(pipe_ctx, pipe_ctx->stream->timing.flags.DSC != 0);
 
 		/* Check if no longer using pipe for ODM, then need to disconnect DSC for that pipe */
 		if (!pipe_ctx->next_odm_pipe && current_pipe_ctx->next_odm_pipe &&
@@ -621,7 +621,7 @@ void dcn35_z10_restore(const struct dc *dc)
 
 void dcn35_init_pipes(struct dc *dc, struct dc_state *context)
 {
-	int i;
+	uint8_t i;
 	struct dce_hwseq *hws = dc->hwseq;
 	struct hubbub *hubbub = dc->res_pool->hubbub;
 	struct pg_cntl *pg_cntl = dc->res_pool->pg_cntl;
@@ -725,7 +725,7 @@ void dcn35_init_pipes(struct dc *dc, struct dc_state *context)
 
 		pipe_ctx->plane_res.hubp = hubp;
 		pipe_ctx->plane_res.dpp = dpp;
-		pipe_ctx->plane_res.mpcc_inst = dpp->inst;
+		pipe_ctx->plane_res.mpcc_inst = (uint8_t)dpp->inst;
 		hubp->mpcc_id = dpp->inst;
 		hubp->opp_id = OPP_ID_INVALID;
 		hubp->power_gated = false;
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
index 9768b8f6b6fb..828f01980115 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
@@ -1158,7 +1158,7 @@ static bool dcn401_check_no_memory_request_for_cab(struct dc *dc)
 static uint32_t dcn401_calculate_cab_allocation(struct dc *dc, struct dc_state *ctx)
 {
 	int i;
-	uint8_t num_ways = 0;
+	uint32_t num_ways = 0;
 	uint32_t mall_ss_size_bytes = 0;
 
 	mall_ss_size_bytes = ctx->bw_ctx.bw.dcn.mall_ss_size_bytes;
@@ -1189,7 +1189,8 @@ static uint32_t dcn401_calculate_cab_allocation(struct dc *dc, struct dc_state *
 bool dcn401_apply_idle_power_optimizations(struct dc *dc, bool enable)
 {
 	union dmub_rb_cmd cmd;
-	uint8_t ways, i;
+	uint32_t ways;
+	uint8_t i;
 	int j;
 	bool mall_ss_unsupported = false;
 	struct dc_plane_state *plane = NULL;
@@ -1242,7 +1243,7 @@ bool dcn401_apply_idle_power_optimizations(struct dc *dc, bool enable)
 			}
 			if (ways <= dc->caps.cache_num_ways && !mall_ss_unsupported) {
 				cmd.cab.header.sub_type = DMUB_CMD__CAB_DCN_SS_FIT_IN_CAB;
-				cmd.cab.cab_alloc_ways = ways;
+				cmd.cab.cab_alloc_ways = (uint8_t)ways;
 				DC_LOG_MALL("cab allocation: %d ways. CAB action: DCN_SS_FIT_IN_CAB\n", ways);
 			} else {
 				cmd.cab.header.sub_type = DMUB_CMD__CAB_DCN_SS_NOT_FIT_IN_CAB;
@@ -1433,12 +1434,15 @@ void dcn401_dmub_hw_control_lock_fast(union block_sequence_params *params)
 void dcn401_fams2_update_config(struct dc *dc, struct dc_state *context, bool enable)
 {
 	bool fams2_info_required;
+	bool fams2_enabled;
+	bool fams2_legacy_no_fams2;
 
 	if (!dc->ctx || !dc->ctx->dmub_srv || !dc->debug.fams2_config.bits.enable)
 		return;
 
-	fams2_info_required = context->bw_ctx.bw.dcn.fams2_global_config.features.bits.enable;
-	fams2_info_required |= context->bw_ctx.bw.dcn.fams2_global_config.features.bits.legacy_method_no_fams2;
+	fams2_enabled = context->bw_ctx.bw.dcn.fams2_global_config.features.bits.enable != 0u;
+	fams2_legacy_no_fams2 = context->bw_ctx.bw.dcn.fams2_global_config.features.bits.legacy_method_no_fams2 != 0u;
+	fams2_info_required = fams2_enabled || fams2_legacy_no_fams2;
 
 	dc_dmub_srv_fams2_update_config(dc, context, enable && fams2_info_required);
 }
@@ -1470,7 +1474,7 @@ static void update_dsc_for_odm_change(struct dc *dc, struct dc_state *context,
 
 	if (otg_master->stream_res.dsc)
 		dcn32_update_dsc_on_stream(otg_master,
-				otg_master->stream->timing.flags.DSC);
+				otg_master->stream->timing.flags.DSC != 0u);
 	if (old_otg_master && old_otg_master->stream_res.dsc) {
 		for (i = 0; i < old_opp_head_count; i++) {
 			old_pipe = old_opp_heads[i];
@@ -3297,7 +3301,7 @@ void dcn401_setup_gsl_group_as_lock_sequence(
 
 		group_idx = find_free_gsl_group(dc);
 		ASSERT(group_idx != 0);
-		pipe_ctx->stream_res.gsl_group = group_idx;
+		pipe_ctx->stream_res.gsl_group = (uint8_t)group_idx;
 
 		/* set gsl group reg field and mark resource used */
 		switch (group_idx) {
diff --git a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h
index d1dba7ffcd9b..1cb2be00bf72 100644
--- a/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/hwss/hw_sequencer.h
@@ -91,6 +91,37 @@ struct program_gamut_remap_params {
 	struct pipe_ctx *pipe_ctx;
 };
 
+struct hubp_enable_3dlut_fl_params {
+	struct hubp *hubp;
+};
+
+struct tg_setup_vertical_interrupt0_params {
+	struct timing_generator *tg;
+	uint32_t start_line;
+	uint32_t end_line;
+};
+
+struct update_info_frame_params {
+	struct dc *dc;
+	struct pipe_ctx *pipe_ctx;
+};
+
+struct setup_periodic_interrupt_params {
+	struct dc *dc;
+	struct pipe_ctx *pipe_ctx;
+};
+
+struct dp_trace_source_sequence_params {
+	struct dc *dc;
+	struct dc_link *link;
+	uint8_t dp_test_mode;
+};
+
+struct set_dmdata_attributes_params {
+	struct hubp *hubp;
+	struct dc_dmdata_attributes attr;
+};
+
 struct program_manual_trigger_params {
 	struct pipe_ctx *pipe_ctx;
 };
@@ -707,11 +738,47 @@ struct abort_cursor_offload_update_params {
 	struct pipe_ctx *pipe_ctx;
 };
 
+struct cursor_lock_params {
+	struct dc *dc;
+	struct pipe_ctx *pipe_ctx;
+	bool lock;
+};
+
+struct begin_cursor_offload_update_params {
+	struct dc *dc;
+	struct pipe_ctx *pipe_ctx;
+};
+
+struct commit_cursor_offload_update_params {
+	struct dc *dc;
+	struct pipe_ctx *pipe_ctx;
+};
+
+struct update_cursor_offload_pipe_params {
+	struct dc *dc;
+	struct pipe_ctx *pipe_ctx;
+};
+
+struct send_cursor_info_to_dmu_params {
+	struct pipe_ctx *pipe_ctx;
+	int pipe_idx;
+};
+
 struct set_cursor_attribute_params {
 	struct dc *dc;
 	struct pipe_ctx *pipe_ctx;
 };
 
+struct hubp_set_cursor_attributes_params {
+	struct hubp *hubp;
+	const struct dc_cursor_attributes *attributes;
+};
+
+struct dpp_set_cursor_attributes_params {
+	struct dpp *dpp;
+	struct dc_cursor_attributes *attributes;
+};
+
 struct set_cursor_position_params {
 	struct dc *dc;
 	struct pipe_ctx *pipe_ctx;
@@ -747,6 +814,12 @@ union block_sequence_params {
 	struct program_triplebuffer_params program_triplebuffer_params;
 	struct set_input_transfer_func_params set_input_transfer_func_params;
 	struct program_gamut_remap_params program_gamut_remap_params;
+	struct hubp_enable_3dlut_fl_params hubp_enable_3dlut_fl_params;
+	struct tg_setup_vertical_interrupt0_params tg_setup_vertical_interrupt0_params;
+	struct update_info_frame_params update_info_frame_params;
+	struct setup_periodic_interrupt_params setup_periodic_interrupt_params;
+	struct dp_trace_source_sequence_params dp_trace_source_sequence_params;
+	struct set_dmdata_attributes_params set_dmdata_attributes_params;
 	struct program_manual_trigger_params program_manual_trigger_params;
 	struct send_dmcub_cmd_params send_dmcub_cmd_params;
 	struct setup_dpp_params setup_dpp_params;
@@ -855,7 +928,14 @@ union block_sequence_params {
 	struct dpp_set_scaler_params dpp_set_scaler_params;
 	struct hubp_mem_program_viewport_params hubp_mem_program_viewport_params;
 	struct abort_cursor_offload_update_params abort_cursor_offload_update_params;
+	struct cursor_lock_params cursor_lock_params;
+	struct begin_cursor_offload_update_params begin_cursor_offload_update_params;
+	struct commit_cursor_offload_update_params commit_cursor_offload_update_params;
+	struct update_cursor_offload_pipe_params update_cursor_offload_pipe_params;
+	struct send_cursor_info_to_dmu_params send_cursor_info_to_dmu_params;
 	struct set_cursor_attribute_params set_cursor_attribute_params;
+	struct hubp_set_cursor_attributes_params hubp_set_cursor_attributes_params;
+	struct dpp_set_cursor_attributes_params dpp_set_cursor_attributes_params;
 	struct set_cursor_position_params set_cursor_position_params;
 	struct set_cursor_sdr_white_level_params set_cursor_sdr_white_level_params;
 	struct program_output_csc_params program_output_csc_params;
@@ -871,6 +951,12 @@ enum block_sequence_func {
 	HUBP_UPDATE_PLANE_ADDR,
 	DPP_SET_INPUT_TRANSFER_FUNC,
 	DPP_PROGRAM_GAMUT_REMAP,
+	HUBP_ENABLE_3DLUT_FL,
+	OTG_SETUP_VERTICAL_INTERRUPT,
+	HWSS_SETUP_PERIODIC_INTERRUPT,
+	HWSS_UPDATE_INFO_FRAME,
+	DP_TRACE_SOURCE_SEQUENCE,
+	HUBP_SET_DMDATA_ATTRIBUTES,
 	OPTC_PROGRAM_MANUAL_TRIGGER,
 	DMUB_SEND_DMCUB_CMD,
 	DPP_SETUP_DPP,
@@ -975,7 +1061,14 @@ enum block_sequence_func {
 	DPP_SET_SCALER,
 	HUBP_MEM_PROGRAM_VIEWPORT,
 	ABORT_CURSOR_OFFLOAD_UPDATE,
+	HWSS_CURSOR_LOCK,
+	HWSS_BEGIN_CURSOR_OFFLOAD_UPDATE,
+	HWSS_COMMIT_CURSOR_OFFLOAD_UPDATE,
+	HWSS_UPDATE_CURSOR_OFFLOAD_PIPE,
+	DC_SEND_CURSOR_INFO_TO_DMU,
 	SET_CURSOR_ATTRIBUTE,
+	HUBP_SET_CURSOR_ATTRIBUTES,
+	DPP_SET_CURSOR_ATTRIBUTES,
 	SET_CURSOR_POSITION,
 	SET_CURSOR_SDR_WHITE_LEVEL,
 	PROGRAM_OUTPUT_CSC,
@@ -1463,6 +1556,18 @@ void hwss_tg_wait_for_state(union block_sequence_params *params);
 
 void hwss_tg_set_vtg_params(union block_sequence_params *params);
 
+void hwss_hubp_enable_3dlut_fl(union block_sequence_params *params);
+
+void hwss_update_info_frame(struct dc *dc, union block_sequence_params *params);
+
+void hwss_setup_periodic_interrupt(struct dc *dc, union block_sequence_params *params);
+
+void hwss_dp_trace_source_sequence(union block_sequence_params *params);
+
+void hwss_set_dmdata_attributes(union block_sequence_params *params);
+
+void hwss_tg_setup_vertical_interrupt0(union block_sequence_params *params);
+
 void hwss_tg_setup_vertical_interrupt2(union block_sequence_params *params);
 
 void hwss_dpp_set_hdr_multiplier(union block_sequence_params *params);
@@ -1603,12 +1708,28 @@ void hwss_hubp_mem_program_viewport(union block_sequence_params *params);
 
 void hwss_abort_cursor_offload_update(union block_sequence_params *params);
 
+void hwss_cursor_lock(union block_sequence_params *params);
+
+void hwss_begin_cursor_offload_update(union block_sequence_params *params);
+
+void hwss_commit_cursor_offload_update(union block_sequence_params *params);
+
+void hwss_update_cursor_offload_pipe(union block_sequence_params *params);
+
+void hwss_send_cursor_info_to_dmu(union block_sequence_params *params);
+
 void hwss_set_cursor_attribute(union block_sequence_params *params);
 
+void hwss_hubp_set_cursor_attributes(union block_sequence_params *params);
+
+void hwss_dpp_set_cursor_attributes(union block_sequence_params *params);
+
 void hwss_set_cursor_position(union block_sequence_params *params);
 
 void hwss_set_cursor_sdr_white_level(union block_sequence_params *params);
 
+void hwss_program_gamut_remap(union block_sequence_params *params);
+
 void hwss_program_output_csc(union block_sequence_params *params);
 
 void hwss_hubp_set_legacy_tiling_compat_level(union block_sequence_params *params);
@@ -1695,6 +1816,9 @@ void hwss_add_tg_wait_for_state(struct block_sequence_state *seq_state,
 void hwss_add_tg_set_vtg_params(struct block_sequence_state *seq_state,
 		struct timing_generator *tg, struct dc_crtc_timing *dc_crtc_timing, bool program_fp2);
 
+void hwss_add_vertical_interrupt_setup(struct block_sequence_state *seq_state,
+		struct timing_generator *tg, uint32_t start_line, uint32_t end_line);
+
 void hwss_add_tg_setup_vertical_interrupt2(struct block_sequence_state *seq_state,
 		struct timing_generator *tg, int start_line);
 
@@ -2012,6 +2136,14 @@ void hwss_add_set_cursor_attribute(struct block_sequence_state *seq_state,
 		struct dc *dc,
 		struct pipe_ctx *pipe_ctx);
 
+void hwss_add_hubp_set_cursor_attributes(struct block_sequence_state *seq_state,
+		struct hubp *hubp,
+		const struct dc_cursor_attributes *attributes);
+
+void hwss_add_dpp_set_cursor_attributes(struct block_sequence_state *seq_state,
+		struct dpp *dpp,
+		struct dc_cursor_attributes *attributes);
+
 void hwss_add_set_cursor_position(struct block_sequence_state *seq_state,
 		struct dc *dc,
 		struct pipe_ctx *pipe_ctx);
@@ -2056,4 +2188,10 @@ void hwss_add_opp_program_left_edge_extra_pixel(struct block_sequence_state *seq
 		enum dc_pixel_encoding pixel_encoding,
 		bool is_otg_master);
 
+void hwss_add_hubp_enable_3dlut_fl(struct block_sequence_state *seq_state,
+		struct hubp *hubp);
+
+void hwss_add_set_dmdata_attributes(struct block_sequence_state *seq_state,
+		struct hubp *hubp, struct dc_dmdata_attributes *attr);
+
 #endif /* __DC_HW_SEQUENCER_H__ */
diff --git a/drivers/gpu/drm/amd/display/dc/inc/bw_fixed.h b/drivers/gpu/drm/amd/display/dc/inc/bw_fixed.h
index d1656c9d50df..d567d4bd585d 100644
--- a/drivers/gpu/drm/amd/display/dc/inc/bw_fixed.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/bw_fixed.h
@@ -79,7 +79,7 @@ static inline struct bw_fixed bw_int_to_fixed(int64_t value)
 
 static inline int32_t bw_fixed_to_int(struct bw_fixed value)
 {
-	return BW_FIXED_GET_INTEGER_PART(value.value);
+	return (int32_t)BW_FIXED_GET_INTEGER_PART(value.value);
 }
 
 struct bw_fixed bw_frc_to_fixed(int64_t num, int64_t denum);
diff --git a/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c b/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
index 015f3659cf77..8958d286dde1 100644
--- a/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
+++ b/drivers/gpu/drm/amd/display/dc/irq/dce110/irq_service_dce110.c
@@ -210,7 +210,7 @@ bool dce110_vblank_set(struct irq_service *irq_service,
 			dc_interrupt_to_irq_source(irq_service->ctx->dc,
 						   info->src_id,
 						   info->ext_id);
-	uint8_t pipe_offset = dal_irq_src - IRQ_TYPE_VBLANK;
+	unsigned int pipe_offset = dal_irq_src - IRQ_TYPE_VBLANK;
 
 	struct timing_generator *tg;
 
diff --git a/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c b/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c
index 060460abc377..ae6ed3a52d53 100644
--- a/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c
+++ b/drivers/gpu/drm/amd/display/dc/link/accessories/link_dp_cts.c
@@ -199,7 +199,6 @@ static void dp_test_get_audio_test_data(struct dc_link *link, bool disable_video
 	unsigned int channel_count;
 	unsigned int channel = 0;
 	unsigned int modes = 0;
-	unsigned int sampling_rate_in_hz = 0;
 
 	// get audio test mode and test pattern parameters
 	core_link_read_dpcd(
@@ -232,38 +231,10 @@ static void dp_test_get_audio_test_data(struct dc_link *link, bool disable_video
 		}
 	}
 
-	// translate sampling rate
-	switch (dpcd_test_mode.bits.sampling_rate) {
-	case AUDIO_SAMPLING_RATE_32KHZ:
-		sampling_rate_in_hz = 32000;
-		break;
-	case AUDIO_SAMPLING_RATE_44_1KHZ:
-		sampling_rate_in_hz = 44100;
-		break;
-	case AUDIO_SAMPLING_RATE_48KHZ:
-		sampling_rate_in_hz = 48000;
-		break;
-	case AUDIO_SAMPLING_RATE_88_2KHZ:
-		sampling_rate_in_hz = 88200;
-		break;
-	case AUDIO_SAMPLING_RATE_96KHZ:
-		sampling_rate_in_hz = 96000;
-		break;
-	case AUDIO_SAMPLING_RATE_176_4KHZ:
-		sampling_rate_in_hz = 176400;
-		break;
-	case AUDIO_SAMPLING_RATE_192KHZ:
-		sampling_rate_in_hz = 192000;
-		break;
-	default:
-		sampling_rate_in_hz = 0;
-		break;
-	}
-
 	link->audio_test_data.flags.test_requested = 1;
 	link->audio_test_data.flags.disable_video = disable_video;
-	link->audio_test_data.sampling_rate = sampling_rate_in_hz;
-	link->audio_test_data.channel_count = channel_count;
+	link->audio_test_data.sampling_rate = (uint8_t)dpcd_test_mode.bits.sampling_rate;
+	link->audio_test_data.channel_count = (uint8_t)channel_count;
 	link->audio_test_data.pattern_type = test_pattern;
 
 	if (test_pattern == DP_TEST_PATTERN_AUDIO_SAWTOOTH) {
@@ -885,7 +856,7 @@ bool dp_set_test_pattern(
 				struct dmub_hw_lock_inst_flags inst_flags = { 0 };
 
 				hw_locks.bits.lock_dig = 1;
-				inst_flags.dig_inst = pipe_ctx->stream_res.tg->inst;
+				inst_flags.dig_inst = (uint8_t)pipe_ctx->stream_res.tg->inst;
 
 				dmub_hw_lock_mgr_cmd(link->ctx->dmub_srv,
 							true,
@@ -933,7 +904,7 @@ bool dp_set_test_pattern(
 				struct dmub_hw_lock_inst_flags inst_flags = { 0 };
 
 				hw_locks.bits.lock_dig = 1;
-				inst_flags.dig_inst = pipe_ctx->stream_res.tg->inst;
+				inst_flags.dig_inst = (uint8_t)pipe_ctx->stream_res.tg->inst;
 
 				dmub_hw_lock_mgr_cmd(link->ctx->dmub_srv,
 							false,
diff --git a/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c b/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c
index dbbedeeed298..04df75114dd5 100644
--- a/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/link/hwss/link_hwss_hpo_dp.c
@@ -63,7 +63,7 @@ void set_hpo_dp_hblank_min_symbol_width(struct pipe_ctx *pipe_ctx,
 		time_slot_in_ms = dc_fixpt_from_fraction(32 * 4, link_bw_in_kbps);
 		mtp_cnt_per_h_blank = dc_fixpt_div(h_blank_in_ms,
 				dc_fixpt_mul_int(time_slot_in_ms, 64));
-		hblank_min_symbol_width = dc_fixpt_floor(
+		hblank_min_symbol_width = (uint16_t)dc_fixpt_floor(
 				dc_fixpt_mul(mtp_cnt_per_h_blank, throttled_vcp_size));
 	}
 
@@ -98,7 +98,7 @@ void setup_hpo_dp_stream_attribute(struct pipe_ctx *pipe_ctx)
 			&stream->timing,
 			stream->output_color_space,
 			stream->use_vsc_sdp_for_colorimetry,
-			stream->timing.flags.DSC,
+			(stream->timing.flags.DSC != 0),
 			false);
 	link->dc->link_srv->dp_trace_source_sequence(link,
 			DPCD_SOURCE_SEQ_AFTER_DP_STREAM_ATTR);
diff --git a/drivers/gpu/drm/amd/display/dc/link/link_detection.c b/drivers/gpu/drm/amd/display/dc/link/link_detection.c
index 794dd6a95918..7924fe4ab3a5 100644
--- a/drivers/gpu/drm/amd/display/dc/link/link_detection.c
+++ b/drivers/gpu/drm/amd/display/dc/link/link_detection.c
@@ -290,12 +290,12 @@ static bool i2c_read(
 	struct i2c_payload payloads[2] = {
 		{
 		.write = true,
-		.address = address,
+		.address = (uint8_t)address,
 		.length = 1,
 		.data = &offs_data },
 		{
 		.write = false,
-		.address = address,
+		.address = (uint8_t)address,
 		.length = len,
 		.data = buffer } };
 
diff --git a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
index e12c25896364..e7d3f9bd8aa5 100644
--- a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
+++ b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
@@ -546,24 +546,24 @@ static void update_psp_stream_config(struct pipe_ctx *pipe_ctx, bool dpms_off)
 	config.dig_fe = (uint8_t) pipe_ctx->stream_res.stream_enc->stream_enc_inst;
 
 	/* stream encoder index */
-	config.stream_enc_idx = pipe_ctx->stream_res.stream_enc->id - ENGINE_ID_DIGA;
+	config.stream_enc_idx = (uint8_t)(pipe_ctx->stream_res.stream_enc->id - ENGINE_ID_DIGA);
 	if (dp_is_128b_132b_signal(pipe_ctx))
 		config.stream_enc_idx =
-				pipe_ctx->stream_res.hpo_dp_stream_enc->id - ENGINE_ID_HPO_DP_0;
+				(uint8_t)(pipe_ctx->stream_res.hpo_dp_stream_enc->id - ENGINE_ID_HPO_DP_0);
 
 	/* dig back end */
 	config.dig_be = pipe_ctx->stream->link->link_enc_hw_inst;
 
 	/* link encoder index */
-	config.link_enc_idx = link_enc->transmitter - TRANSMITTER_UNIPHY_A;
+	config.link_enc_idx = (uint8_t)(link_enc->transmitter - TRANSMITTER_UNIPHY_A);
 	if (dp_is_128b_132b_signal(pipe_ctx))
-		config.link_enc_idx = pipe_ctx->link_res.hpo_dp_link_enc->inst;
+		config.link_enc_idx = (uint8_t)pipe_ctx->link_res.hpo_dp_link_enc->inst;
 
 	/* dio output index is dpia index for DPIA endpoint & dcio index by default */
 	if (pipe_ctx->stream->link->ep_type == DISPLAY_ENDPOINT_USB4_DPIA)
-		config.dio_output_idx = pipe_ctx->stream->link->link_id.enum_id - ENUM_ID_1;
+		config.dio_output_idx = (uint8_t)(pipe_ctx->stream->link->link_id.enum_id - ENUM_ID_1);
 	else
-		config.dio_output_idx = link_enc->transmitter - TRANSMITTER_UNIPHY_A;
+		config.dio_output_idx = (uint8_t)(link_enc->transmitter - TRANSMITTER_UNIPHY_A);
 
 
 	/* phy index */
@@ -1411,7 +1411,7 @@ static bool write_128b_132b_sst_payload_allocation_table(
 
 	if (allocate)	{
 		avg_time_slots_per_mtp = link_calculate_sst_avg_time_slots_per_mtp(stream, link);
-		req_slot_count = dc_fixpt_ceil(avg_time_slots_per_mtp);
+		req_slot_count = (uint8_t)dc_fixpt_ceil(avg_time_slots_per_mtp);
 		/// Validation should filter out modes that exceed link BW
 		ASSERT(req_slot_count <= MAX_MTP_SLOT_COUNT);
 		if (req_slot_count > MAX_MTP_SLOT_COUNT)
@@ -1811,7 +1811,7 @@ static void enable_link_hdmi(struct pipe_ctx *pipe_ctx)
 		write_scdc_data(
 			stream->link->ddc,
 			stream->phy_pix_clk,
-			stream->timing.flags.LTE_340MCSC_SCRAMBLE);
+			(stream->timing.flags.LTE_340MCSC_SCRAMBLE != 0));
 
 	memset(&stream->link->cur_link_settings, 0,
 			sizeof(struct dc_link_settings));
diff --git a/drivers/gpu/drm/amd/display/dc/link/link_factory.c b/drivers/gpu/drm/amd/display/dc/link/link_factory.c
index 7e7682d7dfc8..96a30c29b5e4 100644
--- a/drivers/gpu/drm/amd/display/dc/link/link_factory.c
+++ b/drivers/gpu/drm/amd/display/dc/link/link_factory.c
@@ -516,7 +516,7 @@ static bool construct_phy(struct dc_link *link,
 	       sizeof(struct dc_link_settings));
 
 	link->link_id =
-		bios->funcs->get_connector_id(bios, init_params->connector_index);
+		bios->funcs->get_connector_id(bios, (uint8_t)init_params->connector_index);
 
 	link->ep_type = DISPLAY_ENDPOINT_PHY;
 
@@ -544,7 +544,7 @@ static bool construct_phy(struct dc_link *link,
 
 	if (bios->funcs->get_disp_connector_caps_info) {
 		bios->funcs->get_disp_connector_caps_info(bios, link->link_id, &disp_connect_caps_info);
-		link->is_internal_display = disp_connect_caps_info.INTERNAL_DISPLAY;
+		link->is_internal_display = (disp_connect_caps_info.INTERNAL_DISPLAY != 0);
 		DC_LOG_DC("BIOS object table - is_internal_display: %d", link->is_internal_display);
 	}
 
@@ -895,7 +895,7 @@ static bool construct_dpia(struct dc_link *link,
 	}
 
 	/* Set dpia port index : 0 to number of dpia ports */
-	link->ddc_hw_inst = init_params->connector_index;
+	link->ddc_hw_inst = (uint8_t)init_params->connector_index;
 
 	// Assign Dpia preferred eng_id
 	if (link->dc->res_pool->funcs->get_preferred_eng_id_dpia)
diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c
index a66217e54a09..1bf0903a3cf8 100644
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_ddc.c
@@ -96,7 +96,7 @@ static void i2c_payloads_add(
 	for (pos = 0; pos < len; pos += payload_size) {
 		struct i2c_payload payload = {
 			.write = write,
-			.address = address,
+			.address = (uint8_t)address,
 			.length = DDC_MIN(payload_size, len - pos),
 			.data = data + pos };
 		dal_vector_append(&payloads->payloads, &payload);
@@ -384,8 +384,7 @@ bool link_query_ddc_data(
 		i2c_payloads_add(
 			&payloads, address, read_size, read_buf, false);
 
-		command.number_of_payloads =
-			i2c_payloads_get_count(&payloads);
+		command.number_of_payloads = (uint8_t)i2c_payloads_get_count(&payloads);
 
 		success = dm_helpers_submit_i2c(
 				ddc->ctx,
diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
index 782a45caa13d..01b3d56cdc89 100644
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
@@ -1713,7 +1713,7 @@ enum dc_status dp_retrieve_lttpr_cap(struct dc_link *link)
 		CONN_DATA_DETECT(link, lttpr_dpcd_data, sizeof(lttpr_dpcd_data), "LTTPR Caps: ");
 
 		// Identify closest LTTPR to determine if workarounds required for known embedded LTTPR
-		closest_lttpr_offset = dp_get_closest_lttpr_offset(lttpr_count);
+		closest_lttpr_offset = dp_get_closest_lttpr_offset((uint8_t)lttpr_count);
 
 		core_link_read_dpcd(link, (DP_LTTPR_IEEE_OUI + closest_lttpr_offset),
 				link->dpcd_caps.lttpr_caps.lttpr_ieee_oui, sizeof(link->dpcd_caps.lttpr_caps.lttpr_ieee_oui));
diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia.c
index 766b54631c79..da227889e007 100644
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia.c
@@ -119,7 +119,7 @@ bool dpia_query_hpd_status(struct dc_link *link)
 	/* prepare QUERY_HPD command */
 	cmd.query_hpd.header.type = DMUB_CMD__QUERY_HPD_STATE;
 	cmd.query_hpd.header.payload_bytes = sizeof(cmd.query_hpd.data);
-	cmd.query_hpd.data.instance = link->link_id.enum_id - ENUM_ID_1;
+	cmd.query_hpd.data.instance = (uint8_t)(link->link_id.enum_id - ENUM_ID_1);
 	cmd.query_hpd.data.ch_type = AUX_CHANNEL_DPIA;
 
 	/* Query dpia hpd status from dmub */
diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c
index c958d3f600c8..d79c18c4903a 100644
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_dpia_bw.c
@@ -112,7 +112,7 @@ static int get_estimated_bw(struct dc_link *link)
 	return bw_estimated_bw * (Kbps_TO_Gbps / link->dpia_bw_alloc_config.bw_granularity);
 }
 
-static int get_non_reduced_max_link_rate(struct dc_link *link)
+static uint8_t get_non_reduced_max_link_rate(struct dc_link *link)
 {
 	uint8_t nrd_max_link_rate = 0;
 
@@ -125,7 +125,7 @@ static int get_non_reduced_max_link_rate(struct dc_link *link)
 	return nrd_max_link_rate;
 }
 
-static int get_non_reduced_max_lane_count(struct dc_link *link)
+static uint8_t get_non_reduced_max_lane_count(struct dc_link *link)
 {
 	uint8_t nrd_max_lane_count = 0;
 
@@ -180,7 +180,7 @@ static void dpia_bw_alloc_unplug(struct dc_link *link)
 
 static void link_dpia_send_bw_alloc_request(struct dc_link *link, int req_bw)
 {
-	uint8_t request_reg_val;
+	uint32_t request_reg_val;
 	uint32_t temp, request_bw;
 
 	if (link->dpia_bw_alloc_config.bw_granularity == 0) {
@@ -212,8 +212,8 @@ static void link_dpia_send_bw_alloc_request(struct dc_link *link, int req_bw)
 	link->dpia_bw_alloc_config.allocated_bw = request_bw;
 	DC_LOG_DC("%s:  Link[%d]:  Request BW:  %d", __func__, link->link_index, request_bw);
 
-	core_link_write_dpcd(link, REQUESTED_BW,
-		&request_reg_val,
+	uint8_t requested_bw_dpcd = (uint8_t)request_reg_val;
+	core_link_write_dpcd(link, REQUESTED_BW, &requested_bw_dpcd,
 		sizeof(uint8_t));
 }
 
diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c
index 1860d44f63c1..dd19b912c48c 100644
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_irq_handler.c
@@ -223,7 +223,7 @@ static void handle_hpd_irq_vesa_replay_sink(struct dc_link *link)
 	}
 }
 
-static void handle_hpd_irq_replay_sink(struct dc_link *link, bool *need_re_enable)
+static void handle_hpd_irq_replay_sink(struct dc_link *link, bool *need_re_enable, bool *replay_esd_detection_needed)
 {
 	union dpcd_replay_configuration replay_configuration = {0};
 	union dpcd_replay_configuration replay_sink_status = {0};
@@ -311,6 +311,14 @@ static void handle_hpd_irq_replay_sink(struct dc_link *link, bool *need_re_enabl
 			*need_re_enable = true;
 		}
 	}
+
+	if (!link->replay_settings.replay_allow_active &&
+	    replay_sink_status.bits.SINK_DEVICE_REPLAY_STATUS == 0x7) {
+	    /* If sink device replay status is 0x7 and replay is disabled,
+	     * it means sink is in a bad state and link retraining is needed to recover
+	     */
+	    *replay_esd_detection_needed = true;
+	}
 }
 
 void dp_handle_link_loss(struct dc_link *link)
@@ -469,6 +477,7 @@ bool dp_handle_hpd_rx_irq(struct dc_link *link,
 	enum dc_status result;
 	bool status = false;
 	bool replay_re_enable_needed = false;
+	bool replay_esd_detection_needed = false;
 
 	if (out_link_loss)
 		*out_link_loss = false;
@@ -482,6 +491,7 @@ bool dp_handle_hpd_rx_irq(struct dc_link *link,
 	DC_LOG_HW_HPD_IRQ("%s: Got short pulse HPD on link %d\n",
 		__func__, link->link_index);
 
+	handle_hpd_irq_replay_sink(link, &replay_re_enable_needed, &replay_esd_detection_needed);
 
 	 /* All the "handle_hpd_irq_xxx()" methods
 		 * should be called only after
@@ -528,8 +538,6 @@ bool dp_handle_hpd_rx_irq(struct dc_link *link,
 		/* PSR-related error was detected and handled */
 		return true;
 
-	handle_hpd_irq_replay_sink(link, &replay_re_enable_needed);
-
 	/* If PSR-related error handled, Main link may be off,
 	 * so do not handle as a normal sink status change interrupt.
 	 */
@@ -552,27 +560,30 @@ bool dp_handle_hpd_rx_irq(struct dc_link *link,
 	 * Downstream port status changed,
 	 * then DM should call DC to do the detection.
 	 * NOTE: Now includes eDP link loss detection and retraining
+	 * Link will be retrained if panel is not EDP or
+	 * Replay ESD recovery is needed.
 	 */
-
-	if (dp_parse_link_loss_status(
-			link,
-			&hpd_irq_dpcd_data)) {
-		/* Connectivity log: link loss */
-		CONN_DATA_LINK_LOSS(link,
-					hpd_irq_dpcd_data.raw,
-					sizeof(hpd_irq_dpcd_data),
-					"Status: ");
-
-		if (defer_handling && has_left_work)
-			*has_left_work = true;
-		else
-			dp_handle_link_loss(link);
-
-		status = false;
-		if (out_link_loss)
-			*out_link_loss = true;
-
-		dp_trace_link_loss_increment(link);
+	if (link->connector_signal != SIGNAL_TYPE_EDP || replay_esd_detection_needed) {
+		if (dp_parse_link_loss_status(
+				link,
+				&hpd_irq_dpcd_data)) {
+			/* Connectivity log: link loss */
+			CONN_DATA_LINK_LOSS(link,
+						hpd_irq_dpcd_data.raw,
+						sizeof(hpd_irq_dpcd_data),
+						"Status: ");
+
+			if (defer_handling && has_left_work)
+				*has_left_work = true;
+			else
+				dp_handle_link_loss(link);
+
+			status = false;
+			if (out_link_loss)
+				*out_link_loss = true;
+
+			dp_trace_link_loss_increment(link);
+		}
 	}
 
 	if (link->dpcd_caps.usb4_dp_tun_info.dp_tun_cap.bits.dp_tunneling) {
diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c
index 96afce4ffbfa..72d6e6011a09 100644
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_panel_replay.c
@@ -60,11 +60,10 @@ static void dp_pr_set_static_screen_param(struct dc_link *link)
 		if (dc->current_state->res_ctx.pipe_ctx[i].stream &&
 			dc->current_state->res_ctx.pipe_ctx[i].stream->link == link) {
 			struct dc_stream_state *stream = dc->current_state->res_ctx.pipe_ctx[i].stream;
-			unsigned int vsync_rate_hz = div64_u64(div64_u64(
-											(stream->timing.pix_clk_100hz * (u64)100),
-											stream->timing.v_total),
-											stream->timing.h_total);
-
+			unsigned int vsync_rate_hz = (unsigned int)div64_u64(div64_u64(
+														(stream->timing.pix_clk_100hz * (u64)100),
+														stream->timing.v_total),
+														stream->timing.h_total);
 			params.triggers.cursor_update = true;
 			params.triggers.overlay_update = true;
 			params.triggers.surface_update = true;
@@ -264,7 +263,7 @@ bool dp_pr_enable(struct dc_link *link, bool enable)
 	cmd.pr_enable.header.type = DMUB_CMD__PR;
 	cmd.pr_enable.header.sub_type = DMUB_CMD__PR_ENABLE;
 	cmd.pr_enable.header.payload_bytes = sizeof(struct dmub_cmd_pr_enable_data);
-	cmd.pr_enable.data.panel_inst = panel_inst;
+	cmd.pr_enable.data.panel_inst = (uint8_t)panel_inst;
 	cmd.pr_enable.data.enable = enable ? 1 : 0;
 	dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
 
@@ -301,17 +300,17 @@ bool dp_pr_copy_settings(struct dc_link *link, struct replay_context *replay_con
 	cmd.pr_copy_settings.header.type = DMUB_CMD__PR;
 	cmd.pr_copy_settings.header.sub_type = DMUB_CMD__PR_COPY_SETTINGS;
 	cmd.pr_copy_settings.header.payload_bytes = sizeof(struct dmub_cmd_pr_copy_settings_data);
-	cmd.pr_copy_settings.data.panel_inst = panel_inst;
+	cmd.pr_copy_settings.data.panel_inst = (uint8_t)panel_inst;
 	// HW inst
 	cmd.pr_copy_settings.data.aux_inst = replay_context->aux_inst;
 	cmd.pr_copy_settings.data.digbe_inst = replay_context->digbe_inst;
 	cmd.pr_copy_settings.data.digfe_inst = replay_context->digfe_inst;
 	if (pipe_ctx->plane_res.dpp)
-		cmd.pr_copy_settings.data.dpp_inst = pipe_ctx->plane_res.dpp->inst;
+		cmd.pr_copy_settings.data.dpp_inst = (uint8_t)pipe_ctx->plane_res.dpp->inst;
 	else
 		cmd.pr_copy_settings.data.dpp_inst = 0;
 	if (pipe_ctx->stream_res.tg)
-		cmd.pr_copy_settings.data.otg_inst = pipe_ctx->stream_res.tg->inst;
+		cmd.pr_copy_settings.data.otg_inst = (uint8_t)pipe_ctx->stream_res.tg->inst;
 	else
 		cmd.pr_copy_settings.data.otg_inst = 0;
 
@@ -329,9 +328,9 @@ bool dp_pr_copy_settings(struct dc_link *link, struct replay_context *replay_con
 		link->dpcd_caps.vesa_replay_su_info.pr_su_y_granularity_extended_caps;
 
 	if (pipe_ctx->stream->timing.dsc_cfg.num_slices_v > 0)
-		cmd.pr_copy_settings.data.dsc_slice_height = (pipe_ctx->stream->timing.v_addressable +
+		cmd.pr_copy_settings.data.dsc_slice_height = (uint16_t)((pipe_ctx->stream->timing.v_addressable +
 			pipe_ctx->stream->timing.v_border_top + pipe_ctx->stream->timing.v_border_bottom) /
-			pipe_ctx->stream->timing.dsc_cfg.num_slices_v;
+			pipe_ctx->stream->timing.dsc_cfg.num_slices_v);
 
 	if (dc_is_embedded_signal(link->connector_signal))
 		cmd.pr_copy_settings.data.main_link_activity_option = OPTION_1C;
@@ -358,7 +357,7 @@ bool dp_pr_update_state(struct dc_link *link, struct dmub_cmd_pr_update_state_da
 	cmd.pr_update_state.header.type = DMUB_CMD__PR;
 	cmd.pr_update_state.header.sub_type = DMUB_CMD__PR_UPDATE_STATE;
 	cmd.pr_update_state.header.payload_bytes = sizeof(struct dmub_cmd_pr_update_state_data);
-	cmd.pr_update_state.data.panel_inst = panel_inst;
+	cmd.pr_update_state.data.panel_inst = (uint8_t)panel_inst;
 
 	dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
 	return true;
@@ -379,7 +378,7 @@ bool dp_pr_set_general_cmd(struct dc_link *link, struct dmub_cmd_pr_general_cmd_
 	cmd.pr_general_cmd.header.type = DMUB_CMD__PR;
 	cmd.pr_general_cmd.header.sub_type = DMUB_CMD__PR_GENERAL_CMD;
 	cmd.pr_general_cmd.header.payload_bytes = sizeof(struct dmub_cmd_pr_general_cmd_data);
-	cmd.pr_general_cmd.data.panel_inst = panel_inst;
+	cmd.pr_general_cmd.data.panel_inst = (uint8_t)panel_inst;
 
 	dc_wake_and_execute_dmub_cmd(dc->ctx, &cmd, DM_DMUB_WAIT_TYPE_WAIT);
 	return true;
@@ -397,7 +396,7 @@ bool dp_pr_get_state(const struct dc_link *link, uint64_t *state)
 
 	do {
 		// Send gpint command and wait for ack
-		if (!dc_wake_and_execute_gpint(dc->ctx, DMUB_GPINT__GET_REPLAY_STATE, panel_inst,
+		if (!dc_wake_and_execute_gpint(dc->ctx, DMUB_GPINT__GET_REPLAY_STATE, (uint16_t)panel_inst,
 					       &replay_state, DM_DMUB_WAIT_TYPE_WAIT_WITH_REPLY)) {
 			// Return invalid state when GPINT times out
 			replay_state = PR_STATE_INVALID;
diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c
index 66d0fb1b9b9d..4331e032416f 100644
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_training_8b_10b.c
@@ -132,7 +132,7 @@ void decide_8b_10b_training_settings(
 	 */
 	lt_settings->link_settings.link_spread = link->dp_ss_off ?
 			LINK_SPREAD_DISABLED : LINK_SPREAD_05_DOWNSPREAD_30KHZ;
-	lt_settings->eq_pattern_time = get_eq_training_aux_rd_interval(link, link_setting);
+	lt_settings->eq_pattern_time = (uint16_t)get_eq_training_aux_rd_interval(link, link_setting);
 	lt_settings->pattern_for_cr = decide_cr_training_pattern(link_setting);
 	lt_settings->pattern_for_eq = decide_eq_training_pattern(link, link_res, link_setting);
 	lt_settings->enhanced_framing = 1;
@@ -140,7 +140,7 @@ void decide_8b_10b_training_settings(
 	lt_settings->disallow_per_lane_settings = true;
 	lt_settings->always_match_dpcd_with_hw_lane_settings = true;
 	lt_settings->lttpr_mode = dp_decide_8b_10b_lttpr_mode(link);
-	lt_settings->cr_pattern_time = get_cr_training_aux_rd_interval(link, link_setting, lt_settings->lttpr_mode);
+	lt_settings->cr_pattern_time = (uint16_t)get_cr_training_aux_rd_interval(link, link_setting, lt_settings->lttpr_mode);
 	dp_hw_to_dpcd_lane_settings(lt_settings, lt_settings->hw_lane_settings, lt_settings->dpcd_lane_settings);
 
 	/* Some embedded LTTPRs rely on receiving TPS2 before LT to interop reliably with sensitive VGA dongles
@@ -195,7 +195,7 @@ static void set_link_settings_and_perform_early_tps2_retimer_pre_lt_sequence(str
 	* 6. Begin link training as usual
 	* */
 
-	uint32_t closest_lttpr_address_offset = dp_get_closest_lttpr_offset(lttpr_count);
+	uint32_t closest_lttpr_address_offset = dp_get_closest_lttpr_offset((uint8_t)lttpr_count);
 
 	union dpcd_training_pattern dpcd_pattern = {0};
 
@@ -379,7 +379,7 @@ enum link_training_result perform_8b_10b_channel_equalization_sequence(
 			dpcd_set_lane_settings(link, lt_settings, offset);
 
 		/* 3. wait for receiver to lock-on*/
-		wait_time_microsec = dp_get_eq_aux_rd_interval(link, lt_settings, offset, retries_ch_eq);
+		wait_time_microsec = dp_get_eq_aux_rd_interval(link, lt_settings, offset, (uint8_t)retries_ch_eq);
 
 		dp_wait_for_training_aux_rd_interval(
 				link,
@@ -408,7 +408,7 @@ enum link_training_result perform_8b_10b_channel_equalization_sequence(
 		/* 6. check CHEQ done*/
 		if (dp_is_ch_eq_done(lane_count, dpcd_lane_status) &&
 				dp_is_symbol_locked(lane_count, dpcd_lane_status) &&
-				dp_check_interlane_aligned(dpcd_lane_status_updated, link, retries_ch_eq))
+				dp_check_interlane_aligned(dpcd_lane_status_updated, link, (uint8_t)retries_ch_eq))
 			return LINK_TRAINING_SUCCESS;
 
 		/* 7. update VS/PE/PC2 in lt_settings*/
diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
index 4a2699a374b7..6aa65815af22 100644
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_edp_panel_control.c
@@ -601,12 +601,12 @@ bool edp_set_psr_allow_active(struct dc_link *link, const bool *allow_active,
 		link->psr_settings.psr_power_opt = *power_opts;
 
 		if (psr != NULL && link->psr_settings.psr_feature_enabled && psr->funcs->psr_set_power_opt)
-			psr->funcs->psr_set_power_opt(psr, link->psr_settings.psr_power_opt, panel_inst);
+			psr->funcs->psr_set_power_opt(psr, link->psr_settings.psr_power_opt, (uint8_t)panel_inst);
 	}
 
 	if (psr != NULL && link->psr_settings.psr_feature_enabled &&
 			force_static && psr->funcs->psr_force_static)
-		psr->funcs->psr_force_static(psr, panel_inst);
+		psr->funcs->psr_force_static(psr, (uint8_t)panel_inst);
 
 	/* Enable or Disable PSR */
 	if (allow_active && link->psr_settings.psr_allow_active != *allow_active) {
@@ -615,9 +615,9 @@ bool edp_set_psr_allow_active(struct dc_link *link, const bool *allow_active,
 		if (!link->psr_settings.psr_allow_active)
 			dc_z10_restore(dc);
 
-		if (psr != NULL && link->psr_settings.psr_feature_enabled) {
-			psr->funcs->psr_enable(psr, link->psr_settings.psr_allow_active, wait, panel_inst);
-		} else if ((dmcu != NULL && dmcu->funcs->is_dmcu_initialized(dmcu)) &&
+		if (psr != NULL && link->psr_settings.psr_feature_enabled)
+			psr->funcs->psr_enable(psr, link->psr_settings.psr_allow_active, wait, (uint8_t)panel_inst);
+		else if ((dmcu != NULL && dmcu->funcs->is_dmcu_initialized(dmcu)) &&
 			link->psr_settings.psr_feature_enabled)
 			dmcu->funcs->set_psr_enable(dmcu, link->psr_settings.psr_allow_active, wait);
 		else
@@ -637,7 +637,7 @@ bool edp_get_psr_state(const struct dc_link *link, enum dc_psr_state *state)
 		return false;
 
 	if (psr != NULL && link->psr_settings.psr_feature_enabled)
-		psr->funcs->psr_get_state(psr, state, panel_inst);
+		psr->funcs->psr_get_state(psr, state, (uint8_t)panel_inst);
 	else if (dmcu != NULL && link->psr_settings.psr_feature_enabled)
 		dmcu->funcs->get_psr_state(dmcu, state);
 
@@ -811,7 +811,7 @@ bool edp_setup_psr(struct dc_link *link,
 	psr_context->smuPhyId = transmitter_to_phy_id(link);
 
 	psr_context->crtcTimingVerticalTotal = stream->timing.v_total;
-	psr_context->vsync_rate_hz = div64_u64(div64_u64((stream->
+	psr_context->vsync_rate_hz = (unsigned int)div64_u64(div64_u64((stream->
 					timing.pix_clk_100hz * (u64)100),
 					stream->timing.v_total),
 					stream->timing.h_total);
@@ -885,7 +885,7 @@ bool edp_setup_psr(struct dc_link *link,
 
 	if (psr) {
 		link->psr_settings.psr_feature_enabled = psr->funcs->psr_copy_settings(psr,
-			link, psr_context, panel_inst);
+			link, psr_context, (uint8_t)panel_inst);
 		link->psr_settings.psr_power_opt = 0;
 		link->psr_settings.psr_allow_active = 0;
 	} else {
@@ -913,7 +913,7 @@ void edp_get_psr_residency(const struct dc_link *link, uint32_t *residency, enum
 
 	// PSR residency measurements only supported on DMCUB
 	if (psr != NULL && link->psr_settings.psr_feature_enabled)
-		psr->funcs->psr_get_residency(psr, residency, panel_inst, mode);
+		psr->funcs->psr_get_residency(psr, residency, (uint8_t)panel_inst, mode);
 	else
 		*residency = 0;
 }
@@ -947,7 +947,7 @@ bool edp_set_replay_allow_active(struct dc_link *link, const bool *allow_active,
 	if (power_opts && link->replay_settings.replay_power_opt_active != *power_opts) {
 		if (replay != NULL && link->replay_settings.replay_feature_enabled &&
 			replay->funcs->replay_set_power_opt) {
-			replay->funcs->replay_set_power_opt(replay, *power_opts, panel_inst);
+			replay->funcs->replay_set_power_opt(replay, *power_opts, (uint8_t)panel_inst);
 			link->replay_settings.replay_power_opt_active = *power_opts;
 		}
 	}
@@ -957,7 +957,7 @@ bool edp_set_replay_allow_active(struct dc_link *link, const bool *allow_active,
 		// TODO: Handle mux change case if force_static is set
 		// If force_static is set, just change the replay_allow_active state directly
 		if (replay != NULL && link->replay_settings.replay_feature_enabled)
-			replay->funcs->replay_enable(replay, *allow_active, wait, panel_inst);
+			replay->funcs->replay_enable(replay, *allow_active, wait, (uint8_t)panel_inst);
 		link->replay_settings.replay_allow_active = *allow_active;
 	}
 
@@ -975,7 +975,7 @@ bool edp_get_replay_state(const struct dc_link *link, uint64_t *state)
 		return false;
 
 	if (replay != NULL && link->replay_settings.replay_feature_enabled)
-		replay->funcs->replay_get_state(replay, &pr_state, panel_inst);
+		replay->funcs->replay_get_state(replay, &pr_state, (uint8_t)panel_inst);
 	*state = pr_state;
 
 	return true;
@@ -1046,12 +1046,11 @@ bool edp_setup_freesync_replay(struct dc_link *link, const struct dc_stream_stat
 	replay_context.os_request_force_ffu = link->replay_settings.config.os_request_force_ffu;
 
 	link->replay_settings.replay_feature_enabled =
-			replay->funcs->replay_copy_settings(replay, link, &replay_context, panel_inst);
+			replay->funcs->replay_copy_settings(replay, link, &replay_context, (uint8_t)panel_inst);
 	if (link->replay_settings.replay_feature_enabled) {
 
 		replay_config.bits.FREESYNC_PANEL_REPLAY_MODE = 1;
-		replay_config.bits.TIMING_DESYNC_ERROR_VERIFICATION =
-			link->replay_settings.config.replay_timing_sync_supported;
+		replay_config.bits.TIMING_DESYNC_ERROR_VERIFICATION = 0;
 		replay_config.bits.STATE_TRANSITION_ERROR_DETECTION = 1;
 		dm_helpers_dp_write_dpcd(link->ctx, link,
 			DP_SINK_PR_ENABLE_AND_CONFIGURATION,
@@ -1096,7 +1095,7 @@ bool edp_send_replay_cmd(struct dc_link *link,
 		return false;
 
 	if (dp_pr_get_panel_inst(dc, link, &panel_inst))
-		cmd_data->panel_inst = panel_inst;
+		cmd_data->panel_inst = (uint8_t)panel_inst;
 	else {
 		DC_LOG_DC("%s(): get edp panel inst fail ", __func__);
 		return false;
@@ -1121,7 +1120,7 @@ bool edp_set_coasting_vtotal(struct dc_link *link, uint32_t coasting_vtotal, uin
 
 	if (coasting_vtotal && (link->replay_settings.coasting_vtotal != coasting_vtotal ||
 		link->replay_settings.frame_skip_number != frame_skip_number)) {
-		replay->funcs->replay_set_coasting_vtotal(replay, coasting_vtotal, panel_inst, frame_skip_number);
+		replay->funcs->replay_set_coasting_vtotal(replay, coasting_vtotal, (uint8_t)panel_inst, frame_skip_number);
 		link->replay_settings.coasting_vtotal = coasting_vtotal;
 		link->replay_settings.frame_skip_number = frame_skip_number;
 	}
@@ -1143,7 +1142,7 @@ bool edp_replay_residency(const struct dc_link *link,
 		return false;
 
 	if (replay != NULL && link->replay_settings.replay_feature_enabled)
-		replay->funcs->replay_residency(replay, panel_inst, residency, is_start, mode);
+		replay->funcs->replay_residency(replay, (uint8_t)panel_inst, residency, is_start, mode);
 	else
 		*residency = 0;
 
@@ -1168,7 +1167,7 @@ bool edp_set_replay_power_opt_and_coasting_vtotal(struct dc_link *link,
 		if (link->replay_settings.replay_feature_enabled &&
 			replay->funcs->replay_set_power_opt_and_coasting_vtotal) {
 			replay->funcs->replay_set_power_opt_and_coasting_vtotal(replay,
-				*power_opts, panel_inst, coasting_vtotal, frame_skip_number);
+				*power_opts, (uint8_t)panel_inst, coasting_vtotal, frame_skip_number);
 			link->replay_settings.replay_power_opt_active = *power_opts;
 			link->replay_settings.coasting_vtotal = coasting_vtotal;
 			link->replay_settings.frame_skip_number = frame_skip_number;
@@ -1252,10 +1251,10 @@ static void edp_set_assr_enable(const struct dc *pDC, struct dc_link *link,
 
 	memset(&cmd, 0, sizeof(cmd));
 
-	link_enc_index = link->link_enc->transmitter - TRANSMITTER_UNIPHY_A;
+	link_enc_index = (uint8_t)(link->link_enc->transmitter - TRANSMITTER_UNIPHY_A);
 
 	if (link_res->hpo_dp_link_enc) {
-		link_enc_index = link_res->hpo_dp_link_enc->inst;
+		link_enc_index = (uint8_t)link_res->hpo_dp_link_enc->inst;
 		use_hpo_dp_link_enc = true;
 	}
 
diff --git a/drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.c b/drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.c
index 2a422e223bf2..2e0f07ec04e4 100644
--- a/drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/dcn20_mmhubbub.c
@@ -40,8 +40,8 @@
 #define FN(reg_name, field_name) \
 	mcif_wb20->mcif_wb_shift->field_name, mcif_wb20->mcif_wb_mask->field_name
 
-#define MCIF_ADDR(addr) (((unsigned long long)addr & 0xffffffffff) + 0xFE) >> 8
-#define MCIF_ADDR_HIGH(addr) (unsigned long long)addr >> 40
+#define MCIF_ADDR(addr) ((uint32_t)((((unsigned long long)(addr) & 0xffffffffffULL) + 0xFEULL) >> 8))
+#define MCIF_ADDR_HIGH(addr) ((uint32_t)(((unsigned long long)(addr)) >> 40))
 
 /* wbif programming guide:
  * 1. set up wbif parameter:
diff --git a/drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.c b/drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.c
index c3b089ba511a..6b6f80a3bfd5 100644
--- a/drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.c
+++ b/drivers/gpu/drm/amd/display/dc/mmhubbub/dcn32/dcn32_mmhubbub.c
@@ -40,8 +40,8 @@
 #define FN(reg_name, field_name) \
 	mcif_wb30->mcif_wb_shift->field_name, mcif_wb30->mcif_wb_mask->field_name
 
-#define MCIF_ADDR(addr) (((unsigned long long)addr & 0xffffffffff) + 0xFE) >> 8
-#define MCIF_ADDR_HIGH(addr) (unsigned long long)addr >> 40
+#define MCIF_ADDR(addr) ((uint32_t)((((unsigned long long)(addr) & 0xffffffffffULL) + 0xFEULL) >> 8))
+#define MCIF_ADDR_HIGH(addr) ((uint32_t)(((unsigned long long)(addr)) >> 40))
 
 /* wbif programming guide:
  * 1. set up wbif parameter:
diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c
index 39ce4d4a61a1..c558b1d633f3 100644
--- a/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/optc/dcn20/dcn20_optc.c
@@ -305,8 +305,8 @@ static void optc2_align_vblanks(
 	L = div_u64(L, master_h_total);
 	L = div_u64(L, slave_pixel_clock_100Hz);
 	XY = div_u64(L, p);
-	Y = master_v_active - XY - 1;
-	X = div_u64(((XY + 1) * p - L) * master_h_total, p * master_clock_divider);
+	Y = (uint32_t)(master_v_active - XY - 1);
+	X = (uint32_t)div_u64(((XY + 1) * p - L) * master_h_total, p * master_clock_divider);
 
 	/*
 	 * set master OTG to unlock when V/H
diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn42/dcn42_optc.h b/drivers/gpu/drm/amd/display/dc/optc/dcn42/dcn42_optc.h
index fc7192f01b33..8e7d65317e7c 100644
--- a/drivers/gpu/drm/amd/display/dc/optc/dcn42/dcn42_optc.h
+++ b/drivers/gpu/drm/amd/display/dc/optc/dcn42/dcn42_optc.h
@@ -164,7 +164,6 @@
 	SF(GSL_SOURCE_SELECT, GSL0_READY_SOURCE_SEL, mask_sh),\
 	SF(GSL_SOURCE_SELECT, GSL1_READY_SOURCE_SEL, mask_sh),\
 	SF(GSL_SOURCE_SELECT, GSL2_READY_SOURCE_SEL, mask_sh),\
-	SF(OTG0_OTG_GLOBAL_CONTROL2, MANUAL_FLOW_CONTROL_SEL, mask_sh),\
 	SF(OTG0_OTG_GLOBAL_CONTROL2, GLOBAL_UPDATE_LOCK_EN, mask_sh),\
 	SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_START_X, mask_sh),\
 	SF(OTG0_OTG_GSL_WINDOW_X, OTG_GSL_WINDOW_END_X, mask_sh), \
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c
index f83acfe7a15e..8a0b4ef2977d 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dce110/dce110_resource.c
@@ -1150,7 +1150,7 @@ static struct pipe_ctx *dce110_acquire_underlay(
 	/*pipe_ctx->plane_res.ipp = res_ctx->pool->ipps[underlay_idx];*/
 	pipe_ctx->plane_res.xfm = pool->transforms[underlay_idx];
 	pipe_ctx->stream_res.opp = pool->opps[underlay_idx];
-	pipe_ctx->pipe_idx = underlay_idx;
+	pipe_ctx->pipe_idx = (uint8_t)underlay_idx;
 
 	pipe_ctx->stream = stream;
 
@@ -1160,7 +1160,7 @@ static struct pipe_ctx *dce110_acquire_underlay(
 
 		hws->funcs.enable_display_power_gating(
 				dc,
-				pipe_ctx->stream_res.tg->inst,
+				(uint8_t)pipe_ctx->stream_res.tg->inst,
 				dcb, PIPE_GATING_CONTROL_DISABLE);
 
 		/*
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
index 0fdebe63d355..943635c4fbb8 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn10/dcn10_resource.c
@@ -1139,7 +1139,7 @@ static struct pipe_ctx *dcn10_acquire_free_pipe_for_layer(
 	idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx];
 	idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx];
 	idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx];
-	idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst;
+	idle_pipe->plane_res.mpcc_inst = (uint8_t)pool->dpps[idle_pipe->pipe_idx]->inst;
 
 	return idle_pipe;
 }
@@ -1735,7 +1735,7 @@ struct resource_pool *dcn10_create_resource_pool(
 	if (!pool)
 		return NULL;
 
-	if (dcn10_resource_construct(init_data->num_virtual_links, dc, pool))
+	if (dcn10_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool))
 		return &pool->base;
 
 	kfree(pool);
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
index a99829f23965..4bc7777be60e 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn20/dcn20_resource.c
@@ -1523,13 +1523,13 @@ bool dcn20_split_stream_for_odm(
 
 	*next_odm_pipe = *prev_odm_pipe;
 
-	next_odm_pipe->pipe_idx = pipe_idx;
+	next_odm_pipe->pipe_idx = (uint8_t)pipe_idx;
 	next_odm_pipe->plane_res.mi = pool->mis[next_odm_pipe->pipe_idx];
 	next_odm_pipe->plane_res.hubp = pool->hubps[next_odm_pipe->pipe_idx];
 	next_odm_pipe->plane_res.ipp = pool->ipps[next_odm_pipe->pipe_idx];
 	next_odm_pipe->plane_res.xfm = pool->transforms[next_odm_pipe->pipe_idx];
 	next_odm_pipe->plane_res.dpp = pool->dpps[next_odm_pipe->pipe_idx];
-	next_odm_pipe->plane_res.mpcc_inst = pool->dpps[next_odm_pipe->pipe_idx]->inst;
+	next_odm_pipe->plane_res.mpcc_inst = (uint8_t)pool->dpps[next_odm_pipe->pipe_idx]->inst;
 	next_odm_pipe->stream_res.dsc = NULL;
 	if (prev_odm_pipe->next_odm_pipe && prev_odm_pipe->next_odm_pipe != next_odm_pipe) {
 		next_odm_pipe->next_odm_pipe = prev_odm_pipe->next_odm_pipe;
@@ -1580,13 +1580,13 @@ void dcn20_split_stream_for_mpc(
 	*secondary_pipe = *primary_pipe;
 	secondary_pipe->bottom_pipe = sec_bot_pipe;
 
-	secondary_pipe->pipe_idx = pipe_idx;
+	secondary_pipe->pipe_idx = (uint8_t)pipe_idx;
 	secondary_pipe->plane_res.mi = pool->mis[secondary_pipe->pipe_idx];
 	secondary_pipe->plane_res.hubp = pool->hubps[secondary_pipe->pipe_idx];
 	secondary_pipe->plane_res.ipp = pool->ipps[secondary_pipe->pipe_idx];
 	secondary_pipe->plane_res.xfm = pool->transforms[secondary_pipe->pipe_idx];
 	secondary_pipe->plane_res.dpp = pool->dpps[secondary_pipe->pipe_idx];
-	secondary_pipe->plane_res.mpcc_inst = pool->dpps[secondary_pipe->pipe_idx]->inst;
+	secondary_pipe->plane_res.mpcc_inst = (uint8_t)pool->dpps[secondary_pipe->pipe_idx]->inst;
 	secondary_pipe->stream_res.dsc = NULL;
 	if (primary_pipe->bottom_pipe && primary_pipe->bottom_pipe != secondary_pipe) {
 		ASSERT(!secondary_pipe->bottom_pipe);
@@ -1736,7 +1736,7 @@ struct pipe_ctx *dcn20_find_secondary_pipe(struct dc *dc,
 			preferred_pipe_idx = dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].next_odm_pipe->pipe_idx;
 			if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
 				secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
-				secondary_pipe->pipe_idx = preferred_pipe_idx;
+				secondary_pipe->pipe_idx = (uint8_t)preferred_pipe_idx;
 			}
 		}
 		if (secondary_pipe == NULL &&
@@ -1744,7 +1744,7 @@ struct pipe_ctx *dcn20_find_secondary_pipe(struct dc *dc,
 			preferred_pipe_idx = dc->current_state->res_ctx.pipe_ctx[primary_pipe->pipe_idx].bottom_pipe->pipe_idx;
 			if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
 				secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
-				secondary_pipe->pipe_idx = preferred_pipe_idx;
+				secondary_pipe->pipe_idx = (uint8_t)preferred_pipe_idx;
 			}
 		}
 
@@ -1762,7 +1762,7 @@ struct pipe_ctx *dcn20_find_secondary_pipe(struct dc *dc,
 
 					if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
 						secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
-						secondary_pipe->pipe_idx = preferred_pipe_idx;
+						secondary_pipe->pipe_idx = (uint8_t)preferred_pipe_idx;
 						break;
 					}
 				}
@@ -1783,7 +1783,7 @@ struct pipe_ctx *dcn20_find_secondary_pipe(struct dc *dc,
 
 				if (res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) {
 					secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
-					secondary_pipe->pipe_idx = preferred_pipe_idx;
+					secondary_pipe->pipe_idx = (uint8_t)preferred_pipe_idx;
 					break;
 				}
 			}
@@ -2216,7 +2216,7 @@ struct pipe_ctx *dcn20_acquire_free_pipe_for_layer(
 	sec_dpp_pipe->plane_res.hubp = pool->hubps[sec_dpp_pipe->pipe_idx];
 	sec_dpp_pipe->plane_res.ipp = pool->ipps[sec_dpp_pipe->pipe_idx];
 	sec_dpp_pipe->plane_res.dpp = pool->dpps[sec_dpp_pipe->pipe_idx];
-	sec_dpp_pipe->plane_res.mpcc_inst = pool->dpps[sec_dpp_pipe->pipe_idx]->inst;
+	sec_dpp_pipe->plane_res.mpcc_inst = (uint8_t)pool->dpps[sec_dpp_pipe->pipe_idx]->inst;
 
 	return sec_dpp_pipe;
 }
@@ -2622,7 +2622,7 @@ static bool dcn20_resource_construct(
 		ranges.num_reader_wm_sets = 0;
 
 		if (loaded_bb->num_states == 1) {
-			ranges.reader_wm_sets[0].wm_inst = i;
+			ranges.reader_wm_sets[0].wm_inst = (uint8_t)i;
 			ranges.reader_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
 			ranges.reader_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
 			ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
@@ -2631,7 +2631,7 @@ static bool dcn20_resource_construct(
 			ranges.num_reader_wm_sets = 1;
 		} else if (loaded_bb->num_states > 1) {
 			for (i = 0; i < 4 && i < loaded_bb->num_states; i++) {
-				ranges.reader_wm_sets[i].wm_inst = i;
+				ranges.reader_wm_sets[i].wm_inst = (uint8_t)i;
 				ranges.reader_wm_sets[i].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
 				ranges.reader_wm_sets[i].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
 				DC_FP_START();
@@ -2829,7 +2829,7 @@ struct resource_pool *dcn20_create_resource_pool(
 	if (!pool)
 		return NULL;
 
-	if (dcn20_resource_construct(init_data->num_virtual_links, dc, pool))
+	if (dcn20_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool))
 		return &pool->base;
 
 	BREAK_TO_DEBUGGER();
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
index 84f6d9dc443f..9001423da4f8 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn21/dcn21_resource.c
@@ -1757,7 +1757,7 @@ struct resource_pool *dcn21_create_resource_pool(
 	if (!pool)
 		return NULL;
 
-	if (dcn21_resource_construct(init_data->num_virtual_links, dc, pool))
+	if (dcn21_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool))
 		return &pool->base;
 
 	BREAK_TO_DEBUGGER();
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
index 4a864689c44f..7ba02a453f2e 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn30/dcn30_resource.c
@@ -1563,13 +1563,13 @@ static bool dcn30_split_stream_for_mpc_or_odm(
 
 	*sec_pipe = *pri_pipe;
 
-	sec_pipe->pipe_idx = pipe_idx;
+	sec_pipe->pipe_idx = (uint8_t)pipe_idx;
 	sec_pipe->plane_res.mi = pool->mis[pipe_idx];
 	sec_pipe->plane_res.hubp = pool->hubps[pipe_idx];
 	sec_pipe->plane_res.ipp = pool->ipps[pipe_idx];
 	sec_pipe->plane_res.xfm = pool->transforms[pipe_idx];
 	sec_pipe->plane_res.dpp = pool->dpps[pipe_idx];
-	sec_pipe->plane_res.mpcc_inst = pool->dpps[pipe_idx]->inst;
+	sec_pipe->plane_res.mpcc_inst = (uint8_t)pool->dpps[pipe_idx]->inst;
 	sec_pipe->stream_res.dsc = NULL;
 	if (odm) {
 		if (pri_pipe->next_odm_pipe) {
@@ -1623,7 +1623,7 @@ static struct pipe_ctx *dcn30_find_split_pipe(
 
 	if (old_index >= 0 && context->res_ctx.pipe_ctx[old_index].stream == NULL) {
 		pipe = &context->res_ctx.pipe_ctx[old_index];
-		pipe->pipe_idx = old_index;
+		pipe->pipe_idx = (uint8_t)old_index;
 	}
 
 	if (!pipe)
@@ -1632,7 +1632,7 @@ static struct pipe_ctx *dcn30_find_split_pipe(
 					&& dc->current_state->res_ctx.pipe_ctx[i].prev_odm_pipe == NULL) {
 				if (context->res_ctx.pipe_ctx[i].stream == NULL) {
 					pipe = &context->res_ctx.pipe_ctx[i];
-					pipe->pipe_idx = i;
+					pipe->pipe_idx = (uint8_t)i;
 					break;
 				}
 			}
@@ -1647,7 +1647,7 @@ static struct pipe_ctx *dcn30_find_split_pipe(
 		for (i = dc->res_pool->pipe_count - 1; i >= 0; i--) {
 			if (context->res_ctx.pipe_ctx[i].stream == NULL) {
 				pipe = &context->res_ctx.pipe_ctx[i];
-				pipe->pipe_idx = i;
+				pipe->pipe_idx = (uint8_t)i;
 				break;
 			}
 		}
@@ -2379,7 +2379,7 @@ static bool dcn30_resource_construct(
 	dc->caps.color.dpp.ocsc = 0;
 
 	dc->caps.color.mpc.gamut_remap = 1;
-	dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //3
+	dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut;
 	dc->caps.color.mpc.ogam_ram = 1;
 	dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
 	dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
@@ -2669,7 +2669,7 @@ struct resource_pool *dcn30_create_resource_pool(
 	if (!pool)
 		return NULL;
 
-	if (dcn30_resource_construct(init_data->num_virtual_links, dc, pool))
+	if (dcn30_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool))
 		return &pool->base;
 
 	BREAK_TO_DEBUGGER();
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
index a74b150cbe9c..05e59b6255f7 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn301/dcn301_resource.c
@@ -1358,7 +1358,7 @@ static void set_wm_ranges(
 		struct _vcs_dpi_soc_bounding_box_st *loaded_bb)
 {
 	struct pp_smu_wm_range_sets ranges = {0};
-	int i;
+	unsigned int i;
 
 	ranges.num_reader_wm_sets = 0;
 
@@ -1372,7 +1372,7 @@ static void set_wm_ranges(
 		ranges.num_reader_wm_sets = 1;
 	} else if (loaded_bb->num_states > 1) {
 		for (i = 0; i < 4 && i < loaded_bb->num_states; i++) {
-			ranges.reader_wm_sets[i].wm_inst = i;
+			ranges.reader_wm_sets[i].wm_inst = (uint8_t)i;
 			ranges.reader_wm_sets[i].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
 			ranges.reader_wm_sets[i].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
 			DC_FP_START();
@@ -1506,7 +1506,7 @@ static bool dcn301_resource_construct(
 	dc->caps.color.dpp.ocsc = 0;
 
 	dc->caps.color.mpc.gamut_remap = 1;
-	dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2
+	dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut;
 	dc->caps.color.mpc.ogam_ram = 1;
 	dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
 	dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
@@ -1773,7 +1773,7 @@ struct resource_pool *dcn301_create_resource_pool(
 	if (!pool)
 		return NULL;
 
-	if (dcn301_resource_construct(init_data->num_virtual_links, dc, pool))
+	if (dcn301_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool))
 		return &pool->base;
 
 	BREAK_TO_DEBUGGER();
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
index 539c5aa6bffa..652b98aaa196 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn302/dcn302_resource.c
@@ -1300,7 +1300,7 @@ static bool dcn302_resource_construct(
 	dc->caps.color.dpp.ocsc = 0;
 
 	dc->caps.color.mpc.gamut_remap = 1;
-	dc->caps.color.mpc.num_3dluts = pool->res_cap->num_mpc_3dlut; //3
+	dc->caps.color.mpc.num_3dluts = (uint16_t)pool->res_cap->num_mpc_3dlut;
 	dc->caps.color.mpc.ogam_ram = 1;
 	dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
 	dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
@@ -1560,7 +1560,7 @@ struct resource_pool *dcn302_create_resource_pool(const struct dc_init_data *ini
 	if (!pool)
 		return NULL;
 
-	if (dcn302_resource_construct(init_data->num_virtual_links, dc, pool))
+	if (dcn302_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool))
 		return pool;
 
 	BREAK_TO_DEBUGGER();
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c
index 529eccb4ed3b..b22e72a61393 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn303/dcn303_resource.c
@@ -1244,7 +1244,7 @@ static bool dcn303_resource_construct(
 	dc->caps.color.dpp.ocsc = 0;
 
 	dc->caps.color.mpc.gamut_remap = 1;
-	dc->caps.color.mpc.num_3dluts = pool->res_cap->num_mpc_3dlut; //3
+	dc->caps.color.mpc.num_3dluts = (uint16_t)pool->res_cap->num_mpc_3dlut;
 	dc->caps.color.mpc.ogam_ram = 1;
 	dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
 	dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
@@ -1492,7 +1492,7 @@ struct resource_pool *dcn303_create_resource_pool(const struct dc_init_data *ini
 	if (!pool)
 		return NULL;
 
-	if (dcn303_resource_construct(init_data->num_virtual_links, dc, pool))
+	if (dcn303_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool))
 		return pool;
 
 	BREAK_TO_DEBUGGER();
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
index 39944d90ea98..573d2a680115 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn31/dcn31_resource.c
@@ -1987,7 +1987,7 @@ static bool dcn31_resource_construct(
 	dc->caps.color.dpp.ocsc = 0;
 
 	dc->caps.color.mpc.gamut_remap = 1;
-	dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2
+	dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut; //2
 	dc->caps.color.mpc.ogam_ram = 1;
 	dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
 	dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
@@ -2279,7 +2279,7 @@ struct resource_pool *dcn31_create_resource_pool(
 	if (!pool)
 		return NULL;
 
-	if (dcn31_resource_construct(init_data->num_virtual_links, dc, pool))
+	if (dcn31_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool))
 		return &pool->base;
 
 	BREAK_TO_DEBUGGER();
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
index 5acc545bbe7f..7585151ffcde 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn314/dcn314_resource.c
@@ -1914,7 +1914,7 @@ static bool dcn314_resource_construct(
 	dc->caps.color.dpp.ocsc = 0;
 
 	dc->caps.color.mpc.gamut_remap = 1;
-	dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2
+	dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut; //2
 	dc->caps.color.mpc.ogam_ram = 1;
 	dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
 	dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
@@ -2191,7 +2191,7 @@ struct resource_pool *dcn314_create_resource_pool(
 	if (!pool)
 		return NULL;
 
-	if (dcn314_resource_construct(init_data->num_virtual_links, dc, pool))
+	if (dcn314_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool))
 		return &pool->base;
 
 	BREAK_TO_DEBUGGER();
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
index 975e14f3f5fa..7f8e3304af31 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn315/dcn315_resource.c
@@ -1957,7 +1957,7 @@ static bool dcn315_resource_construct(
 	dc->caps.color.dpp.ocsc = 0;
 
 	dc->caps.color.mpc.gamut_remap = 1;
-	dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2
+	dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut;
 	dc->caps.color.mpc.ogam_ram = 1;
 	dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
 	dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
@@ -2220,7 +2220,7 @@ struct resource_pool *dcn315_create_resource_pool(
 	if (!pool)
 		return NULL;
 
-	if (dcn315_resource_construct(init_data->num_virtual_links, dc, pool))
+	if (dcn315_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool))
 		return &pool->base;
 
 	BREAK_TO_DEBUGGER();
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
index 914d91df174c..a6dd1bb9da64 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn316/dcn316_resource.c
@@ -1833,7 +1833,7 @@ static bool dcn316_resource_construct(
 	dc->caps.color.dpp.ocsc = 0;
 
 	dc->caps.color.mpc.gamut_remap = 1;
-	dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2
+	dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut; //2
 	dc->caps.color.mpc.ogam_ram = 1;
 	dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
 	dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
@@ -2086,7 +2086,7 @@ struct resource_pool *dcn316_create_resource_pool(
 	if (!pool)
 		return NULL;
 
-	if (dcn316_resource_construct(init_data->num_virtual_links, dc, pool))
+	if (dcn316_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool))
 		return &pool->base;
 
 	BREAK_TO_DEBUGGER();
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
index 82f81b586986..bf34fdf781dc 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
@@ -2302,7 +2302,7 @@ static bool dcn32_resource_construct(
 	dc->caps.color.dpp.ocsc = 0;
 
 	dc->caps.color.mpc.gamut_remap = 1;
-	dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //4, configurable to be before or after BLND in MPCC
+	dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut; //4, configurable to be before or after BLND in MPCC
 	dc->caps.color.mpc.ogam_ram = 1;
 	dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
 	dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
@@ -2619,7 +2619,7 @@ struct resource_pool *dcn32_create_resource_pool(
 	if (!pool)
 		return NULL;
 
-	if (dcn32_resource_construct(init_data->num_virtual_links, dc, pool))
+	if (dcn32_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool))
 		return &pool->base;
 
 	BREAK_TO_DEBUGGER();
@@ -2747,7 +2747,7 @@ static struct pipe_ctx *find_idle_secondary_pipe_check_mpo(
 		if ((res_ctx->pipe_ctx[preferred_pipe_idx].stream == NULL) &&
 			!(next_odm_mpo_pipe && next_odm_mpo_pipe->pipe_idx == preferred_pipe_idx)) {
 			secondary_pipe = &res_ctx->pipe_ctx[preferred_pipe_idx];
-			secondary_pipe->pipe_idx = preferred_pipe_idx;
+			secondary_pipe->pipe_idx = (uint8_t)preferred_pipe_idx;
 		}
 	}
 
@@ -2760,7 +2760,7 @@ static struct pipe_ctx *find_idle_secondary_pipe_check_mpo(
 			if ((res_ctx->pipe_ctx[i].stream == NULL) &&
 				!(next_odm_mpo_pipe && next_odm_mpo_pipe->pipe_idx == i)) {
 				secondary_pipe = &res_ctx->pipe_ctx[i];
-				secondary_pipe->pipe_idx = i;
+				secondary_pipe->pipe_idx = (uint8_t)i;
 				break;
 			}
 		}
@@ -2794,7 +2794,7 @@ static struct pipe_ctx *dcn32_acquire_idle_pipe_for_head_pipe_in_layer(
 	pipe = &old_ctx->pipe_ctx[head_index];
 	if (pipe->bottom_pipe && res_ctx->pipe_ctx[pipe->bottom_pipe->pipe_idx].stream == NULL) {
 		idle_pipe = &res_ctx->pipe_ctx[pipe->bottom_pipe->pipe_idx];
-		idle_pipe->pipe_idx = pipe->bottom_pipe->pipe_idx;
+		idle_pipe->pipe_idx = (uint8_t)pipe->bottom_pipe->pipe_idx;
 	} else {
 		idle_pipe = find_idle_secondary_pipe_check_mpo(res_ctx, pool, head_pipe);
 		if (!idle_pipe)
@@ -2808,7 +2808,7 @@ static struct pipe_ctx *dcn32_acquire_idle_pipe_for_head_pipe_in_layer(
 	idle_pipe->plane_res.hubp = pool->hubps[idle_pipe->pipe_idx];
 	idle_pipe->plane_res.ipp = pool->ipps[idle_pipe->pipe_idx];
 	idle_pipe->plane_res.dpp = pool->dpps[idle_pipe->pipe_idx];
-	idle_pipe->plane_res.mpcc_inst = pool->dpps[idle_pipe->pipe_idx]->inst;
+	idle_pipe->plane_res.mpcc_inst = (uint8_t)pool->dpps[idle_pipe->pipe_idx]->inst;
 
 	return idle_pipe;
 }
@@ -2859,7 +2859,7 @@ struct pipe_ctx *dcn32_acquire_free_pipe_as_secondary_dpp_pipe(
 					pool, opp_head_pipe);
 	if (free_pipe_idx >= 0) {
 		free_pipe = &new_ctx->res_ctx.pipe_ctx[free_pipe_idx];
-		free_pipe->pipe_idx = free_pipe_idx;
+		free_pipe->pipe_idx = (uint8_t)free_pipe_idx;
 		free_pipe->stream = opp_head_pipe->stream;
 		free_pipe->stream_res.tg = opp_head_pipe->stream_res.tg;
 		free_pipe->stream_res.opp = opp_head_pipe->stream_res.opp;
@@ -2868,7 +2868,7 @@ struct pipe_ctx *dcn32_acquire_free_pipe_as_secondary_dpp_pipe(
 		free_pipe->plane_res.ipp = pool->ipps[free_pipe->pipe_idx];
 		free_pipe->plane_res.dpp = pool->dpps[free_pipe->pipe_idx];
 		free_pipe->plane_res.mpcc_inst =
-				pool->dpps[free_pipe->pipe_idx]->inst;
+				(uint8_t)pool->dpps[free_pipe->pipe_idx]->inst;
 	} else {
 		ASSERT(opp_head_pipe);
 		free_pipe = NULL;
@@ -2890,7 +2890,7 @@ struct pipe_ctx *dcn32_acquire_free_pipe_as_secondary_opp_head(
 
 	if (free_pipe_idx >= 0) {
 		free_pipe = &new_ctx->res_ctx.pipe_ctx[free_pipe_idx];
-		free_pipe->pipe_idx = free_pipe_idx;
+		free_pipe->pipe_idx = (uint8_t)free_pipe_idx;
 		free_pipe->stream = otg_master->stream;
 		free_pipe->stream_res.tg = otg_master->stream_res.tg;
 		free_pipe->stream_res.dsc = NULL;
@@ -2900,7 +2900,7 @@ struct pipe_ctx *dcn32_acquire_free_pipe_as_secondary_opp_head(
 		free_pipe->plane_res.ipp = pool->ipps[free_pipe_idx];
 		free_pipe->plane_res.xfm = pool->transforms[free_pipe_idx];
 		free_pipe->plane_res.dpp = pool->dpps[free_pipe_idx];
-		free_pipe->plane_res.mpcc_inst = pool->dpps[free_pipe_idx]->inst;
+		free_pipe->plane_res.mpcc_inst = (uint8_t)pool->dpps[free_pipe_idx]->inst;
 		free_pipe->dsc_padding_params = otg_master->dsc_padding_params;
 		if (free_pipe->stream->timing.flags.DSC == 1) {
 			dcn20_acquire_dsc(free_pipe->stream->ctx->dc,
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
index 4808c793590f..b2eac83ef02c 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource_helpers.c
@@ -333,7 +333,7 @@ void dcn32_determine_det_override(struct dc *dc,
 				continue;
 
 			if (context->stream_status[i].plane_count > 0)
-				plane_segments = stream_segments / context->stream_status[i].plane_count;
+				plane_segments = (uint8_t)(stream_segments / context->stream_status[i].plane_count);
 			else
 				plane_segments = stream_segments;
 			for (j = 0; j < dc->res_pool->pipe_count; j++) {
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
index c8c81870d50e..5f5720a3953a 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
@@ -1801,7 +1801,7 @@ static bool dcn321_resource_construct(
 	dc->caps.color.dpp.ocsc = 0;
 
 	dc->caps.color.mpc.gamut_remap = 1;
-	dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //4, configurable to be before or after BLND in MPCC
+	dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut; //4, configurable to be before or after BLND in MPCC
 	dc->caps.color.mpc.ogam_ram = 1;
 	dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
 	dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
@@ -2109,7 +2109,7 @@ struct resource_pool *dcn321_create_resource_pool(
 	if (!pool)
 		return NULL;
 
-	if (dcn321_resource_construct(init_data->num_virtual_links, dc, pool))
+	if (dcn321_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool))
 		return &pool->base;
 
 	BREAK_TO_DEBUGGER();
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
index 2a1b0b152501..82a5bdf38e8a 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn35/dcn35_resource.c
@@ -1948,7 +1948,7 @@ static bool dcn35_resource_construct(
 	dc->caps.color.dpp.ocsc = 0;
 
 	dc->caps.color.mpc.gamut_remap = 1;
-	dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2
+	dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut; //2
 	dc->caps.color.mpc.ogam_ram = 1;
 	dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
 	dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
@@ -2266,7 +2266,7 @@ struct resource_pool *dcn35_create_resource_pool(
 	if (!pool)
 		return NULL;
 
-	if (dcn35_resource_construct(init_data->num_virtual_links, dc, pool))
+	if (dcn35_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool))
 		return &pool->base;
 
 	BREAK_TO_DEBUGGER();
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
index bfd1016aa780..a4922df2f8d6 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
@@ -1921,7 +1921,7 @@ static bool dcn351_resource_construct(
 	dc->caps.color.dpp.ocsc = 0;
 
 	dc->caps.color.mpc.gamut_remap = 1;
-	dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2
+	dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut; //2
 	dc->caps.color.mpc.ogam_ram = 1;
 	dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
 	dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
@@ -2239,7 +2239,7 @@ struct resource_pool *dcn351_create_resource_pool(
 	if (!pool)
 		return NULL;
 
-	if (dcn351_resource_construct(init_data->num_virtual_links, dc, pool))
+	if (dcn351_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool))
 		return &pool->base;
 
 	BREAK_TO_DEBUGGER();
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
index 07a6675a7329..5cc52914e32b 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn36/dcn36_resource.c
@@ -1918,7 +1918,7 @@ static bool dcn36_resource_construct(
 	dc->caps.color.dpp.ocsc = 0;
 
 	dc->caps.color.mpc.gamut_remap = 1;
-	dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //2
+	dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut; //2
 	dc->caps.color.mpc.ogam_ram = 1;
 	dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
 	dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
@@ -2236,7 +2236,7 @@ struct resource_pool *dcn36_create_resource_pool(
 	if (!pool)
 		return NULL;
 
-	if (dcn36_resource_construct(init_data->num_virtual_links, dc, pool))
+	if (dcn36_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool))
 		return &pool->base;
 
 	BREAK_TO_DEBUGGER();
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
index cb93bfbe9e9e..22ce58250db3 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn401/dcn401_resource.c
@@ -2002,7 +2002,7 @@ static bool dcn401_resource_construct(
 	dc->caps.color.dpp.ocsc = 0;
 
 	dc->caps.color.mpc.gamut_remap = 1;
-	dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut; //4, configurable to be before or after BLND in MPCC
+	dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut; //4, configurable to be before or after BLND in MPCC
 	dc->caps.color.mpc.ogam_ram = 1;
 	dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
 	dc->caps.color.mpc.ogam_rom_caps.bt2020 = 0;
@@ -2336,7 +2336,7 @@ struct resource_pool *dcn401_create_resource_pool(
 	if (!pool)
 		return NULL;
 
-	if (dcn401_resource_construct(init_data->num_virtual_links, dc, pool))
+	if (dcn401_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool))
 		return &pool->base;
 
 	BREAK_TO_DEBUGGER();
diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c
index c0d37f00fed9..d5efe1e8fcee 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn42/dcn42_resource.c
@@ -1969,7 +1969,7 @@ static bool dcn42_resource_construct(
 
 	dc->caps.color.mpc.gamut_remap = 1;
 	//configurable to be before or after BLND in MPCC
-	dc->caps.color.mpc.num_3dluts = pool->base.res_cap->num_mpc_3dlut;
+	dc->caps.color.mpc.num_3dluts = (uint16_t)pool->base.res_cap->num_mpc_3dlut;
 	dc->caps.color.mpc.num_rmcm_3dluts = 2;
 	dc->caps.color.mpc.ogam_ram = 1;
 	dc->caps.color.mpc.ogam_rom_caps.srgb = 0;
@@ -2349,7 +2349,7 @@ struct resource_pool *dcn42_create_resource_pool(
 	if (!pool)
 		return NULL;
 
-	if (dcn42_resource_construct(init_data->num_virtual_links, dc, pool))
+	if (dcn42_resource_construct((uint8_t)init_data->num_virtual_links, dc, pool))
 		return &pool->base;
 
 	BREAK_TO_DEBUGGER();
diff --git a/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c b/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c
index 1b397fa7e05c..89f7ccd7f81f 100644
--- a/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c
+++ b/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn401/dcn401_soc_and_ip_translator.c
@@ -42,17 +42,17 @@ static void dcn401_convert_dc_clock_table_to_soc_bb_clock_table(
 
 	/* dcfclk */
 	if (dc_clk_table->num_entries_per_clk.num_dcfclk_levels) {
-		dml_clk_table->dcfclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_dcfclk_levels;
+		dml_clk_table->dcfclk.num_clk_values = (uint8_t)dc_clk_table->num_entries_per_clk.num_dcfclk_levels;
 		for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) {
 			if (i < dml_clk_table->dcfclk.num_clk_values) {
 				if (use_clock_dc_limits && dc_bw_params->dc_mode_limit.dcfclk_mhz &&
 						dc_clk_table->entries[i].dcfclk_mhz > dc_bw_params->dc_mode_limit.dcfclk_mhz) {
 					if (i == 0 || dc_clk_table->entries[i-1].dcfclk_mhz < dc_bw_params->dc_mode_limit.dcfclk_mhz) {
 						dml_clk_table->dcfclk.clk_values_khz[i] = dc_bw_params->dc_mode_limit.dcfclk_mhz * 1000;
-						dml_clk_table->dcfclk.num_clk_values = i + 1;
+						dml_clk_table->dcfclk.num_clk_values = (uint8_t)(i + 1);
 					} else {
 						dml_clk_table->dcfclk.clk_values_khz[i] = 0;
-						dml_clk_table->dcfclk.num_clk_values = i;
+						dml_clk_table->dcfclk.num_clk_values = (uint8_t)i;
 					}
 				} else {
 					dml_clk_table->dcfclk.clk_values_khz[i] = dc_clk_table->entries[i].dcfclk_mhz * 1000;
@@ -65,17 +65,17 @@ static void dcn401_convert_dc_clock_table_to_soc_bb_clock_table(
 
 	/* fclk */
 	if (dc_clk_table->num_entries_per_clk.num_fclk_levels) {
-		dml_clk_table->fclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_fclk_levels;
+		dml_clk_table->fclk.num_clk_values = (uint8_t)dc_clk_table->num_entries_per_clk.num_fclk_levels;
 		for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) {
 			if (i < dml_clk_table->fclk.num_clk_values) {
 				if (use_clock_dc_limits && dc_bw_params->dc_mode_limit.fclk_mhz &&
 						dc_clk_table->entries[i].fclk_mhz > dc_bw_params->dc_mode_limit.fclk_mhz) {
 					if (i == 0 || dc_clk_table->entries[i-1].fclk_mhz < dc_bw_params->dc_mode_limit.fclk_mhz) {
 						dml_clk_table->fclk.clk_values_khz[i] = dc_bw_params->dc_mode_limit.fclk_mhz * 1000;
-						dml_clk_table->fclk.num_clk_values = i + 1;
+						dml_clk_table->fclk.num_clk_values = (uint8_t)(i + 1);
 					} else {
 						dml_clk_table->fclk.clk_values_khz[i] = 0;
-						dml_clk_table->fclk.num_clk_values = i;
+						dml_clk_table->fclk.num_clk_values = (uint8_t)i;
 					}
 				} else {
 					dml_clk_table->fclk.clk_values_khz[i] = dc_clk_table->entries[i].fclk_mhz * 1000;
@@ -88,17 +88,17 @@ static void dcn401_convert_dc_clock_table_to_soc_bb_clock_table(
 
 	/* uclk */
 	if (dc_clk_table->num_entries_per_clk.num_memclk_levels) {
-		dml_clk_table->uclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_memclk_levels;
+		dml_clk_table->uclk.num_clk_values = (uint8_t)dc_clk_table->num_entries_per_clk.num_memclk_levels;
 		for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) {
 			if (i < dml_clk_table->uclk.num_clk_values) {
 				if (use_clock_dc_limits && dc_bw_params->dc_mode_limit.memclk_mhz &&
 						dc_clk_table->entries[i].memclk_mhz > dc_bw_params->dc_mode_limit.memclk_mhz) {
 					if (i == 0 || dc_clk_table->entries[i-1].memclk_mhz < dc_bw_params->dc_mode_limit.memclk_mhz) {
 						dml_clk_table->uclk.clk_values_khz[i] = dc_bw_params->dc_mode_limit.memclk_mhz * 1000;
-						dml_clk_table->uclk.num_clk_values = i + 1;
+						dml_clk_table->uclk.num_clk_values = (uint8_t)(i + 1);
 					} else {
 						dml_clk_table->uclk.clk_values_khz[i] = 0;
-						dml_clk_table->uclk.num_clk_values = i;
+						dml_clk_table->uclk.num_clk_values = (uint8_t)i;
 					}
 				} else {
 					dml_clk_table->uclk.clk_values_khz[i] = dc_clk_table->entries[i].memclk_mhz * 1000;
@@ -114,17 +114,17 @@ static void dcn401_convert_dc_clock_table_to_soc_bb_clock_table(
 
 	/* dispclk */
 	if (dc_clk_table->num_entries_per_clk.num_dispclk_levels) {
-		dml_clk_table->dispclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_dispclk_levels;
+		dml_clk_table->dispclk.num_clk_values = (uint8_t)dc_clk_table->num_entries_per_clk.num_dispclk_levels;
 		for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) {
 			if (i < dml_clk_table->dispclk.num_clk_values) {
 				if (use_clock_dc_limits && dc_bw_params->dc_mode_limit.dispclk_mhz &&
 						dc_clk_table->entries[i].dispclk_mhz > dc_bw_params->dc_mode_limit.dispclk_mhz) {
 					if (i == 0 || dc_clk_table->entries[i-1].dispclk_mhz < dc_bw_params->dc_mode_limit.dispclk_mhz) {
 						dml_clk_table->dispclk.clk_values_khz[i] = dc_bw_params->dc_mode_limit.dispclk_mhz * 1000;
-						dml_clk_table->dispclk.num_clk_values = i + 1;
+						dml_clk_table->dispclk.num_clk_values = (uint8_t)(i + 1);
 					} else {
 						dml_clk_table->dispclk.clk_values_khz[i] = 0;
-						dml_clk_table->dispclk.num_clk_values = i;
+						dml_clk_table->dispclk.num_clk_values = (uint8_t)i;
 					}
 				} else {
 					dml_clk_table->dispclk.clk_values_khz[i] = dc_clk_table->entries[i].dispclk_mhz * 1000;
@@ -137,17 +137,17 @@ static void dcn401_convert_dc_clock_table_to_soc_bb_clock_table(
 
 	/* dppclk */
 	if (dc_clk_table->num_entries_per_clk.num_dppclk_levels) {
-		dml_clk_table->dppclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_dppclk_levels;
+		dml_clk_table->dppclk.num_clk_values = (uint8_t)dc_clk_table->num_entries_per_clk.num_dppclk_levels;
 		for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) {
 			if (i < dml_clk_table->dppclk.num_clk_values) {
 				if (use_clock_dc_limits && dc_bw_params->dc_mode_limit.dppclk_mhz &&
 						dc_clk_table->entries[i].dppclk_mhz > dc_bw_params->dc_mode_limit.dppclk_mhz) {
 					if (i == 0 || dc_clk_table->entries[i-1].dppclk_mhz < dc_bw_params->dc_mode_limit.dppclk_mhz) {
 						dml_clk_table->dppclk.clk_values_khz[i] = dc_bw_params->dc_mode_limit.dppclk_mhz * 1000;
-						dml_clk_table->dppclk.num_clk_values = i + 1;
+						dml_clk_table->dppclk.num_clk_values = (uint8_t)(i + 1);
 					} else {
 						dml_clk_table->dppclk.clk_values_khz[i] = 0;
-						dml_clk_table->dppclk.num_clk_values = i;
+						dml_clk_table->dppclk.num_clk_values = (uint8_t)i;
 					}
 				} else {
 					dml_clk_table->dppclk.clk_values_khz[i] = dc_clk_table->entries[i].dppclk_mhz * 1000;
@@ -160,17 +160,17 @@ static void dcn401_convert_dc_clock_table_to_soc_bb_clock_table(
 
 	/* dtbclk */
 	if (dc_clk_table->num_entries_per_clk.num_dtbclk_levels) {
-		dml_clk_table->dtbclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_dtbclk_levels;
+		dml_clk_table->dtbclk.num_clk_values = (uint8_t)dc_clk_table->num_entries_per_clk.num_dtbclk_levels;
 		for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) {
 			if (i < dml_clk_table->dtbclk.num_clk_values) {
 				if (use_clock_dc_limits && dc_bw_params->dc_mode_limit.dtbclk_mhz &&
 						dc_clk_table->entries[i].dtbclk_mhz > dc_bw_params->dc_mode_limit.dtbclk_mhz) {
 					if (i == 0 || dc_clk_table->entries[i-1].dtbclk_mhz < dc_bw_params->dc_mode_limit.dtbclk_mhz) {
 						dml_clk_table->dtbclk.clk_values_khz[i] = dc_bw_params->dc_mode_limit.dtbclk_mhz * 1000;
-						dml_clk_table->dtbclk.num_clk_values = i + 1;
+						dml_clk_table->dtbclk.num_clk_values = (uint8_t)(i + 1);
 					} else {
 						dml_clk_table->dtbclk.clk_values_khz[i] = 0;
-						dml_clk_table->dtbclk.num_clk_values = i;
+						dml_clk_table->dtbclk.num_clk_values = (uint8_t)i;
 					}
 				} else {
 					dml_clk_table->dtbclk.clk_values_khz[i] = dc_clk_table->entries[i].dtbclk_mhz * 1000;
@@ -183,17 +183,17 @@ static void dcn401_convert_dc_clock_table_to_soc_bb_clock_table(
 
 	/* socclk */
 	if (dc_clk_table->num_entries_per_clk.num_socclk_levels) {
-		dml_clk_table->socclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_socclk_levels;
+		dml_clk_table->socclk.num_clk_values = (uint8_t)dc_clk_table->num_entries_per_clk.num_socclk_levels;
 		for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) {
 			if (i < dml_clk_table->socclk.num_clk_values) {
 				if (use_clock_dc_limits && dc_bw_params->dc_mode_limit.socclk_mhz &&
 						dc_clk_table->entries[i].socclk_mhz > dc_bw_params->dc_mode_limit.socclk_mhz) {
 					if (i == 0 || dc_clk_table->entries[i-1].socclk_mhz < dc_bw_params->dc_mode_limit.socclk_mhz) {
 						dml_clk_table->socclk.clk_values_khz[i] = dc_bw_params->dc_mode_limit.socclk_mhz * 1000;
-						dml_clk_table->socclk.num_clk_values = i + 1;
+						dml_clk_table->socclk.num_clk_values = (uint8_t)(i + 1);
 					} else {
 						dml_clk_table->socclk.clk_values_khz[i] = 0;
-						dml_clk_table->socclk.num_clk_values = i;
+						dml_clk_table->socclk.num_clk_values = (uint8_t)i;
 					}
 				} else {
 					dml_clk_table->socclk.clk_values_khz[i] = dc_clk_table->entries[i].socclk_mhz * 1000;
diff --git a/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.c b/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.c
index e723b4d0aff3..16160f35da1b 100644
--- a/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.c
+++ b/drivers/gpu/drm/amd/display/dc/soc_and_ip_translator/dcn42/dcn42_soc_and_ip_translator.c
@@ -47,8 +47,8 @@ static void dcn42_convert_dc_clock_table_to_soc_bb_clock_table(
 	 * for use with dml we need to fill in using an active value aiming for >= 2x DCFCLK
 	 */
 	if (dc_clk_table->num_entries_per_clk.num_fclk_levels && dc_clk_table->num_entries_per_clk.num_dcfclk_levels) {
-		dml_clk_table->fclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_dcfclk_levels;
-		dml_clk_table->dcfclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_dcfclk_levels;
+		dml_clk_table->fclk.num_clk_values = (uint8_t)dc_clk_table->num_entries_per_clk.num_dcfclk_levels;
+		dml_clk_table->dcfclk.num_clk_values = (uint8_t)dc_clk_table->num_entries_per_clk.num_dcfclk_levels;
 		for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) {
 			if (i < dc_clk_table->num_entries_per_clk.num_dcfclk_levels) {
 				int j, max_fclk = 0;
@@ -70,7 +70,7 @@ static void dcn42_convert_dc_clock_table_to_soc_bb_clock_table(
 
 	/* uclk */
 	if (dc_clk_table->num_entries_per_clk.num_memclk_levels) {
-		dml_clk_table->uclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_memclk_levels;
+		dml_clk_table->uclk.num_clk_values = (uint8_t)dc_clk_table->num_entries_per_clk.num_memclk_levels;
 		for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) {
 			if (i < dml_clk_table->uclk.num_clk_values) {
 				dml_clk_table->uclk.clk_values_khz[i] = dc_clk_table->entries[i].memclk_mhz * 1000;
@@ -84,7 +84,7 @@ static void dcn42_convert_dc_clock_table_to_soc_bb_clock_table(
 
 	/* dispclk */
 	if (dc_clk_table->num_entries_per_clk.num_dispclk_levels) {
-		dml_clk_table->dispclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_dispclk_levels;
+		dml_clk_table->dispclk.num_clk_values = (uint8_t)dc_clk_table->num_entries_per_clk.num_dispclk_levels;
 		for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) {
 			if (i < dml_clk_table->dispclk.num_clk_values) {
 				dml_clk_table->dispclk.clk_values_khz[i] = dc_clk_table->entries[i].dispclk_mhz * 1000;
@@ -101,7 +101,7 @@ static void dcn42_convert_dc_clock_table_to_soc_bb_clock_table(
 
 	/* dppclk */
 	if (dc_clk_table->num_entries_per_clk.num_dppclk_levels) {
-		dml_clk_table->dppclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_dppclk_levels;
+		dml_clk_table->dppclk.num_clk_values = (uint8_t)dc_clk_table->num_entries_per_clk.num_dppclk_levels;
 		for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) {
 			if (i < dml_clk_table->dppclk.num_clk_values) {
 				dml_clk_table->dppclk.clk_values_khz[i] = dc_clk_table->entries[i].dppclk_mhz * 1000;
@@ -117,7 +117,7 @@ static void dcn42_convert_dc_clock_table_to_soc_bb_clock_table(
 
 	/* dtbclk */
 	if (dc_clk_table->num_entries_per_clk.num_dtbclk_levels) {
-		dml_clk_table->dtbclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_dtbclk_levels;
+		dml_clk_table->dtbclk.num_clk_values = (uint8_t)dc_clk_table->num_entries_per_clk.num_dtbclk_levels;
 		for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) {
 			if (i < dml_clk_table->dtbclk.num_clk_values) {
 				dml_clk_table->dtbclk.clk_values_khz[i] = dc_clk_table->entries[i].dtbclk_mhz * 1000;
@@ -129,7 +129,7 @@ static void dcn42_convert_dc_clock_table_to_soc_bb_clock_table(
 
 	/* socclk */
 	if (dc_clk_table->num_entries_per_clk.num_socclk_levels) {
-		dml_clk_table->socclk.num_clk_values = dc_clk_table->num_entries_per_clk.num_socclk_levels;
+		dml_clk_table->socclk.num_clk_values = (uint8_t)dc_clk_table->num_entries_per_clk.num_socclk_levels;
 		for (i = 0; i < min(DML_MAX_CLK_TABLE_SIZE, MAX_NUM_DPM_LVL); i++) {
 			if (i < dml_clk_table->socclk.num_clk_values) {
 				dml_clk_table->socclk.clk_values_khz[i] = dc_clk_table->entries[i].socclk_mhz * 1000;
diff --git a/drivers/gpu/drm/amd/display/modules/inc/mod_power.h b/drivers/gpu/drm/amd/display/modules/inc/mod_power.h
new file mode 100644
index 000000000000..89037f7b7961
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/modules/inc/mod_power.h
@@ -0,0 +1,415 @@
+/* Copyright (c) 2019 Advanced Micro Devices, Inc. All rights reserved. */
+
+#ifndef MODULES_INC_MOD_POWER_H_
+#define MODULES_INC_MOD_POWER_H_
+
+#include "dm_services.h"
+
+struct mod_power_init_params {
+
+	bool disable_fractional_pwm;
+
+	/* Use nits based brightness instead of brightness percentage
+	 */
+	bool use_nits_based_brightness;
+	unsigned int panel_min_millinits;
+	unsigned int panel_max_millinits;
+
+	unsigned int min_backlight_pwm;
+	unsigned int max_backlight_pwm;
+
+	unsigned int min_abm_backlight;
+	unsigned int num_backlight_levels;
+	bool backlight_ramping_override;
+	unsigned int backlight_ramping_reduction;
+	unsigned int backlight_ramping_start;
+	bool def_varibright_enable;
+	unsigned int def_varibright_level;
+	unsigned int varibright_level;
+	unsigned int abm_config_setting;
+
+	bool allow_psr_smu_optimizations;
+
+	bool allow_psr_multi_disp_optimizations;
+
+	bool use_custom_backlight_caps;
+	unsigned int custom_backlight_caps_config_no;
+	bool use_linear_backlight_curve;
+};
+
+struct mod_power {
+	int dummy;
+};
+
+/* VariBright settings structure */
+struct varibright_info {
+	unsigned int level;
+	bool enable;
+	bool activate;
+};
+
+struct mod_power_psr_context {
+    /* ddc line */
+    unsigned int channel;
+    /* Transmitter id */
+    unsigned int transmitter_id;
+    /* Engine Id is used for Dig Be source select */
+    unsigned int engine_id;
+    /* Controller Id used for Dig Fe source select */
+    unsigned int controller_id;
+    /* Pcie or Uniphy */
+    unsigned int phy_type;
+    /* Physical PHY Id used by SMU interpretation */
+    unsigned int smu_phy_id;
+    /* Vertical total pixels from crtc timing.
+     * This is used for static screen detection.
+     * ie. If we want to detect half a frame,
+     * we use this to determine the hyst lines.
+     */
+    unsigned int crtc_timing_vertical_total;
+    /* PSR supported from panel capabilities and
+     * current display configuration
+     */
+    bool psr_supported_display_config;
+    /* Whether fast link training is supported by the panel */
+    bool psr_exit_link_training_required;
+    /* If RFB setup time is greater than the total VBLANK time,
+     * it is not possible for the sink to capture the video frame
+     * in the same frame the SDP is sent. In this case,
+     * the frame capture indication bit should be set and an extra
+     * static frame should be transmitted to the sink.
+     */
+    bool psr_frame_capture_indication_req;
+    /* Set the last possible line SDP may be transmitted without violating
+     * the RFB setup time or entering the active video frame.
+     */
+    unsigned int sdp_transmit_line_num_deadline;
+    /* The VSync rate in Hz used to calculate the
+     * step size for smooth brightness feature
+     */
+    unsigned int vsync_rate_hz;
+    unsigned int skip_psr_wait_for_pll_lock;
+    unsigned int number_of_controllers;
+    /* Unused, for future use. To indicate that first changed frame from
+     * state3 shouldn't result in psr_inactive, but rather to perform
+     * an automatic single frame rfb_update.
+     */
+    bool rfb_update_auto_en;
+    /* Number of frame before entering static screen */
+    unsigned int timehyst_frames;
+    /* Partial frames before entering static screen */
+    unsigned int hyst_lines;
+    /* # of repeated AUX transaction attempts to make before
+     * indicating failure to the driver
+     */
+    unsigned int aux_repeats;
+    /* Controls hw blocks to power down during PSR active state */
+    unsigned int psr_level;
+    /* Controls additional delay after remote frame capture before
+     * continuing powerd own
+     */
+	unsigned int frame_delay;
+	bool allow_smu_optimizations;
+	bool allow_multi_disp_optimizations;
+	unsigned int line_time_in_us;
+	/* Panel self refresh 2 selective update granularity required */
+	bool su_granularity_required;
+	/* psr2 selective update y granularity capability */
+	uint8_t su_y_granularity;
+	uint8_t rate_control_caps;
+	bool os_request_force_ffu;
+};
+
+enum psr_event {
+	psr_event_invalid = 0x0,
+	psr_event_vsync = 0x1,
+	psr_event_full_screen = 0x2,
+	psr_event_defer_enable = 0x4,
+	psr_event_hw_programming = 0x8,
+	psr_event_test_harness_enable_psr = 0x10,
+	psr_event_test_harness_disable_psr = 0x20,
+	psr_event_mpo_video_selective_update = 0x40,
+	psr_event_edp_panel_off_disable_psr = 0x80,
+	psr_event_dynamic_display_switch = 0x100,
+	psr_event_big_screen_video = 0x200,
+	psr_event_dds_defer_stream_enable = 0x800,
+	psr_event_dynamic_link_rate_control = 0x1000,
+	psr_event_vrr_transition = 0x2000,
+	psr_event_pause = 0x4000,
+	psr_event_immediate_flip = 0x8000,
+	psr_event_os_request_disable = 0x10000,
+	psr_event_os_request_force_ffu = 0x20000,
+	psr_event_os_override_hold = 0x40000,
+	psr_event_crc_window_active = 0x80000,
+};
+
+enum replay_event {
+	replay_event_invalid = 0x0,
+	replay_event_vsync = 0x1,
+	replay_event_full_screen = 0x2,
+	replay_event_mpo_video_selective_update = 0x4,
+	replay_event_big_screen_video = 0x8,
+	replay_event_hw_programming = 0x10,
+	replay_event_edp_panel_off_disable_psr = 0x20,
+	replay_event_general_ui = 0x40,
+	replay_event_vrr = 0x80,
+	replay_event_prepare_vtotal = 0x100,
+	replay_event_test_harness_enable_replay = 0x200,
+	replay_event_test_harness_disable_replay = 0x400,
+	replay_event_test_harness_ultra_sleep = 0x800,
+	replay_event_immediate_flip = 0x1000,
+	replay_event_vrr_transition = 0x2000,
+	replay_event_pause = 0x4000,
+	replay_event_disable_replay_while_DPMS = 0x8000,
+	replay_event_test_harness_mode = 0x10000,
+	replay_event_cursor_updating = 0x20000,
+	replay_event_sleep_resume = 0x40000,
+	replay_event_disable_in_AC = 0x80000,
+	replay_event_disable_replay_while_detect_display = 0x100000,
+	replay_event_disable_replay_while_switching_mux = 0x400000,
+	replay_event_infopacket = 0x800000,
+	replay_event_os_request_disable = 0x1000000,
+	replay_event_os_request_force_ffu = 0x2000000,
+	replay_event_os_override_hold = 0x4000000,
+	replay_event_crc_window_active = 0x8000000,
+};
+
+enum replay_enable_option {
+	pr_enable_option_static_screen = 0x1,
+	pr_enable_option_mpo_video = 0x2,
+	pr_enable_option_full_screen_video = 0x4,
+	pr_enable_option_general_ui = 0x8,
+	pr_enable_option_full_screen = 0x10,
+	pr_enable_option_static_screen_coasting = 0x10000,
+	pr_enable_option_mpo_video_coasting = 0x20000,
+	pr_enable_option_full_screen_video_coasting = 0x40000,
+	pr_enable_option_full_screen_coasting = 0x100000,
+};
+
+struct mod_power *mod_power_create(struct dc *dc,
+		struct mod_power_init_params *init_params,
+		unsigned int edp_num);
+
+void mod_power_destroy(struct mod_power *mod_power);
+
+bool mod_power_hw_init(struct mod_power *mod_power);
+
+bool mod_power_add_stream(struct mod_power *mod_power,
+		struct dc_stream_state *stream, struct psr_caps *caps);
+
+bool mod_power_remove_stream(struct mod_power *mod_power,
+		const struct dc_stream_state *stream);
+
+bool mod_power_replace_stream(struct mod_power *mod_power,
+		const struct dc_stream_state *current_stream,
+		struct dc_stream_state *new_stream,
+		struct psr_caps *new_caps);
+
+bool mod_power_set_backlight_nits(struct mod_power *mod_power,
+		struct dc_stream_state *streams,
+		unsigned int backlight_millinit,
+		unsigned int transition_time_millisec,
+		bool skip_aux,
+		bool is_hdr);
+
+bool mod_power_set_backlight_percent(struct mod_power *mod_power,
+		struct dc_stream_state *stream,
+		unsigned int backlight_millipercent,
+		unsigned int transition_time_millisec,
+		bool is_hdr);
+
+void mod_power_update_backlight(struct mod_power *mod_power,
+		struct dc_stream_state *stream,
+		unsigned int backlight_millipercent);
+
+void mod_power_update_backlight_nits(struct mod_power *mod_power,
+		struct dc_stream_state *stream,
+		unsigned int backlight_millinit);
+
+bool mod_power_get_backlight_pwm(struct mod_power *mod_power,
+		unsigned int *backlight_pwm,
+		unsigned int inst);
+
+bool mod_power_get_backlight_nits(struct mod_power *mod_power,
+		unsigned int *backlight_millinit,
+		unsigned int inst);
+
+bool mod_power_get_backlight_percent(struct mod_power *mod_power,
+		unsigned int *backlight_millipercent,
+		unsigned int inst);
+
+bool mod_power_get_hw_target_backlight_pwm_nits(
+		struct mod_power *mod_power,
+		const struct dc_link *link,
+		unsigned int *backlight_millinit,
+		unsigned int inst);
+
+bool mod_power_get_hw_target_backlight_pwm_percent(
+		struct mod_power *mod_power,
+		const struct dc_link *link,
+		unsigned int *backlight_millipercent,
+		unsigned int inst);
+
+bool mod_power_get_hw_target_backlight_pwm(
+		struct mod_power *mod_power,
+		const struct dc_link *link,
+		unsigned int *backlight_u16_16);
+
+bool mod_power_get_hw_backlight_pwm(
+		struct mod_power *mod_power,
+		const struct dc_link *link,
+		unsigned int *backlight);
+
+bool mod_power_get_hw_backlight_pwm_nits(
+		struct mod_power *mod_power,
+		const struct dc_link *link,
+		unsigned int *backlight_millinit,
+		unsigned int inst);
+
+bool mod_power_get_hw_backlight_aux_nits(
+		struct mod_power *mod_power,
+		struct dc_stream_state **streams, int num_streams,
+		unsigned int *backlight_millinit_avg,
+		unsigned int *backlight_millinit_peak);
+
+bool mod_power_get_hw_backlight_pwm_percent(
+		struct mod_power *mod_power,
+		const struct dc_link *link,
+		unsigned int *backlight_millipercent,
+		unsigned int inst);
+
+void mod_power_initialize_backlight_caps
+		(struct mod_power *mod_power);
+
+bool mod_power_get_panel_backlight_boundaries
+				(struct mod_power *mod_power,
+				unsigned int *out_min_backlight,
+				unsigned int *out_max_backlight,
+				unsigned int *out_ac_backlight_percent,
+				unsigned int *out_dc_backlight_percent,
+				unsigned int inst);
+
+bool mod_power_set_smooth_brightness(struct mod_power *mod_power,
+		bool enable_brightness,
+		unsigned int inst);
+
+bool mod_power_notify_mode_change(struct mod_power *mod_power,
+		const struct dc_stream_state *stream,
+		bool is_hdr);
+
+bool mod_power_get_varibright_level(struct mod_power *mod_power,
+		unsigned int *varibright_level);
+
+bool mod_power_get_varibright_hw_level(struct mod_power *mod_power,
+		unsigned int *varibright_level);
+
+bool mod_power_get_varibright_default_level(struct mod_power *mod_power,
+		unsigned int *varibright_level);
+
+bool mod_power_get_varibright_enable(struct mod_power *mod_power,
+		bool *varibright_enable);
+
+bool mod_power_varibright_activate(struct mod_power	*mod_power,
+		bool activate, struct dc_stream_update *stream_update);
+
+bool mod_power_varibright_feature_enable(struct mod_power *mod_power,
+		bool enable, struct dc_stream_update *stream_update);
+
+
+bool mod_power_varibright_set_level(struct mod_power *mod_power,
+		unsigned int level, struct dc_stream_update *stream_update);
+
+bool mod_power_varibright_set_hw_level(struct mod_power *mod_power,
+		unsigned int level,	struct dc_stream_update *stream_update);
+
+bool mod_power_is_abm_active(struct mod_power *mod_power,
+		const struct dc_link *link,
+		unsigned int inst);
+
+
+bool mod_power_set_psr_event(struct mod_power *mod_power,
+		struct dc_stream_state *stream, bool set_event,
+		enum psr_event event, bool wait);
+
+bool mod_power_get_psr_event(struct mod_power *mod_power,
+			struct dc_stream_state *stream,
+			unsigned int *active_psr_events);
+
+bool mod_power_get_psr_state(struct mod_power *mod_power,
+		const struct dc_stream_state *stream,
+		enum dc_psr_state *state);
+
+bool mod_power_get_psr_enabled_status(struct mod_power *mod_power,
+		const struct dc_stream_state *stream,
+		bool *psr_enabled);
+
+bool mod_power_set_replay_event(struct mod_power *mod_power,
+	struct dc_stream_state *stream, bool set_event,
+	enum replay_event event, bool wait_for_disable);
+
+bool mod_power_get_replay_event(struct mod_power *mod_power,
+	struct dc_stream_state *stream,
+	unsigned int *active_replay_events);
+
+bool mod_power_get_replay_active_status(const struct dc_stream_state *stream,
+	bool *replay_active);
+
+bool mod_power_replay_set_coasting_vtotal(struct mod_power *mod_power,
+	const struct dc_stream_state *stream,
+	uint32_t coasting_vtotal, uint16_t frame_skip_number);
+
+void mod_power_replay_residency(const struct dc_stream_state *stream,
+	unsigned int *residency, const bool is_start, const bool is_alpm);
+
+bool mod_power_replay_set_power_opt_and_coasting_vtotal(struct mod_power *mod_power,
+	const struct dc_stream_state *stream, unsigned int active_replay_events, uint32_t coasting_vtotal,
+	bool is_ultra_sleep_mode, uint16_t frame_skip_number);
+
+void mod_power_replay_set_timing_sync_supported(struct mod_power *mod_power,
+	const struct dc_stream_state *stream);
+
+void mod_power_replay_disabled_adaptive_sync_sdp(struct mod_power *mod_power,
+	const struct dc_stream_state *stream, bool force_disabled);
+
+void mod_power_replay_disabled_desync_error_detection(struct mod_power *mod_power,
+	const struct dc_stream_state *stream,  bool force_disabled);
+void mod_power_set_low_rr_activate(struct mod_power *mod_power,
+	const struct dc_stream_state *stream, bool low_rr_supported);
+
+void mod_power_set_video_conferencing_activate(struct mod_power *mod_power,
+	const struct dc_stream_state *stream, bool video_conferencing_activate);
+
+void mod_power_set_live_capture_with_cvt_activate(struct mod_power *mod_power,
+	const struct dc_stream_state *stream, bool live_capture_with_cvt_activate);
+
+void mod_power_set_replay_continuously_resync(struct mod_power *mod_power,
+	const struct dc_stream_state *stream, bool enable);
+
+void mod_power_set_coasting_vtotal_without_frame_update(struct mod_power *mod_power,
+	const struct dc_stream_state *stream, uint32_t coasting_vtotal);
+
+
+
+void mod_power_psr_residency(struct mod_power *mod_power,
+		const struct dc_stream_state *stream,
+		unsigned int *residency,
+		const uint8_t mode);
+bool mod_power_psr_get_active_psr_events(struct mod_power *mod_power,
+		const struct dc_stream_state *stream, unsigned int *active_psr_events);
+bool mod_power_psr_set_sink_vtotal_in_psr_active(struct mod_power *mod_power,
+		const struct dc_stream_state *stream,
+		uint16_t psr_vtotal_idle,
+		uint16_t psr_vtotal_su);
+
+
+
+bool mod_power_backlight_percent_to_nits(struct mod_power *mod_power,
+		struct dc_stream_state *stream,
+		unsigned int backlight_millipercent,
+		unsigned int *backlight_millinit);
+bool mod_power_backlight_nits_to_percent(struct mod_power *mod_power,
+		struct dc_stream_state *stream,
+		unsigned int backlight_millinit,
+		unsigned int *backlight_millipercent);
+
+#endif /* MODULES_INC_MOD_POWER_H_ */
diff --git a/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c b/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c
index 00473c6284d5..55c7250f18d8 100644
--- a/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c
+++ b/drivers/gpu/drm/amd/display/modules/info_packet/info_packet.c
@@ -246,7 +246,7 @@ void set_vsc_packet_colorimetry_data(
 		break;
 	}
 
-	info_packet->sb[16] = (pixelEncoding << 4) | colorimetryFormat;
+	info_packet->sb[16] = (uint8_t)((pixelEncoding << 4) | colorimetryFormat);
 
 	/* Set color depth */
 	switch (stream->timing.display_color_depth) {
diff --git a/drivers/gpu/drm/amd/display/modules/power/Makefile b/drivers/gpu/drm/amd/display/modules/power/Makefile
index 9d1b22d35ece..b27a1ff3d86b 100644
--- a/drivers/gpu/drm/amd/display/modules/power/Makefile
+++ b/drivers/gpu/drm/amd/display/modules/power/Makefile
@@ -23,7 +23,7 @@
 # Makefile for the 'power' sub-module of DAL.
 #
 
-MOD_POWER = power_helpers.o
+MOD_POWER = power_helpers.o power.o
 
 AMD_DAL_MOD_POWER = $(addprefix $(AMDDALPATH)/modules/power/,$(MOD_POWER))
 #$(info ************  DAL POWER MODULE MAKEFILE ************)
diff --git a/drivers/gpu/drm/amd/display/modules/power/power.c b/drivers/gpu/drm/amd/display/modules/power/power.c
new file mode 100644
index 000000000000..81d15a51e045
--- /dev/null
+++ b/drivers/gpu/drm/amd/display/modules/power/power.c
@@ -0,0 +1,3024 @@
+/*
+ * Copyright 2016 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: AMD
+ *
+ */
+
+#include "dm_services.h"
+#include "dc.h"
+#include "mod_power.h"
+#include "core_types.h"
+#include "dmcu.h"
+#include "abm.h"
+#include "power_helpers.h"
+#include "dce/dmub_psr.h"
+#include "dal_asic_id.h"
+#include "link_service.h"
+#include <linux/math.h>
+
+#define DC_TRACE_LEVEL_MESSAGE(...) /* do nothing */
+#define DC_TRACE_LEVEL_MESSAGEP(...) /* do nothing */
+
+#define MOD_POWER_MAX_CONCURRENT_STREAMS 32
+#define SMOOTH_BRIGHTNESS_ADJUSTMENT_TIME_IN_MS 500
+#define LOW_REFRESH_RATE_DURATION_US_UPPER_BOUND 25000
+
+
+struct backlight_state {
+	/* HW uses u16.16 format for backlight PWM */
+	unsigned int backlight_pwm;
+	/* DM may call power module to set backlight
+	 * targeting percent brightness
+	 */
+	unsigned int backlight_millipercent;
+	/* DM may call power module to set backlight based on an explicit
+	 * nits value.
+	 */
+	unsigned int backlight_millinit;
+	unsigned int frame_ramp;
+	bool smooth_brightness_enabled;
+	bool isHDR;
+};
+struct power_entity {
+	struct dc_stream_state *stream;
+	struct psr_caps *caps;
+	struct mod_power_psr_context *psr_context;
+
+	/*PSR cached properties*/
+	bool psr_enabled;
+	unsigned int psr_events;
+	unsigned int psr_power_opt;
+	unsigned int replay_events;
+};
+
+struct backlight_properties {
+	bool use_nits_based_brightness;
+	bool disable_fractional_pwm;
+
+	unsigned int min_abm_backlight;
+	unsigned int num_backlight_levels;
+
+	bool backlight_ramping_override;
+	unsigned int backlight_ramping_reduction;
+	unsigned int backlight_ramping_start;
+
+	/* Backlight cached properties */
+	unsigned int ac_backlight_percent;
+	unsigned int dc_backlight_percent;
+
+	/* backlight LUT stored in HW u16.16 format*/
+	unsigned int *backlight_lut;
+	unsigned int min_backlight_pwm;
+	unsigned int max_backlight_pwm;
+	unsigned int backlight_range;
+
+	/* Describes the panel's min and max luminance in millinits measured
+	 * on full white screen, in min and max backlight settings.
+	 */
+	unsigned int min_brightness_millinits;
+	unsigned int max_brightness_millinits;
+	unsigned int nits_range;
+
+	bool backlight_caps_valid;
+	bool use_custom_backlight_caps;
+	unsigned int custom_backlight_caps_config_no;
+	bool use_linear_backlight_curve;
+};
+
+struct dmcu_varibright_cached_properties {
+	unsigned int varibright_config_setting;
+	unsigned int varibright_level;
+	unsigned int varibright_hw_level;
+	unsigned int def_varibright_level;
+	bool varibright_user_enable;
+	bool varibright_active;
+};
+
+struct core_power {
+	struct mod_power public;
+	struct dc *dc;
+	struct power_entity *map;
+	struct dmcu_varibright_cached_properties varibright_prop;
+	struct backlight_properties bl_prop[MAX_NUM_EDP];
+	struct backlight_state bl_state[MAX_NUM_EDP];
+	unsigned int edp_num;
+
+	bool psr_smu_optimizations_support;
+	bool multi_disp_optimizations_support;
+
+	int num_entities;
+};
+
+union dmcu_abm_set_bl_params {
+	struct {
+		unsigned int gradual_change : 1; /* [0:0] */
+		unsigned int reserved : 15; /* [15:1] */
+		unsigned int frame_ramp : 16; /* [31:16] */
+	} bits;
+	unsigned int u32All;
+};
+
+/* If system or panel does not report some sort of brightness percent to nits
+ * mapping, we will use following default values so backlight control using
+ * nits based interfaces will still work, but might not describe panel
+ * correctly. In this case percentage based backlight control should ideally
+ * be used.
+ * Min = 5 nits
+ * Max = 300 nits
+ */
+
+static const unsigned int pwr_default_min_brightness_millinits = 1000;
+static const unsigned int pwr_default_sdr_brightness_millinits = 270000;
+
+static const unsigned int default_ac_backlight_percent   = 100;
+static const unsigned int default_dc_backlight_percent   = 70;
+
+#define MOD_POWER_TO_CORE(mod_power)\
+		container_of(mod_power, struct core_power, public)
+
+static unsigned int calc_psr_num_static_frames(unsigned int vsync_rate_hz)
+{
+	/* Initialize fail-safe to 2 static frames. */
+	unsigned int num_frames_static = 2;
+
+	/* Calculate number of frames such that at least 30 ms has passed.
+	 * Round up to ensure the static period is not shorter than 30 ms.
+	 */
+	if (vsync_rate_hz != 0)
+		num_frames_static = DIV_ROUND_UP(30000 * vsync_rate_hz, 1000000);
+
+	return num_frames_static;
+}
+
+/* Given a specific dc_stream* this function finds its equivalent
+ * on the core_freesync->map and returns the corresponding index
+ */
+static unsigned int map_index_from_stream(struct core_power *core_power,
+		const struct dc_stream_state *stream)
+{
+	unsigned int index = 0;
+
+	for (index = 0; index < core_power->num_entities; index++) {
+		if (core_power->map[index].stream == stream)
+			return index;
+	}
+	/* Could not find stream requested, this is not trivial, fix when hit*/
+	DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_ERROR,
+						WPP_BIT_FLAG_Firmware_PsrState,
+						"map index from stream: ERROR: core_power=%p stream=%p",
+						core_power,
+						stream);
+	ASSERT(false);
+	/* We come here only when we can't map stream index.
+	 * In good cases, this would happen when we attempt to change
+	 * brightness before stream creation, in which case we create a
+	 * dummy stream with index 0.
+	 * With external monitor connected, the index passed from this return
+	 * is 1. Passing anything greater than 0 from here would always point
+	 * to bad memory.
+	 */
+	return 0;
+}
+
+static uint16_t backlight_8_to_16(unsigned int backlight_8bit)
+{
+	return (uint16_t)(backlight_8bit * 0x101);
+}
+
+
+static unsigned int backlight_millipercent_to_millinit(
+		struct core_power *core_power, unsigned int millipercent, unsigned int inst)
+{
+	unsigned int millinit = 0;
+	unsigned long long numerator = 0;
+
+	if (core_power == NULL)
+		return 0;
+
+	numerator = ((unsigned long long)millipercent) *
+				core_power->bl_prop[inst].nits_range;
+	millinit = ((unsigned int)div_u64(numerator, 100000)) +
+			core_power->bl_prop[inst].min_brightness_millinits;
+
+	return millinit;
+}
+
+static unsigned int backlight_millinit_to_millipercent(
+		struct core_power *core_power, unsigned int millinit, unsigned int inst)
+{
+	unsigned int millipercent = 0;
+	unsigned long long numerator = 0;
+
+	if (core_power == NULL)
+		return 0;
+
+	if (millinit <= core_power->bl_prop[inst].min_brightness_millinits)
+		return 0;
+
+	if (millinit >= core_power->bl_prop[inst].max_brightness_millinits)
+		return (100 * 1000);
+
+	numerator = (((unsigned long long)millinit) -
+			core_power->bl_prop[inst].min_brightness_millinits) * 100000;
+	millipercent = ((unsigned int)div_u64(numerator,
+				core_power->bl_prop[inst].nits_range));
+
+	return millipercent;
+}
+
+static unsigned int backlight_pwm_to_millipercent(
+		struct core_power *core_power, unsigned int pwm, unsigned int inst)
+{
+	unsigned int millipercent = 0;
+	unsigned int max_index = 0;
+
+	if (core_power == NULL)
+		return 0;
+
+	if (!core_power->bl_prop[inst].backlight_caps_valid)
+		return 0;
+
+	/* Doesn't really make sense to have one single backlight level
+	 * possible...
+	 */
+	if (core_power->bl_prop[inst].num_backlight_levels < 2)
+		return 0;
+
+	max_index = core_power->bl_prop[inst].num_backlight_levels - 1;
+
+	if (pwm <= core_power->bl_prop[inst].backlight_lut[0])
+		return 0;
+
+	if (pwm > core_power->bl_prop[inst].backlight_lut[max_index])
+		return (100 * 1000);
+
+	/* We need to do a binary search over the array for where the pwm level
+	 * is in the lut. Based on the index we can determine percentage.
+	 */
+	unsigned int min = 0;
+	unsigned int max = max_index;
+	unsigned int mid = 0;
+
+	while (max >= min) {
+		mid = (min + max) / 2; /* floor of half range */
+
+		if (core_power->bl_prop[inst].backlight_lut[mid] < pwm)
+			min = mid + 1;
+		else if (core_power->bl_prop[inst].backlight_lut[mid] > pwm)
+			max = mid - 1;
+		else
+			break;
+	}
+
+	/* In this case, exact match is not found. Check if mid/min/max
+	 * value is actually closer.
+	 */
+	if (max < min) {
+		unsigned int min_delta;
+		unsigned int mid_delta;
+		unsigned int max_delta;
+
+		min_delta = (core_power->bl_prop[inst].backlight_lut[min] > pwm) ?
+				core_power->bl_prop[inst].backlight_lut[min] - pwm :
+				pwm - core_power->bl_prop[inst].backlight_lut[min];
+
+		mid_delta = (core_power->bl_prop[inst].backlight_lut[mid] > pwm) ?
+				core_power->bl_prop[inst].backlight_lut[mid] - pwm :
+				pwm - core_power->bl_prop[inst].backlight_lut[mid];
+
+		max_delta = (core_power->bl_prop[inst].backlight_lut[max] > pwm) ?
+				core_power->bl_prop[inst].backlight_lut[max] - pwm :
+				pwm - core_power->bl_prop[inst].backlight_lut[max];
+
+		if ((min_delta < mid_delta) && (min_delta < max_delta))
+			mid = min;
+
+		if ((max_delta < mid_delta) && (max_delta < min_delta))
+			mid = max;
+	}
+
+	/* No interpolation, just take closest index */
+	millipercent = 1000 * 100 * mid / max_index;
+
+	return millipercent;
+}
+
+static unsigned int backlight_pwm_to_millinit(
+		struct core_power *core_power, unsigned int pwm, unsigned int inst)
+{
+	unsigned int millinit = 0;
+
+	if (core_power == NULL)
+		return 0;
+
+	if (pwm <= core_power->bl_prop[inst].min_backlight_pwm)
+		return core_power->bl_prop[inst].min_brightness_millinits;
+
+	if (pwm >= core_power->bl_prop[inst].max_backlight_pwm)
+		return core_power->bl_prop[inst].max_brightness_millinits;
+
+	millinit = ((unsigned int)div_u64(((unsigned long long)pwm -
+				core_power->bl_prop[inst].min_backlight_pwm) *
+				core_power->bl_prop[inst].nits_range,
+				core_power->bl_prop[inst].backlight_range));
+
+	millinit += core_power->bl_prop[inst].min_brightness_millinits;
+
+	if (millinit > core_power->bl_prop[inst].max_brightness_millinits)
+		millinit = core_power->bl_prop[inst].max_brightness_millinits;
+
+	return millinit;
+}
+
+static unsigned int backlight_millipercent_to_pwm(
+		struct core_power *core_power, unsigned int millipercent, unsigned int inst)
+{
+	unsigned int pwm = (unsigned int)-1;
+	unsigned int index = 0;
+
+	if (core_power == NULL)
+		return 0;
+
+	// Bypass the brightness mapping LUT
+	if (core_power->bl_prop->use_linear_backlight_curve) {
+		pwm = core_power->bl_prop[inst].min_backlight_pwm +
+			(unsigned int) div_u64((unsigned long long) millipercent *
+			core_power->bl_prop[inst].backlight_range,
+			100000);
+
+		if (pwm > core_power->bl_prop[inst].max_backlight_pwm)
+			pwm = core_power->bl_prop[inst].max_backlight_pwm;
+
+		return pwm;
+	}
+
+	if (millipercent >= (100 * 1000))
+		return core_power->bl_prop[inst].backlight_lut[core_power->bl_prop[inst].num_backlight_levels - 1];
+
+	/* This will give the floor index. */
+	index = ((core_power->bl_prop[inst].num_backlight_levels - 1) *
+						millipercent) / 100000;
+	/* Null check otherwise eDP doesn't lightup when connected to DP1 */
+	if (core_power->bl_prop[inst].backlight_lut == NULL)
+		return pwm;
+
+	pwm = core_power->bl_prop[inst].backlight_lut[index];
+
+	return pwm;
+}
+
+static unsigned int backlight_millinit_to_pwm(
+		struct core_power *core_power, unsigned int millinit, unsigned int inst)
+{
+	unsigned int pwm = 0;
+
+	if (core_power == NULL)
+		return 0;
+
+	/* For nits based brightness, the signal will be a value
+	 * between the minimum and maximum value.
+	 */
+	if (millinit >= core_power->bl_prop[inst].max_brightness_millinits)
+		return core_power->bl_prop[inst].max_backlight_pwm;
+	else if (millinit <= core_power->bl_prop[inst].min_brightness_millinits)
+		return core_power->bl_prop[inst].min_backlight_pwm;
+
+	pwm = ((unsigned int)div_u64(((unsigned long long)millinit -
+			core_power->bl_prop[inst].min_brightness_millinits) *
+			core_power->bl_prop[inst].backlight_range,
+			core_power->bl_prop[inst].nits_range));
+
+	pwm += core_power->bl_prop[inst].min_backlight_pwm;
+
+	if (pwm > core_power->bl_prop[inst].max_backlight_pwm)
+		pwm = core_power->bl_prop[inst].max_backlight_pwm;
+
+	return pwm;
+}
+
+static bool validate_ext_backlight_caps(
+		struct dm_acpi_atif_backlight_caps *ext_backlight_caps)
+{
+	unsigned int i;
+	unsigned int num_of_data_points = 0;
+	unsigned int last_signal_level = 0;
+	unsigned int last_luminance = 0;
+
+	num_of_data_points = ext_backlight_caps->num_data_points;
+
+	/* Validation rules:
+	 * 1. BIOS should carry customized data points and
+	 * the number of data points should not be larger than 99.
+	 * 2. The max_input_signal should be larger than min_input_signal.
+	 * 3. For each data point:
+	 *	a. luminance should be in ascending order and
+	 *	should not be 0 or 100 since the corresponding signal_level
+	 *	are assigned by min_input_signal and max_input_signal.
+	 *	b. signal_level should be in ascending order and
+	 *	be within the range of min/max_input_signal.
+	 */
+	if (num_of_data_points > BL_DATA_POINTS)
+		return false;
+
+	if (ext_backlight_caps->min_input_signal >= ext_backlight_caps->max_input_signal)
+		return false;
+
+	last_signal_level = ext_backlight_caps->min_input_signal;
+	for (i = 0; i < num_of_data_points; i++) {
+		unsigned int luminance = ext_backlight_caps->data_points[i].luminance;
+		unsigned int signal_level = ext_backlight_caps->data_points[i].signal_level;
+
+		if ((luminance <= last_luminance) || (luminance > BL_DATA_POINTS))
+			return false;
+
+		if ((signal_level <= last_signal_level) || (signal_level >= ext_backlight_caps->max_input_signal))
+			return false;
+
+		last_signal_level = signal_level;
+		last_luminance = luminance;
+	}
+
+	return true;
+}
+
+/* hard coded to default backlight curve. */
+static void initialize_backlight_caps(struct core_power *core_power, unsigned int inst)
+{
+	unsigned int i;
+	struct dm_acpi_atif_backlight_caps *ext_backlight_caps = NULL;
+	bool custom_curve_present = false;
+	unsigned int num_levels = 0;
+	struct dc *dc = NULL;
+	enum dm_acpi_display_type acpi_display_type =
+		(inst == 0) ? AcpiDisplayType_LCD1 : AcpiDisplayType_LCD2;
+
+	if (core_power == NULL)
+		return;
+	dc = core_power->dc;
+
+	num_levels = core_power->bl_prop[inst].num_backlight_levels;
+
+	/* Allocate memory for ATIF output
+	 * (do not want to use 256 bytes on the stack)
+	 */
+	ext_backlight_caps = (struct dm_acpi_atif_backlight_caps *)
+		(kzalloc(sizeof(struct dm_acpi_atif_backlight_caps),
+				GFP_KERNEL));
+
+	if (ext_backlight_caps == NULL)
+		return;
+
+	/* Retrieve ACPI extended brightness caps */
+	if (dm_query_extended_brightness_caps
+		(dc->ctx, acpi_display_type, ext_backlight_caps)) {
+		custom_curve_present = validate_ext_backlight_caps(ext_backlight_caps);
+	}
+
+	if (core_power->bl_prop[inst].use_custom_backlight_caps &&
+			fill_custom_backlight_caps(
+					core_power->bl_prop[inst].custom_backlight_caps_config_no,
+					ext_backlight_caps)) {
+		custom_curve_present = validate_ext_backlight_caps(ext_backlight_caps);
+	}
+
+	if (custom_curve_present) {
+		unsigned int index = 1;
+		unsigned int num_of_data_points = ext_backlight_caps->num_data_points;
+
+		core_power->bl_prop[inst].ac_backlight_percent =
+			ext_backlight_caps->ac_level_percentage;
+		core_power->bl_prop[inst].dc_backlight_percent =
+			ext_backlight_caps->dc_level_percentage;
+		core_power->bl_prop[inst].backlight_lut[0] =
+			backlight_8_to_16(
+				ext_backlight_caps->min_input_signal);
+		core_power->bl_prop[inst].backlight_lut[num_levels - 1] =
+			backlight_8_to_16(
+				ext_backlight_caps->max_input_signal);
+
+		/* Filling translation table from data points -
+		 * between every two provided data points we
+		 * lineary interpolate missing values
+		 */
+		for (i = 0; i < num_of_data_points; i++) {
+			unsigned int luminance =
+				ext_backlight_caps->data_points[i].luminance;
+			unsigned int signal_level =
+				backlight_8_to_16(
+					ext_backlight_caps->data_points[i].signal_level);
+
+			/* Since luminance is a percentage, scale it by num_levels*/
+			luminance = (luminance * num_levels) / 101;
+
+			/* Lineary interpolate missing values */
+			if (index < luminance) {
+				unsigned int base_value =
+					core_power->bl_prop[inst].backlight_lut[index-1];
+				unsigned int delta_signal =
+					signal_level - base_value;
+				unsigned int delta_luma =
+					luminance - index + 1;
+				unsigned int step  = delta_signal;
+
+				for (; index < luminance; index++) {
+					core_power->bl_prop[inst].backlight_lut[index] =
+						base_value + (step / delta_luma);
+					step += delta_signal;
+				}
+			}
+
+			/* Now [index == luminance],
+			 * so we can add data point to the translation table
+			 */
+			core_power->bl_prop[inst].backlight_lut[index++] = signal_level;
+		}
+
+		/* Complete the final segment of interpolation -
+		 * between last datapoint and maximum value
+		 */
+		if (index < num_levels - 1) {
+			unsigned int base_value =
+				core_power->bl_prop[inst].backlight_lut[index-1];
+			unsigned int delta_signal =
+				core_power->bl_prop[inst].backlight_lut[num_levels - 1] -
+								base_value;
+			unsigned int delta_luma = num_levels - index;
+			unsigned int step = delta_signal;
+
+			for (; index < num_levels - 1; index++) {
+				core_power->bl_prop[inst].backlight_lut[index] =
+						base_value + (step / delta_luma);
+				step += delta_signal;
+			}
+		}
+	/* Build backlight translation table based on default curve */
+	} else {
+		/* Defines default backlight curve F(x) = A(x*x) + Bx + C.
+		 *
+		 * Backlight curve should always  satisfy:
+		 * F(0) = min, F(100) = max,
+		 * So polynom coefficients are:
+		 * A is 0.0255 - B/100 - min/10000 - (255-max)/10000 =
+		 * (max - min)/10000 - B/100
+		 * B is adjustable factor to modify the curve.
+		 * Bigger B results in less concave curve.
+		 * B range is [0..(max-min)/100]
+		 * C is backlight minimum
+		 */
+		unsigned int backlight_curve_coeff_a_factor =
+				num_levels * num_levels;
+		unsigned int backlight_curve_coeff_b = num_levels;
+		unsigned int delta =
+			core_power->bl_prop[inst].backlight_lut[num_levels - 1] -
+				core_power->bl_prop[inst].backlight_lut[0];
+		unsigned int coeffC = core_power->bl_prop[inst].backlight_lut[0];
+		unsigned int coeffB =
+				(backlight_curve_coeff_b < delta ?
+					backlight_curve_coeff_b : delta);
+		unsigned long long coeffA = delta - coeffB; /* coeffB is B*100 */
+
+		for (i = 1; i < num_levels - 1; i++) {
+			uint64_t lut_val = div_u64(coeffA * i * i, backlight_curve_coeff_a_factor) +
+				div_u64((uint64_t)coeffB * i, backlight_curve_coeff_b) + coeffC;
+
+			ASSERT(lut_val <= 0xFFFFFFFF);
+			core_power->bl_prop[inst].backlight_lut[i] = (unsigned int)lut_val;
+		}
+	}
+
+	if (ext_backlight_caps != NULL)
+		kfree(ext_backlight_caps);
+
+	/* Successfully initialized */
+	core_power->bl_prop[inst].backlight_caps_valid = true;
+}
+
+static void varibright_set_level(struct core_power *core_power)
+{
+	if (!core_power->varibright_prop.varibright_active ||
+		!core_power->varibright_prop.varibright_user_enable)
+		core_power->varibright_prop.varibright_hw_level = 0;
+	else
+		core_power->varibright_prop.varibright_hw_level =
+			core_power->varibright_prop.varibright_level;
+}
+
+bool mod_power_hw_init(struct mod_power *mod_power)
+{
+	struct core_power *core_power = NULL;
+	struct dc *dc = NULL;
+	struct dmcu *dmcu = NULL;
+	struct dmcu_iram_parameters params;
+	int i;
+
+	if (mod_power == NULL)
+		return false;
+
+	core_power = MOD_POWER_TO_CORE(mod_power);
+	dc = core_power->dc;
+
+	for (i = 0; i < core_power->edp_num; i++) {
+		params.set = core_power->varibright_prop.varibright_config_setting;
+		params.backlight_ramping_override = core_power->bl_prop[i].backlight_ramping_override;
+		params.backlight_ramping_reduction = core_power->bl_prop[i].backlight_ramping_reduction;
+		params.backlight_ramping_start = core_power->bl_prop[i].backlight_ramping_start;
+		params.backlight_lut_array = core_power->bl_prop[i].backlight_lut;
+		params.backlight_lut_array_size = core_power->bl_prop[i].num_backlight_levels;
+		params.min_abm_backlight = core_power->bl_prop[i].min_abm_backlight;
+
+		dmcu = dc->res_pool->dmcu;
+
+		// In the case where abm is implemented on dmcub,
+		// dmcu object will be null.
+		// ABM 2.4 and up are implemented on dmcub.
+		if (dmcu) {
+			//DMCU does not support multiple eDP
+			return dmcu_load_iram(dmcu, params);
+		} else if (dc->ctx->dmub_srv) {
+			if (!dmub_init_abm_config(dc->res_pool, params, i))
+				return false;
+		} else
+			return false;
+	}
+	return true;
+}
+
+struct mod_power *mod_power_create(struct dc *dc,
+		struct mod_power_init_params *init_params,
+		unsigned int edp_num)
+{
+	struct core_power *core_power = NULL;
+	int i = 0;
+	int abm_max_config = 0;
+	unsigned int inst = 0;
+	bool is_brightness_range_valid = false;
+
+	if (dc == NULL)
+		goto fail_dc_null;
+
+	core_power = kzalloc(sizeof(struct core_power), GFP_KERNEL);
+
+	if (core_power == NULL)
+		goto fail_alloc_context;
+
+	core_power->edp_num = edp_num;
+	core_power->map = kzalloc(sizeof(struct power_entity) * MOD_POWER_MAX_CONCURRENT_STREAMS,
+				  GFP_KERNEL);
+
+	if (core_power->map == NULL)
+		goto fail_alloc_map;
+
+	for (i = 0; i < MOD_POWER_MAX_CONCURRENT_STREAMS; i++) {
+		core_power->map[i].stream = NULL;
+	}
+
+	for (i = 0; i < MOD_POWER_MAX_CONCURRENT_STREAMS; i++) {
+		core_power->map[i].psr_context =
+				kzalloc(sizeof(struct mod_power_psr_context),
+					GFP_KERNEL);
+		if (core_power->map[i].psr_context == NULL)
+			goto fail_construct;
+	}
+
+	core_power->psr_smu_optimizations_support = init_params->allow_psr_smu_optimizations;
+	core_power->multi_disp_optimizations_support = init_params->allow_psr_multi_disp_optimizations;
+
+	for (inst = 0; inst < edp_num; inst++) {
+		core_power->bl_prop[inst].min_abm_backlight =
+				init_params[inst].min_abm_backlight;
+		core_power->bl_prop[inst].disable_fractional_pwm =
+				init_params[inst].disable_fractional_pwm;
+		core_power->bl_prop[inst].use_linear_backlight_curve =
+				init_params[inst].use_linear_backlight_curve;
+		core_power->bl_prop[inst].use_nits_based_brightness =
+				init_params[inst].use_nits_based_brightness;
+		core_power->bl_prop[inst].backlight_ramping_override =
+				init_params[inst].backlight_ramping_override;
+		core_power->bl_prop[inst].backlight_ramping_reduction =
+				init_params[inst].backlight_ramping_reduction;
+		core_power->bl_prop[inst].backlight_ramping_start =
+				init_params[inst].backlight_ramping_start;
+		core_power->bl_prop[inst].use_custom_backlight_caps =
+				init_params[inst].use_custom_backlight_caps;
+		core_power->bl_prop[inst].custom_backlight_caps_config_no =
+				init_params[inst].custom_backlight_caps_config_no;
+
+		// Do not allow less than 101 backlight levels
+		if (init_params[inst].num_backlight_levels < 101)
+			core_power->bl_prop[inst].num_backlight_levels = 101;
+		else
+			core_power->bl_prop[inst].num_backlight_levels =
+				init_params[inst].num_backlight_levels;
+
+		core_power->bl_prop[inst].backlight_lut = (unsigned int *)
+				(kzalloc(sizeof(unsigned int) *
+				core_power->bl_prop[inst].num_backlight_levels, GFP_KERNEL));
+		if (core_power->bl_prop[inst].backlight_lut == NULL)
+			goto fail_alloc_backlight_array;
+	}
+
+	core_power->varibright_prop.varibright_active = false;
+
+	core_power->varibright_prop.varibright_user_enable =
+			init_params->def_varibright_enable;
+
+	// Table of ABM levels here is 1-4, but level 0 also exists as 'off'
+	if (init_params->varibright_level <= abm_defines_max_level) {
+		core_power->varibright_prop.varibright_level =
+			init_params->varibright_level;
+
+	} else {
+		core_power->varibright_prop.varibright_level = 3;
+	}
+	if (init_params->def_varibright_level <= abm_defines_max_level) {
+		core_power->varibright_prop.def_varibright_level =
+			init_params->def_varibright_level;
+	} else {
+		core_power->varibright_prop.def_varibright_level = 3;
+	}
+
+	// ABM used to contain 4 different configs. There is only 3 since ABM 2.3.
+	if ((dc->res_pool->dmcu != NULL) && (dc->res_pool->dmcu->dmcu_version.abm_version < 0x23))
+		abm_max_config = 4;
+	else
+		abm_max_config = 3;
+
+	if (init_params->abm_config_setting < abm_max_config)
+		core_power->varibright_prop.varibright_config_setting =
+			init_params->abm_config_setting;
+	else
+		core_power->varibright_prop.varibright_config_setting = 0;
+
+	for (inst = 0; inst < edp_num; inst++) {
+		core_power->bl_prop[inst].backlight_lut[0] = init_params[inst].min_backlight_pwm;
+		core_power->bl_prop[inst].backlight_lut[
+			core_power->bl_prop[inst].num_backlight_levels-1] =
+				init_params[inst].max_backlight_pwm;
+		core_power->bl_prop[inst].min_backlight_pwm = init_params[inst].min_backlight_pwm;
+		core_power->bl_prop[inst].max_backlight_pwm = init_params[inst].max_backlight_pwm;
+		core_power->bl_prop[inst].ac_backlight_percent =
+				default_ac_backlight_percent;
+		core_power->bl_prop[inst].dc_backlight_percent =
+				default_dc_backlight_percent;
+		core_power->bl_prop[inst].backlight_caps_valid = false;
+
+		if (core_power->bl_prop[inst].use_nits_based_brightness) {
+			core_power->bl_prop[inst].min_brightness_millinits =
+					init_params[inst].panel_min_millinits;
+			core_power->bl_prop[inst].max_brightness_millinits =
+					init_params[inst].panel_max_millinits;
+		} else {
+
+			core_power->bl_prop[inst].min_brightness_millinits =
+					pwr_default_min_brightness_millinits;
+			core_power->bl_prop[inst].max_brightness_millinits =
+					pwr_default_sdr_brightness_millinits;
+		}
+
+		core_power->bl_prop[inst].backlight_range =
+				core_power->bl_prop[inst].max_backlight_pwm-
+				core_power->bl_prop[inst].min_backlight_pwm;
+
+		core_power->bl_prop[inst].nits_range =
+				core_power->bl_prop[inst].max_brightness_millinits -
+				core_power->bl_prop[inst].min_brightness_millinits;
+
+		core_power->bl_state[inst].smooth_brightness_enabled = true;
+	}
+
+	/* Check if at least 1 instance in core_power is populated before failing */
+	for (inst = 0; inst < edp_num; inst++) {
+		if (core_power->bl_prop[inst].nits_range != 0 && core_power->bl_prop[inst].backlight_range != 0) {
+			is_brightness_range_valid = true;
+			break;
+		}
+
+	}
+	if (!is_brightness_range_valid)
+		goto fail_bad_brightness_range;
+
+	core_power->num_entities = 0;
+
+	core_power->dc = dc;
+	for (inst = 0; inst < edp_num; inst++) {
+		initialize_backlight_caps(core_power, inst);
+		core_power->bl_state[inst].backlight_millipercent =
+			core_power->bl_prop[inst].dc_backlight_percent * 1000;
+		core_power->bl_state[inst].backlight_pwm = backlight_millipercent_to_pwm(core_power,
+		core_power->bl_state[inst].backlight_millipercent, inst);
+		core_power->bl_state[inst].backlight_millinit = backlight_millipercent_to_millinit(core_power,
+		core_power->bl_state[inst].backlight_millipercent, inst);
+	}
+
+	return &core_power->public;
+
+fail_bad_brightness_range:
+fail_alloc_backlight_array:
+	for (inst = 0; inst < edp_num; inst++)
+		if (core_power->bl_prop[inst].backlight_lut)
+			kfree(core_power->bl_prop[inst].backlight_lut);
+fail_construct:
+	for (i = 0; i < MOD_POWER_MAX_CONCURRENT_STREAMS; i++) {
+		if (core_power->map[i].psr_context)
+			kfree(core_power->map[i].psr_context);
+	}
+	kfree(core_power->map);
+
+fail_alloc_map:
+	kfree(core_power);
+
+fail_alloc_context:
+fail_dc_null:
+	return NULL;
+}
+
+void mod_power_destroy(struct mod_power *mod_power)
+{
+	if (mod_power != NULL) {
+		int i;
+		struct core_power *core_power =
+				MOD_POWER_TO_CORE(mod_power);
+
+		for (i = 0; i < MOD_POWER_MAX_CONCURRENT_STREAMS; i++)
+			if (core_power->map[i].psr_context)
+				kfree(core_power->map[i].psr_context);
+
+		for (i = 0; i < core_power->num_entities; i++)
+			if (core_power->map[i].stream)
+				dc_stream_release(core_power->map[i].stream);
+
+		kfree(core_power->map);
+
+		for (i = 0; i < MAX_NUM_EDP; i++)
+			if (core_power->bl_prop[i].backlight_lut)
+				kfree(core_power->bl_prop[i].backlight_lut);
+
+		kfree(core_power);
+	}
+}
+
+bool mod_power_add_stream(struct mod_power *mod_power,
+		struct dc_stream_state *stream, struct psr_caps *caps)
+{
+	struct core_power *core_power = NULL;
+
+	if (mod_power == NULL)
+		return false;
+
+	core_power = MOD_POWER_TO_CORE(mod_power);
+
+	if (core_power->num_entities < MOD_POWER_MAX_CONCURRENT_STREAMS) {
+		dc_stream_retain(stream);
+
+		core_power->map[core_power->num_entities].stream = stream;
+		core_power->map[core_power->num_entities].caps = caps;
+
+		// initialize cached PSR params to something "safe" (something that is
+		// consistent with disabled PSR state)
+		core_power->map[core_power->num_entities].psr_enabled = 0;
+		core_power->map[core_power->num_entities].psr_events = psr_event_vsync;
+		core_power->map[core_power->num_entities].psr_power_opt = 0;
+		core_power->num_entities++;
+		return true;
+	}
+
+	DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_ERROR,
+						WPP_BIT_FLAG_Firmware_PsrState,
+						"mod_power: add_stream: ERROR: stream=%p num_entities=%d >= MOD_POWER_MAX_CONCURRENT_STREAMS",
+						stream,
+						core_power->num_entities);
+
+	return false;
+}
+
+bool mod_power_remove_stream(struct mod_power *mod_power,
+		const struct dc_stream_state *stream)
+{
+	int i = 0;
+	struct core_power *core_power = NULL;
+	unsigned int index = 0;
+
+	if (mod_power == NULL)
+		return false;
+
+	core_power = MOD_POWER_TO_CORE(mod_power);
+	if (core_power->num_entities == 0) {
+		/* trying to remove a stream a second time or have not added yet */
+		BREAK_TO_DEBUGGER();
+		DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_ERROR,
+							WPP_BIT_FLAG_Firmware_PsrState,
+							"mod_power: remove_stream: ERROR: num_entities=0 stream=%p",
+							stream);
+		return false;
+	}
+
+	index = map_index_from_stream(core_power, stream);
+
+	if (index >= core_power->num_entities) {
+		/* trying to remove a stream a second time or have not added yet */
+		BREAK_TO_DEBUGGER();
+		DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_ERROR,
+							WPP_BIT_FLAG_Firmware_PsrState,
+							"mod_power: remove_stream: ERROR: index=%u >= num_entities=%d stream=%p",
+							index,
+							core_power->num_entities,
+							stream);
+		return false;
+	}
+
+	dc_stream_release(core_power->map[index].stream);
+	core_power->map[index].stream = NULL;
+	/* To remove this entity, shift everything after down */
+	for (i = index; i < core_power->num_entities - 1; i++) {
+		core_power->map[i].stream = core_power->map[i + 1].stream;
+		core_power->map[i].caps = core_power->map[i + 1].caps;
+
+		// copy over cached parameters in case they map to PSR capable display
+		core_power->map[i].psr_enabled = core_power->map[i + 1].psr_enabled;
+		core_power->map[i].psr_events = core_power->map[i + 1].psr_events;
+		core_power->map[i].psr_power_opt = core_power->map[i + 1].psr_power_opt;
+
+		memcpy(core_power->map[i].psr_context, core_power->map[i + 1].psr_context, sizeof(struct mod_power_psr_context));
+		memset(core_power->map[i + 1].psr_context, 0, sizeof(struct mod_power_psr_context));
+	}
+	core_power->num_entities--;
+
+	return true;
+}
+
+/*
+ * Replace_stream should be used when there is a mode set for existing
+ * display target with a valid stream. In this case might need to retain
+ * cached PSR state (events, power opt, en/dis) if we are dealing with PSR
+ * capable display. If mod_power_remove and mod_power_add are used instead,
+ * then stream may be assigned to a different slot and may end up with
+ * wrong cached PSR state. It is hard to tell which PSR events should
+ * persist through mode set or what psr_events should be initialized to, so
+ * it might be better just to retain them all.
+ */
+bool mod_power_replace_stream(struct mod_power *mod_power,
+		const struct dc_stream_state *current_stream,
+		struct dc_stream_state *new_stream,
+		struct psr_caps *new_caps)
+{
+	struct core_power *core_power = NULL;
+	unsigned int index = 0;
+
+	if (mod_power == NULL)
+		return false;
+
+	core_power = MOD_POWER_TO_CORE(mod_power);
+	if (core_power->num_entities == 0) {
+		/* no streams exist in the table yet */
+		BREAK_TO_DEBUGGER();
+		DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_ERROR,
+							WPP_BIT_FLAG_Firmware_PsrState,
+							"mod_power: replace_stream: ERROR: num_entities=0 stream=%p",
+							current_stream);
+		return false;
+	}
+
+	index = map_index_from_stream(core_power, current_stream);
+
+	if (index >= core_power->num_entities) {
+		/* trying to replace a non-existent stream */
+		BREAK_TO_DEBUGGER();
+		DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_ERROR,
+							WPP_BIT_FLAG_Firmware_PsrState,
+							"mod_power: replace_stream: ERROR: index=%u >= num_entities=%d stream=%p",
+							index,
+							core_power->num_entities,
+							current_stream);
+		return false;
+	}
+
+	dc_stream_release(core_power->map[index].stream);
+	dc_stream_retain(new_stream);
+	core_power->map[index].stream = new_stream;
+	core_power->map[index].caps = new_caps;
+	memset(core_power->map[index].psr_context, 0, sizeof(struct mod_power_psr_context));
+
+	return true;
+}
+
+static bool set_backlight_millinits_aux(struct core_power *core_power,
+		struct dc_stream_state *stream,
+		unsigned int backlight_millinits,
+		unsigned int transition_time_millisec,
+		unsigned int inst)
+{
+	struct dc_link *link = NULL;
+
+	if (core_power == NULL)
+		return false;
+
+	if (stream == NULL)
+		return true;
+
+	link = dc_stream_get_link(stream);
+
+	return dc_link_set_backlight_level_nits(link, core_power->bl_state[inst].isHDR,
+			backlight_millinits, transition_time_millisec);
+}
+
+static bool set_backlight(struct core_power *core_power,
+		struct dc_stream_state *stream,
+		struct set_backlight_level_params *backlight_level_params,
+		unsigned int inst)
+{
+	bool retv = false;
+	unsigned int frame_ramp = 0;
+	unsigned int vsync_rate_hz;
+	union dmcu_abm_set_bl_params params;
+	const struct dc_link *link = NULL;
+	unsigned int backlight_pwm_u16_16 = backlight_level_params->backlight_pwm_u16_16;
+	unsigned int transition_time_millisec = backlight_level_params->transition_time_in_ms;
+
+	if (core_power == NULL)
+		return false;
+
+	core_power->bl_state[inst].backlight_pwm = backlight_pwm_u16_16;
+
+	if (stream == NULL)
+		return true;
+
+	if (stream->link->connector_signal != SIGNAL_TYPE_EDP)
+		return false;
+
+	if (transition_time_millisec != 0) {
+		unsigned int v_total =
+			(stream->adjust.v_total_max == 0) ? stream->timing.v_total : stream->adjust.v_total_max;
+
+		vsync_rate_hz = (unsigned int)div_u64(div_u64((stream->
+			timing.pix_clk_100hz * 100),
+			v_total),
+			stream->timing.h_total);
+
+		if (core_power->bl_state[inst].smooth_brightness_enabled)
+			frame_ramp = ((vsync_rate_hz *
+				transition_time_millisec) + 500) / 1000;
+	}
+
+	core_power->bl_state[inst].frame_ramp = frame_ramp;
+	params.u32All = 0;
+	params.bits.gradual_change = (frame_ramp > 0);
+	params.bits.frame_ramp = frame_ramp;
+	link = dc_stream_get_link(stream);
+
+	mod_power_set_psr_event(&core_power->public, stream, true, psr_event_hw_programming, true);
+	mod_power_set_replay_event(&core_power->public, stream, true, replay_event_hw_programming, true);
+
+	backlight_level_params->frame_ramp = params.u32All;
+	retv = dc_link_set_backlight_level(link, backlight_level_params);
+
+	mod_power_set_psr_event(&core_power->public, stream, false, psr_event_hw_programming, false);
+	mod_power_set_replay_event(&core_power->public, stream, false, replay_event_hw_programming, false);
+
+	return retv;
+}
+
+static void fill_backlight_level_params(struct core_power *core_power,
+	struct set_backlight_level_params *backlight_level_params,
+	int panel_inst, uint8_t aux_inst, unsigned int backlight_pwm,
+	enum backlight_control_type backlight_control_type,
+	unsigned int backlight_millinit, unsigned int transition_time_millisec,
+	bool is_hdr)
+{
+	struct backlight_properties *bl_prop = &core_power->bl_prop[panel_inst];
+
+	backlight_level_params->aux_inst = aux_inst;
+	backlight_level_params->backlight_pwm_u16_16 = backlight_pwm;
+	backlight_level_params->control_type = backlight_control_type;
+	backlight_level_params->backlight_millinits = backlight_millinit;
+	backlight_level_params->transition_time_in_ms = transition_time_millisec;
+	backlight_level_params->min_luminance = bl_prop->min_brightness_millinits;
+	backlight_level_params->max_luminance = bl_prop->max_brightness_millinits;
+	backlight_level_params->min_backlight_pwm = bl_prop->min_backlight_pwm;
+	backlight_level_params->max_backlight_pwm = bl_prop->max_backlight_pwm;
+
+	if (backlight_control_type == BACKLIGHT_CONTROL_AMD_AUX && !is_hdr)
+		backlight_level_params->control_type = BACKLIGHT_CONTROL_PWM;
+}
+
+bool mod_power_set_backlight_nits(struct mod_power *mod_power,
+		struct dc_stream_state *stream,
+		unsigned int backlight_millinit,
+		unsigned int transition_time_millisec,
+		bool skip_aux,
+		bool is_hdr)
+{
+	struct core_power *core_power = NULL;
+	unsigned int backlight_pwm;
+	unsigned int panel_inst = 0;
+	struct set_backlight_level_params backlight_level_params = { 0 };
+	const struct dc_link *link = NULL;
+	uint8_t aux_inst = 0;
+
+	if (mod_power == NULL)
+		return false;
+
+	core_power = MOD_POWER_TO_CORE(mod_power);
+	link = dc_stream_get_link(stream);
+
+	ASSERT(link->ddc->ddc_pin->hw_info.ddc_channel <= 0xFF);
+	aux_inst = (uint8_t)link->ddc->ddc_pin->hw_info.ddc_channel;
+
+	if (!dc_get_edp_link_panel_inst(core_power->dc, stream->link, &panel_inst))
+		return false;
+
+	if (!skip_aux) {
+		if (!set_backlight_millinits_aux(core_power, stream,
+						backlight_millinit, transition_time_millisec, panel_inst))
+			return false;
+	}
+// always send both AUX (above) and PWM (below)
+	core_power->bl_state[panel_inst].backlight_millinit = backlight_millinit;
+
+	core_power->bl_state[panel_inst].backlight_millipercent =
+		backlight_millinit_to_millipercent(
+				core_power, backlight_millinit, panel_inst);
+
+	backlight_pwm = backlight_millinit_to_pwm(
+				core_power, backlight_millinit, panel_inst);
+
+	fill_backlight_level_params(core_power, &backlight_level_params, panel_inst, aux_inst, backlight_pwm,
+		link->backlight_control_type, backlight_millinit, transition_time_millisec, is_hdr);
+
+	return set_backlight(core_power, stream,
+			&backlight_level_params, panel_inst);
+}
+
+
+bool mod_power_backlight_percent_to_nits(struct mod_power *mod_power,
+		struct dc_stream_state *stream,
+		unsigned int backlight_millipercent,
+		unsigned int *backlight_millinit)
+{
+	struct core_power *core_power = NULL;
+	unsigned int inst = 0;
+
+	if (mod_power == NULL)
+		return false;
+
+	core_power = MOD_POWER_TO_CORE(mod_power);
+
+	if (!dc_get_edp_link_panel_inst(core_power->dc, stream->link, &inst))
+		return false;
+
+	*backlight_millinit = backlight_millipercent_to_millinit(
+			core_power, backlight_millipercent, inst);
+	return true;
+}
+
+bool mod_power_backlight_nits_to_percent(struct mod_power *mod_power,
+		struct dc_stream_state *stream,
+		unsigned int backlight_millinit,
+		unsigned int *backlight_millipercent)
+{
+	struct core_power *core_power = NULL;
+	unsigned int inst = 0;
+
+	if (mod_power == NULL)
+		return false;
+
+	core_power = MOD_POWER_TO_CORE(mod_power);
+
+	if (!dc_get_edp_link_panel_inst(core_power->dc, stream->link, &inst))
+		return false;
+
+	*backlight_millipercent = backlight_millinit_to_millipercent(
+			core_power, backlight_millinit, inst);
+	return true;
+}
+
+bool mod_power_set_backlight_percent(struct mod_power *mod_power,
+		struct dc_stream_state *stream,
+		unsigned int backlight_millipercent,
+		unsigned int transition_time_millisec,
+		bool is_hdr)
+{
+	struct core_power *core_power = NULL;
+	struct set_backlight_level_params backlight_level_params = { 0 };
+	const struct dc_link *link = NULL;
+	unsigned int backlight_pwm;
+	unsigned int panel_inst = 0;
+	uint8_t aux_inst = 0;
+
+	if (mod_power == NULL)
+		return false;
+
+	core_power = MOD_POWER_TO_CORE(mod_power);
+	link = dc_stream_get_link(stream);
+	ASSERT(link->ddc->ddc_pin->hw_info.ddc_channel <= 0xFF);
+	aux_inst = (uint8_t)link->ddc->ddc_pin->hw_info.ddc_channel;
+
+	if (!dc_get_edp_link_panel_inst(core_power->dc, stream->link, &panel_inst))
+		return false;
+	core_power->bl_state[panel_inst].backlight_millipercent = backlight_millipercent;
+
+	core_power->bl_state[panel_inst].backlight_millinit =
+		backlight_millipercent_to_millinit(
+				core_power, backlight_millipercent, panel_inst);
+
+	backlight_pwm = backlight_millipercent_to_pwm(
+				core_power, backlight_millipercent, panel_inst);
+
+	fill_backlight_level_params(core_power, &backlight_level_params, panel_inst,
+		aux_inst, backlight_pwm, link->backlight_control_type,
+		core_power->bl_state[panel_inst].backlight_millinit, transition_time_millisec, is_hdr);
+
+	return set_backlight(core_power, stream,
+			&backlight_level_params, panel_inst);
+}
+
+void mod_power_update_backlight(struct mod_power *mod_power,
+		struct dc_stream_state *stream,
+		unsigned int backlight_millipercent)
+{
+	struct core_power *core_power = NULL;
+	unsigned int inst = 0;
+
+	if (mod_power == NULL)
+		return;
+
+	core_power = MOD_POWER_TO_CORE(mod_power);
+
+	if (!dc_get_edp_link_panel_inst(core_power->dc, stream->link, &inst))
+		return;
+	core_power->bl_state[inst].backlight_millipercent = backlight_millipercent;
+
+	core_power->bl_state[inst].backlight_millinit =
+		backlight_millipercent_to_millinit(
+			core_power, backlight_millipercent, inst);
+
+	core_power->bl_state[inst].backlight_pwm = backlight_millipercent_to_pwm(
+		core_power, backlight_millipercent, inst);
+}
+
+void mod_power_update_backlight_nits(struct mod_power *mod_power,
+		struct dc_stream_state *stream,
+		unsigned int backlight_millinit)
+{
+	struct core_power *core_power = NULL;
+	unsigned int inst = 0;
+
+	if (mod_power == NULL)
+		return;
+
+	core_power = MOD_POWER_TO_CORE(mod_power);
+
+	if (!dc_get_edp_link_panel_inst(core_power->dc, stream->link, &inst))
+		return;
+
+	core_power->bl_state[inst].backlight_millinit = backlight_millinit;
+
+	core_power->bl_state[inst].backlight_millipercent = backlight_millinit_to_millipercent(
+		core_power, backlight_millinit, inst);
+	core_power->bl_state[inst].backlight_pwm = backlight_millinit_to_pwm(
+		core_power, backlight_millinit, inst);
+}
+
+bool mod_power_get_backlight_pwm(struct mod_power *mod_power,
+		unsigned int *backlight_pwm,
+		unsigned int inst)
+{
+	struct core_power *core_power = NULL;
+
+	if (mod_power == NULL)
+		return false;
+
+	core_power = MOD_POWER_TO_CORE(mod_power);
+
+	*backlight_pwm = core_power->bl_state[inst].backlight_pwm;
+
+	return true;
+}
+
+bool mod_power_get_backlight_nits(struct mod_power *mod_power,
+		unsigned int *backlight_millinit,
+		unsigned int inst)
+{
+	struct core_power *core_power = NULL;
+
+	if (mod_power == NULL)
+		return false;
+
+	core_power = MOD_POWER_TO_CORE(mod_power);
+
+	*backlight_millinit = core_power->bl_state[inst].backlight_millinit;
+
+	return true;
+}
+
+bool mod_power_get_backlight_percent(struct mod_power *mod_power,
+		unsigned int *backlight_millipercent,
+		unsigned int inst)
+{
+	struct core_power *core_power = NULL;
+
+	if (mod_power == NULL)
+		return false;
+
+	core_power = MOD_POWER_TO_CORE(mod_power);
+
+	*backlight_millipercent = core_power->bl_state[inst].backlight_millipercent;
+
+	return true;
+}
+
+bool mod_power_get_hw_target_backlight_pwm_nits(struct mod_power *mod_power,
+		const struct dc_link *link,
+		unsigned int *backlight_millinit,
+		unsigned int inst)
+{
+	struct core_power *core_power = NULL;
+	unsigned int backlight_u16_16 = 0;
+
+	if (mod_power == NULL)
+		return false;
+
+	core_power = MOD_POWER_TO_CORE(mod_power);
+
+	if (mod_power_get_hw_target_backlight_pwm(mod_power, link,
+							&backlight_u16_16)) {
+		*backlight_millinit =
+			backlight_pwm_to_millinit(core_power,
+					backlight_u16_16, inst);
+		return true;
+	}
+	return false;
+}
+
+bool mod_power_get_hw_target_backlight_pwm_percent(struct mod_power *mod_power,
+		const struct dc_link *link,
+		unsigned int *backlight_millipercent,
+		unsigned int inst)
+{
+	struct core_power *core_power = NULL;
+	unsigned int backlight_u16_16 = 0;
+
+	if (mod_power == NULL)
+		return false;
+
+	core_power = MOD_POWER_TO_CORE(mod_power);
+
+	if (mod_power_get_hw_target_backlight_pwm(mod_power, link,
+							&backlight_u16_16)) {
+		*backlight_millipercent =
+			backlight_pwm_to_millipercent(core_power,
+					backlight_u16_16, inst);
+		return true;
+	}
+	return false;
+}
+
+bool mod_power_get_hw_target_backlight_pwm(struct mod_power *mod_power,
+		const struct dc_link *link,
+		unsigned int *backlight_u16_16)
+{
+	if (mod_power == NULL)
+		return false;
+
+	*backlight_u16_16 = dc_link_get_target_backlight_pwm(link);
+
+	return true;
+}
+
+bool mod_power_get_hw_backlight_pwm_nits(struct mod_power *mod_power,
+		const struct dc_link *link,
+		unsigned int *backlight_millinit,
+		unsigned int inst)
+{
+	struct core_power *core_power = NULL;
+	unsigned int backlight_u16_16 = 0;
+
+	if (mod_power == NULL)
+		return false;
+
+	core_power = MOD_POWER_TO_CORE(mod_power);
+
+	if (mod_power_get_hw_backlight_pwm(mod_power, link, &backlight_u16_16)) {
+		*backlight_millinit =
+			backlight_pwm_to_millinit(core_power,
+					backlight_u16_16, inst);
+		return true;
+	}
+	return false;
+}
+
+bool mod_power_get_hw_backlight_aux_nits(struct mod_power *mod_power,
+		struct dc_stream_state **streams, int num_streams,
+		unsigned int *backlight_millinit_avg,
+		unsigned int *backlight_millinit_peak)
+{
+	struct core_power *core_power = NULL;
+	struct dc_link *link = NULL;
+	unsigned int stream_index;
+
+	if (mod_power == NULL)
+		return false;
+
+	core_power = MOD_POWER_TO_CORE(mod_power);
+
+	if (core_power == NULL)
+		return false;
+
+	if (num_streams < 1)
+		return true;
+
+	for (stream_index = 0; stream_index < num_streams; stream_index++)
+		if (streams[stream_index]->link->connector_signal == SIGNAL_TYPE_EDP ||
+				streams[stream_index]->link->connector_signal == SIGNAL_TYPE_DISPLAY_PORT)
+			break;
+
+	if (stream_index == num_streams)
+		return false;
+
+	link = dc_stream_get_link(streams[stream_index]);
+	if (link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 0)
+		return false;
+
+	return dc_link_get_backlight_level_nits(link, backlight_millinit_avg,
+			backlight_millinit_peak);
+}
+
+bool mod_power_get_hw_backlight_pwm_percent(struct mod_power *mod_power,
+		const struct dc_link *link,
+		unsigned int *backlight_millipercent,
+		unsigned int inst)
+{
+	struct core_power *core_power = NULL;
+	unsigned int backlight_u16_16 = 0;
+
+	if (mod_power == NULL)
+		return false;
+
+	core_power = MOD_POWER_TO_CORE(mod_power);
+
+	if (mod_power_get_hw_backlight_pwm(mod_power, link, &backlight_u16_16)) {
+		*backlight_millipercent =
+			backlight_pwm_to_millipercent(core_power,
+					backlight_u16_16, inst);
+		return true;
+	}
+	return false;
+}
+
+bool mod_power_get_hw_backlight_pwm(struct mod_power *mod_power,
+		const struct dc_link *link,
+		unsigned int *backlight_u16_16)
+{
+	if (mod_power == NULL)
+		return false;
+
+	*backlight_u16_16 = dc_link_get_backlight_level(link);
+
+	return true;
+}
+
+bool mod_power_get_panel_backlight_boundaries(
+				struct mod_power *mod_power,
+				unsigned int *out_min_backlight,
+				unsigned int *out_max_backlight,
+				unsigned int *out_ac_backlight_percent,
+				unsigned int *out_dc_backlight_percent,
+				unsigned int inst)
+{
+	struct core_power *core_power = NULL;
+
+	if (mod_power == NULL)
+		return false;
+
+	core_power = MOD_POWER_TO_CORE(mod_power);
+
+	/* If cache was successfully updated,
+	 * copy the values to output structure and return success
+	 */
+	if (core_power->bl_prop[inst].backlight_caps_valid) {
+		*out_min_backlight = core_power->bl_prop[inst].backlight_lut[0];
+		*out_max_backlight =
+			core_power->bl_prop[inst].backlight_lut[
+				core_power->bl_prop[inst].num_backlight_levels - 1];
+		*out_ac_backlight_percent =
+			core_power->bl_prop[inst].ac_backlight_percent;
+		*out_dc_backlight_percent =
+			core_power->bl_prop[inst].dc_backlight_percent;
+
+		return true;
+	}
+
+	return false;
+}
+
+bool mod_power_set_smooth_brightness(struct mod_power *mod_power,
+		bool enable_brightness,
+		unsigned int inst)
+{
+	struct core_power *core_power = NULL;
+
+	if (mod_power == NULL)
+		return false;
+
+	core_power = MOD_POWER_TO_CORE(mod_power);
+
+	core_power->bl_state[inst].smooth_brightness_enabled = enable_brightness;
+
+	return true;
+}
+
+bool mod_power_notify_mode_change(struct mod_power *mod_power,
+		const struct dc_stream_state *stream,
+		bool is_hdr)
+{
+	unsigned int stream_index = 0;
+	struct core_power *core_power = NULL;
+	struct dc_link *link = NULL;
+	struct psr_config psr_config = {0};
+	struct psr_context psr_context = {0};
+	struct dc *dc = NULL;
+	unsigned int panel_inst = 0;
+	int active_psr_events = 0;
+	int active_replay_events = 0;
+
+	if ((mod_power == NULL) || (stream == NULL))
+		return false;
+
+	core_power = MOD_POWER_TO_CORE(mod_power);
+
+	if (core_power->num_entities == 0)
+		return false;
+
+	stream_index = map_index_from_stream(core_power, stream);
+
+	if (stream_index >= core_power->num_entities)
+		return false;
+
+	dc = core_power->dc;
+	link = dc_stream_get_link(stream);
+	active_psr_events = core_power->map[stream_index].psr_events;
+	active_replay_events = core_power->map[stream_index].replay_events;
+	if (link != NULL && dc_get_edp_link_panel_inst(dc, link, &panel_inst)) {
+		struct set_backlight_level_params backlight_level_params = { 0 };
+
+		ASSERT(link->ddc->ddc_pin->hw_info.ddc_channel <= 0xFF);
+		uint8_t aux_inst = (uint8_t)link->ddc->ddc_pin->hw_info.ddc_channel;
+
+		if (link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1 ||
+			link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1)
+			dc_link_set_backlight_level_nits(link, core_power->bl_state[panel_inst].isHDR,
+				core_power->bl_state[panel_inst].backlight_millinit, 0);
+
+		backlight_level_params.frame_ramp = 0;
+
+		fill_backlight_level_params(core_power, &backlight_level_params, panel_inst, aux_inst,
+			core_power->bl_state[panel_inst].backlight_pwm, link->backlight_control_type,
+			core_power->bl_state[panel_inst].backlight_millinit, 0, is_hdr);
+
+		dc_link_set_backlight_level(link, &backlight_level_params);
+
+		mod_power_calc_psr_configs(&psr_config, link, stream);
+
+		psr_config.psr_exit_link_training_required = core_power->map[stream_index].caps->psr_exit_link_training_required;
+
+		if (dc->ctx->asic_id.chip_family >= AMDGPU_FAMILY_GC_11_0_1)
+			psr_config.allow_smu_optimizations =
+					core_power->psr_smu_optimizations_support && dc_is_embedded_signal(stream->signal);
+		else
+			psr_config.allow_smu_optimizations =
+					core_power->psr_smu_optimizations_support && mod_power_only_edp(dc->current_state, stream);
+
+		psr_config.allow_multi_disp_optimizations = core_power->multi_disp_optimizations_support;
+
+		psr_config.rate_control_caps = core_power->map[stream_index].caps->rate_control_caps;
+
+		if (active_psr_events & psr_event_os_request_force_ffu) {
+			psr_config.os_request_force_ffu = true;
+		}
+		/*
+		* DSC support:
+		* DSC slice height value must be 'mod' by su_y_granularity.
+		* According to Panel Vendor, there might be varied conditions to fulfill.
+		* Right now, DSC slice height value must be multiple of su_y_granularity.
+		*
+		* The value of DSC slice height is determined in DSC Driver but it does not
+		* propagated out here, so we need to calculate it as below 'slice_height'.
+		*/
+		psr_su_set_dsc_slice_height(dc, link,
+					(struct dc_stream_state *) stream,
+					&psr_config);
+
+		dc_link_setup_psr(link, stream, &psr_config, &psr_context);
+
+		link->replay_settings.replay_smu_opt_enable =
+			(link->replay_settings.config.replay_smu_opt_supported &&
+			mod_power_only_edp(dc->current_state, stream));
+
+		if (active_replay_events & replay_event_os_request_force_ffu) {
+			link->replay_settings.config.os_request_force_ffu = true;
+		}
+
+		if (dc_is_embedded_signal(stream->signal))
+			dc->link_srv->dp_setup_replay(link, stream);
+	}
+
+	return true;
+}
+
+bool mod_power_varibright_feature_enable(struct mod_power *mod_power, bool enable,
+		struct dc_stream_update *stream_update)
+{
+	struct core_power *core_power = NULL;
+
+	if (mod_power == NULL)
+		return false;
+
+	core_power = MOD_POWER_TO_CORE(mod_power);
+	core_power->varibright_prop.varibright_user_enable = enable;
+
+	/* find abm hw level to program, and save in stream update */
+	varibright_set_level(core_power);
+	*stream_update->abm_level = core_power->varibright_prop.varibright_hw_level;
+
+	DC_TRACE_LEVEL_MESSAGEP(DAL_TRACE_LEVEL_INFORMATION,
+						WPP_BIT_FLAG_Backlight_ABM,
+						">ABM feature enable: enable=%u su->varibright_level=%u varibright_hw_level=%u",
+						(unsigned int) enable,
+						*stream_update->abm_level,
+						core_power->varibright_prop.varibright_hw_level);
+	return true;
+}
+
+bool mod_power_varibright_activate(struct mod_power *mod_power,
+		bool activate,
+		struct dc_stream_update *stream_update)
+{
+	struct core_power *core_power = NULL;
+
+	if (mod_power == NULL)
+		return false;
+
+	core_power = MOD_POWER_TO_CORE(mod_power);
+	core_power->varibright_prop.varibright_active = activate;
+
+	/* find abm hw level to program, and save in stream update */
+	varibright_set_level(core_power);
+	*stream_update->abm_level = core_power->varibright_prop.varibright_hw_level;
+
+	DC_TRACE_LEVEL_MESSAGEP(DAL_TRACE_LEVEL_INFORMATION,
+						WPP_BIT_FLAG_Backlight_ABM,
+						">ABM activate: activate=%u su->varibright_level=%u",
+						(unsigned int) activate,
+						*stream_update->abm_level);
+	return true;
+}
+bool mod_power_varibright_set_level(struct mod_power *mod_power, unsigned int level,
+		struct dc_stream_update *stream_update)
+{
+	struct core_power *core_power = NULL;
+
+	if (mod_power == NULL)
+		return false;
+
+	core_power = MOD_POWER_TO_CORE(mod_power);
+	core_power->varibright_prop.varibright_level = level;
+	core_power->varibright_prop.varibright_hw_level = level;
+
+	/* find abm hw level to program, and save in stream update */
+	varibright_set_level(core_power);
+	*stream_update->abm_level = core_power->varibright_prop.varibright_hw_level;
+
+	DC_TRACE_LEVEL_MESSAGEP(DAL_TRACE_LEVEL_INFORMATION,
+						WPP_BIT_FLAG_Backlight_ABM,
+						">ABM set level: level=%u -> (varibright_level=%u varibright_hw_level=%u) -> su->varibright_level=%u",
+						level,
+						core_power->varibright_prop.varibright_level,
+						core_power->varibright_prop.varibright_hw_level,
+						*stream_update->abm_level);
+	return true;
+}
+
+bool mod_power_varibright_set_hw_level(struct mod_power *mod_power, unsigned int level,
+		struct dc_stream_update *stream_update)
+{
+	struct core_power *core_power = NULL;
+
+	if (mod_power == NULL)
+		return false;
+
+	core_power = MOD_POWER_TO_CORE(mod_power);
+
+	if (level == 0 || level == ABM_LEVEL_IMMEDIATE_DISABLE)
+		core_power->varibright_prop.varibright_active = 0;
+	else
+		core_power->varibright_prop.varibright_active = 1;
+	core_power->varibright_prop.varibright_hw_level = level;
+	*stream_update->abm_level = core_power->varibright_prop.varibright_hw_level;
+
+	DC_TRACE_LEVEL_MESSAGEP(DAL_TRACE_LEVEL_INFORMATION,
+						WPP_BIT_FLAG_Backlight_ABM,
+						">ABM set level: level=%u -> (varibright_level=%u varibright_hw_level=%u) -> su->varibright_level=%u",
+						level,
+						core_power->varibright_prop.varibright_level,
+						core_power->varibright_prop.varibright_hw_level,
+						*stream_update->abm_level);
+	return true;
+}
+
+bool mod_power_get_varibright_level(struct mod_power *mod_power,
+		unsigned int *varibright_level)
+{
+	struct core_power *core_power = NULL;
+
+	if (mod_power == NULL)
+		return false;
+
+	core_power = MOD_POWER_TO_CORE(mod_power);
+
+	*varibright_level = core_power->varibright_prop.varibright_level;
+
+	DC_TRACE_LEVEL_MESSAGEP(DAL_TRACE_LEVEL_INFORMATION,
+						WPP_BIT_FLAG_Backlight_ABM,
+						">get varibright level: cp->varibright_level=%u",
+						*varibright_level);
+	return true;
+
+}
+
+bool mod_power_get_varibright_hw_level(struct mod_power *mod_power,
+		unsigned int *varibright_level)
+{
+	struct core_power *core_power = NULL;
+
+	if (mod_power == NULL)
+		return false;
+
+	core_power = MOD_POWER_TO_CORE(mod_power);
+
+	*varibright_level = core_power->varibright_prop.varibright_hw_level;
+	DC_TRACE_LEVEL_MESSAGEP(DAL_TRACE_LEVEL_INFORMATION,
+						WPP_BIT_FLAG_Backlight_ABM,
+						">get varibright HW level: hw_level=%u",
+						*varibright_level);
+	return true;
+}
+
+bool mod_power_get_varibright_default_level(struct mod_power *mod_power,
+		unsigned int *varibright_level)
+{
+	struct core_power *core_power = NULL;
+
+	if (mod_power == NULL)
+		return false;
+
+	core_power = MOD_POWER_TO_CORE(mod_power);
+
+	*varibright_level = core_power->varibright_prop.def_varibright_level;
+	DC_TRACE_LEVEL_MESSAGEP(DAL_TRACE_LEVEL_INFORMATION,
+						WPP_BIT_FLAG_Backlight_ABM,
+						">get varibright default level: def_varibright_level=%u",
+						*varibright_level);
+	return true;
+}
+
+bool mod_power_get_varibright_enable(struct mod_power *mod_power,
+		bool *varibright_enable)
+{
+	struct core_power *core_power = NULL;
+
+	if (mod_power == NULL)
+		return false;
+
+	core_power = MOD_POWER_TO_CORE(mod_power);
+
+	*varibright_enable = core_power->varibright_prop.varibright_user_enable;
+	DC_TRACE_LEVEL_MESSAGEP(DAL_TRACE_LEVEL_INFORMATION,
+				WPP_BIT_FLAG_Backlight_ABM,
+				">get varibright enable state: varibright_user_enable=%u",
+				(unsigned int) (*varibright_enable));
+	return true;
+}
+
+bool mod_power_is_abm_active(struct mod_power *mod_power,
+		const struct dc_link *link,
+		unsigned int inst)
+{
+	unsigned int user_backlight = 0;
+	unsigned int current_backlight = 0;
+	bool is_active = false;
+
+	if (mod_power == NULL)
+		return false;
+
+	mod_power_get_backlight_pwm(mod_power, &user_backlight, inst);
+	mod_power_get_hw_backlight_pwm(mod_power, link,	&current_backlight);
+
+	if (user_backlight != current_backlight)
+		is_active = true;
+	else
+		is_active = false;
+	DC_TRACE_LEVEL_MESSAGEP(DAL_TRACE_LEVEL_INFORMATION,
+						WPP_BIT_FLAG_Backlight_ABM,
+						">get ABM active state: is_active=%u (user_backlight_pwm=%u, current_backlight_pwm=%u)",
+						(unsigned int)is_active,
+						user_backlight,
+						current_backlight);
+	return is_active;
+}
+
+
+static void mod_power_psr_set_power_opt(struct mod_power *mod_power,
+	struct dc_stream_state *stream,
+	unsigned int active_psr_events,
+	bool psr_enable_request)
+{
+	(void)psr_enable_request;
+	struct core_power *core_power = NULL;
+	struct dc_link *link = NULL;
+	unsigned int stream_index = 0;
+	unsigned int power_opt = 0;
+
+	if (!stream)
+		return;
+
+	core_power = MOD_POWER_TO_CORE(mod_power);
+	stream_index = map_index_from_stream(core_power, stream);
+	if (!core_power->map[stream_index].caps->psr_version)
+		return;
+
+	link = dc_stream_get_link(stream);
+
+	if (active_psr_events == 0) {
+		/* Static Screen */
+		power_opt |= (psr_power_opt_smu_opt_static_screen | psr_power_opt_z10_static_screen |
+					psr_power_opt_ds_disable_allow);
+	}
+
+	/* psr_power_opt_flag is a configuration parameter into the module that determines
+	 * which optimizations to enable during psr
+	 */
+	power_opt &= core_power->map[stream_index].caps->psr_power_opt_flag;
+	if (core_power->map[stream_index].psr_power_opt != power_opt) {
+		DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_VERBOSE,
+				WPP_BIT_FLAG_Firmware_PsrState,
+				"mod_power set_power_opt: psr_power_opt=0x%04x, power_opt=0x%04x"
+				"active_psr_events=0x%04x, psr_power_opt_flag=0x%04x",
+				core_power->map[stream_index].psr_power_opt,
+				power_opt,
+				active_psr_events,
+				core_power->map[stream_index].caps->psr_power_opt_flag);
+		dc_link_set_psr_allow_active(link, NULL, false, false, &power_opt);
+		core_power->map[stream_index].psr_power_opt = power_opt;
+	}
+}
+
+static bool set_psr_enable(struct mod_power *mod_power,
+		struct dc_stream_state *stream,
+		bool psr_enable,
+		bool wait,
+		bool force_static)
+{
+	struct core_power *core_power = NULL;
+	enum dc_psr_state state = PSR_STATE0;
+	unsigned int retry_count;
+	const unsigned int max_retry = 1000;
+	struct dc_link *link = NULL;
+
+	if (mod_power == NULL)
+		return false;
+
+	core_power = MOD_POWER_TO_CORE(mod_power);
+
+	if (core_power->num_entities == 0) {
+		DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_ERROR,
+							WPP_BIT_FLAG_Firmware_PsrState,
+							"set psr enable: ERROR: stream=%p num_entities=%d",
+							stream,
+							core_power->num_entities);
+		return false;
+	}
+
+	if (psr_enable)	{
+		unsigned int vsync_rate_hz;
+		struct dc_static_screen_params params = {0};
+
+		vsync_rate_hz = (unsigned int)div_u64(div_u64((
+				stream->timing.pix_clk_100hz * 100),
+				stream->timing.v_total),
+				stream->timing.h_total);
+
+		params.triggers.cursor_update = true;
+		params.triggers.overlay_update = true;
+		params.triggers.surface_update = true;
+		params.num_frames = calc_psr_num_static_frames(vsync_rate_hz);
+
+		DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_INFORMATION,
+							WPP_BIT_FLAG_Firmware_PsrState,
+							"set psr enable: CALCS: pix_clk_100hz=%u v_total=%u h_total=%u vsync_rate_hz=%u num_frames=%u",
+							stream->timing.pix_clk_100hz,
+							stream->timing.v_total,
+							stream->timing.h_total,
+							vsync_rate_hz,
+							params.num_frames);
+
+		dc_stream_set_static_screen_params(core_power->dc,
+						   &stream, 1,
+						   &params);
+	}
+
+	link = dc_stream_get_link(stream);
+
+	if (!dc_link_set_psr_allow_active(link, &psr_enable, false, force_static, NULL)) {
+		DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_ERROR,
+							WPP_BIT_FLAG_Firmware_PsrState,
+							"set psr enable: ERROR: stream=%p link=%p psr_enable=%d",
+							stream,
+							link,
+							psr_enable);
+		return false;
+	}
+
+	if (wait == true) {
+
+		DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_INFORMATION,
+							WPP_BIT_FLAG_Firmware_PsrState,
+							"set psr enable: BEGIN WAIT: psr_enable=%d",
+							(int)psr_enable);
+
+		for (retry_count = 0; retry_count <= max_retry; retry_count++) {
+			dc_link_get_psr_state(link, &state);
+			if (psr_enable) {
+				if (state != PSR_STATE0 &&
+						(!force_static || state == PSR_STATE3))
+					break;
+			} else {
+				if (state == PSR_STATE0)
+					break;
+			}
+			udelay(500);
+		}
+
+		DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_INFORMATION,
+							WPP_BIT_FLAG_Firmware_PsrState,
+							"set psr enable: END WAIT: psr_enable=%d",
+							(int)psr_enable);
+
+		/* assert if max retry hit */
+		if (retry_count >= max_retry) {
+			ASSERT(0);
+			DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_ERROR,
+								WPP_BIT_FLAG_Firmware_PsrState,
+								"set psr enable: ERROR: retry_count=%u: Unexpectedly long wait for PSR state change.",
+								retry_count);
+		}
+	} else {
+		DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_INFORMATION,
+							WPP_BIT_FLAG_Firmware_PsrState,
+							"set psr enable: PSR state change initiated (wait=false): psr_enable=%d",
+							(int)psr_enable);
+	}
+
+	return true;
+}
+
+bool mod_power_get_psr_event(struct mod_power *mod_power,
+			struct dc_stream_state *stream,
+			unsigned int *active_psr_events)
+{
+	struct core_power *core_power = NULL;
+	unsigned int stream_index = 0;
+
+	if (mod_power == NULL)
+		return false;
+
+	core_power = MOD_POWER_TO_CORE(mod_power);
+
+	if (core_power->num_entities == 0)
+		return false;
+
+	stream_index = map_index_from_stream(core_power, stream);
+
+	if (!core_power->map[stream_index].caps->psr_version)
+		return false;
+
+	*active_psr_events = core_power->map[stream_index].psr_events;
+
+	return true;
+}
+
+bool mod_power_set_psr_event(struct mod_power *mod_power,
+		struct dc_stream_state *stream, bool set_event,
+		enum psr_event event, bool wait)
+{
+	struct core_power *core_power = NULL;
+	unsigned int stream_index = 0;
+	unsigned int active_psr_events = 0;
+	bool psr_enable_request = false;
+	bool force_static = false;
+
+	if (mod_power == NULL || stream == NULL)
+		return false;
+
+	core_power = MOD_POWER_TO_CORE(mod_power);
+	stream_index = map_index_from_stream(core_power, stream);
+
+	if (core_power->num_entities == 0) {
+		DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_ERROR,
+							WPP_BIT_FLAG_Firmware_PsrState,
+							"mod_power set_psr_event: ERROR: stream=%p event=%d num_entities=%d",
+							stream,
+							(int)event,
+							core_power->num_entities);
+		return false;
+	}
+
+	if (!core_power->map[stream_index].caps->psr_version)
+		return false;
+
+	if (set_event)
+		core_power->map[stream_index].psr_events |= event;
+	else
+		core_power->map[stream_index].psr_events &= ~event;
+
+	active_psr_events = core_power->map[stream_index].psr_events;
+
+	// ignore other events when we're in forced psr enabled state
+	if (active_psr_events & psr_event_dynamic_display_switch &&
+			event != psr_event_dynamic_display_switch)
+		return false;
+
+	// ignore other events when we're in forced psr enabled state
+	if (active_psr_events & psr_event_os_override_hold &&
+			event != psr_event_os_override_hold)
+		return false;
+
+	// ignore other events when we're in forced psr enabled state
+	// dds events need to be processed while in dynamic_link_rate_control
+	if (active_psr_events & psr_event_dynamic_link_rate_control &&
+			event != psr_event_dynamic_link_rate_control &&
+			event != psr_event_dds_defer_stream_enable &&
+			event != psr_event_dynamic_display_switch)
+		return false;
+
+	if (active_psr_events & (psr_event_test_harness_disable_psr | psr_event_os_request_disable))
+		psr_enable_request = false;
+	else if (active_psr_events & psr_event_pause)
+		psr_enable_request = false;
+	else if (active_psr_events & psr_event_test_harness_enable_psr)
+		psr_enable_request = true;
+	else if (active_psr_events & psr_event_dynamic_display_switch) {
+		psr_enable_request = true;
+		force_static = true;
+	} else if (active_psr_events & psr_event_dynamic_link_rate_control) {
+		psr_enable_request = true;
+		force_static = true;
+	} else if (active_psr_events & psr_event_edp_panel_off_disable_psr)
+		psr_enable_request = false;
+	else if (active_psr_events & (psr_event_hw_programming |
+			psr_event_defer_enable |
+			psr_event_dds_defer_stream_enable |
+			psr_event_vrr_transition |
+			psr_event_immediate_flip))
+		psr_enable_request = false;
+	else if (active_psr_events & psr_event_big_screen_video)
+		psr_enable_request = true;
+	else if (active_psr_events & psr_event_full_screen)
+		psr_enable_request = false;
+	else if (active_psr_events & psr_event_mpo_video_selective_update)
+		psr_enable_request = true;
+	else if (active_psr_events & psr_event_vsync)
+		psr_enable_request = false;
+	else if (active_psr_events & psr_event_crc_window_active)
+		psr_enable_request = false;
+	else
+		psr_enable_request = true;
+
+	DC_TRACE_LEVEL_MESSAGE(DAL_TRACE_LEVEL_VERBOSE,
+						WPP_BIT_FLAG_Firmware_PsrState,
+						"mod_power set_psr_event: before: psr_enabled=%d -> request: set_event=%d event=0x%04x -> result: psr_events=0x%04x psr_enable_request=%d",
+						(int)core_power->map[stream_index].psr_enabled,
+						(int)set_event,
+						(unsigned int)event,
+						(unsigned int)core_power->map[stream_index].psr_events,
+						(int)psr_enable_request);
+	mod_power_psr_set_power_opt(mod_power, stream, active_psr_events, psr_enable_request);
+
+	if (core_power->map[stream_index].psr_enabled != psr_enable_request || force_static) {
+		if (set_psr_enable(mod_power, stream, psr_enable_request, wait, force_static)) {
+			core_power->map[stream_index].psr_enabled = psr_enable_request;
+		}
+	}
+
+	return true;
+}
+
+bool mod_power_get_psr_state(struct mod_power *mod_power,
+		const struct dc_stream_state *stream,
+		enum dc_psr_state *state)
+{
+	struct core_power *core_power = NULL;
+	const struct dc_link *link = NULL;
+
+	if (!stream)
+		return false;
+
+	if (mod_power == NULL)
+		return false;
+
+	core_power = MOD_POWER_TO_CORE(mod_power);
+
+	if (core_power->num_entities == 0)
+		return false;
+
+	link = dc_stream_get_link(stream);
+	return dc_link_get_psr_state(link, state);
+}
+
+bool mod_power_get_psr_enabled_status(struct mod_power *mod_power,
+		const struct dc_stream_state *stream,
+		bool *psr_enabled)
+{
+	struct core_power *core_power = NULL;
+	unsigned int stream_index = 0;
+
+	if (mod_power == NULL)
+		return false;
+
+	core_power = MOD_POWER_TO_CORE(mod_power);
+
+	if (core_power->num_entities == 0)
+		return false;
+
+	stream_index = map_index_from_stream(core_power, stream);
+
+	if (!core_power->map[stream_index].caps->psr_version)
+		return false;
+
+	*psr_enabled = core_power->map[stream_index].psr_enabled;
+
+	return true;
+}
+
+void mod_power_psr_residency(struct mod_power *mod_power,
+		const struct dc_stream_state *stream,
+		unsigned int *residency,
+		const uint8_t mode)
+{
+	struct core_power *core_power = NULL;
+	const struct dc_link *link = NULL;
+
+	if (!stream)
+		return;
+
+	if (mod_power == NULL)
+		return;
+
+	core_power = MOD_POWER_TO_CORE(mod_power);
+
+	if (core_power->num_entities == 0)
+		return;
+
+	link = dc_stream_get_link(stream);
+
+	if (link != NULL)
+		link->dc->link_srv->edp_get_psr_residency(link, residency, mode);
+}
+bool mod_power_psr_get_active_psr_events(struct mod_power *mod_power,
+		const struct dc_stream_state *stream, unsigned int *active_psr_events)
+{
+	struct core_power *core_power = NULL;
+	unsigned int stream_index = 0;
+
+	if (!stream)
+		return false;
+
+	if (mod_power == NULL)
+		return false;
+
+	if (active_psr_events == NULL)
+		return false;
+
+	core_power = MOD_POWER_TO_CORE(mod_power);
+
+	if (core_power->num_entities == 0)
+		return false;
+
+	stream_index = map_index_from_stream(core_power, stream);
+
+	*active_psr_events = core_power->map[stream_index].psr_events;
+	return true;
+}
+
+bool mod_power_psr_set_sink_vtotal_in_psr_active(struct mod_power *mod_power,
+		const struct dc_stream_state *stream,
+		uint16_t psr_vtotal_idle,
+		uint16_t psr_vtotal_su)
+{
+	struct core_power *core_power = NULL;
+	unsigned int stream_index = 0;
+	const struct dc_link *link = NULL;
+
+	if (!stream)
+		return false;
+
+	if (mod_power == NULL)
+		return false;
+
+	core_power = MOD_POWER_TO_CORE(mod_power);
+
+	if (core_power->num_entities == 0)
+		return false;
+
+	stream_index = map_index_from_stream(core_power, stream);
+
+	if (!core_power->map[stream_index].caps->psr_version)
+		return false;
+
+	link = dc_stream_get_link(stream);
+
+	return link->dc->link_srv->edp_set_sink_vtotal_in_psr_active(
+			link, psr_vtotal_idle, psr_vtotal_su);
+}
+
+static bool mod_power_set_replay_active(struct dc_stream_state *stream,
+	bool replay_active,
+	bool wait,
+	bool force_static)
+{
+	uint64_t state;
+	unsigned int retry_count;
+	const unsigned int max_retry = 1000;
+	struct dc_link *link = NULL;
+
+	if (!stream)
+		return false;
+
+	link = dc_stream_get_link(stream);
+
+	if (!link)
+		return false;
+
+	if (!dc_link_set_replay_allow_active(link, &replay_active, false, force_static, NULL))
+		return false;
+
+	if (wait == true) {
+
+		for (retry_count = 0; retry_count <= max_retry; retry_count++) {
+			dc_link_get_replay_state(link, &state);
+			if (replay_active) {
+				if (state != REPLAY_STATE_0 &&
+					(!force_static || state == REPLAY_STATE_3))
+					break;
+			} else {
+				if (state == REPLAY_STATE_0)
+					break;
+			}
+			udelay(500);
+		}
+
+		/* assert if max retry hit */
+		if (retry_count >= max_retry)
+			ASSERT(0);
+	} else {
+		/* To-do: Add trace log */
+	}
+
+	return true;
+}
+
+static unsigned int mod_power_replay_setup_power_opt(struct dc_link *link,
+	unsigned int active_replay_events, bool is_ultra_sleep_mode)
+{
+	unsigned int power_opt = 0;
+
+	if (is_ultra_sleep_mode) {
+		/* Static Screen */
+		power_opt |= (replay_power_opt_smu_opt_static_screen | replay_power_opt_z10_static_screen);
+	} else if (active_replay_events & replay_event_test_harness_ultra_sleep) {
+		power_opt |= replay_power_opt_z10_static_screen;
+	}
+
+	/* replay_power_opt_flag is a configuration parameter into the module that determines
+	 * which optimizations to enable during replay
+	 */
+	power_opt &= link->replay_settings.config.replay_power_opt_supported;
+
+	return power_opt;
+}
+
+static bool mod_power_replay_set_power_opt(struct mod_power *mod_power,
+	struct dc_stream_state *stream,
+	unsigned int active_replay_events,
+	bool is_ultra_sleep_mode)
+{
+	(void)mod_power;
+	struct dc_link *link = NULL;
+	unsigned int power_opt = 0;
+
+	if (!stream)
+		return false;
+
+	link = dc_stream_get_link(stream);
+
+	if (!link || !link->replay_settings.replay_feature_enabled)
+		return false;
+
+	power_opt = mod_power_replay_setup_power_opt(link, active_replay_events, is_ultra_sleep_mode);
+
+	if (!dc_link_set_replay_allow_active(link, NULL, false, false, &power_opt))
+		return false;
+
+	return true;
+}
+
+bool mod_power_get_replay_event(struct mod_power *mod_power,
+	struct dc_stream_state *stream,
+	unsigned int *active_replay_events)
+{
+	struct core_power *core_power = NULL;
+	unsigned int stream_index = 0;
+
+	if (mod_power == NULL)
+		return false;
+
+	core_power = MOD_POWER_TO_CORE(mod_power);
+
+	if (core_power->num_entities == 0)
+		return false;
+
+	stream_index = map_index_from_stream(core_power, stream);
+
+	*active_replay_events = core_power->map[stream_index].replay_events;
+
+	return true;
+}
+
+static bool mod_power_update_replay_active_status(unsigned int active_replay_events,
+	struct dc_link *link, uint32_t *coasting_vtotal, bool *is_full_screen_video, bool *is_ultra_sleep_mode, uint16_t *frame_skip_number, bool *is_video_playback)
+{
+	if (!link || !coasting_vtotal || !is_full_screen_video || !is_video_playback)
+		return false;
+
+	// Check coasting_vtotal_table has been updated.
+	if (!link->replay_settings.coasting_vtotal_table[PR_COASTING_TYPE_STATIC]
+		|| !link->replay_settings.coasting_vtotal_table[PR_COASTING_TYPE_NOM])
+		return false;
+
+	unsigned int replay_enable_option =
+		link->replay_settings.config.replay_enable_option;
+
+	/* TODO: To support test harness and DDS event */
+
+	*coasting_vtotal = link->replay_settings.coasting_vtotal_table[PR_COASTING_TYPE_NOM];
+	ASSERT(link->replay_settings.frame_skip_number_table[PR_COASTING_TYPE_NOM] <= 0xFFFF);
+	*frame_skip_number = (uint16_t)link->replay_settings.frame_skip_number_table[PR_COASTING_TYPE_NOM];
+
+	link->replay_settings.config.replay_timing_sync_supported = false;
+
+	*is_full_screen_video = false;
+
+	*is_ultra_sleep_mode = false;
+
+	*is_video_playback = false;
+
+	/* DSAT test scenario */
+	if (active_replay_events & replay_event_test_harness_mode) {
+		if (link->replay_settings.coasting_vtotal_table[PR_COASTING_TYPE_TEST_HARNESS])
+			*coasting_vtotal =
+				link->replay_settings.coasting_vtotal_table[PR_COASTING_TYPE_TEST_HARNESS];
+		if (link->replay_settings.frame_skip_number_table[PR_COASTING_TYPE_TEST_HARNESS]) {
+			ASSERT(link->replay_settings.frame_skip_number_table[PR_COASTING_TYPE_TEST_HARNESS] <= 0xFFFF);
+			*frame_skip_number =
+				(uint16_t)link->replay_settings.frame_skip_number_table[PR_COASTING_TYPE_TEST_HARNESS];
+		}
+
+		/* During the ultra sleep mode testing, disable the timing sync in short vblank mode */
+		if (active_replay_events & (replay_event_test_harness_enable_replay)) {
+			if ((active_replay_events & replay_event_test_harness_ultra_sleep) &&
+				  !link->replay_settings.config.replay_support_fast_resync_in_ultra_sleep_mode)
+				link->replay_settings.config.replay_timing_sync_supported = false;
+			return true;
+		} else
+			return false;
+	} else if (active_replay_events & (replay_event_test_harness_enable_replay)) {
+		if (link->replay_settings.coasting_vtotal_table[PR_COASTING_TYPE_TEST_HARNESS])
+			*coasting_vtotal = link->replay_settings.coasting_vtotal_table[PR_COASTING_TYPE_TEST_HARNESS];
+		if (link->replay_settings.frame_skip_number_table[PR_COASTING_TYPE_TEST_HARNESS]) {
+			uint32_t frame_skip_val =
+				link->replay_settings.frame_skip_number_table[PR_COASTING_TYPE_TEST_HARNESS];
+
+			ASSERT(frame_skip_val <= 0xFFFF);
+			*frame_skip_number = (uint16_t)frame_skip_val;
+		}
+
+		/* During the ultra sleep mode testing, disable the timing sync in short vblank mode */
+		if ((active_replay_events & replay_event_test_harness_ultra_sleep) &&
+			  !link->replay_settings.config.replay_support_fast_resync_in_ultra_sleep_mode)
+			link->replay_settings.config.replay_timing_sync_supported = false;
+		return true;
+	} else if (active_replay_events & (replay_event_test_harness_disable_replay | replay_event_os_request_disable)) {
+		// set last set coasting vtotal
+		if (link->replay_settings.coasting_vtotal_table[PR_COASTING_TYPE_TEST_HARNESS])
+			*coasting_vtotal = link->replay_settings.coasting_vtotal_table[PR_COASTING_TYPE_TEST_HARNESS];
+		if (link->replay_settings.frame_skip_number_table[PR_COASTING_TYPE_TEST_HARNESS]) {
+			uint32_t frame_skip_val =
+				link->replay_settings.frame_skip_number_table[PR_COASTING_TYPE_TEST_HARNESS];
+
+			ASSERT(frame_skip_val <= 0xFFFF);
+			*frame_skip_number = (uint16_t)frame_skip_val;
+		}
+		return false;
+	}
+
+	/* Inactive conditions */
+	if (active_replay_events & (replay_event_edp_panel_off_disable_psr |
+			replay_event_hw_programming |
+			replay_event_vrr |
+			replay_event_immediate_flip |
+			replay_event_prepare_vtotal |
+			replay_event_vrr_transition |
+			replay_event_pause |
+			replay_event_disable_replay_while_DPMS |
+			replay_event_sleep_resume |
+			replay_event_disable_in_AC |
+			replay_event_disable_replay_while_detect_display |
+			replay_event_infopacket |
+			replay_event_crc_window_active))
+		return false;
+
+	// Full screen scenario
+	if (active_replay_events & replay_event_full_screen) {
+		if (!(replay_enable_option & pr_enable_option_full_screen))
+			return false;
+	}
+
+	/* Full screen video scenario */
+	if (active_replay_events & replay_event_big_screen_video) {
+
+		link->replay_settings.config.replay_timing_sync_supported = false;
+
+		if (replay_enable_option & pr_enable_option_full_screen_video_coasting) {
+			unsigned int fsn_vid =
+				link->replay_settings.frame_skip_number_table[PR_COASTING_TYPE_FULL_SCREEN_VIDEO];
+
+			*coasting_vtotal =
+				link->replay_settings.coasting_vtotal_table[PR_COASTING_TYPE_FULL_SCREEN_VIDEO];
+			ASSERT(fsn_vid <= 0xFFFF);
+			*frame_skip_number = (uint16_t)fsn_vid;
+		}
+
+		*is_video_playback = true;
+
+		if ((replay_enable_option & pr_enable_option_full_screen_video) &&
+			(replay_enable_option & pr_enable_option_full_screen_video_coasting)) {
+			*is_full_screen_video = true;
+			return true;
+		} else
+			return false;
+	}
+
+	/* MPO video scenario
+	 * Some of the cases may contain a full screen UI layer in MPO video scenario which is
+	 * not the expected case to enable Replay.
+	 */
+	if ((active_replay_events & replay_event_mpo_video_selective_update) &&
+		!(active_replay_events & replay_event_full_screen)) {
+
+		link->replay_settings.config.replay_timing_sync_supported = false;
+
+		if (replay_enable_option & pr_enable_option_mpo_video_coasting) {
+			*coasting_vtotal = link->replay_settings.coasting_vtotal_table[PR_COASTING_TYPE_NOM];
+			{
+				uint32_t frame_skip_val =
+					link->replay_settings.frame_skip_number_table[PR_COASTING_TYPE_NOM];
+
+				ASSERT(frame_skip_val <= 0xFFFF);
+				*frame_skip_number = (uint16_t)frame_skip_val;
+			}
+		}
+
+		*is_video_playback = true;
+
+		if (replay_enable_option & pr_enable_option_mpo_video)
+			return true;
+		else
+			return false;
+	}
+
+	/* Static screen scenario */
+	if (!(active_replay_events & replay_event_vsync)) {
+
+		if (replay_enable_option & pr_enable_option_static_screen_coasting) {
+			// Do not adjust eDP refresh rate if static screen + normal sleep mode
+			if ((!(link->replay_settings.config.replay_power_opt_supported &
+				replay_power_opt_z10_static_screen)) ||
+				(active_replay_events & replay_event_cursor_updating)) {
+				// normal sleep mode
+				*coasting_vtotal =
+					link->replay_settings.coasting_vtotal_table[PR_COASTING_TYPE_NOM];
+				{
+					uint32_t frame_skip_val =
+						link->replay_settings.frame_skip_number_table[PR_COASTING_TYPE_NOM];
+
+					ASSERT(frame_skip_val <= 0xFFFF);
+					*frame_skip_number = (uint16_t)frame_skip_val;
+				}
+			} else {
+				// ultra sleep mode
+				*coasting_vtotal =
+					link->replay_settings.coasting_vtotal_table[PR_COASTING_TYPE_STATIC];
+				{
+					uint32_t frame_skip_val =
+						link->replay_settings.frame_skip_number_table[PR_COASTING_TYPE_STATIC];
+
+					ASSERT(frame_skip_val <= 0xFFFF);
+					*frame_skip_number = (uint16_t)frame_skip_val;
+				}
+				*is_ultra_sleep_mode = true;
+			}
+		}
+
+		if (replay_enable_option & pr_enable_option_static_screen) {
+			if (!link->replay_settings.config.replay_support_fast_resync_in_ultra_sleep_mode)
+				link->replay_settings.config.replay_timing_sync_supported = false;
+			return true;
+		} else
+			return false;
+	}
+
+	/* General UI scenario */
+	if (active_replay_events & replay_event_general_ui) {
+		if (replay_enable_option & pr_enable_option_general_ui)
+			return true;
+		else
+			return false;
+	}
+
+	return false;
+}
+
+bool mod_power_replay_set_coasting_vtotal(struct mod_power *mod_power,
+	const struct dc_stream_state *stream,
+	uint32_t coasting_vtotal,
+	uint16_t frame_skip_number)
+{
+	struct core_power *core_power = NULL;
+	struct dc_link *link = NULL;
+
+	if (!stream)
+		return false;
+
+	link = dc_stream_get_link(stream);
+	if (!link || !link->replay_settings.replay_feature_enabled)
+		return false;
+
+	if (mod_power == NULL)
+		return false;
+
+	core_power = MOD_POWER_TO_CORE(mod_power);
+
+	if (core_power->num_entities == 0)
+		return false;
+
+	return link->dc->link_srv->edp_set_coasting_vtotal(link, coasting_vtotal, frame_skip_number);
+}
+
+void mod_power_replay_set_timing_sync_supported(struct mod_power *mod_power,
+	const struct dc_stream_state *stream)
+{
+	struct core_power *core_power = NULL;
+	struct dc_link *link = NULL;
+	unsigned int stream_index = 0;
+	union dmub_replay_cmd_set cmd_data = { 0 };
+
+	if (!stream || mod_power == NULL)
+		return;
+
+	core_power = MOD_POWER_TO_CORE(mod_power);
+	if (core_power->num_entities == 0)
+		return;
+
+	stream_index = map_index_from_stream(core_power, stream);
+	if (stream_index > core_power->num_entities) //invalid index
+		return;
+
+	link = dc_stream_get_link(stream);
+	if (!link || !link->replay_settings.replay_feature_enabled)
+		return;
+
+	cmd_data.sync_data.timing_sync_supported = link->replay_settings.config.replay_timing_sync_supported;
+
+	link->dc->link_srv->edp_send_replay_cmd(link, Replay_Set_Timing_Sync_Supported,
+		&cmd_data);
+}
+
+void mod_power_replay_disabled_adaptive_sync_sdp(struct mod_power *mod_power,
+	const struct dc_stream_state *stream, bool force_disabled)
+{
+	struct core_power *core_power = NULL;
+	struct dc_link *link = NULL;
+	unsigned int stream_index = 0;
+	union dmub_replay_cmd_set cmd_data = { 0 };
+
+	if (!stream || mod_power == NULL)
+		return;
+
+	core_power = MOD_POWER_TO_CORE(mod_power);
+	if (core_power->num_entities == 0)
+		return;
+
+	stream_index = map_index_from_stream(core_power, stream);
+	if (stream_index > core_power->num_entities) //invalid index
+		return;
+
+	link = dc_stream_get_link(stream);
+	if (!link || !link->replay_settings.replay_feature_enabled)
+		return;
+
+	cmd_data.disabled_adaptive_sync_sdp_data.force_disabled = force_disabled;
+
+	link->dc->link_srv->edp_send_replay_cmd(link, Replay_Disabled_Adaptive_Sync_SDP,
+		&cmd_data);
+}
+
+static void mod_power_replay_set_general_cmd(struct mod_power *mod_power,
+	const struct dc_stream_state *stream,
+	const enum dmub_cmd_replay_general_subtype general_cmd_type,
+	const uint32_t param1, const uint32_t param2)
+{
+	struct core_power *core_power = NULL;
+	struct dc_link *link = NULL;
+	unsigned int stream_index = 0;
+	union dmub_replay_cmd_set cmd_data = { 0 };
+
+	if (!stream || mod_power == NULL)
+		return;
+
+	core_power = MOD_POWER_TO_CORE(mod_power);
+	if (core_power->num_entities == 0)
+		return;
+
+	stream_index = map_index_from_stream(core_power, stream);
+	if (stream_index > core_power->num_entities) //invalid index
+		return;
+
+	link = dc_stream_get_link(stream);
+	if (!link || !link->replay_settings.replay_feature_enabled)
+		return;
+
+	cmd_data.set_general_cmd_data.subtype = general_cmd_type;
+	cmd_data.set_general_cmd_data.param1 = param1;
+	cmd_data.set_general_cmd_data.param2 = param2;
+	link->dc->link_srv->edp_send_replay_cmd(link, Replay_Set_General_Cmd,
+		&cmd_data);
+}
+
+void mod_power_replay_disabled_desync_error_detection(struct mod_power *mod_power,
+	const struct dc_stream_state *stream,  bool force_disabled)
+{
+	mod_power_replay_set_general_cmd(mod_power, stream,
+			REPLAY_GENERAL_CMD_DISABLED_DESYNC_ERROR_DETECTION,
+			force_disabled, 0);
+}
+
+static void mod_power_replay_set_pseudo_vtotal(struct mod_power *mod_power,
+	const struct dc_stream_state *stream, uint16_t vtotal)
+{
+	struct core_power *core_power = NULL;
+	struct dc_link *link = NULL;
+	unsigned int stream_index = 0;
+	union dmub_replay_cmd_set cmd_data = { 0 };
+
+	if (!stream || mod_power == NULL)
+		return;
+
+	core_power = MOD_POWER_TO_CORE(mod_power);
+	if (core_power->num_entities == 0)
+		return;
+
+	stream_index = map_index_from_stream(core_power, stream);
+	if (stream_index > core_power->num_entities) //invalid index
+		return;
+
+	link = dc_stream_get_link(stream);
+	if (!link || !link->replay_settings.replay_feature_enabled)
+		return;
+
+	cmd_data.pseudo_vtotal_data.vtotal = vtotal;
+
+	if (link->replay_settings.last_pseudo_vtotal != vtotal) {
+		link->replay_settings.last_pseudo_vtotal = vtotal;
+		link->dc->link_srv->edp_send_replay_cmd(link, Replay_Set_Pseudo_VTotal, &cmd_data);
+	}
+}
+
+static void mod_power_update_error_status(struct mod_power *mod_power,
+	const struct dc_stream_state *stream)
+{
+	struct dc_link *link = NULL;
+	union replay_debug_flags *pDebug = NULL;
+
+	if (mod_power == NULL || stream == NULL)
+		return;
+
+	link = dc_stream_get_link(stream);
+
+	if (!link)
+		return;
+
+	pDebug = (union replay_debug_flags *)&link->replay_settings.config.debug_flags;
+
+	if (0 == pDebug->bitfields.enable_visual_confirm_debug)
+		return;
+
+	mod_power_replay_set_general_cmd(mod_power, stream,
+		REPLAY_GENERAL_CMD_UPDATE_ERROR_STATUS,
+		link->replay_settings.config.replay_error_status.raw, 0);
+}
+
+void mod_power_set_low_rr_activate(struct mod_power *mod_power,
+	const struct dc_stream_state *stream, bool low_rr_supported)
+{
+	struct dc_link *link = NULL;
+
+	if (mod_power == NULL || stream == NULL)
+		return;
+
+	link = dc_stream_get_link(stream);
+
+	if (!link)
+		return;
+
+	mod_power_replay_set_general_cmd(mod_power, stream,
+		REPLAY_GENERAL_CMD_SET_LOW_RR_ACTIVATE,
+		low_rr_supported, 0);
+}
+
+void mod_power_set_video_conferencing_activate(struct mod_power *mod_power,
+	const struct dc_stream_state *stream, bool video_conferencing_activate)
+{
+	struct dc_link *link = NULL;
+
+	if (mod_power == NULL || stream == NULL)
+		return;
+
+	link = dc_stream_get_link(stream);
+	if (!link || !link->replay_settings.replay_feature_enabled)
+		return;
+
+	mod_power_replay_set_general_cmd(mod_power, stream,
+		REPLAY_GENERAL_CMD_VIDEO_CONFERENCING,
+		video_conferencing_activate, 0);
+}
+
+void mod_power_set_coasting_vtotal_without_frame_update(struct mod_power *mod_power,
+	const struct dc_stream_state *stream, uint32_t coasting_vtotal)
+{
+	struct dc_link *link = NULL;
+
+	if (mod_power == NULL || stream == NULL)
+		return;
+
+	link = dc_stream_get_link(stream);
+	if (!link || !link->replay_settings.replay_feature_enabled)
+		return;
+
+	mod_power_replay_set_general_cmd(mod_power, stream,
+		REPLAY_GENERAL_CMD_SET_COASTING_VTOTAL_WITHOUT_FRAME_UPDATE,
+		coasting_vtotal, 0);
+}
+
+void mod_power_set_replay_continuously_resync(struct mod_power *mod_power,
+	const struct dc_stream_state *stream, bool enable)
+{
+	struct dc_link *link = NULL;
+
+	if (mod_power == NULL || stream == NULL)
+		return;
+
+	link = dc_stream_get_link(stream);
+	if (!link || !link->replay_settings.replay_feature_enabled)
+		return;
+
+	mod_power_replay_set_general_cmd(mod_power, stream,
+		REPLAY_GENERAL_CMD_SET_CONTINUOUSLY_RESYNC,
+		enable, 0);
+}
+
+void mod_power_set_live_capture_with_cvt_activate(struct mod_power *mod_power,
+	const struct dc_stream_state *stream, bool live_capture_with_cvt_activate)
+{
+	struct dc_link *link = NULL;
+
+	if (mod_power == NULL || stream == NULL)
+		return;
+
+	link = dc_stream_get_link(stream);
+	if (!link || !link->replay_settings.replay_feature_enabled)
+		return;
+
+	// Check if LIVE_CAPTURE_WITH_CVT bit is enabled in DalRegKey_ReplayOptimization
+	if (!link->replay_settings.config.replay_optimization.bits.LIVE_CAPTURE_WITH_CVT)
+		return;
+
+	if (link->replay_settings.config.live_capture_with_cvt_activated != live_capture_with_cvt_activate) {
+		link->replay_settings.config.live_capture_with_cvt_activated = live_capture_with_cvt_activate;
+		mod_power_replay_set_general_cmd(mod_power, stream,
+			REPLAY_GENERAL_CMD_LIVE_CAPTURE_WITH_CVT,
+			live_capture_with_cvt_activate, 0);
+	}
+}
+
+bool mod_power_set_replay_event(struct mod_power *mod_power,
+	struct dc_stream_state *stream, bool set_event,
+	enum replay_event event, bool wait_for_disable)
+{
+	struct core_power *core_power = NULL;
+	struct dc_link *link = NULL;
+	unsigned int stream_index = 0;
+	unsigned int active_replay_events = 0;
+	bool replay_active_request = false;
+	bool force_static = false;
+	uint32_t coasting_vtotal = 0;
+	bool current_timing_sync_status = false;
+	bool is_full_screen_video = false;
+	bool is_ultra_sleep_mode = false;
+	unsigned int sink_duration_us = 0;
+	bool low_rr_active = false;
+	uint16_t frame_skip_number = 0;
+	bool is_video_playback = false;
+
+	if (!stream)
+		return false;
+
+	if (mod_power == NULL)
+		return false;
+
+	core_power = MOD_POWER_TO_CORE(mod_power);
+
+	if (core_power->num_entities == 0)
+		return false;
+
+	stream_index = map_index_from_stream(core_power, stream);
+
+	if (set_event)
+		core_power->map[stream_index].replay_events |= event;
+	else
+		core_power->map[stream_index].replay_events &= ~event;
+
+	link = dc_stream_get_link(stream);
+	if (!link || !link->replay_settings.replay_feature_enabled)
+		return false;
+
+	if ((core_power->map[stream_index].replay_events & replay_event_disable_replay_while_switching_mux) != 0)
+		return false;
+
+	if ((core_power->map[stream_index].replay_events & replay_event_os_override_hold) != 0)
+		return false;
+
+	active_replay_events = core_power->map[stream_index].replay_events;
+
+	current_timing_sync_status =
+		link->replay_settings.config.replay_timing_sync_supported;
+
+	replay_active_request = mod_power_update_replay_active_status(active_replay_events,
+		link, &coasting_vtotal, &is_full_screen_video, &is_ultra_sleep_mode, &frame_skip_number, &is_video_playback);
+
+	if (is_full_screen_video)
+		mod_power_replay_set_pseudo_vtotal(mod_power, stream,
+			link->replay_settings.low_rr_full_screen_video_pseudo_vtotal);
+	else
+		mod_power_replay_set_pseudo_vtotal(mod_power, stream, 0);
+
+	//If timing_sync_status change, then re-enabled set timing_sync_supported value and re-enabled replay
+	if (current_timing_sync_status != link->replay_settings.config.replay_timing_sync_supported)
+		mod_power_replay_set_timing_sync_supported(mod_power, stream);
+
+	if (link->replay_settings.config.low_rr_supported) {
+		sink_duration_us =
+			(unsigned int)(div_u64(((unsigned long long)(coasting_vtotal)
+				* 10000) * stream->timing.h_total,
+					stream->timing.pix_clk_100hz));
+		low_rr_active = sink_duration_us < LOW_REFRESH_RATE_DURATION_US_UPPER_BOUND ? false : true;
+		if (low_rr_active != link->replay_settings.config.low_rr_activated) {
+			mod_power_set_low_rr_activate(mod_power, stream, low_rr_active);
+			link->replay_settings.config.low_rr_activated = low_rr_active;
+		}
+	}
+
+	// The function return fail when
+	// 1. DMUB function is not support (for backward compatible).
+	// 2. active_replay_events or coasting_vtotal is not updated in the same time
+	if (!mod_power_replay_set_power_opt_and_coasting_vtotal(mod_power,
+		stream, active_replay_events, coasting_vtotal, is_ultra_sleep_mode, frame_skip_number)) {
+		if (!mod_power_replay_set_power_opt(mod_power, stream, active_replay_events, is_ultra_sleep_mode))
+			return false;
+
+		if (!mod_power_replay_set_coasting_vtotal(mod_power, stream, coasting_vtotal, frame_skip_number))
+			return false;
+	}
+
+	mod_power_set_live_capture_with_cvt_activate(mod_power, stream, is_video_playback);
+
+	mod_power_update_error_status(mod_power, stream);
+
+	// If Replay is going to be enable (No matter is disable -> enable or enable -> enable), we don't need to wait.
+	// If Replay is going to be disable
+	//     if disable -> disable
+	//         -> Replay DMUB state should be state 0.
+	//            So no matter wait_for_disable is true or not, it should makes no difference.
+	//     if enable -> disable -> We should wait if wait_for_disable is true.
+	if (replay_active_request)
+		wait_for_disable = false;
+
+	if (!mod_power_set_replay_active(stream, replay_active_request, wait_for_disable, force_static))
+		return false;
+
+	return true;
+}
+
+bool mod_power_get_replay_active_status(const struct dc_stream_state *stream,
+	bool *replay_active)
+{
+	const struct dc_link *link = NULL;
+
+	if (!stream)
+		return false;
+
+	link = dc_stream_get_link(stream);
+	*replay_active = link->replay_settings.replay_allow_active;
+
+	return true;
+}
+
+void mod_power_replay_residency(const struct dc_stream_state *stream,
+	unsigned int *residency, const bool is_start, const bool is_alpm)
+{
+	const struct dc_link *link = NULL;
+	enum pr_residency_mode mode;
+
+	if (!stream)
+		return;
+
+	link = dc_stream_get_link(stream);
+
+	if (is_alpm)
+		mode = PR_RESIDENCY_MODE_ALPM;
+	else
+		mode = PR_RESIDENCY_MODE_PHY;
+
+	if (link && link->dc && link->dc->link_srv)
+		link->dc->link_srv->edp_replay_residency(link, residency, is_start, mode);
+}
+
+bool mod_power_replay_set_power_opt_and_coasting_vtotal(struct mod_power *mod_power,
+	const struct dc_stream_state *stream, unsigned int active_replay_events, uint32_t coasting_vtotal,
+	bool is_ultra_sleep_mode, uint16_t frame_skip_number)
+{
+	struct core_power *core_power = NULL;
+	struct dc_link *link = NULL;
+	unsigned int power_opt = 0;
+
+	if (!stream)
+		return false;
+
+	if (mod_power == NULL)
+		return false;
+
+	core_power = MOD_POWER_TO_CORE(mod_power);
+
+	if (core_power->num_entities == 0)
+		return false;
+
+	link = dc_stream_get_link(stream);
+
+	if (!link || !link->replay_settings.replay_feature_enabled)
+		return false;
+
+	power_opt = mod_power_replay_setup_power_opt(link, active_replay_events, is_ultra_sleep_mode);
+
+	return link->dc->link_srv->edp_set_replay_power_opt_and_coasting_vtotal(link, &power_opt, coasting_vtotal, frame_skip_number);
+}
+
+
+
+
+
diff --git a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c b/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
index 5d444e9eb38f..f8b763db9b8c 100644
--- a/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
+++ b/drivers/gpu/drm/amd/display/modules/power/power_helpers.c
@@ -647,12 +647,12 @@ static void fill_iram_v_2_3(struct iram_table_v_2_2 *ram_table, struct dmcu_iram
 	unsigned int set = params.set;
 
 	ram_table->flags = 0x0;
-	ram_table->min_abm_backlight = (big_endian) ?
+	ram_table->min_abm_backlight = (uint16_t)((big_endian) ?
 		cpu_to_be16(params.min_abm_backlight) :
-		cpu_to_le16(params.min_abm_backlight);
+		cpu_to_le16(params.min_abm_backlight));
 
 	for (i = 0; i < NUM_AGGR_LEVEL; i++) {
-		ram_table->hybrid_factor[i] = abm_settings[set][i].brightness_gain;
+		ram_table->hybrid_factor[i] = (uint8_t)abm_settings[set][i].brightness_gain;
 		ram_table->contrast_factor[i] = abm_settings[set][i].contrast_factor;
 		ram_table->deviation_gain[i] = abm_settings[set][i].deviation_gain;
 		ram_table->min_knee[i] = abm_settings[set][i].min_knee;
@@ -960,8 +960,8 @@ bool psr_su_set_dsc_slice_height(struct dc *dc, struct dc_link *link,
 			      struct dc_stream_state *stream,
 			      struct psr_config *config)
 {
-	uint16_t pic_height;
-	uint16_t slice_height;
+	uint32_t pic_height;
+	uint32_t slice_height;
 
 	config->dsc_slice_height = 0;
 	if (!(link->connector_signal & SIGNAL_TYPE_EDP) ||
@@ -978,7 +978,7 @@ bool psr_su_set_dsc_slice_height(struct dc *dc, struct dc_link *link,
 		return false;
 
 	slice_height = pic_height / stream->timing.dsc_cfg.num_slices_v;
-	config->dsc_slice_height = slice_height;
+	config->dsc_slice_height = (uint16_t)slice_height;
 
 	if (slice_height) {
 		if (config->su_y_granularity &&
@@ -1056,7 +1056,7 @@ void set_replay_low_rr_full_screen_video_src_vtotal(struct dc_link *link, uint16
 void calculate_replay_link_off_frame_count(struct dc_link *link,
 	uint16_t vtotal, uint16_t htotal)
 {
-	uint8_t max_link_off_frame_count = 0;
+	uint32_t max_link_off_frame_count = 0;
 	uint16_t max_deviation_line = 0,  pixel_deviation_per_line = 0;
 
 	if (!link || link->replay_settings.config.replay_version != DC_FREESYNC_REPLAY)
@@ -1093,7 +1093,7 @@ bool fill_custom_backlight_caps(unsigned int config_no, struct dm_acpi_atif_back
 	caps->dc_level_percentage = custom_backlight_profiles[config_no].dc_level_percentage;
 	caps->min_input_signal = custom_backlight_profiles[config_no].min_input_signal;
 	caps->max_input_signal = custom_backlight_profiles[config_no].max_input_signal;
-	caps->num_data_points = custom_backlight_profiles[config_no].num_data_points;
+	caps->num_data_points = (uint8_t)custom_backlight_profiles[config_no].num_data_points;
 	memcpy(caps->data_points, custom_backlight_profiles[config_no].data_points, data_points_size);
 	return true;
 }
diff --git a/drivers/gpu/drm/amd/include/amd_cper.h b/drivers/gpu/drm/amd/include/amd_cper.h
index a252ee4c7874..baa0f30b9c4d 100644
--- a/drivers/gpu/drm/amd/include/amd_cper.h
+++ b/drivers/gpu/drm/amd/include/amd_cper.h
@@ -58,7 +58,7 @@
 
 enum cper_error_severity {
 	CPER_SEV_NON_FATAL_UNCORRECTED = 0,
-	CPER_SEV_FATAL                 = 1,
+	CPER_SEV_FATAL_UNCORRECTED     = 1,
 	CPER_SEV_NON_FATAL_CORRECTED   = 2,
 	CPER_SEV_NUM                   = 3,
 
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_offset.h
index d6a2839b4682..025e5490e6f1 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_offset.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_offset.h
@@ -5475,6 +5475,14 @@
 #define regCHA_PERFCOUNTER3_HI_BASE_IDX                                                                 1
 
 
+// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_perfddec
+// base address: 0x34000
+#define regGC_CANE_PERFCOUNTER0_LO                                                                      0x36c0
+#define regGC_CANE_PERFCOUNTER0_LO_BASE_IDX                                                             1
+#define regGC_CANE_PERFCOUNTER0_HI                                                                      0x36c1
+#define regGC_CANE_PERFCOUNTER0_HI_BASE_IDX                                                             1
+
+
 // addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_perfsdec
 // base address: 0x36000
 #define regCPG_PERFCOUNTER1_SELECT                                                                      0x3800
@@ -5761,6 +5769,16 @@
 #define regCHA_PERFCOUNTER3_SELECT1_BASE_IDX                                                            1
 
 
+// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_perfsdec
+// base address: 0x36000
+#define regGC_CANE_PERFCOUNTER0_SELECT                                                                  0x3e80
+#define regGC_CANE_PERFCOUNTER0_SELECT_BASE_IDX                                                         1
+#define regGC_CANE_PERFCOUNTER0_SELECT1                                                                 0x3e81
+#define regGC_CANE_PERFCOUNTER0_SELECT1_BASE_IDX                                                        1
+#define regGC_CANE_PERFCOUNTER0_MODE                                                                    0x3e82
+#define regGC_CANE_PERFCOUNTER0_MODE_BASE_IDX                                                           1
+
+
 // addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_gdfll_xvmin_xvmin_xvmin_reg_blk
 // base address: 0x3a014
 #define regXVMIN_XVMIN_WR_DATA                                                                          0x4806
@@ -12080,6 +12098,22 @@
 #define regGC_ATC_L2_PERFCOUNTER_HI_BASE_IDX                                                            1
 
 
+// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcutcl2ffbmprdec
+// base address: 0x353d0
+#define regGCUTCL2_FFBM_PERFCOUNTER_LO                                                                  0x34f4
+#define regGCUTCL2_FFBM_PERFCOUNTER_LO_BASE_IDX                                                         1
+#define regGCUTCL2_FFBM_PERFCOUNTER_HI                                                                  0x34f5
+#define regGCUTCL2_FFBM_PERFCOUNTER_HI_BASE_IDX                                                         1
+
+
+// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcutcl2nhttlbprdec
+// base address: 0x353e0
+#define regGCUTCL2_NHTTLB_PERFCOUNTER_LO                                                                0x34f8
+#define regGCUTCL2_NHTTLB_PERFCOUNTER_LO_BASE_IDX                                                       1
+#define regGCUTCL2_NHTTLB_PERFCOUNTER_HI                                                                0x34f9
+#define regGCUTCL2_NHTTLB_PERFCOUNTER_HI_BASE_IDX                                                       1
+
+
 // addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcl2tlbprdec
 // base address: 0x353f0
 #define regGC_L2TLB_PERFCOUNTER_LO                                                                      0x34fc
@@ -12176,6 +12210,82 @@
 #define regGC_ATC_L2_PERFCOUNTER_RSLT_CNTL_BASE_IDX                                                     1
 
 
+// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcutcl2ffbmpldec
+// base address: 0x37bb0
+#define regGCUTCL2_FFBM_PERFCOUNTER0_CFG                                                                0x3eec
+#define regGCUTCL2_FFBM_PERFCOUNTER0_CFG_BASE_IDX                                                       1
+#define regGCUTCL2_FFBM_PERFCOUNTER1_CFG                                                                0x3eed
+#define regGCUTCL2_FFBM_PERFCOUNTER1_CFG_BASE_IDX                                                       1
+#define regGCUTCL2_FFBM_PERFCOUNTER2_CFG                                                                0x3eee
+#define regGCUTCL2_FFBM_PERFCOUNTER2_CFG_BASE_IDX                                                       1
+#define regGCUTCL2_FFBM_PERFCOUNTER3_CFG                                                                0x3eef
+#define regGCUTCL2_FFBM_PERFCOUNTER3_CFG_BASE_IDX                                                       1
+#define regGCUTCL2_FFBM_PERFCOUNTER4_CFG                                                                0x3ef0
+#define regGCUTCL2_FFBM_PERFCOUNTER4_CFG_BASE_IDX                                                       1
+#define regGCUTCL2_FFBM_PERFCOUNTER5_CFG                                                                0x3ef1
+#define regGCUTCL2_FFBM_PERFCOUNTER5_CFG_BASE_IDX                                                       1
+#define regGCUTCL2_FFBM_PERFCOUNTER6_CFG                                                                0x3ef2
+#define regGCUTCL2_FFBM_PERFCOUNTER6_CFG_BASE_IDX                                                       1
+#define regGCUTCL2_FFBM_PERFCOUNTER7_CFG                                                                0x3ef3
+#define regGCUTCL2_FFBM_PERFCOUNTER7_CFG_BASE_IDX                                                       1
+#define regGCUTCL2_FFBM_PERFCOUNTER8_CFG                                                                0x3ef4
+#define regGCUTCL2_FFBM_PERFCOUNTER8_CFG_BASE_IDX                                                       1
+#define regGCUTCL2_FFBM_PERFCOUNTER9_CFG                                                                0x3ef5
+#define regGCUTCL2_FFBM_PERFCOUNTER9_CFG_BASE_IDX                                                       1
+#define regGCUTCL2_FFBM_PERFCOUNTER10_CFG                                                               0x3ef6
+#define regGCUTCL2_FFBM_PERFCOUNTER10_CFG_BASE_IDX                                                      1
+#define regGCUTCL2_FFBM_PERFCOUNTER11_CFG                                                               0x3ef7
+#define regGCUTCL2_FFBM_PERFCOUNTER11_CFG_BASE_IDX                                                      1
+#define regGCUTCL2_FFBM_PERFCOUNTER12_CFG                                                               0x3ef8
+#define regGCUTCL2_FFBM_PERFCOUNTER12_CFG_BASE_IDX                                                      1
+#define regGCUTCL2_FFBM_PERFCOUNTER13_CFG                                                               0x3ef9
+#define regGCUTCL2_FFBM_PERFCOUNTER13_CFG_BASE_IDX                                                      1
+#define regGCUTCL2_FFBM_PERFCOUNTER14_CFG                                                               0x3efa
+#define regGCUTCL2_FFBM_PERFCOUNTER14_CFG_BASE_IDX                                                      1
+#define regGCUTCL2_FFBM_PERFCOUNTER15_CFG                                                               0x3efb
+#define regGCUTCL2_FFBM_PERFCOUNTER15_CFG_BASE_IDX                                                      1
+#define regGCUTCL2_FFBM_PERFCOUNTER_RSLT_CNTL                                                           0x3efc
+#define regGCUTCL2_FFBM_PERFCOUNTER_RSLT_CNTL_BASE_IDX                                                  1
+
+
+// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcutcl2nhttlbpldec
+// base address: 0x37c00
+#define regGCUTCL2_NHTTLB_PERFCOUNTER0_CFG                                                              0x3f00
+#define regGCUTCL2_NHTTLB_PERFCOUNTER0_CFG_BASE_IDX                                                     1
+#define regGCUTCL2_NHTTLB_PERFCOUNTER1_CFG                                                              0x3f01
+#define regGCUTCL2_NHTTLB_PERFCOUNTER1_CFG_BASE_IDX                                                     1
+#define regGCUTCL2_NHTTLB_PERFCOUNTER2_CFG                                                              0x3f02
+#define regGCUTCL2_NHTTLB_PERFCOUNTER2_CFG_BASE_IDX                                                     1
+#define regGCUTCL2_NHTTLB_PERFCOUNTER3_CFG                                                              0x3f03
+#define regGCUTCL2_NHTTLB_PERFCOUNTER3_CFG_BASE_IDX                                                     1
+#define regGCUTCL2_NHTTLB_PERFCOUNTER4_CFG                                                              0x3f04
+#define regGCUTCL2_NHTTLB_PERFCOUNTER4_CFG_BASE_IDX                                                     1
+#define regGCUTCL2_NHTTLB_PERFCOUNTER5_CFG                                                              0x3f05
+#define regGCUTCL2_NHTTLB_PERFCOUNTER5_CFG_BASE_IDX                                                     1
+#define regGCUTCL2_NHTTLB_PERFCOUNTER6_CFG                                                              0x3f06
+#define regGCUTCL2_NHTTLB_PERFCOUNTER6_CFG_BASE_IDX                                                     1
+#define regGCUTCL2_NHTTLB_PERFCOUNTER7_CFG                                                              0x3f07
+#define regGCUTCL2_NHTTLB_PERFCOUNTER7_CFG_BASE_IDX                                                     1
+#define regGCUTCL2_NHTTLB_PERFCOUNTER8_CFG                                                              0x3f08
+#define regGCUTCL2_NHTTLB_PERFCOUNTER8_CFG_BASE_IDX                                                     1
+#define regGCUTCL2_NHTTLB_PERFCOUNTER9_CFG                                                              0x3f09
+#define regGCUTCL2_NHTTLB_PERFCOUNTER9_CFG_BASE_IDX                                                     1
+#define regGCUTCL2_NHTTLB_PERFCOUNTER10_CFG                                                             0x3f0a
+#define regGCUTCL2_NHTTLB_PERFCOUNTER10_CFG_BASE_IDX                                                    1
+#define regGCUTCL2_NHTTLB_PERFCOUNTER11_CFG                                                             0x3f0b
+#define regGCUTCL2_NHTTLB_PERFCOUNTER11_CFG_BASE_IDX                                                    1
+#define regGCUTCL2_NHTTLB_PERFCOUNTER12_CFG                                                             0x3f0c
+#define regGCUTCL2_NHTTLB_PERFCOUNTER12_CFG_BASE_IDX                                                    1
+#define regGCUTCL2_NHTTLB_PERFCOUNTER13_CFG                                                             0x3f0d
+#define regGCUTCL2_NHTTLB_PERFCOUNTER13_CFG_BASE_IDX                                                    1
+#define regGCUTCL2_NHTTLB_PERFCOUNTER14_CFG                                                             0x3f0e
+#define regGCUTCL2_NHTTLB_PERFCOUNTER14_CFG_BASE_IDX                                                    1
+#define regGCUTCL2_NHTTLB_PERFCOUNTER15_CFG                                                             0x3f0f
+#define regGCUTCL2_NHTTLB_PERFCOUNTER15_CFG_BASE_IDX                                                    1
+#define regGCUTCL2_NHTTLB_PERFCOUNTER_RSLT_CNTL                                                         0x3f10
+#define regGCUTCL2_NHTTLB_PERFCOUNTER_RSLT_CNTL_BASE_IDX                                                1
+
+
 // addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcl2tlbpldec
 // base address: 0x37c50
 #define regGC_L2TLB_PERFCOUNTER0_CFG                                                                    0x3f14
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_sh_mask.h
index f606c5cd03c5..1cf890de35cb 100644
--- a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_sh_mask.h
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_0_sh_mask.h
@@ -16951,6 +16951,15 @@
 #define CHA_PERFCOUNTER3_HI__PERFCOUNTER_HI_MASK                                                              0xFFFFFFFFL
 
 
+// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_perfddec
+//GC_CANE_PERFCOUNTER0_LO
+#define GC_CANE_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                        0x0
+#define GC_CANE_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                          0xFFFFFFFFL
+//GC_CANE_PERFCOUNTER0_HI
+#define GC_CANE_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                        0x0
+#define GC_CANE_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                          0xFFFFFFFFL
+
+
 // addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_cpwd_perfsdec
 //CPG_PERFCOUNTER1_SELECT
 #define CPG_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                              0x0
@@ -18123,6 +18132,46 @@
 #define CHA_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK                                                             0xF0000000L
 
 
+// addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_perfsdec
+//GC_CANE_PERFCOUNTER0_SELECT
+#define GC_CANE_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                          0x0
+#define GC_CANE_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                         0xa
+#define GC_CANE_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                         0x14
+#define GC_CANE_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT                                                        0x18
+#define GC_CANE_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT                                                         0x1c
+#define GC_CANE_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                            0x000003FFL
+#define GC_CANE_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                           0x000FFC00L
+#define GC_CANE_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                           0x00F00000L
+#define GC_CANE_PERFCOUNTER0_SELECT__PERF_MODE1_MASK                                                          0x0F000000L
+#define GC_CANE_PERFCOUNTER0_SELECT__PERF_MODE_MASK                                                           0xF0000000L
+//GC_CANE_PERFCOUNTER0_SELECT1
+#define GC_CANE_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                        0x0
+#define GC_CANE_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                        0xa
+#define GC_CANE_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT                                                       0x18
+#define GC_CANE_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT                                                       0x1c
+#define GC_CANE_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                          0x000003FFL
+#define GC_CANE_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                          0x000FFC00L
+#define GC_CANE_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK                                                         0x0F000000L
+#define GC_CANE_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK                                                         0xF0000000L
+//GC_CANE_PERFCOUNTER0_MODE
+#define GC_CANE_PERFCOUNTER0_MODE__COMPARE_MODE0__SHIFT                                                       0x0
+#define GC_CANE_PERFCOUNTER0_MODE__COMPARE_MODE1__SHIFT                                                       0x2
+#define GC_CANE_PERFCOUNTER0_MODE__COMPARE_MODE2__SHIFT                                                       0x4
+#define GC_CANE_PERFCOUNTER0_MODE__COMPARE_MODE3__SHIFT                                                       0x6
+#define GC_CANE_PERFCOUNTER0_MODE__COMPARE_VALUE0__SHIFT                                                      0x8
+#define GC_CANE_PERFCOUNTER0_MODE__COMPARE_VALUE1__SHIFT                                                      0xc
+#define GC_CANE_PERFCOUNTER0_MODE__COMPARE_VALUE2__SHIFT                                                      0x10
+#define GC_CANE_PERFCOUNTER0_MODE__COMPARE_VALUE3__SHIFT                                                      0x14
+#define GC_CANE_PERFCOUNTER0_MODE__COMPARE_MODE0_MASK                                                         0x00000003L
+#define GC_CANE_PERFCOUNTER0_MODE__COMPARE_MODE1_MASK                                                         0x0000000CL
+#define GC_CANE_PERFCOUNTER0_MODE__COMPARE_MODE2_MASK                                                         0x00000030L
+#define GC_CANE_PERFCOUNTER0_MODE__COMPARE_MODE3_MASK                                                         0x000000C0L
+#define GC_CANE_PERFCOUNTER0_MODE__COMPARE_VALUE0_MASK                                                        0x00000F00L
+#define GC_CANE_PERFCOUNTER0_MODE__COMPARE_VALUE1_MASK                                                        0x0000F000L
+#define GC_CANE_PERFCOUNTER0_MODE__COMPARE_VALUE2_MASK                                                        0x000F0000L
+#define GC_CANE_PERFCOUNTER0_MODE__COMPARE_VALUE3_MASK                                                        0x00F00000L
+
+
 // addressBlock: CHIP_XCD_gfxip_xcc_gfx_cpwd_gdfll_xvmin_xvmin_xvmin_reg_blk
 //XVMIN_XVMIN_WR_DATA
 #define XVMIN_XVMIN_WR_DATA__XVMINDATA__SHIFT                                                                 0x0
@@ -43203,6 +43252,28 @@
 #define GC_ATC_L2_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                          0xFFFF0000L
 
 
+// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcutcl2ffbmprdec
+//GCUTCL2_FFBM_PERFCOUNTER_LO
+#define GCUTCL2_FFBM_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                        0x0
+#define GCUTCL2_FFBM_PERFCOUNTER_LO__COUNTER_LO_MASK                                                          0xFFFFFFFFL
+//GCUTCL2_FFBM_PERFCOUNTER_HI
+#define GCUTCL2_FFBM_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                        0x0
+#define GCUTCL2_FFBM_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                     0x10
+#define GCUTCL2_FFBM_PERFCOUNTER_HI__COUNTER_HI_MASK                                                          0x0000FFFFL
+#define GCUTCL2_FFBM_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                       0xFFFF0000L
+
+
+// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcutcl2nhttlbprdec
+//GCUTCL2_NHTTLB_PERFCOUNTER_LO
+#define GCUTCL2_NHTTLB_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                      0x0
+#define GCUTCL2_NHTTLB_PERFCOUNTER_LO__COUNTER_LO_MASK                                                        0xFFFFFFFFL
+//GCUTCL2_NHTTLB_PERFCOUNTER_HI
+#define GCUTCL2_NHTTLB_PERFCOUNTER_HI__COUNTER_HI__SHIFT                                                      0x0
+#define GCUTCL2_NHTTLB_PERFCOUNTER_HI__COMPARE_VALUE__SHIFT                                                   0x10
+#define GCUTCL2_NHTTLB_PERFCOUNTER_HI__COUNTER_HI_MASK                                                        0x0000FFFFL
+#define GCUTCL2_NHTTLB_PERFCOUNTER_HI__COMPARE_VALUE_MASK                                                     0xFFFF0000L
+
+
 // addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcl2tlbprdec
 //GC_L2TLB_PERFCOUNTER_LO
 #define GC_L2TLB_PERFCOUNTER_LO__COUNTER_LO__SHIFT                                                            0x0
@@ -43660,6 +43731,390 @@
 #define GC_ATC_L2_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                            0x04000000L
 
 
+// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcutcl2ffbmpldec
+//GCUTCL2_FFBM_PERFCOUNTER0_CFG
+#define GCUTCL2_FFBM_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                        0x0
+#define GCUTCL2_FFBM_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                    0x8
+#define GCUTCL2_FFBM_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                       0x18
+#define GCUTCL2_FFBM_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                          0x1c
+#define GCUTCL2_FFBM_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                           0x1d
+#define GCUTCL2_FFBM_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                          0x000000FFL
+#define GCUTCL2_FFBM_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                      0x0000FF00L
+#define GCUTCL2_FFBM_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                         0x0F000000L
+#define GCUTCL2_FFBM_PERFCOUNTER0_CFG__ENABLE_MASK                                                            0x10000000L
+#define GCUTCL2_FFBM_PERFCOUNTER0_CFG__CLEAR_MASK                                                             0x20000000L
+//GCUTCL2_FFBM_PERFCOUNTER1_CFG
+#define GCUTCL2_FFBM_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                        0x0
+#define GCUTCL2_FFBM_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                    0x8
+#define GCUTCL2_FFBM_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                       0x18
+#define GCUTCL2_FFBM_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                          0x1c
+#define GCUTCL2_FFBM_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                           0x1d
+#define GCUTCL2_FFBM_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                          0x000000FFL
+#define GCUTCL2_FFBM_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                      0x0000FF00L
+#define GCUTCL2_FFBM_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                         0x0F000000L
+#define GCUTCL2_FFBM_PERFCOUNTER1_CFG__ENABLE_MASK                                                            0x10000000L
+#define GCUTCL2_FFBM_PERFCOUNTER1_CFG__CLEAR_MASK                                                             0x20000000L
+//GCUTCL2_FFBM_PERFCOUNTER2_CFG
+#define GCUTCL2_FFBM_PERFCOUNTER2_CFG__PERF_SEL__SHIFT                                                        0x0
+#define GCUTCL2_FFBM_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT                                                    0x8
+#define GCUTCL2_FFBM_PERFCOUNTER2_CFG__PERF_MODE__SHIFT                                                       0x18
+#define GCUTCL2_FFBM_PERFCOUNTER2_CFG__ENABLE__SHIFT                                                          0x1c
+#define GCUTCL2_FFBM_PERFCOUNTER2_CFG__CLEAR__SHIFT                                                           0x1d
+#define GCUTCL2_FFBM_PERFCOUNTER2_CFG__PERF_SEL_MASK                                                          0x000000FFL
+#define GCUTCL2_FFBM_PERFCOUNTER2_CFG__PERF_SEL_END_MASK                                                      0x0000FF00L
+#define GCUTCL2_FFBM_PERFCOUNTER2_CFG__PERF_MODE_MASK                                                         0x0F000000L
+#define GCUTCL2_FFBM_PERFCOUNTER2_CFG__ENABLE_MASK                                                            0x10000000L
+#define GCUTCL2_FFBM_PERFCOUNTER2_CFG__CLEAR_MASK                                                             0x20000000L
+//GCUTCL2_FFBM_PERFCOUNTER3_CFG
+#define GCUTCL2_FFBM_PERFCOUNTER3_CFG__PERF_SEL__SHIFT                                                        0x0
+#define GCUTCL2_FFBM_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT                                                    0x8
+#define GCUTCL2_FFBM_PERFCOUNTER3_CFG__PERF_MODE__SHIFT                                                       0x18
+#define GCUTCL2_FFBM_PERFCOUNTER3_CFG__ENABLE__SHIFT                                                          0x1c
+#define GCUTCL2_FFBM_PERFCOUNTER3_CFG__CLEAR__SHIFT                                                           0x1d
+#define GCUTCL2_FFBM_PERFCOUNTER3_CFG__PERF_SEL_MASK                                                          0x000000FFL
+#define GCUTCL2_FFBM_PERFCOUNTER3_CFG__PERF_SEL_END_MASK                                                      0x0000FF00L
+#define GCUTCL2_FFBM_PERFCOUNTER3_CFG__PERF_MODE_MASK                                                         0x0F000000L
+#define GCUTCL2_FFBM_PERFCOUNTER3_CFG__ENABLE_MASK                                                            0x10000000L
+#define GCUTCL2_FFBM_PERFCOUNTER3_CFG__CLEAR_MASK                                                             0x20000000L
+//GCUTCL2_FFBM_PERFCOUNTER4_CFG
+#define GCUTCL2_FFBM_PERFCOUNTER4_CFG__PERF_SEL__SHIFT                                                        0x0
+#define GCUTCL2_FFBM_PERFCOUNTER4_CFG__PERF_SEL_END__SHIFT                                                    0x8
+#define GCUTCL2_FFBM_PERFCOUNTER4_CFG__PERF_MODE__SHIFT                                                       0x18
+#define GCUTCL2_FFBM_PERFCOUNTER4_CFG__ENABLE__SHIFT                                                          0x1c
+#define GCUTCL2_FFBM_PERFCOUNTER4_CFG__CLEAR__SHIFT                                                           0x1d
+#define GCUTCL2_FFBM_PERFCOUNTER4_CFG__PERF_SEL_MASK                                                          0x000000FFL
+#define GCUTCL2_FFBM_PERFCOUNTER4_CFG__PERF_SEL_END_MASK                                                      0x0000FF00L
+#define GCUTCL2_FFBM_PERFCOUNTER4_CFG__PERF_MODE_MASK                                                         0x0F000000L
+#define GCUTCL2_FFBM_PERFCOUNTER4_CFG__ENABLE_MASK                                                            0x10000000L
+#define GCUTCL2_FFBM_PERFCOUNTER4_CFG__CLEAR_MASK                                                             0x20000000L
+//GCUTCL2_FFBM_PERFCOUNTER5_CFG
+#define GCUTCL2_FFBM_PERFCOUNTER5_CFG__PERF_SEL__SHIFT                                                        0x0
+#define GCUTCL2_FFBM_PERFCOUNTER5_CFG__PERF_SEL_END__SHIFT                                                    0x8
+#define GCUTCL2_FFBM_PERFCOUNTER5_CFG__PERF_MODE__SHIFT                                                       0x18
+#define GCUTCL2_FFBM_PERFCOUNTER5_CFG__ENABLE__SHIFT                                                          0x1c
+#define GCUTCL2_FFBM_PERFCOUNTER5_CFG__CLEAR__SHIFT                                                           0x1d
+#define GCUTCL2_FFBM_PERFCOUNTER5_CFG__PERF_SEL_MASK                                                          0x000000FFL
+#define GCUTCL2_FFBM_PERFCOUNTER5_CFG__PERF_SEL_END_MASK                                                      0x0000FF00L
+#define GCUTCL2_FFBM_PERFCOUNTER5_CFG__PERF_MODE_MASK                                                         0x0F000000L
+#define GCUTCL2_FFBM_PERFCOUNTER5_CFG__ENABLE_MASK                                                            0x10000000L
+#define GCUTCL2_FFBM_PERFCOUNTER5_CFG__CLEAR_MASK                                                             0x20000000L
+//GCUTCL2_FFBM_PERFCOUNTER6_CFG
+#define GCUTCL2_FFBM_PERFCOUNTER6_CFG__PERF_SEL__SHIFT                                                        0x0
+#define GCUTCL2_FFBM_PERFCOUNTER6_CFG__PERF_SEL_END__SHIFT                                                    0x8
+#define GCUTCL2_FFBM_PERFCOUNTER6_CFG__PERF_MODE__SHIFT                                                       0x18
+#define GCUTCL2_FFBM_PERFCOUNTER6_CFG__ENABLE__SHIFT                                                          0x1c
+#define GCUTCL2_FFBM_PERFCOUNTER6_CFG__CLEAR__SHIFT                                                           0x1d
+#define GCUTCL2_FFBM_PERFCOUNTER6_CFG__PERF_SEL_MASK                                                          0x000000FFL
+#define GCUTCL2_FFBM_PERFCOUNTER6_CFG__PERF_SEL_END_MASK                                                      0x0000FF00L
+#define GCUTCL2_FFBM_PERFCOUNTER6_CFG__PERF_MODE_MASK                                                         0x0F000000L
+#define GCUTCL2_FFBM_PERFCOUNTER6_CFG__ENABLE_MASK                                                            0x10000000L
+#define GCUTCL2_FFBM_PERFCOUNTER6_CFG__CLEAR_MASK                                                             0x20000000L
+//GCUTCL2_FFBM_PERFCOUNTER7_CFG
+#define GCUTCL2_FFBM_PERFCOUNTER7_CFG__PERF_SEL__SHIFT                                                        0x0
+#define GCUTCL2_FFBM_PERFCOUNTER7_CFG__PERF_SEL_END__SHIFT                                                    0x8
+#define GCUTCL2_FFBM_PERFCOUNTER7_CFG__PERF_MODE__SHIFT                                                       0x18
+#define GCUTCL2_FFBM_PERFCOUNTER7_CFG__ENABLE__SHIFT                                                          0x1c
+#define GCUTCL2_FFBM_PERFCOUNTER7_CFG__CLEAR__SHIFT                                                           0x1d
+#define GCUTCL2_FFBM_PERFCOUNTER7_CFG__PERF_SEL_MASK                                                          0x000000FFL
+#define GCUTCL2_FFBM_PERFCOUNTER7_CFG__PERF_SEL_END_MASK                                                      0x0000FF00L
+#define GCUTCL2_FFBM_PERFCOUNTER7_CFG__PERF_MODE_MASK                                                         0x0F000000L
+#define GCUTCL2_FFBM_PERFCOUNTER7_CFG__ENABLE_MASK                                                            0x10000000L
+#define GCUTCL2_FFBM_PERFCOUNTER7_CFG__CLEAR_MASK                                                             0x20000000L
+//GCUTCL2_FFBM_PERFCOUNTER8_CFG
+#define GCUTCL2_FFBM_PERFCOUNTER8_CFG__PERF_SEL__SHIFT                                                        0x0
+#define GCUTCL2_FFBM_PERFCOUNTER8_CFG__PERF_SEL_END__SHIFT                                                    0x8
+#define GCUTCL2_FFBM_PERFCOUNTER8_CFG__PERF_MODE__SHIFT                                                       0x18
+#define GCUTCL2_FFBM_PERFCOUNTER8_CFG__ENABLE__SHIFT                                                          0x1c
+#define GCUTCL2_FFBM_PERFCOUNTER8_CFG__CLEAR__SHIFT                                                           0x1d
+#define GCUTCL2_FFBM_PERFCOUNTER8_CFG__PERF_SEL_MASK                                                          0x000000FFL
+#define GCUTCL2_FFBM_PERFCOUNTER8_CFG__PERF_SEL_END_MASK                                                      0x0000FF00L
+#define GCUTCL2_FFBM_PERFCOUNTER8_CFG__PERF_MODE_MASK                                                         0x0F000000L
+#define GCUTCL2_FFBM_PERFCOUNTER8_CFG__ENABLE_MASK                                                            0x10000000L
+#define GCUTCL2_FFBM_PERFCOUNTER8_CFG__CLEAR_MASK                                                             0x20000000L
+//GCUTCL2_FFBM_PERFCOUNTER9_CFG
+#define GCUTCL2_FFBM_PERFCOUNTER9_CFG__PERF_SEL__SHIFT                                                        0x0
+#define GCUTCL2_FFBM_PERFCOUNTER9_CFG__PERF_SEL_END__SHIFT                                                    0x8
+#define GCUTCL2_FFBM_PERFCOUNTER9_CFG__PERF_MODE__SHIFT                                                       0x18
+#define GCUTCL2_FFBM_PERFCOUNTER9_CFG__ENABLE__SHIFT                                                          0x1c
+#define GCUTCL2_FFBM_PERFCOUNTER9_CFG__CLEAR__SHIFT                                                           0x1d
+#define GCUTCL2_FFBM_PERFCOUNTER9_CFG__PERF_SEL_MASK                                                          0x000000FFL
+#define GCUTCL2_FFBM_PERFCOUNTER9_CFG__PERF_SEL_END_MASK                                                      0x0000FF00L
+#define GCUTCL2_FFBM_PERFCOUNTER9_CFG__PERF_MODE_MASK                                                         0x0F000000L
+#define GCUTCL2_FFBM_PERFCOUNTER9_CFG__ENABLE_MASK                                                            0x10000000L
+#define GCUTCL2_FFBM_PERFCOUNTER9_CFG__CLEAR_MASK                                                             0x20000000L
+//GCUTCL2_FFBM_PERFCOUNTER10_CFG
+#define GCUTCL2_FFBM_PERFCOUNTER10_CFG__PERF_SEL__SHIFT                                                       0x0
+#define GCUTCL2_FFBM_PERFCOUNTER10_CFG__PERF_SEL_END__SHIFT                                                   0x8
+#define GCUTCL2_FFBM_PERFCOUNTER10_CFG__PERF_MODE__SHIFT                                                      0x18
+#define GCUTCL2_FFBM_PERFCOUNTER10_CFG__ENABLE__SHIFT                                                         0x1c
+#define GCUTCL2_FFBM_PERFCOUNTER10_CFG__CLEAR__SHIFT                                                          0x1d
+#define GCUTCL2_FFBM_PERFCOUNTER10_CFG__PERF_SEL_MASK                                                         0x000000FFL
+#define GCUTCL2_FFBM_PERFCOUNTER10_CFG__PERF_SEL_END_MASK                                                     0x0000FF00L
+#define GCUTCL2_FFBM_PERFCOUNTER10_CFG__PERF_MODE_MASK                                                        0x0F000000L
+#define GCUTCL2_FFBM_PERFCOUNTER10_CFG__ENABLE_MASK                                                           0x10000000L
+#define GCUTCL2_FFBM_PERFCOUNTER10_CFG__CLEAR_MASK                                                            0x20000000L
+//GCUTCL2_FFBM_PERFCOUNTER11_CFG
+#define GCUTCL2_FFBM_PERFCOUNTER11_CFG__PERF_SEL__SHIFT                                                       0x0
+#define GCUTCL2_FFBM_PERFCOUNTER11_CFG__PERF_SEL_END__SHIFT                                                   0x8
+#define GCUTCL2_FFBM_PERFCOUNTER11_CFG__PERF_MODE__SHIFT                                                      0x18
+#define GCUTCL2_FFBM_PERFCOUNTER11_CFG__ENABLE__SHIFT                                                         0x1c
+#define GCUTCL2_FFBM_PERFCOUNTER11_CFG__CLEAR__SHIFT                                                          0x1d
+#define GCUTCL2_FFBM_PERFCOUNTER11_CFG__PERF_SEL_MASK                                                         0x000000FFL
+#define GCUTCL2_FFBM_PERFCOUNTER11_CFG__PERF_SEL_END_MASK                                                     0x0000FF00L
+#define GCUTCL2_FFBM_PERFCOUNTER11_CFG__PERF_MODE_MASK                                                        0x0F000000L
+#define GCUTCL2_FFBM_PERFCOUNTER11_CFG__ENABLE_MASK                                                           0x10000000L
+#define GCUTCL2_FFBM_PERFCOUNTER11_CFG__CLEAR_MASK                                                            0x20000000L
+//GCUTCL2_FFBM_PERFCOUNTER12_CFG
+#define GCUTCL2_FFBM_PERFCOUNTER12_CFG__PERF_SEL__SHIFT                                                       0x0
+#define GCUTCL2_FFBM_PERFCOUNTER12_CFG__PERF_SEL_END__SHIFT                                                   0x8
+#define GCUTCL2_FFBM_PERFCOUNTER12_CFG__PERF_MODE__SHIFT                                                      0x18
+#define GCUTCL2_FFBM_PERFCOUNTER12_CFG__ENABLE__SHIFT                                                         0x1c
+#define GCUTCL2_FFBM_PERFCOUNTER12_CFG__CLEAR__SHIFT                                                          0x1d
+#define GCUTCL2_FFBM_PERFCOUNTER12_CFG__PERF_SEL_MASK                                                         0x000000FFL
+#define GCUTCL2_FFBM_PERFCOUNTER12_CFG__PERF_SEL_END_MASK                                                     0x0000FF00L
+#define GCUTCL2_FFBM_PERFCOUNTER12_CFG__PERF_MODE_MASK                                                        0x0F000000L
+#define GCUTCL2_FFBM_PERFCOUNTER12_CFG__ENABLE_MASK                                                           0x10000000L
+#define GCUTCL2_FFBM_PERFCOUNTER12_CFG__CLEAR_MASK                                                            0x20000000L
+//GCUTCL2_FFBM_PERFCOUNTER13_CFG
+#define GCUTCL2_FFBM_PERFCOUNTER13_CFG__PERF_SEL__SHIFT                                                       0x0
+#define GCUTCL2_FFBM_PERFCOUNTER13_CFG__PERF_SEL_END__SHIFT                                                   0x8
+#define GCUTCL2_FFBM_PERFCOUNTER13_CFG__PERF_MODE__SHIFT                                                      0x18
+#define GCUTCL2_FFBM_PERFCOUNTER13_CFG__ENABLE__SHIFT                                                         0x1c
+#define GCUTCL2_FFBM_PERFCOUNTER13_CFG__CLEAR__SHIFT                                                          0x1d
+#define GCUTCL2_FFBM_PERFCOUNTER13_CFG__PERF_SEL_MASK                                                         0x000000FFL
+#define GCUTCL2_FFBM_PERFCOUNTER13_CFG__PERF_SEL_END_MASK                                                     0x0000FF00L
+#define GCUTCL2_FFBM_PERFCOUNTER13_CFG__PERF_MODE_MASK                                                        0x0F000000L
+#define GCUTCL2_FFBM_PERFCOUNTER13_CFG__ENABLE_MASK                                                           0x10000000L
+#define GCUTCL2_FFBM_PERFCOUNTER13_CFG__CLEAR_MASK                                                            0x20000000L
+//GCUTCL2_FFBM_PERFCOUNTER14_CFG
+#define GCUTCL2_FFBM_PERFCOUNTER14_CFG__PERF_SEL__SHIFT                                                       0x0
+#define GCUTCL2_FFBM_PERFCOUNTER14_CFG__PERF_SEL_END__SHIFT                                                   0x8
+#define GCUTCL2_FFBM_PERFCOUNTER14_CFG__PERF_MODE__SHIFT                                                      0x18
+#define GCUTCL2_FFBM_PERFCOUNTER14_CFG__ENABLE__SHIFT                                                         0x1c
+#define GCUTCL2_FFBM_PERFCOUNTER14_CFG__CLEAR__SHIFT                                                          0x1d
+#define GCUTCL2_FFBM_PERFCOUNTER14_CFG__PERF_SEL_MASK                                                         0x000000FFL
+#define GCUTCL2_FFBM_PERFCOUNTER14_CFG__PERF_SEL_END_MASK                                                     0x0000FF00L
+#define GCUTCL2_FFBM_PERFCOUNTER14_CFG__PERF_MODE_MASK                                                        0x0F000000L
+#define GCUTCL2_FFBM_PERFCOUNTER14_CFG__ENABLE_MASK                                                           0x10000000L
+#define GCUTCL2_FFBM_PERFCOUNTER14_CFG__CLEAR_MASK                                                            0x20000000L
+//GCUTCL2_FFBM_PERFCOUNTER15_CFG
+#define GCUTCL2_FFBM_PERFCOUNTER15_CFG__PERF_SEL__SHIFT                                                       0x0
+#define GCUTCL2_FFBM_PERFCOUNTER15_CFG__PERF_SEL_END__SHIFT                                                   0x8
+#define GCUTCL2_FFBM_PERFCOUNTER15_CFG__PERF_MODE__SHIFT                                                      0x18
+#define GCUTCL2_FFBM_PERFCOUNTER15_CFG__ENABLE__SHIFT                                                         0x1c
+#define GCUTCL2_FFBM_PERFCOUNTER15_CFG__CLEAR__SHIFT                                                          0x1d
+#define GCUTCL2_FFBM_PERFCOUNTER15_CFG__PERF_SEL_MASK                                                         0x000000FFL
+#define GCUTCL2_FFBM_PERFCOUNTER15_CFG__PERF_SEL_END_MASK                                                     0x0000FF00L
+#define GCUTCL2_FFBM_PERFCOUNTER15_CFG__PERF_MODE_MASK                                                        0x0F000000L
+#define GCUTCL2_FFBM_PERFCOUNTER15_CFG__ENABLE_MASK                                                           0x10000000L
+#define GCUTCL2_FFBM_PERFCOUNTER15_CFG__CLEAR_MASK                                                            0x20000000L
+//GCUTCL2_FFBM_PERFCOUNTER_RSLT_CNTL
+#define GCUTCL2_FFBM_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                        0x0
+#define GCUTCL2_FFBM_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                              0x8
+#define GCUTCL2_FFBM_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                               0x10
+#define GCUTCL2_FFBM_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                                 0x18
+#define GCUTCL2_FFBM_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                                  0x19
+#define GCUTCL2_FFBM_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                       0x1a
+#define GCUTCL2_FFBM_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                          0x0000000FL
+#define GCUTCL2_FFBM_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                                0x0000FF00L
+#define GCUTCL2_FFBM_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                                 0x00FF0000L
+#define GCUTCL2_FFBM_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                                   0x01000000L
+#define GCUTCL2_FFBM_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                    0x02000000L
+#define GCUTCL2_FFBM_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                         0x04000000L
+
+
+// addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcutcl2nhttlbpldec
+//GCUTCL2_NHTTLB_PERFCOUNTER0_CFG
+#define GCUTCL2_NHTTLB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                      0x0
+#define GCUTCL2_NHTTLB_PERFCOUNTER0_CFG__PERF_SEL_END__SHIFT                                                  0x8
+#define GCUTCL2_NHTTLB_PERFCOUNTER0_CFG__PERF_MODE__SHIFT                                                     0x18
+#define GCUTCL2_NHTTLB_PERFCOUNTER0_CFG__ENABLE__SHIFT                                                        0x1c
+#define GCUTCL2_NHTTLB_PERFCOUNTER0_CFG__CLEAR__SHIFT                                                         0x1d
+#define GCUTCL2_NHTTLB_PERFCOUNTER0_CFG__PERF_SEL_MASK                                                        0x000000FFL
+#define GCUTCL2_NHTTLB_PERFCOUNTER0_CFG__PERF_SEL_END_MASK                                                    0x0000FF00L
+#define GCUTCL2_NHTTLB_PERFCOUNTER0_CFG__PERF_MODE_MASK                                                       0x0F000000L
+#define GCUTCL2_NHTTLB_PERFCOUNTER0_CFG__ENABLE_MASK                                                          0x10000000L
+#define GCUTCL2_NHTTLB_PERFCOUNTER0_CFG__CLEAR_MASK                                                           0x20000000L
+//GCUTCL2_NHTTLB_PERFCOUNTER1_CFG
+#define GCUTCL2_NHTTLB_PERFCOUNTER1_CFG__PERF_SEL__SHIFT                                                      0x0
+#define GCUTCL2_NHTTLB_PERFCOUNTER1_CFG__PERF_SEL_END__SHIFT                                                  0x8
+#define GCUTCL2_NHTTLB_PERFCOUNTER1_CFG__PERF_MODE__SHIFT                                                     0x18
+#define GCUTCL2_NHTTLB_PERFCOUNTER1_CFG__ENABLE__SHIFT                                                        0x1c
+#define GCUTCL2_NHTTLB_PERFCOUNTER1_CFG__CLEAR__SHIFT                                                         0x1d
+#define GCUTCL2_NHTTLB_PERFCOUNTER1_CFG__PERF_SEL_MASK                                                        0x000000FFL
+#define GCUTCL2_NHTTLB_PERFCOUNTER1_CFG__PERF_SEL_END_MASK                                                    0x0000FF00L
+#define GCUTCL2_NHTTLB_PERFCOUNTER1_CFG__PERF_MODE_MASK                                                       0x0F000000L
+#define GCUTCL2_NHTTLB_PERFCOUNTER1_CFG__ENABLE_MASK                                                          0x10000000L
+#define GCUTCL2_NHTTLB_PERFCOUNTER1_CFG__CLEAR_MASK                                                           0x20000000L
+//GCUTCL2_NHTTLB_PERFCOUNTER2_CFG
+#define GCUTCL2_NHTTLB_PERFCOUNTER2_CFG__PERF_SEL__SHIFT                                                      0x0
+#define GCUTCL2_NHTTLB_PERFCOUNTER2_CFG__PERF_SEL_END__SHIFT                                                  0x8
+#define GCUTCL2_NHTTLB_PERFCOUNTER2_CFG__PERF_MODE__SHIFT                                                     0x18
+#define GCUTCL2_NHTTLB_PERFCOUNTER2_CFG__ENABLE__SHIFT                                                        0x1c
+#define GCUTCL2_NHTTLB_PERFCOUNTER2_CFG__CLEAR__SHIFT                                                         0x1d
+#define GCUTCL2_NHTTLB_PERFCOUNTER2_CFG__PERF_SEL_MASK                                                        0x000000FFL
+#define GCUTCL2_NHTTLB_PERFCOUNTER2_CFG__PERF_SEL_END_MASK                                                    0x0000FF00L
+#define GCUTCL2_NHTTLB_PERFCOUNTER2_CFG__PERF_MODE_MASK                                                       0x0F000000L
+#define GCUTCL2_NHTTLB_PERFCOUNTER2_CFG__ENABLE_MASK                                                          0x10000000L
+#define GCUTCL2_NHTTLB_PERFCOUNTER2_CFG__CLEAR_MASK                                                           0x20000000L
+//GCUTCL2_NHTTLB_PERFCOUNTER3_CFG
+#define GCUTCL2_NHTTLB_PERFCOUNTER3_CFG__PERF_SEL__SHIFT                                                      0x0
+#define GCUTCL2_NHTTLB_PERFCOUNTER3_CFG__PERF_SEL_END__SHIFT                                                  0x8
+#define GCUTCL2_NHTTLB_PERFCOUNTER3_CFG__PERF_MODE__SHIFT                                                     0x18
+#define GCUTCL2_NHTTLB_PERFCOUNTER3_CFG__ENABLE__SHIFT                                                        0x1c
+#define GCUTCL2_NHTTLB_PERFCOUNTER3_CFG__CLEAR__SHIFT                                                         0x1d
+#define GCUTCL2_NHTTLB_PERFCOUNTER3_CFG__PERF_SEL_MASK                                                        0x000000FFL
+#define GCUTCL2_NHTTLB_PERFCOUNTER3_CFG__PERF_SEL_END_MASK                                                    0x0000FF00L
+#define GCUTCL2_NHTTLB_PERFCOUNTER3_CFG__PERF_MODE_MASK                                                       0x0F000000L
+#define GCUTCL2_NHTTLB_PERFCOUNTER3_CFG__ENABLE_MASK                                                          0x10000000L
+#define GCUTCL2_NHTTLB_PERFCOUNTER3_CFG__CLEAR_MASK                                                           0x20000000L
+//GCUTCL2_NHTTLB_PERFCOUNTER4_CFG
+#define GCUTCL2_NHTTLB_PERFCOUNTER4_CFG__PERF_SEL__SHIFT                                                      0x0
+#define GCUTCL2_NHTTLB_PERFCOUNTER4_CFG__PERF_SEL_END__SHIFT                                                  0x8
+#define GCUTCL2_NHTTLB_PERFCOUNTER4_CFG__PERF_MODE__SHIFT                                                     0x18
+#define GCUTCL2_NHTTLB_PERFCOUNTER4_CFG__ENABLE__SHIFT                                                        0x1c
+#define GCUTCL2_NHTTLB_PERFCOUNTER4_CFG__CLEAR__SHIFT                                                         0x1d
+#define GCUTCL2_NHTTLB_PERFCOUNTER4_CFG__PERF_SEL_MASK                                                        0x000000FFL
+#define GCUTCL2_NHTTLB_PERFCOUNTER4_CFG__PERF_SEL_END_MASK                                                    0x0000FF00L
+#define GCUTCL2_NHTTLB_PERFCOUNTER4_CFG__PERF_MODE_MASK                                                       0x0F000000L
+#define GCUTCL2_NHTTLB_PERFCOUNTER4_CFG__ENABLE_MASK                                                          0x10000000L
+#define GCUTCL2_NHTTLB_PERFCOUNTER4_CFG__CLEAR_MASK                                                           0x20000000L
+//GCUTCL2_NHTTLB_PERFCOUNTER5_CFG
+#define GCUTCL2_NHTTLB_PERFCOUNTER5_CFG__PERF_SEL__SHIFT                                                      0x0
+#define GCUTCL2_NHTTLB_PERFCOUNTER5_CFG__PERF_SEL_END__SHIFT                                                  0x8
+#define GCUTCL2_NHTTLB_PERFCOUNTER5_CFG__PERF_MODE__SHIFT                                                     0x18
+#define GCUTCL2_NHTTLB_PERFCOUNTER5_CFG__ENABLE__SHIFT                                                        0x1c
+#define GCUTCL2_NHTTLB_PERFCOUNTER5_CFG__CLEAR__SHIFT                                                         0x1d
+#define GCUTCL2_NHTTLB_PERFCOUNTER5_CFG__PERF_SEL_MASK                                                        0x000000FFL
+#define GCUTCL2_NHTTLB_PERFCOUNTER5_CFG__PERF_SEL_END_MASK                                                    0x0000FF00L
+#define GCUTCL2_NHTTLB_PERFCOUNTER5_CFG__PERF_MODE_MASK                                                       0x0F000000L
+#define GCUTCL2_NHTTLB_PERFCOUNTER5_CFG__ENABLE_MASK                                                          0x10000000L
+#define GCUTCL2_NHTTLB_PERFCOUNTER5_CFG__CLEAR_MASK                                                           0x20000000L
+//GCUTCL2_NHTTLB_PERFCOUNTER6_CFG
+#define GCUTCL2_NHTTLB_PERFCOUNTER6_CFG__PERF_SEL__SHIFT                                                      0x0
+#define GCUTCL2_NHTTLB_PERFCOUNTER6_CFG__PERF_SEL_END__SHIFT                                                  0x8
+#define GCUTCL2_NHTTLB_PERFCOUNTER6_CFG__PERF_MODE__SHIFT                                                     0x18
+#define GCUTCL2_NHTTLB_PERFCOUNTER6_CFG__ENABLE__SHIFT                                                        0x1c
+#define GCUTCL2_NHTTLB_PERFCOUNTER6_CFG__CLEAR__SHIFT                                                         0x1d
+#define GCUTCL2_NHTTLB_PERFCOUNTER6_CFG__PERF_SEL_MASK                                                        0x000000FFL
+#define GCUTCL2_NHTTLB_PERFCOUNTER6_CFG__PERF_SEL_END_MASK                                                    0x0000FF00L
+#define GCUTCL2_NHTTLB_PERFCOUNTER6_CFG__PERF_MODE_MASK                                                       0x0F000000L
+#define GCUTCL2_NHTTLB_PERFCOUNTER6_CFG__ENABLE_MASK                                                          0x10000000L
+#define GCUTCL2_NHTTLB_PERFCOUNTER6_CFG__CLEAR_MASK                                                           0x20000000L
+//GCUTCL2_NHTTLB_PERFCOUNTER7_CFG
+#define GCUTCL2_NHTTLB_PERFCOUNTER7_CFG__PERF_SEL__SHIFT                                                      0x0
+#define GCUTCL2_NHTTLB_PERFCOUNTER7_CFG__PERF_SEL_END__SHIFT                                                  0x8
+#define GCUTCL2_NHTTLB_PERFCOUNTER7_CFG__PERF_MODE__SHIFT                                                     0x18
+#define GCUTCL2_NHTTLB_PERFCOUNTER7_CFG__ENABLE__SHIFT                                                        0x1c
+#define GCUTCL2_NHTTLB_PERFCOUNTER7_CFG__CLEAR__SHIFT                                                         0x1d
+#define GCUTCL2_NHTTLB_PERFCOUNTER7_CFG__PERF_SEL_MASK                                                        0x000000FFL
+#define GCUTCL2_NHTTLB_PERFCOUNTER7_CFG__PERF_SEL_END_MASK                                                    0x0000FF00L
+#define GCUTCL2_NHTTLB_PERFCOUNTER7_CFG__PERF_MODE_MASK                                                       0x0F000000L
+#define GCUTCL2_NHTTLB_PERFCOUNTER7_CFG__ENABLE_MASK                                                          0x10000000L
+#define GCUTCL2_NHTTLB_PERFCOUNTER7_CFG__CLEAR_MASK                                                           0x20000000L
+//GCUTCL2_NHTTLB_PERFCOUNTER8_CFG
+#define GCUTCL2_NHTTLB_PERFCOUNTER8_CFG__PERF_SEL__SHIFT                                                      0x0
+#define GCUTCL2_NHTTLB_PERFCOUNTER8_CFG__PERF_SEL_END__SHIFT                                                  0x8
+#define GCUTCL2_NHTTLB_PERFCOUNTER8_CFG__PERF_MODE__SHIFT                                                     0x18
+#define GCUTCL2_NHTTLB_PERFCOUNTER8_CFG__ENABLE__SHIFT                                                        0x1c
+#define GCUTCL2_NHTTLB_PERFCOUNTER8_CFG__CLEAR__SHIFT                                                         0x1d
+#define GCUTCL2_NHTTLB_PERFCOUNTER8_CFG__PERF_SEL_MASK                                                        0x000000FFL
+#define GCUTCL2_NHTTLB_PERFCOUNTER8_CFG__PERF_SEL_END_MASK                                                    0x0000FF00L
+#define GCUTCL2_NHTTLB_PERFCOUNTER8_CFG__PERF_MODE_MASK                                                       0x0F000000L
+#define GCUTCL2_NHTTLB_PERFCOUNTER8_CFG__ENABLE_MASK                                                          0x10000000L
+#define GCUTCL2_NHTTLB_PERFCOUNTER8_CFG__CLEAR_MASK                                                           0x20000000L
+//GCUTCL2_NHTTLB_PERFCOUNTER9_CFG
+#define GCUTCL2_NHTTLB_PERFCOUNTER9_CFG__PERF_SEL__SHIFT                                                      0x0
+#define GCUTCL2_NHTTLB_PERFCOUNTER9_CFG__PERF_SEL_END__SHIFT                                                  0x8
+#define GCUTCL2_NHTTLB_PERFCOUNTER9_CFG__PERF_MODE__SHIFT                                                     0x18
+#define GCUTCL2_NHTTLB_PERFCOUNTER9_CFG__ENABLE__SHIFT                                                        0x1c
+#define GCUTCL2_NHTTLB_PERFCOUNTER9_CFG__CLEAR__SHIFT                                                         0x1d
+#define GCUTCL2_NHTTLB_PERFCOUNTER9_CFG__PERF_SEL_MASK                                                        0x000000FFL
+#define GCUTCL2_NHTTLB_PERFCOUNTER9_CFG__PERF_SEL_END_MASK                                                    0x0000FF00L
+#define GCUTCL2_NHTTLB_PERFCOUNTER9_CFG__PERF_MODE_MASK                                                       0x0F000000L
+#define GCUTCL2_NHTTLB_PERFCOUNTER9_CFG__ENABLE_MASK                                                          0x10000000L
+#define GCUTCL2_NHTTLB_PERFCOUNTER9_CFG__CLEAR_MASK                                                           0x20000000L
+//GCUTCL2_NHTTLB_PERFCOUNTER10_CFG
+#define GCUTCL2_NHTTLB_PERFCOUNTER10_CFG__PERF_SEL__SHIFT                                                     0x0
+#define GCUTCL2_NHTTLB_PERFCOUNTER10_CFG__PERF_SEL_END__SHIFT                                                 0x8
+#define GCUTCL2_NHTTLB_PERFCOUNTER10_CFG__PERF_MODE__SHIFT                                                    0x18
+#define GCUTCL2_NHTTLB_PERFCOUNTER10_CFG__ENABLE__SHIFT                                                       0x1c
+#define GCUTCL2_NHTTLB_PERFCOUNTER10_CFG__CLEAR__SHIFT                                                        0x1d
+#define GCUTCL2_NHTTLB_PERFCOUNTER10_CFG__PERF_SEL_MASK                                                       0x000000FFL
+#define GCUTCL2_NHTTLB_PERFCOUNTER10_CFG__PERF_SEL_END_MASK                                                   0x0000FF00L
+#define GCUTCL2_NHTTLB_PERFCOUNTER10_CFG__PERF_MODE_MASK                                                      0x0F000000L
+#define GCUTCL2_NHTTLB_PERFCOUNTER10_CFG__ENABLE_MASK                                                         0x10000000L
+#define GCUTCL2_NHTTLB_PERFCOUNTER10_CFG__CLEAR_MASK                                                          0x20000000L
+//GCUTCL2_NHTTLB_PERFCOUNTER11_CFG
+#define GCUTCL2_NHTTLB_PERFCOUNTER11_CFG__PERF_SEL__SHIFT                                                     0x0
+#define GCUTCL2_NHTTLB_PERFCOUNTER11_CFG__PERF_SEL_END__SHIFT                                                 0x8
+#define GCUTCL2_NHTTLB_PERFCOUNTER11_CFG__PERF_MODE__SHIFT                                                    0x18
+#define GCUTCL2_NHTTLB_PERFCOUNTER11_CFG__ENABLE__SHIFT                                                       0x1c
+#define GCUTCL2_NHTTLB_PERFCOUNTER11_CFG__CLEAR__SHIFT                                                        0x1d
+#define GCUTCL2_NHTTLB_PERFCOUNTER11_CFG__PERF_SEL_MASK                                                       0x000000FFL
+#define GCUTCL2_NHTTLB_PERFCOUNTER11_CFG__PERF_SEL_END_MASK                                                   0x0000FF00L
+#define GCUTCL2_NHTTLB_PERFCOUNTER11_CFG__PERF_MODE_MASK                                                      0x0F000000L
+#define GCUTCL2_NHTTLB_PERFCOUNTER11_CFG__ENABLE_MASK                                                         0x10000000L
+#define GCUTCL2_NHTTLB_PERFCOUNTER11_CFG__CLEAR_MASK                                                          0x20000000L
+//GCUTCL2_NHTTLB_PERFCOUNTER12_CFG
+#define GCUTCL2_NHTTLB_PERFCOUNTER12_CFG__PERF_SEL__SHIFT                                                     0x0
+#define GCUTCL2_NHTTLB_PERFCOUNTER12_CFG__PERF_SEL_END__SHIFT                                                 0x8
+#define GCUTCL2_NHTTLB_PERFCOUNTER12_CFG__PERF_MODE__SHIFT                                                    0x18
+#define GCUTCL2_NHTTLB_PERFCOUNTER12_CFG__ENABLE__SHIFT                                                       0x1c
+#define GCUTCL2_NHTTLB_PERFCOUNTER12_CFG__CLEAR__SHIFT                                                        0x1d
+#define GCUTCL2_NHTTLB_PERFCOUNTER12_CFG__PERF_SEL_MASK                                                       0x000000FFL
+#define GCUTCL2_NHTTLB_PERFCOUNTER12_CFG__PERF_SEL_END_MASK                                                   0x0000FF00L
+#define GCUTCL2_NHTTLB_PERFCOUNTER12_CFG__PERF_MODE_MASK                                                      0x0F000000L
+#define GCUTCL2_NHTTLB_PERFCOUNTER12_CFG__ENABLE_MASK                                                         0x10000000L
+#define GCUTCL2_NHTTLB_PERFCOUNTER12_CFG__CLEAR_MASK                                                          0x20000000L
+//GCUTCL2_NHTTLB_PERFCOUNTER13_CFG
+#define GCUTCL2_NHTTLB_PERFCOUNTER13_CFG__PERF_SEL__SHIFT                                                     0x0
+#define GCUTCL2_NHTTLB_PERFCOUNTER13_CFG__PERF_SEL_END__SHIFT                                                 0x8
+#define GCUTCL2_NHTTLB_PERFCOUNTER13_CFG__PERF_MODE__SHIFT                                                    0x18
+#define GCUTCL2_NHTTLB_PERFCOUNTER13_CFG__ENABLE__SHIFT                                                       0x1c
+#define GCUTCL2_NHTTLB_PERFCOUNTER13_CFG__CLEAR__SHIFT                                                        0x1d
+#define GCUTCL2_NHTTLB_PERFCOUNTER13_CFG__PERF_SEL_MASK                                                       0x000000FFL
+#define GCUTCL2_NHTTLB_PERFCOUNTER13_CFG__PERF_SEL_END_MASK                                                   0x0000FF00L
+#define GCUTCL2_NHTTLB_PERFCOUNTER13_CFG__PERF_MODE_MASK                                                      0x0F000000L
+#define GCUTCL2_NHTTLB_PERFCOUNTER13_CFG__ENABLE_MASK                                                         0x10000000L
+#define GCUTCL2_NHTTLB_PERFCOUNTER13_CFG__CLEAR_MASK                                                          0x20000000L
+//GCUTCL2_NHTTLB_PERFCOUNTER14_CFG
+#define GCUTCL2_NHTTLB_PERFCOUNTER14_CFG__PERF_SEL__SHIFT                                                     0x0
+#define GCUTCL2_NHTTLB_PERFCOUNTER14_CFG__PERF_SEL_END__SHIFT                                                 0x8
+#define GCUTCL2_NHTTLB_PERFCOUNTER14_CFG__PERF_MODE__SHIFT                                                    0x18
+#define GCUTCL2_NHTTLB_PERFCOUNTER14_CFG__ENABLE__SHIFT                                                       0x1c
+#define GCUTCL2_NHTTLB_PERFCOUNTER14_CFG__CLEAR__SHIFT                                                        0x1d
+#define GCUTCL2_NHTTLB_PERFCOUNTER14_CFG__PERF_SEL_MASK                                                       0x000000FFL
+#define GCUTCL2_NHTTLB_PERFCOUNTER14_CFG__PERF_SEL_END_MASK                                                   0x0000FF00L
+#define GCUTCL2_NHTTLB_PERFCOUNTER14_CFG__PERF_MODE_MASK                                                      0x0F000000L
+#define GCUTCL2_NHTTLB_PERFCOUNTER14_CFG__ENABLE_MASK                                                         0x10000000L
+#define GCUTCL2_NHTTLB_PERFCOUNTER14_CFG__CLEAR_MASK                                                          0x20000000L
+//GCUTCL2_NHTTLB_PERFCOUNTER15_CFG
+#define GCUTCL2_NHTTLB_PERFCOUNTER15_CFG__PERF_SEL__SHIFT                                                     0x0
+#define GCUTCL2_NHTTLB_PERFCOUNTER15_CFG__PERF_SEL_END__SHIFT                                                 0x8
+#define GCUTCL2_NHTTLB_PERFCOUNTER15_CFG__PERF_MODE__SHIFT                                                    0x18
+#define GCUTCL2_NHTTLB_PERFCOUNTER15_CFG__ENABLE__SHIFT                                                       0x1c
+#define GCUTCL2_NHTTLB_PERFCOUNTER15_CFG__CLEAR__SHIFT                                                        0x1d
+#define GCUTCL2_NHTTLB_PERFCOUNTER15_CFG__PERF_SEL_MASK                                                       0x000000FFL
+#define GCUTCL2_NHTTLB_PERFCOUNTER15_CFG__PERF_SEL_END_MASK                                                   0x0000FF00L
+#define GCUTCL2_NHTTLB_PERFCOUNTER15_CFG__PERF_MODE_MASK                                                      0x0F000000L
+#define GCUTCL2_NHTTLB_PERFCOUNTER15_CFG__ENABLE_MASK                                                         0x10000000L
+#define GCUTCL2_NHTTLB_PERFCOUNTER15_CFG__CLEAR_MASK                                                          0x20000000L
+//GCUTCL2_NHTTLB_PERFCOUNTER_RSLT_CNTL
+#define GCUTCL2_NHTTLB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT__SHIFT                                      0x0
+#define GCUTCL2_NHTTLB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER__SHIFT                                            0x8
+#define GCUTCL2_NHTTLB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER__SHIFT                                             0x10
+#define GCUTCL2_NHTTLB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY__SHIFT                                               0x18
+#define GCUTCL2_NHTTLB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL__SHIFT                                                0x19
+#define GCUTCL2_NHTTLB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE__SHIFT                                     0x1a
+#define GCUTCL2_NHTTLB_PERFCOUNTER_RSLT_CNTL__PERF_COUNTER_SELECT_MASK                                        0x0000000FL
+#define GCUTCL2_NHTTLB_PERFCOUNTER_RSLT_CNTL__START_TRIGGER_MASK                                              0x0000FF00L
+#define GCUTCL2_NHTTLB_PERFCOUNTER_RSLT_CNTL__STOP_TRIGGER_MASK                                               0x00FF0000L
+#define GCUTCL2_NHTTLB_PERFCOUNTER_RSLT_CNTL__ENABLE_ANY_MASK                                                 0x01000000L
+#define GCUTCL2_NHTTLB_PERFCOUNTER_RSLT_CNTL__CLEAR_ALL_MASK                                                  0x02000000L
+#define GCUTCL2_NHTTLB_PERFCOUNTER_RSLT_CNTL__STOP_ALL_ON_SATURATE_MASK                                       0x04000000L
+
+
 // addressBlock: CHIP_XCD_gfxip_aigc_gcutcl2_inst0_gcl2tlbpldec
 //GC_L2TLB_PERFCOUNTER0_CFG
 #define GC_L2TLB_PERFCOUNTER0_CFG__PERF_SEL__SHIFT                                                            0x0
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_1_offset.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_1_offset.h
new file mode 100755
index 000000000000..f10e6168ad54
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_1_offset.h
@@ -0,0 +1,149 @@
+/*
+ * Copyright 2025 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#ifndef _gc_12_1_1_OFFSET_HEADER
+#define _gc_12_1_1_OFFSET_HEADER
+
+
+
+// addressBlock: aigc_grbma_grbma_grbmadec
+// base address: 0x18000
+#define regGRBMA_GFX_INDEX                                                                              0x0011
+#define regGRBMA_GFX_INDEX_BASE_IDX                                                                     1
+
+
+// addressBlock: aigc_grbma_grbma_perfddec
+// base address: 0x19200
+#define regGRBMA_PERFCOUNTER0_LO                                                                        0x0480
+#define regGRBMA_PERFCOUNTER0_LO_BASE_IDX                                                               1
+#define regGRBMA_PERFCOUNTER0_HI                                                                        0x0481
+#define regGRBMA_PERFCOUNTER0_HI_BASE_IDX                                                               1
+#define regGRBMA_PERFCOUNTER1_LO                                                                        0x0482
+#define regGRBMA_PERFCOUNTER1_LO_BASE_IDX                                                               1
+#define regGRBMA_PERFCOUNTER1_HI                                                                        0x0483
+#define regGRBMA_PERFCOUNTER1_HI_BASE_IDX                                                               1
+
+
+// addressBlock: aigc_grbma_grbma_perfsdec
+// base address: 0x19300
+#define regGRBMA_PERFCOUNTER0_SELECT                                                                    0x04c0
+#define regGRBMA_PERFCOUNTER0_SELECT_BASE_IDX                                                           1
+#define regGRBMA_PERFCOUNTER1_SELECT                                                                    0x04c1
+#define regGRBMA_PERFCOUNTER1_SELECT_BASE_IDX                                                           1
+#define regAID_PERFMON_CNTL                                                                             0x04c2
+#define regAID_PERFMON_CNTL_BASE_IDX                                                                    1
+
+
+// addressBlock: aigc_gl2x_gfx_se_perfsdec
+// base address: 0x19300
+#define regGL2C_PERFCOUNTER0_SELECT                                                                     0x04e8
+#define regGL2C_PERFCOUNTER0_SELECT_BASE_IDX                                                            1
+#define regGL2C_PERFCOUNTER0_SELECT1                                                                    0x04e9
+#define regGL2C_PERFCOUNTER0_SELECT1_BASE_IDX                                                           1
+#define regGL2C_PERFCOUNTER1_SELECT                                                                     0x04ea
+#define regGL2C_PERFCOUNTER1_SELECT_BASE_IDX                                                            1
+#define regGL2C_PERFCOUNTER1_SELECT1                                                                    0x04eb
+#define regGL2C_PERFCOUNTER1_SELECT1_BASE_IDX                                                           1
+#define regGL2C_PERFCOUNTER2_SELECT                                                                     0x04ec
+#define regGL2C_PERFCOUNTER2_SELECT_BASE_IDX                                                            1
+#define regGL2C_PERFCOUNTER2_SELECT1                                                                    0x04ed
+#define regGL2C_PERFCOUNTER2_SELECT1_BASE_IDX                                                           1
+#define regGL2C_PERFCOUNTER3_SELECT                                                                     0x04ee
+#define regGL2C_PERFCOUNTER3_SELECT_BASE_IDX                                                            1
+#define regGL2C_PERFCOUNTER3_SELECT1                                                                    0x04ef
+#define regGL2C_PERFCOUNTER3_SELECT1_BASE_IDX                                                           1
+#define regGL2A_PERFCOUNTER0_SELECT                                                                     0x04f0
+#define regGL2A_PERFCOUNTER0_SELECT_BASE_IDX                                                            1
+#define regGL2A_PERFCOUNTER0_SELECT1                                                                    0x04f1
+#define regGL2A_PERFCOUNTER0_SELECT1_BASE_IDX                                                           1
+#define regGL2A_PERFCOUNTER1_SELECT                                                                     0x04f2
+#define regGL2A_PERFCOUNTER1_SELECT_BASE_IDX                                                            1
+#define regGL2A_PERFCOUNTER1_SELECT1                                                                    0x04f3
+#define regGL2A_PERFCOUNTER1_SELECT1_BASE_IDX                                                           1
+#define regGL2A_PERFCOUNTER2_SELECT                                                                     0x04f4
+#define regGL2A_PERFCOUNTER2_SELECT_BASE_IDX                                                            1
+#define regGL2A_PERFCOUNTER2_SELECT1                                                                    0x04f5
+#define regGL2A_PERFCOUNTER2_SELECT1_BASE_IDX                                                           1
+#define regGL2A_PERFCOUNTER3_SELECT                                                                     0x04f6
+#define regGL2A_PERFCOUNTER3_SELECT_BASE_IDX                                                            1
+#define regGL2A_PERFCOUNTER3_SELECT1                                                                    0x04f7
+#define regGL2A_PERFCOUNTER3_SELECT1_BASE_IDX                                                           1
+
+
+// addressBlock: aigc_gl2x_gfx_se_perfddec
+// base address: 0x19200
+#define regGL2C_PERFCOUNTER0_LO                                                                         0x04a0
+#define regGL2C_PERFCOUNTER0_LO_BASE_IDX                                                                1
+#define regGL2C_PERFCOUNTER0_HI                                                                         0x04a1
+#define regGL2C_PERFCOUNTER0_HI_BASE_IDX                                                                1
+#define regGL2C_PERFCOUNTER1_LO                                                                         0x04a2
+#define regGL2C_PERFCOUNTER1_LO_BASE_IDX                                                                1
+#define regGL2C_PERFCOUNTER1_HI                                                                         0x04a3
+#define regGL2C_PERFCOUNTER1_HI_BASE_IDX                                                                1
+#define regGL2C_PERFCOUNTER2_LO                                                                         0x04a4
+#define regGL2C_PERFCOUNTER2_LO_BASE_IDX                                                                1
+#define regGL2C_PERFCOUNTER2_HI                                                                         0x04a5
+#define regGL2C_PERFCOUNTER2_HI_BASE_IDX                                                                1
+#define regGL2C_PERFCOUNTER3_LO                                                                         0x04a6
+#define regGL2C_PERFCOUNTER3_LO_BASE_IDX                                                                1
+#define regGL2C_PERFCOUNTER3_HI                                                                         0x04a7
+#define regGL2C_PERFCOUNTER3_HI_BASE_IDX                                                                1
+#define regGL2A_PERFCOUNTER0_LO                                                                         0x04a8
+#define regGL2A_PERFCOUNTER0_LO_BASE_IDX                                                                1
+#define regGL2A_PERFCOUNTER0_HI                                                                         0x04a9
+#define regGL2A_PERFCOUNTER0_HI_BASE_IDX                                                                1
+#define regGL2A_PERFCOUNTER1_LO                                                                         0x04aa
+#define regGL2A_PERFCOUNTER1_LO_BASE_IDX                                                                1
+#define regGL2A_PERFCOUNTER1_HI                                                                         0x04ab
+#define regGL2A_PERFCOUNTER1_HI_BASE_IDX                                                                1
+#define regGL2A_PERFCOUNTER2_LO                                                                         0x04ac
+#define regGL2A_PERFCOUNTER2_LO_BASE_IDX                                                                1
+#define regGL2A_PERFCOUNTER2_HI                                                                         0x04ad
+#define regGL2A_PERFCOUNTER2_HI_BASE_IDX                                                                1
+#define regGL2A_PERFCOUNTER3_LO                                                                         0x04ae
+#define regGL2A_PERFCOUNTER3_LO_BASE_IDX                                                                1
+#define regGL2A_PERFCOUNTER3_HI                                                                         0x04af
+#define regGL2A_PERFCOUNTER3_HI_BASE_IDX                                                                1
+
+
+// addressBlock: aigc_gfx_gcea_se_gfx_se_perfsdec
+// base address: 0x19320
+#define regGC_EA_SE_PERFCOUNTER0_SELECT                                                                 0x04c8
+#define regGC_EA_SE_PERFCOUNTER0_SELECT_BASE_IDX                                                        1
+#define regGC_EA_SE_PERFCOUNTER0_SELECT1                                                                0x04c9
+#define regGC_EA_SE_PERFCOUNTER0_SELECT1_BASE_IDX                                                       1
+#define regGC_EA_SE_PERFCOUNTER1_SELECT                                                                 0x04ca
+#define regGC_EA_SE_PERFCOUNTER1_SELECT_BASE_IDX                                                        1
+
+
+// addressBlock: aigc_gfx_gcea_se_gfx_se_perfddec
+// base address: 0x19240
+#define regGC_EA_SE_PERFCOUNTER0_LO                                                                     0x0490
+#define regGC_EA_SE_PERFCOUNTER0_LO_BASE_IDX                                                            1
+#define regGC_EA_SE_PERFCOUNTER0_HI                                                                     0x0491
+#define regGC_EA_SE_PERFCOUNTER0_HI_BASE_IDX                                                            1
+#define regGC_EA_SE_PERFCOUNTER1_LO                                                                     0x0492
+#define regGC_EA_SE_PERFCOUNTER1_LO_BASE_IDX                                                            1
+#define regGC_EA_SE_PERFCOUNTER1_HI                                                                     0x0493
+#define regGC_EA_SE_PERFCOUNTER1_HI_BASE_IDX                                                            1
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_1_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_1_sh_mask.h
new file mode 100755
index 000000000000..8d09c8150a53
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/gc/gc_12_1_1_sh_mask.h
@@ -0,0 +1,377 @@
+/*
+ * Copyright 2025 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#ifndef _gc_12_1_1_SH_MASK_HEADER
+#define _gc_12_1_1_SH_MASK_HEADER
+
+
+// addressBlock: aigc_grbma_grbma_grbmadec
+//GRBMA_GFX_INDEX
+#define GRBMA_GFX_INDEX__INSTANCE_INDEX__SHIFT                                                                0x0
+#define GRBMA_GFX_INDEX__SA_INDEX__SHIFT                                                                      0x8
+#define GRBMA_GFX_INDEX__SE_INDEX__SHIFT                                                                      0x10
+#define GRBMA_GFX_INDEX__SA_BROADCAST_WRITES__SHIFT                                                           0x1d
+#define GRBMA_GFX_INDEX__INSTANCE_BROADCAST_WRITES__SHIFT                                                     0x1e
+#define GRBMA_GFX_INDEX__SE_BROADCAST_WRITES__SHIFT                                                           0x1f
+#define GRBMA_GFX_INDEX__INSTANCE_INDEX_MASK                                                                  0x0000007FL
+#define GRBMA_GFX_INDEX__SA_INDEX_MASK                                                                        0x00000300L
+#define GRBMA_GFX_INDEX__SE_INDEX_MASK                                                                        0x000F0000L
+#define GRBMA_GFX_INDEX__SA_BROADCAST_WRITES_MASK                                                             0x20000000L
+#define GRBMA_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK                                                       0x40000000L
+#define GRBMA_GFX_INDEX__SE_BROADCAST_WRITES_MASK                                                             0x80000000L
+
+
+// addressBlock: aigc_grbma_grbma_perfddec
+//GRBMA_PERFCOUNTER0_LO
+#define GRBMA_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                          0x0
+#define GRBMA_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                            0xFFFFFFFFL
+//GRBMA_PERFCOUNTER0_HI
+#define GRBMA_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                          0x0
+#define GRBMA_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                            0xFFFFFFFFL
+//GRBMA_PERFCOUNTER1_LO
+#define GRBMA_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                          0x0
+#define GRBMA_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                            0xFFFFFFFFL
+//GRBMA_PERFCOUNTER1_HI
+#define GRBMA_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                          0x0
+#define GRBMA_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                            0xFFFFFFFFL
+
+
+// addressBlock: aigc_grbma_grbma_perfsdec
+//GRBMA_PERFCOUNTER0_SELECT
+#define GRBMA_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                            0x0
+#define GRBMA_PERFCOUNTER0_SELECT__GL1CC_BUSY_USER_DEFINED_MASK__SHIFT                                        0x6
+#define GRBMA_PERFCOUNTER0_SELECT__GL1XCC_BUSY_USER_DEFINED_MASK__SHIFT                                       0x7
+#define GRBMA_PERFCOUNTER0_SELECT__PMR_BUSY_USER_DEFINED_MASK__SHIFT                                          0x8
+#define GRBMA_PERFCOUNTER0_SELECT__SC_CLEAN_USER_DEFINED_MASK__SHIFT                                          0x9
+#define GRBMA_PERFCOUNTER0_SELECT__WGS_BUSY_USER_DEFINED_MASK__SHIFT                                          0xa
+#define GRBMA_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT                                          0xb
+#define GRBMA_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT                                          0xc
+#define GRBMA_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT                                           0xd
+#define GRBMA_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT                                           0xe
+#define GRBMA_PERFCOUNTER0_SELECT__GL2C_BUSY_USER_DEFINED_MASK__SHIFT                                         0xf
+#define GRBMA_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT                                          0x10
+#define GRBMA_PERFCOUNTER0_SELECT__XCAC_BUSY_USER_DEFINED_MASK__SHIFT                                         0x11
+#define GRBMA_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT                                           0x12
+#define GRBMA_PERFCOUNTER0_SELECT__GL2A_BUSY_USER_DEFINED_MASK__SHIFT                                         0x13
+#define GRBMA_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT                                           0x14
+#define GRBMA_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT                                           0x15
+#define GRBMA_PERFCOUNTER0_SELECT__EA_LINK_BUSY_USER_DEFINED_MASK__SHIFT                                      0x17
+#define GRBMA_PERFCOUNTER0_SELECT__AIGC_CAC_BUSY_USER_DEFINED_MASK__SHIFT                                     0x18
+#define GRBMA_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT                                          0x19
+#define GRBMA_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT                                          0x1a
+#define GRBMA_PERFCOUNTER0_SELECT__TCP_BUSY_USER_DEFINED_MASK__SHIFT                                          0x1b
+#define GRBMA_PERFCOUNTER0_SELECT__GE_BUSY_USER_DEFINED_MASK__SHIFT                                           0x1c
+#define GRBMA_PERFCOUNTER0_SELECT__UTCL1_BUSY_USER_DEFINED_MASK__SHIFT                                        0x1d
+#define GRBMA_PERFCOUNTER0_SELECT__EA_BUSY_USER_DEFINED_MASK__SHIFT                                           0x1e
+#define GRBMA_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                              0x0000003FL
+#define GRBMA_PERFCOUNTER0_SELECT__GL1CC_BUSY_USER_DEFINED_MASK_MASK                                          0x00000040L
+#define GRBMA_PERFCOUNTER0_SELECT__GL1XCC_BUSY_USER_DEFINED_MASK_MASK                                         0x00000080L
+#define GRBMA_PERFCOUNTER0_SELECT__PMR_BUSY_USER_DEFINED_MASK_MASK                                            0x00000100L
+#define GRBMA_PERFCOUNTER0_SELECT__SC_CLEAN_USER_DEFINED_MASK_MASK                                            0x00000200L
+#define GRBMA_PERFCOUNTER0_SELECT__WGS_BUSY_USER_DEFINED_MASK_MASK                                            0x00000400L
+#define GRBMA_PERFCOUNTER0_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK                                            0x00000800L
+#define GRBMA_PERFCOUNTER0_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK                                            0x00001000L
+#define GRBMA_PERFCOUNTER0_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK                                             0x00002000L
+#define GRBMA_PERFCOUNTER0_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK                                             0x00004000L
+#define GRBMA_PERFCOUNTER0_SELECT__GL2C_BUSY_USER_DEFINED_MASK_MASK                                           0x00008000L
+#define GRBMA_PERFCOUNTER0_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK                                            0x00010000L
+#define GRBMA_PERFCOUNTER0_SELECT__XCAC_BUSY_USER_DEFINED_MASK_MASK                                           0x00020000L
+#define GRBMA_PERFCOUNTER0_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK                                             0x00040000L
+#define GRBMA_PERFCOUNTER0_SELECT__GL2A_BUSY_USER_DEFINED_MASK_MASK                                           0x00080000L
+#define GRBMA_PERFCOUNTER0_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK                                             0x00100000L
+#define GRBMA_PERFCOUNTER0_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK                                             0x00200000L
+#define GRBMA_PERFCOUNTER0_SELECT__EA_LINK_BUSY_USER_DEFINED_MASK_MASK                                        0x00800000L
+#define GRBMA_PERFCOUNTER0_SELECT__AIGC_CAC_BUSY_USER_DEFINED_MASK_MASK                                       0x01000000L
+#define GRBMA_PERFCOUNTER0_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK                                            0x02000000L
+#define GRBMA_PERFCOUNTER0_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK                                            0x04000000L
+#define GRBMA_PERFCOUNTER0_SELECT__TCP_BUSY_USER_DEFINED_MASK_MASK                                            0x08000000L
+#define GRBMA_PERFCOUNTER0_SELECT__GE_BUSY_USER_DEFINED_MASK_MASK                                             0x10000000L
+#define GRBMA_PERFCOUNTER0_SELECT__UTCL1_BUSY_USER_DEFINED_MASK_MASK                                          0x20000000L
+#define GRBMA_PERFCOUNTER0_SELECT__EA_BUSY_USER_DEFINED_MASK_MASK                                             0x40000000L
+//GRBMA_PERFCOUNTER1_SELECT
+#define GRBMA_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                            0x0
+#define GRBMA_PERFCOUNTER1_SELECT__GL1CC_BUSY_USER_DEFINED_MASK__SHIFT                                        0x6
+#define GRBMA_PERFCOUNTER1_SELECT__GL1XCC_BUSY_USER_DEFINED_MASK__SHIFT                                       0x7
+#define GRBMA_PERFCOUNTER1_SELECT__PMR_BUSY_USER_DEFINED_MASK__SHIFT                                          0x8
+#define GRBMA_PERFCOUNTER1_SELECT__SC_CLEAN_USER_DEFINED_MASK__SHIFT                                          0x9
+#define GRBMA_PERFCOUNTER1_SELECT__WGS_BUSY_USER_DEFINED_MASK__SHIFT                                          0xa
+#define GRBMA_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK__SHIFT                                          0xb
+#define GRBMA_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK__SHIFT                                          0xc
+#define GRBMA_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK__SHIFT                                           0xd
+#define GRBMA_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK__SHIFT                                           0xe
+#define GRBMA_PERFCOUNTER1_SELECT__GL2C_BUSY_USER_DEFINED_MASK__SHIFT                                         0xf
+#define GRBMA_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK__SHIFT                                          0x10
+#define GRBMA_PERFCOUNTER1_SELECT__XCAC_BUSY_USER_DEFINED_MASK__SHIFT                                         0x11
+#define GRBMA_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK__SHIFT                                           0x12
+#define GRBMA_PERFCOUNTER1_SELECT__GL2A_BUSY_USER_DEFINED_MASK__SHIFT                                         0x13
+#define GRBMA_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK__SHIFT                                           0x14
+#define GRBMA_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK__SHIFT                                           0x15
+#define GRBMA_PERFCOUNTER1_SELECT__EA_LINK_BUSY_USER_DEFINED_MASK__SHIFT                                      0x17
+#define GRBMA_PERFCOUNTER1_SELECT__AIGC_CAC_BUSY_USER_DEFINED_MASK__SHIFT                                     0x18
+#define GRBMA_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK__SHIFT                                          0x19
+#define GRBMA_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK__SHIFT                                          0x1a
+#define GRBMA_PERFCOUNTER1_SELECT__TCP_BUSY_USER_DEFINED_MASK__SHIFT                                          0x1b
+#define GRBMA_PERFCOUNTER1_SELECT__GE_BUSY_USER_DEFINED_MASK__SHIFT                                           0x1c
+#define GRBMA_PERFCOUNTER1_SELECT__UTCL1_BUSY_USER_DEFINED_MASK__SHIFT                                        0x1d
+#define GRBMA_PERFCOUNTER1_SELECT__EA_BUSY_USER_DEFINED_MASK__SHIFT                                           0x1e
+#define GRBMA_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                              0x0000003FL
+#define GRBMA_PERFCOUNTER1_SELECT__GL1CC_BUSY_USER_DEFINED_MASK_MASK                                          0x00000040L
+#define GRBMA_PERFCOUNTER1_SELECT__GL1XCC_BUSY_USER_DEFINED_MASK_MASK                                         0x00000080L
+#define GRBMA_PERFCOUNTER1_SELECT__PMR_BUSY_USER_DEFINED_MASK_MASK                                            0x00000100L
+#define GRBMA_PERFCOUNTER1_SELECT__SC_CLEAN_USER_DEFINED_MASK_MASK                                            0x00000200L
+#define GRBMA_PERFCOUNTER1_SELECT__WGS_BUSY_USER_DEFINED_MASK_MASK                                            0x00000400L
+#define GRBMA_PERFCOUNTER1_SELECT__DB_CLEAN_USER_DEFINED_MASK_MASK                                            0x00000800L
+#define GRBMA_PERFCOUNTER1_SELECT__CB_CLEAN_USER_DEFINED_MASK_MASK                                            0x00001000L
+#define GRBMA_PERFCOUNTER1_SELECT__TA_BUSY_USER_DEFINED_MASK_MASK                                             0x00002000L
+#define GRBMA_PERFCOUNTER1_SELECT__SX_BUSY_USER_DEFINED_MASK_MASK                                             0x00004000L
+#define GRBMA_PERFCOUNTER1_SELECT__GL2C_BUSY_USER_DEFINED_MASK_MASK                                           0x00008000L
+#define GRBMA_PERFCOUNTER1_SELECT__SPI_BUSY_USER_DEFINED_MASK_MASK                                            0x00010000L
+#define GRBMA_PERFCOUNTER1_SELECT__XCAC_BUSY_USER_DEFINED_MASK_MASK                                           0x00020000L
+#define GRBMA_PERFCOUNTER1_SELECT__PA_BUSY_USER_DEFINED_MASK_MASK                                             0x00040000L
+#define GRBMA_PERFCOUNTER1_SELECT__GL2A_BUSY_USER_DEFINED_MASK_MASK                                           0x00080000L
+#define GRBMA_PERFCOUNTER1_SELECT__DB_BUSY_USER_DEFINED_MASK_MASK                                             0x00100000L
+#define GRBMA_PERFCOUNTER1_SELECT__CB_BUSY_USER_DEFINED_MASK_MASK                                             0x00200000L
+#define GRBMA_PERFCOUNTER1_SELECT__EA_LINK_BUSY_USER_DEFINED_MASK_MASK                                        0x00800000L
+#define GRBMA_PERFCOUNTER1_SELECT__AIGC_CAC_BUSY_USER_DEFINED_MASK_MASK                                       0x01000000L
+#define GRBMA_PERFCOUNTER1_SELECT__BCI_BUSY_USER_DEFINED_MASK_MASK                                            0x02000000L
+#define GRBMA_PERFCOUNTER1_SELECT__RLC_BUSY_USER_DEFINED_MASK_MASK                                            0x04000000L
+#define GRBMA_PERFCOUNTER1_SELECT__TCP_BUSY_USER_DEFINED_MASK_MASK                                            0x08000000L
+#define GRBMA_PERFCOUNTER1_SELECT__GE_BUSY_USER_DEFINED_MASK_MASK                                             0x10000000L
+#define GRBMA_PERFCOUNTER1_SELECT__UTCL1_BUSY_USER_DEFINED_MASK_MASK                                          0x20000000L
+#define GRBMA_PERFCOUNTER1_SELECT__EA_BUSY_USER_DEFINED_MASK_MASK                                             0x40000000L
+//AID_PERFMON_CNTL
+#define AID_PERFMON_CNTL__PERFMON_STATE__SHIFT                                                                0x0
+#define AID_PERFMON_CNTL__SPM_PERFMON_STATE__SHIFT                                                            0x4
+#define AID_PERFMON_CNTL__PERFMON_ENABLE_MODE__SHIFT                                                          0x8
+#define AID_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE__SHIFT                                                        0xa
+#define AID_PERFMON_CNTL__PERFMON_STATE_MASK                                                                  0x0000000FL
+#define AID_PERFMON_CNTL__SPM_PERFMON_STATE_MASK                                                              0x000000F0L
+#define AID_PERFMON_CNTL__PERFMON_ENABLE_MODE_MASK                                                            0x00000300L
+#define AID_PERFMON_CNTL__PERFMON_SAMPLE_ENABLE_MASK                                                          0x00000400L
+
+
+// addressBlock: aigc_gl2x_gfx_se_perfsdec
+//GL2C_PERFCOUNTER0_SELECT
+#define GL2C_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                             0x0
+#define GL2C_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                            0xa
+#define GL2C_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                            0x14
+#define GL2C_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT                                                           0x18
+#define GL2C_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT                                                            0x1c
+#define GL2C_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                               0x000003FFL
+#define GL2C_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                              0x000FFC00L
+#define GL2C_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                              0x00F00000L
+#define GL2C_PERFCOUNTER0_SELECT__PERF_MODE1_MASK                                                             0x0F000000L
+#define GL2C_PERFCOUNTER0_SELECT__PERF_MODE_MASK                                                              0xF0000000L
+//GL2C_PERFCOUNTER0_SELECT1
+#define GL2C_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                           0x0
+#define GL2C_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                           0xa
+#define GL2C_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT                                                          0x18
+#define GL2C_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT                                                          0x1c
+#define GL2C_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                             0x000003FFL
+#define GL2C_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                             0x000FFC00L
+#define GL2C_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK                                                            0x0F000000L
+#define GL2C_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK                                                            0xF0000000L
+//GL2C_PERFCOUNTER1_SELECT
+#define GL2C_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                             0x0
+#define GL2C_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT                                                            0xa
+#define GL2C_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT                                                            0x14
+#define GL2C_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT                                                           0x18
+#define GL2C_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT                                                            0x1c
+#define GL2C_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                               0x000003FFL
+#define GL2C_PERFCOUNTER1_SELECT__PERF_SEL1_MASK                                                              0x000FFC00L
+#define GL2C_PERFCOUNTER1_SELECT__CNTR_MODE_MASK                                                              0x00F00000L
+#define GL2C_PERFCOUNTER1_SELECT__PERF_MODE1_MASK                                                             0x0F000000L
+#define GL2C_PERFCOUNTER1_SELECT__PERF_MODE_MASK                                                              0xF0000000L
+//GL2C_PERFCOUNTER1_SELECT1
+#define GL2C_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT                                                           0x0
+#define GL2C_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT                                                           0xa
+#define GL2C_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT                                                          0x18
+#define GL2C_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT                                                          0x1c
+#define GL2C_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK                                                             0x000003FFL
+#define GL2C_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK                                                             0x000FFC00L
+#define GL2C_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK                                                            0x0F000000L
+#define GL2C_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK                                                            0xF0000000L
+//GL2C_PERFCOUNTER2_SELECT
+#define GL2C_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT                                                             0x0
+#define GL2C_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT                                                            0xa
+#define GL2C_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT                                                            0x14
+#define GL2C_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT                                                           0x18
+#define GL2C_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT                                                            0x1c
+#define GL2C_PERFCOUNTER2_SELECT__PERF_SEL_MASK                                                               0x000003FFL
+#define GL2C_PERFCOUNTER2_SELECT__PERF_SEL1_MASK                                                              0x000FFC00L
+#define GL2C_PERFCOUNTER2_SELECT__CNTR_MODE_MASK                                                              0x00F00000L
+#define GL2C_PERFCOUNTER2_SELECT__PERF_MODE1_MASK                                                             0x0F000000L
+#define GL2C_PERFCOUNTER2_SELECT__PERF_MODE_MASK                                                              0xF0000000L
+//GL2C_PERFCOUNTER2_SELECT1
+#define GL2C_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT                                                           0x0
+#define GL2C_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT                                                           0xa
+#define GL2C_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT                                                          0x18
+#define GL2C_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT                                                          0x1c
+#define GL2C_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK                                                             0x000003FFL
+#define GL2C_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK                                                             0x000FFC00L
+#define GL2C_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK                                                            0x0F000000L
+#define GL2C_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK                                                            0xF0000000L
+//GL2C_PERFCOUNTER3_SELECT
+#define GL2C_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT                                                             0x0
+#define GL2C_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT                                                            0xa
+#define GL2C_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT                                                            0x14
+#define GL2C_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT                                                           0x18
+#define GL2C_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT                                                            0x1c
+#define GL2C_PERFCOUNTER3_SELECT__PERF_SEL_MASK                                                               0x000003FFL
+#define GL2C_PERFCOUNTER3_SELECT__PERF_SEL1_MASK                                                              0x000FFC00L
+#define GL2C_PERFCOUNTER3_SELECT__CNTR_MODE_MASK                                                              0x00F00000L
+#define GL2C_PERFCOUNTER3_SELECT__PERF_MODE1_MASK                                                             0x0F000000L
+#define GL2C_PERFCOUNTER3_SELECT__PERF_MODE_MASK                                                              0xF0000000L
+//GL2C_PERFCOUNTER3_SELECT1
+#define GL2C_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT                                                           0x0
+#define GL2C_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT                                                           0xa
+#define GL2C_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT                                                          0x18
+#define GL2C_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT                                                          0x1c
+#define GL2C_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK                                                             0x000003FFL
+#define GL2C_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK                                                             0x000FFC00L
+#define GL2C_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK                                                            0x0F000000L
+#define GL2C_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK                                                            0xF0000000L
+//GL2A_PERFCOUNTER0_SELECT
+#define GL2A_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                             0x0
+#define GL2A_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                            0xa
+#define GL2A_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                            0x14
+#define GL2A_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT                                                           0x18
+#define GL2A_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT                                                            0x1c
+#define GL2A_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                               0x000003FFL
+#define GL2A_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                              0x000FFC00L
+#define GL2A_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                              0x00F00000L
+#define GL2A_PERFCOUNTER0_SELECT__PERF_MODE1_MASK                                                             0x0F000000L
+#define GL2A_PERFCOUNTER0_SELECT__PERF_MODE_MASK                                                              0xF0000000L
+//GL2A_PERFCOUNTER0_SELECT1
+#define GL2A_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                           0x0
+#define GL2A_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                           0xa
+#define GL2A_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT                                                          0x18
+#define GL2A_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT                                                          0x1c
+#define GL2A_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                             0x000003FFL
+#define GL2A_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                             0x000FFC00L
+#define GL2A_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK                                                            0x0F000000L
+#define GL2A_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK                                                            0xF0000000L
+//GL2A_PERFCOUNTER1_SELECT
+#define GL2A_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                             0x0
+#define GL2A_PERFCOUNTER1_SELECT__PERF_SEL1__SHIFT                                                            0xa
+#define GL2A_PERFCOUNTER1_SELECT__CNTR_MODE__SHIFT                                                            0x14
+#define GL2A_PERFCOUNTER1_SELECT__PERF_MODE1__SHIFT                                                           0x18
+#define GL2A_PERFCOUNTER1_SELECT__PERF_MODE__SHIFT                                                            0x1c
+#define GL2A_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                               0x000003FFL
+#define GL2A_PERFCOUNTER1_SELECT__PERF_SEL1_MASK                                                              0x000FFC00L
+#define GL2A_PERFCOUNTER1_SELECT__CNTR_MODE_MASK                                                              0x00F00000L
+#define GL2A_PERFCOUNTER1_SELECT__PERF_MODE1_MASK                                                             0x0F000000L
+#define GL2A_PERFCOUNTER1_SELECT__PERF_MODE_MASK                                                              0xF0000000L
+//GL2A_PERFCOUNTER1_SELECT1
+#define GL2A_PERFCOUNTER1_SELECT1__PERF_SEL2__SHIFT                                                           0x0
+#define GL2A_PERFCOUNTER1_SELECT1__PERF_SEL3__SHIFT                                                           0xa
+#define GL2A_PERFCOUNTER1_SELECT1__PERF_MODE3__SHIFT                                                          0x18
+#define GL2A_PERFCOUNTER1_SELECT1__PERF_MODE2__SHIFT                                                          0x1c
+#define GL2A_PERFCOUNTER1_SELECT1__PERF_SEL2_MASK                                                             0x000003FFL
+#define GL2A_PERFCOUNTER1_SELECT1__PERF_SEL3_MASK                                                             0x000FFC00L
+#define GL2A_PERFCOUNTER1_SELECT1__PERF_MODE3_MASK                                                            0x0F000000L
+#define GL2A_PERFCOUNTER1_SELECT1__PERF_MODE2_MASK                                                            0xF0000000L
+//GL2A_PERFCOUNTER2_SELECT
+#define GL2A_PERFCOUNTER2_SELECT__PERF_SEL__SHIFT                                                             0x0
+#define GL2A_PERFCOUNTER2_SELECT__PERF_SEL1__SHIFT                                                            0xa
+#define GL2A_PERFCOUNTER2_SELECT__CNTR_MODE__SHIFT                                                            0x14
+#define GL2A_PERFCOUNTER2_SELECT__PERF_MODE1__SHIFT                                                           0x18
+#define GL2A_PERFCOUNTER2_SELECT__PERF_MODE__SHIFT                                                            0x1c
+#define GL2A_PERFCOUNTER2_SELECT__PERF_SEL_MASK                                                               0x000003FFL
+#define GL2A_PERFCOUNTER2_SELECT__PERF_SEL1_MASK                                                              0x000FFC00L
+#define GL2A_PERFCOUNTER2_SELECT__CNTR_MODE_MASK                                                              0x00F00000L
+#define GL2A_PERFCOUNTER2_SELECT__PERF_MODE1_MASK                                                             0x0F000000L
+#define GL2A_PERFCOUNTER2_SELECT__PERF_MODE_MASK                                                              0xF0000000L
+//GL2A_PERFCOUNTER2_SELECT1
+#define GL2A_PERFCOUNTER2_SELECT1__PERF_SEL2__SHIFT                                                           0x0
+#define GL2A_PERFCOUNTER2_SELECT1__PERF_SEL3__SHIFT                                                           0xa
+#define GL2A_PERFCOUNTER2_SELECT1__PERF_MODE3__SHIFT                                                          0x18
+#define GL2A_PERFCOUNTER2_SELECT1__PERF_MODE2__SHIFT                                                          0x1c
+#define GL2A_PERFCOUNTER2_SELECT1__PERF_SEL2_MASK                                                             0x000003FFL
+#define GL2A_PERFCOUNTER2_SELECT1__PERF_SEL3_MASK                                                             0x000FFC00L
+#define GL2A_PERFCOUNTER2_SELECT1__PERF_MODE3_MASK                                                            0x0F000000L
+#define GL2A_PERFCOUNTER2_SELECT1__PERF_MODE2_MASK                                                            0xF0000000L
+//GL2A_PERFCOUNTER3_SELECT
+#define GL2A_PERFCOUNTER3_SELECT__PERF_SEL__SHIFT                                                             0x0
+#define GL2A_PERFCOUNTER3_SELECT__PERF_SEL1__SHIFT                                                            0xa
+#define GL2A_PERFCOUNTER3_SELECT__CNTR_MODE__SHIFT                                                            0x14
+#define GL2A_PERFCOUNTER3_SELECT__PERF_MODE1__SHIFT                                                           0x18
+#define GL2A_PERFCOUNTER3_SELECT__PERF_MODE__SHIFT                                                            0x1c
+#define GL2A_PERFCOUNTER3_SELECT__PERF_SEL_MASK                                                               0x000003FFL
+#define GL2A_PERFCOUNTER3_SELECT__PERF_SEL1_MASK                                                              0x000FFC00L
+#define GL2A_PERFCOUNTER3_SELECT__CNTR_MODE_MASK                                                              0x00F00000L
+#define GL2A_PERFCOUNTER3_SELECT__PERF_MODE1_MASK                                                             0x0F000000L
+#define GL2A_PERFCOUNTER3_SELECT__PERF_MODE_MASK                                                              0xF0000000L
+//GL2A_PERFCOUNTER3_SELECT1
+#define GL2A_PERFCOUNTER3_SELECT1__PERF_SEL2__SHIFT                                                           0x0
+#define GL2A_PERFCOUNTER3_SELECT1__PERF_SEL3__SHIFT                                                           0xa
+#define GL2A_PERFCOUNTER3_SELECT1__PERF_MODE3__SHIFT                                                          0x18
+#define GL2A_PERFCOUNTER3_SELECT1__PERF_MODE2__SHIFT                                                          0x1c
+#define GL2A_PERFCOUNTER3_SELECT1__PERF_SEL2_MASK                                                             0x000003FFL
+#define GL2A_PERFCOUNTER3_SELECT1__PERF_SEL3_MASK                                                             0x000FFC00L
+#define GL2A_PERFCOUNTER3_SELECT1__PERF_MODE3_MASK                                                            0x0F000000L
+#define GL2A_PERFCOUNTER3_SELECT1__PERF_MODE2_MASK                                                            0xF0000000L
+
+
+// addressBlock: aigc_gfx_gcea_se_gfx_se_perfsdec
+//GC_EA_SE_PERFCOUNTER0_SELECT
+#define GC_EA_SE_PERFCOUNTER0_SELECT__PERF_SEL__SHIFT                                                         0x0
+#define GC_EA_SE_PERFCOUNTER0_SELECT__PERF_SEL1__SHIFT                                                        0xa
+#define GC_EA_SE_PERFCOUNTER0_SELECT__CNTR_MODE__SHIFT                                                        0x14
+#define GC_EA_SE_PERFCOUNTER0_SELECT__PERF_MODE1__SHIFT                                                       0x18
+#define GC_EA_SE_PERFCOUNTER0_SELECT__PERF_MODE__SHIFT                                                        0x1c
+#define GC_EA_SE_PERFCOUNTER0_SELECT__PERF_SEL_MASK                                                           0x000003FFL
+#define GC_EA_SE_PERFCOUNTER0_SELECT__PERF_SEL1_MASK                                                          0x000FFC00L
+#define GC_EA_SE_PERFCOUNTER0_SELECT__CNTR_MODE_MASK                                                          0x00F00000L
+#define GC_EA_SE_PERFCOUNTER0_SELECT__PERF_MODE1_MASK                                                         0x0F000000L
+#define GC_EA_SE_PERFCOUNTER0_SELECT__PERF_MODE_MASK                                                          0xF0000000L
+//GC_EA_SE_PERFCOUNTER0_SELECT1
+#define GC_EA_SE_PERFCOUNTER0_SELECT1__PERF_SEL2__SHIFT                                                       0x0
+#define GC_EA_SE_PERFCOUNTER0_SELECT1__PERF_SEL3__SHIFT                                                       0xa
+#define GC_EA_SE_PERFCOUNTER0_SELECT1__PERF_MODE3__SHIFT                                                      0x18
+#define GC_EA_SE_PERFCOUNTER0_SELECT1__PERF_MODE2__SHIFT                                                      0x1c
+#define GC_EA_SE_PERFCOUNTER0_SELECT1__PERF_SEL2_MASK                                                         0x000003FFL
+#define GC_EA_SE_PERFCOUNTER0_SELECT1__PERF_SEL3_MASK                                                         0x000FFC00L
+#define GC_EA_SE_PERFCOUNTER0_SELECT1__PERF_MODE3_MASK                                                        0x0F000000L
+#define GC_EA_SE_PERFCOUNTER0_SELECT1__PERF_MODE2_MASK                                                        0xF0000000L
+//GC_EA_SE_PERFCOUNTER1_SELECT
+#define GC_EA_SE_PERFCOUNTER1_SELECT__PERF_SEL__SHIFT                                                         0x0
+#define GC_EA_SE_PERFCOUNTER1_SELECT__COUNTER_MODE__SHIFT                                                     0x1c
+#define GC_EA_SE_PERFCOUNTER1_SELECT__PERF_SEL_MASK                                                           0x000003FFL
+#define GC_EA_SE_PERFCOUNTER1_SELECT__COUNTER_MODE_MASK                                                       0xF0000000L
+
+
+// addressBlock: aigc_gfx_gcea_se_gfx_se_perfddec
+//GC_EA_SE_PERFCOUNTER0_LO
+#define GC_EA_SE_PERFCOUNTER0_LO__PERFCOUNTER_LO__SHIFT                                                       0x0
+#define GC_EA_SE_PERFCOUNTER0_LO__PERFCOUNTER_LO_MASK                                                         0xFFFFFFFFL
+//GC_EA_SE_PERFCOUNTER0_HI
+#define GC_EA_SE_PERFCOUNTER0_HI__PERFCOUNTER_HI__SHIFT                                                       0x0
+#define GC_EA_SE_PERFCOUNTER0_HI__PERFCOUNTER_HI_MASK                                                         0xFFFFFFFFL
+//GC_EA_SE_PERFCOUNTER1_LO
+#define GC_EA_SE_PERFCOUNTER1_LO__PERFCOUNTER_LO__SHIFT                                                       0x0
+#define GC_EA_SE_PERFCOUNTER1_LO__PERFCOUNTER_LO_MASK                                                         0xFFFFFFFFL
+//GC_EA_SE_PERFCOUNTER1_HI
+#define GC_EA_SE_PERFCOUNTER1_HI__PERFCOUNTER_HI__SHIFT                                                       0x0
+#define GC_EA_SE_PERFCOUNTER1_HI__PERFCOUNTER_HI_MASK                                                         0xFFFFFFFFL
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_3_2_offset.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_3_2_offset.h
new file mode 100644
index 000000000000..0b42c1c9c848
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_3_2_offset.h
@@ -0,0 +1,13149 @@
+/*
+ * Copyright 2025 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#ifndef _nbio_6_3_2_OFFSET_HEADER
+#define _nbio_6_3_2_OFFSET_HEADER
+
+
+
+// addressBlock: nbif0_nbif0_bif_bx_SYSDEC
+// base address: 0x0
+#define regBIF_BX0_SYSHUB_INDEX_OVLP                                                                    0x0008
+#define regBIF_BX0_SYSHUB_INDEX_OVLP_BASE_IDX                                                           0
+#define regBIF_BX0_SYSHUB_DATA_OVLP                                                                     0x0009
+#define regBIF_BX0_SYSHUB_DATA_OVLP_BASE_IDX                                                            0
+#define regBIF_BX0_SYSHUB_INDEX_HI_OVLP                                                                 0x000a
+#define regBIF_BX0_SYSHUB_INDEX_HI_OVLP_BASE_IDX                                                        0
+#define regBIF_BX0_PCIE_INDEX                                                                           0x000c
+#define regBIF_BX0_PCIE_INDEX_BASE_IDX                                                                  0
+#define regBIF_BX0_PCIE_DATA                                                                            0x000d
+#define regBIF_BX0_PCIE_DATA_BASE_IDX                                                                   0
+#define regBIF_BX0_PCIE_INDEX2                                                                          0x000e
+#define regBIF_BX0_PCIE_INDEX2_BASE_IDX                                                                 0
+#define regBIF_BX0_PCIE_DATA2                                                                           0x000f
+#define regBIF_BX0_PCIE_DATA2_BASE_IDX                                                                  0
+#define regBIF_BX0_PCIE_INDEX_HI                                                                        0x0010
+#define regBIF_BX0_PCIE_INDEX_HI_BASE_IDX                                                               0
+#define regBIF_BX0_PCIE_INDEX2_HI                                                                       0x0011
+#define regBIF_BX0_PCIE_INDEX2_HI_BASE_IDX                                                              0
+#define regBIF_BX0_SBIOS_SCRATCH_0                                                                      0x0034
+#define regBIF_BX0_SBIOS_SCRATCH_0_BASE_IDX                                                             1
+#define regBIF_BX0_SBIOS_SCRATCH_1                                                                      0x0035
+#define regBIF_BX0_SBIOS_SCRATCH_1_BASE_IDX                                                             1
+#define regBIF_BX0_SBIOS_SCRATCH_2                                                                      0x0036
+#define regBIF_BX0_SBIOS_SCRATCH_2_BASE_IDX                                                             1
+#define regBIF_BX0_SBIOS_SCRATCH_3                                                                      0x0037
+#define regBIF_BX0_SBIOS_SCRATCH_3_BASE_IDX                                                             1
+#define regBIF_BX0_BIOS_SCRATCH_0                                                                       0x0038
+#define regBIF_BX0_BIOS_SCRATCH_0_BASE_IDX                                                              1
+#define regBIF_BX0_BIOS_SCRATCH_1                                                                       0x0039
+#define regBIF_BX0_BIOS_SCRATCH_1_BASE_IDX                                                              1
+#define regBIF_BX0_BIOS_SCRATCH_2                                                                       0x003a
+#define regBIF_BX0_BIOS_SCRATCH_2_BASE_IDX                                                              1
+#define regBIF_BX0_BIOS_SCRATCH_3                                                                       0x003b
+#define regBIF_BX0_BIOS_SCRATCH_3_BASE_IDX                                                              1
+#define regBIF_BX0_BIOS_SCRATCH_4                                                                       0x003c
+#define regBIF_BX0_BIOS_SCRATCH_4_BASE_IDX                                                              1
+#define regBIF_BX0_BIOS_SCRATCH_5                                                                       0x003d
+#define regBIF_BX0_BIOS_SCRATCH_5_BASE_IDX                                                              1
+#define regBIF_BX0_BIOS_SCRATCH_6                                                                       0x003e
+#define regBIF_BX0_BIOS_SCRATCH_6_BASE_IDX                                                              1
+#define regBIF_BX0_BIOS_SCRATCH_7                                                                       0x003f
+#define regBIF_BX0_BIOS_SCRATCH_7_BASE_IDX                                                              1
+#define regBIF_BX0_BIOS_SCRATCH_8                                                                       0x0040
+#define regBIF_BX0_BIOS_SCRATCH_8_BASE_IDX                                                              1
+#define regBIF_BX0_BIOS_SCRATCH_9                                                                       0x0041
+#define regBIF_BX0_BIOS_SCRATCH_9_BASE_IDX                                                              1
+#define regBIF_BX0_BIOS_SCRATCH_10                                                                      0x0042
+#define regBIF_BX0_BIOS_SCRATCH_10_BASE_IDX                                                             1
+#define regBIF_BX0_BIOS_SCRATCH_11                                                                      0x0043
+#define regBIF_BX0_BIOS_SCRATCH_11_BASE_IDX                                                             1
+#define regBIF_BX0_BIOS_SCRATCH_12                                                                      0x0044
+#define regBIF_BX0_BIOS_SCRATCH_12_BASE_IDX                                                             1
+#define regBIF_BX0_BIOS_SCRATCH_13                                                                      0x0045
+#define regBIF_BX0_BIOS_SCRATCH_13_BASE_IDX                                                             1
+#define regBIF_BX0_BIOS_SCRATCH_14                                                                      0x0046
+#define regBIF_BX0_BIOS_SCRATCH_14_BASE_IDX                                                             1
+#define regBIF_BX0_BIOS_SCRATCH_15                                                                      0x0047
+#define regBIF_BX0_BIOS_SCRATCH_15_BASE_IDX                                                             1
+#define regBIF_BX0_BIF_RLC_INTR_CNTL                                                                    0x004c
+#define regBIF_BX0_BIF_RLC_INTR_CNTL_BASE_IDX                                                           1
+#define regBIF_BX0_BIF_VCE_INTR_CNTL                                                                    0x004d
+#define regBIF_BX0_BIF_VCE_INTR_CNTL_BASE_IDX                                                           1
+#define regBIF_BX0_BIF_UVD_INTR_CNTL                                                                    0x004e
+#define regBIF_BX0_BIF_UVD_INTR_CNTL_BASE_IDX                                                           1
+#define regBIF_BX0_BIF_Engine_INTR_CNTL                                                                 0x004f
+#define regBIF_BX0_BIF_Engine_INTR_CNTL_BASE_IDX                                                        1
+#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR0                                                                0x006c
+#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR0_BASE_IDX                                                       1
+#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR0                                                          0x006d
+#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR0_BASE_IDX                                                 1
+#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR1                                                                0x006e
+#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR1_BASE_IDX                                                       1
+#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR1                                                          0x006f
+#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR1_BASE_IDX                                                 1
+#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR2                                                                0x0070
+#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR2_BASE_IDX                                                       1
+#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR2                                                          0x0071
+#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR2_BASE_IDX                                                 1
+#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR3                                                                0x0072
+#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR3_BASE_IDX                                                       1
+#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR3                                                          0x0073
+#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR3_BASE_IDX                                                 1
+#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR4                                                                0x0074
+#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR4_BASE_IDX                                                       1
+#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR4                                                          0x0075
+#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR4_BASE_IDX                                                 1
+#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR5                                                                0x0076
+#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR5_BASE_IDX                                                       1
+#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR5                                                          0x0077
+#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR5_BASE_IDX                                                 1
+#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR6                                                                0x0078
+#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR6_BASE_IDX                                                       1
+#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR6                                                          0x0079
+#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR6_BASE_IDX                                                 1
+#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR7                                                                0x007a
+#define regBIF_BX0_GFX_MMIOREG_CAM_ADDR7_BASE_IDX                                                       1
+#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR7                                                          0x007b
+#define regBIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR7_BASE_IDX                                                 1
+#define regBIF_BX0_GFX_MMIOREG_CAM_CNTL                                                                 0x007c
+#define regBIF_BX0_GFX_MMIOREG_CAM_CNTL_BASE_IDX                                                        1
+#define regBIF_BX0_GFX_MMIOREG_CAM_ZERO_CPL                                                             0x007d
+#define regBIF_BX0_GFX_MMIOREG_CAM_ZERO_CPL_BASE_IDX                                                    1
+#define regBIF_BX0_GFX_MMIOREG_CAM_ONE_CPL                                                              0x007e
+#define regBIF_BX0_GFX_MMIOREG_CAM_ONE_CPL_BASE_IDX                                                     1
+#define regBIF_BX0_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL                                                     0x007f
+#define regBIF_BX0_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL_BASE_IDX                                            1
+#define regBIF_BX0_DRIVER_SCRATCH_0                                                                     0x0080
+#define regBIF_BX0_DRIVER_SCRATCH_0_BASE_IDX                                                            1
+#define regBIF_BX0_DRIVER_SCRATCH_1                                                                     0x0081
+#define regBIF_BX0_DRIVER_SCRATCH_1_BASE_IDX                                                            1
+#define regBIF_BX0_DRIVER_SCRATCH_2                                                                     0x0082
+#define regBIF_BX0_DRIVER_SCRATCH_2_BASE_IDX                                                            1
+#define regBIF_BX0_DRIVER_SCRATCH_3                                                                     0x0083
+#define regBIF_BX0_DRIVER_SCRATCH_3_BASE_IDX                                                            1
+#define regBIF_BX0_DRIVER_SCRATCH_4                                                                     0x0084
+#define regBIF_BX0_DRIVER_SCRATCH_4_BASE_IDX                                                            1
+#define regBIF_BX0_DRIVER_SCRATCH_5                                                                     0x0085
+#define regBIF_BX0_DRIVER_SCRATCH_5_BASE_IDX                                                            1
+#define regBIF_BX0_DRIVER_SCRATCH_6                                                                     0x0086
+#define regBIF_BX0_DRIVER_SCRATCH_6_BASE_IDX                                                            1
+#define regBIF_BX0_DRIVER_SCRATCH_7                                                                     0x0087
+#define regBIF_BX0_DRIVER_SCRATCH_7_BASE_IDX                                                            1
+#define regBIF_BX0_DRIVER_SCRATCH_8                                                                     0x0088
+#define regBIF_BX0_DRIVER_SCRATCH_8_BASE_IDX                                                            1
+#define regBIF_BX0_DRIVER_SCRATCH_9                                                                     0x0089
+#define regBIF_BX0_DRIVER_SCRATCH_9_BASE_IDX                                                            1
+#define regBIF_BX0_DRIVER_SCRATCH_10                                                                    0x008a
+#define regBIF_BX0_DRIVER_SCRATCH_10_BASE_IDX                                                           1
+#define regBIF_BX0_DRIVER_SCRATCH_11                                                                    0x008b
+#define regBIF_BX0_DRIVER_SCRATCH_11_BASE_IDX                                                           1
+#define regBIF_BX0_DRIVER_SCRATCH_12                                                                    0x008c
+#define regBIF_BX0_DRIVER_SCRATCH_12_BASE_IDX                                                           1
+#define regBIF_BX0_DRIVER_SCRATCH_13                                                                    0x008d
+#define regBIF_BX0_DRIVER_SCRATCH_13_BASE_IDX                                                           1
+#define regBIF_BX0_DRIVER_SCRATCH_14                                                                    0x008e
+#define regBIF_BX0_DRIVER_SCRATCH_14_BASE_IDX                                                           1
+#define regBIF_BX0_DRIVER_SCRATCH_15                                                                    0x008f
+#define regBIF_BX0_DRIVER_SCRATCH_15_BASE_IDX                                                           1
+#define regBIF_BX0_FW_SCRATCH_0                                                                         0x0090
+#define regBIF_BX0_FW_SCRATCH_0_BASE_IDX                                                                1
+#define regBIF_BX0_FW_SCRATCH_1                                                                         0x0091
+#define regBIF_BX0_FW_SCRATCH_1_BASE_IDX                                                                1
+#define regBIF_BX0_FW_SCRATCH_2                                                                         0x0092
+#define regBIF_BX0_FW_SCRATCH_2_BASE_IDX                                                                1
+#define regBIF_BX0_FW_SCRATCH_3                                                                         0x0093
+#define regBIF_BX0_FW_SCRATCH_3_BASE_IDX                                                                1
+#define regBIF_BX0_FW_SCRATCH_4                                                                         0x0094
+#define regBIF_BX0_FW_SCRATCH_4_BASE_IDX                                                                1
+#define regBIF_BX0_FW_SCRATCH_5                                                                         0x0095
+#define regBIF_BX0_FW_SCRATCH_5_BASE_IDX                                                                1
+#define regBIF_BX0_FW_SCRATCH_6                                                                         0x0096
+#define regBIF_BX0_FW_SCRATCH_6_BASE_IDX                                                                1
+#define regBIF_BX0_FW_SCRATCH_7                                                                         0x0097
+#define regBIF_BX0_FW_SCRATCH_7_BASE_IDX                                                                1
+#define regBIF_BX0_FW_SCRATCH_8                                                                         0x0098
+#define regBIF_BX0_FW_SCRATCH_8_BASE_IDX                                                                1
+#define regBIF_BX0_FW_SCRATCH_9                                                                         0x0099
+#define regBIF_BX0_FW_SCRATCH_9_BASE_IDX                                                                1
+#define regBIF_BX0_FW_SCRATCH_10                                                                        0x009a
+#define regBIF_BX0_FW_SCRATCH_10_BASE_IDX                                                               1
+#define regBIF_BX0_FW_SCRATCH_11                                                                        0x009b
+#define regBIF_BX0_FW_SCRATCH_11_BASE_IDX                                                               1
+#define regBIF_BX0_FW_SCRATCH_12                                                                        0x009c
+#define regBIF_BX0_FW_SCRATCH_12_BASE_IDX                                                               1
+#define regBIF_BX0_FW_SCRATCH_13                                                                        0x009d
+#define regBIF_BX0_FW_SCRATCH_13_BASE_IDX                                                               1
+#define regBIF_BX0_FW_SCRATCH_14                                                                        0x009e
+#define regBIF_BX0_FW_SCRATCH_14_BASE_IDX                                                               1
+#define regBIF_BX0_FW_SCRATCH_15                                                                        0x009f
+#define regBIF_BX0_FW_SCRATCH_15_BASE_IDX                                                               1
+#define regBIF_BX0_SBIOS_SCRATCH_4                                                                      0x00a0
+#define regBIF_BX0_SBIOS_SCRATCH_4_BASE_IDX                                                             1
+#define regBIF_BX0_SBIOS_SCRATCH_5                                                                      0x00a1
+#define regBIF_BX0_SBIOS_SCRATCH_5_BASE_IDX                                                             1
+#define regBIF_BX0_SBIOS_SCRATCH_6                                                                      0x00a2
+#define regBIF_BX0_SBIOS_SCRATCH_6_BASE_IDX                                                             1
+#define regBIF_BX0_SBIOS_SCRATCH_7                                                                      0x00a3
+#define regBIF_BX0_SBIOS_SCRATCH_7_BASE_IDX                                                             1
+#define regBIF_BX0_SBIOS_SCRATCH_8                                                                      0x00a4
+#define regBIF_BX0_SBIOS_SCRATCH_8_BASE_IDX                                                             1
+#define regBIF_BX0_SBIOS_SCRATCH_9                                                                      0x00a5
+#define regBIF_BX0_SBIOS_SCRATCH_9_BASE_IDX                                                             1
+#define regBIF_BX0_SBIOS_SCRATCH_10                                                                     0x00a6
+#define regBIF_BX0_SBIOS_SCRATCH_10_BASE_IDX                                                            1
+#define regBIF_BX0_SBIOS_SCRATCH_11                                                                     0x00a7
+#define regBIF_BX0_SBIOS_SCRATCH_11_BASE_IDX                                                            1
+#define regBIF_BX0_SBIOS_SCRATCH_12                                                                     0x00a8
+#define regBIF_BX0_SBIOS_SCRATCH_12_BASE_IDX                                                            1
+#define regBIF_BX0_SBIOS_SCRATCH_13                                                                     0x00a9
+#define regBIF_BX0_SBIOS_SCRATCH_13_BASE_IDX                                                            1
+#define regBIF_BX0_SBIOS_SCRATCH_14                                                                     0x00aa
+#define regBIF_BX0_SBIOS_SCRATCH_14_BASE_IDX                                                            1
+#define regBIF_BX0_SBIOS_SCRATCH_15                                                                     0x00ab
+#define regBIF_BX0_SBIOS_SCRATCH_15_BASE_IDX                                                            1
+
+
+// addressBlock: nbif0_nbif0_rcc_dwn_dev0_BIFDEC1
+// base address: 0x0
+#define regRCC_DWN_DEV0_0_DN_PCIE_RESERVED                                                              0x0068
+#define regRCC_DWN_DEV0_0_DN_PCIE_RESERVED_BASE_IDX                                                     2
+#define regRCC_DWN_DEV0_0_DN_PCIE_SCRATCH                                                               0x0069
+#define regRCC_DWN_DEV0_0_DN_PCIE_SCRATCH_BASE_IDX                                                      2
+#define regRCC_DWN_DEV0_0_DN_PCIE_CNTL                                                                  0x006b
+#define regRCC_DWN_DEV0_0_DN_PCIE_CNTL_BASE_IDX                                                         2
+#define regRCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL                                                           0x006c
+#define regRCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL_BASE_IDX                                                  2
+#define regRCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2                                                              0x006d
+#define regRCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2_BASE_IDX                                                     2
+#define regRCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL                                                              0x006e
+#define regRCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL_BASE_IDX                                                     2
+#define regRCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL                                                              0x006f
+#define regRCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL_BASE_IDX                                                     2
+#define regRCC_DWN_DEV0_0_DN_PCIE_STRAP_F0                                                              0x0070
+#define regRCC_DWN_DEV0_0_DN_PCIE_STRAP_F0_BASE_IDX                                                     2
+#define regRCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC                                                            0x0071
+#define regRCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC_BASE_IDX                                                   2
+#define regRCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC2                                                           0x0072
+#define regRCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC2_BASE_IDX                                                  2
+
+
+// addressBlock: nbif0_nbif0_rcc_dwnp_dev0_BIFDEC1
+// base address: 0x0
+#define regRCC_DWNP_DEV0_0_PCIE_ERR_CNTL                                                                0x0074
+#define regRCC_DWNP_DEV0_0_PCIE_ERR_CNTL_BASE_IDX                                                       2
+#define regRCC_DWNP_DEV0_0_PCIE_RX_CNTL                                                                 0x0075
+#define regRCC_DWNP_DEV0_0_PCIE_RX_CNTL_BASE_IDX                                                        2
+#define regRCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL                                                           0x0076
+#define regRCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL_BASE_IDX                                                  2
+#define regRCC_DWNP_DEV0_0_PCIE_LC_CNTL2                                                                0x0077
+#define regRCC_DWNP_DEV0_0_PCIE_LC_CNTL2_BASE_IDX                                                       2
+#define regRCC_DWNP_DEV0_0_PCIEP_STRAP_MISC                                                             0x0078
+#define regRCC_DWNP_DEV0_0_PCIEP_STRAP_MISC_BASE_IDX                                                    2
+#define regRCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP                                                         0x0079
+#define regRCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP_BASE_IDX                                                2
+
+
+// addressBlock: nbif0_nbif0_rcc_ep_dev0_BIFDEC1
+// base address: 0x0
+#define regRCC_EP_DEV0_0_EP_PCIE_SCRATCH                                                                0x004b
+#define regRCC_EP_DEV0_0_EP_PCIE_SCRATCH_BASE_IDX                                                       2
+#define regRCC_EP_DEV0_0_EP_PCIE_CNTL                                                                   0x004d
+#define regRCC_EP_DEV0_0_EP_PCIE_CNTL_BASE_IDX                                                          2
+#define regRCC_EP_DEV0_0_EP_PCIE_INT_CNTL                                                               0x004e
+#define regRCC_EP_DEV0_0_EP_PCIE_INT_CNTL_BASE_IDX                                                      2
+#define regRCC_EP_DEV0_0_EP_PCIE_INT_STATUS                                                             0x004f
+#define regRCC_EP_DEV0_0_EP_PCIE_INT_STATUS_BASE_IDX                                                    2
+#define regRCC_EP_DEV0_0_EP_PCIE_RX_CNTL2                                                               0x0050
+#define regRCC_EP_DEV0_0_EP_PCIE_RX_CNTL2_BASE_IDX                                                      2
+#define regRCC_EP_DEV0_0_EP_PCIE_BUS_CNTL                                                               0x0051
+#define regRCC_EP_DEV0_0_EP_PCIE_BUS_CNTL_BASE_IDX                                                      2
+#define regRCC_EP_DEV0_0_EP_PCIE_CFG_CNTL                                                               0x0052
+#define regRCC_EP_DEV0_0_EP_PCIE_CFG_CNTL_BASE_IDX                                                      2
+#define regRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL                                                            0x0054
+#define regRCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL_BASE_IDX                                                   2
+#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0                                               0x0055
+#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX                                      2
+#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1                                               0x0055
+#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX                                      2
+#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2                                               0x0055
+#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX                                      2
+#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3                                               0x0055
+#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX                                      2
+#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4                                               0x0056
+#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX                                      2
+#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5                                               0x0056
+#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX                                      2
+#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6                                               0x0056
+#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX                                      2
+#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7                                               0x0056
+#define regRCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX                                      2
+#define regRCC_EP_DEV0_0_EP_PCIE_STRAP_MISC                                                             0x0057
+#define regRCC_EP_DEV0_0_EP_PCIE_STRAP_MISC_BASE_IDX                                                    2
+#define regRCC_EP_DEV0_0_EP_PCIE_STRAP_MISC2                                                            0x0058
+#define regRCC_EP_DEV0_0_EP_PCIE_STRAP_MISC2_BASE_IDX                                                   2
+#define regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP                                                             0x005a
+#define regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP_BASE_IDX                                                    2
+#define regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR                                               0x005b
+#define regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR_BASE_IDX                                      2
+#define regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL                                                            0x005b
+#define regRCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL_BASE_IDX                                                   2
+#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0                                               0x005b
+#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX                                      2
+#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1                                               0x005c
+#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX                                      2
+#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2                                               0x005c
+#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX                                      2
+#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3                                               0x005c
+#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX                                      2
+#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4                                               0x005c
+#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX                                      2
+#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5                                               0x005d
+#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX                                      2
+#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6                                               0x005d
+#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX                                      2
+#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7                                               0x005d
+#define regRCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX                                      2
+#define regRCC_EP_DEV0_0_EP_PCIE_PME_CONTROL                                                            0x005d
+#define regRCC_EP_DEV0_0_EP_PCIE_PME_CONTROL_BASE_IDX                                                   2
+#define regRCC_EP_DEV0_0_EP_PCIEP_RESERVED                                                              0x005e
+#define regRCC_EP_DEV0_0_EP_PCIEP_RESERVED_BASE_IDX                                                     2
+#define regRCC_EP_DEV0_0_EP_PCIE_TX_CNTL                                                                0x0060
+#define regRCC_EP_DEV0_0_EP_PCIE_TX_CNTL_BASE_IDX                                                       2
+#define regRCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID                                                        0x0061
+#define regRCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID_BASE_IDX                                               2
+#define regRCC_EP_DEV0_0_EP_PCIE_ERR_CNTL                                                               0x0062
+#define regRCC_EP_DEV0_0_EP_PCIE_ERR_CNTL_BASE_IDX                                                      2
+#define regRCC_EP_DEV0_0_EP_PCIE_RX_CNTL                                                                0x0063
+#define regRCC_EP_DEV0_0_EP_PCIE_RX_CNTL_BASE_IDX                                                       2
+#define regRCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL                                                          0x0064
+#define regRCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL_BASE_IDX                                                 2
+#define regRCC_EP_DEV0_0_EP_PCIE_DEVICE_CNTL3                                                           0x0065
+#define regRCC_EP_DEV0_0_EP_PCIE_DEVICE_CNTL3_BASE_IDX                                                  2
+
+
+// addressBlock: nbif0_nbif0_bif_bx_pf_SYSPFVFDEC
+// base address: 0x0
+#define regBIF_BX_PF0_MM_INDEX                                                                          0x0000
+#define regBIF_BX_PF0_MM_INDEX_BASE_IDX                                                                 0
+#define regBIF_BX_PF0_MM_DATA                                                                           0x0001
+#define regBIF_BX_PF0_MM_DATA_BASE_IDX                                                                  0
+#define regBIF_BX_PF0_MM_INDEX_HI                                                                       0x0006
+#define regBIF_BX_PF0_MM_INDEX_HI_BASE_IDX                                                              0
+#define regBIF_BX_PF0_RSMU_INDEX                                                                        0x0000
+#define regBIF_BX_PF0_RSMU_INDEX_BASE_IDX                                                               1
+#define regBIF_BX_PF0_RSMU_DATA                                                                         0x0001
+#define regBIF_BX_PF0_RSMU_DATA_BASE_IDX                                                                1
+#define regBIF_BX_PF0_RSMU_INDEX_HI                                                                     0x0002
+#define regBIF_BX_PF0_RSMU_INDEX_HI_BASE_IDX                                                            1
+
+
+// addressBlock: nbif0_nbif0_bif_bx_BIFDEC1
+// base address: 0x0
+#define regBIF_BX0_CC_BIF_BX_STRAP0                                                                     0x00e2
+#define regBIF_BX0_CC_BIF_BX_STRAP0_BASE_IDX                                                            2
+#define regBIF_BX0_CC_BIF_BX_PINSTRAP0                                                                  0x00e4
+#define regBIF_BX0_CC_BIF_BX_PINSTRAP0_BASE_IDX                                                         2
+#define regBIF_BX0_BIF_MM_INDACCESS_CNTL                                                                0x00e6
+#define regBIF_BX0_BIF_MM_INDACCESS_CNTL_BASE_IDX                                                       2
+#define regBIF_BX0_BUS_CNTL                                                                             0x00e7
+#define regBIF_BX0_BUS_CNTL_BASE_IDX                                                                    2
+#define regBIF_BX0_BIF_SCRATCH0                                                                         0x00e8
+#define regBIF_BX0_BIF_SCRATCH0_BASE_IDX                                                                2
+#define regBIF_BX0_BIF_SCRATCH1                                                                         0x00e9
+#define regBIF_BX0_BIF_SCRATCH1_BASE_IDX                                                                2
+#define regBIF_BX0_BX_RESET_EN                                                                          0x00ed
+#define regBIF_BX0_BX_RESET_EN_BASE_IDX                                                                 2
+#define regBIF_BX0_MM_CFGREGS_CNTL                                                                      0x00ee
+#define regBIF_BX0_MM_CFGREGS_CNTL_BASE_IDX                                                             2
+#define regBIF_BX0_BX_RESET_CNTL                                                                        0x00f0
+#define regBIF_BX0_BX_RESET_CNTL_BASE_IDX                                                               2
+#define regBIF_BX0_INTERRUPT_CNTL                                                                       0x00f1
+#define regBIF_BX0_INTERRUPT_CNTL_BASE_IDX                                                              2
+#define regBIF_BX0_INTERRUPT_CNTL2                                                                      0x00f2
+#define regBIF_BX0_INTERRUPT_CNTL2_BASE_IDX                                                             2
+#define regBIF_BX0_CLKREQB_PAD_CNTL                                                                     0x00f8
+#define regBIF_BX0_CLKREQB_PAD_CNTL_BASE_IDX                                                            2
+#define regBIF_BX0_BIF_FEATURES_CONTROL_MISC                                                            0x00fb
+#define regBIF_BX0_BIF_FEATURES_CONTROL_MISC_BASE_IDX                                                   2
+#define regBIF_BX0_HDP_ATOMIC_CONTROL_MISC                                                              0x00fc
+#define regBIF_BX0_HDP_ATOMIC_CONTROL_MISC_BASE_IDX                                                     2
+#define regBIF_BX0_BIF_DOORBELL_CNTL                                                                    0x00fd
+#define regBIF_BX0_BIF_DOORBELL_CNTL_BASE_IDX                                                           2
+#define regBIF_BX0_BIF_DOORBELL_INT_CNTL                                                                0x00fe
+#define regBIF_BX0_BIF_DOORBELL_INT_CNTL_BASE_IDX                                                       2
+#define regBIF_BX0_BIF_FB_EN                                                                            0x0100
+#define regBIF_BX0_BIF_FB_EN_BASE_IDX                                                                   2
+#define regBIF_BX0_BIF_INTR_CNTL                                                                        0x0101
+#define regBIF_BX0_BIF_INTR_CNTL_BASE_IDX                                                               2
+#define regBIF_BX0_BIF_MST_TRANS_PENDING_VF                                                             0x0109
+#define regBIF_BX0_BIF_MST_TRANS_PENDING_VF_BASE_IDX                                                    2
+#define regBIF_BX0_BIF_SLV_TRANS_PENDING_VF                                                             0x010a
+#define regBIF_BX0_BIF_SLV_TRANS_PENDING_VF_BASE_IDX                                                    2
+#define regBIF_BX0_BACO_CNTL                                                                            0x010b
+#define regBIF_BX0_BACO_CNTL_BASE_IDX                                                                   2
+#define regBIF_BX0_BIF_BACO_EXIT_TIME0                                                                  0x010c
+#define regBIF_BX0_BIF_BACO_EXIT_TIME0_BASE_IDX                                                         2
+#define regBIF_BX0_BIF_BACO_EXIT_TIMER1                                                                 0x010d
+#define regBIF_BX0_BIF_BACO_EXIT_TIMER1_BASE_IDX                                                        2
+#define regBIF_BX0_BIF_BACO_EXIT_TIMER2                                                                 0x010e
+#define regBIF_BX0_BIF_BACO_EXIT_TIMER2_BASE_IDX                                                        2
+#define regBIF_BX0_BIF_BACO_EXIT_TIMER3                                                                 0x010f
+#define regBIF_BX0_BIF_BACO_EXIT_TIMER3_BASE_IDX                                                        2
+#define regBIF_BX0_BIF_BACO_EXIT_TIMER4                                                                 0x0110
+#define regBIF_BX0_BIF_BACO_EXIT_TIMER4_BASE_IDX                                                        2
+#define regBIF_BX0_MEM_TYPE_CNTL                                                                        0x0111
+#define regBIF_BX0_MEM_TYPE_CNTL_BASE_IDX                                                               2
+#define regBIF_BX0_NBIF_GFX_ADDR_LUT_CNTL                                                               0x0113
+#define regBIF_BX0_NBIF_GFX_ADDR_LUT_CNTL_BASE_IDX                                                      2
+#define regBIF_BX0_NBIF_GFX_ADDR_LUT_0                                                                  0x0114
+#define regBIF_BX0_NBIF_GFX_ADDR_LUT_0_BASE_IDX                                                         2
+#define regBIF_BX0_NBIF_GFX_ADDR_LUT_1                                                                  0x0115
+#define regBIF_BX0_NBIF_GFX_ADDR_LUT_1_BASE_IDX                                                         2
+#define regBIF_BX0_NBIF_GFX_ADDR_LUT_2                                                                  0x0116
+#define regBIF_BX0_NBIF_GFX_ADDR_LUT_2_BASE_IDX                                                         2
+#define regBIF_BX0_NBIF_GFX_ADDR_LUT_3                                                                  0x0117
+#define regBIF_BX0_NBIF_GFX_ADDR_LUT_3_BASE_IDX                                                         2
+#define regBIF_BX0_NBIF_GFX_ADDR_LUT_4                                                                  0x0118
+#define regBIF_BX0_NBIF_GFX_ADDR_LUT_4_BASE_IDX                                                         2
+#define regBIF_BX0_NBIF_GFX_ADDR_LUT_5                                                                  0x0119
+#define regBIF_BX0_NBIF_GFX_ADDR_LUT_5_BASE_IDX                                                         2
+#define regBIF_BX0_NBIF_GFX_ADDR_LUT_6                                                                  0x011a
+#define regBIF_BX0_NBIF_GFX_ADDR_LUT_6_BASE_IDX                                                         2
+#define regBIF_BX0_NBIF_GFX_ADDR_LUT_7                                                                  0x011b
+#define regBIF_BX0_NBIF_GFX_ADDR_LUT_7_BASE_IDX                                                         2
+#define regBIF_BX0_NBIF_GFX_ADDR_LUT_8                                                                  0x011c
+#define regBIF_BX0_NBIF_GFX_ADDR_LUT_8_BASE_IDX                                                         2
+#define regBIF_BX0_NBIF_GFX_ADDR_LUT_9                                                                  0x011d
+#define regBIF_BX0_NBIF_GFX_ADDR_LUT_9_BASE_IDX                                                         2
+#define regBIF_BX0_NBIF_GFX_ADDR_LUT_10                                                                 0x011e
+#define regBIF_BX0_NBIF_GFX_ADDR_LUT_10_BASE_IDX                                                        2
+#define regBIF_BX0_NBIF_GFX_ADDR_LUT_11                                                                 0x011f
+#define regBIF_BX0_NBIF_GFX_ADDR_LUT_11_BASE_IDX                                                        2
+#define regBIF_BX0_NBIF_GFX_ADDR_LUT_12                                                                 0x0120
+#define regBIF_BX0_NBIF_GFX_ADDR_LUT_12_BASE_IDX                                                        2
+#define regBIF_BX0_NBIF_GFX_ADDR_LUT_13                                                                 0x0121
+#define regBIF_BX0_NBIF_GFX_ADDR_LUT_13_BASE_IDX                                                        2
+#define regBIF_BX0_NBIF_GFX_ADDR_LUT_14                                                                 0x0122
+#define regBIF_BX0_NBIF_GFX_ADDR_LUT_14_BASE_IDX                                                        2
+#define regBIF_BX0_NBIF_GFX_ADDR_LUT_15                                                                 0x0123
+#define regBIF_BX0_NBIF_GFX_ADDR_LUT_15_BASE_IDX                                                        2
+#define regBIF_BX0_VF_REGWR_EN                                                                          0x0124
+#define regBIF_BX0_VF_REGWR_EN_BASE_IDX                                                                 2
+#define regBIF_BX0_VF_DOORBELL_EN                                                                       0x0125
+#define regBIF_BX0_VF_DOORBELL_EN_BASE_IDX                                                              2
+#define regBIF_BX0_VF_FB_EN                                                                             0x0126
+#define regBIF_BX0_VF_FB_EN_BASE_IDX                                                                    2
+#define regBIF_BX0_VF_REGWR_STATUS                                                                      0x0127
+#define regBIF_BX0_VF_REGWR_STATUS_BASE_IDX                                                             2
+#define regBIF_BX0_VF_DOORBELL_STATUS                                                                   0x0128
+#define regBIF_BX0_VF_DOORBELL_STATUS_BASE_IDX                                                          2
+#define regBIF_BX0_VF_FB_STATUS                                                                         0x0129
+#define regBIF_BX0_VF_FB_STATUS_BASE_IDX                                                                2
+#define regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL                                                             0x012d
+#define regBIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL_BASE_IDX                                                    2
+#define regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL                                                             0x012e
+#define regBIF_BX0_REMAP_HDP_REG_FLUSH_CNTL_BASE_IDX                                                    2
+#define regBIF_BX0_BIF_RB_CNTL                                                                          0x012f
+#define regBIF_BX0_BIF_RB_CNTL_BASE_IDX                                                                 2
+#define regBIF_BX0_BIF_RB_BASE                                                                          0x0130
+#define regBIF_BX0_BIF_RB_BASE_BASE_IDX                                                                 2
+#define regBIF_BX0_BIF_RB_RPTR                                                                          0x0131
+#define regBIF_BX0_BIF_RB_RPTR_BASE_IDX                                                                 2
+#define regBIF_BX0_BIF_RB_WPTR                                                                          0x0132
+#define regBIF_BX0_BIF_RB_WPTR_BASE_IDX                                                                 2
+#define regBIF_BX0_BIF_RB_WPTR_ADDR_HI                                                                  0x0133
+#define regBIF_BX0_BIF_RB_WPTR_ADDR_HI_BASE_IDX                                                         2
+#define regBIF_BX0_BIF_RB_WPTR_ADDR_LO                                                                  0x0134
+#define regBIF_BX0_BIF_RB_WPTR_ADDR_LO_BASE_IDX                                                         2
+#define regBIF_BX0_MAILBOX_INDEX                                                                        0x0135
+#define regBIF_BX0_MAILBOX_INDEX_BASE_IDX                                                               2
+#define regBIF_BX0_BACO_AZ_ENHANCE_CTRL                                                                 0x0141
+#define regBIF_BX0_BACO_AZ_ENHANCE_CTRL_BASE_IDX                                                        2
+#define regBIF_BX0_BIF_MP1_INTR_CTRL                                                                    0x0142
+#define regBIF_BX0_BIF_MP1_INTR_CTRL_BASE_IDX                                                           2
+#define regBIF_BX0_BIF_PERSTB_PAD_CNTL                                                                  0x0145
+#define regBIF_BX0_BIF_PERSTB_PAD_CNTL_BASE_IDX                                                         2
+#define regBIF_BX0_BIF_PX_EN_PAD_CNTL                                                                   0x0146
+#define regBIF_BX0_BIF_PX_EN_PAD_CNTL_BASE_IDX                                                          2
+#define regBIF_BX0_BIF_REFPADKIN_PAD_CNTL                                                               0x0147
+#define regBIF_BX0_BIF_REFPADKIN_PAD_CNTL_BASE_IDX                                                      2
+#define regBIF_BX0_BIF_CLKREQB_PAD_CNTL                                                                 0x0148
+#define regBIF_BX0_BIF_CLKREQB_PAD_CNTL_BASE_IDX                                                        2
+#define regBIF_BX0_BIF_PWRBRK_PAD_CNTL                                                                  0x0149
+#define regBIF_BX0_BIF_PWRBRK_PAD_CNTL_BASE_IDX                                                         2
+#define regBIF_BX0_BIF_GPUIOV_SCH_CFG_SIZE                                                              0x0165
+#define regBIF_BX0_BIF_GPUIOV_SCH_CFG_SIZE_BASE_IDX                                                     2
+
+
+// addressBlock: nbif0_nbif0_rcc_dev0_BIFDEC1
+// base address: 0x0
+#define regRCC_DEV0_0_RCC_ERR_INT_CNTL                                                                  0x0086
+#define regRCC_DEV0_0_RCC_ERR_INT_CNTL_BASE_IDX                                                         2
+#define regRCC_DEV0_0_RCC_BACO_CNTL_MISC                                                                0x0087
+#define regRCC_DEV0_0_RCC_BACO_CNTL_MISC_BASE_IDX                                                       2
+#define regRCC_DEV0_0_RCC_RESET_EN                                                                      0x0088
+#define regRCC_DEV0_0_RCC_RESET_EN_BASE_IDX                                                             2
+#define regRCC_DEV0_0_RCC_VDM_SUPPORT                                                                   0x0089
+#define regRCC_DEV0_0_RCC_VDM_SUPPORT_BASE_IDX                                                          2
+#define regRCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0                                                            0x008a
+#define regRCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0_BASE_IDX                                                   2
+#define regRCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1                                                            0x008b
+#define regRCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1_BASE_IDX                                                   2
+#define regRCC_DEV0_0_RCC_GPUIOV_REGION                                                                 0x008c
+#define regRCC_DEV0_0_RCC_GPUIOV_REGION_BASE_IDX                                                        2
+#define regRCC_DEV0_0_RCC_GPU_HOSTVM_EN                                                                 0x008d
+#define regRCC_DEV0_0_RCC_GPU_HOSTVM_EN_BASE_IDX                                                        2
+#define regRCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL                                                         0x008e
+#define regRCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL_BASE_IDX                                                2
+#define regRCC_DEV0_0_RCC_CONSOLE_IOV_FIRST_VF_OFFSET                                                   0x008f
+#define regRCC_DEV0_0_RCC_CONSOLE_IOV_FIRST_VF_OFFSET_BASE_IDX                                          2
+#define regRCC_DEV0_0_RCC_CONSOLE_IOV_VF_STRIDE                                                         0x008f
+#define regRCC_DEV0_0_RCC_CONSOLE_IOV_VF_STRIDE_BASE_IDX                                                2
+#define regRCC_DEV0_0_RCC_PEER_REG_RANGE0                                                               0x00be
+#define regRCC_DEV0_0_RCC_PEER_REG_RANGE0_BASE_IDX                                                      2
+#define regRCC_DEV0_0_RCC_PEER_REG_RANGE1                                                               0x00bf
+#define regRCC_DEV0_0_RCC_PEER_REG_RANGE1_BASE_IDX                                                      2
+#define regRCC_DEV0_0_RCC_BUS_CNTL                                                                      0x00c1
+#define regRCC_DEV0_0_RCC_BUS_CNTL_BASE_IDX                                                             2
+#define regRCC_DEV0_0_RCC_CONFIG_CNTL                                                                   0x00c2
+#define regRCC_DEV0_0_RCC_CONFIG_CNTL_BASE_IDX                                                          2
+#define regRCC_DEV0_0_RCC_CONFIG_F0_BASE                                                                0x00c6
+#define regRCC_DEV0_0_RCC_CONFIG_F0_BASE_BASE_IDX                                                       2
+#define regRCC_DEV0_0_RCC_CONFIG_APER_SIZE                                                              0x00c7
+#define regRCC_DEV0_0_RCC_CONFIG_APER_SIZE_BASE_IDX                                                     2
+#define regRCC_DEV0_0_RCC_CONFIG_REG_APER_SIZE                                                          0x00c8
+#define regRCC_DEV0_0_RCC_CONFIG_REG_APER_SIZE_BASE_IDX                                                 2
+#define regRCC_DEV0_0_RCC_XDMA_LO                                                                       0x00c9
+#define regRCC_DEV0_0_RCC_XDMA_LO_BASE_IDX                                                              2
+#define regRCC_DEV0_0_RCC_XDMA_HI                                                                       0x00ca
+#define regRCC_DEV0_0_RCC_XDMA_HI_BASE_IDX                                                              2
+#define regRCC_DEV0_0_RCC_FEATURES_CONTROL_MISC                                                         0x00cb
+#define regRCC_DEV0_0_RCC_FEATURES_CONTROL_MISC_BASE_IDX                                                2
+#define regRCC_DEV0_0_RCC_BUSNUM_CNTL1                                                                  0x00cc
+#define regRCC_DEV0_0_RCC_BUSNUM_CNTL1_BASE_IDX                                                         2
+#define regRCC_DEV0_0_RCC_BUSNUM_LIST0                                                                  0x00cd
+#define regRCC_DEV0_0_RCC_BUSNUM_LIST0_BASE_IDX                                                         2
+#define regRCC_DEV0_0_RCC_BUSNUM_LIST1                                                                  0x00ce
+#define regRCC_DEV0_0_RCC_BUSNUM_LIST1_BASE_IDX                                                         2
+#define regRCC_DEV0_0_RCC_BUSNUM_CNTL2                                                                  0x00cf
+#define regRCC_DEV0_0_RCC_BUSNUM_CNTL2_BASE_IDX                                                         2
+#define regRCC_DEV0_0_RCC_CAPTURE_HOST_BUSNUM                                                           0x00d0
+#define regRCC_DEV0_0_RCC_CAPTURE_HOST_BUSNUM_BASE_IDX                                                  2
+#define regRCC_DEV0_0_RCC_HOST_BUSNUM                                                                   0x00d1
+#define regRCC_DEV0_0_RCC_HOST_BUSNUM_BASE_IDX                                                          2
+#define regRCC_DEV0_0_RCC_PEER0_FB_OFFSET_HI                                                            0x00d2
+#define regRCC_DEV0_0_RCC_PEER0_FB_OFFSET_HI_BASE_IDX                                                   2
+#define regRCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO                                                            0x00d3
+#define regRCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO_BASE_IDX                                                   2
+#define regRCC_DEV0_0_RCC_PEER1_FB_OFFSET_HI                                                            0x00d4
+#define regRCC_DEV0_0_RCC_PEER1_FB_OFFSET_HI_BASE_IDX                                                   2
+#define regRCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO                                                            0x00d5
+#define regRCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO_BASE_IDX                                                   2
+#define regRCC_DEV0_0_RCC_PEER2_FB_OFFSET_HI                                                            0x00d6
+#define regRCC_DEV0_0_RCC_PEER2_FB_OFFSET_HI_BASE_IDX                                                   2
+#define regRCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO                                                            0x00d7
+#define regRCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO_BASE_IDX                                                   2
+#define regRCC_DEV0_0_RCC_PEER3_FB_OFFSET_HI                                                            0x00d8
+#define regRCC_DEV0_0_RCC_PEER3_FB_OFFSET_HI_BASE_IDX                                                   2
+#define regRCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO                                                            0x00d9
+#define regRCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO_BASE_IDX                                                   2
+#define regRCC_DEV0_0_RCC_DEVFUNCNUM_LIST0                                                              0x00da
+#define regRCC_DEV0_0_RCC_DEVFUNCNUM_LIST0_BASE_IDX                                                     2
+#define regRCC_DEV0_0_RCC_DEVFUNCNUM_LIST1                                                              0x00db
+#define regRCC_DEV0_0_RCC_DEVFUNCNUM_LIST1_BASE_IDX                                                     2
+#define regRCC_DEV0_0_RCC_DEV0_LINK_CNTL                                                                0x00dd
+#define regRCC_DEV0_0_RCC_DEV0_LINK_CNTL_BASE_IDX                                                       2
+#define regRCC_DEV0_0_RCC_CMN_LINK_CNTL                                                                 0x00de
+#define regRCC_DEV0_0_RCC_CMN_LINK_CNTL_BASE_IDX                                                        2
+#define regRCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE                                                        0x00df
+#define regRCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE_BASE_IDX                                               2
+#define regRCC_DEV0_0_RCC_LTR_LSWITCH_CNTL                                                              0x00e0
+#define regRCC_DEV0_0_RCC_LTR_LSWITCH_CNTL_BASE_IDX                                                     2
+#define regRCC_DEV0_0_RCC_MH_ARB_CNTL                                                                   0x00e1
+#define regRCC_DEV0_0_RCC_MH_ARB_CNTL_BASE_IDX                                                          2
+
+
+// addressBlock: nbif0_nbif0_rcc_dev0_epf0_BIFDEC2
+// base address: 0x0
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_LO                                                          0x0400
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_LO_BASE_IDX                                                 3
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_HI                                                          0x0401
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_HI_BASE_IDX                                                 3
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT0_MSG_DATA                                                         0x0402
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT0_MSG_DATA_BASE_IDX                                                3
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT0_CONTROL                                                          0x0403
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT0_CONTROL_BASE_IDX                                                 3
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_LO                                                          0x0404
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_LO_BASE_IDX                                                 3
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_HI                                                          0x0405
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_HI_BASE_IDX                                                 3
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT1_MSG_DATA                                                         0x0406
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT1_MSG_DATA_BASE_IDX                                                3
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT1_CONTROL                                                          0x0407
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT1_CONTROL_BASE_IDX                                                 3
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_LO                                                          0x0408
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_LO_BASE_IDX                                                 3
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_HI                                                          0x0409
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_HI_BASE_IDX                                                 3
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT2_MSG_DATA                                                         0x040a
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT2_MSG_DATA_BASE_IDX                                                3
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT2_CONTROL                                                          0x040b
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT2_CONTROL_BASE_IDX                                                 3
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_LO                                                          0x040c
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_LO_BASE_IDX                                                 3
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_HI                                                          0x040d
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_HI_BASE_IDX                                                 3
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT3_MSG_DATA                                                         0x040e
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT3_MSG_DATA_BASE_IDX                                                3
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT3_CONTROL                                                          0x040f
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT3_CONTROL_BASE_IDX                                                 3
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT4_ADDR_LO                                                          0x0410
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT4_ADDR_LO_BASE_IDX                                                 3
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT4_ADDR_HI                                                          0x0411
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT4_ADDR_HI_BASE_IDX                                                 3
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT4_MSG_DATA                                                         0x0412
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT4_MSG_DATA_BASE_IDX                                                3
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT4_CONTROL                                                          0x0413
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT4_CONTROL_BASE_IDX                                                 3
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT5_ADDR_LO                                                          0x0414
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT5_ADDR_LO_BASE_IDX                                                 3
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT5_ADDR_HI                                                          0x0415
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT5_ADDR_HI_BASE_IDX                                                 3
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT5_MSG_DATA                                                         0x0416
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT5_MSG_DATA_BASE_IDX                                                3
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT5_CONTROL                                                          0x0417
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT5_CONTROL_BASE_IDX                                                 3
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT6_ADDR_LO                                                          0x0418
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT6_ADDR_LO_BASE_IDX                                                 3
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT6_ADDR_HI                                                          0x0419
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT6_ADDR_HI_BASE_IDX                                                 3
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT6_MSG_DATA                                                         0x041a
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT6_MSG_DATA_BASE_IDX                                                3
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT6_CONTROL                                                          0x041b
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT6_CONTROL_BASE_IDX                                                 3
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT7_ADDR_LO                                                          0x041c
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT7_ADDR_LO_BASE_IDX                                                 3
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT7_ADDR_HI                                                          0x041d
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT7_ADDR_HI_BASE_IDX                                                 3
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT7_MSG_DATA                                                         0x041e
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT7_MSG_DATA_BASE_IDX                                                3
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT7_CONTROL                                                          0x041f
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT7_CONTROL_BASE_IDX                                                 3
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT8_ADDR_LO                                                          0x0420
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT8_ADDR_LO_BASE_IDX                                                 3
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT8_ADDR_HI                                                          0x0421
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT8_ADDR_HI_BASE_IDX                                                 3
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT8_MSG_DATA                                                         0x0422
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT8_MSG_DATA_BASE_IDX                                                3
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT8_CONTROL                                                          0x0423
+#define regRCC_DEV0_EPF0_GFXMSIX_VECT8_CONTROL_BASE_IDX                                                 3
+#define regRCC_DEV0_EPF0_GFXMSIX_PBA                                                                    0x0800
+#define regRCC_DEV0_EPF0_GFXMSIX_PBA_BASE_IDX                                                           3
+
+
+// addressBlock: nbif0_nbif0_rcc_strap_BIFDEC1
+// base address: 0x0
+#define regRCC_STRAP0_RCC_BIF_STRAP0                                                                    0x0000
+#define regRCC_STRAP0_RCC_BIF_STRAP0_BASE_IDX                                                           2
+#define regRCC_STRAP0_RCC_BIF_STRAP1                                                                    0x0001
+#define regRCC_STRAP0_RCC_BIF_STRAP1_BASE_IDX                                                           2
+#define regRCC_STRAP0_RCC_BIF_STRAP10                                                                   0x0002
+#define regRCC_STRAP0_RCC_BIF_STRAP10_BASE_IDX                                                          2
+#define regRCC_STRAP0_RCC_BIF_STRAP11                                                                   0x0003
+#define regRCC_STRAP0_RCC_BIF_STRAP11_BASE_IDX                                                          2
+#define regRCC_STRAP0_RCC_BIF_STRAP12                                                                   0x0004
+#define regRCC_STRAP0_RCC_BIF_STRAP12_BASE_IDX                                                          2
+#define regRCC_STRAP0_RCC_BIF_STRAP13                                                                   0x0005
+#define regRCC_STRAP0_RCC_BIF_STRAP13_BASE_IDX                                                          2
+#define regRCC_STRAP0_RCC_BIF_STRAP2                                                                    0x0006
+#define regRCC_STRAP0_RCC_BIF_STRAP2_BASE_IDX                                                           2
+#define regRCC_STRAP0_RCC_BIF_STRAP3                                                                    0x0007
+#define regRCC_STRAP0_RCC_BIF_STRAP3_BASE_IDX                                                           2
+#define regRCC_STRAP0_RCC_BIF_STRAP4                                                                    0x0008
+#define regRCC_STRAP0_RCC_BIF_STRAP4_BASE_IDX                                                           2
+#define regRCC_STRAP0_RCC_BIF_STRAP5                                                                    0x0009
+#define regRCC_STRAP0_RCC_BIF_STRAP5_BASE_IDX                                                           2
+#define regRCC_STRAP0_RCC_BIF_STRAP6                                                                    0x000a
+#define regRCC_STRAP0_RCC_BIF_STRAP6_BASE_IDX                                                           2
+#define regRCC_STRAP0_RCC_BIF_STRAP7                                                                    0x000b
+#define regRCC_STRAP0_RCC_BIF_STRAP7_BASE_IDX                                                           2
+#define regRCC_STRAP0_RCC_BIF_STRAP8                                                                    0x000c
+#define regRCC_STRAP0_RCC_BIF_STRAP8_BASE_IDX                                                           2
+#define regRCC_STRAP0_RCC_BIF_STRAP9                                                                    0x000d
+#define regRCC_STRAP0_RCC_BIF_STRAP9_BASE_IDX                                                           2
+#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP0                                                              0x000e
+#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP0_BASE_IDX                                                     2
+#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP1                                                              0x000f
+#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP1_BASE_IDX                                                     2
+#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP10                                                             0x0010
+#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP10_BASE_IDX                                                    2
+#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP11                                                             0x0011
+#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP11_BASE_IDX                                                    2
+#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP12                                                             0x0012
+#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP12_BASE_IDX                                                    2
+#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP13                                                             0x0013
+#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP13_BASE_IDX                                                    2
+#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP14                                                             0x0014
+#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP14_BASE_IDX                                                    2
+#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP15                                                             0x0015
+#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP15_BASE_IDX                                                    2
+#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP16                                                             0x0016
+#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP16_BASE_IDX                                                    2
+#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP17                                                             0x0017
+#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP17_BASE_IDX                                                    2
+#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP18                                                             0x0018
+#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP18_BASE_IDX                                                    2
+#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP2                                                              0x0019
+#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP2_BASE_IDX                                                     2
+#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP3                                                              0x001a
+#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP3_BASE_IDX                                                     2
+#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP4                                                              0x001b
+#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP4_BASE_IDX                                                     2
+#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP5                                                              0x001c
+#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP5_BASE_IDX                                                     2
+#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP6                                                              0x001d
+#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP6_BASE_IDX                                                     2
+#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP7                                                              0x001e
+#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP7_BASE_IDX                                                     2
+#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP8                                                              0x001f
+#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP8_BASE_IDX                                                     2
+#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP9                                                              0x0020
+#define regRCC_STRAP0_RCC_DEV0_PORT_STRAP9_BASE_IDX                                                     2
+#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0                                                              0x0021
+#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP0_BASE_IDX                                                     2
+#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP1                                                              0x0022
+#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP1_BASE_IDX                                                     2
+#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP13                                                             0x0023
+#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP13_BASE_IDX                                                    2
+#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP14                                                             0x0024
+#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP14_BASE_IDX                                                    2
+#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP15                                                             0x0025
+#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP15_BASE_IDX                                                    2
+#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP16                                                             0x0026
+#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP16_BASE_IDX                                                    2
+#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP17                                                             0x0027
+#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP17_BASE_IDX                                                    2
+#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP18                                                             0x0028
+#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP18_BASE_IDX                                                    2
+#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP19                                                             0x0029
+#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP19_BASE_IDX                                                    2
+#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP2                                                              0x002a
+#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP2_BASE_IDX                                                     2
+#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP22                                                             0x002b
+#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP22_BASE_IDX                                                    2
+#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP23                                                             0x002c
+#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP23_BASE_IDX                                                    2
+#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP24                                                             0x002d
+#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP24_BASE_IDX                                                    2
+#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP3                                                              0x002e
+#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP3_BASE_IDX                                                     2
+#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP4                                                              0x002f
+#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP4_BASE_IDX                                                     2
+#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP5                                                              0x0030
+#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP5_BASE_IDX                                                     2
+#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP8                                                              0x0031
+#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP8_BASE_IDX                                                     2
+#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP9                                                              0x0032
+#define regRCC_STRAP0_RCC_DEV0_EPF0_STRAP9_BASE_IDX                                                     2
+#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP0                                                              0x0033
+#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP0_BASE_IDX                                                     2
+#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP1                                                              0x0034
+#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP1_BASE_IDX                                                     2
+#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP10                                                             0x0035
+#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP10_BASE_IDX                                                    2
+#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP11                                                             0x0036
+#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP11_BASE_IDX                                                    2
+#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP12                                                             0x0037
+#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP12_BASE_IDX                                                    2
+#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP13                                                             0x0038
+#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP13_BASE_IDX                                                    2
+#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP14                                                             0x0039
+#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP14_BASE_IDX                                                    2
+#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP15                                                             0x003a
+#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP15_BASE_IDX                                                    2
+#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP16                                                             0x003b
+#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP16_BASE_IDX                                                    2
+#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP17                                                             0x003c
+#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP17_BASE_IDX                                                    2
+#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP18                                                             0x003d
+#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP18_BASE_IDX                                                    2
+#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP19                                                             0x003e
+#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP19_BASE_IDX                                                    2
+#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP2                                                              0x003f
+#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP2_BASE_IDX                                                     2
+#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP20                                                             0x0040
+#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP20_BASE_IDX                                                    2
+#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP21                                                             0x0041
+#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP21_BASE_IDX                                                    2
+#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP23                                                             0x0042
+#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP23_BASE_IDX                                                    2
+#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP24                                                             0x0043
+#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP24_BASE_IDX                                                    2
+#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP3                                                              0x0044
+#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP3_BASE_IDX                                                     2
+#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP4                                                              0x0045
+#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP4_BASE_IDX                                                     2
+#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP5                                                              0x0046
+#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP5_BASE_IDX                                                     2
+#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP6                                                              0x0047
+#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP6_BASE_IDX                                                     2
+#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP7                                                              0x0048
+#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP7_BASE_IDX                                                     2
+#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP8                                                              0x0049
+#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP8_BASE_IDX                                                     2
+#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP9                                                              0x004a
+#define regRCC_STRAP0_RCC_DEV0_EPF1_STRAP9_BASE_IDX                                                     2
+
+
+// addressBlock: nbif0_nbif0_bif_bx_pf_BIFPFVFDEC1
+// base address: 0x0
+#define regBIF_BX_PF0_BIF_BME_STATUS                                                                    0x00eb
+#define regBIF_BX_PF0_BIF_BME_STATUS_BASE_IDX                                                           2
+#define regBIF_BX_PF0_BIF_ATOMIC_ERR_LOG                                                                0x00ec
+#define regBIF_BX_PF0_BIF_ATOMIC_ERR_LOG_BASE_IDX                                                       2
+#define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH                                              0x00f3
+#define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX                                     2
+#define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW                                               0x00f4
+#define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX                                      2
+#define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL                                                   0x00f5
+#define regBIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX                                          2
+#define regBIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL                                                      0x00f6
+#define regBIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX                                             2
+#define regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL                                                      0x00f7
+#define regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX                                             2
+#define regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL                                                 0x00f9
+#define regBIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX                                        2
+#define regBIF_BX_PF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL                                            0x00fa
+#define regBIF_BX_PF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX                                   2
+#define regBIF_BX_PF0_GPU_HDP_FLUSH_REQ                                                                 0x0106
+#define regBIF_BX_PF0_GPU_HDP_FLUSH_REQ_BASE_IDX                                                        2
+#define regBIF_BX_PF0_GPU_HDP_FLUSH_DONE                                                                0x0107
+#define regBIF_BX_PF0_GPU_HDP_FLUSH_DONE_BASE_IDX                                                       2
+#define regBIF_BX_PF0_BIF_TRANS_PENDING                                                                 0x0108
+#define regBIF_BX_PF0_BIF_TRANS_PENDING_BASE_IDX                                                        2
+#define regBIF_BX_PF0_NBIF_GFX_ADDR_LUT_BYPASS                                                          0x0112
+#define regBIF_BX_PF0_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX                                                 2
+#define regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0                                                            0x0136
+#define regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX                                                   2
+#define regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1                                                            0x0137
+#define regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX                                                   2
+#define regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2                                                            0x0138
+#define regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX                                                   2
+#define regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3                                                            0x0139
+#define regBIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX                                                   2
+#define regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW0                                                            0x013a
+#define regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX                                                   2
+#define regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW1                                                            0x013b
+#define regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX                                                   2
+#define regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2                                                            0x013c
+#define regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX                                                   2
+#define regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW3                                                            0x013d
+#define regBIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX                                                   2
+#define regBIF_BX_PF0_MAILBOX_CONTROL                                                                   0x013e
+#define regBIF_BX_PF0_MAILBOX_CONTROL_BASE_IDX                                                          2
+#define regBIF_BX_PF0_MAILBOX_INT_CNTL                                                                  0x013f
+#define regBIF_BX_PF0_MAILBOX_INT_CNTL_BASE_IDX                                                         2
+#define regBIF_BX_PF0_BIF_VMHV_MAILBOX                                                                  0x0140
+#define regBIF_BX_PF0_BIF_VMHV_MAILBOX_BASE_IDX                                                         2
+#define regBIF_BX_PF0_PARTITION_COMPUTE_CAP                                                             0x0161
+#define regBIF_BX_PF0_PARTITION_COMPUTE_CAP_BASE_IDX                                                    2
+#define regBIF_BX_PF0_PARTITION_MEM_CAP                                                                 0x0162
+#define regBIF_BX_PF0_PARTITION_MEM_CAP_BASE_IDX                                                        2
+#define regBIF_BX_PF0_PARTITION_COMPUTE_STATUS                                                          0x0163
+#define regBIF_BX_PF0_PARTITION_COMPUTE_STATUS_BASE_IDX                                                 2
+#define regBIF_BX_PF0_PARTITION_MEM_STATUS                                                              0x0164
+#define regBIF_BX_PF0_PARTITION_MEM_STATUS_BASE_IDX                                                     2
+
+
+// addressBlock: nbif0_nbif0_rcc_dev0_epf0_BIFPFVFDEC1
+// base address: 0x0
+#define regRCC_DEV0_EPF0_RCC_ERR_LOG                                                                    0x0085
+#define regRCC_DEV0_EPF0_RCC_ERR_LOG_BASE_IDX                                                           2
+#define regRCC_DEV0_EPF0_RCC_DOORBELL_APER_EN                                                           0x00c0
+#define regRCC_DEV0_EPF0_RCC_DOORBELL_APER_EN_BASE_IDX                                                  2
+#define regRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE                                                             0x00c3
+#define regRCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE_BASE_IDX                                                    2
+#define regRCC_DEV0_EPF0_RCC_CONFIG_RESERVED                                                            0x00c4
+#define regRCC_DEV0_EPF0_RCC_CONFIG_RESERVED_BASE_IDX                                                   2
+#define regRCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER                                                        0x00c5
+#define regRCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX                                               2
+
+
+// addressBlock: nbif0_nbif0_gdc_GDCDEC
+// base address: 0x0
+#define regGDC0_NGDC_SDP_PORT_CTRL                                                                      0x0180
+#define regGDC0_NGDC_SDP_PORT_CTRL_BASE_IDX                                                             2
+#define regGDC0_SHUB_REGS_IF_CTL                                                                        0x0181
+#define regGDC0_SHUB_REGS_IF_CTL_BASE_IDX                                                               2
+#define regGDC0_NGDC_MGCG_CTRL                                                                          0x0187
+#define regGDC0_NGDC_MGCG_CTRL_BASE_IDX                                                                 2
+#define regGDC0_S2A_MISC_CNTL                                                                           0x0188
+#define regGDC0_S2A_MISC_CNTL_BASE_IDX                                                                  2
+#define regGDC0_NGDC_MCA_SMN_CTRL0                                                                      0x018b
+#define regGDC0_NGDC_MCA_SMN_CTRL0_BASE_IDX                                                             2
+#define regGDC0_NGDC_EARLY_WAKEUP_CTRL                                                                  0x018c
+#define regGDC0_NGDC_EARLY_WAKEUP_CTRL_BASE_IDX                                                         2
+#define regGDC0_GDC_GDCCLK_S2A_ERR_RSP_CNTL                                                             0x0198
+#define regGDC0_GDC_GDCCLK_S2A_ERR_RSP_CNTL_BASE_IDX                                                    2
+#define regGDC0_GDC_DMA_SION_PCTRL                                                                      0x0199
+#define regGDC0_GDC_DMA_SION_PCTRL_BASE_IDX                                                             2
+#define regGDC0_NGDC_MP4SDP_CNTL                                                                        0x019b
+#define regGDC0_NGDC_MP4SDP_CNTL_BASE_IDX                                                               2
+#define regGDC0_DOORBELL_VCN_TARGET_VF0                                                                 0x01f3
+#define regGDC0_DOORBELL_VCN_TARGET_VF0_BASE_IDX                                                        2
+#define regGDC0_DOORBELL_VCN_TARGET_VF1                                                                 0x01f3
+#define regGDC0_DOORBELL_VCN_TARGET_VF1_BASE_IDX                                                        2
+#define regGDC0_DOORBELL_VCN_TARGET_VF2                                                                 0x01f4
+#define regGDC0_DOORBELL_VCN_TARGET_VF2_BASE_IDX                                                        2
+#define regGDC0_DOORBELL_VCN_TARGET_VF3                                                                 0x01f4
+#define regGDC0_DOORBELL_VCN_TARGET_VF3_BASE_IDX                                                        2
+#define regGDC0_DOORBELL_VCN_TARGET_VF4                                                                 0x01f5
+#define regGDC0_DOORBELL_VCN_TARGET_VF4_BASE_IDX                                                        2
+#define regGDC0_DOORBELL_VCN_TARGET_VF5                                                                 0x01f5
+#define regGDC0_DOORBELL_VCN_TARGET_VF5_BASE_IDX                                                        2
+#define regGDC0_DOORBELL_VCN_TARGET_VF6                                                                 0x01f6
+#define regGDC0_DOORBELL_VCN_TARGET_VF6_BASE_IDX                                                        2
+#define regGDC0_DOORBELL_VCN_TARGET_VF7                                                                 0x01f6
+#define regGDC0_DOORBELL_VCN_TARGET_VF7_BASE_IDX                                                        2
+#define regGDC0_DOORBELL_ACCESS_EN_PF                                                                   0x01f7
+#define regGDC0_DOORBELL_ACCESS_EN_PF_BASE_IDX                                                          2
+#define regGDC0_DOORBELL_ACCESS_EN_VF0                                                                  0x01f7
+#define regGDC0_DOORBELL_ACCESS_EN_VF0_BASE_IDX                                                         2
+#define regGDC0_DOORBELL_ACCESS_EN_VF1                                                                  0x01f8
+#define regGDC0_DOORBELL_ACCESS_EN_VF1_BASE_IDX                                                         2
+#define regGDC0_DOORBELL_ACCESS_EN_VF2                                                                  0x01f8
+#define regGDC0_DOORBELL_ACCESS_EN_VF2_BASE_IDX                                                         2
+#define regGDC0_DOORBELL_ACCESS_EN_VF3                                                                  0x01f9
+#define regGDC0_DOORBELL_ACCESS_EN_VF3_BASE_IDX                                                         2
+#define regGDC0_DOORBELL_ACCESS_EN_VF4                                                                  0x01f9
+#define regGDC0_DOORBELL_ACCESS_EN_VF4_BASE_IDX                                                         2
+#define regGDC0_DOORBELL_ACCESS_EN_VF5                                                                  0x01fa
+#define regGDC0_DOORBELL_ACCESS_EN_VF5_BASE_IDX                                                         2
+#define regGDC0_DOORBELL_ACCESS_EN_VF6                                                                  0x01fa
+#define regGDC0_DOORBELL_ACCESS_EN_VF6_BASE_IDX                                                         2
+#define regGDC0_DOORBELL_ACCESS_EN_VF7                                                                  0x01fb
+#define regGDC0_DOORBELL_ACCESS_EN_VF7_BASE_IDX                                                         2
+#define regGDC0_NGDC_CNDI_BUS_PORT_CTRL                                                                 0x01fc
+#define regGDC0_NGDC_CNDI_BUS_PORT_CTRL_BASE_IDX                                                        2
+#define regGDC0_NGDC_CNDI_BUS_POOL_CRED_CTRL                                                            0x01fd
+#define regGDC0_NGDC_CNDI_BUS_POOL_CRED_CTRL_BASE_IDX                                                   2
+
+
+// addressBlock: nbif0_nbif0_gdc_s2a_GDCS2A_DEC
+// base address: 0x0
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL                                                           0x01cb
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL_BASE_IDX                                                  2
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL1                                                          0x01cc
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL1_BASE_IDX                                                 2
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL                                                           0x01cd
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL_BASE_IDX                                                  2
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL1                                                          0x01ce
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL1_BASE_IDX                                                 2
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL                                                           0x01cf
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL_BASE_IDX                                                  2
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL1                                                          0x01d0
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL1_BASE_IDX                                                 2
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL                                                           0x01d1
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL_BASE_IDX                                                  2
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL1                                                          0x01d2
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL1_BASE_IDX                                                 2
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL                                                           0x01d3
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL_BASE_IDX                                                  2
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL1                                                          0x01d4
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL1_BASE_IDX                                                 2
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL                                                           0x01d5
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL_BASE_IDX                                                  2
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL1                                                          0x01d6
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL1_BASE_IDX                                                 2
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL                                                           0x01d7
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL_BASE_IDX                                                  2
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL1                                                          0x01d8
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL1_BASE_IDX                                                 2
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL                                                           0x01d9
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL_BASE_IDX                                                  2
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL1                                                          0x01da
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL1_BASE_IDX                                                 2
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL                                                           0x01db
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL_BASE_IDX                                                  2
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL1                                                          0x01dc
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL1_BASE_IDX                                                 2
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL                                                           0x01dd
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL_BASE_IDX                                                  2
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL1                                                          0x01de
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL1_BASE_IDX                                                 2
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL                                                          0x01df
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL_BASE_IDX                                                 2
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL1                                                         0x01e0
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL1_BASE_IDX                                                2
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL                                                          0x01e1
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL_BASE_IDX                                                 2
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL1                                                         0x01e2
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL1_BASE_IDX                                                2
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL                                                          0x01e3
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL_BASE_IDX                                                 2
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL1                                                         0x01e4
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL1_BASE_IDX                                                2
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL                                                          0x01e5
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL_BASE_IDX                                                 2
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL1                                                         0x01e6
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL1_BASE_IDX                                                2
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL                                                          0x01e7
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL_BASE_IDX                                                 2
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL1                                                         0x01e8
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL1_BASE_IDX                                                2
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL                                                          0x01e9
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL_BASE_IDX                                                 2
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL1                                                         0x01ea
+#define regGDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL1_BASE_IDX                                                2
+#define regGDC_S2A0_S2A_DOORBELL_COMMON_CTRL_REG                                                        0x01eb
+#define regGDC_S2A0_S2A_DOORBELL_COMMON_CTRL_REG_BASE_IDX                                               2
+#define regGDC_S2A0_NBIF_GFX_DOORBELL_STATUS                                                            0x01ec
+#define regGDC_S2A0_NBIF_GFX_DOORBELL_STATUS_BASE_IDX                                                   2
+
+
+// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_bifcfgdecp
+// base address: 0x0
+#define cfgBIF_CFG_DEV0_EPF0_VENDOR_ID                                                                  0x0000
+#define cfgBIF_CFG_DEV0_EPF0_DEVICE_ID                                                                  0x0002
+#define cfgBIF_CFG_DEV0_EPF0_COMMAND                                                                    0x0004
+#define cfgBIF_CFG_DEV0_EPF0_STATUS                                                                     0x0006
+#define cfgBIF_CFG_DEV0_EPF0_REVISION_ID                                                                0x0008
+#define cfgBIF_CFG_DEV0_EPF0_PROG_INTERFACE                                                             0x0009
+#define cfgBIF_CFG_DEV0_EPF0_SUB_CLASS                                                                  0x000a
+#define cfgBIF_CFG_DEV0_EPF0_BASE_CLASS                                                                 0x000b
+#define cfgBIF_CFG_DEV0_EPF0_CACHE_LINE                                                                 0x000c
+#define cfgBIF_CFG_DEV0_EPF0_LATENCY                                                                    0x000d
+#define cfgBIF_CFG_DEV0_EPF0_HEADER                                                                     0x000e
+#define cfgBIF_CFG_DEV0_EPF0_BIST                                                                       0x000f
+#define cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_1                                                                0x0010
+#define cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_2                                                                0x0014
+#define cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_3                                                                0x0018
+#define cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_4                                                                0x001c
+#define cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_5                                                                0x0020
+#define cfgBIF_CFG_DEV0_EPF0_BASE_ADDR_6                                                                0x0024
+#define cfgBIF_CFG_DEV0_EPF0_CARDBUS_CIS_PTR                                                            0x0028
+#define cfgBIF_CFG_DEV0_EPF0_ADAPTER_ID                                                                 0x002c
+#define cfgBIF_CFG_DEV0_EPF0_ROM_BASE_ADDR                                                              0x0030
+#define cfgBIF_CFG_DEV0_EPF0_CAP_PTR                                                                    0x0034
+#define cfgBIF_CFG_DEV0_EPF0_INTERRUPT_LINE                                                             0x003c
+#define cfgBIF_CFG_DEV0_EPF0_INTERRUPT_PIN                                                              0x003d
+#define cfgBIF_CFG_DEV0_EPF0_MIN_GRANT                                                                  0x003e
+#define cfgBIF_CFG_DEV0_EPF0_MAX_LATENCY                                                                0x003f
+#define cfgVENDOR_CAP_LIST                                                                              0x0048
+#define cfgADAPTER_ID_W                                                                                 0x004c
+#define cfgBIF_CFG_DEV0_EPF0_PMI_CAP_LIST                                                               0x0050
+#define cfgBIF_CFG_DEV0_EPF0_PMI_CAP                                                                    0x0052
+#define cfgBIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL                                                            0x0054
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_CAP_LIST                                                              0x0064
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_CAP                                                                   0x0066
+#define cfgBIF_CFG_DEV0_EPF0_DEVICE_CAP                                                                 0x0068
+#define cfgBIF_CFG_DEV0_EPF0_DEVICE_CNTL                                                                0x006c
+#define cfgBIF_CFG_DEV0_EPF0_DEVICE_STATUS                                                              0x006e
+#define cfgBIF_CFG_DEV0_EPF0_DEVICE_CAP2                                                                0x0088
+#define cfgBIF_CFG_DEV0_EPF0_DEVICE_CNTL2                                                               0x008c
+#define cfgBIF_CFG_DEV0_EPF0_DEVICE_STATUS2                                                             0x008e
+#define cfgBIF_CFG_DEV0_EPF0_MSI_CAP_LIST                                                               0x00a0
+#define cfgBIF_CFG_DEV0_EPF0_MSI_MSG_CNTL                                                               0x00a2
+#define cfgBIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_LO                                                            0x00a4
+#define cfgBIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_HI                                                            0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_MSI_MSG_DATA                                                               0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA                                                           0x00aa
+#define cfgBIF_CFG_DEV0_EPF0_MSI_MASK                                                                   0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_MSI_MSG_DATA_64                                                            0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA_64                                                        0x00ae
+#define cfgBIF_CFG_DEV0_EPF0_MSI_MASK_64                                                                0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_MSI_PENDING                                                                0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_MSI_PENDING_64                                                             0x00b4
+#define cfgBIF_CFG_DEV0_EPF0_MSIX_CAP_LIST                                                              0x00c0
+#define cfgBIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL                                                              0x00c2
+#define cfgBIF_CFG_DEV0_EPF0_MSIX_TABLE                                                                 0x00c4
+#define cfgBIF_CFG_DEV0_EPF0_MSIX_PBA                                                                   0x00c8
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_NULL2_ENH_CAP_LIST                                                    0x0600
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                              0x0604
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS                                                     0x0608
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK                                                       0x060c
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY                                                   0x0610
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS                                                       0x0614
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK                                                         0x0618
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL                                                      0x061c
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG0                                                              0x0620
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG1                                                              0x0624
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG2                                                              0x0628
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG3                                                              0x062c
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG4                                                              0x063c
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG0                                                       0x063c
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG5                                                              0x0640
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG1                                                       0x0640
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG6                                                              0x0644
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG2                                                       0x0644
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG7                                                              0x0648
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG3                                                       0x0648
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG8                                                              0x064c
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG9                                                              0x0650
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG10                                                             0x0654
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG11                                                             0x0658
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG12                                                             0x065c
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_HDR_LOG13                                                             0x0660
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST                                           0x0664
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW1                                                    0x0668
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW2                                                    0x066c
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST                                                      0x06dc
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_ACS_CAP                                                               0x06e0
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL                                                              0x06e2
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_RTR_ENH_CAP_LIST                                                      0x071c
+#define cfgBIF_CFG_DEV0_EPF0_RTR_DATA1                                                                  0x0720
+#define cfgBIF_CFG_DEV0_EPF0_RTR_DATA2                                                                  0x0724
+#define cfgPCIE_PWR_BUDGET_ENH_CAP_LIST                                                                 0x0728
+#define cfgPCIE_PWR_BUDGET_DATA_SELECT                                                                  0x072c
+#define cfgPCIE_PWR_BUDGET_DATA                                                                         0x0730
+#define cfgPCIE_PWR_BUDGET_CAP                                                                          0x0734
+#define cfgPCIE_DPA_ENH_CAP_LIST                                                                        0x0738
+#define cfgPCIE_DPA_CAP                                                                                 0x073c
+#define cfgPCIE_DPA_LATENCY_INDICATOR                                                                   0x0740
+#define cfgPCIE_DPA_STATUS                                                                              0x0744
+#define cfgPCIE_DPA_CNTL                                                                                0x0746
+#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_0                                                                0x0748
+#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_1                                                                0x0749
+#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_2                                                                0x074a
+#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_3                                                                0x074b
+#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_4                                                                0x074c
+#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_5                                                                0x074d
+#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_6                                                                0x074e
+#define cfgPCIE_DPA_SUBSTATE_PWR_ALLOC_7                                                                0x074f
+#define cfgPCIE_LTR_ENH_CAP_LIST                                                                        0x0768
+#define cfgPCIE_LTR_CAP                                                                                 0x076c
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST                                                      0x0770
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_ARI_CAP                                                               0x0774
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL                                                              0x0776
+#define cfgPCIE_BAR_ENH_CAP_LIST                                                                        0x0778
+#define cfgPCIE_BAR1_CAP                                                                                0x077c
+#define cfgPCIE_BAR1_CNTL                                                                               0x0780
+#define cfgPCIE_BAR2_CAP                                                                                0x0784
+#define cfgPCIE_BAR2_CNTL                                                                               0x0788
+#define cfgPCIE_BAR3_CAP                                                                                0x078c
+#define cfgPCIE_BAR3_CNTL                                                                               0x0790
+#define cfgPCIE_BAR4_CAP                                                                                0x0794
+#define cfgPCIE_BAR4_CNTL                                                                               0x0798
+#define cfgPCIE_BAR5_CAP                                                                                0x079c
+#define cfgPCIE_BAR5_CNTL                                                                               0x07a0
+#define cfgPCIE_BAR6_CAP                                                                                0x07a4
+#define cfgPCIE_BAR6_CNTL                                                                               0x07a8
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST                                                      0x07ac
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_ATS_CAP                                                               0x07b0
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_ATS_CNTL                                                              0x07b2
+#define cfgPCIE_PAGE_REQ_ENH_CAP_LIST                                                                   0x07b4
+#define cfgPCIE_PAGE_REQ_CNTL                                                                           0x07b8
+#define cfgPCIE_PAGE_REQ_STATUS                                                                         0x07ba
+#define cfgPCIE_OUTSTAND_PAGE_REQ_CAPACITY                                                              0x07bc
+#define cfgPCIE_OUTSTAND_PAGE_REQ_ALLOC                                                                 0x07c0
+#define cfgPCIE_PASID_ENH_CAP_LIST                                                                      0x07c4
+#define cfgPCIE_PASID_CAP                                                                               0x07c8
+#define cfgPCIE_PASID_CNTL                                                                              0x07ca
+#define cfgPCIE_SRIOV_ENH_CAP_LIST                                                                      0x07cc
+#define cfgPCIE_SRIOV_CAP                                                                               0x07d0
+#define cfgPCIE_SRIOV_CONTROL                                                                           0x07d4
+#define cfgPCIE_SRIOV_STATUS                                                                            0x07d6
+#define cfgPCIE_SRIOV_INITIAL_VFS                                                                       0x07d8
+#define cfgPCIE_SRIOV_TOTAL_VFS                                                                         0x07da
+#define cfgPCIE_SRIOV_NUM_VFS                                                                           0x07dc
+#define cfgPCIE_SRIOV_FUNC_DEP_LINK                                                                     0x07de
+#define cfgPCIE_SRIOV_FIRST_VF_OFFSET                                                                   0x07e0
+#define cfgPCIE_SRIOV_VF_STRIDE                                                                         0x07e2
+#define cfgPCIE_SRIOV_VF_DEVICE_ID                                                                      0x07e6
+#define cfgPCIE_SRIOV_SUPPORTED_PAGE_SIZE                                                               0x07e8
+#define cfgPCIE_SRIOV_SYSTEM_PAGE_SIZE                                                                  0x07ec
+#define cfgPCIE_SRIOV_VF_BASE_ADDR_0                                                                    0x07f0
+#define cfgPCIE_SRIOV_VF_BASE_ADDR_1                                                                    0x07f4
+#define cfgPCIE_SRIOV_VF_BASE_ADDR_2                                                                    0x07f8
+#define cfgPCIE_SRIOV_VF_BASE_ADDR_3                                                                    0x07fc
+#define cfgPCIE_SRIOV_VF_BASE_ADDR_4                                                                    0x0800
+#define cfgPCIE_SRIOV_VF_BASE_ADDR_5                                                                    0x0804
+#define cfgPCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET                                                   0x0808
+#define cfgPCIE_VF_RESIZE_BAR_ENH_CAP_LIST                                                              0x08e0
+#define cfgPCIE_VF_RESIZE_BAR1_CAP                                                                      0x08e4
+#define cfgPCIE_VF_RESIZE_BAR1_CNTL                                                                     0x08e8
+#define cfgPCIE_VF_RESIZE_BAR2_CAP                                                                      0x08ec
+#define cfgPCIE_VF_RESIZE_BAR2_CNTL                                                                     0x08f0
+#define cfgPCIE_VF_RESIZE_BAR3_CAP                                                                      0x08f4
+#define cfgPCIE_VF_RESIZE_BAR3_CNTL                                                                     0x08f8
+#define cfgPCIE_VF_RESIZE_BAR4_CAP                                                                      0x08fc
+#define cfgPCIE_VF_RESIZE_BAR4_CNTL                                                                     0x0900
+#define cfgPCIE_VF_RESIZE_BAR5_CAP                                                                      0x0904
+#define cfgPCIE_VF_RESIZE_BAR5_CNTL                                                                     0x0908
+#define cfgPCIE_VF_RESIZE_BAR6_CAP                                                                      0x090c
+#define cfgPCIE_VF_RESIZE_BAR6_CNTL                                                                     0x0910
+#define cfgPCIE_DOE_ENH_CAP_LIST                                                                        0x0914
+#define cfgPCIE_DOE_CAP                                                                                 0x0918
+#define cfgPCIE_DOE_CNTL                                                                                0x091c
+#define cfgPCIE_DOE_STS                                                                                 0x0920
+#define cfgPCIE_DOE_WMBOX                                                                               0x0924
+#define cfgPCIE_DOE_RMBOX                                                                               0x0928
+#define cfgPCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV                                                     0x09ac
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV                                                              0x09b0
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW                                                 0x09b4
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE                                                  0x09b8
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS                                                  0x09bc
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL                                                0x09c0
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0                                                0x09c4
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1                                                0x09c8
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2                                                0x09cc
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB                                                     0x09d4
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION                                                       0x09dc
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE                                         0x09e0
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS0                                                     0x0a04
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1                                                     0x0a08
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2                                                     0x0a0c
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3                                                     0x0a10
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4                                                     0x0a14
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW0                                                     0x0a1c
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW1                                                     0x0a20
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW2                                                     0x0a24
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW3                                                     0x0a28
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW4                                                     0x0a2c
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW5                                                     0x0a30
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW6                                                     0x0a34
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW7                                                     0x0a38
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW8                                                     0x0a3c
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW0                                                     0x0a4c
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW1                                                     0x0a50
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW2                                                     0x0a54
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW3                                                     0x0a58
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW4                                                     0x0a5c
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW5                                                     0x0a60
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW6                                                     0x0a64
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW7                                                     0x0a68
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW8                                                     0x0a6c
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW0                                                     0x0a7c
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW1                                                     0x0a80
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW2                                                     0x0a84
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW3                                                     0x0a88
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW4                                                     0x0a8c
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW5                                                     0x0a90
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW6                                                     0x0a94
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW7                                                     0x0a98
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW8                                                     0x0a9c
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW0                                                     0x0aac
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW1                                                     0x0ab0
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW2                                                     0x0ab4
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW3                                                     0x0ab8
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW4                                                     0x0abc
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW5                                                     0x0ac0
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW6                                                     0x0ac4
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW7                                                     0x0ac8
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW8                                                     0x0acc
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW0                                                     0x0adc
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW1                                                     0x0ae0
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW2                                                     0x0ae4
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW3                                                     0x0ae8
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW4                                                     0x0aec
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW5                                                     0x0af0
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW6                                                     0x0af4
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW7                                                     0x0af8
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW8                                                     0x0afc
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW0                                                     0x0b0c
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW1                                                     0x0b10
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW2                                                     0x0b14
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW3                                                     0x0b18
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW4                                                     0x0b1c
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW5                                                     0x0b20
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW6                                                     0x0b24
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW7                                                     0x0b28
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW8                                                     0x0b2c
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW0                                                     0x0b3c
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW1                                                     0x0b40
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW2                                                     0x0b44
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW3                                                     0x0b48
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW4                                                     0x0b4c
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW5                                                     0x0b50
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW6                                                     0x0b54
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW7                                                     0x0b58
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW8                                                     0x0b5c
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW0                                                     0x0b6c
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW1                                                     0x0b70
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW2                                                     0x0b74
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW3                                                     0x0b78
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW4                                                     0x0b7c
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW5                                                     0x0b80
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW6                                                     0x0b84
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW7                                                     0x0b88
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW8                                                     0x0b8c
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW0                                                     0x0b9c
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW1                                                     0x0ba0
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW2                                                     0x0ba4
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW3                                                     0x0ba8
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW4                                                     0x0bac
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW5                                                     0x0bb0
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW6                                                     0x0bb4
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW7                                                     0x0bb8
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW8                                                     0x0bbc
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW0                                                     0x0bcc
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW1                                                     0x0bd0
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW2                                                     0x0bd4
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW3                                                     0x0bd8
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW4                                                     0x0bdc
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW5                                                     0x0be0
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW6                                                     0x0be4
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW7                                                     0x0be8
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW8                                                     0x0bec
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW0                                                    0x0bfc
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW1                                                    0x0c00
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW2                                                    0x0c04
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW3                                                    0x0c08
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW4                                                    0x0c0c
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW5                                                    0x0c10
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW6                                                    0x0c14
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW7                                                    0x0c18
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW8                                                    0x0c1c
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW0                                                    0x0c2c
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW1                                                    0x0c30
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW2                                                    0x0c34
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW3                                                    0x0c38
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW4                                                    0x0c3c
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW5                                                    0x0c40
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW6                                                    0x0c44
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW7                                                    0x0c48
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW8                                                    0x0c4c
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW0                                                    0x0c5c
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW1                                                    0x0c60
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW2                                                    0x0c64
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW3                                                    0x0c68
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW4                                                    0x0c6c
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW5                                                    0x0c70
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW6                                                    0x0c74
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW7                                                    0x0c78
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW8                                                    0x0c7c
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW0                                                    0x0c8c
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW1                                                    0x0c90
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW2                                                    0x0c94
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW3                                                    0x0c98
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW4                                                    0x0c9c
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW5                                                    0x0ca0
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW6                                                    0x0ca4
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW7                                                    0x0ca8
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW8                                                    0x0cac
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW0                                                    0x0cbc
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW1                                                    0x0cc0
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW2                                                    0x0cc4
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW3                                                    0x0cc8
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW4                                                    0x0ccc
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW5                                                    0x0cd0
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW6                                                    0x0cd4
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW7                                                    0x0cd8
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW8                                                    0x0cdc
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW0                                                    0x0cec
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW1                                                    0x0cf0
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW2                                                    0x0cf4
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW3                                                    0x0cf8
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW4                                                    0x0cfc
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW5                                                    0x0d00
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW6                                                    0x0d04
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW7                                                    0x0d08
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW8                                                    0x0d0c
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW0                                                    0x0d1c
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW1                                                    0x0d20
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW2                                                    0x0d24
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW3                                                    0x0d28
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW4                                                    0x0d2c
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW5                                                    0x0d30
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW6                                                    0x0d34
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW7                                                    0x0d38
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW8                                                    0x0d3c
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW0                                                    0x0d4c
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW1                                                    0x0d50
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW2                                                    0x0d54
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW3                                                    0x0d58
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW4                                                    0x0d5c
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW5                                                    0x0d60
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW6                                                    0x0d64
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW7                                                    0x0d68
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW8                                                    0x0d6c
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW0                                                    0x0d7c
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW1                                                    0x0d80
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW2                                                    0x0d84
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW3                                                    0x0d88
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW4                                                    0x0d8c
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW5                                                    0x0d90
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW6                                                    0x0d94
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW7                                                    0x0d98
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW8                                                    0x0d9c
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW0                                                    0x0dac
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW1                                                    0x0db0
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW2                                                    0x0db4
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW3                                                    0x0db8
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW4                                                    0x0dbc
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW5                                                    0x0dc0
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW6                                                    0x0dc4
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW7                                                    0x0dc8
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW8                                                    0x0dcc
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE                                          0x0ddc
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE                                         0x0de0
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE                                        0x0de4
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE                                        0x0de8
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS                                          0x0dec
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS                                         0x0df0
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS                                        0x0df4
+#define cfgPCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS                                        0x0df8
+
+
+// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_bifcfgpciedecp
+// base address: 0x0
+#define cfgBIF_CFG_DEV0_EPF0_LINK_CAP                                                                   0x0070
+#define cfgBIF_CFG_DEV0_EPF0_LINK_CNTL                                                                  0x0074
+#define cfgBIF_CFG_DEV0_EPF0_LINK_STATUS                                                                0x0076
+#define cfgBIF_CFG_DEV0_EPF0_LINK_CAP2                                                                  0x0090
+#define cfgBIF_CFG_DEV0_EPF0_LINK_CNTL2                                                                 0x0094
+#define cfgBIF_CFG_DEV0_EPF0_LINK_STATUS2                                                               0x0096
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                          0x0100
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR                                                   0x0104
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC1                                                      0x0108
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC2                                                      0x010c
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST                                                0x0110
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3                                                            0x0114
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_ERROR_STATUS                                                     0x0118
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL                                              0x011c
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL                                              0x011e
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL                                              0x0120
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL                                              0x0122
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL                                              0x0124
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL                                              0x0126
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL                                              0x0128
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL                                              0x012a
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL                                              0x012c
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL                                              0x012e
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL                                             0x0130
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL                                             0x0132
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL                                             0x0134
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL                                             0x0136
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL                                             0x0138
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL                                             0x013a
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST                                                 0x01b8
+#define cfgBIF_CFG_DEV0_EPF0_LINK_CAP_16GT                                                              0x01bc
+#define cfgBIF_CFG_DEV0_EPF0_LINK_CNTL_16GT                                                             0x01c0
+#define cfgBIF_CFG_DEV0_EPF0_LINK_STATUS_16GT                                                           0x01c4
+#define cfgBIF_CFG_DEV0_EPF0_LOCAL_PARITY_MISMATCH_STATUS_16GT                                          0x01c8
+#define cfgBIF_CFG_DEV0_EPF0_RTM1_PARITY_MISMATCH_STATUS_16GT                                           0x01cc
+#define cfgBIF_CFG_DEV0_EPF0_RTM2_PARITY_MISMATCH_STATUS_16GT                                           0x01d0
+#define cfgBIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT                                              0x01d8
+#define cfgBIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT                                              0x01d9
+#define cfgBIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT                                              0x01da
+#define cfgBIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT                                              0x01db
+#define cfgBIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT                                              0x01dc
+#define cfgBIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT                                              0x01dd
+#define cfgBIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT                                              0x01de
+#define cfgBIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT                                              0x01df
+#define cfgBIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT                                              0x01e0
+#define cfgBIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT                                              0x01e1
+#define cfgBIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT                                             0x01e2
+#define cfgBIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT                                             0x01e3
+#define cfgBIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT                                             0x01e4
+#define cfgBIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT                                             0x01e5
+#define cfgBIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT                                             0x01e6
+#define cfgBIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT                                             0x01e7
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_PHY_32GT_ENH_CAP_LIST                                                 0x01f8
+#define cfgBIF_CFG_DEV0_EPF0_LINK_CAP_32GT                                                              0x01fc
+#define cfgBIF_CFG_DEV0_EPF0_LINK_CNTL_32GT                                                             0x0200
+#define cfgBIF_CFG_DEV0_EPF0_LINK_STATUS_32GT                                                           0x0204
+#define cfgBIF_CFG_DEV0_EPF0_RECEIVED_MODIFIED_TS_DATA1                                                 0x0208
+#define cfgBIF_CFG_DEV0_EPF0_RECEIVED_MODIFIED_TS_DATA2                                                 0x020c
+#define cfgBIF_CFG_DEV0_EPF0_TRANSMITTED_MODIFIED_TS_DATA1                                              0x0210
+#define cfgBIF_CFG_DEV0_EPF0_TRANSMITTED_MODIFIED_TS_DATA2                                              0x0214
+#define cfgBIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_32GT                                              0x0218
+#define cfgBIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_32GT                                              0x0219
+#define cfgBIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_32GT                                              0x021a
+#define cfgBIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_32GT                                              0x021b
+#define cfgBIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_32GT                                              0x021c
+#define cfgBIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_32GT                                              0x021d
+#define cfgBIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_32GT                                              0x021e
+#define cfgBIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_32GT                                              0x021f
+#define cfgBIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_32GT                                              0x0220
+#define cfgBIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_32GT                                              0x0221
+#define cfgBIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_32GT                                             0x0222
+#define cfgBIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_32GT                                             0x0223
+#define cfgBIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_32GT                                             0x0224
+#define cfgBIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_32GT                                             0x0225
+#define cfgBIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_32GT                                             0x0226
+#define cfgBIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_32GT                                             0x0227
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_AP_ENH_CAP_LIST                                                       0x0238
+#define cfgBIF_CFG_DEV0_EPF0_AP_CAP                                                                     0x023c
+#define cfgBIF_CFG_DEV0_EPF0_AP_CNTL                                                                    0x0240
+#define cfgBIF_CFG_DEV0_EPF0_AP_DATA1                                                                   0x0244
+#define cfgBIF_CFG_DEV0_EPF0_AP_DATA2                                                                   0x0248
+#define cfgBIF_CFG_DEV0_EPF0_AP_SEL_EN_MASK                                                             0x024c
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST                                                0x0250
+#define cfgBIF_CFG_DEV0_EPF0_MARGINING_PORT_CAP                                                         0x0254
+#define cfgBIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS                                                      0x0256
+#define cfgBIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL                                                 0x0258
+#define cfgBIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS                                               0x025a
+#define cfgBIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL                                                 0x025c
+#define cfgBIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS                                               0x025e
+#define cfgBIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL                                                 0x0260
+#define cfgBIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS                                               0x0262
+#define cfgBIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL                                                 0x0264
+#define cfgBIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS                                               0x0266
+#define cfgBIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL                                                 0x0268
+#define cfgBIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS                                               0x026a
+#define cfgBIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL                                                 0x026c
+#define cfgBIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS                                               0x026e
+#define cfgBIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL                                                 0x0270
+#define cfgBIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS                                               0x0272
+#define cfgBIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL                                                 0x0274
+#define cfgBIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS                                               0x0276
+#define cfgBIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL                                                 0x0278
+#define cfgBIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS                                               0x027a
+#define cfgBIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL                                                 0x027c
+#define cfgBIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS                                               0x027e
+#define cfgBIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL                                                0x0280
+#define cfgBIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS                                              0x0282
+#define cfgBIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL                                                0x0284
+#define cfgBIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS                                              0x0286
+#define cfgBIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL                                                0x0288
+#define cfgBIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS                                              0x028a
+#define cfgBIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL                                                0x028c
+#define cfgBIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS                                              0x028e
+#define cfgBIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL                                                0x0290
+#define cfgBIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS                                              0x0292
+#define cfgBIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL                                                0x0294
+#define cfgBIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS                                              0x0296
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_NULL1_ENH_CAP_LIST                                                    0x0400
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST                                                       0x0404
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1                                                      0x0408
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2                                                      0x040c
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL                                                          0x0410
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_PORT_VC_STATUS                                                        0x0412
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP                                                      0x0414
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL                                                     0x0418
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS                                                   0x041e
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP                                                      0x0420
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL                                                     0x0424
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS                                                   0x042a
+#define cfgBIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST                                                      0x0430
+#define cfgBIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP                                                      0x0434
+#define cfgBIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS                                                   0x0438
+#define cfgBIF_CFG_DEV0_EPF0_IDE_ENH_CAP_LIST                                                           0x0e00
+#define cfgBIF_CFG_DEV0_EPF0_IDE_CAP                                                                    0x0e04
+#define cfgBIF_CFG_DEV0_EPF0_IDE_CNTL                                                                   0x0e08
+#define cfgBIF_CFG_DEV0_EPF0_LINK_IDE_STREAM_0_CNTL                                                     0x0e0c
+#define cfgBIF_CFG_DEV0_EPF0_LINK_IDE_STREAM_0_STATUS                                                   0x0e10
+#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CAP                                                 0x0e14
+#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CNTL                                                0x0e18
+#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_STATUS                                              0x0e1c
+#define cfgBIF_CFG_DEV0_EPF0_IDE_0_RID_ASSOCIATION_REG1                                                 0x0e20
+#define cfgBIF_CFG_DEV0_EPF0_IDE_0_RID_ASSOCIATION_REG2                                                 0x0e24
+#define cfgBIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_0_REG1                                              0x0e28
+#define cfgBIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_0_REG2                                              0x0e2c
+#define cfgBIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_0_REG3                                              0x0e30
+#define cfgBIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_1_REG1                                              0x0e34
+#define cfgBIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_1_REG2                                              0x0e38
+#define cfgBIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_1_REG3                                              0x0e3c
+#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CAP                                                 0x0e40
+#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CNTL                                                0x0e44
+#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_STATUS                                              0x0e48
+#define cfgBIF_CFG_DEV0_EPF0_IDE_1_RID_ASSOCIATION_REG1                                                 0x0e4c
+#define cfgBIF_CFG_DEV0_EPF0_IDE_1_RID_ASSOCIATION_REG2                                                 0x0e50
+#define cfgBIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_0_REG1                                              0x0e54
+#define cfgBIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_0_REG2                                              0x0e58
+#define cfgBIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_0_REG3                                              0x0e5c
+#define cfgBIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_1_REG1                                              0x0e60
+#define cfgBIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_1_REG2                                              0x0e64
+#define cfgBIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_1_REG3                                              0x0e68
+#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CAP                                                 0x0e6c
+#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CNTL                                                0x0e70
+#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_STATUS                                              0x0e74
+#define cfgBIF_CFG_DEV0_EPF0_IDE_2_RID_ASSOCIATION_REG1                                                 0x0e78
+#define cfgBIF_CFG_DEV0_EPF0_IDE_2_RID_ASSOCIATION_REG2                                                 0x0e7c
+#define cfgBIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_0_REG1                                              0x0e80
+#define cfgBIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_0_REG2                                              0x0e84
+#define cfgBIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_0_REG3                                              0x0e88
+#define cfgBIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_1_REG1                                              0x0e8c
+#define cfgBIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_1_REG2                                              0x0e90
+#define cfgBIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_1_REG3                                              0x0e94
+#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CAP                                                 0x0e98
+#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CNTL                                                0x0e9c
+#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_STATUS                                              0x0ea0
+#define cfgBIF_CFG_DEV0_EPF0_IDE_3_RID_ASSOCIATION_REG1                                                 0x0ea4
+#define cfgBIF_CFG_DEV0_EPF0_IDE_3_RID_ASSOCIATION_REG2                                                 0x0ea8
+#define cfgBIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_0_REG1                                              0x0eac
+#define cfgBIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_0_REG2                                              0x0eb0
+#define cfgBIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_0_REG3                                              0x0eb4
+#define cfgBIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_1_REG1                                              0x0eb8
+#define cfgBIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_1_REG2                                              0x0ebc
+#define cfgBIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_1_REG3                                              0x0ec0
+#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CAP                                                 0x0ec4
+#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CNTL                                                0x0ec8
+#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_STATUS                                              0x0ecc
+#define cfgBIF_CFG_DEV0_EPF0_IDE_4_RID_ASSOCIATION_REG1                                                 0x0ed0
+#define cfgBIF_CFG_DEV0_EPF0_IDE_4_RID_ASSOCIATION_REG2                                                 0x0ed4
+#define cfgBIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_0_REG1                                              0x0ed8
+#define cfgBIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_0_REG2                                              0x0edc
+#define cfgBIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_0_REG3                                              0x0ee0
+#define cfgBIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_1_REG1                                              0x0ee4
+#define cfgBIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_1_REG2                                              0x0ee8
+#define cfgBIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_1_REG3                                              0x0eec
+#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CAP                                                 0x0ef0
+#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CNTL                                                0x0ef4
+#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_STATUS                                              0x0ef8
+#define cfgBIF_CFG_DEV0_EPF0_IDE_5_RID_ASSOCIATION_REG1                                                 0x0efc
+#define cfgBIF_CFG_DEV0_EPF0_IDE_5_RID_ASSOCIATION_REG2                                                 0x0f00
+#define cfgBIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_0_REG1                                              0x0f04
+#define cfgBIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_0_REG2                                              0x0f08
+#define cfgBIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_0_REG3                                              0x0f0c
+#define cfgBIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_1_REG1                                              0x0f10
+#define cfgBIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_1_REG2                                              0x0f14
+#define cfgBIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_1_REG3                                              0x0f18
+#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CAP                                                 0x0f1c
+#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CNTL                                                0x0f20
+#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_STATUS                                              0x0f24
+#define cfgBIF_CFG_DEV0_EPF0_IDE_6_RID_ASSOCIATION_REG1                                                 0x0f28
+#define cfgBIF_CFG_DEV0_EPF0_IDE_6_RID_ASSOCIATION_REG2                                                 0x0f2c
+#define cfgBIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_0_REG1                                              0x0f30
+#define cfgBIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_0_REG2                                              0x0f34
+#define cfgBIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_0_REG3                                              0x0f38
+#define cfgBIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_1_REG1                                              0x0f3c
+#define cfgBIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_1_REG2                                              0x0f40
+#define cfgBIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_1_REG3                                              0x0f44
+#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CAP                                                 0x0f48
+#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CNTL                                                0x0f4c
+#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_STATUS                                              0x0f50
+#define cfgBIF_CFG_DEV0_EPF0_IDE_7_RID_ASSOCIATION_REG1                                                 0x0f54
+#define cfgBIF_CFG_DEV0_EPF0_IDE_7_RID_ASSOCIATION_REG2                                                 0x0f58
+#define cfgBIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_0_REG1                                              0x0f5c
+#define cfgBIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_0_REG2                                              0x0f60
+#define cfgBIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_0_REG3                                              0x0f64
+#define cfgBIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_1_REG1                                              0x0f68
+#define cfgBIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_1_REG2                                              0x0f6c
+#define cfgBIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_1_REG3                                              0x0f70
+#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CAP                                                 0x0f74
+#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CNTL                                                0x0f78
+#define cfgBIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_STATUS                                              0x0f7c
+#define cfgBIF_CFG_DEV0_EPF0_IDE_8_RID_ASSOCIATION_REG1                                                 0x0f80
+#define cfgBIF_CFG_DEV0_EPF0_IDE_8_RID_ASSOCIATION_REG2                                                 0x0f84
+#define cfgBIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_0_REG1                                              0x0f88
+#define cfgBIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_0_REG2                                              0x0f8c
+#define cfgBIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_0_REG3                                              0x0f90
+#define cfgBIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_1_REG1                                              0x0f94
+#define cfgBIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_1_REG2                                              0x0f98
+#define cfgBIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_1_REG3                                              0x0f9c
+
+
+// addressBlock: nbif0_nbif0_bif_cfg_dev0_rc_bifcfgdecp
+// base address: 0x10100000
+#define regBIF_CFG_DEV0_RC0_VENDOR_ID                                                                   0x0000
+#define regBIF_CFG_DEV0_RC0_VENDOR_ID_BASE_IDX                                                          5
+#define regBIF_CFG_DEV0_RC0_DEVICE_ID                                                                   0x0000
+#define regBIF_CFG_DEV0_RC0_DEVICE_ID_BASE_IDX                                                          5
+#define regBIF_CFG_DEV0_RC0_COMMAND                                                                     0x0001
+#define regBIF_CFG_DEV0_RC0_COMMAND_BASE_IDX                                                            5
+#define regBIF_CFG_DEV0_RC0_STATUS                                                                      0x0001
+#define regBIF_CFG_DEV0_RC0_STATUS_BASE_IDX                                                             5
+#define regBIF_CFG_DEV0_RC0_REVISION_ID                                                                 0x0002
+#define regBIF_CFG_DEV0_RC0_REVISION_ID_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_RC0_PROG_INTERFACE                                                              0x0002
+#define regBIF_CFG_DEV0_RC0_PROG_INTERFACE_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_RC0_SUB_CLASS                                                                   0x0002
+#define regBIF_CFG_DEV0_RC0_SUB_CLASS_BASE_IDX                                                          5
+#define regBIF_CFG_DEV0_RC0_BASE_CLASS                                                                  0x0002
+#define regBIF_CFG_DEV0_RC0_BASE_CLASS_BASE_IDX                                                         5
+#define regBIF_CFG_DEV0_RC0_CACHE_LINE                                                                  0x0003
+#define regBIF_CFG_DEV0_RC0_CACHE_LINE_BASE_IDX                                                         5
+#define regBIF_CFG_DEV0_RC0_LATENCY                                                                     0x0003
+#define regBIF_CFG_DEV0_RC0_LATENCY_BASE_IDX                                                            5
+#define regBIF_CFG_DEV0_RC0_HEADER                                                                      0x0003
+#define regBIF_CFG_DEV0_RC0_HEADER_BASE_IDX                                                             5
+#define regBIF_CFG_DEV0_RC0_BIST                                                                        0x0003
+#define regBIF_CFG_DEV0_RC0_BIST_BASE_IDX                                                               5
+#define regBIF_CFG_DEV0_RC0_BASE_ADDR_1                                                                 0x0004
+#define regBIF_CFG_DEV0_RC0_BASE_ADDR_1_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_RC0_BASE_ADDR_2                                                                 0x0005
+#define regBIF_CFG_DEV0_RC0_BASE_ADDR_2_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY                                                      0x0006
+#define regBIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_RC0_IO_BASE_LIMIT                                                               0x0007
+#define regBIF_CFG_DEV0_RC0_IO_BASE_LIMIT_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_RC0_SECONDARY_STATUS                                                            0x0007
+#define regBIF_CFG_DEV0_RC0_SECONDARY_STATUS_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_RC0_MEM_BASE_LIMIT                                                              0x0008
+#define regBIF_CFG_DEV0_RC0_MEM_BASE_LIMIT_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_RC0_PREF_BASE_LIMIT                                                             0x0009
+#define regBIF_CFG_DEV0_RC0_PREF_BASE_LIMIT_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_RC0_PREF_BASE_UPPER                                                             0x000a
+#define regBIF_CFG_DEV0_RC0_PREF_BASE_UPPER_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_RC0_PREF_LIMIT_UPPER                                                            0x000b
+#define regBIF_CFG_DEV0_RC0_PREF_LIMIT_UPPER_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI                                                            0x000c
+#define regBIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_RC0_CAP_PTR                                                                     0x000d
+#define regBIF_CFG_DEV0_RC0_CAP_PTR_BASE_IDX                                                            5
+#define regBIF_CFG_DEV0_RC0_ROM_BASE_ADDR                                                               0x000e
+#define regBIF_CFG_DEV0_RC0_ROM_BASE_ADDR_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_RC0_INTERRUPT_LINE                                                              0x000f
+#define regBIF_CFG_DEV0_RC0_INTERRUPT_LINE_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_RC0_INTERRUPT_PIN                                                               0x000f
+#define regBIF_CFG_DEV0_RC0_INTERRUPT_PIN_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL                                                             0x000f
+#define regBIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_RC0_EXT_BRIDGE_CNTL                                                             0x0010
+#define regBIF_CFG_DEV0_RC0_EXT_BRIDGE_CNTL_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_RC0_PMI_CAP_LIST                                                                0x0014
+#define regBIF_CFG_DEV0_RC0_PMI_CAP_LIST_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_RC0_PMI_CAP                                                                     0x0014
+#define regBIF_CFG_DEV0_RC0_PMI_CAP_BASE_IDX                                                            5
+#define regBIF_CFG_DEV0_RC0_PMI_STATUS_CNTL                                                             0x0015
+#define regBIF_CFG_DEV0_RC0_PMI_STATUS_CNTL_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_RC0_PCIE_CAP_LIST                                                               0x0016
+#define regBIF_CFG_DEV0_RC0_PCIE_CAP_LIST_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_RC0_PCIE_CAP                                                                    0x0016
+#define regBIF_CFG_DEV0_RC0_PCIE_CAP_BASE_IDX                                                           5
+#define regBIF_CFG_DEV0_RC0_DEVICE_CAP                                                                  0x0017
+#define regBIF_CFG_DEV0_RC0_DEVICE_CAP_BASE_IDX                                                         5
+#define regBIF_CFG_DEV0_RC0_DEVICE_CNTL                                                                 0x0018
+#define regBIF_CFG_DEV0_RC0_DEVICE_CNTL_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_RC0_DEVICE_STATUS                                                               0x0018
+#define regBIF_CFG_DEV0_RC0_DEVICE_STATUS_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_RC0_LINK_CAP                                                                    0x0019
+#define regBIF_CFG_DEV0_RC0_LINK_CAP_BASE_IDX                                                           5
+#define regBIF_CFG_DEV0_RC0_LINK_CNTL                                                                   0x001a
+#define regBIF_CFG_DEV0_RC0_LINK_CNTL_BASE_IDX                                                          5
+#define regBIF_CFG_DEV0_RC0_LINK_STATUS                                                                 0x001a
+#define regBIF_CFG_DEV0_RC0_LINK_STATUS_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_RC0_SLOT_CAP                                                                    0x001b
+#define regBIF_CFG_DEV0_RC0_SLOT_CAP_BASE_IDX                                                           5
+#define regBIF_CFG_DEV0_RC0_SLOT_CNTL                                                                   0x001c
+#define regBIF_CFG_DEV0_RC0_SLOT_CNTL_BASE_IDX                                                          5
+#define regBIF_CFG_DEV0_RC0_SLOT_STATUS                                                                 0x001c
+#define regBIF_CFG_DEV0_RC0_SLOT_STATUS_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_RC0_ROOT_CNTL                                                                   0x001d
+#define regBIF_CFG_DEV0_RC0_ROOT_CNTL_BASE_IDX                                                          5
+#define regBIF_CFG_DEV0_RC0_ROOT_CAP                                                                    0x001d
+#define regBIF_CFG_DEV0_RC0_ROOT_CAP_BASE_IDX                                                           5
+#define regBIF_CFG_DEV0_RC0_ROOT_STATUS                                                                 0x001e
+#define regBIF_CFG_DEV0_RC0_ROOT_STATUS_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_RC0_DEVICE_CAP2                                                                 0x001f
+#define regBIF_CFG_DEV0_RC0_DEVICE_CAP2_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_RC0_DEVICE_CNTL2                                                                0x0020
+#define regBIF_CFG_DEV0_RC0_DEVICE_CNTL2_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_RC0_DEVICE_STATUS2                                                              0x0020
+#define regBIF_CFG_DEV0_RC0_DEVICE_STATUS2_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_RC0_LINK_CAP2                                                                   0x0021
+#define regBIF_CFG_DEV0_RC0_LINK_CAP2_BASE_IDX                                                          5
+#define regBIF_CFG_DEV0_RC0_LINK_CNTL2                                                                  0x0022
+#define regBIF_CFG_DEV0_RC0_LINK_CNTL2_BASE_IDX                                                         5
+#define regBIF_CFG_DEV0_RC0_LINK_STATUS2                                                                0x0022
+#define regBIF_CFG_DEV0_RC0_LINK_STATUS2_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_RC0_SLOT_CAP2                                                                   0x0023
+#define regBIF_CFG_DEV0_RC0_SLOT_CAP2_BASE_IDX                                                          5
+#define regBIF_CFG_DEV0_RC0_SLOT_CNTL2                                                                  0x0024
+#define regBIF_CFG_DEV0_RC0_SLOT_CNTL2_BASE_IDX                                                         5
+#define regBIF_CFG_DEV0_RC0_SLOT_STATUS2                                                                0x0024
+#define regBIF_CFG_DEV0_RC0_SLOT_STATUS2_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_RC0_MSI_CAP_LIST                                                                0x0028
+#define regBIF_CFG_DEV0_RC0_MSI_CAP_LIST_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_RC0_MSI_MSG_CNTL                                                                0x0028
+#define regBIF_CFG_DEV0_RC0_MSI_MSG_CNTL_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_RC0_MSI_MSG_ADDR_LO                                                             0x0029
+#define regBIF_CFG_DEV0_RC0_MSI_MSG_ADDR_LO_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_RC0_MSI_MSG_ADDR_HI                                                             0x002a
+#define regBIF_CFG_DEV0_RC0_MSI_MSG_ADDR_HI_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_RC0_MSI_MSG_DATA                                                                0x002a
+#define regBIF_CFG_DEV0_RC0_MSI_MSG_DATA_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA                                                            0x002a
+#define regBIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_RC0_MSI_MSG_DATA_64                                                             0x002b
+#define regBIF_CFG_DEV0_RC0_MSI_MSG_DATA_64_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA_64                                                         0x002b
+#define regBIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA_64_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_RC0_SSID_CAP_LIST                                                               0x0030
+#define regBIF_CFG_DEV0_RC0_SSID_CAP_LIST_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_RC0_SSID_CAP                                                                    0x0031
+#define regBIF_CFG_DEV0_RC0_SSID_CAP_BASE_IDX                                                           5
+#define regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                           0x0040
+#define regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX                                  5
+#define regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR                                                    0x0041
+#define regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC1                                                       0x0042
+#define regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC1_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC2                                                       0x0043
+#define regBIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC2_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST                                                 0x0044
+#define regBIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3                                                             0x0045
+#define regBIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_RC0_PCIE_LANE_ERROR_STATUS                                                      0x0046
+#define regBIF_CFG_DEV0_RC0_PCIE_LANE_ERROR_STATUS_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL                                               0x0047
+#define regBIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL                                               0x0047
+#define regBIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL                                               0x0048
+#define regBIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL                                               0x0048
+#define regBIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL                                               0x0049
+#define regBIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL                                               0x0049
+#define regBIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL                                               0x004a
+#define regBIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL                                               0x004a
+#define regBIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL                                               0x004b
+#define regBIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL                                               0x004b
+#define regBIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL                                              0x004c
+#define regBIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL                                              0x004c
+#define regBIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL                                              0x004d
+#define regBIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL                                              0x004d
+#define regBIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL                                              0x004e
+#define regBIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL                                              0x004e
+#define regBIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST                                                  0x006e
+#define regBIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_RC0_LINK_CAP_16GT                                                               0x006f
+#define regBIF_CFG_DEV0_RC0_LINK_CAP_16GT_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_RC0_LINK_CNTL_16GT                                                              0x0070
+#define regBIF_CFG_DEV0_RC0_LINK_CNTL_16GT_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_RC0_LINK_STATUS_16GT                                                            0x0071
+#define regBIF_CFG_DEV0_RC0_LINK_STATUS_16GT_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT                                           0x0072
+#define regBIF_CFG_DEV0_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT_BASE_IDX                                  5
+#define regBIF_CFG_DEV0_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT                                            0x0073
+#define regBIF_CFG_DEV0_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT                                            0x0074
+#define regBIF_CFG_DEV0_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT                                               0x0076
+#define regBIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT                                               0x0076
+#define regBIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT                                               0x0076
+#define regBIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT                                               0x0076
+#define regBIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT                                               0x0077
+#define regBIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT                                               0x0077
+#define regBIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT                                               0x0077
+#define regBIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT                                               0x0077
+#define regBIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT                                               0x0078
+#define regBIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT                                               0x0078
+#define regBIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT                                              0x0078
+#define regBIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT                                              0x0078
+#define regBIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT                                              0x0079
+#define regBIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT                                              0x0079
+#define regBIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT                                              0x0079
+#define regBIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT                                              0x0079
+#define regBIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_RC0_PCIE_PHY_32GT_ENH_CAP_LIST                                                  0x007e
+#define regBIF_CFG_DEV0_RC0_PCIE_PHY_32GT_ENH_CAP_LIST_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_RC0_LINK_CAP_32GT                                                               0x007f
+#define regBIF_CFG_DEV0_RC0_LINK_CAP_32GT_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_RC0_LINK_CNTL_32GT                                                              0x0080
+#define regBIF_CFG_DEV0_RC0_LINK_CNTL_32GT_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_RC0_LINK_STATUS_32GT                                                            0x0081
+#define regBIF_CFG_DEV0_RC0_LINK_STATUS_32GT_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_RC0_RECEIVED_MODIFIED_TS_DATA1                                                  0x0082
+#define regBIF_CFG_DEV0_RC0_RECEIVED_MODIFIED_TS_DATA1_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_RC0_RECEIVED_MODIFIED_TS_DATA2                                                  0x0083
+#define regBIF_CFG_DEV0_RC0_RECEIVED_MODIFIED_TS_DATA2_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_RC0_TRANSMITTED_MODIFIED_TS_DATA1                                               0x0084
+#define regBIF_CFG_DEV0_RC0_TRANSMITTED_MODIFIED_TS_DATA1_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_TRANSMITTED_MODIFIED_TS_DATA2                                               0x0085
+#define regBIF_CFG_DEV0_RC0_TRANSMITTED_MODIFIED_TS_DATA2_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_32GT                                               0x0086
+#define regBIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_32GT_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_32GT                                               0x0086
+#define regBIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_32GT_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_32GT                                               0x0086
+#define regBIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_32GT_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_32GT                                               0x0086
+#define regBIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_32GT_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_32GT                                               0x0087
+#define regBIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_32GT_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_32GT                                               0x0087
+#define regBIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_32GT_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_32GT                                               0x0087
+#define regBIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_32GT_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_32GT                                               0x0087
+#define regBIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_32GT_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_32GT                                               0x0088
+#define regBIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_32GT_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_32GT                                               0x0088
+#define regBIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_32GT_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_32GT                                              0x0088
+#define regBIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_32GT_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_32GT                                              0x0088
+#define regBIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_32GT_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_32GT                                              0x0089
+#define regBIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_32GT_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_32GT                                              0x0089
+#define regBIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_32GT_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_32GT                                              0x0089
+#define regBIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_32GT_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_32GT                                              0x0089
+#define regBIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_32GT_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_RC0_PCIE_AP_ENH_CAP_LIST                                                        0x008e
+#define regBIF_CFG_DEV0_RC0_PCIE_AP_ENH_CAP_LIST_BASE_IDX                                               5
+#define regBIF_CFG_DEV0_RC0_AP_CAP                                                                      0x008f
+#define regBIF_CFG_DEV0_RC0_AP_CAP_BASE_IDX                                                             5
+#define regBIF_CFG_DEV0_RC0_AP_CNTL                                                                     0x0090
+#define regBIF_CFG_DEV0_RC0_AP_CNTL_BASE_IDX                                                            5
+#define regBIF_CFG_DEV0_RC0_AP_DATA1                                                                    0x0091
+#define regBIF_CFG_DEV0_RC0_AP_DATA1_BASE_IDX                                                           5
+#define regBIF_CFG_DEV0_RC0_AP_DATA2                                                                    0x0092
+#define regBIF_CFG_DEV0_RC0_AP_DATA2_BASE_IDX                                                           5
+#define regBIF_CFG_DEV0_RC0_AP_SEL_EN_MASK                                                              0x0093
+#define regBIF_CFG_DEV0_RC0_AP_SEL_EN_MASK_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST                                                 0x0094
+#define regBIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_RC0_MARGINING_PORT_CAP                                                          0x0095
+#define regBIF_CFG_DEV0_RC0_MARGINING_PORT_CAP_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS                                                       0x0095
+#define regBIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL                                                  0x0096
+#define regBIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS                                                0x0096
+#define regBIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS_BASE_IDX                                       5
+#define regBIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL                                                  0x0097
+#define regBIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS                                                0x0097
+#define regBIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS_BASE_IDX                                       5
+#define regBIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL                                                  0x0098
+#define regBIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS                                                0x0098
+#define regBIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS_BASE_IDX                                       5
+#define regBIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL                                                  0x0099
+#define regBIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS                                                0x0099
+#define regBIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS_BASE_IDX                                       5
+#define regBIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL                                                  0x009a
+#define regBIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS                                                0x009a
+#define regBIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS_BASE_IDX                                       5
+#define regBIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL                                                  0x009b
+#define regBIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS                                                0x009b
+#define regBIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS_BASE_IDX                                       5
+#define regBIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL                                                  0x009c
+#define regBIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS                                                0x009c
+#define regBIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS_BASE_IDX                                       5
+#define regBIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL                                                  0x009d
+#define regBIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS                                                0x009d
+#define regBIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS_BASE_IDX                                       5
+#define regBIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL                                                  0x009e
+#define regBIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS                                                0x009e
+#define regBIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS_BASE_IDX                                       5
+#define regBIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL                                                  0x009f
+#define regBIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS                                                0x009f
+#define regBIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS_BASE_IDX                                       5
+#define regBIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL                                                 0x00a0
+#define regBIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS                                               0x00a0
+#define regBIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL                                                 0x00a1
+#define regBIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS                                               0x00a1
+#define regBIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL                                                 0x00a2
+#define regBIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS                                               0x00a2
+#define regBIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL                                                 0x00a3
+#define regBIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS                                               0x00a3
+#define regBIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL                                                 0x00a4
+#define regBIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS                                               0x00a4
+#define regBIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL                                                 0x00a5
+#define regBIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS                                               0x00a5
+#define regBIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_PCIE_NULL1_ENH_CAP_LIST                                                     0x0100
+#define regBIF_CFG_DEV0_RC0_PCIE_NULL1_ENH_CAP_LIST_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST                                                        0x0101
+#define regBIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST_BASE_IDX                                               5
+#define regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1                                                       0x0102
+#define regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2                                                       0x0103
+#define regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL                                                           0x0104
+#define regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_STATUS                                                         0x0104
+#define regBIF_CFG_DEV0_RC0_PCIE_PORT_VC_STATUS_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP                                                       0x0105
+#define regBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL                                                      0x0106
+#define regBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS                                                    0x0107
+#define regBIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP                                                       0x0108
+#define regBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL                                                      0x0109
+#define regBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS                                                    0x010a
+#define regBIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST                                                       0x010c
+#define regBIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP                                                       0x010d
+#define regBIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS                                                    0x010e
+#define regBIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_RC0_PCIE_NULL2_ENH_CAP_LIST                                                     0x0180
+#define regBIF_CFG_DEV0_RC0_PCIE_NULL2_ENH_CAP_LIST_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                               0x0181
+#define regBIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS                                                      0x0182
+#define regBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK                                                        0x0183
+#define regBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK_BASE_IDX                                               5
+#define regBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY                                                    0x0184
+#define regBIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS                                                        0x0185
+#define regBIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS_BASE_IDX                                               5
+#define regBIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK                                                          0x0186
+#define regBIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL                                                       0x0187
+#define regBIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG0                                                               0x0188
+#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG0_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG1                                                               0x0189
+#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG1_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG2                                                               0x018a
+#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG2_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG3                                                               0x018b
+#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG3_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD                                                           0x018c
+#define regBIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS                                                        0x018d
+#define regBIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS_BASE_IDX                                               5
+#define regBIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID                                                             0x018e
+#define regBIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG4                                                               0x018f
+#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG4_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG0                                                        0x018f
+#define regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG0_BASE_IDX                                               5
+#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG5                                                               0x0190
+#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG5_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG1                                                        0x0190
+#define regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG1_BASE_IDX                                               5
+#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG6                                                               0x0191
+#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG6_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG2                                                        0x0191
+#define regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG2_BASE_IDX                                               5
+#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG7                                                               0x0192
+#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG7_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG3                                                        0x0192
+#define regBIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG3_BASE_IDX                                               5
+#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG8                                                               0x0193
+#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG8_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG9                                                               0x0194
+#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG9_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG10                                                              0x0195
+#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG10_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG11                                                              0x0196
+#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG11_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG12                                                              0x0197
+#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG12_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG13                                                              0x0198
+#define regBIF_CFG_DEV0_RC0_PCIE_HDR_LOG13_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST                                            0x0199
+#define regBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW1                                                     0x019a
+#define regBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW1_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW2                                                     0x019b
+#define regBIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW2_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST                                                       0x01b7
+#define regBIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_RC0_PCIE_ACS_CAP                                                                0x01b8
+#define regBIF_CFG_DEV0_RC0_PCIE_ACS_CAP_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_RC0_PCIE_ACS_CNTL                                                               0x01b8
+#define regBIF_CFG_DEV0_RC0_PCIE_ACS_CNTL_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_RC0_PCIE_RTR_ENH_CAP_LIST                                                       0x01c7
+#define regBIF_CFG_DEV0_RC0_PCIE_RTR_ENH_CAP_LIST_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_RC0_RTR_DATA1                                                                   0x01c8
+#define regBIF_CFG_DEV0_RC0_RTR_DATA1_BASE_IDX                                                          5
+#define regBIF_CFG_DEV0_RC0_RTR_DATA2                                                                   0x01c9
+#define regBIF_CFG_DEV0_RC0_RTR_DATA2_BASE_IDX                                                          5
+#define regBIF_CFG_DEV0_RC0_IDE_ENH_CAP_LIST                                                            0x0380
+#define regBIF_CFG_DEV0_RC0_IDE_ENH_CAP_LIST_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_RC0_IDE_CAP                                                                     0x0381
+#define regBIF_CFG_DEV0_RC0_IDE_CAP_BASE_IDX                                                            5
+#define regBIF_CFG_DEV0_RC0_IDE_CNTL                                                                    0x0382
+#define regBIF_CFG_DEV0_RC0_IDE_CNTL_BASE_IDX                                                           5
+#define regBIF_CFG_DEV0_RC0_LINK_IDE_STREAM_0_CNTL                                                      0x0383
+#define regBIF_CFG_DEV0_RC0_LINK_IDE_STREAM_0_CNTL_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_RC0_LINK_IDE_STREAM_0_STATUS                                                    0x0384
+#define regBIF_CFG_DEV0_RC0_LINK_IDE_STREAM_0_STATUS_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CAP                                                  0x0385
+#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CAP_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CNTL                                                 0x0386
+#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CNTL_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_STATUS                                               0x0387
+#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_STATUS_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_IDE_0_RID_ASSOCIATION_REG1                                                  0x0388
+#define regBIF_CFG_DEV0_RC0_IDE_0_RID_ASSOCIATION_REG1_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_RC0_IDE_0_RID_ASSOCIATION_REG2                                                  0x0389
+#define regBIF_CFG_DEV0_RC0_IDE_0_RID_ASSOCIATION_REG2_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_0_REG1                                               0x038a
+#define regBIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_0_REG1_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_0_REG2                                               0x038b
+#define regBIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_0_REG2_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_0_REG3                                               0x038c
+#define regBIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_0_REG3_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_1_REG1                                               0x038d
+#define regBIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_1_REG1_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_1_REG2                                               0x038e
+#define regBIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_1_REG2_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_1_REG3                                               0x038f
+#define regBIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_1_REG3_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CAP                                                  0x0390
+#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CAP_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CNTL                                                 0x0391
+#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CNTL_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_STATUS                                               0x0392
+#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_STATUS_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_IDE_1_RID_ASSOCIATION_REG1                                                  0x0393
+#define regBIF_CFG_DEV0_RC0_IDE_1_RID_ASSOCIATION_REG1_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_RC0_IDE_1_RID_ASSOCIATION_REG2                                                  0x0394
+#define regBIF_CFG_DEV0_RC0_IDE_1_RID_ASSOCIATION_REG2_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_0_REG1                                               0x0395
+#define regBIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_0_REG1_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_0_REG2                                               0x0396
+#define regBIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_0_REG2_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_0_REG3                                               0x0397
+#define regBIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_0_REG3_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_1_REG1                                               0x0398
+#define regBIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_1_REG1_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_1_REG2                                               0x0399
+#define regBIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_1_REG2_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_1_REG3                                               0x039a
+#define regBIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_1_REG3_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CAP                                                  0x039b
+#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CAP_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CNTL                                                 0x039c
+#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CNTL_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_STATUS                                               0x039d
+#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_STATUS_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_IDE_2_RID_ASSOCIATION_REG1                                                  0x039e
+#define regBIF_CFG_DEV0_RC0_IDE_2_RID_ASSOCIATION_REG1_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_RC0_IDE_2_RID_ASSOCIATION_REG2                                                  0x039f
+#define regBIF_CFG_DEV0_RC0_IDE_2_RID_ASSOCIATION_REG2_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_0_REG1                                               0x03a0
+#define regBIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_0_REG1_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_0_REG2                                               0x03a1
+#define regBIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_0_REG2_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_0_REG3                                               0x03a2
+#define regBIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_0_REG3_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_1_REG1                                               0x03a3
+#define regBIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_1_REG1_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_1_REG2                                               0x03a4
+#define regBIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_1_REG2_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_1_REG3                                               0x03a5
+#define regBIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_1_REG3_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CAP                                                  0x03a6
+#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CAP_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CNTL                                                 0x03a7
+#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CNTL_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_STATUS                                               0x03a8
+#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_STATUS_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_IDE_3_RID_ASSOCIATION_REG1                                                  0x03a9
+#define regBIF_CFG_DEV0_RC0_IDE_3_RID_ASSOCIATION_REG1_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_RC0_IDE_3_RID_ASSOCIATION_REG2                                                  0x03aa
+#define regBIF_CFG_DEV0_RC0_IDE_3_RID_ASSOCIATION_REG2_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_0_REG1                                               0x03ab
+#define regBIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_0_REG1_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_0_REG2                                               0x03ac
+#define regBIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_0_REG2_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_0_REG3                                               0x03ad
+#define regBIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_0_REG3_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_1_REG1                                               0x03ae
+#define regBIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_1_REG1_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_1_REG2                                               0x03af
+#define regBIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_1_REG2_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_1_REG3                                               0x03b0
+#define regBIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_1_REG3_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CAP                                                  0x03b1
+#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CAP_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CNTL                                                 0x03b2
+#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CNTL_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_STATUS                                               0x03b3
+#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_STATUS_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_IDE_4_RID_ASSOCIATION_REG1                                                  0x03b4
+#define regBIF_CFG_DEV0_RC0_IDE_4_RID_ASSOCIATION_REG1_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_RC0_IDE_4_RID_ASSOCIATION_REG2                                                  0x03b5
+#define regBIF_CFG_DEV0_RC0_IDE_4_RID_ASSOCIATION_REG2_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_0_REG1                                               0x03b6
+#define regBIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_0_REG1_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_0_REG2                                               0x03b7
+#define regBIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_0_REG2_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_0_REG3                                               0x03b8
+#define regBIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_0_REG3_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_1_REG1                                               0x03b9
+#define regBIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_1_REG1_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_1_REG2                                               0x03ba
+#define regBIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_1_REG2_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_1_REG3                                               0x03bb
+#define regBIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_1_REG3_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CAP                                                  0x03bc
+#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CAP_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CNTL                                                 0x03bd
+#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CNTL_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_STATUS                                               0x03be
+#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_STATUS_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_IDE_5_RID_ASSOCIATION_REG1                                                  0x03bf
+#define regBIF_CFG_DEV0_RC0_IDE_5_RID_ASSOCIATION_REG1_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_RC0_IDE_5_RID_ASSOCIATION_REG2                                                  0x03c0
+#define regBIF_CFG_DEV0_RC0_IDE_5_RID_ASSOCIATION_REG2_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_0_REG1                                               0x03c1
+#define regBIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_0_REG1_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_0_REG2                                               0x03c2
+#define regBIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_0_REG2_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_0_REG3                                               0x03c3
+#define regBIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_0_REG3_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_1_REG1                                               0x03c4
+#define regBIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_1_REG1_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_1_REG2                                               0x03c5
+#define regBIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_1_REG2_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_1_REG3                                               0x03c6
+#define regBIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_1_REG3_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CAP                                                  0x03c7
+#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CAP_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CNTL                                                 0x03c8
+#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CNTL_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_STATUS                                               0x03c9
+#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_STATUS_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_IDE_6_RID_ASSOCIATION_REG1                                                  0x03ca
+#define regBIF_CFG_DEV0_RC0_IDE_6_RID_ASSOCIATION_REG1_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_RC0_IDE_6_RID_ASSOCIATION_REG2                                                  0x03cb
+#define regBIF_CFG_DEV0_RC0_IDE_6_RID_ASSOCIATION_REG2_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_0_REG1                                               0x03cc
+#define regBIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_0_REG1_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_0_REG2                                               0x03cd
+#define regBIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_0_REG2_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_0_REG3                                               0x03ce
+#define regBIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_0_REG3_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_1_REG1                                               0x03cf
+#define regBIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_1_REG1_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_1_REG2                                               0x03d0
+#define regBIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_1_REG2_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_1_REG3                                               0x03d1
+#define regBIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_1_REG3_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CAP                                                  0x03d2
+#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CAP_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CNTL                                                 0x03d3
+#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CNTL_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_STATUS                                               0x03d4
+#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_STATUS_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_IDE_7_RID_ASSOCIATION_REG1                                                  0x03d5
+#define regBIF_CFG_DEV0_RC0_IDE_7_RID_ASSOCIATION_REG1_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_RC0_IDE_7_RID_ASSOCIATION_REG2                                                  0x03d6
+#define regBIF_CFG_DEV0_RC0_IDE_7_RID_ASSOCIATION_REG2_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_0_REG1                                               0x03d7
+#define regBIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_0_REG1_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_0_REG2                                               0x03d8
+#define regBIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_0_REG2_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_0_REG3                                               0x03d9
+#define regBIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_0_REG3_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_1_REG1                                               0x03da
+#define regBIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_1_REG1_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_1_REG2                                               0x03db
+#define regBIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_1_REG2_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_1_REG3                                               0x03dc
+#define regBIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_1_REG3_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CAP                                                  0x03dd
+#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CAP_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CNTL                                                 0x03de
+#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CNTL_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_STATUS                                               0x03df
+#define regBIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_STATUS_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_IDE_8_RID_ASSOCIATION_REG1                                                  0x03e0
+#define regBIF_CFG_DEV0_RC0_IDE_8_RID_ASSOCIATION_REG1_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_RC0_IDE_8_RID_ASSOCIATION_REG2                                                  0x03e1
+#define regBIF_CFG_DEV0_RC0_IDE_8_RID_ASSOCIATION_REG2_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_0_REG1                                               0x03e2
+#define regBIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_0_REG1_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_0_REG2                                               0x03e3
+#define regBIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_0_REG2_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_0_REG3                                               0x03e4
+#define regBIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_0_REG3_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_1_REG1                                               0x03e5
+#define regBIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_1_REG1_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_1_REG2                                               0x03e6
+#define regBIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_1_REG2_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_1_REG3                                               0x03e7
+#define regBIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_1_REG3_BASE_IDX                                      5
+
+
+// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_bifcfgdecp
+// base address: 0x10140000
+#define regBIF_CFG_DEV0_EPF0_0_VENDOR_ID                                                                0x10000
+#define regBIF_CFG_DEV0_EPF0_0_VENDOR_ID_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF0_0_DEVICE_ID                                                                0x10000
+#define regBIF_CFG_DEV0_EPF0_0_DEVICE_ID_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF0_0_COMMAND                                                                  0x10001
+#define regBIF_CFG_DEV0_EPF0_0_COMMAND_BASE_IDX                                                         5
+#define regBIF_CFG_DEV0_EPF0_0_STATUS                                                                   0x10001
+#define regBIF_CFG_DEV0_EPF0_0_STATUS_BASE_IDX                                                          5
+#define regBIF_CFG_DEV0_EPF0_0_REVISION_ID                                                              0x10002
+#define regBIF_CFG_DEV0_EPF0_0_REVISION_ID_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_0_PROG_INTERFACE                                                           0x10002
+#define regBIF_CFG_DEV0_EPF0_0_PROG_INTERFACE_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_0_SUB_CLASS                                                                0x10002
+#define regBIF_CFG_DEV0_EPF0_0_SUB_CLASS_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF0_0_BASE_CLASS                                                               0x10002
+#define regBIF_CFG_DEV0_EPF0_0_BASE_CLASS_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF0_0_CACHE_LINE                                                               0x10003
+#define regBIF_CFG_DEV0_EPF0_0_CACHE_LINE_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF0_0_LATENCY                                                                  0x10003
+#define regBIF_CFG_DEV0_EPF0_0_LATENCY_BASE_IDX                                                         5
+#define regBIF_CFG_DEV0_EPF0_0_HEADER                                                                   0x10003
+#define regBIF_CFG_DEV0_EPF0_0_HEADER_BASE_IDX                                                          5
+#define regBIF_CFG_DEV0_EPF0_0_BIST                                                                     0x10003
+#define regBIF_CFG_DEV0_EPF0_0_BIST_BASE_IDX                                                            5
+#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_1                                                              0x10004
+#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_1_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_2                                                              0x10005
+#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_2_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_3                                                              0x10006
+#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_3_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_4                                                              0x10007
+#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_4_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_5                                                              0x10008
+#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_5_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_6                                                              0x10009
+#define regBIF_CFG_DEV0_EPF0_0_BASE_ADDR_6_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_0_CARDBUS_CIS_PTR                                                          0x1000a
+#define regBIF_CFG_DEV0_EPF0_0_CARDBUS_CIS_PTR_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_0_ADAPTER_ID                                                               0x1000b
+#define regBIF_CFG_DEV0_EPF0_0_ADAPTER_ID_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR                                                            0x1000c
+#define regBIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_0_CAP_PTR                                                                  0x1000d
+#define regBIF_CFG_DEV0_EPF0_0_CAP_PTR_BASE_IDX                                                         5
+#define regBIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE                                                           0x1000f
+#define regBIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN                                                            0x1000f
+#define regBIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_0_MIN_GRANT                                                                0x1000f
+#define regBIF_CFG_DEV0_EPF0_0_MIN_GRANT_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF0_0_MAX_LATENCY                                                              0x1000f
+#define regBIF_CFG_DEV0_EPF0_0_MAX_LATENCY_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST                                                          0x10012
+#define regBIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W                                                             0x10013
+#define regBIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST                                                             0x10014
+#define regBIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF0_0_PMI_CAP                                                                  0x10014
+#define regBIF_CFG_DEV0_EPF0_0_PMI_CAP_BASE_IDX                                                         5
+#define regBIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL                                                          0x10015
+#define regBIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST                                                            0x10019
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_CAP                                                                 0x10019
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_CAP_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_EPF0_0_DEVICE_CAP                                                               0x1001a
+#define regBIF_CFG_DEV0_EPF0_0_DEVICE_CAP_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL                                                              0x1001b
+#define regBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS                                                            0x1001b
+#define regBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_0_DEVICE_CAP2                                                              0x10022
+#define regBIF_CFG_DEV0_EPF0_0_DEVICE_CAP2_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2                                                             0x10023
+#define regBIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2                                                           0x10023
+#define regBIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST                                                             0x10028
+#define regBIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL                                                             0x10028
+#define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO                                                          0x10029
+#define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI                                                          0x1002a
+#define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA                                                             0x1002a
+#define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA                                                         0x1002a
+#define regBIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF0_0_MSI_MASK                                                                 0x1002b
+#define regBIF_CFG_DEV0_EPF0_0_MSI_MASK_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64                                                          0x1002b
+#define regBIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA_64                                                      0x1002b
+#define regBIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA_64_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF0_0_MSI_MASK_64                                                              0x1002c
+#define regBIF_CFG_DEV0_EPF0_0_MSI_MASK_64_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_0_MSI_PENDING                                                              0x1002c
+#define regBIF_CFG_DEV0_EPF0_0_MSI_PENDING_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_0_MSI_PENDING_64                                                           0x1002d
+#define regBIF_CFG_DEV0_EPF0_0_MSI_PENDING_64_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST                                                            0x10030
+#define regBIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL                                                            0x10030
+#define regBIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_0_MSIX_TABLE                                                               0x10031
+#define regBIF_CFG_DEV0_EPF0_0_MSIX_TABLE_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF0_0_MSIX_PBA                                                                 0x10032
+#define regBIF_CFG_DEV0_EPF0_0_MSIX_PBA_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_NULL2_ENH_CAP_LIST                                                  0x10180
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_NULL2_ENH_CAP_LIST_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                            0x10181
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS                                                   0x10182
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK                                                     0x10183
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY                                                 0x10184
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS                                                     0x10185
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK                                                       0x10186
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL                                                    0x10187
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0                                                            0x10188
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1                                                            0x10189
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2                                                            0x1018a
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3                                                            0x1018b
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG4                                                            0x1018f
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG4_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0                                                     0x1018f
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG5                                                            0x10190
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG5_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1                                                     0x10190
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG6                                                            0x10191
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG6_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2                                                     0x10191
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG7                                                            0x10192
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG7_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3                                                     0x10192
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG8                                                            0x10193
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG8_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG9                                                            0x10194
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG9_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG10                                                           0x10195
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG10_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG11                                                           0x10196
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG11_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG12                                                           0x10197
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG12_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG13                                                           0x10198
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG13_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST                                         0x10199
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST_BASE_IDX                                5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1                                                  0x1019a
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2                                                  0x1019b
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST                                                    0x101b7
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP                                                             0x101b8
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL                                                            0x101b8
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_RTR_ENH_CAP_LIST                                                    0x101c7
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_RTR_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF0_0_RTR_DATA1                                                                0x101c8
+#define regBIF_CFG_DEV0_EPF0_0_RTR_DATA1_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF0_0_RTR_DATA2                                                                0x101c9
+#define regBIF_CFG_DEV0_EPF0_0_RTR_DATA2_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST                                             0x101ca
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX                                    5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT                                              0x101cb
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA                                                     0x101cc
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP                                                      0x101cd
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST                                                    0x101ce
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP                                                             0x101cf
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR                                               0x101d0
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS                                                          0x101d1
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL                                                            0x101d1
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0                                            0x101d2
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1                                            0x101d2
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2                                            0x101d2
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3                                            0x101d2
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4                                            0x101d3
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5                                            0x101d3
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6                                            0x101d3
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7                                            0x101d3
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST                                                    0x101da
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP                                                             0x101db
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST                                                    0x101dc
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP                                                             0x101dd
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL                                                            0x101dd
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST                                                    0x101de
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP                                                            0x101df
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL                                                           0x101e0
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP                                                            0x101e1
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL                                                           0x101e2
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP                                                            0x101e3
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL                                                           0x101e4
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP                                                            0x101e5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL                                                           0x101e6
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP                                                            0x101e7
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL                                                           0x101e8
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP                                                            0x101e9
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL                                                           0x101ea
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST                                                    0x101eb
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP                                                             0x101ec
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL                                                            0x101ec
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST                                               0x101ed
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL                                                       0x101ee
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS                                                     0x101ee
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY                                          0x101ef
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY_BASE_IDX                                 5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC                                             0x101f0
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC_BASE_IDX                                    5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST                                                  0x101f1
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP                                                           0x101f2
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL                                                          0x101f2
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST                                                  0x101f3
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP                                                           0x101f4
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL                                                       0x101f5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS                                                        0x101f5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS_BASE_IDX                                               5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS                                                   0x101f6
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS                                                     0x101f6
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS                                                       0x101f7
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK                                                 0x101f7
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET                                               0x101f8
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE                                                     0x101f8
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID                                                  0x101f9
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE                                           0x101fa
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE_BASE_IDX                                  5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE                                              0x101fb
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0                                                0x101fc
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0_BASE_IDX                                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1                                                0x101fd
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1_BASE_IDX                                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2                                                0x101fe
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2_BASE_IDX                                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3                                                0x101ff
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3_BASE_IDX                                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4                                                0x10200
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4_BASE_IDX                                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5                                                0x10201
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5_BASE_IDX                                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET                               0x10202
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_BASE_IDX                      5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST                                          0x10238
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST_BASE_IDX                                 5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CAP                                                  0x10239
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CAP_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL                                                 0x1023a
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CAP                                                  0x1023b
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CAP_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL                                                 0x1023c
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CAP                                                  0x1023d
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CAP_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL                                                 0x1023e
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CAP                                                  0x1023f
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CAP_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL                                                 0x10240
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CAP                                                  0x10241
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CAP_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL                                                 0x10242
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CAP                                                  0x10243
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CAP_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL                                                 0x10244
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_DOE_ENH_CAP_LIST                                                    0x10245
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_DOE_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_DOE_CAP                                                             0x10246
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_DOE_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_DOE_CNTL                                                            0x10247
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_DOE_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_DOE_STS                                                             0x10248
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_DOE_STS_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_DOE_WMBOX                                                           0x10249
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_DOE_WMBOX_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_DOE_RMBOX                                                           0x1024a
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_DOE_RMBOX_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV                                 0x1026b
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV                                          0x1026c
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_BASE_IDX                                 5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW                             0x1026d
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW_BASE_IDX                    5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE                              0x1026e
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE_BASE_IDX                     5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS                              0x1026f
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS_BASE_IDX                     5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL                            0x10270
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL_BASE_IDX                   5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0                            0x10271
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0_BASE_IDX                   5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1                            0x10272
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1_BASE_IDX                   5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2                            0x10273
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2_BASE_IDX                   5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB                                 0x10275
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION                                   0x10277
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION_BASE_IDX                          5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE                     0x10278
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE_BASE_IDX            5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS0                                 0x10281
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS0_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1                                 0x10282
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2                                 0x10283
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3                                 0x10284
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4                                 0x10285
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW0                                 0x10287
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW0_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW1                                 0x10288
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW1_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW2                                 0x10289
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW2_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW3                                 0x1028a
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW3_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW4                                 0x1028b
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW4_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW5                                 0x1028c
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW5_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW6                                 0x1028d
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW6_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW7                                 0x1028e
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW7_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW8                                 0x1028f
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW8_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW0                                 0x10293
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW0_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW1                                 0x10294
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW1_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW2                                 0x10295
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW2_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW3                                 0x10296
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW3_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW4                                 0x10297
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW4_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW5                                 0x10298
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW5_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW6                                 0x10299
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW6_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW7                                 0x1029a
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW7_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW8                                 0x1029b
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW8_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW0                                 0x1029f
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW0_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW1                                 0x102a0
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW1_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW2                                 0x102a1
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW2_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW3                                 0x102a2
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW3_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW4                                 0x102a3
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW4_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW5                                 0x102a4
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW5_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW6                                 0x102a5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW6_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW7                                 0x102a6
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW7_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW8                                 0x102a7
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW8_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW0                                 0x102ab
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW0_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW1                                 0x102ac
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW1_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW2                                 0x102ad
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW2_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW3                                 0x102ae
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW3_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW4                                 0x102af
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW4_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW5                                 0x102b0
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW5_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW6                                 0x102b1
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW6_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW7                                 0x102b2
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW7_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW8                                 0x102b3
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW8_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW0                                 0x102b7
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW0_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW1                                 0x102b8
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW1_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW2                                 0x102b9
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW2_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW3                                 0x102ba
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW3_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW4                                 0x102bb
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW4_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW5                                 0x102bc
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW5_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW6                                 0x102bd
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW6_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW7                                 0x102be
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW7_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW8                                 0x102bf
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW8_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW0                                 0x102c3
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW0_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW1                                 0x102c4
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW1_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW2                                 0x102c5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW2_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW3                                 0x102c6
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW3_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW4                                 0x102c7
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW4_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW5                                 0x102c8
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW5_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW6                                 0x102c9
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW6_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW7                                 0x102ca
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW7_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW8                                 0x102cb
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW8_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW0                                 0x102cf
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW0_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW1                                 0x102d0
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW1_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW2                                 0x102d1
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW2_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW3                                 0x102d2
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW3_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW4                                 0x102d3
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW4_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW5                                 0x102d4
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW5_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW6                                 0x102d5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW6_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW7                                 0x102d6
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW7_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW8                                 0x102d7
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW8_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW0                                 0x102db
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW0_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW1                                 0x102dc
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW1_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW2                                 0x102dd
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW2_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW3                                 0x102de
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW3_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW4                                 0x102df
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW4_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW5                                 0x102e0
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW5_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW6                                 0x102e1
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW6_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW7                                 0x102e2
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW7_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW8                                 0x102e3
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW8_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW0                                 0x102e7
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW0_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW1                                 0x102e8
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW1_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW2                                 0x102e9
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW2_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW3                                 0x102ea
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW3_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW4                                 0x102eb
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW4_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW5                                 0x102ec
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW5_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW6                                 0x102ed
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW6_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW7                                 0x102ee
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW7_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW8                                 0x102ef
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW8_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW0                                 0x102f3
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW0_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW1                                 0x102f4
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW1_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW2                                 0x102f5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW2_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW3                                 0x102f6
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW3_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW4                                 0x102f7
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW4_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW5                                 0x102f8
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW5_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW6                                 0x102f9
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW6_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW7                                 0x102fa
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW7_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW8                                 0x102fb
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW8_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW0                                0x102ff
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW0_BASE_IDX                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW1                                0x10300
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW1_BASE_IDX                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW2                                0x10301
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW2_BASE_IDX                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW3                                0x10302
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW3_BASE_IDX                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW4                                0x10303
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW4_BASE_IDX                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW5                                0x10304
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW5_BASE_IDX                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW6                                0x10305
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW6_BASE_IDX                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW7                                0x10306
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW7_BASE_IDX                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW8                                0x10307
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW8_BASE_IDX                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW0                                0x1030b
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW0_BASE_IDX                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW1                                0x1030c
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW1_BASE_IDX                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW2                                0x1030d
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW2_BASE_IDX                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW3                                0x1030e
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW3_BASE_IDX                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW4                                0x1030f
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW4_BASE_IDX                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW5                                0x10310
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW5_BASE_IDX                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW6                                0x10311
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW6_BASE_IDX                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW7                                0x10312
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW7_BASE_IDX                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW8                                0x10313
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW8_BASE_IDX                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW0                                0x10317
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW0_BASE_IDX                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW1                                0x10318
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW1_BASE_IDX                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW2                                0x10319
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW2_BASE_IDX                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW3                                0x1031a
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW3_BASE_IDX                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW4                                0x1031b
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW4_BASE_IDX                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW5                                0x1031c
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW5_BASE_IDX                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW6                                0x1031d
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW6_BASE_IDX                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW7                                0x1031e
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW7_BASE_IDX                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW8                                0x1031f
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW8_BASE_IDX                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW0                                0x10323
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW0_BASE_IDX                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW1                                0x10324
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW1_BASE_IDX                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW2                                0x10325
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW2_BASE_IDX                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW3                                0x10326
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW3_BASE_IDX                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW4                                0x10327
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW4_BASE_IDX                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW5                                0x10328
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW5_BASE_IDX                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW6                                0x10329
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW6_BASE_IDX                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW7                                0x1032a
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW7_BASE_IDX                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW8                                0x1032b
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW8_BASE_IDX                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW0                                0x1032f
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW0_BASE_IDX                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW1                                0x10330
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW1_BASE_IDX                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW2                                0x10331
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW2_BASE_IDX                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW3                                0x10332
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW3_BASE_IDX                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW4                                0x10333
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW4_BASE_IDX                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW5                                0x10334
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW5_BASE_IDX                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW6                                0x10335
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW6_BASE_IDX                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW7                                0x10336
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW7_BASE_IDX                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW8                                0x10337
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW8_BASE_IDX                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW0                                0x1033b
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW0_BASE_IDX                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW1                                0x1033c
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW1_BASE_IDX                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW2                                0x1033d
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW2_BASE_IDX                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW3                                0x1033e
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW3_BASE_IDX                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW4                                0x1033f
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW4_BASE_IDX                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW5                                0x10340
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW5_BASE_IDX                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW6                                0x10341
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW6_BASE_IDX                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW7                                0x10342
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW7_BASE_IDX                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW8                                0x10343
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW8_BASE_IDX                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW0                                0x10347
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW0_BASE_IDX                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW1                                0x10348
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW1_BASE_IDX                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW2                                0x10349
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW2_BASE_IDX                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW3                                0x1034a
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW3_BASE_IDX                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW4                                0x1034b
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW4_BASE_IDX                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW5                                0x1034c
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW5_BASE_IDX                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW6                                0x1034d
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW6_BASE_IDX                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW7                                0x1034e
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW7_BASE_IDX                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW8                                0x1034f
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW8_BASE_IDX                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW0                                0x10353
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW0_BASE_IDX                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW1                                0x10354
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW1_BASE_IDX                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW2                                0x10355
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW2_BASE_IDX                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW3                                0x10356
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW3_BASE_IDX                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW4                                0x10357
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW4_BASE_IDX                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW5                                0x10358
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW5_BASE_IDX                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW6                                0x10359
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW6_BASE_IDX                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW7                                0x1035a
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW7_BASE_IDX                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW8                                0x1035b
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW8_BASE_IDX                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW0                                0x1035f
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW0_BASE_IDX                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW1                                0x10360
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW1_BASE_IDX                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW2                                0x10361
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW2_BASE_IDX                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW3                                0x10362
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW3_BASE_IDX                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW4                                0x10363
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW4_BASE_IDX                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW5                                0x10364
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW5_BASE_IDX                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW6                                0x10365
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW6_BASE_IDX                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW7                                0x10366
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW7_BASE_IDX                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW8                                0x10367
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW8_BASE_IDX                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW0                                0x1036b
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW0_BASE_IDX                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW1                                0x1036c
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW1_BASE_IDX                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW2                                0x1036d
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW2_BASE_IDX                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW3                                0x1036e
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW3_BASE_IDX                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW4                                0x1036f
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW4_BASE_IDX                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW5                                0x10370
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW5_BASE_IDX                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW6                                0x10371
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW6_BASE_IDX                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW7                                0x10372
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW7_BASE_IDX                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW8                                0x10373
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW8_BASE_IDX                       5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE                      0x10377
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE_BASE_IDX             5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE                     0x10378
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE_BASE_IDX            5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE                    0x10379
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE_BASE_IDX           5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE                    0x1037a
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE_BASE_IDX           5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS                      0x1037b
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS_BASE_IDX             5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS                     0x1037c
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS_BASE_IDX            5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS                    0x1037d
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS_BASE_IDX           5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS                    0x1037e
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS_BASE_IDX           5
+
+
+// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_bifcfgpciedecp
+// base address: 0x10140000
+#define regBIF_CFG_DEV0_EPF0_0_LINK_CAP                                                                 0x1001c
+#define regBIF_CFG_DEV0_EPF0_0_LINK_CAP_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_EPF0_0_LINK_CNTL                                                                0x1001d
+#define regBIF_CFG_DEV0_EPF0_0_LINK_CNTL_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF0_0_LINK_STATUS                                                              0x1001d
+#define regBIF_CFG_DEV0_EPF0_0_LINK_STATUS_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_0_LINK_CAP2                                                                0x10024
+#define regBIF_CFG_DEV0_EPF0_0_LINK_CAP2_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF0_0_LINK_CNTL2                                                               0x10025
+#define regBIF_CFG_DEV0_EPF0_0_LINK_CNTL2_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF0_0_LINK_STATUS2                                                             0x10025
+#define regBIF_CFG_DEV0_EPF0_0_LINK_STATUS2_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                        0x10040
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX                               5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR                                                 0x10041
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1                                                    0x10042
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2                                                    0x10043
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST                                              0x10044
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3                                                          0x10045
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS                                                   0x10046
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL                                            0x10047
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL                                            0x10047
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL                                            0x10048
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL                                            0x10048
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL                                            0x10049
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL                                            0x10049
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL                                            0x1004a
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL                                            0x1004a
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL                                            0x1004b
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL                                            0x1004b
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL                                           0x1004c
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL_BASE_IDX                                  5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL                                           0x1004c
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL_BASE_IDX                                  5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL                                           0x1004d
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL_BASE_IDX                                  5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL                                           0x1004d
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL_BASE_IDX                                  5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL                                           0x1004e
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL_BASE_IDX                                  5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL                                           0x1004e
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL_BASE_IDX                                  5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST                                               0x1006e
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF0_0_LINK_CAP_16GT                                                            0x1006f
+#define regBIF_CFG_DEV0_EPF0_0_LINK_CAP_16GT_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_0_LINK_CNTL_16GT                                                           0x10070
+#define regBIF_CFG_DEV0_EPF0_0_LINK_CNTL_16GT_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT                                                         0x10071
+#define regBIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT                                        0x10072
+#define regBIF_CFG_DEV0_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT_BASE_IDX                               5
+#define regBIF_CFG_DEV0_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT                                         0x10073
+#define regBIF_CFG_DEV0_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT_BASE_IDX                                5
+#define regBIF_CFG_DEV0_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT                                         0x10074
+#define regBIF_CFG_DEV0_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT_BASE_IDX                                5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT                                            0x10076
+#define regBIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT                                            0x10076
+#define regBIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT                                            0x10076
+#define regBIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT                                            0x10076
+#define regBIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT                                            0x10077
+#define regBIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT                                            0x10077
+#define regBIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT                                            0x10077
+#define regBIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT                                            0x10077
+#define regBIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT                                            0x10078
+#define regBIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT                                            0x10078
+#define regBIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT                                           0x10078
+#define regBIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT_BASE_IDX                                  5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT                                           0x10078
+#define regBIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT_BASE_IDX                                  5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT                                           0x10079
+#define regBIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT_BASE_IDX                                  5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT                                           0x10079
+#define regBIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT_BASE_IDX                                  5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT                                           0x10079
+#define regBIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT_BASE_IDX                                  5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT                                           0x10079
+#define regBIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT_BASE_IDX                                  5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_PHY_32GT_ENH_CAP_LIST                                               0x1007e
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_PHY_32GT_ENH_CAP_LIST_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT                                                            0x1007f
+#define regBIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_0_LINK_CNTL_32GT                                                           0x10080
+#define regBIF_CFG_DEV0_EPF0_0_LINK_CNTL_32GT_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT                                                         0x10081
+#define regBIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF0_0_RECEIVED_MODIFIED_TS_DATA1                                               0x10082
+#define regBIF_CFG_DEV0_EPF0_0_RECEIVED_MODIFIED_TS_DATA1_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF0_0_RECEIVED_MODIFIED_TS_DATA2                                               0x10083
+#define regBIF_CFG_DEV0_EPF0_0_RECEIVED_MODIFIED_TS_DATA2_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF0_0_TRANSMITTED_MODIFIED_TS_DATA1                                            0x10084
+#define regBIF_CFG_DEV0_EPF0_0_TRANSMITTED_MODIFIED_TS_DATA1_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_TRANSMITTED_MODIFIED_TS_DATA2                                            0x10085
+#define regBIF_CFG_DEV0_EPF0_0_TRANSMITTED_MODIFIED_TS_DATA2_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_32GT                                            0x10086
+#define regBIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_32GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_32GT                                            0x10086
+#define regBIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_32GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_32GT                                            0x10086
+#define regBIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_32GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_32GT                                            0x10086
+#define regBIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_32GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_32GT                                            0x10087
+#define regBIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_32GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_32GT                                            0x10087
+#define regBIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_32GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_32GT                                            0x10087
+#define regBIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_32GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_32GT                                            0x10087
+#define regBIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_32GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_32GT                                            0x10088
+#define regBIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_32GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_32GT                                            0x10088
+#define regBIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_32GT_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_32GT                                           0x10088
+#define regBIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_32GT_BASE_IDX                                  5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_32GT                                           0x10088
+#define regBIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_32GT_BASE_IDX                                  5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_32GT                                           0x10089
+#define regBIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_32GT_BASE_IDX                                  5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_32GT                                           0x10089
+#define regBIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_32GT_BASE_IDX                                  5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_32GT                                           0x10089
+#define regBIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_32GT_BASE_IDX                                  5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_32GT                                           0x10089
+#define regBIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_32GT_BASE_IDX                                  5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_AP_ENH_CAP_LIST                                                     0x1008e
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_AP_ENH_CAP_LIST_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF0_0_AP_CAP                                                                   0x1008f
+#define regBIF_CFG_DEV0_EPF0_0_AP_CAP_BASE_IDX                                                          5
+#define regBIF_CFG_DEV0_EPF0_0_AP_CNTL                                                                  0x10090
+#define regBIF_CFG_DEV0_EPF0_0_AP_CNTL_BASE_IDX                                                         5
+#define regBIF_CFG_DEV0_EPF0_0_AP_DATA1                                                                 0x10091
+#define regBIF_CFG_DEV0_EPF0_0_AP_DATA1_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_EPF0_0_AP_DATA2                                                                 0x10092
+#define regBIF_CFG_DEV0_EPF0_0_AP_DATA2_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_EPF0_0_AP_SEL_EN_MASK                                                           0x10093
+#define regBIF_CFG_DEV0_EPF0_0_AP_SEL_EN_MASK_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST                                              0x10094
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_EPF0_0_MARGINING_PORT_CAP                                                       0x10095
+#define regBIF_CFG_DEV0_EPF0_0_MARGINING_PORT_CAP_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS                                                    0x10095
+#define regBIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL                                               0x10096
+#define regBIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS                                             0x10096
+#define regBIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS_BASE_IDX                                    5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL                                               0x10097
+#define regBIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS                                             0x10097
+#define regBIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS_BASE_IDX                                    5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL                                               0x10098
+#define regBIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS                                             0x10098
+#define regBIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS_BASE_IDX                                    5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL                                               0x10099
+#define regBIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS                                             0x10099
+#define regBIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS_BASE_IDX                                    5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL                                               0x1009a
+#define regBIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS                                             0x1009a
+#define regBIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS_BASE_IDX                                    5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL                                               0x1009b
+#define regBIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS                                             0x1009b
+#define regBIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS_BASE_IDX                                    5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL                                               0x1009c
+#define regBIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS                                             0x1009c
+#define regBIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS_BASE_IDX                                    5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL                                               0x1009d
+#define regBIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS                                             0x1009d
+#define regBIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS_BASE_IDX                                    5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL                                               0x1009e
+#define regBIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS                                             0x1009e
+#define regBIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS_BASE_IDX                                    5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL                                               0x1009f
+#define regBIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS                                             0x1009f
+#define regBIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS_BASE_IDX                                    5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL                                              0x100a0
+#define regBIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS                                            0x100a0
+#define regBIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL                                              0x100a1
+#define regBIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS                                            0x100a1
+#define regBIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL                                              0x100a2
+#define regBIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS                                            0x100a2
+#define regBIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL                                              0x100a3
+#define regBIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS                                            0x100a3
+#define regBIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL                                              0x100a4
+#define regBIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS                                            0x100a4
+#define regBIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL                                              0x100a5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS                                            0x100a5
+#define regBIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_NULL1_ENH_CAP_LIST                                                  0x10100
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_NULL1_ENH_CAP_LIST_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST                                                     0x10101
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1                                                    0x10102
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2                                                    0x10103
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL                                                        0x10104
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL_BASE_IDX                                               5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS                                                      0x10104
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP                                                    0x10105
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL                                                   0x10106
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS                                                 0x10107
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP                                                    0x10108
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL                                                   0x10109
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS                                                 0x1010a
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST                                                    0x1010c
+#define regBIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP                                                    0x1010d
+#define regBIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS                                                 0x1010e
+#define regBIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF0_0_IDE_ENH_CAP_LIST                                                         0x10380
+#define regBIF_CFG_DEV0_EPF0_0_IDE_ENH_CAP_LIST_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF0_0_IDE_CAP                                                                  0x10381
+#define regBIF_CFG_DEV0_EPF0_0_IDE_CAP_BASE_IDX                                                         5
+#define regBIF_CFG_DEV0_EPF0_0_IDE_CNTL                                                                 0x10382
+#define regBIF_CFG_DEV0_EPF0_0_IDE_CNTL_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_EPF0_0_LINK_IDE_STREAM_0_CNTL                                                   0x10383
+#define regBIF_CFG_DEV0_EPF0_0_LINK_IDE_STREAM_0_CNTL_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF0_0_LINK_IDE_STREAM_0_STATUS                                                 0x10384
+#define regBIF_CFG_DEV0_EPF0_0_LINK_IDE_STREAM_0_STATUS_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CAP                                               0x10385
+#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CAP_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CNTL                                              0x10386
+#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_STATUS                                            0x10387
+#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_STATUS_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_IDE_0_RID_ASSOCIATION_REG1                                               0x10388
+#define regBIF_CFG_DEV0_EPF0_0_IDE_0_RID_ASSOCIATION_REG1_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF0_0_IDE_0_RID_ASSOCIATION_REG2                                               0x10389
+#define regBIF_CFG_DEV0_EPF0_0_IDE_0_RID_ASSOCIATION_REG2_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_0_REG1                                            0x1038a
+#define regBIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_0_REG1_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_0_REG2                                            0x1038b
+#define regBIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_0_REG2_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_0_REG3                                            0x1038c
+#define regBIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_0_REG3_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_1_REG1                                            0x1038d
+#define regBIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_1_REG1_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_1_REG2                                            0x1038e
+#define regBIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_1_REG2_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_1_REG3                                            0x1038f
+#define regBIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_1_REG3_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CAP                                               0x10390
+#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CAP_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CNTL                                              0x10391
+#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_STATUS                                            0x10392
+#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_STATUS_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_IDE_1_RID_ASSOCIATION_REG1                                               0x10393
+#define regBIF_CFG_DEV0_EPF0_0_IDE_1_RID_ASSOCIATION_REG1_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF0_0_IDE_1_RID_ASSOCIATION_REG2                                               0x10394
+#define regBIF_CFG_DEV0_EPF0_0_IDE_1_RID_ASSOCIATION_REG2_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_0_REG1                                            0x10395
+#define regBIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_0_REG1_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_0_REG2                                            0x10396
+#define regBIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_0_REG2_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_0_REG3                                            0x10397
+#define regBIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_0_REG3_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_1_REG1                                            0x10398
+#define regBIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_1_REG1_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_1_REG2                                            0x10399
+#define regBIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_1_REG2_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_1_REG3                                            0x1039a
+#define regBIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_1_REG3_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CAP                                               0x1039b
+#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CAP_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CNTL                                              0x1039c
+#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_STATUS                                            0x1039d
+#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_STATUS_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_IDE_2_RID_ASSOCIATION_REG1                                               0x1039e
+#define regBIF_CFG_DEV0_EPF0_0_IDE_2_RID_ASSOCIATION_REG1_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF0_0_IDE_2_RID_ASSOCIATION_REG2                                               0x1039f
+#define regBIF_CFG_DEV0_EPF0_0_IDE_2_RID_ASSOCIATION_REG2_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_0_REG1                                            0x103a0
+#define regBIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_0_REG1_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_0_REG2                                            0x103a1
+#define regBIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_0_REG2_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_0_REG3                                            0x103a2
+#define regBIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_0_REG3_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_1_REG1                                            0x103a3
+#define regBIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_1_REG1_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_1_REG2                                            0x103a4
+#define regBIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_1_REG2_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_1_REG3                                            0x103a5
+#define regBIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_1_REG3_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CAP                                               0x103a6
+#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CAP_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CNTL                                              0x103a7
+#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_STATUS                                            0x103a8
+#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_STATUS_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_IDE_3_RID_ASSOCIATION_REG1                                               0x103a9
+#define regBIF_CFG_DEV0_EPF0_0_IDE_3_RID_ASSOCIATION_REG1_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF0_0_IDE_3_RID_ASSOCIATION_REG2                                               0x103aa
+#define regBIF_CFG_DEV0_EPF0_0_IDE_3_RID_ASSOCIATION_REG2_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_0_REG1                                            0x103ab
+#define regBIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_0_REG1_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_0_REG2                                            0x103ac
+#define regBIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_0_REG2_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_0_REG3                                            0x103ad
+#define regBIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_0_REG3_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_1_REG1                                            0x103ae
+#define regBIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_1_REG1_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_1_REG2                                            0x103af
+#define regBIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_1_REG2_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_1_REG3                                            0x103b0
+#define regBIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_1_REG3_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CAP                                               0x103b1
+#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CAP_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CNTL                                              0x103b2
+#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_STATUS                                            0x103b3
+#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_STATUS_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_IDE_4_RID_ASSOCIATION_REG1                                               0x103b4
+#define regBIF_CFG_DEV0_EPF0_0_IDE_4_RID_ASSOCIATION_REG1_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF0_0_IDE_4_RID_ASSOCIATION_REG2                                               0x103b5
+#define regBIF_CFG_DEV0_EPF0_0_IDE_4_RID_ASSOCIATION_REG2_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_0_REG1                                            0x103b6
+#define regBIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_0_REG1_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_0_REG2                                            0x103b7
+#define regBIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_0_REG2_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_0_REG3                                            0x103b8
+#define regBIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_0_REG3_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_1_REG1                                            0x103b9
+#define regBIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_1_REG1_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_1_REG2                                            0x103ba
+#define regBIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_1_REG2_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_1_REG3                                            0x103bb
+#define regBIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_1_REG3_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CAP                                               0x103bc
+#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CAP_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CNTL                                              0x103bd
+#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_STATUS                                            0x103be
+#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_STATUS_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_IDE_5_RID_ASSOCIATION_REG1                                               0x103bf
+#define regBIF_CFG_DEV0_EPF0_0_IDE_5_RID_ASSOCIATION_REG1_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF0_0_IDE_5_RID_ASSOCIATION_REG2                                               0x103c0
+#define regBIF_CFG_DEV0_EPF0_0_IDE_5_RID_ASSOCIATION_REG2_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_0_REG1                                            0x103c1
+#define regBIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_0_REG1_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_0_REG2                                            0x103c2
+#define regBIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_0_REG2_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_0_REG3                                            0x103c3
+#define regBIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_0_REG3_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_1_REG1                                            0x103c4
+#define regBIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_1_REG1_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_1_REG2                                            0x103c5
+#define regBIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_1_REG2_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_1_REG3                                            0x103c6
+#define regBIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_1_REG3_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CAP                                               0x103c7
+#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CAP_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CNTL                                              0x103c8
+#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_STATUS                                            0x103c9
+#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_STATUS_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_IDE_6_RID_ASSOCIATION_REG1                                               0x103ca
+#define regBIF_CFG_DEV0_EPF0_0_IDE_6_RID_ASSOCIATION_REG1_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF0_0_IDE_6_RID_ASSOCIATION_REG2                                               0x103cb
+#define regBIF_CFG_DEV0_EPF0_0_IDE_6_RID_ASSOCIATION_REG2_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_0_REG1                                            0x103cc
+#define regBIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_0_REG1_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_0_REG2                                            0x103cd
+#define regBIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_0_REG2_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_0_REG3                                            0x103ce
+#define regBIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_0_REG3_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_1_REG1                                            0x103cf
+#define regBIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_1_REG1_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_1_REG2                                            0x103d0
+#define regBIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_1_REG2_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_1_REG3                                            0x103d1
+#define regBIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_1_REG3_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CAP                                               0x103d2
+#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CAP_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CNTL                                              0x103d3
+#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_STATUS                                            0x103d4
+#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_STATUS_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_IDE_7_RID_ASSOCIATION_REG1                                               0x103d5
+#define regBIF_CFG_DEV0_EPF0_0_IDE_7_RID_ASSOCIATION_REG1_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF0_0_IDE_7_RID_ASSOCIATION_REG2                                               0x103d6
+#define regBIF_CFG_DEV0_EPF0_0_IDE_7_RID_ASSOCIATION_REG2_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_0_REG1                                            0x103d7
+#define regBIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_0_REG1_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_0_REG2                                            0x103d8
+#define regBIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_0_REG2_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_0_REG3                                            0x103d9
+#define regBIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_0_REG3_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_1_REG1                                            0x103da
+#define regBIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_1_REG1_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_1_REG2                                            0x103db
+#define regBIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_1_REG2_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_1_REG3                                            0x103dc
+#define regBIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_1_REG3_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CAP                                               0x103dd
+#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CAP_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CNTL                                              0x103de
+#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CNTL_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_STATUS                                            0x103df
+#define regBIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_STATUS_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_IDE_8_RID_ASSOCIATION_REG1                                               0x103e0
+#define regBIF_CFG_DEV0_EPF0_0_IDE_8_RID_ASSOCIATION_REG1_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF0_0_IDE_8_RID_ASSOCIATION_REG2                                               0x103e1
+#define regBIF_CFG_DEV0_EPF0_0_IDE_8_RID_ASSOCIATION_REG2_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_0_REG1                                            0x103e2
+#define regBIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_0_REG1_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_0_REG2                                            0x103e3
+#define regBIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_0_REG2_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_0_REG3                                            0x103e4
+#define regBIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_0_REG3_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_1_REG1                                            0x103e5
+#define regBIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_1_REG1_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_1_REG2                                            0x103e6
+#define regBIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_1_REG2_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_1_REG3                                            0x103e7
+#define regBIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_1_REG3_BASE_IDX                                   5
+
+
+// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_vf0_bifcfgdecp
+// base address: 0x10140000
+#define regBIF_CFG_DEV0_EPF0_VF0_VENDOR_ID                                                              0x10000
+#define regBIF_CFG_DEV0_EPF0_VF0_VENDOR_ID_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_ID                                                              0x10000
+#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_ID_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_VF0_COMMAND                                                                0x10001
+#define regBIF_CFG_DEV0_EPF0_VF0_COMMAND_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF0_VF0_STATUS                                                                 0x10001
+#define regBIF_CFG_DEV0_EPF0_VF0_STATUS_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_EPF0_VF0_REVISION_ID                                                            0x10002
+#define regBIF_CFG_DEV0_EPF0_VF0_REVISION_ID_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF0_PROG_INTERFACE                                                         0x10002
+#define regBIF_CFG_DEV0_EPF0_VF0_PROG_INTERFACE_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF0_VF0_SUB_CLASS                                                              0x10002
+#define regBIF_CFG_DEV0_EPF0_VF0_SUB_CLASS_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_VF0_BASE_CLASS                                                             0x10002
+#define regBIF_CFG_DEV0_EPF0_VF0_BASE_CLASS_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF0_VF0_CACHE_LINE                                                             0x10003
+#define regBIF_CFG_DEV0_EPF0_VF0_CACHE_LINE_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF0_VF0_LATENCY                                                                0x10003
+#define regBIF_CFG_DEV0_EPF0_VF0_LATENCY_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF0_VF0_HEADER                                                                 0x10003
+#define regBIF_CFG_DEV0_EPF0_VF0_HEADER_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_EPF0_VF0_BIST                                                                   0x10003
+#define regBIF_CFG_DEV0_EPF0_VF0_BIST_BASE_IDX                                                          5
+#define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_1                                                            0x10004
+#define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_1_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_2                                                            0x10005
+#define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_2_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_3                                                            0x10006
+#define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_3_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_4                                                            0x10007
+#define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_4_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_5                                                            0x10008
+#define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_5_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_6                                                            0x10009
+#define regBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_6_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF0_CARDBUS_CIS_PTR                                                        0x1000a
+#define regBIF_CFG_DEV0_EPF0_VF0_CARDBUS_CIS_PTR_BASE_IDX                                               5
+#define regBIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID                                                             0x1000b
+#define regBIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR                                                          0x1000c
+#define regBIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF0_CAP_PTR                                                                0x1000d
+#define regBIF_CFG_DEV0_EPF0_VF0_CAP_PTR_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF0_VF0_INTERRUPT_LINE                                                         0x1000f
+#define regBIF_CFG_DEV0_EPF0_VF0_INTERRUPT_LINE_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF0_VF0_INTERRUPT_PIN                                                          0x1000f
+#define regBIF_CFG_DEV0_EPF0_VF0_INTERRUPT_PIN_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF0_MIN_GRANT                                                              0x1000f
+#define regBIF_CFG_DEV0_EPF0_VF0_MIN_GRANT_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_VF0_MAX_LATENCY                                                            0x1000f
+#define regBIF_CFG_DEV0_EPF0_VF0_MAX_LATENCY_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST                                                          0x10019
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_CAP                                                               0x10019
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP                                                             0x1001a
+#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL                                                            0x1001b
+#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS                                                          0x1001b
+#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF0_LINK_CAP                                                               0x1001c
+#define regBIF_CFG_DEV0_EPF0_VF0_LINK_CAP_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF0_VF0_LINK_CNTL                                                              0x1001d
+#define regBIF_CFG_DEV0_EPF0_VF0_LINK_CNTL_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_VF0_LINK_STATUS                                                            0x1001d
+#define regBIF_CFG_DEV0_EPF0_VF0_LINK_STATUS_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2                                                            0x10022
+#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2                                                           0x10023
+#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS2                                                         0x10023
+#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS2_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF0_VF0_LINK_CAP2                                                              0x10024
+#define regBIF_CFG_DEV0_EPF0_VF0_LINK_CAP2_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2                                                             0x10025
+#define regBIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2                                                           0x10025
+#define regBIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST                                                           0x10028
+#define regBIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL                                                           0x10028
+#define regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_LO                                                        0x10029
+#define regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_LO_BASE_IDX                                               5
+#define regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_HI                                                        0x1002a
+#define regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_HI_BASE_IDX                                               5
+#define regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA                                                           0x1002a
+#define regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA                                                       0x1002a
+#define regBIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_EPF0_VF0_MSI_MASK                                                               0x1002b
+#define regBIF_CFG_DEV0_EPF0_VF0_MSI_MASK_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA_64                                                        0x1002b
+#define regBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA_64_BASE_IDX                                               5
+#define regBIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA_64                                                    0x1002b
+#define regBIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA_64_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF0_VF0_MSI_MASK_64                                                            0x1002c
+#define regBIF_CFG_DEV0_EPF0_VF0_MSI_MASK_64_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF0_MSI_PENDING                                                            0x1002c
+#define regBIF_CFG_DEV0_EPF0_VF0_MSI_PENDING_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF0_MSI_PENDING_64                                                         0x1002d
+#define regBIF_CFG_DEV0_EPF0_VF0_MSI_PENDING_64_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST                                                          0x10030
+#define regBIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL                                                          0x10030
+#define regBIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE                                                             0x10031
+#define regBIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF0_VF0_MSIX_PBA                                                               0x10032
+#define regBIF_CFG_DEV0_EPF0_VF0_MSIX_PBA_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                      0x10040
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX                             5
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR                                               0x10041
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC1                                                  0x10042
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC1_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC2                                                  0x10043
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC2_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_DEVICE3_ENH_CAP_LIST                                              0x100b6
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_DEVICE3_ENH_CAP_LIST_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP3                                                            0x100b7
+#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP3_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL3                                                           0x100b8
+#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL3_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS3                                                         0x100b9
+#define regBIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS3_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_NULL1_ENH_CAP_LIST                                                0x10100
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_NULL1_ENH_CAP_LIST_BASE_IDX                                       5
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_NULL2_ENH_CAP_LIST                                                0x10180
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_NULL2_ENH_CAP_LIST_BASE_IDX                                       5
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                          0x10181
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX                                 5
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS                                                 0x10182
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK                                                   0x10183
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY                                               0x10184
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS                                                   0x10185
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK                                                     0x10186
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL                                                  0x10187
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG0                                                          0x10188
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG0_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG1                                                          0x10189
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG1_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG2                                                          0x1018a
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG2_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG3                                                          0x1018b
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG3_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG4                                                          0x1018f
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG4_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG0                                                   0x1018f
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG0_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG5                                                          0x10190
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG5_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG1                                                   0x10190
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG1_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG6                                                          0x10191
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG6_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG2                                                   0x10191
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG2_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG7                                                          0x10192
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG7_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG3                                                   0x10192
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG3_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG8                                                          0x10193
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG8_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG9                                                          0x10194
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG9_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG10                                                         0x10195
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG10_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG11                                                         0x10196
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG11_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG12                                                         0x10197
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG12_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG13                                                         0x10198
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG13_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_RTR_ENH_CAP_LIST                                                  0x101c7
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_RTR_ENH_CAP_LIST_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF0_VF0_RTR_DATA1                                                              0x101c8
+#define regBIF_CFG_DEV0_EPF0_VF0_RTR_DATA1_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_VF0_RTR_DATA2                                                              0x101c9
+#define regBIF_CFG_DEV0_EPF0_VF0_RTR_DATA2_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST                                                  0x101dc
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP                                                           0x101dd
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL                                                          0x101dd
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_ENH_CAP_LIST                                                  0x101eb
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_ENH_CAP_LIST_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP                                                           0x101ec
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CNTL                                                          0x101ec
+#define regBIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CNTL_BASE_IDX                                                 5
+
+
+// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_vf1_bifcfgdecp
+// base address: 0x10140000
+#define regBIF_CFG_DEV0_EPF0_VF1_VENDOR_ID                                                              0x10000
+#define regBIF_CFG_DEV0_EPF0_VF1_VENDOR_ID_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_ID                                                              0x10000
+#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_ID_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_VF1_COMMAND                                                                0x10001
+#define regBIF_CFG_DEV0_EPF0_VF1_COMMAND_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF0_VF1_STATUS                                                                 0x10001
+#define regBIF_CFG_DEV0_EPF0_VF1_STATUS_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_EPF0_VF1_REVISION_ID                                                            0x10002
+#define regBIF_CFG_DEV0_EPF0_VF1_REVISION_ID_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF1_PROG_INTERFACE                                                         0x10002
+#define regBIF_CFG_DEV0_EPF0_VF1_PROG_INTERFACE_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF0_VF1_SUB_CLASS                                                              0x10002
+#define regBIF_CFG_DEV0_EPF0_VF1_SUB_CLASS_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_VF1_BASE_CLASS                                                             0x10002
+#define regBIF_CFG_DEV0_EPF0_VF1_BASE_CLASS_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF0_VF1_CACHE_LINE                                                             0x10003
+#define regBIF_CFG_DEV0_EPF0_VF1_CACHE_LINE_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF0_VF1_LATENCY                                                                0x10003
+#define regBIF_CFG_DEV0_EPF0_VF1_LATENCY_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF0_VF1_HEADER                                                                 0x10003
+#define regBIF_CFG_DEV0_EPF0_VF1_HEADER_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_EPF0_VF1_BIST                                                                   0x10003
+#define regBIF_CFG_DEV0_EPF0_VF1_BIST_BASE_IDX                                                          5
+#define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_1                                                            0x10004
+#define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_1_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_2                                                            0x10005
+#define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_2_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_3                                                            0x10006
+#define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_3_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_4                                                            0x10007
+#define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_4_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_5                                                            0x10008
+#define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_5_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_6                                                            0x10009
+#define regBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_6_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF1_CARDBUS_CIS_PTR                                                        0x1000a
+#define regBIF_CFG_DEV0_EPF0_VF1_CARDBUS_CIS_PTR_BASE_IDX                                               5
+#define regBIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID                                                             0x1000b
+#define regBIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR                                                          0x1000c
+#define regBIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF1_CAP_PTR                                                                0x1000d
+#define regBIF_CFG_DEV0_EPF0_VF1_CAP_PTR_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF0_VF1_INTERRUPT_LINE                                                         0x1000f
+#define regBIF_CFG_DEV0_EPF0_VF1_INTERRUPT_LINE_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF0_VF1_INTERRUPT_PIN                                                          0x1000f
+#define regBIF_CFG_DEV0_EPF0_VF1_INTERRUPT_PIN_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF1_MIN_GRANT                                                              0x1000f
+#define regBIF_CFG_DEV0_EPF0_VF1_MIN_GRANT_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_VF1_MAX_LATENCY                                                            0x1000f
+#define regBIF_CFG_DEV0_EPF0_VF1_MAX_LATENCY_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST                                                          0x10019
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_CAP                                                               0x10019
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP                                                             0x1001a
+#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL                                                            0x1001b
+#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS                                                          0x1001b
+#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF1_LINK_CAP                                                               0x1001c
+#define regBIF_CFG_DEV0_EPF0_VF1_LINK_CAP_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF0_VF1_LINK_CNTL                                                              0x1001d
+#define regBIF_CFG_DEV0_EPF0_VF1_LINK_CNTL_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_VF1_LINK_STATUS                                                            0x1001d
+#define regBIF_CFG_DEV0_EPF0_VF1_LINK_STATUS_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2                                                            0x10022
+#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2                                                           0x10023
+#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS2                                                         0x10023
+#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS2_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF0_VF1_LINK_CAP2                                                              0x10024
+#define regBIF_CFG_DEV0_EPF0_VF1_LINK_CAP2_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2                                                             0x10025
+#define regBIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2                                                           0x10025
+#define regBIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST                                                           0x10028
+#define regBIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL                                                           0x10028
+#define regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_LO                                                        0x10029
+#define regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_LO_BASE_IDX                                               5
+#define regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_HI                                                        0x1002a
+#define regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_HI_BASE_IDX                                               5
+#define regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA                                                           0x1002a
+#define regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA                                                       0x1002a
+#define regBIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_EPF0_VF1_MSI_MASK                                                               0x1002b
+#define regBIF_CFG_DEV0_EPF0_VF1_MSI_MASK_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA_64                                                        0x1002b
+#define regBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA_64_BASE_IDX                                               5
+#define regBIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA_64                                                    0x1002b
+#define regBIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA_64_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF0_VF1_MSI_MASK_64                                                            0x1002c
+#define regBIF_CFG_DEV0_EPF0_VF1_MSI_MASK_64_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF1_MSI_PENDING                                                            0x1002c
+#define regBIF_CFG_DEV0_EPF0_VF1_MSI_PENDING_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF1_MSI_PENDING_64                                                         0x1002d
+#define regBIF_CFG_DEV0_EPF0_VF1_MSI_PENDING_64_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST                                                          0x10030
+#define regBIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL                                                          0x10030
+#define regBIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE                                                             0x10031
+#define regBIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF0_VF1_MSIX_PBA                                                               0x10032
+#define regBIF_CFG_DEV0_EPF0_VF1_MSIX_PBA_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                      0x10040
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX                             5
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR                                               0x10041
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC1                                                  0x10042
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC1_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC2                                                  0x10043
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC2_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_DEVICE3_ENH_CAP_LIST                                              0x100b6
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_DEVICE3_ENH_CAP_LIST_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP3                                                            0x100b7
+#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP3_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL3                                                           0x100b8
+#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL3_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS3                                                         0x100b9
+#define regBIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS3_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_NULL1_ENH_CAP_LIST                                                0x10100
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_NULL1_ENH_CAP_LIST_BASE_IDX                                       5
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_NULL2_ENH_CAP_LIST                                                0x10180
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_NULL2_ENH_CAP_LIST_BASE_IDX                                       5
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                          0x10181
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX                                 5
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS                                                 0x10182
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK                                                   0x10183
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY                                               0x10184
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS                                                   0x10185
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK                                                     0x10186
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL                                                  0x10187
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG0                                                          0x10188
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG0_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG1                                                          0x10189
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG1_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG2                                                          0x1018a
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG2_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG3                                                          0x1018b
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG3_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG4                                                          0x1018f
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG4_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG0                                                   0x1018f
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG0_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG5                                                          0x10190
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG5_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG1                                                   0x10190
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG1_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG6                                                          0x10191
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG6_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG2                                                   0x10191
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG2_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG7                                                          0x10192
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG7_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG3                                                   0x10192
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG3_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG8                                                          0x10193
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG8_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG9                                                          0x10194
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG9_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG10                                                         0x10195
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG10_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG11                                                         0x10196
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG11_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG12                                                         0x10197
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG12_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG13                                                         0x10198
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG13_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_RTR_ENH_CAP_LIST                                                  0x101c7
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_RTR_ENH_CAP_LIST_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF0_VF1_RTR_DATA1                                                              0x101c8
+#define regBIF_CFG_DEV0_EPF0_VF1_RTR_DATA1_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_VF1_RTR_DATA2                                                              0x101c9
+#define regBIF_CFG_DEV0_EPF0_VF1_RTR_DATA2_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST                                                  0x101dc
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP                                                           0x101dd
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL                                                          0x101dd
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_ENH_CAP_LIST                                                  0x101eb
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_ENH_CAP_LIST_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP                                                           0x101ec
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CNTL                                                          0x101ec
+#define regBIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CNTL_BASE_IDX                                                 5
+
+
+// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_vf2_bifcfgdecp
+// base address: 0x10140000
+#define regBIF_CFG_DEV0_EPF0_VF2_VENDOR_ID                                                              0x10000
+#define regBIF_CFG_DEV0_EPF0_VF2_VENDOR_ID_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_ID                                                              0x10000
+#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_ID_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_VF2_COMMAND                                                                0x10001
+#define regBIF_CFG_DEV0_EPF0_VF2_COMMAND_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF0_VF2_STATUS                                                                 0x10001
+#define regBIF_CFG_DEV0_EPF0_VF2_STATUS_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_EPF0_VF2_REVISION_ID                                                            0x10002
+#define regBIF_CFG_DEV0_EPF0_VF2_REVISION_ID_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF2_PROG_INTERFACE                                                         0x10002
+#define regBIF_CFG_DEV0_EPF0_VF2_PROG_INTERFACE_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF0_VF2_SUB_CLASS                                                              0x10002
+#define regBIF_CFG_DEV0_EPF0_VF2_SUB_CLASS_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_VF2_BASE_CLASS                                                             0x10002
+#define regBIF_CFG_DEV0_EPF0_VF2_BASE_CLASS_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF0_VF2_CACHE_LINE                                                             0x10003
+#define regBIF_CFG_DEV0_EPF0_VF2_CACHE_LINE_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF0_VF2_LATENCY                                                                0x10003
+#define regBIF_CFG_DEV0_EPF0_VF2_LATENCY_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF0_VF2_HEADER                                                                 0x10003
+#define regBIF_CFG_DEV0_EPF0_VF2_HEADER_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_EPF0_VF2_BIST                                                                   0x10003
+#define regBIF_CFG_DEV0_EPF0_VF2_BIST_BASE_IDX                                                          5
+#define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_1                                                            0x10004
+#define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_1_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_2                                                            0x10005
+#define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_2_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_3                                                            0x10006
+#define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_3_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_4                                                            0x10007
+#define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_4_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_5                                                            0x10008
+#define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_5_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_6                                                            0x10009
+#define regBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_6_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF2_CARDBUS_CIS_PTR                                                        0x1000a
+#define regBIF_CFG_DEV0_EPF0_VF2_CARDBUS_CIS_PTR_BASE_IDX                                               5
+#define regBIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID                                                             0x1000b
+#define regBIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR                                                          0x1000c
+#define regBIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF2_CAP_PTR                                                                0x1000d
+#define regBIF_CFG_DEV0_EPF0_VF2_CAP_PTR_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF0_VF2_INTERRUPT_LINE                                                         0x1000f
+#define regBIF_CFG_DEV0_EPF0_VF2_INTERRUPT_LINE_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF0_VF2_INTERRUPT_PIN                                                          0x1000f
+#define regBIF_CFG_DEV0_EPF0_VF2_INTERRUPT_PIN_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF2_MIN_GRANT                                                              0x1000f
+#define regBIF_CFG_DEV0_EPF0_VF2_MIN_GRANT_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_VF2_MAX_LATENCY                                                            0x1000f
+#define regBIF_CFG_DEV0_EPF0_VF2_MAX_LATENCY_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST                                                          0x10019
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_CAP                                                               0x10019
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP                                                             0x1001a
+#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL                                                            0x1001b
+#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS                                                          0x1001b
+#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF2_LINK_CAP                                                               0x1001c
+#define regBIF_CFG_DEV0_EPF0_VF2_LINK_CAP_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF0_VF2_LINK_CNTL                                                              0x1001d
+#define regBIF_CFG_DEV0_EPF0_VF2_LINK_CNTL_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_VF2_LINK_STATUS                                                            0x1001d
+#define regBIF_CFG_DEV0_EPF0_VF2_LINK_STATUS_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2                                                            0x10022
+#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2                                                           0x10023
+#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS2                                                         0x10023
+#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS2_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF0_VF2_LINK_CAP2                                                              0x10024
+#define regBIF_CFG_DEV0_EPF0_VF2_LINK_CAP2_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2                                                             0x10025
+#define regBIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2                                                           0x10025
+#define regBIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST                                                           0x10028
+#define regBIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL                                                           0x10028
+#define regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_LO                                                        0x10029
+#define regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_LO_BASE_IDX                                               5
+#define regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_HI                                                        0x1002a
+#define regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_HI_BASE_IDX                                               5
+#define regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA                                                           0x1002a
+#define regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA                                                       0x1002a
+#define regBIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_EPF0_VF2_MSI_MASK                                                               0x1002b
+#define regBIF_CFG_DEV0_EPF0_VF2_MSI_MASK_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA_64                                                        0x1002b
+#define regBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA_64_BASE_IDX                                               5
+#define regBIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA_64                                                    0x1002b
+#define regBIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA_64_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF0_VF2_MSI_MASK_64                                                            0x1002c
+#define regBIF_CFG_DEV0_EPF0_VF2_MSI_MASK_64_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF2_MSI_PENDING                                                            0x1002c
+#define regBIF_CFG_DEV0_EPF0_VF2_MSI_PENDING_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF2_MSI_PENDING_64                                                         0x1002d
+#define regBIF_CFG_DEV0_EPF0_VF2_MSI_PENDING_64_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST                                                          0x10030
+#define regBIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL                                                          0x10030
+#define regBIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE                                                             0x10031
+#define regBIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF0_VF2_MSIX_PBA                                                               0x10032
+#define regBIF_CFG_DEV0_EPF0_VF2_MSIX_PBA_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                      0x10040
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX                             5
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR                                               0x10041
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC1                                                  0x10042
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC1_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC2                                                  0x10043
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC2_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_DEVICE3_ENH_CAP_LIST                                              0x100b6
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_DEVICE3_ENH_CAP_LIST_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP3                                                            0x100b7
+#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP3_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL3                                                           0x100b8
+#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL3_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS3                                                         0x100b9
+#define regBIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS3_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_NULL1_ENH_CAP_LIST                                                0x10100
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_NULL1_ENH_CAP_LIST_BASE_IDX                                       5
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_NULL2_ENH_CAP_LIST                                                0x10180
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_NULL2_ENH_CAP_LIST_BASE_IDX                                       5
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                          0x10181
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX                                 5
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS                                                 0x10182
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK                                                   0x10183
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY                                               0x10184
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS                                                   0x10185
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK                                                     0x10186
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL                                                  0x10187
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG0                                                          0x10188
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG0_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG1                                                          0x10189
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG1_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG2                                                          0x1018a
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG2_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG3                                                          0x1018b
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG3_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG4                                                          0x1018f
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG4_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG0                                                   0x1018f
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG0_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG5                                                          0x10190
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG5_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG1                                                   0x10190
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG1_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG6                                                          0x10191
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG6_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG2                                                   0x10191
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG2_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG7                                                          0x10192
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG7_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG3                                                   0x10192
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG3_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG8                                                          0x10193
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG8_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG9                                                          0x10194
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG9_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG10                                                         0x10195
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG10_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG11                                                         0x10196
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG11_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG12                                                         0x10197
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG12_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG13                                                         0x10198
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG13_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_RTR_ENH_CAP_LIST                                                  0x101c7
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_RTR_ENH_CAP_LIST_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF0_VF2_RTR_DATA1                                                              0x101c8
+#define regBIF_CFG_DEV0_EPF0_VF2_RTR_DATA1_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_VF2_RTR_DATA2                                                              0x101c9
+#define regBIF_CFG_DEV0_EPF0_VF2_RTR_DATA2_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST                                                  0x101dc
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP                                                           0x101dd
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL                                                          0x101dd
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_ENH_CAP_LIST                                                  0x101eb
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_ENH_CAP_LIST_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP                                                           0x101ec
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CNTL                                                          0x101ec
+#define regBIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CNTL_BASE_IDX                                                 5
+
+
+// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_vf3_bifcfgdecp
+// base address: 0x10140000
+#define regBIF_CFG_DEV0_EPF0_VF3_VENDOR_ID                                                              0x10000
+#define regBIF_CFG_DEV0_EPF0_VF3_VENDOR_ID_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_ID                                                              0x10000
+#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_ID_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_VF3_COMMAND                                                                0x10001
+#define regBIF_CFG_DEV0_EPF0_VF3_COMMAND_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF0_VF3_STATUS                                                                 0x10001
+#define regBIF_CFG_DEV0_EPF0_VF3_STATUS_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_EPF0_VF3_REVISION_ID                                                            0x10002
+#define regBIF_CFG_DEV0_EPF0_VF3_REVISION_ID_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF3_PROG_INTERFACE                                                         0x10002
+#define regBIF_CFG_DEV0_EPF0_VF3_PROG_INTERFACE_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF0_VF3_SUB_CLASS                                                              0x10002
+#define regBIF_CFG_DEV0_EPF0_VF3_SUB_CLASS_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_VF3_BASE_CLASS                                                             0x10002
+#define regBIF_CFG_DEV0_EPF0_VF3_BASE_CLASS_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF0_VF3_CACHE_LINE                                                             0x10003
+#define regBIF_CFG_DEV0_EPF0_VF3_CACHE_LINE_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF0_VF3_LATENCY                                                                0x10003
+#define regBIF_CFG_DEV0_EPF0_VF3_LATENCY_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF0_VF3_HEADER                                                                 0x10003
+#define regBIF_CFG_DEV0_EPF0_VF3_HEADER_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_EPF0_VF3_BIST                                                                   0x10003
+#define regBIF_CFG_DEV0_EPF0_VF3_BIST_BASE_IDX                                                          5
+#define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_1                                                            0x10004
+#define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_1_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_2                                                            0x10005
+#define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_2_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_3                                                            0x10006
+#define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_3_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_4                                                            0x10007
+#define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_4_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_5                                                            0x10008
+#define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_5_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_6                                                            0x10009
+#define regBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_6_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF3_CARDBUS_CIS_PTR                                                        0x1000a
+#define regBIF_CFG_DEV0_EPF0_VF3_CARDBUS_CIS_PTR_BASE_IDX                                               5
+#define regBIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID                                                             0x1000b
+#define regBIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR                                                          0x1000c
+#define regBIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF3_CAP_PTR                                                                0x1000d
+#define regBIF_CFG_DEV0_EPF0_VF3_CAP_PTR_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF0_VF3_INTERRUPT_LINE                                                         0x1000f
+#define regBIF_CFG_DEV0_EPF0_VF3_INTERRUPT_LINE_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF0_VF3_INTERRUPT_PIN                                                          0x1000f
+#define regBIF_CFG_DEV0_EPF0_VF3_INTERRUPT_PIN_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF3_MIN_GRANT                                                              0x1000f
+#define regBIF_CFG_DEV0_EPF0_VF3_MIN_GRANT_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_VF3_MAX_LATENCY                                                            0x1000f
+#define regBIF_CFG_DEV0_EPF0_VF3_MAX_LATENCY_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST                                                          0x10019
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_CAP                                                               0x10019
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP                                                             0x1001a
+#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL                                                            0x1001b
+#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS                                                          0x1001b
+#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF3_LINK_CAP                                                               0x1001c
+#define regBIF_CFG_DEV0_EPF0_VF3_LINK_CAP_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF0_VF3_LINK_CNTL                                                              0x1001d
+#define regBIF_CFG_DEV0_EPF0_VF3_LINK_CNTL_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_VF3_LINK_STATUS                                                            0x1001d
+#define regBIF_CFG_DEV0_EPF0_VF3_LINK_STATUS_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2                                                            0x10022
+#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2                                                           0x10023
+#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS2                                                         0x10023
+#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS2_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF0_VF3_LINK_CAP2                                                              0x10024
+#define regBIF_CFG_DEV0_EPF0_VF3_LINK_CAP2_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2                                                             0x10025
+#define regBIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2                                                           0x10025
+#define regBIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST                                                           0x10028
+#define regBIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL                                                           0x10028
+#define regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_LO                                                        0x10029
+#define regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_LO_BASE_IDX                                               5
+#define regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_HI                                                        0x1002a
+#define regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_HI_BASE_IDX                                               5
+#define regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA                                                           0x1002a
+#define regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA                                                       0x1002a
+#define regBIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_EPF0_VF3_MSI_MASK                                                               0x1002b
+#define regBIF_CFG_DEV0_EPF0_VF3_MSI_MASK_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA_64                                                        0x1002b
+#define regBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA_64_BASE_IDX                                               5
+#define regBIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA_64                                                    0x1002b
+#define regBIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA_64_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF0_VF3_MSI_MASK_64                                                            0x1002c
+#define regBIF_CFG_DEV0_EPF0_VF3_MSI_MASK_64_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF3_MSI_PENDING                                                            0x1002c
+#define regBIF_CFG_DEV0_EPF0_VF3_MSI_PENDING_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF3_MSI_PENDING_64                                                         0x1002d
+#define regBIF_CFG_DEV0_EPF0_VF3_MSI_PENDING_64_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST                                                          0x10030
+#define regBIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL                                                          0x10030
+#define regBIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE                                                             0x10031
+#define regBIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF0_VF3_MSIX_PBA                                                               0x10032
+#define regBIF_CFG_DEV0_EPF0_VF3_MSIX_PBA_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                      0x10040
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX                             5
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR                                               0x10041
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC1                                                  0x10042
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC1_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC2                                                  0x10043
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC2_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_DEVICE3_ENH_CAP_LIST                                              0x100b6
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_DEVICE3_ENH_CAP_LIST_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP3                                                            0x100b7
+#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP3_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL3                                                           0x100b8
+#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL3_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS3                                                         0x100b9
+#define regBIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS3_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_NULL1_ENH_CAP_LIST                                                0x10100
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_NULL1_ENH_CAP_LIST_BASE_IDX                                       5
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_NULL2_ENH_CAP_LIST                                                0x10180
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_NULL2_ENH_CAP_LIST_BASE_IDX                                       5
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                          0x10181
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX                                 5
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS                                                 0x10182
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK                                                   0x10183
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY                                               0x10184
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS                                                   0x10185
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK                                                     0x10186
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL                                                  0x10187
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG0                                                          0x10188
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG0_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG1                                                          0x10189
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG1_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG2                                                          0x1018a
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG2_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG3                                                          0x1018b
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG3_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG4                                                          0x1018f
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG4_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG0                                                   0x1018f
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG0_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG5                                                          0x10190
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG5_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG1                                                   0x10190
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG1_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG6                                                          0x10191
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG6_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG2                                                   0x10191
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG2_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG7                                                          0x10192
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG7_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG3                                                   0x10192
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG3_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG8                                                          0x10193
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG8_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG9                                                          0x10194
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG9_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG10                                                         0x10195
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG10_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG11                                                         0x10196
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG11_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG12                                                         0x10197
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG12_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG13                                                         0x10198
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG13_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_RTR_ENH_CAP_LIST                                                  0x101c7
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_RTR_ENH_CAP_LIST_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF0_VF3_RTR_DATA1                                                              0x101c8
+#define regBIF_CFG_DEV0_EPF0_VF3_RTR_DATA1_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_VF3_RTR_DATA2                                                              0x101c9
+#define regBIF_CFG_DEV0_EPF0_VF3_RTR_DATA2_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST                                                  0x101dc
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP                                                           0x101dd
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL                                                          0x101dd
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_ENH_CAP_LIST                                                  0x101eb
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_ENH_CAP_LIST_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP                                                           0x101ec
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CNTL                                                          0x101ec
+#define regBIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CNTL_BASE_IDX                                                 5
+
+
+// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_vf4_bifcfgdecp
+// base address: 0x10140000
+#define regBIF_CFG_DEV0_EPF0_VF4_VENDOR_ID                                                              0x10000
+#define regBIF_CFG_DEV0_EPF0_VF4_VENDOR_ID_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_ID                                                              0x10000
+#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_ID_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_VF4_COMMAND                                                                0x10001
+#define regBIF_CFG_DEV0_EPF0_VF4_COMMAND_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF0_VF4_STATUS                                                                 0x10001
+#define regBIF_CFG_DEV0_EPF0_VF4_STATUS_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_EPF0_VF4_REVISION_ID                                                            0x10002
+#define regBIF_CFG_DEV0_EPF0_VF4_REVISION_ID_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF4_PROG_INTERFACE                                                         0x10002
+#define regBIF_CFG_DEV0_EPF0_VF4_PROG_INTERFACE_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF0_VF4_SUB_CLASS                                                              0x10002
+#define regBIF_CFG_DEV0_EPF0_VF4_SUB_CLASS_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_VF4_BASE_CLASS                                                             0x10002
+#define regBIF_CFG_DEV0_EPF0_VF4_BASE_CLASS_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF0_VF4_CACHE_LINE                                                             0x10003
+#define regBIF_CFG_DEV0_EPF0_VF4_CACHE_LINE_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF0_VF4_LATENCY                                                                0x10003
+#define regBIF_CFG_DEV0_EPF0_VF4_LATENCY_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF0_VF4_HEADER                                                                 0x10003
+#define regBIF_CFG_DEV0_EPF0_VF4_HEADER_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_EPF0_VF4_BIST                                                                   0x10003
+#define regBIF_CFG_DEV0_EPF0_VF4_BIST_BASE_IDX                                                          5
+#define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_1                                                            0x10004
+#define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_1_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_2                                                            0x10005
+#define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_2_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_3                                                            0x10006
+#define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_3_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_4                                                            0x10007
+#define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_4_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_5                                                            0x10008
+#define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_5_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_6                                                            0x10009
+#define regBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_6_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF4_CARDBUS_CIS_PTR                                                        0x1000a
+#define regBIF_CFG_DEV0_EPF0_VF4_CARDBUS_CIS_PTR_BASE_IDX                                               5
+#define regBIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID                                                             0x1000b
+#define regBIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR                                                          0x1000c
+#define regBIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF4_CAP_PTR                                                                0x1000d
+#define regBIF_CFG_DEV0_EPF0_VF4_CAP_PTR_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF0_VF4_INTERRUPT_LINE                                                         0x1000f
+#define regBIF_CFG_DEV0_EPF0_VF4_INTERRUPT_LINE_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF0_VF4_INTERRUPT_PIN                                                          0x1000f
+#define regBIF_CFG_DEV0_EPF0_VF4_INTERRUPT_PIN_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF4_MIN_GRANT                                                              0x1000f
+#define regBIF_CFG_DEV0_EPF0_VF4_MIN_GRANT_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_VF4_MAX_LATENCY                                                            0x1000f
+#define regBIF_CFG_DEV0_EPF0_VF4_MAX_LATENCY_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST                                                          0x10019
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_CAP                                                               0x10019
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP                                                             0x1001a
+#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL                                                            0x1001b
+#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS                                                          0x1001b
+#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF4_LINK_CAP                                                               0x1001c
+#define regBIF_CFG_DEV0_EPF0_VF4_LINK_CAP_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF0_VF4_LINK_CNTL                                                              0x1001d
+#define regBIF_CFG_DEV0_EPF0_VF4_LINK_CNTL_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_VF4_LINK_STATUS                                                            0x1001d
+#define regBIF_CFG_DEV0_EPF0_VF4_LINK_STATUS_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2                                                            0x10022
+#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2                                                           0x10023
+#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS2                                                         0x10023
+#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS2_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF0_VF4_LINK_CAP2                                                              0x10024
+#define regBIF_CFG_DEV0_EPF0_VF4_LINK_CAP2_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2                                                             0x10025
+#define regBIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2                                                           0x10025
+#define regBIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST                                                           0x10028
+#define regBIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL                                                           0x10028
+#define regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_LO                                                        0x10029
+#define regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_LO_BASE_IDX                                               5
+#define regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_HI                                                        0x1002a
+#define regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_HI_BASE_IDX                                               5
+#define regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA                                                           0x1002a
+#define regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA                                                       0x1002a
+#define regBIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_EPF0_VF4_MSI_MASK                                                               0x1002b
+#define regBIF_CFG_DEV0_EPF0_VF4_MSI_MASK_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA_64                                                        0x1002b
+#define regBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA_64_BASE_IDX                                               5
+#define regBIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA_64                                                    0x1002b
+#define regBIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA_64_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF0_VF4_MSI_MASK_64                                                            0x1002c
+#define regBIF_CFG_DEV0_EPF0_VF4_MSI_MASK_64_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF4_MSI_PENDING                                                            0x1002c
+#define regBIF_CFG_DEV0_EPF0_VF4_MSI_PENDING_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF4_MSI_PENDING_64                                                         0x1002d
+#define regBIF_CFG_DEV0_EPF0_VF4_MSI_PENDING_64_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST                                                          0x10030
+#define regBIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL                                                          0x10030
+#define regBIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE                                                             0x10031
+#define regBIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF0_VF4_MSIX_PBA                                                               0x10032
+#define regBIF_CFG_DEV0_EPF0_VF4_MSIX_PBA_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                      0x10040
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX                             5
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR                                               0x10041
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC1                                                  0x10042
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC1_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC2                                                  0x10043
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC2_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_DEVICE3_ENH_CAP_LIST                                              0x100b6
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_DEVICE3_ENH_CAP_LIST_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP3                                                            0x100b7
+#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP3_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL3                                                           0x100b8
+#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL3_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS3                                                         0x100b9
+#define regBIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS3_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_NULL1_ENH_CAP_LIST                                                0x10100
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_NULL1_ENH_CAP_LIST_BASE_IDX                                       5
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_NULL2_ENH_CAP_LIST                                                0x10180
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_NULL2_ENH_CAP_LIST_BASE_IDX                                       5
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                          0x10181
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX                                 5
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS                                                 0x10182
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK                                                   0x10183
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY                                               0x10184
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS                                                   0x10185
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK                                                     0x10186
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL                                                  0x10187
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG0                                                          0x10188
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG0_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG1                                                          0x10189
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG1_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG2                                                          0x1018a
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG2_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG3                                                          0x1018b
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG3_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG4                                                          0x1018f
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG4_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG0                                                   0x1018f
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG0_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG5                                                          0x10190
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG5_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG1                                                   0x10190
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG1_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG6                                                          0x10191
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG6_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG2                                                   0x10191
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG2_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG7                                                          0x10192
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG7_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG3                                                   0x10192
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG3_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG8                                                          0x10193
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG8_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG9                                                          0x10194
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG9_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG10                                                         0x10195
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG10_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG11                                                         0x10196
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG11_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG12                                                         0x10197
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG12_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG13                                                         0x10198
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG13_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_RTR_ENH_CAP_LIST                                                  0x101c7
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_RTR_ENH_CAP_LIST_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF0_VF4_RTR_DATA1                                                              0x101c8
+#define regBIF_CFG_DEV0_EPF0_VF4_RTR_DATA1_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_VF4_RTR_DATA2                                                              0x101c9
+#define regBIF_CFG_DEV0_EPF0_VF4_RTR_DATA2_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST                                                  0x101dc
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP                                                           0x101dd
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL                                                          0x101dd
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_ENH_CAP_LIST                                                  0x101eb
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_ENH_CAP_LIST_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP                                                           0x101ec
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CNTL                                                          0x101ec
+#define regBIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CNTL_BASE_IDX                                                 5
+
+
+// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_vf5_bifcfgdecp
+// base address: 0x10140000
+#define regBIF_CFG_DEV0_EPF0_VF5_VENDOR_ID                                                              0x10000
+#define regBIF_CFG_DEV0_EPF0_VF5_VENDOR_ID_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_ID                                                              0x10000
+#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_ID_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_VF5_COMMAND                                                                0x10001
+#define regBIF_CFG_DEV0_EPF0_VF5_COMMAND_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF0_VF5_STATUS                                                                 0x10001
+#define regBIF_CFG_DEV0_EPF0_VF5_STATUS_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_EPF0_VF5_REVISION_ID                                                            0x10002
+#define regBIF_CFG_DEV0_EPF0_VF5_REVISION_ID_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF5_PROG_INTERFACE                                                         0x10002
+#define regBIF_CFG_DEV0_EPF0_VF5_PROG_INTERFACE_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF0_VF5_SUB_CLASS                                                              0x10002
+#define regBIF_CFG_DEV0_EPF0_VF5_SUB_CLASS_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_VF5_BASE_CLASS                                                             0x10002
+#define regBIF_CFG_DEV0_EPF0_VF5_BASE_CLASS_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF0_VF5_CACHE_LINE                                                             0x10003
+#define regBIF_CFG_DEV0_EPF0_VF5_CACHE_LINE_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF0_VF5_LATENCY                                                                0x10003
+#define regBIF_CFG_DEV0_EPF0_VF5_LATENCY_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF0_VF5_HEADER                                                                 0x10003
+#define regBIF_CFG_DEV0_EPF0_VF5_HEADER_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_EPF0_VF5_BIST                                                                   0x10003
+#define regBIF_CFG_DEV0_EPF0_VF5_BIST_BASE_IDX                                                          5
+#define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_1                                                            0x10004
+#define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_1_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_2                                                            0x10005
+#define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_2_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_3                                                            0x10006
+#define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_3_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_4                                                            0x10007
+#define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_4_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_5                                                            0x10008
+#define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_5_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_6                                                            0x10009
+#define regBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_6_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF5_CARDBUS_CIS_PTR                                                        0x1000a
+#define regBIF_CFG_DEV0_EPF0_VF5_CARDBUS_CIS_PTR_BASE_IDX                                               5
+#define regBIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID                                                             0x1000b
+#define regBIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR                                                          0x1000c
+#define regBIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF5_CAP_PTR                                                                0x1000d
+#define regBIF_CFG_DEV0_EPF0_VF5_CAP_PTR_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF0_VF5_INTERRUPT_LINE                                                         0x1000f
+#define regBIF_CFG_DEV0_EPF0_VF5_INTERRUPT_LINE_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF0_VF5_INTERRUPT_PIN                                                          0x1000f
+#define regBIF_CFG_DEV0_EPF0_VF5_INTERRUPT_PIN_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF5_MIN_GRANT                                                              0x1000f
+#define regBIF_CFG_DEV0_EPF0_VF5_MIN_GRANT_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_VF5_MAX_LATENCY                                                            0x1000f
+#define regBIF_CFG_DEV0_EPF0_VF5_MAX_LATENCY_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST                                                          0x10019
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_CAP                                                               0x10019
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP                                                             0x1001a
+#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL                                                            0x1001b
+#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS                                                          0x1001b
+#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF5_LINK_CAP                                                               0x1001c
+#define regBIF_CFG_DEV0_EPF0_VF5_LINK_CAP_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF0_VF5_LINK_CNTL                                                              0x1001d
+#define regBIF_CFG_DEV0_EPF0_VF5_LINK_CNTL_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_VF5_LINK_STATUS                                                            0x1001d
+#define regBIF_CFG_DEV0_EPF0_VF5_LINK_STATUS_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2                                                            0x10022
+#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2                                                           0x10023
+#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS2                                                         0x10023
+#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS2_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF0_VF5_LINK_CAP2                                                              0x10024
+#define regBIF_CFG_DEV0_EPF0_VF5_LINK_CAP2_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2                                                             0x10025
+#define regBIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2                                                           0x10025
+#define regBIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST                                                           0x10028
+#define regBIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL                                                           0x10028
+#define regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_LO                                                        0x10029
+#define regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_LO_BASE_IDX                                               5
+#define regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_HI                                                        0x1002a
+#define regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_HI_BASE_IDX                                               5
+#define regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA                                                           0x1002a
+#define regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA                                                       0x1002a
+#define regBIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_EPF0_VF5_MSI_MASK                                                               0x1002b
+#define regBIF_CFG_DEV0_EPF0_VF5_MSI_MASK_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA_64                                                        0x1002b
+#define regBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA_64_BASE_IDX                                               5
+#define regBIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA_64                                                    0x1002b
+#define regBIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA_64_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF0_VF5_MSI_MASK_64                                                            0x1002c
+#define regBIF_CFG_DEV0_EPF0_VF5_MSI_MASK_64_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF5_MSI_PENDING                                                            0x1002c
+#define regBIF_CFG_DEV0_EPF0_VF5_MSI_PENDING_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF5_MSI_PENDING_64                                                         0x1002d
+#define regBIF_CFG_DEV0_EPF0_VF5_MSI_PENDING_64_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST                                                          0x10030
+#define regBIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL                                                          0x10030
+#define regBIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE                                                             0x10031
+#define regBIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF0_VF5_MSIX_PBA                                                               0x10032
+#define regBIF_CFG_DEV0_EPF0_VF5_MSIX_PBA_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                      0x10040
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX                             5
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR                                               0x10041
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC1                                                  0x10042
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC1_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC2                                                  0x10043
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC2_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_DEVICE3_ENH_CAP_LIST                                              0x100b6
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_DEVICE3_ENH_CAP_LIST_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP3                                                            0x100b7
+#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP3_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL3                                                           0x100b8
+#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL3_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS3                                                         0x100b9
+#define regBIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS3_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_NULL1_ENH_CAP_LIST                                                0x10100
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_NULL1_ENH_CAP_LIST_BASE_IDX                                       5
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_NULL2_ENH_CAP_LIST                                                0x10180
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_NULL2_ENH_CAP_LIST_BASE_IDX                                       5
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                          0x10181
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX                                 5
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS                                                 0x10182
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK                                                   0x10183
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY                                               0x10184
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS                                                   0x10185
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK                                                     0x10186
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL                                                  0x10187
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG0                                                          0x10188
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG0_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG1                                                          0x10189
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG1_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG2                                                          0x1018a
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG2_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG3                                                          0x1018b
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG3_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG4                                                          0x1018f
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG4_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG0                                                   0x1018f
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG0_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG5                                                          0x10190
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG5_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG1                                                   0x10190
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG1_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG6                                                          0x10191
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG6_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG2                                                   0x10191
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG2_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG7                                                          0x10192
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG7_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG3                                                   0x10192
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG3_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG8                                                          0x10193
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG8_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG9                                                          0x10194
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG9_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG10                                                         0x10195
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG10_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG11                                                         0x10196
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG11_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG12                                                         0x10197
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG12_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG13                                                         0x10198
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG13_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_RTR_ENH_CAP_LIST                                                  0x101c7
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_RTR_ENH_CAP_LIST_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF0_VF5_RTR_DATA1                                                              0x101c8
+#define regBIF_CFG_DEV0_EPF0_VF5_RTR_DATA1_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_VF5_RTR_DATA2                                                              0x101c9
+#define regBIF_CFG_DEV0_EPF0_VF5_RTR_DATA2_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST                                                  0x101dc
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP                                                           0x101dd
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL                                                          0x101dd
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_ENH_CAP_LIST                                                  0x101eb
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_ENH_CAP_LIST_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP                                                           0x101ec
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CNTL                                                          0x101ec
+#define regBIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CNTL_BASE_IDX                                                 5
+
+
+// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_vf6_bifcfgdecp
+// base address: 0x10140000
+#define regBIF_CFG_DEV0_EPF0_VF6_VENDOR_ID                                                              0x10000
+#define regBIF_CFG_DEV0_EPF0_VF6_VENDOR_ID_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_ID                                                              0x10000
+#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_ID_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_VF6_COMMAND                                                                0x10001
+#define regBIF_CFG_DEV0_EPF0_VF6_COMMAND_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF0_VF6_STATUS                                                                 0x10001
+#define regBIF_CFG_DEV0_EPF0_VF6_STATUS_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_EPF0_VF6_REVISION_ID                                                            0x10002
+#define regBIF_CFG_DEV0_EPF0_VF6_REVISION_ID_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF6_PROG_INTERFACE                                                         0x10002
+#define regBIF_CFG_DEV0_EPF0_VF6_PROG_INTERFACE_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF0_VF6_SUB_CLASS                                                              0x10002
+#define regBIF_CFG_DEV0_EPF0_VF6_SUB_CLASS_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_VF6_BASE_CLASS                                                             0x10002
+#define regBIF_CFG_DEV0_EPF0_VF6_BASE_CLASS_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF0_VF6_CACHE_LINE                                                             0x10003
+#define regBIF_CFG_DEV0_EPF0_VF6_CACHE_LINE_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF0_VF6_LATENCY                                                                0x10003
+#define regBIF_CFG_DEV0_EPF0_VF6_LATENCY_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF0_VF6_HEADER                                                                 0x10003
+#define regBIF_CFG_DEV0_EPF0_VF6_HEADER_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_EPF0_VF6_BIST                                                                   0x10003
+#define regBIF_CFG_DEV0_EPF0_VF6_BIST_BASE_IDX                                                          5
+#define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_1                                                            0x10004
+#define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_1_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_2                                                            0x10005
+#define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_2_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_3                                                            0x10006
+#define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_3_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_4                                                            0x10007
+#define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_4_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_5                                                            0x10008
+#define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_5_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_6                                                            0x10009
+#define regBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_6_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF6_CARDBUS_CIS_PTR                                                        0x1000a
+#define regBIF_CFG_DEV0_EPF0_VF6_CARDBUS_CIS_PTR_BASE_IDX                                               5
+#define regBIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID                                                             0x1000b
+#define regBIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR                                                          0x1000c
+#define regBIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF6_CAP_PTR                                                                0x1000d
+#define regBIF_CFG_DEV0_EPF0_VF6_CAP_PTR_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF0_VF6_INTERRUPT_LINE                                                         0x1000f
+#define regBIF_CFG_DEV0_EPF0_VF6_INTERRUPT_LINE_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF0_VF6_INTERRUPT_PIN                                                          0x1000f
+#define regBIF_CFG_DEV0_EPF0_VF6_INTERRUPT_PIN_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF6_MIN_GRANT                                                              0x1000f
+#define regBIF_CFG_DEV0_EPF0_VF6_MIN_GRANT_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_VF6_MAX_LATENCY                                                            0x1000f
+#define regBIF_CFG_DEV0_EPF0_VF6_MAX_LATENCY_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST                                                          0x10019
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_CAP                                                               0x10019
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP                                                             0x1001a
+#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL                                                            0x1001b
+#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS                                                          0x1001b
+#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF6_LINK_CAP                                                               0x1001c
+#define regBIF_CFG_DEV0_EPF0_VF6_LINK_CAP_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF0_VF6_LINK_CNTL                                                              0x1001d
+#define regBIF_CFG_DEV0_EPF0_VF6_LINK_CNTL_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_VF6_LINK_STATUS                                                            0x1001d
+#define regBIF_CFG_DEV0_EPF0_VF6_LINK_STATUS_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2                                                            0x10022
+#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2                                                           0x10023
+#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS2                                                         0x10023
+#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS2_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF0_VF6_LINK_CAP2                                                              0x10024
+#define regBIF_CFG_DEV0_EPF0_VF6_LINK_CAP2_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2                                                             0x10025
+#define regBIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2                                                           0x10025
+#define regBIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST                                                           0x10028
+#define regBIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL                                                           0x10028
+#define regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_LO                                                        0x10029
+#define regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_LO_BASE_IDX                                               5
+#define regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_HI                                                        0x1002a
+#define regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_HI_BASE_IDX                                               5
+#define regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA                                                           0x1002a
+#define regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA                                                       0x1002a
+#define regBIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_EPF0_VF6_MSI_MASK                                                               0x1002b
+#define regBIF_CFG_DEV0_EPF0_VF6_MSI_MASK_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA_64                                                        0x1002b
+#define regBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA_64_BASE_IDX                                               5
+#define regBIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA_64                                                    0x1002b
+#define regBIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA_64_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF0_VF6_MSI_MASK_64                                                            0x1002c
+#define regBIF_CFG_DEV0_EPF0_VF6_MSI_MASK_64_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF6_MSI_PENDING                                                            0x1002c
+#define regBIF_CFG_DEV0_EPF0_VF6_MSI_PENDING_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF6_MSI_PENDING_64                                                         0x1002d
+#define regBIF_CFG_DEV0_EPF0_VF6_MSI_PENDING_64_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST                                                          0x10030
+#define regBIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL                                                          0x10030
+#define regBIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE                                                             0x10031
+#define regBIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF0_VF6_MSIX_PBA                                                               0x10032
+#define regBIF_CFG_DEV0_EPF0_VF6_MSIX_PBA_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                      0x10040
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX                             5
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR                                               0x10041
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC1                                                  0x10042
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC1_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC2                                                  0x10043
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC2_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_DEVICE3_ENH_CAP_LIST                                              0x100b6
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_DEVICE3_ENH_CAP_LIST_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP3                                                            0x100b7
+#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP3_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL3                                                           0x100b8
+#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL3_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS3                                                         0x100b9
+#define regBIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS3_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_NULL1_ENH_CAP_LIST                                                0x10100
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_NULL1_ENH_CAP_LIST_BASE_IDX                                       5
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_NULL2_ENH_CAP_LIST                                                0x10180
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_NULL2_ENH_CAP_LIST_BASE_IDX                                       5
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                          0x10181
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX                                 5
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS                                                 0x10182
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK                                                   0x10183
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY                                               0x10184
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS                                                   0x10185
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK                                                     0x10186
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL                                                  0x10187
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG0                                                          0x10188
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG0_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG1                                                          0x10189
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG1_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG2                                                          0x1018a
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG2_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG3                                                          0x1018b
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG3_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG4                                                          0x1018f
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG4_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG0                                                   0x1018f
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG0_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG5                                                          0x10190
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG5_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG1                                                   0x10190
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG1_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG6                                                          0x10191
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG6_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG2                                                   0x10191
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG2_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG7                                                          0x10192
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG7_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG3                                                   0x10192
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG3_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG8                                                          0x10193
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG8_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG9                                                          0x10194
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG9_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG10                                                         0x10195
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG10_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG11                                                         0x10196
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG11_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG12                                                         0x10197
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG12_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG13                                                         0x10198
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG13_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_RTR_ENH_CAP_LIST                                                  0x101c7
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_RTR_ENH_CAP_LIST_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF0_VF6_RTR_DATA1                                                              0x101c8
+#define regBIF_CFG_DEV0_EPF0_VF6_RTR_DATA1_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_VF6_RTR_DATA2                                                              0x101c9
+#define regBIF_CFG_DEV0_EPF0_VF6_RTR_DATA2_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST                                                  0x101dc
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP                                                           0x101dd
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL                                                          0x101dd
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_ENH_CAP_LIST                                                  0x101eb
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_ENH_CAP_LIST_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP                                                           0x101ec
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CNTL                                                          0x101ec
+#define regBIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CNTL_BASE_IDX                                                 5
+
+
+// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_vf7_bifcfgdecp
+// base address: 0x10140000
+#define regBIF_CFG_DEV0_EPF0_VF7_VENDOR_ID                                                              0x10000
+#define regBIF_CFG_DEV0_EPF0_VF7_VENDOR_ID_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_ID                                                              0x10000
+#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_ID_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_VF7_COMMAND                                                                0x10001
+#define regBIF_CFG_DEV0_EPF0_VF7_COMMAND_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF0_VF7_STATUS                                                                 0x10001
+#define regBIF_CFG_DEV0_EPF0_VF7_STATUS_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_EPF0_VF7_REVISION_ID                                                            0x10002
+#define regBIF_CFG_DEV0_EPF0_VF7_REVISION_ID_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF7_PROG_INTERFACE                                                         0x10002
+#define regBIF_CFG_DEV0_EPF0_VF7_PROG_INTERFACE_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF0_VF7_SUB_CLASS                                                              0x10002
+#define regBIF_CFG_DEV0_EPF0_VF7_SUB_CLASS_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_VF7_BASE_CLASS                                                             0x10002
+#define regBIF_CFG_DEV0_EPF0_VF7_BASE_CLASS_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF0_VF7_CACHE_LINE                                                             0x10003
+#define regBIF_CFG_DEV0_EPF0_VF7_CACHE_LINE_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF0_VF7_LATENCY                                                                0x10003
+#define regBIF_CFG_DEV0_EPF0_VF7_LATENCY_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF0_VF7_HEADER                                                                 0x10003
+#define regBIF_CFG_DEV0_EPF0_VF7_HEADER_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_EPF0_VF7_BIST                                                                   0x10003
+#define regBIF_CFG_DEV0_EPF0_VF7_BIST_BASE_IDX                                                          5
+#define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_1                                                            0x10004
+#define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_1_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_2                                                            0x10005
+#define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_2_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_3                                                            0x10006
+#define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_3_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_4                                                            0x10007
+#define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_4_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_5                                                            0x10008
+#define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_5_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_6                                                            0x10009
+#define regBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_6_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF7_CARDBUS_CIS_PTR                                                        0x1000a
+#define regBIF_CFG_DEV0_EPF0_VF7_CARDBUS_CIS_PTR_BASE_IDX                                               5
+#define regBIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID                                                             0x1000b
+#define regBIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR                                                          0x1000c
+#define regBIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF7_CAP_PTR                                                                0x1000d
+#define regBIF_CFG_DEV0_EPF0_VF7_CAP_PTR_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF0_VF7_INTERRUPT_LINE                                                         0x1000f
+#define regBIF_CFG_DEV0_EPF0_VF7_INTERRUPT_LINE_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF0_VF7_INTERRUPT_PIN                                                          0x1000f
+#define regBIF_CFG_DEV0_EPF0_VF7_INTERRUPT_PIN_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF7_MIN_GRANT                                                              0x1000f
+#define regBIF_CFG_DEV0_EPF0_VF7_MIN_GRANT_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_VF7_MAX_LATENCY                                                            0x1000f
+#define regBIF_CFG_DEV0_EPF0_VF7_MAX_LATENCY_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST                                                          0x10019
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_CAP                                                               0x10019
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP                                                             0x1001a
+#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL                                                            0x1001b
+#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS                                                          0x1001b
+#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF7_LINK_CAP                                                               0x1001c
+#define regBIF_CFG_DEV0_EPF0_VF7_LINK_CAP_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF0_VF7_LINK_CNTL                                                              0x1001d
+#define regBIF_CFG_DEV0_EPF0_VF7_LINK_CNTL_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_VF7_LINK_STATUS                                                            0x1001d
+#define regBIF_CFG_DEV0_EPF0_VF7_LINK_STATUS_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2                                                            0x10022
+#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2                                                           0x10023
+#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS2                                                         0x10023
+#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS2_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF0_VF7_LINK_CAP2                                                              0x10024
+#define regBIF_CFG_DEV0_EPF0_VF7_LINK_CAP2_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2                                                             0x10025
+#define regBIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2                                                           0x10025
+#define regBIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST                                                           0x10028
+#define regBIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL                                                           0x10028
+#define regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_LO                                                        0x10029
+#define regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_LO_BASE_IDX                                               5
+#define regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_HI                                                        0x1002a
+#define regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_HI_BASE_IDX                                               5
+#define regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA                                                           0x1002a
+#define regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA                                                       0x1002a
+#define regBIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_EPF0_VF7_MSI_MASK                                                               0x1002b
+#define regBIF_CFG_DEV0_EPF0_VF7_MSI_MASK_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA_64                                                        0x1002b
+#define regBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA_64_BASE_IDX                                               5
+#define regBIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA_64                                                    0x1002b
+#define regBIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA_64_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF0_VF7_MSI_MASK_64                                                            0x1002c
+#define regBIF_CFG_DEV0_EPF0_VF7_MSI_MASK_64_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF7_MSI_PENDING                                                            0x1002c
+#define regBIF_CFG_DEV0_EPF0_VF7_MSI_PENDING_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF7_MSI_PENDING_64                                                         0x1002d
+#define regBIF_CFG_DEV0_EPF0_VF7_MSI_PENDING_64_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST                                                          0x10030
+#define regBIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL                                                          0x10030
+#define regBIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE                                                             0x10031
+#define regBIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF0_VF7_MSIX_PBA                                                               0x10032
+#define regBIF_CFG_DEV0_EPF0_VF7_MSIX_PBA_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                      0x10040
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX                             5
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR                                               0x10041
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC1                                                  0x10042
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC1_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC2                                                  0x10043
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC2_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_DEVICE3_ENH_CAP_LIST                                              0x100b6
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_DEVICE3_ENH_CAP_LIST_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP3                                                            0x100b7
+#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP3_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL3                                                           0x100b8
+#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL3_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS3                                                         0x100b9
+#define regBIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS3_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_NULL1_ENH_CAP_LIST                                                0x10100
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_NULL1_ENH_CAP_LIST_BASE_IDX                                       5
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_NULL2_ENH_CAP_LIST                                                0x10180
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_NULL2_ENH_CAP_LIST_BASE_IDX                                       5
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                          0x10181
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX                                 5
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS                                                 0x10182
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK                                                   0x10183
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY                                               0x10184
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS                                                   0x10185
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK                                                     0x10186
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL                                                  0x10187
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG0                                                          0x10188
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG0_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG1                                                          0x10189
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG1_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG2                                                          0x1018a
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG2_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG3                                                          0x1018b
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG3_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG4                                                          0x1018f
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG4_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG0                                                   0x1018f
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG0_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG5                                                          0x10190
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG5_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG1                                                   0x10190
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG1_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG6                                                          0x10191
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG6_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG2                                                   0x10191
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG2_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG7                                                          0x10192
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG7_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG3                                                   0x10192
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG3_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG8                                                          0x10193
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG8_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG9                                                          0x10194
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG9_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG10                                                         0x10195
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG10_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG11                                                         0x10196
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG11_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG12                                                         0x10197
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG12_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG13                                                         0x10198
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG13_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_RTR_ENH_CAP_LIST                                                  0x101c7
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_RTR_ENH_CAP_LIST_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF0_VF7_RTR_DATA1                                                              0x101c8
+#define regBIF_CFG_DEV0_EPF0_VF7_RTR_DATA1_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_VF7_RTR_DATA2                                                              0x101c9
+#define regBIF_CFG_DEV0_EPF0_VF7_RTR_DATA2_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST                                                  0x101dc
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP                                                           0x101dd
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL                                                          0x101dd
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_ENH_CAP_LIST                                                  0x101eb
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_ENH_CAP_LIST_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP                                                           0x101ec
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CNTL                                                          0x101ec
+#define regBIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CNTL_BASE_IDX                                                 5
+
+
+// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf0_BIFPFVFDEC1
+// base address: 0x10120000
+#define regBIF_BX_DEV0_EPF0_VF0_0_BIF_BME_STATUS                                                        0x8e0b
+#define regBIF_BX_DEV0_EPF0_VF0_0_BIF_BME_STATUS_BASE_IDX                                               5
+#define regBIF_BX_DEV0_EPF0_VF0_0_BIF_ATOMIC_ERR_LOG                                                    0x8e0c
+#define regBIF_BX_DEV0_EPF0_VF0_0_BIF_ATOMIC_ERR_LOG_BASE_IDX                                           5
+#define regBIF_BX_DEV0_EPF0_VF0_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH                                  0x8e13
+#define regBIF_BX_DEV0_EPF0_VF0_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX                         5
+#define regBIF_BX_DEV0_EPF0_VF0_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW                                   0x8e14
+#define regBIF_BX_DEV0_EPF0_VF0_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX                          5
+#define regBIF_BX_DEV0_EPF0_VF0_0_DOORBELL_SELFRING_GPA_APER_CNTL                                       0x8e15
+#define regBIF_BX_DEV0_EPF0_VF0_0_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX                              5
+#define regBIF_BX_DEV0_EPF0_VF0_0_HDP_REG_COHERENCY_FLUSH_CNTL                                          0x8e16
+#define regBIF_BX_DEV0_EPF0_VF0_0_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX                                 5
+#define regBIF_BX_DEV0_EPF0_VF0_0_HDP_MEM_COHERENCY_FLUSH_CNTL                                          0x8e17
+#define regBIF_BX_DEV0_EPF0_VF0_0_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX                                 5
+#define regBIF_BX_DEV0_EPF0_VF0_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL                                     0x8e19
+#define regBIF_BX_DEV0_EPF0_VF0_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX                            5
+#define regBIF_BX_DEV0_EPF0_VF0_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL                                0x8e1a
+#define regBIF_BX_DEV0_EPF0_VF0_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX                       5
+#define regBIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ                                                     0x8e26
+#define regBIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ_BASE_IDX                                            5
+#define regBIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE                                                    0x8e27
+#define regBIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE_BASE_IDX                                           5
+#define regBIF_BX_DEV0_EPF0_VF0_0_BIF_TRANS_PENDING                                                     0x8e28
+#define regBIF_BX_DEV0_EPF0_VF0_0_BIF_TRANS_PENDING_BASE_IDX                                            5
+#define regBIF_BX_DEV0_EPF0_VF0_0_NBIF_GFX_ADDR_LUT_BYPASS                                              0x8e32
+#define regBIF_BX_DEV0_EPF0_VF0_0_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX                                     5
+#define regBIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_TRN_DW0                                                0x8e56
+#define regBIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX                                       5
+#define regBIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_TRN_DW1                                                0x8e57
+#define regBIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX                                       5
+#define regBIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_TRN_DW2                                                0x8e58
+#define regBIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX                                       5
+#define regBIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_TRN_DW3                                                0x8e59
+#define regBIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX                                       5
+#define regBIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_RCV_DW0                                                0x8e5a
+#define regBIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX                                       5
+#define regBIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_RCV_DW1                                                0x8e5b
+#define regBIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX                                       5
+#define regBIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_RCV_DW2                                                0x8e5c
+#define regBIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX                                       5
+#define regBIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_RCV_DW3                                                0x8e5d
+#define regBIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX                                       5
+#define regBIF_BX_DEV0_EPF0_VF0_0_MAILBOX_CONTROL                                                       0x8e5e
+#define regBIF_BX_DEV0_EPF0_VF0_0_MAILBOX_CONTROL_BASE_IDX                                              5
+#define regBIF_BX_DEV0_EPF0_VF0_0_MAILBOX_INT_CNTL                                                      0x8e5f
+#define regBIF_BX_DEV0_EPF0_VF0_0_MAILBOX_INT_CNTL_BASE_IDX                                             5
+#define regBIF_BX_DEV0_EPF0_VF0_0_BIF_VMHV_MAILBOX                                                      0x8e60
+#define regBIF_BX_DEV0_EPF0_VF0_0_BIF_VMHV_MAILBOX_BASE_IDX                                             5
+#define regBIF_BX_DEV0_EPF0_VF0_0_PARTITION_COMPUTE_CAP                                                 0x8e81
+#define regBIF_BX_DEV0_EPF0_VF0_0_PARTITION_COMPUTE_CAP_BASE_IDX                                        5
+#define regBIF_BX_DEV0_EPF0_VF0_0_PARTITION_MEM_CAP                                                     0x8e82
+#define regBIF_BX_DEV0_EPF0_VF0_0_PARTITION_MEM_CAP_BASE_IDX                                            5
+#define regBIF_BX_DEV0_EPF0_VF0_0_PARTITION_COMPUTE_STATUS                                              0x8e83
+#define regBIF_BX_DEV0_EPF0_VF0_0_PARTITION_COMPUTE_STATUS_BASE_IDX                                     5
+#define regBIF_BX_DEV0_EPF0_VF0_0_PARTITION_MEM_STATUS                                                  0x8e84
+#define regBIF_BX_DEV0_EPF0_VF0_0_PARTITION_MEM_STATUS_BASE_IDX                                         5
+
+
+// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf0_SYSPFVFDEC
+// base address: 0x10120000
+#define regBIF_BX_DEV0_EPF0_VF0_0_MM_INDEX                                                              0x8000
+#define regBIF_BX_DEV0_EPF0_VF0_0_MM_INDEX_BASE_IDX                                                     5
+#define regBIF_BX_DEV0_EPF0_VF0_0_MM_DATA                                                               0x8001
+#define regBIF_BX_DEV0_EPF0_VF0_0_MM_DATA_BASE_IDX                                                      5
+#define regBIF_BX_DEV0_EPF0_VF0_0_MM_INDEX_HI                                                           0x8006
+#define regBIF_BX_DEV0_EPF0_VF0_0_MM_INDEX_HI_BASE_IDX                                                  5
+
+
+// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf0_BIFPFVFDEC1:1
+// base address: 0x0
+#define regBIF_BX_DEV0_EPF0_VF0_1_BIF_BME_STATUS                                                        0x00eb
+#define regBIF_BX_DEV0_EPF0_VF0_1_BIF_BME_STATUS_BASE_IDX                                               2
+#define regBIF_BX_DEV0_EPF0_VF0_1_BIF_ATOMIC_ERR_LOG                                                    0x00ec
+#define regBIF_BX_DEV0_EPF0_VF0_1_BIF_ATOMIC_ERR_LOG_BASE_IDX                                           2
+#define regBIF_BX_DEV0_EPF0_VF0_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH                                  0x00f3
+#define regBIF_BX_DEV0_EPF0_VF0_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX                         2
+#define regBIF_BX_DEV0_EPF0_VF0_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW                                   0x00f4
+#define regBIF_BX_DEV0_EPF0_VF0_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX                          2
+#define regBIF_BX_DEV0_EPF0_VF0_1_DOORBELL_SELFRING_GPA_APER_CNTL                                       0x00f5
+#define regBIF_BX_DEV0_EPF0_VF0_1_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX                              2
+#define regBIF_BX_DEV0_EPF0_VF0_1_HDP_REG_COHERENCY_FLUSH_CNTL                                          0x00f6
+#define regBIF_BX_DEV0_EPF0_VF0_1_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX                                 2
+#define regBIF_BX_DEV0_EPF0_VF0_1_HDP_MEM_COHERENCY_FLUSH_CNTL                                          0x00f7
+#define regBIF_BX_DEV0_EPF0_VF0_1_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX                                 2
+#define regBIF_BX_DEV0_EPF0_VF0_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL                                     0x00f9
+#define regBIF_BX_DEV0_EPF0_VF0_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX                            2
+#define regBIF_BX_DEV0_EPF0_VF0_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL                                0x00fa
+#define regBIF_BX_DEV0_EPF0_VF0_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX                       2
+#define regBIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ                                                     0x0106
+#define regBIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ_BASE_IDX                                            2
+#define regBIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE                                                    0x0107
+#define regBIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE_BASE_IDX                                           2
+#define regBIF_BX_DEV0_EPF0_VF0_1_BIF_TRANS_PENDING                                                     0x0108
+#define regBIF_BX_DEV0_EPF0_VF0_1_BIF_TRANS_PENDING_BASE_IDX                                            2
+#define regBIF_BX_DEV0_EPF0_VF0_1_NBIF_GFX_ADDR_LUT_BYPASS                                              0x0112
+#define regBIF_BX_DEV0_EPF0_VF0_1_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX                                     2
+#define regBIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_TRN_DW0                                                0x0136
+#define regBIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX                                       2
+#define regBIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_TRN_DW1                                                0x0137
+#define regBIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX                                       2
+#define regBIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_TRN_DW2                                                0x0138
+#define regBIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX                                       2
+#define regBIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_TRN_DW3                                                0x0139
+#define regBIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX                                       2
+#define regBIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_RCV_DW0                                                0x013a
+#define regBIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX                                       2
+#define regBIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_RCV_DW1                                                0x013b
+#define regBIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX                                       2
+#define regBIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_RCV_DW2                                                0x013c
+#define regBIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX                                       2
+#define regBIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_RCV_DW3                                                0x013d
+#define regBIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX                                       2
+#define regBIF_BX_DEV0_EPF0_VF0_1_MAILBOX_CONTROL                                                       0x013e
+#define regBIF_BX_DEV0_EPF0_VF0_1_MAILBOX_CONTROL_BASE_IDX                                              2
+#define regBIF_BX_DEV0_EPF0_VF0_1_MAILBOX_INT_CNTL                                                      0x013f
+#define regBIF_BX_DEV0_EPF0_VF0_1_MAILBOX_INT_CNTL_BASE_IDX                                             2
+#define regBIF_BX_DEV0_EPF0_VF0_1_BIF_VMHV_MAILBOX                                                      0x0140
+#define regBIF_BX_DEV0_EPF0_VF0_1_BIF_VMHV_MAILBOX_BASE_IDX                                             2
+#define regBIF_BX_DEV0_EPF0_VF0_1_PARTITION_COMPUTE_CAP                                                 0x0161
+#define regBIF_BX_DEV0_EPF0_VF0_1_PARTITION_COMPUTE_CAP_BASE_IDX                                        2
+#define regBIF_BX_DEV0_EPF0_VF0_1_PARTITION_MEM_CAP                                                     0x0162
+#define regBIF_BX_DEV0_EPF0_VF0_1_PARTITION_MEM_CAP_BASE_IDX                                            2
+#define regBIF_BX_DEV0_EPF0_VF0_1_PARTITION_COMPUTE_STATUS                                              0x0163
+#define regBIF_BX_DEV0_EPF0_VF0_1_PARTITION_COMPUTE_STATUS_BASE_IDX                                     2
+#define regBIF_BX_DEV0_EPF0_VF0_1_PARTITION_MEM_STATUS                                                  0x0164
+#define regBIF_BX_DEV0_EPF0_VF0_1_PARTITION_MEM_STATUS_BASE_IDX                                         2
+
+
+// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf0_SYSPFVFDEC:1
+// base address: 0x0
+#define regBIF_BX_DEV0_EPF0_VF0_1_MM_INDEX                                                              0x0000
+#define regBIF_BX_DEV0_EPF0_VF0_1_MM_INDEX_BASE_IDX                                                     0
+#define regBIF_BX_DEV0_EPF0_VF0_1_MM_DATA                                                               0x0001
+#define regBIF_BX_DEV0_EPF0_VF0_1_MM_DATA_BASE_IDX                                                      0
+#define regBIF_BX_DEV0_EPF0_VF0_1_MM_INDEX_HI                                                           0x0006
+#define regBIF_BX_DEV0_EPF0_VF0_1_MM_INDEX_HI_BASE_IDX                                                  0
+
+
+// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf0_BIFPFVFDEC1
+// base address: 0x0
+#define regRCC_DEV0_EPF0_VF0_RCC_ERR_LOG                                                                0x0085
+#define regRCC_DEV0_EPF0_VF0_RCC_ERR_LOG_BASE_IDX                                                       2
+#define regRCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN                                                       0x00c0
+#define regRCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN_BASE_IDX                                              2
+#define regRCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE                                                         0x00c3
+#define regRCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE_BASE_IDX                                                2
+#define regRCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED                                                        0x00c4
+#define regRCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED_BASE_IDX                                               2
+#define regRCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER                                                    0x00c5
+#define regRCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX                                           2
+
+
+// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf0_BIFDEC2
+// base address: 0x0
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO                                                      0x0400
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI                                                      0x0401
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA                                                     0x0402
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA_BASE_IDX                                            3
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL                                                      0x0403
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO                                                      0x0404
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI                                                      0x0405
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA                                                     0x0406
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA_BASE_IDX                                            3
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL                                                      0x0407
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO                                                      0x0408
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI                                                      0x0409
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA                                                     0x040a
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA_BASE_IDX                                            3
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL                                                      0x040b
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_LO                                                      0x040c
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_LO_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_HI                                                      0x040d
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_HI_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_MSG_DATA                                                     0x040e
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_MSG_DATA_BASE_IDX                                            3
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_CONTROL                                                      0x040f
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_CONTROL_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT4_ADDR_LO                                                      0x0410
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT4_ADDR_LO_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT4_ADDR_HI                                                      0x0411
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT4_ADDR_HI_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT4_MSG_DATA                                                     0x0412
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT4_MSG_DATA_BASE_IDX                                            3
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT4_CONTROL                                                      0x0413
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT4_CONTROL_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT5_ADDR_LO                                                      0x0414
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT5_ADDR_LO_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT5_ADDR_HI                                                      0x0415
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT5_ADDR_HI_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT5_MSG_DATA                                                     0x0416
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT5_MSG_DATA_BASE_IDX                                            3
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT5_CONTROL                                                      0x0417
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT5_CONTROL_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT6_ADDR_LO                                                      0x0418
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT6_ADDR_LO_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT6_ADDR_HI                                                      0x0419
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT6_ADDR_HI_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT6_MSG_DATA                                                     0x041a
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT6_MSG_DATA_BASE_IDX                                            3
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT6_CONTROL                                                      0x041b
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT6_CONTROL_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT7_ADDR_LO                                                      0x041c
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT7_ADDR_LO_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT7_ADDR_HI                                                      0x041d
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT7_ADDR_HI_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT7_MSG_DATA                                                     0x041e
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT7_MSG_DATA_BASE_IDX                                            3
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT7_CONTROL                                                      0x041f
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT7_CONTROL_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT8_ADDR_LO                                                      0x0420
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT8_ADDR_LO_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT8_ADDR_HI                                                      0x0421
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT8_ADDR_HI_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT8_MSG_DATA                                                     0x0422
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT8_MSG_DATA_BASE_IDX                                            3
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT8_CONTROL                                                      0x0423
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_VECT8_CONTROL_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_PBA                                                                0x0800
+#define regRCC_DEV0_EPF0_VF0_GFXMSIX_PBA_BASE_IDX                                                       3
+
+
+// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf1_BIFPFVFDEC1
+// base address: 0x10120000
+#define regBIF_BX_DEV0_EPF0_VF1_0_BIF_BME_STATUS                                                        0x8e0b
+#define regBIF_BX_DEV0_EPF0_VF1_0_BIF_BME_STATUS_BASE_IDX                                               5
+#define regBIF_BX_DEV0_EPF0_VF1_0_BIF_ATOMIC_ERR_LOG                                                    0x8e0c
+#define regBIF_BX_DEV0_EPF0_VF1_0_BIF_ATOMIC_ERR_LOG_BASE_IDX                                           5
+#define regBIF_BX_DEV0_EPF0_VF1_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH                                  0x8e13
+#define regBIF_BX_DEV0_EPF0_VF1_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX                         5
+#define regBIF_BX_DEV0_EPF0_VF1_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW                                   0x8e14
+#define regBIF_BX_DEV0_EPF0_VF1_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX                          5
+#define regBIF_BX_DEV0_EPF0_VF1_0_DOORBELL_SELFRING_GPA_APER_CNTL                                       0x8e15
+#define regBIF_BX_DEV0_EPF0_VF1_0_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX                              5
+#define regBIF_BX_DEV0_EPF0_VF1_0_HDP_REG_COHERENCY_FLUSH_CNTL                                          0x8e16
+#define regBIF_BX_DEV0_EPF0_VF1_0_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX                                 5
+#define regBIF_BX_DEV0_EPF0_VF1_0_HDP_MEM_COHERENCY_FLUSH_CNTL                                          0x8e17
+#define regBIF_BX_DEV0_EPF0_VF1_0_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX                                 5
+#define regBIF_BX_DEV0_EPF0_VF1_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL                                     0x8e19
+#define regBIF_BX_DEV0_EPF0_VF1_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX                            5
+#define regBIF_BX_DEV0_EPF0_VF1_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL                                0x8e1a
+#define regBIF_BX_DEV0_EPF0_VF1_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX                       5
+#define regBIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ                                                     0x8e26
+#define regBIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ_BASE_IDX                                            5
+#define regBIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE                                                    0x8e27
+#define regBIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE_BASE_IDX                                           5
+#define regBIF_BX_DEV0_EPF0_VF1_0_BIF_TRANS_PENDING                                                     0x8e28
+#define regBIF_BX_DEV0_EPF0_VF1_0_BIF_TRANS_PENDING_BASE_IDX                                            5
+#define regBIF_BX_DEV0_EPF0_VF1_0_NBIF_GFX_ADDR_LUT_BYPASS                                              0x8e32
+#define regBIF_BX_DEV0_EPF0_VF1_0_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX                                     5
+#define regBIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_TRN_DW0                                                0x8e56
+#define regBIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX                                       5
+#define regBIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_TRN_DW1                                                0x8e57
+#define regBIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX                                       5
+#define regBIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_TRN_DW2                                                0x8e58
+#define regBIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX                                       5
+#define regBIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_TRN_DW3                                                0x8e59
+#define regBIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX                                       5
+#define regBIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_RCV_DW0                                                0x8e5a
+#define regBIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX                                       5
+#define regBIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_RCV_DW1                                                0x8e5b
+#define regBIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX                                       5
+#define regBIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_RCV_DW2                                                0x8e5c
+#define regBIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX                                       5
+#define regBIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_RCV_DW3                                                0x8e5d
+#define regBIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX                                       5
+#define regBIF_BX_DEV0_EPF0_VF1_0_MAILBOX_CONTROL                                                       0x8e5e
+#define regBIF_BX_DEV0_EPF0_VF1_0_MAILBOX_CONTROL_BASE_IDX                                              5
+#define regBIF_BX_DEV0_EPF0_VF1_0_MAILBOX_INT_CNTL                                                      0x8e5f
+#define regBIF_BX_DEV0_EPF0_VF1_0_MAILBOX_INT_CNTL_BASE_IDX                                             5
+#define regBIF_BX_DEV0_EPF0_VF1_0_BIF_VMHV_MAILBOX                                                      0x8e60
+#define regBIF_BX_DEV0_EPF0_VF1_0_BIF_VMHV_MAILBOX_BASE_IDX                                             5
+#define regBIF_BX_DEV0_EPF0_VF1_0_PARTITION_COMPUTE_CAP                                                 0x8e81
+#define regBIF_BX_DEV0_EPF0_VF1_0_PARTITION_COMPUTE_CAP_BASE_IDX                                        5
+#define regBIF_BX_DEV0_EPF0_VF1_0_PARTITION_MEM_CAP                                                     0x8e82
+#define regBIF_BX_DEV0_EPF0_VF1_0_PARTITION_MEM_CAP_BASE_IDX                                            5
+#define regBIF_BX_DEV0_EPF0_VF1_0_PARTITION_COMPUTE_STATUS                                              0x8e83
+#define regBIF_BX_DEV0_EPF0_VF1_0_PARTITION_COMPUTE_STATUS_BASE_IDX                                     5
+#define regBIF_BX_DEV0_EPF0_VF1_0_PARTITION_MEM_STATUS                                                  0x8e84
+#define regBIF_BX_DEV0_EPF0_VF1_0_PARTITION_MEM_STATUS_BASE_IDX                                         5
+
+
+// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf1_SYSPFVFDEC
+// base address: 0x10120000
+#define regBIF_BX_DEV0_EPF0_VF1_0_MM_INDEX                                                              0x8000
+#define regBIF_BX_DEV0_EPF0_VF1_0_MM_INDEX_BASE_IDX                                                     5
+#define regBIF_BX_DEV0_EPF0_VF1_0_MM_DATA                                                               0x8001
+#define regBIF_BX_DEV0_EPF0_VF1_0_MM_DATA_BASE_IDX                                                      5
+#define regBIF_BX_DEV0_EPF0_VF1_0_MM_INDEX_HI                                                           0x8006
+#define regBIF_BX_DEV0_EPF0_VF1_0_MM_INDEX_HI_BASE_IDX                                                  5
+
+
+// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf1_BIFPFVFDEC1:1
+// base address: 0x0
+#define regBIF_BX_DEV0_EPF0_VF1_1_BIF_BME_STATUS                                                        0x00eb
+#define regBIF_BX_DEV0_EPF0_VF1_1_BIF_BME_STATUS_BASE_IDX                                               2
+#define regBIF_BX_DEV0_EPF0_VF1_1_BIF_ATOMIC_ERR_LOG                                                    0x00ec
+#define regBIF_BX_DEV0_EPF0_VF1_1_BIF_ATOMIC_ERR_LOG_BASE_IDX                                           2
+#define regBIF_BX_DEV0_EPF0_VF1_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH                                  0x00f3
+#define regBIF_BX_DEV0_EPF0_VF1_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX                         2
+#define regBIF_BX_DEV0_EPF0_VF1_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW                                   0x00f4
+#define regBIF_BX_DEV0_EPF0_VF1_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX                          2
+#define regBIF_BX_DEV0_EPF0_VF1_1_DOORBELL_SELFRING_GPA_APER_CNTL                                       0x00f5
+#define regBIF_BX_DEV0_EPF0_VF1_1_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX                              2
+#define regBIF_BX_DEV0_EPF0_VF1_1_HDP_REG_COHERENCY_FLUSH_CNTL                                          0x00f6
+#define regBIF_BX_DEV0_EPF0_VF1_1_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX                                 2
+#define regBIF_BX_DEV0_EPF0_VF1_1_HDP_MEM_COHERENCY_FLUSH_CNTL                                          0x00f7
+#define regBIF_BX_DEV0_EPF0_VF1_1_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX                                 2
+#define regBIF_BX_DEV0_EPF0_VF1_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL                                     0x00f9
+#define regBIF_BX_DEV0_EPF0_VF1_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX                            2
+#define regBIF_BX_DEV0_EPF0_VF1_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL                                0x00fa
+#define regBIF_BX_DEV0_EPF0_VF1_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX                       2
+#define regBIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ                                                     0x0106
+#define regBIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ_BASE_IDX                                            2
+#define regBIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE                                                    0x0107
+#define regBIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE_BASE_IDX                                           2
+#define regBIF_BX_DEV0_EPF0_VF1_1_BIF_TRANS_PENDING                                                     0x0108
+#define regBIF_BX_DEV0_EPF0_VF1_1_BIF_TRANS_PENDING_BASE_IDX                                            2
+#define regBIF_BX_DEV0_EPF0_VF1_1_NBIF_GFX_ADDR_LUT_BYPASS                                              0x0112
+#define regBIF_BX_DEV0_EPF0_VF1_1_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX                                     2
+#define regBIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_TRN_DW0                                                0x0136
+#define regBIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX                                       2
+#define regBIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_TRN_DW1                                                0x0137
+#define regBIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX                                       2
+#define regBIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_TRN_DW2                                                0x0138
+#define regBIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX                                       2
+#define regBIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_TRN_DW3                                                0x0139
+#define regBIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX                                       2
+#define regBIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_RCV_DW0                                                0x013a
+#define regBIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX                                       2
+#define regBIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_RCV_DW1                                                0x013b
+#define regBIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX                                       2
+#define regBIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_RCV_DW2                                                0x013c
+#define regBIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX                                       2
+#define regBIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_RCV_DW3                                                0x013d
+#define regBIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX                                       2
+#define regBIF_BX_DEV0_EPF0_VF1_1_MAILBOX_CONTROL                                                       0x013e
+#define regBIF_BX_DEV0_EPF0_VF1_1_MAILBOX_CONTROL_BASE_IDX                                              2
+#define regBIF_BX_DEV0_EPF0_VF1_1_MAILBOX_INT_CNTL                                                      0x013f
+#define regBIF_BX_DEV0_EPF0_VF1_1_MAILBOX_INT_CNTL_BASE_IDX                                             2
+#define regBIF_BX_DEV0_EPF0_VF1_1_BIF_VMHV_MAILBOX                                                      0x0140
+#define regBIF_BX_DEV0_EPF0_VF1_1_BIF_VMHV_MAILBOX_BASE_IDX                                             2
+#define regBIF_BX_DEV0_EPF0_VF1_1_PARTITION_COMPUTE_CAP                                                 0x0161
+#define regBIF_BX_DEV0_EPF0_VF1_1_PARTITION_COMPUTE_CAP_BASE_IDX                                        2
+#define regBIF_BX_DEV0_EPF0_VF1_1_PARTITION_MEM_CAP                                                     0x0162
+#define regBIF_BX_DEV0_EPF0_VF1_1_PARTITION_MEM_CAP_BASE_IDX                                            2
+#define regBIF_BX_DEV0_EPF0_VF1_1_PARTITION_COMPUTE_STATUS                                              0x0163
+#define regBIF_BX_DEV0_EPF0_VF1_1_PARTITION_COMPUTE_STATUS_BASE_IDX                                     2
+#define regBIF_BX_DEV0_EPF0_VF1_1_PARTITION_MEM_STATUS                                                  0x0164
+#define regBIF_BX_DEV0_EPF0_VF1_1_PARTITION_MEM_STATUS_BASE_IDX                                         2
+
+
+// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf1_SYSPFVFDEC:1
+// base address: 0x0
+#define regBIF_BX_DEV0_EPF0_VF1_1_MM_INDEX                                                              0x0000
+#define regBIF_BX_DEV0_EPF0_VF1_1_MM_INDEX_BASE_IDX                                                     0
+#define regBIF_BX_DEV0_EPF0_VF1_1_MM_DATA                                                               0x0001
+#define regBIF_BX_DEV0_EPF0_VF1_1_MM_DATA_BASE_IDX                                                      0
+#define regBIF_BX_DEV0_EPF0_VF1_1_MM_INDEX_HI                                                           0x0006
+#define regBIF_BX_DEV0_EPF0_VF1_1_MM_INDEX_HI_BASE_IDX                                                  0
+
+
+// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf1_BIFPFVFDEC1
+// base address: 0x0
+#define regRCC_DEV0_EPF0_VF1_RCC_ERR_LOG                                                                0x0085
+#define regRCC_DEV0_EPF0_VF1_RCC_ERR_LOG_BASE_IDX                                                       2
+#define regRCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN                                                       0x00c0
+#define regRCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN_BASE_IDX                                              2
+#define regRCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE                                                         0x00c3
+#define regRCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE_BASE_IDX                                                2
+#define regRCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED                                                        0x00c4
+#define regRCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED_BASE_IDX                                               2
+#define regRCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER                                                    0x00c5
+#define regRCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX                                           2
+
+
+// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf1_BIFDEC2
+// base address: 0x0
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO                                                      0x0400
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI                                                      0x0401
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA                                                     0x0402
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA_BASE_IDX                                            3
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL                                                      0x0403
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO                                                      0x0404
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI                                                      0x0405
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA                                                     0x0406
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA_BASE_IDX                                            3
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL                                                      0x0407
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO                                                      0x0408
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI                                                      0x0409
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA                                                     0x040a
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA_BASE_IDX                                            3
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL                                                      0x040b
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_LO                                                      0x040c
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_LO_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_HI                                                      0x040d
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_HI_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_MSG_DATA                                                     0x040e
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_MSG_DATA_BASE_IDX                                            3
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_CONTROL                                                      0x040f
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_CONTROL_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT4_ADDR_LO                                                      0x0410
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT4_ADDR_LO_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT4_ADDR_HI                                                      0x0411
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT4_ADDR_HI_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT4_MSG_DATA                                                     0x0412
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT4_MSG_DATA_BASE_IDX                                            3
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT4_CONTROL                                                      0x0413
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT4_CONTROL_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT5_ADDR_LO                                                      0x0414
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT5_ADDR_LO_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT5_ADDR_HI                                                      0x0415
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT5_ADDR_HI_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT5_MSG_DATA                                                     0x0416
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT5_MSG_DATA_BASE_IDX                                            3
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT5_CONTROL                                                      0x0417
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT5_CONTROL_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT6_ADDR_LO                                                      0x0418
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT6_ADDR_LO_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT6_ADDR_HI                                                      0x0419
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT6_ADDR_HI_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT6_MSG_DATA                                                     0x041a
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT6_MSG_DATA_BASE_IDX                                            3
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT6_CONTROL                                                      0x041b
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT6_CONTROL_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT7_ADDR_LO                                                      0x041c
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT7_ADDR_LO_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT7_ADDR_HI                                                      0x041d
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT7_ADDR_HI_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT7_MSG_DATA                                                     0x041e
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT7_MSG_DATA_BASE_IDX                                            3
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT7_CONTROL                                                      0x041f
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT7_CONTROL_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT8_ADDR_LO                                                      0x0420
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT8_ADDR_LO_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT8_ADDR_HI                                                      0x0421
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT8_ADDR_HI_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT8_MSG_DATA                                                     0x0422
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT8_MSG_DATA_BASE_IDX                                            3
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT8_CONTROL                                                      0x0423
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_VECT8_CONTROL_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_PBA                                                                0x0800
+#define regRCC_DEV0_EPF0_VF1_GFXMSIX_PBA_BASE_IDX                                                       3
+
+
+// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf2_BIFPFVFDEC1
+// base address: 0x10120000
+#define regBIF_BX_DEV0_EPF0_VF2_0_BIF_BME_STATUS                                                        0x8e0b
+#define regBIF_BX_DEV0_EPF0_VF2_0_BIF_BME_STATUS_BASE_IDX                                               5
+#define regBIF_BX_DEV0_EPF0_VF2_0_BIF_ATOMIC_ERR_LOG                                                    0x8e0c
+#define regBIF_BX_DEV0_EPF0_VF2_0_BIF_ATOMIC_ERR_LOG_BASE_IDX                                           5
+#define regBIF_BX_DEV0_EPF0_VF2_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH                                  0x8e13
+#define regBIF_BX_DEV0_EPF0_VF2_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX                         5
+#define regBIF_BX_DEV0_EPF0_VF2_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW                                   0x8e14
+#define regBIF_BX_DEV0_EPF0_VF2_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX                          5
+#define regBIF_BX_DEV0_EPF0_VF2_0_DOORBELL_SELFRING_GPA_APER_CNTL                                       0x8e15
+#define regBIF_BX_DEV0_EPF0_VF2_0_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX                              5
+#define regBIF_BX_DEV0_EPF0_VF2_0_HDP_REG_COHERENCY_FLUSH_CNTL                                          0x8e16
+#define regBIF_BX_DEV0_EPF0_VF2_0_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX                                 5
+#define regBIF_BX_DEV0_EPF0_VF2_0_HDP_MEM_COHERENCY_FLUSH_CNTL                                          0x8e17
+#define regBIF_BX_DEV0_EPF0_VF2_0_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX                                 5
+#define regBIF_BX_DEV0_EPF0_VF2_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL                                     0x8e19
+#define regBIF_BX_DEV0_EPF0_VF2_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX                            5
+#define regBIF_BX_DEV0_EPF0_VF2_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL                                0x8e1a
+#define regBIF_BX_DEV0_EPF0_VF2_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX                       5
+#define regBIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ                                                     0x8e26
+#define regBIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ_BASE_IDX                                            5
+#define regBIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE                                                    0x8e27
+#define regBIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE_BASE_IDX                                           5
+#define regBIF_BX_DEV0_EPF0_VF2_0_BIF_TRANS_PENDING                                                     0x8e28
+#define regBIF_BX_DEV0_EPF0_VF2_0_BIF_TRANS_PENDING_BASE_IDX                                            5
+#define regBIF_BX_DEV0_EPF0_VF2_0_NBIF_GFX_ADDR_LUT_BYPASS                                              0x8e32
+#define regBIF_BX_DEV0_EPF0_VF2_0_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX                                     5
+#define regBIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_TRN_DW0                                                0x8e56
+#define regBIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX                                       5
+#define regBIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_TRN_DW1                                                0x8e57
+#define regBIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX                                       5
+#define regBIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_TRN_DW2                                                0x8e58
+#define regBIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX                                       5
+#define regBIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_TRN_DW3                                                0x8e59
+#define regBIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX                                       5
+#define regBIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_RCV_DW0                                                0x8e5a
+#define regBIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX                                       5
+#define regBIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_RCV_DW1                                                0x8e5b
+#define regBIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX                                       5
+#define regBIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_RCV_DW2                                                0x8e5c
+#define regBIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX                                       5
+#define regBIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_RCV_DW3                                                0x8e5d
+#define regBIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX                                       5
+#define regBIF_BX_DEV0_EPF0_VF2_0_MAILBOX_CONTROL                                                       0x8e5e
+#define regBIF_BX_DEV0_EPF0_VF2_0_MAILBOX_CONTROL_BASE_IDX                                              5
+#define regBIF_BX_DEV0_EPF0_VF2_0_MAILBOX_INT_CNTL                                                      0x8e5f
+#define regBIF_BX_DEV0_EPF0_VF2_0_MAILBOX_INT_CNTL_BASE_IDX                                             5
+#define regBIF_BX_DEV0_EPF0_VF2_0_BIF_VMHV_MAILBOX                                                      0x8e60
+#define regBIF_BX_DEV0_EPF0_VF2_0_BIF_VMHV_MAILBOX_BASE_IDX                                             5
+#define regBIF_BX_DEV0_EPF0_VF2_0_PARTITION_COMPUTE_CAP                                                 0x8e81
+#define regBIF_BX_DEV0_EPF0_VF2_0_PARTITION_COMPUTE_CAP_BASE_IDX                                        5
+#define regBIF_BX_DEV0_EPF0_VF2_0_PARTITION_MEM_CAP                                                     0x8e82
+#define regBIF_BX_DEV0_EPF0_VF2_0_PARTITION_MEM_CAP_BASE_IDX                                            5
+#define regBIF_BX_DEV0_EPF0_VF2_0_PARTITION_COMPUTE_STATUS                                              0x8e83
+#define regBIF_BX_DEV0_EPF0_VF2_0_PARTITION_COMPUTE_STATUS_BASE_IDX                                     5
+#define regBIF_BX_DEV0_EPF0_VF2_0_PARTITION_MEM_STATUS                                                  0x8e84
+#define regBIF_BX_DEV0_EPF0_VF2_0_PARTITION_MEM_STATUS_BASE_IDX                                         5
+
+
+// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf2_SYSPFVFDEC
+// base address: 0x10120000
+#define regBIF_BX_DEV0_EPF0_VF2_0_MM_INDEX                                                              0x8000
+#define regBIF_BX_DEV0_EPF0_VF2_0_MM_INDEX_BASE_IDX                                                     5
+#define regBIF_BX_DEV0_EPF0_VF2_0_MM_DATA                                                               0x8001
+#define regBIF_BX_DEV0_EPF0_VF2_0_MM_DATA_BASE_IDX                                                      5
+#define regBIF_BX_DEV0_EPF0_VF2_0_MM_INDEX_HI                                                           0x8006
+#define regBIF_BX_DEV0_EPF0_VF2_0_MM_INDEX_HI_BASE_IDX                                                  5
+
+
+// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf2_BIFPFVFDEC1:1
+// base address: 0x0
+#define regBIF_BX_DEV0_EPF0_VF2_1_BIF_BME_STATUS                                                        0x00eb
+#define regBIF_BX_DEV0_EPF0_VF2_1_BIF_BME_STATUS_BASE_IDX                                               2
+#define regBIF_BX_DEV0_EPF0_VF2_1_BIF_ATOMIC_ERR_LOG                                                    0x00ec
+#define regBIF_BX_DEV0_EPF0_VF2_1_BIF_ATOMIC_ERR_LOG_BASE_IDX                                           2
+#define regBIF_BX_DEV0_EPF0_VF2_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH                                  0x00f3
+#define regBIF_BX_DEV0_EPF0_VF2_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX                         2
+#define regBIF_BX_DEV0_EPF0_VF2_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW                                   0x00f4
+#define regBIF_BX_DEV0_EPF0_VF2_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX                          2
+#define regBIF_BX_DEV0_EPF0_VF2_1_DOORBELL_SELFRING_GPA_APER_CNTL                                       0x00f5
+#define regBIF_BX_DEV0_EPF0_VF2_1_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX                              2
+#define regBIF_BX_DEV0_EPF0_VF2_1_HDP_REG_COHERENCY_FLUSH_CNTL                                          0x00f6
+#define regBIF_BX_DEV0_EPF0_VF2_1_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX                                 2
+#define regBIF_BX_DEV0_EPF0_VF2_1_HDP_MEM_COHERENCY_FLUSH_CNTL                                          0x00f7
+#define regBIF_BX_DEV0_EPF0_VF2_1_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX                                 2
+#define regBIF_BX_DEV0_EPF0_VF2_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL                                     0x00f9
+#define regBIF_BX_DEV0_EPF0_VF2_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX                            2
+#define regBIF_BX_DEV0_EPF0_VF2_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL                                0x00fa
+#define regBIF_BX_DEV0_EPF0_VF2_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX                       2
+#define regBIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ                                                     0x0106
+#define regBIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ_BASE_IDX                                            2
+#define regBIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE                                                    0x0107
+#define regBIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE_BASE_IDX                                           2
+#define regBIF_BX_DEV0_EPF0_VF2_1_BIF_TRANS_PENDING                                                     0x0108
+#define regBIF_BX_DEV0_EPF0_VF2_1_BIF_TRANS_PENDING_BASE_IDX                                            2
+#define regBIF_BX_DEV0_EPF0_VF2_1_NBIF_GFX_ADDR_LUT_BYPASS                                              0x0112
+#define regBIF_BX_DEV0_EPF0_VF2_1_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX                                     2
+#define regBIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_TRN_DW0                                                0x0136
+#define regBIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX                                       2
+#define regBIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_TRN_DW1                                                0x0137
+#define regBIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX                                       2
+#define regBIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_TRN_DW2                                                0x0138
+#define regBIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX                                       2
+#define regBIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_TRN_DW3                                                0x0139
+#define regBIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX                                       2
+#define regBIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_RCV_DW0                                                0x013a
+#define regBIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX                                       2
+#define regBIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_RCV_DW1                                                0x013b
+#define regBIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX                                       2
+#define regBIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_RCV_DW2                                                0x013c
+#define regBIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX                                       2
+#define regBIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_RCV_DW3                                                0x013d
+#define regBIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX                                       2
+#define regBIF_BX_DEV0_EPF0_VF2_1_MAILBOX_CONTROL                                                       0x013e
+#define regBIF_BX_DEV0_EPF0_VF2_1_MAILBOX_CONTROL_BASE_IDX                                              2
+#define regBIF_BX_DEV0_EPF0_VF2_1_MAILBOX_INT_CNTL                                                      0x013f
+#define regBIF_BX_DEV0_EPF0_VF2_1_MAILBOX_INT_CNTL_BASE_IDX                                             2
+#define regBIF_BX_DEV0_EPF0_VF2_1_BIF_VMHV_MAILBOX                                                      0x0140
+#define regBIF_BX_DEV0_EPF0_VF2_1_BIF_VMHV_MAILBOX_BASE_IDX                                             2
+#define regBIF_BX_DEV0_EPF0_VF2_1_PARTITION_COMPUTE_CAP                                                 0x0161
+#define regBIF_BX_DEV0_EPF0_VF2_1_PARTITION_COMPUTE_CAP_BASE_IDX                                        2
+#define regBIF_BX_DEV0_EPF0_VF2_1_PARTITION_MEM_CAP                                                     0x0162
+#define regBIF_BX_DEV0_EPF0_VF2_1_PARTITION_MEM_CAP_BASE_IDX                                            2
+#define regBIF_BX_DEV0_EPF0_VF2_1_PARTITION_COMPUTE_STATUS                                              0x0163
+#define regBIF_BX_DEV0_EPF0_VF2_1_PARTITION_COMPUTE_STATUS_BASE_IDX                                     2
+#define regBIF_BX_DEV0_EPF0_VF2_1_PARTITION_MEM_STATUS                                                  0x0164
+#define regBIF_BX_DEV0_EPF0_VF2_1_PARTITION_MEM_STATUS_BASE_IDX                                         2
+
+
+// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf2_SYSPFVFDEC:1
+// base address: 0x0
+#define regBIF_BX_DEV0_EPF0_VF2_1_MM_INDEX                                                              0x0000
+#define regBIF_BX_DEV0_EPF0_VF2_1_MM_INDEX_BASE_IDX                                                     0
+#define regBIF_BX_DEV0_EPF0_VF2_1_MM_DATA                                                               0x0001
+#define regBIF_BX_DEV0_EPF0_VF2_1_MM_DATA_BASE_IDX                                                      0
+#define regBIF_BX_DEV0_EPF0_VF2_1_MM_INDEX_HI                                                           0x0006
+#define regBIF_BX_DEV0_EPF0_VF2_1_MM_INDEX_HI_BASE_IDX                                                  0
+
+
+// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf2_BIFPFVFDEC1
+// base address: 0x0
+#define regRCC_DEV0_EPF0_VF2_RCC_ERR_LOG                                                                0x0085
+#define regRCC_DEV0_EPF0_VF2_RCC_ERR_LOG_BASE_IDX                                                       2
+#define regRCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN                                                       0x00c0
+#define regRCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN_BASE_IDX                                              2
+#define regRCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE                                                         0x00c3
+#define regRCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE_BASE_IDX                                                2
+#define regRCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED                                                        0x00c4
+#define regRCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED_BASE_IDX                                               2
+#define regRCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER                                                    0x00c5
+#define regRCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX                                           2
+
+
+// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf2_BIFDEC2
+// base address: 0x0
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO                                                      0x0400
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI                                                      0x0401
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA                                                     0x0402
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA_BASE_IDX                                            3
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL                                                      0x0403
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO                                                      0x0404
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI                                                      0x0405
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA                                                     0x0406
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA_BASE_IDX                                            3
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL                                                      0x0407
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO                                                      0x0408
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI                                                      0x0409
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA                                                     0x040a
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA_BASE_IDX                                            3
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL                                                      0x040b
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_LO                                                      0x040c
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_LO_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_HI                                                      0x040d
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_HI_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_MSG_DATA                                                     0x040e
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_MSG_DATA_BASE_IDX                                            3
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_CONTROL                                                      0x040f
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_CONTROL_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT4_ADDR_LO                                                      0x0410
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT4_ADDR_LO_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT4_ADDR_HI                                                      0x0411
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT4_ADDR_HI_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT4_MSG_DATA                                                     0x0412
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT4_MSG_DATA_BASE_IDX                                            3
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT4_CONTROL                                                      0x0413
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT4_CONTROL_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT5_ADDR_LO                                                      0x0414
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT5_ADDR_LO_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT5_ADDR_HI                                                      0x0415
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT5_ADDR_HI_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT5_MSG_DATA                                                     0x0416
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT5_MSG_DATA_BASE_IDX                                            3
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT5_CONTROL                                                      0x0417
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT5_CONTROL_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT6_ADDR_LO                                                      0x0418
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT6_ADDR_LO_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT6_ADDR_HI                                                      0x0419
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT6_ADDR_HI_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT6_MSG_DATA                                                     0x041a
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT6_MSG_DATA_BASE_IDX                                            3
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT6_CONTROL                                                      0x041b
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT6_CONTROL_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT7_ADDR_LO                                                      0x041c
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT7_ADDR_LO_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT7_ADDR_HI                                                      0x041d
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT7_ADDR_HI_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT7_MSG_DATA                                                     0x041e
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT7_MSG_DATA_BASE_IDX                                            3
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT7_CONTROL                                                      0x041f
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT7_CONTROL_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT8_ADDR_LO                                                      0x0420
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT8_ADDR_LO_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT8_ADDR_HI                                                      0x0421
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT8_ADDR_HI_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT8_MSG_DATA                                                     0x0422
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT8_MSG_DATA_BASE_IDX                                            3
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT8_CONTROL                                                      0x0423
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_VECT8_CONTROL_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_PBA                                                                0x0800
+#define regRCC_DEV0_EPF0_VF2_GFXMSIX_PBA_BASE_IDX                                                       3
+
+
+// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf3_BIFPFVFDEC1
+// base address: 0x10120000
+#define regBIF_BX_DEV0_EPF0_VF3_0_BIF_BME_STATUS                                                        0x8e0b
+#define regBIF_BX_DEV0_EPF0_VF3_0_BIF_BME_STATUS_BASE_IDX                                               5
+#define regBIF_BX_DEV0_EPF0_VF3_0_BIF_ATOMIC_ERR_LOG                                                    0x8e0c
+#define regBIF_BX_DEV0_EPF0_VF3_0_BIF_ATOMIC_ERR_LOG_BASE_IDX                                           5
+#define regBIF_BX_DEV0_EPF0_VF3_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH                                  0x8e13
+#define regBIF_BX_DEV0_EPF0_VF3_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX                         5
+#define regBIF_BX_DEV0_EPF0_VF3_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW                                   0x8e14
+#define regBIF_BX_DEV0_EPF0_VF3_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX                          5
+#define regBIF_BX_DEV0_EPF0_VF3_0_DOORBELL_SELFRING_GPA_APER_CNTL                                       0x8e15
+#define regBIF_BX_DEV0_EPF0_VF3_0_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX                              5
+#define regBIF_BX_DEV0_EPF0_VF3_0_HDP_REG_COHERENCY_FLUSH_CNTL                                          0x8e16
+#define regBIF_BX_DEV0_EPF0_VF3_0_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX                                 5
+#define regBIF_BX_DEV0_EPF0_VF3_0_HDP_MEM_COHERENCY_FLUSH_CNTL                                          0x8e17
+#define regBIF_BX_DEV0_EPF0_VF3_0_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX                                 5
+#define regBIF_BX_DEV0_EPF0_VF3_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL                                     0x8e19
+#define regBIF_BX_DEV0_EPF0_VF3_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX                            5
+#define regBIF_BX_DEV0_EPF0_VF3_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL                                0x8e1a
+#define regBIF_BX_DEV0_EPF0_VF3_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX                       5
+#define regBIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ                                                     0x8e26
+#define regBIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ_BASE_IDX                                            5
+#define regBIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE                                                    0x8e27
+#define regBIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE_BASE_IDX                                           5
+#define regBIF_BX_DEV0_EPF0_VF3_0_BIF_TRANS_PENDING                                                     0x8e28
+#define regBIF_BX_DEV0_EPF0_VF3_0_BIF_TRANS_PENDING_BASE_IDX                                            5
+#define regBIF_BX_DEV0_EPF0_VF3_0_NBIF_GFX_ADDR_LUT_BYPASS                                              0x8e32
+#define regBIF_BX_DEV0_EPF0_VF3_0_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX                                     5
+#define regBIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_TRN_DW0                                                0x8e56
+#define regBIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX                                       5
+#define regBIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_TRN_DW1                                                0x8e57
+#define regBIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX                                       5
+#define regBIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_TRN_DW2                                                0x8e58
+#define regBIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX                                       5
+#define regBIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_TRN_DW3                                                0x8e59
+#define regBIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX                                       5
+#define regBIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_RCV_DW0                                                0x8e5a
+#define regBIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX                                       5
+#define regBIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_RCV_DW1                                                0x8e5b
+#define regBIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX                                       5
+#define regBIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_RCV_DW2                                                0x8e5c
+#define regBIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX                                       5
+#define regBIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_RCV_DW3                                                0x8e5d
+#define regBIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX                                       5
+#define regBIF_BX_DEV0_EPF0_VF3_0_MAILBOX_CONTROL                                                       0x8e5e
+#define regBIF_BX_DEV0_EPF0_VF3_0_MAILBOX_CONTROL_BASE_IDX                                              5
+#define regBIF_BX_DEV0_EPF0_VF3_0_MAILBOX_INT_CNTL                                                      0x8e5f
+#define regBIF_BX_DEV0_EPF0_VF3_0_MAILBOX_INT_CNTL_BASE_IDX                                             5
+#define regBIF_BX_DEV0_EPF0_VF3_0_BIF_VMHV_MAILBOX                                                      0x8e60
+#define regBIF_BX_DEV0_EPF0_VF3_0_BIF_VMHV_MAILBOX_BASE_IDX                                             5
+#define regBIF_BX_DEV0_EPF0_VF3_0_PARTITION_COMPUTE_CAP                                                 0x8e81
+#define regBIF_BX_DEV0_EPF0_VF3_0_PARTITION_COMPUTE_CAP_BASE_IDX                                        5
+#define regBIF_BX_DEV0_EPF0_VF3_0_PARTITION_MEM_CAP                                                     0x8e82
+#define regBIF_BX_DEV0_EPF0_VF3_0_PARTITION_MEM_CAP_BASE_IDX                                            5
+#define regBIF_BX_DEV0_EPF0_VF3_0_PARTITION_COMPUTE_STATUS                                              0x8e83
+#define regBIF_BX_DEV0_EPF0_VF3_0_PARTITION_COMPUTE_STATUS_BASE_IDX                                     5
+#define regBIF_BX_DEV0_EPF0_VF3_0_PARTITION_MEM_STATUS                                                  0x8e84
+#define regBIF_BX_DEV0_EPF0_VF3_0_PARTITION_MEM_STATUS_BASE_IDX                                         5
+
+
+// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf3_SYSPFVFDEC
+// base address: 0x10120000
+#define regBIF_BX_DEV0_EPF0_VF3_0_MM_INDEX                                                              0x8000
+#define regBIF_BX_DEV0_EPF0_VF3_0_MM_INDEX_BASE_IDX                                                     5
+#define regBIF_BX_DEV0_EPF0_VF3_0_MM_DATA                                                               0x8001
+#define regBIF_BX_DEV0_EPF0_VF3_0_MM_DATA_BASE_IDX                                                      5
+#define regBIF_BX_DEV0_EPF0_VF3_0_MM_INDEX_HI                                                           0x8006
+#define regBIF_BX_DEV0_EPF0_VF3_0_MM_INDEX_HI_BASE_IDX                                                  5
+
+
+// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf3_BIFPFVFDEC1:1
+// base address: 0x0
+#define regBIF_BX_DEV0_EPF0_VF3_1_BIF_BME_STATUS                                                        0x00eb
+#define regBIF_BX_DEV0_EPF0_VF3_1_BIF_BME_STATUS_BASE_IDX                                               2
+#define regBIF_BX_DEV0_EPF0_VF3_1_BIF_ATOMIC_ERR_LOG                                                    0x00ec
+#define regBIF_BX_DEV0_EPF0_VF3_1_BIF_ATOMIC_ERR_LOG_BASE_IDX                                           2
+#define regBIF_BX_DEV0_EPF0_VF3_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH                                  0x00f3
+#define regBIF_BX_DEV0_EPF0_VF3_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX                         2
+#define regBIF_BX_DEV0_EPF0_VF3_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW                                   0x00f4
+#define regBIF_BX_DEV0_EPF0_VF3_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX                          2
+#define regBIF_BX_DEV0_EPF0_VF3_1_DOORBELL_SELFRING_GPA_APER_CNTL                                       0x00f5
+#define regBIF_BX_DEV0_EPF0_VF3_1_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX                              2
+#define regBIF_BX_DEV0_EPF0_VF3_1_HDP_REG_COHERENCY_FLUSH_CNTL                                          0x00f6
+#define regBIF_BX_DEV0_EPF0_VF3_1_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX                                 2
+#define regBIF_BX_DEV0_EPF0_VF3_1_HDP_MEM_COHERENCY_FLUSH_CNTL                                          0x00f7
+#define regBIF_BX_DEV0_EPF0_VF3_1_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX                                 2
+#define regBIF_BX_DEV0_EPF0_VF3_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL                                     0x00f9
+#define regBIF_BX_DEV0_EPF0_VF3_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX                            2
+#define regBIF_BX_DEV0_EPF0_VF3_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL                                0x00fa
+#define regBIF_BX_DEV0_EPF0_VF3_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX                       2
+#define regBIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ                                                     0x0106
+#define regBIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ_BASE_IDX                                            2
+#define regBIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE                                                    0x0107
+#define regBIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE_BASE_IDX                                           2
+#define regBIF_BX_DEV0_EPF0_VF3_1_BIF_TRANS_PENDING                                                     0x0108
+#define regBIF_BX_DEV0_EPF0_VF3_1_BIF_TRANS_PENDING_BASE_IDX                                            2
+#define regBIF_BX_DEV0_EPF0_VF3_1_NBIF_GFX_ADDR_LUT_BYPASS                                              0x0112
+#define regBIF_BX_DEV0_EPF0_VF3_1_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX                                     2
+#define regBIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_TRN_DW0                                                0x0136
+#define regBIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX                                       2
+#define regBIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_TRN_DW1                                                0x0137
+#define regBIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX                                       2
+#define regBIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_TRN_DW2                                                0x0138
+#define regBIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX                                       2
+#define regBIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_TRN_DW3                                                0x0139
+#define regBIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX                                       2
+#define regBIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_RCV_DW0                                                0x013a
+#define regBIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX                                       2
+#define regBIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_RCV_DW1                                                0x013b
+#define regBIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX                                       2
+#define regBIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_RCV_DW2                                                0x013c
+#define regBIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX                                       2
+#define regBIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_RCV_DW3                                                0x013d
+#define regBIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX                                       2
+#define regBIF_BX_DEV0_EPF0_VF3_1_MAILBOX_CONTROL                                                       0x013e
+#define regBIF_BX_DEV0_EPF0_VF3_1_MAILBOX_CONTROL_BASE_IDX                                              2
+#define regBIF_BX_DEV0_EPF0_VF3_1_MAILBOX_INT_CNTL                                                      0x013f
+#define regBIF_BX_DEV0_EPF0_VF3_1_MAILBOX_INT_CNTL_BASE_IDX                                             2
+#define regBIF_BX_DEV0_EPF0_VF3_1_BIF_VMHV_MAILBOX                                                      0x0140
+#define regBIF_BX_DEV0_EPF0_VF3_1_BIF_VMHV_MAILBOX_BASE_IDX                                             2
+#define regBIF_BX_DEV0_EPF0_VF3_1_PARTITION_COMPUTE_CAP                                                 0x0161
+#define regBIF_BX_DEV0_EPF0_VF3_1_PARTITION_COMPUTE_CAP_BASE_IDX                                        2
+#define regBIF_BX_DEV0_EPF0_VF3_1_PARTITION_MEM_CAP                                                     0x0162
+#define regBIF_BX_DEV0_EPF0_VF3_1_PARTITION_MEM_CAP_BASE_IDX                                            2
+#define regBIF_BX_DEV0_EPF0_VF3_1_PARTITION_COMPUTE_STATUS                                              0x0163
+#define regBIF_BX_DEV0_EPF0_VF3_1_PARTITION_COMPUTE_STATUS_BASE_IDX                                     2
+#define regBIF_BX_DEV0_EPF0_VF3_1_PARTITION_MEM_STATUS                                                  0x0164
+#define regBIF_BX_DEV0_EPF0_VF3_1_PARTITION_MEM_STATUS_BASE_IDX                                         2
+
+
+// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf3_SYSPFVFDEC:1
+// base address: 0x0
+#define regBIF_BX_DEV0_EPF0_VF3_1_MM_INDEX                                                              0x0000
+#define regBIF_BX_DEV0_EPF0_VF3_1_MM_INDEX_BASE_IDX                                                     0
+#define regBIF_BX_DEV0_EPF0_VF3_1_MM_DATA                                                               0x0001
+#define regBIF_BX_DEV0_EPF0_VF3_1_MM_DATA_BASE_IDX                                                      0
+#define regBIF_BX_DEV0_EPF0_VF3_1_MM_INDEX_HI                                                           0x0006
+#define regBIF_BX_DEV0_EPF0_VF3_1_MM_INDEX_HI_BASE_IDX                                                  0
+
+
+// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf3_BIFPFVFDEC1
+// base address: 0x0
+#define regRCC_DEV0_EPF0_VF3_RCC_ERR_LOG                                                                0x0085
+#define regRCC_DEV0_EPF0_VF3_RCC_ERR_LOG_BASE_IDX                                                       2
+#define regRCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN                                                       0x00c0
+#define regRCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN_BASE_IDX                                              2
+#define regRCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE                                                         0x00c3
+#define regRCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE_BASE_IDX                                                2
+#define regRCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED                                                        0x00c4
+#define regRCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED_BASE_IDX                                               2
+#define regRCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER                                                    0x00c5
+#define regRCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX                                           2
+
+
+// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf3_BIFDEC2
+// base address: 0x0
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO                                                      0x0400
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI                                                      0x0401
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA                                                     0x0402
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA_BASE_IDX                                            3
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL                                                      0x0403
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO                                                      0x0404
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI                                                      0x0405
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA                                                     0x0406
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA_BASE_IDX                                            3
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL                                                      0x0407
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO                                                      0x0408
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI                                                      0x0409
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA                                                     0x040a
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA_BASE_IDX                                            3
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL                                                      0x040b
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_LO                                                      0x040c
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_LO_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_HI                                                      0x040d
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_HI_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_MSG_DATA                                                     0x040e
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_MSG_DATA_BASE_IDX                                            3
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_CONTROL                                                      0x040f
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_CONTROL_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT4_ADDR_LO                                                      0x0410
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT4_ADDR_LO_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT4_ADDR_HI                                                      0x0411
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT4_ADDR_HI_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT4_MSG_DATA                                                     0x0412
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT4_MSG_DATA_BASE_IDX                                            3
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT4_CONTROL                                                      0x0413
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT4_CONTROL_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT5_ADDR_LO                                                      0x0414
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT5_ADDR_LO_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT5_ADDR_HI                                                      0x0415
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT5_ADDR_HI_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT5_MSG_DATA                                                     0x0416
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT5_MSG_DATA_BASE_IDX                                            3
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT5_CONTROL                                                      0x0417
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT5_CONTROL_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT6_ADDR_LO                                                      0x0418
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT6_ADDR_LO_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT6_ADDR_HI                                                      0x0419
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT6_ADDR_HI_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT6_MSG_DATA                                                     0x041a
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT6_MSG_DATA_BASE_IDX                                            3
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT6_CONTROL                                                      0x041b
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT6_CONTROL_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT7_ADDR_LO                                                      0x041c
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT7_ADDR_LO_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT7_ADDR_HI                                                      0x041d
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT7_ADDR_HI_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT7_MSG_DATA                                                     0x041e
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT7_MSG_DATA_BASE_IDX                                            3
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT7_CONTROL                                                      0x041f
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT7_CONTROL_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT8_ADDR_LO                                                      0x0420
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT8_ADDR_LO_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT8_ADDR_HI                                                      0x0421
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT8_ADDR_HI_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT8_MSG_DATA                                                     0x0422
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT8_MSG_DATA_BASE_IDX                                            3
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT8_CONTROL                                                      0x0423
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_VECT8_CONTROL_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_PBA                                                                0x0800
+#define regRCC_DEV0_EPF0_VF3_GFXMSIX_PBA_BASE_IDX                                                       3
+
+
+// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf4_BIFPFVFDEC1
+// base address: 0x10120000
+#define regBIF_BX_DEV0_EPF0_VF4_0_BIF_BME_STATUS                                                        0x8e0b
+#define regBIF_BX_DEV0_EPF0_VF4_0_BIF_BME_STATUS_BASE_IDX                                               5
+#define regBIF_BX_DEV0_EPF0_VF4_0_BIF_ATOMIC_ERR_LOG                                                    0x8e0c
+#define regBIF_BX_DEV0_EPF0_VF4_0_BIF_ATOMIC_ERR_LOG_BASE_IDX                                           5
+#define regBIF_BX_DEV0_EPF0_VF4_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH                                  0x8e13
+#define regBIF_BX_DEV0_EPF0_VF4_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX                         5
+#define regBIF_BX_DEV0_EPF0_VF4_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW                                   0x8e14
+#define regBIF_BX_DEV0_EPF0_VF4_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX                          5
+#define regBIF_BX_DEV0_EPF0_VF4_0_DOORBELL_SELFRING_GPA_APER_CNTL                                       0x8e15
+#define regBIF_BX_DEV0_EPF0_VF4_0_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX                              5
+#define regBIF_BX_DEV0_EPF0_VF4_0_HDP_REG_COHERENCY_FLUSH_CNTL                                          0x8e16
+#define regBIF_BX_DEV0_EPF0_VF4_0_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX                                 5
+#define regBIF_BX_DEV0_EPF0_VF4_0_HDP_MEM_COHERENCY_FLUSH_CNTL                                          0x8e17
+#define regBIF_BX_DEV0_EPF0_VF4_0_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX                                 5
+#define regBIF_BX_DEV0_EPF0_VF4_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL                                     0x8e19
+#define regBIF_BX_DEV0_EPF0_VF4_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX                            5
+#define regBIF_BX_DEV0_EPF0_VF4_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL                                0x8e1a
+#define regBIF_BX_DEV0_EPF0_VF4_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX                       5
+#define regBIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ                                                     0x8e26
+#define regBIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ_BASE_IDX                                            5
+#define regBIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE                                                    0x8e27
+#define regBIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE_BASE_IDX                                           5
+#define regBIF_BX_DEV0_EPF0_VF4_0_BIF_TRANS_PENDING                                                     0x8e28
+#define regBIF_BX_DEV0_EPF0_VF4_0_BIF_TRANS_PENDING_BASE_IDX                                            5
+#define regBIF_BX_DEV0_EPF0_VF4_0_NBIF_GFX_ADDR_LUT_BYPASS                                              0x8e32
+#define regBIF_BX_DEV0_EPF0_VF4_0_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX                                     5
+#define regBIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_TRN_DW0                                                0x8e56
+#define regBIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX                                       5
+#define regBIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_TRN_DW1                                                0x8e57
+#define regBIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX                                       5
+#define regBIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_TRN_DW2                                                0x8e58
+#define regBIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX                                       5
+#define regBIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_TRN_DW3                                                0x8e59
+#define regBIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX                                       5
+#define regBIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_RCV_DW0                                                0x8e5a
+#define regBIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX                                       5
+#define regBIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_RCV_DW1                                                0x8e5b
+#define regBIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX                                       5
+#define regBIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_RCV_DW2                                                0x8e5c
+#define regBIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX                                       5
+#define regBIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_RCV_DW3                                                0x8e5d
+#define regBIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX                                       5
+#define regBIF_BX_DEV0_EPF0_VF4_0_MAILBOX_CONTROL                                                       0x8e5e
+#define regBIF_BX_DEV0_EPF0_VF4_0_MAILBOX_CONTROL_BASE_IDX                                              5
+#define regBIF_BX_DEV0_EPF0_VF4_0_MAILBOX_INT_CNTL                                                      0x8e5f
+#define regBIF_BX_DEV0_EPF0_VF4_0_MAILBOX_INT_CNTL_BASE_IDX                                             5
+#define regBIF_BX_DEV0_EPF0_VF4_0_BIF_VMHV_MAILBOX                                                      0x8e60
+#define regBIF_BX_DEV0_EPF0_VF4_0_BIF_VMHV_MAILBOX_BASE_IDX                                             5
+#define regBIF_BX_DEV0_EPF0_VF4_0_PARTITION_COMPUTE_CAP                                                 0x8e81
+#define regBIF_BX_DEV0_EPF0_VF4_0_PARTITION_COMPUTE_CAP_BASE_IDX                                        5
+#define regBIF_BX_DEV0_EPF0_VF4_0_PARTITION_MEM_CAP                                                     0x8e82
+#define regBIF_BX_DEV0_EPF0_VF4_0_PARTITION_MEM_CAP_BASE_IDX                                            5
+#define regBIF_BX_DEV0_EPF0_VF4_0_PARTITION_COMPUTE_STATUS                                              0x8e83
+#define regBIF_BX_DEV0_EPF0_VF4_0_PARTITION_COMPUTE_STATUS_BASE_IDX                                     5
+#define regBIF_BX_DEV0_EPF0_VF4_0_PARTITION_MEM_STATUS                                                  0x8e84
+#define regBIF_BX_DEV0_EPF0_VF4_0_PARTITION_MEM_STATUS_BASE_IDX                                         5
+
+
+// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf4_SYSPFVFDEC
+// base address: 0x10120000
+#define regBIF_BX_DEV0_EPF0_VF4_0_MM_INDEX                                                              0x8000
+#define regBIF_BX_DEV0_EPF0_VF4_0_MM_INDEX_BASE_IDX                                                     5
+#define regBIF_BX_DEV0_EPF0_VF4_0_MM_DATA                                                               0x8001
+#define regBIF_BX_DEV0_EPF0_VF4_0_MM_DATA_BASE_IDX                                                      5
+#define regBIF_BX_DEV0_EPF0_VF4_0_MM_INDEX_HI                                                           0x8006
+#define regBIF_BX_DEV0_EPF0_VF4_0_MM_INDEX_HI_BASE_IDX                                                  5
+
+
+// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf4_BIFPFVFDEC1:1
+// base address: 0x0
+#define regBIF_BX_DEV0_EPF0_VF4_1_BIF_BME_STATUS                                                        0x00eb
+#define regBIF_BX_DEV0_EPF0_VF4_1_BIF_BME_STATUS_BASE_IDX                                               2
+#define regBIF_BX_DEV0_EPF0_VF4_1_BIF_ATOMIC_ERR_LOG                                                    0x00ec
+#define regBIF_BX_DEV0_EPF0_VF4_1_BIF_ATOMIC_ERR_LOG_BASE_IDX                                           2
+#define regBIF_BX_DEV0_EPF0_VF4_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH                                  0x00f3
+#define regBIF_BX_DEV0_EPF0_VF4_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX                         2
+#define regBIF_BX_DEV0_EPF0_VF4_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW                                   0x00f4
+#define regBIF_BX_DEV0_EPF0_VF4_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX                          2
+#define regBIF_BX_DEV0_EPF0_VF4_1_DOORBELL_SELFRING_GPA_APER_CNTL                                       0x00f5
+#define regBIF_BX_DEV0_EPF0_VF4_1_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX                              2
+#define regBIF_BX_DEV0_EPF0_VF4_1_HDP_REG_COHERENCY_FLUSH_CNTL                                          0x00f6
+#define regBIF_BX_DEV0_EPF0_VF4_1_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX                                 2
+#define regBIF_BX_DEV0_EPF0_VF4_1_HDP_MEM_COHERENCY_FLUSH_CNTL                                          0x00f7
+#define regBIF_BX_DEV0_EPF0_VF4_1_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX                                 2
+#define regBIF_BX_DEV0_EPF0_VF4_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL                                     0x00f9
+#define regBIF_BX_DEV0_EPF0_VF4_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX                            2
+#define regBIF_BX_DEV0_EPF0_VF4_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL                                0x00fa
+#define regBIF_BX_DEV0_EPF0_VF4_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX                       2
+#define regBIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ                                                     0x0106
+#define regBIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ_BASE_IDX                                            2
+#define regBIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE                                                    0x0107
+#define regBIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE_BASE_IDX                                           2
+#define regBIF_BX_DEV0_EPF0_VF4_1_BIF_TRANS_PENDING                                                     0x0108
+#define regBIF_BX_DEV0_EPF0_VF4_1_BIF_TRANS_PENDING_BASE_IDX                                            2
+#define regBIF_BX_DEV0_EPF0_VF4_1_NBIF_GFX_ADDR_LUT_BYPASS                                              0x0112
+#define regBIF_BX_DEV0_EPF0_VF4_1_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX                                     2
+#define regBIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_TRN_DW0                                                0x0136
+#define regBIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX                                       2
+#define regBIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_TRN_DW1                                                0x0137
+#define regBIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX                                       2
+#define regBIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_TRN_DW2                                                0x0138
+#define regBIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX                                       2
+#define regBIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_TRN_DW3                                                0x0139
+#define regBIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX                                       2
+#define regBIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_RCV_DW0                                                0x013a
+#define regBIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX                                       2
+#define regBIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_RCV_DW1                                                0x013b
+#define regBIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX                                       2
+#define regBIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_RCV_DW2                                                0x013c
+#define regBIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX                                       2
+#define regBIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_RCV_DW3                                                0x013d
+#define regBIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX                                       2
+#define regBIF_BX_DEV0_EPF0_VF4_1_MAILBOX_CONTROL                                                       0x013e
+#define regBIF_BX_DEV0_EPF0_VF4_1_MAILBOX_CONTROL_BASE_IDX                                              2
+#define regBIF_BX_DEV0_EPF0_VF4_1_MAILBOX_INT_CNTL                                                      0x013f
+#define regBIF_BX_DEV0_EPF0_VF4_1_MAILBOX_INT_CNTL_BASE_IDX                                             2
+#define regBIF_BX_DEV0_EPF0_VF4_1_BIF_VMHV_MAILBOX                                                      0x0140
+#define regBIF_BX_DEV0_EPF0_VF4_1_BIF_VMHV_MAILBOX_BASE_IDX                                             2
+#define regBIF_BX_DEV0_EPF0_VF4_1_PARTITION_COMPUTE_CAP                                                 0x0161
+#define regBIF_BX_DEV0_EPF0_VF4_1_PARTITION_COMPUTE_CAP_BASE_IDX                                        2
+#define regBIF_BX_DEV0_EPF0_VF4_1_PARTITION_MEM_CAP                                                     0x0162
+#define regBIF_BX_DEV0_EPF0_VF4_1_PARTITION_MEM_CAP_BASE_IDX                                            2
+#define regBIF_BX_DEV0_EPF0_VF4_1_PARTITION_COMPUTE_STATUS                                              0x0163
+#define regBIF_BX_DEV0_EPF0_VF4_1_PARTITION_COMPUTE_STATUS_BASE_IDX                                     2
+#define regBIF_BX_DEV0_EPF0_VF4_1_PARTITION_MEM_STATUS                                                  0x0164
+#define regBIF_BX_DEV0_EPF0_VF4_1_PARTITION_MEM_STATUS_BASE_IDX                                         2
+
+
+// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf4_SYSPFVFDEC:1
+// base address: 0x0
+#define regBIF_BX_DEV0_EPF0_VF4_1_MM_INDEX                                                              0x0000
+#define regBIF_BX_DEV0_EPF0_VF4_1_MM_INDEX_BASE_IDX                                                     0
+#define regBIF_BX_DEV0_EPF0_VF4_1_MM_DATA                                                               0x0001
+#define regBIF_BX_DEV0_EPF0_VF4_1_MM_DATA_BASE_IDX                                                      0
+#define regBIF_BX_DEV0_EPF0_VF4_1_MM_INDEX_HI                                                           0x0006
+#define regBIF_BX_DEV0_EPF0_VF4_1_MM_INDEX_HI_BASE_IDX                                                  0
+
+
+// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf4_BIFPFVFDEC1
+// base address: 0x0
+#define regRCC_DEV0_EPF0_VF4_RCC_ERR_LOG                                                                0x0085
+#define regRCC_DEV0_EPF0_VF4_RCC_ERR_LOG_BASE_IDX                                                       2
+#define regRCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN                                                       0x00c0
+#define regRCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN_BASE_IDX                                              2
+#define regRCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE                                                         0x00c3
+#define regRCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE_BASE_IDX                                                2
+#define regRCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED                                                        0x00c4
+#define regRCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED_BASE_IDX                                               2
+#define regRCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER                                                    0x00c5
+#define regRCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX                                           2
+
+
+// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf4_BIFDEC2
+// base address: 0x0
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO                                                      0x0400
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI                                                      0x0401
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA                                                     0x0402
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA_BASE_IDX                                            3
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL                                                      0x0403
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO                                                      0x0404
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI                                                      0x0405
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA                                                     0x0406
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA_BASE_IDX                                            3
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL                                                      0x0407
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO                                                      0x0408
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI                                                      0x0409
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA                                                     0x040a
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA_BASE_IDX                                            3
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL                                                      0x040b
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_LO                                                      0x040c
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_LO_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_HI                                                      0x040d
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_HI_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_MSG_DATA                                                     0x040e
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_MSG_DATA_BASE_IDX                                            3
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_CONTROL                                                      0x040f
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_CONTROL_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT4_ADDR_LO                                                      0x0410
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT4_ADDR_LO_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT4_ADDR_HI                                                      0x0411
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT4_ADDR_HI_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT4_MSG_DATA                                                     0x0412
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT4_MSG_DATA_BASE_IDX                                            3
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT4_CONTROL                                                      0x0413
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT4_CONTROL_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT5_ADDR_LO                                                      0x0414
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT5_ADDR_LO_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT5_ADDR_HI                                                      0x0415
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT5_ADDR_HI_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT5_MSG_DATA                                                     0x0416
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT5_MSG_DATA_BASE_IDX                                            3
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT5_CONTROL                                                      0x0417
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT5_CONTROL_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT6_ADDR_LO                                                      0x0418
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT6_ADDR_LO_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT6_ADDR_HI                                                      0x0419
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT6_ADDR_HI_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT6_MSG_DATA                                                     0x041a
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT6_MSG_DATA_BASE_IDX                                            3
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT6_CONTROL                                                      0x041b
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT6_CONTROL_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT7_ADDR_LO                                                      0x041c
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT7_ADDR_LO_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT7_ADDR_HI                                                      0x041d
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT7_ADDR_HI_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT7_MSG_DATA                                                     0x041e
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT7_MSG_DATA_BASE_IDX                                            3
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT7_CONTROL                                                      0x041f
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT7_CONTROL_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT8_ADDR_LO                                                      0x0420
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT8_ADDR_LO_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT8_ADDR_HI                                                      0x0421
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT8_ADDR_HI_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT8_MSG_DATA                                                     0x0422
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT8_MSG_DATA_BASE_IDX                                            3
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT8_CONTROL                                                      0x0423
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_VECT8_CONTROL_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_PBA                                                                0x0800
+#define regRCC_DEV0_EPF0_VF4_GFXMSIX_PBA_BASE_IDX                                                       3
+
+
+// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf5_BIFPFVFDEC1
+// base address: 0x10120000
+#define regBIF_BX_DEV0_EPF0_VF5_0_BIF_BME_STATUS                                                        0x8e0b
+#define regBIF_BX_DEV0_EPF0_VF5_0_BIF_BME_STATUS_BASE_IDX                                               5
+#define regBIF_BX_DEV0_EPF0_VF5_0_BIF_ATOMIC_ERR_LOG                                                    0x8e0c
+#define regBIF_BX_DEV0_EPF0_VF5_0_BIF_ATOMIC_ERR_LOG_BASE_IDX                                           5
+#define regBIF_BX_DEV0_EPF0_VF5_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH                                  0x8e13
+#define regBIF_BX_DEV0_EPF0_VF5_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX                         5
+#define regBIF_BX_DEV0_EPF0_VF5_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW                                   0x8e14
+#define regBIF_BX_DEV0_EPF0_VF5_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX                          5
+#define regBIF_BX_DEV0_EPF0_VF5_0_DOORBELL_SELFRING_GPA_APER_CNTL                                       0x8e15
+#define regBIF_BX_DEV0_EPF0_VF5_0_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX                              5
+#define regBIF_BX_DEV0_EPF0_VF5_0_HDP_REG_COHERENCY_FLUSH_CNTL                                          0x8e16
+#define regBIF_BX_DEV0_EPF0_VF5_0_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX                                 5
+#define regBIF_BX_DEV0_EPF0_VF5_0_HDP_MEM_COHERENCY_FLUSH_CNTL                                          0x8e17
+#define regBIF_BX_DEV0_EPF0_VF5_0_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX                                 5
+#define regBIF_BX_DEV0_EPF0_VF5_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL                                     0x8e19
+#define regBIF_BX_DEV0_EPF0_VF5_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX                            5
+#define regBIF_BX_DEV0_EPF0_VF5_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL                                0x8e1a
+#define regBIF_BX_DEV0_EPF0_VF5_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX                       5
+#define regBIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ                                                     0x8e26
+#define regBIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ_BASE_IDX                                            5
+#define regBIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE                                                    0x8e27
+#define regBIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE_BASE_IDX                                           5
+#define regBIF_BX_DEV0_EPF0_VF5_0_BIF_TRANS_PENDING                                                     0x8e28
+#define regBIF_BX_DEV0_EPF0_VF5_0_BIF_TRANS_PENDING_BASE_IDX                                            5
+#define regBIF_BX_DEV0_EPF0_VF5_0_NBIF_GFX_ADDR_LUT_BYPASS                                              0x8e32
+#define regBIF_BX_DEV0_EPF0_VF5_0_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX                                     5
+#define regBIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_TRN_DW0                                                0x8e56
+#define regBIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX                                       5
+#define regBIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_TRN_DW1                                                0x8e57
+#define regBIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX                                       5
+#define regBIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_TRN_DW2                                                0x8e58
+#define regBIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX                                       5
+#define regBIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_TRN_DW3                                                0x8e59
+#define regBIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX                                       5
+#define regBIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_RCV_DW0                                                0x8e5a
+#define regBIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX                                       5
+#define regBIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_RCV_DW1                                                0x8e5b
+#define regBIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX                                       5
+#define regBIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_RCV_DW2                                                0x8e5c
+#define regBIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX                                       5
+#define regBIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_RCV_DW3                                                0x8e5d
+#define regBIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX                                       5
+#define regBIF_BX_DEV0_EPF0_VF5_0_MAILBOX_CONTROL                                                       0x8e5e
+#define regBIF_BX_DEV0_EPF0_VF5_0_MAILBOX_CONTROL_BASE_IDX                                              5
+#define regBIF_BX_DEV0_EPF0_VF5_0_MAILBOX_INT_CNTL                                                      0x8e5f
+#define regBIF_BX_DEV0_EPF0_VF5_0_MAILBOX_INT_CNTL_BASE_IDX                                             5
+#define regBIF_BX_DEV0_EPF0_VF5_0_BIF_VMHV_MAILBOX                                                      0x8e60
+#define regBIF_BX_DEV0_EPF0_VF5_0_BIF_VMHV_MAILBOX_BASE_IDX                                             5
+#define regBIF_BX_DEV0_EPF0_VF5_0_PARTITION_COMPUTE_CAP                                                 0x8e81
+#define regBIF_BX_DEV0_EPF0_VF5_0_PARTITION_COMPUTE_CAP_BASE_IDX                                        5
+#define regBIF_BX_DEV0_EPF0_VF5_0_PARTITION_MEM_CAP                                                     0x8e82
+#define regBIF_BX_DEV0_EPF0_VF5_0_PARTITION_MEM_CAP_BASE_IDX                                            5
+#define regBIF_BX_DEV0_EPF0_VF5_0_PARTITION_COMPUTE_STATUS                                              0x8e83
+#define regBIF_BX_DEV0_EPF0_VF5_0_PARTITION_COMPUTE_STATUS_BASE_IDX                                     5
+#define regBIF_BX_DEV0_EPF0_VF5_0_PARTITION_MEM_STATUS                                                  0x8e84
+#define regBIF_BX_DEV0_EPF0_VF5_0_PARTITION_MEM_STATUS_BASE_IDX                                         5
+
+
+// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf5_SYSPFVFDEC
+// base address: 0x10120000
+#define regBIF_BX_DEV0_EPF0_VF5_0_MM_INDEX                                                              0x8000
+#define regBIF_BX_DEV0_EPF0_VF5_0_MM_INDEX_BASE_IDX                                                     5
+#define regBIF_BX_DEV0_EPF0_VF5_0_MM_DATA                                                               0x8001
+#define regBIF_BX_DEV0_EPF0_VF5_0_MM_DATA_BASE_IDX                                                      5
+#define regBIF_BX_DEV0_EPF0_VF5_0_MM_INDEX_HI                                                           0x8006
+#define regBIF_BX_DEV0_EPF0_VF5_0_MM_INDEX_HI_BASE_IDX                                                  5
+
+
+// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf5_BIFPFVFDEC1:1
+// base address: 0x0
+#define regBIF_BX_DEV0_EPF0_VF5_1_BIF_BME_STATUS                                                        0x00eb
+#define regBIF_BX_DEV0_EPF0_VF5_1_BIF_BME_STATUS_BASE_IDX                                               2
+#define regBIF_BX_DEV0_EPF0_VF5_1_BIF_ATOMIC_ERR_LOG                                                    0x00ec
+#define regBIF_BX_DEV0_EPF0_VF5_1_BIF_ATOMIC_ERR_LOG_BASE_IDX                                           2
+#define regBIF_BX_DEV0_EPF0_VF5_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH                                  0x00f3
+#define regBIF_BX_DEV0_EPF0_VF5_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX                         2
+#define regBIF_BX_DEV0_EPF0_VF5_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW                                   0x00f4
+#define regBIF_BX_DEV0_EPF0_VF5_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX                          2
+#define regBIF_BX_DEV0_EPF0_VF5_1_DOORBELL_SELFRING_GPA_APER_CNTL                                       0x00f5
+#define regBIF_BX_DEV0_EPF0_VF5_1_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX                              2
+#define regBIF_BX_DEV0_EPF0_VF5_1_HDP_REG_COHERENCY_FLUSH_CNTL                                          0x00f6
+#define regBIF_BX_DEV0_EPF0_VF5_1_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX                                 2
+#define regBIF_BX_DEV0_EPF0_VF5_1_HDP_MEM_COHERENCY_FLUSH_CNTL                                          0x00f7
+#define regBIF_BX_DEV0_EPF0_VF5_1_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX                                 2
+#define regBIF_BX_DEV0_EPF0_VF5_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL                                     0x00f9
+#define regBIF_BX_DEV0_EPF0_VF5_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX                            2
+#define regBIF_BX_DEV0_EPF0_VF5_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL                                0x00fa
+#define regBIF_BX_DEV0_EPF0_VF5_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX                       2
+#define regBIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ                                                     0x0106
+#define regBIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ_BASE_IDX                                            2
+#define regBIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE                                                    0x0107
+#define regBIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE_BASE_IDX                                           2
+#define regBIF_BX_DEV0_EPF0_VF5_1_BIF_TRANS_PENDING                                                     0x0108
+#define regBIF_BX_DEV0_EPF0_VF5_1_BIF_TRANS_PENDING_BASE_IDX                                            2
+#define regBIF_BX_DEV0_EPF0_VF5_1_NBIF_GFX_ADDR_LUT_BYPASS                                              0x0112
+#define regBIF_BX_DEV0_EPF0_VF5_1_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX                                     2
+#define regBIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_TRN_DW0                                                0x0136
+#define regBIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX                                       2
+#define regBIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_TRN_DW1                                                0x0137
+#define regBIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX                                       2
+#define regBIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_TRN_DW2                                                0x0138
+#define regBIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX                                       2
+#define regBIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_TRN_DW3                                                0x0139
+#define regBIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX                                       2
+#define regBIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_RCV_DW0                                                0x013a
+#define regBIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX                                       2
+#define regBIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_RCV_DW1                                                0x013b
+#define regBIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX                                       2
+#define regBIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_RCV_DW2                                                0x013c
+#define regBIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX                                       2
+#define regBIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_RCV_DW3                                                0x013d
+#define regBIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX                                       2
+#define regBIF_BX_DEV0_EPF0_VF5_1_MAILBOX_CONTROL                                                       0x013e
+#define regBIF_BX_DEV0_EPF0_VF5_1_MAILBOX_CONTROL_BASE_IDX                                              2
+#define regBIF_BX_DEV0_EPF0_VF5_1_MAILBOX_INT_CNTL                                                      0x013f
+#define regBIF_BX_DEV0_EPF0_VF5_1_MAILBOX_INT_CNTL_BASE_IDX                                             2
+#define regBIF_BX_DEV0_EPF0_VF5_1_BIF_VMHV_MAILBOX                                                      0x0140
+#define regBIF_BX_DEV0_EPF0_VF5_1_BIF_VMHV_MAILBOX_BASE_IDX                                             2
+#define regBIF_BX_DEV0_EPF0_VF5_1_PARTITION_COMPUTE_CAP                                                 0x0161
+#define regBIF_BX_DEV0_EPF0_VF5_1_PARTITION_COMPUTE_CAP_BASE_IDX                                        2
+#define regBIF_BX_DEV0_EPF0_VF5_1_PARTITION_MEM_CAP                                                     0x0162
+#define regBIF_BX_DEV0_EPF0_VF5_1_PARTITION_MEM_CAP_BASE_IDX                                            2
+#define regBIF_BX_DEV0_EPF0_VF5_1_PARTITION_COMPUTE_STATUS                                              0x0163
+#define regBIF_BX_DEV0_EPF0_VF5_1_PARTITION_COMPUTE_STATUS_BASE_IDX                                     2
+#define regBIF_BX_DEV0_EPF0_VF5_1_PARTITION_MEM_STATUS                                                  0x0164
+#define regBIF_BX_DEV0_EPF0_VF5_1_PARTITION_MEM_STATUS_BASE_IDX                                         2
+
+
+// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf5_SYSPFVFDEC:1
+// base address: 0x0
+#define regBIF_BX_DEV0_EPF0_VF5_1_MM_INDEX                                                              0x0000
+#define regBIF_BX_DEV0_EPF0_VF5_1_MM_INDEX_BASE_IDX                                                     0
+#define regBIF_BX_DEV0_EPF0_VF5_1_MM_DATA                                                               0x0001
+#define regBIF_BX_DEV0_EPF0_VF5_1_MM_DATA_BASE_IDX                                                      0
+#define regBIF_BX_DEV0_EPF0_VF5_1_MM_INDEX_HI                                                           0x0006
+#define regBIF_BX_DEV0_EPF0_VF5_1_MM_INDEX_HI_BASE_IDX                                                  0
+
+
+// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf5_BIFPFVFDEC1
+// base address: 0x0
+#define regRCC_DEV0_EPF0_VF5_RCC_ERR_LOG                                                                0x0085
+#define regRCC_DEV0_EPF0_VF5_RCC_ERR_LOG_BASE_IDX                                                       2
+#define regRCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN                                                       0x00c0
+#define regRCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN_BASE_IDX                                              2
+#define regRCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE                                                         0x00c3
+#define regRCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE_BASE_IDX                                                2
+#define regRCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED                                                        0x00c4
+#define regRCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED_BASE_IDX                                               2
+#define regRCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER                                                    0x00c5
+#define regRCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX                                           2
+
+
+// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf5_BIFDEC2
+// base address: 0x0
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO                                                      0x0400
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI                                                      0x0401
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA                                                     0x0402
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA_BASE_IDX                                            3
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL                                                      0x0403
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO                                                      0x0404
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI                                                      0x0405
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA                                                     0x0406
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA_BASE_IDX                                            3
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL                                                      0x0407
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO                                                      0x0408
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI                                                      0x0409
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA                                                     0x040a
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA_BASE_IDX                                            3
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL                                                      0x040b
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_LO                                                      0x040c
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_LO_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_HI                                                      0x040d
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_HI_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_MSG_DATA                                                     0x040e
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_MSG_DATA_BASE_IDX                                            3
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_CONTROL                                                      0x040f
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_CONTROL_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT4_ADDR_LO                                                      0x0410
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT4_ADDR_LO_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT4_ADDR_HI                                                      0x0411
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT4_ADDR_HI_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT4_MSG_DATA                                                     0x0412
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT4_MSG_DATA_BASE_IDX                                            3
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT4_CONTROL                                                      0x0413
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT4_CONTROL_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT5_ADDR_LO                                                      0x0414
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT5_ADDR_LO_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT5_ADDR_HI                                                      0x0415
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT5_ADDR_HI_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT5_MSG_DATA                                                     0x0416
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT5_MSG_DATA_BASE_IDX                                            3
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT5_CONTROL                                                      0x0417
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT5_CONTROL_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT6_ADDR_LO                                                      0x0418
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT6_ADDR_LO_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT6_ADDR_HI                                                      0x0419
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT6_ADDR_HI_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT6_MSG_DATA                                                     0x041a
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT6_MSG_DATA_BASE_IDX                                            3
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT6_CONTROL                                                      0x041b
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT6_CONTROL_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT7_ADDR_LO                                                      0x041c
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT7_ADDR_LO_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT7_ADDR_HI                                                      0x041d
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT7_ADDR_HI_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT7_MSG_DATA                                                     0x041e
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT7_MSG_DATA_BASE_IDX                                            3
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT7_CONTROL                                                      0x041f
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT7_CONTROL_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT8_ADDR_LO                                                      0x0420
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT8_ADDR_LO_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT8_ADDR_HI                                                      0x0421
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT8_ADDR_HI_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT8_MSG_DATA                                                     0x0422
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT8_MSG_DATA_BASE_IDX                                            3
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT8_CONTROL                                                      0x0423
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_VECT8_CONTROL_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_PBA                                                                0x0800
+#define regRCC_DEV0_EPF0_VF5_GFXMSIX_PBA_BASE_IDX                                                       3
+
+
+// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf6_BIFPFVFDEC1
+// base address: 0x10120000
+#define regBIF_BX_DEV0_EPF0_VF6_0_BIF_BME_STATUS                                                        0x8e0b
+#define regBIF_BX_DEV0_EPF0_VF6_0_BIF_BME_STATUS_BASE_IDX                                               5
+#define regBIF_BX_DEV0_EPF0_VF6_0_BIF_ATOMIC_ERR_LOG                                                    0x8e0c
+#define regBIF_BX_DEV0_EPF0_VF6_0_BIF_ATOMIC_ERR_LOG_BASE_IDX                                           5
+#define regBIF_BX_DEV0_EPF0_VF6_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH                                  0x8e13
+#define regBIF_BX_DEV0_EPF0_VF6_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX                         5
+#define regBIF_BX_DEV0_EPF0_VF6_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW                                   0x8e14
+#define regBIF_BX_DEV0_EPF0_VF6_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX                          5
+#define regBIF_BX_DEV0_EPF0_VF6_0_DOORBELL_SELFRING_GPA_APER_CNTL                                       0x8e15
+#define regBIF_BX_DEV0_EPF0_VF6_0_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX                              5
+#define regBIF_BX_DEV0_EPF0_VF6_0_HDP_REG_COHERENCY_FLUSH_CNTL                                          0x8e16
+#define regBIF_BX_DEV0_EPF0_VF6_0_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX                                 5
+#define regBIF_BX_DEV0_EPF0_VF6_0_HDP_MEM_COHERENCY_FLUSH_CNTL                                          0x8e17
+#define regBIF_BX_DEV0_EPF0_VF6_0_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX                                 5
+#define regBIF_BX_DEV0_EPF0_VF6_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL                                     0x8e19
+#define regBIF_BX_DEV0_EPF0_VF6_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX                            5
+#define regBIF_BX_DEV0_EPF0_VF6_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL                                0x8e1a
+#define regBIF_BX_DEV0_EPF0_VF6_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX                       5
+#define regBIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ                                                     0x8e26
+#define regBIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ_BASE_IDX                                            5
+#define regBIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE                                                    0x8e27
+#define regBIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE_BASE_IDX                                           5
+#define regBIF_BX_DEV0_EPF0_VF6_0_BIF_TRANS_PENDING                                                     0x8e28
+#define regBIF_BX_DEV0_EPF0_VF6_0_BIF_TRANS_PENDING_BASE_IDX                                            5
+#define regBIF_BX_DEV0_EPF0_VF6_0_NBIF_GFX_ADDR_LUT_BYPASS                                              0x8e32
+#define regBIF_BX_DEV0_EPF0_VF6_0_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX                                     5
+#define regBIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_TRN_DW0                                                0x8e56
+#define regBIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX                                       5
+#define regBIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_TRN_DW1                                                0x8e57
+#define regBIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX                                       5
+#define regBIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_TRN_DW2                                                0x8e58
+#define regBIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX                                       5
+#define regBIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_TRN_DW3                                                0x8e59
+#define regBIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX                                       5
+#define regBIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_RCV_DW0                                                0x8e5a
+#define regBIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX                                       5
+#define regBIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_RCV_DW1                                                0x8e5b
+#define regBIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX                                       5
+#define regBIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_RCV_DW2                                                0x8e5c
+#define regBIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX                                       5
+#define regBIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_RCV_DW3                                                0x8e5d
+#define regBIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX                                       5
+#define regBIF_BX_DEV0_EPF0_VF6_0_MAILBOX_CONTROL                                                       0x8e5e
+#define regBIF_BX_DEV0_EPF0_VF6_0_MAILBOX_CONTROL_BASE_IDX                                              5
+#define regBIF_BX_DEV0_EPF0_VF6_0_MAILBOX_INT_CNTL                                                      0x8e5f
+#define regBIF_BX_DEV0_EPF0_VF6_0_MAILBOX_INT_CNTL_BASE_IDX                                             5
+#define regBIF_BX_DEV0_EPF0_VF6_0_BIF_VMHV_MAILBOX                                                      0x8e60
+#define regBIF_BX_DEV0_EPF0_VF6_0_BIF_VMHV_MAILBOX_BASE_IDX                                             5
+#define regBIF_BX_DEV0_EPF0_VF6_0_PARTITION_COMPUTE_CAP                                                 0x8e81
+#define regBIF_BX_DEV0_EPF0_VF6_0_PARTITION_COMPUTE_CAP_BASE_IDX                                        5
+#define regBIF_BX_DEV0_EPF0_VF6_0_PARTITION_MEM_CAP                                                     0x8e82
+#define regBIF_BX_DEV0_EPF0_VF6_0_PARTITION_MEM_CAP_BASE_IDX                                            5
+#define regBIF_BX_DEV0_EPF0_VF6_0_PARTITION_COMPUTE_STATUS                                              0x8e83
+#define regBIF_BX_DEV0_EPF0_VF6_0_PARTITION_COMPUTE_STATUS_BASE_IDX                                     5
+#define regBIF_BX_DEV0_EPF0_VF6_0_PARTITION_MEM_STATUS                                                  0x8e84
+#define regBIF_BX_DEV0_EPF0_VF6_0_PARTITION_MEM_STATUS_BASE_IDX                                         5
+
+
+// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf6_SYSPFVFDEC
+// base address: 0x10120000
+#define regBIF_BX_DEV0_EPF0_VF6_0_MM_INDEX                                                              0x8000
+#define regBIF_BX_DEV0_EPF0_VF6_0_MM_INDEX_BASE_IDX                                                     5
+#define regBIF_BX_DEV0_EPF0_VF6_0_MM_DATA                                                               0x8001
+#define regBIF_BX_DEV0_EPF0_VF6_0_MM_DATA_BASE_IDX                                                      5
+#define regBIF_BX_DEV0_EPF0_VF6_0_MM_INDEX_HI                                                           0x8006
+#define regBIF_BX_DEV0_EPF0_VF6_0_MM_INDEX_HI_BASE_IDX                                                  5
+
+
+// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf6_BIFPFVFDEC1:1
+// base address: 0x0
+#define regBIF_BX_DEV0_EPF0_VF6_1_BIF_BME_STATUS                                                        0x00eb
+#define regBIF_BX_DEV0_EPF0_VF6_1_BIF_BME_STATUS_BASE_IDX                                               2
+#define regBIF_BX_DEV0_EPF0_VF6_1_BIF_ATOMIC_ERR_LOG                                                    0x00ec
+#define regBIF_BX_DEV0_EPF0_VF6_1_BIF_ATOMIC_ERR_LOG_BASE_IDX                                           2
+#define regBIF_BX_DEV0_EPF0_VF6_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH                                  0x00f3
+#define regBIF_BX_DEV0_EPF0_VF6_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX                         2
+#define regBIF_BX_DEV0_EPF0_VF6_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW                                   0x00f4
+#define regBIF_BX_DEV0_EPF0_VF6_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX                          2
+#define regBIF_BX_DEV0_EPF0_VF6_1_DOORBELL_SELFRING_GPA_APER_CNTL                                       0x00f5
+#define regBIF_BX_DEV0_EPF0_VF6_1_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX                              2
+#define regBIF_BX_DEV0_EPF0_VF6_1_HDP_REG_COHERENCY_FLUSH_CNTL                                          0x00f6
+#define regBIF_BX_DEV0_EPF0_VF6_1_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX                                 2
+#define regBIF_BX_DEV0_EPF0_VF6_1_HDP_MEM_COHERENCY_FLUSH_CNTL                                          0x00f7
+#define regBIF_BX_DEV0_EPF0_VF6_1_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX                                 2
+#define regBIF_BX_DEV0_EPF0_VF6_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL                                     0x00f9
+#define regBIF_BX_DEV0_EPF0_VF6_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX                            2
+#define regBIF_BX_DEV0_EPF0_VF6_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL                                0x00fa
+#define regBIF_BX_DEV0_EPF0_VF6_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX                       2
+#define regBIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ                                                     0x0106
+#define regBIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ_BASE_IDX                                            2
+#define regBIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE                                                    0x0107
+#define regBIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE_BASE_IDX                                           2
+#define regBIF_BX_DEV0_EPF0_VF6_1_BIF_TRANS_PENDING                                                     0x0108
+#define regBIF_BX_DEV0_EPF0_VF6_1_BIF_TRANS_PENDING_BASE_IDX                                            2
+#define regBIF_BX_DEV0_EPF0_VF6_1_NBIF_GFX_ADDR_LUT_BYPASS                                              0x0112
+#define regBIF_BX_DEV0_EPF0_VF6_1_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX                                     2
+#define regBIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_TRN_DW0                                                0x0136
+#define regBIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX                                       2
+#define regBIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_TRN_DW1                                                0x0137
+#define regBIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX                                       2
+#define regBIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_TRN_DW2                                                0x0138
+#define regBIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX                                       2
+#define regBIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_TRN_DW3                                                0x0139
+#define regBIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX                                       2
+#define regBIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_RCV_DW0                                                0x013a
+#define regBIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX                                       2
+#define regBIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_RCV_DW1                                                0x013b
+#define regBIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX                                       2
+#define regBIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_RCV_DW2                                                0x013c
+#define regBIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX                                       2
+#define regBIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_RCV_DW3                                                0x013d
+#define regBIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX                                       2
+#define regBIF_BX_DEV0_EPF0_VF6_1_MAILBOX_CONTROL                                                       0x013e
+#define regBIF_BX_DEV0_EPF0_VF6_1_MAILBOX_CONTROL_BASE_IDX                                              2
+#define regBIF_BX_DEV0_EPF0_VF6_1_MAILBOX_INT_CNTL                                                      0x013f
+#define regBIF_BX_DEV0_EPF0_VF6_1_MAILBOX_INT_CNTL_BASE_IDX                                             2
+#define regBIF_BX_DEV0_EPF0_VF6_1_BIF_VMHV_MAILBOX                                                      0x0140
+#define regBIF_BX_DEV0_EPF0_VF6_1_BIF_VMHV_MAILBOX_BASE_IDX                                             2
+#define regBIF_BX_DEV0_EPF0_VF6_1_PARTITION_COMPUTE_CAP                                                 0x0161
+#define regBIF_BX_DEV0_EPF0_VF6_1_PARTITION_COMPUTE_CAP_BASE_IDX                                        2
+#define regBIF_BX_DEV0_EPF0_VF6_1_PARTITION_MEM_CAP                                                     0x0162
+#define regBIF_BX_DEV0_EPF0_VF6_1_PARTITION_MEM_CAP_BASE_IDX                                            2
+#define regBIF_BX_DEV0_EPF0_VF6_1_PARTITION_COMPUTE_STATUS                                              0x0163
+#define regBIF_BX_DEV0_EPF0_VF6_1_PARTITION_COMPUTE_STATUS_BASE_IDX                                     2
+#define regBIF_BX_DEV0_EPF0_VF6_1_PARTITION_MEM_STATUS                                                  0x0164
+#define regBIF_BX_DEV0_EPF0_VF6_1_PARTITION_MEM_STATUS_BASE_IDX                                         2
+
+
+// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf6_SYSPFVFDEC:1
+// base address: 0x0
+#define regBIF_BX_DEV0_EPF0_VF6_1_MM_INDEX                                                              0x0000
+#define regBIF_BX_DEV0_EPF0_VF6_1_MM_INDEX_BASE_IDX                                                     0
+#define regBIF_BX_DEV0_EPF0_VF6_1_MM_DATA                                                               0x0001
+#define regBIF_BX_DEV0_EPF0_VF6_1_MM_DATA_BASE_IDX                                                      0
+#define regBIF_BX_DEV0_EPF0_VF6_1_MM_INDEX_HI                                                           0x0006
+#define regBIF_BX_DEV0_EPF0_VF6_1_MM_INDEX_HI_BASE_IDX                                                  0
+
+
+// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf6_BIFPFVFDEC1
+// base address: 0x0
+#define regRCC_DEV0_EPF0_VF6_RCC_ERR_LOG                                                                0x0085
+#define regRCC_DEV0_EPF0_VF6_RCC_ERR_LOG_BASE_IDX                                                       2
+#define regRCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN                                                       0x00c0
+#define regRCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN_BASE_IDX                                              2
+#define regRCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE                                                         0x00c3
+#define regRCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE_BASE_IDX                                                2
+#define regRCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED                                                        0x00c4
+#define regRCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED_BASE_IDX                                               2
+#define regRCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER                                                    0x00c5
+#define regRCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX                                           2
+
+
+// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf6_BIFDEC2
+// base address: 0x0
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO                                                      0x0400
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI                                                      0x0401
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA                                                     0x0402
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA_BASE_IDX                                            3
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL                                                      0x0403
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO                                                      0x0404
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI                                                      0x0405
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA                                                     0x0406
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA_BASE_IDX                                            3
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL                                                      0x0407
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO                                                      0x0408
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI                                                      0x0409
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA                                                     0x040a
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA_BASE_IDX                                            3
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL                                                      0x040b
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_LO                                                      0x040c
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_LO_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_HI                                                      0x040d
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_HI_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_MSG_DATA                                                     0x040e
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_MSG_DATA_BASE_IDX                                            3
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_CONTROL                                                      0x040f
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_CONTROL_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT4_ADDR_LO                                                      0x0410
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT4_ADDR_LO_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT4_ADDR_HI                                                      0x0411
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT4_ADDR_HI_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT4_MSG_DATA                                                     0x0412
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT4_MSG_DATA_BASE_IDX                                            3
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT4_CONTROL                                                      0x0413
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT4_CONTROL_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT5_ADDR_LO                                                      0x0414
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT5_ADDR_LO_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT5_ADDR_HI                                                      0x0415
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT5_ADDR_HI_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT5_MSG_DATA                                                     0x0416
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT5_MSG_DATA_BASE_IDX                                            3
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT5_CONTROL                                                      0x0417
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT5_CONTROL_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT6_ADDR_LO                                                      0x0418
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT6_ADDR_LO_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT6_ADDR_HI                                                      0x0419
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT6_ADDR_HI_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT6_MSG_DATA                                                     0x041a
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT6_MSG_DATA_BASE_IDX                                            3
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT6_CONTROL                                                      0x041b
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT6_CONTROL_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT7_ADDR_LO                                                      0x041c
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT7_ADDR_LO_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT7_ADDR_HI                                                      0x041d
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT7_ADDR_HI_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT7_MSG_DATA                                                     0x041e
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT7_MSG_DATA_BASE_IDX                                            3
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT7_CONTROL                                                      0x041f
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT7_CONTROL_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT8_ADDR_LO                                                      0x0420
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT8_ADDR_LO_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT8_ADDR_HI                                                      0x0421
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT8_ADDR_HI_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT8_MSG_DATA                                                     0x0422
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT8_MSG_DATA_BASE_IDX                                            3
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT8_CONTROL                                                      0x0423
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_VECT8_CONTROL_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_PBA                                                                0x0800
+#define regRCC_DEV0_EPF0_VF6_GFXMSIX_PBA_BASE_IDX                                                       3
+
+
+// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf7_BIFPFVFDEC1
+// base address: 0x10120000
+#define regBIF_BX_DEV0_EPF0_VF7_0_BIF_BME_STATUS                                                        0x8e0b
+#define regBIF_BX_DEV0_EPF0_VF7_0_BIF_BME_STATUS_BASE_IDX                                               5
+#define regBIF_BX_DEV0_EPF0_VF7_0_BIF_ATOMIC_ERR_LOG                                                    0x8e0c
+#define regBIF_BX_DEV0_EPF0_VF7_0_BIF_ATOMIC_ERR_LOG_BASE_IDX                                           5
+#define regBIF_BX_DEV0_EPF0_VF7_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH                                  0x8e13
+#define regBIF_BX_DEV0_EPF0_VF7_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX                         5
+#define regBIF_BX_DEV0_EPF0_VF7_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW                                   0x8e14
+#define regBIF_BX_DEV0_EPF0_VF7_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX                          5
+#define regBIF_BX_DEV0_EPF0_VF7_0_DOORBELL_SELFRING_GPA_APER_CNTL                                       0x8e15
+#define regBIF_BX_DEV0_EPF0_VF7_0_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX                              5
+#define regBIF_BX_DEV0_EPF0_VF7_0_HDP_REG_COHERENCY_FLUSH_CNTL                                          0x8e16
+#define regBIF_BX_DEV0_EPF0_VF7_0_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX                                 5
+#define regBIF_BX_DEV0_EPF0_VF7_0_HDP_MEM_COHERENCY_FLUSH_CNTL                                          0x8e17
+#define regBIF_BX_DEV0_EPF0_VF7_0_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX                                 5
+#define regBIF_BX_DEV0_EPF0_VF7_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL                                     0x8e19
+#define regBIF_BX_DEV0_EPF0_VF7_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX                            5
+#define regBIF_BX_DEV0_EPF0_VF7_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL                                0x8e1a
+#define regBIF_BX_DEV0_EPF0_VF7_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX                       5
+#define regBIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ                                                     0x8e26
+#define regBIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ_BASE_IDX                                            5
+#define regBIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE                                                    0x8e27
+#define regBIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE_BASE_IDX                                           5
+#define regBIF_BX_DEV0_EPF0_VF7_0_BIF_TRANS_PENDING                                                     0x8e28
+#define regBIF_BX_DEV0_EPF0_VF7_0_BIF_TRANS_PENDING_BASE_IDX                                            5
+#define regBIF_BX_DEV0_EPF0_VF7_0_NBIF_GFX_ADDR_LUT_BYPASS                                              0x8e32
+#define regBIF_BX_DEV0_EPF0_VF7_0_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX                                     5
+#define regBIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_TRN_DW0                                                0x8e56
+#define regBIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX                                       5
+#define regBIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_TRN_DW1                                                0x8e57
+#define regBIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX                                       5
+#define regBIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_TRN_DW2                                                0x8e58
+#define regBIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX                                       5
+#define regBIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_TRN_DW3                                                0x8e59
+#define regBIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX                                       5
+#define regBIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_RCV_DW0                                                0x8e5a
+#define regBIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX                                       5
+#define regBIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_RCV_DW1                                                0x8e5b
+#define regBIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX                                       5
+#define regBIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_RCV_DW2                                                0x8e5c
+#define regBIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX                                       5
+#define regBIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_RCV_DW3                                                0x8e5d
+#define regBIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX                                       5
+#define regBIF_BX_DEV0_EPF0_VF7_0_MAILBOX_CONTROL                                                       0x8e5e
+#define regBIF_BX_DEV0_EPF0_VF7_0_MAILBOX_CONTROL_BASE_IDX                                              5
+#define regBIF_BX_DEV0_EPF0_VF7_0_MAILBOX_INT_CNTL                                                      0x8e5f
+#define regBIF_BX_DEV0_EPF0_VF7_0_MAILBOX_INT_CNTL_BASE_IDX                                             5
+#define regBIF_BX_DEV0_EPF0_VF7_0_BIF_VMHV_MAILBOX                                                      0x8e60
+#define regBIF_BX_DEV0_EPF0_VF7_0_BIF_VMHV_MAILBOX_BASE_IDX                                             5
+#define regBIF_BX_DEV0_EPF0_VF7_0_PARTITION_COMPUTE_CAP                                                 0x8e81
+#define regBIF_BX_DEV0_EPF0_VF7_0_PARTITION_COMPUTE_CAP_BASE_IDX                                        5
+#define regBIF_BX_DEV0_EPF0_VF7_0_PARTITION_MEM_CAP                                                     0x8e82
+#define regBIF_BX_DEV0_EPF0_VF7_0_PARTITION_MEM_CAP_BASE_IDX                                            5
+#define regBIF_BX_DEV0_EPF0_VF7_0_PARTITION_COMPUTE_STATUS                                              0x8e83
+#define regBIF_BX_DEV0_EPF0_VF7_0_PARTITION_COMPUTE_STATUS_BASE_IDX                                     5
+#define regBIF_BX_DEV0_EPF0_VF7_0_PARTITION_MEM_STATUS                                                  0x8e84
+#define regBIF_BX_DEV0_EPF0_VF7_0_PARTITION_MEM_STATUS_BASE_IDX                                         5
+
+
+// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf7_SYSPFVFDEC
+// base address: 0x10120000
+#define regBIF_BX_DEV0_EPF0_VF7_0_MM_INDEX                                                              0x8000
+#define regBIF_BX_DEV0_EPF0_VF7_0_MM_INDEX_BASE_IDX                                                     5
+#define regBIF_BX_DEV0_EPF0_VF7_0_MM_DATA                                                               0x8001
+#define regBIF_BX_DEV0_EPF0_VF7_0_MM_DATA_BASE_IDX                                                      5
+#define regBIF_BX_DEV0_EPF0_VF7_0_MM_INDEX_HI                                                           0x8006
+#define regBIF_BX_DEV0_EPF0_VF7_0_MM_INDEX_HI_BASE_IDX                                                  5
+
+
+// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf7_BIFPFVFDEC1:1
+// base address: 0x0
+#define regBIF_BX_DEV0_EPF0_VF7_1_BIF_BME_STATUS                                                        0x00eb
+#define regBIF_BX_DEV0_EPF0_VF7_1_BIF_BME_STATUS_BASE_IDX                                               2
+#define regBIF_BX_DEV0_EPF0_VF7_1_BIF_ATOMIC_ERR_LOG                                                    0x00ec
+#define regBIF_BX_DEV0_EPF0_VF7_1_BIF_ATOMIC_ERR_LOG_BASE_IDX                                           2
+#define regBIF_BX_DEV0_EPF0_VF7_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH                                  0x00f3
+#define regBIF_BX_DEV0_EPF0_VF7_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX                         2
+#define regBIF_BX_DEV0_EPF0_VF7_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW                                   0x00f4
+#define regBIF_BX_DEV0_EPF0_VF7_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX                          2
+#define regBIF_BX_DEV0_EPF0_VF7_1_DOORBELL_SELFRING_GPA_APER_CNTL                                       0x00f5
+#define regBIF_BX_DEV0_EPF0_VF7_1_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX                              2
+#define regBIF_BX_DEV0_EPF0_VF7_1_HDP_REG_COHERENCY_FLUSH_CNTL                                          0x00f6
+#define regBIF_BX_DEV0_EPF0_VF7_1_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX                                 2
+#define regBIF_BX_DEV0_EPF0_VF7_1_HDP_MEM_COHERENCY_FLUSH_CNTL                                          0x00f7
+#define regBIF_BX_DEV0_EPF0_VF7_1_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX                                 2
+#define regBIF_BX_DEV0_EPF0_VF7_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL                                     0x00f9
+#define regBIF_BX_DEV0_EPF0_VF7_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX                            2
+#define regBIF_BX_DEV0_EPF0_VF7_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL                                0x00fa
+#define regBIF_BX_DEV0_EPF0_VF7_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX                       2
+#define regBIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ                                                     0x0106
+#define regBIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ_BASE_IDX                                            2
+#define regBIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE                                                    0x0107
+#define regBIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE_BASE_IDX                                           2
+#define regBIF_BX_DEV0_EPF0_VF7_1_BIF_TRANS_PENDING                                                     0x0108
+#define regBIF_BX_DEV0_EPF0_VF7_1_BIF_TRANS_PENDING_BASE_IDX                                            2
+#define regBIF_BX_DEV0_EPF0_VF7_1_NBIF_GFX_ADDR_LUT_BYPASS                                              0x0112
+#define regBIF_BX_DEV0_EPF0_VF7_1_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX                                     2
+#define regBIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_TRN_DW0                                                0x0136
+#define regBIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX                                       2
+#define regBIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_TRN_DW1                                                0x0137
+#define regBIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX                                       2
+#define regBIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_TRN_DW2                                                0x0138
+#define regBIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX                                       2
+#define regBIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_TRN_DW3                                                0x0139
+#define regBIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX                                       2
+#define regBIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_RCV_DW0                                                0x013a
+#define regBIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX                                       2
+#define regBIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_RCV_DW1                                                0x013b
+#define regBIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX                                       2
+#define regBIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_RCV_DW2                                                0x013c
+#define regBIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX                                       2
+#define regBIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_RCV_DW3                                                0x013d
+#define regBIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX                                       2
+#define regBIF_BX_DEV0_EPF0_VF7_1_MAILBOX_CONTROL                                                       0x013e
+#define regBIF_BX_DEV0_EPF0_VF7_1_MAILBOX_CONTROL_BASE_IDX                                              2
+#define regBIF_BX_DEV0_EPF0_VF7_1_MAILBOX_INT_CNTL                                                      0x013f
+#define regBIF_BX_DEV0_EPF0_VF7_1_MAILBOX_INT_CNTL_BASE_IDX                                             2
+#define regBIF_BX_DEV0_EPF0_VF7_1_BIF_VMHV_MAILBOX                                                      0x0140
+#define regBIF_BX_DEV0_EPF0_VF7_1_BIF_VMHV_MAILBOX_BASE_IDX                                             2
+#define regBIF_BX_DEV0_EPF0_VF7_1_PARTITION_COMPUTE_CAP                                                 0x0161
+#define regBIF_BX_DEV0_EPF0_VF7_1_PARTITION_COMPUTE_CAP_BASE_IDX                                        2
+#define regBIF_BX_DEV0_EPF0_VF7_1_PARTITION_MEM_CAP                                                     0x0162
+#define regBIF_BX_DEV0_EPF0_VF7_1_PARTITION_MEM_CAP_BASE_IDX                                            2
+#define regBIF_BX_DEV0_EPF0_VF7_1_PARTITION_COMPUTE_STATUS                                              0x0163
+#define regBIF_BX_DEV0_EPF0_VF7_1_PARTITION_COMPUTE_STATUS_BASE_IDX                                     2
+#define regBIF_BX_DEV0_EPF0_VF7_1_PARTITION_MEM_STATUS                                                  0x0164
+#define regBIF_BX_DEV0_EPF0_VF7_1_PARTITION_MEM_STATUS_BASE_IDX                                         2
+
+
+// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf7_SYSPFVFDEC:1
+// base address: 0x0
+#define regBIF_BX_DEV0_EPF0_VF7_1_MM_INDEX                                                              0x0000
+#define regBIF_BX_DEV0_EPF0_VF7_1_MM_INDEX_BASE_IDX                                                     0
+#define regBIF_BX_DEV0_EPF0_VF7_1_MM_DATA                                                               0x0001
+#define regBIF_BX_DEV0_EPF0_VF7_1_MM_DATA_BASE_IDX                                                      0
+#define regBIF_BX_DEV0_EPF0_VF7_1_MM_INDEX_HI                                                           0x0006
+#define regBIF_BX_DEV0_EPF0_VF7_1_MM_INDEX_HI_BASE_IDX                                                  0
+
+
+// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf7_BIFPFVFDEC1
+// base address: 0x0
+#define regRCC_DEV0_EPF0_VF7_RCC_ERR_LOG                                                                0x0085
+#define regRCC_DEV0_EPF0_VF7_RCC_ERR_LOG_BASE_IDX                                                       2
+#define regRCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN                                                       0x00c0
+#define regRCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN_BASE_IDX                                              2
+#define regRCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE                                                         0x00c3
+#define regRCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE_BASE_IDX                                                2
+#define regRCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED                                                        0x00c4
+#define regRCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED_BASE_IDX                                               2
+#define regRCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER                                                    0x00c5
+#define regRCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER_BASE_IDX                                           2
+
+
+// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf7_BIFDEC2
+// base address: 0x0
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO                                                      0x0400
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI                                                      0x0401
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA                                                     0x0402
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA_BASE_IDX                                            3
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL                                                      0x0403
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO                                                      0x0404
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI                                                      0x0405
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA                                                     0x0406
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA_BASE_IDX                                            3
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL                                                      0x0407
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO                                                      0x0408
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI                                                      0x0409
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA                                                     0x040a
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA_BASE_IDX                                            3
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL                                                      0x040b
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_LO                                                      0x040c
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_LO_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_HI                                                      0x040d
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_HI_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_MSG_DATA                                                     0x040e
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_MSG_DATA_BASE_IDX                                            3
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_CONTROL                                                      0x040f
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_CONTROL_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT4_ADDR_LO                                                      0x0410
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT4_ADDR_LO_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT4_ADDR_HI                                                      0x0411
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT4_ADDR_HI_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT4_MSG_DATA                                                     0x0412
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT4_MSG_DATA_BASE_IDX                                            3
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT4_CONTROL                                                      0x0413
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT4_CONTROL_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT5_ADDR_LO                                                      0x0414
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT5_ADDR_LO_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT5_ADDR_HI                                                      0x0415
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT5_ADDR_HI_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT5_MSG_DATA                                                     0x0416
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT5_MSG_DATA_BASE_IDX                                            3
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT5_CONTROL                                                      0x0417
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT5_CONTROL_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT6_ADDR_LO                                                      0x0418
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT6_ADDR_LO_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT6_ADDR_HI                                                      0x0419
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT6_ADDR_HI_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT6_MSG_DATA                                                     0x041a
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT6_MSG_DATA_BASE_IDX                                            3
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT6_CONTROL                                                      0x041b
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT6_CONTROL_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT7_ADDR_LO                                                      0x041c
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT7_ADDR_LO_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT7_ADDR_HI                                                      0x041d
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT7_ADDR_HI_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT7_MSG_DATA                                                     0x041e
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT7_MSG_DATA_BASE_IDX                                            3
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT7_CONTROL                                                      0x041f
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT7_CONTROL_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT8_ADDR_LO                                                      0x0420
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT8_ADDR_LO_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT8_ADDR_HI                                                      0x0421
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT8_ADDR_HI_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT8_MSG_DATA                                                     0x0422
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT8_MSG_DATA_BASE_IDX                                            3
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT8_CONTROL                                                      0x0423
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_VECT8_CONTROL_BASE_IDX                                             3
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_PBA                                                                0x0800
+#define regRCC_DEV0_EPF0_VF7_GFXMSIX_PBA_BASE_IDX                                                       3
+
+
+// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf1_bifcfgdecp
+// base address: 0x10141000
+#define regBIF_CFG_DEV0_EPF1_VENDOR_ID                                                                  0x10400
+#define regBIF_CFG_DEV0_EPF1_VENDOR_ID_BASE_IDX                                                         5
+#define regBIF_CFG_DEV0_EPF1_DEVICE_ID                                                                  0x10400
+#define regBIF_CFG_DEV0_EPF1_DEVICE_ID_BASE_IDX                                                         5
+#define regBIF_CFG_DEV0_EPF1_COMMAND                                                                    0x10401
+#define regBIF_CFG_DEV0_EPF1_COMMAND_BASE_IDX                                                           5
+#define regBIF_CFG_DEV0_EPF1_STATUS                                                                     0x10401
+#define regBIF_CFG_DEV0_EPF1_STATUS_BASE_IDX                                                            5
+#define regBIF_CFG_DEV0_EPF1_REVISION_ID                                                                0x10402
+#define regBIF_CFG_DEV0_EPF1_REVISION_ID_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF1_PROG_INTERFACE                                                             0x10402
+#define regBIF_CFG_DEV0_EPF1_PROG_INTERFACE_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF1_SUB_CLASS                                                                  0x10402
+#define regBIF_CFG_DEV0_EPF1_SUB_CLASS_BASE_IDX                                                         5
+#define regBIF_CFG_DEV0_EPF1_BASE_CLASS                                                                 0x10402
+#define regBIF_CFG_DEV0_EPF1_BASE_CLASS_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_EPF1_CACHE_LINE                                                                 0x10403
+#define regBIF_CFG_DEV0_EPF1_CACHE_LINE_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_EPF1_LATENCY                                                                    0x10403
+#define regBIF_CFG_DEV0_EPF1_LATENCY_BASE_IDX                                                           5
+#define regBIF_CFG_DEV0_EPF1_HEADER                                                                     0x10403
+#define regBIF_CFG_DEV0_EPF1_HEADER_BASE_IDX                                                            5
+#define regBIF_CFG_DEV0_EPF1_BIST                                                                       0x10403
+#define regBIF_CFG_DEV0_EPF1_BIST_BASE_IDX                                                              5
+#define regBIF_CFG_DEV0_EPF1_BASE_ADDR_1                                                                0x10404
+#define regBIF_CFG_DEV0_EPF1_BASE_ADDR_1_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF1_BASE_ADDR_2                                                                0x10405
+#define regBIF_CFG_DEV0_EPF1_BASE_ADDR_2_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF1_BASE_ADDR_3                                                                0x10406
+#define regBIF_CFG_DEV0_EPF1_BASE_ADDR_3_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF1_BASE_ADDR_4                                                                0x10407
+#define regBIF_CFG_DEV0_EPF1_BASE_ADDR_4_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF1_BASE_ADDR_5                                                                0x10408
+#define regBIF_CFG_DEV0_EPF1_BASE_ADDR_5_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF1_BASE_ADDR_6                                                                0x10409
+#define regBIF_CFG_DEV0_EPF1_BASE_ADDR_6_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF1_CARDBUS_CIS_PTR                                                            0x1040a
+#define regBIF_CFG_DEV0_EPF1_CARDBUS_CIS_PTR_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF1_ADAPTER_ID                                                                 0x1040b
+#define regBIF_CFG_DEV0_EPF1_ADAPTER_ID_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_EPF1_ROM_BASE_ADDR                                                              0x1040c
+#define regBIF_CFG_DEV0_EPF1_ROM_BASE_ADDR_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF1_CAP_PTR                                                                    0x1040d
+#define regBIF_CFG_DEV0_EPF1_CAP_PTR_BASE_IDX                                                           5
+#define regBIF_CFG_DEV0_EPF1_INTERRUPT_LINE                                                             0x1040f
+#define regBIF_CFG_DEV0_EPF1_INTERRUPT_LINE_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF1_INTERRUPT_PIN                                                              0x1040f
+#define regBIF_CFG_DEV0_EPF1_INTERRUPT_PIN_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF1_MIN_GRANT                                                                  0x1040f
+#define regBIF_CFG_DEV0_EPF1_MIN_GRANT_BASE_IDX                                                         5
+#define regBIF_CFG_DEV0_EPF1_MAX_LATENCY                                                                0x1040f
+#define regBIF_CFG_DEV0_EPF1_MAX_LATENCY_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST                                                            0x10412
+#define regBIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF1_ADAPTER_ID_W                                                               0x10413
+#define regBIF_CFG_DEV0_EPF1_ADAPTER_ID_W_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF1_PMI_CAP_LIST                                                               0x10414
+#define regBIF_CFG_DEV0_EPF1_PMI_CAP_LIST_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF1_PMI_CAP                                                                    0x10414
+#define regBIF_CFG_DEV0_EPF1_PMI_CAP_BASE_IDX                                                           5
+#define regBIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL                                                            0x10415
+#define regBIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL_BASE_IDX                                                   5
+#define regSBRN                                                                                         0x10418
+#define regSBRN_BASE_IDX                                                                                5
+#define regFLADJ                                                                                        0x10418
+#define regFLADJ_BASE_IDX                                                                               5
+#define regBIF_CFG_DEV0_EPF1_PCIE_CAP_LIST                                                              0x10419
+#define regBIF_CFG_DEV0_EPF1_PCIE_CAP_LIST_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF1_PCIE_CAP                                                                   0x10419
+#define regBIF_CFG_DEV0_EPF1_PCIE_CAP_BASE_IDX                                                          5
+#define regBIF_CFG_DEV0_EPF1_DEVICE_CAP                                                                 0x1041a
+#define regBIF_CFG_DEV0_EPF1_DEVICE_CAP_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_EPF1_DEVICE_CNTL                                                                0x1041b
+#define regBIF_CFG_DEV0_EPF1_DEVICE_CNTL_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF1_DEVICE_STATUS                                                              0x1041b
+#define regBIF_CFG_DEV0_EPF1_DEVICE_STATUS_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF1_LINK_CAP                                                                   0x1041c
+#define regBIF_CFG_DEV0_EPF1_LINK_CAP_BASE_IDX                                                          5
+#define regBIF_CFG_DEV0_EPF1_LINK_CNTL                                                                  0x1041d
+#define regBIF_CFG_DEV0_EPF1_LINK_CNTL_BASE_IDX                                                         5
+#define regBIF_CFG_DEV0_EPF1_LINK_STATUS                                                                0x1041d
+#define regBIF_CFG_DEV0_EPF1_LINK_STATUS_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF1_DEVICE_CAP2                                                                0x10422
+#define regBIF_CFG_DEV0_EPF1_DEVICE_CAP2_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF1_DEVICE_CNTL2                                                               0x10423
+#define regBIF_CFG_DEV0_EPF1_DEVICE_CNTL2_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF1_DEVICE_STATUS2                                                             0x10423
+#define regBIF_CFG_DEV0_EPF1_DEVICE_STATUS2_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF1_LINK_CAP2                                                                  0x10424
+#define regBIF_CFG_DEV0_EPF1_LINK_CAP2_BASE_IDX                                                         5
+#define regBIF_CFG_DEV0_EPF1_LINK_CNTL2                                                                 0x10425
+#define regBIF_CFG_DEV0_EPF1_LINK_CNTL2_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_EPF1_LINK_STATUS2                                                               0x10425
+#define regBIF_CFG_DEV0_EPF1_LINK_STATUS2_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF1_MSI_CAP_LIST                                                               0x10428
+#define regBIF_CFG_DEV0_EPF1_MSI_CAP_LIST_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF1_MSI_MSG_CNTL                                                               0x10428
+#define regBIF_CFG_DEV0_EPF1_MSI_MSG_CNTL_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_LO                                                            0x10429
+#define regBIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_LO_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_HI                                                            0x1042a
+#define regBIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_HI_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF1_MSI_MSG_DATA                                                               0x1042a
+#define regBIF_CFG_DEV0_EPF1_MSI_MSG_DATA_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA                                                           0x1042a
+#define regBIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF1_MSI_MASK                                                                   0x1042b
+#define regBIF_CFG_DEV0_EPF1_MSI_MASK_BASE_IDX                                                          5
+#define regBIF_CFG_DEV0_EPF1_MSI_MSG_DATA_64                                                            0x1042b
+#define regBIF_CFG_DEV0_EPF1_MSI_MSG_DATA_64_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA_64                                                        0x1042b
+#define regBIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA_64_BASE_IDX                                               5
+#define regBIF_CFG_DEV0_EPF1_MSI_MASK_64                                                                0x1042c
+#define regBIF_CFG_DEV0_EPF1_MSI_MASK_64_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF1_MSI_PENDING                                                                0x1042c
+#define regBIF_CFG_DEV0_EPF1_MSI_PENDING_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF1_MSI_PENDING_64                                                             0x1042d
+#define regBIF_CFG_DEV0_EPF1_MSI_PENDING_64_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF1_MSIX_CAP_LIST                                                              0x10430
+#define regBIF_CFG_DEV0_EPF1_MSIX_CAP_LIST_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL                                                              0x10430
+#define regBIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF1_MSIX_TABLE                                                                 0x10431
+#define regBIF_CFG_DEV0_EPF1_MSIX_TABLE_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_EPF1_MSIX_PBA                                                                   0x10432
+#define regBIF_CFG_DEV0_EPF1_MSIX_PBA_BASE_IDX                                                          5
+#define regBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                          0x10440
+#define regBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX                                 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR                                                   0x10441
+#define regBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC1                                                      0x10442
+#define regBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC1_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC2                                                      0x10443
+#define regBIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC2_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF1_PCIE_DEVICE3_ENH_CAP_LIST                                                  0x104b6
+#define regBIF_CFG_DEV0_EPF1_PCIE_DEVICE3_ENH_CAP_LIST_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF1_DEVICE_CAP3                                                                0x104b7
+#define regBIF_CFG_DEV0_EPF1_DEVICE_CAP3_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF1_DEVICE_CNTL3                                                               0x104b8
+#define regBIF_CFG_DEV0_EPF1_DEVICE_CNTL3_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF1_DEVICE_STATUS3                                                             0x104b9
+#define regBIF_CFG_DEV0_EPF1_DEVICE_STATUS3_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF1_PCIE_NULL1_ENH_CAP_LIST                                                    0x10500
+#define regBIF_CFG_DEV0_EPF1_PCIE_NULL1_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF1_PCIE_NULL2_ENH_CAP_LIST                                                    0x10580
+#define regBIF_CFG_DEV0_EPF1_PCIE_NULL2_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                              0x10581
+#define regBIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS                                                     0x10582
+#define regBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK                                                       0x10583
+#define regBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY                                                   0x10584
+#define regBIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS                                                       0x10585
+#define regBIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK                                                         0x10586
+#define regBIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL                                                      0x10587
+#define regBIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG0                                                              0x10588
+#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG0_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG1                                                              0x10589
+#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG1_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG2                                                              0x1058a
+#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG2_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG3                                                              0x1058b
+#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG3_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG4                                                              0x1058f
+#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG4_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG0                                                       0x1058f
+#define regBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG0_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG5                                                              0x10590
+#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG5_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG1                                                       0x10590
+#define regBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG1_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG6                                                              0x10591
+#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG6_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG2                                                       0x10591
+#define regBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG2_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG7                                                              0x10592
+#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG7_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG3                                                       0x10592
+#define regBIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG3_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG8                                                              0x10593
+#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG8_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG9                                                              0x10594
+#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG9_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG10                                                             0x10595
+#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG10_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG11                                                             0x10596
+#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG11_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG12                                                             0x10597
+#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG12_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG13                                                             0x10598
+#define regBIF_CFG_DEV0_EPF1_PCIE_HDR_LOG13_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST                                                      0x105b7
+#define regBIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF1_PCIE_ACS_CAP                                                               0x105b8
+#define regBIF_CFG_DEV0_EPF1_PCIE_ACS_CAP_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL                                                              0x105b8
+#define regBIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF1_PCIE_RTR_ENH_CAP_LIST                                                      0x105c7
+#define regBIF_CFG_DEV0_EPF1_PCIE_RTR_ENH_CAP_LIST_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF1_RTR_DATA1                                                                  0x105c8
+#define regBIF_CFG_DEV0_EPF1_RTR_DATA1_BASE_IDX                                                         5
+#define regBIF_CFG_DEV0_EPF1_RTR_DATA2                                                                  0x105c9
+#define regBIF_CFG_DEV0_EPF1_RTR_DATA2_BASE_IDX                                                         5
+#define regBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST                                               0x105ca
+#define regBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_SELECT                                                0x105cb
+#define regBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_SELECT_BASE_IDX                                       5
+#define regBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA                                                       0x105cc
+#define regBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_CAP                                                        0x105cd
+#define regBIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_CAP_BASE_IDX                                               5
+#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST                                                      0x105ce
+#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_CAP                                                               0x105cf
+#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_CAP_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_LATENCY_INDICATOR                                                 0x105d0
+#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_LATENCY_INDICATOR_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS                                                            0x105d1
+#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_CNTL                                                              0x105d1
+#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_CNTL_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0                                              0x105d2
+#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1                                              0x105d2
+#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2                                              0x105d2
+#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3                                              0x105d2
+#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4                                              0x105d3
+#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5                                              0x105d3
+#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6                                              0x105d3
+#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7                                              0x105d3
+#define regBIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST                                                      0x105dc
+#define regBIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF1_PCIE_ARI_CAP                                                               0x105dd
+#define regBIF_CFG_DEV0_EPF1_PCIE_ARI_CAP_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL                                                              0x105dd
+#define regBIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST                                                      0x105de
+#define regBIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST_BASE_IDX                                             5
+#define regBIF_CFG_DEV0_EPF1_PCIE_BAR1_CAP                                                              0x105df
+#define regBIF_CFG_DEV0_EPF1_PCIE_BAR1_CAP_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL                                                             0x105e0
+#define regBIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF1_PCIE_BAR2_CAP                                                              0x105e1
+#define regBIF_CFG_DEV0_EPF1_PCIE_BAR2_CAP_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL                                                             0x105e2
+#define regBIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF1_PCIE_BAR3_CAP                                                              0x105e3
+#define regBIF_CFG_DEV0_EPF1_PCIE_BAR3_CAP_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL                                                             0x105e4
+#define regBIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF1_PCIE_BAR4_CAP                                                              0x105e5
+#define regBIF_CFG_DEV0_EPF1_PCIE_BAR4_CAP_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL                                                             0x105e6
+#define regBIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF1_PCIE_BAR5_CAP                                                              0x105e7
+#define regBIF_CFG_DEV0_EPF1_PCIE_BAR5_CAP_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL                                                             0x105e8
+#define regBIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF1_PCIE_BAR6_CAP                                                              0x105e9
+#define regBIF_CFG_DEV0_EPF1_PCIE_BAR6_CAP_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL                                                             0x105ea
+#define regBIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST                                                    0x105f1
+#define regBIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF1_PCIE_PASID_CAP                                                             0x105f2
+#define regBIF_CFG_DEV0_EPF1_PCIE_PASID_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL                                                            0x105f2
+#define regBIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST                                                    0x105f3
+#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP                                                             0x105f4
+#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL                                                         0x105f5
+#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_STATUS                                                          0x105f5
+#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_STATUS_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_INITIAL_VFS                                                     0x105f6
+#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_INITIAL_VFS_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_TOTAL_VFS                                                       0x105f6
+#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_TOTAL_VFS_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_NUM_VFS                                                         0x105f7
+#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_NUM_VFS_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_FUNC_DEP_LINK                                                   0x105f7
+#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_FUNC_DEP_LINK_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_FIRST_VF_OFFSET                                                 0x105f8
+#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_FIRST_VF_OFFSET_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_STRIDE                                                       0x105f8
+#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_STRIDE_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_DEVICE_ID                                                    0x105f9
+#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_DEVICE_ID_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE                                             0x105fa
+#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE_BASE_IDX                                    5
+#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_SYSTEM_PAGE_SIZE                                                0x105fb
+#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_SYSTEM_PAGE_SIZE_BASE_IDX                                       5
+#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_0                                                  0x105fc
+#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_0_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_1                                                  0x105fd
+#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_1_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_2                                                  0x105fe
+#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_2_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_3                                                  0x105ff
+#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_3_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_4                                                  0x10600
+#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_4_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_5                                                  0x10601
+#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_5_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET                                 0x10602
+#define regBIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_BASE_IDX                        5
+#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST                                            0x10638
+#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST_BASE_IDX                                   5
+#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CAP                                                    0x10639
+#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CAP_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL                                                   0x1063a
+#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CAP                                                    0x1063b
+#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CAP_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL                                                   0x1063c
+#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CAP                                                    0x1063d
+#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CAP_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL                                                   0x1063e
+#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CAP                                                    0x1063f
+#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CAP_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL                                                   0x10640
+#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CAP                                                    0x10641
+#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CAP_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL                                                   0x10642
+#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CAP                                                    0x10643
+#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CAP_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL                                                   0x10644
+#define regBIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL_BASE_IDX                                          5
+
+
+// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf1_vf0_bifcfgdecp
+// base address: 0x10141000
+#define regBIF_CFG_DEV0_EPF1_VF0_VENDOR_ID                                                              0x10400
+#define regBIF_CFG_DEV0_EPF1_VF0_VENDOR_ID_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF1_VF0_DEVICE_ID                                                              0x10400
+#define regBIF_CFG_DEV0_EPF1_VF0_DEVICE_ID_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF1_VF0_COMMAND                                                                0x10401
+#define regBIF_CFG_DEV0_EPF1_VF0_COMMAND_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF1_VF0_STATUS                                                                 0x10401
+#define regBIF_CFG_DEV0_EPF1_VF0_STATUS_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_EPF1_VF0_REVISION_ID                                                            0x10402
+#define regBIF_CFG_DEV0_EPF1_VF0_REVISION_ID_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF1_VF0_PROG_INTERFACE                                                         0x10402
+#define regBIF_CFG_DEV0_EPF1_VF0_PROG_INTERFACE_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF1_VF0_SUB_CLASS                                                              0x10402
+#define regBIF_CFG_DEV0_EPF1_VF0_SUB_CLASS_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF1_VF0_BASE_CLASS                                                             0x10402
+#define regBIF_CFG_DEV0_EPF1_VF0_BASE_CLASS_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF1_VF0_CACHE_LINE                                                             0x10403
+#define regBIF_CFG_DEV0_EPF1_VF0_CACHE_LINE_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF1_VF0_LATENCY                                                                0x10403
+#define regBIF_CFG_DEV0_EPF1_VF0_LATENCY_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF1_VF0_HEADER                                                                 0x10403
+#define regBIF_CFG_DEV0_EPF1_VF0_HEADER_BASE_IDX                                                        5
+#define regBIF_CFG_DEV0_EPF1_VF0_BIST                                                                   0x10403
+#define regBIF_CFG_DEV0_EPF1_VF0_BIST_BASE_IDX                                                          5
+#define regBIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_1                                                            0x10404
+#define regBIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_1_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_2                                                            0x10405
+#define regBIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_2_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_3                                                            0x10406
+#define regBIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_3_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_4                                                            0x10407
+#define regBIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_4_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_5                                                            0x10408
+#define regBIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_5_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_6                                                            0x10409
+#define regBIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_6_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF1_VF0_CARDBUS_CIS_PTR                                                        0x1040a
+#define regBIF_CFG_DEV0_EPF1_VF0_CARDBUS_CIS_PTR_BASE_IDX                                               5
+#define regBIF_CFG_DEV0_EPF1_VF0_ADAPTER_ID                                                             0x1040b
+#define regBIF_CFG_DEV0_EPF1_VF0_ADAPTER_ID_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF1_VF0_ROM_BASE_ADDR                                                          0x1040c
+#define regBIF_CFG_DEV0_EPF1_VF0_ROM_BASE_ADDR_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF1_VF0_CAP_PTR                                                                0x1040d
+#define regBIF_CFG_DEV0_EPF1_VF0_CAP_PTR_BASE_IDX                                                       5
+#define regBIF_CFG_DEV0_EPF1_VF0_INTERRUPT_LINE                                                         0x1040f
+#define regBIF_CFG_DEV0_EPF1_VF0_INTERRUPT_LINE_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF1_VF0_INTERRUPT_PIN                                                          0x1040f
+#define regBIF_CFG_DEV0_EPF1_VF0_INTERRUPT_PIN_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF1_VF0_MIN_GRANT                                                              0x1040f
+#define regBIF_CFG_DEV0_EPF1_VF0_MIN_GRANT_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF1_VF0_MAX_LATENCY                                                            0x1040f
+#define regBIF_CFG_DEV0_EPF1_VF0_MAX_LATENCY_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_CAP_LIST                                                          0x10419
+#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_CAP_LIST_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_CAP                                                               0x10419
+#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_CAP_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP                                                             0x1041a
+#define regBIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL                                                            0x1041b
+#define regBIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS                                                          0x1041b
+#define regBIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF1_VF0_LINK_CAP                                                               0x1041c
+#define regBIF_CFG_DEV0_EPF1_VF0_LINK_CAP_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF1_VF0_LINK_CNTL                                                              0x1041d
+#define regBIF_CFG_DEV0_EPF1_VF0_LINK_CNTL_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF1_VF0_LINK_STATUS                                                            0x1041d
+#define regBIF_CFG_DEV0_EPF1_VF0_LINK_STATUS_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2                                                            0x10422
+#define regBIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL2                                                           0x10423
+#define regBIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL2_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS2                                                         0x10423
+#define regBIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS2_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF1_VF0_LINK_CAP2                                                              0x10424
+#define regBIF_CFG_DEV0_EPF1_VF0_LINK_CAP2_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF1_VF0_LINK_CNTL2                                                             0x10425
+#define regBIF_CFG_DEV0_EPF1_VF0_LINK_CNTL2_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF1_VF0_LINK_STATUS2                                                           0x10425
+#define regBIF_CFG_DEV0_EPF1_VF0_LINK_STATUS2_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF1_VF0_MSI_CAP_LIST                                                           0x10428
+#define regBIF_CFG_DEV0_EPF1_VF0_MSI_CAP_LIST_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF1_VF0_MSI_MSG_CNTL                                                           0x10428
+#define regBIF_CFG_DEV0_EPF1_VF0_MSI_MSG_CNTL_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF1_VF0_MSI_MSG_ADDR_LO                                                        0x10429
+#define regBIF_CFG_DEV0_EPF1_VF0_MSI_MSG_ADDR_LO_BASE_IDX                                               5
+#define regBIF_CFG_DEV0_EPF1_VF0_MSI_MSG_ADDR_HI                                                        0x1042a
+#define regBIF_CFG_DEV0_EPF1_VF0_MSI_MSG_ADDR_HI_BASE_IDX                                               5
+#define regBIF_CFG_DEV0_EPF1_VF0_MSI_MSG_DATA                                                           0x1042a
+#define regBIF_CFG_DEV0_EPF1_VF0_MSI_MSG_DATA_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF1_VF0_MSI_EXT_MSG_DATA                                                       0x1042a
+#define regBIF_CFG_DEV0_EPF1_VF0_MSI_EXT_MSG_DATA_BASE_IDX                                              5
+#define regBIF_CFG_DEV0_EPF1_VF0_MSI_MASK                                                               0x1042b
+#define regBIF_CFG_DEV0_EPF1_VF0_MSI_MASK_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF1_VF0_MSI_MSG_DATA_64                                                        0x1042b
+#define regBIF_CFG_DEV0_EPF1_VF0_MSI_MSG_DATA_64_BASE_IDX                                               5
+#define regBIF_CFG_DEV0_EPF1_VF0_MSI_EXT_MSG_DATA_64                                                    0x1042b
+#define regBIF_CFG_DEV0_EPF1_VF0_MSI_EXT_MSG_DATA_64_BASE_IDX                                           5
+#define regBIF_CFG_DEV0_EPF1_VF0_MSI_MASK_64                                                            0x1042c
+#define regBIF_CFG_DEV0_EPF1_VF0_MSI_MASK_64_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF1_VF0_MSI_PENDING                                                            0x1042c
+#define regBIF_CFG_DEV0_EPF1_VF0_MSI_PENDING_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF1_VF0_MSI_PENDING_64                                                         0x1042d
+#define regBIF_CFG_DEV0_EPF1_VF0_MSI_PENDING_64_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF1_VF0_MSIX_CAP_LIST                                                          0x10430
+#define regBIF_CFG_DEV0_EPF1_VF0_MSIX_CAP_LIST_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF1_VF0_MSIX_MSG_CNTL                                                          0x10430
+#define regBIF_CFG_DEV0_EPF1_VF0_MSIX_MSG_CNTL_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF1_VF0_MSIX_TABLE                                                             0x10431
+#define regBIF_CFG_DEV0_EPF1_VF0_MSIX_TABLE_BASE_IDX                                                    5
+#define regBIF_CFG_DEV0_EPF1_VF0_MSIX_PBA                                                               0x10432
+#define regBIF_CFG_DEV0_EPF1_VF0_MSIX_PBA_BASE_IDX                                                      5
+#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                      0x10440
+#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_BASE_IDX                             5
+#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC_HDR                                               0x10441
+#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC_HDR_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC1                                                  0x10442
+#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC1_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC2                                                  0x10443
+#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC2_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_DEVICE3_ENH_CAP_LIST                                              0x104b6
+#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_DEVICE3_ENH_CAP_LIST_BASE_IDX                                     5
+#define regBIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP3                                                            0x104b7
+#define regBIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP3_BASE_IDX                                                   5
+#define regBIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL3                                                           0x104b8
+#define regBIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL3_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS3                                                         0x104b9
+#define regBIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS3_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_NULL1_ENH_CAP_LIST                                                0x10500
+#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_NULL1_ENH_CAP_LIST_BASE_IDX                                       5
+#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_NULL2_ENH_CAP_LIST                                                0x10580
+#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_NULL2_ENH_CAP_LIST_BASE_IDX                                       5
+#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                          0x10581
+#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST_BASE_IDX                                 5
+#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS                                                 0x10582
+#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS_BASE_IDX                                        5
+#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK                                                   0x10583
+#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY                                               0x10584
+#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY_BASE_IDX                                      5
+#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_STATUS                                                   0x10585
+#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_STATUS_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_MASK                                                     0x10586
+#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_MASK_BASE_IDX                                            5
+#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_CAP_CNTL                                                  0x10587
+#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_CAP_CNTL_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG0                                                          0x10588
+#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG0_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG1                                                          0x10589
+#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG1_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG2                                                          0x1058a
+#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG2_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG3                                                          0x1058b
+#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG3_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG4                                                          0x1058f
+#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG4_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_TLP_PREFIX_LOG0                                                   0x1058f
+#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_TLP_PREFIX_LOG0_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG5                                                          0x10590
+#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG5_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_TLP_PREFIX_LOG1                                                   0x10590
+#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_TLP_PREFIX_LOG1_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG6                                                          0x10591
+#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG6_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_TLP_PREFIX_LOG2                                                   0x10591
+#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_TLP_PREFIX_LOG2_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG7                                                          0x10592
+#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG7_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_TLP_PREFIX_LOG3                                                   0x10592
+#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_TLP_PREFIX_LOG3_BASE_IDX                                          5
+#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG8                                                          0x10593
+#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG8_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG9                                                          0x10594
+#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG9_BASE_IDX                                                 5
+#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG10                                                         0x10595
+#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG10_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG11                                                         0x10596
+#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG11_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG12                                                         0x10597
+#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG12_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG13                                                         0x10598
+#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG13_BASE_IDX                                                5
+#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_RTR_ENH_CAP_LIST                                                  0x105c7
+#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_RTR_ENH_CAP_LIST_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF1_VF0_RTR_DATA1                                                              0x105c8
+#define regBIF_CFG_DEV0_EPF1_VF0_RTR_DATA1_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF1_VF0_RTR_DATA2                                                              0x105c9
+#define regBIF_CFG_DEV0_EPF1_VF0_RTR_DATA2_BASE_IDX                                                     5
+#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_ENH_CAP_LIST                                                  0x105dc
+#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_ENH_CAP_LIST_BASE_IDX                                         5
+#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_CAP                                                           0x105dd
+#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_CAP_BASE_IDX                                                  5
+#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_CNTL                                                          0x105dd
+#define regBIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_CNTL_BASE_IDX                                                 5
+
+
+// addressBlock: nbif0_nbif0_rcc_dev0_RCCPORTDEC
+// base address: 0x10131000
+#define regRCC_DEV0_1_RCC_VDM_SUPPORT                                                                   0xc440
+#define regRCC_DEV0_1_RCC_VDM_SUPPORT_BASE_IDX                                                          5
+#define regRCC_DEV0_1_RCC_BUS_CNTL                                                                      0xc441
+#define regRCC_DEV0_1_RCC_BUS_CNTL_BASE_IDX                                                             5
+#define regRCC_DEV0_1_RCC_FEATURES_CONTROL_MISC                                                         0xc442
+#define regRCC_DEV0_1_RCC_FEATURES_CONTROL_MISC_BASE_IDX                                                5
+#define regRCC_DEV0_1_RCC_DEV0_LINK_CNTL                                                                0xc443
+#define regRCC_DEV0_1_RCC_DEV0_LINK_CNTL_BASE_IDX                                                       5
+#define regRCC_DEV0_1_RCC_CMN_LINK_CNTL                                                                 0xc444
+#define regRCC_DEV0_1_RCC_CMN_LINK_CNTL_BASE_IDX                                                        5
+#define regRCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE                                                        0xc445
+#define regRCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE_BASE_IDX                                               5
+#define regRCC_DEV0_1_RCC_LTR_LSWITCH_CNTL                                                              0xc446
+#define regRCC_DEV0_1_RCC_LTR_LSWITCH_CNTL_BASE_IDX                                                     5
+#define regRCC_DEV0_1_RCC_MH_ARB_CNTL                                                                   0xc447
+#define regRCC_DEV0_1_RCC_MH_ARB_CNTL_BASE_IDX                                                          5
+#define regRCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0                                                            0xc448
+#define regRCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0_BASE_IDX                                                   5
+#define regRCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1                                                            0xc449
+#define regRCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1_BASE_IDX                                                   5
+
+
+// addressBlock: nbif0_nbif0_rcc_ep_dev0_RCCPORTDEC
+// base address: 0x10131000
+#define regRCC_EP_DEV0_1_EP_PCIE_SCRATCH                                                                0xc44c
+#define regRCC_EP_DEV0_1_EP_PCIE_SCRATCH_BASE_IDX                                                       5
+#define regRCC_EP_DEV0_1_EP_PCIE_CNTL                                                                   0xc44e
+#define regRCC_EP_DEV0_1_EP_PCIE_CNTL_BASE_IDX                                                          5
+#define regRCC_EP_DEV0_1_EP_PCIE_INT_CNTL                                                               0xc44f
+#define regRCC_EP_DEV0_1_EP_PCIE_INT_CNTL_BASE_IDX                                                      5
+#define regRCC_EP_DEV0_1_EP_PCIE_INT_STATUS                                                             0xc450
+#define regRCC_EP_DEV0_1_EP_PCIE_INT_STATUS_BASE_IDX                                                    5
+#define regRCC_EP_DEV0_1_EP_PCIE_RX_CNTL2                                                               0xc451
+#define regRCC_EP_DEV0_1_EP_PCIE_RX_CNTL2_BASE_IDX                                                      5
+#define regRCC_EP_DEV0_1_EP_PCIE_BUS_CNTL                                                               0xc452
+#define regRCC_EP_DEV0_1_EP_PCIE_BUS_CNTL_BASE_IDX                                                      5
+#define regRCC_EP_DEV0_1_EP_PCIE_CFG_CNTL                                                               0xc453
+#define regRCC_EP_DEV0_1_EP_PCIE_CFG_CNTL_BASE_IDX                                                      5
+#define regRCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL                                                            0xc454
+#define regRCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL_BASE_IDX                                                   5
+#define regRCC_EP_DEV0_1_EP_PCIE_STRAP_MISC                                                             0xc455
+#define regRCC_EP_DEV0_1_EP_PCIE_STRAP_MISC_BASE_IDX                                                    5
+#define regRCC_EP_DEV0_1_EP_PCIE_STRAP_MISC2                                                            0xc456
+#define regRCC_EP_DEV0_1_EP_PCIE_STRAP_MISC2_BASE_IDX                                                   5
+#define regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP                                                             0xc457
+#define regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP_BASE_IDX                                                    5
+#define regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR                                               0xc458
+#define regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR_BASE_IDX                                      5
+#define regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL                                                            0xc458
+#define regRCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL_BASE_IDX                                                   5
+#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0                                               0xc458
+#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX                                      5
+#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1                                               0xc459
+#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX                                      5
+#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2                                               0xc459
+#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX                                      5
+#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3                                               0xc459
+#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX                                      5
+#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4                                               0xc459
+#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX                                      5
+#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5                                               0xc45a
+#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX                                      5
+#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6                                               0xc45a
+#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX                                      5
+#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7                                               0xc45a
+#define regRCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX                                      5
+#define regRCC_EP_DEV0_1_EP_PCIE_PME_CONTROL                                                            0xc45c
+#define regRCC_EP_DEV0_1_EP_PCIE_PME_CONTROL_BASE_IDX                                                   5
+#define regRCC_EP_DEV0_1_EP_PCIEP_RESERVED                                                              0xc45d
+#define regRCC_EP_DEV0_1_EP_PCIEP_RESERVED_BASE_IDX                                                     5
+#define regRCC_EP_DEV0_1_EP_PCIE_TX_CNTL                                                                0xc45f
+#define regRCC_EP_DEV0_1_EP_PCIE_TX_CNTL_BASE_IDX                                                       5
+#define regRCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID                                                        0xc460
+#define regRCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID_BASE_IDX                                               5
+#define regRCC_EP_DEV0_1_EP_PCIE_ERR_CNTL                                                               0xc461
+#define regRCC_EP_DEV0_1_EP_PCIE_ERR_CNTL_BASE_IDX                                                      5
+#define regRCC_EP_DEV0_1_EP_PCIE_RX_CNTL                                                                0xc462
+#define regRCC_EP_DEV0_1_EP_PCIE_RX_CNTL_BASE_IDX                                                       5
+#define regRCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL                                                          0xc463
+#define regRCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL_BASE_IDX                                                 5
+#define regRCC_EP_DEV0_1_EP_PCIE_DEVICE_CNTL3                                                           0xc464
+#define regRCC_EP_DEV0_1_EP_PCIE_DEVICE_CNTL3_BASE_IDX                                                  5
+
+
+// addressBlock: nbif0_nbif0_rcc_dwn_dev0_RCCPORTDEC
+// base address: 0x10131000
+#define regRCC_DWN_DEV0_1_DN_PCIE_RESERVED                                                              0xc468
+#define regRCC_DWN_DEV0_1_DN_PCIE_RESERVED_BASE_IDX                                                     5
+#define regRCC_DWN_DEV0_1_DN_PCIE_SCRATCH                                                               0xc469
+#define regRCC_DWN_DEV0_1_DN_PCIE_SCRATCH_BASE_IDX                                                      5
+#define regRCC_DWN_DEV0_1_DN_PCIE_CNTL                                                                  0xc46b
+#define regRCC_DWN_DEV0_1_DN_PCIE_CNTL_BASE_IDX                                                         5
+#define regRCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL                                                           0xc46c
+#define regRCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL_BASE_IDX                                                  5
+#define regRCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2                                                              0xc46d
+#define regRCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2_BASE_IDX                                                     5
+#define regRCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL                                                              0xc46e
+#define regRCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL_BASE_IDX                                                     5
+#define regRCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL                                                              0xc46f
+#define regRCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL_BASE_IDX                                                     5
+#define regRCC_DWN_DEV0_1_DN_PCIE_STRAP_F0                                                              0xc470
+#define regRCC_DWN_DEV0_1_DN_PCIE_STRAP_F0_BASE_IDX                                                     5
+#define regRCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC                                                            0xc471
+#define regRCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC_BASE_IDX                                                   5
+#define regRCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC2                                                           0xc472
+#define regRCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC2_BASE_IDX                                                  5
+
+
+// addressBlock: nbif0_nbif0_rcc_dwnp_dev0_RCCPORTDEC
+// base address: 0x10131000
+#define regRCC_DWNP_DEV0_1_PCIE_ERR_CNTL                                                                0xc475
+#define regRCC_DWNP_DEV0_1_PCIE_ERR_CNTL_BASE_IDX                                                       5
+#define regRCC_DWNP_DEV0_1_PCIE_RX_CNTL                                                                 0xc476
+#define regRCC_DWNP_DEV0_1_PCIE_RX_CNTL_BASE_IDX                                                        5
+#define regRCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL                                                           0xc477
+#define regRCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL_BASE_IDX                                                  5
+#define regRCC_DWNP_DEV0_1_PCIE_LC_CNTL2                                                                0xc478
+#define regRCC_DWNP_DEV0_1_PCIE_LC_CNTL2_BASE_IDX                                                       5
+#define regRCC_DWNP_DEV0_1_PCIEP_STRAP_MISC                                                             0xc479
+#define regRCC_DWNP_DEV0_1_PCIEP_STRAP_MISC_BASE_IDX                                                    5
+#define regRCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP                                                         0xc47a
+#define regRCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP_BASE_IDX                                                5
+
+
+// addressBlock: nbif0_nbif0_rcc_pfc_amdgfx_RCCPFCDEC
+// base address: 0x10134000
+#define regRCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL                                                              0xd040
+#define regRCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL_BASE_IDX                                                     5
+#define regRCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE                                                           0xd041
+#define regRCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE_BASE_IDX                                                  5
+#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0                                                      0xd042
+#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0_BASE_IDX                                             5
+#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_1                                                      0xd043
+#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_1_BASE_IDX                                             5
+#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_2                                                      0xd044
+#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_2_BASE_IDX                                             5
+#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_3                                                      0xd045
+#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_3_BASE_IDX                                             5
+#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_4                                                      0xd046
+#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_4_BASE_IDX                                             5
+#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_5                                                      0xd047
+#define regRCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_5_BASE_IDX                                             5
+#define regRCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL                                                           0xd048
+#define regRCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL_BASE_IDX                                                  5
+#define regRCC_PFC_AMDGFX_RCC_PFC_MISC_CNTL                                                             0xd049
+#define regRCC_PFC_AMDGFX_RCC_PFC_MISC_CNTL_BASE_IDX                                                    5
+#define regRCC_PFC_AMDGFX_RCC_NFC                                                                       0xd04a
+#define regRCC_PFC_AMDGFX_RCC_NFC_BASE_IDX                                                              5
+
+
+// addressBlock: nbif0_nbif0_rcc_shadow_reg_shadowdec
+// base address: 0x10130000
+#define regSHADOW_COMMAND                                                                               0xc001
+#define regSHADOW_COMMAND_BASE_IDX                                                                      5
+#define regSHADOW_BASE_ADDR_1                                                                           0xc004
+#define regSHADOW_BASE_ADDR_1_BASE_IDX                                                                  5
+#define regSHADOW_BASE_ADDR_2                                                                           0xc005
+#define regSHADOW_BASE_ADDR_2_BASE_IDX                                                                  5
+#define regSHADOW_SUB_BUS_NUMBER_LATENCY                                                                0xc006
+#define regSHADOW_SUB_BUS_NUMBER_LATENCY_BASE_IDX                                                       5
+#define regSHADOW_IO_BASE_LIMIT                                                                         0xc007
+#define regSHADOW_IO_BASE_LIMIT_BASE_IDX                                                                5
+#define regSHADOW_MEM_BASE_LIMIT                                                                        0xc008
+#define regSHADOW_MEM_BASE_LIMIT_BASE_IDX                                                               5
+#define regSHADOW_PREF_BASE_LIMIT                                                                       0xc009
+#define regSHADOW_PREF_BASE_LIMIT_BASE_IDX                                                              5
+#define regSHADOW_PREF_BASE_UPPER                                                                       0xc00a
+#define regSHADOW_PREF_BASE_UPPER_BASE_IDX                                                              5
+#define regSHADOW_PREF_LIMIT_UPPER                                                                      0xc00b
+#define regSHADOW_PREF_LIMIT_UPPER_BASE_IDX                                                             5
+#define regSHADOW_IO_BASE_LIMIT_HI                                                                      0xc00c
+#define regSHADOW_IO_BASE_LIMIT_HI_BASE_IDX                                                             5
+#define regSHADOW_IRQ_BRIDGE_CNTL                                                                       0xc00f
+#define regSHADOW_IRQ_BRIDGE_CNTL_BASE_IDX                                                              5
+#define regSUC_INDEX                                                                                    0xc038
+#define regSUC_INDEX_BASE_IDX                                                                           5
+#define regSUC_DATA                                                                                     0xc039
+#define regSUC_DATA_BASE_IDX                                                                            5
+
+
+// addressBlock: nbif0_nbif0_bif_swus_SUMDEC
+// base address: 0x1013b000
+#define regSUM_INDEX                                                                                    0xec38
+#define regSUM_INDEX_BASE_IDX                                                                           5
+#define regSUM_DATA                                                                                     0xec39
+#define regSUM_DATA_BASE_IDX                                                                            5
+#define regSUM_INDEX_HI                                                                                 0xec3b
+#define regSUM_INDEX_HI_BASE_IDX                                                                        5
+
+
+// addressBlock: nbif0_nbif0_rcc_strap_rcc_strap_internal
+// base address: 0x10100000
+#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP0                                                              0xc400
+#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP0_BASE_IDX                                                     5
+#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP1                                                              0xc401
+#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP1_BASE_IDX                                                     5
+#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP2                                                              0xc402
+#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP2_BASE_IDX                                                     5
+#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP3                                                              0xc403
+#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP3_BASE_IDX                                                     5
+#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP4                                                              0xc404
+#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP4_BASE_IDX                                                     5
+#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP5                                                              0xc405
+#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP5_BASE_IDX                                                     5
+#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP6                                                              0xc406
+#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP6_BASE_IDX                                                     5
+#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP7                                                              0xc407
+#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP7_BASE_IDX                                                     5
+#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP8                                                              0xc408
+#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP8_BASE_IDX                                                     5
+#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP9                                                              0xc409
+#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP9_BASE_IDX                                                     5
+#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP10                                                             0xc40a
+#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP10_BASE_IDX                                                    5
+#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP11                                                             0xc40b
+#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP11_BASE_IDX                                                    5
+#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP12                                                             0xc40c
+#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP12_BASE_IDX                                                    5
+#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP13                                                             0xc40d
+#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP13_BASE_IDX                                                    5
+#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP14                                                             0xc40e
+#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP14_BASE_IDX                                                    5
+#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP15                                                             0xc40f
+#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP15_BASE_IDX                                                    5
+#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP16                                                             0xc410
+#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP16_BASE_IDX                                                    5
+#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP17                                                             0xc411
+#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP17_BASE_IDX                                                    5
+#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP18                                                             0xc412
+#define regRCC_STRAP1_RCC_DEV0_PORT_STRAP18_BASE_IDX                                                    5
+#define regRCC_DEV1_PORT_STRAP0                                                                         0xc480
+#define regRCC_DEV1_PORT_STRAP0_BASE_IDX                                                                5
+#define regRCC_DEV1_PORT_STRAP1                                                                         0xc481
+#define regRCC_DEV1_PORT_STRAP1_BASE_IDX                                                                5
+#define regRCC_DEV1_PORT_STRAP2                                                                         0xc482
+#define regRCC_DEV1_PORT_STRAP2_BASE_IDX                                                                5
+#define regRCC_DEV1_PORT_STRAP3                                                                         0xc483
+#define regRCC_DEV1_PORT_STRAP3_BASE_IDX                                                                5
+#define regRCC_DEV1_PORT_STRAP4                                                                         0xc484
+#define regRCC_DEV1_PORT_STRAP4_BASE_IDX                                                                5
+#define regRCC_DEV1_PORT_STRAP5                                                                         0xc485
+#define regRCC_DEV1_PORT_STRAP5_BASE_IDX                                                                5
+#define regRCC_DEV1_PORT_STRAP6                                                                         0xc486
+#define regRCC_DEV1_PORT_STRAP6_BASE_IDX                                                                5
+#define regRCC_DEV1_PORT_STRAP7                                                                         0xc487
+#define regRCC_DEV1_PORT_STRAP7_BASE_IDX                                                                5
+#define regRCC_DEV1_PORT_STRAP8                                                                         0xc488
+#define regRCC_DEV1_PORT_STRAP8_BASE_IDX                                                                5
+#define regRCC_DEV1_PORT_STRAP9                                                                         0xc489
+#define regRCC_DEV1_PORT_STRAP9_BASE_IDX                                                                5
+#define regRCC_DEV1_PORT_STRAP10                                                                        0xc48a
+#define regRCC_DEV1_PORT_STRAP10_BASE_IDX                                                               5
+#define regRCC_DEV1_PORT_STRAP11                                                                        0xc48b
+#define regRCC_DEV1_PORT_STRAP11_BASE_IDX                                                               5
+#define regRCC_DEV1_PORT_STRAP12                                                                        0xc48c
+#define regRCC_DEV1_PORT_STRAP12_BASE_IDX                                                               5
+#define regRCC_DEV1_PORT_STRAP13                                                                        0xc48d
+#define regRCC_DEV1_PORT_STRAP13_BASE_IDX                                                               5
+#define regRCC_DEV1_PORT_STRAP14                                                                        0xc48e
+#define regRCC_DEV1_PORT_STRAP14_BASE_IDX                                                               5
+#define regRCC_DEV1_PORT_STRAP15                                                                        0xc48f
+#define regRCC_DEV1_PORT_STRAP15_BASE_IDX                                                               5
+#define regRCC_DEV1_PORT_STRAP16                                                                        0xc490
+#define regRCC_DEV1_PORT_STRAP16_BASE_IDX                                                               5
+#define regRCC_DEV2_PORT_STRAP0                                                                         0xc500
+#define regRCC_DEV2_PORT_STRAP0_BASE_IDX                                                                5
+#define regRCC_DEV2_PORT_STRAP1                                                                         0xc501
+#define regRCC_DEV2_PORT_STRAP1_BASE_IDX                                                                5
+#define regRCC_DEV2_PORT_STRAP2                                                                         0xc502
+#define regRCC_DEV2_PORT_STRAP2_BASE_IDX                                                                5
+#define regRCC_DEV2_PORT_STRAP3                                                                         0xc503
+#define regRCC_DEV2_PORT_STRAP3_BASE_IDX                                                                5
+#define regRCC_DEV2_PORT_STRAP4                                                                         0xc504
+#define regRCC_DEV2_PORT_STRAP4_BASE_IDX                                                                5
+#define regRCC_DEV2_PORT_STRAP5                                                                         0xc505
+#define regRCC_DEV2_PORT_STRAP5_BASE_IDX                                                                5
+#define regRCC_DEV2_PORT_STRAP6                                                                         0xc506
+#define regRCC_DEV2_PORT_STRAP6_BASE_IDX                                                                5
+#define regRCC_DEV2_PORT_STRAP7                                                                         0xc507
+#define regRCC_DEV2_PORT_STRAP7_BASE_IDX                                                                5
+#define regRCC_DEV2_PORT_STRAP8                                                                         0xc508
+#define regRCC_DEV2_PORT_STRAP8_BASE_IDX                                                                5
+#define regRCC_DEV2_PORT_STRAP9                                                                         0xc509
+#define regRCC_DEV2_PORT_STRAP9_BASE_IDX                                                                5
+#define regRCC_DEV2_PORT_STRAP10                                                                        0xc50a
+#define regRCC_DEV2_PORT_STRAP10_BASE_IDX                                                               5
+#define regRCC_DEV2_PORT_STRAP11                                                                        0xc50b
+#define regRCC_DEV2_PORT_STRAP11_BASE_IDX                                                               5
+#define regRCC_DEV2_PORT_STRAP12                                                                        0xc50c
+#define regRCC_DEV2_PORT_STRAP12_BASE_IDX                                                               5
+#define regRCC_DEV2_PORT_STRAP13                                                                        0xc50d
+#define regRCC_DEV2_PORT_STRAP13_BASE_IDX                                                               5
+#define regRCC_DEV2_PORT_STRAP14                                                                        0xc50e
+#define regRCC_DEV2_PORT_STRAP14_BASE_IDX                                                               5
+#define regRCC_DEV2_PORT_STRAP15                                                                        0xc50f
+#define regRCC_DEV2_PORT_STRAP15_BASE_IDX                                                               5
+#define regRCC_DEV2_PORT_STRAP16                                                                        0xc510
+#define regRCC_DEV2_PORT_STRAP16_BASE_IDX                                                               5
+#define regRCC_STRAP1_RCC_BIF_STRAP0                                                                    0xc600
+#define regRCC_STRAP1_RCC_BIF_STRAP0_BASE_IDX                                                           5
+#define regRCC_STRAP1_RCC_BIF_STRAP1                                                                    0xc601
+#define regRCC_STRAP1_RCC_BIF_STRAP1_BASE_IDX                                                           5
+#define regRCC_STRAP1_RCC_BIF_STRAP2                                                                    0xc602
+#define regRCC_STRAP1_RCC_BIF_STRAP2_BASE_IDX                                                           5
+#define regRCC_STRAP1_RCC_BIF_STRAP3                                                                    0xc603
+#define regRCC_STRAP1_RCC_BIF_STRAP3_BASE_IDX                                                           5
+#define regRCC_STRAP1_RCC_BIF_STRAP4                                                                    0xc604
+#define regRCC_STRAP1_RCC_BIF_STRAP4_BASE_IDX                                                           5
+#define regRCC_STRAP1_RCC_BIF_STRAP5                                                                    0xc605
+#define regRCC_STRAP1_RCC_BIF_STRAP5_BASE_IDX                                                           5
+#define regRCC_STRAP1_RCC_BIF_STRAP6                                                                    0xc606
+#define regRCC_STRAP1_RCC_BIF_STRAP6_BASE_IDX                                                           5
+#define regRCC_STRAP1_RCC_BIF_STRAP7                                                                    0xc607
+#define regRCC_STRAP1_RCC_BIF_STRAP7_BASE_IDX                                                           5
+#define regRCC_STRAP1_RCC_BIF_STRAP8                                                                    0xc608
+#define regRCC_STRAP1_RCC_BIF_STRAP8_BASE_IDX                                                           5
+#define regRCC_STRAP1_RCC_BIF_STRAP9                                                                    0xc609
+#define regRCC_STRAP1_RCC_BIF_STRAP9_BASE_IDX                                                           5
+#define regRCC_STRAP1_RCC_BIF_STRAP10                                                                   0xc60a
+#define regRCC_STRAP1_RCC_BIF_STRAP10_BASE_IDX                                                          5
+#define regRCC_STRAP1_RCC_BIF_STRAP11                                                                   0xc60b
+#define regRCC_STRAP1_RCC_BIF_STRAP11_BASE_IDX                                                          5
+#define regRCC_STRAP1_RCC_BIF_STRAP12                                                                   0xc60c
+#define regRCC_STRAP1_RCC_BIF_STRAP12_BASE_IDX                                                          5
+#define regRCC_STRAP1_RCC_BIF_STRAP13                                                                   0xc60d
+#define regRCC_STRAP1_RCC_BIF_STRAP13_BASE_IDX                                                          5
+#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP0                                                              0xd000
+#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP0_BASE_IDX                                                     5
+#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP1                                                              0xd001
+#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP1_BASE_IDX                                                     5
+#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP2                                                              0xd002
+#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP2_BASE_IDX                                                     5
+#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP3                                                              0xd003
+#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP3_BASE_IDX                                                     5
+#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP4                                                              0xd004
+#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP4_BASE_IDX                                                     5
+#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP5                                                              0xd005
+#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP5_BASE_IDX                                                     5
+#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP8                                                              0xd008
+#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP8_BASE_IDX                                                     5
+#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP9                                                              0xd009
+#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP9_BASE_IDX                                                     5
+#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP13                                                             0xd00d
+#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP13_BASE_IDX                                                    5
+#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP14                                                             0xd00e
+#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP14_BASE_IDX                                                    5
+#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP15                                                             0xd00f
+#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP15_BASE_IDX                                                    5
+#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP16                                                             0xd010
+#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP16_BASE_IDX                                                    5
+#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP17                                                             0xd011
+#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP17_BASE_IDX                                                    5
+#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP18                                                             0xd012
+#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP18_BASE_IDX                                                    5
+#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP19                                                             0xd013
+#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP19_BASE_IDX                                                    5
+#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP22                                                             0xd016
+#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP22_BASE_IDX                                                    5
+#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP23                                                             0xd017
+#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP23_BASE_IDX                                                    5
+#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP24                                                             0xd018
+#define regRCC_STRAP1_RCC_DEV0_EPF0_STRAP24_BASE_IDX                                                    5
+#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP0                                                              0xd080
+#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP0_BASE_IDX                                                     5
+#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP1                                                              0xd081
+#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP1_BASE_IDX                                                     5
+#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP2                                                              0xd082
+#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP2_BASE_IDX                                                     5
+#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP3                                                              0xd083
+#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP3_BASE_IDX                                                     5
+#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP4                                                              0xd084
+#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP4_BASE_IDX                                                     5
+#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP5                                                              0xd085
+#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP5_BASE_IDX                                                     5
+#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP6                                                              0xd086
+#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP6_BASE_IDX                                                     5
+#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP7                                                              0xd087
+#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP7_BASE_IDX                                                     5
+#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP8                                                              0xd088
+#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP8_BASE_IDX                                                     5
+#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP9                                                              0xd089
+#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP9_BASE_IDX                                                     5
+#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP10                                                             0xd08a
+#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP10_BASE_IDX                                                    5
+#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP11                                                             0xd08b
+#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP11_BASE_IDX                                                    5
+#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP12                                                             0xd08c
+#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP12_BASE_IDX                                                    5
+#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP13                                                             0xd08d
+#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP13_BASE_IDX                                                    5
+#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP14                                                             0xd08e
+#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP14_BASE_IDX                                                    5
+#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP15                                                             0xd08f
+#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP15_BASE_IDX                                                    5
+#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP16                                                             0xd090
+#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP16_BASE_IDX                                                    5
+#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP17                                                             0xd091
+#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP17_BASE_IDX                                                    5
+#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP18                                                             0xd092
+#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP18_BASE_IDX                                                    5
+#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP19                                                             0xd093
+#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP19_BASE_IDX                                                    5
+#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP20                                                             0xd094
+#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP20_BASE_IDX                                                    5
+#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP21                                                             0xd095
+#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP21_BASE_IDX                                                    5
+#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP23                                                             0xd097
+#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP23_BASE_IDX                                                    5
+#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP24                                                             0xd098
+#define regRCC_STRAP1_RCC_DEV0_EPF1_STRAP24_BASE_IDX                                                    5
+#define regRCC_DEV0_EPF2_STRAP0                                                                         0xd100
+#define regRCC_DEV0_EPF2_STRAP0_BASE_IDX                                                                5
+#define regRCC_DEV0_EPF2_STRAP2                                                                         0xd102
+#define regRCC_DEV0_EPF2_STRAP2_BASE_IDX                                                                5
+#define regRCC_DEV0_EPF2_STRAP3                                                                         0xd103
+#define regRCC_DEV0_EPF2_STRAP3_BASE_IDX                                                                5
+#define regRCC_DEV0_EPF2_STRAP4                                                                         0xd104
+#define regRCC_DEV0_EPF2_STRAP4_BASE_IDX                                                                5
+#define regRCC_DEV0_EPF2_STRAP5                                                                         0xd105
+#define regRCC_DEV0_EPF2_STRAP5_BASE_IDX                                                                5
+#define regRCC_DEV0_EPF2_STRAP6                                                                         0xd106
+#define regRCC_DEV0_EPF2_STRAP6_BASE_IDX                                                                5
+#define regRCC_DEV0_EPF2_STRAP7                                                                         0xd107
+#define regRCC_DEV0_EPF2_STRAP7_BASE_IDX                                                                5
+#define regRCC_DEV0_EPF2_STRAP9                                                                         0xd109
+#define regRCC_DEV0_EPF2_STRAP9_BASE_IDX                                                                5
+#define regRCC_DEV0_EPF2_STRAP10                                                                        0xd10a
+#define regRCC_DEV0_EPF2_STRAP10_BASE_IDX                                                               5
+#define regRCC_DEV0_EPF2_STRAP11                                                                        0xd10b
+#define regRCC_DEV0_EPF2_STRAP11_BASE_IDX                                                               5
+#define regRCC_DEV0_EPF2_STRAP12                                                                        0xd10c
+#define regRCC_DEV0_EPF2_STRAP12_BASE_IDX                                                               5
+#define regRCC_DEV0_EPF2_STRAP13                                                                        0xd10d
+#define regRCC_DEV0_EPF2_STRAP13_BASE_IDX                                                               5
+#define regRCC_DEV0_EPF2_STRAP14                                                                        0xd10e
+#define regRCC_DEV0_EPF2_STRAP14_BASE_IDX                                                               5
+#define regRCC_DEV0_EPF2_STRAP15                                                                        0xd10f
+#define regRCC_DEV0_EPF2_STRAP15_BASE_IDX                                                               5
+#define regRCC_DEV0_EPF2_STRAP16                                                                        0xd110
+#define regRCC_DEV0_EPF2_STRAP16_BASE_IDX                                                               5
+#define regRCC_DEV0_EPF2_STRAP20                                                                        0xd114
+#define regRCC_DEV0_EPF2_STRAP20_BASE_IDX                                                               5
+#define regRCC_DEV0_EPF3_STRAP0                                                                         0xd180
+#define regRCC_DEV0_EPF3_STRAP0_BASE_IDX                                                                5
+#define regRCC_DEV0_EPF3_STRAP2                                                                         0xd182
+#define regRCC_DEV0_EPF3_STRAP2_BASE_IDX                                                                5
+#define regRCC_DEV0_EPF3_STRAP3                                                                         0xd183
+#define regRCC_DEV0_EPF3_STRAP3_BASE_IDX                                                                5
+#define regRCC_DEV0_EPF3_STRAP4                                                                         0xd184
+#define regRCC_DEV0_EPF3_STRAP4_BASE_IDX                                                                5
+#define regRCC_DEV0_EPF3_STRAP5                                                                         0xd185
+#define regRCC_DEV0_EPF3_STRAP5_BASE_IDX                                                                5
+#define regRCC_DEV0_EPF3_STRAP6                                                                         0xd186
+#define regRCC_DEV0_EPF3_STRAP6_BASE_IDX                                                                5
+#define regRCC_DEV0_EPF3_STRAP7                                                                         0xd187
+#define regRCC_DEV0_EPF3_STRAP7_BASE_IDX                                                                5
+#define regRCC_DEV0_EPF3_STRAP9                                                                         0xd189
+#define regRCC_DEV0_EPF3_STRAP9_BASE_IDX                                                                5
+#define regRCC_DEV0_EPF3_STRAP10                                                                        0xd18a
+#define regRCC_DEV0_EPF3_STRAP10_BASE_IDX                                                               5
+#define regRCC_DEV0_EPF3_STRAP11                                                                        0xd18b
+#define regRCC_DEV0_EPF3_STRAP11_BASE_IDX                                                               5
+#define regRCC_DEV0_EPF3_STRAP12                                                                        0xd18c
+#define regRCC_DEV0_EPF3_STRAP12_BASE_IDX                                                               5
+#define regRCC_DEV0_EPF3_STRAP13                                                                        0xd18d
+#define regRCC_DEV0_EPF3_STRAP13_BASE_IDX                                                               5
+#define regRCC_DEV0_EPF3_STRAP14                                                                        0xd18e
+#define regRCC_DEV0_EPF3_STRAP14_BASE_IDX                                                               5
+#define regRCC_DEV0_EPF3_STRAP15                                                                        0xd18f
+#define regRCC_DEV0_EPF3_STRAP15_BASE_IDX                                                               5
+#define regRCC_DEV0_EPF3_STRAP16                                                                        0xd190
+#define regRCC_DEV0_EPF3_STRAP16_BASE_IDX                                                               5
+#define regRCC_DEV0_EPF3_STRAP20                                                                        0xd194
+#define regRCC_DEV0_EPF3_STRAP20_BASE_IDX                                                               5
+#define regRCC_DEV0_EPF4_STRAP0                                                                         0xd200
+#define regRCC_DEV0_EPF4_STRAP0_BASE_IDX                                                                5
+#define regRCC_DEV0_EPF4_STRAP2                                                                         0xd202
+#define regRCC_DEV0_EPF4_STRAP2_BASE_IDX                                                                5
+#define regRCC_DEV0_EPF4_STRAP3                                                                         0xd203
+#define regRCC_DEV0_EPF4_STRAP3_BASE_IDX                                                                5
+#define regRCC_DEV0_EPF4_STRAP4                                                                         0xd204
+#define regRCC_DEV0_EPF4_STRAP4_BASE_IDX                                                                5
+#define regRCC_DEV0_EPF4_STRAP5                                                                         0xd205
+#define regRCC_DEV0_EPF4_STRAP5_BASE_IDX                                                                5
+#define regRCC_DEV0_EPF4_STRAP6                                                                         0xd206
+#define regRCC_DEV0_EPF4_STRAP6_BASE_IDX                                                                5
+#define regRCC_DEV0_EPF4_STRAP7                                                                         0xd207
+#define regRCC_DEV0_EPF4_STRAP7_BASE_IDX                                                                5
+#define regRCC_DEV0_EPF4_STRAP9                                                                         0xd209
+#define regRCC_DEV0_EPF4_STRAP9_BASE_IDX                                                                5
+#define regRCC_DEV0_EPF4_STRAP13                                                                        0xd20d
+#define regRCC_DEV0_EPF4_STRAP13_BASE_IDX                                                               5
+#define regRCC_DEV0_EPF4_STRAP14                                                                        0xd20e
+#define regRCC_DEV0_EPF4_STRAP14_BASE_IDX                                                               5
+#define regRCC_DEV0_EPF4_STRAP15                                                                        0xd20f
+#define regRCC_DEV0_EPF4_STRAP15_BASE_IDX                                                               5
+#define regRCC_DEV0_EPF4_STRAP16                                                                        0xd210
+#define regRCC_DEV0_EPF4_STRAP16_BASE_IDX                                                               5
+#define regRCC_DEV0_EPF5_STRAP0                                                                         0xd280
+#define regRCC_DEV0_EPF5_STRAP0_BASE_IDX                                                                5
+#define regRCC_DEV0_EPF5_STRAP2                                                                         0xd282
+#define regRCC_DEV0_EPF5_STRAP2_BASE_IDX                                                                5
+#define regRCC_DEV0_EPF5_STRAP3                                                                         0xd283
+#define regRCC_DEV0_EPF5_STRAP3_BASE_IDX                                                                5
+#define regRCC_DEV0_EPF5_STRAP4                                                                         0xd284
+#define regRCC_DEV0_EPF5_STRAP4_BASE_IDX                                                                5
+#define regRCC_DEV0_EPF5_STRAP5                                                                         0xd285
+#define regRCC_DEV0_EPF5_STRAP5_BASE_IDX                                                                5
+#define regRCC_DEV0_EPF5_STRAP6                                                                         0xd286
+#define regRCC_DEV0_EPF5_STRAP6_BASE_IDX                                                                5
+#define regRCC_DEV0_EPF5_STRAP7                                                                         0xd287
+#define regRCC_DEV0_EPF5_STRAP7_BASE_IDX                                                                5
+#define regRCC_DEV0_EPF5_STRAP9                                                                         0xd289
+#define regRCC_DEV0_EPF5_STRAP9_BASE_IDX                                                                5
+#define regRCC_DEV0_EPF5_STRAP13                                                                        0xd28d
+#define regRCC_DEV0_EPF5_STRAP13_BASE_IDX                                                               5
+#define regRCC_DEV0_EPF5_STRAP14                                                                        0xd28e
+#define regRCC_DEV0_EPF5_STRAP14_BASE_IDX                                                               5
+#define regRCC_DEV0_EPF5_STRAP15                                                                        0xd28f
+#define regRCC_DEV0_EPF5_STRAP15_BASE_IDX                                                               5
+#define regRCC_DEV0_EPF5_STRAP16                                                                        0xd290
+#define regRCC_DEV0_EPF5_STRAP16_BASE_IDX                                                               5
+#define regRCC_DEV0_EPF6_STRAP0                                                                         0xd300
+#define regRCC_DEV0_EPF6_STRAP0_BASE_IDX                                                                5
+#define regRCC_DEV0_EPF6_STRAP2                                                                         0xd302
+#define regRCC_DEV0_EPF6_STRAP2_BASE_IDX                                                                5
+#define regRCC_DEV0_EPF6_STRAP3                                                                         0xd303
+#define regRCC_DEV0_EPF6_STRAP3_BASE_IDX                                                                5
+#define regRCC_DEV0_EPF6_STRAP4                                                                         0xd304
+#define regRCC_DEV0_EPF6_STRAP4_BASE_IDX                                                                5
+#define regRCC_DEV0_EPF6_STRAP5                                                                         0xd305
+#define regRCC_DEV0_EPF6_STRAP5_BASE_IDX                                                                5
+#define regRCC_DEV0_EPF6_STRAP6                                                                         0xd306
+#define regRCC_DEV0_EPF6_STRAP6_BASE_IDX                                                                5
+#define regRCC_DEV0_EPF6_STRAP7                                                                         0xd307
+#define regRCC_DEV0_EPF6_STRAP7_BASE_IDX                                                                5
+#define regRCC_DEV0_EPF6_STRAP9                                                                         0xd309
+#define regRCC_DEV0_EPF6_STRAP9_BASE_IDX                                                                5
+#define regRCC_DEV0_EPF6_STRAP13                                                                        0xd30d
+#define regRCC_DEV0_EPF6_STRAP13_BASE_IDX                                                               5
+#define regRCC_DEV0_EPF6_STRAP14                                                                        0xd30e
+#define regRCC_DEV0_EPF6_STRAP14_BASE_IDX                                                               5
+#define regRCC_DEV0_EPF6_STRAP15                                                                        0xd30f
+#define regRCC_DEV0_EPF6_STRAP15_BASE_IDX                                                               5
+#define regRCC_DEV0_EPF6_STRAP16                                                                        0xd310
+#define regRCC_DEV0_EPF6_STRAP16_BASE_IDX                                                               5
+#define regRCC_DEV0_EPF7_STRAP0                                                                         0xd380
+#define regRCC_DEV0_EPF7_STRAP0_BASE_IDX                                                                5
+#define regRCC_DEV0_EPF7_STRAP2                                                                         0xd382
+#define regRCC_DEV0_EPF7_STRAP2_BASE_IDX                                                                5
+#define regRCC_DEV0_EPF7_STRAP3                                                                         0xd383
+#define regRCC_DEV0_EPF7_STRAP3_BASE_IDX                                                                5
+#define regRCC_DEV0_EPF7_STRAP4                                                                         0xd384
+#define regRCC_DEV0_EPF7_STRAP4_BASE_IDX                                                                5
+#define regRCC_DEV0_EPF7_STRAP5                                                                         0xd385
+#define regRCC_DEV0_EPF7_STRAP5_BASE_IDX                                                                5
+#define regRCC_DEV0_EPF7_STRAP6                                                                         0xd386
+#define regRCC_DEV0_EPF7_STRAP6_BASE_IDX                                                                5
+#define regRCC_DEV0_EPF7_STRAP9                                                                         0xd389
+#define regRCC_DEV0_EPF7_STRAP9_BASE_IDX                                                                5
+#define regRCC_DEV0_EPF7_STRAP13                                                                        0xd38d
+#define regRCC_DEV0_EPF7_STRAP13_BASE_IDX                                                               5
+#define regRCC_DEV0_EPF7_STRAP14                                                                        0xd38e
+#define regRCC_DEV0_EPF7_STRAP14_BASE_IDX                                                               5
+#define regRCC_DEV0_EPF7_STRAP15                                                                        0xd38f
+#define regRCC_DEV0_EPF7_STRAP15_BASE_IDX                                                               5
+#define regRCC_DEV0_EPF7_STRAP16                                                                        0xd390
+#define regRCC_DEV0_EPF7_STRAP16_BASE_IDX                                                               5
+#define regRCC_DEV1_EPF0_STRAP0                                                                         0xd400
+#define regRCC_DEV1_EPF0_STRAP0_BASE_IDX                                                                5
+#define regRCC_DEV1_EPF0_STRAP2                                                                         0xd402
+#define regRCC_DEV1_EPF0_STRAP2_BASE_IDX                                                                5
+#define regRCC_DEV1_EPF0_STRAP3                                                                         0xd403
+#define regRCC_DEV1_EPF0_STRAP3_BASE_IDX                                                                5
+#define regRCC_DEV1_EPF0_STRAP4                                                                         0xd404
+#define regRCC_DEV1_EPF0_STRAP4_BASE_IDX                                                                5
+#define regRCC_DEV1_EPF0_STRAP5                                                                         0xd405
+#define regRCC_DEV1_EPF0_STRAP5_BASE_IDX                                                                5
+#define regRCC_DEV1_EPF0_STRAP6                                                                         0xd406
+#define regRCC_DEV1_EPF0_STRAP6_BASE_IDX                                                                5
+#define regRCC_DEV1_EPF0_STRAP9                                                                         0xd409
+#define regRCC_DEV1_EPF0_STRAP9_BASE_IDX                                                                5
+#define regRCC_DEV1_EPF0_STRAP13                                                                        0xd40d
+#define regRCC_DEV1_EPF0_STRAP13_BASE_IDX                                                               5
+#define regRCC_DEV1_EPF0_STRAP14                                                                        0xd40e
+#define regRCC_DEV1_EPF0_STRAP14_BASE_IDX                                                               5
+#define regRCC_DEV1_EPF0_STRAP15                                                                        0xd40f
+#define regRCC_DEV1_EPF0_STRAP15_BASE_IDX                                                               5
+#define regRCC_DEV1_EPF0_STRAP16                                                                        0xd410
+#define regRCC_DEV1_EPF0_STRAP16_BASE_IDX                                                               5
+#define regRCC_DEV1_EPF1_STRAP0                                                                         0xd480
+#define regRCC_DEV1_EPF1_STRAP0_BASE_IDX                                                                5
+#define regRCC_DEV1_EPF1_STRAP1                                                                         0xd481
+#define regRCC_DEV1_EPF1_STRAP1_BASE_IDX                                                                5
+#define regRCC_DEV1_EPF1_STRAP2                                                                         0xd482
+#define regRCC_DEV1_EPF1_STRAP2_BASE_IDX                                                                5
+#define regRCC_DEV1_EPF1_STRAP3                                                                         0xd483
+#define regRCC_DEV1_EPF1_STRAP3_BASE_IDX                                                                5
+#define regRCC_DEV1_EPF1_STRAP4                                                                         0xd484
+#define regRCC_DEV1_EPF1_STRAP4_BASE_IDX                                                                5
+#define regRCC_DEV1_EPF1_STRAP5                                                                         0xd485
+#define regRCC_DEV1_EPF1_STRAP5_BASE_IDX                                                                5
+#define regRCC_DEV1_EPF1_STRAP6                                                                         0xd486
+#define regRCC_DEV1_EPF1_STRAP6_BASE_IDX                                                                5
+#define regRCC_DEV1_EPF1_STRAP7                                                                         0xd487
+#define regRCC_DEV1_EPF1_STRAP7_BASE_IDX                                                                5
+#define regRCC_DEV1_EPF1_STRAP8                                                                         0xd488
+#define regRCC_DEV1_EPF1_STRAP8_BASE_IDX                                                                5
+#define regRCC_DEV1_EPF1_STRAP9                                                                         0xd489
+#define regRCC_DEV1_EPF1_STRAP9_BASE_IDX                                                                5
+#define regRCC_DEV1_EPF1_STRAP13                                                                        0xd48d
+#define regRCC_DEV1_EPF1_STRAP13_BASE_IDX                                                               5
+#define regRCC_DEV1_EPF1_STRAP14                                                                        0xd48e
+#define regRCC_DEV1_EPF1_STRAP14_BASE_IDX                                                               5
+#define regRCC_DEV1_EPF1_STRAP15                                                                        0xd48f
+#define regRCC_DEV1_EPF1_STRAP15_BASE_IDX                                                               5
+#define regRCC_DEV1_EPF1_STRAP16                                                                        0xd490
+#define regRCC_DEV1_EPF1_STRAP16_BASE_IDX                                                               5
+#define regRCC_DEV1_EPF1_STRAP17                                                                        0xd491
+#define regRCC_DEV1_EPF1_STRAP17_BASE_IDX                                                               5
+#define regRCC_DEV1_EPF1_STRAP18                                                                        0xd492
+#define regRCC_DEV1_EPF1_STRAP18_BASE_IDX                                                               5
+#define regRCC_DEV1_EPF1_STRAP19                                                                        0xd493
+#define regRCC_DEV1_EPF1_STRAP19_BASE_IDX                                                               5
+#define regRCC_DEV1_EPF1_STRAP20                                                                        0xd494
+#define regRCC_DEV1_EPF1_STRAP20_BASE_IDX                                                               5
+#define regRCC_DEV1_EPF1_STRAP21                                                                        0xd495
+#define regRCC_DEV1_EPF1_STRAP21_BASE_IDX                                                               5
+#define regRCC_DEV1_EPF2_STRAP0                                                                         0xd500
+#define regRCC_DEV1_EPF2_STRAP0_BASE_IDX                                                                5
+#define regRCC_DEV1_EPF2_STRAP1                                                                         0xd501
+#define regRCC_DEV1_EPF2_STRAP1_BASE_IDX                                                                5
+#define regRCC_DEV1_EPF2_STRAP2                                                                         0xd502
+#define regRCC_DEV1_EPF2_STRAP2_BASE_IDX                                                                5
+#define regRCC_DEV1_EPF2_STRAP3                                                                         0xd503
+#define regRCC_DEV1_EPF2_STRAP3_BASE_IDX                                                                5
+#define regRCC_DEV1_EPF2_STRAP4                                                                         0xd504
+#define regRCC_DEV1_EPF2_STRAP4_BASE_IDX                                                                5
+#define regRCC_DEV1_EPF2_STRAP5                                                                         0xd505
+#define regRCC_DEV1_EPF2_STRAP5_BASE_IDX                                                                5
+#define regRCC_DEV1_EPF2_STRAP6                                                                         0xd506
+#define regRCC_DEV1_EPF2_STRAP6_BASE_IDX                                                                5
+#define regRCC_DEV1_EPF2_STRAP7                                                                         0xd507
+#define regRCC_DEV1_EPF2_STRAP7_BASE_IDX                                                                5
+#define regRCC_DEV1_EPF2_STRAP8                                                                         0xd508
+#define regRCC_DEV1_EPF2_STRAP8_BASE_IDX                                                                5
+#define regRCC_DEV1_EPF2_STRAP9                                                                         0xd509
+#define regRCC_DEV1_EPF2_STRAP9_BASE_IDX                                                                5
+#define regRCC_DEV1_EPF2_STRAP13                                                                        0xd50d
+#define regRCC_DEV1_EPF2_STRAP13_BASE_IDX                                                               5
+#define regRCC_DEV1_EPF2_STRAP14                                                                        0xd50e
+#define regRCC_DEV1_EPF2_STRAP14_BASE_IDX                                                               5
+#define regRCC_DEV1_EPF2_STRAP15                                                                        0xd50f
+#define regRCC_DEV1_EPF2_STRAP15_BASE_IDX                                                               5
+#define regRCC_DEV1_EPF2_STRAP16                                                                        0xd510
+#define regRCC_DEV1_EPF2_STRAP16_BASE_IDX                                                               5
+#define regRCC_DEV1_EPF2_STRAP17                                                                        0xd511
+#define regRCC_DEV1_EPF2_STRAP17_BASE_IDX                                                               5
+#define regRCC_DEV1_EPF2_STRAP18                                                                        0xd512
+#define regRCC_DEV1_EPF2_STRAP18_BASE_IDX                                                               5
+#define regRCC_DEV1_EPF2_STRAP19                                                                        0xd513
+#define regRCC_DEV1_EPF2_STRAP19_BASE_IDX                                                               5
+#define regRCC_DEV1_EPF2_STRAP20                                                                        0xd514
+#define regRCC_DEV1_EPF2_STRAP20_BASE_IDX                                                               5
+#define regRCC_DEV1_EPF2_STRAP21                                                                        0xd515
+#define regRCC_DEV1_EPF2_STRAP21_BASE_IDX                                                               5
+#define regRCC_DEV1_EPF3_STRAP0                                                                         0xd580
+#define regRCC_DEV1_EPF3_STRAP0_BASE_IDX                                                                5
+#define regRCC_DEV1_EPF3_STRAP2                                                                         0xd582
+#define regRCC_DEV1_EPF3_STRAP2_BASE_IDX                                                                5
+#define regRCC_DEV1_EPF3_STRAP3                                                                         0xd583
+#define regRCC_DEV1_EPF3_STRAP3_BASE_IDX                                                                5
+#define regRCC_DEV1_EPF3_STRAP4                                                                         0xd584
+#define regRCC_DEV1_EPF3_STRAP4_BASE_IDX                                                                5
+#define regRCC_DEV1_EPF3_STRAP5                                                                         0xd585
+#define regRCC_DEV1_EPF3_STRAP5_BASE_IDX                                                                5
+#define regRCC_DEV1_EPF3_STRAP6                                                                         0xd586
+#define regRCC_DEV1_EPF3_STRAP6_BASE_IDX                                                                5
+#define regRCC_DEV1_EPF3_STRAP7                                                                         0xd587
+#define regRCC_DEV1_EPF3_STRAP7_BASE_IDX                                                                5
+#define regRCC_DEV1_EPF3_STRAP13                                                                        0xd58d
+#define regRCC_DEV1_EPF3_STRAP13_BASE_IDX                                                               5
+#define regRCC_DEV1_EPF3_STRAP14                                                                        0xd58e
+#define regRCC_DEV1_EPF3_STRAP14_BASE_IDX                                                               5
+#define regRCC_DEV1_EPF3_STRAP15                                                                        0xd58f
+#define regRCC_DEV1_EPF3_STRAP15_BASE_IDX                                                               5
+#define regRCC_DEV1_EPF3_STRAP16                                                                        0xd590
+#define regRCC_DEV1_EPF3_STRAP16_BASE_IDX                                                               5
+#define regRCC_DEV1_EPF4_STRAP6                                                                         0xd606
+#define regRCC_DEV1_EPF4_STRAP6_BASE_IDX                                                                5
+#define regRCC_DEV1_EPF5_STRAP6                                                                         0xd686
+#define regRCC_DEV1_EPF5_STRAP6_BASE_IDX                                                                5
+#define regRCC_DEV1_EPF6_STRAP6                                                                         0xd706
+#define regRCC_DEV1_EPF6_STRAP6_BASE_IDX                                                                5
+#define regRCC_DEV2_EPF0_STRAP0                                                                         0xd800
+#define regRCC_DEV2_EPF0_STRAP0_BASE_IDX                                                                5
+#define regRCC_DEV2_EPF0_STRAP2                                                                         0xd802
+#define regRCC_DEV2_EPF0_STRAP2_BASE_IDX                                                                5
+#define regRCC_DEV2_EPF0_STRAP3                                                                         0xd803
+#define regRCC_DEV2_EPF0_STRAP3_BASE_IDX                                                                5
+#define regRCC_DEV2_EPF0_STRAP4                                                                         0xd804
+#define regRCC_DEV2_EPF0_STRAP4_BASE_IDX                                                                5
+#define regRCC_DEV2_EPF0_STRAP5                                                                         0xd805
+#define regRCC_DEV2_EPF0_STRAP5_BASE_IDX                                                                5
+#define regRCC_DEV2_EPF0_STRAP6                                                                         0xd806
+#define regRCC_DEV2_EPF0_STRAP6_BASE_IDX                                                                5
+#define regRCC_DEV2_EPF0_STRAP7                                                                         0xd807
+#define regRCC_DEV2_EPF0_STRAP7_BASE_IDX                                                                5
+#define regRCC_DEV2_EPF0_STRAP13                                                                        0xd80d
+#define regRCC_DEV2_EPF0_STRAP13_BASE_IDX                                                               5
+#define regRCC_DEV2_EPF0_STRAP14                                                                        0xd80e
+#define regRCC_DEV2_EPF0_STRAP14_BASE_IDX                                                               5
+#define regRCC_DEV2_EPF0_STRAP15                                                                        0xd80f
+#define regRCC_DEV2_EPF0_STRAP15_BASE_IDX                                                               5
+#define regRCC_DEV2_EPF0_STRAP16                                                                        0xd810
+#define regRCC_DEV2_EPF0_STRAP16_BASE_IDX                                                               5
+#define regRCC_DEV2_EPF0_STRAP18                                                                        0xd812
+#define regRCC_DEV2_EPF0_STRAP18_BASE_IDX                                                               5
+#define regRCC_DEV2_EPF0_STRAP25                                                                        0xd819
+#define regRCC_DEV2_EPF0_STRAP25_BASE_IDX                                                               5
+#define regRCC_DEV2_EPF0_STRAP26                                                                        0xd81a
+#define regRCC_DEV2_EPF0_STRAP26_BASE_IDX                                                               5
+#define regRCC_DEV2_EPF1_STRAP0                                                                         0xd880
+#define regRCC_DEV2_EPF1_STRAP0_BASE_IDX                                                                5
+#define regRCC_DEV2_EPF1_STRAP2                                                                         0xd882
+#define regRCC_DEV2_EPF1_STRAP2_BASE_IDX                                                                5
+#define regRCC_DEV2_EPF1_STRAP3                                                                         0xd883
+#define regRCC_DEV2_EPF1_STRAP3_BASE_IDX                                                                5
+#define regRCC_DEV2_EPF1_STRAP4                                                                         0xd884
+#define regRCC_DEV2_EPF1_STRAP4_BASE_IDX                                                                5
+#define regRCC_DEV2_EPF1_STRAP5                                                                         0xd885
+#define regRCC_DEV2_EPF1_STRAP5_BASE_IDX                                                                5
+#define regRCC_DEV2_EPF1_STRAP6                                                                         0xd886
+#define regRCC_DEV2_EPF1_STRAP6_BASE_IDX                                                                5
+#define regRCC_DEV2_EPF1_STRAP7                                                                         0xd887
+#define regRCC_DEV2_EPF1_STRAP7_BASE_IDX                                                                5
+#define regRCC_DEV2_EPF1_STRAP13                                                                        0xd88d
+#define regRCC_DEV2_EPF1_STRAP13_BASE_IDX                                                               5
+#define regRCC_DEV2_EPF1_STRAP14                                                                        0xd88e
+#define regRCC_DEV2_EPF1_STRAP14_BASE_IDX                                                               5
+#define regRCC_DEV2_EPF1_STRAP15                                                                        0xd88f
+#define regRCC_DEV2_EPF1_STRAP15_BASE_IDX                                                               5
+#define regRCC_DEV2_EPF1_STRAP16                                                                        0xd890
+#define regRCC_DEV2_EPF1_STRAP16_BASE_IDX                                                               5
+#define regRCC_DEV2_EPF2_STRAP0                                                                         0xd900
+#define regRCC_DEV2_EPF2_STRAP0_BASE_IDX                                                                5
+#define regRCC_DEV2_EPF2_STRAP2                                                                         0xd902
+#define regRCC_DEV2_EPF2_STRAP2_BASE_IDX                                                                5
+#define regRCC_DEV2_EPF2_STRAP3                                                                         0xd903
+#define regRCC_DEV2_EPF2_STRAP3_BASE_IDX                                                                5
+#define regRCC_DEV2_EPF2_STRAP4                                                                         0xd904
+#define regRCC_DEV2_EPF2_STRAP4_BASE_IDX                                                                5
+#define regRCC_DEV2_EPF2_STRAP5                                                                         0xd905
+#define regRCC_DEV2_EPF2_STRAP5_BASE_IDX                                                                5
+#define regRCC_DEV2_EPF2_STRAP6                                                                         0xd906
+#define regRCC_DEV2_EPF2_STRAP6_BASE_IDX                                                                5
+#define regRCC_DEV2_EPF2_STRAP7                                                                         0xd907
+#define regRCC_DEV2_EPF2_STRAP7_BASE_IDX                                                                5
+#define regRCC_DEV2_EPF2_STRAP13                                                                        0xd90d
+#define regRCC_DEV2_EPF2_STRAP13_BASE_IDX                                                               5
+#define regRCC_DEV2_EPF2_STRAP14                                                                        0xd90e
+#define regRCC_DEV2_EPF2_STRAP14_BASE_IDX                                                               5
+#define regRCC_DEV2_EPF2_STRAP15                                                                        0xd90f
+#define regRCC_DEV2_EPF2_STRAP15_BASE_IDX                                                               5
+#define regRCC_DEV2_EPF2_STRAP16                                                                        0xd910
+#define regRCC_DEV2_EPF2_STRAP16_BASE_IDX                                                               5
+#define regRCC_DEV2_EPF3_STRAP0                                                                         0xd980
+#define regRCC_DEV2_EPF3_STRAP0_BASE_IDX                                                                5
+#define regRCC_DEV2_EPF3_STRAP2                                                                         0xd982
+#define regRCC_DEV2_EPF3_STRAP2_BASE_IDX                                                                5
+#define regRCC_DEV2_EPF3_STRAP3                                                                         0xd983
+#define regRCC_DEV2_EPF3_STRAP3_BASE_IDX                                                                5
+#define regRCC_DEV2_EPF3_STRAP4                                                                         0xd984
+#define regRCC_DEV2_EPF3_STRAP4_BASE_IDX                                                                5
+#define regRCC_DEV2_EPF3_STRAP5                                                                         0xd985
+#define regRCC_DEV2_EPF3_STRAP5_BASE_IDX                                                                5
+#define regRCC_DEV2_EPF3_STRAP6                                                                         0xd986
+#define regRCC_DEV2_EPF3_STRAP6_BASE_IDX                                                                5
+#define regRCC_DEV2_EPF3_STRAP7                                                                         0xd987
+#define regRCC_DEV2_EPF3_STRAP7_BASE_IDX                                                                5
+#define regRCC_DEV2_EPF3_STRAP13                                                                        0xd98d
+#define regRCC_DEV2_EPF3_STRAP13_BASE_IDX                                                               5
+#define regRCC_DEV2_EPF3_STRAP14                                                                        0xd98e
+#define regRCC_DEV2_EPF3_STRAP14_BASE_IDX                                                               5
+#define regRCC_DEV2_EPF3_STRAP15                                                                        0xd98f
+#define regRCC_DEV2_EPF3_STRAP15_BASE_IDX                                                               5
+#define regRCC_DEV2_EPF3_STRAP16                                                                        0xd990
+#define regRCC_DEV2_EPF3_STRAP16_BASE_IDX                                                               5
+#define regRCC_DEV2_EPF4_STRAP0                                                                         0xda00
+#define regRCC_DEV2_EPF4_STRAP0_BASE_IDX                                                                5
+#define regRCC_DEV2_EPF4_STRAP2                                                                         0xda02
+#define regRCC_DEV2_EPF4_STRAP2_BASE_IDX                                                                5
+#define regRCC_DEV2_EPF4_STRAP3                                                                         0xda03
+#define regRCC_DEV2_EPF4_STRAP3_BASE_IDX                                                                5
+#define regRCC_DEV2_EPF4_STRAP4                                                                         0xda04
+#define regRCC_DEV2_EPF4_STRAP4_BASE_IDX                                                                5
+#define regRCC_DEV2_EPF4_STRAP5                                                                         0xda05
+#define regRCC_DEV2_EPF4_STRAP5_BASE_IDX                                                                5
+#define regRCC_DEV2_EPF4_STRAP6                                                                         0xda06
+#define regRCC_DEV2_EPF4_STRAP6_BASE_IDX                                                                5
+#define regRCC_DEV2_EPF4_STRAP7                                                                         0xda07
+#define regRCC_DEV2_EPF4_STRAP7_BASE_IDX                                                                5
+#define regRCC_DEV2_EPF4_STRAP13                                                                        0xda0d
+#define regRCC_DEV2_EPF4_STRAP13_BASE_IDX                                                               5
+#define regRCC_DEV2_EPF4_STRAP14                                                                        0xda0e
+#define regRCC_DEV2_EPF4_STRAP14_BASE_IDX                                                               5
+#define regRCC_DEV2_EPF4_STRAP15                                                                        0xda0f
+#define regRCC_DEV2_EPF4_STRAP15_BASE_IDX                                                               5
+#define regRCC_DEV2_EPF4_STRAP16                                                                        0xda10
+#define regRCC_DEV2_EPF4_STRAP16_BASE_IDX                                                               5
+#define regRCC_DEV2_EPF5_STRAP0                                                                         0xda80
+#define regRCC_DEV2_EPF5_STRAP0_BASE_IDX                                                                5
+#define regRCC_DEV2_EPF5_STRAP2                                                                         0xda82
+#define regRCC_DEV2_EPF5_STRAP2_BASE_IDX                                                                5
+#define regRCC_DEV2_EPF5_STRAP3                                                                         0xda83
+#define regRCC_DEV2_EPF5_STRAP3_BASE_IDX                                                                5
+#define regRCC_DEV2_EPF5_STRAP4                                                                         0xda84
+#define regRCC_DEV2_EPF5_STRAP4_BASE_IDX                                                                5
+#define regRCC_DEV2_EPF5_STRAP5                                                                         0xda85
+#define regRCC_DEV2_EPF5_STRAP5_BASE_IDX                                                                5
+#define regRCC_DEV2_EPF5_STRAP6                                                                         0xda86
+#define regRCC_DEV2_EPF5_STRAP6_BASE_IDX                                                                5
+#define regRCC_DEV2_EPF5_STRAP7                                                                         0xda87
+#define regRCC_DEV2_EPF5_STRAP7_BASE_IDX                                                                5
+#define regRCC_DEV2_EPF5_STRAP13                                                                        0xda8d
+#define regRCC_DEV2_EPF5_STRAP13_BASE_IDX                                                               5
+#define regRCC_DEV2_EPF5_STRAP14                                                                        0xda8e
+#define regRCC_DEV2_EPF5_STRAP14_BASE_IDX                                                               5
+#define regRCC_DEV2_EPF5_STRAP15                                                                        0xda8f
+#define regRCC_DEV2_EPF5_STRAP15_BASE_IDX                                                               5
+#define regRCC_DEV2_EPF5_STRAP16                                                                        0xda90
+#define regRCC_DEV2_EPF5_STRAP16_BASE_IDX                                                               5
+#define regRCC_DEV2_EPF6_STRAP0                                                                         0xdb00
+#define regRCC_DEV2_EPF6_STRAP0_BASE_IDX                                                                5
+#define regRCC_DEV2_EPF6_STRAP2                                                                         0xdb02
+#define regRCC_DEV2_EPF6_STRAP2_BASE_IDX                                                                5
+#define regRCC_DEV2_EPF6_STRAP3                                                                         0xdb03
+#define regRCC_DEV2_EPF6_STRAP3_BASE_IDX                                                                5
+#define regRCC_DEV2_EPF6_STRAP4                                                                         0xdb04
+#define regRCC_DEV2_EPF6_STRAP4_BASE_IDX                                                                5
+#define regRCC_DEV2_EPF6_STRAP5                                                                         0xdb05
+#define regRCC_DEV2_EPF6_STRAP5_BASE_IDX                                                                5
+#define regRCC_DEV2_EPF6_STRAP6                                                                         0xdb06
+#define regRCC_DEV2_EPF6_STRAP6_BASE_IDX                                                                5
+#define regRCC_DEV2_EPF6_STRAP7                                                                         0xdb07
+#define regRCC_DEV2_EPF6_STRAP7_BASE_IDX                                                                5
+#define regRCC_DEV2_EPF6_STRAP13                                                                        0xdb0d
+#define regRCC_DEV2_EPF6_STRAP13_BASE_IDX                                                               5
+#define regRCC_DEV2_EPF6_STRAP14                                                                        0xdb0e
+#define regRCC_DEV2_EPF6_STRAP14_BASE_IDX                                                               5
+#define regRCC_DEV2_EPF6_STRAP15                                                                        0xdb0f
+#define regRCC_DEV2_EPF6_STRAP15_BASE_IDX                                                               5
+#define regRCC_DEV2_EPF6_STRAP16                                                                        0xdb10
+#define regRCC_DEV2_EPF6_STRAP16_BASE_IDX                                                               5
+
+
+// addressBlock: nbif0_nbif0_bif_rst_bif_rst_regblk
+// base address: 0x10100000
+#define regHARD_RST_CTRL                                                                                0xe000
+#define regHARD_RST_CTRL_BASE_IDX                                                                       5
+#define regSELF_SOFT_RST                                                                                0xe002
+#define regSELF_SOFT_RST_BASE_IDX                                                                       5
+#define regBIF_GFX_DRV_VPU_RST                                                                          0xe003
+#define regBIF_GFX_DRV_VPU_RST_BASE_IDX                                                                 5
+#define regBIF_RST_MISC_CTRL                                                                            0xe004
+#define regBIF_RST_MISC_CTRL_BASE_IDX                                                                   5
+#define regBIF_RST_MISC_CTRL2                                                                           0xe005
+#define regBIF_RST_MISC_CTRL2_BASE_IDX                                                                  5
+#define regBIF_RST_MISC_CTRL3                                                                           0xe006
+#define regBIF_RST_MISC_CTRL3_BASE_IDX                                                                  5
+#define regDEV0_PF0_FLR_RST_CTRL                                                                        0xe008
+#define regDEV0_PF0_FLR_RST_CTRL_BASE_IDX                                                               5
+#define regDEV0_PF1_FLR_RST_CTRL                                                                        0xe009
+#define regDEV0_PF1_FLR_RST_CTRL_BASE_IDX                                                               5
+#define regBIF_INST_RESET_INTR_STS                                                                      0xe010
+#define regBIF_INST_RESET_INTR_STS_BASE_IDX                                                             5
+#define regBIF_PF_FLR_INTR_STS                                                                          0xe011
+#define regBIF_PF_FLR_INTR_STS_BASE_IDX                                                                 5
+#define regBIF_D3HOTD0_INTR_STS                                                                         0xe012
+#define regBIF_D3HOTD0_INTR_STS_BASE_IDX                                                                5
+#define regBIF_POWER_INTR_STS                                                                           0xe014
+#define regBIF_POWER_INTR_STS_BASE_IDX                                                                  5
+#define regBIF_PF_DSTATE_INTR_STS                                                                       0xe015
+#define regBIF_PF_DSTATE_INTR_STS_BASE_IDX                                                              5
+#define regSELF_SOFT_RST_2                                                                              0xe016
+#define regSELF_SOFT_RST_2_BASE_IDX                                                                     5
+#define regSION_SDP_PORT_RST                                                                            0xe017
+#define regSION_SDP_PORT_RST_BASE_IDX                                                                   5
+#define regBIF_INST_RESET_INTR_MASK                                                                     0xe020
+#define regBIF_INST_RESET_INTR_MASK_BASE_IDX                                                            5
+#define regBIF_PF_FLR_INTR_MASK                                                                         0xe021
+#define regBIF_PF_FLR_INTR_MASK_BASE_IDX                                                                5
+#define regBIF_D3HOTD0_INTR_MASK                                                                        0xe022
+#define regBIF_D3HOTD0_INTR_MASK_BASE_IDX                                                               5
+#define regBIF_POWER_INTR_MASK                                                                          0xe024
+#define regBIF_POWER_INTR_MASK_BASE_IDX                                                                 5
+#define regBIF_PF_DSTATE_INTR_MASK                                                                      0xe025
+#define regBIF_PF_DSTATE_INTR_MASK_BASE_IDX                                                             5
+#define regBIF_DEV0_PF0_VF_FLR_INTR_MASK                                                                0xe028
+#define regBIF_DEV0_PF0_VF_FLR_INTR_MASK_BASE_IDX                                                       5
+#define regBIF_DEV0_PF1_VF_FLR_INTR_MASK                                                                0xe029
+#define regBIF_DEV0_PF1_VF_FLR_INTR_MASK_BASE_IDX                                                       5
+#define regBIF_PF_FLR_RST                                                                               0xe040
+#define regBIF_PF_FLR_RST_BASE_IDX                                                                      5
+#define regBIF_PF_FLR_PROTECT                                                                           0xe042
+#define regBIF_PF_FLR_PROTECT_BASE_IDX                                                                  5
+#define regBIF_PF_FLR_PROTECT3                                                                          0xe044
+#define regBIF_PF_FLR_PROTECT3_BASE_IDX                                                                 5
+#define regBIF_DEV0_PF0_DSTATE_VALUE                                                                    0xe050
+#define regBIF_DEV0_PF0_DSTATE_VALUE_BASE_IDX                                                           5
+#define regBIF_DEV0_PF1_DSTATE_VALUE                                                                    0xe051
+#define regBIF_DEV0_PF1_DSTATE_VALUE_BASE_IDX                                                           5
+#define regGFX_RST_CNTL_IND0                                                                            0xe05d
+#define regGFX_RST_CNTL_IND0_BASE_IDX                                                                   5
+#define regGFX_RST_CNTL_SOFT_PF                                                                         0xe05e
+#define regGFX_RST_CNTL_SOFT_PF_BASE_IDX                                                                5
+#define regGFX_RST_CNTL_IND1                                                                            0xe05f
+#define regGFX_RST_CNTL_IND1_BASE_IDX                                                                   5
+#define regGFX_RST_CNTL_IND2                                                                            0xe060
+#define regGFX_RST_CNTL_IND2_BASE_IDX                                                                   5
+#define regGFX_RST_CNTL_IND3                                                                            0xe061
+#define regGFX_RST_CNTL_IND3_BASE_IDX                                                                   5
+#define regGFX_RST_CNTL_IND4                                                                            0xe062
+#define regGFX_RST_CNTL_IND4_BASE_IDX                                                                   5
+#define regGFX_RST_CNTL_IND5                                                                            0xe063
+#define regGFX_RST_CNTL_IND5_BASE_IDX                                                                   5
+#define regGFX_RST_CNTL_IND6                                                                            0xe064
+#define regGFX_RST_CNTL_IND6_BASE_IDX                                                                   5
+#define regGFX_RST_CNTL_IND7                                                                            0xe065
+#define regGFX_RST_CNTL_IND7_BASE_IDX                                                                   5
+#define regGFX_RST_CNTL_IND8                                                                            0xe066
+#define regGFX_RST_CNTL_IND8_BASE_IDX                                                                   5
+#define regDEV0_PF0_D3HOTD0_RST_CTRL                                                                    0xe07e
+#define regDEV0_PF0_D3HOTD0_RST_CTRL_BASE_IDX                                                           5
+#define regDEV0_PF1_D3HOTD0_RST_CTRL                                                                    0xe07f
+#define regDEV0_PF1_D3HOTD0_RST_CTRL_BASE_IDX                                                           5
+#define regBIF_DEV0_PF0_VF_FLR_PROTECT                                                                  0xe086
+#define regBIF_DEV0_PF0_VF_FLR_PROTECT_BASE_IDX                                                         5
+#define regBIF_DEV0_PF1_VF_FLR_PROTECT                                                                  0xe087
+#define regBIF_DEV0_PF1_VF_FLR_PROTECT_BASE_IDX                                                         5
+#define regBIF_SRIOVEN_SET_INTR_STS                                                                     0xe088
+#define regBIF_SRIOVEN_SET_INTR_STS_BASE_IDX                                                            5
+#define regBIF_SRIOVEN_CLR_INTR_STS                                                                     0xe089
+#define regBIF_SRIOVEN_CLR_INTR_STS_BASE_IDX                                                            5
+#define regBIF_SRIOVEN_SET_INTR_MASK                                                                    0xe08a
+#define regBIF_SRIOVEN_SET_INTR_MASK_BASE_IDX                                                           5
+#define regBIF_SRIOVEN_CLR_INTR_MASK                                                                    0xe08b
+#define regBIF_SRIOVEN_CLR_INTR_MASK_BASE_IDX                                                           5
+#define regBIF_PORT0_DSTATE_VALUE                                                                       0xe230
+#define regBIF_PORT0_DSTATE_VALUE_BASE_IDX                                                              5
+#define regBIF_DEV0_PF0_RST_VF_FLR_IDLE                                                                 0xe2c4
+#define regBIF_DEV0_PF0_RST_VF_FLR_IDLE_BASE_IDX                                                        5
+#define regBIF_DEV0_PF1_RST_VF_FLR_IDLE                                                                 0xe2c5
+#define regBIF_DEV0_PF1_RST_VF_FLR_IDLE_BASE_IDX                                                        5
+#define regBIF_DEV0_PF0_VF_FLR_INTR_STS                                                                 0xe2c8
+#define regBIF_DEV0_PF0_VF_FLR_INTR_STS_BASE_IDX                                                        5
+#define regBIF_DEV0_PF1_VF_FLR_INTR_STS                                                                 0xe2c9
+#define regBIF_DEV0_PF1_VF_FLR_INTR_STS_BASE_IDX                                                        5
+#define regBIF_DEV0_PF0_VF_FLR_RST                                                                      0xe2cc
+#define regBIF_DEV0_PF0_VF_FLR_RST_BASE_IDX                                                             5
+#define regBIF_DEV0_PF1_VF_FLR_RST                                                                      0xe2cd
+#define regBIF_DEV0_PF1_VF_FLR_RST_BASE_IDX                                                             5
+
+
+// addressBlock: nbif0_nbif0_bif_misc_bif_misc_regblk
+// base address: 0x10100000
+#define regDOE_PRV_CTRL0_DEV0F0                                                                         0xc806
+#define regDOE_PRV_CTRL0_DEV0F0_BASE_IDX                                                                5
+#define regDOE_PRV_CMD_DEV0F0                                                                           0xc807
+#define regDOE_PRV_CMD_DEV0F0_BASE_IDX                                                                  5
+#define regDOE_PRV_WDATA_DEV0F0                                                                         0xc808
+#define regDOE_PRV_WDATA_DEV0F0_BASE_IDX                                                                5
+#define regDOE_PRV_STS_DEV0F0                                                                           0xc809
+#define regDOE_PRV_STS_DEV0F0_BASE_IDX                                                                  5
+#define regDOE_PRV_RDATA_DEV0F0                                                                         0xc80a
+#define regDOE_PRV_RDATA_DEV0F0_BASE_IDX                                                                5
+#define regNBIF_RC_INTR_CNTL                                                                            0xc81b
+#define regNBIF_RC_INTR_CNTL_BASE_IDX                                                                   5
+#define regBIF_DEV0_PF0_TDISP_CNTL                                                                      0xc8c0
+#define regBIF_DEV0_PF0_TDISP_CNTL_BASE_IDX                                                             5
+#define regBIF_DEV0_PF1_TDISP_CNTL                                                                      0xc8c1
+#define regBIF_DEV0_PF1_TDISP_CNTL_BASE_IDX                                                             5
+#define regBIF_DEV0_PF0_VF0_TDISP_CNTL                                                                  0xc8d0
+#define regBIF_DEV0_PF0_VF0_TDISP_CNTL_BASE_IDX                                                         5
+#define regBIF_DEV0_PF0_VF1_TDISP_CNTL                                                                  0xc8d1
+#define regBIF_DEV0_PF0_VF1_TDISP_CNTL_BASE_IDX                                                         5
+#define regBIF_DEV0_PF0_VF2_TDISP_CNTL                                                                  0xc8d2
+#define regBIF_DEV0_PF0_VF2_TDISP_CNTL_BASE_IDX                                                         5
+#define regBIF_DEV0_PF0_VF3_TDISP_CNTL                                                                  0xc8d3
+#define regBIF_DEV0_PF0_VF3_TDISP_CNTL_BASE_IDX                                                         5
+#define regBIF_DEV0_PF0_VF4_TDISP_CNTL                                                                  0xc8d4
+#define regBIF_DEV0_PF0_VF4_TDISP_CNTL_BASE_IDX                                                         5
+#define regBIF_DEV0_PF0_VF5_TDISP_CNTL                                                                  0xc8d5
+#define regBIF_DEV0_PF0_VF5_TDISP_CNTL_BASE_IDX                                                         5
+#define regBIF_DEV0_PF0_VF6_TDISP_CNTL                                                                  0xc8d6
+#define regBIF_DEV0_PF0_VF6_TDISP_CNTL_BASE_IDX                                                         5
+#define regBIF_DEV0_PF0_VF7_TDISP_CNTL                                                                  0xc8d7
+#define regBIF_DEV0_PF0_VF7_TDISP_CNTL_BASE_IDX                                                         5
+#define regBIF_DEV0_PF1_VF0_TDISP_CNTL                                                                  0xc8d8
+#define regBIF_DEV0_PF1_VF0_TDISP_CNTL_BASE_IDX                                                         5
+#define regBIF_TDISP_ERROR_DEV0_PF0_INST0                                                               0xc9d0
+#define regBIF_TDISP_ERROR_DEV0_PF0_INST0_BASE_IDX                                                      5
+#define regBIF_TDISP_ERROR_DEV0_PF1_INST0                                                               0xc9d1
+#define regBIF_TDISP_ERROR_DEV0_PF1_INST0_BASE_IDX                                                      5
+#define regBIF_TDISP_UNLOCKED_DEV0_PF0_INST0                                                            0xc9d8
+#define regBIF_TDISP_UNLOCKED_DEV0_PF0_INST0_BASE_IDX                                                   5
+#define regBIF_TDISP_UNLOCKED_DEV0_PF1_INST0                                                            0xc9d9
+#define regBIF_TDISP_UNLOCKED_DEV0_PF1_INST0_BASE_IDX                                                   5
+#define regBIF_TDISP_MISC_CNTL_DEV0                                                                     0xc9e0
+#define regBIF_TDISP_MISC_CNTL_DEV0_BASE_IDX                                                            5
+#define regBIF_TDISP_MISC_CNTL                                                                          0xc9e4
+#define regBIF_TDISP_MISC_CNTL_BASE_IDX                                                                 5
+#define regBIF_RCC_IDE_TDISP_CNTL                                                                       0xc9e5
+#define regBIF_RCC_IDE_TDISP_CNTL_BASE_IDX                                                              5
+#define regBIF_DEV0_SELECTIVE_IDE_0_BOUND_PF0_31                                                        0xca00
+#define regBIF_DEV0_SELECTIVE_IDE_0_BOUND_PF0_31_BASE_IDX                                               5
+#define regBIF_DEV0_SELECTIVE_IDE_0_BOUND_PF0_VF0_31                                                    0xca01
+#define regBIF_DEV0_SELECTIVE_IDE_0_BOUND_PF0_VF0_31_BASE_IDX                                           5
+#define regBIF_DEV0_SELECTIVE_IDE_0_BOUND_PF1_VF0_31                                                    0xca02
+#define regBIF_DEV0_SELECTIVE_IDE_0_BOUND_PF1_VF0_31_BASE_IDX                                           5
+#define regBIF_DEV0_SELECTIVE_IDE_1_BOUND_PF0_31                                                        0xca03
+#define regBIF_DEV0_SELECTIVE_IDE_1_BOUND_PF0_31_BASE_IDX                                               5
+#define regBIF_DEV0_SELECTIVE_IDE_1_BOUND_PF0_VF0_31                                                    0xca04
+#define regBIF_DEV0_SELECTIVE_IDE_1_BOUND_PF0_VF0_31_BASE_IDX                                           5
+#define regBIF_DEV0_SELECTIVE_IDE_1_BOUND_PF1_VF0_31                                                    0xca05
+#define regBIF_DEV0_SELECTIVE_IDE_1_BOUND_PF1_VF0_31_BASE_IDX                                           5
+#define regBIF_DEV0_SELECTIVE_IDE_2_BOUND_PF0_31                                                        0xca06
+#define regBIF_DEV0_SELECTIVE_IDE_2_BOUND_PF0_31_BASE_IDX                                               5
+#define regBIF_DEV0_SELECTIVE_IDE_2_BOUND_PF0_VF0_31                                                    0xca07
+#define regBIF_DEV0_SELECTIVE_IDE_2_BOUND_PF0_VF0_31_BASE_IDX                                           5
+#define regBIF_DEV0_SELECTIVE_IDE_2_BOUND_PF1_VF0_31                                                    0xca08
+#define regBIF_DEV0_SELECTIVE_IDE_2_BOUND_PF1_VF0_31_BASE_IDX                                           5
+#define regBIF_DEV0_SELECTIVE_IDE_3_BOUND_PF0_31                                                        0xca09
+#define regBIF_DEV0_SELECTIVE_IDE_3_BOUND_PF0_31_BASE_IDX                                               5
+#define regBIF_DEV0_SELECTIVE_IDE_3_BOUND_PF0_VF0_31                                                    0xca0a
+#define regBIF_DEV0_SELECTIVE_IDE_3_BOUND_PF0_VF0_31_BASE_IDX                                           5
+#define regBIF_DEV0_SELECTIVE_IDE_3_BOUND_PF1_VF0_31                                                    0xca0b
+#define regBIF_DEV0_SELECTIVE_IDE_3_BOUND_PF1_VF0_31_BASE_IDX                                           5
+#define regBIF_DEV0_SELECTIVE_IDE_4_BOUND_PF0_31                                                        0xca0c
+#define regBIF_DEV0_SELECTIVE_IDE_4_BOUND_PF0_31_BASE_IDX                                               5
+#define regBIF_DEV0_SELECTIVE_IDE_4_BOUND_PF0_VF0_31                                                    0xca0d
+#define regBIF_DEV0_SELECTIVE_IDE_4_BOUND_PF0_VF0_31_BASE_IDX                                           5
+#define regBIF_DEV0_SELECTIVE_IDE_4_BOUND_PF1_VF0_31                                                    0xca0e
+#define regBIF_DEV0_SELECTIVE_IDE_4_BOUND_PF1_VF0_31_BASE_IDX                                           5
+#define regBIF_DEV0_SELECTIVE_IDE_5_BOUND_PF0_31                                                        0xca0f
+#define regBIF_DEV0_SELECTIVE_IDE_5_BOUND_PF0_31_BASE_IDX                                               5
+#define regBIF_DEV0_SELECTIVE_IDE_5_BOUND_PF0_VF0_31                                                    0xca10
+#define regBIF_DEV0_SELECTIVE_IDE_5_BOUND_PF0_VF0_31_BASE_IDX                                           5
+#define regBIF_DEV0_SELECTIVE_IDE_5_BOUND_PF1_VF0_31                                                    0xca11
+#define regBIF_DEV0_SELECTIVE_IDE_5_BOUND_PF1_VF0_31_BASE_IDX                                           5
+#define regBIF_DEV0_SELECTIVE_IDE_6_BOUND_PF0_31                                                        0xca12
+#define regBIF_DEV0_SELECTIVE_IDE_6_BOUND_PF0_31_BASE_IDX                                               5
+#define regBIF_DEV0_SELECTIVE_IDE_6_BOUND_PF0_VF0_31                                                    0xca13
+#define regBIF_DEV0_SELECTIVE_IDE_6_BOUND_PF0_VF0_31_BASE_IDX                                           5
+#define regBIF_DEV0_SELECTIVE_IDE_6_BOUND_PF1_VF0_31                                                    0xca14
+#define regBIF_DEV0_SELECTIVE_IDE_6_BOUND_PF1_VF0_31_BASE_IDX                                           5
+#define regBIF_DEV0_SELECTIVE_IDE_7_BOUND_PF0_31                                                        0xca15
+#define regBIF_DEV0_SELECTIVE_IDE_7_BOUND_PF0_31_BASE_IDX                                               5
+#define regBIF_DEV0_SELECTIVE_IDE_7_BOUND_PF0_VF0_31                                                    0xca16
+#define regBIF_DEV0_SELECTIVE_IDE_7_BOUND_PF0_VF0_31_BASE_IDX                                           5
+#define regBIF_DEV0_SELECTIVE_IDE_7_BOUND_PF1_VF0_31                                                    0xca17
+#define regBIF_DEV0_SELECTIVE_IDE_7_BOUND_PF1_VF0_31_BASE_IDX                                           5
+#define regBIF_DEV0_SELECTIVE_IDE_8_BOUND_PF0_31                                                        0xca18
+#define regBIF_DEV0_SELECTIVE_IDE_8_BOUND_PF0_31_BASE_IDX                                               5
+#define regBIF_DEV0_SELECTIVE_IDE_8_BOUND_PF0_VF0_31                                                    0xca19
+#define regBIF_DEV0_SELECTIVE_IDE_8_BOUND_PF0_VF0_31_BASE_IDX                                           5
+#define regBIF_DEV0_SELECTIVE_IDE_8_BOUND_PF1_VF0_31                                                    0xca1a
+#define regBIF_DEV0_SELECTIVE_IDE_8_BOUND_PF1_VF0_31_BASE_IDX                                           5
+#define regBIF_SYSTEM_EN                                                                                0xca1b
+#define regBIF_SYSTEM_EN_BASE_IDX                                                                       5
+#define regBIF_MASK_SYSTEM_EN                                                                           0xca1c
+#define regBIF_MASK_SYSTEM_EN_BASE_IDX                                                                  5
+#define regGPUIOV_SCH0                                                                                  0xcb40
+#define regGPUIOV_SCH0_BASE_IDX                                                                         5
+#define regGPUIOV_SCH1                                                                                  0xcb41
+#define regGPUIOV_SCH1_BASE_IDX                                                                         5
+#define regGPUIOV_SCH2                                                                                  0xcb42
+#define regGPUIOV_SCH2_BASE_IDX                                                                         5
+#define regGPUIOV_SCH3                                                                                  0xcb43
+#define regGPUIOV_SCH3_BASE_IDX                                                                         5
+#define regGPUIOV_SCH4                                                                                  0xcb44
+#define regGPUIOV_SCH4_BASE_IDX                                                                         5
+#define regGPUIOV_SCH5                                                                                  0xcb45
+#define regGPUIOV_SCH5_BASE_IDX                                                                         5
+#define regGPUIOV_SCH6                                                                                  0xcb46
+#define regGPUIOV_SCH6_BASE_IDX                                                                         5
+#define regGPUIOV_SCH7                                                                                  0xcb47
+#define regGPUIOV_SCH7_BASE_IDX                                                                         5
+#define regGPUIOV_SCH8                                                                                  0xcb48
+#define regGPUIOV_SCH8_BASE_IDX                                                                         5
+#define regGPUIOV_SCH9                                                                                  0xcb49
+#define regGPUIOV_SCH9_BASE_IDX                                                                         5
+#define regGPUIOV_SCH10                                                                                 0xcb4a
+#define regGPUIOV_SCH10_BASE_IDX                                                                        5
+#define regGPUIOV_SCH11                                                                                 0xcb4b
+#define regGPUIOV_SCH11_BASE_IDX                                                                        5
+#define regGPUIOV_SCH12                                                                                 0xcb4c
+#define regGPUIOV_SCH12_BASE_IDX                                                                        5
+#define regGPUIOV_SCH13                                                                                 0xcb4d
+#define regGPUIOV_SCH13_BASE_IDX                                                                        5
+#define regGPUIOV_SCH14                                                                                 0xcb4e
+#define regGPUIOV_SCH14_BASE_IDX                                                                        5
+#define regGPUIOV_SCH15                                                                                 0xcb4f
+#define regGPUIOV_SCH15_BASE_IDX                                                                        5
+#define regGPUIOV_SCH16                                                                                 0xcb50
+#define regGPUIOV_SCH16_BASE_IDX                                                                        5
+#define regGPUIOV_SCH17                                                                                 0xcb51
+#define regGPUIOV_SCH17_BASE_IDX                                                                        5
+#define regGPUIOV_SCH18                                                                                 0xcb52
+#define regGPUIOV_SCH18_BASE_IDX                                                                        5
+#define regGPUIOV_SCH19                                                                                 0xcb53
+#define regGPUIOV_SCH19_BASE_IDX                                                                        5
+#define regGPUIOV_MMHUB_P2P_CNTL                                                                        0xcb54
+#define regGPUIOV_MMHUB_P2P_CNTL_BASE_IDX                                                               5
+#define regBIF_AER_INTR_CTRL                                                                            0xcb55
+#define regBIF_AER_INTR_CTRL_BASE_IDX                                                                   5
+#define regBIF_AER_INTR_STS                                                                             0xcb56
+#define regBIF_AER_INTR_STS_BASE_IDX                                                                    5
+#define regBIF_PCIE_MSG_CTRL                                                                            0xcb57
+#define regBIF_PCIE_MSG_CTRL_BASE_IDX                                                                   5
+#define regBIF_PCIE_MSG_HEADER_DW0                                                                      0xcb58
+#define regBIF_PCIE_MSG_HEADER_DW0_BASE_IDX                                                             5
+#define regBIF_PCIE_MSG_HEADER_DW1                                                                      0xcb59
+#define regBIF_PCIE_MSG_HEADER_DW1_BASE_IDX                                                             5
+#define regBIF_PCIE_MSG_HEADER_DW2                                                                      0xcb5a
+#define regBIF_PCIE_MSG_HEADER_DW2_BASE_IDX                                                             5
+#define regBIF_PCIE_MSG_HEADER_DW3                                                                      0xcb5b
+#define regBIF_PCIE_MSG_HEADER_DW3_BASE_IDX                                                             5
+#define regBIF_PCIE_MSG_DATA_DW0                                                                        0xcb5c
+#define regBIF_PCIE_MSG_DATA_DW0_BASE_IDX                                                               5
+#define regBIF_PCIE_MSG_DATA_DW1                                                                        0xcb5d
+#define regBIF_PCIE_MSG_DATA_DW1_BASE_IDX                                                               5
+#define regBIF_PCIE_MSG_DATA_DW2                                                                        0xcb5e
+#define regBIF_PCIE_MSG_DATA_DW2_BASE_IDX                                                               5
+#define regBIF_PCIE_MSG_DATA_DW3                                                                        0xcb5f
+#define regBIF_PCIE_MSG_DATA_DW3_BASE_IDX                                                               5
+#define regBIFC_SEC_AER_SMN_CTRL0                                                                       0xcb60
+#define regBIFC_SEC_AER_SMN_CTRL0_BASE_IDX                                                              5
+#define regBIFC_SEC_AER_SMN_CTRL1                                                                       0xcb61
+#define regBIFC_SEC_AER_SMN_CTRL1_BASE_IDX                                                              5
+#define regBIFC_SEC_AER_SMN_CTRL2                                                                       0xcb62
+#define regBIFC_SEC_AER_SMN_CTRL2_BASE_IDX                                                              5
+#define regBIF_PCIE_ERR_CTRL0                                                                           0xcb63
+#define regBIF_PCIE_ERR_CTRL0_BASE_IDX                                                                  5
+#define regBIF_PCIE_ERR_CTRL1                                                                           0xcb64
+#define regBIF_PCIE_ERR_CTRL1_BASE_IDX                                                                  5
+#define regBIF_PCIE_ERR_CTRL2                                                                           0xcb65
+#define regBIF_PCIE_ERR_CTRL2_BASE_IDX                                                                  5
+#define regBIF_AER_UNCORR_ERR_STATUS                                                                    0xcb66
+#define regBIF_AER_UNCORR_ERR_STATUS_BASE_IDX                                                           5
+#define regBIF_AER_UNCORR_ERR_MASK                                                                      0xcb67
+#define regBIF_AER_UNCORR_ERR_MASK_BASE_IDX                                                             5
+#define regBIF_AER_UNCORR_ERR_SEVERITY                                                                  0xcb68
+#define regBIF_AER_UNCORR_ERR_SEVERITY_BASE_IDX                                                         5
+#define regBIF_AER_CORR_ERR_STATUS                                                                      0xcb69
+#define regBIF_AER_CORR_ERR_STATUS_BASE_IDX                                                             5
+#define regBIF_AER_CORR_ERR_MASK                                                                        0xcb6a
+#define regBIF_AER_CORR_ERR_MASK_BASE_IDX                                                               5
+#define regRCC_EP_STICKY_RESTORE_0                                                                      0xcb6b
+#define regRCC_EP_STICKY_RESTORE_0_BASE_IDX                                                             5
+#define regRCC_EP_STICKY_RESTORE_1                                                                      0xcb6c
+#define regRCC_EP_STICKY_RESTORE_1_BASE_IDX                                                             5
+#define regRCC_EP_STICKY_RESTORE_2                                                                      0xcb6d
+#define regRCC_EP_STICKY_RESTORE_2_BASE_IDX                                                             5
+#define regRCC_EP_STICKY_RESTORE_3                                                                      0xcb6e
+#define regRCC_EP_STICKY_RESTORE_3_BASE_IDX                                                             5
+#define regRCC_EP_STICKY_RESTORE_4                                                                      0xcb6f
+#define regRCC_EP_STICKY_RESTORE_4_BASE_IDX                                                             5
+#define regRCC_EP_STICKY_RESTORE_5                                                                      0xcb70
+#define regRCC_EP_STICKY_RESTORE_5_BASE_IDX                                                             5
+#define regRCC_EP_STICKY_RESTORE_6                                                                      0xcb71
+#define regRCC_EP_STICKY_RESTORE_6_BASE_IDX                                                             5
+#define regRCC_EP_STICKY_RESTORE_7                                                                      0xcb72
+#define regRCC_EP_STICKY_RESTORE_7_BASE_IDX                                                             5
+#define regRCC_EP_STICKY_RESTORE_8                                                                      0xcb73
+#define regRCC_EP_STICKY_RESTORE_8_BASE_IDX                                                             5
+#define regRCC_EP_STICKY_RESTORE_9                                                                      0xcb74
+#define regRCC_EP_STICKY_RESTORE_9_BASE_IDX                                                             5
+#define regRCC_EP_STICKY_RESTORE_10                                                                     0xcb75
+#define regRCC_EP_STICKY_RESTORE_10_BASE_IDX                                                            5
+#define regRCC_EP_STICKY_RESTORE_11                                                                     0xcb76
+#define regRCC_EP_STICKY_RESTORE_11_BASE_IDX                                                            5
+#define regRCC_EP_STICKY_RESTORE_12                                                                     0xcb77
+#define regRCC_EP_STICKY_RESTORE_12_BASE_IDX                                                            5
+#define regRCC_EP_STICKY_RESTORE_13                                                                     0xcb78
+#define regRCC_EP_STICKY_RESTORE_13_BASE_IDX                                                            5
+#define regBIF_DEVICE3_STATUS                                                                           0xcb79
+#define regBIF_DEVICE3_STATUS_BASE_IDX                                                                  5
+#define regBIFC_SEC_MCTP_SMN_CTRL0                                                                      0xcb81
+#define regBIFC_SEC_MCTP_SMN_CTRL0_BASE_IDX                                                             5
+#define regBIFC_SEC_MCTP_SMN_CTRL1                                                                      0xcb82
+#define regBIFC_SEC_MCTP_SMN_CTRL1_BASE_IDX                                                             5
+#define regNBIF_MCTP_GENERIC_CNTL                                                                       0xcc08
+#define regNBIF_MCTP_GENERIC_CNTL_BASE_IDX                                                              5
+#define regNBIF_MCTP_GENERIC_STATUS                                                                     0xcc09
+#define regNBIF_MCTP_GENERIC_STATUS_BASE_IDX                                                            5
+#define regSDPVW_UPDATE_EN                                                                              0xcc22
+#define regSDPVW_UPDATE_EN_BASE_IDX                                                                     5
+#define regREGS_ROM_OFFSET_CTRL                                                                         0xcc23
+#define regREGS_ROM_OFFSET_CTRL_BASE_IDX                                                                5
+#define regBIFL_SEC_RAS_POISON_DATA_DROP_CTRL                                                           0xcc24
+#define regBIFL_SEC_RAS_POISON_DATA_DROP_CTRL_BASE_IDX                                                  5
+#define regREGS_INDEX_DATA_PAIR_CTRL                                                                    0xcc25
+#define regREGS_INDEX_DATA_PAIR_CTRL_BASE_IDX                                                           5
+#define regBIFL_SEC_RAS_RESPONSE_DROP_CTRL                                                              0xcc26
+#define regBIFL_SEC_RAS_RESPONSE_DROP_CTRL_BASE_IDX                                                     5
+#define regBIFC_SEC_MCA_SMN_CTRL0                                                                       0xcc44
+#define regBIFC_SEC_MCA_SMN_CTRL0_BASE_IDX                                                              5
+#define regBIFC_SEC_MCA_SMN_CTRL1                                                                       0xcc45
+#define regBIFC_SEC_MCA_SMN_CTRL1_BASE_IDX                                                              5
+#define regBIFL_SEC_RAS_POISON_DBUG_CTRL                                                                0xcc46
+#define regBIFL_SEC_RAS_POISON_DBUG_CTRL_BASE_IDX                                                       5
+#define regBIFL_SEC_RAS_PARITY_DBUG_CTRL                                                                0xcc47
+#define regBIFL_SEC_RAS_PARITY_DBUG_CTRL_BASE_IDX                                                       5
+#define regBIFL_SEC_RAS_NTB_DBUG_CTRL                                                                   0xcc48
+#define regBIFL_SEC_RAS_NTB_DBUG_CTRL_BASE_IDX                                                          5
+#define regBIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL                                                           0xcc4a
+#define regBIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL_BASE_IDX                                                  5
+#define regBIFL_SEC_RAS_TIMEOUT_DBUG_CTRL                                                               0xcc4c
+#define regBIFL_SEC_RAS_TIMEOUT_DBUG_CTRL_BASE_IDX                                                      5
+#define regBIFL_SEC_RAS_LEAF0_RRESP_POISON_CTRL                                                         0xcc5b
+#define regBIFL_SEC_RAS_LEAF0_RRESP_POISON_CTRL_BASE_IDX                                                5
+#define regBIFL_SEC_RAS_LEAF0_RUSER_POISON_CTRL                                                         0xcc5c
+#define regBIFL_SEC_RAS_LEAF0_RUSER_POISON_CTRL_BASE_IDX                                                5
+#define regBIFL_SEC_RAS_LEAF1_RRESP_POISON_CTRL                                                         0xcc5d
+#define regBIFL_SEC_RAS_LEAF1_RRESP_POISON_CTRL_BASE_IDX                                                5
+#define regBIFL_SEC_RAS_LEAF1_RUSER_POISON_CTRL                                                         0xcc5e
+#define regBIFL_SEC_RAS_LEAF1_RUSER_POISON_CTRL_BASE_IDX                                                5
+#define regBIFL_SEC_RAS_LEAF2_RRESP_POISON_CTRL                                                         0xcc5f
+#define regBIFL_SEC_RAS_LEAF2_RRESP_POISON_CTRL_BASE_IDX                                                5
+#define regBIFL_SEC_RAS_LEAF2_RUSER_POISON_CTRL                                                         0xcc60
+#define regBIFL_SEC_RAS_LEAF2_RUSER_POISON_CTRL_BASE_IDX                                                5
+#define regBIFL_SEC_RAS_LEAF3_RRESP_POISON_CTRL                                                         0xcc61
+#define regBIFL_SEC_RAS_LEAF3_RRESP_POISON_CTRL_BASE_IDX                                                5
+#define regBIFL_SEC_RAS_LEAF3_RUSER_POISON_CTRL                                                         0xcc62
+#define regBIFL_SEC_RAS_LEAF3_RUSER_POISON_CTRL_BASE_IDX                                                5
+#define regBIFL_SEC_RAS_LEAF4_RRESP_POISON_CTRL                                                         0xcc63
+#define regBIFL_SEC_RAS_LEAF4_RRESP_POISON_CTRL_BASE_IDX                                                5
+#define regBIFL_SEC_RAS_LEAF4_RUSER_POISON_CTRL                                                         0xcc64
+#define regBIFL_SEC_RAS_LEAF4_RUSER_POISON_CTRL_BASE_IDX                                                5
+#define regBIFL_SEC_RAS_LEAF5_RRESP_POISON_CTRL                                                         0xcc65
+#define regBIFL_SEC_RAS_LEAF5_RRESP_POISON_CTRL_BASE_IDX                                                5
+#define regBIFL_SEC_RAS_LEAF5_RUSER_POISON_CTRL                                                         0xcc66
+#define regBIFL_SEC_RAS_LEAF5_RUSER_POISON_CTRL_BASE_IDX                                                5
+#define regBIFL_SEC_RAS_LEAF6_RRESP_POISON_CTRL                                                         0xcc67
+#define regBIFL_SEC_RAS_LEAF6_RRESP_POISON_CTRL_BASE_IDX                                                5
+#define regBIFL_SEC_RAS_LEAF6_RUSER_POISON_CTRL                                                         0xcc68
+#define regBIFL_SEC_RAS_LEAF6_RUSER_POISON_CTRL_BASE_IDX                                                5
+#define regBIFL_SEC_RAS_LEAF7_RRESP_POISON_CTRL                                                         0xcc69
+#define regBIFL_SEC_RAS_LEAF7_RRESP_POISON_CTRL_BASE_IDX                                                5
+#define regBIFL_SEC_RAS_LEAF7_RUSER_POISON_CTRL                                                         0xcc6a
+#define regBIFL_SEC_RAS_LEAF7_RUSER_POISON_CTRL_BASE_IDX                                                5
+#define regBIFL_SEC_RAS_LEAF8_RRESP_POISON_CTRL                                                         0xcc6b
+#define regBIFL_SEC_RAS_LEAF8_RRESP_POISON_CTRL_BASE_IDX                                                5
+#define regBIFL_SEC_RAS_LEAF8_RUSER_POISON_CTRL                                                         0xcc6c
+#define regBIFL_SEC_RAS_LEAF8_RUSER_POISON_CTRL_BASE_IDX                                                5
+#define regBIFL_SEC_RAS_LEAF9_RRESP_POISON_CTRL                                                         0xcc6d
+#define regBIFL_SEC_RAS_LEAF9_RRESP_POISON_CTRL_BASE_IDX                                                5
+#define regBIFL_SEC_RAS_LEAF9_RUSER_POISON_CTRL                                                         0xcc6e
+#define regBIFL_SEC_RAS_LEAF9_RUSER_POISON_CTRL_BASE_IDX                                                5
+#define regBIFL_SEC_RAS_LEAF10_RRESP_POISON_CTRL                                                        0xcc6f
+#define regBIFL_SEC_RAS_LEAF10_RRESP_POISON_CTRL_BASE_IDX                                               5
+#define regBIFL_SEC_RAS_LEAF10_RUSER_POISON_CTRL                                                        0xcc70
+#define regBIFL_SEC_RAS_LEAF10_RUSER_POISON_CTRL_BASE_IDX                                               5
+#define regBIFL_SEC_RAS_LEAF11_RRESP_POISON_CTRL                                                        0xcc71
+#define regBIFL_SEC_RAS_LEAF11_RRESP_POISON_CTRL_BASE_IDX                                               5
+#define regBIFL_SEC_RAS_LEAF11_RUSER_POISON_CTRL                                                        0xcc72
+#define regBIFL_SEC_RAS_LEAF11_RUSER_POISON_CTRL_BASE_IDX                                               5
+#define regBIFL_SEC_RAS_LEAF12_RRESP_POISON_CTRL                                                        0xcc73
+#define regBIFL_SEC_RAS_LEAF12_RRESP_POISON_CTRL_BASE_IDX                                               5
+#define regBIFL_SEC_RAS_LEAF12_RUSER_POISON_CTRL                                                        0xcc74
+#define regBIFL_SEC_RAS_LEAF12_RUSER_POISON_CTRL_BASE_IDX                                               5
+#define regBIFL_SEC_RAS_LEAF13_RRESP_POISON_CTRL                                                        0xcc75
+#define regBIFL_SEC_RAS_LEAF13_RRESP_POISON_CTRL_BASE_IDX                                               5
+#define regBIFL_SEC_RAS_LEAF13_RUSER_POISON_CTRL                                                        0xcc76
+#define regBIFL_SEC_RAS_LEAF13_RUSER_POISON_CTRL_BASE_IDX                                               5
+#define regBIFL_SEC_RAS_LEAF14_RRESP_POISON_CTRL                                                        0xcc77
+#define regBIFL_SEC_RAS_LEAF14_RRESP_POISON_CTRL_BASE_IDX                                               5
+#define regBIFL_SEC_RAS_LEAF14_RUSER_POISON_CTRL                                                        0xcc78
+#define regBIFL_SEC_RAS_LEAF14_RUSER_POISON_CTRL_BASE_IDX                                               5
+#define regBIFL_SEC_RAS_LEAF15_RRESP_POISON_CTRL                                                        0xcc79
+#define regBIFL_SEC_RAS_LEAF15_RRESP_POISON_CTRL_BASE_IDX                                               5
+#define regBIFL_SEC_RAS_LEAF15_RUSER_POISON_CTRL                                                        0xcc7a
+#define regBIFL_SEC_RAS_LEAF15_RUSER_POISON_CTRL_BASE_IDX                                               5
+#define regBIFL_SEC_RAS_LEAF16_RRESP_POISON_CTRL                                                        0xcc7b
+#define regBIFL_SEC_RAS_LEAF16_RRESP_POISON_CTRL_BASE_IDX                                               5
+#define regBIFL_SEC_RAS_LEAF16_RUSER_POISON_CTRL                                                        0xcc7c
+#define regBIFL_SEC_RAS_LEAF16_RUSER_POISON_CTRL_BASE_IDX                                               5
+#define regBIFL_SEC_RAS_LEAF17_RRESP_POISON_CTRL                                                        0xcc7d
+#define regBIFL_SEC_RAS_LEAF17_RRESP_POISON_CTRL_BASE_IDX                                               5
+#define regBIFL_SEC_RAS_LEAF17_RUSER_POISON_CTRL                                                        0xcc7e
+#define regBIFL_SEC_RAS_LEAF17_RUSER_POISON_CTRL_BASE_IDX                                               5
+#define regBIFL_SEC_RAS_LEAF18_RRESP_POISON_CTRL                                                        0xcc7f
+#define regBIFL_SEC_RAS_LEAF18_RRESP_POISON_CTRL_BASE_IDX                                               5
+#define regBIFL_SEC_RAS_LEAF18_RUSER_POISON_CTRL                                                        0xcc80
+#define regBIFL_SEC_RAS_LEAF18_RUSER_POISON_CTRL_BASE_IDX                                               5
+#define regBIFL_SEC_RAS_LEAF19_RRESP_POISON_CTRL                                                        0xcc81
+#define regBIFL_SEC_RAS_LEAF19_RRESP_POISON_CTRL_BASE_IDX                                               5
+#define regBIFL_SEC_RAS_LEAF19_RUSER_POISON_CTRL                                                        0xcc82
+#define regBIFL_SEC_RAS_LEAF19_RUSER_POISON_CTRL_BASE_IDX                                               5
+#define regNBIF_STRAP_BIOS_CNTL                                                                         0xcc89
+#define regNBIF_STRAP_BIOS_CNTL_BASE_IDX                                                                5
+#define regSMN_MST_NORMAL_SECURITY                                                                      0xcdea
+#define regSMN_MST_NORMAL_SECURITY_BASE_IDX                                                             5
+#define regOVERRIDE_TYPE_FOR_CHAIN_CTRL                                                                 0xcdec
+#define regOVERRIDE_TYPE_FOR_CHAIN_CTRL_BASE_IDX                                                        5
+#define regPROCESSING_HINT_SUPPORT_CNTL                                                                 0xcded
+#define regPROCESSING_HINT_SUPPORT_CNTL_BASE_IDX                                                        5
+#define regDEV0_PF0_VF0_MMIO0_FENCE                                                                     0xce40
+#define regDEV0_PF0_VF0_MMIO0_FENCE_BASE_IDX                                                            5
+#define regDEV0_PF0_VF1_MMIO0_FENCE                                                                     0xce41
+#define regDEV0_PF0_VF1_MMIO0_FENCE_BASE_IDX                                                            5
+#define regDEV0_PF0_VF2_MMIO0_FENCE                                                                     0xce42
+#define regDEV0_PF0_VF2_MMIO0_FENCE_BASE_IDX                                                            5
+#define regDEV0_PF0_VF3_MMIO0_FENCE                                                                     0xce43
+#define regDEV0_PF0_VF3_MMIO0_FENCE_BASE_IDX                                                            5
+#define regDEV0_PF0_VF4_MMIO0_FENCE                                                                     0xce44
+#define regDEV0_PF0_VF4_MMIO0_FENCE_BASE_IDX                                                            5
+#define regDEV0_PF0_VF5_MMIO0_FENCE                                                                     0xce45
+#define regDEV0_PF0_VF5_MMIO0_FENCE_BASE_IDX                                                            5
+#define regDEV0_PF0_VF6_MMIO0_FENCE                                                                     0xce46
+#define regDEV0_PF0_VF6_MMIO0_FENCE_BASE_IDX                                                            5
+#define regDEV0_PF0_VF7_MMIO0_FENCE                                                                     0xce47
+#define regDEV0_PF0_VF7_MMIO0_FENCE_BASE_IDX                                                            5
+#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE0_START                                                         0xce48
+#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE0_START_BASE_IDX                                                5
+#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE0_END                                                           0xce49
+#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE0_END_BASE_IDX                                                  5
+#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE1_START                                                         0xce4a
+#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE1_START_BASE_IDX                                                5
+#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE1_END                                                           0xce4b
+#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE1_END_BASE_IDX                                                  5
+#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE2_START                                                         0xce4c
+#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE2_START_BASE_IDX                                                5
+#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE2_END                                                           0xce4d
+#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE2_END_BASE_IDX                                                  5
+#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE3_START                                                         0xce4e
+#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE3_START_BASE_IDX                                                5
+#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE3_END                                                           0xce4f
+#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE3_END_BASE_IDX                                                  5
+#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE4_START                                                         0xce50
+#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE4_START_BASE_IDX                                                5
+#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE4_END                                                           0xce51
+#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE4_END_BASE_IDX                                                  5
+#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE5_START                                                         0xce52
+#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE5_START_BASE_IDX                                                5
+#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE5_END                                                           0xce53
+#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE5_END_BASE_IDX                                                  5
+#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE6_START                                                         0xce54
+#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE6_START_BASE_IDX                                                5
+#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE6_END                                                           0xce55
+#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE6_END_BASE_IDX                                                  5
+#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE7_START                                                         0xce56
+#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE7_START_BASE_IDX                                                5
+#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE7_END                                                           0xce57
+#define regDEV0_PF0_VF_MMIO0_FENCE_RANGE7_END_BASE_IDX                                                  5
+#define regDEV0_PF1_VF0_MMIO0_FENCE                                                                     0xce58
+#define regDEV0_PF1_VF0_MMIO0_FENCE_BASE_IDX                                                            5
+#define regDEV0_PF1_VF_MMIO0_FENCE_RANGE0_START                                                         0xce59
+#define regDEV0_PF1_VF_MMIO0_FENCE_RANGE0_START_BASE_IDX                                                5
+#define regDEV0_PF1_VF_MMIO0_FENCE_RANGE0_END                                                           0xce5a
+#define regDEV0_PF1_VF_MMIO0_FENCE_RANGE0_END_BASE_IDX                                                  5
+#define regDEV0_PF1_VF_MMIO0_FENCE_RANGE1_START                                                         0xce5b
+#define regDEV0_PF1_VF_MMIO0_FENCE_RANGE1_START_BASE_IDX                                                5
+#define regDEV0_PF1_VF_MMIO0_FENCE_RANGE1_END                                                           0xce5c
+#define regDEV0_PF1_VF_MMIO0_FENCE_RANGE1_END_BASE_IDX                                                  5
+#define regDEV0_PF1_VF_MMIO0_FENCE_RANGE2_START                                                         0xce5d
+#define regDEV0_PF1_VF_MMIO0_FENCE_RANGE2_START_BASE_IDX                                                5
+#define regDEV0_PF1_VF_MMIO0_FENCE_RANGE2_END                                                           0xce5e
+#define regDEV0_PF1_VF_MMIO0_FENCE_RANGE2_END_BASE_IDX                                                  5
+#define regDEV0_PF1_VF_MMIO0_FENCE_RANGE3_START                                                         0xce5f
+#define regDEV0_PF1_VF_MMIO0_FENCE_RANGE3_START_BASE_IDX                                                5
+#define regDEV0_PF1_VF_MMIO0_FENCE_RANGE3_END                                                           0xce60
+#define regDEV0_PF1_VF_MMIO0_FENCE_RANGE3_END_BASE_IDX                                                  5
+#define regDEV0_PF0_PF_MMIO0_FENCE_WR                                                                   0xce61
+#define regDEV0_PF0_PF_MMIO0_FENCE_WR_BASE_IDX                                                          5
+#define regDEV0_PF0_PF_MMIO0_FENCE_RD                                                                   0xce62
+#define regDEV0_PF0_PF_MMIO0_FENCE_RD_BASE_IDX                                                          5
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE0_START                                                         0xce63
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE0_START_BASE_IDX                                                5
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE0_END                                                           0xce64
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE0_END_BASE_IDX                                                  5
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE1_START                                                         0xce65
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE1_START_BASE_IDX                                                5
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE1_END                                                           0xce66
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE1_END_BASE_IDX                                                  5
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE2_START                                                         0xce67
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE2_START_BASE_IDX                                                5
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE2_END                                                           0xce68
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE2_END_BASE_IDX                                                  5
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE3_START                                                         0xce69
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE3_START_BASE_IDX                                                5
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE3_END                                                           0xce6a
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE3_END_BASE_IDX                                                  5
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE4_START                                                         0xce6b
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE4_START_BASE_IDX                                                5
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE4_END                                                           0xce6c
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE4_END_BASE_IDX                                                  5
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE5_START                                                         0xce6d
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE5_START_BASE_IDX                                                5
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE5_END                                                           0xce6e
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE5_END_BASE_IDX                                                  5
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE6_START                                                         0xce6f
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE6_START_BASE_IDX                                                5
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE6_END                                                           0xce70
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE6_END_BASE_IDX                                                  5
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE7_START                                                         0xce71
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE7_START_BASE_IDX                                                5
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE7_END                                                           0xce72
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE7_END_BASE_IDX                                                  5
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE8_START                                                         0xce73
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE8_START_BASE_IDX                                                5
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE8_END                                                           0xce74
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE8_END_BASE_IDX                                                  5
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE9_START                                                         0xce75
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE9_START_BASE_IDX                                                5
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE9_END                                                           0xce76
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE9_END_BASE_IDX                                                  5
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE10_START                                                        0xce77
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE10_START_BASE_IDX                                               5
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE10_END                                                          0xce78
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE10_END_BASE_IDX                                                 5
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE11_START                                                        0xce79
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE11_START_BASE_IDX                                               5
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE11_END                                                          0xce7a
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE11_END_BASE_IDX                                                 5
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE12_START                                                        0xce7b
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE12_START_BASE_IDX                                               5
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE12_END                                                          0xce7c
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE12_END_BASE_IDX                                                 5
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE13_START                                                        0xce7d
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE13_START_BASE_IDX                                               5
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE13_END                                                          0xce7e
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE13_END_BASE_IDX                                                 5
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE14_START                                                        0xce7f
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE14_START_BASE_IDX                                               5
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE14_END                                                          0xce80
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE14_END_BASE_IDX                                                 5
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE15_START                                                        0xce81
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE15_START_BASE_IDX                                               5
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE15_END                                                          0xce82
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE15_END_BASE_IDX                                                 5
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE16_START                                                        0xce83
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE16_START_BASE_IDX                                               5
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE16_END                                                          0xce84
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE16_END_BASE_IDX                                                 5
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE17_START                                                        0xce85
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE17_START_BASE_IDX                                               5
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE17_END                                                          0xce86
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE17_END_BASE_IDX                                                 5
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE18_START                                                        0xce87
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE18_START_BASE_IDX                                               5
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE18_END                                                          0xce88
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE18_END_BASE_IDX                                                 5
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE19_START                                                        0xce89
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE19_START_BASE_IDX                                               5
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE19_END                                                          0xce8a
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE19_END_BASE_IDX                                                 5
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE20_START                                                        0xce8b
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE20_START_BASE_IDX                                               5
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE20_END                                                          0xce8c
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE20_END_BASE_IDX                                                 5
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE21_START                                                        0xce8d
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE21_START_BASE_IDX                                               5
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE21_END                                                          0xce8e
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE21_END_BASE_IDX                                                 5
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE22_START                                                        0xce8f
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE22_START_BASE_IDX                                               5
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE22_END                                                          0xce90
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE22_END_BASE_IDX                                                 5
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE23_START                                                        0xce91
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE23_START_BASE_IDX                                               5
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE23_END                                                          0xce92
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE23_END_BASE_IDX                                                 5
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE24_START                                                        0xce93
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE24_START_BASE_IDX                                               5
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE24_END                                                          0xce94
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE24_END_BASE_IDX                                                 5
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE25_START                                                        0xce95
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE25_START_BASE_IDX                                               5
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE25_END                                                          0xce96
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE25_END_BASE_IDX                                                 5
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE26_START                                                        0xce97
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE26_START_BASE_IDX                                               5
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE26_END                                                          0xce98
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE26_END_BASE_IDX                                                 5
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE27_START                                                        0xce99
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE27_START_BASE_IDX                                               5
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE27_END                                                          0xce9a
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE27_END_BASE_IDX                                                 5
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE28_START                                                        0xce9b
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE28_START_BASE_IDX                                               5
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE28_END                                                          0xce9c
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE28_END_BASE_IDX                                                 5
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE29_START                                                        0xce9d
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE29_START_BASE_IDX                                               5
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE29_END                                                          0xce9e
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE29_END_BASE_IDX                                                 5
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE30_START                                                        0xce9f
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE30_START_BASE_IDX                                               5
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE30_END                                                          0xcea0
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE30_END_BASE_IDX                                                 5
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE31_START                                                        0xcea1
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE31_START_BASE_IDX                                               5
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE31_END                                                          0xcea2
+#define regDEV0_PF0_PF_MMIO0_FENCE_RANGE31_END_BASE_IDX                                                 5
+#define regDEV0_PF1_PF_MMIO0_FENCE_WR                                                                   0xcea3
+#define regDEV0_PF1_PF_MMIO0_FENCE_WR_BASE_IDX                                                          5
+#define regDEV0_PF1_PF_MMIO0_FENCE_RD                                                                   0xcea4
+#define regDEV0_PF1_PF_MMIO0_FENCE_RD_BASE_IDX                                                          5
+#define regDEV0_PF1_PF_MMIO0_FENCE_RANGE0_START                                                         0xcea5
+#define regDEV0_PF1_PF_MMIO0_FENCE_RANGE0_START_BASE_IDX                                                5
+#define regDEV0_PF1_PF_MMIO0_FENCE_RANGE0_END                                                           0xcea6
+#define regDEV0_PF1_PF_MMIO0_FENCE_RANGE0_END_BASE_IDX                                                  5
+#define regDEV0_PF1_PF_MMIO0_FENCE_RANGE1_START                                                         0xcea7
+#define regDEV0_PF1_PF_MMIO0_FENCE_RANGE1_START_BASE_IDX                                                5
+#define regDEV0_PF1_PF_MMIO0_FENCE_RANGE1_END                                                           0xcea8
+#define regDEV0_PF1_PF_MMIO0_FENCE_RANGE1_END_BASE_IDX                                                  5
+#define regDEV0_PF1_PF_MMIO0_FENCE_RANGE2_START                                                         0xcea9
+#define regDEV0_PF1_PF_MMIO0_FENCE_RANGE2_START_BASE_IDX                                                5
+#define regDEV0_PF1_PF_MMIO0_FENCE_RANGE2_END                                                           0xceaa
+#define regDEV0_PF1_PF_MMIO0_FENCE_RANGE2_END_BASE_IDX                                                  5
+#define regDEV0_PF1_PF_MMIO0_FENCE_RANGE3_START                                                         0xceab
+#define regDEV0_PF1_PF_MMIO0_FENCE_RANGE3_START_BASE_IDX                                                5
+#define regDEV0_PF1_PF_MMIO0_FENCE_RANGE3_END                                                           0xceac
+#define regDEV0_PF1_PF_MMIO0_FENCE_RANGE3_END_BASE_IDX                                                  5
+#define regMISC_SCRATCH                                                                                 0xe800
+#define regMISC_SCRATCH_BASE_IDX                                                                        5
+#define regINTR_LINE_POLARITY                                                                           0xe801
+#define regINTR_LINE_POLARITY_BASE_IDX                                                                  5
+#define regINTR_LINE_ENABLE                                                                             0xe802
+#define regINTR_LINE_ENABLE_BASE_IDX                                                                    5
+#define regOUTSTANDING_VC_ALLOC                                                                         0xe803
+#define regOUTSTANDING_VC_ALLOC_BASE_IDX                                                                5
+#define regBIFC_MISC_CTRL0                                                                              0xe804
+#define regBIFC_MISC_CTRL0_BASE_IDX                                                                     5
+#define regBIFC_MISC_CTRL1                                                                              0xe805
+#define regBIFC_MISC_CTRL1_BASE_IDX                                                                     5
+#define regBIFC_BME_ERR_LOG_LB                                                                          0xe806
+#define regBIFC_BME_ERR_LOG_LB_BASE_IDX                                                                 5
+#define regBIFC_LC_TIMER_CTRL                                                                           0xe807
+#define regBIFC_LC_TIMER_CTRL_BASE_IDX                                                                  5
+#define regBIFC_RCCBIH_BME_ERR_LOG0                                                                     0xe808
+#define regBIFC_RCCBIH_BME_ERR_LOG0_BASE_IDX                                                            5
+#define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1                                                            0xe80a
+#define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1_BASE_IDX                                                   5
+#define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3                                                            0xe80b
+#define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3_BASE_IDX                                                   5
+#define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5                                                            0xe80c
+#define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5_BASE_IDX                                                   5
+#define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7                                                            0xe80d
+#define regBIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7_BASE_IDX                                                   5
+#define regBIFC_DMA_ATTR_CNTL2_DEV0                                                                     0xe81a
+#define regBIFC_DMA_ATTR_CNTL2_DEV0_BASE_IDX                                                            5
+#define regBIFC_MISC_CTRL2                                                                              0xe822
+#define regBIFC_MISC_CTRL2_BASE_IDX                                                                     5
+#define regBME_DUMMY_CNTL_0                                                                             0xe825
+#define regBME_DUMMY_CNTL_0_BASE_IDX                                                                    5
+#define regBIFC_THT_CNTL                                                                                0xe827
+#define regBIFC_THT_CNTL_BASE_IDX                                                                       5
+#define regBIFC_HSTARB_CNTL                                                                             0xe828
+#define regBIFC_HSTARB_CNTL_BASE_IDX                                                                    5
+#define regBIFC_GSI_CNTL                                                                                0xe829
+#define regBIFC_GSI_CNTL_BASE_IDX                                                                       5
+#define regBIFC_PCIEFUNC_CNTL                                                                           0xe82a
+#define regBIFC_PCIEFUNC_CNTL_BASE_IDX                                                                  5
+#define regBIFC_PASID_CHECK_DIS                                                                         0xe82b
+#define regBIFC_PASID_CHECK_DIS_BASE_IDX                                                                5
+#define regBIFC_SDP_CNTL_0                                                                              0xe82c
+#define regBIFC_SDP_CNTL_0_BASE_IDX                                                                     5
+#define regBIFC_SDP_CNTL_1                                                                              0xe82d
+#define regBIFC_SDP_CNTL_1_BASE_IDX                                                                     5
+#define regBIFC_PASID_STS                                                                               0xe82e
+#define regBIFC_PASID_STS_BASE_IDX                                                                      5
+#define regBIFC_ATHUB_ACT_CNTL                                                                          0xe82f
+#define regBIFC_ATHUB_ACT_CNTL_BASE_IDX                                                                 5
+#define regBIFC_PERF_CNTL_0                                                                             0xe830
+#define regBIFC_PERF_CNTL_0_BASE_IDX                                                                    5
+#define regBIF_MISC_BIFC_PERF_CNTL_1                                                                    0xe831
+#define regBIF_MISC_BIFC_PERF_CNTL_1_BASE_IDX                                                           5
+#define regBIFC_PERF_CNT_MMIO_RD_L32BIT                                                                 0xe832
+#define regBIFC_PERF_CNT_MMIO_RD_L32BIT_BASE_IDX                                                        5
+#define regBIFC_PERF_CNT_MMIO_WR_L32BIT                                                                 0xe833
+#define regBIFC_PERF_CNT_MMIO_WR_L32BIT_BASE_IDX                                                        5
+#define regBIF_MISC_BIFC_PERF_CNT_DMA_RD_L32BIT                                                         0xe834
+#define regBIF_MISC_BIFC_PERF_CNT_DMA_RD_L32BIT_BASE_IDX                                                5
+#define regBIF_MISC_BIFC_PERF_CNT_DMA_WR_L32BIT                                                         0xe835
+#define regBIF_MISC_BIFC_PERF_CNT_DMA_WR_L32BIT_BASE_IDX                                                5
+#define regNBIF_REGIF_ERRSET_CTRL                                                                       0xe836
+#define regNBIF_REGIF_ERRSET_CTRL_BASE_IDX                                                              5
+#define regBIFC_SDP_CNTL_2                                                                              0xe837
+#define regBIFC_SDP_CNTL_2_BASE_IDX                                                                     5
+#define regNBIF_PGMST_CTRL                                                                              0xe838
+#define regNBIF_PGMST_CTRL_BASE_IDX                                                                     5
+#define regNBIF_PGSLV_CTRL                                                                              0xe839
+#define regNBIF_PGSLV_CTRL_BASE_IDX                                                                     5
+#define regNBIF_PG_MISC_CTRL                                                                            0xe83a
+#define regNBIF_PG_MISC_CTRL_BASE_IDX                                                                   5
+#define regSMN_MST_EP_CNTL3                                                                             0xe83c
+#define regSMN_MST_EP_CNTL3_BASE_IDX                                                                    5
+#define regSMN_MST_EP_CNTL4                                                                             0xe83d
+#define regSMN_MST_EP_CNTL4_BASE_IDX                                                                    5
+#define regSMN_MST_CNTL1                                                                                0xe83e
+#define regSMN_MST_CNTL1_BASE_IDX                                                                       5
+#define regSMN_MST_EP_CNTL5                                                                             0xe83f
+#define regSMN_MST_EP_CNTL5_BASE_IDX                                                                    5
+#define regBIF_SELFRING_BUFFER_VID                                                                      0xe840
+#define regBIF_SELFRING_BUFFER_VID_BASE_IDX                                                             5
+#define regBIF_SELFRING_VECTOR_CNTL                                                                     0xe841
+#define regBIF_SELFRING_VECTOR_CNTL_BASE_IDX                                                            5
+#define regHDP_ERR_STATUS_EXT                                                                           0xe842
+#define regHDP_ERR_STATUS_EXT_BASE_IDX                                                                  5
+#define regNBIF_STRAP_WRITE_CTRL                                                                        0xe845
+#define regNBIF_STRAP_WRITE_CTRL_BASE_IDX                                                               5
+#define regNBIF_INTX_DSTATE_MISC_CNTL                                                                   0xe846
+#define regNBIF_INTX_DSTATE_MISC_CNTL_BASE_IDX                                                          5
+#define regNBIF_PENDING_MISC_CNTL                                                                       0xe847
+#define regNBIF_PENDING_MISC_CNTL_BASE_IDX                                                              5
+#define regBIF_GMI_WRR_WEIGHT                                                                           0xe848
+#define regBIF_GMI_WRR_WEIGHT_BASE_IDX                                                                  5
+#define regBIF_GMI_WRR_WEIGHT2                                                                          0xe849
+#define regBIF_GMI_WRR_WEIGHT2_BASE_IDX                                                                 5
+#define regBIF_GMI_WRR_WEIGHT3                                                                          0xe84a
+#define regBIF_GMI_WRR_WEIGHT3_BASE_IDX                                                                 5
+#define regBIF_GMI_WRR_WEIGHT4                                                                          0xe84b
+#define regBIF_GMI_WRR_WEIGHT4_BASE_IDX                                                                 5
+#define regNBIF_PWRBRK_REQUEST                                                                          0xe84c
+#define regNBIF_PWRBRK_REQUEST_BASE_IDX                                                                 5
+#define regBIF_ATOMIC_ERR_LOG_DEV0_F0                                                                   0xe850
+#define regBIF_ATOMIC_ERR_LOG_DEV0_F0_BASE_IDX                                                          5
+#define regBIF_ATOMIC_ERR_LOG_DEV0_F1                                                                   0xe851
+#define regBIF_ATOMIC_ERR_LOG_DEV0_F1_BASE_IDX                                                          5
+#define regBIF_DMA_MP4_ERR_LOG                                                                          0xe870
+#define regBIF_DMA_MP4_ERR_LOG_BASE_IDX                                                                 5
+#define regBIF_PASID_ERR_LOG                                                                            0xe871
+#define regBIF_PASID_ERR_LOG_BASE_IDX                                                                   5
+#define regBIF_PASID_ERR_CLR                                                                            0xe872
+#define regBIF_PASID_ERR_CLR_BASE_IDX                                                                   5
+#define regNBIF_VWIRE_CTRL                                                                              0xe880
+#define regNBIF_VWIRE_CTRL_BASE_IDX                                                                     5
+#define regNBIF_MGCG_CTRL_LCLK                                                                          0xe887
+#define regNBIF_MGCG_CTRL_LCLK_BASE_IDX                                                                 5
+#define regNBIF_DS_CTRL_LCLK                                                                            0xe888
+#define regNBIF_DS_CTRL_LCLK_BASE_IDX                                                                   5
+#define regSMN_MST_CNTL0                                                                                0xe889
+#define regSMN_MST_CNTL0_BASE_IDX                                                                       5
+#define regSMN_MST_EP_CNTL1                                                                             0xe88a
+#define regSMN_MST_EP_CNTL1_BASE_IDX                                                                    5
+#define regSMN_MST_EP_CNTL2                                                                             0xe88b
+#define regSMN_MST_EP_CNTL2_BASE_IDX                                                                    5
+#define regNBIF_SDP_VWR_VCHG_DIS_CTRL                                                                   0xe88c
+#define regNBIF_SDP_VWR_VCHG_DIS_CTRL_BASE_IDX                                                          5
+#define regNBIF_SDP_VWR_VCHG_RST_CTRL0                                                                  0xe88d
+#define regNBIF_SDP_VWR_VCHG_RST_CTRL0_BASE_IDX                                                         5
+#define regNBIF_SDP_VWR_VCHG_RST_CTRL1                                                                  0xe88e
+#define regNBIF_SDP_VWR_VCHG_RST_CTRL1_BASE_IDX                                                         5
+#define regNBIF_SDP_VWR_VCHG_TRIG                                                                       0xe88f
+#define regNBIF_SDP_VWR_VCHG_TRIG_BASE_IDX                                                              5
+#define regNBIO_LCLK_DEEPSLEEP_MASK                                                                     0xe890
+#define regNBIO_LCLK_DEEPSLEEP_MASK_BASE_IDX                                                            5
+#define regNBIF_DS_CTRL_USBCLK                                                                          0xe891
+#define regNBIF_DS_CTRL_USBCLK_BASE_IDX                                                                 5
+#define regNBIF_SHUB_TODET_CLIENT_MISC3                                                                 0xe897
+#define regNBIF_SHUB_TODET_CLIENT_MISC3_BASE_IDX                                                        5
+#define regNBIF_SHUB_TODET_CTRL                                                                         0xe898
+#define regNBIF_SHUB_TODET_CTRL_BASE_IDX                                                                5
+#define regNBIF_SHUB_TODET_CLIENT_CTRL                                                                  0xe899
+#define regNBIF_SHUB_TODET_CLIENT_CTRL_BASE_IDX                                                         5
+#define regNBIF_SHUB_TODET_CLIENT_STATUS                                                                0xe89a
+#define regNBIF_SHUB_TODET_CLIENT_STATUS_BASE_IDX                                                       5
+#define regNBIF_SHUB_TODET_SYNCFLOOD_CTRL                                                               0xe89b
+#define regNBIF_SHUB_TODET_SYNCFLOOD_CTRL_BASE_IDX                                                      5
+#define regNBIF_SHUB_TODET_CLIENT_CTRL2                                                                 0xe89c
+#define regNBIF_SHUB_TODET_CLIENT_CTRL2_BASE_IDX                                                        5
+#define regNBIF_SHUB_TODET_CLIENT_STATUS2                                                               0xe89d
+#define regNBIF_SHUB_TODET_CLIENT_STATUS2_BASE_IDX                                                      5
+#define regNBIF_SHUB_TODET_SYNCFLOOD_CTRL2                                                              0xe89e
+#define regNBIF_SHUB_TODET_SYNCFLOOD_CTRL2_BASE_IDX                                                     5
+#define regDMA_SDP_PORT_DEBUG                                                                           0xe8a0
+#define regDMA_SDP_PORT_DEBUG_BASE_IDX                                                                  5
+#define regSDP_PORT_MONITOR_CONTROL                                                                     0xe8a2
+#define regSDP_PORT_MONITOR_CONTROL_BASE_IDX                                                            5
+#define regSDP_PORT_MONITOR_ADDRESS0                                                                    0xe8a3
+#define regSDP_PORT_MONITOR_ADDRESS0_BASE_IDX                                                           5
+#define regSDP_PORT_MONITOR_ADDRESS1                                                                    0xe8a4
+#define regSDP_PORT_MONITOR_ADDRESS1_BASE_IDX                                                           5
+#define regSDP_PORT_MONITOR_UNITID                                                                      0xe8a5
+#define regSDP_PORT_MONITOR_UNITID_BASE_IDX                                                             5
+#define regSDP_PORT_MONITOR_INFO0                                                                       0xe8a6
+#define regSDP_PORT_MONITOR_INFO0_BASE_IDX                                                              5
+#define regSDP_PORT_MONITOR_INFO1                                                                       0xe8a7
+#define regSDP_PORT_MONITOR_INFO1_BASE_IDX                                                              5
+#define regSDP_PORT_MONITOR_INFO2                                                                       0xe8a8
+#define regSDP_PORT_MONITOR_INFO2_BASE_IDX                                                              5
+#define regSDP_PORT_MONITOR_INFO3                                                                       0xe8a9
+#define regSDP_PORT_MONITOR_INFO3_BASE_IDX                                                              5
+#define regSDP_PORT_MONITOR_INFO4                                                                       0xe8aa
+#define regSDP_PORT_MONITOR_INFO4_BASE_IDX                                                              5
+#define regBIFC_BME_ERR_LOG_HB                                                                          0xe8ab
+#define regBIFC_BME_ERR_LOG_HB_BASE_IDX                                                                 5
+#define regBIFC_GFX_INT_MONITOR_MASK                                                                    0xe8ad
+#define regBIFC_GFX_INT_MONITOR_MASK_BASE_IDX                                                           5
+#define regBIFC_GFX_INT_MONITOR_STS                                                                     0xe8ae
+#define regBIFC_GFX_INT_MONITOR_STS_BASE_IDX                                                            5
+#define regBIFC_GFX_INT_MONITOR_CTRL                                                                    0xe8af
+#define regBIFC_GFX_INT_MONITOR_CTRL_BASE_IDX                                                           5
+#define regNBIF_FLUSH_CTRL                                                                              0xe8b1
+#define regNBIF_FLUSH_CTRL_BASE_IDX                                                                     5
+#define regNBIF_GUI_FLUSH_CNTL                                                                          0xe8b3
+#define regNBIF_GUI_FLUSH_CNTL_BASE_IDX                                                                 5
+#define regBIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC                                                            0xe8c0
+#define regBIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC_BASE_IDX                                                   5
+#define regBIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC                                                            0xe8c1
+#define regBIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC_BASE_IDX                                                   5
+#define regBIFC_GMI_SDP_REQ_POOLCRED_ALLOC                                                              0xe8c2
+#define regBIFC_GMI_SDP_REQ_POOLCRED_ALLOC_BASE_IDX                                                     5
+#define regBIFC_GMI_SDP_DAT_POOLCRED_ALLOC                                                              0xe8c3
+#define regBIFC_GMI_SDP_DAT_POOLCRED_ALLOC_BASE_IDX                                                     5
+#define regBIFC_GMI_SST_RDRSP_POOLCRED_ALLOC                                                            0xe8c4
+#define regBIFC_GMI_SST_RDRSP_POOLCRED_ALLOC_BASE_IDX                                                   5
+#define regBIFC_GMI_SST_WRRSP_POOLCRED_ALLOC                                                            0xe8c5
+#define regBIFC_GMI_SST_WRRSP_POOLCRED_ALLOC_BASE_IDX                                                   5
+#define regDISCON_HYSTERESIS_HEAD_CTRL                                                                  0xe8c6
+#define regDISCON_HYSTERESIS_HEAD_CTRL_BASE_IDX                                                         5
+#define regBIFC_GSI_SDP_REQ_POOLCRED_ALLOC                                                              0xe8c7
+#define regBIFC_GSI_SDP_REQ_POOLCRED_ALLOC_BASE_IDX                                                     5
+#define regBIFC_GSI_SDP_DAT_POOLCRED_ALLOC                                                              0xe8c8
+#define regBIFC_GSI_SDP_DAT_POOLCRED_ALLOC_BASE_IDX                                                     5
+#define regBIFC_MCA_SMN_CTRL0                                                                           0xe8cb
+#define regBIFC_MCA_SMN_CTRL0_BASE_IDX                                                                  5
+#define regBIFC_MCTP_SMN_CTRL0                                                                          0xe8ce
+#define regBIFC_MCTP_SMN_CTRL0_BASE_IDX                                                                 5
+#define regNBIF_REGIF_DEBUG_COUNTER_CTRL                                                                0xe8cf
+#define regNBIF_REGIF_DEBUG_COUNTER_CTRL_BASE_IDX                                                       5
+#define regBIFC_EARLY_WAKEUP_CNTL                                                                       0xe8d2
+#define regBIFC_EARLY_WAKEUP_CNTL_BASE_IDX                                                              5
+#define regBIFC_PERF_CNT_MMIO_RD_H16BIT                                                                 0xe8f0
+#define regBIFC_PERF_CNT_MMIO_RD_H16BIT_BASE_IDX                                                        5
+#define regBIFC_PERF_CNT_MMIO_WR_H16BIT                                                                 0xe8f1
+#define regBIFC_PERF_CNT_MMIO_WR_H16BIT_BASE_IDX                                                        5
+#define regBIF_MISC_BIFC_PERF_CNT_DMA_RD_H16BIT                                                         0xe8f2
+#define regBIF_MISC_BIFC_PERF_CNT_DMA_RD_H16BIT_BASE_IDX                                                5
+#define regBIF_MISC_BIFC_PERF_CNT_DMA_WR_H16BIT                                                         0xe8f3
+#define regBIF_MISC_BIFC_PERF_CNT_DMA_WR_H16BIT_BASE_IDX                                                5
+#define regBIF_MISC_NBIF_PERF_COM_COUNT_ENABLE                                                          0xe8f4
+#define regBIF_MISC_NBIF_PERF_COM_COUNT_ENABLE_BASE_IDX                                                 5
+#define regBIF_MISC_NBIF_SDP_PERF_CNT_FSM                                                               0xe8f5
+#define regBIF_MISC_NBIF_SDP_PERF_CNT_FSM_BASE_IDX                                                      5
+#define regBIF_MISC_NBIF_SDP_PERF_COUNTER                                                               0xe8f6
+#define regBIF_MISC_NBIF_SDP_PERF_COUNTER_BASE_IDX                                                      5
+#define regBIF_MISC_NBIF_SDP_PERF_CNT_0_VALUE_L32BIT                                                    0xe8f7
+#define regBIF_MISC_NBIF_SDP_PERF_CNT_0_VALUE_L32BIT_BASE_IDX                                           5
+#define regBIF_MISC_NBIF_SDP_PERF_CNT_1_VALUE_L32BIT                                                    0xe8f8
+#define regBIF_MISC_NBIF_SDP_PERF_CNT_1_VALUE_L32BIT_BASE_IDX                                           5
+#define regBIF_MISC_NBIF_SDP_PERF_CNT_2_VALUE_L32BIT                                                    0xe8f9
+#define regBIF_MISC_NBIF_SDP_PERF_CNT_2_VALUE_L32BIT_BASE_IDX                                           5
+#define regBIF_MISC_NBIF_SDP_PERF_CNT_3_VALUE_L32BIT                                                    0xe8fa
+#define regBIF_MISC_NBIF_SDP_PERF_CNT_3_VALUE_L32BIT_BASE_IDX                                           5
+#define regBIF_MISC_NBIF_SDP_PERF_CNT_0_VALUE_H16BIT                                                    0xe8fb
+#define regBIF_MISC_NBIF_SDP_PERF_CNT_0_VALUE_H16BIT_BASE_IDX                                           5
+#define regBIF_MISC_NBIF_SDP_PERF_CNT_1_VALUE_H16BIT                                                    0xe8fc
+#define regBIF_MISC_NBIF_SDP_PERF_CNT_1_VALUE_H16BIT_BASE_IDX                                           5
+#define regBIF_MISC_NBIF_SDP_PERF_CNT_2_VALUE_H16BIT                                                    0xe8fd
+#define regBIF_MISC_NBIF_SDP_PERF_CNT_2_VALUE_H16BIT_BASE_IDX                                           5
+#define regBIF_MISC_NBIF_SDP_PERF_CNT_3_VALUE_H16BIT                                                    0xe8fe
+#define regBIF_MISC_NBIF_SDP_PERF_CNT_3_VALUE_H16BIT_BASE_IDX                                           5
+#define regBIF_MISC_NBIF_BX_PERF_CNT_FSM                                                                0xe8ff
+#define regBIF_MISC_NBIF_BX_PERF_CNT_FSM_BASE_IDX                                                       5
+#define regNBIF_TDISP_ENTER_ERR_CNTL                                                                    0xe905
+#define regNBIF_TDISP_ENTER_ERR_CNTL_BASE_IDX                                                           5
+#define regBIF_UNITID_ERR_LOG                                                                           0xe906
+#define regBIF_UNITID_ERR_LOG_BASE_IDX                                                                  5
+#define regNBIF_COM_COUNT_VALUE                                                                         0xe908
+#define regNBIF_COM_COUNT_VALUE_BASE_IDX                                                                5
+#define regNBIF_ERREREVNT_SIDEBAND_RAS_V1_CTRL                                                          0xe909
+#define regNBIF_ERREREVNT_SIDEBAND_RAS_V1_CTRL_BASE_IDX                                                 5
+#define regNBIF_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL                                                   0xe90a
+#define regNBIF_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL_BASE_IDX                                          5
+#define regBIF_AER_CNTL                                                                                 0xe92c
+#define regBIF_AER_CNTL_BASE_IDX                                                                        5
+#define regNBIF_IDE_INFO_CNTL                                                                           0xe92d
+#define regNBIF_IDE_INFO_CNTL_BASE_IDX                                                                  5
+#define regBIFC_EXP_MISC_CTRL0                                                                          0xe9c0
+#define regBIFC_EXP_MISC_CTRL0_BASE_IDX                                                                 5
+#define regSECOND_HDP_MEM_FLUSH_CNTL_PF                                                                 0xea80
+#define regSECOND_HDP_MEM_FLUSH_CNTL_PF_BASE_IDX                                                        5
+#define regSECOND_HDP_MEM_FLUSH_CNTL_VF0                                                                0xea81
+#define regSECOND_HDP_MEM_FLUSH_CNTL_VF0_BASE_IDX                                                       5
+#define regSECOND_HDP_MEM_FLUSH_CNTL_VF1                                                                0xea82
+#define regSECOND_HDP_MEM_FLUSH_CNTL_VF1_BASE_IDX                                                       5
+#define regSECOND_HDP_MEM_FLUSH_CNTL_VF2                                                                0xea83
+#define regSECOND_HDP_MEM_FLUSH_CNTL_VF2_BASE_IDX                                                       5
+#define regSECOND_HDP_MEM_FLUSH_CNTL_VF3                                                                0xea84
+#define regSECOND_HDP_MEM_FLUSH_CNTL_VF3_BASE_IDX                                                       5
+#define regSECOND_HDP_MEM_FLUSH_CNTL_VF4                                                                0xea85
+#define regSECOND_HDP_MEM_FLUSH_CNTL_VF4_BASE_IDX                                                       5
+#define regSECOND_HDP_MEM_FLUSH_CNTL_VF5                                                                0xea86
+#define regSECOND_HDP_MEM_FLUSH_CNTL_VF5_BASE_IDX                                                       5
+#define regSECOND_HDP_MEM_FLUSH_CNTL_VF6                                                                0xea87
+#define regSECOND_HDP_MEM_FLUSH_CNTL_VF6_BASE_IDX                                                       5
+#define regSECOND_HDP_MEM_FLUSH_CNTL_VF7                                                                0xea88
+#define regSECOND_HDP_MEM_FLUSH_CNTL_VF7_BASE_IDX                                                       5
+#define regSECOND_HDP_REG_FLUSH_CNTL_PF                                                                 0xea89
+#define regSECOND_HDP_REG_FLUSH_CNTL_PF_BASE_IDX                                                        5
+#define regSECOND_HDP_REG_FLUSH_CNTL_VF0                                                                0xea8a
+#define regSECOND_HDP_REG_FLUSH_CNTL_VF0_BASE_IDX                                                       5
+#define regSECOND_HDP_REG_FLUSH_CNTL_VF1                                                                0xea8b
+#define regSECOND_HDP_REG_FLUSH_CNTL_VF1_BASE_IDX                                                       5
+#define regSECOND_HDP_REG_FLUSH_CNTL_VF2                                                                0xea8c
+#define regSECOND_HDP_REG_FLUSH_CNTL_VF2_BASE_IDX                                                       5
+#define regSECOND_HDP_REG_FLUSH_CNTL_VF3                                                                0xea8d
+#define regSECOND_HDP_REG_FLUSH_CNTL_VF3_BASE_IDX                                                       5
+#define regSECOND_HDP_REG_FLUSH_CNTL_VF4                                                                0xea8e
+#define regSECOND_HDP_REG_FLUSH_CNTL_VF4_BASE_IDX                                                       5
+#define regSECOND_HDP_REG_FLUSH_CNTL_VF5                                                                0xea8f
+#define regSECOND_HDP_REG_FLUSH_CNTL_VF5_BASE_IDX                                                       5
+#define regSECOND_HDP_REG_FLUSH_CNTL_VF6                                                                0xea90
+#define regSECOND_HDP_REG_FLUSH_CNTL_VF6_BASE_IDX                                                       5
+#define regSECOND_HDP_REG_FLUSH_CNTL_VF7                                                                0xea91
+#define regSECOND_HDP_REG_FLUSH_CNTL_VF7_BASE_IDX                                                       5
+#define regGPU_HDP_FLUSH_GFX_FW                                                                         0xf4c0
+#define regGPU_HDP_FLUSH_GFX_FW_BASE_IDX                                                                5
+#define regNBIF_RRMT_CNTL                                                                               0xf500
+#define regNBIF_RRMT_CNTL_BASE_IDX                                                                      5
+#define regRRMT_NBIF_MISC_REG1                                                                          0xf501
+#define regRRMT_NBIF_MISC_REG1_BASE_IDX                                                                 5
+#define regRRMT_LUT_INDEX                                                                               0xf502
+#define regRRMT_LUT_INDEX_BASE_IDX                                                                      5
+#define regRRMT_LUT_DATA                                                                                0xf503
+#define regRRMT_LUT_DATA_BASE_IDX                                                                       5
+
+
+// addressBlock: nbif0_nbif0_bif_misc_pfvf_dev0_epf0_bif_misc_pfvf_regblk
+// base address: 0x10100000
+#define regBIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0                                                 0xf600
+#define regBIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0_BASE_IDX                                        5
+#define regBIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1                                                 0xf601
+#define regBIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1_BASE_IDX                                        5
+#define regBIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2                                                 0xf602
+#define regBIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2_BASE_IDX                                        5
+#define regBIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3                                                 0xf603
+#define regBIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3_BASE_IDX                                        5
+#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0                                             0xf604
+#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0_BASE_IDX                                    5
+#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1                                             0xf605
+#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1_BASE_IDX                                    5
+#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2                                             0xf606
+#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2_BASE_IDX                                    5
+#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3                                             0xf607
+#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3_BASE_IDX                                    5
+#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0                                          0xf608
+#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0_BASE_IDX                                 5
+#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1                                          0xf609
+#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1_BASE_IDX                                 5
+#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2                                          0xf60a
+#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2_BASE_IDX                                 5
+#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3                                          0xf60b
+#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3_BASE_IDX                                 5
+#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0                                             0xf60c
+#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0_BASE_IDX                                    5
+#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1                                             0xf60d
+#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1_BASE_IDX                                    5
+#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2                                             0xf60e
+#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2_BASE_IDX                                    5
+#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3                                             0xf60f
+#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3_BASE_IDX                                    5
+#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0                                                 0xf610
+#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0_BASE_IDX                                        5
+#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1                                                 0xf611
+#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1_BASE_IDX                                        5
+#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2                                                 0xf612
+#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2_BASE_IDX                                        5
+#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3                                                 0xf613
+#define regBIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3_BASE_IDX                                        5
+
+
+// addressBlock: nbif0_nbif0_bif_misc_pfvf_dev0_epf1_bif_misc_pfvf_regblk
+// base address: 0x10100000
+#define regBIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0                                                 0xf619
+#define regBIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0_BASE_IDX                                        5
+#define regBIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1                                                 0xf61a
+#define regBIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1_BASE_IDX                                        5
+#define regBIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2                                                 0xf61b
+#define regBIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2_BASE_IDX                                        5
+#define regBIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3                                                 0xf61c
+#define regBIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3_BASE_IDX                                        5
+#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0                                             0xf61d
+#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0_BASE_IDX                                    5
+#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1                                             0xf61e
+#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1_BASE_IDX                                    5
+#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2                                             0xf61f
+#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2_BASE_IDX                                    5
+#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3                                             0xf620
+#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3_BASE_IDX                                    5
+#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0                                          0xf621
+#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0_BASE_IDX                                 5
+#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1                                          0xf622
+#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1_BASE_IDX                                 5
+#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2                                          0xf623
+#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2_BASE_IDX                                 5
+#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3                                          0xf624
+#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3_BASE_IDX                                 5
+#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0                                             0xf625
+#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0_BASE_IDX                                    5
+#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1                                             0xf626
+#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1_BASE_IDX                                    5
+#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2                                             0xf627
+#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2_BASE_IDX                                    5
+#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3                                             0xf628
+#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3_BASE_IDX                                    5
+#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0                                                 0xf629
+#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0_BASE_IDX                                        5
+#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1                                                 0xf62a
+#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1_BASE_IDX                                        5
+#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2                                                 0xf62b
+#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2_BASE_IDX                                        5
+#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3                                                 0xf62c
+#define regBIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3_BASE_IDX                                        5
+
+
+// addressBlock: nbif0_nbif0_bif_trap_bif_trap_regblk
+// base address: 0x10100000
+#define regNBIF_TRAP_NP_STATUS                                                                          0x4000
+#define regNBIF_TRAP_NP_STATUS_BASE_IDX                                                                 5
+#define regNBIF_TRAP_NP_REQUEST0                                                                        0x4001
+#define regNBIF_TRAP_NP_REQUEST0_BASE_IDX                                                               5
+#define regNBIF_TRAP_NP_REQUEST1                                                                        0x4002
+#define regNBIF_TRAP_NP_REQUEST1_BASE_IDX                                                               5
+#define regNBIF_TRAP_NP_REQUEST2                                                                        0x4003
+#define regNBIF_TRAP_NP_REQUEST2_BASE_IDX                                                               5
+#define regNBIF_TRAP_NP_REQUEST3                                                                        0x4004
+#define regNBIF_TRAP_NP_REQUEST3_BASE_IDX                                                               5
+#define regNBIF_TRAP_NP_REQUEST4                                                                        0x4005
+#define regNBIF_TRAP_NP_REQUEST4_BASE_IDX                                                               5
+#define regNBIF_TRAP_NP_REQUEST5                                                                        0x4006
+#define regNBIF_TRAP_NP_REQUEST5_BASE_IDX                                                               5
+#define regNBIF_TRAP_NP_REQUEST6                                                                        0x4007
+#define regNBIF_TRAP_NP_REQUEST6_BASE_IDX                                                               5
+#define regNBIF_TRAP_NP_REQUEST_DATASTRB0                                                               0x4008
+#define regNBIF_TRAP_NP_REQUEST_DATASTRB0_BASE_IDX                                                      5
+#define regNBIF_TRAP_NP_REQUEST_DATASTRB1                                                               0x4009
+#define regNBIF_TRAP_NP_REQUEST_DATASTRB1_BASE_IDX                                                      5
+#define regNBIF_TRAP_NP_REQUEST_DATASTRB2                                                               0x400a
+#define regNBIF_TRAP_NP_REQUEST_DATASTRB2_BASE_IDX                                                      5
+#define regNBIF_TRAP_NP_REQUEST_DATASTRB3                                                               0x400b
+#define regNBIF_TRAP_NP_REQUEST_DATASTRB3_BASE_IDX                                                      5
+#define regNBIF_TRAP_NP_REQUEST_DATASTRB4                                                               0x400c
+#define regNBIF_TRAP_NP_REQUEST_DATASTRB4_BASE_IDX                                                      5
+#define regNBIF_TRAP_NP_REQUEST_DATASTRB5                                                               0x400d
+#define regNBIF_TRAP_NP_REQUEST_DATASTRB5_BASE_IDX                                                      5
+#define regNBIF_TRAP_NP_REQUEST_DATASTRB6                                                               0x400e
+#define regNBIF_TRAP_NP_REQUEST_DATASTRB6_BASE_IDX                                                      5
+#define regNBIF_TRAP_NP_REQUEST_DATASTRB7                                                               0x400f
+#define regNBIF_TRAP_NP_REQUEST_DATASTRB7_BASE_IDX                                                      5
+#define regNBIF_TRAP_NP_REQUEST_DATA0                                                                   0x4010
+#define regNBIF_TRAP_NP_REQUEST_DATA0_BASE_IDX                                                          5
+#define regNBIF_TRAP_NP_REQUEST_DATA1                                                                   0x4011
+#define regNBIF_TRAP_NP_REQUEST_DATA1_BASE_IDX                                                          5
+#define regNBIF_TRAP_NP_REQUEST_DATA2                                                                   0x4012
+#define regNBIF_TRAP_NP_REQUEST_DATA2_BASE_IDX                                                          5
+#define regNBIF_TRAP_NP_REQUEST_DATA3                                                                   0x4013
+#define regNBIF_TRAP_NP_REQUEST_DATA3_BASE_IDX                                                          5
+#define regNBIF_TRAP_NP_REQUEST_DATA4                                                                   0x4014
+#define regNBIF_TRAP_NP_REQUEST_DATA4_BASE_IDX                                                          5
+#define regNBIF_TRAP_NP_REQUEST_DATA5                                                                   0x4015
+#define regNBIF_TRAP_NP_REQUEST_DATA5_BASE_IDX                                                          5
+#define regNBIF_TRAP_NP_REQUEST_DATA6                                                                   0x4016
+#define regNBIF_TRAP_NP_REQUEST_DATA6_BASE_IDX                                                          5
+#define regNBIF_TRAP_NP_REQUEST_DATA7                                                                   0x4017
+#define regNBIF_TRAP_NP_REQUEST_DATA7_BASE_IDX                                                          5
+#define regNBIF_TRAP_NP_REQUEST_DATA8                                                                   0x4018
+#define regNBIF_TRAP_NP_REQUEST_DATA8_BASE_IDX                                                          5
+#define regNBIF_TRAP_NP_REQUEST_DATA9                                                                   0x4019
+#define regNBIF_TRAP_NP_REQUEST_DATA9_BASE_IDX                                                          5
+#define regNBIF_TRAP_NP_REQUEST_DATA10                                                                  0x401a
+#define regNBIF_TRAP_NP_REQUEST_DATA10_BASE_IDX                                                         5
+#define regNBIF_TRAP_NP_REQUEST_DATA11                                                                  0x401b
+#define regNBIF_TRAP_NP_REQUEST_DATA11_BASE_IDX                                                         5
+#define regNBIF_TRAP_NP_REQUEST_DATA12                                                                  0x401c
+#define regNBIF_TRAP_NP_REQUEST_DATA12_BASE_IDX                                                         5
+#define regNBIF_TRAP_NP_REQUEST_DATA13                                                                  0x401d
+#define regNBIF_TRAP_NP_REQUEST_DATA13_BASE_IDX                                                         5
+#define regNBIF_TRAP_NP_REQUEST_DATA14                                                                  0x401e
+#define regNBIF_TRAP_NP_REQUEST_DATA14_BASE_IDX                                                         5
+#define regNBIF_TRAP_NP_REQUEST_DATA15                                                                  0x401f
+#define regNBIF_TRAP_NP_REQUEST_DATA15_BASE_IDX                                                         5
+#define regNBIF_TRAP_NP_REQUEST_DATA16                                                                  0x4020
+#define regNBIF_TRAP_NP_REQUEST_DATA16_BASE_IDX                                                         5
+#define regNBIF_TRAP_NP_REQUEST_DATA17                                                                  0x4021
+#define regNBIF_TRAP_NP_REQUEST_DATA17_BASE_IDX                                                         5
+#define regNBIF_TRAP_NP_REQUEST_DATA18                                                                  0x4022
+#define regNBIF_TRAP_NP_REQUEST_DATA18_BASE_IDX                                                         5
+#define regNBIF_TRAP_NP_REQUEST_DATA19                                                                  0x4023
+#define regNBIF_TRAP_NP_REQUEST_DATA19_BASE_IDX                                                         5
+#define regNBIF_TRAP_NP_REQUEST_DATA20                                                                  0x4024
+#define regNBIF_TRAP_NP_REQUEST_DATA20_BASE_IDX                                                         5
+#define regNBIF_TRAP_NP_REQUEST_DATA21                                                                  0x4025
+#define regNBIF_TRAP_NP_REQUEST_DATA21_BASE_IDX                                                         5
+#define regNBIF_TRAP_NP_REQUEST_DATA22                                                                  0x4026
+#define regNBIF_TRAP_NP_REQUEST_DATA22_BASE_IDX                                                         5
+#define regNBIF_TRAP_NP_REQUEST_DATA23                                                                  0x4027
+#define regNBIF_TRAP_NP_REQUEST_DATA23_BASE_IDX                                                         5
+#define regNBIF_TRAP_NP_REQUEST_DATA24                                                                  0x4028
+#define regNBIF_TRAP_NP_REQUEST_DATA24_BASE_IDX                                                         5
+#define regNBIF_TRAP_NP_REQUEST_DATA25                                                                  0x4029
+#define regNBIF_TRAP_NP_REQUEST_DATA25_BASE_IDX                                                         5
+#define regNBIF_TRAP_NP_REQUEST_DATA26                                                                  0x402a
+#define regNBIF_TRAP_NP_REQUEST_DATA26_BASE_IDX                                                         5
+#define regNBIF_TRAP_NP_REQUEST_DATA27                                                                  0x402b
+#define regNBIF_TRAP_NP_REQUEST_DATA27_BASE_IDX                                                         5
+#define regNBIF_TRAP_NP_REQUEST_DATA28                                                                  0x402c
+#define regNBIF_TRAP_NP_REQUEST_DATA28_BASE_IDX                                                         5
+#define regNBIF_TRAP_NP_REQUEST_DATA29                                                                  0x402d
+#define regNBIF_TRAP_NP_REQUEST_DATA29_BASE_IDX                                                         5
+#define regNBIF_TRAP_NP_REQUEST_DATA30                                                                  0x402e
+#define regNBIF_TRAP_NP_REQUEST_DATA30_BASE_IDX                                                         5
+#define regNBIF_TRAP_NP_REQUEST_DATA31                                                                  0x402f
+#define regNBIF_TRAP_NP_REQUEST_DATA31_BASE_IDX                                                         5
+#define regNBIF_TRAP_NP_REQUEST_DATA32                                                                  0x4030
+#define regNBIF_TRAP_NP_REQUEST_DATA32_BASE_IDX                                                         5
+#define regNBIF_TRAP_NP_REQUEST_DATA33                                                                  0x4031
+#define regNBIF_TRAP_NP_REQUEST_DATA33_BASE_IDX                                                         5
+#define regNBIF_TRAP_NP_REQUEST_DATA34                                                                  0x4032
+#define regNBIF_TRAP_NP_REQUEST_DATA34_BASE_IDX                                                         5
+#define regNBIF_TRAP_NP_REQUEST_DATA35                                                                  0x4033
+#define regNBIF_TRAP_NP_REQUEST_DATA35_BASE_IDX                                                         5
+#define regNBIF_TRAP_NP_REQUEST_DATA36                                                                  0x4034
+#define regNBIF_TRAP_NP_REQUEST_DATA36_BASE_IDX                                                         5
+#define regNBIF_TRAP_NP_REQUEST_DATA37                                                                  0x4035
+#define regNBIF_TRAP_NP_REQUEST_DATA37_BASE_IDX                                                         5
+#define regNBIF_TRAP_NP_REQUEST_DATA38                                                                  0x4036
+#define regNBIF_TRAP_NP_REQUEST_DATA38_BASE_IDX                                                         5
+#define regNBIF_TRAP_NP_REQUEST_DATA39                                                                  0x4037
+#define regNBIF_TRAP_NP_REQUEST_DATA39_BASE_IDX                                                         5
+#define regNBIF_TRAP_NP_REQUEST_DATA40                                                                  0x4038
+#define regNBIF_TRAP_NP_REQUEST_DATA40_BASE_IDX                                                         5
+#define regNBIF_TRAP_NP_REQUEST_DATA41                                                                  0x4039
+#define regNBIF_TRAP_NP_REQUEST_DATA41_BASE_IDX                                                         5
+#define regNBIF_TRAP_NP_REQUEST_DATA42                                                                  0x403a
+#define regNBIF_TRAP_NP_REQUEST_DATA42_BASE_IDX                                                         5
+#define regNBIF_TRAP_NP_REQUEST_DATA43                                                                  0x403b
+#define regNBIF_TRAP_NP_REQUEST_DATA43_BASE_IDX                                                         5
+#define regNBIF_TRAP_NP_REQUEST_DATA44                                                                  0x403c
+#define regNBIF_TRAP_NP_REQUEST_DATA44_BASE_IDX                                                         5
+#define regNBIF_TRAP_NP_REQUEST_DATA45                                                                  0x403d
+#define regNBIF_TRAP_NP_REQUEST_DATA45_BASE_IDX                                                         5
+#define regNBIF_TRAP_NP_REQUEST_DATA46                                                                  0x403e
+#define regNBIF_TRAP_NP_REQUEST_DATA46_BASE_IDX                                                         5
+#define regNBIF_TRAP_NP_REQUEST_DATA47                                                                  0x403f
+#define regNBIF_TRAP_NP_REQUEST_DATA47_BASE_IDX                                                         5
+#define regNBIF_TRAP_NP_REQUEST_DATA48                                                                  0x4040
+#define regNBIF_TRAP_NP_REQUEST_DATA48_BASE_IDX                                                         5
+#define regNBIF_TRAP_NP_REQUEST_DATA49                                                                  0x4041
+#define regNBIF_TRAP_NP_REQUEST_DATA49_BASE_IDX                                                         5
+#define regNBIF_TRAP_NP_REQUEST_DATA50                                                                  0x4042
+#define regNBIF_TRAP_NP_REQUEST_DATA50_BASE_IDX                                                         5
+#define regNBIF_TRAP_NP_REQUEST_DATA51                                                                  0x4043
+#define regNBIF_TRAP_NP_REQUEST_DATA51_BASE_IDX                                                         5
+#define regNBIF_TRAP_NP_REQUEST_DATA52                                                                  0x4044
+#define regNBIF_TRAP_NP_REQUEST_DATA52_BASE_IDX                                                         5
+#define regNBIF_TRAP_NP_REQUEST_DATA53                                                                  0x4045
+#define regNBIF_TRAP_NP_REQUEST_DATA53_BASE_IDX                                                         5
+#define regNBIF_TRAP_NP_REQUEST_DATA54                                                                  0x4046
+#define regNBIF_TRAP_NP_REQUEST_DATA54_BASE_IDX                                                         5
+#define regNBIF_TRAP_NP_REQUEST_DATA55                                                                  0x4047
+#define regNBIF_TRAP_NP_REQUEST_DATA55_BASE_IDX                                                         5
+#define regNBIF_TRAP_NP_REQUEST_DATA56                                                                  0x4048
+#define regNBIF_TRAP_NP_REQUEST_DATA56_BASE_IDX                                                         5
+#define regNBIF_TRAP_NP_REQUEST_DATA57                                                                  0x4049
+#define regNBIF_TRAP_NP_REQUEST_DATA57_BASE_IDX                                                         5
+#define regNBIF_TRAP_NP_REQUEST_DATA58                                                                  0x404a
+#define regNBIF_TRAP_NP_REQUEST_DATA58_BASE_IDX                                                         5
+#define regNBIF_TRAP_NP_REQUEST_DATA59                                                                  0x404b
+#define regNBIF_TRAP_NP_REQUEST_DATA59_BASE_IDX                                                         5
+#define regNBIF_TRAP_NP_REQUEST_DATA60                                                                  0x404c
+#define regNBIF_TRAP_NP_REQUEST_DATA60_BASE_IDX                                                         5
+#define regNBIF_TRAP_NP_REQUEST_DATA61                                                                  0x404d
+#define regNBIF_TRAP_NP_REQUEST_DATA61_BASE_IDX                                                         5
+#define regNBIF_TRAP_NP_REQUEST_DATA62                                                                  0x404e
+#define regNBIF_TRAP_NP_REQUEST_DATA62_BASE_IDX                                                         5
+#define regNBIF_TRAP_NP_REQUEST_DATA63                                                                  0x404f
+#define regNBIF_TRAP_NP_REQUEST_DATA63_BASE_IDX                                                         5
+#define regNBIF_TRAP_NP_RESPONSE_CONTROL                                                                0x4050
+#define regNBIF_TRAP_NP_RESPONSE_CONTROL_BASE_IDX                                                       5
+#define regNBIF_TRAP_NP_RESPONSE0                                                                       0x4051
+#define regNBIF_TRAP_NP_RESPONSE0_BASE_IDX                                                              5
+#define regNBIF_TRAP_NP_RESPONSE1                                                                       0x4052
+#define regNBIF_TRAP_NP_RESPONSE1_BASE_IDX                                                              5
+#define regNBIF_TRAP_NP_RESPONSE2                                                                       0x4053
+#define regNBIF_TRAP_NP_RESPONSE2_BASE_IDX                                                              5
+#define regNBIF_TRAP_NP_RESPONSE3                                                                       0x4054
+#define regNBIF_TRAP_NP_RESPONSE3_BASE_IDX                                                              5
+#define regNBIF_TRAP_NP_RESPONSE4                                                                       0x4055
+#define regNBIF_TRAP_NP_RESPONSE4_BASE_IDX                                                              5
+#define regNBIF_TRAP_NP_RESPONSE5                                                                       0x4056
+#define regNBIF_TRAP_NP_RESPONSE5_BASE_IDX                                                              5
+#define regNBIF_TRAP_NP_RESPONSE_DATA0                                                                  0x4057
+#define regNBIF_TRAP_NP_RESPONSE_DATA0_BASE_IDX                                                         5
+#define regNBIF_TRAP_NP_RESPONSE_DATA1                                                                  0x4058
+#define regNBIF_TRAP_NP_RESPONSE_DATA1_BASE_IDX                                                         5
+#define regNBIF_TRAP_NP_RESPONSE_DATA2                                                                  0x4059
+#define regNBIF_TRAP_NP_RESPONSE_DATA2_BASE_IDX                                                         5
+#define regNBIF_TRAP_NP_RESPONSE_DATA3                                                                  0x405a
+#define regNBIF_TRAP_NP_RESPONSE_DATA3_BASE_IDX                                                         5
+#define regNBIF_TRAP_NP_RESPONSE_DATA4                                                                  0x405b
+#define regNBIF_TRAP_NP_RESPONSE_DATA4_BASE_IDX                                                         5
+#define regNBIF_TRAP_NP_RESPONSE_DATA5                                                                  0x405c
+#define regNBIF_TRAP_NP_RESPONSE_DATA5_BASE_IDX                                                         5
+#define regNBIF_TRAP_NP_RESPONSE_DATA6                                                                  0x405d
+#define regNBIF_TRAP_NP_RESPONSE_DATA6_BASE_IDX                                                         5
+#define regNBIF_TRAP_NP_RESPONSE_DATA7                                                                  0x405e
+#define regNBIF_TRAP_NP_RESPONSE_DATA7_BASE_IDX                                                         5
+#define regNBIF_TRAP_NP_RESPONSE_DATA8                                                                  0x405f
+#define regNBIF_TRAP_NP_RESPONSE_DATA8_BASE_IDX                                                         5
+#define regNBIF_TRAP_NP_RESPONSE_DATA9                                                                  0x4060
+#define regNBIF_TRAP_NP_RESPONSE_DATA9_BASE_IDX                                                         5
+#define regNBIF_TRAP_NP_RESPONSE_DATA10                                                                 0x4061
+#define regNBIF_TRAP_NP_RESPONSE_DATA10_BASE_IDX                                                        5
+#define regNBIF_TRAP_NP_RESPONSE_DATA11                                                                 0x4062
+#define regNBIF_TRAP_NP_RESPONSE_DATA11_BASE_IDX                                                        5
+#define regNBIF_TRAP_NP_RESPONSE_DATA12                                                                 0x4063
+#define regNBIF_TRAP_NP_RESPONSE_DATA12_BASE_IDX                                                        5
+#define regNBIF_TRAP_NP_RESPONSE_DATA13                                                                 0x4064
+#define regNBIF_TRAP_NP_RESPONSE_DATA13_BASE_IDX                                                        5
+#define regNBIF_TRAP_NP_RESPONSE_DATA14                                                                 0x4065
+#define regNBIF_TRAP_NP_RESPONSE_DATA14_BASE_IDX                                                        5
+#define regNBIF_TRAP_NP_RESPONSE_DATA15                                                                 0x4066
+#define regNBIF_TRAP_NP_RESPONSE_DATA15_BASE_IDX                                                        5
+#define regNBIF_TRAP_NP_RESPONSE_DATA16                                                                 0x4067
+#define regNBIF_TRAP_NP_RESPONSE_DATA16_BASE_IDX                                                        5
+#define regNBIF_TRAP_NP_RESPONSE_DATA17                                                                 0x4068
+#define regNBIF_TRAP_NP_RESPONSE_DATA17_BASE_IDX                                                        5
+#define regNBIF_TRAP_NP_RESPONSE_DATA18                                                                 0x4069
+#define regNBIF_TRAP_NP_RESPONSE_DATA18_BASE_IDX                                                        5
+#define regNBIF_TRAP_NP_RESPONSE_DATA19                                                                 0x406a
+#define regNBIF_TRAP_NP_RESPONSE_DATA19_BASE_IDX                                                        5
+#define regNBIF_TRAP_NP_RESPONSE_DATA20                                                                 0x406b
+#define regNBIF_TRAP_NP_RESPONSE_DATA20_BASE_IDX                                                        5
+#define regNBIF_TRAP_NP_RESPONSE_DATA21                                                                 0x406c
+#define regNBIF_TRAP_NP_RESPONSE_DATA21_BASE_IDX                                                        5
+#define regNBIF_TRAP_NP_RESPONSE_DATA22                                                                 0x406d
+#define regNBIF_TRAP_NP_RESPONSE_DATA22_BASE_IDX                                                        5
+#define regNBIF_TRAP_NP_RESPONSE_DATA23                                                                 0x406e
+#define regNBIF_TRAP_NP_RESPONSE_DATA23_BASE_IDX                                                        5
+#define regNBIF_TRAP_NP_RESPONSE_DATA24                                                                 0x406f
+#define regNBIF_TRAP_NP_RESPONSE_DATA24_BASE_IDX                                                        5
+#define regNBIF_TRAP_NP_RESPONSE_DATA25                                                                 0x4070
+#define regNBIF_TRAP_NP_RESPONSE_DATA25_BASE_IDX                                                        5
+#define regNBIF_TRAP_NP_RESPONSE_DATA26                                                                 0x4071
+#define regNBIF_TRAP_NP_RESPONSE_DATA26_BASE_IDX                                                        5
+#define regNBIF_TRAP_NP_RESPONSE_DATA27                                                                 0x4072
+#define regNBIF_TRAP_NP_RESPONSE_DATA27_BASE_IDX                                                        5
+#define regNBIF_TRAP_NP_RESPONSE_DATA28                                                                 0x4073
+#define regNBIF_TRAP_NP_RESPONSE_DATA28_BASE_IDX                                                        5
+#define regNBIF_TRAP_NP_RESPONSE_DATA29                                                                 0x4074
+#define regNBIF_TRAP_NP_RESPONSE_DATA29_BASE_IDX                                                        5
+#define regNBIF_TRAP_NP_RESPONSE_DATA30                                                                 0x4075
+#define regNBIF_TRAP_NP_RESPONSE_DATA30_BASE_IDX                                                        5
+#define regNBIF_TRAP_NP_RESPONSE_DATA31                                                                 0x4076
+#define regNBIF_TRAP_NP_RESPONSE_DATA31_BASE_IDX                                                        5
+#define regNBIF_TRAP_NP_RESPONSE_DATA32                                                                 0x4077
+#define regNBIF_TRAP_NP_RESPONSE_DATA32_BASE_IDX                                                        5
+#define regNBIF_TRAP_NP_RESPONSE_DATA33                                                                 0x4078
+#define regNBIF_TRAP_NP_RESPONSE_DATA33_BASE_IDX                                                        5
+#define regNBIF_TRAP_NP_RESPONSE_DATA34                                                                 0x4079
+#define regNBIF_TRAP_NP_RESPONSE_DATA34_BASE_IDX                                                        5
+#define regNBIF_TRAP_NP_RESPONSE_DATA35                                                                 0x407a
+#define regNBIF_TRAP_NP_RESPONSE_DATA35_BASE_IDX                                                        5
+#define regNBIF_TRAP_NP_RESPONSE_DATA36                                                                 0x407b
+#define regNBIF_TRAP_NP_RESPONSE_DATA36_BASE_IDX                                                        5
+#define regNBIF_TRAP_NP_RESPONSE_DATA37                                                                 0x407c
+#define regNBIF_TRAP_NP_RESPONSE_DATA37_BASE_IDX                                                        5
+#define regNBIF_TRAP_NP_RESPONSE_DATA38                                                                 0x407d
+#define regNBIF_TRAP_NP_RESPONSE_DATA38_BASE_IDX                                                        5
+#define regNBIF_TRAP_NP_RESPONSE_DATA39                                                                 0x407e
+#define regNBIF_TRAP_NP_RESPONSE_DATA39_BASE_IDX                                                        5
+#define regNBIF_TRAP_NP_RESPONSE_DATA40                                                                 0x407f
+#define regNBIF_TRAP_NP_RESPONSE_DATA40_BASE_IDX                                                        5
+#define regNBIF_TRAP_NP_RESPONSE_DATA41                                                                 0x4080
+#define regNBIF_TRAP_NP_RESPONSE_DATA41_BASE_IDX                                                        5
+#define regNBIF_TRAP_NP_RESPONSE_DATA42                                                                 0x4081
+#define regNBIF_TRAP_NP_RESPONSE_DATA42_BASE_IDX                                                        5
+#define regNBIF_TRAP_NP_RESPONSE_DATA43                                                                 0x4082
+#define regNBIF_TRAP_NP_RESPONSE_DATA43_BASE_IDX                                                        5
+#define regNBIF_TRAP_NP_RESPONSE_DATA44                                                                 0x4083
+#define regNBIF_TRAP_NP_RESPONSE_DATA44_BASE_IDX                                                        5
+#define regNBIF_TRAP_NP_RESPONSE_DATA45                                                                 0x4084
+#define regNBIF_TRAP_NP_RESPONSE_DATA45_BASE_IDX                                                        5
+#define regNBIF_TRAP_NP_RESPONSE_DATA46                                                                 0x4085
+#define regNBIF_TRAP_NP_RESPONSE_DATA46_BASE_IDX                                                        5
+#define regNBIF_TRAP_NP_RESPONSE_DATA47                                                                 0x4086
+#define regNBIF_TRAP_NP_RESPONSE_DATA47_BASE_IDX                                                        5
+#define regNBIF_TRAP_NP_RESPONSE_DATA48                                                                 0x4087
+#define regNBIF_TRAP_NP_RESPONSE_DATA48_BASE_IDX                                                        5
+#define regNBIF_TRAP_NP_RESPONSE_DATA49                                                                 0x4088
+#define regNBIF_TRAP_NP_RESPONSE_DATA49_BASE_IDX                                                        5
+#define regNBIF_TRAP_NP_RESPONSE_DATA50                                                                 0x4089
+#define regNBIF_TRAP_NP_RESPONSE_DATA50_BASE_IDX                                                        5
+#define regNBIF_TRAP_NP_RESPONSE_DATA51                                                                 0x408a
+#define regNBIF_TRAP_NP_RESPONSE_DATA51_BASE_IDX                                                        5
+#define regNBIF_TRAP_NP_RESPONSE_DATA52                                                                 0x408b
+#define regNBIF_TRAP_NP_RESPONSE_DATA52_BASE_IDX                                                        5
+#define regNBIF_TRAP_NP_RESPONSE_DATA53                                                                 0x408c
+#define regNBIF_TRAP_NP_RESPONSE_DATA53_BASE_IDX                                                        5
+#define regNBIF_TRAP_NP_RESPONSE_DATA54                                                                 0x408d
+#define regNBIF_TRAP_NP_RESPONSE_DATA54_BASE_IDX                                                        5
+#define regNBIF_TRAP_NP_RESPONSE_DATA55                                                                 0x408e
+#define regNBIF_TRAP_NP_RESPONSE_DATA55_BASE_IDX                                                        5
+#define regNBIF_TRAP_NP_RESPONSE_DATA56                                                                 0x408f
+#define regNBIF_TRAP_NP_RESPONSE_DATA56_BASE_IDX                                                        5
+#define regNBIF_TRAP_NP_RESPONSE_DATA57                                                                 0x4090
+#define regNBIF_TRAP_NP_RESPONSE_DATA57_BASE_IDX                                                        5
+#define regNBIF_TRAP_NP_RESPONSE_DATA58                                                                 0x4091
+#define regNBIF_TRAP_NP_RESPONSE_DATA58_BASE_IDX                                                        5
+#define regNBIF_TRAP_NP_RESPONSE_DATA59                                                                 0x4092
+#define regNBIF_TRAP_NP_RESPONSE_DATA59_BASE_IDX                                                        5
+#define regNBIF_TRAP_NP_RESPONSE_DATA60                                                                 0x4093
+#define regNBIF_TRAP_NP_RESPONSE_DATA60_BASE_IDX                                                        5
+#define regNBIF_TRAP_NP_RESPONSE_DATA61                                                                 0x4094
+#define regNBIF_TRAP_NP_RESPONSE_DATA61_BASE_IDX                                                        5
+#define regNBIF_TRAP_NP_RESPONSE_DATA62                                                                 0x4095
+#define regNBIF_TRAP_NP_RESPONSE_DATA62_BASE_IDX                                                        5
+#define regNBIF_TRAP_NP_RESPONSE_DATA63                                                                 0x4096
+#define regNBIF_TRAP_NP_RESPONSE_DATA63_BASE_IDX                                                        5
+#define regNBIF_TRAP_NP_0_CONTROL0                                                                      0x4097
+#define regNBIF_TRAP_NP_0_CONTROL0_BASE_IDX                                                             5
+#define regNBIF_TRAP_NP_0_ADDRESS_LO                                                                    0x4098
+#define regNBIF_TRAP_NP_0_ADDRESS_LO_BASE_IDX                                                           5
+#define regNBIF_TRAP_NP_0_ADDRESS_HI                                                                    0x4099
+#define regNBIF_TRAP_NP_0_ADDRESS_HI_BASE_IDX                                                           5
+#define regNBIF_TRAP_NP_0_COMMAND                                                                       0x409a
+#define regNBIF_TRAP_NP_0_COMMAND_BASE_IDX                                                              5
+#define regNBIF_TRAP_NP_0_ADDRESS_LO_MASK                                                               0x409b
+#define regNBIF_TRAP_NP_0_ADDRESS_LO_MASK_BASE_IDX                                                      5
+#define regNBIF_TRAP_NP_0_ADDRESS_HI_MASK                                                               0x409c
+#define regNBIF_TRAP_NP_0_ADDRESS_HI_MASK_BASE_IDX                                                      5
+#define regNBIF_TRAP_NP_0_COMMAND_MASK                                                                  0x409d
+#define regNBIF_TRAP_NP_0_COMMAND_MASK_BASE_IDX                                                         5
+#define regNBIF_TRAP_NP_1_CONTROL0                                                                      0x409e
+#define regNBIF_TRAP_NP_1_CONTROL0_BASE_IDX                                                             5
+#define regNBIF_TRAP_NP_1_ADDRESS_LO                                                                    0x409f
+#define regNBIF_TRAP_NP_1_ADDRESS_LO_BASE_IDX                                                           5
+#define regNBIF_TRAP_NP_1_ADDRESS_HI                                                                    0x40a0
+#define regNBIF_TRAP_NP_1_ADDRESS_HI_BASE_IDX                                                           5
+#define regNBIF_TRAP_NP_1_COMMAND                                                                       0x40a1
+#define regNBIF_TRAP_NP_1_COMMAND_BASE_IDX                                                              5
+#define regNBIF_TRAP_NP_1_ADDRESS_LO_MASK                                                               0x40a2
+#define regNBIF_TRAP_NP_1_ADDRESS_LO_MASK_BASE_IDX                                                      5
+#define regNBIF_TRAP_NP_1_ADDRESS_HI_MASK                                                               0x40a3
+#define regNBIF_TRAP_NP_1_ADDRESS_HI_MASK_BASE_IDX                                                      5
+#define regNBIF_TRAP_NP_1_COMMAND_MASK                                                                  0x40a4
+#define regNBIF_TRAP_NP_1_COMMAND_MASK_BASE_IDX                                                         5
+#define regNBIF_TRAP_NP_2_CONTROL0                                                                      0x40a5
+#define regNBIF_TRAP_NP_2_CONTROL0_BASE_IDX                                                             5
+#define regNBIF_TRAP_NP_2_ADDRESS_LO                                                                    0x40a6
+#define regNBIF_TRAP_NP_2_ADDRESS_LO_BASE_IDX                                                           5
+#define regNBIF_TRAP_NP_2_ADDRESS_HI                                                                    0x40a7
+#define regNBIF_TRAP_NP_2_ADDRESS_HI_BASE_IDX                                                           5
+#define regNBIF_TRAP_NP_2_COMMAND                                                                       0x40a8
+#define regNBIF_TRAP_NP_2_COMMAND_BASE_IDX                                                              5
+#define regNBIF_TRAP_NP_2_ADDRESS_LO_MASK                                                               0x40a9
+#define regNBIF_TRAP_NP_2_ADDRESS_LO_MASK_BASE_IDX                                                      5
+#define regNBIF_TRAP_NP_2_ADDRESS_HI_MASK                                                               0x40aa
+#define regNBIF_TRAP_NP_2_ADDRESS_HI_MASK_BASE_IDX                                                      5
+#define regNBIF_TRAP_NP_2_COMMAND_MASK                                                                  0x40ab
+#define regNBIF_TRAP_NP_2_COMMAND_MASK_BASE_IDX                                                         5
+#define regNBIF_TRAP_NP_3_CONTROL0                                                                      0x40ac
+#define regNBIF_TRAP_NP_3_CONTROL0_BASE_IDX                                                             5
+#define regNBIF_TRAP_NP_3_ADDRESS_LO                                                                    0x40ad
+#define regNBIF_TRAP_NP_3_ADDRESS_LO_BASE_IDX                                                           5
+#define regNBIF_TRAP_NP_3_ADDRESS_HI                                                                    0x40ae
+#define regNBIF_TRAP_NP_3_ADDRESS_HI_BASE_IDX                                                           5
+#define regNBIF_TRAP_NP_3_COMMAND                                                                       0x40af
+#define regNBIF_TRAP_NP_3_COMMAND_BASE_IDX                                                              5
+#define regNBIF_TRAP_NP_3_ADDRESS_LO_MASK                                                               0x40b0
+#define regNBIF_TRAP_NP_3_ADDRESS_LO_MASK_BASE_IDX                                                      5
+#define regNBIF_TRAP_NP_3_ADDRESS_HI_MASK                                                               0x40b1
+#define regNBIF_TRAP_NP_3_ADDRESS_HI_MASK_BASE_IDX                                                      5
+#define regNBIF_TRAP_NP_3_COMMAND_MASK                                                                  0x40b2
+#define regNBIF_TRAP_NP_3_COMMAND_MASK_BASE_IDX                                                         5
+#define regNBIF_TRAP_NP_4_CONTROL0                                                                      0x40b3
+#define regNBIF_TRAP_NP_4_CONTROL0_BASE_IDX                                                             5
+#define regNBIF_TRAP_NP_4_ADDRESS_LO                                                                    0x40b4
+#define regNBIF_TRAP_NP_4_ADDRESS_LO_BASE_IDX                                                           5
+#define regNBIF_TRAP_NP_4_ADDRESS_HI                                                                    0x40b5
+#define regNBIF_TRAP_NP_4_ADDRESS_HI_BASE_IDX                                                           5
+#define regNBIF_TRAP_NP_4_COMMAND                                                                       0x40b6
+#define regNBIF_TRAP_NP_4_COMMAND_BASE_IDX                                                              5
+#define regNBIF_TRAP_NP_4_ADDRESS_LO_MASK                                                               0x40b7
+#define regNBIF_TRAP_NP_4_ADDRESS_LO_MASK_BASE_IDX                                                      5
+#define regNBIF_TRAP_NP_4_ADDRESS_HI_MASK                                                               0x40b8
+#define regNBIF_TRAP_NP_4_ADDRESS_HI_MASK_BASE_IDX                                                      5
+#define regNBIF_TRAP_NP_4_COMMAND_MASK                                                                  0x40b9
+#define regNBIF_TRAP_NP_4_COMMAND_MASK_BASE_IDX                                                         5
+#define regNBIF_TRAP_NP_5_CONTROL0                                                                      0x40ba
+#define regNBIF_TRAP_NP_5_CONTROL0_BASE_IDX                                                             5
+#define regNBIF_TRAP_NP_5_ADDRESS_LO                                                                    0x40bb
+#define regNBIF_TRAP_NP_5_ADDRESS_LO_BASE_IDX                                                           5
+#define regNBIF_TRAP_NP_5_ADDRESS_HI                                                                    0x40bc
+#define regNBIF_TRAP_NP_5_ADDRESS_HI_BASE_IDX                                                           5
+#define regNBIF_TRAP_NP_5_COMMAND                                                                       0x40bd
+#define regNBIF_TRAP_NP_5_COMMAND_BASE_IDX                                                              5
+#define regNBIF_TRAP_NP_5_ADDRESS_LO_MASK                                                               0x40be
+#define regNBIF_TRAP_NP_5_ADDRESS_LO_MASK_BASE_IDX                                                      5
+#define regNBIF_TRAP_NP_5_ADDRESS_HI_MASK                                                               0x40bf
+#define regNBIF_TRAP_NP_5_ADDRESS_HI_MASK_BASE_IDX                                                      5
+#define regNBIF_TRAP_NP_5_COMMAND_MASK                                                                  0x40c0
+#define regNBIF_TRAP_NP_5_COMMAND_MASK_BASE_IDX                                                         5
+#define regNBIF_TRAP_NP_6_CONTROL0                                                                      0x40c1
+#define regNBIF_TRAP_NP_6_CONTROL0_BASE_IDX                                                             5
+#define regNBIF_TRAP_NP_6_ADDRESS_LO                                                                    0x40c2
+#define regNBIF_TRAP_NP_6_ADDRESS_LO_BASE_IDX                                                           5
+#define regNBIF_TRAP_NP_6_ADDRESS_HI                                                                    0x40c3
+#define regNBIF_TRAP_NP_6_ADDRESS_HI_BASE_IDX                                                           5
+#define regNBIF_TRAP_NP_6_COMMAND                                                                       0x40c4
+#define regNBIF_TRAP_NP_6_COMMAND_BASE_IDX                                                              5
+#define regNBIF_TRAP_NP_6_ADDRESS_LO_MASK                                                               0x40c5
+#define regNBIF_TRAP_NP_6_ADDRESS_LO_MASK_BASE_IDX                                                      5
+#define regNBIF_TRAP_NP_6_ADDRESS_HI_MASK                                                               0x40c6
+#define regNBIF_TRAP_NP_6_ADDRESS_HI_MASK_BASE_IDX                                                      5
+#define regNBIF_TRAP_NP_6_COMMAND_MASK                                                                  0x40c7
+#define regNBIF_TRAP_NP_6_COMMAND_MASK_BASE_IDX                                                         5
+#define regNBIF_TRAP_NP_7_CONTROL0                                                                      0x40c8
+#define regNBIF_TRAP_NP_7_CONTROL0_BASE_IDX                                                             5
+#define regNBIF_TRAP_NP_7_ADDRESS_LO                                                                    0x40c9
+#define regNBIF_TRAP_NP_7_ADDRESS_LO_BASE_IDX                                                           5
+#define regNBIF_TRAP_NP_7_ADDRESS_HI                                                                    0x40ca
+#define regNBIF_TRAP_NP_7_ADDRESS_HI_BASE_IDX                                                           5
+#define regNBIF_TRAP_NP_7_COMMAND                                                                       0x40cb
+#define regNBIF_TRAP_NP_7_COMMAND_BASE_IDX                                                              5
+#define regNBIF_TRAP_NP_7_ADDRESS_LO_MASK                                                               0x40cc
+#define regNBIF_TRAP_NP_7_ADDRESS_LO_MASK_BASE_IDX                                                      5
+#define regNBIF_TRAP_NP_7_ADDRESS_HI_MASK                                                               0x40cd
+#define regNBIF_TRAP_NP_7_ADDRESS_HI_MASK_BASE_IDX                                                      5
+#define regNBIF_TRAP_NP_7_COMMAND_MASK                                                                  0x40ce
+#define regNBIF_TRAP_NP_7_COMMAND_MASK_BASE_IDX                                                         5
+#define regNBIF_TRAP_NP_8_CONTROL0                                                                      0x40cf
+#define regNBIF_TRAP_NP_8_CONTROL0_BASE_IDX                                                             5
+#define regNBIF_TRAP_NP_8_ADDRESS_LO                                                                    0x40d0
+#define regNBIF_TRAP_NP_8_ADDRESS_LO_BASE_IDX                                                           5
+#define regNBIF_TRAP_NP_8_ADDRESS_HI                                                                    0x40d1
+#define regNBIF_TRAP_NP_8_ADDRESS_HI_BASE_IDX                                                           5
+#define regNBIF_TRAP_NP_8_COMMAND                                                                       0x40d2
+#define regNBIF_TRAP_NP_8_COMMAND_BASE_IDX                                                              5
+#define regNBIF_TRAP_NP_8_ADDRESS_LO_MASK                                                               0x40d3
+#define regNBIF_TRAP_NP_8_ADDRESS_LO_MASK_BASE_IDX                                                      5
+#define regNBIF_TRAP_NP_8_ADDRESS_HI_MASK                                                               0x40d4
+#define regNBIF_TRAP_NP_8_ADDRESS_HI_MASK_BASE_IDX                                                      5
+#define regNBIF_TRAP_NP_8_COMMAND_MASK                                                                  0x40d5
+#define regNBIF_TRAP_NP_8_COMMAND_MASK_BASE_IDX                                                         5
+#define regNBIF_TRAP_NP_9_CONTROL0                                                                      0x40d6
+#define regNBIF_TRAP_NP_9_CONTROL0_BASE_IDX                                                             5
+#define regNBIF_TRAP_NP_9_ADDRESS_LO                                                                    0x40d7
+#define regNBIF_TRAP_NP_9_ADDRESS_LO_BASE_IDX                                                           5
+#define regNBIF_TRAP_NP_9_ADDRESS_HI                                                                    0x40d8
+#define regNBIF_TRAP_NP_9_ADDRESS_HI_BASE_IDX                                                           5
+#define regNBIF_TRAP_NP_9_COMMAND                                                                       0x40d9
+#define regNBIF_TRAP_NP_9_COMMAND_BASE_IDX                                                              5
+#define regNBIF_TRAP_NP_9_ADDRESS_LO_MASK                                                               0x40da
+#define regNBIF_TRAP_NP_9_ADDRESS_LO_MASK_BASE_IDX                                                      5
+#define regNBIF_TRAP_NP_9_ADDRESS_HI_MASK                                                               0x40db
+#define regNBIF_TRAP_NP_9_ADDRESS_HI_MASK_BASE_IDX                                                      5
+#define regNBIF_TRAP_NP_9_COMMAND_MASK                                                                  0x40dc
+#define regNBIF_TRAP_NP_9_COMMAND_MASK_BASE_IDX                                                         5
+#define regNBIF_TRAP_NP_10_CONTROL0                                                                     0x40dd
+#define regNBIF_TRAP_NP_10_CONTROL0_BASE_IDX                                                            5
+#define regNBIF_TRAP_NP_10_ADDRESS_LO                                                                   0x40de
+#define regNBIF_TRAP_NP_10_ADDRESS_LO_BASE_IDX                                                          5
+#define regNBIF_TRAP_NP_10_ADDRESS_HI                                                                   0x40df
+#define regNBIF_TRAP_NP_10_ADDRESS_HI_BASE_IDX                                                          5
+#define regNBIF_TRAP_NP_10_COMMAND                                                                      0x40e0
+#define regNBIF_TRAP_NP_10_COMMAND_BASE_IDX                                                             5
+#define regNBIF_TRAP_NP_10_ADDRESS_LO_MASK                                                              0x40e1
+#define regNBIF_TRAP_NP_10_ADDRESS_LO_MASK_BASE_IDX                                                     5
+#define regNBIF_TRAP_NP_10_ADDRESS_HI_MASK                                                              0x40e2
+#define regNBIF_TRAP_NP_10_ADDRESS_HI_MASK_BASE_IDX                                                     5
+#define regNBIF_TRAP_NP_10_COMMAND_MASK                                                                 0x40e3
+#define regNBIF_TRAP_NP_10_COMMAND_MASK_BASE_IDX                                                        5
+#define regNBIF_TRAP_NP_11_CONTROL0                                                                     0x40e4
+#define regNBIF_TRAP_NP_11_CONTROL0_BASE_IDX                                                            5
+#define regNBIF_TRAP_NP_11_ADDRESS_LO                                                                   0x40e5
+#define regNBIF_TRAP_NP_11_ADDRESS_LO_BASE_IDX                                                          5
+#define regNBIF_TRAP_NP_11_ADDRESS_HI                                                                   0x40e6
+#define regNBIF_TRAP_NP_11_ADDRESS_HI_BASE_IDX                                                          5
+#define regNBIF_TRAP_NP_11_COMMAND                                                                      0x40e7
+#define regNBIF_TRAP_NP_11_COMMAND_BASE_IDX                                                             5
+#define regNBIF_TRAP_NP_11_ADDRESS_LO_MASK                                                              0x40e8
+#define regNBIF_TRAP_NP_11_ADDRESS_LO_MASK_BASE_IDX                                                     5
+#define regNBIF_TRAP_NP_11_ADDRESS_HI_MASK                                                              0x40e9
+#define regNBIF_TRAP_NP_11_ADDRESS_HI_MASK_BASE_IDX                                                     5
+#define regNBIF_TRAP_NP_11_COMMAND_MASK                                                                 0x40ea
+#define regNBIF_TRAP_NP_11_COMMAND_MASK_BASE_IDX                                                        5
+#define regNBIF_TRAP_NP_12_CONTROL0                                                                     0x40eb
+#define regNBIF_TRAP_NP_12_CONTROL0_BASE_IDX                                                            5
+#define regNBIF_TRAP_NP_12_ADDRESS_LO                                                                   0x40ec
+#define regNBIF_TRAP_NP_12_ADDRESS_LO_BASE_IDX                                                          5
+#define regNBIF_TRAP_NP_12_ADDRESS_HI                                                                   0x40ed
+#define regNBIF_TRAP_NP_12_ADDRESS_HI_BASE_IDX                                                          5
+#define regNBIF_TRAP_NP_12_COMMAND                                                                      0x40ee
+#define regNBIF_TRAP_NP_12_COMMAND_BASE_IDX                                                             5
+#define regNBIF_TRAP_NP_12_ADDRESS_LO_MASK                                                              0x40ef
+#define regNBIF_TRAP_NP_12_ADDRESS_LO_MASK_BASE_IDX                                                     5
+#define regNBIF_TRAP_NP_12_ADDRESS_HI_MASK                                                              0x40f0
+#define regNBIF_TRAP_NP_12_ADDRESS_HI_MASK_BASE_IDX                                                     5
+#define regNBIF_TRAP_NP_12_COMMAND_MASK                                                                 0x40f1
+#define regNBIF_TRAP_NP_12_COMMAND_MASK_BASE_IDX                                                        5
+#define regNBIF_TRAP_NP_13_CONTROL0                                                                     0x40f2
+#define regNBIF_TRAP_NP_13_CONTROL0_BASE_IDX                                                            5
+#define regNBIF_TRAP_NP_13_ADDRESS_LO                                                                   0x40f3
+#define regNBIF_TRAP_NP_13_ADDRESS_LO_BASE_IDX                                                          5
+#define regNBIF_TRAP_NP_13_ADDRESS_HI                                                                   0x40f4
+#define regNBIF_TRAP_NP_13_ADDRESS_HI_BASE_IDX                                                          5
+#define regNBIF_TRAP_NP_13_COMMAND                                                                      0x40f5
+#define regNBIF_TRAP_NP_13_COMMAND_BASE_IDX                                                             5
+#define regNBIF_TRAP_NP_13_ADDRESS_LO_MASK                                                              0x40f6
+#define regNBIF_TRAP_NP_13_ADDRESS_LO_MASK_BASE_IDX                                                     5
+#define regNBIF_TRAP_NP_13_ADDRESS_HI_MASK                                                              0x40f7
+#define regNBIF_TRAP_NP_13_ADDRESS_HI_MASK_BASE_IDX                                                     5
+#define regNBIF_TRAP_NP_13_COMMAND_MASK                                                                 0x40f8
+#define regNBIF_TRAP_NP_13_COMMAND_MASK_BASE_IDX                                                        5
+#define regNBIF_TRAP_NP_14_CONTROL0                                                                     0x40f9
+#define regNBIF_TRAP_NP_14_CONTROL0_BASE_IDX                                                            5
+#define regNBIF_TRAP_NP_14_ADDRESS_LO                                                                   0x40fa
+#define regNBIF_TRAP_NP_14_ADDRESS_LO_BASE_IDX                                                          5
+#define regNBIF_TRAP_NP_14_ADDRESS_HI                                                                   0x40fb
+#define regNBIF_TRAP_NP_14_ADDRESS_HI_BASE_IDX                                                          5
+#define regNBIF_TRAP_NP_14_COMMAND                                                                      0x40fc
+#define regNBIF_TRAP_NP_14_COMMAND_BASE_IDX                                                             5
+#define regNBIF_TRAP_NP_14_ADDRESS_LO_MASK                                                              0x40fd
+#define regNBIF_TRAP_NP_14_ADDRESS_LO_MASK_BASE_IDX                                                     5
+#define regNBIF_TRAP_NP_14_ADDRESS_HI_MASK                                                              0x40fe
+#define regNBIF_TRAP_NP_14_ADDRESS_HI_MASK_BASE_IDX                                                     5
+#define regNBIF_TRAP_NP_14_COMMAND_MASK                                                                 0x40ff
+#define regNBIF_TRAP_NP_14_COMMAND_MASK_BASE_IDX                                                        5
+#define regNBIF_TRAP_NP_15_CONTROL0                                                                     0x4100
+#define regNBIF_TRAP_NP_15_CONTROL0_BASE_IDX                                                            5
+#define regNBIF_TRAP_NP_15_ADDRESS_LO                                                                   0x4101
+#define regNBIF_TRAP_NP_15_ADDRESS_LO_BASE_IDX                                                          5
+#define regNBIF_TRAP_NP_15_ADDRESS_HI                                                                   0x4102
+#define regNBIF_TRAP_NP_15_ADDRESS_HI_BASE_IDX                                                          5
+#define regNBIF_TRAP_NP_15_COMMAND                                                                      0x4103
+#define regNBIF_TRAP_NP_15_COMMAND_BASE_IDX                                                             5
+#define regNBIF_TRAP_NP_15_ADDRESS_LO_MASK                                                              0x4104
+#define regNBIF_TRAP_NP_15_ADDRESS_LO_MASK_BASE_IDX                                                     5
+#define regNBIF_TRAP_NP_15_ADDRESS_HI_MASK                                                              0x4105
+#define regNBIF_TRAP_NP_15_ADDRESS_HI_MASK_BASE_IDX                                                     5
+#define regNBIF_TRAP_NP_15_COMMAND_MASK                                                                 0x4106
+#define regNBIF_TRAP_NP_15_COMMAND_MASK_BASE_IDX                                                        5
+#define regNBIF_TRAP_NP_S2_CONTROL0                                                                     0x4107
+#define regNBIF_TRAP_NP_S2_CONTROL0_BASE_IDX                                                            5
+#define regNBIF_TRAP_NP_S2_ADDRESS_LO                                                                   0x4108
+#define regNBIF_TRAP_NP_S2_ADDRESS_LO_BASE_IDX                                                          5
+#define regNBIF_TRAP_NP_S2_ADDRESS_HI                                                                   0x4109
+#define regNBIF_TRAP_NP_S2_ADDRESS_HI_BASE_IDX                                                          5
+#define regNBIF_TRAP_NP_S2_COMMAND                                                                      0x410a
+#define regNBIF_TRAP_NP_S2_COMMAND_BASE_IDX                                                             5
+#define regNBIF_TRAP_NP_S2_ADDRESS_LO_MASK                                                              0x410b
+#define regNBIF_TRAP_NP_S2_ADDRESS_LO_MASK_BASE_IDX                                                     5
+#define regNBIF_TRAP_NP_S2_ADDRESS_HI_MASK                                                              0x410c
+#define regNBIF_TRAP_NP_S2_ADDRESS_HI_MASK_BASE_IDX                                                     5
+#define regNBIF_TRAP_NP_S2_COMMAND_MASK                                                                 0x410d
+#define regNBIF_TRAP_NP_S2_COMMAND_MASK_BASE_IDX                                                        5
+
+
+// addressBlock: nbif0_nbif0_bif_ras_bif_ras_regblk
+// base address: 0x10100000
+#define regBIFL_RAS_CENTRAL_CNTL                                                                        0xe400
+#define regBIFL_RAS_CENTRAL_CNTL_BASE_IDX                                                               5
+#define regBIFL_RAS_CENTRAL_STATUS                                                                      0xe404
+#define regBIFL_RAS_CENTRAL_STATUS_BASE_IDX                                                             5
+#define regBIFL_RAS_LEAF0_CTRL                                                                          0xe408
+#define regBIFL_RAS_LEAF0_CTRL_BASE_IDX                                                                 5
+#define regBIFL_RAS_LEAF1_CTRL                                                                          0xe409
+#define regBIFL_RAS_LEAF1_CTRL_BASE_IDX                                                                 5
+#define regBIFL_RAS_LEAF2_CTRL                                                                          0xe40a
+#define regBIFL_RAS_LEAF2_CTRL_BASE_IDX                                                                 5
+#define regBIFL_RAS_LEAF3_CTRL                                                                          0xe40b
+#define regBIFL_RAS_LEAF3_CTRL_BASE_IDX                                                                 5
+#define regBIFL_RAS_LEAF4_CTRL                                                                          0xe40c
+#define regBIFL_RAS_LEAF4_CTRL_BASE_IDX                                                                 5
+#define regBIFL_RAS_LEAF5_CTRL                                                                          0xe40d
+#define regBIFL_RAS_LEAF5_CTRL_BASE_IDX                                                                 5
+#define regBIFL_RAS_LEAF6_CTRL                                                                          0xe40e
+#define regBIFL_RAS_LEAF6_CTRL_BASE_IDX                                                                 5
+#define regBIFL_RAS_LEAF7_CTRL                                                                          0xe40f
+#define regBIFL_RAS_LEAF7_CTRL_BASE_IDX                                                                 5
+#define regBIFL_RAS_LEAF8_CTRL                                                                          0xe410
+#define regBIFL_RAS_LEAF8_CTRL_BASE_IDX                                                                 5
+#define regBIFL_RAS_LEAF9_CTRL                                                                          0xe411
+#define regBIFL_RAS_LEAF9_CTRL_BASE_IDX                                                                 5
+#define regBIFL_RAS_LEAF10_CTRL                                                                         0xe412
+#define regBIFL_RAS_LEAF10_CTRL_BASE_IDX                                                                5
+#define regBIFL_RAS_LEAF11_CTRL                                                                         0xe413
+#define regBIFL_RAS_LEAF11_CTRL_BASE_IDX                                                                5
+#define regBIFL_RAS_LEAF12_CTRL                                                                         0xe414
+#define regBIFL_RAS_LEAF12_CTRL_BASE_IDX                                                                5
+#define regBIFL_RAS_LEAF13_CTRL                                                                         0xe415
+#define regBIFL_RAS_LEAF13_CTRL_BASE_IDX                                                                5
+#define regBIFL_RAS_LEAF14_CTRL                                                                         0xe416
+#define regBIFL_RAS_LEAF14_CTRL_BASE_IDX                                                                5
+#define regBIFL_RAS_LEAF15_CTRL                                                                         0xe417
+#define regBIFL_RAS_LEAF15_CTRL_BASE_IDX                                                                5
+#define regBIFL_RAS_LEAF16_CTRL                                                                         0xe418
+#define regBIFL_RAS_LEAF16_CTRL_BASE_IDX                                                                5
+#define regBIFL_RAS_LEAF17_CTRL                                                                         0xe419
+#define regBIFL_RAS_LEAF17_CTRL_BASE_IDX                                                                5
+#define regBIFL_RAS_LEAF18_CTRL                                                                         0xe41a
+#define regBIFL_RAS_LEAF18_CTRL_BASE_IDX                                                                5
+#define regBIFL_RAS_LEAF19_CTRL                                                                         0xe41b
+#define regBIFL_RAS_LEAF19_CTRL_BASE_IDX                                                                5
+#define regBIFL_RAS_LEAF2_MISC_CTRL                                                                     0xe42e
+#define regBIFL_RAS_LEAF2_MISC_CTRL_BASE_IDX                                                            5
+#define regBIFL_RAS_LEAF2_MISC_CTRL2                                                                    0xe42f
+#define regBIFL_RAS_LEAF2_MISC_CTRL2_BASE_IDX                                                           5
+#define regBIFL_RAS_LEAF_NTB_CTRL                                                                       0xe430
+#define regBIFL_RAS_LEAF_NTB_CTRL_BASE_IDX                                                              5
+#define regBIFL_RAS_LEAF0_STATUS                                                                        0xe431
+#define regBIFL_RAS_LEAF0_STATUS_BASE_IDX                                                               5
+#define regBIFL_RAS_LEAF1_STATUS                                                                        0xe432
+#define regBIFL_RAS_LEAF1_STATUS_BASE_IDX                                                               5
+#define regBIFL_RAS_LEAF2_STATUS                                                                        0xe433
+#define regBIFL_RAS_LEAF2_STATUS_BASE_IDX                                                               5
+#define regBIFL_RAS_LEAF3_STATUS                                                                        0xe434
+#define regBIFL_RAS_LEAF3_STATUS_BASE_IDX                                                               5
+#define regBIFL_RAS_LEAF4_STATUS                                                                        0xe435
+#define regBIFL_RAS_LEAF4_STATUS_BASE_IDX                                                               5
+#define regBIFL_RAS_LEAF5_STATUS                                                                        0xe436
+#define regBIFL_RAS_LEAF5_STATUS_BASE_IDX                                                               5
+#define regBIFL_RAS_LEAF6_STATUS                                                                        0xe437
+#define regBIFL_RAS_LEAF6_STATUS_BASE_IDX                                                               5
+#define regBIFL_RAS_LEAF7_STATUS                                                                        0xe438
+#define regBIFL_RAS_LEAF7_STATUS_BASE_IDX                                                               5
+#define regBIFL_RAS_LEAF8_STATUS                                                                        0xe439
+#define regBIFL_RAS_LEAF8_STATUS_BASE_IDX                                                               5
+#define regBIFL_RAS_LEAF9_STATUS                                                                        0xe43a
+#define regBIFL_RAS_LEAF9_STATUS_BASE_IDX                                                               5
+#define regBIFL_RAS_LEAF10_STATUS                                                                       0xe43b
+#define regBIFL_RAS_LEAF10_STATUS_BASE_IDX                                                              5
+#define regBIFL_RAS_LEAF11_STATUS                                                                       0xe43c
+#define regBIFL_RAS_LEAF11_STATUS_BASE_IDX                                                              5
+#define regBIFL_RAS_LEAF12_STATUS                                                                       0xe43d
+#define regBIFL_RAS_LEAF12_STATUS_BASE_IDX                                                              5
+#define regBIFL_RAS_LEAF13_STATUS                                                                       0xe43e
+#define regBIFL_RAS_LEAF13_STATUS_BASE_IDX                                                              5
+#define regBIFL_RAS_LEAF14_STATUS                                                                       0xe43f
+#define regBIFL_RAS_LEAF14_STATUS_BASE_IDX                                                              5
+#define regBIFL_RAS_LEAF15_STATUS                                                                       0xe440
+#define regBIFL_RAS_LEAF15_STATUS_BASE_IDX                                                              5
+#define regBIFL_RAS_LEAF16_STATUS                                                                       0xe441
+#define regBIFL_RAS_LEAF16_STATUS_BASE_IDX                                                              5
+#define regBIFL_RAS_LEAF17_STATUS                                                                       0xe442
+#define regBIFL_RAS_LEAF17_STATUS_BASE_IDX                                                              5
+#define regBIFL_RAS_LEAF18_STATUS                                                                       0xe443
+#define regBIFL_RAS_LEAF18_STATUS_BASE_IDX                                                              5
+#define regBIFL_RAS_LEAF19_STATUS                                                                       0xe444
+#define regBIFL_RAS_LEAF19_STATUS_BASE_IDX                                                              5
+#define regBIFL_DFV_POISON_INJ_IOHUB_ORIG_SDP                                                           0xe450
+#define regBIFL_DFV_POISON_INJ_IOHUB_ORIG_SDP_BASE_IDX                                                  5
+#define regBIFL_DFV_POISON_INJ_IOHUB_CMPL_SDP                                                           0xe451
+#define regBIFL_DFV_POISON_INJ_IOHUB_CMPL_SDP_BASE_IDX                                                  5
+#define regBIFL_DFV_POISON_INJ_ATHUB_CMPL_SDP                                                           0xe452
+#define regBIFL_DFV_POISON_INJ_ATHUB_CMPL_SDP_BASE_IDX                                                  5
+#define regBIFL_DFV_POISON_INJ_ATHUB_ORIG_SDP                                                           0xe453
+#define regBIFL_DFV_POISON_INJ_ATHUB_ORIG_SDP_BASE_IDX                                                  5
+#define regBIFL_DFV_POISON_INJ_CNT_IOHUB_ORIG_SDP                                                       0xe458
+#define regBIFL_DFV_POISON_INJ_CNT_IOHUB_ORIG_SDP_BASE_IDX                                              5
+#define regBIFL_DFV_POISON_INJ_CNT_IOHUB_CMPL_SDP                                                       0xe459
+#define regBIFL_DFV_POISON_INJ_CNT_IOHUB_CMPL_SDP_BASE_IDX                                              5
+#define regBIFL_DFV_POISON_INJ_CNT_ATHUB_CMPL_SDP                                                       0xe45a
+#define regBIFL_DFV_POISON_INJ_CNT_ATHUB_CMPL_SDP_BASE_IDX                                              5
+#define regBIFL_DFV_POISON_INJ_CNT_ATHUB_ORIG_SDP                                                       0xe45b
+#define regBIFL_DFV_POISON_INJ_CNT_ATHUB_ORIG_SDP_BASE_IDX                                              5
+#define regBIFL_DFV_POISON_INJ_LOG_IOHUB_ORIG_SDP                                                       0xe460
+#define regBIFL_DFV_POISON_INJ_LOG_IOHUB_ORIG_SDP_BASE_IDX                                              5
+#define regBIFL_DFV_POISON_INJ_LOG_IOHUB_CMPL_SDP                                                       0xe461
+#define regBIFL_DFV_POISON_INJ_LOG_IOHUB_CMPL_SDP_BASE_IDX                                              5
+#define regBIFL_DFV_POISON_INJ_LOG_ATHUB_CMPL_SDP                                                       0xe462
+#define regBIFL_DFV_POISON_INJ_LOG_ATHUB_CMPL_SDP_BASE_IDX                                              5
+#define regBIFL_DFV_POISON_INJ_LOG_ATHUB_ORIG_SDP                                                       0xe463
+#define regBIFL_DFV_POISON_INJ_LOG_ATHUB_ORIG_SDP_BASE_IDX                                              5
+#define regBIFL_IOHUB_RAS_IH_CNTL                                                                       0xe7fe
+#define regBIFL_IOHUB_RAS_IH_CNTL_BASE_IDX                                                              5
+#define regBIFL_RAS_VWR_FROM_IOHUB                                                                      0xe7ff
+#define regBIFL_RAS_VWR_FROM_IOHUB_BASE_IDX                                                             5
+
+
+// addressBlock: nbif0_nbif0_rcc_dwn_dev0_BIFDEC1
+// base address: 0x10120000
+#define regRCC_DWN_DEV0_2_DN_PCIE_RESERVED                                                              0x8d88
+#define regRCC_DWN_DEV0_2_DN_PCIE_RESERVED_BASE_IDX                                                     5
+#define regRCC_DWN_DEV0_2_DN_PCIE_SCRATCH                                                               0x8d89
+#define regRCC_DWN_DEV0_2_DN_PCIE_SCRATCH_BASE_IDX                                                      5
+#define regRCC_DWN_DEV0_2_DN_PCIE_CNTL                                                                  0x8d8b
+#define regRCC_DWN_DEV0_2_DN_PCIE_CNTL_BASE_IDX                                                         5
+#define regRCC_DWN_DEV0_2_DN_PCIE_CONFIG_CNTL                                                           0x8d8c
+#define regRCC_DWN_DEV0_2_DN_PCIE_CONFIG_CNTL_BASE_IDX                                                  5
+#define regRCC_DWN_DEV0_2_DN_PCIE_RX_CNTL2                                                              0x8d8d
+#define regRCC_DWN_DEV0_2_DN_PCIE_RX_CNTL2_BASE_IDX                                                     5
+#define regRCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL                                                              0x8d8e
+#define regRCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL_BASE_IDX                                                     5
+#define regRCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL                                                              0x8d8f
+#define regRCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL_BASE_IDX                                                     5
+#define regRCC_DWN_DEV0_2_DN_PCIE_STRAP_F0                                                              0x8d90
+#define regRCC_DWN_DEV0_2_DN_PCIE_STRAP_F0_BASE_IDX                                                     5
+#define regRCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC                                                            0x8d91
+#define regRCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC_BASE_IDX                                                   5
+#define regRCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC2                                                           0x8d92
+#define regRCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC2_BASE_IDX                                                  5
+
+
+// addressBlock: nbif0_nbif0_rcc_dwnp_dev0_BIFDEC1
+// base address: 0x10120000
+#define regRCC_DWNP_DEV0_2_PCIE_ERR_CNTL                                                                0x8d94
+#define regRCC_DWNP_DEV0_2_PCIE_ERR_CNTL_BASE_IDX                                                       5
+#define regRCC_DWNP_DEV0_2_PCIE_RX_CNTL                                                                 0x8d95
+#define regRCC_DWNP_DEV0_2_PCIE_RX_CNTL_BASE_IDX                                                        5
+#define regRCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL                                                           0x8d96
+#define regRCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL_BASE_IDX                                                  5
+#define regRCC_DWNP_DEV0_2_PCIE_LC_CNTL2                                                                0x8d97
+#define regRCC_DWNP_DEV0_2_PCIE_LC_CNTL2_BASE_IDX                                                       5
+#define regRCC_DWNP_DEV0_2_PCIEP_STRAP_MISC                                                             0x8d98
+#define regRCC_DWNP_DEV0_2_PCIEP_STRAP_MISC_BASE_IDX                                                    5
+#define regRCC_DWNP_DEV0_2_LTR_MSG_INFO_FROM_EP                                                         0x8d99
+#define regRCC_DWNP_DEV0_2_LTR_MSG_INFO_FROM_EP_BASE_IDX                                                5
+
+
+// addressBlock: nbif0_nbif0_rcc_ep_dev0_BIFDEC1
+// base address: 0x10120000
+#define regRCC_EP_DEV0_2_EP_PCIE_SCRATCH                                                                0x8d6b
+#define regRCC_EP_DEV0_2_EP_PCIE_SCRATCH_BASE_IDX                                                       5
+#define regRCC_EP_DEV0_2_EP_PCIE_CNTL                                                                   0x8d6d
+#define regRCC_EP_DEV0_2_EP_PCIE_CNTL_BASE_IDX                                                          5
+#define regRCC_EP_DEV0_2_EP_PCIE_INT_CNTL                                                               0x8d6e
+#define regRCC_EP_DEV0_2_EP_PCIE_INT_CNTL_BASE_IDX                                                      5
+#define regRCC_EP_DEV0_2_EP_PCIE_INT_STATUS                                                             0x8d6f
+#define regRCC_EP_DEV0_2_EP_PCIE_INT_STATUS_BASE_IDX                                                    5
+#define regRCC_EP_DEV0_2_EP_PCIE_RX_CNTL2                                                               0x8d70
+#define regRCC_EP_DEV0_2_EP_PCIE_RX_CNTL2_BASE_IDX                                                      5
+#define regRCC_EP_DEV0_2_EP_PCIE_BUS_CNTL                                                               0x8d71
+#define regRCC_EP_DEV0_2_EP_PCIE_BUS_CNTL_BASE_IDX                                                      5
+#define regRCC_EP_DEV0_2_EP_PCIE_CFG_CNTL                                                               0x8d72
+#define regRCC_EP_DEV0_2_EP_PCIE_CFG_CNTL_BASE_IDX                                                      5
+#define regRCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL                                                            0x8d74
+#define regRCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL_BASE_IDX                                                   5
+#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0                                               0x8d75
+#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX                                      5
+#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1                                               0x8d75
+#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX                                      5
+#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2                                               0x8d75
+#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX                                      5
+#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3                                               0x8d75
+#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX                                      5
+#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4                                               0x8d76
+#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX                                      5
+#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5                                               0x8d76
+#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX                                      5
+#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6                                               0x8d76
+#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX                                      5
+#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7                                               0x8d76
+#define regRCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX                                      5
+#define regRCC_EP_DEV0_2_EP_PCIE_STRAP_MISC                                                             0x8d77
+#define regRCC_EP_DEV0_2_EP_PCIE_STRAP_MISC_BASE_IDX                                                    5
+#define regRCC_EP_DEV0_2_EP_PCIE_STRAP_MISC2                                                            0x8d78
+#define regRCC_EP_DEV0_2_EP_PCIE_STRAP_MISC2_BASE_IDX                                                   5
+#define regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP                                                             0x8d7a
+#define regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP_BASE_IDX                                                    5
+#define regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_LATENCY_INDICATOR                                               0x8d7b
+#define regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_LATENCY_INDICATOR_BASE_IDX                                      5
+#define regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL                                                            0x8d7b
+#define regRCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL_BASE_IDX                                                   5
+#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0                                               0x8d7b
+#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0_BASE_IDX                                      5
+#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1                                               0x8d7c
+#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1_BASE_IDX                                      5
+#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2                                               0x8d7c
+#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2_BASE_IDX                                      5
+#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3                                               0x8d7c
+#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3_BASE_IDX                                      5
+#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4                                               0x8d7c
+#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4_BASE_IDX                                      5
+#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5                                               0x8d7d
+#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5_BASE_IDX                                      5
+#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6                                               0x8d7d
+#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6_BASE_IDX                                      5
+#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7                                               0x8d7d
+#define regRCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7_BASE_IDX                                      5
+#define regRCC_EP_DEV0_2_EP_PCIE_PME_CONTROL                                                            0x8d7d
+#define regRCC_EP_DEV0_2_EP_PCIE_PME_CONTROL_BASE_IDX                                                   5
+#define regRCC_EP_DEV0_2_EP_PCIEP_RESERVED                                                              0x8d7e
+#define regRCC_EP_DEV0_2_EP_PCIEP_RESERVED_BASE_IDX                                                     5
+#define regRCC_EP_DEV0_2_EP_PCIE_TX_CNTL                                                                0x8d80
+#define regRCC_EP_DEV0_2_EP_PCIE_TX_CNTL_BASE_IDX                                                       5
+#define regRCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID                                                        0x8d81
+#define regRCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID_BASE_IDX                                               5
+#define regRCC_EP_DEV0_2_EP_PCIE_ERR_CNTL                                                               0x8d82
+#define regRCC_EP_DEV0_2_EP_PCIE_ERR_CNTL_BASE_IDX                                                      5
+#define regRCC_EP_DEV0_2_EP_PCIE_RX_CNTL                                                                0x8d83
+#define regRCC_EP_DEV0_2_EP_PCIE_RX_CNTL_BASE_IDX                                                       5
+#define regRCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL                                                          0x8d84
+#define regRCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL_BASE_IDX                                                 5
+#define regRCC_EP_DEV0_2_EP_PCIE_DEVICE_CNTL3                                                           0x8d85
+#define regRCC_EP_DEV0_2_EP_PCIE_DEVICE_CNTL3_BASE_IDX                                                  5
+
+
+// addressBlock: nbif0_nbif0_rcc_dev0_BIFDEC1
+// base address: 0x10120000
+#define regRCC_DEV0_1_RCC_ERR_INT_CNTL                                                                  0x8da6
+#define regRCC_DEV0_1_RCC_ERR_INT_CNTL_BASE_IDX                                                         5
+#define regRCC_DEV0_1_RCC_BACO_CNTL_MISC                                                                0x8da7
+#define regRCC_DEV0_1_RCC_BACO_CNTL_MISC_BASE_IDX                                                       5
+#define regRCC_DEV0_1_RCC_RESET_EN                                                                      0x8da8
+#define regRCC_DEV0_1_RCC_RESET_EN_BASE_IDX                                                             5
+#define regRCC_DEV0_2_RCC_VDM_SUPPORT                                                                   0x8da9
+#define regRCC_DEV0_2_RCC_VDM_SUPPORT_BASE_IDX                                                          5
+#define regRCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0                                                            0x8daa
+#define regRCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0_BASE_IDX                                                   5
+#define regRCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1                                                            0x8dab
+#define regRCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1_BASE_IDX                                                   5
+#define regRCC_DEV0_1_RCC_GPUIOV_REGION                                                                 0x8dac
+#define regRCC_DEV0_1_RCC_GPUIOV_REGION_BASE_IDX                                                        5
+#define regRCC_DEV0_1_RCC_GPU_HOSTVM_EN                                                                 0x8dad
+#define regRCC_DEV0_1_RCC_GPU_HOSTVM_EN_BASE_IDX                                                        5
+#define regRCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL                                                         0x8dae
+#define regRCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL_BASE_IDX                                                5
+#define regRCC_DEV0_1_RCC_CONSOLE_IOV_FIRST_VF_OFFSET                                                   0x8daf
+#define regRCC_DEV0_1_RCC_CONSOLE_IOV_FIRST_VF_OFFSET_BASE_IDX                                          5
+#define regRCC_DEV0_1_RCC_CONSOLE_IOV_VF_STRIDE                                                         0x8daf
+#define regRCC_DEV0_1_RCC_CONSOLE_IOV_VF_STRIDE_BASE_IDX                                                5
+#define regRCC_DEV0_1_RCC_PEER_REG_RANGE0                                                               0x8dde
+#define regRCC_DEV0_1_RCC_PEER_REG_RANGE0_BASE_IDX                                                      5
+#define regRCC_DEV0_1_RCC_PEER_REG_RANGE1                                                               0x8ddf
+#define regRCC_DEV0_1_RCC_PEER_REG_RANGE1_BASE_IDX                                                      5
+#define regRCC_DEV0_2_RCC_BUS_CNTL                                                                      0x8de1
+#define regRCC_DEV0_2_RCC_BUS_CNTL_BASE_IDX                                                             5
+#define regRCC_DEV0_1_RCC_CONFIG_CNTL                                                                   0x8de2
+#define regRCC_DEV0_1_RCC_CONFIG_CNTL_BASE_IDX                                                          5
+#define regRCC_DEV0_1_RCC_CONFIG_F0_BASE                                                                0x8de6
+#define regRCC_DEV0_1_RCC_CONFIG_F0_BASE_BASE_IDX                                                       5
+#define regRCC_DEV0_1_RCC_CONFIG_APER_SIZE                                                              0x8de7
+#define regRCC_DEV0_1_RCC_CONFIG_APER_SIZE_BASE_IDX                                                     5
+#define regRCC_DEV0_1_RCC_CONFIG_REG_APER_SIZE                                                          0x8de8
+#define regRCC_DEV0_1_RCC_CONFIG_REG_APER_SIZE_BASE_IDX                                                 5
+#define regRCC_DEV0_1_RCC_XDMA_LO                                                                       0x8de9
+#define regRCC_DEV0_1_RCC_XDMA_LO_BASE_IDX                                                              5
+#define regRCC_DEV0_1_RCC_XDMA_HI                                                                       0x8dea
+#define regRCC_DEV0_1_RCC_XDMA_HI_BASE_IDX                                                              5
+#define regRCC_DEV0_2_RCC_FEATURES_CONTROL_MISC                                                         0x8deb
+#define regRCC_DEV0_2_RCC_FEATURES_CONTROL_MISC_BASE_IDX                                                5
+#define regRCC_DEV0_1_RCC_BUSNUM_CNTL1                                                                  0x8dec
+#define regRCC_DEV0_1_RCC_BUSNUM_CNTL1_BASE_IDX                                                         5
+#define regRCC_DEV0_1_RCC_BUSNUM_LIST0                                                                  0x8ded
+#define regRCC_DEV0_1_RCC_BUSNUM_LIST0_BASE_IDX                                                         5
+#define regRCC_DEV0_1_RCC_BUSNUM_LIST1                                                                  0x8dee
+#define regRCC_DEV0_1_RCC_BUSNUM_LIST1_BASE_IDX                                                         5
+#define regRCC_DEV0_1_RCC_BUSNUM_CNTL2                                                                  0x8def
+#define regRCC_DEV0_1_RCC_BUSNUM_CNTL2_BASE_IDX                                                         5
+#define regRCC_DEV0_1_RCC_CAPTURE_HOST_BUSNUM                                                           0x8df0
+#define regRCC_DEV0_1_RCC_CAPTURE_HOST_BUSNUM_BASE_IDX                                                  5
+#define regRCC_DEV0_1_RCC_HOST_BUSNUM                                                                   0x8df1
+#define regRCC_DEV0_1_RCC_HOST_BUSNUM_BASE_IDX                                                          5
+#define regRCC_DEV0_1_RCC_PEER0_FB_OFFSET_HI                                                            0x8df2
+#define regRCC_DEV0_1_RCC_PEER0_FB_OFFSET_HI_BASE_IDX                                                   5
+#define regRCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO                                                            0x8df3
+#define regRCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO_BASE_IDX                                                   5
+#define regRCC_DEV0_1_RCC_PEER1_FB_OFFSET_HI                                                            0x8df4
+#define regRCC_DEV0_1_RCC_PEER1_FB_OFFSET_HI_BASE_IDX                                                   5
+#define regRCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO                                                            0x8df5
+#define regRCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO_BASE_IDX                                                   5
+#define regRCC_DEV0_1_RCC_PEER2_FB_OFFSET_HI                                                            0x8df6
+#define regRCC_DEV0_1_RCC_PEER2_FB_OFFSET_HI_BASE_IDX                                                   5
+#define regRCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO                                                            0x8df7
+#define regRCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO_BASE_IDX                                                   5
+#define regRCC_DEV0_1_RCC_PEER3_FB_OFFSET_HI                                                            0x8df8
+#define regRCC_DEV0_1_RCC_PEER3_FB_OFFSET_HI_BASE_IDX                                                   5
+#define regRCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO                                                            0x8df9
+#define regRCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO_BASE_IDX                                                   5
+#define regRCC_DEV0_1_RCC_DEVFUNCNUM_LIST0                                                              0x8dfa
+#define regRCC_DEV0_1_RCC_DEVFUNCNUM_LIST0_BASE_IDX                                                     5
+#define regRCC_DEV0_1_RCC_DEVFUNCNUM_LIST1                                                              0x8dfb
+#define regRCC_DEV0_1_RCC_DEVFUNCNUM_LIST1_BASE_IDX                                                     5
+#define regRCC_DEV0_2_RCC_DEV0_LINK_CNTL                                                                0x8dfd
+#define regRCC_DEV0_2_RCC_DEV0_LINK_CNTL_BASE_IDX                                                       5
+#define regRCC_DEV0_2_RCC_CMN_LINK_CNTL                                                                 0x8dfe
+#define regRCC_DEV0_2_RCC_CMN_LINK_CNTL_BASE_IDX                                                        5
+#define regRCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE                                                        0x8dff
+#define regRCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE_BASE_IDX                                               5
+#define regRCC_DEV0_2_RCC_LTR_LSWITCH_CNTL                                                              0x8e00
+#define regRCC_DEV0_2_RCC_LTR_LSWITCH_CNTL_BASE_IDX                                                     5
+#define regRCC_DEV0_2_RCC_MH_ARB_CNTL                                                                   0x8e01
+#define regRCC_DEV0_2_RCC_MH_ARB_CNTL_BASE_IDX                                                          5
+
+
+// addressBlock: nbif0_nbif0_bif_bx_SYSDEC
+// base address: 0x10120000
+#define regBIF_BX1_SYSHUB_INDEX_OVLP                                                                    0x8008
+#define regBIF_BX1_SYSHUB_INDEX_OVLP_BASE_IDX                                                           5
+#define regBIF_BX1_SYSHUB_DATA_OVLP                                                                     0x8009
+#define regBIF_BX1_SYSHUB_DATA_OVLP_BASE_IDX                                                            5
+#define regBIF_BX1_SYSHUB_INDEX_HI_OVLP                                                                 0x800a
+#define regBIF_BX1_SYSHUB_INDEX_HI_OVLP_BASE_IDX                                                        5
+#define regBIF_BX1_PCIE_INDEX                                                                           0x800c
+#define regBIF_BX1_PCIE_INDEX_BASE_IDX                                                                  5
+#define regBIF_BX1_PCIE_DATA                                                                            0x800d
+#define regBIF_BX1_PCIE_DATA_BASE_IDX                                                                   5
+#define regBIF_BX1_PCIE_INDEX2                                                                          0x800e
+#define regBIF_BX1_PCIE_INDEX2_BASE_IDX                                                                 5
+#define regBIF_BX1_PCIE_DATA2                                                                           0x800f
+#define regBIF_BX1_PCIE_DATA2_BASE_IDX                                                                  5
+#define regBIF_BX1_PCIE_INDEX_HI                                                                        0x8010
+#define regBIF_BX1_PCIE_INDEX_HI_BASE_IDX                                                               5
+#define regBIF_BX1_PCIE_INDEX2_HI                                                                       0x8011
+#define regBIF_BX1_PCIE_INDEX2_HI_BASE_IDX                                                              5
+#define regBIF_BX1_SBIOS_SCRATCH_0                                                                      0x8048
+#define regBIF_BX1_SBIOS_SCRATCH_0_BASE_IDX                                                             5
+#define regBIF_BX1_SBIOS_SCRATCH_1                                                                      0x8049
+#define regBIF_BX1_SBIOS_SCRATCH_1_BASE_IDX                                                             5
+#define regBIF_BX1_SBIOS_SCRATCH_2                                                                      0x804a
+#define regBIF_BX1_SBIOS_SCRATCH_2_BASE_IDX                                                             5
+#define regBIF_BX1_SBIOS_SCRATCH_3                                                                      0x804b
+#define regBIF_BX1_SBIOS_SCRATCH_3_BASE_IDX                                                             5
+#define regBIF_BX1_BIOS_SCRATCH_0                                                                       0x804c
+#define regBIF_BX1_BIOS_SCRATCH_0_BASE_IDX                                                              5
+#define regBIF_BX1_BIOS_SCRATCH_1                                                                       0x804d
+#define regBIF_BX1_BIOS_SCRATCH_1_BASE_IDX                                                              5
+#define regBIF_BX1_BIOS_SCRATCH_2                                                                       0x804e
+#define regBIF_BX1_BIOS_SCRATCH_2_BASE_IDX                                                              5
+#define regBIF_BX1_BIOS_SCRATCH_3                                                                       0x804f
+#define regBIF_BX1_BIOS_SCRATCH_3_BASE_IDX                                                              5
+#define regBIF_BX1_BIOS_SCRATCH_4                                                                       0x8050
+#define regBIF_BX1_BIOS_SCRATCH_4_BASE_IDX                                                              5
+#define regBIF_BX1_BIOS_SCRATCH_5                                                                       0x8051
+#define regBIF_BX1_BIOS_SCRATCH_5_BASE_IDX                                                              5
+#define regBIF_BX1_BIOS_SCRATCH_6                                                                       0x8052
+#define regBIF_BX1_BIOS_SCRATCH_6_BASE_IDX                                                              5
+#define regBIF_BX1_BIOS_SCRATCH_7                                                                       0x8053
+#define regBIF_BX1_BIOS_SCRATCH_7_BASE_IDX                                                              5
+#define regBIF_BX1_BIOS_SCRATCH_8                                                                       0x8054
+#define regBIF_BX1_BIOS_SCRATCH_8_BASE_IDX                                                              5
+#define regBIF_BX1_BIOS_SCRATCH_9                                                                       0x8055
+#define regBIF_BX1_BIOS_SCRATCH_9_BASE_IDX                                                              5
+#define regBIF_BX1_BIOS_SCRATCH_10                                                                      0x8056
+#define regBIF_BX1_BIOS_SCRATCH_10_BASE_IDX                                                             5
+#define regBIF_BX1_BIOS_SCRATCH_11                                                                      0x8057
+#define regBIF_BX1_BIOS_SCRATCH_11_BASE_IDX                                                             5
+#define regBIF_BX1_BIOS_SCRATCH_12                                                                      0x8058
+#define regBIF_BX1_BIOS_SCRATCH_12_BASE_IDX                                                             5
+#define regBIF_BX1_BIOS_SCRATCH_13                                                                      0x8059
+#define regBIF_BX1_BIOS_SCRATCH_13_BASE_IDX                                                             5
+#define regBIF_BX1_BIOS_SCRATCH_14                                                                      0x805a
+#define regBIF_BX1_BIOS_SCRATCH_14_BASE_IDX                                                             5
+#define regBIF_BX1_BIOS_SCRATCH_15                                                                      0x805b
+#define regBIF_BX1_BIOS_SCRATCH_15_BASE_IDX                                                             5
+#define regBIF_BX1_BIF_RLC_INTR_CNTL                                                                    0x8060
+#define regBIF_BX1_BIF_RLC_INTR_CNTL_BASE_IDX                                                           5
+#define regBIF_BX1_BIF_VCE_INTR_CNTL                                                                    0x8061
+#define regBIF_BX1_BIF_VCE_INTR_CNTL_BASE_IDX                                                           5
+#define regBIF_BX1_BIF_UVD_INTR_CNTL                                                                    0x8062
+#define regBIF_BX1_BIF_UVD_INTR_CNTL_BASE_IDX                                                           5
+#define regBIF_BX1_BIF_Engine_INTR_CNTL                                                                 0x8063
+#define regBIF_BX1_BIF_Engine_INTR_CNTL_BASE_IDX                                                        5
+#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR0                                                                0x8080
+#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR0_BASE_IDX                                                       5
+#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR0                                                          0x8081
+#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR0_BASE_IDX                                                 5
+#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR1                                                                0x8082
+#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR1_BASE_IDX                                                       5
+#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR1                                                          0x8083
+#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR1_BASE_IDX                                                 5
+#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR2                                                                0x8084
+#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR2_BASE_IDX                                                       5
+#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR2                                                          0x8085
+#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR2_BASE_IDX                                                 5
+#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR3                                                                0x8086
+#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR3_BASE_IDX                                                       5
+#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR3                                                          0x8087
+#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR3_BASE_IDX                                                 5
+#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR4                                                                0x8088
+#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR4_BASE_IDX                                                       5
+#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR4                                                          0x8089
+#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR4_BASE_IDX                                                 5
+#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR5                                                                0x808a
+#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR5_BASE_IDX                                                       5
+#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR5                                                          0x808b
+#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR5_BASE_IDX                                                 5
+#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR6                                                                0x808c
+#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR6_BASE_IDX                                                       5
+#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR6                                                          0x808d
+#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR6_BASE_IDX                                                 5
+#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR7                                                                0x808e
+#define regBIF_BX1_GFX_MMIOREG_CAM_ADDR7_BASE_IDX                                                       5
+#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR7                                                          0x808f
+#define regBIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR7_BASE_IDX                                                 5
+#define regBIF_BX1_GFX_MMIOREG_CAM_CNTL                                                                 0x8090
+#define regBIF_BX1_GFX_MMIOREG_CAM_CNTL_BASE_IDX                                                        5
+#define regBIF_BX1_GFX_MMIOREG_CAM_ZERO_CPL                                                             0x8091
+#define regBIF_BX1_GFX_MMIOREG_CAM_ZERO_CPL_BASE_IDX                                                    5
+#define regBIF_BX1_GFX_MMIOREG_CAM_ONE_CPL                                                              0x8092
+#define regBIF_BX1_GFX_MMIOREG_CAM_ONE_CPL_BASE_IDX                                                     5
+#define regBIF_BX1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL                                                     0x8093
+#define regBIF_BX1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL_BASE_IDX                                            5
+#define regBIF_BX1_DRIVER_SCRATCH_0                                                                     0x8094
+#define regBIF_BX1_DRIVER_SCRATCH_0_BASE_IDX                                                            5
+#define regBIF_BX1_DRIVER_SCRATCH_1                                                                     0x8095
+#define regBIF_BX1_DRIVER_SCRATCH_1_BASE_IDX                                                            5
+#define regBIF_BX1_DRIVER_SCRATCH_2                                                                     0x8096
+#define regBIF_BX1_DRIVER_SCRATCH_2_BASE_IDX                                                            5
+#define regBIF_BX1_DRIVER_SCRATCH_3                                                                     0x8097
+#define regBIF_BX1_DRIVER_SCRATCH_3_BASE_IDX                                                            5
+#define regBIF_BX1_DRIVER_SCRATCH_4                                                                     0x8098
+#define regBIF_BX1_DRIVER_SCRATCH_4_BASE_IDX                                                            5
+#define regBIF_BX1_DRIVER_SCRATCH_5                                                                     0x8099
+#define regBIF_BX1_DRIVER_SCRATCH_5_BASE_IDX                                                            5
+#define regBIF_BX1_DRIVER_SCRATCH_6                                                                     0x809a
+#define regBIF_BX1_DRIVER_SCRATCH_6_BASE_IDX                                                            5
+#define regBIF_BX1_DRIVER_SCRATCH_7                                                                     0x809b
+#define regBIF_BX1_DRIVER_SCRATCH_7_BASE_IDX                                                            5
+#define regBIF_BX1_DRIVER_SCRATCH_8                                                                     0x809c
+#define regBIF_BX1_DRIVER_SCRATCH_8_BASE_IDX                                                            5
+#define regBIF_BX1_DRIVER_SCRATCH_9                                                                     0x809d
+#define regBIF_BX1_DRIVER_SCRATCH_9_BASE_IDX                                                            5
+#define regBIF_BX1_DRIVER_SCRATCH_10                                                                    0x809e
+#define regBIF_BX1_DRIVER_SCRATCH_10_BASE_IDX                                                           5
+#define regBIF_BX1_DRIVER_SCRATCH_11                                                                    0x809f
+#define regBIF_BX1_DRIVER_SCRATCH_11_BASE_IDX                                                           5
+#define regBIF_BX1_DRIVER_SCRATCH_12                                                                    0x80a0
+#define regBIF_BX1_DRIVER_SCRATCH_12_BASE_IDX                                                           5
+#define regBIF_BX1_DRIVER_SCRATCH_13                                                                    0x80a1
+#define regBIF_BX1_DRIVER_SCRATCH_13_BASE_IDX                                                           5
+#define regBIF_BX1_DRIVER_SCRATCH_14                                                                    0x80a2
+#define regBIF_BX1_DRIVER_SCRATCH_14_BASE_IDX                                                           5
+#define regBIF_BX1_DRIVER_SCRATCH_15                                                                    0x80a3
+#define regBIF_BX1_DRIVER_SCRATCH_15_BASE_IDX                                                           5
+#define regBIF_BX1_FW_SCRATCH_0                                                                         0x80a4
+#define regBIF_BX1_FW_SCRATCH_0_BASE_IDX                                                                5
+#define regBIF_BX1_FW_SCRATCH_1                                                                         0x80a5
+#define regBIF_BX1_FW_SCRATCH_1_BASE_IDX                                                                5
+#define regBIF_BX1_FW_SCRATCH_2                                                                         0x80a6
+#define regBIF_BX1_FW_SCRATCH_2_BASE_IDX                                                                5
+#define regBIF_BX1_FW_SCRATCH_3                                                                         0x80a7
+#define regBIF_BX1_FW_SCRATCH_3_BASE_IDX                                                                5
+#define regBIF_BX1_FW_SCRATCH_4                                                                         0x80a8
+#define regBIF_BX1_FW_SCRATCH_4_BASE_IDX                                                                5
+#define regBIF_BX1_FW_SCRATCH_5                                                                         0x80a9
+#define regBIF_BX1_FW_SCRATCH_5_BASE_IDX                                                                5
+#define regBIF_BX1_FW_SCRATCH_6                                                                         0x80aa
+#define regBIF_BX1_FW_SCRATCH_6_BASE_IDX                                                                5
+#define regBIF_BX1_FW_SCRATCH_7                                                                         0x80ab
+#define regBIF_BX1_FW_SCRATCH_7_BASE_IDX                                                                5
+#define regBIF_BX1_FW_SCRATCH_8                                                                         0x80ac
+#define regBIF_BX1_FW_SCRATCH_8_BASE_IDX                                                                5
+#define regBIF_BX1_FW_SCRATCH_9                                                                         0x80ad
+#define regBIF_BX1_FW_SCRATCH_9_BASE_IDX                                                                5
+#define regBIF_BX1_FW_SCRATCH_10                                                                        0x80ae
+#define regBIF_BX1_FW_SCRATCH_10_BASE_IDX                                                               5
+#define regBIF_BX1_FW_SCRATCH_11                                                                        0x80af
+#define regBIF_BX1_FW_SCRATCH_11_BASE_IDX                                                               5
+#define regBIF_BX1_FW_SCRATCH_12                                                                        0x80b0
+#define regBIF_BX1_FW_SCRATCH_12_BASE_IDX                                                               5
+#define regBIF_BX1_FW_SCRATCH_13                                                                        0x80b1
+#define regBIF_BX1_FW_SCRATCH_13_BASE_IDX                                                               5
+#define regBIF_BX1_FW_SCRATCH_14                                                                        0x80b2
+#define regBIF_BX1_FW_SCRATCH_14_BASE_IDX                                                               5
+#define regBIF_BX1_FW_SCRATCH_15                                                                        0x80b3
+#define regBIF_BX1_FW_SCRATCH_15_BASE_IDX                                                               5
+#define regBIF_BX1_SBIOS_SCRATCH_4                                                                      0x80b4
+#define regBIF_BX1_SBIOS_SCRATCH_4_BASE_IDX                                                             5
+#define regBIF_BX1_SBIOS_SCRATCH_5                                                                      0x80b5
+#define regBIF_BX1_SBIOS_SCRATCH_5_BASE_IDX                                                             5
+#define regBIF_BX1_SBIOS_SCRATCH_6                                                                      0x80b6
+#define regBIF_BX1_SBIOS_SCRATCH_6_BASE_IDX                                                             5
+#define regBIF_BX1_SBIOS_SCRATCH_7                                                                      0x80b7
+#define regBIF_BX1_SBIOS_SCRATCH_7_BASE_IDX                                                             5
+#define regBIF_BX1_SBIOS_SCRATCH_8                                                                      0x80b8
+#define regBIF_BX1_SBIOS_SCRATCH_8_BASE_IDX                                                             5
+#define regBIF_BX1_SBIOS_SCRATCH_9                                                                      0x80b9
+#define regBIF_BX1_SBIOS_SCRATCH_9_BASE_IDX                                                             5
+#define regBIF_BX1_SBIOS_SCRATCH_10                                                                     0x80ba
+#define regBIF_BX1_SBIOS_SCRATCH_10_BASE_IDX                                                            5
+#define regBIF_BX1_SBIOS_SCRATCH_11                                                                     0x80bb
+#define regBIF_BX1_SBIOS_SCRATCH_11_BASE_IDX                                                            5
+#define regBIF_BX1_SBIOS_SCRATCH_12                                                                     0x80bc
+#define regBIF_BX1_SBIOS_SCRATCH_12_BASE_IDX                                                            5
+#define regBIF_BX1_SBIOS_SCRATCH_13                                                                     0x80bd
+#define regBIF_BX1_SBIOS_SCRATCH_13_BASE_IDX                                                            5
+#define regBIF_BX1_SBIOS_SCRATCH_14                                                                     0x80be
+#define regBIF_BX1_SBIOS_SCRATCH_14_BASE_IDX                                                            5
+#define regBIF_BX1_SBIOS_SCRATCH_15                                                                     0x80bf
+#define regBIF_BX1_SBIOS_SCRATCH_15_BASE_IDX                                                            5
+
+
+// addressBlock: nbif0_nbif0_bif_bx_pf_SYSPFVFDEC
+// base address: 0x10120000
+#define regBIF_BX_PF1_MM_INDEX                                                                          0x8000
+#define regBIF_BX_PF1_MM_INDEX_BASE_IDX                                                                 5
+#define regBIF_BX_PF1_MM_DATA                                                                           0x8001
+#define regBIF_BX_PF1_MM_DATA_BASE_IDX                                                                  5
+#define regBIF_BX_PF1_MM_INDEX_HI                                                                       0x8006
+#define regBIF_BX_PF1_MM_INDEX_HI_BASE_IDX                                                              5
+
+
+// addressBlock: nbif0_nbif0_bif_bx_BIFDEC1
+// base address: 0x10120000
+#define regBIF_BX1_CC_BIF_BX_STRAP0                                                                     0x8e02
+#define regBIF_BX1_CC_BIF_BX_STRAP0_BASE_IDX                                                            5
+#define regBIF_BX1_CC_BIF_BX_PINSTRAP0                                                                  0x8e04
+#define regBIF_BX1_CC_BIF_BX_PINSTRAP0_BASE_IDX                                                         5
+#define regBIF_BX1_BIF_MM_INDACCESS_CNTL                                                                0x8e06
+#define regBIF_BX1_BIF_MM_INDACCESS_CNTL_BASE_IDX                                                       5
+#define regBIF_BX1_BUS_CNTL                                                                             0x8e07
+#define regBIF_BX1_BUS_CNTL_BASE_IDX                                                                    5
+#define regBIF_BX1_BIF_SCRATCH0                                                                         0x8e08
+#define regBIF_BX1_BIF_SCRATCH0_BASE_IDX                                                                5
+#define regBIF_BX1_BIF_SCRATCH1                                                                         0x8e09
+#define regBIF_BX1_BIF_SCRATCH1_BASE_IDX                                                                5
+#define regBIF_BX1_BX_RESET_EN                                                                          0x8e0d
+#define regBIF_BX1_BX_RESET_EN_BASE_IDX                                                                 5
+#define regBIF_BX1_MM_CFGREGS_CNTL                                                                      0x8e0e
+#define regBIF_BX1_MM_CFGREGS_CNTL_BASE_IDX                                                             5
+#define regBIF_BX1_BX_RESET_CNTL                                                                        0x8e10
+#define regBIF_BX1_BX_RESET_CNTL_BASE_IDX                                                               5
+#define regBIF_BX1_INTERRUPT_CNTL                                                                       0x8e11
+#define regBIF_BX1_INTERRUPT_CNTL_BASE_IDX                                                              5
+#define regBIF_BX1_INTERRUPT_CNTL2                                                                      0x8e12
+#define regBIF_BX1_INTERRUPT_CNTL2_BASE_IDX                                                             5
+#define regBIF_BX1_CLKREQB_PAD_CNTL                                                                     0x8e18
+#define regBIF_BX1_CLKREQB_PAD_CNTL_BASE_IDX                                                            5
+#define regBIF_BX1_BIF_FEATURES_CONTROL_MISC                                                            0x8e1b
+#define regBIF_BX1_BIF_FEATURES_CONTROL_MISC_BASE_IDX                                                   5
+#define regBIF_BX1_HDP_ATOMIC_CONTROL_MISC                                                              0x8e1c
+#define regBIF_BX1_HDP_ATOMIC_CONTROL_MISC_BASE_IDX                                                     5
+#define regBIF_BX1_BIF_DOORBELL_CNTL                                                                    0x8e1d
+#define regBIF_BX1_BIF_DOORBELL_CNTL_BASE_IDX                                                           5
+#define regBIF_BX1_BIF_DOORBELL_INT_CNTL                                                                0x8e1e
+#define regBIF_BX1_BIF_DOORBELL_INT_CNTL_BASE_IDX                                                       5
+#define regBIF_BX1_BIF_FB_EN                                                                            0x8e20
+#define regBIF_BX1_BIF_FB_EN_BASE_IDX                                                                   5
+#define regBIF_BX1_BIF_INTR_CNTL                                                                        0x8e21
+#define regBIF_BX1_BIF_INTR_CNTL_BASE_IDX                                                               5
+#define regBIF_BX1_BIF_MST_TRANS_PENDING_VF                                                             0x8e29
+#define regBIF_BX1_BIF_MST_TRANS_PENDING_VF_BASE_IDX                                                    5
+#define regBIF_BX1_BIF_SLV_TRANS_PENDING_VF                                                             0x8e2a
+#define regBIF_BX1_BIF_SLV_TRANS_PENDING_VF_BASE_IDX                                                    5
+#define regBIF_BX1_BACO_CNTL                                                                            0x8e2b
+#define regBIF_BX1_BACO_CNTL_BASE_IDX                                                                   5
+#define regBIF_BX1_BIF_BACO_EXIT_TIME0                                                                  0x8e2c
+#define regBIF_BX1_BIF_BACO_EXIT_TIME0_BASE_IDX                                                         5
+#define regBIF_BX1_BIF_BACO_EXIT_TIMER1                                                                 0x8e2d
+#define regBIF_BX1_BIF_BACO_EXIT_TIMER1_BASE_IDX                                                        5
+#define regBIF_BX1_BIF_BACO_EXIT_TIMER2                                                                 0x8e2e
+#define regBIF_BX1_BIF_BACO_EXIT_TIMER2_BASE_IDX                                                        5
+#define regBIF_BX1_BIF_BACO_EXIT_TIMER3                                                                 0x8e2f
+#define regBIF_BX1_BIF_BACO_EXIT_TIMER3_BASE_IDX                                                        5
+#define regBIF_BX1_BIF_BACO_EXIT_TIMER4                                                                 0x8e30
+#define regBIF_BX1_BIF_BACO_EXIT_TIMER4_BASE_IDX                                                        5
+#define regBIF_BX1_MEM_TYPE_CNTL                                                                        0x8e31
+#define regBIF_BX1_MEM_TYPE_CNTL_BASE_IDX                                                               5
+#define regBIF_BX1_NBIF_GFX_ADDR_LUT_CNTL                                                               0x8e33
+#define regBIF_BX1_NBIF_GFX_ADDR_LUT_CNTL_BASE_IDX                                                      5
+#define regBIF_BX1_NBIF_GFX_ADDR_LUT_0                                                                  0x8e34
+#define regBIF_BX1_NBIF_GFX_ADDR_LUT_0_BASE_IDX                                                         5
+#define regBIF_BX1_NBIF_GFX_ADDR_LUT_1                                                                  0x8e35
+#define regBIF_BX1_NBIF_GFX_ADDR_LUT_1_BASE_IDX                                                         5
+#define regBIF_BX1_NBIF_GFX_ADDR_LUT_2                                                                  0x8e36
+#define regBIF_BX1_NBIF_GFX_ADDR_LUT_2_BASE_IDX                                                         5
+#define regBIF_BX1_NBIF_GFX_ADDR_LUT_3                                                                  0x8e37
+#define regBIF_BX1_NBIF_GFX_ADDR_LUT_3_BASE_IDX                                                         5
+#define regBIF_BX1_NBIF_GFX_ADDR_LUT_4                                                                  0x8e38
+#define regBIF_BX1_NBIF_GFX_ADDR_LUT_4_BASE_IDX                                                         5
+#define regBIF_BX1_NBIF_GFX_ADDR_LUT_5                                                                  0x8e39
+#define regBIF_BX1_NBIF_GFX_ADDR_LUT_5_BASE_IDX                                                         5
+#define regBIF_BX1_NBIF_GFX_ADDR_LUT_6                                                                  0x8e3a
+#define regBIF_BX1_NBIF_GFX_ADDR_LUT_6_BASE_IDX                                                         5
+#define regBIF_BX1_NBIF_GFX_ADDR_LUT_7                                                                  0x8e3b
+#define regBIF_BX1_NBIF_GFX_ADDR_LUT_7_BASE_IDX                                                         5
+#define regBIF_BX1_NBIF_GFX_ADDR_LUT_8                                                                  0x8e3c
+#define regBIF_BX1_NBIF_GFX_ADDR_LUT_8_BASE_IDX                                                         5
+#define regBIF_BX1_NBIF_GFX_ADDR_LUT_9                                                                  0x8e3d
+#define regBIF_BX1_NBIF_GFX_ADDR_LUT_9_BASE_IDX                                                         5
+#define regBIF_BX1_NBIF_GFX_ADDR_LUT_10                                                                 0x8e3e
+#define regBIF_BX1_NBIF_GFX_ADDR_LUT_10_BASE_IDX                                                        5
+#define regBIF_BX1_NBIF_GFX_ADDR_LUT_11                                                                 0x8e3f
+#define regBIF_BX1_NBIF_GFX_ADDR_LUT_11_BASE_IDX                                                        5
+#define regBIF_BX1_NBIF_GFX_ADDR_LUT_12                                                                 0x8e40
+#define regBIF_BX1_NBIF_GFX_ADDR_LUT_12_BASE_IDX                                                        5
+#define regBIF_BX1_NBIF_GFX_ADDR_LUT_13                                                                 0x8e41
+#define regBIF_BX1_NBIF_GFX_ADDR_LUT_13_BASE_IDX                                                        5
+#define regBIF_BX1_NBIF_GFX_ADDR_LUT_14                                                                 0x8e42
+#define regBIF_BX1_NBIF_GFX_ADDR_LUT_14_BASE_IDX                                                        5
+#define regBIF_BX1_NBIF_GFX_ADDR_LUT_15                                                                 0x8e43
+#define regBIF_BX1_NBIF_GFX_ADDR_LUT_15_BASE_IDX                                                        5
+#define regBIF_BX1_VF_REGWR_EN                                                                          0x8e44
+#define regBIF_BX1_VF_REGWR_EN_BASE_IDX                                                                 5
+#define regBIF_BX1_VF_DOORBELL_EN                                                                       0x8e45
+#define regBIF_BX1_VF_DOORBELL_EN_BASE_IDX                                                              5
+#define regBIF_BX1_VF_FB_EN                                                                             0x8e46
+#define regBIF_BX1_VF_FB_EN_BASE_IDX                                                                    5
+#define regBIF_BX1_VF_REGWR_STATUS                                                                      0x8e47
+#define regBIF_BX1_VF_REGWR_STATUS_BASE_IDX                                                             5
+#define regBIF_BX1_VF_DOORBELL_STATUS                                                                   0x8e48
+#define regBIF_BX1_VF_DOORBELL_STATUS_BASE_IDX                                                          5
+#define regBIF_BX1_VF_FB_STATUS                                                                         0x8e49
+#define regBIF_BX1_VF_FB_STATUS_BASE_IDX                                                                5
+#define regBIF_BX1_REMAP_HDP_MEM_FLUSH_CNTL                                                             0x8e4d
+#define regBIF_BX1_REMAP_HDP_MEM_FLUSH_CNTL_BASE_IDX                                                    5
+#define regBIF_BX1_REMAP_HDP_REG_FLUSH_CNTL                                                             0x8e4e
+#define regBIF_BX1_REMAP_HDP_REG_FLUSH_CNTL_BASE_IDX                                                    5
+#define regBIF_BX1_BIF_RB_CNTL                                                                          0x8e4f
+#define regBIF_BX1_BIF_RB_CNTL_BASE_IDX                                                                 5
+#define regBIF_BX1_BIF_RB_BASE                                                                          0x8e50
+#define regBIF_BX1_BIF_RB_BASE_BASE_IDX                                                                 5
+#define regBIF_BX1_BIF_RB_RPTR                                                                          0x8e51
+#define regBIF_BX1_BIF_RB_RPTR_BASE_IDX                                                                 5
+#define regBIF_BX1_BIF_RB_WPTR                                                                          0x8e52
+#define regBIF_BX1_BIF_RB_WPTR_BASE_IDX                                                                 5
+#define regBIF_BX1_BIF_RB_WPTR_ADDR_HI                                                                  0x8e53
+#define regBIF_BX1_BIF_RB_WPTR_ADDR_HI_BASE_IDX                                                         5
+#define regBIF_BX1_BIF_RB_WPTR_ADDR_LO                                                                  0x8e54
+#define regBIF_BX1_BIF_RB_WPTR_ADDR_LO_BASE_IDX                                                         5
+#define regBIF_BX1_MAILBOX_INDEX                                                                        0x8e55
+#define regBIF_BX1_MAILBOX_INDEX_BASE_IDX                                                               5
+#define regBIF_BX1_BACO_AZ_ENHANCE_CTRL                                                                 0x8e61
+#define regBIF_BX1_BACO_AZ_ENHANCE_CTRL_BASE_IDX                                                        5
+#define regBIF_BX1_BIF_MP1_INTR_CTRL                                                                    0x8e62
+#define regBIF_BX1_BIF_MP1_INTR_CTRL_BASE_IDX                                                           5
+#define regBIF_BX1_BIF_PERSTB_PAD_CNTL                                                                  0x8e65
+#define regBIF_BX1_BIF_PERSTB_PAD_CNTL_BASE_IDX                                                         5
+#define regBIF_BX1_BIF_PX_EN_PAD_CNTL                                                                   0x8e66
+#define regBIF_BX1_BIF_PX_EN_PAD_CNTL_BASE_IDX                                                          5
+#define regBIF_BX1_BIF_REFPADKIN_PAD_CNTL                                                               0x8e67
+#define regBIF_BX1_BIF_REFPADKIN_PAD_CNTL_BASE_IDX                                                      5
+#define regBIF_BX1_BIF_CLKREQB_PAD_CNTL                                                                 0x8e68
+#define regBIF_BX1_BIF_CLKREQB_PAD_CNTL_BASE_IDX                                                        5
+#define regBIF_BX1_BIF_PWRBRK_PAD_CNTL                                                                  0x8e69
+#define regBIF_BX1_BIF_PWRBRK_PAD_CNTL_BASE_IDX                                                         5
+#define regBIF_BX1_BIF_GPUIOV_SCH_CFG_SIZE                                                              0x8e85
+#define regBIF_BX1_BIF_GPUIOV_SCH_CFG_SIZE_BASE_IDX                                                     5
+
+
+// addressBlock: nbif0_nbif0_bif_bx_pf_BIFPFVFDEC1
+// base address: 0x10120000
+#define regBIF_BX_PF1_BIF_BME_STATUS                                                                    0x8e0b
+#define regBIF_BX_PF1_BIF_BME_STATUS_BASE_IDX                                                           5
+#define regBIF_BX_PF1_BIF_ATOMIC_ERR_LOG                                                                0x8e0c
+#define regBIF_BX_PF1_BIF_ATOMIC_ERR_LOG_BASE_IDX                                                       5
+#define regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH                                              0x8e13
+#define regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH_BASE_IDX                                     5
+#define regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW                                               0x8e14
+#define regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW_BASE_IDX                                      5
+#define regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL                                                   0x8e15
+#define regBIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL_BASE_IDX                                          5
+#define regBIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL                                                      0x8e16
+#define regBIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL_BASE_IDX                                             5
+#define regBIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL                                                      0x8e17
+#define regBIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL_BASE_IDX                                             5
+#define regBIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL                                                 0x8e19
+#define regBIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL_BASE_IDX                                        5
+#define regBIF_BX_PF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL                                            0x8e1a
+#define regBIF_BX_PF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL_BASE_IDX                                   5
+#define regBIF_BX_PF1_GPU_HDP_FLUSH_REQ                                                                 0x8e26
+#define regBIF_BX_PF1_GPU_HDP_FLUSH_REQ_BASE_IDX                                                        5
+#define regBIF_BX_PF1_GPU_HDP_FLUSH_DONE                                                                0x8e27
+#define regBIF_BX_PF1_GPU_HDP_FLUSH_DONE_BASE_IDX                                                       5
+#define regBIF_BX_PF1_BIF_TRANS_PENDING                                                                 0x8e28
+#define regBIF_BX_PF1_BIF_TRANS_PENDING_BASE_IDX                                                        5
+#define regBIF_BX_PF1_NBIF_GFX_ADDR_LUT_BYPASS                                                          0x8e32
+#define regBIF_BX_PF1_NBIF_GFX_ADDR_LUT_BYPASS_BASE_IDX                                                 5
+#define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0                                                            0x8e56
+#define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0_BASE_IDX                                                   5
+#define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1                                                            0x8e57
+#define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1_BASE_IDX                                                   5
+#define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2                                                            0x8e58
+#define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2_BASE_IDX                                                   5
+#define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3                                                            0x8e59
+#define regBIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3_BASE_IDX                                                   5
+#define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0                                                            0x8e5a
+#define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0_BASE_IDX                                                   5
+#define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1                                                            0x8e5b
+#define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1_BASE_IDX                                                   5
+#define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2                                                            0x8e5c
+#define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2_BASE_IDX                                                   5
+#define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3                                                            0x8e5d
+#define regBIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3_BASE_IDX                                                   5
+#define regBIF_BX_PF1_MAILBOX_CONTROL                                                                   0x8e5e
+#define regBIF_BX_PF1_MAILBOX_CONTROL_BASE_IDX                                                          5
+#define regBIF_BX_PF1_MAILBOX_INT_CNTL                                                                  0x8e5f
+#define regBIF_BX_PF1_MAILBOX_INT_CNTL_BASE_IDX                                                         5
+#define regBIF_BX_PF1_BIF_VMHV_MAILBOX                                                                  0x8e60
+#define regBIF_BX_PF1_BIF_VMHV_MAILBOX_BASE_IDX                                                         5
+#define regBIF_BX_PF1_PARTITION_COMPUTE_CAP                                                             0x8e81
+#define regBIF_BX_PF1_PARTITION_COMPUTE_CAP_BASE_IDX                                                    5
+#define regBIF_BX_PF1_PARTITION_MEM_CAP                                                                 0x8e82
+#define regBIF_BX_PF1_PARTITION_MEM_CAP_BASE_IDX                                                        5
+#define regBIF_BX_PF1_PARTITION_COMPUTE_STATUS                                                          0x8e83
+#define regBIF_BX_PF1_PARTITION_COMPUTE_STATUS_BASE_IDX                                                 5
+#define regBIF_BX_PF1_PARTITION_MEM_STATUS                                                              0x8e84
+#define regBIF_BX_PF1_PARTITION_MEM_STATUS_BASE_IDX                                                     5
+
+
+// addressBlock: nbif0_nbif0_rcc_strap_BIFDEC1:1
+// base address: 0x10120000
+#define regRCC_STRAP2_RCC_BIF_STRAP0                                                                    0x8d20
+#define regRCC_STRAP2_RCC_BIF_STRAP0_BASE_IDX                                                           5
+#define regRCC_STRAP2_RCC_BIF_STRAP1                                                                    0x8d21
+#define regRCC_STRAP2_RCC_BIF_STRAP1_BASE_IDX                                                           5
+#define regRCC_STRAP2_RCC_BIF_STRAP10                                                                   0x8d22
+#define regRCC_STRAP2_RCC_BIF_STRAP10_BASE_IDX                                                          5
+#define regRCC_STRAP2_RCC_BIF_STRAP11                                                                   0x8d23
+#define regRCC_STRAP2_RCC_BIF_STRAP11_BASE_IDX                                                          5
+#define regRCC_STRAP2_RCC_BIF_STRAP12                                                                   0x8d24
+#define regRCC_STRAP2_RCC_BIF_STRAP12_BASE_IDX                                                          5
+#define regRCC_STRAP2_RCC_BIF_STRAP13                                                                   0x8d25
+#define regRCC_STRAP2_RCC_BIF_STRAP13_BASE_IDX                                                          5
+#define regRCC_STRAP2_RCC_BIF_STRAP2                                                                    0x8d26
+#define regRCC_STRAP2_RCC_BIF_STRAP2_BASE_IDX                                                           5
+#define regRCC_STRAP2_RCC_BIF_STRAP3                                                                    0x8d27
+#define regRCC_STRAP2_RCC_BIF_STRAP3_BASE_IDX                                                           5
+#define regRCC_STRAP2_RCC_BIF_STRAP4                                                                    0x8d28
+#define regRCC_STRAP2_RCC_BIF_STRAP4_BASE_IDX                                                           5
+#define regRCC_STRAP2_RCC_BIF_STRAP5                                                                    0x8d29
+#define regRCC_STRAP2_RCC_BIF_STRAP5_BASE_IDX                                                           5
+#define regRCC_STRAP2_RCC_BIF_STRAP6                                                                    0x8d2a
+#define regRCC_STRAP2_RCC_BIF_STRAP6_BASE_IDX                                                           5
+#define regRCC_STRAP2_RCC_BIF_STRAP7                                                                    0x8d2b
+#define regRCC_STRAP2_RCC_BIF_STRAP7_BASE_IDX                                                           5
+#define regRCC_STRAP2_RCC_BIF_STRAP8                                                                    0x8d2c
+#define regRCC_STRAP2_RCC_BIF_STRAP8_BASE_IDX                                                           5
+#define regRCC_STRAP2_RCC_BIF_STRAP9                                                                    0x8d2d
+#define regRCC_STRAP2_RCC_BIF_STRAP9_BASE_IDX                                                           5
+#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP0                                                              0x8d2e
+#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP0_BASE_IDX                                                     5
+#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP1                                                              0x8d2f
+#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP1_BASE_IDX                                                     5
+#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP10                                                             0x8d30
+#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP10_BASE_IDX                                                    5
+#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP11                                                             0x8d31
+#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP11_BASE_IDX                                                    5
+#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP12                                                             0x8d32
+#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP12_BASE_IDX                                                    5
+#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP13                                                             0x8d33
+#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP13_BASE_IDX                                                    5
+#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP14                                                             0x8d34
+#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP14_BASE_IDX                                                    5
+#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP15                                                             0x8d35
+#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP15_BASE_IDX                                                    5
+#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP16                                                             0x8d36
+#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP16_BASE_IDX                                                    5
+#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP17                                                             0x8d37
+#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP17_BASE_IDX                                                    5
+#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP18                                                             0x8d38
+#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP18_BASE_IDX                                                    5
+#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP2                                                              0x8d39
+#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP2_BASE_IDX                                                     5
+#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP3                                                              0x8d3a
+#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP3_BASE_IDX                                                     5
+#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP4                                                              0x8d3b
+#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP4_BASE_IDX                                                     5
+#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP5                                                              0x8d3c
+#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP5_BASE_IDX                                                     5
+#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP6                                                              0x8d3d
+#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP6_BASE_IDX                                                     5
+#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP7                                                              0x8d3e
+#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP7_BASE_IDX                                                     5
+#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP8                                                              0x8d3f
+#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP8_BASE_IDX                                                     5
+#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP9                                                              0x8d40
+#define regRCC_STRAP2_RCC_DEV0_PORT_STRAP9_BASE_IDX                                                     5
+#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP0                                                              0x8d41
+#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP0_BASE_IDX                                                     5
+#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP1                                                              0x8d42
+#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP1_BASE_IDX                                                     5
+#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP13                                                             0x8d43
+#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP13_BASE_IDX                                                    5
+#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP14                                                             0x8d44
+#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP14_BASE_IDX                                                    5
+#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP15                                                             0x8d45
+#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP15_BASE_IDX                                                    5
+#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP16                                                             0x8d46
+#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP16_BASE_IDX                                                    5
+#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP17                                                             0x8d47
+#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP17_BASE_IDX                                                    5
+#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP18                                                             0x8d48
+#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP18_BASE_IDX                                                    5
+#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP19                                                             0x8d49
+#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP19_BASE_IDX                                                    5
+#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP2                                                              0x8d4a
+#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP2_BASE_IDX                                                     5
+#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP22                                                             0x8d4b
+#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP22_BASE_IDX                                                    5
+#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP23                                                             0x8d4c
+#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP23_BASE_IDX                                                    5
+#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP24                                                             0x8d4d
+#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP24_BASE_IDX                                                    5
+#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP3                                                              0x8d4e
+#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP3_BASE_IDX                                                     5
+#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP4                                                              0x8d4f
+#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP4_BASE_IDX                                                     5
+#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP5                                                              0x8d50
+#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP5_BASE_IDX                                                     5
+#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP8                                                              0x8d51
+#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP8_BASE_IDX                                                     5
+#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP9                                                              0x8d52
+#define regRCC_STRAP2_RCC_DEV0_EPF0_STRAP9_BASE_IDX                                                     5
+#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP0                                                              0x8d53
+#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP0_BASE_IDX                                                     5
+#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP1                                                              0x8d54
+#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP1_BASE_IDX                                                     5
+#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP10                                                             0x8d55
+#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP10_BASE_IDX                                                    5
+#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP11                                                             0x8d56
+#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP11_BASE_IDX                                                    5
+#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP12                                                             0x8d57
+#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP12_BASE_IDX                                                    5
+#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP13                                                             0x8d58
+#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP13_BASE_IDX                                                    5
+#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP14                                                             0x8d59
+#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP14_BASE_IDX                                                    5
+#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP15                                                             0x8d5a
+#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP15_BASE_IDX                                                    5
+#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP16                                                             0x8d5b
+#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP16_BASE_IDX                                                    5
+#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP17                                                             0x8d5c
+#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP17_BASE_IDX                                                    5
+#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP18                                                             0x8d5d
+#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP18_BASE_IDX                                                    5
+#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP19                                                             0x8d5e
+#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP19_BASE_IDX                                                    5
+#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP2                                                              0x8d5f
+#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP2_BASE_IDX                                                     5
+#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP20                                                             0x8d60
+#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP20_BASE_IDX                                                    5
+#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP21                                                             0x8d61
+#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP21_BASE_IDX                                                    5
+#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP23                                                             0x8d62
+#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP23_BASE_IDX                                                    5
+#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP24                                                             0x8d63
+#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP24_BASE_IDX                                                    5
+#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP3                                                              0x8d64
+#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP3_BASE_IDX                                                     5
+#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP4                                                              0x8d65
+#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP4_BASE_IDX                                                     5
+#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP5                                                              0x8d66
+#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP5_BASE_IDX                                                     5
+#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP6                                                              0x8d67
+#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP6_BASE_IDX                                                     5
+#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP7                                                              0x8d68
+#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP7_BASE_IDX                                                     5
+#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP8                                                              0x8d69
+#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP8_BASE_IDX                                                     5
+#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP9                                                              0x8d6a
+#define regRCC_STRAP2_RCC_DEV0_EPF1_STRAP9_BASE_IDX                                                     5
+
+
+// addressBlock: nbif0_hpdma0_hpdma_private_hpdma_private_regblk
+// base address: 0x10100000
+#define regNBIF_SDP_PERF_COUNTER_2                                                                      0x100a
+#define regNBIF_SDP_PERF_COUNTER_2_BASE_IDX                                                             5
+#define regNBIF_SHUB_TODET_CLIENT_STATUS3                                                               0x10d1
+#define regNBIF_SHUB_TODET_CLIENT_STATUS3_BASE_IDX                                                      5
+#define regBIF_AER_ERR_LOG_DEV0_F0                                                                      0x10d5
+#define regBIF_AER_ERR_LOG_DEV0_F0_BASE_IDX                                                             5
+#define regBIF_AER_ERR_LOG_DEV0_F0_vf0                                                                  0x10d6
+#define regBIF_AER_ERR_LOG_DEV0_F0_vf0_BASE_IDX                                                         5
+#define regBIF_AER_ERR_LOG_DEV0_F0_vf1                                                                  0x10d7
+#define regBIF_AER_ERR_LOG_DEV0_F0_vf1_BASE_IDX                                                         5
+#define regBIF_AER_ERR_LOG_DEV0_F0_vf2                                                                  0x10d8
+#define regBIF_AER_ERR_LOG_DEV0_F0_vf2_BASE_IDX                                                         5
+#define regBIF_AER_ERR_LOG_DEV0_F0_vf3                                                                  0x10d9
+#define regBIF_AER_ERR_LOG_DEV0_F0_vf3_BASE_IDX                                                         5
+#define regBIF_AER_ERR_LOG_DEV0_F0_vf4                                                                  0x10da
+#define regBIF_AER_ERR_LOG_DEV0_F0_vf4_BASE_IDX                                                         5
+#define regBIF_AER_ERR_LOG_DEV0_F0_vf5                                                                  0x10db
+#define regBIF_AER_ERR_LOG_DEV0_F0_vf5_BASE_IDX                                                         5
+#define regBIF_AER_ERR_LOG_DEV0_F0_vf6                                                                  0x10dc
+#define regBIF_AER_ERR_LOG_DEV0_F0_vf6_BASE_IDX                                                         5
+#define regBIF_AER_ERR_LOG_DEV0_F0_vf7                                                                  0x10dd
+#define regBIF_AER_ERR_LOG_DEV0_F0_vf7_BASE_IDX                                                         5
+
+
+// addressBlock: nbif0_hphost0_hphost_private_hphost_private_regblk
+// base address: 0x10106000
+#define regNBIF_AON_SVA_DISABLE_SAD                                                                     0x189a
+#define regNBIF_AON_SVA_DISABLE_SAD_BASE_IDX                                                            5
+
+
+// addressBlock: nbif0_nbif0_gdc_dma_sion_SIONDEC
+// base address: 0x1400000
+#define regGDC_DMA_SION_CL0_RdRsp_BurstTarget_REG0                                                      0x4f7400
+#define regGDC_DMA_SION_CL0_RdRsp_BurstTarget_REG0_BASE_IDX                                             3
+#define regGDC_DMA_SION_CL0_RdRsp_BurstTarget_REG1                                                      0x4f7401
+#define regGDC_DMA_SION_CL0_RdRsp_BurstTarget_REG1_BASE_IDX                                             3
+#define regGDC_DMA_SION_CL0_RdRsp_TimeSlot_REG0                                                         0x4f7402
+#define regGDC_DMA_SION_CL0_RdRsp_TimeSlot_REG0_BASE_IDX                                                3
+#define regGDC_DMA_SION_CL0_RdRsp_TimeSlot_REG1                                                         0x4f7403
+#define regGDC_DMA_SION_CL0_RdRsp_TimeSlot_REG1_BASE_IDX                                                3
+#define regGDC_DMA_SION_CL0_WrRsp_BurstTarget_REG0                                                      0x4f7404
+#define regGDC_DMA_SION_CL0_WrRsp_BurstTarget_REG0_BASE_IDX                                             3
+#define regGDC_DMA_SION_CL0_WrRsp_BurstTarget_REG1                                                      0x4f7405
+#define regGDC_DMA_SION_CL0_WrRsp_BurstTarget_REG1_BASE_IDX                                             3
+#define regGDC_DMA_SION_CL0_WrRsp_TimeSlot_REG0                                                         0x4f7406
+#define regGDC_DMA_SION_CL0_WrRsp_TimeSlot_REG0_BASE_IDX                                                3
+#define regGDC_DMA_SION_CL0_WrRsp_TimeSlot_REG1                                                         0x4f7407
+#define regGDC_DMA_SION_CL0_WrRsp_TimeSlot_REG1_BASE_IDX                                                3
+#define regGDC_DMA_SION_CL0_Req_BurstTarget_REG0                                                        0x4f7408
+#define regGDC_DMA_SION_CL0_Req_BurstTarget_REG0_BASE_IDX                                               3
+#define regGDC_DMA_SION_CL0_Req_BurstTarget_REG1                                                        0x4f7409
+#define regGDC_DMA_SION_CL0_Req_BurstTarget_REG1_BASE_IDX                                               3
+#define regGDC_DMA_SION_CL0_Req_TimeSlot_REG0                                                           0x4f740a
+#define regGDC_DMA_SION_CL0_Req_TimeSlot_REG0_BASE_IDX                                                  3
+#define regGDC_DMA_SION_CL0_Req_TimeSlot_REG1                                                           0x4f740b
+#define regGDC_DMA_SION_CL0_Req_TimeSlot_REG1_BASE_IDX                                                  3
+#define regGDC_DMA_SION_CL0_ReqPoolCredit_Alloc_REG0                                                    0x4f740c
+#define regGDC_DMA_SION_CL0_ReqPoolCredit_Alloc_REG0_BASE_IDX                                           3
+#define regGDC_DMA_SION_CL0_ReqPoolCredit_Alloc_REG1                                                    0x4f740d
+#define regGDC_DMA_SION_CL0_ReqPoolCredit_Alloc_REG1_BASE_IDX                                           3
+#define regGDC_DMA_SION_CL0_DataPoolCredit_Alloc_REG0                                                   0x4f740e
+#define regGDC_DMA_SION_CL0_DataPoolCredit_Alloc_REG0_BASE_IDX                                          3
+#define regGDC_DMA_SION_CL0_DataPoolCredit_Alloc_REG1                                                   0x4f740f
+#define regGDC_DMA_SION_CL0_DataPoolCredit_Alloc_REG1_BASE_IDX                                          3
+#define regGDC_DMA_SION_CL0_RdRspPoolCredit_Alloc_REG0                                                  0x4f7410
+#define regGDC_DMA_SION_CL0_RdRspPoolCredit_Alloc_REG0_BASE_IDX                                         3
+#define regGDC_DMA_SION_CL0_RdRspPoolCredit_Alloc_REG1                                                  0x4f7411
+#define regGDC_DMA_SION_CL0_RdRspPoolCredit_Alloc_REG1_BASE_IDX                                         3
+#define regGDC_DMA_SION_CL0_WrRspPoolCredit_Alloc_REG0                                                  0x4f7412
+#define regGDC_DMA_SION_CL0_WrRspPoolCredit_Alloc_REG0_BASE_IDX                                         3
+#define regGDC_DMA_SION_CL0_WrRspPoolCredit_Alloc_REG1                                                  0x4f7413
+#define regGDC_DMA_SION_CL0_WrRspPoolCredit_Alloc_REG1_BASE_IDX                                         3
+#define regGDC_DMA_SION_CL1_RdRsp_BurstTarget_REG0                                                      0x4f7414
+#define regGDC_DMA_SION_CL1_RdRsp_BurstTarget_REG0_BASE_IDX                                             3
+#define regGDC_DMA_SION_CL1_RdRsp_BurstTarget_REG1                                                      0x4f7415
+#define regGDC_DMA_SION_CL1_RdRsp_BurstTarget_REG1_BASE_IDX                                             3
+#define regGDC_DMA_SION_CL1_RdRsp_TimeSlot_REG0                                                         0x4f7416
+#define regGDC_DMA_SION_CL1_RdRsp_TimeSlot_REG0_BASE_IDX                                                3
+#define regGDC_DMA_SION_CL1_RdRsp_TimeSlot_REG1                                                         0x4f7417
+#define regGDC_DMA_SION_CL1_RdRsp_TimeSlot_REG1_BASE_IDX                                                3
+#define regGDC_DMA_SION_CL1_WrRsp_BurstTarget_REG0                                                      0x4f7418
+#define regGDC_DMA_SION_CL1_WrRsp_BurstTarget_REG0_BASE_IDX                                             3
+#define regGDC_DMA_SION_CL1_WrRsp_BurstTarget_REG1                                                      0x4f7419
+#define regGDC_DMA_SION_CL1_WrRsp_BurstTarget_REG1_BASE_IDX                                             3
+#define regGDC_DMA_SION_CL1_WrRsp_TimeSlot_REG0                                                         0x4f741a
+#define regGDC_DMA_SION_CL1_WrRsp_TimeSlot_REG0_BASE_IDX                                                3
+#define regGDC_DMA_SION_CL1_WrRsp_TimeSlot_REG1                                                         0x4f741b
+#define regGDC_DMA_SION_CL1_WrRsp_TimeSlot_REG1_BASE_IDX                                                3
+#define regGDC_DMA_SION_CL1_Req_BurstTarget_REG0                                                        0x4f741c
+#define regGDC_DMA_SION_CL1_Req_BurstTarget_REG0_BASE_IDX                                               3
+#define regGDC_DMA_SION_CL1_Req_BurstTarget_REG1                                                        0x4f741d
+#define regGDC_DMA_SION_CL1_Req_BurstTarget_REG1_BASE_IDX                                               3
+#define regGDC_DMA_SION_CL1_Req_TimeSlot_REG0                                                           0x4f741e
+#define regGDC_DMA_SION_CL1_Req_TimeSlot_REG0_BASE_IDX                                                  3
+#define regGDC_DMA_SION_CL1_Req_TimeSlot_REG1                                                           0x4f741f
+#define regGDC_DMA_SION_CL1_Req_TimeSlot_REG1_BASE_IDX                                                  3
+#define regGDC_DMA_SION_CL1_ReqPoolCredit_Alloc_REG0                                                    0x4f7420
+#define regGDC_DMA_SION_CL1_ReqPoolCredit_Alloc_REG0_BASE_IDX                                           3
+#define regGDC_DMA_SION_CL1_ReqPoolCredit_Alloc_REG1                                                    0x4f7421
+#define regGDC_DMA_SION_CL1_ReqPoolCredit_Alloc_REG1_BASE_IDX                                           3
+#define regGDC_DMA_SION_CL1_DataPoolCredit_Alloc_REG0                                                   0x4f7422
+#define regGDC_DMA_SION_CL1_DataPoolCredit_Alloc_REG0_BASE_IDX                                          3
+#define regGDC_DMA_SION_CL1_DataPoolCredit_Alloc_REG1                                                   0x4f7423
+#define regGDC_DMA_SION_CL1_DataPoolCredit_Alloc_REG1_BASE_IDX                                          3
+#define regGDC_DMA_SION_CL1_RdRspPoolCredit_Alloc_REG0                                                  0x4f7424
+#define regGDC_DMA_SION_CL1_RdRspPoolCredit_Alloc_REG0_BASE_IDX                                         3
+#define regGDC_DMA_SION_CL1_RdRspPoolCredit_Alloc_REG1                                                  0x4f7425
+#define regGDC_DMA_SION_CL1_RdRspPoolCredit_Alloc_REG1_BASE_IDX                                         3
+#define regGDC_DMA_SION_CL1_WrRspPoolCredit_Alloc_REG0                                                  0x4f7426
+#define regGDC_DMA_SION_CL1_WrRspPoolCredit_Alloc_REG0_BASE_IDX                                         3
+#define regGDC_DMA_SION_CL1_WrRspPoolCredit_Alloc_REG1                                                  0x4f7427
+#define regGDC_DMA_SION_CL1_WrRspPoolCredit_Alloc_REG1_BASE_IDX                                         3
+#define regGDC_DMA_SION_CL2_RdRsp_BurstTarget_REG0                                                      0x4f7428
+#define regGDC_DMA_SION_CL2_RdRsp_BurstTarget_REG0_BASE_IDX                                             3
+#define regGDC_DMA_SION_CL2_RdRsp_BurstTarget_REG1                                                      0x4f7429
+#define regGDC_DMA_SION_CL2_RdRsp_BurstTarget_REG1_BASE_IDX                                             3
+#define regGDC_DMA_SION_CL2_RdRsp_TimeSlot_REG0                                                         0x4f742a
+#define regGDC_DMA_SION_CL2_RdRsp_TimeSlot_REG0_BASE_IDX                                                3
+#define regGDC_DMA_SION_CL2_RdRsp_TimeSlot_REG1                                                         0x4f742b
+#define regGDC_DMA_SION_CL2_RdRsp_TimeSlot_REG1_BASE_IDX                                                3
+#define regGDC_DMA_SION_CL2_WrRsp_BurstTarget_REG0                                                      0x4f742c
+#define regGDC_DMA_SION_CL2_WrRsp_BurstTarget_REG0_BASE_IDX                                             3
+#define regGDC_DMA_SION_CL2_WrRsp_BurstTarget_REG1                                                      0x4f742d
+#define regGDC_DMA_SION_CL2_WrRsp_BurstTarget_REG1_BASE_IDX                                             3
+#define regGDC_DMA_SION_CL2_WrRsp_TimeSlot_REG0                                                         0x4f742e
+#define regGDC_DMA_SION_CL2_WrRsp_TimeSlot_REG0_BASE_IDX                                                3
+#define regGDC_DMA_SION_CL2_WrRsp_TimeSlot_REG1                                                         0x4f742f
+#define regGDC_DMA_SION_CL2_WrRsp_TimeSlot_REG1_BASE_IDX                                                3
+#define regGDC_DMA_SION_CL2_Req_BurstTarget_REG0                                                        0x4f7430
+#define regGDC_DMA_SION_CL2_Req_BurstTarget_REG0_BASE_IDX                                               3
+#define regGDC_DMA_SION_CL2_Req_BurstTarget_REG1                                                        0x4f7431
+#define regGDC_DMA_SION_CL2_Req_BurstTarget_REG1_BASE_IDX                                               3
+#define regGDC_DMA_SION_CL2_Req_TimeSlot_REG0                                                           0x4f7432
+#define regGDC_DMA_SION_CL2_Req_TimeSlot_REG0_BASE_IDX                                                  3
+#define regGDC_DMA_SION_CL2_Req_TimeSlot_REG1                                                           0x4f7433
+#define regGDC_DMA_SION_CL2_Req_TimeSlot_REG1_BASE_IDX                                                  3
+#define regGDC_DMA_SION_CL2_ReqPoolCredit_Alloc_REG0                                                    0x4f7434
+#define regGDC_DMA_SION_CL2_ReqPoolCredit_Alloc_REG0_BASE_IDX                                           3
+#define regGDC_DMA_SION_CL2_ReqPoolCredit_Alloc_REG1                                                    0x4f7435
+#define regGDC_DMA_SION_CL2_ReqPoolCredit_Alloc_REG1_BASE_IDX                                           3
+#define regGDC_DMA_SION_CL2_DataPoolCredit_Alloc_REG0                                                   0x4f7436
+#define regGDC_DMA_SION_CL2_DataPoolCredit_Alloc_REG0_BASE_IDX                                          3
+#define regGDC_DMA_SION_CL2_DataPoolCredit_Alloc_REG1                                                   0x4f7437
+#define regGDC_DMA_SION_CL2_DataPoolCredit_Alloc_REG1_BASE_IDX                                          3
+#define regGDC_DMA_SION_CL2_RdRspPoolCredit_Alloc_REG0                                                  0x4f7438
+#define regGDC_DMA_SION_CL2_RdRspPoolCredit_Alloc_REG0_BASE_IDX                                         3
+#define regGDC_DMA_SION_CL2_RdRspPoolCredit_Alloc_REG1                                                  0x4f7439
+#define regGDC_DMA_SION_CL2_RdRspPoolCredit_Alloc_REG1_BASE_IDX                                         3
+#define regGDC_DMA_SION_CL2_WrRspPoolCredit_Alloc_REG0                                                  0x4f743a
+#define regGDC_DMA_SION_CL2_WrRspPoolCredit_Alloc_REG0_BASE_IDX                                         3
+#define regGDC_DMA_SION_CL2_WrRspPoolCredit_Alloc_REG1                                                  0x4f743b
+#define regGDC_DMA_SION_CL2_WrRspPoolCredit_Alloc_REG1_BASE_IDX                                         3
+#define regGDC_DMA_SION_CNTL_REG0                                                                       0x4f743c
+#define regGDC_DMA_SION_CNTL_REG0_BASE_IDX                                                              3
+#define regGDC_DMA_SION_CNTL_REG1                                                                       0x4f743d
+#define regGDC_DMA_SION_CNTL_REG1_BASE_IDX                                                              3
+
+
+// addressBlock: nbif0_nbif0_gdc_hst_sion_SIONDEC
+// base address: 0x1400000
+#define regGDC_HST_SION_CL0_RdRsp_BurstTarget_REG0                                                      0x4f7600
+#define regGDC_HST_SION_CL0_RdRsp_BurstTarget_REG0_BASE_IDX                                             3
+#define regGDC_HST_SION_CL0_RdRsp_BurstTarget_REG1                                                      0x4f7601
+#define regGDC_HST_SION_CL0_RdRsp_BurstTarget_REG1_BASE_IDX                                             3
+#define regGDC_HST_SION_CL0_RdRsp_TimeSlot_REG0                                                         0x4f7602
+#define regGDC_HST_SION_CL0_RdRsp_TimeSlot_REG0_BASE_IDX                                                3
+#define regGDC_HST_SION_CL0_RdRsp_TimeSlot_REG1                                                         0x4f7603
+#define regGDC_HST_SION_CL0_RdRsp_TimeSlot_REG1_BASE_IDX                                                3
+#define regGDC_HST_SION_CL0_WrRsp_BurstTarget_REG0                                                      0x4f7604
+#define regGDC_HST_SION_CL0_WrRsp_BurstTarget_REG0_BASE_IDX                                             3
+#define regGDC_HST_SION_CL0_WrRsp_BurstTarget_REG1                                                      0x4f7605
+#define regGDC_HST_SION_CL0_WrRsp_BurstTarget_REG1_BASE_IDX                                             3
+#define regGDC_HST_SION_CL0_WrRsp_TimeSlot_REG0                                                         0x4f7606
+#define regGDC_HST_SION_CL0_WrRsp_TimeSlot_REG0_BASE_IDX                                                3
+#define regGDC_HST_SION_CL0_WrRsp_TimeSlot_REG1                                                         0x4f7607
+#define regGDC_HST_SION_CL0_WrRsp_TimeSlot_REG1_BASE_IDX                                                3
+#define regGDC_HST_SION_CL0_Req_BurstTarget_REG0                                                        0x4f7608
+#define regGDC_HST_SION_CL0_Req_BurstTarget_REG0_BASE_IDX                                               3
+#define regGDC_HST_SION_CL0_Req_BurstTarget_REG1                                                        0x4f7609
+#define regGDC_HST_SION_CL0_Req_BurstTarget_REG1_BASE_IDX                                               3
+#define regGDC_HST_SION_CL0_Req_TimeSlot_REG0                                                           0x4f760a
+#define regGDC_HST_SION_CL0_Req_TimeSlot_REG0_BASE_IDX                                                  3
+#define regGDC_HST_SION_CL0_Req_TimeSlot_REG1                                                           0x4f760b
+#define regGDC_HST_SION_CL0_Req_TimeSlot_REG1_BASE_IDX                                                  3
+#define regGDC_HST_SION_CL0_ReqPoolCredit_Alloc_REG0                                                    0x4f760c
+#define regGDC_HST_SION_CL0_ReqPoolCredit_Alloc_REG0_BASE_IDX                                           3
+#define regGDC_HST_SION_CL0_ReqPoolCredit_Alloc_REG1                                                    0x4f760d
+#define regGDC_HST_SION_CL0_ReqPoolCredit_Alloc_REG1_BASE_IDX                                           3
+#define regGDC_HST_SION_CL0_DataPoolCredit_Alloc_REG0                                                   0x4f760e
+#define regGDC_HST_SION_CL0_DataPoolCredit_Alloc_REG0_BASE_IDX                                          3
+#define regGDC_HST_SION_CL0_DataPoolCredit_Alloc_REG1                                                   0x4f760f
+#define regGDC_HST_SION_CL0_DataPoolCredit_Alloc_REG1_BASE_IDX                                          3
+#define regGDC_HST_SION_CL0_RdRspPoolCredit_Alloc_REG0                                                  0x4f7610
+#define regGDC_HST_SION_CL0_RdRspPoolCredit_Alloc_REG0_BASE_IDX                                         3
+#define regGDC_HST_SION_CL0_RdRspPoolCredit_Alloc_REG1                                                  0x4f7611
+#define regGDC_HST_SION_CL0_RdRspPoolCredit_Alloc_REG1_BASE_IDX                                         3
+#define regGDC_HST_SION_CL0_WrRspPoolCredit_Alloc_REG0                                                  0x4f7612
+#define regGDC_HST_SION_CL0_WrRspPoolCredit_Alloc_REG0_BASE_IDX                                         3
+#define regGDC_HST_SION_CL0_WrRspPoolCredit_Alloc_REG1                                                  0x4f7613
+#define regGDC_HST_SION_CL0_WrRspPoolCredit_Alloc_REG1_BASE_IDX                                         3
+#define regGDC_HST_SION_CL1_RdRsp_BurstTarget_REG0                                                      0x4f7614
+#define regGDC_HST_SION_CL1_RdRsp_BurstTarget_REG0_BASE_IDX                                             3
+#define regGDC_HST_SION_CL1_RdRsp_BurstTarget_REG1                                                      0x4f7615
+#define regGDC_HST_SION_CL1_RdRsp_BurstTarget_REG1_BASE_IDX                                             3
+#define regGDC_HST_SION_CL1_RdRsp_TimeSlot_REG0                                                         0x4f7616
+#define regGDC_HST_SION_CL1_RdRsp_TimeSlot_REG0_BASE_IDX                                                3
+#define regGDC_HST_SION_CL1_RdRsp_TimeSlot_REG1                                                         0x4f7617
+#define regGDC_HST_SION_CL1_RdRsp_TimeSlot_REG1_BASE_IDX                                                3
+#define regGDC_HST_SION_CL1_WrRsp_BurstTarget_REG0                                                      0x4f7618
+#define regGDC_HST_SION_CL1_WrRsp_BurstTarget_REG0_BASE_IDX                                             3
+#define regGDC_HST_SION_CL1_WrRsp_BurstTarget_REG1                                                      0x4f7619
+#define regGDC_HST_SION_CL1_WrRsp_BurstTarget_REG1_BASE_IDX                                             3
+#define regGDC_HST_SION_CL1_WrRsp_TimeSlot_REG0                                                         0x4f761a
+#define regGDC_HST_SION_CL1_WrRsp_TimeSlot_REG0_BASE_IDX                                                3
+#define regGDC_HST_SION_CL1_WrRsp_TimeSlot_REG1                                                         0x4f761b
+#define regGDC_HST_SION_CL1_WrRsp_TimeSlot_REG1_BASE_IDX                                                3
+#define regGDC_HST_SION_CL1_Req_BurstTarget_REG0                                                        0x4f761c
+#define regGDC_HST_SION_CL1_Req_BurstTarget_REG0_BASE_IDX                                               3
+#define regGDC_HST_SION_CL1_Req_BurstTarget_REG1                                                        0x4f761d
+#define regGDC_HST_SION_CL1_Req_BurstTarget_REG1_BASE_IDX                                               3
+#define regGDC_HST_SION_CL1_Req_TimeSlot_REG0                                                           0x4f761e
+#define regGDC_HST_SION_CL1_Req_TimeSlot_REG0_BASE_IDX                                                  3
+#define regGDC_HST_SION_CL1_Req_TimeSlot_REG1                                                           0x4f761f
+#define regGDC_HST_SION_CL1_Req_TimeSlot_REG1_BASE_IDX                                                  3
+#define regGDC_HST_SION_CL1_ReqPoolCredit_Alloc_REG0                                                    0x4f7620
+#define regGDC_HST_SION_CL1_ReqPoolCredit_Alloc_REG0_BASE_IDX                                           3
+#define regGDC_HST_SION_CL1_ReqPoolCredit_Alloc_REG1                                                    0x4f7621
+#define regGDC_HST_SION_CL1_ReqPoolCredit_Alloc_REG1_BASE_IDX                                           3
+#define regGDC_HST_SION_CL1_DataPoolCredit_Alloc_REG0                                                   0x4f7622
+#define regGDC_HST_SION_CL1_DataPoolCredit_Alloc_REG0_BASE_IDX                                          3
+#define regGDC_HST_SION_CL1_DataPoolCredit_Alloc_REG1                                                   0x4f7623
+#define regGDC_HST_SION_CL1_DataPoolCredit_Alloc_REG1_BASE_IDX                                          3
+#define regGDC_HST_SION_CL1_RdRspPoolCredit_Alloc_REG0                                                  0x4f7624
+#define regGDC_HST_SION_CL1_RdRspPoolCredit_Alloc_REG0_BASE_IDX                                         3
+#define regGDC_HST_SION_CL1_RdRspPoolCredit_Alloc_REG1                                                  0x4f7625
+#define regGDC_HST_SION_CL1_RdRspPoolCredit_Alloc_REG1_BASE_IDX                                         3
+#define regGDC_HST_SION_CL1_WrRspPoolCredit_Alloc_REG0                                                  0x4f7626
+#define regGDC_HST_SION_CL1_WrRspPoolCredit_Alloc_REG0_BASE_IDX                                         3
+#define regGDC_HST_SION_CL1_WrRspPoolCredit_Alloc_REG1                                                  0x4f7627
+#define regGDC_HST_SION_CL1_WrRspPoolCredit_Alloc_REG1_BASE_IDX                                         3
+#define regGDC_HST_SION_CNTL_REG0                                                                       0x4f7628
+#define regGDC_HST_SION_CNTL_REG0_BASE_IDX                                                              3
+#define regGDC_HST_SION_CNTL_REG1                                                                       0x4f7629
+#define regGDC_HST_SION_CNTL_REG1_BASE_IDX                                                              3
+
+
+// addressBlock: nbif0_nbif0_gdc_GDCDEC
+// base address: 0x1400000
+#define regGDC1_NGDC_SDP_PORT_CTRL                                                                      0x4f0aa0
+#define regGDC1_NGDC_SDP_PORT_CTRL_BASE_IDX                                                             3
+#define regGDC1_SHUB_REGS_IF_CTL                                                                        0x4f0aa1
+#define regGDC1_SHUB_REGS_IF_CTL_BASE_IDX                                                               3
+#define regGDC1_NGDC_MGCG_CTRL                                                                          0x4f0aa7
+#define regGDC1_NGDC_MGCG_CTRL_BASE_IDX                                                                 3
+#define regGDC1_S2A_MISC_CNTL                                                                           0x4f0aa8
+#define regGDC1_S2A_MISC_CNTL_BASE_IDX                                                                  3
+#define regGDC1_NGDC_MCA_SMN_CTRL0                                                                      0x4f0aab
+#define regGDC1_NGDC_MCA_SMN_CTRL0_BASE_IDX                                                             3
+#define regGDC1_NGDC_EARLY_WAKEUP_CTRL                                                                  0x4f0aac
+#define regGDC1_NGDC_EARLY_WAKEUP_CTRL_BASE_IDX                                                         3
+#define regGDC1_GDC_GDCCLK_S2A_ERR_RSP_CNTL                                                             0x4f0ab8
+#define regGDC1_GDC_GDCCLK_S2A_ERR_RSP_CNTL_BASE_IDX                                                    3
+#define regGDC1_GDC_DMA_SION_PCTRL                                                                      0x4f0ab9
+#define regGDC1_GDC_DMA_SION_PCTRL_BASE_IDX                                                             3
+#define regGDC1_NGDC_MP4SDP_CNTL                                                                        0x4f0abb
+#define regGDC1_NGDC_MP4SDP_CNTL_BASE_IDX                                                               3
+#define regGDC1_DOORBELL_VCN_TARGET_VF0                                                                 0x4f0b13
+#define regGDC1_DOORBELL_VCN_TARGET_VF0_BASE_IDX                                                        3
+#define regGDC1_DOORBELL_VCN_TARGET_VF1                                                                 0x4f0b13
+#define regGDC1_DOORBELL_VCN_TARGET_VF1_BASE_IDX                                                        3
+#define regGDC1_DOORBELL_VCN_TARGET_VF2                                                                 0x4f0b14
+#define regGDC1_DOORBELL_VCN_TARGET_VF2_BASE_IDX                                                        3
+#define regGDC1_DOORBELL_VCN_TARGET_VF3                                                                 0x4f0b14
+#define regGDC1_DOORBELL_VCN_TARGET_VF3_BASE_IDX                                                        3
+#define regGDC1_DOORBELL_VCN_TARGET_VF4                                                                 0x4f0b15
+#define regGDC1_DOORBELL_VCN_TARGET_VF4_BASE_IDX                                                        3
+#define regGDC1_DOORBELL_VCN_TARGET_VF5                                                                 0x4f0b15
+#define regGDC1_DOORBELL_VCN_TARGET_VF5_BASE_IDX                                                        3
+#define regGDC1_DOORBELL_VCN_TARGET_VF6                                                                 0x4f0b16
+#define regGDC1_DOORBELL_VCN_TARGET_VF6_BASE_IDX                                                        3
+#define regGDC1_DOORBELL_VCN_TARGET_VF7                                                                 0x4f0b16
+#define regGDC1_DOORBELL_VCN_TARGET_VF7_BASE_IDX                                                        3
+#define regGDC1_DOORBELL_ACCESS_EN_PF                                                                   0x4f0b17
+#define regGDC1_DOORBELL_ACCESS_EN_PF_BASE_IDX                                                          3
+#define regGDC1_DOORBELL_ACCESS_EN_VF0                                                                  0x4f0b17
+#define regGDC1_DOORBELL_ACCESS_EN_VF0_BASE_IDX                                                         3
+#define regGDC1_DOORBELL_ACCESS_EN_VF1                                                                  0x4f0b18
+#define regGDC1_DOORBELL_ACCESS_EN_VF1_BASE_IDX                                                         3
+#define regGDC1_DOORBELL_ACCESS_EN_VF2                                                                  0x4f0b18
+#define regGDC1_DOORBELL_ACCESS_EN_VF2_BASE_IDX                                                         3
+#define regGDC1_DOORBELL_ACCESS_EN_VF3                                                                  0x4f0b19
+#define regGDC1_DOORBELL_ACCESS_EN_VF3_BASE_IDX                                                         3
+#define regGDC1_DOORBELL_ACCESS_EN_VF4                                                                  0x4f0b19
+#define regGDC1_DOORBELL_ACCESS_EN_VF4_BASE_IDX                                                         3
+#define regGDC1_DOORBELL_ACCESS_EN_VF5                                                                  0x4f0b1a
+#define regGDC1_DOORBELL_ACCESS_EN_VF5_BASE_IDX                                                         3
+#define regGDC1_DOORBELL_ACCESS_EN_VF6                                                                  0x4f0b1a
+#define regGDC1_DOORBELL_ACCESS_EN_VF6_BASE_IDX                                                         3
+#define regGDC1_DOORBELL_ACCESS_EN_VF7                                                                  0x4f0b1b
+#define regGDC1_DOORBELL_ACCESS_EN_VF7_BASE_IDX                                                         3
+#define regGDC1_NGDC_CNDI_BUS_PORT_CTRL                                                                 0x4f0b1c
+#define regGDC1_NGDC_CNDI_BUS_PORT_CTRL_BASE_IDX                                                        3
+#define regGDC1_NGDC_CNDI_BUS_POOL_CRED_CTRL                                                            0x4f0b1d
+#define regGDC1_NGDC_CNDI_BUS_POOL_CRED_CTRL_BASE_IDX                                                   3
+
+
+// addressBlock: nbif0_nbif0_gdc_ras_gdc_ras_regblk
+// base address: 0x1400000
+#define regGDCSOC_ERR_RSP_CNTL                                                                          0x4f5c00
+#define regGDCSOC_ERR_RSP_CNTL_BASE_IDX                                                                 3
+#define regGDCSOC_RAS_CENTRAL_STATUS                                                                    0x4f5c10
+#define regGDCSOC_RAS_CENTRAL_STATUS_BASE_IDX                                                           3
+#define regGDCSOC_RAS_LEAF0_CTRL                                                                        0x4f5c20
+#define regGDCSOC_RAS_LEAF0_CTRL_BASE_IDX                                                               3
+#define regGDCSOC_RAS_LEAF1_CTRL                                                                        0x4f5c21
+#define regGDCSOC_RAS_LEAF1_CTRL_BASE_IDX                                                               3
+#define regGDCSOC_RAS_LEAF2_CTRL                                                                        0x4f5c22
+#define regGDCSOC_RAS_LEAF2_CTRL_BASE_IDX                                                               3
+#define regGDCSOC_RAS_LEAF3_CTRL                                                                        0x4f5c23
+#define regGDCSOC_RAS_LEAF3_CTRL_BASE_IDX                                                               3
+#define regGDCSOC_RAS_LEAF4_CTRL                                                                        0x4f5c24
+#define regGDCSOC_RAS_LEAF4_CTRL_BASE_IDX                                                               3
+#define regGDCSOC_RAS_LEAF5_CTRL                                                                        0x4f5c25
+#define regGDCSOC_RAS_LEAF5_CTRL_BASE_IDX                                                               3
+#define regGDCSOC_RAS_LEAF6_CTRL                                                                        0x4f5c26
+#define regGDCSOC_RAS_LEAF6_CTRL_BASE_IDX                                                               3
+#define regGDCSOC_RAS_LEAF7_CTRL                                                                        0x4f5c27
+#define regGDCSOC_RAS_LEAF7_CTRL_BASE_IDX                                                               3
+#define regGDCSOC_RAS_LEAF8_CTRL                                                                        0x4f5c28
+#define regGDCSOC_RAS_LEAF8_CTRL_BASE_IDX                                                               3
+#define regGDCSOC_RAS_LEAF9_CTRL                                                                        0x4f5c29
+#define regGDCSOC_RAS_LEAF9_CTRL_BASE_IDX                                                               3
+#define regGDCSOC_RAS_LEAF10_CTRL                                                                       0x4f5c2a
+#define regGDCSOC_RAS_LEAF10_CTRL_BASE_IDX                                                              3
+#define regGDCSOC_RAS_LEAF11_CTRL                                                                       0x4f5c2b
+#define regGDCSOC_RAS_LEAF11_CTRL_BASE_IDX                                                              3
+#define regGDCSOC_RAS_LEAF12_CTRL                                                                       0x4f5c2c
+#define regGDCSOC_RAS_LEAF12_CTRL_BASE_IDX                                                              3
+#define regGDCSOC_RAS_LEAF13_CTRL                                                                       0x4f5c2d
+#define regGDCSOC_RAS_LEAF13_CTRL_BASE_IDX                                                              3
+#define regGDCSOC_RAS_LEAF0_STATUS                                                                      0x4f5c30
+#define regGDCSOC_RAS_LEAF0_STATUS_BASE_IDX                                                             3
+#define regGDCSOC_RAS_LEAF1_STATUS                                                                      0x4f5c31
+#define regGDCSOC_RAS_LEAF1_STATUS_BASE_IDX                                                             3
+#define regGDCSOC_RAS_LEAF2_STATUS                                                                      0x4f5c32
+#define regGDCSOC_RAS_LEAF2_STATUS_BASE_IDX                                                             3
+#define regGDCSOC_RAS_LEAF3_STATUS                                                                      0x4f5c33
+#define regGDCSOC_RAS_LEAF3_STATUS_BASE_IDX                                                             3
+#define regGDCSOC_RAS_LEAF4_STATUS                                                                      0x4f5c34
+#define regGDCSOC_RAS_LEAF4_STATUS_BASE_IDX                                                             3
+#define regGDCSOC_RAS_LEAF5_STATUS                                                                      0x4f5c35
+#define regGDCSOC_RAS_LEAF5_STATUS_BASE_IDX                                                             3
+#define regGDCSOC_RAS_LEAF6_STATUS                                                                      0x4f5c36
+#define regGDCSOC_RAS_LEAF6_STATUS_BASE_IDX                                                             3
+#define regGDCSOC_RAS_LEAF7_STATUS                                                                      0x4f5c37
+#define regGDCSOC_RAS_LEAF7_STATUS_BASE_IDX                                                             3
+#define regGDCSOC_RAS_LEAF8_STATUS                                                                      0x4f5c38
+#define regGDCSOC_RAS_LEAF8_STATUS_BASE_IDX                                                             3
+#define regGDCSOC_RAS_LEAF9_STATUS                                                                      0x4f5c39
+#define regGDCSOC_RAS_LEAF9_STATUS_BASE_IDX                                                             3
+#define regGDCSOC_RAS_LEAF10_STATUS                                                                     0x4f5c3a
+#define regGDCSOC_RAS_LEAF10_STATUS_BASE_IDX                                                            3
+#define regGDCSOC_RAS_LEAF11_STATUS                                                                     0x4f5c3b
+#define regGDCSOC_RAS_LEAF11_STATUS_BASE_IDX                                                            3
+#define regGDCSOC_RAS_LEAF12_STATUS                                                                     0x4f5c3c
+#define regGDCSOC_RAS_LEAF12_STATUS_BASE_IDX                                                            3
+#define regGDCSOC_RAS_LEAF13_STATUS                                                                     0x4f5c3d
+#define regGDCSOC_RAS_LEAF13_STATUS_BASE_IDX                                                            3
+
+
+// addressBlock: nbif0_nbif0_gdc_sec_GDCSEC_DEC
+// base address: 0x1400000
+#define regGDC_SEC_MCA_SMN_CTRL0                                                                        0x4f7001
+#define regGDC_SEC_MCA_SMN_CTRL0_BASE_IDX                                                               3
+#define regGDC_SEC_MCA_SMN_CTRL1                                                                        0x4f7002
+#define regGDC_SEC_MCA_SMN_CTRL1_BASE_IDX                                                               3
+#define regXCD_DOORBELL_FENCE                                                                           0x4f7003
+#define regXCD_DOORBELL_FENCE_BASE_IDX                                                                  3
+#define regSHUB_PWRBRK_DEGLITCH                                                                         0x4f7004
+#define regSHUB_PWRBRK_DEGLITCH_BASE_IDX                                                                3
+#define regSHUB_DIE_CTRL                                                                                0x4f7005
+#define regSHUB_DIE_CTRL_BASE_IDX                                                                       3
+#define regGDC_A2S_ROUTING_TABLE_SECLVL_TRUST_LEVEL                                                     0x4f700a
+#define regGDC_A2S_ROUTING_TABLE_SECLVL_TRUST_LEVEL_BASE_IDX                                            3
+#define regXCD_DOORBELL_FENCE_1                                                                         0x4f700b
+#define regXCD_DOORBELL_FENCE_1_BASE_IDX                                                                3
+#define regNGDC_CNDI_DOORBELL_REQUSER_0                                                                 0x4f700c
+#define regNGDC_CNDI_DOORBELL_REQUSER_0_BASE_IDX                                                        3
+#define regNGDC_CNDI_DOORBELL_REQUSER_1                                                                 0x4f700d
+#define regNGDC_CNDI_DOORBELL_REQUSER_1_BASE_IDX                                                        3
+#define regNGDC_CNDI_DOORBELL_REQUSER_2                                                                 0x4f700e
+#define regNGDC_CNDI_DOORBELL_REQUSER_2_BASE_IDX                                                        3
+#define regNGDC_CNDI_DOORBELL_REQUSER_3                                                                 0x4f700f
+#define regNGDC_CNDI_DOORBELL_REQUSER_3_BASE_IDX                                                        3
+#define regNGDC_CNDI_DOORBELL_REQUSER_4                                                                 0x4f7010
+#define regNGDC_CNDI_DOORBELL_REQUSER_4_BASE_IDX                                                        3
+#define regNGDC_CNDI_DOORBELL_REQUSER_5                                                                 0x4f7011
+#define regNGDC_CNDI_DOORBELL_REQUSER_5_BASE_IDX                                                        3
+#define regNGDC_CNDI_DOORBELL_REQADDR_32_33BIT_0                                                        0x4f7012
+#define regNGDC_CNDI_DOORBELL_REQADDR_32_33BIT_0_BASE_IDX                                               3
+#define regNGDC_CNDI_DOORBELL_REQADDR_32_33BIT_1                                                        0x4f7013
+#define regNGDC_CNDI_DOORBELL_REQADDR_32_33BIT_1_BASE_IDX                                               3
+
+
+// addressBlock: nbif0_nbif0_gdc_rst_GDCRST_DEC
+// base address: 0x1400000
+#define regSHUB_PF_FLR_RST                                                                              0x4f7800
+#define regSHUB_PF_FLR_RST_BASE_IDX                                                                     3
+#define regSHUB_GFX_DRV_VPU_RST                                                                         0x4f7801
+#define regSHUB_GFX_DRV_VPU_RST_BASE_IDX                                                                3
+#define regSHUB_LINK_RESET                                                                              0x4f7802
+#define regSHUB_LINK_RESET_BASE_IDX                                                                     3
+#define regSHUB_HST_NIC400_SW_CTRL_RESET                                                                0x4f7803
+#define regSHUB_HST_NIC400_SW_CTRL_RESET_BASE_IDX                                                       3
+#define regSHUB_DEV0_PF0_VF_FLR_RST                                                                     0x4f7808
+#define regSHUB_DEV0_PF0_VF_FLR_RST_BASE_IDX                                                            3
+#define regSHUB_DEV0_PF1_VF_FLR_RST                                                                     0x4f7809
+#define regSHUB_DEV0_PF1_VF_FLR_RST_BASE_IDX                                                            3
+#define regSHUB_HARD_RST_CTRL                                                                           0x4f7810
+#define regSHUB_HARD_RST_CTRL_BASE_IDX                                                                  3
+#define regSHUB_SOFT_RST_CTRL                                                                           0x4f7811
+#define regSHUB_SOFT_RST_CTRL_BASE_IDX                                                                  3
+#define regSHUB_SDP_PORT_RST                                                                            0x4f7812
+#define regSHUB_SDP_PORT_RST_BASE_IDX                                                                   3
+#define regSHUB_RST_MISC_TRL                                                                            0x4f7813
+#define regSHUB_RST_MISC_TRL_BASE_IDX                                                                   3
+
+
+// addressBlock: nbif0_nbif0_gdc_s2a_GDCS2A_DEC
+// base address: 0x1400000
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL                                                           0x4f0aeb
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL_BASE_IDX                                                  3
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL1                                                          0x4f0aec
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL1_BASE_IDX                                                 3
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL                                                           0x4f0aed
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL_BASE_IDX                                                  3
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL1                                                          0x4f0aee
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL1_BASE_IDX                                                 3
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL                                                           0x4f0aef
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL_BASE_IDX                                                  3
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL1                                                          0x4f0af0
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL1_BASE_IDX                                                 3
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL                                                           0x4f0af1
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL_BASE_IDX                                                  3
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL1                                                          0x4f0af2
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL1_BASE_IDX                                                 3
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL                                                           0x4f0af3
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL_BASE_IDX                                                  3
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL1                                                          0x4f0af4
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL1_BASE_IDX                                                 3
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL                                                           0x4f0af5
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL_BASE_IDX                                                  3
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL1                                                          0x4f0af6
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL1_BASE_IDX                                                 3
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL                                                           0x4f0af7
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL_BASE_IDX                                                  3
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL1                                                          0x4f0af8
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL1_BASE_IDX                                                 3
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL                                                           0x4f0af9
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL_BASE_IDX                                                  3
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL1                                                          0x4f0afa
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL1_BASE_IDX                                                 3
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL                                                           0x4f0afb
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL_BASE_IDX                                                  3
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL1                                                          0x4f0afc
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL1_BASE_IDX                                                 3
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL                                                           0x4f0afd
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL_BASE_IDX                                                  3
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL1                                                          0x4f0afe
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL1_BASE_IDX                                                 3
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL                                                          0x4f0aff
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL_BASE_IDX                                                 3
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL1                                                         0x4f0b00
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL1_BASE_IDX                                                3
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL                                                          0x4f0b01
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL_BASE_IDX                                                 3
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL1                                                         0x4f0b02
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL1_BASE_IDX                                                3
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL                                                          0x4f0b03
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL_BASE_IDX                                                 3
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL1                                                         0x4f0b04
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL1_BASE_IDX                                                3
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL                                                          0x4f0b05
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL_BASE_IDX                                                 3
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL1                                                         0x4f0b06
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL1_BASE_IDX                                                3
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL                                                          0x4f0b07
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL_BASE_IDX                                                 3
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL1                                                         0x4f0b08
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL1_BASE_IDX                                                3
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL                                                          0x4f0b09
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL_BASE_IDX                                                 3
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL1                                                         0x4f0b0a
+#define regGDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL1_BASE_IDX                                                3
+#define regGDC_S2A1_S2A_DOORBELL_COMMON_CTRL_REG                                                        0x4f0b0b
+#define regGDC_S2A1_S2A_DOORBELL_COMMON_CTRL_REG_BASE_IDX                                               3
+#define regGDC_S2A1_NBIF_GFX_DOORBELL_STATUS                                                            0x4f0b0c
+#define regGDC_S2A1_NBIF_GFX_DOORBELL_STATUS_BASE_IDX                                                   3
+
+
+// addressBlock: nbif0_nbif0_gdc_misc_GDCMISC_DEC
+// base address: 0x1400000
+#define regGDC_DMA_SION_CRED_RST                                                                        0x4f3401
+#define regGDC_DMA_SION_CRED_RST_BASE_IDX                                                               3
+#define regGDC_HST_SION_PER_SDP_PORT_RST                                                                0x4f3402
+#define regGDC_HST_SION_PER_SDP_PORT_RST_BASE_IDX                                                       3
+#define regGDC_HST_SION_PER_SDP_CNTL_REG1                                                               0x4f3403
+#define regGDC_HST_SION_PER_SDP_CNTL_REG1_BASE_IDX                                                      3
+#define regGDC_HST_AXI_STALL_FOR_FLUSH                                                                  0x4f3404
+#define regGDC_HST_AXI_STALL_FOR_FLUSH_BASE_IDX                                                         3
+#define regSYSHUB_SDP_DEBUG_COUNTER_CTRL                                                                0x4f3405
+#define regSYSHUB_SDP_DEBUG_COUNTER_CTRL_BASE_IDX                                                       3
+#define regNBIF_PWRBRK_IN_PAD_CNTL                                                                      0x4f3801
+#define regNBIF_PWRBRK_IN_PAD_CNTL_BASE_IDX                                                             3
+#define regNBIF_PWRBRK_OUT_PAD_CNTL                                                                     0x4f3802
+#define regNBIF_PWRBRK_OUT_PAD_CNTL_BASE_IDX                                                            3
+#define regSHUB_OOB_CRUSH_DUMP_CTRL                                                                     0x4f3803
+#define regSHUB_OOB_CRUSH_DUMP_CTRL_BASE_IDX                                                            3
+#define regSHUB_MP_ERREVENT_MASK_CTRL                                                                   0x4f3804
+#define regSHUB_MP_ERREVENT_MASK_CTRL_BASE_IDX                                                          3
+#define regSHUB_ERREREVNT_SIDEBAND_RAS_V1_CTRL                                                          0x4f3805
+#define regSHUB_ERREREVNT_SIDEBAND_RAS_V1_CTRL_BASE_IDX                                                 3
+#define regSHUB_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL                                                   0x4f3806
+#define regSHUB_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL_BASE_IDX                                          3
+
+
+// addressBlock: nbif0_nbif0_gdc_sec_misc_GDCSEC_MISC_DEC
+// base address: 0x1400000
+#define regGDCSOC_SEC_DFV_POISON_INJ_DMACK0V3_AXI                                                       0x4f2883
+#define regGDCSOC_SEC_DFV_POISON_INJ_DMACK0V3_AXI_BASE_IDX                                              3
+#define regGDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0V3_AXI                                                   0x4f2884
+#define regGDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0V3_AXI_BASE_IDX                                          3
+#define regGDCSOC_SEC_DFV_POISON_INJ_LOG_DMACK0V3_AXI                                                   0x4f2885
+#define regGDCSOC_SEC_DFV_POISON_INJ_LOG_DMACK0V3_AXI_BASE_IDX                                          3
+#define regGDCSOC_SEC_DFV_POISON_INJ_DMACK0B_AXI                                                        0x4f2886
+#define regGDCSOC_SEC_DFV_POISON_INJ_DMACK0B_AXI_BASE_IDX                                               3
+#define regGDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0B_AXI                                                    0x4f2887
+#define regGDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0B_AXI_BASE_IDX                                           3
+#define regGDCSOC_SEC_DFV_POISON_INJ_LOG_DMACK0B_AXI                                                    0x4f2888
+#define regGDCSOC_SEC_DFV_POISON_INJ_LOG_DMACK0B_AXI_BASE_IDX                                           3
+#define regGDCSOC_SEC_DFV_POISON_INJ_DMACK0V4_AXI                                                       0x4f2889
+#define regGDCSOC_SEC_DFV_POISON_INJ_DMACK0V4_AXI_BASE_IDX                                              3
+#define regGDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0V4_AXI                                                   0x4f288a
+#define regGDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0V4_AXI_BASE_IDX                                          3
+#define regGDCSOC_SEC_DFV_POISON_INJ_LOG_DMACK0V4_AXI                                                   0x4f288b
+#define regGDCSOC_SEC_DFV_POISON_INJ_LOG_DMACK0V4_AXI_BASE_IDX                                          3
+#define regGDCSOC_SEC_DFV_POISON_INJ_DMACK0V4B_AXI                                                      0x4f288c
+#define regGDCSOC_SEC_DFV_POISON_INJ_DMACK0V4B_AXI_BASE_IDX                                             3
+#define regGDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0V4B_AXI                                                  0x4f288d
+#define regGDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0V4B_AXI_BASE_IDX                                         3
+#define regGDCSOC_SEC_DFV_POISON_INJ_LOG_DMACK0V4B_AXI                                                  0x4f288e
+#define regGDCSOC_SEC_DFV_POISON_INJ_LOG_DMACK0V4B_AXI_BASE_IDX                                         3
+#define regGDCSOC_SEC_DFV_POISON_INJ_DMACK0V7_AXI                                                       0x4f288f
+#define regGDCSOC_SEC_DFV_POISON_INJ_DMACK0V7_AXI_BASE_IDX                                              3
+#define regGDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0V7_AXI                                                   0x4f2890
+#define regGDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0V7_AXI_BASE_IDX                                          3
+#define regGDCSOC_SEC_DFV_POISON_INJ_LOG_DMACK0V7_AXI                                                   0x4f2891
+#define regGDCSOC_SEC_DFV_POISON_INJ_LOG_DMACK0V7_AXI_BASE_IDX                                          3
+#define regGDCSOC_SEC_DFV_POISON_INJ_SHUB_CNDI_ORIG_SDP                                                 0x4f2898
+#define regGDCSOC_SEC_DFV_POISON_INJ_SHUB_CNDI_ORIG_SDP_BASE_IDX                                        3
+#define regGDCSOC_SEC_DFV_POISON_INJ_CNT_SHUB_CNDI_ORIG_SDP                                             0x4f2899
+#define regGDCSOC_SEC_DFV_POISON_INJ_CNT_SHUB_CNDI_ORIG_SDP_BASE_IDX                                    3
+#define regGDCSOC_SEC_DFV_POISON_INJ_LOG_SHUB_CNDI_ORIG_SDP                                             0x4f289a
+#define regGDCSOC_SEC_DFV_POISON_INJ_LOG_SHUB_CNDI_ORIG_SDP_BASE_IDX                                    3
+#define regGDCSOC_SEC_DFV_POISON_INJ_DMACK0B1_AXI                                                       0x4f28a7
+#define regGDCSOC_SEC_DFV_POISON_INJ_DMACK0B1_AXI_BASE_IDX                                              3
+#define regGDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0B1_AXI                                                   0x4f28a8
+#define regGDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0B1_AXI_BASE_IDX                                          3
+#define regGDCSOC_SEC_DFV_POISON_INJ_LOG_DMACK0B1_AXI                                                   0x4f28a9
+#define regGDCSOC_SEC_DFV_POISON_INJ_LOG_DMACK0B1_AXI_BASE_IDX                                          3
+#define regGDCSOC_SEC_RAS_POISON_DBUG_CTRL                                                              0x4f2c00
+#define regGDCSOC_SEC_RAS_POISON_DBUG_CTRL_BASE_IDX                                                     3
+#define regGDCSOC_SEC_RAS_PARITY_DBUG_CTRL                                                              0x4f2c01
+#define regGDCSOC_SEC_RAS_PARITY_DBUG_CTRL_BASE_IDX                                                     3
+#define regGDCSOC_SEC_RAS_RCVERREVENT_DBUG_CTRL                                                         0x4f2c02
+#define regGDCSOC_SEC_RAS_RCVERREVENT_DBUG_CTRL_BASE_IDX                                                3
+#define regGDCSOC_SEC_RAS_TIMEOUT_DBUG_CTRL                                                             0x4f2c03
+#define regGDCSOC_SEC_RAS_TIMEOUT_DBUG_CTRL_BASE_IDX                                                    3
+#define regGDCSOC_SEC_RAS_POISON_DATA_DROP_CTRL                                                         0x4f2c04
+#define regGDCSOC_SEC_RAS_POISON_DATA_DROP_CTRL_BASE_IDX                                                3
+#define regGDCSOC_SEC_RAS_RESPONSE_DROP_CTRL                                                            0x4f2c05
+#define regGDCSOC_SEC_RAS_RESPONSE_DROP_CTRL_BASE_IDX                                                   3
+#define regGDCSOC_SEC_RAS_LEAF0_RRESP_POISON_CTRL                                                       0x4f2c06
+#define regGDCSOC_SEC_RAS_LEAF0_RRESP_POISON_CTRL_BASE_IDX                                              3
+#define regGDCSOC_SEC_RAS_LEAF0_RUSER_POISON_CTRL                                                       0x4f2c07
+#define regGDCSOC_SEC_RAS_LEAF0_RUSER_POISON_CTRL_BASE_IDX                                              3
+#define regGDCSOC_SEC_RAS_LEAF1_RRESP_POISON_CTRL                                                       0x4f2c08
+#define regGDCSOC_SEC_RAS_LEAF1_RRESP_POISON_CTRL_BASE_IDX                                              3
+#define regGDCSOC_SEC_RAS_LEAF1_RUSER_POISON_CTRL                                                       0x4f2c09
+#define regGDCSOC_SEC_RAS_LEAF1_RUSER_POISON_CTRL_BASE_IDX                                              3
+#define regGDCSOC_SEC_RAS_LEAF2_RRESP_POISON_CTRL                                                       0x4f2c0a
+#define regGDCSOC_SEC_RAS_LEAF2_RRESP_POISON_CTRL_BASE_IDX                                              3
+#define regGDCSOC_SEC_RAS_LEAF2_RUSER_POISON_CTRL                                                       0x4f2c0b
+#define regGDCSOC_SEC_RAS_LEAF2_RUSER_POISON_CTRL_BASE_IDX                                              3
+#define regGDCSOC_SEC_RAS_LEAF3_RRESP_POISON_CTRL                                                       0x4f2c0c
+#define regGDCSOC_SEC_RAS_LEAF3_RRESP_POISON_CTRL_BASE_IDX                                              3
+#define regGDCSOC_SEC_RAS_LEAF3_RUSER_POISON_CTRL                                                       0x4f2c0d
+#define regGDCSOC_SEC_RAS_LEAF3_RUSER_POISON_CTRL_BASE_IDX                                              3
+#define regGDCSOC_SEC_RAS_LEAF4_RRESP_POISON_CTRL                                                       0x4f2c0e
+#define regGDCSOC_SEC_RAS_LEAF4_RRESP_POISON_CTRL_BASE_IDX                                              3
+#define regGDCSOC_SEC_RAS_LEAF4_RUSER_POISON_CTRL                                                       0x4f2c0f
+#define regGDCSOC_SEC_RAS_LEAF4_RUSER_POISON_CTRL_BASE_IDX                                              3
+#define regGDCSOC_SEC_RAS_LEAF5_RRESP_POISON_CTRL                                                       0x4f2c10
+#define regGDCSOC_SEC_RAS_LEAF5_RRESP_POISON_CTRL_BASE_IDX                                              3
+#define regGDCSOC_SEC_RAS_LEAF5_RUSER_POISON_CTRL                                                       0x4f2c11
+#define regGDCSOC_SEC_RAS_LEAF5_RUSER_POISON_CTRL_BASE_IDX                                              3
+#define regGDCSOC_SEC_RAS_LEAF6_RRESP_POISON_CTRL                                                       0x4f2c12
+#define regGDCSOC_SEC_RAS_LEAF6_RRESP_POISON_CTRL_BASE_IDX                                              3
+#define regGDCSOC_SEC_RAS_LEAF6_RUSER_POISON_CTRL                                                       0x4f2c13
+#define regGDCSOC_SEC_RAS_LEAF6_RUSER_POISON_CTRL_BASE_IDX                                              3
+#define regGDCSOC_SEC_RAS_LEAF7_RRESP_POISON_CTRL                                                       0x4f2c14
+#define regGDCSOC_SEC_RAS_LEAF7_RRESP_POISON_CTRL_BASE_IDX                                              3
+#define regGDCSOC_SEC_RAS_LEAF7_RUSER_POISON_CTRL                                                       0x4f2c15
+#define regGDCSOC_SEC_RAS_LEAF7_RUSER_POISON_CTRL_BASE_IDX                                              3
+#define regGDCSOC_SEC_RAS_LEAF8_RRESP_POISON_CTRL                                                       0x4f2c16
+#define regGDCSOC_SEC_RAS_LEAF8_RRESP_POISON_CTRL_BASE_IDX                                              3
+#define regGDCSOC_SEC_RAS_LEAF8_RUSER_POISON_CTRL                                                       0x4f2c17
+#define regGDCSOC_SEC_RAS_LEAF8_RUSER_POISON_CTRL_BASE_IDX                                              3
+#define regGDCSOC_SEC_RAS_LEAF9_RRESP_POISON_CTRL                                                       0x4f2c18
+#define regGDCSOC_SEC_RAS_LEAF9_RRESP_POISON_CTRL_BASE_IDX                                              3
+#define regGDCSOC_SEC_RAS_LEAF9_RUSER_POISON_CTRL                                                       0x4f2c19
+#define regGDCSOC_SEC_RAS_LEAF9_RUSER_POISON_CTRL_BASE_IDX                                              3
+#define regGDCSOC_SEC_RAS_LEAF10_RRESP_POISON_CTRL                                                      0x4f2c1a
+#define regGDCSOC_SEC_RAS_LEAF10_RRESP_POISON_CTRL_BASE_IDX                                             3
+#define regGDCSOC_SEC_RAS_LEAF10_RUSER_POISON_CTRL                                                      0x4f2c1b
+#define regGDCSOC_SEC_RAS_LEAF10_RUSER_POISON_CTRL_BASE_IDX                                             3
+#define regGDCSOC_SEC_RAS_LEAF11_RRESP_POISON_CTRL                                                      0x4f2c1c
+#define regGDCSOC_SEC_RAS_LEAF11_RRESP_POISON_CTRL_BASE_IDX                                             3
+#define regGDCSOC_SEC_RAS_LEAF11_RUSER_POISON_CTRL                                                      0x4f2c1d
+#define regGDCSOC_SEC_RAS_LEAF11_RUSER_POISON_CTRL_BASE_IDX                                             3
+#define regGDCSOC_SEC_RAS_LEAF12_RRESP_POISON_CTRL                                                      0x4f2c1e
+#define regGDCSOC_SEC_RAS_LEAF12_RRESP_POISON_CTRL_BASE_IDX                                             3
+#define regGDCSOC_SEC_RAS_LEAF12_RUSER_POISON_CTRL                                                      0x4f2c1f
+#define regGDCSOC_SEC_RAS_LEAF12_RUSER_POISON_CTRL_BASE_IDX                                             3
+#define regGDCSOC_SEC_RAS_LEAF13_RRESP_POISON_CTRL                                                      0x4f2c20
+#define regGDCSOC_SEC_RAS_LEAF13_RRESP_POISON_CTRL_BASE_IDX                                             3
+#define regGDCSOC_SEC_RAS_LEAF13_RUSER_POISON_CTRL                                                      0x4f2c21
+#define regGDCSOC_SEC_RAS_LEAF13_RUSER_POISON_CTRL_BASE_IDX                                             3
+
+
+// addressBlock: nbif0_nbif0_gdc_a2s_GDCA2S_DEC
+// base address: 0x1400000
+#define regA2S_CNTL_SW0                                                                                 0x4f0c40
+#define regA2S_CNTL_SW0_BASE_IDX                                                                        3
+#define regA2S_CNTL_SW1                                                                                 0x4f0c41
+#define regA2S_CNTL_SW1_BASE_IDX                                                                        3
+#define regA2S_CNTL_SW2                                                                                 0x4f0c42
+#define regA2S_CNTL_SW2_BASE_IDX                                                                        3
+#define regA2S_CNTL_SW3                                                                                 0x4f0c43
+#define regA2S_CNTL_SW3_BASE_IDX                                                                        3
+#define regA2S_CNTL_SW4                                                                                 0x4f0c44
+#define regA2S_CNTL_SW4_BASE_IDX                                                                        3
+#define regA2S_CNTL_SW5                                                                                 0x4f0c45
+#define regA2S_CNTL_SW5_BASE_IDX                                                                        3
+#define regA2S_CNTL_2_SW0                                                                               0x4f0c50
+#define regA2S_CNTL_2_SW0_BASE_IDX                                                                      3
+#define regA2S_CNTL_2_SW1                                                                               0x4f0c51
+#define regA2S_CNTL_2_SW1_BASE_IDX                                                                      3
+#define regA2S_CNTL_2_SW2                                                                               0x4f0c52
+#define regA2S_CNTL_2_SW2_BASE_IDX                                                                      3
+#define regA2S_CNTL_2_SW3                                                                               0x4f0c53
+#define regA2S_CNTL_2_SW3_BASE_IDX                                                                      3
+#define regA2S_CNTL_2_SW4                                                                               0x4f0c54
+#define regA2S_CNTL_2_SW4_BASE_IDX                                                                      3
+#define regA2S_CNTL_2_SW5                                                                               0x4f0c55
+#define regA2S_CNTL_2_SW5_BASE_IDX                                                                      3
+#define regA2S_WRSIZEFULL_SUPPORT_DISABLE                                                               0x4f0c5c
+#define regA2S_WRSIZEFULL_SUPPORT_DISABLE_BASE_IDX                                                      3
+#define regROUTING_TABLE_CNTL                                                                           0x4f0c60
+#define regROUTING_TABLE_CNTL_BASE_IDX                                                                  3
+#define regROUTING_TABLE_DATA0                                                                          0x4f0c61
+#define regROUTING_TABLE_DATA0_BASE_IDX                                                                 3
+#define regA2S_ARB_CONTROL_FOR_VC0                                                                      0x4f0c68
+#define regA2S_ARB_CONTROL_FOR_VC0_BASE_IDX                                                             3
+#define regA2S_ARB_CONTROL_FOR_VC1                                                                      0x4f0c69
+#define regA2S_ARB_CONTROL_FOR_VC1_BASE_IDX                                                             3
+#define regA2S_ARB_CONTROL_FOR_VC2                                                                      0x4f0c6a
+#define regA2S_ARB_CONTROL_FOR_VC2_BASE_IDX                                                             3
+#define regA2S_ARB_CONTROL_FOR_VC3                                                                      0x4f0c6b
+#define regA2S_ARB_CONTROL_FOR_VC3_BASE_IDX                                                             3
+#define regA2S_ARB_CONTROL_FOR_VC4                                                                      0x4f0c6c
+#define regA2S_ARB_CONTROL_FOR_VC4_BASE_IDX                                                             3
+#define regA2S_ARB_CONTROL_FOR_VC5                                                                      0x4f0c6d
+#define regA2S_ARB_CONTROL_FOR_VC5_BASE_IDX                                                             3
+#define regA2S_ARB_CONTROL_FOR_VC6                                                                      0x4f0c6e
+#define regA2S_ARB_CONTROL_FOR_VC6_BASE_IDX                                                             3
+#define regA2S_ARB_CONTROL_FOR_VC7                                                                      0x4f0c6f
+#define regA2S_ARB_CONTROL_FOR_VC7_BASE_IDX                                                             3
+#define regA2S_RW_ARB_CNTL                                                                              0x4f0c70
+#define regA2S_RW_ARB_CNTL_BASE_IDX                                                                     3
+#define regA2S_REQ_RSP_TAG_CNTL                                                                         0x4f0c71
+#define regA2S_REQ_RSP_TAG_CNTL_BASE_IDX                                                                3
+#define regA2S_MISC_CNTL                                                                                0x4f0c72
+#define regA2S_MISC_CNTL_BASE_IDX                                                                       3
+#define regA2S_TAG_ALLOC_0                                                                              0x4f0c74
+#define regA2S_TAG_ALLOC_0_BASE_IDX                                                                     3
+#define regA2S_TAG_ALLOC_1                                                                              0x4f0c75
+#define regA2S_TAG_ALLOC_1_BASE_IDX                                                                     3
+#define regA2S_TAG_ALLOC_2                                                                              0x4f0c76
+#define regA2S_TAG_ALLOC_2_BASE_IDX                                                                     3
+#define regA2S_TAG_ALLOC_3                                                                              0x4f0c77
+#define regA2S_TAG_ALLOC_3_BASE_IDX                                                                     3
+#define regSHUB_A2S_TAG_ALLOC_FOR_CHAIN_0                                                               0x4f0c78
+#define regSHUB_A2S_TAG_ALLOC_FOR_CHAIN_0_BASE_IDX                                                      3
+#define regSHUB_A2S_TAG_ALLOC_FOR_CHAIN_1                                                               0x4f0c79
+#define regSHUB_A2S_TAG_ALLOC_FOR_CHAIN_1_BASE_IDX                                                      3
+#define regGDC_SDP_PORT_CTRL                                                                            0x4f0c7c
+#define regGDC_SDP_PORT_CTRL_BASE_IDX                                                                   3
+#define regGDC_A2S_SDP_REQ_POOLCRED_ALLOC                                                               0x4f0c7d
+#define regGDC_A2S_SDP_REQ_POOLCRED_ALLOC_BASE_IDX                                                      3
+#define regGDC_A2S_SDP_DAT_POOLCRED_ALLOC                                                               0x4f0c7e
+#define regGDC_A2S_SDP_DAT_POOLCRED_ALLOC_BASE_IDX                                                      3
+#define regSHUB_PERF_COMMON_COUNTER                                                                     0x4f0c80
+#define regSHUB_PERF_COMMON_COUNTER_BASE_IDX                                                            3
+#define regSHUB_A2S_PERF_CNT_FSM                                                                        0x4f0c81
+#define regSHUB_A2S_PERF_CNT_FSM_BASE_IDX                                                               3
+#define regSHUB_A2S_PERF_CNT_RSP_UNITID                                                                 0x4f0c83
+#define regSHUB_A2S_PERF_CNT_RSP_UNITID_BASE_IDX                                                        3
+#define regSHUB_A2S_PERF_CNT_0_CTRL                                                                     0x4f0c84
+#define regSHUB_A2S_PERF_CNT_0_CTRL_BASE_IDX                                                            3
+#define regSHUB_A2S_PERF_CNT_1_CTRL                                                                     0x4f0c85
+#define regSHUB_A2S_PERF_CNT_1_CTRL_BASE_IDX                                                            3
+#define regSHUB_A2S_PERF_CNT_2_CTRL                                                                     0x4f0c86
+#define regSHUB_A2S_PERF_CNT_2_CTRL_BASE_IDX                                                            3
+#define regSHUB_A2S_PERF_CNT_3_CTRL                                                                     0x4f0c87
+#define regSHUB_A2S_PERF_CNT_3_CTRL_BASE_IDX                                                            3
+#define regSHUB_A2S_PERF_CNT_0_VALUE_L32BIT                                                             0x4f0c88
+#define regSHUB_A2S_PERF_CNT_0_VALUE_L32BIT_BASE_IDX                                                    3
+#define regSHUB_A2S_PERF_CNT_0_VALUE_H16BIT                                                             0x4f0c89
+#define regSHUB_A2S_PERF_CNT_0_VALUE_H16BIT_BASE_IDX                                                    3
+#define regSHUB_A2S_PERF_CNT_1_VALUE_L32BIT                                                             0x4f0c8a
+#define regSHUB_A2S_PERF_CNT_1_VALUE_L32BIT_BASE_IDX                                                    3
+#define regSHUB_A2S_PERF_CNT_1_VALUE_H16BIT                                                             0x4f0c8b
+#define regSHUB_A2S_PERF_CNT_1_VALUE_H16BIT_BASE_IDX                                                    3
+#define regSHUB_A2S_PERF_CNT_2_VALUE_L32BIT                                                             0x4f0c8c
+#define regSHUB_A2S_PERF_CNT_2_VALUE_L32BIT_BASE_IDX                                                    3
+#define regSHUB_A2S_PERF_CNT_2_VALUE_H16BIT                                                             0x4f0c8d
+#define regSHUB_A2S_PERF_CNT_2_VALUE_H16BIT_BASE_IDX                                                    3
+#define regSHUB_A2S_PERF_CNT_3_VALUE_L32BIT                                                             0x4f0c8e
+#define regSHUB_A2S_PERF_CNT_3_VALUE_L32BIT_BASE_IDX                                                    3
+#define regSHUB_A2S_PERF_CNT_3_VALUE_H16BIT                                                             0x4f0c8f
+#define regSHUB_A2S_PERF_CNT_3_VALUE_H16BIT_BASE_IDX                                                    3
+#define regSHUB_TO_ALL_PERF_COUNTER                                                                     0x4f0c90
+#define regSHUB_TO_ALL_PERF_COUNTER_BASE_IDX                                                            3
+#define regGDC_PERF_COUNTER_RESET                                                                       0x4f0c91
+#define regGDC_PERF_COUNTER_RESET_BASE_IDX                                                              3
+#define regSHUB_COM_COUNT_VALUE                                                                         0x4f0c92
+#define regSHUB_COM_COUNT_VALUE_BASE_IDX                                                                3
+#define regA2S_QUEUE_FIFO_ARB_CNTL                                                                      0x4f0c93
+#define regA2S_QUEUE_FIFO_ARB_CNTL_BASE_IDX                                                             3
+#define regWR_A2S_RSP_WRR_CNTL                                                                          0x4f0c94
+#define regWR_A2S_RSP_WRR_CNTL_BASE_IDX                                                                 3
+#define regRD_A2S_RSP_WRR_CNTL                                                                          0x4f0c95
+#define regRD_A2S_RSP_WRR_CNTL_BASE_IDX                                                                 3
+
+
+// addressBlock: nbif0_nbif0_syshub_mmreg_syshubdirect
+// base address: 0x1400000
+#define regSYSHUB_DS_CTRL_SOCCLK                                                                        0x4f3c00
+#define regSYSHUB_DS_CTRL_SOCCLK_BASE_IDX                                                               3
+#define regSYSHUB_DS_CTRL2_SOCCLK                                                                       0x4f3c01
+#define regSYSHUB_DS_CTRL2_SOCCLK_BASE_IDX                                                              3
+#define regSYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK                                                     0x4f3c02
+#define regSYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK_BASE_IDX                                            3
+#define regSYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK                                                        0x4f3c03
+#define regSYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK_BASE_IDX                                               3
+#define regSYSHUB_MGCG_CTRL_SOCCLK                                                                      0x4f3c08
+#define regSYSHUB_MGCG_CTRL_SOCCLK_BASE_IDX                                                             3
+#define regSYSHUB_SCRATCH_SOCCLK                                                                        0x4f3c0a
+#define regSYSHUB_SCRATCH_SOCCLK_BASE_IDX                                                               3
+#define regSYSHUB_HANG_CNTL_SOCCLK                                                                      0x4f3c0c
+#define regSYSHUB_HANG_CNTL_SOCCLK_BASE_IDX                                                             3
+#define regSYSHUB_SELECT_SOCCLK                                                                         0x4f3c0d
+#define regSYSHUB_SELECT_SOCCLK_BASE_IDX                                                                3
+#define regSYSHUB_DS_AW_READY_SOCCLK                                                                    0x4f3c11
+#define regSYSHUB_DS_AW_READY_SOCCLK_BASE_IDX                                                           3
+#define regSYSHUB_DS_AR_READY_SOCCLK                                                                    0x4f3c12
+#define regSYSHUB_DS_AR_READY_SOCCLK_BASE_IDX                                                           3
+#define regSYSHUB_DS_W_READY_SOCCLK                                                                     0x4f3c13
+#define regSYSHUB_DS_W_READY_SOCCLK_BASE_IDX                                                            3
+#define regSYSHUB_DS_R_READY_SOCCLK                                                                     0x4f3c14
+#define regSYSHUB_DS_R_READY_SOCCLK_BASE_IDX                                                            3
+#define regSYSHUB_DS_B_READY_SOCCLK                                                                     0x4f3c15
+#define regSYSHUB_DS_B_READY_SOCCLK_BASE_IDX                                                            3
+#define regSYSHUB_AXI_DEBUG_COUNTER_CNTL_SOCCLK                                                         0x4f3c16
+#define regSYSHUB_AXI_DEBUG_COUNTER_CNTL_SOCCLK_BASE_IDX                                                3
+#define regDMA_CLK0_SW0_SYSHUB_QOS_CNTL                                                                 0x4f3e00
+#define regDMA_CLK0_SW0_SYSHUB_QOS_CNTL_BASE_IDX                                                        3
+#define regDMA_CLK0_SW1_SYSHUB_QOS_CNTL                                                                 0x4f3e01
+#define regDMA_CLK0_SW1_SYSHUB_QOS_CNTL_BASE_IDX                                                        3
+#define regDMA_CLK0_SW0_CL0_CNTL                                                                        0x4f3e40
+#define regDMA_CLK0_SW0_CL0_CNTL_BASE_IDX                                                               3
+#define regDMA_CLK0_SW0_CL1_CNTL                                                                        0x4f3e41
+#define regDMA_CLK0_SW0_CL1_CNTL_BASE_IDX                                                               3
+#define regDMA_CLK0_SW1_CL0_CNTL                                                                        0x4f3e60
+#define regDMA_CLK0_SW1_CL0_CNTL_BASE_IDX                                                               3
+#define regDMA_CLK0_SW1_CL1_CNTL                                                                        0x4f3e61
+#define regDMA_CLK0_SW1_CL1_CNTL_BASE_IDX                                                               3
+#define regDMA_CLK0_SW2_CL0_CNTL                                                                        0x4f3e80
+#define regDMA_CLK0_SW2_CL0_CNTL_BASE_IDX                                                               3
+#define regDMA_CLK0_SW3_CL0_CNTL                                                                        0x4f3ea0
+#define regDMA_CLK0_SW3_CL0_CNTL_BASE_IDX                                                               3
+#define regDMA_CLK0_SW4_CL0_CNTL                                                                        0x4f3ec0
+#define regDMA_CLK0_SW4_CL0_CNTL_BASE_IDX                                                               3
+#define regDMA_CLK0_SW5_CL0_CNTL                                                                        0x4f3ee0
+#define regDMA_CLK0_SW5_CL0_CNTL_BASE_IDX                                                               3
+#define regNIC400_0_AMIB_0_FN_MOD_BM_ISS                                                                0x4f7c02
+#define regNIC400_0_AMIB_0_FN_MOD_BM_ISS_BASE_IDX                                                       3
+#define regNIC400_0_AMIB_0_FN_MOD                                                                       0x4f7c42
+#define regNIC400_0_AMIB_0_FN_MOD_BASE_IDX                                                              3
+#define regNIC400_0_ASIB_0_FN_MOD                                                                       0x4f8842
+#define regNIC400_0_ASIB_0_FN_MOD_BASE_IDX                                                              3
+#define regNIC400_0_ASIB_0_QOS_CNTL                                                                     0x4f8843
+#define regNIC400_0_ASIB_0_QOS_CNTL_BASE_IDX                                                            3
+#define regNIC400_0_ASIB_0_MAX_OT                                                                       0x4f8844
+#define regNIC400_0_ASIB_0_MAX_OT_BASE_IDX                                                              3
+#define regNIC400_0_ASIB_0_MAX_COMB_OT                                                                  0x4f8845
+#define regNIC400_0_ASIB_0_MAX_COMB_OT_BASE_IDX                                                         3
+#define regNIC400_0_ASIB_0_AW_P                                                                         0x4f8846
+#define regNIC400_0_ASIB_0_AW_P_BASE_IDX                                                                3
+#define regNIC400_0_ASIB_0_AW_B                                                                         0x4f8847
+#define regNIC400_0_ASIB_0_AW_B_BASE_IDX                                                                3
+#define regNIC400_0_ASIB_0_AW_R                                                                         0x4f8848
+#define regNIC400_0_ASIB_0_AW_R_BASE_IDX                                                                3
+#define regNIC400_0_ASIB_0_AR_P                                                                         0x4f8849
+#define regNIC400_0_ASIB_0_AR_P_BASE_IDX                                                                3
+#define regNIC400_0_ASIB_0_AR_B                                                                         0x4f884a
+#define regNIC400_0_ASIB_0_AR_B_BASE_IDX                                                                3
+#define regNIC400_0_ASIB_0_AR_R                                                                         0x4f884b
+#define regNIC400_0_ASIB_0_AR_R_BASE_IDX                                                                3
+#define regNIC400_0_ASIB_0_TARGET_FC                                                                    0x4f884c
+#define regNIC400_0_ASIB_0_TARGET_FC_BASE_IDX                                                           3
+#define regNIC400_0_ASIB_0_KI_FC                                                                        0x4f884d
+#define regNIC400_0_ASIB_0_KI_FC_BASE_IDX                                                               3
+#define regNIC400_0_ASIB_0_QOS_RANGE                                                                    0x4f884e
+#define regNIC400_0_ASIB_0_QOS_RANGE_BASE_IDX                                                           3
+#define regNIC400_0_ASIB_1_FN_MOD                                                                       0x4f8c42
+#define regNIC400_0_ASIB_1_FN_MOD_BASE_IDX                                                              3
+#define regNIC400_0_ASIB_1_QOS_CNTL                                                                     0x4f8c43
+#define regNIC400_0_ASIB_1_QOS_CNTL_BASE_IDX                                                            3
+#define regNIC400_0_ASIB_1_MAX_OT                                                                       0x4f8c44
+#define regNIC400_0_ASIB_1_MAX_OT_BASE_IDX                                                              3
+#define regNIC400_0_ASIB_1_MAX_COMB_OT                                                                  0x4f8c45
+#define regNIC400_0_ASIB_1_MAX_COMB_OT_BASE_IDX                                                         3
+#define regNIC400_0_ASIB_1_AW_P                                                                         0x4f8c46
+#define regNIC400_0_ASIB_1_AW_P_BASE_IDX                                                                3
+#define regNIC400_0_ASIB_1_AW_B                                                                         0x4f8c47
+#define regNIC400_0_ASIB_1_AW_B_BASE_IDX                                                                3
+#define regNIC400_0_ASIB_1_AW_R                                                                         0x4f8c48
+#define regNIC400_0_ASIB_1_AW_R_BASE_IDX                                                                3
+#define regNIC400_0_ASIB_1_AR_P                                                                         0x4f8c49
+#define regNIC400_0_ASIB_1_AR_P_BASE_IDX                                                                3
+#define regNIC400_0_ASIB_1_AR_B                                                                         0x4f8c4a
+#define regNIC400_0_ASIB_1_AR_B_BASE_IDX                                                                3
+#define regNIC400_0_ASIB_1_AR_R                                                                         0x4f8c4b
+#define regNIC400_0_ASIB_1_AR_R_BASE_IDX                                                                3
+#define regNIC400_0_ASIB_1_TARGET_FC                                                                    0x4f8c4c
+#define regNIC400_0_ASIB_1_TARGET_FC_BASE_IDX                                                           3
+#define regNIC400_0_ASIB_1_KI_FC                                                                        0x4f8c4d
+#define regNIC400_0_ASIB_1_KI_FC_BASE_IDX                                                               3
+#define regNIC400_0_ASIB_1_QOS_RANGE                                                                    0x4f8c4e
+#define regNIC400_0_ASIB_1_QOS_RANGE_BASE_IDX                                                           3
+#define regNIC400_0_IB_0_FN_MOD                                                                         0x4fb842
+#define regNIC400_0_IB_0_FN_MOD_BASE_IDX                                                                3
+#define regNIC400_1_AMIB_0_FN_MOD_BM_ISS                                                                0x4fbc02
+#define regNIC400_1_AMIB_0_FN_MOD_BM_ISS_BASE_IDX                                                       3
+#define regNIC400_1_AMIB_0_FN_MOD                                                                       0x4fbc42
+#define regNIC400_1_AMIB_0_FN_MOD_BASE_IDX                                                              3
+#define regNIC400_1_ASIB_0_FN_MOD                                                                       0x4fc842
+#define regNIC400_1_ASIB_0_FN_MOD_BASE_IDX                                                              3
+#define regNIC400_1_ASIB_0_QOS_CNTL                                                                     0x4fc843
+#define regNIC400_1_ASIB_0_QOS_CNTL_BASE_IDX                                                            3
+#define regNIC400_1_ASIB_0_MAX_OT                                                                       0x4fc844
+#define regNIC400_1_ASIB_0_MAX_OT_BASE_IDX                                                              3
+#define regNIC400_1_ASIB_0_MAX_COMB_OT                                                                  0x4fc845
+#define regNIC400_1_ASIB_0_MAX_COMB_OT_BASE_IDX                                                         3
+#define regNIC400_1_ASIB_0_AW_P                                                                         0x4fc846
+#define regNIC400_1_ASIB_0_AW_P_BASE_IDX                                                                3
+#define regNIC400_1_ASIB_0_AW_B                                                                         0x4fc847
+#define regNIC400_1_ASIB_0_AW_B_BASE_IDX                                                                3
+#define regNIC400_1_ASIB_0_AW_R                                                                         0x4fc848
+#define regNIC400_1_ASIB_0_AW_R_BASE_IDX                                                                3
+#define regNIC400_1_ASIB_0_AR_P                                                                         0x4fc849
+#define regNIC400_1_ASIB_0_AR_P_BASE_IDX                                                                3
+#define regNIC400_1_ASIB_0_AR_B                                                                         0x4fc84a
+#define regNIC400_1_ASIB_0_AR_B_BASE_IDX                                                                3
+#define regNIC400_1_ASIB_0_AR_R                                                                         0x4fc84b
+#define regNIC400_1_ASIB_0_AR_R_BASE_IDX                                                                3
+#define regNIC400_1_ASIB_0_TARGET_FC                                                                    0x4fc84c
+#define regNIC400_1_ASIB_0_TARGET_FC_BASE_IDX                                                           3
+#define regNIC400_1_ASIB_0_KI_FC                                                                        0x4fc84d
+#define regNIC400_1_ASIB_0_KI_FC_BASE_IDX                                                               3
+#define regNIC400_1_ASIB_0_QOS_RANGE                                                                    0x4fc84e
+#define regNIC400_1_ASIB_0_QOS_RANGE_BASE_IDX                                                           3
+#define regNIC400_1_ASIB_1_FN_MOD                                                                       0x4fcc42
+#define regNIC400_1_ASIB_1_FN_MOD_BASE_IDX                                                              3
+#define regNIC400_1_ASIB_1_QOS_CNTL                                                                     0x4fcc43
+#define regNIC400_1_ASIB_1_QOS_CNTL_BASE_IDX                                                            3
+#define regNIC400_1_ASIB_1_MAX_OT                                                                       0x4fcc44
+#define regNIC400_1_ASIB_1_MAX_OT_BASE_IDX                                                              3
+#define regNIC400_1_ASIB_1_MAX_COMB_OT                                                                  0x4fcc45
+#define regNIC400_1_ASIB_1_MAX_COMB_OT_BASE_IDX                                                         3
+#define regNIC400_1_ASIB_1_AW_P                                                                         0x4fcc46
+#define regNIC400_1_ASIB_1_AW_P_BASE_IDX                                                                3
+#define regNIC400_1_ASIB_1_AW_B                                                                         0x4fcc47
+#define regNIC400_1_ASIB_1_AW_B_BASE_IDX                                                                3
+#define regNIC400_1_ASIB_1_AW_R                                                                         0x4fcc48
+#define regNIC400_1_ASIB_1_AW_R_BASE_IDX                                                                3
+#define regNIC400_1_ASIB_1_AR_P                                                                         0x4fcc49
+#define regNIC400_1_ASIB_1_AR_P_BASE_IDX                                                                3
+#define regNIC400_1_ASIB_1_AR_B                                                                         0x4fcc4a
+#define regNIC400_1_ASIB_1_AR_B_BASE_IDX                                                                3
+#define regNIC400_1_ASIB_1_AR_R                                                                         0x4fcc4b
+#define regNIC400_1_ASIB_1_AR_R_BASE_IDX                                                                3
+#define regNIC400_1_ASIB_1_TARGET_FC                                                                    0x4fcc4c
+#define regNIC400_1_ASIB_1_TARGET_FC_BASE_IDX                                                           3
+#define regNIC400_1_ASIB_1_KI_FC                                                                        0x4fcc4d
+#define regNIC400_1_ASIB_1_KI_FC_BASE_IDX                                                               3
+#define regNIC400_1_ASIB_1_QOS_RANGE                                                                    0x4fcc4e
+#define regNIC400_1_ASIB_1_QOS_RANGE_BASE_IDX                                                           3
+#define regNIC400_1_IB_0_FN_MOD                                                                         0x4ff842
+#define regNIC400_1_IB_0_FN_MOD_BASE_IDX                                                                3
+
+
+// addressBlock: nbif0_nbif0_syshub_mmreg_syshubdec
+// base address: 0x0
+#define regSYSHUB_INDEX                                                                                 0x0008
+#define regSYSHUB_INDEX_BASE_IDX                                                                        0
+#define regSYSHUB_DATA                                                                                  0x0009
+#define regSYSHUB_DATA_BASE_IDX                                                                         0
+
+
+// addressBlock: nbif0_nbif0_bif_cfg_dev0_rc_bifcfgdecp
+// base address: 0x0
+#define cfgBIF_CFG_DEV0_RC_VENDOR_ID                                                                    0x0000
+#define cfgBIF_CFG_DEV0_RC_DEVICE_ID                                                                    0x0002
+#define cfgBIF_CFG_DEV0_RC_COMMAND                                                                      0x0004
+#define cfgBIF_CFG_DEV0_RC_STATUS                                                                       0x0006
+#define cfgBIF_CFG_DEV0_RC_REVISION_ID                                                                  0x0008
+#define cfgBIF_CFG_DEV0_RC_PROG_INTERFACE                                                               0x0009
+#define cfgBIF_CFG_DEV0_RC_SUB_CLASS                                                                    0x000a
+#define cfgBIF_CFG_DEV0_RC_BASE_CLASS                                                                   0x000b
+#define cfgBIF_CFG_DEV0_RC_CACHE_LINE                                                                   0x000c
+#define cfgBIF_CFG_DEV0_RC_LATENCY                                                                      0x000d
+#define cfgBIF_CFG_DEV0_RC_HEADER                                                                       0x000e
+#define cfgBIF_CFG_DEV0_RC_BIST                                                                         0x000f
+#define cfgBIF_CFG_DEV0_RC_BASE_ADDR_1                                                                  0x0010
+#define cfgBIF_CFG_DEV0_RC_BASE_ADDR_2                                                                  0x0014
+#define cfgSUB_BUS_NUMBER_LATENCY                                                                       0x0018
+#define cfgIO_BASE_LIMIT                                                                                0x001c
+#define cfgSECONDARY_STATUS                                                                             0x001e
+#define cfgMEM_BASE_LIMIT                                                                               0x0020
+#define cfgPREF_BASE_LIMIT                                                                              0x0024
+#define cfgPREF_BASE_UPPER                                                                              0x0028
+#define cfgPREF_LIMIT_UPPER                                                                             0x002c
+#define cfgIO_BASE_LIMIT_HI                                                                             0x0030
+#define cfgBIF_CFG_DEV0_RC_CAP_PTR                                                                      0x0034
+#define cfgBIF_CFG_DEV0_RC_ROM_BASE_ADDR                                                                0x0038
+#define cfgBIF_CFG_DEV0_RC_INTERRUPT_LINE                                                               0x003c
+#define cfgBIF_CFG_DEV0_RC_INTERRUPT_PIN                                                                0x003d
+#define cfgIRQ_BRIDGE_CNTL                                                                              0x003e
+#define cfgEXT_BRIDGE_CNTL                                                                              0x0040
+#define cfgBIF_CFG_DEV0_RC_PMI_CAP_LIST                                                                 0x0050
+#define cfgBIF_CFG_DEV0_RC_PMI_CAP                                                                      0x0052
+#define cfgBIF_CFG_DEV0_RC_PMI_STATUS_CNTL                                                              0x0054
+#define cfgBIF_CFG_DEV0_RC_PCIE_CAP_LIST                                                                0x0058
+#define cfgBIF_CFG_DEV0_RC_PCIE_CAP                                                                     0x005a
+#define cfgBIF_CFG_DEV0_RC_DEVICE_CAP                                                                   0x005c
+#define cfgBIF_CFG_DEV0_RC_DEVICE_CNTL                                                                  0x0060
+#define cfgBIF_CFG_DEV0_RC_DEVICE_STATUS                                                                0x0062
+#define cfgBIF_CFG_DEV0_RC_LINK_CAP                                                                     0x0064
+#define cfgBIF_CFG_DEV0_RC_LINK_CNTL                                                                    0x0068
+#define cfgBIF_CFG_DEV0_RC_LINK_STATUS                                                                  0x006a
+#define cfgSLOT_CAP                                                                                     0x006c
+#define cfgSLOT_CNTL                                                                                    0x0070
+#define cfgSLOT_STATUS                                                                                  0x0072
+#define cfgROOT_CNTL                                                                                    0x0074
+#define cfgROOT_CAP                                                                                     0x0076
+#define cfgROOT_STATUS                                                                                  0x0078
+#define cfgBIF_CFG_DEV0_RC_DEVICE_CAP2                                                                  0x007c
+#define cfgBIF_CFG_DEV0_RC_DEVICE_CNTL2                                                                 0x0080
+#define cfgBIF_CFG_DEV0_RC_DEVICE_STATUS2                                                               0x0082
+#define cfgBIF_CFG_DEV0_RC_LINK_CAP2                                                                    0x0084
+#define cfgBIF_CFG_DEV0_RC_LINK_CNTL2                                                                   0x0088
+#define cfgBIF_CFG_DEV0_RC_LINK_STATUS2                                                                 0x008a
+#define cfgSLOT_CAP2                                                                                    0x008c
+#define cfgSLOT_CNTL2                                                                                   0x0090
+#define cfgSLOT_STATUS2                                                                                 0x0092
+#define cfgBIF_CFG_DEV0_RC_MSI_CAP_LIST                                                                 0x00a0
+#define cfgBIF_CFG_DEV0_RC_MSI_MSG_CNTL                                                                 0x00a2
+#define cfgBIF_CFG_DEV0_RC_MSI_MSG_ADDR_LO                                                              0x00a4
+#define cfgBIF_CFG_DEV0_RC_MSI_MSG_ADDR_HI                                                              0x00a8
+#define cfgBIF_CFG_DEV0_RC_MSI_MSG_DATA                                                                 0x00a8
+#define cfgBIF_CFG_DEV0_RC_MSI_EXT_MSG_DATA                                                             0x00aa
+#define cfgBIF_CFG_DEV0_RC_MSI_MSG_DATA_64                                                              0x00ac
+#define cfgBIF_CFG_DEV0_RC_MSI_EXT_MSG_DATA_64                                                          0x00ae
+#define cfgSSID_CAP_LIST                                                                                0x00c0
+#define cfgSSID_CAP                                                                                     0x00c4
+#define cfgBIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                            0x0100
+#define cfgBIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_HDR                                                     0x0104
+#define cfgBIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC1                                                        0x0108
+#define cfgBIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC2                                                        0x010c
+#define cfgBIF_CFG_DEV0_RC_PCIE_SECONDARY_ENH_CAP_LIST                                                  0x0110
+#define cfgBIF_CFG_DEV0_RC_PCIE_LINK_CNTL3                                                              0x0114
+#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_ERROR_STATUS                                                       0x0118
+#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL                                                0x011c
+#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL                                                0x011e
+#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL                                                0x0120
+#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL                                                0x0122
+#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL                                                0x0124
+#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL                                                0x0126
+#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL                                                0x0128
+#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL                                                0x012a
+#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL                                                0x012c
+#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL                                                0x012e
+#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL                                               0x0130
+#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL                                               0x0132
+#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL                                               0x0134
+#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL                                               0x0136
+#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL                                               0x0138
+#define cfgBIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL                                               0x013a
+#define cfgBIF_CFG_DEV0_RC_PCIE_PHY_16GT_ENH_CAP_LIST                                                   0x01b8
+#define cfgBIF_CFG_DEV0_RC_LINK_CAP_16GT                                                                0x01bc
+#define cfgBIF_CFG_DEV0_RC_LINK_CNTL_16GT                                                               0x01c0
+#define cfgBIF_CFG_DEV0_RC_LINK_STATUS_16GT                                                             0x01c4
+#define cfgBIF_CFG_DEV0_RC_LOCAL_PARITY_MISMATCH_STATUS_16GT                                            0x01c8
+#define cfgBIF_CFG_DEV0_RC_RTM1_PARITY_MISMATCH_STATUS_16GT                                             0x01cc
+#define cfgBIF_CFG_DEV0_RC_RTM2_PARITY_MISMATCH_STATUS_16GT                                             0x01d0
+#define cfgBIF_CFG_DEV0_RC_LANE_0_EQUALIZATION_CNTL_16GT                                                0x01d8
+#define cfgBIF_CFG_DEV0_RC_LANE_1_EQUALIZATION_CNTL_16GT                                                0x01d9
+#define cfgBIF_CFG_DEV0_RC_LANE_2_EQUALIZATION_CNTL_16GT                                                0x01da
+#define cfgBIF_CFG_DEV0_RC_LANE_3_EQUALIZATION_CNTL_16GT                                                0x01db
+#define cfgBIF_CFG_DEV0_RC_LANE_4_EQUALIZATION_CNTL_16GT                                                0x01dc
+#define cfgBIF_CFG_DEV0_RC_LANE_5_EQUALIZATION_CNTL_16GT                                                0x01dd
+#define cfgBIF_CFG_DEV0_RC_LANE_6_EQUALIZATION_CNTL_16GT                                                0x01de
+#define cfgBIF_CFG_DEV0_RC_LANE_7_EQUALIZATION_CNTL_16GT                                                0x01df
+#define cfgBIF_CFG_DEV0_RC_LANE_8_EQUALIZATION_CNTL_16GT                                                0x01e0
+#define cfgBIF_CFG_DEV0_RC_LANE_9_EQUALIZATION_CNTL_16GT                                                0x01e1
+#define cfgBIF_CFG_DEV0_RC_LANE_10_EQUALIZATION_CNTL_16GT                                               0x01e2
+#define cfgBIF_CFG_DEV0_RC_LANE_11_EQUALIZATION_CNTL_16GT                                               0x01e3
+#define cfgBIF_CFG_DEV0_RC_LANE_12_EQUALIZATION_CNTL_16GT                                               0x01e4
+#define cfgBIF_CFG_DEV0_RC_LANE_13_EQUALIZATION_CNTL_16GT                                               0x01e5
+#define cfgBIF_CFG_DEV0_RC_LANE_14_EQUALIZATION_CNTL_16GT                                               0x01e6
+#define cfgBIF_CFG_DEV0_RC_LANE_15_EQUALIZATION_CNTL_16GT                                               0x01e7
+#define cfgBIF_CFG_DEV0_RC_PCIE_PHY_32GT_ENH_CAP_LIST                                                   0x01f8
+#define cfgBIF_CFG_DEV0_RC_LINK_CAP_32GT                                                                0x01fc
+#define cfgBIF_CFG_DEV0_RC_LINK_CNTL_32GT                                                               0x0200
+#define cfgBIF_CFG_DEV0_RC_LINK_STATUS_32GT                                                             0x0204
+#define cfgBIF_CFG_DEV0_RC_RECEIVED_MODIFIED_TS_DATA1                                                   0x0208
+#define cfgBIF_CFG_DEV0_RC_RECEIVED_MODIFIED_TS_DATA2                                                   0x020c
+#define cfgBIF_CFG_DEV0_RC_TRANSMITTED_MODIFIED_TS_DATA1                                                0x0210
+#define cfgBIF_CFG_DEV0_RC_TRANSMITTED_MODIFIED_TS_DATA2                                                0x0214
+#define cfgBIF_CFG_DEV0_RC_LANE_0_EQUALIZATION_CNTL_32GT                                                0x0218
+#define cfgBIF_CFG_DEV0_RC_LANE_1_EQUALIZATION_CNTL_32GT                                                0x0219
+#define cfgBIF_CFG_DEV0_RC_LANE_2_EQUALIZATION_CNTL_32GT                                                0x021a
+#define cfgBIF_CFG_DEV0_RC_LANE_3_EQUALIZATION_CNTL_32GT                                                0x021b
+#define cfgBIF_CFG_DEV0_RC_LANE_4_EQUALIZATION_CNTL_32GT                                                0x021c
+#define cfgBIF_CFG_DEV0_RC_LANE_5_EQUALIZATION_CNTL_32GT                                                0x021d
+#define cfgBIF_CFG_DEV0_RC_LANE_6_EQUALIZATION_CNTL_32GT                                                0x021e
+#define cfgBIF_CFG_DEV0_RC_LANE_7_EQUALIZATION_CNTL_32GT                                                0x021f
+#define cfgBIF_CFG_DEV0_RC_LANE_8_EQUALIZATION_CNTL_32GT                                                0x0220
+#define cfgBIF_CFG_DEV0_RC_LANE_9_EQUALIZATION_CNTL_32GT                                                0x0221
+#define cfgBIF_CFG_DEV0_RC_LANE_10_EQUALIZATION_CNTL_32GT                                               0x0222
+#define cfgBIF_CFG_DEV0_RC_LANE_11_EQUALIZATION_CNTL_32GT                                               0x0223
+#define cfgBIF_CFG_DEV0_RC_LANE_12_EQUALIZATION_CNTL_32GT                                               0x0224
+#define cfgBIF_CFG_DEV0_RC_LANE_13_EQUALIZATION_CNTL_32GT                                               0x0225
+#define cfgBIF_CFG_DEV0_RC_LANE_14_EQUALIZATION_CNTL_32GT                                               0x0226
+#define cfgBIF_CFG_DEV0_RC_LANE_15_EQUALIZATION_CNTL_32GT                                               0x0227
+#define cfgBIF_CFG_DEV0_RC_PCIE_AP_ENH_CAP_LIST                                                         0x0238
+#define cfgBIF_CFG_DEV0_RC_AP_CAP                                                                       0x023c
+#define cfgBIF_CFG_DEV0_RC_AP_CNTL                                                                      0x0240
+#define cfgBIF_CFG_DEV0_RC_AP_DATA1                                                                     0x0244
+#define cfgBIF_CFG_DEV0_RC_AP_DATA2                                                                     0x0248
+#define cfgBIF_CFG_DEV0_RC_AP_SEL_EN_MASK                                                               0x024c
+#define cfgBIF_CFG_DEV0_RC_PCIE_MARGINING_ENH_CAP_LIST                                                  0x0250
+#define cfgBIF_CFG_DEV0_RC_MARGINING_PORT_CAP                                                           0x0254
+#define cfgBIF_CFG_DEV0_RC_MARGINING_PORT_STATUS                                                        0x0256
+#define cfgBIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL                                                   0x0258
+#define cfgBIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS                                                 0x025a
+#define cfgBIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL                                                   0x025c
+#define cfgBIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS                                                 0x025e
+#define cfgBIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL                                                   0x0260
+#define cfgBIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS                                                 0x0262
+#define cfgBIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL                                                   0x0264
+#define cfgBIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS                                                 0x0266
+#define cfgBIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL                                                   0x0268
+#define cfgBIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS                                                 0x026a
+#define cfgBIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL                                                   0x026c
+#define cfgBIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS                                                 0x026e
+#define cfgBIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL                                                   0x0270
+#define cfgBIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS                                                 0x0272
+#define cfgBIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL                                                   0x0274
+#define cfgBIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS                                                 0x0276
+#define cfgBIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL                                                   0x0278
+#define cfgBIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS                                                 0x027a
+#define cfgBIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL                                                   0x027c
+#define cfgBIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS                                                 0x027e
+#define cfgBIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL                                                  0x0280
+#define cfgBIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS                                                0x0282
+#define cfgBIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL                                                  0x0284
+#define cfgBIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS                                                0x0286
+#define cfgBIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL                                                  0x0288
+#define cfgBIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS                                                0x028a
+#define cfgBIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL                                                  0x028c
+#define cfgBIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS                                                0x028e
+#define cfgBIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL                                                  0x0290
+#define cfgBIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS                                                0x0292
+#define cfgBIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL                                                  0x0294
+#define cfgBIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS                                                0x0296
+#define cfgBIF_CFG_DEV0_RC_PCIE_NULL1_ENH_CAP_LIST                                                      0x0400
+#define cfgBIF_CFG_DEV0_RC_PCIE_VC_ENH_CAP_LIST                                                         0x0404
+#define cfgBIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1                                                        0x0408
+#define cfgBIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG2                                                        0x040c
+#define cfgBIF_CFG_DEV0_RC_PCIE_PORT_VC_CNTL                                                            0x0410
+#define cfgBIF_CFG_DEV0_RC_PCIE_PORT_VC_STATUS                                                          0x0412
+#define cfgBIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP                                                        0x0414
+#define cfgBIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL                                                       0x0418
+#define cfgBIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_STATUS                                                     0x041e
+#define cfgBIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP                                                        0x0420
+#define cfgBIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL                                                       0x0424
+#define cfgBIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_STATUS                                                     0x042a
+#define cfgBIF_CFG_DEV0_RC_PCIE_DLF_ENH_CAP_LIST                                                        0x0430
+#define cfgBIF_CFG_DEV0_RC_DATA_LINK_FEATURE_CAP                                                        0x0434
+#define cfgBIF_CFG_DEV0_RC_DATA_LINK_FEATURE_STATUS                                                     0x0438
+#define cfgBIF_CFG_DEV0_RC_PCIE_NULL2_ENH_CAP_LIST                                                      0x0600
+#define cfgBIF_CFG_DEV0_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                                0x0604
+#define cfgBIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS                                                       0x0608
+#define cfgBIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK                                                         0x060c
+#define cfgBIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY                                                     0x0610
+#define cfgBIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS                                                         0x0614
+#define cfgBIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK                                                           0x0618
+#define cfgBIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL                                                        0x061c
+#define cfgBIF_CFG_DEV0_RC_PCIE_HDR_LOG0                                                                0x0620
+#define cfgBIF_CFG_DEV0_RC_PCIE_HDR_LOG1                                                                0x0624
+#define cfgBIF_CFG_DEV0_RC_PCIE_HDR_LOG2                                                                0x0628
+#define cfgBIF_CFG_DEV0_RC_PCIE_HDR_LOG3                                                                0x062c
+#define cfgPCIE_ROOT_ERR_CMD                                                                            0x0630
+#define cfgPCIE_ROOT_ERR_STATUS                                                                         0x0634
+#define cfgPCIE_ERR_SRC_ID                                                                              0x0638
+#define cfgBIF_CFG_DEV0_RC_PCIE_HDR_LOG4                                                                0x063c
+#define cfgBIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG0                                                         0x063c
+#define cfgBIF_CFG_DEV0_RC_PCIE_HDR_LOG5                                                                0x0640
+#define cfgBIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG1                                                         0x0640
+#define cfgBIF_CFG_DEV0_RC_PCIE_HDR_LOG6                                                                0x0644
+#define cfgBIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG2                                                         0x0644
+#define cfgBIF_CFG_DEV0_RC_PCIE_HDR_LOG7                                                                0x0648
+#define cfgBIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG3                                                         0x0648
+#define cfgBIF_CFG_DEV0_RC_PCIE_HDR_LOG8                                                                0x064c
+#define cfgBIF_CFG_DEV0_RC_PCIE_HDR_LOG9                                                                0x0650
+#define cfgBIF_CFG_DEV0_RC_PCIE_HDR_LOG10                                                               0x0654
+#define cfgBIF_CFG_DEV0_RC_PCIE_HDR_LOG11                                                               0x0658
+#define cfgBIF_CFG_DEV0_RC_PCIE_HDR_LOG12                                                               0x065c
+#define cfgBIF_CFG_DEV0_RC_PCIE_HDR_LOG13                                                               0x0660
+#define cfgBIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST                                             0x0664
+#define cfgBIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_DW1                                                      0x0668
+#define cfgBIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_DW2                                                      0x066c
+#define cfgBIF_CFG_DEV0_RC_PCIE_ACS_ENH_CAP_LIST                                                        0x06dc
+#define cfgBIF_CFG_DEV0_RC_PCIE_ACS_CAP                                                                 0x06e0
+#define cfgBIF_CFG_DEV0_RC_PCIE_ACS_CNTL                                                                0x06e2
+#define cfgBIF_CFG_DEV0_RC_PCIE_RTR_ENH_CAP_LIST                                                        0x071c
+#define cfgBIF_CFG_DEV0_RC_RTR_DATA1                                                                    0x0720
+#define cfgBIF_CFG_DEV0_RC_RTR_DATA2                                                                    0x0724
+#define cfgBIF_CFG_DEV0_RC_IDE_ENH_CAP_LIST                                                             0x0e00
+#define cfgBIF_CFG_DEV0_RC_IDE_CAP                                                                      0x0e04
+#define cfgBIF_CFG_DEV0_RC_IDE_CNTL                                                                     0x0e08
+#define cfgBIF_CFG_DEV0_RC_LINK_IDE_STREAM_0_CNTL                                                       0x0e0c
+#define cfgBIF_CFG_DEV0_RC_LINK_IDE_STREAM_0_STATUS                                                     0x0e10
+#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CAP                                                   0x0e14
+#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CNTL                                                  0x0e18
+#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_STATUS                                                0x0e1c
+#define cfgBIF_CFG_DEV0_RC_IDE_0_RID_ASSOCIATION_REG1                                                   0x0e20
+#define cfgBIF_CFG_DEV0_RC_IDE_0_RID_ASSOCIATION_REG2                                                   0x0e24
+#define cfgBIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_0_REG1                                                0x0e28
+#define cfgBIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_0_REG2                                                0x0e2c
+#define cfgBIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_0_REG3                                                0x0e30
+#define cfgBIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_1_REG1                                                0x0e34
+#define cfgBIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_1_REG2                                                0x0e38
+#define cfgBIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_1_REG3                                                0x0e3c
+#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CAP                                                   0x0e40
+#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CNTL                                                  0x0e44
+#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_STATUS                                                0x0e48
+#define cfgBIF_CFG_DEV0_RC_IDE_1_RID_ASSOCIATION_REG1                                                   0x0e4c
+#define cfgBIF_CFG_DEV0_RC_IDE_1_RID_ASSOCIATION_REG2                                                   0x0e50
+#define cfgBIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_0_REG1                                                0x0e54
+#define cfgBIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_0_REG2                                                0x0e58
+#define cfgBIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_0_REG3                                                0x0e5c
+#define cfgBIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_1_REG1                                                0x0e60
+#define cfgBIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_1_REG2                                                0x0e64
+#define cfgBIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_1_REG3                                                0x0e68
+#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CAP                                                   0x0e6c
+#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CNTL                                                  0x0e70
+#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_STATUS                                                0x0e74
+#define cfgBIF_CFG_DEV0_RC_IDE_2_RID_ASSOCIATION_REG1                                                   0x0e78
+#define cfgBIF_CFG_DEV0_RC_IDE_2_RID_ASSOCIATION_REG2                                                   0x0e7c
+#define cfgBIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_0_REG1                                                0x0e80
+#define cfgBIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_0_REG2                                                0x0e84
+#define cfgBIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_0_REG3                                                0x0e88
+#define cfgBIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_1_REG1                                                0x0e8c
+#define cfgBIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_1_REG2                                                0x0e90
+#define cfgBIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_1_REG3                                                0x0e94
+#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CAP                                                   0x0e98
+#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CNTL                                                  0x0e9c
+#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_STATUS                                                0x0ea0
+#define cfgBIF_CFG_DEV0_RC_IDE_3_RID_ASSOCIATION_REG1                                                   0x0ea4
+#define cfgBIF_CFG_DEV0_RC_IDE_3_RID_ASSOCIATION_REG2                                                   0x0ea8
+#define cfgBIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_0_REG1                                                0x0eac
+#define cfgBIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_0_REG2                                                0x0eb0
+#define cfgBIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_0_REG3                                                0x0eb4
+#define cfgBIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_1_REG1                                                0x0eb8
+#define cfgBIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_1_REG2                                                0x0ebc
+#define cfgBIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_1_REG3                                                0x0ec0
+#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CAP                                                   0x0ec4
+#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CNTL                                                  0x0ec8
+#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_STATUS                                                0x0ecc
+#define cfgBIF_CFG_DEV0_RC_IDE_4_RID_ASSOCIATION_REG1                                                   0x0ed0
+#define cfgBIF_CFG_DEV0_RC_IDE_4_RID_ASSOCIATION_REG2                                                   0x0ed4
+#define cfgBIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_0_REG1                                                0x0ed8
+#define cfgBIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_0_REG2                                                0x0edc
+#define cfgBIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_0_REG3                                                0x0ee0
+#define cfgBIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_1_REG1                                                0x0ee4
+#define cfgBIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_1_REG2                                                0x0ee8
+#define cfgBIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_1_REG3                                                0x0eec
+#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CAP                                                   0x0ef0
+#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CNTL                                                  0x0ef4
+#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_STATUS                                                0x0ef8
+#define cfgBIF_CFG_DEV0_RC_IDE_5_RID_ASSOCIATION_REG1                                                   0x0efc
+#define cfgBIF_CFG_DEV0_RC_IDE_5_RID_ASSOCIATION_REG2                                                   0x0f00
+#define cfgBIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_0_REG1                                                0x0f04
+#define cfgBIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_0_REG2                                                0x0f08
+#define cfgBIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_0_REG3                                                0x0f0c
+#define cfgBIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_1_REG1                                                0x0f10
+#define cfgBIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_1_REG2                                                0x0f14
+#define cfgBIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_1_REG3                                                0x0f18
+#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CAP                                                   0x0f1c
+#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CNTL                                                  0x0f20
+#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_STATUS                                                0x0f24
+#define cfgBIF_CFG_DEV0_RC_IDE_6_RID_ASSOCIATION_REG1                                                   0x0f28
+#define cfgBIF_CFG_DEV0_RC_IDE_6_RID_ASSOCIATION_REG2                                                   0x0f2c
+#define cfgBIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_0_REG1                                                0x0f30
+#define cfgBIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_0_REG2                                                0x0f34
+#define cfgBIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_0_REG3                                                0x0f38
+#define cfgBIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_1_REG1                                                0x0f3c
+#define cfgBIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_1_REG2                                                0x0f40
+#define cfgBIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_1_REG3                                                0x0f44
+#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CAP                                                   0x0f48
+#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CNTL                                                  0x0f4c
+#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_STATUS                                                0x0f50
+#define cfgBIF_CFG_DEV0_RC_IDE_7_RID_ASSOCIATION_REG1                                                   0x0f54
+#define cfgBIF_CFG_DEV0_RC_IDE_7_RID_ASSOCIATION_REG2                                                   0x0f58
+#define cfgBIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_0_REG1                                                0x0f5c
+#define cfgBIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_0_REG2                                                0x0f60
+#define cfgBIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_0_REG3                                                0x0f64
+#define cfgBIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_1_REG1                                                0x0f68
+#define cfgBIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_1_REG2                                                0x0f6c
+#define cfgBIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_1_REG3                                                0x0f70
+#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CAP                                                   0x0f74
+#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CNTL                                                  0x0f78
+#define cfgBIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_STATUS                                                0x0f7c
+#define cfgBIF_CFG_DEV0_RC_IDE_8_RID_ASSOCIATION_REG1                                                   0x0f80
+#define cfgBIF_CFG_DEV0_RC_IDE_8_RID_ASSOCIATION_REG2                                                   0x0f84
+#define cfgBIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_0_REG1                                                0x0f88
+#define cfgBIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_0_REG2                                                0x0f8c
+#define cfgBIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_0_REG3                                                0x0f90
+#define cfgBIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_1_REG1                                                0x0f94
+#define cfgBIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_1_REG2                                                0x0f98
+#define cfgBIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_1_REG3                                                0x0f9c
+
+
+// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_vf0_bifcfgdecp
+// base address: 0x0
+#define cfgBIF_CFG_DEV0_EPF0_VF0_VENDOR_ID                                                              0x0000
+#define cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_ID                                                              0x0002
+#define cfgBIF_CFG_DEV0_EPF0_VF0_COMMAND                                                                0x0004
+#define cfgBIF_CFG_DEV0_EPF0_VF0_STATUS                                                                 0x0006
+#define cfgBIF_CFG_DEV0_EPF0_VF0_REVISION_ID                                                            0x0008
+#define cfgBIF_CFG_DEV0_EPF0_VF0_PROG_INTERFACE                                                         0x0009
+#define cfgBIF_CFG_DEV0_EPF0_VF0_SUB_CLASS                                                              0x000a
+#define cfgBIF_CFG_DEV0_EPF0_VF0_BASE_CLASS                                                             0x000b
+#define cfgBIF_CFG_DEV0_EPF0_VF0_CACHE_LINE                                                             0x000c
+#define cfgBIF_CFG_DEV0_EPF0_VF0_LATENCY                                                                0x000d
+#define cfgBIF_CFG_DEV0_EPF0_VF0_HEADER                                                                 0x000e
+#define cfgBIF_CFG_DEV0_EPF0_VF0_BIST                                                                   0x000f
+#define cfgBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_1                                                            0x0010
+#define cfgBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_2                                                            0x0014
+#define cfgBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_3                                                            0x0018
+#define cfgBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_4                                                            0x001c
+#define cfgBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_5                                                            0x0020
+#define cfgBIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_6                                                            0x0024
+#define cfgBIF_CFG_DEV0_EPF0_VF0_CARDBUS_CIS_PTR                                                        0x0028
+#define cfgBIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID                                                             0x002c
+#define cfgBIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR                                                          0x0030
+#define cfgBIF_CFG_DEV0_EPF0_VF0_CAP_PTR                                                                0x0034
+#define cfgBIF_CFG_DEV0_EPF0_VF0_INTERRUPT_LINE                                                         0x003c
+#define cfgBIF_CFG_DEV0_EPF0_VF0_INTERRUPT_PIN                                                          0x003d
+#define cfgBIF_CFG_DEV0_EPF0_VF0_MIN_GRANT                                                              0x003e
+#define cfgBIF_CFG_DEV0_EPF0_VF0_MAX_LATENCY                                                            0x003f
+#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST                                                          0x0064
+#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_CAP                                                               0x0066
+#define cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP                                                             0x0068
+#define cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL                                                            0x006c
+#define cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS                                                          0x006e
+#define cfgBIF_CFG_DEV0_EPF0_VF0_LINK_CAP                                                               0x0070
+#define cfgBIF_CFG_DEV0_EPF0_VF0_LINK_CNTL                                                              0x0074
+#define cfgBIF_CFG_DEV0_EPF0_VF0_LINK_STATUS                                                            0x0076
+#define cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2                                                            0x0088
+#define cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2                                                           0x008c
+#define cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS2                                                         0x008e
+#define cfgBIF_CFG_DEV0_EPF0_VF0_LINK_CAP2                                                              0x0090
+#define cfgBIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2                                                             0x0094
+#define cfgBIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2                                                           0x0096
+#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST                                                           0x00a0
+#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL                                                           0x00a2
+#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_LO                                                        0x00a4
+#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_HI                                                        0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA                                                           0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA                                                       0x00aa
+#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_MASK                                                               0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA_64                                                        0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA_64                                                    0x00ae
+#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_MASK_64                                                            0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_PENDING                                                            0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF0_MSI_PENDING_64                                                         0x00b4
+#define cfgBIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST                                                          0x00c0
+#define cfgBIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL                                                          0x00c2
+#define cfgBIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE                                                             0x00c4
+#define cfgBIF_CFG_DEV0_EPF0_VF0_MSIX_PBA                                                               0x00c8
+#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                      0x0100
+#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR                                               0x0104
+#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC1                                                  0x0108
+#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC2                                                  0x010c
+#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_DEVICE3_ENH_CAP_LIST                                              0x02d8
+#define cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP3                                                            0x02dc
+#define cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL3                                                           0x02e0
+#define cfgBIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS3                                                         0x02e4
+#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_NULL1_ENH_CAP_LIST                                                0x0400
+#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_NULL2_ENH_CAP_LIST                                                0x0600
+#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                          0x0604
+#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS                                                 0x0608
+#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK                                                   0x060c
+#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY                                               0x0610
+#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS                                                   0x0614
+#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK                                                     0x0618
+#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL                                                  0x061c
+#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG0                                                          0x0620
+#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG1                                                          0x0624
+#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG2                                                          0x0628
+#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG3                                                          0x062c
+#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG4                                                          0x063c
+#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG0                                                   0x063c
+#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG5                                                          0x0640
+#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG1                                                   0x0640
+#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG6                                                          0x0644
+#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG2                                                   0x0644
+#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG7                                                          0x0648
+#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG3                                                   0x0648
+#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG8                                                          0x064c
+#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG9                                                          0x0650
+#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG10                                                         0x0654
+#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG11                                                         0x0658
+#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG12                                                         0x065c
+#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG13                                                         0x0660
+#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_RTR_ENH_CAP_LIST                                                  0x071c
+#define cfgBIF_CFG_DEV0_EPF0_VF0_RTR_DATA1                                                              0x0720
+#define cfgBIF_CFG_DEV0_EPF0_VF0_RTR_DATA2                                                              0x0724
+#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST                                                  0x0770
+#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP                                                           0x0774
+#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL                                                          0x0776
+#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_ENH_CAP_LIST                                                  0x07ac
+#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP                                                           0x07b0
+#define cfgBIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CNTL                                                          0x07b2
+
+
+// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_vf1_bifcfgdecp
+// base address: 0x0
+#define cfgBIF_CFG_DEV0_EPF0_VF1_VENDOR_ID                                                              0x0000
+#define cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_ID                                                              0x0002
+#define cfgBIF_CFG_DEV0_EPF0_VF1_COMMAND                                                                0x0004
+#define cfgBIF_CFG_DEV0_EPF0_VF1_STATUS                                                                 0x0006
+#define cfgBIF_CFG_DEV0_EPF0_VF1_REVISION_ID                                                            0x0008
+#define cfgBIF_CFG_DEV0_EPF0_VF1_PROG_INTERFACE                                                         0x0009
+#define cfgBIF_CFG_DEV0_EPF0_VF1_SUB_CLASS                                                              0x000a
+#define cfgBIF_CFG_DEV0_EPF0_VF1_BASE_CLASS                                                             0x000b
+#define cfgBIF_CFG_DEV0_EPF0_VF1_CACHE_LINE                                                             0x000c
+#define cfgBIF_CFG_DEV0_EPF0_VF1_LATENCY                                                                0x000d
+#define cfgBIF_CFG_DEV0_EPF0_VF1_HEADER                                                                 0x000e
+#define cfgBIF_CFG_DEV0_EPF0_VF1_BIST                                                                   0x000f
+#define cfgBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_1                                                            0x0010
+#define cfgBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_2                                                            0x0014
+#define cfgBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_3                                                            0x0018
+#define cfgBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_4                                                            0x001c
+#define cfgBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_5                                                            0x0020
+#define cfgBIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_6                                                            0x0024
+#define cfgBIF_CFG_DEV0_EPF0_VF1_CARDBUS_CIS_PTR                                                        0x0028
+#define cfgBIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID                                                             0x002c
+#define cfgBIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR                                                          0x0030
+#define cfgBIF_CFG_DEV0_EPF0_VF1_CAP_PTR                                                                0x0034
+#define cfgBIF_CFG_DEV0_EPF0_VF1_INTERRUPT_LINE                                                         0x003c
+#define cfgBIF_CFG_DEV0_EPF0_VF1_INTERRUPT_PIN                                                          0x003d
+#define cfgBIF_CFG_DEV0_EPF0_VF1_MIN_GRANT                                                              0x003e
+#define cfgBIF_CFG_DEV0_EPF0_VF1_MAX_LATENCY                                                            0x003f
+#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST                                                          0x0064
+#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_CAP                                                               0x0066
+#define cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP                                                             0x0068
+#define cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL                                                            0x006c
+#define cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS                                                          0x006e
+#define cfgBIF_CFG_DEV0_EPF0_VF1_LINK_CAP                                                               0x0070
+#define cfgBIF_CFG_DEV0_EPF0_VF1_LINK_CNTL                                                              0x0074
+#define cfgBIF_CFG_DEV0_EPF0_VF1_LINK_STATUS                                                            0x0076
+#define cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2                                                            0x0088
+#define cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2                                                           0x008c
+#define cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS2                                                         0x008e
+#define cfgBIF_CFG_DEV0_EPF0_VF1_LINK_CAP2                                                              0x0090
+#define cfgBIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2                                                             0x0094
+#define cfgBIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2                                                           0x0096
+#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST                                                           0x00a0
+#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL                                                           0x00a2
+#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_LO                                                        0x00a4
+#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_HI                                                        0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA                                                           0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA                                                       0x00aa
+#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_MASK                                                               0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA_64                                                        0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA_64                                                    0x00ae
+#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_MASK_64                                                            0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_PENDING                                                            0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF1_MSI_PENDING_64                                                         0x00b4
+#define cfgBIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST                                                          0x00c0
+#define cfgBIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL                                                          0x00c2
+#define cfgBIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE                                                             0x00c4
+#define cfgBIF_CFG_DEV0_EPF0_VF1_MSIX_PBA                                                               0x00c8
+#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                      0x0100
+#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR                                               0x0104
+#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC1                                                  0x0108
+#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC2                                                  0x010c
+#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_DEVICE3_ENH_CAP_LIST                                              0x02d8
+#define cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP3                                                            0x02dc
+#define cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL3                                                           0x02e0
+#define cfgBIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS3                                                         0x02e4
+#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_NULL1_ENH_CAP_LIST                                                0x0400
+#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_NULL2_ENH_CAP_LIST                                                0x0600
+#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                          0x0604
+#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS                                                 0x0608
+#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK                                                   0x060c
+#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY                                               0x0610
+#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS                                                   0x0614
+#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK                                                     0x0618
+#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL                                                  0x061c
+#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG0                                                          0x0620
+#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG1                                                          0x0624
+#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG2                                                          0x0628
+#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG3                                                          0x062c
+#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG4                                                          0x063c
+#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG0                                                   0x063c
+#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG5                                                          0x0640
+#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG1                                                   0x0640
+#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG6                                                          0x0644
+#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG2                                                   0x0644
+#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG7                                                          0x0648
+#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG3                                                   0x0648
+#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG8                                                          0x064c
+#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG9                                                          0x0650
+#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG10                                                         0x0654
+#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG11                                                         0x0658
+#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG12                                                         0x065c
+#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG13                                                         0x0660
+#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_RTR_ENH_CAP_LIST                                                  0x071c
+#define cfgBIF_CFG_DEV0_EPF0_VF1_RTR_DATA1                                                              0x0720
+#define cfgBIF_CFG_DEV0_EPF0_VF1_RTR_DATA2                                                              0x0724
+#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST                                                  0x0770
+#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP                                                           0x0774
+#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL                                                          0x0776
+#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_ENH_CAP_LIST                                                  0x07ac
+#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP                                                           0x07b0
+#define cfgBIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CNTL                                                          0x07b2
+
+
+// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_vf2_bifcfgdecp
+// base address: 0x0
+#define cfgBIF_CFG_DEV0_EPF0_VF2_VENDOR_ID                                                              0x0000
+#define cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_ID                                                              0x0002
+#define cfgBIF_CFG_DEV0_EPF0_VF2_COMMAND                                                                0x0004
+#define cfgBIF_CFG_DEV0_EPF0_VF2_STATUS                                                                 0x0006
+#define cfgBIF_CFG_DEV0_EPF0_VF2_REVISION_ID                                                            0x0008
+#define cfgBIF_CFG_DEV0_EPF0_VF2_PROG_INTERFACE                                                         0x0009
+#define cfgBIF_CFG_DEV0_EPF0_VF2_SUB_CLASS                                                              0x000a
+#define cfgBIF_CFG_DEV0_EPF0_VF2_BASE_CLASS                                                             0x000b
+#define cfgBIF_CFG_DEV0_EPF0_VF2_CACHE_LINE                                                             0x000c
+#define cfgBIF_CFG_DEV0_EPF0_VF2_LATENCY                                                                0x000d
+#define cfgBIF_CFG_DEV0_EPF0_VF2_HEADER                                                                 0x000e
+#define cfgBIF_CFG_DEV0_EPF0_VF2_BIST                                                                   0x000f
+#define cfgBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_1                                                            0x0010
+#define cfgBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_2                                                            0x0014
+#define cfgBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_3                                                            0x0018
+#define cfgBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_4                                                            0x001c
+#define cfgBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_5                                                            0x0020
+#define cfgBIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_6                                                            0x0024
+#define cfgBIF_CFG_DEV0_EPF0_VF2_CARDBUS_CIS_PTR                                                        0x0028
+#define cfgBIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID                                                             0x002c
+#define cfgBIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR                                                          0x0030
+#define cfgBIF_CFG_DEV0_EPF0_VF2_CAP_PTR                                                                0x0034
+#define cfgBIF_CFG_DEV0_EPF0_VF2_INTERRUPT_LINE                                                         0x003c
+#define cfgBIF_CFG_DEV0_EPF0_VF2_INTERRUPT_PIN                                                          0x003d
+#define cfgBIF_CFG_DEV0_EPF0_VF2_MIN_GRANT                                                              0x003e
+#define cfgBIF_CFG_DEV0_EPF0_VF2_MAX_LATENCY                                                            0x003f
+#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST                                                          0x0064
+#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_CAP                                                               0x0066
+#define cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP                                                             0x0068
+#define cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL                                                            0x006c
+#define cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS                                                          0x006e
+#define cfgBIF_CFG_DEV0_EPF0_VF2_LINK_CAP                                                               0x0070
+#define cfgBIF_CFG_DEV0_EPF0_VF2_LINK_CNTL                                                              0x0074
+#define cfgBIF_CFG_DEV0_EPF0_VF2_LINK_STATUS                                                            0x0076
+#define cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2                                                            0x0088
+#define cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2                                                           0x008c
+#define cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS2                                                         0x008e
+#define cfgBIF_CFG_DEV0_EPF0_VF2_LINK_CAP2                                                              0x0090
+#define cfgBIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2                                                             0x0094
+#define cfgBIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2                                                           0x0096
+#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST                                                           0x00a0
+#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL                                                           0x00a2
+#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_LO                                                        0x00a4
+#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_HI                                                        0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA                                                           0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA                                                       0x00aa
+#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_MASK                                                               0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA_64                                                        0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA_64                                                    0x00ae
+#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_MASK_64                                                            0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_PENDING                                                            0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF2_MSI_PENDING_64                                                         0x00b4
+#define cfgBIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST                                                          0x00c0
+#define cfgBIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL                                                          0x00c2
+#define cfgBIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE                                                             0x00c4
+#define cfgBIF_CFG_DEV0_EPF0_VF2_MSIX_PBA                                                               0x00c8
+#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                      0x0100
+#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR                                               0x0104
+#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC1                                                  0x0108
+#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC2                                                  0x010c
+#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_DEVICE3_ENH_CAP_LIST                                              0x02d8
+#define cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP3                                                            0x02dc
+#define cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL3                                                           0x02e0
+#define cfgBIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS3                                                         0x02e4
+#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_NULL1_ENH_CAP_LIST                                                0x0400
+#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_NULL2_ENH_CAP_LIST                                                0x0600
+#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                          0x0604
+#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS                                                 0x0608
+#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK                                                   0x060c
+#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY                                               0x0610
+#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS                                                   0x0614
+#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK                                                     0x0618
+#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL                                                  0x061c
+#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG0                                                          0x0620
+#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG1                                                          0x0624
+#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG2                                                          0x0628
+#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG3                                                          0x062c
+#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG4                                                          0x063c
+#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG0                                                   0x063c
+#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG5                                                          0x0640
+#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG1                                                   0x0640
+#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG6                                                          0x0644
+#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG2                                                   0x0644
+#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG7                                                          0x0648
+#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG3                                                   0x0648
+#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG8                                                          0x064c
+#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG9                                                          0x0650
+#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG10                                                         0x0654
+#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG11                                                         0x0658
+#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG12                                                         0x065c
+#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG13                                                         0x0660
+#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_RTR_ENH_CAP_LIST                                                  0x071c
+#define cfgBIF_CFG_DEV0_EPF0_VF2_RTR_DATA1                                                              0x0720
+#define cfgBIF_CFG_DEV0_EPF0_VF2_RTR_DATA2                                                              0x0724
+#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST                                                  0x0770
+#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP                                                           0x0774
+#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL                                                          0x0776
+#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_ENH_CAP_LIST                                                  0x07ac
+#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP                                                           0x07b0
+#define cfgBIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CNTL                                                          0x07b2
+
+
+// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_vf3_bifcfgdecp
+// base address: 0x0
+#define cfgBIF_CFG_DEV0_EPF0_VF3_VENDOR_ID                                                              0x0000
+#define cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_ID                                                              0x0002
+#define cfgBIF_CFG_DEV0_EPF0_VF3_COMMAND                                                                0x0004
+#define cfgBIF_CFG_DEV0_EPF0_VF3_STATUS                                                                 0x0006
+#define cfgBIF_CFG_DEV0_EPF0_VF3_REVISION_ID                                                            0x0008
+#define cfgBIF_CFG_DEV0_EPF0_VF3_PROG_INTERFACE                                                         0x0009
+#define cfgBIF_CFG_DEV0_EPF0_VF3_SUB_CLASS                                                              0x000a
+#define cfgBIF_CFG_DEV0_EPF0_VF3_BASE_CLASS                                                             0x000b
+#define cfgBIF_CFG_DEV0_EPF0_VF3_CACHE_LINE                                                             0x000c
+#define cfgBIF_CFG_DEV0_EPF0_VF3_LATENCY                                                                0x000d
+#define cfgBIF_CFG_DEV0_EPF0_VF3_HEADER                                                                 0x000e
+#define cfgBIF_CFG_DEV0_EPF0_VF3_BIST                                                                   0x000f
+#define cfgBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_1                                                            0x0010
+#define cfgBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_2                                                            0x0014
+#define cfgBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_3                                                            0x0018
+#define cfgBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_4                                                            0x001c
+#define cfgBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_5                                                            0x0020
+#define cfgBIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_6                                                            0x0024
+#define cfgBIF_CFG_DEV0_EPF0_VF3_CARDBUS_CIS_PTR                                                        0x0028
+#define cfgBIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID                                                             0x002c
+#define cfgBIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR                                                          0x0030
+#define cfgBIF_CFG_DEV0_EPF0_VF3_CAP_PTR                                                                0x0034
+#define cfgBIF_CFG_DEV0_EPF0_VF3_INTERRUPT_LINE                                                         0x003c
+#define cfgBIF_CFG_DEV0_EPF0_VF3_INTERRUPT_PIN                                                          0x003d
+#define cfgBIF_CFG_DEV0_EPF0_VF3_MIN_GRANT                                                              0x003e
+#define cfgBIF_CFG_DEV0_EPF0_VF3_MAX_LATENCY                                                            0x003f
+#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST                                                          0x0064
+#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_CAP                                                               0x0066
+#define cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP                                                             0x0068
+#define cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL                                                            0x006c
+#define cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS                                                          0x006e
+#define cfgBIF_CFG_DEV0_EPF0_VF3_LINK_CAP                                                               0x0070
+#define cfgBIF_CFG_DEV0_EPF0_VF3_LINK_CNTL                                                              0x0074
+#define cfgBIF_CFG_DEV0_EPF0_VF3_LINK_STATUS                                                            0x0076
+#define cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2                                                            0x0088
+#define cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2                                                           0x008c
+#define cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS2                                                         0x008e
+#define cfgBIF_CFG_DEV0_EPF0_VF3_LINK_CAP2                                                              0x0090
+#define cfgBIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2                                                             0x0094
+#define cfgBIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2                                                           0x0096
+#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST                                                           0x00a0
+#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL                                                           0x00a2
+#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_LO                                                        0x00a4
+#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_HI                                                        0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA                                                           0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA                                                       0x00aa
+#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_MASK                                                               0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA_64                                                        0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA_64                                                    0x00ae
+#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_MASK_64                                                            0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_PENDING                                                            0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF3_MSI_PENDING_64                                                         0x00b4
+#define cfgBIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST                                                          0x00c0
+#define cfgBIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL                                                          0x00c2
+#define cfgBIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE                                                             0x00c4
+#define cfgBIF_CFG_DEV0_EPF0_VF3_MSIX_PBA                                                               0x00c8
+#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                      0x0100
+#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR                                               0x0104
+#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC1                                                  0x0108
+#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC2                                                  0x010c
+#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_DEVICE3_ENH_CAP_LIST                                              0x02d8
+#define cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP3                                                            0x02dc
+#define cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL3                                                           0x02e0
+#define cfgBIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS3                                                         0x02e4
+#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_NULL1_ENH_CAP_LIST                                                0x0400
+#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_NULL2_ENH_CAP_LIST                                                0x0600
+#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                          0x0604
+#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS                                                 0x0608
+#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK                                                   0x060c
+#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY                                               0x0610
+#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS                                                   0x0614
+#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK                                                     0x0618
+#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL                                                  0x061c
+#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG0                                                          0x0620
+#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG1                                                          0x0624
+#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG2                                                          0x0628
+#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG3                                                          0x062c
+#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG4                                                          0x063c
+#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG0                                                   0x063c
+#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG5                                                          0x0640
+#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG1                                                   0x0640
+#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG6                                                          0x0644
+#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG2                                                   0x0644
+#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG7                                                          0x0648
+#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG3                                                   0x0648
+#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG8                                                          0x064c
+#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG9                                                          0x0650
+#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG10                                                         0x0654
+#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG11                                                         0x0658
+#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG12                                                         0x065c
+#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG13                                                         0x0660
+#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_RTR_ENH_CAP_LIST                                                  0x071c
+#define cfgBIF_CFG_DEV0_EPF0_VF3_RTR_DATA1                                                              0x0720
+#define cfgBIF_CFG_DEV0_EPF0_VF3_RTR_DATA2                                                              0x0724
+#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST                                                  0x0770
+#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP                                                           0x0774
+#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL                                                          0x0776
+#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_ENH_CAP_LIST                                                  0x07ac
+#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP                                                           0x07b0
+#define cfgBIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CNTL                                                          0x07b2
+
+
+// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_vf4_bifcfgdecp
+// base address: 0x0
+#define cfgBIF_CFG_DEV0_EPF0_VF4_VENDOR_ID                                                              0x0000
+#define cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_ID                                                              0x0002
+#define cfgBIF_CFG_DEV0_EPF0_VF4_COMMAND                                                                0x0004
+#define cfgBIF_CFG_DEV0_EPF0_VF4_STATUS                                                                 0x0006
+#define cfgBIF_CFG_DEV0_EPF0_VF4_REVISION_ID                                                            0x0008
+#define cfgBIF_CFG_DEV0_EPF0_VF4_PROG_INTERFACE                                                         0x0009
+#define cfgBIF_CFG_DEV0_EPF0_VF4_SUB_CLASS                                                              0x000a
+#define cfgBIF_CFG_DEV0_EPF0_VF4_BASE_CLASS                                                             0x000b
+#define cfgBIF_CFG_DEV0_EPF0_VF4_CACHE_LINE                                                             0x000c
+#define cfgBIF_CFG_DEV0_EPF0_VF4_LATENCY                                                                0x000d
+#define cfgBIF_CFG_DEV0_EPF0_VF4_HEADER                                                                 0x000e
+#define cfgBIF_CFG_DEV0_EPF0_VF4_BIST                                                                   0x000f
+#define cfgBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_1                                                            0x0010
+#define cfgBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_2                                                            0x0014
+#define cfgBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_3                                                            0x0018
+#define cfgBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_4                                                            0x001c
+#define cfgBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_5                                                            0x0020
+#define cfgBIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_6                                                            0x0024
+#define cfgBIF_CFG_DEV0_EPF0_VF4_CARDBUS_CIS_PTR                                                        0x0028
+#define cfgBIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID                                                             0x002c
+#define cfgBIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR                                                          0x0030
+#define cfgBIF_CFG_DEV0_EPF0_VF4_CAP_PTR                                                                0x0034
+#define cfgBIF_CFG_DEV0_EPF0_VF4_INTERRUPT_LINE                                                         0x003c
+#define cfgBIF_CFG_DEV0_EPF0_VF4_INTERRUPT_PIN                                                          0x003d
+#define cfgBIF_CFG_DEV0_EPF0_VF4_MIN_GRANT                                                              0x003e
+#define cfgBIF_CFG_DEV0_EPF0_VF4_MAX_LATENCY                                                            0x003f
+#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST                                                          0x0064
+#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_CAP                                                               0x0066
+#define cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP                                                             0x0068
+#define cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL                                                            0x006c
+#define cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS                                                          0x006e
+#define cfgBIF_CFG_DEV0_EPF0_VF4_LINK_CAP                                                               0x0070
+#define cfgBIF_CFG_DEV0_EPF0_VF4_LINK_CNTL                                                              0x0074
+#define cfgBIF_CFG_DEV0_EPF0_VF4_LINK_STATUS                                                            0x0076
+#define cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2                                                            0x0088
+#define cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2                                                           0x008c
+#define cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS2                                                         0x008e
+#define cfgBIF_CFG_DEV0_EPF0_VF4_LINK_CAP2                                                              0x0090
+#define cfgBIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2                                                             0x0094
+#define cfgBIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2                                                           0x0096
+#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST                                                           0x00a0
+#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL                                                           0x00a2
+#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_LO                                                        0x00a4
+#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_HI                                                        0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA                                                           0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA                                                       0x00aa
+#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_MASK                                                               0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA_64                                                        0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA_64                                                    0x00ae
+#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_MASK_64                                                            0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_PENDING                                                            0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF4_MSI_PENDING_64                                                         0x00b4
+#define cfgBIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST                                                          0x00c0
+#define cfgBIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL                                                          0x00c2
+#define cfgBIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE                                                             0x00c4
+#define cfgBIF_CFG_DEV0_EPF0_VF4_MSIX_PBA                                                               0x00c8
+#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                      0x0100
+#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR                                               0x0104
+#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC1                                                  0x0108
+#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC2                                                  0x010c
+#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_DEVICE3_ENH_CAP_LIST                                              0x02d8
+#define cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP3                                                            0x02dc
+#define cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL3                                                           0x02e0
+#define cfgBIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS3                                                         0x02e4
+#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_NULL1_ENH_CAP_LIST                                                0x0400
+#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_NULL2_ENH_CAP_LIST                                                0x0600
+#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                          0x0604
+#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS                                                 0x0608
+#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK                                                   0x060c
+#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY                                               0x0610
+#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS                                                   0x0614
+#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK                                                     0x0618
+#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL                                                  0x061c
+#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG0                                                          0x0620
+#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG1                                                          0x0624
+#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG2                                                          0x0628
+#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG3                                                          0x062c
+#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG4                                                          0x063c
+#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG0                                                   0x063c
+#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG5                                                          0x0640
+#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG1                                                   0x0640
+#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG6                                                          0x0644
+#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG2                                                   0x0644
+#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG7                                                          0x0648
+#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG3                                                   0x0648
+#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG8                                                          0x064c
+#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG9                                                          0x0650
+#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG10                                                         0x0654
+#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG11                                                         0x0658
+#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG12                                                         0x065c
+#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG13                                                         0x0660
+#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_RTR_ENH_CAP_LIST                                                  0x071c
+#define cfgBIF_CFG_DEV0_EPF0_VF4_RTR_DATA1                                                              0x0720
+#define cfgBIF_CFG_DEV0_EPF0_VF4_RTR_DATA2                                                              0x0724
+#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST                                                  0x0770
+#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP                                                           0x0774
+#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL                                                          0x0776
+#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_ENH_CAP_LIST                                                  0x07ac
+#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP                                                           0x07b0
+#define cfgBIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CNTL                                                          0x07b2
+
+
+// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_vf5_bifcfgdecp
+// base address: 0x0
+#define cfgBIF_CFG_DEV0_EPF0_VF5_VENDOR_ID                                                              0x0000
+#define cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_ID                                                              0x0002
+#define cfgBIF_CFG_DEV0_EPF0_VF5_COMMAND                                                                0x0004
+#define cfgBIF_CFG_DEV0_EPF0_VF5_STATUS                                                                 0x0006
+#define cfgBIF_CFG_DEV0_EPF0_VF5_REVISION_ID                                                            0x0008
+#define cfgBIF_CFG_DEV0_EPF0_VF5_PROG_INTERFACE                                                         0x0009
+#define cfgBIF_CFG_DEV0_EPF0_VF5_SUB_CLASS                                                              0x000a
+#define cfgBIF_CFG_DEV0_EPF0_VF5_BASE_CLASS                                                             0x000b
+#define cfgBIF_CFG_DEV0_EPF0_VF5_CACHE_LINE                                                             0x000c
+#define cfgBIF_CFG_DEV0_EPF0_VF5_LATENCY                                                                0x000d
+#define cfgBIF_CFG_DEV0_EPF0_VF5_HEADER                                                                 0x000e
+#define cfgBIF_CFG_DEV0_EPF0_VF5_BIST                                                                   0x000f
+#define cfgBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_1                                                            0x0010
+#define cfgBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_2                                                            0x0014
+#define cfgBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_3                                                            0x0018
+#define cfgBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_4                                                            0x001c
+#define cfgBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_5                                                            0x0020
+#define cfgBIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_6                                                            0x0024
+#define cfgBIF_CFG_DEV0_EPF0_VF5_CARDBUS_CIS_PTR                                                        0x0028
+#define cfgBIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID                                                             0x002c
+#define cfgBIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR                                                          0x0030
+#define cfgBIF_CFG_DEV0_EPF0_VF5_CAP_PTR                                                                0x0034
+#define cfgBIF_CFG_DEV0_EPF0_VF5_INTERRUPT_LINE                                                         0x003c
+#define cfgBIF_CFG_DEV0_EPF0_VF5_INTERRUPT_PIN                                                          0x003d
+#define cfgBIF_CFG_DEV0_EPF0_VF5_MIN_GRANT                                                              0x003e
+#define cfgBIF_CFG_DEV0_EPF0_VF5_MAX_LATENCY                                                            0x003f
+#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST                                                          0x0064
+#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_CAP                                                               0x0066
+#define cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP                                                             0x0068
+#define cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL                                                            0x006c
+#define cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS                                                          0x006e
+#define cfgBIF_CFG_DEV0_EPF0_VF5_LINK_CAP                                                               0x0070
+#define cfgBIF_CFG_DEV0_EPF0_VF5_LINK_CNTL                                                              0x0074
+#define cfgBIF_CFG_DEV0_EPF0_VF5_LINK_STATUS                                                            0x0076
+#define cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2                                                            0x0088
+#define cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2                                                           0x008c
+#define cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS2                                                         0x008e
+#define cfgBIF_CFG_DEV0_EPF0_VF5_LINK_CAP2                                                              0x0090
+#define cfgBIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2                                                             0x0094
+#define cfgBIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2                                                           0x0096
+#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST                                                           0x00a0
+#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL                                                           0x00a2
+#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_LO                                                        0x00a4
+#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_HI                                                        0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA                                                           0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA                                                       0x00aa
+#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_MASK                                                               0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA_64                                                        0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA_64                                                    0x00ae
+#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_MASK_64                                                            0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_PENDING                                                            0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF5_MSI_PENDING_64                                                         0x00b4
+#define cfgBIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST                                                          0x00c0
+#define cfgBIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL                                                          0x00c2
+#define cfgBIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE                                                             0x00c4
+#define cfgBIF_CFG_DEV0_EPF0_VF5_MSIX_PBA                                                               0x00c8
+#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                      0x0100
+#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR                                               0x0104
+#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC1                                                  0x0108
+#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC2                                                  0x010c
+#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_DEVICE3_ENH_CAP_LIST                                              0x02d8
+#define cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP3                                                            0x02dc
+#define cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL3                                                           0x02e0
+#define cfgBIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS3                                                         0x02e4
+#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_NULL1_ENH_CAP_LIST                                                0x0400
+#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_NULL2_ENH_CAP_LIST                                                0x0600
+#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                          0x0604
+#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS                                                 0x0608
+#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK                                                   0x060c
+#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY                                               0x0610
+#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS                                                   0x0614
+#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK                                                     0x0618
+#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL                                                  0x061c
+#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG0                                                          0x0620
+#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG1                                                          0x0624
+#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG2                                                          0x0628
+#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG3                                                          0x062c
+#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG4                                                          0x063c
+#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG0                                                   0x063c
+#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG5                                                          0x0640
+#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG1                                                   0x0640
+#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG6                                                          0x0644
+#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG2                                                   0x0644
+#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG7                                                          0x0648
+#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG3                                                   0x0648
+#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG8                                                          0x064c
+#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG9                                                          0x0650
+#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG10                                                         0x0654
+#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG11                                                         0x0658
+#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG12                                                         0x065c
+#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG13                                                         0x0660
+#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_RTR_ENH_CAP_LIST                                                  0x071c
+#define cfgBIF_CFG_DEV0_EPF0_VF5_RTR_DATA1                                                              0x0720
+#define cfgBIF_CFG_DEV0_EPF0_VF5_RTR_DATA2                                                              0x0724
+#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST                                                  0x0770
+#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP                                                           0x0774
+#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL                                                          0x0776
+#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_ENH_CAP_LIST                                                  0x07ac
+#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP                                                           0x07b0
+#define cfgBIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CNTL                                                          0x07b2
+
+
+// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_vf6_bifcfgdecp
+// base address: 0x0
+#define cfgBIF_CFG_DEV0_EPF0_VF6_VENDOR_ID                                                              0x0000
+#define cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_ID                                                              0x0002
+#define cfgBIF_CFG_DEV0_EPF0_VF6_COMMAND                                                                0x0004
+#define cfgBIF_CFG_DEV0_EPF0_VF6_STATUS                                                                 0x0006
+#define cfgBIF_CFG_DEV0_EPF0_VF6_REVISION_ID                                                            0x0008
+#define cfgBIF_CFG_DEV0_EPF0_VF6_PROG_INTERFACE                                                         0x0009
+#define cfgBIF_CFG_DEV0_EPF0_VF6_SUB_CLASS                                                              0x000a
+#define cfgBIF_CFG_DEV0_EPF0_VF6_BASE_CLASS                                                             0x000b
+#define cfgBIF_CFG_DEV0_EPF0_VF6_CACHE_LINE                                                             0x000c
+#define cfgBIF_CFG_DEV0_EPF0_VF6_LATENCY                                                                0x000d
+#define cfgBIF_CFG_DEV0_EPF0_VF6_HEADER                                                                 0x000e
+#define cfgBIF_CFG_DEV0_EPF0_VF6_BIST                                                                   0x000f
+#define cfgBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_1                                                            0x0010
+#define cfgBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_2                                                            0x0014
+#define cfgBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_3                                                            0x0018
+#define cfgBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_4                                                            0x001c
+#define cfgBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_5                                                            0x0020
+#define cfgBIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_6                                                            0x0024
+#define cfgBIF_CFG_DEV0_EPF0_VF6_CARDBUS_CIS_PTR                                                        0x0028
+#define cfgBIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID                                                             0x002c
+#define cfgBIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR                                                          0x0030
+#define cfgBIF_CFG_DEV0_EPF0_VF6_CAP_PTR                                                                0x0034
+#define cfgBIF_CFG_DEV0_EPF0_VF6_INTERRUPT_LINE                                                         0x003c
+#define cfgBIF_CFG_DEV0_EPF0_VF6_INTERRUPT_PIN                                                          0x003d
+#define cfgBIF_CFG_DEV0_EPF0_VF6_MIN_GRANT                                                              0x003e
+#define cfgBIF_CFG_DEV0_EPF0_VF6_MAX_LATENCY                                                            0x003f
+#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST                                                          0x0064
+#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_CAP                                                               0x0066
+#define cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP                                                             0x0068
+#define cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL                                                            0x006c
+#define cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS                                                          0x006e
+#define cfgBIF_CFG_DEV0_EPF0_VF6_LINK_CAP                                                               0x0070
+#define cfgBIF_CFG_DEV0_EPF0_VF6_LINK_CNTL                                                              0x0074
+#define cfgBIF_CFG_DEV0_EPF0_VF6_LINK_STATUS                                                            0x0076
+#define cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2                                                            0x0088
+#define cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2                                                           0x008c
+#define cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS2                                                         0x008e
+#define cfgBIF_CFG_DEV0_EPF0_VF6_LINK_CAP2                                                              0x0090
+#define cfgBIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2                                                             0x0094
+#define cfgBIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2                                                           0x0096
+#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST                                                           0x00a0
+#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL                                                           0x00a2
+#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_LO                                                        0x00a4
+#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_HI                                                        0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA                                                           0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA                                                       0x00aa
+#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_MASK                                                               0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA_64                                                        0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA_64                                                    0x00ae
+#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_MASK_64                                                            0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_PENDING                                                            0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF6_MSI_PENDING_64                                                         0x00b4
+#define cfgBIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST                                                          0x00c0
+#define cfgBIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL                                                          0x00c2
+#define cfgBIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE                                                             0x00c4
+#define cfgBIF_CFG_DEV0_EPF0_VF6_MSIX_PBA                                                               0x00c8
+#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                      0x0100
+#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR                                               0x0104
+#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC1                                                  0x0108
+#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC2                                                  0x010c
+#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_DEVICE3_ENH_CAP_LIST                                              0x02d8
+#define cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP3                                                            0x02dc
+#define cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL3                                                           0x02e0
+#define cfgBIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS3                                                         0x02e4
+#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_NULL1_ENH_CAP_LIST                                                0x0400
+#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_NULL2_ENH_CAP_LIST                                                0x0600
+#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                          0x0604
+#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS                                                 0x0608
+#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK                                                   0x060c
+#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY                                               0x0610
+#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS                                                   0x0614
+#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK                                                     0x0618
+#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL                                                  0x061c
+#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG0                                                          0x0620
+#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG1                                                          0x0624
+#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG2                                                          0x0628
+#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG3                                                          0x062c
+#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG4                                                          0x063c
+#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG0                                                   0x063c
+#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG5                                                          0x0640
+#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG1                                                   0x0640
+#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG6                                                          0x0644
+#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG2                                                   0x0644
+#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG7                                                          0x0648
+#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG3                                                   0x0648
+#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG8                                                          0x064c
+#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG9                                                          0x0650
+#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG10                                                         0x0654
+#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG11                                                         0x0658
+#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG12                                                         0x065c
+#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG13                                                         0x0660
+#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_RTR_ENH_CAP_LIST                                                  0x071c
+#define cfgBIF_CFG_DEV0_EPF0_VF6_RTR_DATA1                                                              0x0720
+#define cfgBIF_CFG_DEV0_EPF0_VF6_RTR_DATA2                                                              0x0724
+#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST                                                  0x0770
+#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP                                                           0x0774
+#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL                                                          0x0776
+#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_ENH_CAP_LIST                                                  0x07ac
+#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP                                                           0x07b0
+#define cfgBIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CNTL                                                          0x07b2
+
+
+// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_vf7_bifcfgdecp
+// base address: 0x0
+#define cfgBIF_CFG_DEV0_EPF0_VF7_VENDOR_ID                                                              0x0000
+#define cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_ID                                                              0x0002
+#define cfgBIF_CFG_DEV0_EPF0_VF7_COMMAND                                                                0x0004
+#define cfgBIF_CFG_DEV0_EPF0_VF7_STATUS                                                                 0x0006
+#define cfgBIF_CFG_DEV0_EPF0_VF7_REVISION_ID                                                            0x0008
+#define cfgBIF_CFG_DEV0_EPF0_VF7_PROG_INTERFACE                                                         0x0009
+#define cfgBIF_CFG_DEV0_EPF0_VF7_SUB_CLASS                                                              0x000a
+#define cfgBIF_CFG_DEV0_EPF0_VF7_BASE_CLASS                                                             0x000b
+#define cfgBIF_CFG_DEV0_EPF0_VF7_CACHE_LINE                                                             0x000c
+#define cfgBIF_CFG_DEV0_EPF0_VF7_LATENCY                                                                0x000d
+#define cfgBIF_CFG_DEV0_EPF0_VF7_HEADER                                                                 0x000e
+#define cfgBIF_CFG_DEV0_EPF0_VF7_BIST                                                                   0x000f
+#define cfgBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_1                                                            0x0010
+#define cfgBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_2                                                            0x0014
+#define cfgBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_3                                                            0x0018
+#define cfgBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_4                                                            0x001c
+#define cfgBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_5                                                            0x0020
+#define cfgBIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_6                                                            0x0024
+#define cfgBIF_CFG_DEV0_EPF0_VF7_CARDBUS_CIS_PTR                                                        0x0028
+#define cfgBIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID                                                             0x002c
+#define cfgBIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR                                                          0x0030
+#define cfgBIF_CFG_DEV0_EPF0_VF7_CAP_PTR                                                                0x0034
+#define cfgBIF_CFG_DEV0_EPF0_VF7_INTERRUPT_LINE                                                         0x003c
+#define cfgBIF_CFG_DEV0_EPF0_VF7_INTERRUPT_PIN                                                          0x003d
+#define cfgBIF_CFG_DEV0_EPF0_VF7_MIN_GRANT                                                              0x003e
+#define cfgBIF_CFG_DEV0_EPF0_VF7_MAX_LATENCY                                                            0x003f
+#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST                                                          0x0064
+#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_CAP                                                               0x0066
+#define cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP                                                             0x0068
+#define cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL                                                            0x006c
+#define cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS                                                          0x006e
+#define cfgBIF_CFG_DEV0_EPF0_VF7_LINK_CAP                                                               0x0070
+#define cfgBIF_CFG_DEV0_EPF0_VF7_LINK_CNTL                                                              0x0074
+#define cfgBIF_CFG_DEV0_EPF0_VF7_LINK_STATUS                                                            0x0076
+#define cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2                                                            0x0088
+#define cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2                                                           0x008c
+#define cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS2                                                         0x008e
+#define cfgBIF_CFG_DEV0_EPF0_VF7_LINK_CAP2                                                              0x0090
+#define cfgBIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2                                                             0x0094
+#define cfgBIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2                                                           0x0096
+#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST                                                           0x00a0
+#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL                                                           0x00a2
+#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_LO                                                        0x00a4
+#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_HI                                                        0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA                                                           0x00a8
+#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA                                                       0x00aa
+#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_MASK                                                               0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA_64                                                        0x00ac
+#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA_64                                                    0x00ae
+#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_MASK_64                                                            0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_PENDING                                                            0x00b0
+#define cfgBIF_CFG_DEV0_EPF0_VF7_MSI_PENDING_64                                                         0x00b4
+#define cfgBIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST                                                          0x00c0
+#define cfgBIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL                                                          0x00c2
+#define cfgBIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE                                                             0x00c4
+#define cfgBIF_CFG_DEV0_EPF0_VF7_MSIX_PBA                                                               0x00c8
+#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                      0x0100
+#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR                                               0x0104
+#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC1                                                  0x0108
+#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC2                                                  0x010c
+#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_DEVICE3_ENH_CAP_LIST                                              0x02d8
+#define cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP3                                                            0x02dc
+#define cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL3                                                           0x02e0
+#define cfgBIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS3                                                         0x02e4
+#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_NULL1_ENH_CAP_LIST                                                0x0400
+#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_NULL2_ENH_CAP_LIST                                                0x0600
+#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                          0x0604
+#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS                                                 0x0608
+#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK                                                   0x060c
+#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY                                               0x0610
+#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS                                                   0x0614
+#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK                                                     0x0618
+#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL                                                  0x061c
+#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG0                                                          0x0620
+#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG1                                                          0x0624
+#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG2                                                          0x0628
+#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG3                                                          0x062c
+#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG4                                                          0x063c
+#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG0                                                   0x063c
+#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG5                                                          0x0640
+#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG1                                                   0x0640
+#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG6                                                          0x0644
+#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG2                                                   0x0644
+#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG7                                                          0x0648
+#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG3                                                   0x0648
+#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG8                                                          0x064c
+#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG9                                                          0x0650
+#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG10                                                         0x0654
+#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG11                                                         0x0658
+#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG12                                                         0x065c
+#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG13                                                         0x0660
+#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_RTR_ENH_CAP_LIST                                                  0x071c
+#define cfgBIF_CFG_DEV0_EPF0_VF7_RTR_DATA1                                                              0x0720
+#define cfgBIF_CFG_DEV0_EPF0_VF7_RTR_DATA2                                                              0x0724
+#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST                                                  0x0770
+#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP                                                           0x0774
+#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL                                                          0x0776
+#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_ENH_CAP_LIST                                                  0x07ac
+#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP                                                           0x07b0
+#define cfgBIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CNTL                                                          0x07b2
+
+
+// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf1_vf0_bifcfgdecp
+// base address: 0x0
+#define cfgBIF_CFG_DEV0_EPF1_VF0_VENDOR_ID                                                              0x0000
+#define cfgBIF_CFG_DEV0_EPF1_VF0_DEVICE_ID                                                              0x0002
+#define cfgBIF_CFG_DEV0_EPF1_VF0_COMMAND                                                                0x0004
+#define cfgBIF_CFG_DEV0_EPF1_VF0_STATUS                                                                 0x0006
+#define cfgBIF_CFG_DEV0_EPF1_VF0_REVISION_ID                                                            0x0008
+#define cfgBIF_CFG_DEV0_EPF1_VF0_PROG_INTERFACE                                                         0x0009
+#define cfgBIF_CFG_DEV0_EPF1_VF0_SUB_CLASS                                                              0x000a
+#define cfgBIF_CFG_DEV0_EPF1_VF0_BASE_CLASS                                                             0x000b
+#define cfgBIF_CFG_DEV0_EPF1_VF0_CACHE_LINE                                                             0x000c
+#define cfgBIF_CFG_DEV0_EPF1_VF0_LATENCY                                                                0x000d
+#define cfgBIF_CFG_DEV0_EPF1_VF0_HEADER                                                                 0x000e
+#define cfgBIF_CFG_DEV0_EPF1_VF0_BIST                                                                   0x000f
+#define cfgBIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_1                                                            0x0010
+#define cfgBIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_2                                                            0x0014
+#define cfgBIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_3                                                            0x0018
+#define cfgBIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_4                                                            0x001c
+#define cfgBIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_5                                                            0x0020
+#define cfgBIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_6                                                            0x0024
+#define cfgBIF_CFG_DEV0_EPF1_VF0_CARDBUS_CIS_PTR                                                        0x0028
+#define cfgBIF_CFG_DEV0_EPF1_VF0_ADAPTER_ID                                                             0x002c
+#define cfgBIF_CFG_DEV0_EPF1_VF0_ROM_BASE_ADDR                                                          0x0030
+#define cfgBIF_CFG_DEV0_EPF1_VF0_CAP_PTR                                                                0x0034
+#define cfgBIF_CFG_DEV0_EPF1_VF0_INTERRUPT_LINE                                                         0x003c
+#define cfgBIF_CFG_DEV0_EPF1_VF0_INTERRUPT_PIN                                                          0x003d
+#define cfgBIF_CFG_DEV0_EPF1_VF0_MIN_GRANT                                                              0x003e
+#define cfgBIF_CFG_DEV0_EPF1_VF0_MAX_LATENCY                                                            0x003f
+#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_CAP_LIST                                                          0x0064
+#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_CAP                                                               0x0066
+#define cfgBIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP                                                             0x0068
+#define cfgBIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL                                                            0x006c
+#define cfgBIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS                                                          0x006e
+#define cfgBIF_CFG_DEV0_EPF1_VF0_LINK_CAP                                                               0x0070
+#define cfgBIF_CFG_DEV0_EPF1_VF0_LINK_CNTL                                                              0x0074
+#define cfgBIF_CFG_DEV0_EPF1_VF0_LINK_STATUS                                                            0x0076
+#define cfgBIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2                                                            0x0088
+#define cfgBIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL2                                                           0x008c
+#define cfgBIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS2                                                         0x008e
+#define cfgBIF_CFG_DEV0_EPF1_VF0_LINK_CAP2                                                              0x0090
+#define cfgBIF_CFG_DEV0_EPF1_VF0_LINK_CNTL2                                                             0x0094
+#define cfgBIF_CFG_DEV0_EPF1_VF0_LINK_STATUS2                                                           0x0096
+#define cfgBIF_CFG_DEV0_EPF1_VF0_MSI_CAP_LIST                                                           0x00a0
+#define cfgBIF_CFG_DEV0_EPF1_VF0_MSI_MSG_CNTL                                                           0x00a2
+#define cfgBIF_CFG_DEV0_EPF1_VF0_MSI_MSG_ADDR_LO                                                        0x00a4
+#define cfgBIF_CFG_DEV0_EPF1_VF0_MSI_MSG_ADDR_HI                                                        0x00a8
+#define cfgBIF_CFG_DEV0_EPF1_VF0_MSI_MSG_DATA                                                           0x00a8
+#define cfgBIF_CFG_DEV0_EPF1_VF0_MSI_EXT_MSG_DATA                                                       0x00aa
+#define cfgBIF_CFG_DEV0_EPF1_VF0_MSI_MASK                                                               0x00ac
+#define cfgBIF_CFG_DEV0_EPF1_VF0_MSI_MSG_DATA_64                                                        0x00ac
+#define cfgBIF_CFG_DEV0_EPF1_VF0_MSI_EXT_MSG_DATA_64                                                    0x00ae
+#define cfgBIF_CFG_DEV0_EPF1_VF0_MSI_MASK_64                                                            0x00b0
+#define cfgBIF_CFG_DEV0_EPF1_VF0_MSI_PENDING                                                            0x00b0
+#define cfgBIF_CFG_DEV0_EPF1_VF0_MSI_PENDING_64                                                         0x00b4
+#define cfgBIF_CFG_DEV0_EPF1_VF0_MSIX_CAP_LIST                                                          0x00c0
+#define cfgBIF_CFG_DEV0_EPF1_VF0_MSIX_MSG_CNTL                                                          0x00c2
+#define cfgBIF_CFG_DEV0_EPF1_VF0_MSIX_TABLE                                                             0x00c4
+#define cfgBIF_CFG_DEV0_EPF1_VF0_MSIX_PBA                                                               0x00c8
+#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST                                      0x0100
+#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC_HDR                                               0x0104
+#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC1                                                  0x0108
+#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC2                                                  0x010c
+#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_DEVICE3_ENH_CAP_LIST                                              0x02d8
+#define cfgBIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP3                                                            0x02dc
+#define cfgBIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL3                                                           0x02e0
+#define cfgBIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS3                                                         0x02e4
+#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_NULL1_ENH_CAP_LIST                                                0x0400
+#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_NULL2_ENH_CAP_LIST                                                0x0600
+#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST                                          0x0604
+#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS                                                 0x0608
+#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK                                                   0x060c
+#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY                                               0x0610
+#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_STATUS                                                   0x0614
+#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_MASK                                                     0x0618
+#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_CAP_CNTL                                                  0x061c
+#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG0                                                          0x0620
+#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG1                                                          0x0624
+#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG2                                                          0x0628
+#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG3                                                          0x062c
+#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG4                                                          0x063c
+#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_TLP_PREFIX_LOG0                                                   0x063c
+#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG5                                                          0x0640
+#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_TLP_PREFIX_LOG1                                                   0x0640
+#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG6                                                          0x0644
+#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_TLP_PREFIX_LOG2                                                   0x0644
+#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG7                                                          0x0648
+#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_TLP_PREFIX_LOG3                                                   0x0648
+#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG8                                                          0x064c
+#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG9                                                          0x0650
+#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG10                                                         0x0654
+#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG11                                                         0x0658
+#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG12                                                         0x065c
+#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG13                                                         0x0660
+#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_RTR_ENH_CAP_LIST                                                  0x071c
+#define cfgBIF_CFG_DEV0_EPF1_VF0_RTR_DATA1                                                              0x0720
+#define cfgBIF_CFG_DEV0_EPF1_VF0_RTR_DATA2                                                              0x0724
+#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_ENH_CAP_LIST                                                  0x0770
+#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_CAP                                                           0x0774
+#define cfgBIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_CNTL                                                          0x0776
+
+
+#endif
diff --git a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_3_2_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_3_2_sh_mask.h
new file mode 100644
index 000000000000..9f8f8b3eba02
--- /dev/null
+++ b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_6_3_2_sh_mask.h
@@ -0,0 +1,49475 @@
+/*
+ * Copyright 2025 Advanced Micro Devices, Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ */
+#ifndef _nbio_6_3_2_SH_MASK_HEADER
+#define _nbio_6_3_2_SH_MASK_HEADER
+
+
+// addressBlock: nbif0_nbif0_bif_bx_SYSDEC
+//BIF_BX0_SYSHUB_INDEX_OVLP
+#define BIF_BX0_SYSHUB_INDEX_OVLP__SYSHUB_OFFSET__SHIFT                                                       0x0
+#define BIF_BX0_SYSHUB_INDEX_OVLP__SYSHUB_OFFSET_MASK                                                         0x003FFFFFL
+//BIF_BX0_SYSHUB_DATA_OVLP
+#define BIF_BX0_SYSHUB_DATA_OVLP__SYSHUB_DATA__SHIFT                                                          0x0
+#define BIF_BX0_SYSHUB_DATA_OVLP__SYSHUB_DATA_MASK                                                            0xFFFFFFFFL
+//BIF_BX0_SYSHUB_INDEX_HI_OVLP
+#define BIF_BX0_SYSHUB_INDEX_HI_OVLP__SYSHUB_OFFSET_HI__SHIFT                                                 0x0
+#define BIF_BX0_SYSHUB_INDEX_HI_OVLP__SYSHUB_OFFSET_HI_MASK                                                   0x0000FFFFL
+//BIF_BX0_PCIE_INDEX
+#define BIF_BX0_PCIE_INDEX__PCIE_INDEX__SHIFT                                                                 0x0
+#define BIF_BX0_PCIE_INDEX__PCIE_INDEX_MASK                                                                   0xFFFFFFFFL
+//BIF_BX0_PCIE_DATA
+#define BIF_BX0_PCIE_DATA__PCIE_DATA__SHIFT                                                                   0x0
+#define BIF_BX0_PCIE_DATA__PCIE_DATA_MASK                                                                     0xFFFFFFFFL
+//BIF_BX0_PCIE_INDEX2
+#define BIF_BX0_PCIE_INDEX2__PCIE_INDEX2__SHIFT                                                               0x0
+#define BIF_BX0_PCIE_INDEX2__PCIE_INDEX2_MASK                                                                 0xFFFFFFFFL
+//BIF_BX0_PCIE_DATA2
+#define BIF_BX0_PCIE_DATA2__PCIE_DATA2__SHIFT                                                                 0x0
+#define BIF_BX0_PCIE_DATA2__PCIE_DATA2_MASK                                                                   0xFFFFFFFFL
+//BIF_BX0_PCIE_INDEX_HI
+#define BIF_BX0_PCIE_INDEX_HI__PCIE_INDEX_HI__SHIFT                                                           0x0
+#define BIF_BX0_PCIE_INDEX_HI__PCIE_INDEX_HI_MASK                                                             0x0000FFFFL
+//BIF_BX0_PCIE_INDEX2_HI
+#define BIF_BX0_PCIE_INDEX2_HI__PCIE_INDEX2_HI__SHIFT                                                         0x0
+#define BIF_BX0_PCIE_INDEX2_HI__PCIE_INDEX2_HI_MASK                                                           0x0000FFFFL
+//BIF_BX0_SBIOS_SCRATCH_0
+#define BIF_BX0_SBIOS_SCRATCH_0__SBIOS_SCRATCH_0__SHIFT                                                       0x0
+#define BIF_BX0_SBIOS_SCRATCH_0__SBIOS_SCRATCH_0_MASK                                                         0xFFFFFFFFL
+//BIF_BX0_SBIOS_SCRATCH_1
+#define BIF_BX0_SBIOS_SCRATCH_1__SBIOS_SCRATCH_1__SHIFT                                                       0x0
+#define BIF_BX0_SBIOS_SCRATCH_1__SBIOS_SCRATCH_1_MASK                                                         0xFFFFFFFFL
+//BIF_BX0_SBIOS_SCRATCH_2
+#define BIF_BX0_SBIOS_SCRATCH_2__SBIOS_SCRATCH_2__SHIFT                                                       0x0
+#define BIF_BX0_SBIOS_SCRATCH_2__SBIOS_SCRATCH_2_MASK                                                         0xFFFFFFFFL
+//BIF_BX0_SBIOS_SCRATCH_3
+#define BIF_BX0_SBIOS_SCRATCH_3__SBIOS_SCRATCH_3__SHIFT                                                       0x0
+#define BIF_BX0_SBIOS_SCRATCH_3__SBIOS_SCRATCH_3_MASK                                                         0xFFFFFFFFL
+//BIF_BX0_BIOS_SCRATCH_0
+#define BIF_BX0_BIOS_SCRATCH_0__BIOS_SCRATCH_0__SHIFT                                                         0x0
+#define BIF_BX0_BIOS_SCRATCH_0__BIOS_SCRATCH_0_MASK                                                           0xFFFFFFFFL
+//BIF_BX0_BIOS_SCRATCH_1
+#define BIF_BX0_BIOS_SCRATCH_1__BIOS_SCRATCH_1__SHIFT                                                         0x0
+#define BIF_BX0_BIOS_SCRATCH_1__BIOS_SCRATCH_1_MASK                                                           0xFFFFFFFFL
+//BIF_BX0_BIOS_SCRATCH_2
+#define BIF_BX0_BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT                                                         0x0
+#define BIF_BX0_BIOS_SCRATCH_2__BIOS_SCRATCH_2_MASK                                                           0xFFFFFFFFL
+//BIF_BX0_BIOS_SCRATCH_3
+#define BIF_BX0_BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT                                                         0x0
+#define BIF_BX0_BIOS_SCRATCH_3__BIOS_SCRATCH_3_MASK                                                           0xFFFFFFFFL
+//BIF_BX0_BIOS_SCRATCH_4
+#define BIF_BX0_BIOS_SCRATCH_4__BIOS_SCRATCH_4__SHIFT                                                         0x0
+#define BIF_BX0_BIOS_SCRATCH_4__BIOS_SCRATCH_4_MASK                                                           0xFFFFFFFFL
+//BIF_BX0_BIOS_SCRATCH_5
+#define BIF_BX0_BIOS_SCRATCH_5__BIOS_SCRATCH_5__SHIFT                                                         0x0
+#define BIF_BX0_BIOS_SCRATCH_5__BIOS_SCRATCH_5_MASK                                                           0xFFFFFFFFL
+//BIF_BX0_BIOS_SCRATCH_6
+#define BIF_BX0_BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT                                                         0x0
+#define BIF_BX0_BIOS_SCRATCH_6__BIOS_SCRATCH_6_MASK                                                           0xFFFFFFFFL
+//BIF_BX0_BIOS_SCRATCH_7
+#define BIF_BX0_BIOS_SCRATCH_7__BIOS_SCRATCH_7__SHIFT                                                         0x0
+#define BIF_BX0_BIOS_SCRATCH_7__BIOS_SCRATCH_7_MASK                                                           0xFFFFFFFFL
+//BIF_BX0_BIOS_SCRATCH_8
+#define BIF_BX0_BIOS_SCRATCH_8__BIOS_SCRATCH_8__SHIFT                                                         0x0
+#define BIF_BX0_BIOS_SCRATCH_8__BIOS_SCRATCH_8_MASK                                                           0xFFFFFFFFL
+//BIF_BX0_BIOS_SCRATCH_9
+#define BIF_BX0_BIOS_SCRATCH_9__BIOS_SCRATCH_9__SHIFT                                                         0x0
+#define BIF_BX0_BIOS_SCRATCH_9__BIOS_SCRATCH_9_MASK                                                           0xFFFFFFFFL
+//BIF_BX0_BIOS_SCRATCH_10
+#define BIF_BX0_BIOS_SCRATCH_10__BIOS_SCRATCH_10__SHIFT                                                       0x0
+#define BIF_BX0_BIOS_SCRATCH_10__BIOS_SCRATCH_10_MASK                                                         0xFFFFFFFFL
+//BIF_BX0_BIOS_SCRATCH_11
+#define BIF_BX0_BIOS_SCRATCH_11__BIOS_SCRATCH_11__SHIFT                                                       0x0
+#define BIF_BX0_BIOS_SCRATCH_11__BIOS_SCRATCH_11_MASK                                                         0xFFFFFFFFL
+//BIF_BX0_BIOS_SCRATCH_12
+#define BIF_BX0_BIOS_SCRATCH_12__BIOS_SCRATCH_12__SHIFT                                                       0x0
+#define BIF_BX0_BIOS_SCRATCH_12__BIOS_SCRATCH_12_MASK                                                         0xFFFFFFFFL
+//BIF_BX0_BIOS_SCRATCH_13
+#define BIF_BX0_BIOS_SCRATCH_13__BIOS_SCRATCH_13__SHIFT                                                       0x0
+#define BIF_BX0_BIOS_SCRATCH_13__BIOS_SCRATCH_13_MASK                                                         0xFFFFFFFFL
+//BIF_BX0_BIOS_SCRATCH_14
+#define BIF_BX0_BIOS_SCRATCH_14__BIOS_SCRATCH_14__SHIFT                                                       0x0
+#define BIF_BX0_BIOS_SCRATCH_14__BIOS_SCRATCH_14_MASK                                                         0xFFFFFFFFL
+//BIF_BX0_BIOS_SCRATCH_15
+#define BIF_BX0_BIOS_SCRATCH_15__BIOS_SCRATCH_15__SHIFT                                                       0x0
+#define BIF_BX0_BIOS_SCRATCH_15__BIOS_SCRATCH_15_MASK                                                         0xFFFFFFFFL
+//BIF_BX0_BIF_RLC_INTR_CNTL
+//BIF_BX0_BIF_VCE_INTR_CNTL
+//BIF_BX0_BIF_UVD_INTR_CNTL
+//BIF_BX0_BIF_Engine_INTR_CNTL
+#define BIF_BX0_BIF_Engine_INTR_CNTL__Engine_CMD_COMPLETE__SHIFT                                              0x0
+#define BIF_BX0_BIF_Engine_INTR_CNTL__Engine_HANG_SELF_RECOVERED__SHIFT                                       0x1
+#define BIF_BX0_BIF_Engine_INTR_CNTL__Engine_HANG_NEED_FLR__SHIFT                                             0x2
+#define BIF_BX0_BIF_Engine_INTR_CNTL__Engine_VM_BUSY_TRANSITION__SHIFT                                        0x3
+#define BIF_BX0_BIF_Engine_INTR_CNTL__Engine_INST_SEL__SHIFT                                                  0x1b
+#define BIF_BX0_BIF_Engine_INTR_CNTL__Engine_CMD_COMPLETE_MASK                                                0x00000001L
+#define BIF_BX0_BIF_Engine_INTR_CNTL__Engine_HANG_SELF_RECOVERED_MASK                                         0x00000002L
+#define BIF_BX0_BIF_Engine_INTR_CNTL__Engine_HANG_NEED_FLR_MASK                                               0x00000004L
+#define BIF_BX0_BIF_Engine_INTR_CNTL__Engine_VM_BUSY_TRANSITION_MASK                                          0x00000008L
+#define BIF_BX0_BIF_Engine_INTR_CNTL__Engine_INST_SEL_MASK                                                    0xF8000000L
+//BIF_BX0_GFX_MMIOREG_CAM_ADDR0
+#define BIF_BX0_GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0__SHIFT                                                       0x0
+#define BIF_BX0_GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0_MASK                                                         0x000FFFFFL
+//BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR0
+#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0__SHIFT                                           0x0
+#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0_MASK                                             0x000FFFFFL
+//BIF_BX0_GFX_MMIOREG_CAM_ADDR1
+#define BIF_BX0_GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1__SHIFT                                                       0x0
+#define BIF_BX0_GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1_MASK                                                         0x000FFFFFL
+//BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR1
+#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1__SHIFT                                           0x0
+#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1_MASK                                             0x000FFFFFL
+//BIF_BX0_GFX_MMIOREG_CAM_ADDR2
+#define BIF_BX0_GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2__SHIFT                                                       0x0
+#define BIF_BX0_GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2_MASK                                                         0x000FFFFFL
+//BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR2
+#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2__SHIFT                                           0x0
+#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2_MASK                                             0x000FFFFFL
+//BIF_BX0_GFX_MMIOREG_CAM_ADDR3
+#define BIF_BX0_GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3__SHIFT                                                       0x0
+#define BIF_BX0_GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3_MASK                                                         0x000FFFFFL
+//BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR3
+#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3__SHIFT                                           0x0
+#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3_MASK                                             0x000FFFFFL
+//BIF_BX0_GFX_MMIOREG_CAM_ADDR4
+#define BIF_BX0_GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4__SHIFT                                                       0x0
+#define BIF_BX0_GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4_MASK                                                         0x000FFFFFL
+//BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR4
+#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4__SHIFT                                           0x0
+#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4_MASK                                             0x000FFFFFL
+//BIF_BX0_GFX_MMIOREG_CAM_ADDR5
+#define BIF_BX0_GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5__SHIFT                                                       0x0
+#define BIF_BX0_GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5_MASK                                                         0x000FFFFFL
+//BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR5
+#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5__SHIFT                                           0x0
+#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5_MASK                                             0x000FFFFFL
+//BIF_BX0_GFX_MMIOREG_CAM_ADDR6
+#define BIF_BX0_GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6__SHIFT                                                       0x0
+#define BIF_BX0_GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6_MASK                                                         0x000FFFFFL
+//BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR6
+#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6__SHIFT                                           0x0
+#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6_MASK                                             0x000FFFFFL
+//BIF_BX0_GFX_MMIOREG_CAM_ADDR7
+#define BIF_BX0_GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7__SHIFT                                                       0x0
+#define BIF_BX0_GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7_MASK                                                         0x000FFFFFL
+//BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR7
+#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7__SHIFT                                           0x0
+#define BIF_BX0_GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7_MASK                                             0x000FFFFFL
+//BIF_BX0_GFX_MMIOREG_CAM_CNTL
+#define BIF_BX0_GFX_MMIOREG_CAM_CNTL__CAM_ENABLE__SHIFT                                                       0x0
+#define BIF_BX0_GFX_MMIOREG_CAM_CNTL__CAM_ENABLE_MASK                                                         0x000000FFL
+//BIF_BX0_GFX_MMIOREG_CAM_ZERO_CPL
+#define BIF_BX0_GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL__SHIFT                                                 0x0
+#define BIF_BX0_GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL_MASK                                                   0xFFFFFFFFL
+//BIF_BX0_GFX_MMIOREG_CAM_ONE_CPL
+#define BIF_BX0_GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL__SHIFT                                                   0x0
+#define BIF_BX0_GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL_MASK                                                     0xFFFFFFFFL
+//BIF_BX0_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL
+#define BIF_BX0_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL__SHIFT                                 0x0
+#define BIF_BX0_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL_MASK                                   0xFFFFFFFFL
+//BIF_BX0_DRIVER_SCRATCH_0
+#define BIF_BX0_DRIVER_SCRATCH_0__DRIVER_SCRATCH_0__SHIFT                                                     0x0
+#define BIF_BX0_DRIVER_SCRATCH_0__DRIVER_SCRATCH_0_MASK                                                       0xFFFFFFFFL
+//BIF_BX0_DRIVER_SCRATCH_1
+#define BIF_BX0_DRIVER_SCRATCH_1__DRIVER_SCRATCH_1__SHIFT                                                     0x0
+#define BIF_BX0_DRIVER_SCRATCH_1__DRIVER_SCRATCH_1_MASK                                                       0xFFFFFFFFL
+//BIF_BX0_DRIVER_SCRATCH_2
+#define BIF_BX0_DRIVER_SCRATCH_2__DRIVER_SCRATCH_2__SHIFT                                                     0x0
+#define BIF_BX0_DRIVER_SCRATCH_2__DRIVER_SCRATCH_2_MASK                                                       0xFFFFFFFFL
+//BIF_BX0_DRIVER_SCRATCH_3
+#define BIF_BX0_DRIVER_SCRATCH_3__DRIVER_SCRATCH_3__SHIFT                                                     0x0
+#define BIF_BX0_DRIVER_SCRATCH_3__DRIVER_SCRATCH_3_MASK                                                       0xFFFFFFFFL
+//BIF_BX0_DRIVER_SCRATCH_4
+#define BIF_BX0_DRIVER_SCRATCH_4__DRIVER_SCRATCH_4__SHIFT                                                     0x0
+#define BIF_BX0_DRIVER_SCRATCH_4__DRIVER_SCRATCH_4_MASK                                                       0xFFFFFFFFL
+//BIF_BX0_DRIVER_SCRATCH_5
+#define BIF_BX0_DRIVER_SCRATCH_5__DRIVER_SCRATCH_5__SHIFT                                                     0x0
+#define BIF_BX0_DRIVER_SCRATCH_5__DRIVER_SCRATCH_5_MASK                                                       0xFFFFFFFFL
+//BIF_BX0_DRIVER_SCRATCH_6
+#define BIF_BX0_DRIVER_SCRATCH_6__DRIVER_SCRATCH_6__SHIFT                                                     0x0
+#define BIF_BX0_DRIVER_SCRATCH_6__DRIVER_SCRATCH_6_MASK                                                       0xFFFFFFFFL
+//BIF_BX0_DRIVER_SCRATCH_7
+#define BIF_BX0_DRIVER_SCRATCH_7__DRIVER_SCRATCH_7__SHIFT                                                     0x0
+#define BIF_BX0_DRIVER_SCRATCH_7__DRIVER_SCRATCH_7_MASK                                                       0xFFFFFFFFL
+//BIF_BX0_DRIVER_SCRATCH_8
+#define BIF_BX0_DRIVER_SCRATCH_8__DRIVER_SCRATCH_8__SHIFT                                                     0x0
+#define BIF_BX0_DRIVER_SCRATCH_8__DRIVER_SCRATCH_8_MASK                                                       0xFFFFFFFFL
+//BIF_BX0_DRIVER_SCRATCH_9
+#define BIF_BX0_DRIVER_SCRATCH_9__DRIVER_SCRATCH_9__SHIFT                                                     0x0
+#define BIF_BX0_DRIVER_SCRATCH_9__DRIVER_SCRATCH_9_MASK                                                       0xFFFFFFFFL
+//BIF_BX0_DRIVER_SCRATCH_10
+#define BIF_BX0_DRIVER_SCRATCH_10__DRIVER_SCRATCH_10__SHIFT                                                   0x0
+#define BIF_BX0_DRIVER_SCRATCH_10__DRIVER_SCRATCH_10_MASK                                                     0xFFFFFFFFL
+//BIF_BX0_DRIVER_SCRATCH_11
+#define BIF_BX0_DRIVER_SCRATCH_11__DRIVER_SCRATCH_11__SHIFT                                                   0x0
+#define BIF_BX0_DRIVER_SCRATCH_11__DRIVER_SCRATCH_11_MASK                                                     0xFFFFFFFFL
+//BIF_BX0_DRIVER_SCRATCH_12
+#define BIF_BX0_DRIVER_SCRATCH_12__DRIVER_SCRATCH_12__SHIFT                                                   0x0
+#define BIF_BX0_DRIVER_SCRATCH_12__DRIVER_SCRATCH_12_MASK                                                     0xFFFFFFFFL
+//BIF_BX0_DRIVER_SCRATCH_13
+#define BIF_BX0_DRIVER_SCRATCH_13__DRIVER_SCRATCH_13__SHIFT                                                   0x0
+#define BIF_BX0_DRIVER_SCRATCH_13__DRIVER_SCRATCH_13_MASK                                                     0xFFFFFFFFL
+//BIF_BX0_DRIVER_SCRATCH_14
+#define BIF_BX0_DRIVER_SCRATCH_14__DRIVER_SCRATCH_14__SHIFT                                                   0x0
+#define BIF_BX0_DRIVER_SCRATCH_14__DRIVER_SCRATCH_14_MASK                                                     0xFFFFFFFFL
+//BIF_BX0_DRIVER_SCRATCH_15
+#define BIF_BX0_DRIVER_SCRATCH_15__DRIVER_SCRATCH_15__SHIFT                                                   0x0
+#define BIF_BX0_DRIVER_SCRATCH_15__DRIVER_SCRATCH_15_MASK                                                     0xFFFFFFFFL
+//BIF_BX0_FW_SCRATCH_0
+#define BIF_BX0_FW_SCRATCH_0__FW_SCRATCH_0__SHIFT                                                             0x0
+#define BIF_BX0_FW_SCRATCH_0__FW_SCRATCH_0_MASK                                                               0xFFFFFFFFL
+//BIF_BX0_FW_SCRATCH_1
+#define BIF_BX0_FW_SCRATCH_1__FW_SCRATCH_1__SHIFT                                                             0x0
+#define BIF_BX0_FW_SCRATCH_1__FW_SCRATCH_1_MASK                                                               0xFFFFFFFFL
+//BIF_BX0_FW_SCRATCH_2
+#define BIF_BX0_FW_SCRATCH_2__FW_SCRATCH_2__SHIFT                                                             0x0
+#define BIF_BX0_FW_SCRATCH_2__FW_SCRATCH_2_MASK                                                               0xFFFFFFFFL
+//BIF_BX0_FW_SCRATCH_3
+#define BIF_BX0_FW_SCRATCH_3__FW_SCRATCH_3__SHIFT                                                             0x0
+#define BIF_BX0_FW_SCRATCH_3__FW_SCRATCH_3_MASK                                                               0xFFFFFFFFL
+//BIF_BX0_FW_SCRATCH_4
+#define BIF_BX0_FW_SCRATCH_4__FW_SCRATCH_4__SHIFT                                                             0x0
+#define BIF_BX0_FW_SCRATCH_4__FW_SCRATCH_4_MASK                                                               0xFFFFFFFFL
+//BIF_BX0_FW_SCRATCH_5
+#define BIF_BX0_FW_SCRATCH_5__FW_SCRATCH_5__SHIFT                                                             0x0
+#define BIF_BX0_FW_SCRATCH_5__FW_SCRATCH_5_MASK                                                               0xFFFFFFFFL
+//BIF_BX0_FW_SCRATCH_6
+#define BIF_BX0_FW_SCRATCH_6__FW_SCRATCH_6__SHIFT                                                             0x0
+#define BIF_BX0_FW_SCRATCH_6__FW_SCRATCH_6_MASK                                                               0xFFFFFFFFL
+//BIF_BX0_FW_SCRATCH_7
+#define BIF_BX0_FW_SCRATCH_7__FW_SCRATCH_7__SHIFT                                                             0x0
+#define BIF_BX0_FW_SCRATCH_7__FW_SCRATCH_7_MASK                                                               0xFFFFFFFFL
+//BIF_BX0_FW_SCRATCH_8
+#define BIF_BX0_FW_SCRATCH_8__FW_SCRATCH_8__SHIFT                                                             0x0
+#define BIF_BX0_FW_SCRATCH_8__FW_SCRATCH_8_MASK                                                               0xFFFFFFFFL
+//BIF_BX0_FW_SCRATCH_9
+#define BIF_BX0_FW_SCRATCH_9__FW_SCRATCH_9__SHIFT                                                             0x0
+#define BIF_BX0_FW_SCRATCH_9__FW_SCRATCH_9_MASK                                                               0xFFFFFFFFL
+//BIF_BX0_FW_SCRATCH_10
+#define BIF_BX0_FW_SCRATCH_10__FW_SCRATCH_10__SHIFT                                                           0x0
+#define BIF_BX0_FW_SCRATCH_10__FW_SCRATCH_10_MASK                                                             0xFFFFFFFFL
+//BIF_BX0_FW_SCRATCH_11
+#define BIF_BX0_FW_SCRATCH_11__FW_SCRATCH_11__SHIFT                                                           0x0
+#define BIF_BX0_FW_SCRATCH_11__FW_SCRATCH_11_MASK                                                             0xFFFFFFFFL
+//BIF_BX0_FW_SCRATCH_12
+#define BIF_BX0_FW_SCRATCH_12__FW_SCRATCH_12__SHIFT                                                           0x0
+#define BIF_BX0_FW_SCRATCH_12__FW_SCRATCH_12_MASK                                                             0xFFFFFFFFL
+//BIF_BX0_FW_SCRATCH_13
+#define BIF_BX0_FW_SCRATCH_13__FW_SCRATCH_13__SHIFT                                                           0x0
+#define BIF_BX0_FW_SCRATCH_13__FW_SCRATCH_13_MASK                                                             0xFFFFFFFFL
+//BIF_BX0_FW_SCRATCH_14
+#define BIF_BX0_FW_SCRATCH_14__FW_SCRATCH_14__SHIFT                                                           0x0
+#define BIF_BX0_FW_SCRATCH_14__FW_SCRATCH_14_MASK                                                             0xFFFFFFFFL
+//BIF_BX0_FW_SCRATCH_15
+#define BIF_BX0_FW_SCRATCH_15__FW_SCRATCH_15__SHIFT                                                           0x0
+#define BIF_BX0_FW_SCRATCH_15__FW_SCRATCH_15_MASK                                                             0xFFFFFFFFL
+//BIF_BX0_SBIOS_SCRATCH_4
+#define BIF_BX0_SBIOS_SCRATCH_4__SBIOS_SCRATCH_4__SHIFT                                                       0x0
+#define BIF_BX0_SBIOS_SCRATCH_4__SBIOS_SCRATCH_4_MASK                                                         0xFFFFFFFFL
+//BIF_BX0_SBIOS_SCRATCH_5
+#define BIF_BX0_SBIOS_SCRATCH_5__SBIOS_SCRATCH_5__SHIFT                                                       0x0
+#define BIF_BX0_SBIOS_SCRATCH_5__SBIOS_SCRATCH_5_MASK                                                         0xFFFFFFFFL
+//BIF_BX0_SBIOS_SCRATCH_6
+#define BIF_BX0_SBIOS_SCRATCH_6__SBIOS_SCRATCH_6__SHIFT                                                       0x0
+#define BIF_BX0_SBIOS_SCRATCH_6__SBIOS_SCRATCH_6_MASK                                                         0xFFFFFFFFL
+//BIF_BX0_SBIOS_SCRATCH_7
+#define BIF_BX0_SBIOS_SCRATCH_7__SBIOS_SCRATCH_7__SHIFT                                                       0x0
+#define BIF_BX0_SBIOS_SCRATCH_7__SBIOS_SCRATCH_7_MASK                                                         0xFFFFFFFFL
+//BIF_BX0_SBIOS_SCRATCH_8
+#define BIF_BX0_SBIOS_SCRATCH_8__SBIOS_SCRATCH_8__SHIFT                                                       0x0
+#define BIF_BX0_SBIOS_SCRATCH_8__SBIOS_SCRATCH_8_MASK                                                         0xFFFFFFFFL
+//BIF_BX0_SBIOS_SCRATCH_9
+#define BIF_BX0_SBIOS_SCRATCH_9__SBIOS_SCRATCH_9__SHIFT                                                       0x0
+#define BIF_BX0_SBIOS_SCRATCH_9__SBIOS_SCRATCH_9_MASK                                                         0xFFFFFFFFL
+//BIF_BX0_SBIOS_SCRATCH_10
+#define BIF_BX0_SBIOS_SCRATCH_10__SBIOS_SCRATCH_10__SHIFT                                                     0x0
+#define BIF_BX0_SBIOS_SCRATCH_10__SBIOS_SCRATCH_10_MASK                                                       0xFFFFFFFFL
+//BIF_BX0_SBIOS_SCRATCH_11
+#define BIF_BX0_SBIOS_SCRATCH_11__SBIOS_SCRATCH_11__SHIFT                                                     0x0
+#define BIF_BX0_SBIOS_SCRATCH_11__SBIOS_SCRATCH_11_MASK                                                       0xFFFFFFFFL
+//BIF_BX0_SBIOS_SCRATCH_12
+#define BIF_BX0_SBIOS_SCRATCH_12__SBIOS_SCRATCH_12__SHIFT                                                     0x0
+#define BIF_BX0_SBIOS_SCRATCH_12__SBIOS_SCRATCH_12_MASK                                                       0xFFFFFFFFL
+//BIF_BX0_SBIOS_SCRATCH_13
+#define BIF_BX0_SBIOS_SCRATCH_13__SBIOS_SCRATCH_13__SHIFT                                                     0x0
+#define BIF_BX0_SBIOS_SCRATCH_13__SBIOS_SCRATCH_13_MASK                                                       0xFFFFFFFFL
+//BIF_BX0_SBIOS_SCRATCH_14
+#define BIF_BX0_SBIOS_SCRATCH_14__SBIOS_SCRATCH_14__SHIFT                                                     0x0
+#define BIF_BX0_SBIOS_SCRATCH_14__SBIOS_SCRATCH_14_MASK                                                       0xFFFFFFFFL
+//BIF_BX0_SBIOS_SCRATCH_15
+#define BIF_BX0_SBIOS_SCRATCH_15__SBIOS_SCRATCH_15__SHIFT                                                     0x0
+#define BIF_BX0_SBIOS_SCRATCH_15__SBIOS_SCRATCH_15_MASK                                                       0xFFFFFFFFL
+
+
+// addressBlock: nbif0_nbif0_rcc_dwn_dev0_BIFDEC1
+//RCC_DWN_DEV0_0_DN_PCIE_RESERVED
+#define RCC_DWN_DEV0_0_DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT                                                 0x0
+#define RCC_DWN_DEV0_0_DN_PCIE_RESERVED__PCIE_RESERVED_MASK                                                   0xFFFFFFFFL
+//RCC_DWN_DEV0_0_DN_PCIE_SCRATCH
+#define RCC_DWN_DEV0_0_DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT                                                   0x0
+#define RCC_DWN_DEV0_0_DN_PCIE_SCRATCH__PCIE_SCRATCH_MASK                                                     0xFFFFFFFFL
+//RCC_DWN_DEV0_0_DN_PCIE_CNTL
+#define RCC_DWN_DEV0_0_DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT                                                    0x0
+#define RCC_DWN_DEV0_0_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT                                              0x7
+#define RCC_DWN_DEV0_0_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT                                              0x1e
+#define RCC_DWN_DEV0_0_DN_PCIE_CNTL__HWINIT_WR_LOCK_MASK                                                      0x00000001L
+#define RCC_DWN_DEV0_0_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN_MASK                                                0x00000080L
+#define RCC_DWN_DEV0_0_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK                                                0x40000000L
+//RCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL
+#define RCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT                                0x19
+#define RCC_DWN_DEV0_0_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK                                  0x06000000L
+//RCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2
+#define RCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT                                               0x1c
+#define RCC_DWN_DEV0_0_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK                                                 0x70000000L
+//RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL
+#define RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT                                             0x7
+#define RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT                                   0x8
+#define RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK                                               0x00000080L
+#define RCC_DWN_DEV0_0_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN_MASK                                     0x00000100L
+//RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL
+#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT                                      0x0
+#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT                                 0x1
+#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT                                 0x2
+#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT                                 0x3
+#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT                                 0x4
+#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN6_HIDDEN_REG__SHIFT                                 0x5
+#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK                                        0x00000001L
+#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK                                   0x00000002L
+#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK                                   0x00000004L
+#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK                                   0x00000008L
+#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK                                   0x00000010L
+#define RCC_DWN_DEV0_0_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN6_HIDDEN_REG_MASK                                   0x00000020L
+//RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0
+#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_EN__SHIFT                                                   0x0
+#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT                                                0x11
+#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__SHIFT                                        0x15
+#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_EN_MASK                                                     0x00000001L
+#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN_MASK                                                  0x00020000L
+#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP_MASK                                          0x00E00000L
+//RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC
+#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT                                             0x18
+#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT                                          0x1d
+#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK                                               0x01000000L
+#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK                                            0x20000000L
+//RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC2
+#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT                                    0x2
+#define RCC_DWN_DEV0_0_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK                                      0x00000004L
+
+
+// addressBlock: nbif0_nbif0_rcc_dwnp_dev0_BIFDEC1
+//RCC_DWNP_DEV0_0_PCIE_ERR_CNTL
+#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT                                               0x0
+#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT                                             0x8
+#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT                                    0xb
+#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT                                        0x11
+#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR__SHIFT                                               0x12
+#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR__SHIFT                                           0x13
+#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR__SHIFT                                              0x14
+#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK                                                 0x00000001L
+#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK                                               0x00000700L
+#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK                                      0x00000800L
+#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK                                          0x00020000L
+#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR_MASK                                                 0x00040000L
+#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR_MASK                                             0x00080000L
+#define RCC_DWNP_DEV0_0_PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR_MASK                                                0x00100000L
+//RCC_DWNP_DEV0_0_PCIE_RX_CNTL
+#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT                                        0x8
+#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT                                              0x9
+#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT                                          0x14
+#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT                                     0x15
+#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT                                           0x1b
+#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK                                          0x00000100L
+#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN_MASK                                                0x00000200L
+#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK                                            0x00100000L
+#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN_MASK                                       0x00200000L
+#define RCC_DWNP_DEV0_0_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK                                             0x08000000L
+//RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL
+#define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT                                           0x0
+#define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT                                           0x1
+#define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT                                           0x2
+#define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP__SHIFT                                           0x3
+#define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN6_EN_STRAP__SHIFT                                           0x4
+#define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK                                             0x00000001L
+#define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK                                             0x00000002L
+#define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK                                             0x00000004L
+#define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP_MASK                                             0x00000008L
+#define RCC_DWNP_DEV0_0_PCIE_LC_SPEED_CNTL__LC_GEN6_EN_STRAP_MASK                                             0x00000010L
+//RCC_DWNP_DEV0_0_PCIE_LC_CNTL2
+#define RCC_DWNP_DEV0_0_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS__SHIFT                               0x0
+#define RCC_DWNP_DEV0_0_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT                                     0x1b
+#define RCC_DWNP_DEV0_0_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS_MASK                                 0x00000001L
+#define RCC_DWNP_DEV0_0_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK                                       0x08000000L
+//RCC_DWNP_DEV0_0_PCIEP_STRAP_MISC
+#define RCC_DWNP_DEV0_0_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN__SHIFT                                          0xa
+#define RCC_DWNP_DEV0_0_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN_MASK                                            0x00000400L
+//RCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP
+#define RCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT                                     0x0
+#define RCC_DWNP_DEV0_0_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP_MASK                                       0xFFFFFFFFL
+
+
+// addressBlock: nbif0_nbif0_rcc_ep_dev0_BIFDEC1
+//RCC_EP_DEV0_0_EP_PCIE_SCRATCH
+#define RCC_EP_DEV0_0_EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT                                                    0x0
+#define RCC_EP_DEV0_0_EP_PCIE_SCRATCH__PCIE_SCRATCH_MASK                                                      0xFFFFFFFFL
+//RCC_EP_DEV0_0_EP_PCIE_CNTL
+#define RCC_EP_DEV0_0_EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT                                                  0x7
+#define RCC_EP_DEV0_0_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT                                            0x8
+#define RCC_EP_DEV0_0_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT                                               0x1e
+#define RCC_EP_DEV0_0_EP_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK                                                    0x00000080L
+#define RCC_EP_DEV0_0_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK                                              0x00000100L
+#define RCC_EP_DEV0_0_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK                                                 0x40000000L
+//RCC_EP_DEV0_0_EP_PCIE_INT_CNTL
+#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT                                                0x0
+#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT                                           0x1
+#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT                                               0x2
+#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT                                            0x3
+#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT                                                0x4
+#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT                                         0x6
+#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK                                                  0x00000001L
+#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK                                             0x00000002L
+#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK                                                 0x00000004L
+#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK                                              0x00000008L
+#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK                                                  0x00000010L
+#define RCC_EP_DEV0_0_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK                                           0x00000040L
+//RCC_EP_DEV0_0_EP_PCIE_INT_STATUS
+#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT                                          0x0
+#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT                                     0x1
+#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT                                         0x2
+#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT                                      0x3
+#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT                                          0x4
+#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT                                   0x6
+#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0__SHIFT                                0x7
+#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK                                            0x00000001L
+#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK                                       0x00000002L
+#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK                                           0x00000004L
+#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK                                        0x00000008L
+#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK                                            0x00000010L
+#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK                                     0x00000040L
+#define RCC_EP_DEV0_0_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0_MASK                                  0x00000080L
+//RCC_EP_DEV0_0_EP_PCIE_RX_CNTL2
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT                                   0x0
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK                                     0x00000001L
+//RCC_EP_DEV0_0_EP_PCIE_BUS_CNTL
+#define RCC_EP_DEV0_0_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT                                              0x7
+#define RCC_EP_DEV0_0_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK                                                0x00000080L
+//RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL
+#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT                                       0x0
+#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT                                  0x1
+#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT                                  0x2
+#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT                                  0x3
+#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT                                  0x4
+#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN6_HIDDEN_REG__SHIFT                                  0x5
+#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK                                         0x00000001L
+#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK                                    0x00000002L
+#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK                                    0x00000004L
+#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK                                    0x00000008L
+#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK                                    0x00000010L
+#define RCC_EP_DEV0_0_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN6_HIDDEN_REG_MASK                                    0x00000020L
+//RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT                                      0x0
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT                                       0x3
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT                                      0x6
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT                                     0x7
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT                                      0xa
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT                                     0xd
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT                               0xe
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT                                 0xf
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT                                            0x10
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN__SHIFT                                   0x11
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK                                        0x00000007L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK                                         0x00000038L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK                                        0x00000040L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK                                       0x00000380L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK                                        0x00001C00L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK                                       0x00002000L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK                                 0x00004000L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK                                   0x00008000L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK                                              0x00010000L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN_MASK                                     0x00020000L
+//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0
+#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1
+#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2
+#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3
+#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4
+#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5
+#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6
+#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7
+#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_0_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_0_EP_PCIE_STRAP_MISC
+#define RCC_EP_DEV0_0_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT                                           0x1d
+#define RCC_EP_DEV0_0_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK                                             0x20000000L
+//RCC_EP_DEV0_0_EP_PCIE_STRAP_MISC2
+#define RCC_EP_DEV0_0_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT                                         0x4
+#define RCC_EP_DEV0_0_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED_MASK                                           0x00000010L
+//RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP
+#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT                                               0x8
+#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT                                              0xc
+#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT                                              0x10
+#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT                                              0x18
+#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK                                                 0x00000300L
+#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK                                                0x00003000L
+#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK                                                0x00FF0000L
+#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK                                                0xFF000000L
+//RCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR
+#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT                       0x0
+#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK                         0xFFL
+//RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL
+#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT                                             0x0
+#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT                                         0x8
+#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK                                               0x001FL
+#define RCC_EP_DEV0_0_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK                                           0x0100L
+//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_0_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_0_EP_PCIE_PME_CONTROL
+#define RCC_EP_DEV0_0_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT                                           0x0
+#define RCC_EP_DEV0_0_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER_MASK                                             0x1FL
+//RCC_EP_DEV0_0_EP_PCIEP_RESERVED
+#define RCC_EP_DEV0_0_EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT                                                0x0
+#define RCC_EP_DEV0_0_EP_PCIEP_RESERVED__PCIEP_RESERVED_MASK                                                  0xFFFFFFFFL
+//RCC_EP_DEV0_0_EP_PCIE_TX_CNTL
+#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT                                                 0xa
+#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT                                                  0xc
+#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT                                                   0x18
+#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT                                                   0x19
+#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT                                                   0x1a
+#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK                                                   0x00000C00L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK                                                    0x00003000L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK                                                     0x01000000L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK                                                     0x02000000L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK                                                     0x04000000L
+//RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID
+#define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT                                0x0
+#define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT                                  0x3
+#define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT                                     0x8
+#define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK                                  0x00000007L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK                                    0x000000F8L
+#define RCC_EP_DEV0_0_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK                                       0x0000FF00L
+//RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT                                              0x0
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT                                            0x8
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT                                       0x11
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT                               0x12
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT                                   0x18
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT                                   0x19
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT                                   0x1a
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED__SHIFT                                   0x1b
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED__SHIFT                                   0x1c
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED__SHIFT                                   0x1d
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED__SHIFT                                   0x1e
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED__SHIFT                                   0x1f
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK                                                0x00000001L
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK                                              0x00000700L
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK                                         0x00020000L
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK                                 0x00040000L
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK                                     0x01000000L
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK                                     0x02000000L
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK                                     0x04000000L
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED_MASK                                     0x08000000L
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED_MASK                                     0x10000000L
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED_MASK                                     0x20000000L
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED_MASK                                     0x40000000L
+#define RCC_EP_DEV0_0_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED_MASK                                     0x80000000L
+//RCC_EP_DEV0_0_EP_PCIE_RX_CNTL
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT                                       0x8
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT                                                0x9
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT                                         0x14
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT                                       0x15
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT                                         0x16
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT                                      0x18
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT                                          0x19
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT                                                      0x1a
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK                                         0x00000100L
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK                                                  0x00000200L
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK                                           0x00100000L
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK                                         0x00200000L
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK                                           0x00400000L
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK                                        0x01000000L
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK                                            0x02000000L
+#define RCC_EP_DEV0_0_EP_PCIE_RX_CNTL__RX_TPH_DIS_MASK                                                        0x04000000L
+//RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL
+#define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT                                          0x0
+#define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT                                          0x1
+#define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT                                          0x2
+#define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP__SHIFT                                          0x3
+#define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN6_EN_STRAP__SHIFT                                          0x4
+#define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK                                            0x00000001L
+#define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK                                            0x00000002L
+#define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK                                            0x00000004L
+#define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP_MASK                                            0x00000008L
+#define RCC_EP_DEV0_0_EP_PCIE_LC_SPEED_CNTL__LC_GEN6_EN_STRAP_MASK                                            0x00000010L
+//RCC_EP_DEV0_0_EP_PCIE_DEVICE_CNTL3
+#define RCC_EP_DEV0_0_EP_PCIE_DEVICE_CNTL3__SHADOW_F0_DEVICE_CNTL3_14BIT_TAG_REQUESTER_ENABLE__SHIFT          0x2
+#define RCC_EP_DEV0_0_EP_PCIE_DEVICE_CNTL3__SHADOW_F0_DEVICE_CNTL3_14BIT_TAG_REQUESTER_ENABLE_MASK            0x00000004L
+
+
+// addressBlock: nbif0_nbif0_bif_bx_pf_SYSPFVFDEC
+//BIF_BX_PF0_MM_INDEX
+#define BIF_BX_PF0_MM_INDEX__MM_OFFSET__SHIFT                                                                 0x0
+#define BIF_BX_PF0_MM_INDEX__MM_APER__SHIFT                                                                   0x1f
+#define BIF_BX_PF0_MM_INDEX__MM_OFFSET_MASK                                                                   0x7FFFFFFFL
+#define BIF_BX_PF0_MM_INDEX__MM_APER_MASK                                                                     0x80000000L
+//BIF_BX_PF0_MM_DATA
+#define BIF_BX_PF0_MM_DATA__MM_DATA__SHIFT                                                                    0x0
+#define BIF_BX_PF0_MM_DATA__MM_DATA_MASK                                                                      0xFFFFFFFFL
+//BIF_BX_PF0_MM_INDEX_HI
+#define BIF_BX_PF0_MM_INDEX_HI__MM_OFFSET_HI__SHIFT                                                           0x0
+#define BIF_BX_PF0_MM_INDEX_HI__MM_OFFSET_HI_MASK                                                             0xFFFFFFFFL
+//BIF_BX_PF0_RSMU_INDEX
+#define BIF_BX_PF0_RSMU_INDEX__RSMU_INDEX__SHIFT                                                              0x0
+#define BIF_BX_PF0_RSMU_INDEX__RSMU_INDEX_MASK                                                                0xFFFFFFFFL
+//BIF_BX_PF0_RSMU_DATA
+#define BIF_BX_PF0_RSMU_DATA__RSMU_DATA__SHIFT                                                                0x0
+#define BIF_BX_PF0_RSMU_DATA__RSMU_DATA_MASK                                                                  0xFFFFFFFFL
+//BIF_BX_PF0_RSMU_INDEX_HI
+#define BIF_BX_PF0_RSMU_INDEX_HI__RSMU_INDEX_HI__SHIFT                                                        0x0
+#define BIF_BX_PF0_RSMU_INDEX_HI__RSMU_INDEX_HI_MASK                                                          0x0000FFFFL
+
+
+// addressBlock: nbif0_nbif0_bif_bx_BIFDEC1
+//BIF_BX0_CC_BIF_BX_STRAP0
+#define BIF_BX0_CC_BIF_BX_STRAP0__STRAP_RESERVED__SHIFT                                                       0x19
+#define BIF_BX0_CC_BIF_BX_STRAP0__STRAP_RESERVED_MASK                                                         0xFE000000L
+//BIF_BX0_CC_BIF_BX_PINSTRAP0
+//BIF_BX0_BIF_MM_INDACCESS_CNTL
+#define BIF_BX0_BIF_MM_INDACCESS_CNTL__WRITE_DIS__SHIFT                                                       0x0
+#define BIF_BX0_BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT                                                0x1
+#define BIF_BX0_BIF_MM_INDACCESS_CNTL__WRITE_DIS_MASK                                                         0x00000001L
+#define BIF_BX0_BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK                                                  0x00000002L
+//BIF_BX0_BUS_CNTL
+#define BIF_BX0_BUS_CNTL__VGA_REG_COHERENCY_DIS__SHIFT                                                        0x6
+#define BIF_BX0_BUS_CNTL__VGA_MEM_COHERENCY_DIS__SHIFT                                                        0x7
+#define BIF_BX0_BUS_CNTL__SET_AZ_TC__SHIFT                                                                    0xa
+#define BIF_BX0_BUS_CNTL__SET_MC_TC__SHIFT                                                                    0xd
+#define BIF_BX0_BUS_CNTL__ZERO_BE_WR_EN__SHIFT                                                                0x10
+#define BIF_BX0_BUS_CNTL__ZERO_BE_RD_EN__SHIFT                                                                0x11
+#define BIF_BX0_BUS_CNTL__RD_STALL_IO_WR__SHIFT                                                               0x12
+#define BIF_BX0_BUS_CNTL__HDP_FB_FLUSH_STALL_DOORBELL_DIS__SHIFT                                              0x18
+#define BIF_BX0_BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS__SHIFT                                          0x19
+#define BIF_BX0_BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS__SHIFT                                         0x1a
+#define BIF_BX0_BUS_CNTL__MMDAT_RD_HDP_TRIGGER_HDP_FB_FLUSH_DIS__SHIFT                                        0x1b
+#define BIF_BX0_BUS_CNTL__HDP_FB_FLUSH_STALL_MMDAT_RD_HDP_DIS__SHIFT                                          0x1c
+#define BIF_BX0_BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN__SHIFT                                                     0x1d
+#define BIF_BX0_BUS_CNTL__VGAFB_ZERO_BE_WR_EN__SHIFT                                                          0x1e
+#define BIF_BX0_BUS_CNTL__VGAFB_ZERO_BE_RD_EN__SHIFT                                                          0x1f
+#define BIF_BX0_BUS_CNTL__VGA_REG_COHERENCY_DIS_MASK                                                          0x00000040L
+#define BIF_BX0_BUS_CNTL__VGA_MEM_COHERENCY_DIS_MASK                                                          0x00000080L
+#define BIF_BX0_BUS_CNTL__SET_AZ_TC_MASK                                                                      0x00001C00L
+#define BIF_BX0_BUS_CNTL__SET_MC_TC_MASK                                                                      0x0000E000L
+#define BIF_BX0_BUS_CNTL__ZERO_BE_WR_EN_MASK                                                                  0x00010000L
+#define BIF_BX0_BUS_CNTL__ZERO_BE_RD_EN_MASK                                                                  0x00020000L
+#define BIF_BX0_BUS_CNTL__RD_STALL_IO_WR_MASK                                                                 0x00040000L
+#define BIF_BX0_BUS_CNTL__HDP_FB_FLUSH_STALL_DOORBELL_DIS_MASK                                                0x01000000L
+#define BIF_BX0_BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS_MASK                                            0x02000000L
+#define BIF_BX0_BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS_MASK                                           0x04000000L
+#define BIF_BX0_BUS_CNTL__MMDAT_RD_HDP_TRIGGER_HDP_FB_FLUSH_DIS_MASK                                          0x08000000L
+#define BIF_BX0_BUS_CNTL__HDP_FB_FLUSH_STALL_MMDAT_RD_HDP_DIS_MASK                                            0x10000000L
+#define BIF_BX0_BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN_MASK                                                       0x20000000L
+#define BIF_BX0_BUS_CNTL__VGAFB_ZERO_BE_WR_EN_MASK                                                            0x40000000L
+#define BIF_BX0_BUS_CNTL__VGAFB_ZERO_BE_RD_EN_MASK                                                            0x80000000L
+//BIF_BX0_BIF_SCRATCH0
+#define BIF_BX0_BIF_SCRATCH0__BIF_SCRATCH0__SHIFT                                                             0x0
+#define BIF_BX0_BIF_SCRATCH0__BIF_SCRATCH0_MASK                                                               0xFFFFFFFFL
+//BIF_BX0_BIF_SCRATCH1
+#define BIF_BX0_BIF_SCRATCH1__BIF_SCRATCH1__SHIFT                                                             0x0
+#define BIF_BX0_BIF_SCRATCH1__BIF_SCRATCH1_MASK                                                               0xFFFFFFFFL
+//BIF_BX0_BX_RESET_EN
+#define BIF_BX0_BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN__SHIFT                                                  0x10
+#define BIF_BX0_BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN_MASK                                                    0x00010000L
+//BIF_BX0_MM_CFGREGS_CNTL
+#define BIF_BX0_MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL__SHIFT                                                       0x0
+#define BIF_BX0_MM_CFGREGS_CNTL__MM_CFG_DEV_SEL__SHIFT                                                        0x6
+#define BIF_BX0_MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN__SHIFT                                                       0x1f
+#define BIF_BX0_MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL_MASK                                                         0x00000007L
+#define BIF_BX0_MM_CFGREGS_CNTL__MM_CFG_DEV_SEL_MASK                                                          0x000000C0L
+#define BIF_BX0_MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN_MASK                                                         0x80000000L
+//BIF_BX0_BX_RESET_CNTL
+#define BIF_BX0_BX_RESET_CNTL__LINK_TRAIN_EN__SHIFT                                                           0x0
+#define BIF_BX0_BX_RESET_CNTL__LINK_TRAIN_EN_MASK                                                             0x00000001L
+//BIF_BX0_INTERRUPT_CNTL
+#define BIF_BX0_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE__SHIFT                                                   0x0
+#define BIF_BX0_INTERRUPT_CNTL__IH_DUMMY_RD_EN__SHIFT                                                         0x1
+#define BIF_BX0_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN__SHIFT                                                     0x3
+#define BIF_BX0_INTERRUPT_CNTL__IH_INTR_DLY_CNTR__SHIFT                                                       0x4
+#define BIF_BX0_INTERRUPT_CNTL__GEN_IH_INT_EN__SHIFT                                                          0x8
+#define BIF_BX0_INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN__SHIFT                                                 0xf
+#define BIF_BX0_INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN__SHIFT                                               0x10
+#define BIF_BX0_INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS__SHIFT                                   0x11
+#define BIF_BX0_INTERRUPT_CNTL__BIF_RB_REQ_RELAX_ORDER_EN__SHIFT                                              0x12
+#define BIF_BX0_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK                                                     0x00000001L
+#define BIF_BX0_INTERRUPT_CNTL__IH_DUMMY_RD_EN_MASK                                                           0x00000002L
+#define BIF_BX0_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK                                                       0x00000008L
+#define BIF_BX0_INTERRUPT_CNTL__IH_INTR_DLY_CNTR_MASK                                                         0x000000F0L
+#define BIF_BX0_INTERRUPT_CNTL__GEN_IH_INT_EN_MASK                                                            0x00000100L
+#define BIF_BX0_INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN_MASK                                                   0x00008000L
+#define BIF_BX0_INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN_MASK                                                 0x00010000L
+#define BIF_BX0_INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS_MASK                                     0x00020000L
+#define BIF_BX0_INTERRUPT_CNTL__BIF_RB_REQ_RELAX_ORDER_EN_MASK                                                0x00040000L
+//BIF_BX0_INTERRUPT_CNTL2
+#define BIF_BX0_INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR__SHIFT                                                      0x0
+#define BIF_BX0_INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR_MASK                                                        0xFFFFFFFFL
+//BIF_BX0_CLKREQB_PAD_CNTL
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_A__SHIFT                                                        0x0
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL__SHIFT                                                      0x1
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE__SHIFT                                                     0x2
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE__SHIFT                                                    0x3
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0__SHIFT                                                      0x5
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1__SHIFT                                                      0x6
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2__SHIFT                                                      0x7
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3__SHIFT                                                      0x8
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN__SHIFT                                                    0x9
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE__SHIFT                                                     0xa
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN__SHIFT                                                   0xb
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN__SHIFT                                                  0xc
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_Y__SHIFT                                                        0xd
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_A_MASK                                                          0x00000001L
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL_MASK                                                        0x00000002L
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE_MASK                                                       0x00000004L
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE_MASK                                                      0x00000018L
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0_MASK                                                        0x00000020L
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1_MASK                                                        0x00000040L
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2_MASK                                                        0x00000080L
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3_MASK                                                        0x00000100L
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN_MASK                                                      0x00000200L
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE_MASK                                                       0x00000400L
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN_MASK                                                     0x00000800L
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN_MASK                                                    0x00001000L
+#define BIF_BX0_CLKREQB_PAD_CNTL__CLKREQB_PAD_Y_MASK                                                          0x00002000L
+//BIF_BX0_BIF_FEATURES_CONTROL_MISC
+#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS__SHIFT                                          0x0
+#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS__SHIFT                                          0x1
+#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS__SHIFT                                          0x2
+#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS__SHIFT                                          0x3
+#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_RB_MSI_VEC_NOT_ENABLED_MODE__SHIFT                             0xb
+#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN__SHIFT                                      0xc
+#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS__SHIFT                                          0xd
+#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__ATOMIC_ONLY_WRITE_DIS__SHIFT                                       0xe
+#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN__SHIFT                                           0xf
+#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__HDP_NP_OSTD_LIMIT__SHIFT                                           0x10
+#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR__SHIFT                   0x19
+#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS_MASK                                            0x00000001L
+#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS_MASK                                            0x00000002L
+#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS_MASK                                            0x00000004L
+#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS_MASK                                            0x00000008L
+#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_RB_MSI_VEC_NOT_ENABLED_MODE_MASK                               0x00000800L
+#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN_MASK                                        0x00001000L
+#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS_MASK                                            0x00002000L
+#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__ATOMIC_ONLY_WRITE_DIS_MASK                                         0x00004000L
+#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN_MASK                                             0x00008000L
+#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__HDP_NP_OSTD_LIMIT_MASK                                             0x01FF0000L
+#define BIF_BX0_BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR_MASK                     0x02000000L
+//BIF_BX0_HDP_ATOMIC_CONTROL_MISC
+#define BIF_BX0_HDP_ATOMIC_CONTROL_MISC__HDP_NP_ATOMIC_OSTD_LIMIT__SHIFT                                      0x0
+#define BIF_BX0_HDP_ATOMIC_CONTROL_MISC__HDP_NP_ATOMIC_OSTD_LIMIT_MASK                                        0x000000FFL
+//BIF_BX0_BIF_DOORBELL_CNTL
+#define BIF_BX0_BIF_DOORBELL_CNTL__SELF_RING_DIS__SHIFT                                                       0x0
+#define BIF_BX0_BIF_DOORBELL_CNTL__TRANS_CHECK_DIS__SHIFT                                                     0x1
+#define BIF_BX0_BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN__SHIFT                                                    0x2
+#define BIF_BX0_BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS__SHIFT                                         0x3
+#define BIF_BX0_BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN__SHIFT                                                 0x4
+#define BIF_BX0_BIF_DOORBELL_CNTL__SELF_RING_DIS_LOCAL__SHIFT                                                 0x5
+#define BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS__SHIFT                                                  0x18
+#define BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0__SHIFT                                               0x19
+#define BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1__SHIFT                                               0x1a
+#define BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2__SHIFT                                               0x1b
+#define BIF_BX0_BIF_DOORBELL_CNTL__SELF_RING_DIS_MASK                                                         0x00000001L
+#define BIF_BX0_BIF_DOORBELL_CNTL__TRANS_CHECK_DIS_MASK                                                       0x00000002L
+#define BIF_BX0_BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN_MASK                                                      0x00000004L
+#define BIF_BX0_BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS_MASK                                           0x00000008L
+#define BIF_BX0_BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN_MASK                                                   0x00000010L
+#define BIF_BX0_BIF_DOORBELL_CNTL__SELF_RING_DIS_LOCAL_MASK                                                   0x00000020L
+#define BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS_MASK                                                    0x01000000L
+#define BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0_MASK                                                 0x02000000L
+#define BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1_MASK                                                 0x04000000L
+#define BIF_BX0_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2_MASK                                                 0x08000000L
+//BIF_BX0_BIF_DOORBELL_INT_CNTL
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS__SHIFT                                       0x0
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_STATUS__SHIFT                                      0x1
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS__SHIFT                            0x2
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR__SHIFT                                        0x10
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_CLEAR__SHIFT                                       0x11
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR__SHIFT                             0x12
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_ERR_EVENT_INTERRUPT_ENABLE__SHIFT                            0x17
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_DISABLE__SHIFT                                      0x18
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_DISABLE__SHIFT                                     0x19
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_DISABLE__SHIFT                           0x1a
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_DB_INTR_STATUS_WHEN_RB_ENABLE__SHIFT                               0x1c
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_IOH_RAS_INTR_STATUS_WHEN_RB_ENABLE__SHIFT                          0x1d
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_ATH_RAS_INTR_STATUS_WHEN_RB_ENABLE__SHIFT                          0x1e
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__TIMEOUT_ERR_EVENT_INTERRUPT_ENABLE__SHIFT                              0x1f
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS_MASK                                         0x00000001L
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_STATUS_MASK                                        0x00000002L
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS_MASK                              0x00000004L
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR_MASK                                          0x00010000L
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_CLEAR_MASK                                         0x00020000L
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR_MASK                               0x00040000L
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_ERR_EVENT_INTERRUPT_ENABLE_MASK                              0x00800000L
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_DISABLE_MASK                                        0x01000000L
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_DISABLE_MASK                                       0x02000000L
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_DISABLE_MASK                             0x04000000L
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_DB_INTR_STATUS_WHEN_RB_ENABLE_MASK                                 0x10000000L
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_IOH_RAS_INTR_STATUS_WHEN_RB_ENABLE_MASK                            0x20000000L
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__SET_ATH_RAS_INTR_STATUS_WHEN_RB_ENABLE_MASK                            0x40000000L
+#define BIF_BX0_BIF_DOORBELL_INT_CNTL__TIMEOUT_ERR_EVENT_INTERRUPT_ENABLE_MASK                                0x80000000L
+//BIF_BX0_BIF_FB_EN
+#define BIF_BX0_BIF_FB_EN__FB_READ_EN__SHIFT                                                                  0x0
+#define BIF_BX0_BIF_FB_EN__FB_WRITE_EN__SHIFT                                                                 0x1
+#define BIF_BX0_BIF_FB_EN__FB_READ_EN_MASK                                                                    0x00000001L
+#define BIF_BX0_BIF_FB_EN__FB_WRITE_EN_MASK                                                                   0x00000002L
+//BIF_BX0_BIF_INTR_CNTL
+#define BIF_BX0_BIF_INTR_CNTL__RAS_INTR_VEC_SEL__SHIFT                                                        0x0
+#define BIF_BX0_BIF_INTR_CNTL__RAS_INTR_VEC_SEL_MASK                                                          0x00000001L
+//BIF_BX0_BIF_MST_TRANS_PENDING_VF
+#define BIF_BX0_BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING__SHIFT                                        0x0
+#define BIF_BX0_BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING_MASK                                          0x7FFFFFFFL
+//BIF_BX0_BIF_SLV_TRANS_PENDING_VF
+#define BIF_BX0_BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING__SHIFT                                        0x0
+#define BIF_BX0_BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING_MASK                                          0x7FFFFFFFL
+//BIF_BX0_BACO_CNTL
+#define BIF_BX0_BACO_CNTL__BACO_EN__SHIFT                                                                     0x0
+#define BIF_BX0_BACO_CNTL__BACO_DUMMY_EN__SHIFT                                                               0x2
+#define BIF_BX0_BACO_CNTL__BACO_POWER_OFF__SHIFT                                                              0x3
+#define BIF_BX0_BACO_CNTL__BACO_DSTATE_BYPASS__SHIFT                                                          0x5
+#define BIF_BX0_BACO_CNTL__BACO_RST_INTR_MASK__SHIFT                                                          0x6
+#define BIF_BX0_BACO_CNTL__BACO_MODE__SHIFT                                                                   0x8
+#define BIF_BX0_BACO_CNTL__RCU_BIF_CONFIG_DONE__SHIFT                                                         0x9
+#define BIF_BX0_BACO_CNTL__PWRGOOD_VDDSOC__SHIFT                                                              0x10
+#define BIF_BX0_BACO_CNTL__BACO_AUTO_EXIT__SHIFT                                                              0x1f
+#define BIF_BX0_BACO_CNTL__BACO_EN_MASK                                                                       0x00000001L
+#define BIF_BX0_BACO_CNTL__BACO_DUMMY_EN_MASK                                                                 0x00000004L
+#define BIF_BX0_BACO_CNTL__BACO_POWER_OFF_MASK                                                                0x00000008L
+#define BIF_BX0_BACO_CNTL__BACO_DSTATE_BYPASS_MASK                                                            0x00000020L
+#define BIF_BX0_BACO_CNTL__BACO_RST_INTR_MASK_MASK                                                            0x00000040L
+#define BIF_BX0_BACO_CNTL__BACO_MODE_MASK                                                                     0x00000100L
+#define BIF_BX0_BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK                                                           0x00000200L
+#define BIF_BX0_BACO_CNTL__PWRGOOD_VDDSOC_MASK                                                                0x00010000L
+#define BIF_BX0_BACO_CNTL__BACO_AUTO_EXIT_MASK                                                                0x80000000L
+//BIF_BX0_BIF_BACO_EXIT_TIME0
+#define BIF_BX0_BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER__SHIFT                                          0x0
+#define BIF_BX0_BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER_MASK                                            0x000FFFFFL
+//BIF_BX0_BIF_BACO_EXIT_TIMER1
+#define BIF_BX0_BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER__SHIFT                                         0x0
+#define BIF_BX0_BIF_BACO_EXIT_TIMER1__BACO_HW_AUTO_FLUSH_EN__SHIFT                                            0x18
+#define BIF_BX0_BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS__SHIFT                                                 0x1a
+#define BIF_BX0_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH__SHIFT                                           0x1b
+#define BIF_BX0_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW__SHIFT                                            0x1c
+#define BIF_BX0_BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL__SHIFT                                                    0x1d
+#define BIF_BX0_BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS__SHIFT                                     0x1f
+#define BIF_BX0_BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER_MASK                                           0x000FFFFFL
+#define BIF_BX0_BIF_BACO_EXIT_TIMER1__BACO_HW_AUTO_FLUSH_EN_MASK                                              0x01000000L
+#define BIF_BX0_BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS_MASK                                                   0x04000000L
+#define BIF_BX0_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH_MASK                                             0x08000000L
+#define BIF_BX0_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW_MASK                                              0x10000000L
+#define BIF_BX0_BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL_MASK                                                      0x60000000L
+#define BIF_BX0_BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS_MASK                                       0x80000000L
+//BIF_BX0_BIF_BACO_EXIT_TIMER2
+#define BIF_BX0_BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER__SHIFT                                         0x0
+#define BIF_BX0_BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER_MASK                                           0x000FFFFFL
+//BIF_BX0_BIF_BACO_EXIT_TIMER3
+#define BIF_BX0_BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER__SHIFT                                     0x0
+#define BIF_BX0_BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER_MASK                                       0x000FFFFFL
+//BIF_BX0_BIF_BACO_EXIT_TIMER4
+#define BIF_BX0_BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER__SHIFT                                      0x0
+#define BIF_BX0_BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER_MASK                                        0x000FFFFFL
+//BIF_BX0_MEM_TYPE_CNTL
+#define BIF_BX0_MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3__SHIFT                                                        0x0
+#define BIF_BX0_MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3_MASK                                                          0x00000001L
+//BIF_BX0_NBIF_GFX_ADDR_LUT_CNTL
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_CNTL__LUT_ENABLE__SHIFT                                                     0x0
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_CNTL__MSI_ADDR_MODE__SHIFT                                                  0x1
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_CNTL__LUT_BC_MODE__SHIFT                                                    0x8
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_CNTL__LUT_ENABLE_MASK                                                       0x00000001L
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_CNTL__MSI_ADDR_MODE_MASK                                                    0x00000002L
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_CNTL__LUT_BC_MODE_MASK                                                      0x00000100L
+//BIF_BX0_NBIF_GFX_ADDR_LUT_0
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_0__ADDR__SHIFT                                                              0x0
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_0__ADDR_MASK                                                                0x00FFFFFFL
+//BIF_BX0_NBIF_GFX_ADDR_LUT_1
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_1__ADDR__SHIFT                                                              0x0
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_1__ADDR_MASK                                                                0x00FFFFFFL
+//BIF_BX0_NBIF_GFX_ADDR_LUT_2
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_2__ADDR__SHIFT                                                              0x0
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_2__ADDR_MASK                                                                0x00FFFFFFL
+//BIF_BX0_NBIF_GFX_ADDR_LUT_3
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_3__ADDR__SHIFT                                                              0x0
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_3__ADDR_MASK                                                                0x00FFFFFFL
+//BIF_BX0_NBIF_GFX_ADDR_LUT_4
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_4__ADDR__SHIFT                                                              0x0
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_4__ADDR_MASK                                                                0x00FFFFFFL
+//BIF_BX0_NBIF_GFX_ADDR_LUT_5
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_5__ADDR__SHIFT                                                              0x0
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_5__ADDR_MASK                                                                0x00FFFFFFL
+//BIF_BX0_NBIF_GFX_ADDR_LUT_6
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_6__ADDR__SHIFT                                                              0x0
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_6__ADDR_MASK                                                                0x00FFFFFFL
+//BIF_BX0_NBIF_GFX_ADDR_LUT_7
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_7__ADDR__SHIFT                                                              0x0
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_7__ADDR_MASK                                                                0x00FFFFFFL
+//BIF_BX0_NBIF_GFX_ADDR_LUT_8
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_8__ADDR__SHIFT                                                              0x0
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_8__ADDR_MASK                                                                0x00FFFFFFL
+//BIF_BX0_NBIF_GFX_ADDR_LUT_9
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_9__ADDR__SHIFT                                                              0x0
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_9__ADDR_MASK                                                                0x00FFFFFFL
+//BIF_BX0_NBIF_GFX_ADDR_LUT_10
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_10__ADDR__SHIFT                                                             0x0
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_10__ADDR_MASK                                                               0x00FFFFFFL
+//BIF_BX0_NBIF_GFX_ADDR_LUT_11
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_11__ADDR__SHIFT                                                             0x0
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_11__ADDR_MASK                                                               0x00FFFFFFL
+//BIF_BX0_NBIF_GFX_ADDR_LUT_12
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_12__ADDR__SHIFT                                                             0x0
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_12__ADDR_MASK                                                               0x00FFFFFFL
+//BIF_BX0_NBIF_GFX_ADDR_LUT_13
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_13__ADDR__SHIFT                                                             0x0
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_13__ADDR_MASK                                                               0x00FFFFFFL
+//BIF_BX0_NBIF_GFX_ADDR_LUT_14
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_14__ADDR__SHIFT                                                             0x0
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_14__ADDR_MASK                                                               0x00FFFFFFL
+//BIF_BX0_NBIF_GFX_ADDR_LUT_15
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_15__ADDR__SHIFT                                                             0x0
+#define BIF_BX0_NBIF_GFX_ADDR_LUT_15__ADDR_MASK                                                               0x00FFFFFFL
+//BIF_BX0_VF_REGWR_EN
+#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF0__SHIFT                                                           0x0
+#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF1__SHIFT                                                           0x1
+#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF2__SHIFT                                                           0x2
+#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF3__SHIFT                                                           0x3
+#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF4__SHIFT                                                           0x4
+#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF5__SHIFT                                                           0x5
+#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF6__SHIFT                                                           0x6
+#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF7__SHIFT                                                           0x7
+#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF8__SHIFT                                                           0x8
+#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF9__SHIFT                                                           0x9
+#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF10__SHIFT                                                          0xa
+#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF11__SHIFT                                                          0xb
+#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF12__SHIFT                                                          0xc
+#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF13__SHIFT                                                          0xd
+#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF14__SHIFT                                                          0xe
+#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF15__SHIFT                                                          0xf
+#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF16__SHIFT                                                          0x10
+#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF17__SHIFT                                                          0x11
+#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF18__SHIFT                                                          0x12
+#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF19__SHIFT                                                          0x13
+#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF20__SHIFT                                                          0x14
+#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF21__SHIFT                                                          0x15
+#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF22__SHIFT                                                          0x16
+#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF23__SHIFT                                                          0x17
+#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF24__SHIFT                                                          0x18
+#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF25__SHIFT                                                          0x19
+#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF26__SHIFT                                                          0x1a
+#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF27__SHIFT                                                          0x1b
+#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF28__SHIFT                                                          0x1c
+#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF29__SHIFT                                                          0x1d
+#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF30__SHIFT                                                          0x1e
+#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF0_MASK                                                             0x00000001L
+#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF1_MASK                                                             0x00000002L
+#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF2_MASK                                                             0x00000004L
+#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF3_MASK                                                             0x00000008L
+#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF4_MASK                                                             0x00000010L
+#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF5_MASK                                                             0x00000020L
+#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF6_MASK                                                             0x00000040L
+#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF7_MASK                                                             0x00000080L
+#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF8_MASK                                                             0x00000100L
+#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF9_MASK                                                             0x00000200L
+#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF10_MASK                                                            0x00000400L
+#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF11_MASK                                                            0x00000800L
+#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF12_MASK                                                            0x00001000L
+#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF13_MASK                                                            0x00002000L
+#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF14_MASK                                                            0x00004000L
+#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF15_MASK                                                            0x00008000L
+#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF16_MASK                                                            0x00010000L
+#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF17_MASK                                                            0x00020000L
+#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF18_MASK                                                            0x00040000L
+#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF19_MASK                                                            0x00080000L
+#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF20_MASK                                                            0x00100000L
+#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF21_MASK                                                            0x00200000L
+#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF22_MASK                                                            0x00400000L
+#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF23_MASK                                                            0x00800000L
+#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF24_MASK                                                            0x01000000L
+#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF25_MASK                                                            0x02000000L
+#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF26_MASK                                                            0x04000000L
+#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF27_MASK                                                            0x08000000L
+#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF28_MASK                                                            0x10000000L
+#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF29_MASK                                                            0x20000000L
+#define BIF_BX0_VF_REGWR_EN__VF_REGWR_EN_VF30_MASK                                                            0x40000000L
+//BIF_BX0_VF_DOORBELL_EN
+#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF0__SHIFT                                                     0x0
+#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF1__SHIFT                                                     0x1
+#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF2__SHIFT                                                     0x2
+#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF3__SHIFT                                                     0x3
+#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF4__SHIFT                                                     0x4
+#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF5__SHIFT                                                     0x5
+#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF6__SHIFT                                                     0x6
+#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF7__SHIFT                                                     0x7
+#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF8__SHIFT                                                     0x8
+#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF9__SHIFT                                                     0x9
+#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF10__SHIFT                                                    0xa
+#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF11__SHIFT                                                    0xb
+#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF12__SHIFT                                                    0xc
+#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF13__SHIFT                                                    0xd
+#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF14__SHIFT                                                    0xe
+#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF15__SHIFT                                                    0xf
+#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF16__SHIFT                                                    0x10
+#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF17__SHIFT                                                    0x11
+#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF18__SHIFT                                                    0x12
+#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF19__SHIFT                                                    0x13
+#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF20__SHIFT                                                    0x14
+#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF21__SHIFT                                                    0x15
+#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF22__SHIFT                                                    0x16
+#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF23__SHIFT                                                    0x17
+#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF24__SHIFT                                                    0x18
+#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF25__SHIFT                                                    0x19
+#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF26__SHIFT                                                    0x1a
+#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF27__SHIFT                                                    0x1b
+#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF28__SHIFT                                                    0x1c
+#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF29__SHIFT                                                    0x1d
+#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF30__SHIFT                                                    0x1e
+#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_RD_LOG_DIS__SHIFT                                                 0x1f
+#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF0_MASK                                                       0x00000001L
+#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF1_MASK                                                       0x00000002L
+#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF2_MASK                                                       0x00000004L
+#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF3_MASK                                                       0x00000008L
+#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF4_MASK                                                       0x00000010L
+#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF5_MASK                                                       0x00000020L
+#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF6_MASK                                                       0x00000040L
+#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF7_MASK                                                       0x00000080L
+#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF8_MASK                                                       0x00000100L
+#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF9_MASK                                                       0x00000200L
+#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF10_MASK                                                      0x00000400L
+#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF11_MASK                                                      0x00000800L
+#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF12_MASK                                                      0x00001000L
+#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF13_MASK                                                      0x00002000L
+#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF14_MASK                                                      0x00004000L
+#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF15_MASK                                                      0x00008000L
+#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF16_MASK                                                      0x00010000L
+#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF17_MASK                                                      0x00020000L
+#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF18_MASK                                                      0x00040000L
+#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF19_MASK                                                      0x00080000L
+#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF20_MASK                                                      0x00100000L
+#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF21_MASK                                                      0x00200000L
+#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF22_MASK                                                      0x00400000L
+#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF23_MASK                                                      0x00800000L
+#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF24_MASK                                                      0x01000000L
+#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF25_MASK                                                      0x02000000L
+#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF26_MASK                                                      0x04000000L
+#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF27_MASK                                                      0x08000000L
+#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF28_MASK                                                      0x10000000L
+#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF29_MASK                                                      0x20000000L
+#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_EN_VF30_MASK                                                      0x40000000L
+#define BIF_BX0_VF_DOORBELL_EN__VF_DOORBELL_RD_LOG_DIS_MASK                                                   0x80000000L
+//BIF_BX0_VF_FB_EN
+#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF0__SHIFT                                                                 0x0
+#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF1__SHIFT                                                                 0x1
+#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF2__SHIFT                                                                 0x2
+#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF3__SHIFT                                                                 0x3
+#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF4__SHIFT                                                                 0x4
+#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF5__SHIFT                                                                 0x5
+#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF6__SHIFT                                                                 0x6
+#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF7__SHIFT                                                                 0x7
+#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF8__SHIFT                                                                 0x8
+#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF9__SHIFT                                                                 0x9
+#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF10__SHIFT                                                                0xa
+#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF11__SHIFT                                                                0xb
+#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF12__SHIFT                                                                0xc
+#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF13__SHIFT                                                                0xd
+#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF14__SHIFT                                                                0xe
+#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF15__SHIFT                                                                0xf
+#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF16__SHIFT                                                                0x10
+#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF17__SHIFT                                                                0x11
+#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF18__SHIFT                                                                0x12
+#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF19__SHIFT                                                                0x13
+#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF20__SHIFT                                                                0x14
+#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF21__SHIFT                                                                0x15
+#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF22__SHIFT                                                                0x16
+#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF23__SHIFT                                                                0x17
+#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF24__SHIFT                                                                0x18
+#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF25__SHIFT                                                                0x19
+#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF26__SHIFT                                                                0x1a
+#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF27__SHIFT                                                                0x1b
+#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF28__SHIFT                                                                0x1c
+#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF29__SHIFT                                                                0x1d
+#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF30__SHIFT                                                                0x1e
+#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF0_MASK                                                                   0x00000001L
+#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF1_MASK                                                                   0x00000002L
+#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF2_MASK                                                                   0x00000004L
+#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF3_MASK                                                                   0x00000008L
+#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF4_MASK                                                                   0x00000010L
+#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF5_MASK                                                                   0x00000020L
+#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF6_MASK                                                                   0x00000040L
+#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF7_MASK                                                                   0x00000080L
+#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF8_MASK                                                                   0x00000100L
+#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF9_MASK                                                                   0x00000200L
+#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF10_MASK                                                                  0x00000400L
+#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF11_MASK                                                                  0x00000800L
+#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF12_MASK                                                                  0x00001000L
+#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF13_MASK                                                                  0x00002000L
+#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF14_MASK                                                                  0x00004000L
+#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF15_MASK                                                                  0x00008000L
+#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF16_MASK                                                                  0x00010000L
+#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF17_MASK                                                                  0x00020000L
+#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF18_MASK                                                                  0x00040000L
+#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF19_MASK                                                                  0x00080000L
+#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF20_MASK                                                                  0x00100000L
+#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF21_MASK                                                                  0x00200000L
+#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF22_MASK                                                                  0x00400000L
+#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF23_MASK                                                                  0x00800000L
+#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF24_MASK                                                                  0x01000000L
+#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF25_MASK                                                                  0x02000000L
+#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF26_MASK                                                                  0x04000000L
+#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF27_MASK                                                                  0x08000000L
+#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF28_MASK                                                                  0x10000000L
+#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF29_MASK                                                                  0x20000000L
+#define BIF_BX0_VF_FB_EN__VF_FB_EN_VF30_MASK                                                                  0x40000000L
+//BIF_BX0_VF_REGWR_STATUS
+#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF0__SHIFT                                                   0x0
+#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF1__SHIFT                                                   0x1
+#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF2__SHIFT                                                   0x2
+#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF3__SHIFT                                                   0x3
+#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF4__SHIFT                                                   0x4
+#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF5__SHIFT                                                   0x5
+#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF6__SHIFT                                                   0x6
+#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF7__SHIFT                                                   0x7
+#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF8__SHIFT                                                   0x8
+#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF9__SHIFT                                                   0x9
+#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF10__SHIFT                                                  0xa
+#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF11__SHIFT                                                  0xb
+#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF12__SHIFT                                                  0xc
+#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF13__SHIFT                                                  0xd
+#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF14__SHIFT                                                  0xe
+#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF15__SHIFT                                                  0xf
+#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF16__SHIFT                                                  0x10
+#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF17__SHIFT                                                  0x11
+#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF18__SHIFT                                                  0x12
+#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF19__SHIFT                                                  0x13
+#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF20__SHIFT                                                  0x14
+#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF21__SHIFT                                                  0x15
+#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF22__SHIFT                                                  0x16
+#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF23__SHIFT                                                  0x17
+#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF24__SHIFT                                                  0x18
+#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF25__SHIFT                                                  0x19
+#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF26__SHIFT                                                  0x1a
+#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF27__SHIFT                                                  0x1b
+#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF28__SHIFT                                                  0x1c
+#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF29__SHIFT                                                  0x1d
+#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF30__SHIFT                                                  0x1e
+#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF0_MASK                                                     0x00000001L
+#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF1_MASK                                                     0x00000002L
+#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF2_MASK                                                     0x00000004L
+#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF3_MASK                                                     0x00000008L
+#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF4_MASK                                                     0x00000010L
+#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF5_MASK                                                     0x00000020L
+#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF6_MASK                                                     0x00000040L
+#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF7_MASK                                                     0x00000080L
+#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF8_MASK                                                     0x00000100L
+#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF9_MASK                                                     0x00000200L
+#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF10_MASK                                                    0x00000400L
+#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF11_MASK                                                    0x00000800L
+#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF12_MASK                                                    0x00001000L
+#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF13_MASK                                                    0x00002000L
+#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF14_MASK                                                    0x00004000L
+#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF15_MASK                                                    0x00008000L
+#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF16_MASK                                                    0x00010000L
+#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF17_MASK                                                    0x00020000L
+#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF18_MASK                                                    0x00040000L
+#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF19_MASK                                                    0x00080000L
+#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF20_MASK                                                    0x00100000L
+#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF21_MASK                                                    0x00200000L
+#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF22_MASK                                                    0x00400000L
+#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF23_MASK                                                    0x00800000L
+#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF24_MASK                                                    0x01000000L
+#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF25_MASK                                                    0x02000000L
+#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF26_MASK                                                    0x04000000L
+#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF27_MASK                                                    0x08000000L
+#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF28_MASK                                                    0x10000000L
+#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF29_MASK                                                    0x20000000L
+#define BIF_BX0_VF_REGWR_STATUS__VF_REGWR_STATUS_VF30_MASK                                                    0x40000000L
+//BIF_BX0_VF_DOORBELL_STATUS
+#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF0__SHIFT                                             0x0
+#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF1__SHIFT                                             0x1
+#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF2__SHIFT                                             0x2
+#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF3__SHIFT                                             0x3
+#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF4__SHIFT                                             0x4
+#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF5__SHIFT                                             0x5
+#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF6__SHIFT                                             0x6
+#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF7__SHIFT                                             0x7
+#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF8__SHIFT                                             0x8
+#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF9__SHIFT                                             0x9
+#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF10__SHIFT                                            0xa
+#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF11__SHIFT                                            0xb
+#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF12__SHIFT                                            0xc
+#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF13__SHIFT                                            0xd
+#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF14__SHIFT                                            0xe
+#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF15__SHIFT                                            0xf
+#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF16__SHIFT                                            0x10
+#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF17__SHIFT                                            0x11
+#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF18__SHIFT                                            0x12
+#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF19__SHIFT                                            0x13
+#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF20__SHIFT                                            0x14
+#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF21__SHIFT                                            0x15
+#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF22__SHIFT                                            0x16
+#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF23__SHIFT                                            0x17
+#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF24__SHIFT                                            0x18
+#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF25__SHIFT                                            0x19
+#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF26__SHIFT                                            0x1a
+#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF27__SHIFT                                            0x1b
+#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF28__SHIFT                                            0x1c
+#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF29__SHIFT                                            0x1d
+#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF30__SHIFT                                            0x1e
+#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF0_MASK                                               0x00000001L
+#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF1_MASK                                               0x00000002L
+#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF2_MASK                                               0x00000004L
+#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF3_MASK                                               0x00000008L
+#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF4_MASK                                               0x00000010L
+#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF5_MASK                                               0x00000020L
+#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF6_MASK                                               0x00000040L
+#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF7_MASK                                               0x00000080L
+#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF8_MASK                                               0x00000100L
+#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF9_MASK                                               0x00000200L
+#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF10_MASK                                              0x00000400L
+#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF11_MASK                                              0x00000800L
+#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF12_MASK                                              0x00001000L
+#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF13_MASK                                              0x00002000L
+#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF14_MASK                                              0x00004000L
+#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF15_MASK                                              0x00008000L
+#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF16_MASK                                              0x00010000L
+#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF17_MASK                                              0x00020000L
+#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF18_MASK                                              0x00040000L
+#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF19_MASK                                              0x00080000L
+#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF20_MASK                                              0x00100000L
+#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF21_MASK                                              0x00200000L
+#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF22_MASK                                              0x00400000L
+#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF23_MASK                                              0x00800000L
+#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF24_MASK                                              0x01000000L
+#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF25_MASK                                              0x02000000L
+#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF26_MASK                                              0x04000000L
+#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF27_MASK                                              0x08000000L
+#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF28_MASK                                              0x10000000L
+#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF29_MASK                                              0x20000000L
+#define BIF_BX0_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF30_MASK                                              0x40000000L
+//BIF_BX0_VF_FB_STATUS
+#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF0__SHIFT                                                         0x0
+#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF1__SHIFT                                                         0x1
+#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF2__SHIFT                                                         0x2
+#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF3__SHIFT                                                         0x3
+#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF4__SHIFT                                                         0x4
+#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF5__SHIFT                                                         0x5
+#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF6__SHIFT                                                         0x6
+#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF7__SHIFT                                                         0x7
+#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF8__SHIFT                                                         0x8
+#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF9__SHIFT                                                         0x9
+#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF10__SHIFT                                                        0xa
+#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF11__SHIFT                                                        0xb
+#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF12__SHIFT                                                        0xc
+#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF13__SHIFT                                                        0xd
+#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF14__SHIFT                                                        0xe
+#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF15__SHIFT                                                        0xf
+#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF16__SHIFT                                                        0x10
+#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF17__SHIFT                                                        0x11
+#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF18__SHIFT                                                        0x12
+#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF19__SHIFT                                                        0x13
+#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF20__SHIFT                                                        0x14
+#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF21__SHIFT                                                        0x15
+#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF22__SHIFT                                                        0x16
+#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF23__SHIFT                                                        0x17
+#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF24__SHIFT                                                        0x18
+#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF25__SHIFT                                                        0x19
+#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF26__SHIFT                                                        0x1a
+#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF27__SHIFT                                                        0x1b
+#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF28__SHIFT                                                        0x1c
+#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF29__SHIFT                                                        0x1d
+#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF30__SHIFT                                                        0x1e
+#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF0_MASK                                                           0x00000001L
+#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF1_MASK                                                           0x00000002L
+#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF2_MASK                                                           0x00000004L
+#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF3_MASK                                                           0x00000008L
+#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF4_MASK                                                           0x00000010L
+#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF5_MASK                                                           0x00000020L
+#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF6_MASK                                                           0x00000040L
+#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF7_MASK                                                           0x00000080L
+#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF8_MASK                                                           0x00000100L
+#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF9_MASK                                                           0x00000200L
+#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF10_MASK                                                          0x00000400L
+#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF11_MASK                                                          0x00000800L
+#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF12_MASK                                                          0x00001000L
+#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF13_MASK                                                          0x00002000L
+#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF14_MASK                                                          0x00004000L
+#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF15_MASK                                                          0x00008000L
+#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF16_MASK                                                          0x00010000L
+#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF17_MASK                                                          0x00020000L
+#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF18_MASK                                                          0x00040000L
+#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF19_MASK                                                          0x00080000L
+#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF20_MASK                                                          0x00100000L
+#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF21_MASK                                                          0x00200000L
+#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF22_MASK                                                          0x00400000L
+#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF23_MASK                                                          0x00800000L
+#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF24_MASK                                                          0x01000000L
+#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF25_MASK                                                          0x02000000L
+#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF26_MASK                                                          0x04000000L
+#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF27_MASK                                                          0x08000000L
+#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF28_MASK                                                          0x10000000L
+#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF29_MASK                                                          0x20000000L
+#define BIF_BX0_VF_FB_STATUS__VF_FB_STATUS_VF30_MASK                                                          0x40000000L
+//BIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL
+#define BIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS__SHIFT                                                      0x2
+#define BIF_BX0_REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS_MASK                                                        0x0007FFFCL
+//BIF_BX0_REMAP_HDP_REG_FLUSH_CNTL
+#define BIF_BX0_REMAP_HDP_REG_FLUSH_CNTL__ADDRESS__SHIFT                                                      0x2
+#define BIF_BX0_REMAP_HDP_REG_FLUSH_CNTL__ADDRESS_MASK                                                        0x0007FFFCL
+//BIF_BX0_BIF_RB_CNTL
+#define BIF_BX0_BIF_RB_CNTL__RB_ENABLE__SHIFT                                                                 0x0
+#define BIF_BX0_BIF_RB_CNTL__RB_SIZE__SHIFT                                                                   0x1
+#define BIF_BX0_BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT                                                     0x8
+#define BIF_BX0_BIF_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT                                                      0x9
+#define BIF_BX0_BIF_RB_CNTL__BIF_RB_TRAN__SHIFT                                                               0x11
+#define BIF_BX0_BIF_RB_CNTL__DIS_PROTECT_WHEN_RB_FULL__SHIFT                                                  0x19
+#define BIF_BX0_BIF_RB_CNTL__RB_INTR_FIX_PRIORITY__SHIFT                                                      0x1a
+#define BIF_BX0_BIF_RB_CNTL__RB_INTR_ARB_MODE__SHIFT                                                          0x1d
+#define BIF_BX0_BIF_RB_CNTL__RB_RST_BY_FLR_DISABLE__SHIFT                                                     0x1e
+#define BIF_BX0_BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT                                                       0x1f
+#define BIF_BX0_BIF_RB_CNTL__RB_ENABLE_MASK                                                                   0x00000001L
+#define BIF_BX0_BIF_RB_CNTL__RB_SIZE_MASK                                                                     0x0000003EL
+#define BIF_BX0_BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK                                                       0x00000100L
+#define BIF_BX0_BIF_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK                                                        0x00003E00L
+#define BIF_BX0_BIF_RB_CNTL__BIF_RB_TRAN_MASK                                                                 0x00020000L
+#define BIF_BX0_BIF_RB_CNTL__DIS_PROTECT_WHEN_RB_FULL_MASK                                                    0x02000000L
+#define BIF_BX0_BIF_RB_CNTL__RB_INTR_FIX_PRIORITY_MASK                                                        0x1C000000L
+#define BIF_BX0_BIF_RB_CNTL__RB_INTR_ARB_MODE_MASK                                                            0x20000000L
+#define BIF_BX0_BIF_RB_CNTL__RB_RST_BY_FLR_DISABLE_MASK                                                       0x40000000L
+#define BIF_BX0_BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK                                                         0x80000000L
+//BIF_BX0_BIF_RB_BASE
+#define BIF_BX0_BIF_RB_BASE__ADDR__SHIFT                                                                      0x0
+#define BIF_BX0_BIF_RB_BASE__ADDR_MASK                                                                        0xFFFFFFFFL
+//BIF_BX0_BIF_RB_RPTR
+#define BIF_BX0_BIF_RB_RPTR__OFFSET__SHIFT                                                                    0x2
+#define BIF_BX0_BIF_RB_RPTR__OFFSET_MASK                                                                      0x0003FFFCL
+//BIF_BX0_BIF_RB_WPTR
+#define BIF_BX0_BIF_RB_WPTR__BIF_RB_OVERFLOW__SHIFT                                                           0x0
+#define BIF_BX0_BIF_RB_WPTR__OFFSET__SHIFT                                                                    0x2
+#define BIF_BX0_BIF_RB_WPTR__BIF_RB_OVERFLOW_MASK                                                             0x00000001L
+#define BIF_BX0_BIF_RB_WPTR__OFFSET_MASK                                                                      0x0003FFFCL
+//BIF_BX0_BIF_RB_WPTR_ADDR_HI
+#define BIF_BX0_BIF_RB_WPTR_ADDR_HI__ADDR__SHIFT                                                              0x0
+#define BIF_BX0_BIF_RB_WPTR_ADDR_HI__ADDR_MASK                                                                0x000000FFL
+//BIF_BX0_BIF_RB_WPTR_ADDR_LO
+#define BIF_BX0_BIF_RB_WPTR_ADDR_LO__ADDR__SHIFT                                                              0x2
+#define BIF_BX0_BIF_RB_WPTR_ADDR_LO__ADDR_MASK                                                                0xFFFFFFFCL
+//BIF_BX0_MAILBOX_INDEX
+#define BIF_BX0_MAILBOX_INDEX__MAILBOX_INDEX__SHIFT                                                           0x0
+#define BIF_BX0_MAILBOX_INDEX__MAILBOX_INDEX_MASK                                                             0x0000001FL
+//BIF_BX0_BACO_AZ_ENHANCE_CTRL
+#define BIF_BX0_BACO_AZ_ENHANCE_CTRL__GCTL_OFFSET__SHIFT                                                      0x2
+#define BIF_BX0_BACO_AZ_ENHANCE_CTRL__AZ_CRST_WRITTEN_ONE__SHIFT                                              0x10
+#define BIF_BX0_BACO_AZ_ENHANCE_CTRL__AZ_CRST_WRITTEN_ZERO__SHIFT                                             0x11
+#define BIF_BX0_BACO_AZ_ENHANCE_CTRL__AZ_MMIO_RDRSPDATA_FORCE_ZERO__SHIFT                                     0x1f
+#define BIF_BX0_BACO_AZ_ENHANCE_CTRL__GCTL_OFFSET_MASK                                                        0x00003FFCL
+#define BIF_BX0_BACO_AZ_ENHANCE_CTRL__AZ_CRST_WRITTEN_ONE_MASK                                                0x00010000L
+#define BIF_BX0_BACO_AZ_ENHANCE_CTRL__AZ_CRST_WRITTEN_ZERO_MASK                                               0x00020000L
+#define BIF_BX0_BACO_AZ_ENHANCE_CTRL__AZ_MMIO_RDRSPDATA_FORCE_ZERO_MASK                                       0x80000000L
+//BIF_BX0_BIF_MP1_INTR_CTRL
+#define BIF_BX0_BIF_MP1_INTR_CTRL__BACO_EXIT_DONE__SHIFT                                                      0x0
+#define BIF_BX0_BIF_MP1_INTR_CTRL__BACO_EXIT_DONE_MASK                                                        0x00000001L
+//BIF_BX0_BIF_PERSTB_PAD_CNTL
+#define BIF_BX0_BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL__SHIFT                                                   0x0
+#define BIF_BX0_BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL_MASK                                                     0x0000FFFFL
+//BIF_BX0_BIF_PX_EN_PAD_CNTL
+#define BIF_BX0_BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL__SHIFT                                                     0x0
+#define BIF_BX0_BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL_MASK                                                       0x00000FFFL
+//BIF_BX0_BIF_REFPADKIN_PAD_CNTL
+#define BIF_BX0_BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL__SHIFT                                             0x0
+#define BIF_BX0_BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL_MASK                                               0x000000FFL
+//BIF_BX0_BIF_CLKREQB_PAD_CNTL
+#define BIF_BX0_BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL__SHIFT                                                 0x0
+#define BIF_BX0_BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_MASK                                                   0x7FFFFFFFL
+//BIF_BX0_BIF_PWRBRK_PAD_CNTL
+#define BIF_BX0_BIF_PWRBRK_PAD_CNTL__PWRBRK_PAD_CNTL__SHIFT                                                   0x0
+#define BIF_BX0_BIF_PWRBRK_PAD_CNTL__PWRBRK_PAD_CNTL_MASK                                                     0x000000FFL
+//BIF_BX0_BIF_GPUIOV_SCH_CFG_SIZE
+#define BIF_BX0_BIF_GPUIOV_SCH_CFG_SIZE__GPUIOV_SCH_CFG_SIZE__SHIFT                                           0x0
+#define BIF_BX0_BIF_GPUIOV_SCH_CFG_SIZE__GPUIOV_SCH_CFG_SIZE_MASK                                             0x0000000FL
+
+
+// addressBlock: nbif0_nbif0_rcc_dev0_BIFDEC1
+//RCC_DEV0_0_RCC_ERR_INT_CNTL
+#define RCC_DEV0_0_RCC_ERR_INT_CNTL__INVALID_REG_ACCESS_IN_SRIOV_INT_EN__SHIFT                                0x0
+#define RCC_DEV0_0_RCC_ERR_INT_CNTL__INVALID_REG_ACCESS_IN_SRIOV_INT_EN_MASK                                  0x00000001L
+//RCC_DEV0_0_RCC_BACO_CNTL_MISC
+#define RCC_DEV0_0_RCC_BACO_CNTL_MISC__BIF_ROM_REQ_DIS__SHIFT                                                 0x0
+#define RCC_DEV0_0_RCC_BACO_CNTL_MISC__BIF_AZ_REQ_DIS__SHIFT                                                  0x1
+#define RCC_DEV0_0_RCC_BACO_CNTL_MISC__BIF_ROM_REQ_DIS_MASK                                                   0x00000001L
+#define RCC_DEV0_0_RCC_BACO_CNTL_MISC__BIF_AZ_REQ_DIS_MASK                                                    0x00000002L
+//RCC_DEV0_0_RCC_RESET_EN
+#define RCC_DEV0_0_RCC_RESET_EN__DB_APER_RESET_EN__SHIFT                                                      0xf
+#define RCC_DEV0_0_RCC_RESET_EN__DB_APER_RESET_EN_MASK                                                        0x00008000L
+//RCC_DEV0_0_RCC_VDM_SUPPORT
+#define RCC_DEV0_0_RCC_VDM_SUPPORT__MCTP_SUPPORT__SHIFT                                                       0x0
+#define RCC_DEV0_0_RCC_VDM_SUPPORT__AMPTP_SUPPORT__SHIFT                                                      0x1
+#define RCC_DEV0_0_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT__SHIFT                                                  0x2
+#define RCC_DEV0_0_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE__SHIFT                                        0x3
+#define RCC_DEV0_0_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE__SHIFT                                    0x4
+#define RCC_DEV0_0_RCC_VDM_SUPPORT__MCTP_SUPPORT_MASK                                                         0x00000001L
+#define RCC_DEV0_0_RCC_VDM_SUPPORT__AMPTP_SUPPORT_MASK                                                        0x00000002L
+#define RCC_DEV0_0_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT_MASK                                                    0x00000004L
+#define RCC_DEV0_0_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE_MASK                                          0x00000008L
+#define RCC_DEV0_0_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE_MASK                                      0x00000010L
+//RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED__SHIFT                                 0x0
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING__SHIFT                              0x1
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE__SHIFT                                0x2
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER__SHIFT                                 0x3
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD__SHIFT                           0x4
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS__SHIFT                                  0x5
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET__SHIFT                                 0xb
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS__SHIFT                                 0x12
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET__SHIFT                                0x19
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED_MASK                                   0x00000001L
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING_MASK                                0x00000002L
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE_MASK                                  0x00000004L
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER_MASK                                   0x00000008L
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD_MASK                             0x00000010L
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS_MASK                                    0x000007E0L
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET_MASK                                   0x0003F800L
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS_MASK                                   0x01FC0000L
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET_MASK                                  0xFE000000L
+//RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE__SHIFT                             0x0
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING__SHIFT                              0x6
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES__SHIFT                                         0xc
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT__SHIFT                                      0x11
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE_MASK                               0x0000003FL
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING_MASK                                0x00000FC0L
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES_MASK                                           0x0001F000L
+#define RCC_DEV0_0_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT_MASK                                        0x00FE0000L
+//RCC_DEV0_0_RCC_GPUIOV_REGION
+#define RCC_DEV0_0_RCC_GPUIOV_REGION__LFB_REGION__SHIFT                                                       0x0
+#define RCC_DEV0_0_RCC_GPUIOV_REGION__MAX_REGION__SHIFT                                                       0x4
+#define RCC_DEV0_0_RCC_GPUIOV_REGION__LFB_REGION_MASK                                                         0x0000000FL
+#define RCC_DEV0_0_RCC_GPUIOV_REGION__MAX_REGION_MASK                                                         0x000000F0L
+//RCC_DEV0_0_RCC_GPU_HOSTVM_EN
+#define RCC_DEV0_0_RCC_GPU_HOSTVM_EN__GPU_HOSTVM_EN__SHIFT                                                    0x0
+#define RCC_DEV0_0_RCC_GPU_HOSTVM_EN__GPU_HOSTVM_EN_MASK                                                      0x00000001L
+//RCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL
+#define RCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL__RCC_CONSOLE_IOV_MODE_ENABLE__SHIFT                              0x0
+#define RCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL__MULTIOS_IH_SUPPORT_EN__SHIFT                                    0x1
+#define RCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL__RCC_CONSOLE_IOV_MODE_ENABLE_MASK                                0x00000001L
+#define RCC_DEV0_0_RCC_CONSOLE_IOV_MODE_CNTL__MULTIOS_IH_SUPPORT_EN_MASK                                      0x00000002L
+//RCC_DEV0_0_RCC_CONSOLE_IOV_FIRST_VF_OFFSET
+#define RCC_DEV0_0_RCC_CONSOLE_IOV_FIRST_VF_OFFSET__CONSOLE_IOV_FIRST_VF_OFFSET__SHIFT                        0x0
+#define RCC_DEV0_0_RCC_CONSOLE_IOV_FIRST_VF_OFFSET__CONSOLE_IOV_FIRST_VF_OFFSET_MASK                          0xFFFFL
+//RCC_DEV0_0_RCC_CONSOLE_IOV_VF_STRIDE
+#define RCC_DEV0_0_RCC_CONSOLE_IOV_VF_STRIDE__CONSOLE_IOV_VF_STRIDE__SHIFT                                    0x0
+#define RCC_DEV0_0_RCC_CONSOLE_IOV_VF_STRIDE__CONSOLE_IOV_VF_STRIDE_MASK                                      0xFFFFL
+//RCC_DEV0_0_RCC_PEER_REG_RANGE0
+#define RCC_DEV0_0_RCC_PEER_REG_RANGE0__START_ADDR__SHIFT                                                     0x0
+#define RCC_DEV0_0_RCC_PEER_REG_RANGE0__END_ADDR__SHIFT                                                       0x10
+#define RCC_DEV0_0_RCC_PEER_REG_RANGE0__START_ADDR_MASK                                                       0x0000FFFFL
+#define RCC_DEV0_0_RCC_PEER_REG_RANGE0__END_ADDR_MASK                                                         0xFFFF0000L
+//RCC_DEV0_0_RCC_PEER_REG_RANGE1
+#define RCC_DEV0_0_RCC_PEER_REG_RANGE1__START_ADDR__SHIFT                                                     0x0
+#define RCC_DEV0_0_RCC_PEER_REG_RANGE1__END_ADDR__SHIFT                                                       0x10
+#define RCC_DEV0_0_RCC_PEER_REG_RANGE1__START_ADDR_MASK                                                       0x0000FFFFL
+#define RCC_DEV0_0_RCC_PEER_REG_RANGE1__END_ADDR_MASK                                                         0xFFFF0000L
+//RCC_DEV0_0_RCC_BUS_CNTL
+#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS__SHIFT                                                            0x2
+#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS__SHIFT                                                           0x3
+#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_BM_DIS__SHIFT                                                            0x4
+#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS_DN__SHIFT                                                         0x5
+#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS_DN__SHIFT                                                        0x6
+#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS_UP__SHIFT                                                         0x7
+#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS_UP__SHIFT                                                        0x8
+#define RCC_DEV0_0_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT__SHIFT                                                 0xc
+#define RCC_DEV0_0_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC__SHIFT                                           0xd
+#define RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR__SHIFT                                          0x10
+#define RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR__SHIFT                                          0x11
+#define RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR__SHIFT                                          0x12
+#define RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR__SHIFT                                          0x13
+#define RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR__SHIFT                                          0x14
+#define RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR__SHIFT                                          0x15
+#define RCC_DEV0_0_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE__SHIFT                                                 0x18
+#define RCC_DEV0_0_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE__SHIFT                                                 0x19
+#define RCC_DEV0_0_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE__SHIFT                                            0x1c
+#define RCC_DEV0_0_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE__SHIFT                                            0x1d
+#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS_MASK                                                              0x00000004L
+#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS_MASK                                                             0x00000008L
+#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_BM_DIS_MASK                                                              0x00000010L
+#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS_DN_MASK                                                           0x00000020L
+#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS_DN_MASK                                                          0x00000040L
+#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_IO_DIS_UP_MASK                                                           0x00000080L
+#define RCC_DEV0_0_RCC_BUS_CNTL__PMI_MEM_DIS_UP_MASK                                                          0x00000100L
+#define RCC_DEV0_0_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT_MASK                                                   0x00001000L
+#define RCC_DEV0_0_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC_MASK                                             0x00002000L
+#define RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR_MASK                                            0x00010000L
+#define RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR_MASK                                            0x00020000L
+#define RCC_DEV0_0_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR_MASK                                            0x00040000L
+#define RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR_MASK                                            0x00080000L
+#define RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR_MASK                                            0x00100000L
+#define RCC_DEV0_0_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR_MASK                                            0x00200000L
+#define RCC_DEV0_0_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE_MASK                                                   0x01000000L
+#define RCC_DEV0_0_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE_MASK                                                   0x0E000000L
+#define RCC_DEV0_0_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE_MASK                                              0x10000000L
+#define RCC_DEV0_0_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE_MASK                                              0xE0000000L
+//RCC_DEV0_0_RCC_CONFIG_CNTL
+#define RCC_DEV0_0_RCC_CONFIG_CNTL__CFG_VGA_RAM_EN__SHIFT                                                     0x0
+#define RCC_DEV0_0_RCC_CONFIG_CNTL__GENMO_MONO_ADDRESS_B__SHIFT                                               0x2
+#define RCC_DEV0_0_RCC_CONFIG_CNTL__GRPH_ADRSEL__SHIFT                                                        0x3
+#define RCC_DEV0_0_RCC_CONFIG_CNTL__CFG_VGA_RAM_EN_MASK                                                       0x00000001L
+#define RCC_DEV0_0_RCC_CONFIG_CNTL__GENMO_MONO_ADDRESS_B_MASK                                                 0x00000004L
+#define RCC_DEV0_0_RCC_CONFIG_CNTL__GRPH_ADRSEL_MASK                                                          0x00000018L
+//RCC_DEV0_0_RCC_CONFIG_F0_BASE
+#define RCC_DEV0_0_RCC_CONFIG_F0_BASE__F0_BASE__SHIFT                                                         0x0
+#define RCC_DEV0_0_RCC_CONFIG_F0_BASE__F0_BASE_MASK                                                           0xFFFFFFFFL
+//RCC_DEV0_0_RCC_CONFIG_APER_SIZE
+#define RCC_DEV0_0_RCC_CONFIG_APER_SIZE__APER_SIZE__SHIFT                                                     0x0
+#define RCC_DEV0_0_RCC_CONFIG_APER_SIZE__APER_SIZE_MASK                                                       0xFFFFFFFFL
+//RCC_DEV0_0_RCC_CONFIG_REG_APER_SIZE
+#define RCC_DEV0_0_RCC_CONFIG_REG_APER_SIZE__REG_APER_SIZE__SHIFT                                             0x0
+#define RCC_DEV0_0_RCC_CONFIG_REG_APER_SIZE__REG_APER_SIZE_MASK                                               0x07FFFFFFL
+//RCC_DEV0_0_RCC_XDMA_LO
+#define RCC_DEV0_0_RCC_XDMA_LO__BIF_XDMA_LOWER_BOUND__SHIFT                                                   0x0
+#define RCC_DEV0_0_RCC_XDMA_LO__BIF_XDMA_APER_EN__SHIFT                                                       0x1f
+#define RCC_DEV0_0_RCC_XDMA_LO__BIF_XDMA_LOWER_BOUND_MASK                                                     0x7FFFFFFFL
+#define RCC_DEV0_0_RCC_XDMA_LO__BIF_XDMA_APER_EN_MASK                                                         0x80000000L
+//RCC_DEV0_0_RCC_XDMA_HI
+#define RCC_DEV0_0_RCC_XDMA_HI__BIF_XDMA_UPPER_BOUND__SHIFT                                                   0x0
+#define RCC_DEV0_0_RCC_XDMA_HI__BIF_XDMA_UPPER_BOUND_MASK                                                     0x7FFFFFFFL
+//RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS__SHIFT                                   0x7
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__SHIFT                                 0x8
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR__SHIFT                                    0x9
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR__SHIFT                                    0xa
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR__SHIFT                                 0xb
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR__SHIFT                                  0xc
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR__SHIFT                                      0xd
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS__SHIFT                      0xe
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS__SHIFT                         0xf
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS__SHIFT                                 0x10
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS__SHIFT                           0x11
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN__SHIFT                               0x12
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS__SHIFT                     0x13
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS_MASK                                     0x00000080L
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN_MASK                                   0x00000100L
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR_MASK                                      0x00000200L
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR_MASK                                      0x00000400L
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR_MASK                                   0x00000800L
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR_MASK                                    0x00001000L
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR_MASK                                        0x00002000L
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS_MASK                        0x00004000L
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS_MASK                           0x00008000L
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS_MASK                                   0x00010000L
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS_MASK                             0x00020000L
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN_MASK                                 0x00040000L
+#define RCC_DEV0_0_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS_MASK                       0x00080000L
+//RCC_DEV0_0_RCC_BUSNUM_CNTL1
+#define RCC_DEV0_0_RCC_BUSNUM_CNTL1__ID_MASK__SHIFT                                                           0x0
+#define RCC_DEV0_0_RCC_BUSNUM_CNTL1__ID_MASK_MASK                                                             0x000000FFL
+//RCC_DEV0_0_RCC_BUSNUM_LIST0
+#define RCC_DEV0_0_RCC_BUSNUM_LIST0__ID0__SHIFT                                                               0x0
+#define RCC_DEV0_0_RCC_BUSNUM_LIST0__ID1__SHIFT                                                               0x8
+#define RCC_DEV0_0_RCC_BUSNUM_LIST0__ID2__SHIFT                                                               0x10
+#define RCC_DEV0_0_RCC_BUSNUM_LIST0__ID3__SHIFT                                                               0x18
+#define RCC_DEV0_0_RCC_BUSNUM_LIST0__ID0_MASK                                                                 0x000000FFL
+#define RCC_DEV0_0_RCC_BUSNUM_LIST0__ID1_MASK                                                                 0x0000FF00L
+#define RCC_DEV0_0_RCC_BUSNUM_LIST0__ID2_MASK                                                                 0x00FF0000L
+#define RCC_DEV0_0_RCC_BUSNUM_LIST0__ID3_MASK                                                                 0xFF000000L
+//RCC_DEV0_0_RCC_BUSNUM_LIST1
+#define RCC_DEV0_0_RCC_BUSNUM_LIST1__ID4__SHIFT                                                               0x0
+#define RCC_DEV0_0_RCC_BUSNUM_LIST1__ID5__SHIFT                                                               0x8
+#define RCC_DEV0_0_RCC_BUSNUM_LIST1__ID6__SHIFT                                                               0x10
+#define RCC_DEV0_0_RCC_BUSNUM_LIST1__ID7__SHIFT                                                               0x18
+#define RCC_DEV0_0_RCC_BUSNUM_LIST1__ID4_MASK                                                                 0x000000FFL
+#define RCC_DEV0_0_RCC_BUSNUM_LIST1__ID5_MASK                                                                 0x0000FF00L
+#define RCC_DEV0_0_RCC_BUSNUM_LIST1__ID6_MASK                                                                 0x00FF0000L
+#define RCC_DEV0_0_RCC_BUSNUM_LIST1__ID7_MASK                                                                 0xFF000000L
+//RCC_DEV0_0_RCC_BUSNUM_CNTL2
+#define RCC_DEV0_0_RCC_BUSNUM_CNTL2__AUTOUPDATE_SEL__SHIFT                                                    0x0
+#define RCC_DEV0_0_RCC_BUSNUM_CNTL2__AUTOUPDATE_EN__SHIFT                                                     0x8
+#define RCC_DEV0_0_RCC_BUSNUM_CNTL2__HDPREG_CNTL__SHIFT                                                       0x10
+#define RCC_DEV0_0_RCC_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH__SHIFT                                           0x11
+#define RCC_DEV0_0_RCC_BUSNUM_CNTL2__AUTOUPDATE_SEL_MASK                                                      0x000000FFL
+#define RCC_DEV0_0_RCC_BUSNUM_CNTL2__AUTOUPDATE_EN_MASK                                                       0x00000100L
+#define RCC_DEV0_0_RCC_BUSNUM_CNTL2__HDPREG_CNTL_MASK                                                         0x00010000L
+#define RCC_DEV0_0_RCC_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH_MASK                                             0x00020000L
+//RCC_DEV0_0_RCC_CAPTURE_HOST_BUSNUM
+#define RCC_DEV0_0_RCC_CAPTURE_HOST_BUSNUM__CHECK_EN__SHIFT                                                   0x0
+#define RCC_DEV0_0_RCC_CAPTURE_HOST_BUSNUM__CHECK_EN_MASK                                                     0x00000001L
+//RCC_DEV0_0_RCC_HOST_BUSNUM
+#define RCC_DEV0_0_RCC_HOST_BUSNUM__HOST_ID__SHIFT                                                            0x0
+#define RCC_DEV0_0_RCC_HOST_BUSNUM__HOST_ID_MASK                                                              0x0000FFFFL
+//RCC_DEV0_0_RCC_PEER0_FB_OFFSET_HI
+#define RCC_DEV0_0_RCC_PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI__SHIFT                                          0x0
+#define RCC_DEV0_0_RCC_PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI_MASK                                            0x000FFFFFL
+//RCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO
+#define RCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO__SHIFT                                          0x0
+#define RCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_EN__SHIFT                                                 0x1f
+#define RCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO_MASK                                            0x000FFFFFL
+#define RCC_DEV0_0_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_EN_MASK                                                   0x80000000L
+//RCC_DEV0_0_RCC_PEER1_FB_OFFSET_HI
+#define RCC_DEV0_0_RCC_PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI__SHIFT                                          0x0
+#define RCC_DEV0_0_RCC_PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI_MASK                                            0x000FFFFFL
+//RCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO
+#define RCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO__SHIFT                                          0x0
+#define RCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_EN__SHIFT                                                 0x1f
+#define RCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO_MASK                                            0x000FFFFFL
+#define RCC_DEV0_0_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_EN_MASK                                                   0x80000000L
+//RCC_DEV0_0_RCC_PEER2_FB_OFFSET_HI
+#define RCC_DEV0_0_RCC_PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI__SHIFT                                          0x0
+#define RCC_DEV0_0_RCC_PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI_MASK                                            0x000FFFFFL
+//RCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO
+#define RCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO__SHIFT                                          0x0
+#define RCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_EN__SHIFT                                                 0x1f
+#define RCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO_MASK                                            0x000FFFFFL
+#define RCC_DEV0_0_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_EN_MASK                                                   0x80000000L
+//RCC_DEV0_0_RCC_PEER3_FB_OFFSET_HI
+#define RCC_DEV0_0_RCC_PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI__SHIFT                                          0x0
+#define RCC_DEV0_0_RCC_PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI_MASK                                            0x000FFFFFL
+//RCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO
+#define RCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO__SHIFT                                          0x0
+#define RCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_EN__SHIFT                                                 0x1f
+#define RCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO_MASK                                            0x000FFFFFL
+#define RCC_DEV0_0_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_EN_MASK                                                   0x80000000L
+//RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0
+#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID0__SHIFT                                                   0x0
+#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID1__SHIFT                                                   0x8
+#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID2__SHIFT                                                   0x10
+#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID3__SHIFT                                                   0x18
+#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID0_MASK                                                     0x000000FFL
+#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID1_MASK                                                     0x0000FF00L
+#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID2_MASK                                                     0x00FF0000L
+#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID3_MASK                                                     0xFF000000L
+//RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1
+#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID4__SHIFT                                                   0x0
+#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID5__SHIFT                                                   0x8
+#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID6__SHIFT                                                   0x10
+#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID7__SHIFT                                                   0x18
+#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID4_MASK                                                     0x000000FFL
+#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID5_MASK                                                     0x0000FF00L
+#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID6_MASK                                                     0x00FF0000L
+#define RCC_DEV0_0_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID7_MASK                                                     0xFF000000L
+//RCC_DEV0_0_RCC_DEV0_LINK_CNTL
+#define RCC_DEV0_0_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT__SHIFT                                                  0x0
+#define RCC_DEV0_0_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY__SHIFT                                                 0x8
+#define RCC_DEV0_0_RCC_DEV0_LINK_CNTL__SWUS_SRB_RST_TLS_DIS__SHIFT                                            0x10
+#define RCC_DEV0_0_RCC_DEV0_LINK_CNTL__SWUS_LDN_RST_TLS_DIS__SHIFT                                            0x11
+#define RCC_DEV0_0_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT_MASK                                                    0x00000001L
+#define RCC_DEV0_0_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY_MASK                                                   0x00000100L
+#define RCC_DEV0_0_RCC_DEV0_LINK_CNTL__SWUS_SRB_RST_TLS_DIS_MASK                                              0x00010000L
+#define RCC_DEV0_0_RCC_DEV0_LINK_CNTL__SWUS_LDN_RST_TLS_DIS_MASK                                              0x00020000L
+//RCC_DEV0_0_RCC_CMN_LINK_CNTL
+#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS__SHIFT                                             0x0
+#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS__SHIFT                                              0x1
+#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS__SHIFT                                             0x2
+#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN__SHIFT                                          0x3
+#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER__SHIFT                                             0x10
+#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS_MASK                                               0x00000001L
+#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS_MASK                                                0x00000002L
+#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS_MASK                                               0x00000004L
+#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN_MASK                                            0x00000008L
+#define RCC_DEV0_0_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER_MASK                                               0xFFFF0000L
+//RCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE
+#define RCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS__SHIFT                                            0x0
+#define RCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV__SHIFT                                            0x8
+#define RCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE__EP_REQID_SEG__SHIFT                                            0x10
+#define RCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS_MASK                                              0x000000FFL
+#define RCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV_MASK                                              0x00001F00L
+#define RCC_DEV0_0_RCC_EP_REQUESTERID_RESTORE__EP_REQID_SEG_MASK                                              0x00FF0000L
+//RCC_DEV0_0_RCC_LTR_LSWITCH_CNTL
+#define RCC_DEV0_0_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE__SHIFT                                         0x0
+#define RCC_DEV0_0_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE_MASK                                           0x000003FFL
+//RCC_DEV0_0_RCC_MH_ARB_CNTL
+#define RCC_DEV0_0_RCC_MH_ARB_CNTL__MH_ARB_MODE__SHIFT                                                        0x0
+#define RCC_DEV0_0_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY__SHIFT                                                0x1
+#define RCC_DEV0_0_RCC_MH_ARB_CNTL__MH_ARB_MODE_MASK                                                          0x00000001L
+#define RCC_DEV0_0_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY_MASK                                                  0x0000FFFEL
+
+
+// addressBlock: nbif0_nbif0_rcc_dev0_epf0_BIFDEC2
+//RCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_LO
+#define RCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT                                               0x2
+#define RCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK                                                 0xFFFFFFFCL
+//RCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_HI
+#define RCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT                                               0x0
+#define RCC_DEV0_EPF0_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK                                                 0xFFFFFFFFL
+//RCC_DEV0_EPF0_GFXMSIX_VECT0_MSG_DATA
+#define RCC_DEV0_EPF0_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT                                                 0x0
+#define RCC_DEV0_EPF0_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK                                                   0xFFFFFFFFL
+//RCC_DEV0_EPF0_GFXMSIX_VECT0_CONTROL
+#define RCC_DEV0_EPF0_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT                                                  0x0
+#define RCC_DEV0_EPF0_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK                                                    0x00000001L
+//RCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_LO
+#define RCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT                                               0x2
+#define RCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK                                                 0xFFFFFFFCL
+//RCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_HI
+#define RCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT                                               0x0
+#define RCC_DEV0_EPF0_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK                                                 0xFFFFFFFFL
+//RCC_DEV0_EPF0_GFXMSIX_VECT1_MSG_DATA
+#define RCC_DEV0_EPF0_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT                                                 0x0
+#define RCC_DEV0_EPF0_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK                                                   0xFFFFFFFFL
+//RCC_DEV0_EPF0_GFXMSIX_VECT1_CONTROL
+#define RCC_DEV0_EPF0_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT                                                  0x0
+#define RCC_DEV0_EPF0_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK                                                    0x00000001L
+//RCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_LO
+#define RCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT                                               0x2
+#define RCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK                                                 0xFFFFFFFCL
+//RCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_HI
+#define RCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT                                               0x0
+#define RCC_DEV0_EPF0_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK                                                 0xFFFFFFFFL
+//RCC_DEV0_EPF0_GFXMSIX_VECT2_MSG_DATA
+#define RCC_DEV0_EPF0_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT                                                 0x0
+#define RCC_DEV0_EPF0_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK                                                   0xFFFFFFFFL
+//RCC_DEV0_EPF0_GFXMSIX_VECT2_CONTROL
+#define RCC_DEV0_EPF0_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT                                                  0x0
+#define RCC_DEV0_EPF0_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK                                                    0x00000001L
+//RCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_LO
+#define RCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT                                               0x2
+#define RCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK                                                 0xFFFFFFFCL
+//RCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_HI
+#define RCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT                                               0x0
+#define RCC_DEV0_EPF0_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK                                                 0xFFFFFFFFL
+//RCC_DEV0_EPF0_GFXMSIX_VECT3_MSG_DATA
+#define RCC_DEV0_EPF0_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT                                                 0x0
+#define RCC_DEV0_EPF0_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK                                                   0xFFFFFFFFL
+//RCC_DEV0_EPF0_GFXMSIX_VECT3_CONTROL
+#define RCC_DEV0_EPF0_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT                                                  0x0
+#define RCC_DEV0_EPF0_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK                                                    0x00000001L
+//RCC_DEV0_EPF0_GFXMSIX_VECT4_ADDR_LO
+#define RCC_DEV0_EPF0_GFXMSIX_VECT4_ADDR_LO__MSG_ADDR_LO__SHIFT                                               0x2
+#define RCC_DEV0_EPF0_GFXMSIX_VECT4_ADDR_LO__MSG_ADDR_LO_MASK                                                 0xFFFFFFFCL
+//RCC_DEV0_EPF0_GFXMSIX_VECT4_ADDR_HI
+#define RCC_DEV0_EPF0_GFXMSIX_VECT4_ADDR_HI__MSG_ADDR_HI__SHIFT                                               0x0
+#define RCC_DEV0_EPF0_GFXMSIX_VECT4_ADDR_HI__MSG_ADDR_HI_MASK                                                 0xFFFFFFFFL
+//RCC_DEV0_EPF0_GFXMSIX_VECT4_MSG_DATA
+#define RCC_DEV0_EPF0_GFXMSIX_VECT4_MSG_DATA__MSG_DATA__SHIFT                                                 0x0
+#define RCC_DEV0_EPF0_GFXMSIX_VECT4_MSG_DATA__MSG_DATA_MASK                                                   0xFFFFFFFFL
+//RCC_DEV0_EPF0_GFXMSIX_VECT4_CONTROL
+#define RCC_DEV0_EPF0_GFXMSIX_VECT4_CONTROL__MASK_BIT__SHIFT                                                  0x0
+#define RCC_DEV0_EPF0_GFXMSIX_VECT4_CONTROL__MASK_BIT_MASK                                                    0x00000001L
+//RCC_DEV0_EPF0_GFXMSIX_VECT5_ADDR_LO
+#define RCC_DEV0_EPF0_GFXMSIX_VECT5_ADDR_LO__MSG_ADDR_LO__SHIFT                                               0x2
+#define RCC_DEV0_EPF0_GFXMSIX_VECT5_ADDR_LO__MSG_ADDR_LO_MASK                                                 0xFFFFFFFCL
+//RCC_DEV0_EPF0_GFXMSIX_VECT5_ADDR_HI
+#define RCC_DEV0_EPF0_GFXMSIX_VECT5_ADDR_HI__MSG_ADDR_HI__SHIFT                                               0x0
+#define RCC_DEV0_EPF0_GFXMSIX_VECT5_ADDR_HI__MSG_ADDR_HI_MASK                                                 0xFFFFFFFFL
+//RCC_DEV0_EPF0_GFXMSIX_VECT5_MSG_DATA
+#define RCC_DEV0_EPF0_GFXMSIX_VECT5_MSG_DATA__MSG_DATA__SHIFT                                                 0x0
+#define RCC_DEV0_EPF0_GFXMSIX_VECT5_MSG_DATA__MSG_DATA_MASK                                                   0xFFFFFFFFL
+//RCC_DEV0_EPF0_GFXMSIX_VECT5_CONTROL
+#define RCC_DEV0_EPF0_GFXMSIX_VECT5_CONTROL__MASK_BIT__SHIFT                                                  0x0
+#define RCC_DEV0_EPF0_GFXMSIX_VECT5_CONTROL__MASK_BIT_MASK                                                    0x00000001L
+//RCC_DEV0_EPF0_GFXMSIX_VECT6_ADDR_LO
+#define RCC_DEV0_EPF0_GFXMSIX_VECT6_ADDR_LO__MSG_ADDR_LO__SHIFT                                               0x2
+#define RCC_DEV0_EPF0_GFXMSIX_VECT6_ADDR_LO__MSG_ADDR_LO_MASK                                                 0xFFFFFFFCL
+//RCC_DEV0_EPF0_GFXMSIX_VECT6_ADDR_HI
+#define RCC_DEV0_EPF0_GFXMSIX_VECT6_ADDR_HI__MSG_ADDR_HI__SHIFT                                               0x0
+#define RCC_DEV0_EPF0_GFXMSIX_VECT6_ADDR_HI__MSG_ADDR_HI_MASK                                                 0xFFFFFFFFL
+//RCC_DEV0_EPF0_GFXMSIX_VECT6_MSG_DATA
+#define RCC_DEV0_EPF0_GFXMSIX_VECT6_MSG_DATA__MSG_DATA__SHIFT                                                 0x0
+#define RCC_DEV0_EPF0_GFXMSIX_VECT6_MSG_DATA__MSG_DATA_MASK                                                   0xFFFFFFFFL
+//RCC_DEV0_EPF0_GFXMSIX_VECT6_CONTROL
+#define RCC_DEV0_EPF0_GFXMSIX_VECT6_CONTROL__MASK_BIT__SHIFT                                                  0x0
+#define RCC_DEV0_EPF0_GFXMSIX_VECT6_CONTROL__MASK_BIT_MASK                                                    0x00000001L
+//RCC_DEV0_EPF0_GFXMSIX_VECT7_ADDR_LO
+#define RCC_DEV0_EPF0_GFXMSIX_VECT7_ADDR_LO__MSG_ADDR_LO__SHIFT                                               0x2
+#define RCC_DEV0_EPF0_GFXMSIX_VECT7_ADDR_LO__MSG_ADDR_LO_MASK                                                 0xFFFFFFFCL
+//RCC_DEV0_EPF0_GFXMSIX_VECT7_ADDR_HI
+#define RCC_DEV0_EPF0_GFXMSIX_VECT7_ADDR_HI__MSG_ADDR_HI__SHIFT                                               0x0
+#define RCC_DEV0_EPF0_GFXMSIX_VECT7_ADDR_HI__MSG_ADDR_HI_MASK                                                 0xFFFFFFFFL
+//RCC_DEV0_EPF0_GFXMSIX_VECT7_MSG_DATA
+#define RCC_DEV0_EPF0_GFXMSIX_VECT7_MSG_DATA__MSG_DATA__SHIFT                                                 0x0
+#define RCC_DEV0_EPF0_GFXMSIX_VECT7_MSG_DATA__MSG_DATA_MASK                                                   0xFFFFFFFFL
+//RCC_DEV0_EPF0_GFXMSIX_VECT7_CONTROL
+#define RCC_DEV0_EPF0_GFXMSIX_VECT7_CONTROL__MASK_BIT__SHIFT                                                  0x0
+#define RCC_DEV0_EPF0_GFXMSIX_VECT7_CONTROL__MASK_BIT_MASK                                                    0x00000001L
+//RCC_DEV0_EPF0_GFXMSIX_VECT8_ADDR_LO
+#define RCC_DEV0_EPF0_GFXMSIX_VECT8_ADDR_LO__MSG_ADDR_LO__SHIFT                                               0x2
+#define RCC_DEV0_EPF0_GFXMSIX_VECT8_ADDR_LO__MSG_ADDR_LO_MASK                                                 0xFFFFFFFCL
+//RCC_DEV0_EPF0_GFXMSIX_VECT8_ADDR_HI
+#define RCC_DEV0_EPF0_GFXMSIX_VECT8_ADDR_HI__MSG_ADDR_HI__SHIFT                                               0x0
+#define RCC_DEV0_EPF0_GFXMSIX_VECT8_ADDR_HI__MSG_ADDR_HI_MASK                                                 0xFFFFFFFFL
+//RCC_DEV0_EPF0_GFXMSIX_VECT8_MSG_DATA
+#define RCC_DEV0_EPF0_GFXMSIX_VECT8_MSG_DATA__MSG_DATA__SHIFT                                                 0x0
+#define RCC_DEV0_EPF0_GFXMSIX_VECT8_MSG_DATA__MSG_DATA_MASK                                                   0xFFFFFFFFL
+//RCC_DEV0_EPF0_GFXMSIX_VECT8_CONTROL
+#define RCC_DEV0_EPF0_GFXMSIX_VECT8_CONTROL__MASK_BIT__SHIFT                                                  0x0
+#define RCC_DEV0_EPF0_GFXMSIX_VECT8_CONTROL__MASK_BIT_MASK                                                    0x00000001L
+//RCC_DEV0_EPF0_GFXMSIX_PBA
+#define RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT                                                 0x0
+#define RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT                                                 0x1
+#define RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_2__SHIFT                                                 0x2
+#define RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_3__SHIFT                                                 0x3
+#define RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK                                                   0x00000001L
+#define RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK                                                   0x00000002L
+#define RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_2_MASK                                                   0x00000004L
+#define RCC_DEV0_EPF0_GFXMSIX_PBA__MSIX_PENDING_BITS_3_MASK                                                   0x00000008L
+
+
+// addressBlock: nbif0_nbif0_rcc_strap_BIFDEC1
+//RCC_STRAP0_RCC_BIF_STRAP0
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_GEN4_DIS__SHIFT                                                      0x0
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_EXPANSION_ROM_VALIDATION_SUPPORT__SHIFT                              0x1
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_PX_CAPABLE__SHIFT                                                    0x7
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3__SHIFT                                                 0x8
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN__SHIFT                                  0x9
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR__SHIFT                                         0xa
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN__SHIFT                                     0xb
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR__SHIFT                                              0xc
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR__SHIFT                                             0xd
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_AUD_PIN__SHIFT                                                       0x12
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN__SHIFT                                               0x14
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIF_GFX_IOBAR_DIS_AND_REGBAR_64BIT_EN__SHIFT                         0x15
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_GPUIOV_EN__SHIFT                                                     0x16
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_OVERRIDE__SHIFT                                          0x17
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_GEN3_DIS__SHIFT                                                      0x18
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4__SHIFT                                                 0x19
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_QUICKSIM_START__SHIFT                                                0x1a
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING__SHIFT                                     0x1b
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_IGNORE_LOCAL_PREFIX_UR_SWUS__SHIFT                                   0x1c
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN__SHIFT                                      0x1d
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE__SHIFT                                                   0x1e
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN__SHIFT                                            0x1f
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_GEN4_DIS_MASK                                                        0x00000001L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_EXPANSION_ROM_VALIDATION_SUPPORT_MASK                                0x00000002L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK                                                      0x00000080L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3_MASK                                                   0x00000100L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN_MASK                                    0x00000200L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR_MASK                                           0x00000400L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN_MASK                                       0x00000800L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR_MASK                                                0x00001000L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR_MASK                                               0x00002000L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_AUD_PIN_MASK                                                         0x000C0000L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN_MASK                                                 0x00100000L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIF_GFX_IOBAR_DIS_AND_REGBAR_64BIT_EN_MASK                           0x00200000L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_GPUIOV_EN_MASK                                                       0x00400000L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_OVERRIDE_MASK                                            0x00800000L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_GEN3_DIS_MASK                                                        0x01000000L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4_MASK                                                   0x02000000L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_QUICKSIM_START_MASK                                                  0x04000000L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING_MASK                                       0x08000000L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_IGNORE_LOCAL_PREFIX_UR_SWUS_MASK                                     0x10000000L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN_MASK                                        0x20000000L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE_MASK                                                     0x40000000L
+#define RCC_STRAP0_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN_MASK                                              0x80000000L
+//RCC_STRAP0_RCC_BIF_STRAP1
+#define RCC_STRAP0_RCC_BIF_STRAP1__FUSESTRAP_VALID__SHIFT                                                     0x0
+#define RCC_STRAP0_RCC_BIF_STRAP1__ROMSTRAP_VALID__SHIFT                                                      0x1
+#define RCC_STRAP0_RCC_BIF_STRAP1__WRITE_DISABLE__SHIFT                                                       0x2
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN__SHIFT                                      0x3
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_FLIT_MODE_SUPPORT__SHIFT                                             0x4
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS__SHIFT                                     0x5
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE__SHIFT                                       0x6
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGINING_READY__SHIFT                                               0x7
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN__SHIFT                                                  0x8
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN__SHIFT                                                 0x9
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE__SHIFT                                                  0xa
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE__SHIFT                                        0xc
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_HWREV_LSB2__SHIFT                                                    0xd
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWREV_LSB2__SHIFT                                                    0xf
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY__SHIFT                                             0x11
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS__SHIFT                                             0x12
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_DLF_EN__SHIFT                                                        0x13
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_PHY_16GT_EN__SHIFT                                                   0x14
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGIN_EN__SHIFT                                                     0x15
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN__SHIFT                                             0x16
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN__SHIFT                                     0x17
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE__SHIFT                                             0x1a
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_GSI_SMN_POSTWR_MULTI_EN__SHIFT                                       0x1b
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_DLF_EN_EP__SHIFT                                                     0x1d
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_AP_EN__SHIFT                                                         0x1e
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_AP_EN_DN__SHIFT                                                      0x1f
+#define RCC_STRAP0_RCC_BIF_STRAP1__FUSESTRAP_VALID_MASK                                                       0x00000001L
+#define RCC_STRAP0_RCC_BIF_STRAP1__ROMSTRAP_VALID_MASK                                                        0x00000002L
+#define RCC_STRAP0_RCC_BIF_STRAP1__WRITE_DISABLE_MASK                                                         0x00000004L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN_MASK                                        0x00000008L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_FLIT_MODE_SUPPORT_MASK                                               0x00000010L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS_MASK                                       0x00000020L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE_MASK                                         0x00000040L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGINING_READY_MASK                                                 0x00000080L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN_MASK                                                    0x00000100L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN_MASK                                                   0x00000200L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE_MASK                                                    0x00000C00L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE_MASK                                          0x00001000L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_HWREV_LSB2_MASK                                                      0x00006000L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_SWREV_LSB2_MASK                                                      0x00018000L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY_MASK                                               0x00020000L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS_MASK                                               0x00040000L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_DLF_EN_MASK                                                          0x00080000L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_PHY_16GT_EN_MASK                                                     0x00100000L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_MARGIN_EN_MASK                                                       0x00200000L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN_MASK                                               0x00400000L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN_MASK                                       0x00800000L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE_MASK                                               0x04000000L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_GSI_SMN_POSTWR_MULTI_EN_MASK                                         0x18000000L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_DLF_EN_EP_MASK                                                       0x20000000L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_AP_EN_MASK                                                           0x40000000L
+#define RCC_STRAP0_RCC_BIF_STRAP1__STRAP_AP_EN_DN_MASK                                                        0x80000000L
+//RCC_STRAP0_RCC_BIF_STRAP10
+//RCC_STRAP0_RCC_BIF_STRAP11
+//RCC_STRAP0_RCC_BIF_STRAP12
+//RCC_STRAP0_RCC_BIF_STRAP13
+#define RCC_STRAP0_RCC_BIF_STRAP13__STRAP_PCIE_SMN_APER__SHIFT                                                0x0
+#define RCC_STRAP0_RCC_BIF_STRAP13__STRAP_PCIE_SMN_APER_MASK                                                  0x00000FFFL
+//RCC_STRAP0_RCC_BIF_STRAP2
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE__SHIFT                                     0x0
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SWUS_SPT__SHIFT                                                      0x1
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SWDS_SPT__SHIFT                                                      0x2
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS__SHIFT                                            0x3
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS__SHIFT                                            0x4
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA__SHIFT                                        0x5
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA__SHIFT                                      0x6
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS__SHIFT                                 0x8
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS__SHIFT                                        0x9
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN__SHIFT                                   0xa
+#define RCC_STRAP0_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2__SHIFT                                                 0xd
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS__SHIFT                                             0xe
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN__SHIFT                                 0xf
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE__SHIFT                                         0x10
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS__SHIFT                                        0x18
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_ARI_EN_UP__SHIFT                                                     0x19
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_VLINK_PMETO_LDN_EXIT_BY_LNKRST_DIS__SHIFT                            0x1f
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE_MASK                                       0x00000001L
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SWUS_SPT_MASK                                                        0x00000002L
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SWDS_SPT_MASK                                                        0x00000004L
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS_MASK                                              0x00000008L
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS_MASK                                              0x00000010L
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA_MASK                                          0x00000020L
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA_MASK                                        0x00000040L
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS_MASK                                   0x00000100L
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS_MASK                                          0x00000200L
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN_MASK                                     0x00000C00L
+#define RCC_STRAP0_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2_MASK                                                   0x00002000L
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK                                               0x00004000L
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN_MASK                                   0x00008000L
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE_MASK                                           0x00FF0000L
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS_MASK                                          0x01000000L
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_ARI_EN_UP_MASK                                                       0x02000000L
+#define RCC_STRAP0_RCC_BIF_STRAP2__STRAP_VLINK_PMETO_LDN_EXIT_BY_LNKRST_DIS_MASK                              0x80000000L
+//RCC_STRAP0_RCC_BIF_STRAP3
+#define RCC_STRAP0_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT                                         0x0
+#define RCC_STRAP0_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT                                       0x10
+#define RCC_STRAP0_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK                                           0x0000FFFFL
+#define RCC_STRAP0_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK                                         0xFFFF0000L
+//RCC_STRAP0_RCC_BIF_STRAP4
+#define RCC_STRAP0_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER__SHIFT                                          0x0
+#define RCC_STRAP0_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER__SHIFT                                           0x10
+#define RCC_STRAP0_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER_MASK                                            0x0000FFFFL
+#define RCC_STRAP0_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER_MASK                                             0xFFFF0000L
+//RCC_STRAP0_RCC_BIF_STRAP5
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT                                         0x0
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN__SHIFT                                      0x10
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN__SHIFT                                   0x11
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS__SHIFT                                    0x12
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS__SHIFT                                        0x13
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS__SHIFT                                    0x14
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_REG_PROTECTION_DIS__SHIFT                                            0x15
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE__SHIFT                                         0x16
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE__SHIFT                          0x18
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                0x19
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                 0x1b
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER__SHIFT                                           0x1c
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_BIF_GFX_REG_APER_REMAPPING_EN__SHIFT                                 0x1f
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK                                           0x0000FFFFL
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN_MASK                                        0x00010000L
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN_MASK                                     0x00020000L
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS_MASK                                      0x00040000L
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS_MASK                                          0x00080000L
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS_MASK                                      0x00100000L
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_REG_PROTECTION_DIS_MASK                                              0x00200000L
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE_MASK                                           0x00C00000L
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE_MASK                            0x01000000L
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED_MASK                                  0x06000000L
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ_MASK                                   0x08000000L
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER_MASK                                             0x70000000L
+#define RCC_STRAP0_RCC_BIF_STRAP5__STRAP_BIF_GFX_REG_APER_REMAPPING_EN_MASK                                   0x80000000L
+//RCC_STRAP0_RCC_BIF_STRAP6
+#define RCC_STRAP0_RCC_BIF_STRAP6__STRAP_GEN5_DIS__SHIFT                                                      0x0
+#define RCC_STRAP0_RCC_BIF_STRAP6__STRAP_BIF_KILL_GEN5__SHIFT                                                 0x1
+#define RCC_STRAP0_RCC_BIF_STRAP6__STRAP_PHY_32GT_EN__SHIFT                                                   0x2
+#define RCC_STRAP0_RCC_BIF_STRAP6__STRAP_DOE_VERSION_SEL__SHIFT                                               0x3
+#define RCC_STRAP0_RCC_BIF_STRAP6__STRAP_PRODUCTION_MODE__SHIFT                                               0x5
+#define RCC_STRAP0_RCC_BIF_STRAP6__STRAP_MEM_AP_SIZE_PIN__SHIFT                                               0xa
+#define RCC_STRAP0_RCC_BIF_STRAP6__RESERVED_BIF_STRAP6__SHIFT                                                 0xf
+#define RCC_STRAP0_RCC_BIF_STRAP6__STRAP_GEN5_DIS_MASK                                                        0x00000001L
+#define RCC_STRAP0_RCC_BIF_STRAP6__STRAP_BIF_KILL_GEN5_MASK                                                   0x00000002L
+#define RCC_STRAP0_RCC_BIF_STRAP6__STRAP_PHY_32GT_EN_MASK                                                     0x00000004L
+#define RCC_STRAP0_RCC_BIF_STRAP6__STRAP_DOE_VERSION_SEL_MASK                                                 0x00000008L
+#define RCC_STRAP0_RCC_BIF_STRAP6__STRAP_PRODUCTION_MODE_MASK                                                 0x00000020L
+#define RCC_STRAP0_RCC_BIF_STRAP6__STRAP_MEM_AP_SIZE_PIN_MASK                                                 0x00007C00L
+#define RCC_STRAP0_RCC_BIF_STRAP6__RESERVED_BIF_STRAP6_MASK                                                   0xFFFF8000L
+//RCC_STRAP0_RCC_BIF_STRAP7
+#define RCC_STRAP0_RCC_BIF_STRAP7__STRAP_GEN6_DIS__SHIFT                                                      0x19
+#define RCC_STRAP0_RCC_BIF_STRAP7__STRAP_BIF_KILL_GEN6__SHIFT                                                 0x1a
+#define RCC_STRAP0_RCC_BIF_STRAP7__STRAP_GEN6_DIS_MASK                                                        0x02000000L
+#define RCC_STRAP0_RCC_BIF_STRAP7__STRAP_BIF_KILL_GEN6_MASK                                                   0x04000000L
+//RCC_STRAP0_RCC_BIF_STRAP8
+//RCC_STRAP0_RCC_BIF_STRAP9
+//RCC_STRAP0_RCC_DEV0_PORT_STRAP0
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0__SHIFT                                       0x0
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0__SHIFT                                          0x10
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0__SHIFT                                          0x11
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0__SHIFT                                          0x12
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0__SHIFT                                0x13
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_NEGO_GLOBAL_EN_DEV0__SHIFT                                     0x14
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0__SHIFT                                   0x15
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0__SHIFT                            0x18
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0__SHIFT                             0x19
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0__SHIFT                             0x1c
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0__SHIFT                                      0x1f
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0_MASK                                         0x0000FFFFL
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0_MASK                                            0x00010000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0_MASK                                            0x00020000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0_MASK                                            0x00040000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0_MASK                                  0x00080000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_NEGO_GLOBAL_EN_DEV0_MASK                                       0x00100000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0_MASK                                     0x00E00000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0_MASK                              0x01000000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0_MASK                               0x0E000000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0_MASK                               0x70000000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0_MASK                                        0x80000000L
+//RCC_STRAP0_RCC_DEV0_PORT_STRAP1
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0__SHIFT                                       0x0
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0__SHIFT                                   0x10
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0_MASK                                         0x0000FFFFL
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0_MASK                                     0xFFFF0000L
+//RCC_STRAP0_RCC_DEV0_PORT_STRAP10
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DEV0__SHIFT                              0x0
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DN_DEV0__SHIFT                           0x1
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE1_SUPPORTED_DEV0__SHIFT                  0x2
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE2_SUPPORTED_DEV0__SHIFT                  0x3
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODEING_ON_DEV0__SHIFT                         0x4
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODE_REQUEST_DEV0__SHIFT                       0x5
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_MODIFIED_TS_INFOR1_DEV0__SHIFT                                0x6
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_GEN6_COMPLIANCE_DEV0__SHIFT                                   0x14
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_MAX_E2E_TLP_PREFIXES_DEV0__SHIFT                              0x18
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_MAX_E2E_TLP_PREFIXES_DN_DEV0__SHIFT                           0x1a
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DEV0_MASK                                0x00000001L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DN_DEV0_MASK                             0x00000002L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE1_SUPPORTED_DEV0_MASK                    0x00000004L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE2_SUPPORTED_DEV0_MASK                    0x00000008L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODEING_ON_DEV0_MASK                           0x00000010L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODE_REQUEST_DEV0_MASK                         0x00000020L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_MODIFIED_TS_INFOR1_DEV0_MASK                                  0x0007FFC0L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_GEN6_COMPLIANCE_DEV0_MASK                                     0x00100000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_MAX_E2E_TLP_PREFIXES_DEV0_MASK                                0x03000000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP10__STRAP_MAX_E2E_TLP_PREFIXES_DN_DEV0_MASK                             0x0C000000L
+//RCC_STRAP0_RCC_DEV0_PORT_STRAP11
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_MODIFIED_TS_VENDOR_ID_DEV0__SHIFT                             0x0
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_RTR_RESET_TIME_DN_DEV0__SHIFT                                 0x10
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_RTR_VALID_DN_DEV0__SHIFT                                      0x1c
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_RTR_EN_DN_DEV0__SHIFT                                         0x1d
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_SDPVW_REG_UPDATE_EN_DEV0__SHIFT                               0x1e
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_VF_14BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT                  0x1f
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_MODIFIED_TS_VENDOR_ID_DEV0_MASK                               0x0000FFFFL
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_RTR_RESET_TIME_DN_DEV0_MASK                                   0x0FFF0000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_RTR_VALID_DN_DEV0_MASK                                        0x10000000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_RTR_EN_DN_DEV0_MASK                                           0x20000000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_SDPVW_REG_UPDATE_EN_DEV0_MASK                                 0x40000000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP11__STRAP_VF_14BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK                    0x80000000L
+//RCC_STRAP0_RCC_DEV0_PORT_STRAP12
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP12__STRAP_MODIFIED_TS_INFOR2_DEV0__SHIFT                                0x0
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP12__STRAP_14BIT_TAG_COMPLETER_SUPPORTED_DEV0__SHIFT                     0x18
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP12__STRAP_14BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT                     0x19
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP12__STRAP_RECEIVER_L0P_SUPPORTED_DEV0__SHIFT                            0x1a
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP12__STRAP_PORT_L0P_EXIT_LATENCY_DEV0__SHIFT                             0x1b
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP12__STRAP_MODIFIED_TS_INFOR2_DEV0_MASK                                  0x00FFFFFFL
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP12__STRAP_14BIT_TAG_COMPLETER_SUPPORTED_DEV0_MASK                       0x01000000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP12__STRAP_14BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK                       0x02000000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP12__STRAP_RECEIVER_L0P_SUPPORTED_DEV0_MASK                              0x04000000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP12__STRAP_PORT_L0P_EXIT_LATENCY_DEV0_MASK                               0x38000000L
+//RCC_STRAP0_RCC_DEV0_PORT_STRAP13
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_COUNT_DEV0__SHIFT                          0x0
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_SELECTIVE_ENABLE_SUPPORTED_DEV0__SHIFT     0x8
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_DETAILS_DEV0__SHIFT                        0x9
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP13__STRAP_RTR_D3HOTD0_TIME_DN_DEV0__SHIFT                               0x14
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_COUNT_DEV0_MASK                            0x000000FFL
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_SELECTIVE_ENABLE_SUPPORTED_DEV0_MASK       0x00000100L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_DETAILS_DEV0_MASK                          0x000FFE00L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP13__STRAP_RTR_D3HOTD0_TIME_DN_DEV0_MASK                                 0xFFF00000L
+//RCC_STRAP0_RCC_DEV0_PORT_STRAP14
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_CTO_LOGGING_SUPPORT_DEV0__SHIFT                               0x0
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_ACS_ENH_CAPABILITY_DN_DEV0__SHIFT                             0x1
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_COMMAND_COMPLETED_DEV0__SHIFT                                 0x2
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_ERR_COR_SUBCLASS_CAPABLE_DEV0__SHIFT                          0x3
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_DOE_EN_UP_DEV0__SHIFT                                         0x4
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_RX_MPS_FIXED_DEV0__SHIFT                                      0x5
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_RX_MPS_FIXED_DN_DEV0__SHIFT                                   0x6
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_IDE_EN_DEV0__SHIFT                                            0x7
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_RETIMER_L0P_EXIT_LATENCY_DEV0__SHIFT                          0x9
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_DEVICE3_EN_DN_DEV0__SHIFT                                     0xc
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_IDE_EN_DN_DEV0__SHIFT                                         0xd
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_CTO_LOGGING_SUPPORT_DEV0_MASK                                 0x00000001L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_ACS_ENH_CAPABILITY_DN_DEV0_MASK                               0x00000002L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_COMMAND_COMPLETED_DEV0_MASK                                   0x00000004L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_ERR_COR_SUBCLASS_CAPABLE_DEV0_MASK                            0x00000008L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_DOE_EN_UP_DEV0_MASK                                           0x00000010L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_RX_MPS_FIXED_DEV0_MASK                                        0x00000020L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_RX_MPS_FIXED_DN_DEV0_MASK                                     0x00000040L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_IDE_EN_DEV0_MASK                                              0x00000080L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_RETIMER_L0P_EXIT_LATENCY_DEV0_MASK                            0x00000E00L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_DEVICE3_EN_DN_DEV0_MASK                                       0x00001000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP14__STRAP_IDE_EN_DN_DEV0_MASK                                           0x00002000L
+//RCC_STRAP0_RCC_DEV0_PORT_STRAP15
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP15__STRAP_DSN_CODE_L_DN_DEV0__SHIFT                                     0x0
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP15__STRAP_DSN_CODE_L_DN_DEV0_MASK                                       0xFFFFFFFFL
+//RCC_STRAP0_RCC_DEV0_PORT_STRAP16
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP16__STRAP_DSN_CODE_H_DN_DEV0__SHIFT                                     0x0
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP16__STRAP_DSN_CODE_H_DN_DEV0_MASK                                       0xFFFFFFFFL
+//RCC_STRAP0_RCC_DEV0_PORT_STRAP17
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP17__STRAP_LINK_IDE_STREAM_SUPPORTED_DEV0__SHIFT                         0x0
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP17__STRAP_SELECTIVE_IDE_STREAM_SUPPORTED_DEV0__SHIFT                    0x1
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP17__STRAP_FLOW_THROUGH_IDE_STREAM_SUPPORTED_DEV0__SHIFT                 0x2
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP17__STRAP_PARTIAL_HDR_ENCRYPTION_SUPPORTED_DEV0__SHIFT                  0x3
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP17__STRAP_AGGREGATION_SUPPORTED_DEV0__SHIFT                             0x4
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP17__STRAP_PCRC_SUPPORTED_DEV0__SHIFT                                    0x5
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP17__STRAP_IDE_KM_PROTOCOL_SUPPORTED_DEV0__SHIFT                         0x6
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP17__STRAP_SELECTIVE_IDE_FOR_CFG_REQ_SUPPORTED_DEV0__SHIFT               0x7
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP17__STRAP_NUM_OF_TCS_SUPPORTED_FOR_LINK_IDE_DEV0__SHIFT                 0xd
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP17__STRAP_NUM_OF_SELECTIVE_IDE_STREAMS_SUPPORTED_DEV0__SHIFT            0x10
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP17__STRAP_TEE_LIMITED_SUPPORTED_DEV0__SHIFT                             0x18
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP17__STRAP_XT_SUPPORTED_DEV0__SHIFT                                      0x19
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP17__STRAP_LINK_IDE_STREAM_SUPPORTED_DEV0_MASK                           0x00000001L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP17__STRAP_SELECTIVE_IDE_STREAM_SUPPORTED_DEV0_MASK                      0x00000002L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP17__STRAP_FLOW_THROUGH_IDE_STREAM_SUPPORTED_DEV0_MASK                   0x00000004L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP17__STRAP_PARTIAL_HDR_ENCRYPTION_SUPPORTED_DEV0_MASK                    0x00000008L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP17__STRAP_AGGREGATION_SUPPORTED_DEV0_MASK                               0x00000010L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP17__STRAP_PCRC_SUPPORTED_DEV0_MASK                                      0x00000020L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP17__STRAP_IDE_KM_PROTOCOL_SUPPORTED_DEV0_MASK                           0x00000040L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP17__STRAP_SELECTIVE_IDE_FOR_CFG_REQ_SUPPORTED_DEV0_MASK                 0x00000080L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP17__STRAP_NUM_OF_TCS_SUPPORTED_FOR_LINK_IDE_DEV0_MASK                   0x0000E000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP17__STRAP_NUM_OF_SELECTIVE_IDE_STREAMS_SUPPORTED_DEV0_MASK              0x00FF0000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP17__STRAP_TEE_LIMITED_SUPPORTED_DEV0_MASK                               0x01000000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP17__STRAP_XT_SUPPORTED_DEV0_MASK                                        0x02000000L
+//RCC_STRAP0_RCC_DEV0_PORT_STRAP18
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP18__STRAP_NUM_ADDR_ASSOCIATION_REG_BLKS_DEV0__SHIFT                     0x0
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP18__STRAP_NUM_ADDR_ASSOCIATION_REG_BLKS_DEV0_MASK                       0x0000000FL
+//RCC_STRAP0_RCC_DEV0_PORT_STRAP2
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0__SHIFT                                 0x0
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0__SHIFT                                          0x1
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0__SHIFT                                      0x2
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0__SHIFT                                          0x3
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0__SHIFT                                      0x4
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0__SHIFT                                        0x5
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0__SHIFT                             0x7
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0__SHIFT                                0x8
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0__SHIFT                                    0x9
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0__SHIFT                              0xc
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0__SHIFT                      0xd
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0__SHIFT                                    0xe
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0__SHIFT                                            0xf
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0__SHIFT                                    0x10
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0__SHIFT                                    0x11
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0__SHIFT                             0x14
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0__SHIFT                                   0x17
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0__SHIFT                              0x1a
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0__SHIFT                                    0x1d
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0_MASK                                   0x00000001L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0_MASK                                            0x00000002L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0_MASK                                        0x00000004L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0_MASK                                            0x00000008L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0_MASK                                        0x00000010L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0_MASK                                          0x00000020L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0_MASK                               0x00000080L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0_MASK                                  0x00000100L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0_MASK                                      0x00000E00L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0_MASK                                0x00001000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0_MASK                        0x00002000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0_MASK                                      0x00004000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0_MASK                                              0x00008000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0_MASK                                      0x00010000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0_MASK                                      0x00020000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0_MASK                               0x00700000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0_MASK                                     0x03800000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0_MASK                                0x1C000000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0_MASK                                      0xE0000000L
+//RCC_STRAP0_RCC_DEV0_PORT_STRAP3
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0__SHIFT                     0x0
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0__SHIFT                                             0x1
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0__SHIFT                                          0x2
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0__SHIFT                                0x3
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0__SHIFT                                          0x6
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0__SHIFT                                  0x7
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0__SHIFT                                   0x8
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0__SHIFT                                     0x9
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT  0xb
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0__SHIFT  0xe
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT  0x12
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0__SHIFT  0x15
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0__SHIFT                                         0x19
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0__SHIFT                                      0x1b
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0__SHIFT                                       0x1d
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0__SHIFT                                         0x1f
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0_MASK                       0x00000001L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0_MASK                                               0x00000002L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0_MASK                                            0x00000004L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0_MASK                                  0x00000038L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0_MASK                                            0x00000040L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0_MASK                                    0x00000080L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0_MASK                                     0x00000100L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0_MASK                                       0x00000600L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK  0x00003800L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0_MASK  0x0003C000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK  0x001C0000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0_MASK  0x01E00000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0_MASK                                           0x06000000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0_MASK                                        0x18000000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0_MASK                                         0x20000000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0_MASK                                           0x80000000L
+//RCC_STRAP0_RCC_DEV0_PORT_STRAP4
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0__SHIFT                              0x0
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0__SHIFT                              0x8
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0__SHIFT                              0x10
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0__SHIFT                              0x18
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0_MASK                                0x000000FFL
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0_MASK                                0x0000FF00L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0_MASK                                0x00FF0000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0_MASK                                0xFF000000L
+//RCC_STRAP0_RCC_DEV0_PORT_STRAP5
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0__SHIFT                              0x0
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0__SHIFT                              0x8
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0__SHIFT                        0x10
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0__SHIFT                                 0x11
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0__SHIFT                                  0x12
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0__SHIFT                                           0x13
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0__SHIFT                                           0x14
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0__SHIFT                                        0x15
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0__SHIFT                                0x16
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0__SHIFT                           0x17
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0__SHIFT                        0x18
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0__SHIFT                        0x19
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0__SHIFT                     0x1a
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0__SHIFT                         0x1b
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0__SHIFT                          0x1c
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0__SHIFT                       0x1d
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV0__SHIFT                                         0x1e
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0__SHIFT                                            0x1f
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0_MASK                                0x000000FFL
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0_MASK                                0x0000FF00L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0_MASK                          0x00010000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0_MASK                                   0x00020000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0_MASK                                    0x00040000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0_MASK                                             0x00080000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0_MASK                                             0x00100000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0_MASK                                          0x00200000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0_MASK                                  0x00400000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0_MASK                             0x00800000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0_MASK                          0x01000000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0_MASK                          0x02000000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0_MASK                       0x04000000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0_MASK                           0x08000000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0_MASK                            0x10000000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0_MASK                         0x20000000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV0_MASK                                           0x40000000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0_MASK                                              0x80000000L
+//RCC_STRAP0_RCC_DEV0_PORT_STRAP6
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0__SHIFT                                         0x0
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0__SHIFT                         0x1
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV0__SHIFT                                    0x2
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0__SHIFT                          0x3
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0__SHIFT                          0x4
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0__SHIFT                      0x5
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT                      0x6
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT                   0x7
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0__SHIFT     0x8
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0__SHIFT     0xc
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0__SHIFT                              0x10
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV0__SHIFT                            0x12
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV0__SHIFT                     0x13
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_GEN5_COMPLIANCE_DEV0__SHIFT                                    0x14
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_TARGET_LINK_SPEED_DEV0__SHIFT                                  0x15
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0__SHIFT     0x18
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0__SHIFT     0x1c
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0_MASK                                           0x00000001L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0_MASK                           0x00000002L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV0_MASK                                      0x00000004L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0_MASK                            0x00000008L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0_MASK                            0x00000010L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0_MASK                        0x00000020L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK                        0x00000040L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK                     0x00000080L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0_MASK       0x00000F00L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0_MASK       0x0000F000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0_MASK                                0x00030000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV0_MASK                              0x00040000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV0_MASK                       0x00080000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_GEN5_COMPLIANCE_DEV0_MASK                                      0x00100000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_TARGET_LINK_SPEED_DEV0_MASK                                    0x00E00000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0_MASK       0x0F000000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0_MASK       0xF0000000L
+//RCC_STRAP0_RCC_DEV0_PORT_STRAP7
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0__SHIFT                                        0x0
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0__SHIFT                                    0x8
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0__SHIFT                                    0xc
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0__SHIFT                                          0x10
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0__SHIFT                                          0x18
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0__SHIFT                                          0x1d
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0_MASK                                          0x000000FFL
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0_MASK                                      0x00000F00L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0_MASK                                      0x0000F000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0_MASK                                            0x00FF0000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0_MASK                                            0x1F000000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0_MASK                                            0xE0000000L
+//RCC_STRAP0_RCC_DEV0_PORT_STRAP8
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0__SHIFT                              0x0
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0__SHIFT                              0x8
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0__SHIFT                              0x10
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0__SHIFT                              0x18
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0_MASK                                0x000000FFL
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0_MASK                                0x0000FF00L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0_MASK                                0x00FF0000L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0_MASK                                0xFF000000L
+//RCC_STRAP0_RCC_DEV0_PORT_STRAP9
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0__SHIFT                              0x0
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0__SHIFT                              0x8
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV0__SHIFT                                       0x10
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0_MASK                                0x000000FFL
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0_MASK                                0x0000FF00L
+#define RCC_STRAP0_RCC_DEV0_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV0_MASK                                         0xFFFF0000L
+//RCC_STRAP0_RCC_DEV0_EPF0_STRAP0
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT                                       0x0
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT                                    0x10
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__SHIFT                                    0x14
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT                                      0x18
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__SHIFT                                         0x1c
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__SHIFT                           0x1d
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__SHIFT                                      0x1e
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__SHIFT                                      0x1f
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0_MASK                                         0x0000FFFFL
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0_MASK                                      0x000F0000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0_MASK                                      0x00F00000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK                                        0x0F000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0_MASK                                           0x10000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0_MASK                             0x20000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0_MASK                                        0x40000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0_MASK                                        0x80000000L
+//RCC_STRAP0_RCC_DEV0_EPF0_STRAP1
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0__SHIFT                              0x0
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0__SHIFT                       0x10
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0_MASK                                0x0000FFFFL
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0_MASK                         0xFFFF0000L
+//RCC_STRAP0_RCC_DEV0_EPF0_STRAP13
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0__SHIFT                                 0x0
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0__SHIFT                                 0x8
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0__SHIFT                                0x10
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_SRIOV_TOTAL_VFS_DEV0_F0__SHIFT                                0x18
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0_MASK                                   0x000000FFL
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0_MASK                                   0x0000FF00L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0_MASK                                  0x00FF0000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP13__STRAP_SRIOV_TOTAL_VFS_DEV0_F0_MASK                                  0xFF000000L
+//RCC_STRAP0_RCC_DEV0_EPF0_STRAP14
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP14__STRAP_VENDOR_ID_DEV0_F0__SHIFT                                      0x0
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP14__STRAP_VENDOR_ID_DEV0_F0_MASK                                        0x0000FFFFL
+//RCC_STRAP0_RCC_DEV0_EPF0_STRAP15
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F0__SHIFT                                 0x0
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F0__SHIFT                                  0xc
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_VALID_DEV0_F0__SHIFT                                      0x18
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_INVALIDATE_QUEUE_DEPTH_DEV0_F0__SHIFT                     0x19
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_PAGE_ALIGNED_REQUEST_DEV0_F0__SHIFT                       0x1e
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F0_MASK                                   0x00000FFFL
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F0_MASK                                    0x00FFF000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_VALID_DEV0_F0_MASK                                        0x01000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_INVALIDATE_QUEUE_DEPTH_DEV0_F0_MASK                       0x3E000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_PAGE_ALIGNED_REQUEST_DEV0_F0_MASK                         0x40000000L
+//RCC_STRAP0_RCC_DEV0_EPF0_STRAP16
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F0__SHIFT                                   0x0
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F0__SHIFT                               0xc
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F0_MASK                                     0x00000FFFL
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F0_MASK                                 0x00FFF000L
+//RCC_STRAP0_RCC_DEV0_EPF0_STRAP17
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F0__SHIFT                              0x0
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_VALID_DEV0_F0__SHIFT                                   0xc
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F0__SHIFT                                0xd
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F0_MASK                                0x00000FFFL
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_VALID_DEV0_F0_MASK                                     0x00001000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F0_MASK                                  0x01FFE000L
+//RCC_STRAP0_RCC_DEV0_EPF0_STRAP18
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F0__SHIFT                            0x0
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP18__STRAP_SRIOV_FUNC_DEP_LINK_DEV0_F0__SHIFT                            0xc
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F0_MASK                              0x00000FFFL
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP18__STRAP_SRIOV_FUNC_DEP_LINK_DEV0_F0_MASK                              0x000FF000L
+//RCC_STRAP0_RCC_DEV0_EPF0_STRAP19
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP19__STRAP_SRIOV_FIRST_VF_OFFSET_DEV0_F0__SHIFT                          0x0
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP19__STRAP_SRIOV_VF_STRIDE_DEV0_F0__SHIFT                                0x10
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP19__STRAP_SRIOV_FIRST_VF_OFFSET_DEV0_F0_MASK                            0x0000FFFFL
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP19__STRAP_SRIOV_VF_STRIDE_DEV0_F0_MASK                                  0xFFFF0000L
+//RCC_STRAP0_RCC_DEV0_EPF0_STRAP2
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0__SHIFT                                        0x0
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_RELAXED_ORDERING_SUPPORTED_DEV0_F0__SHIFT                      0x1
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_CAP_HIERARCHY_PRESERVED_DEV0_F0__SHIFT                     0x2
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_DEVICE3_EN_DEV0_F0__SHIFT                                      0x3
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_TEE_EXCLUSIVE_ATTR_SUPPORTED_DEV0_F0__SHIFT                    0x4
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0__SHIFT                                       0x6
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0__SHIFT                                   0x7
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0__SHIFT                                   0x8
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0__SHIFT                                 0x9
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0__SHIFT                          0xe
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0__SHIFT                                          0xf
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0__SHIFT                                          0x10
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0__SHIFT                                          0x11
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0__SHIFT                                          0x12
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0__SHIFT                                0x14
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0__SHIFT                                          0x15
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0__SHIFT                                          0x16
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0__SHIFT                                           0x17
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0__SHIFT                                   0x18
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0__SHIFT                                     0x1b
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0__SHIFT                                        0x1c
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0__SHIFT                  0x1d
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0__SHIFT               0x1e
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0__SHIFT                       0x1f
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0_MASK                                          0x00000001L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_RELAXED_ORDERING_SUPPORTED_DEV0_F0_MASK                        0x00000002L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_CAP_HIERARCHY_PRESERVED_DEV0_F0_MASK                       0x00000004L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_DEVICE3_EN_DEV0_F0_MASK                                        0x00000008L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_TEE_EXCLUSIVE_ATTR_SUPPORTED_DEV0_F0_MASK                      0x00000010L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0_MASK                                         0x00000040L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0_MASK                                     0x00000080L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0_MASK                                     0x00000100L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0_MASK                                   0x00003E00L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0_MASK                            0x00004000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0_MASK                                            0x00008000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0_MASK                                            0x00010000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0_MASK                                            0x00020000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0_MASK                                            0x00040000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0_MASK                                  0x00100000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0_MASK                                            0x00200000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0_MASK                                            0x00400000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0_MASK                                             0x00800000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0_MASK                                     0x07000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0_MASK                                       0x08000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0_MASK                                          0x10000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0_MASK                    0x20000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0_MASK                 0x40000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0_MASK                         0x80000000L
+//RCC_STRAP0_RCC_DEV0_EPF0_STRAP22
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP22__STRAP_GPUIOV_VSEC_LENGTH_DEV0_F0__SHIFT                             0x0
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP22__STRAP_MEM_AP_SIZE_DEV0_F0__SHIFT                                    0xc
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP22__STRAP_VF_MEM_AP_SIZE_DEV0_F0__SHIFT                                 0x11
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP22__STRAP_PF_RESIZABLE_BAR_DEFAULT_SIZE_DEV0_F0__SHIFT                  0x16
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP22__STRAP_VF_RESIZABLE_BAR_DEFAULT_SIZE_DEV0_F0__SHIFT                  0x1b
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP22__STRAP_GPUIOV_VSEC_LENGTH_DEV0_F0_MASK                               0x00000FFFL
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP22__STRAP_MEM_AP_SIZE_DEV0_F0_MASK                                      0x0001F000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP22__STRAP_VF_MEM_AP_SIZE_DEV0_F0_MASK                                   0x003E0000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP22__STRAP_PF_RESIZABLE_BAR_DEFAULT_SIZE_DEV0_F0_MASK                    0x07C00000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP22__STRAP_VF_RESIZABLE_BAR_DEFAULT_SIZE_DEV0_F0_MASK                    0xF8000000L
+//RCC_STRAP0_RCC_DEV0_EPF0_STRAP23
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP23__STRAP_DSN_CODE_L_DEV0_F0__SHIFT                                     0x0
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP23__STRAP_DSN_CODE_L_DEV0_F0_MASK                                       0xFFFFFFFFL
+//RCC_STRAP0_RCC_DEV0_EPF0_STRAP24
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP24__STRAP_DSN_CODE_H_DEV0_F0__SHIFT                                     0x0
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP24__STRAP_DSN_CODE_H_DEV0_F0_MASK                                       0xFFFFFFFFL
+//RCC_STRAP0_RCC_DEV0_EPF0_STRAP3
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0__SHIFT                                       0x0
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0__SHIFT                      0x10
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0__SHIFT                                          0x11
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0__SHIFT                                          0x12
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0__SHIFT                              0x13
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0__SHIFT                                         0x14
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0__SHIFT                                  0x15
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0__SHIFT                                         0x18
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_TRANSLATED_REQ_WITH_PASID_SUPPORTED_DEV0_F0__SHIFT             0x19
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0__SHIFT                        0x1a
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0__SHIFT                       0x1b
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0__SHIFT                                0x1c
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV0_F0__SHIFT                                       0x1d
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F0__SHIFT                               0x1e
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_RTR_EN_DEV0_F0__SHIFT                                          0x1f
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0_MASK                                         0x0000FFFFL
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0_MASK                        0x00010000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0_MASK                                            0x00020000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0_MASK                                            0x00040000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0_MASK                                0x00080000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0_MASK                                           0x00100000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0_MASK                                    0x00E00000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0_MASK                                           0x01000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_TRANSLATED_REQ_WITH_PASID_SUPPORTED_DEV0_F0_MASK               0x02000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0_MASK                          0x04000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0_MASK                         0x08000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0_MASK                                  0x10000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV0_F0_MASK                                         0x20000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F0_MASK                                 0x40000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP3__STRAP_RTR_EN_DEV0_F0_MASK                                            0x80000000L
+//RCC_STRAP0_RCC_DEV0_EPF0_STRAP4
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0__SHIFT                                 0x0
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_DOE_EN_DEV0_F0__SHIFT                                          0x12
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0__SHIFT                                 0x14
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0__SHIFT                                       0x15
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0__SHIFT                                          0x16
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0__SHIFT                                     0x17
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0__SHIFT                                   0x1c
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F0__SHIFT                                  0x1f
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0_MASK                                   0x000003FFL
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_DOE_EN_DEV0_F0_MASK                                            0x00040000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0_MASK                                   0x00100000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0_MASK                                         0x00200000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0_MASK                                            0x00400000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0_MASK                                       0x0F800000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0_MASK                                     0x70000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F0_MASK                                    0x80000000L
+//RCC_STRAP0_RCC_DEV0_EPF0_STRAP5
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0__SHIFT                                   0x0
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP5__STRAP_AUX_CURRENT_DEV0_F0__SHIFT                                     0x1b
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F0__SHIFT                            0x1e
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0_MASK                                     0x0000FFFFL
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP5__STRAP_AUX_CURRENT_DEV0_F0_MASK                                       0x38000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F0_MASK                              0x40000000L
+//RCC_STRAP0_RCC_DEV0_EPF0_STRAP8
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0__SHIFT                              0x0
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0__SHIFT                                0x3
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0__SHIFT                                     0x4
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0__SHIFT                                      0x7
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0__SHIFT                                   0x8
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0__SHIFT                                     0xd
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0__SHIFT                           0x10
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0__SHIFT                                  0x17
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0__SHIFT                                0x1b
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0__SHIFT                           0x1e
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0_MASK                                0x00000007L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0_MASK                                  0x00000008L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0_MASK                                       0x00000070L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0_MASK                                        0x00000080L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0_MASK                                     0x00000100L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0_MASK                                       0x0000E000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0_MASK                             0x00070000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0_MASK                                    0x03800000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0_MASK                                  0x38000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0_MASK                             0xC0000000L
+//RCC_STRAP0_RCC_DEV0_EPF0_STRAP9
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0__SHIFT                           0x0
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0__SHIFT                               0x12
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0__SHIFT                        0x13
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0__SHIFT                                 0x14
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_FB_ALWAYS_ON_DEV0_F0__SHIFT                                    0x15
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_FB_CPL_TYPE_SEL_DEV0_F0__SHIFT                                 0x16
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_GPUIOV_VSEC_REV_DEV0_F0__SHIFT                                 0x18
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_TEE_IO_SUPPORT_DEV0_F0__SHIFT                                  0x1c
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0_MASK                             0x0000FFFFL
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0_MASK                                 0x00040000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0_MASK                          0x00080000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0_MASK                                   0x00100000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_FB_ALWAYS_ON_DEV0_F0_MASK                                      0x00200000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_FB_CPL_TYPE_SEL_DEV0_F0_MASK                                   0x00C00000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_GPUIOV_VSEC_REV_DEV0_F0_MASK                                   0x0F000000L
+#define RCC_STRAP0_RCC_DEV0_EPF0_STRAP9__STRAP_TEE_IO_SUPPORT_DEV0_F0_MASK                                    0x10000000L
+//RCC_STRAP0_RCC_DEV0_EPF1_STRAP0
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1__SHIFT                                       0x0
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1__SHIFT                                    0x10
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1__SHIFT                                    0x14
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1__SHIFT                                         0x1c
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1__SHIFT                           0x1d
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1__SHIFT                                      0x1e
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1__SHIFT                                      0x1f
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1_MASK                                         0x0000FFFFL
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1_MASK                                      0x000F0000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1_MASK                                      0x00F00000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1_MASK                                           0x10000000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1_MASK                             0x20000000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1_MASK                                        0x40000000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1_MASK                                        0x80000000L
+//RCC_STRAP0_RCC_DEV0_EPF1_STRAP1
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F1__SHIFT                              0x0
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F1__SHIFT                       0x10
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F1_MASK                                0x0000FFFFL
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F1_MASK                         0xFFFF0000L
+//RCC_STRAP0_RCC_DEV0_EPF1_STRAP10
+//RCC_STRAP0_RCC_DEV0_EPF1_STRAP11
+//RCC_STRAP0_RCC_DEV0_EPF1_STRAP12
+//RCC_STRAP0_RCC_DEV0_EPF1_STRAP13
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F1__SHIFT                                 0x0
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F1__SHIFT                                 0x8
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F1__SHIFT                                0x10
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP13__STRAP_SRIOV_TOTAL_VFS_DEV0_F1__SHIFT                                0x18
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F1_MASK                                   0x000000FFL
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F1_MASK                                   0x0000FF00L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F1_MASK                                  0x00FF0000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP13__STRAP_SRIOV_TOTAL_VFS_DEV0_F1_MASK                                  0xFF000000L
+//RCC_STRAP0_RCC_DEV0_EPF1_STRAP14
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP14__STRAP_VENDOR_ID_DEV0_F1__SHIFT                                      0x0
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP14__STRAP_VENDOR_ID_DEV0_F1_MASK                                        0x0000FFFFL
+//RCC_STRAP0_RCC_DEV0_EPF1_STRAP15
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F1__SHIFT                                 0x0
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F1__SHIFT                                  0xc
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP15__STRAP_RTR_VALID_DEV0_F1__SHIFT                                      0x18
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F1_MASK                                   0x00000FFFL
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F1_MASK                                    0x00FFF000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP15__STRAP_RTR_VALID_DEV0_F1_MASK                                        0x01000000L
+//RCC_STRAP0_RCC_DEV0_EPF1_STRAP16
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F1__SHIFT                                   0x0
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F1__SHIFT                               0xc
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F1_MASK                                     0x00000FFFL
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F1_MASK                                 0x00FFF000L
+//RCC_STRAP0_RCC_DEV0_EPF1_STRAP17
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F1__SHIFT                              0x0
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP17__STRAP_RTR_VF_VALID_DEV0_F1__SHIFT                                   0xc
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F1__SHIFT                                0xd
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F1_MASK                                0x00000FFFL
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP17__STRAP_RTR_VF_VALID_DEV0_F1_MASK                                     0x00001000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F1_MASK                                  0x01FFE000L
+//RCC_STRAP0_RCC_DEV0_EPF1_STRAP18
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F1__SHIFT                            0x0
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP18__STRAP_SRIOV_FUNC_DEP_LINK_DEV0_F1__SHIFT                            0xc
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F1_MASK                              0x00000FFFL
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP18__STRAP_SRIOV_FUNC_DEP_LINK_DEV0_F1_MASK                              0x000FF000L
+//RCC_STRAP0_RCC_DEV0_EPF1_STRAP19
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP19__STRAP_SRIOV_FIRST_VF_OFFSET_DEV0_F1__SHIFT                          0x0
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP19__STRAP_SRIOV_VF_STRIDE_DEV0_F1__SHIFT                                0x10
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP19__STRAP_SRIOV_FIRST_VF_OFFSET_DEV0_F1_MASK                            0x0000FFFFL
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP19__STRAP_SRIOV_VF_STRIDE_DEV0_F1_MASK                                  0xFFFF0000L
+//RCC_STRAP0_RCC_DEV0_EPF1_STRAP2
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_SRIOV_EN_DEV0_F1__SHIFT                                        0x0
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_ARI_CAP_HIERARCHY_PRESERVED_DEV0_F1__SHIFT                     0x2
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_DEVICE3_EN_DEV0_F1__SHIFT                                      0x3
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_TEE_EXCLUSIVE_ATTR_SUPPORTED_DEV0_F1__SHIFT                    0x4
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1__SHIFT                                   0x7
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1__SHIFT                                   0x8
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1__SHIFT                                 0x9
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1__SHIFT                          0xe
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1__SHIFT                                          0x10
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1__SHIFT                                          0x11
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1__SHIFT                                0x14
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1__SHIFT                                          0x15
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1__SHIFT                                   0x18
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F1__SHIFT                                     0x1b
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1__SHIFT                                        0x1c
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1__SHIFT                  0x1d
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1__SHIFT               0x1e
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1__SHIFT                       0x1f
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_SRIOV_EN_DEV0_F1_MASK                                          0x00000001L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_ARI_CAP_HIERARCHY_PRESERVED_DEV0_F1_MASK                       0x00000004L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_DEVICE3_EN_DEV0_F1_MASK                                        0x00000008L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_TEE_EXCLUSIVE_ATTR_SUPPORTED_DEV0_F1_MASK                      0x00000010L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1_MASK                                     0x00000080L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1_MASK                                     0x00000100L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1_MASK                                   0x00003E00L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1_MASK                            0x00004000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1_MASK                                            0x00010000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1_MASK                                            0x00020000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1_MASK                                  0x00100000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1_MASK                                            0x00200000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1_MASK                                     0x07000000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F1_MASK                                       0x08000000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1_MASK                                          0x10000000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1_MASK                    0x20000000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1_MASK                 0x40000000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1_MASK                         0x80000000L
+//RCC_STRAP0_RCC_DEV0_EPF1_STRAP20
+//RCC_STRAP0_RCC_DEV0_EPF1_STRAP21
+//RCC_STRAP0_RCC_DEV0_EPF1_STRAP23
+//RCC_STRAP0_RCC_DEV0_EPF1_STRAP24
+//RCC_STRAP0_RCC_DEV0_EPF1_STRAP3
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1__SHIFT                                       0x0
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1__SHIFT                      0x10
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1__SHIFT                                          0x11
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1__SHIFT                                          0x12
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1__SHIFT                              0x13
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1__SHIFT                                         0x14
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1__SHIFT                                         0x18
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_TRANSLATED_REQ_WITH_PASID_SUPPORTED_DEV0_F1__SHIFT             0x19
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1__SHIFT                        0x1a
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1__SHIFT                       0x1b
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F1__SHIFT                                0x1c
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV0_F1__SHIFT                                       0x1d
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F1__SHIFT                               0x1e
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_RTR_EN_DEV0_F1__SHIFT                                          0x1f
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1_MASK                                         0x0000FFFFL
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1_MASK                        0x00010000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1_MASK                                            0x00020000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1_MASK                                            0x00040000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1_MASK                                0x00080000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1_MASK                                           0x00100000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1_MASK                                           0x01000000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_TRANSLATED_REQ_WITH_PASID_SUPPORTED_DEV0_F1_MASK               0x02000000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1_MASK                          0x04000000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1_MASK                         0x08000000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F1_MASK                                  0x10000000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV0_F1_MASK                                         0x20000000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F1_MASK                                 0x40000000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP3__STRAP_RTR_EN_DEV0_F1_MASK                                            0x80000000L
+//RCC_STRAP0_RCC_DEV0_EPF1_STRAP4
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1__SHIFT                                 0x14
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1__SHIFT                                       0x15
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1__SHIFT                                          0x16
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1__SHIFT                                     0x17
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1__SHIFT                                   0x1c
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1__SHIFT                                  0x1f
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1_MASK                                   0x00100000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1_MASK                                         0x00200000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1_MASK                                            0x00400000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1_MASK                                       0x0F800000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1_MASK                                     0x70000000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1_MASK                                    0x80000000L
+//RCC_STRAP0_RCC_DEV0_EPF1_STRAP5
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1__SHIFT                                   0x0
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP5__STRAP_AUX_CURRENT_DEV0_F1__SHIFT                                     0x1b
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F1__SHIFT                            0x1e
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1_MASK                                     0x0000FFFFL
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP5__STRAP_AUX_CURRENT_DEV0_F1_MASK                                       0x38000000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F1_MASK                              0x40000000L
+//RCC_STRAP0_RCC_DEV0_EPF1_STRAP6
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1__SHIFT                                        0x0
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F1__SHIFT                           0x1
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1__SHIFT                                  0x2
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_EN_DEV0_F1__SHIFT                                        0x8
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F1__SHIFT                           0x9
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_64BAR_EN_DEV0_F1__SHIFT                                  0xa
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_EN_DEV0_F1__SHIFT                                        0x10
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F1__SHIFT                           0x11
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_64BAR_EN_DEV0_F1__SHIFT                                  0x12
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER3_EN_DEV0_F1__SHIFT                                        0x18
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV0_F1__SHIFT                           0x19
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER4_EN_DEV0_F1__SHIFT                                        0x1a
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER4_PREFETCHABLE_EN_DEV0_F1__SHIFT                           0x1b
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1_MASK                                          0x00000001L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F1_MASK                             0x00000002L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1_MASK                                    0x00000004L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_EN_DEV0_F1_MASK                                          0x00000100L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F1_MASK                             0x00000200L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_64BAR_EN_DEV0_F1_MASK                                    0x00000400L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_EN_DEV0_F1_MASK                                          0x00010000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F1_MASK                             0x00020000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_64BAR_EN_DEV0_F1_MASK                                    0x00040000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER3_EN_DEV0_F1_MASK                                          0x01000000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV0_F1_MASK                             0x02000000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER4_EN_DEV0_F1_MASK                                          0x04000000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP6__STRAP_APER4_PREFETCHABLE_EN_DEV0_F1_MASK                             0x08000000L
+//RCC_STRAP0_RCC_DEV0_EPF1_STRAP7
+//RCC_STRAP0_RCC_DEV0_EPF1_STRAP8
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F1__SHIFT                                0x1b
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F1__SHIFT                           0x1e
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F1_MASK                                  0x38000000L
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F1_MASK                             0xC0000000L
+//RCC_STRAP0_RCC_DEV0_EPF1_STRAP9
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F1__SHIFT                           0x0
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP9__STRAP_TEE_IO_SUPPORT_DEV0_F1__SHIFT                                  0x1c
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F1_MASK                             0x0000FFFFL
+#define RCC_STRAP0_RCC_DEV0_EPF1_STRAP9__STRAP_TEE_IO_SUPPORT_DEV0_F1_MASK                                    0x10000000L
+
+
+// addressBlock: nbif0_nbif0_bif_bx_pf_BIFPFVFDEC1
+//BIF_BX_PF0_BIF_BME_STATUS
+#define BIF_BX_PF0_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT                                                      0x0
+#define BIF_BX_PF0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT                                                0x10
+#define BIF_BX_PF0_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK                                                        0x00000001L
+#define BIF_BX_PF0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK                                                  0x00010000L
+//BIF_BX_PF0_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT                                                0x0
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT                                             0x1
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT                                                0x2
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT                                                    0x3
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT                                          0x10
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT                                       0x11
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT                                          0x12
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT                                              0x13
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK                                                  0x00000001L
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK                                               0x00000002L
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK                                                  0x00000004L
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK                                                      0x00000008L
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK                                            0x00010000L
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK                                         0x00020000L
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK                                            0x00040000L
+#define BIF_BX_PF0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK                                                0x00080000L
+//BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT          0x0
+#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK            0xFFFFFFFFL
+//BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT            0x0
+#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK              0xFFFFFFFFL
+//BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT                      0x0
+#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT                    0x1
+#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT                    0x8
+#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK                        0x00000001L
+#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK                      0x00000002L
+#define BIF_BX_PF0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK                      0x000FFF00L
+//BIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT                                    0x0
+#define BIF_BX_PF0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK                                      0x00000001L
+//BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT                                    0x0
+#define BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK                                      0x00000001L
+//BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL
+#define BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT                          0x0
+#define BIF_BX_PF0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK                            0x00000001L
+//BIF_BX_PF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL
+#define BIF_BX_PF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT                0x0
+#define BIF_BX_PF0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK                  0x00000001L
+//BIF_BX_PF0_GPU_HDP_FLUSH_REQ
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP0__SHIFT                                                              0x0
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP1__SHIFT                                                              0x1
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP2__SHIFT                                                              0x2
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP3__SHIFT                                                              0x3
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP4__SHIFT                                                              0x4
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP5__SHIFT                                                              0x5
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP6__SHIFT                                                              0x6
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP7__SHIFT                                                              0x7
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP8__SHIFT                                                              0x8
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP9__SHIFT                                                              0x9
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT                                                            0xa
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT                                                            0xb
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT                                                        0xc
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT                                                        0xd
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT                                                        0xe
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT                                                        0xf
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT                                                        0x10
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT                                                        0x11
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT                                                        0x12
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT                                                        0x13
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT                                                        0x14
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT                                                        0x15
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT                                                       0x16
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT                                                       0x17
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT                                                       0x18
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT                                                       0x19
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT                                                       0x1a
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT                                                       0x1b
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT                                                       0x1c
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT                                                       0x1d
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT                                                       0x1e
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT                                                       0x1f
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP0_MASK                                                                0x00000001L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP1_MASK                                                                0x00000002L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP2_MASK                                                                0x00000004L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP3_MASK                                                                0x00000008L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP4_MASK                                                                0x00000010L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP5_MASK                                                                0x00000020L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP6_MASK                                                                0x00000040L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP7_MASK                                                                0x00000080L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP8_MASK                                                                0x00000100L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__CP9_MASK                                                                0x00000200L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__SDMA0_MASK                                                              0x00000400L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__SDMA1_MASK                                                              0x00000800L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK                                                          0x00001000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK                                                          0x00002000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK                                                          0x00004000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK                                                          0x00008000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK                                                          0x00010000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK                                                          0x00020000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK                                                          0x00040000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK                                                          0x00080000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK                                                          0x00100000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK                                                          0x00200000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK                                                         0x00400000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK                                                         0x00800000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK                                                         0x01000000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK                                                         0x02000000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK                                                         0x04000000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK                                                         0x08000000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK                                                         0x10000000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK                                                         0x20000000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK                                                         0x40000000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK                                                         0x80000000L
+//BIF_BX_PF0_GPU_HDP_FLUSH_DONE
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0__SHIFT                                                             0x0
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1__SHIFT                                                             0x1
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2__SHIFT                                                             0x2
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3__SHIFT                                                             0x3
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4__SHIFT                                                             0x4
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5__SHIFT                                                             0x5
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6__SHIFT                                                             0x6
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7__SHIFT                                                             0x7
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8__SHIFT                                                             0x8
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9__SHIFT                                                             0x9
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT                                                           0xa
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT                                                           0xb
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT                                                       0xc
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT                                                       0xd
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT                                                       0xe
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT                                                       0xf
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT                                                       0x10
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT                                                       0x11
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT                                                       0x12
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT                                                       0x13
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT                                                       0x14
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT                                                       0x15
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT                                                      0x16
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT                                                      0x17
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT                                                      0x18
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT                                                      0x19
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT                                                      0x1a
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT                                                      0x1b
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT                                                      0x1c
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT                                                      0x1d
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT                                                      0x1e
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT                                                      0x1f
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP0_MASK                                                               0x00000001L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP1_MASK                                                               0x00000002L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP2_MASK                                                               0x00000004L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP3_MASK                                                               0x00000008L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP4_MASK                                                               0x00000010L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP5_MASK                                                               0x00000020L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP6_MASK                                                               0x00000040L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP7_MASK                                                               0x00000080L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP8_MASK                                                               0x00000100L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__CP9_MASK                                                               0x00000200L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA0_MASK                                                             0x00000400L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__SDMA1_MASK                                                             0x00000800L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK                                                         0x00001000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK                                                         0x00002000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK                                                         0x00004000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK                                                         0x00008000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK                                                         0x00010000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK                                                         0x00020000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK                                                         0x00040000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK                                                         0x00080000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK                                                         0x00100000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK                                                         0x00200000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK                                                        0x00400000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK                                                        0x00800000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK                                                        0x01000000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK                                                        0x02000000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK                                                        0x04000000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK                                                        0x08000000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK                                                        0x10000000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK                                                        0x20000000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK                                                        0x40000000L
+#define BIF_BX_PF0_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK                                                        0x80000000L
+//BIF_BX_PF0_BIF_TRANS_PENDING
+#define BIF_BX_PF0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT                                            0x0
+#define BIF_BX_PF0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT                                            0x1
+#define BIF_BX_PF0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK                                              0x00000001L
+#define BIF_BX_PF0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK                                              0x00000002L
+//BIF_BX_PF0_NBIF_GFX_ADDR_LUT_BYPASS
+#define BIF_BX_PF0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT                                                0x0
+#define BIF_BX_PF0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK                                                  0x00000001L
+//BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT                                                 0x0
+#define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK                                                   0xFFFFFFFFL
+//BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT                                                 0x0
+#define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK                                                   0xFFFFFFFFL
+//BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT                                                 0x0
+#define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK                                                   0xFFFFFFFFL
+//BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT                                                 0x0
+#define BIF_BX_PF0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK                                                   0xFFFFFFFFL
+//BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT                                                 0x0
+#define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK                                                   0xFFFFFFFFL
+//BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT                                                 0x0
+#define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK                                                   0xFFFFFFFFL
+//BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT                                                 0x0
+#define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK                                                   0xFFFFFFFFL
+//BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT                                                 0x0
+#define BIF_BX_PF0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK                                                   0xFFFFFFFFL
+//BIF_BX_PF0_MAILBOX_CONTROL
+#define BIF_BX_PF0_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT                                                      0x0
+#define BIF_BX_PF0_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT                                                        0x1
+#define BIF_BX_PF0_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT                                                      0x8
+#define BIF_BX_PF0_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT                                                        0x9
+#define BIF_BX_PF0_MAILBOX_CONTROL__TRN_MSG_VALID_MASK                                                        0x00000001L
+#define BIF_BX_PF0_MAILBOX_CONTROL__TRN_MSG_ACK_MASK                                                          0x00000002L
+#define BIF_BX_PF0_MAILBOX_CONTROL__RCV_MSG_VALID_MASK                                                        0x00000100L
+#define BIF_BX_PF0_MAILBOX_CONTROL__RCV_MSG_ACK_MASK                                                          0x00000200L
+//BIF_BX_PF0_MAILBOX_INT_CNTL
+#define BIF_BX_PF0_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT                                                      0x0
+#define BIF_BX_PF0_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT                                                        0x1
+#define BIF_BX_PF0_MAILBOX_INT_CNTL__VALID_INT_EN_MASK                                                        0x00000001L
+#define BIF_BX_PF0_MAILBOX_INT_CNTL__ACK_INT_EN_MASK                                                          0x00000002L
+//BIF_BX_PF0_BIF_VMHV_MAILBOX
+#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT                                      0x0
+#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT                                    0x1
+#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT                                         0x8
+#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT                                        0xf
+#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT                                         0x10
+#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT                                        0x17
+#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT                                          0x18
+#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT                                          0x19
+#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK                                        0x00000001L
+#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK                                      0x00000002L
+#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK                                           0x00000F00L
+#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK                                          0x00008000L
+#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK                                           0x000F0000L
+#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK                                          0x00800000L
+#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK                                            0x01000000L
+#define BIF_BX_PF0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK                                            0x02000000L
+//BIF_BX_PF0_PARTITION_COMPUTE_CAP
+#define BIF_BX_PF0_PARTITION_COMPUTE_CAP__SPX_SUPPORT__SHIFT                                                  0x0
+#define BIF_BX_PF0_PARTITION_COMPUTE_CAP__DPX_SUPPORT__SHIFT                                                  0x1
+#define BIF_BX_PF0_PARTITION_COMPUTE_CAP__TPX_SUPPORT__SHIFT                                                  0x2
+#define BIF_BX_PF0_PARTITION_COMPUTE_CAP__QPX_SUPPORT__SHIFT                                                  0x3
+#define BIF_BX_PF0_PARTITION_COMPUTE_CAP__CPX_SUPPORT__SHIFT                                                  0x4
+#define BIF_BX_PF0_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY__SHIFT                                             0xa
+#define BIF_BX_PF0_PARTITION_COMPUTE_CAP__SPX_SUPPORT_MASK                                                    0x00000001L
+#define BIF_BX_PF0_PARTITION_COMPUTE_CAP__DPX_SUPPORT_MASK                                                    0x00000002L
+#define BIF_BX_PF0_PARTITION_COMPUTE_CAP__TPX_SUPPORT_MASK                                                    0x00000004L
+#define BIF_BX_PF0_PARTITION_COMPUTE_CAP__QPX_SUPPORT_MASK                                                    0x00000008L
+#define BIF_BX_PF0_PARTITION_COMPUTE_CAP__CPX_SUPPORT_MASK                                                    0x00000010L
+#define BIF_BX_PF0_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY_MASK                                               0x0003FC00L
+//BIF_BX_PF0_PARTITION_MEM_CAP
+#define BIF_BX_PF0_PARTITION_MEM_CAP__NPS1_SUPPORT__SHIFT                                                     0x0
+#define BIF_BX_PF0_PARTITION_MEM_CAP__NPS2_SUPPORT__SHIFT                                                     0x1
+#define BIF_BX_PF0_PARTITION_MEM_CAP__NPS3_SUPPORT__SHIFT                                                     0x2
+#define BIF_BX_PF0_PARTITION_MEM_CAP__NPS4_SUPPORT__SHIFT                                                     0x3
+#define BIF_BX_PF0_PARTITION_MEM_CAP__NPS6_SUPPORT__SHIFT                                                     0x5
+#define BIF_BX_PF0_PARTITION_MEM_CAP__NPS8_SUPPORT__SHIFT                                                     0x7
+#define BIF_BX_PF0_PARTITION_MEM_CAP__NPS1_SUPPORT_MASK                                                       0x00000001L
+#define BIF_BX_PF0_PARTITION_MEM_CAP__NPS2_SUPPORT_MASK                                                       0x00000002L
+#define BIF_BX_PF0_PARTITION_MEM_CAP__NPS3_SUPPORT_MASK                                                       0x00000004L
+#define BIF_BX_PF0_PARTITION_MEM_CAP__NPS4_SUPPORT_MASK                                                       0x00000008L
+#define BIF_BX_PF0_PARTITION_MEM_CAP__NPS6_SUPPORT_MASK                                                       0x00000020L
+#define BIF_BX_PF0_PARTITION_MEM_CAP__NPS8_SUPPORT_MASK                                                       0x00000080L
+//BIF_BX_PF0_PARTITION_COMPUTE_STATUS
+#define BIF_BX_PF0_PARTITION_COMPUTE_STATUS__PARTITION_MODE__SHIFT                                            0x4
+#define BIF_BX_PF0_PARTITION_COMPUTE_STATUS__PARTITION_MODE_MASK                                              0x000000F0L
+//BIF_BX_PF0_PARTITION_MEM_STATUS
+#define BIF_BX_PF0_PARTITION_MEM_STATUS__CHANGE_STATUS__SHIFT                                                 0x0
+#define BIF_BX_PF0_PARTITION_MEM_STATUS__NPS_MODE__SHIFT                                                      0x4
+#define BIF_BX_PF0_PARTITION_MEM_STATUS__CHANGE_STATUS_MASK                                                   0x0000000FL
+#define BIF_BX_PF0_PARTITION_MEM_STATUS__NPS_MODE_MASK                                                        0x00000FF0L
+
+
+// addressBlock: nbif0_nbif0_rcc_dev0_epf0_BIFPFVFDEC1
+//RCC_DEV0_EPF0_RCC_ERR_LOG
+#define RCC_DEV0_EPF0_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT                                  0x0
+#define RCC_DEV0_EPF0_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT                                         0x1
+#define RCC_DEV0_EPF0_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK                                    0x00000001L
+#define RCC_DEV0_EPF0_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK                                           0x00000002L
+//RCC_DEV0_EPF0_RCC_DOORBELL_APER_EN
+#define RCC_DEV0_EPF0_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT                                       0x0
+#define RCC_DEV0_EPF0_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK                                         0x00000001L
+//RCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE
+#define RCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT                                               0x0
+#define RCC_DEV0_EPF0_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK                                                 0xFFFFFFFFL
+//RCC_DEV0_EPF0_RCC_CONFIG_RESERVED
+#define RCC_DEV0_EPF0_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER
+#define RCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT                                         0x0
+#define RCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT                                              0x1f
+#define RCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK                                           0x00000001L
+#define RCC_DEV0_EPF0_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK                                                0x80000000L
+
+
+// addressBlock: nbif0_nbif0_gdc_GDCDEC
+//GDC0_NGDC_SDP_PORT_CTRL
+#define GDC0_NGDC_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS__SHIFT                                                 0x0
+#define GDC0_NGDC_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS_H__SHIFT                                               0x10
+#define GDC0_NGDC_SDP_PORT_CTRL__SDP_DISCON_DIS__SHIFT                                                        0x1f
+#define GDC0_NGDC_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS_MASK                                                   0x000000FFL
+#define GDC0_NGDC_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS_H_MASK                                                 0x000F0000L
+#define GDC0_NGDC_SDP_PORT_CTRL__SDP_DISCON_DIS_MASK                                                          0x80000000L
+//GDC0_SHUB_REGS_IF_CTL
+#define GDC0_SHUB_REGS_IF_CTL__SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS__SHIFT                                0x0
+#define GDC0_SHUB_REGS_IF_CTL__SHUB_REGS_VF_PROTECTION_DIS__SHIFT                                             0x1
+#define GDC0_SHUB_REGS_IF_CTL__SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS_MASK                                  0x00000001L
+#define GDC0_SHUB_REGS_IF_CTL__SHUB_REGS_VF_PROTECTION_DIS_MASK                                               0x00000002L
+//GDC0_NGDC_MGCG_CTRL
+#define GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_EN__SHIFT                                                              0x0
+#define GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_MODE__SHIFT                                                            0x1
+#define GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_HYSTERESIS__SHIFT                                                      0x2
+#define GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_HST_DIS__SHIFT                                                         0xa
+#define GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_DMA_DIS__SHIFT                                                         0xb
+#define GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_REG_DIS__SHIFT                                                         0xc
+#define GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_AER_DIS__SHIFT                                                         0xd
+#define GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_DBG_DIS__SHIFT                                                         0xe
+#define GDC0_NGDC_MGCG_CTRL__NGDC_SRAM_FGCG_EN__SHIFT                                                         0xf
+#define GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_EN_MASK                                                                0x00000001L
+#define GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_MODE_MASK                                                              0x00000002L
+#define GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_HYSTERESIS_MASK                                                        0x000003FCL
+#define GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_HST_DIS_MASK                                                           0x00000400L
+#define GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_DMA_DIS_MASK                                                           0x00000800L
+#define GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_REG_DIS_MASK                                                           0x00001000L
+#define GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_AER_DIS_MASK                                                           0x00002000L
+#define GDC0_NGDC_MGCG_CTRL__NGDC_MGCG_DBG_DIS_MASK                                                           0x00004000L
+#define GDC0_NGDC_MGCG_CTRL__NGDC_SRAM_FGCG_EN_MASK                                                           0x00008000L
+//GDC0_S2A_MISC_CNTL
+#define GDC0_S2A_MISC_CNTL__AXI_HST_CPL_EP_DIS__SHIFT                                                         0x3
+#define GDC0_S2A_MISC_CNTL__ATM_ARB_MODE__SHIFT                                                               0x8
+#define GDC0_S2A_MISC_CNTL__RB_ARB_MODE__SHIFT                                                                0xa
+#define GDC0_S2A_MISC_CNTL__HSTR_ARB_MODE__SHIFT                                                              0xc
+#define GDC0_S2A_MISC_CNTL__HDP_PERF_ENH_DIS__SHIFT                                                           0xf
+#define GDC0_S2A_MISC_CNTL__WRSP_ARB_MODE__SHIFT                                                              0x10
+#define GDC0_S2A_MISC_CNTL__AXI_HST_CPL_EP_DIS_MASK                                                           0x00000008L
+#define GDC0_S2A_MISC_CNTL__ATM_ARB_MODE_MASK                                                                 0x00000300L
+#define GDC0_S2A_MISC_CNTL__RB_ARB_MODE_MASK                                                                  0x00000C00L
+#define GDC0_S2A_MISC_CNTL__HSTR_ARB_MODE_MASK                                                                0x00003000L
+#define GDC0_S2A_MISC_CNTL__HDP_PERF_ENH_DIS_MASK                                                             0x00008000L
+#define GDC0_S2A_MISC_CNTL__WRSP_ARB_MODE_MASK                                                                0x000F0000L
+//GDC0_NGDC_MCA_SMN_CTRL0
+#define GDC0_NGDC_MCA_SMN_CTRL0__MCA_SMN_POSTED__SHIFT                                                        0x0
+#define GDC0_NGDC_MCA_SMN_CTRL0__MCA_SMN_POSTED_MASK                                                          0x00000001L
+//GDC0_NGDC_EARLY_WAKEUP_CTRL
+#define GDC0_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_BY_CLIENT_ACTIVE__SHIFT                                0x0
+#define GDC0_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_BY_CLIENT_DS_EXIT__SHIFT                               0x1
+#define GDC0_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_ALLOW_AER_ACTIVE__SHIFT                                0x2
+#define GDC0_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_BY_CLIENT_ACTIVE_MASK                                  0x00000001L
+#define GDC0_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_BY_CLIENT_DS_EXIT_MASK                                 0x00000002L
+#define GDC0_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_ALLOW_AER_ACTIVE_MASK                                  0x00000004L
+//GDC0_GDC_GDCCLK_S2A_ERR_RSP_CNTL
+#define GDC0_GDC_GDCCLK_S2A_ERR_RSP_CNTL__GDC_GDCCLK_S2A_RDRSP_BYPASS__SHIFT                                  0x0
+#define GDC0_GDC_GDCCLK_S2A_ERR_RSP_CNTL__GDC_GDCCLK_S2A_RDRSP_ACCUM_SEL__SHIFT                               0x1
+#define GDC0_GDC_GDCCLK_S2A_ERR_RSP_CNTL__GDC_GDCCLK_S2A_RDRSP_FORCE_EN__SHIFT                                0x2
+#define GDC0_GDC_GDCCLK_S2A_ERR_RSP_CNTL__GDC_GDCCLK_S2A_RDRSP_FORCE_DATA__SHIFT                              0x3
+#define GDC0_GDC_GDCCLK_S2A_ERR_RSP_CNTL__GDC_GDCCLK_S2A_RDRSP_STATUS_ACCUM_EN__SHIFT                         0x4
+#define GDC0_GDC_GDCCLK_S2A_ERR_RSP_CNTL__GDC_GDCCLK_S2A_RDRSP_DATASTATUS_ACCUM_EN__SHIFT                     0x5
+#define GDC0_GDC_GDCCLK_S2A_ERR_RSP_CNTL__GDC_GDCCLK_S2A_RDRSP_BYPASS_MASK                                    0x00000001L
+#define GDC0_GDC_GDCCLK_S2A_ERR_RSP_CNTL__GDC_GDCCLK_S2A_RDRSP_ACCUM_SEL_MASK                                 0x00000002L
+#define GDC0_GDC_GDCCLK_S2A_ERR_RSP_CNTL__GDC_GDCCLK_S2A_RDRSP_FORCE_EN_MASK                                  0x00000004L
+#define GDC0_GDC_GDCCLK_S2A_ERR_RSP_CNTL__GDC_GDCCLK_S2A_RDRSP_FORCE_DATA_MASK                                0x00000008L
+#define GDC0_GDC_GDCCLK_S2A_ERR_RSP_CNTL__GDC_GDCCLK_S2A_RDRSP_STATUS_ACCUM_EN_MASK                           0x00000010L
+#define GDC0_GDC_GDCCLK_S2A_ERR_RSP_CNTL__GDC_GDCCLK_S2A_RDRSP_DATASTATUS_ACCUM_EN_MASK                       0x00000020L
+//GDC0_GDC_DMA_SION_PCTRL
+#define GDC0_GDC_DMA_SION_PCTRL__BIF_SDP_DISCON_DIS__SHIFT                                                    0x0
+#define GDC0_GDC_DMA_SION_PCTRL__SYSHUB_SDP_DISCON_DIS__SHIFT                                                 0x3
+#define GDC0_GDC_DMA_SION_PCTRL__INT_SDP_DISCON_DIS__SHIFT                                                    0x6
+#define GDC0_GDC_DMA_SION_PCTRL__BIF_SDP_DISCON_DIS_MASK                                                      0x00000001L
+#define GDC0_GDC_DMA_SION_PCTRL__SYSHUB_SDP_DISCON_DIS_MASK                                                   0x00000008L
+#define GDC0_GDC_DMA_SION_PCTRL__INT_SDP_DISCON_DIS_MASK                                                      0x00000040L
+//GDC0_NGDC_MP4SDP_CNTL
+#define GDC0_NGDC_MP4SDP_CNTL__MP4SDP_BLKLVL_VC0_OVERRIDE_EN__SHIFT                                           0x0
+#define GDC0_NGDC_MP4SDP_CNTL__MP4SDP_BLKLVL_VC0_OVERRIDE_VAL__SHIFT                                          0x1
+#define GDC0_NGDC_MP4SDP_CNTL__MP4SDP_BLKLVL_VC1_OVERRIDE_EN__SHIFT                                           0x4
+#define GDC0_NGDC_MP4SDP_CNTL__MP4SDP_BLKLVL_VC1_OVERRIDE_VAL__SHIFT                                          0x5
+#define GDC0_NGDC_MP4SDP_CNTL__MP4SDP_BLKLVL_VC4_OVERRIDE_EN__SHIFT                                           0x8
+#define GDC0_NGDC_MP4SDP_CNTL__MP4SDP_BLKLVL_VC4_OVERRIDE_VAL__SHIFT                                          0x9
+#define GDC0_NGDC_MP4SDP_CNTL__MP4SDP_BLKLVL_VC0_OVERRIDE_EN_MASK                                             0x00000001L
+#define GDC0_NGDC_MP4SDP_CNTL__MP4SDP_BLKLVL_VC0_OVERRIDE_VAL_MASK                                            0x00000006L
+#define GDC0_NGDC_MP4SDP_CNTL__MP4SDP_BLKLVL_VC1_OVERRIDE_EN_MASK                                             0x00000010L
+#define GDC0_NGDC_MP4SDP_CNTL__MP4SDP_BLKLVL_VC1_OVERRIDE_VAL_MASK                                            0x00000060L
+#define GDC0_NGDC_MP4SDP_CNTL__MP4SDP_BLKLVL_VC4_OVERRIDE_EN_MASK                                             0x00000100L
+#define GDC0_NGDC_MP4SDP_CNTL__MP4SDP_BLKLVL_VC4_OVERRIDE_VAL_MASK                                            0x00000600L
+//GDC0_DOORBELL_VCN_TARGET_VF0
+#define GDC0_DOORBELL_VCN_TARGET_VF0__DOORBELL_VCN0_TARGET_VF0__SHIFT                                         0x0
+#define GDC0_DOORBELL_VCN_TARGET_VF0__DOORBELL_VCN1_TARGET_VF0__SHIFT                                         0x4
+#define GDC0_DOORBELL_VCN_TARGET_VF0__DOORBELL_VCN2_TARGET_VF0__SHIFT                                         0x8
+#define GDC0_DOORBELL_VCN_TARGET_VF0__DOORBELL_VCN3_TARGET_VF0__SHIFT                                         0xc
+#define GDC0_DOORBELL_VCN_TARGET_VF0__DOORBELL_VCN0_TARGET_VF0_MASK                                           0x000FL
+#define GDC0_DOORBELL_VCN_TARGET_VF0__DOORBELL_VCN1_TARGET_VF0_MASK                                           0x00F0L
+#define GDC0_DOORBELL_VCN_TARGET_VF0__DOORBELL_VCN2_TARGET_VF0_MASK                                           0x0F00L
+#define GDC0_DOORBELL_VCN_TARGET_VF0__DOORBELL_VCN3_TARGET_VF0_MASK                                           0xF000L
+//GDC0_DOORBELL_VCN_TARGET_VF1
+#define GDC0_DOORBELL_VCN_TARGET_VF1__DOORBELL_VCN0_TARGET_VF1__SHIFT                                         0x0
+#define GDC0_DOORBELL_VCN_TARGET_VF1__DOORBELL_VCN1_TARGET_VF1__SHIFT                                         0x4
+#define GDC0_DOORBELL_VCN_TARGET_VF1__DOORBELL_VCN2_TARGET_VF1__SHIFT                                         0x8
+#define GDC0_DOORBELL_VCN_TARGET_VF1__DOORBELL_VCN3_TARGET_VF1__SHIFT                                         0xc
+#define GDC0_DOORBELL_VCN_TARGET_VF1__DOORBELL_VCN0_TARGET_VF1_MASK                                           0x000FL
+#define GDC0_DOORBELL_VCN_TARGET_VF1__DOORBELL_VCN1_TARGET_VF1_MASK                                           0x00F0L
+#define GDC0_DOORBELL_VCN_TARGET_VF1__DOORBELL_VCN2_TARGET_VF1_MASK                                           0x0F00L
+#define GDC0_DOORBELL_VCN_TARGET_VF1__DOORBELL_VCN3_TARGET_VF1_MASK                                           0xF000L
+//GDC0_DOORBELL_VCN_TARGET_VF2
+#define GDC0_DOORBELL_VCN_TARGET_VF2__DOORBELL_VCN0_TARGET_VF2__SHIFT                                         0x0
+#define GDC0_DOORBELL_VCN_TARGET_VF2__DOORBELL_VCN1_TARGET_VF2__SHIFT                                         0x4
+#define GDC0_DOORBELL_VCN_TARGET_VF2__DOORBELL_VCN2_TARGET_VF2__SHIFT                                         0x8
+#define GDC0_DOORBELL_VCN_TARGET_VF2__DOORBELL_VCN3_TARGET_VF2__SHIFT                                         0xc
+#define GDC0_DOORBELL_VCN_TARGET_VF2__DOORBELL_VCN0_TARGET_VF2_MASK                                           0x000FL
+#define GDC0_DOORBELL_VCN_TARGET_VF2__DOORBELL_VCN1_TARGET_VF2_MASK                                           0x00F0L
+#define GDC0_DOORBELL_VCN_TARGET_VF2__DOORBELL_VCN2_TARGET_VF2_MASK                                           0x0F00L
+#define GDC0_DOORBELL_VCN_TARGET_VF2__DOORBELL_VCN3_TARGET_VF2_MASK                                           0xF000L
+//GDC0_DOORBELL_VCN_TARGET_VF3
+#define GDC0_DOORBELL_VCN_TARGET_VF3__DOORBELL_VCN0_TARGET_VF3__SHIFT                                         0x0
+#define GDC0_DOORBELL_VCN_TARGET_VF3__DOORBELL_VCN1_TARGET_VF3__SHIFT                                         0x4
+#define GDC0_DOORBELL_VCN_TARGET_VF3__DOORBELL_VCN2_TARGET_VF3__SHIFT                                         0x8
+#define GDC0_DOORBELL_VCN_TARGET_VF3__DOORBELL_VCN3_TARGET_VF3__SHIFT                                         0xc
+#define GDC0_DOORBELL_VCN_TARGET_VF3__DOORBELL_VCN0_TARGET_VF3_MASK                                           0x000FL
+#define GDC0_DOORBELL_VCN_TARGET_VF3__DOORBELL_VCN1_TARGET_VF3_MASK                                           0x00F0L
+#define GDC0_DOORBELL_VCN_TARGET_VF3__DOORBELL_VCN2_TARGET_VF3_MASK                                           0x0F00L
+#define GDC0_DOORBELL_VCN_TARGET_VF3__DOORBELL_VCN3_TARGET_VF3_MASK                                           0xF000L
+//GDC0_DOORBELL_VCN_TARGET_VF4
+#define GDC0_DOORBELL_VCN_TARGET_VF4__DOORBELL_VCN0_TARGET_VF4__SHIFT                                         0x0
+#define GDC0_DOORBELL_VCN_TARGET_VF4__DOORBELL_VCN1_TARGET_VF4__SHIFT                                         0x4
+#define GDC0_DOORBELL_VCN_TARGET_VF4__DOORBELL_VCN2_TARGET_VF4__SHIFT                                         0x8
+#define GDC0_DOORBELL_VCN_TARGET_VF4__DOORBELL_VCN3_TARGET_VF4__SHIFT                                         0xc
+#define GDC0_DOORBELL_VCN_TARGET_VF4__DOORBELL_VCN0_TARGET_VF4_MASK                                           0x000FL
+#define GDC0_DOORBELL_VCN_TARGET_VF4__DOORBELL_VCN1_TARGET_VF4_MASK                                           0x00F0L
+#define GDC0_DOORBELL_VCN_TARGET_VF4__DOORBELL_VCN2_TARGET_VF4_MASK                                           0x0F00L
+#define GDC0_DOORBELL_VCN_TARGET_VF4__DOORBELL_VCN3_TARGET_VF4_MASK                                           0xF000L
+//GDC0_DOORBELL_VCN_TARGET_VF5
+#define GDC0_DOORBELL_VCN_TARGET_VF5__DOORBELL_VCN0_TARGET_VF5__SHIFT                                         0x0
+#define GDC0_DOORBELL_VCN_TARGET_VF5__DOORBELL_VCN1_TARGET_VF5__SHIFT                                         0x4
+#define GDC0_DOORBELL_VCN_TARGET_VF5__DOORBELL_VCN2_TARGET_VF5__SHIFT                                         0x8
+#define GDC0_DOORBELL_VCN_TARGET_VF5__DOORBELL_VCN3_TARGET_VF5__SHIFT                                         0xc
+#define GDC0_DOORBELL_VCN_TARGET_VF5__DOORBELL_VCN0_TARGET_VF5_MASK                                           0x000FL
+#define GDC0_DOORBELL_VCN_TARGET_VF5__DOORBELL_VCN1_TARGET_VF5_MASK                                           0x00F0L
+#define GDC0_DOORBELL_VCN_TARGET_VF5__DOORBELL_VCN2_TARGET_VF5_MASK                                           0x0F00L
+#define GDC0_DOORBELL_VCN_TARGET_VF5__DOORBELL_VCN3_TARGET_VF5_MASK                                           0xF000L
+//GDC0_DOORBELL_VCN_TARGET_VF6
+#define GDC0_DOORBELL_VCN_TARGET_VF6__DOORBELL_VCN0_TARGET_VF6__SHIFT                                         0x0
+#define GDC0_DOORBELL_VCN_TARGET_VF6__DOORBELL_VCN1_TARGET_VF6__SHIFT                                         0x4
+#define GDC0_DOORBELL_VCN_TARGET_VF6__DOORBELL_VCN2_TARGET_VF6__SHIFT                                         0x8
+#define GDC0_DOORBELL_VCN_TARGET_VF6__DOORBELL_VCN3_TARGET_VF6__SHIFT                                         0xc
+#define GDC0_DOORBELL_VCN_TARGET_VF6__DOORBELL_VCN0_TARGET_VF6_MASK                                           0x000FL
+#define GDC0_DOORBELL_VCN_TARGET_VF6__DOORBELL_VCN1_TARGET_VF6_MASK                                           0x00F0L
+#define GDC0_DOORBELL_VCN_TARGET_VF6__DOORBELL_VCN2_TARGET_VF6_MASK                                           0x0F00L
+#define GDC0_DOORBELL_VCN_TARGET_VF6__DOORBELL_VCN3_TARGET_VF6_MASK                                           0xF000L
+//GDC0_DOORBELL_VCN_TARGET_VF7
+#define GDC0_DOORBELL_VCN_TARGET_VF7__DOORBELL_VCN0_TARGET_VF7__SHIFT                                         0x0
+#define GDC0_DOORBELL_VCN_TARGET_VF7__DOORBELL_VCN1_TARGET_VF7__SHIFT                                         0x4
+#define GDC0_DOORBELL_VCN_TARGET_VF7__DOORBELL_VCN2_TARGET_VF7__SHIFT                                         0x8
+#define GDC0_DOORBELL_VCN_TARGET_VF7__DOORBELL_VCN3_TARGET_VF7__SHIFT                                         0xc
+#define GDC0_DOORBELL_VCN_TARGET_VF7__DOORBELL_VCN0_TARGET_VF7_MASK                                           0x000FL
+#define GDC0_DOORBELL_VCN_TARGET_VF7__DOORBELL_VCN1_TARGET_VF7_MASK                                           0x00F0L
+#define GDC0_DOORBELL_VCN_TARGET_VF7__DOORBELL_VCN2_TARGET_VF7_MASK                                           0x0F00L
+#define GDC0_DOORBELL_VCN_TARGET_VF7__DOORBELL_VCN3_TARGET_VF7_MASK                                           0xF000L
+//GDC0_DOORBELL_ACCESS_EN_PF
+#define GDC0_DOORBELL_ACCESS_EN_PF__DOORBELL_ACCESS_EN_PF__SHIFT                                              0x0
+#define GDC0_DOORBELL_ACCESS_EN_PF__DOORBELL_ACCESS_EN_PF_MASK                                                0x00FFL
+//GDC0_DOORBELL_ACCESS_EN_VF0
+#define GDC0_DOORBELL_ACCESS_EN_VF0__DOORBELL_ACCESS_EN_VF0__SHIFT                                            0x0
+#define GDC0_DOORBELL_ACCESS_EN_VF0__XCD_ACCESS_EN_VF0__SHIFT                                                 0x8
+#define GDC0_DOORBELL_ACCESS_EN_VF0__DOORBELL_ACCESS_EN_VF0_MASK                                              0x00FFL
+#define GDC0_DOORBELL_ACCESS_EN_VF0__XCD_ACCESS_EN_VF0_MASK                                                   0xFF00L
+//GDC0_DOORBELL_ACCESS_EN_VF1
+#define GDC0_DOORBELL_ACCESS_EN_VF1__DOORBELL_ACCESS_EN_VF1__SHIFT                                            0x0
+#define GDC0_DOORBELL_ACCESS_EN_VF1__XCD_ACCESS_EN_VF1__SHIFT                                                 0x8
+#define GDC0_DOORBELL_ACCESS_EN_VF1__DOORBELL_ACCESS_EN_VF1_MASK                                              0x00FFL
+#define GDC0_DOORBELL_ACCESS_EN_VF1__XCD_ACCESS_EN_VF1_MASK                                                   0xFF00L
+//GDC0_DOORBELL_ACCESS_EN_VF2
+#define GDC0_DOORBELL_ACCESS_EN_VF2__DOORBELL_ACCESS_EN_VF2__SHIFT                                            0x0
+#define GDC0_DOORBELL_ACCESS_EN_VF2__XCD_ACCESS_EN_VF2__SHIFT                                                 0x8
+#define GDC0_DOORBELL_ACCESS_EN_VF2__DOORBELL_ACCESS_EN_VF2_MASK                                              0x00FFL
+#define GDC0_DOORBELL_ACCESS_EN_VF2__XCD_ACCESS_EN_VF2_MASK                                                   0xFF00L
+//GDC0_DOORBELL_ACCESS_EN_VF3
+#define GDC0_DOORBELL_ACCESS_EN_VF3__DOORBELL_ACCESS_EN_VF3__SHIFT                                            0x0
+#define GDC0_DOORBELL_ACCESS_EN_VF3__XCD_ACCESS_EN_VF3__SHIFT                                                 0x8
+#define GDC0_DOORBELL_ACCESS_EN_VF3__DOORBELL_ACCESS_EN_VF3_MASK                                              0x00FFL
+#define GDC0_DOORBELL_ACCESS_EN_VF3__XCD_ACCESS_EN_VF3_MASK                                                   0xFF00L
+//GDC0_DOORBELL_ACCESS_EN_VF4
+#define GDC0_DOORBELL_ACCESS_EN_VF4__DOORBELL_ACCESS_EN_VF4__SHIFT                                            0x0
+#define GDC0_DOORBELL_ACCESS_EN_VF4__XCD_ACCESS_EN_VF4__SHIFT                                                 0x8
+#define GDC0_DOORBELL_ACCESS_EN_VF4__DOORBELL_ACCESS_EN_VF4_MASK                                              0x00FFL
+#define GDC0_DOORBELL_ACCESS_EN_VF4__XCD_ACCESS_EN_VF4_MASK                                                   0xFF00L
+//GDC0_DOORBELL_ACCESS_EN_VF5
+#define GDC0_DOORBELL_ACCESS_EN_VF5__DOORBELL_ACCESS_EN_VF5__SHIFT                                            0x0
+#define GDC0_DOORBELL_ACCESS_EN_VF5__XCD_ACCESS_EN_VF5__SHIFT                                                 0x8
+#define GDC0_DOORBELL_ACCESS_EN_VF5__DOORBELL_ACCESS_EN_VF5_MASK                                              0x00FFL
+#define GDC0_DOORBELL_ACCESS_EN_VF5__XCD_ACCESS_EN_VF5_MASK                                                   0xFF00L
+//GDC0_DOORBELL_ACCESS_EN_VF6
+#define GDC0_DOORBELL_ACCESS_EN_VF6__DOORBELL_ACCESS_EN_VF6__SHIFT                                            0x0
+#define GDC0_DOORBELL_ACCESS_EN_VF6__XCD_ACCESS_EN_VF6__SHIFT                                                 0x8
+#define GDC0_DOORBELL_ACCESS_EN_VF6__DOORBELL_ACCESS_EN_VF6_MASK                                              0x00FFL
+#define GDC0_DOORBELL_ACCESS_EN_VF6__XCD_ACCESS_EN_VF6_MASK                                                   0xFF00L
+//GDC0_DOORBELL_ACCESS_EN_VF7
+#define GDC0_DOORBELL_ACCESS_EN_VF7__DOORBELL_ACCESS_EN_VF7__SHIFT                                            0x0
+#define GDC0_DOORBELL_ACCESS_EN_VF7__XCD_ACCESS_EN_VF7__SHIFT                                                 0x8
+#define GDC0_DOORBELL_ACCESS_EN_VF7__DOORBELL_ACCESS_EN_VF7_MASK                                              0x00FFL
+#define GDC0_DOORBELL_ACCESS_EN_VF7__XCD_ACCESS_EN_VF7_MASK                                                   0xFF00L
+//GDC0_NGDC_CNDI_BUS_PORT_CTRL
+#define GDC0_NGDC_CNDI_BUS_PORT_CTRL__CNDI_ORIG_DISCON_HYSTERESIS__SHIFT                                      0x0
+#define GDC0_NGDC_CNDI_BUS_PORT_CTRL__CNDI_ORIG_DISCON_DIS_SOCCLK__SHIFT                                      0xc
+#define GDC0_NGDC_CNDI_BUS_PORT_CTRL__CNDI_CMPL_DISCON_HYSTERESIS__SHIFT                                      0xd
+#define GDC0_NGDC_CNDI_BUS_PORT_CTRL__CNDI_CMPL_DISCON_DIS_SOCCLK__SHIFT                                      0x19
+#define GDC0_NGDC_CNDI_BUS_PORT_CTRL__CNDI_ORIG_PORT_IDLE__SHIFT                                              0x1a
+#define GDC0_NGDC_CNDI_BUS_PORT_CTRL__SHUB_CNDI_VDCI_CKEN_MASK__SHIFT                                         0x1b
+#define GDC0_NGDC_CNDI_BUS_PORT_CTRL__CNDI_ORIG_DISCON_HYSTERESIS_MASK                                        0x00000FFFL
+#define GDC0_NGDC_CNDI_BUS_PORT_CTRL__CNDI_ORIG_DISCON_DIS_SOCCLK_MASK                                        0x00001000L
+#define GDC0_NGDC_CNDI_BUS_PORT_CTRL__CNDI_CMPL_DISCON_HYSTERESIS_MASK                                        0x01FFE000L
+#define GDC0_NGDC_CNDI_BUS_PORT_CTRL__CNDI_CMPL_DISCON_DIS_SOCCLK_MASK                                        0x02000000L
+#define GDC0_NGDC_CNDI_BUS_PORT_CTRL__CNDI_ORIG_PORT_IDLE_MASK                                                0x04000000L
+#define GDC0_NGDC_CNDI_BUS_PORT_CTRL__SHUB_CNDI_VDCI_CKEN_MASK_MASK                                           0x08000000L
+//GDC0_NGDC_CNDI_BUS_POOL_CRED_CTRL
+#define GDC0_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_CMPL_WRRSP_POOLCRED_ALLOC_VC0_ALLOC__SHIFT                    0x0
+#define GDC0_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_CMPL_WRRSP_POOLCRED_ALLOC_VC1_ALLOC__SHIFT                    0x4
+#define GDC0_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_CMPL_RDRSP_POOLCRED_ALLOC_VC0_ALLOC__SHIFT                    0x8
+#define GDC0_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_CMPL_RDRSP_POOLCRED_ALLOC_VC1_ALLOC__SHIFT                    0xc
+#define GDC0_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_ORIG_REQ_POOL_CREDIT_ALLOC_OVERRIDE_DYNAMIC__SHIFT            0x10
+#define GDC0_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_ORIG_ORIGDATA_POOL_CREDIT_ALLOC_OVERRIDE_DYNAMIC__SHIFT       0x11
+#define GDC0_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_CMPL_WRRSP_POOL_CREDIT_ALLOC_OVERRIDE_DYNAMIC__SHIFT          0x12
+#define GDC0_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_CMPL_RDRSP_POOL_CREDIT_ALLOC_OVERRIDE_DYNAMIC__SHIFT          0x13
+#define GDC0_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_CMPL_WRRSP_POOLCRED_ALLOC_VC0_ALLOC_MASK                      0x0000000FL
+#define GDC0_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_CMPL_WRRSP_POOLCRED_ALLOC_VC1_ALLOC_MASK                      0x000000F0L
+#define GDC0_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_CMPL_RDRSP_POOLCRED_ALLOC_VC0_ALLOC_MASK                      0x00000F00L
+#define GDC0_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_CMPL_RDRSP_POOLCRED_ALLOC_VC1_ALLOC_MASK                      0x0000F000L
+#define GDC0_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_ORIG_REQ_POOL_CREDIT_ALLOC_OVERRIDE_DYNAMIC_MASK              0x00010000L
+#define GDC0_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_ORIG_ORIGDATA_POOL_CREDIT_ALLOC_OVERRIDE_DYNAMIC_MASK         0x00020000L
+#define GDC0_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_CMPL_WRRSP_POOL_CREDIT_ALLOC_OVERRIDE_DYNAMIC_MASK            0x00040000L
+#define GDC0_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_CMPL_RDRSP_POOL_CREDIT_ALLOC_OVERRIDE_DYNAMIC_MASK            0x00080000L
+
+
+// addressBlock: nbif0_nbif0_gdc_s2a_GDCS2A_DEC
+//GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_ENABLE__SHIFT                                  0x0
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_AWID__SHIFT                                    0x1
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_FENCE_ENABLE__SHIFT                            0x6
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_RANGE_OFFSET__SHIFT                            0x7
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_RANGE_SIZE__SHIFT                              0x11
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_64BIT_SUPPORT_DIS__SHIFT                       0x19
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_NEED_DEDUCT_RANGE_OFFSET__SHIFT                0x1a
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_DROP_EN__SHIFT                                 0x1b
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_AWADDR_31_28_VALUE__SHIFT                      0x1c
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_ENABLE_MASK                                    0x00000001L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_AWID_MASK                                      0x0000003EL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_FENCE_ENABLE_MASK                              0x00000040L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_RANGE_OFFSET_MASK                              0x0001FF80L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_RANGE_SIZE_MASK                                0x01FE0000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_64BIT_SUPPORT_DIS_MASK                         0x02000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_NEED_DEDUCT_RANGE_OFFSET_MASK                  0x04000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_DROP_EN_MASK                                   0x08000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_AWADDR_31_28_VALUE_MASK                        0xF0000000L
+//GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL1
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL1__S2A_DOORBELL_PORT0_TARGET_PORT_TYPE__SHIFT                       0x0
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL1__S2A_DOORBELL_PORT0_TARGET_DIEID__SHIFT                           0x2
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL1__S2A_DOORBELL_PORT0_TARGET_PORT_ID__SHIFT                         0x4
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL1__S2A_DOORBELL_PORT0_OVERRIDE_POISON_DATA__SHIFT                   0x6
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL1__S2A_DOORBELL_PORT0_4K_PAGE_DECODE_DISABLE__SHIFT                 0x7
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL1__S2A_DOORBELL_PORT0_TARGET_PORT_TYPE_MASK                         0x00000003L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL1__S2A_DOORBELL_PORT0_TARGET_DIEID_MASK                             0x0000000CL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL1__S2A_DOORBELL_PORT0_TARGET_PORT_ID_MASK                           0x00000030L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL1__S2A_DOORBELL_PORT0_OVERRIDE_POISON_DATA_MASK                     0x00000040L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_0_CTRL1__S2A_DOORBELL_PORT0_4K_PAGE_DECODE_DISABLE_MASK                   0x00000080L
+//GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_ENABLE__SHIFT                                  0x0
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_AWID__SHIFT                                    0x1
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_FENCE_ENABLE__SHIFT                            0x6
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_RANGE_OFFSET__SHIFT                            0x7
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_RANGE_SIZE__SHIFT                              0x11
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_64BIT_SUPPORT_DIS__SHIFT                       0x19
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_NEED_DEDUCT_RANGE_OFFSET__SHIFT                0x1a
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_DROP_EN__SHIFT                                 0x1b
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE__SHIFT                      0x1c
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_ENABLE_MASK                                    0x00000001L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_AWID_MASK                                      0x0000003EL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_FENCE_ENABLE_MASK                              0x00000040L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_RANGE_OFFSET_MASK                              0x0001FF80L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_RANGE_SIZE_MASK                                0x01FE0000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_64BIT_SUPPORT_DIS_MASK                         0x02000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_NEED_DEDUCT_RANGE_OFFSET_MASK                  0x04000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_DROP_EN_MASK                                   0x08000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE_MASK                        0xF0000000L
+//GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL1
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL1__S2A_DOORBELL_PORT1_TARGET_PORT_TYPE__SHIFT                       0x0
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL1__S2A_DOORBELL_PORT1_TARGET_DIEID__SHIFT                           0x2
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL1__S2A_DOORBELL_PORT1_TARGET_PORT_ID__SHIFT                         0x4
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL1__S2A_DOORBELL_PORT1_OVERRIDE_POISON_DATA__SHIFT                   0x6
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL1__S2A_DOORBELL_PORT1_4K_PAGE_DECODE_DISABLE__SHIFT                 0x7
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL1__S2A_DOORBELL_PORT1_TARGET_PORT_TYPE_MASK                         0x00000003L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL1__S2A_DOORBELL_PORT1_TARGET_DIEID_MASK                             0x0000000CL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL1__S2A_DOORBELL_PORT1_TARGET_PORT_ID_MASK                           0x00000030L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL1__S2A_DOORBELL_PORT1_OVERRIDE_POISON_DATA_MASK                     0x00000040L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_1_CTRL1__S2A_DOORBELL_PORT1_4K_PAGE_DECODE_DISABLE_MASK                   0x00000080L
+//GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_ENABLE__SHIFT                                  0x0
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_AWID__SHIFT                                    0x1
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_FENCE_ENABLE__SHIFT                            0x6
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_RANGE_OFFSET__SHIFT                            0x7
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_RANGE_SIZE__SHIFT                              0x11
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_64BIT_SUPPORT_DIS__SHIFT                       0x19
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_NEED_DEDUCT_RANGE_OFFSET__SHIFT                0x1a
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_DROP_EN__SHIFT                                 0x1b
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_AWADDR_31_28_VALUE__SHIFT                      0x1c
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_ENABLE_MASK                                    0x00000001L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_AWID_MASK                                      0x0000003EL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_FENCE_ENABLE_MASK                              0x00000040L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_RANGE_OFFSET_MASK                              0x0001FF80L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_RANGE_SIZE_MASK                                0x01FE0000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_64BIT_SUPPORT_DIS_MASK                         0x02000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_NEED_DEDUCT_RANGE_OFFSET_MASK                  0x04000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_DROP_EN_MASK                                   0x08000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_AWADDR_31_28_VALUE_MASK                        0xF0000000L
+//GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL1
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL1__S2A_DOORBELL_PORT2_TARGET_PORT_TYPE__SHIFT                       0x0
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL1__S2A_DOORBELL_PORT2_TARGET_DIEID__SHIFT                           0x2
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL1__S2A_DOORBELL_PORT2_TARGET_PORT_ID__SHIFT                         0x4
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL1__S2A_DOORBELL_PORT2_OVERRIDE_POISON_DATA__SHIFT                   0x6
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL1__S2A_DOORBELL_PORT2_4K_PAGE_DECODE_DISABLE__SHIFT                 0x7
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL1__S2A_DOORBELL_PORT2_TARGET_PORT_TYPE_MASK                         0x00000003L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL1__S2A_DOORBELL_PORT2_TARGET_DIEID_MASK                             0x0000000CL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL1__S2A_DOORBELL_PORT2_TARGET_PORT_ID_MASK                           0x00000030L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL1__S2A_DOORBELL_PORT2_OVERRIDE_POISON_DATA_MASK                     0x00000040L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_2_CTRL1__S2A_DOORBELL_PORT2_4K_PAGE_DECODE_DISABLE_MASK                   0x00000080L
+//GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_ENABLE__SHIFT                                  0x0
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_AWID__SHIFT                                    0x1
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_FENCE_ENABLE__SHIFT                            0x6
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_RANGE_OFFSET__SHIFT                            0x7
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_RANGE_SIZE__SHIFT                              0x11
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_64BIT_SUPPORT_DIS__SHIFT                       0x19
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_NEED_DEDUCT_RANGE_OFFSET__SHIFT                0x1a
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_DROP_EN__SHIFT                                 0x1b
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_AWADDR_31_28_VALUE__SHIFT                      0x1c
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_ENABLE_MASK                                    0x00000001L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_AWID_MASK                                      0x0000003EL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_FENCE_ENABLE_MASK                              0x00000040L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_RANGE_OFFSET_MASK                              0x0001FF80L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_RANGE_SIZE_MASK                                0x01FE0000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_64BIT_SUPPORT_DIS_MASK                         0x02000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_NEED_DEDUCT_RANGE_OFFSET_MASK                  0x04000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_DROP_EN_MASK                                   0x08000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_AWADDR_31_28_VALUE_MASK                        0xF0000000L
+//GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL1
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL1__S2A_DOORBELL_PORT3_TARGET_PORT_TYPE__SHIFT                       0x0
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL1__S2A_DOORBELL_PORT3_TARGET_DIEID__SHIFT                           0x2
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL1__S2A_DOORBELL_PORT3_TARGET_PORT_ID__SHIFT                         0x4
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL1__S2A_DOORBELL_PORT3_OVERRIDE_POISON_DATA__SHIFT                   0x6
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL1__S2A_DOORBELL_PORT3_4K_PAGE_DECODE_DISABLE__SHIFT                 0x7
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL1__S2A_DOORBELL_PORT3_TARGET_PORT_TYPE_MASK                         0x00000003L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL1__S2A_DOORBELL_PORT3_TARGET_DIEID_MASK                             0x0000000CL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL1__S2A_DOORBELL_PORT3_TARGET_PORT_ID_MASK                           0x00000030L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL1__S2A_DOORBELL_PORT3_OVERRIDE_POISON_DATA_MASK                     0x00000040L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_3_CTRL1__S2A_DOORBELL_PORT3_4K_PAGE_DECODE_DISABLE_MASK                   0x00000080L
+//GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_ENABLE__SHIFT                                  0x0
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_AWID__SHIFT                                    0x1
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_FENCE_ENABLE__SHIFT                            0x6
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_RANGE_OFFSET__SHIFT                            0x7
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_RANGE_SIZE__SHIFT                              0x11
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_64BIT_SUPPORT_DIS__SHIFT                       0x19
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_NEED_DEDUCT_RANGE_OFFSET__SHIFT                0x1a
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_DROP_EN__SHIFT                                 0x1b
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_AWADDR_31_28_VALUE__SHIFT                      0x1c
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_ENABLE_MASK                                    0x00000001L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_AWID_MASK                                      0x0000003EL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_FENCE_ENABLE_MASK                              0x00000040L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_RANGE_OFFSET_MASK                              0x0001FF80L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_RANGE_SIZE_MASK                                0x01FE0000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_64BIT_SUPPORT_DIS_MASK                         0x02000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_NEED_DEDUCT_RANGE_OFFSET_MASK                  0x04000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_DROP_EN_MASK                                   0x08000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_AWADDR_31_28_VALUE_MASK                        0xF0000000L
+//GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL1
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL1__S2A_DOORBELL_PORT4_TARGET_PORT_TYPE__SHIFT                       0x0
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL1__S2A_DOORBELL_PORT4_TARGET_DIEID__SHIFT                           0x2
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL1__S2A_DOORBELL_PORT4_TARGET_PORT_ID__SHIFT                         0x4
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL1__S2A_DOORBELL_PORT4_OVERRIDE_POISON_DATA__SHIFT                   0x6
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL1__S2A_DOORBELL_PORT4_4K_PAGE_DECODE_DISABLE__SHIFT                 0x7
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL1__S2A_DOORBELL_PORT4_TARGET_PORT_TYPE_MASK                         0x00000003L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL1__S2A_DOORBELL_PORT4_TARGET_DIEID_MASK                             0x0000000CL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL1__S2A_DOORBELL_PORT4_TARGET_PORT_ID_MASK                           0x00000030L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL1__S2A_DOORBELL_PORT4_OVERRIDE_POISON_DATA_MASK                     0x00000040L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_4_CTRL1__S2A_DOORBELL_PORT4_4K_PAGE_DECODE_DISABLE_MASK                   0x00000080L
+//GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_ENABLE__SHIFT                                  0x0
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_AWID__SHIFT                                    0x1
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_FENCE_ENABLE__SHIFT                            0x6
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_RANGE_OFFSET__SHIFT                            0x7
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_RANGE_SIZE__SHIFT                              0x11
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_64BIT_SUPPORT_DIS__SHIFT                       0x19
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_NEED_DEDUCT_RANGE_OFFSET__SHIFT                0x1a
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_DROP_EN__SHIFT                                 0x1b
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_AWADDR_31_28_VALUE__SHIFT                      0x1c
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_ENABLE_MASK                                    0x00000001L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_AWID_MASK                                      0x0000003EL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_FENCE_ENABLE_MASK                              0x00000040L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_RANGE_OFFSET_MASK                              0x0001FF80L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_RANGE_SIZE_MASK                                0x01FE0000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_64BIT_SUPPORT_DIS_MASK                         0x02000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_NEED_DEDUCT_RANGE_OFFSET_MASK                  0x04000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_DROP_EN_MASK                                   0x08000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_AWADDR_31_28_VALUE_MASK                        0xF0000000L
+//GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL1
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL1__S2A_DOORBELL_PORT5_TARGET_PORT_TYPE__SHIFT                       0x0
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL1__S2A_DOORBELL_PORT5_TARGET_DIEID__SHIFT                           0x2
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL1__S2A_DOORBELL_PORT5_TARGET_PORT_ID__SHIFT                         0x4
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL1__S2A_DOORBELL_PORT5_OVERRIDE_POISON_DATA__SHIFT                   0x6
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL1__S2A_DOORBELL_PORT5_4K_PAGE_DECODE_DISABLE__SHIFT                 0x7
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL1__S2A_DOORBELL_PORT5_TARGET_PORT_TYPE_MASK                         0x00000003L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL1__S2A_DOORBELL_PORT5_TARGET_DIEID_MASK                             0x0000000CL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL1__S2A_DOORBELL_PORT5_TARGET_PORT_ID_MASK                           0x00000030L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL1__S2A_DOORBELL_PORT5_OVERRIDE_POISON_DATA_MASK                     0x00000040L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_5_CTRL1__S2A_DOORBELL_PORT5_4K_PAGE_DECODE_DISABLE_MASK                   0x00000080L
+//GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_ENABLE__SHIFT                                  0x0
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_AWID__SHIFT                                    0x1
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_FENCE_ENABLE__SHIFT                            0x6
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_RANGE_OFFSET__SHIFT                            0x7
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_RANGE_SIZE__SHIFT                              0x11
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_64BIT_SUPPORT_DIS__SHIFT                       0x19
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_NEED_DEDUCT_RANGE_OFFSET__SHIFT                0x1a
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_DROP_EN__SHIFT                                 0x1b
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_AWADDR_31_28_VALUE__SHIFT                      0x1c
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_ENABLE_MASK                                    0x00000001L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_AWID_MASK                                      0x0000003EL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_FENCE_ENABLE_MASK                              0x00000040L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_RANGE_OFFSET_MASK                              0x0001FF80L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_RANGE_SIZE_MASK                                0x01FE0000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_64BIT_SUPPORT_DIS_MASK                         0x02000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_NEED_DEDUCT_RANGE_OFFSET_MASK                  0x04000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_DROP_EN_MASK                                   0x08000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_AWADDR_31_28_VALUE_MASK                        0xF0000000L
+//GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL1
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL1__S2A_DOORBELL_PORT6_TARGET_PORT_TYPE__SHIFT                       0x0
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL1__S2A_DOORBELL_PORT6_TARGET_DIEID__SHIFT                           0x2
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL1__S2A_DOORBELL_PORT6_TARGET_PORT_ID__SHIFT                         0x4
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL1__S2A_DOORBELL_PORT6_OVERRIDE_POISON_DATA__SHIFT                   0x6
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL1__S2A_DOORBELL_PORT6_4K_PAGE_DECODE_DISABLE__SHIFT                 0x7
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL1__S2A_DOORBELL_PORT6_TARGET_PORT_TYPE_MASK                         0x00000003L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL1__S2A_DOORBELL_PORT6_TARGET_DIEID_MASK                             0x0000000CL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL1__S2A_DOORBELL_PORT6_TARGET_PORT_ID_MASK                           0x00000030L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL1__S2A_DOORBELL_PORT6_OVERRIDE_POISON_DATA_MASK                     0x00000040L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_6_CTRL1__S2A_DOORBELL_PORT6_4K_PAGE_DECODE_DISABLE_MASK                   0x00000080L
+//GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_ENABLE__SHIFT                                  0x0
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_AWID__SHIFT                                    0x1
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_FENCE_ENABLE__SHIFT                            0x6
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_RANGE_OFFSET__SHIFT                            0x7
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_RANGE_SIZE__SHIFT                              0x11
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_64BIT_SUPPORT_DIS__SHIFT                       0x19
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_NEED_DEDUCT_RANGE_OFFSET__SHIFT                0x1a
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_DROP_EN__SHIFT                                 0x1b
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_AWADDR_31_28_VALUE__SHIFT                      0x1c
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_ENABLE_MASK                                    0x00000001L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_AWID_MASK                                      0x0000003EL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_FENCE_ENABLE_MASK                              0x00000040L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_RANGE_OFFSET_MASK                              0x0001FF80L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_RANGE_SIZE_MASK                                0x01FE0000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_64BIT_SUPPORT_DIS_MASK                         0x02000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_NEED_DEDUCT_RANGE_OFFSET_MASK                  0x04000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_DROP_EN_MASK                                   0x08000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_AWADDR_31_28_VALUE_MASK                        0xF0000000L
+//GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL1
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL1__S2A_DOORBELL_PORT7_TARGET_PORT_TYPE__SHIFT                       0x0
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL1__S2A_DOORBELL_PORT7_TARGET_DIEID__SHIFT                           0x2
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL1__S2A_DOORBELL_PORT7_TARGET_PORT_ID__SHIFT                         0x4
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL1__S2A_DOORBELL_PORT7_OVERRIDE_POISON_DATA__SHIFT                   0x6
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL1__S2A_DOORBELL_PORT7_4K_PAGE_DECODE_DISABLE__SHIFT                 0x7
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL1__S2A_DOORBELL_PORT7_TARGET_PORT_TYPE_MASK                         0x00000003L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL1__S2A_DOORBELL_PORT7_TARGET_DIEID_MASK                             0x0000000CL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL1__S2A_DOORBELL_PORT7_TARGET_PORT_ID_MASK                           0x00000030L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL1__S2A_DOORBELL_PORT7_OVERRIDE_POISON_DATA_MASK                     0x00000040L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_7_CTRL1__S2A_DOORBELL_PORT7_4K_PAGE_DECODE_DISABLE_MASK                   0x00000080L
+//GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_ENABLE__SHIFT                                  0x0
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_AWID__SHIFT                                    0x1
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_FENCE_ENABLE__SHIFT                            0x6
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_RANGE_OFFSET__SHIFT                            0x7
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_RANGE_SIZE__SHIFT                              0x11
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_64BIT_SUPPORT_DIS__SHIFT                       0x19
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_NEED_DEDUCT_RANGE_OFFSET__SHIFT                0x1a
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_DROP_EN__SHIFT                                 0x1b
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_AWADDR_31_28_VALUE__SHIFT                      0x1c
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_ENABLE_MASK                                    0x00000001L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_AWID_MASK                                      0x0000003EL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_FENCE_ENABLE_MASK                              0x00000040L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_RANGE_OFFSET_MASK                              0x0001FF80L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_RANGE_SIZE_MASK                                0x01FE0000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_64BIT_SUPPORT_DIS_MASK                         0x02000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_NEED_DEDUCT_RANGE_OFFSET_MASK                  0x04000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_DROP_EN_MASK                                   0x08000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_AWADDR_31_28_VALUE_MASK                        0xF0000000L
+//GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL1
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL1__S2A_DOORBELL_PORT8_TARGET_PORT_TYPE__SHIFT                       0x0
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL1__S2A_DOORBELL_PORT8_TARGET_DIEID__SHIFT                           0x2
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL1__S2A_DOORBELL_PORT8_TARGET_PORT_ID__SHIFT                         0x4
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL1__S2A_DOORBELL_PORT8_OVERRIDE_POISON_DATA__SHIFT                   0x6
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL1__S2A_DOORBELL_PORT8_4K_PAGE_DECODE_DISABLE__SHIFT                 0x7
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL1__S2A_DOORBELL_PORT8_TARGET_PORT_TYPE_MASK                         0x00000003L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL1__S2A_DOORBELL_PORT8_TARGET_DIEID_MASK                             0x0000000CL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL1__S2A_DOORBELL_PORT8_TARGET_PORT_ID_MASK                           0x00000030L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL1__S2A_DOORBELL_PORT8_OVERRIDE_POISON_DATA_MASK                     0x00000040L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_8_CTRL1__S2A_DOORBELL_PORT8_4K_PAGE_DECODE_DISABLE_MASK                   0x00000080L
+//GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_ENABLE__SHIFT                                  0x0
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_AWID__SHIFT                                    0x1
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_FENCE_ENABLE__SHIFT                            0x6
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_RANGE_OFFSET__SHIFT                            0x7
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_RANGE_SIZE__SHIFT                              0x11
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_64BIT_SUPPORT_DIS__SHIFT                       0x19
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_NEED_DEDUCT_RANGE_OFFSET__SHIFT                0x1a
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_DROP_EN__SHIFT                                 0x1b
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_AWADDR_31_28_VALUE__SHIFT                      0x1c
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_ENABLE_MASK                                    0x00000001L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_AWID_MASK                                      0x0000003EL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_FENCE_ENABLE_MASK                              0x00000040L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_RANGE_OFFSET_MASK                              0x0001FF80L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_RANGE_SIZE_MASK                                0x01FE0000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_64BIT_SUPPORT_DIS_MASK                         0x02000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_NEED_DEDUCT_RANGE_OFFSET_MASK                  0x04000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_DROP_EN_MASK                                   0x08000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_AWADDR_31_28_VALUE_MASK                        0xF0000000L
+//GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL1
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL1__S2A_DOORBELL_PORT9_TARGET_PORT_TYPE__SHIFT                       0x0
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL1__S2A_DOORBELL_PORT9_TARGET_DIEID__SHIFT                           0x2
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL1__S2A_DOORBELL_PORT9_TARGET_PORT_ID__SHIFT                         0x4
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL1__S2A_DOORBELL_PORT9_OVERRIDE_POISON_DATA__SHIFT                   0x6
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL1__S2A_DOORBELL_PORT9_4K_PAGE_DECODE_DISABLE__SHIFT                 0x7
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL1__S2A_DOORBELL_PORT9_TARGET_PORT_TYPE_MASK                         0x00000003L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL1__S2A_DOORBELL_PORT9_TARGET_DIEID_MASK                             0x0000000CL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL1__S2A_DOORBELL_PORT9_TARGET_PORT_ID_MASK                           0x00000030L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL1__S2A_DOORBELL_PORT9_OVERRIDE_POISON_DATA_MASK                     0x00000040L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_9_CTRL1__S2A_DOORBELL_PORT9_4K_PAGE_DECODE_DISABLE_MASK                   0x00000080L
+//GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_ENABLE__SHIFT                                0x0
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_AWID__SHIFT                                  0x1
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_FENCE_ENABLE__SHIFT                          0x6
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_RANGE_OFFSET__SHIFT                          0x7
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_RANGE_SIZE__SHIFT                            0x11
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_64BIT_SUPPORT_DIS__SHIFT                     0x19
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_NEED_DEDUCT_RANGE_OFFSET__SHIFT              0x1a
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_DROP_EN__SHIFT                               0x1b
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_AWADDR_31_28_VALUE__SHIFT                    0x1c
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_ENABLE_MASK                                  0x00000001L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_AWID_MASK                                    0x0000003EL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_FENCE_ENABLE_MASK                            0x00000040L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_RANGE_OFFSET_MASK                            0x0001FF80L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_RANGE_SIZE_MASK                              0x01FE0000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_64BIT_SUPPORT_DIS_MASK                       0x02000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_NEED_DEDUCT_RANGE_OFFSET_MASK                0x04000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_DROP_EN_MASK                                 0x08000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_AWADDR_31_28_VALUE_MASK                      0xF0000000L
+//GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL1
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL1__S2A_DOORBELL_PORT10_TARGET_PORT_TYPE__SHIFT                     0x0
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL1__S2A_DOORBELL_PORT10_TARGET_DIEID__SHIFT                         0x2
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL1__S2A_DOORBELL_PORT10_TARGET_PORT_ID__SHIFT                       0x4
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL1__S2A_DOORBELL_PORT10_OVERRIDE_POISON_DATA__SHIFT                 0x6
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL1__S2A_DOORBELL_PORT10_4K_PAGE_DECODE_DISABLE__SHIFT               0x7
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL1__S2A_DOORBELL_PORT10_TARGET_PORT_TYPE_MASK                       0x00000003L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL1__S2A_DOORBELL_PORT10_TARGET_DIEID_MASK                           0x0000000CL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL1__S2A_DOORBELL_PORT10_TARGET_PORT_ID_MASK                         0x00000030L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL1__S2A_DOORBELL_PORT10_OVERRIDE_POISON_DATA_MASK                   0x00000040L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_10_CTRL1__S2A_DOORBELL_PORT10_4K_PAGE_DECODE_DISABLE_MASK                 0x00000080L
+//GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_ENABLE__SHIFT                                0x0
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_AWID__SHIFT                                  0x1
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_FENCE_ENABLE__SHIFT                          0x6
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_RANGE_OFFSET__SHIFT                          0x7
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_RANGE_SIZE__SHIFT                            0x11
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_64BIT_SUPPORT_DIS__SHIFT                     0x19
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_NEED_DEDUCT_RANGE_OFFSET__SHIFT              0x1a
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_DROP_EN__SHIFT                               0x1b
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_AWADDR_31_28_VALUE__SHIFT                    0x1c
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_ENABLE_MASK                                  0x00000001L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_AWID_MASK                                    0x0000003EL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_FENCE_ENABLE_MASK                            0x00000040L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_RANGE_OFFSET_MASK                            0x0001FF80L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_RANGE_SIZE_MASK                              0x01FE0000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_64BIT_SUPPORT_DIS_MASK                       0x02000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_NEED_DEDUCT_RANGE_OFFSET_MASK                0x04000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_DROP_EN_MASK                                 0x08000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_AWADDR_31_28_VALUE_MASK                      0xF0000000L
+//GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL1
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL1__S2A_DOORBELL_PORT11_TARGET_PORT_TYPE__SHIFT                     0x0
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL1__S2A_DOORBELL_PORT11_TARGET_DIEID__SHIFT                         0x2
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL1__S2A_DOORBELL_PORT11_TARGET_PORT_ID__SHIFT                       0x4
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL1__S2A_DOORBELL_PORT11_OVERRIDE_POISON_DATA__SHIFT                 0x6
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL1__S2A_DOORBELL_PORT11_4K_PAGE_DECODE_DISABLE__SHIFT               0x7
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL1__S2A_DOORBELL_PORT11_TARGET_PORT_TYPE_MASK                       0x00000003L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL1__S2A_DOORBELL_PORT11_TARGET_DIEID_MASK                           0x0000000CL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL1__S2A_DOORBELL_PORT11_TARGET_PORT_ID_MASK                         0x00000030L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL1__S2A_DOORBELL_PORT11_OVERRIDE_POISON_DATA_MASK                   0x00000040L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_11_CTRL1__S2A_DOORBELL_PORT11_4K_PAGE_DECODE_DISABLE_MASK                 0x00000080L
+//GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_ENABLE__SHIFT                                0x0
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_AWID__SHIFT                                  0x1
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_FENCE_ENABLE__SHIFT                          0x6
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_RANGE_OFFSET__SHIFT                          0x7
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_RANGE_SIZE__SHIFT                            0x11
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_64BIT_SUPPORT_DIS__SHIFT                     0x19
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_NEED_DEDUCT_RANGE_OFFSET__SHIFT              0x1a
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_DROP_EN__SHIFT                               0x1b
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_AWADDR_31_28_VALUE__SHIFT                    0x1c
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_ENABLE_MASK                                  0x00000001L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_AWID_MASK                                    0x0000003EL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_FENCE_ENABLE_MASK                            0x00000040L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_RANGE_OFFSET_MASK                            0x0001FF80L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_RANGE_SIZE_MASK                              0x01FE0000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_64BIT_SUPPORT_DIS_MASK                       0x02000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_NEED_DEDUCT_RANGE_OFFSET_MASK                0x04000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_DROP_EN_MASK                                 0x08000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_AWADDR_31_28_VALUE_MASK                      0xF0000000L
+//GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL1
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL1__S2A_DOORBELL_PORT12_TARGET_PORT_TYPE__SHIFT                     0x0
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL1__S2A_DOORBELL_PORT12_TARGET_DIEID__SHIFT                         0x2
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL1__S2A_DOORBELL_PORT12_TARGET_PORT_ID__SHIFT                       0x4
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL1__S2A_DOORBELL_PORT12_OVERRIDE_POISON_DATA__SHIFT                 0x6
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL1__S2A_DOORBELL_PORT12_4K_PAGE_DECODE_DISABLE__SHIFT               0x7
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL1__S2A_DOORBELL_PORT12_TARGET_PORT_TYPE_MASK                       0x00000003L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL1__S2A_DOORBELL_PORT12_TARGET_DIEID_MASK                           0x0000000CL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL1__S2A_DOORBELL_PORT12_TARGET_PORT_ID_MASK                         0x00000030L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL1__S2A_DOORBELL_PORT12_OVERRIDE_POISON_DATA_MASK                   0x00000040L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_12_CTRL1__S2A_DOORBELL_PORT12_4K_PAGE_DECODE_DISABLE_MASK                 0x00000080L
+//GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_ENABLE__SHIFT                                0x0
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_AWID__SHIFT                                  0x1
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_FENCE_ENABLE__SHIFT                          0x6
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_RANGE_OFFSET__SHIFT                          0x7
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_RANGE_SIZE__SHIFT                            0x11
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_64BIT_SUPPORT_DIS__SHIFT                     0x19
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_NEED_DEDUCT_RANGE_OFFSET__SHIFT              0x1a
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_DROP_EN__SHIFT                               0x1b
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_AWADDR_31_28_VALUE__SHIFT                    0x1c
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_ENABLE_MASK                                  0x00000001L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_AWID_MASK                                    0x0000003EL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_FENCE_ENABLE_MASK                            0x00000040L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_RANGE_OFFSET_MASK                            0x0001FF80L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_RANGE_SIZE_MASK                              0x01FE0000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_64BIT_SUPPORT_DIS_MASK                       0x02000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_NEED_DEDUCT_RANGE_OFFSET_MASK                0x04000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_DROP_EN_MASK                                 0x08000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_AWADDR_31_28_VALUE_MASK                      0xF0000000L
+//GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL1
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL1__S2A_DOORBELL_PORT13_TARGET_PORT_TYPE__SHIFT                     0x0
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL1__S2A_DOORBELL_PORT13_TARGET_DIEID__SHIFT                         0x2
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL1__S2A_DOORBELL_PORT13_TARGET_PORT_ID__SHIFT                       0x4
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL1__S2A_DOORBELL_PORT13_OVERRIDE_POISON_DATA__SHIFT                 0x6
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL1__S2A_DOORBELL_PORT13_4K_PAGE_DECODE_DISABLE__SHIFT               0x7
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL1__S2A_DOORBELL_PORT13_TARGET_PORT_TYPE_MASK                       0x00000003L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL1__S2A_DOORBELL_PORT13_TARGET_DIEID_MASK                           0x0000000CL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL1__S2A_DOORBELL_PORT13_TARGET_PORT_ID_MASK                         0x00000030L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL1__S2A_DOORBELL_PORT13_OVERRIDE_POISON_DATA_MASK                   0x00000040L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_13_CTRL1__S2A_DOORBELL_PORT13_4K_PAGE_DECODE_DISABLE_MASK                 0x00000080L
+//GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_ENABLE__SHIFT                                0x0
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_AWID__SHIFT                                  0x1
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_FENCE_ENABLE__SHIFT                          0x6
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_RANGE_OFFSET__SHIFT                          0x7
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_RANGE_SIZE__SHIFT                            0x11
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_64BIT_SUPPORT_DIS__SHIFT                     0x19
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_NEED_DEDUCT_RANGE_OFFSET__SHIFT              0x1a
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_DROP_EN__SHIFT                               0x1b
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_AWADDR_31_28_VALUE__SHIFT                    0x1c
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_ENABLE_MASK                                  0x00000001L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_AWID_MASK                                    0x0000003EL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_FENCE_ENABLE_MASK                            0x00000040L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_RANGE_OFFSET_MASK                            0x0001FF80L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_RANGE_SIZE_MASK                              0x01FE0000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_64BIT_SUPPORT_DIS_MASK                       0x02000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_NEED_DEDUCT_RANGE_OFFSET_MASK                0x04000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_DROP_EN_MASK                                 0x08000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_AWADDR_31_28_VALUE_MASK                      0xF0000000L
+//GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL1
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL1__S2A_DOORBELL_PORT14_TARGET_PORT_TYPE__SHIFT                     0x0
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL1__S2A_DOORBELL_PORT14_TARGET_DIEID__SHIFT                         0x2
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL1__S2A_DOORBELL_PORT14_TARGET_PORT_ID__SHIFT                       0x4
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL1__S2A_DOORBELL_PORT14_OVERRIDE_POISON_DATA__SHIFT                 0x6
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL1__S2A_DOORBELL_PORT14_4K_PAGE_DECODE_DISABLE__SHIFT               0x7
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL1__S2A_DOORBELL_PORT14_TARGET_PORT_TYPE_MASK                       0x00000003L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL1__S2A_DOORBELL_PORT14_TARGET_DIEID_MASK                           0x0000000CL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL1__S2A_DOORBELL_PORT14_TARGET_PORT_ID_MASK                         0x00000030L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL1__S2A_DOORBELL_PORT14_OVERRIDE_POISON_DATA_MASK                   0x00000040L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_14_CTRL1__S2A_DOORBELL_PORT14_4K_PAGE_DECODE_DISABLE_MASK                 0x00000080L
+//GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_ENABLE__SHIFT                                0x0
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_AWID__SHIFT                                  0x1
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_FENCE_ENABLE__SHIFT                          0x6
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_RANGE_OFFSET__SHIFT                          0x7
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_RANGE_SIZE__SHIFT                            0x11
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_64BIT_SUPPORT_DIS__SHIFT                     0x19
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_NEED_DEDUCT_RANGE_OFFSET__SHIFT              0x1a
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_DROP_EN__SHIFT                               0x1b
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_AWADDR_31_28_VALUE__SHIFT                    0x1c
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_ENABLE_MASK                                  0x00000001L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_AWID_MASK                                    0x0000003EL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_FENCE_ENABLE_MASK                            0x00000040L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_RANGE_OFFSET_MASK                            0x0001FF80L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_RANGE_SIZE_MASK                              0x01FE0000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_64BIT_SUPPORT_DIS_MASK                       0x02000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_NEED_DEDUCT_RANGE_OFFSET_MASK                0x04000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_DROP_EN_MASK                                 0x08000000L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_AWADDR_31_28_VALUE_MASK                      0xF0000000L
+//GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL1
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL1__S2A_DOORBELL_PORT15_TARGET_PORT_TYPE__SHIFT                     0x0
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL1__S2A_DOORBELL_PORT15_TARGET_DIEID__SHIFT                         0x2
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL1__S2A_DOORBELL_PORT15_TARGET_PORT_ID__SHIFT                       0x4
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL1__S2A_DOORBELL_PORT15_OVERRIDE_POISON_DATA__SHIFT                 0x6
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL1__S2A_DOORBELL_PORT15_4K_PAGE_DECODE_DISABLE__SHIFT               0x7
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL1__S2A_DOORBELL_PORT15_TARGET_PORT_TYPE_MASK                       0x00000003L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL1__S2A_DOORBELL_PORT15_TARGET_DIEID_MASK                           0x0000000CL
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL1__S2A_DOORBELL_PORT15_TARGET_PORT_ID_MASK                         0x00000030L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL1__S2A_DOORBELL_PORT15_OVERRIDE_POISON_DATA_MASK                   0x00000040L
+#define GDC_S2A0_S2A_DOORBELL_ENTRY_15_CTRL1__S2A_DOORBELL_PORT15_4K_PAGE_DECODE_DISABLE_MASK                 0x00000080L
+//GDC_S2A0_S2A_DOORBELL_COMMON_CTRL_REG
+#define GDC_S2A0_S2A_DOORBELL_COMMON_CTRL_REG__S2A_DOORBELL_FENCE_ONCE_TRIGGER_DIS__SHIFT                     0x0
+#define GDC_S2A0_S2A_DOORBELL_COMMON_CTRL_REG__S2A_DOORBE_FENCE_INTR_ENABLE__SHIFT                            0x1
+#define GDC_S2A0_S2A_DOORBELL_COMMON_CTRL_REG__S2A_DOORBELL_FENCE_ONCE_TRIGGER_DIS_MASK                       0x00000001L
+#define GDC_S2A0_S2A_DOORBELL_COMMON_CTRL_REG__S2A_DOORBE_FENCE_INTR_ENABLE_MASK                              0x00000002L
+//GDC_S2A0_NBIF_GFX_DOORBELL_STATUS
+#define GDC_S2A0_NBIF_GFX_DOORBELL_STATUS__NBIF_GFX_DOORBELL_SENT__SHIFT                                      0x0
+#define GDC_S2A0_NBIF_GFX_DOORBELL_STATUS__S2A_DOORBELL_ALL_CLR_EN__SHIFT                                     0x10
+#define GDC_S2A0_NBIF_GFX_DOORBELL_STATUS__S2A_DOORBELL_ALL_CLR_ST__SHIFT                                     0x18
+#define GDC_S2A0_NBIF_GFX_DOORBELL_STATUS__NBIF_GFX_DOORBELL_SENT_MASK                                        0x0000FFFFL
+#define GDC_S2A0_NBIF_GFX_DOORBELL_STATUS__S2A_DOORBELL_ALL_CLR_EN_MASK                                       0x00010000L
+#define GDC_S2A0_NBIF_GFX_DOORBELL_STATUS__S2A_DOORBELL_ALL_CLR_ST_MASK                                       0x01000000L
+
+
+// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VENDOR_ID__VENDOR_ID__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF0_VENDOR_ID__VENDOR_ID_MASK                                                           0xFFFFL
+//BIF_CFG_DEV0_EPF0_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_DEVICE_ID__DEVICE_ID__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF0_DEVICE_ID__DEVICE_ID_MASK                                                           0xFFFFL
+//BIF_CFG_DEV0_EPF0_COMMAND
+#define BIF_CFG_DEV0_EPF0_COMMAND__IO_ACCESS_EN__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_EPF0_COMMAND__MEM_ACCESS_EN__SHIFT                                                       0x1
+#define BIF_CFG_DEV0_EPF0_COMMAND__BUS_MASTER_EN__SHIFT                                                       0x2
+#define BIF_CFG_DEV0_EPF0_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                    0x3
+#define BIF_CFG_DEV0_EPF0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                             0x4
+#define BIF_CFG_DEV0_EPF0_COMMAND__PAL_SNOOP_EN__SHIFT                                                        0x5
+#define BIF_CFG_DEV0_EPF0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                               0x6
+#define BIF_CFG_DEV0_EPF0_COMMAND__AD_STEPPING__SHIFT                                                         0x7
+#define BIF_CFG_DEV0_EPF0_COMMAND__SERR_EN__SHIFT                                                             0x8
+#define BIF_CFG_DEV0_EPF0_COMMAND__FAST_B2B_EN__SHIFT                                                         0x9
+#define BIF_CFG_DEV0_EPF0_COMMAND__INT_DIS__SHIFT                                                             0xa
+#define BIF_CFG_DEV0_EPF0_COMMAND__IO_ACCESS_EN_MASK                                                          0x0001L
+#define BIF_CFG_DEV0_EPF0_COMMAND__MEM_ACCESS_EN_MASK                                                         0x0002L
+#define BIF_CFG_DEV0_EPF0_COMMAND__BUS_MASTER_EN_MASK                                                         0x0004L
+#define BIF_CFG_DEV0_EPF0_COMMAND__SPECIAL_CYCLE_EN_MASK                                                      0x0008L
+#define BIF_CFG_DEV0_EPF0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                               0x0010L
+#define BIF_CFG_DEV0_EPF0_COMMAND__PAL_SNOOP_EN_MASK                                                          0x0020L
+#define BIF_CFG_DEV0_EPF0_COMMAND__PARITY_ERROR_RESPONSE_MASK                                                 0x0040L
+#define BIF_CFG_DEV0_EPF0_COMMAND__AD_STEPPING_MASK                                                           0x0080L
+#define BIF_CFG_DEV0_EPF0_COMMAND__SERR_EN_MASK                                                               0x0100L
+#define BIF_CFG_DEV0_EPF0_COMMAND__FAST_B2B_EN_MASK                                                           0x0200L
+#define BIF_CFG_DEV0_EPF0_COMMAND__INT_DIS_MASK                                                               0x0400L
+//BIF_CFG_DEV0_EPF0_STATUS
+#define BIF_CFG_DEV0_EPF0_STATUS__IMMEDIATE_READINESS__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF0_STATUS__INT_STATUS__SHIFT                                                           0x3
+#define BIF_CFG_DEV0_EPF0_STATUS__CAP_LIST__SHIFT                                                             0x4
+#define BIF_CFG_DEV0_EPF0_STATUS__PCI_66_CAP__SHIFT                                                           0x5
+#define BIF_CFG_DEV0_EPF0_STATUS__FAST_BACK_CAPABLE__SHIFT                                                    0x7
+#define BIF_CFG_DEV0_EPF0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                             0x8
+#define BIF_CFG_DEV0_EPF0_STATUS__DEVSEL_TIMING__SHIFT                                                        0x9
+#define BIF_CFG_DEV0_EPF0_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                  0xb
+#define BIF_CFG_DEV0_EPF0_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                                0xc
+#define BIF_CFG_DEV0_EPF0_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                                0xd
+#define BIF_CFG_DEV0_EPF0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                                0xe
+#define BIF_CFG_DEV0_EPF0_STATUS__PARITY_ERROR_DETECTED__SHIFT                                                0xf
+#define BIF_CFG_DEV0_EPF0_STATUS__IMMEDIATE_READINESS_MASK                                                    0x0001L
+#define BIF_CFG_DEV0_EPF0_STATUS__INT_STATUS_MASK                                                             0x0008L
+#define BIF_CFG_DEV0_EPF0_STATUS__CAP_LIST_MASK                                                               0x0010L
+#define BIF_CFG_DEV0_EPF0_STATUS__PCI_66_CAP_MASK                                                             0x0020L
+#define BIF_CFG_DEV0_EPF0_STATUS__FAST_BACK_CAPABLE_MASK                                                      0x0080L
+#define BIF_CFG_DEV0_EPF0_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                               0x0100L
+#define BIF_CFG_DEV0_EPF0_STATUS__DEVSEL_TIMING_MASK                                                          0x0600L
+#define BIF_CFG_DEV0_EPF0_STATUS__SIGNAL_TARGET_ABORT_MASK                                                    0x0800L
+#define BIF_CFG_DEV0_EPF0_STATUS__RECEIVED_TARGET_ABORT_MASK                                                  0x1000L
+#define BIF_CFG_DEV0_EPF0_STATUS__RECEIVED_MASTER_ABORT_MASK                                                  0x2000L
+#define BIF_CFG_DEV0_EPF0_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                  0x4000L
+#define BIF_CFG_DEV0_EPF0_STATUS__PARITY_ERROR_DETECTED_MASK                                                  0x8000L
+//BIF_CFG_DEV0_EPF0_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_REVISION_ID__MINOR_REV_ID__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF0_REVISION_ID__MAJOR_REV_ID__SHIFT                                                    0x4
+#define BIF_CFG_DEV0_EPF0_REVISION_ID__MINOR_REV_ID_MASK                                                      0x0FL
+#define BIF_CFG_DEV0_EPF0_REVISION_ID__MAJOR_REV_ID_MASK                                                      0xF0L
+//BIF_CFG_DEV0_EPF0_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF0_PROG_INTERFACE__PROG_INTERFACE_MASK                                                 0xFFL
+//BIF_CFG_DEV0_EPF0_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_SUB_CLASS__SUB_CLASS__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF0_SUB_CLASS__SUB_CLASS_MASK                                                           0xFFL
+//BIF_CFG_DEV0_EPF0_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_BASE_CLASS__BASE_CLASS__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF0_BASE_CLASS__BASE_CLASS_MASK                                                         0xFFL
+//BIF_CFG_DEV0_EPF0_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF0_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                    0xFFL
+//BIF_CFG_DEV0_EPF0_LATENCY
+#define BIF_CFG_DEV0_EPF0_LATENCY__LATENCY_TIMER__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF0_LATENCY__LATENCY_TIMER_MASK                                                         0xFFL
+//BIF_CFG_DEV0_EPF0_HEADER
+#define BIF_CFG_DEV0_EPF0_HEADER__HEADER_TYPE__SHIFT                                                          0x0
+#define BIF_CFG_DEV0_EPF0_HEADER__DEVICE_TYPE__SHIFT                                                          0x7
+#define BIF_CFG_DEV0_EPF0_HEADER__HEADER_TYPE_MASK                                                            0x7FL
+#define BIF_CFG_DEV0_EPF0_HEADER__DEVICE_TYPE_MASK                                                            0x80L
+//BIF_CFG_DEV0_EPF0_BIST
+#define BIF_CFG_DEV0_EPF0_BIST__BIST_COMP__SHIFT                                                              0x0
+#define BIF_CFG_DEV0_EPF0_BIST__BIST_STRT__SHIFT                                                              0x6
+#define BIF_CFG_DEV0_EPF0_BIST__BIST_CAP__SHIFT                                                               0x7
+#define BIF_CFG_DEV0_EPF0_BIST__BIST_COMP_MASK                                                                0x0FL
+#define BIF_CFG_DEV0_EPF0_BIST__BIST_STRT_MASK                                                                0x40L
+#define BIF_CFG_DEV0_EPF0_BIST__BIST_CAP_MASK                                                                 0x80L
+//BIF_CFG_DEV0_EPF0_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_BASE_ADDR_1__BASE_ADDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF0_BASE_ADDR_1__BASE_ADDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_BASE_ADDR_2__BASE_ADDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF0_BASE_ADDR_2__BASE_ADDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_BASE_ADDR_3__BASE_ADDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF0_BASE_ADDR_3__BASE_ADDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_BASE_ADDR_4__BASE_ADDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF0_BASE_ADDR_4__BASE_ADDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_BASE_ADDR_5__BASE_ADDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF0_BASE_ADDR_5__BASE_ADDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_BASE_ADDR_6__BASE_ADDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF0_BASE_ADDR_6__BASE_ADDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                                     0x10
+#define BIF_CFG_DEV0_EPF0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                       0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT                                         0x1
+#define BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT                                        0x4
+#define BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                     0xb
+#define BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__ROM_ENABLE_MASK                                                      0x00000001L
+#define BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK                                           0x0000000EL
+#define BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK                                          0x000000F0L
+#define BIF_CFG_DEV0_EPF0_ROM_BASE_ADDR__BASE_ADDR_MASK                                                       0xFFFFF800L
+//BIF_CFG_DEV0_EPF0_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_CAP_PTR__CAP_PTR__SHIFT                                                             0x0
+#define BIF_CFG_DEV0_EPF0_CAP_PTR__CAP_PTR_MASK                                                               0xFFL
+//BIF_CFG_DEV0_EPF0_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF0_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                                 0xFFL
+//BIF_CFG_DEV0_EPF0_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF0_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                   0xFFL
+//BIF_CFG_DEV0_EPF0_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_MIN_GRANT__MIN_GNT__SHIFT                                                           0x0
+#define BIF_CFG_DEV0_EPF0_MIN_GRANT__MIN_GNT_MASK                                                             0xFFL
+//BIF_CFG_DEV0_EPF0_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_MAX_LATENCY__MAX_LAT__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF0_MAX_LATENCY__MAX_LAT_MASK                                                           0xFFL
+//VENDOR_CAP_LIST
+#define VENDOR_CAP_LIST__CAP_ID__SHIFT                                                                        0x0
+#define VENDOR_CAP_LIST__NEXT_PTR__SHIFT                                                                      0x8
+#define VENDOR_CAP_LIST__LENGTH__SHIFT                                                                        0x10
+#define VENDOR_CAP_LIST__CAP_ID_MASK                                                                          0x000000FFL
+#define VENDOR_CAP_LIST__NEXT_PTR_MASK                                                                        0x0000FF00L
+#define VENDOR_CAP_LIST__LENGTH_MASK                                                                          0x00FF0000L
+//ADAPTER_ID_W
+#define ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT                                                              0x0
+#define ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT                                                                     0x10
+#define ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK                                                                0x0000FFFFL
+#define ADAPTER_ID_W__SUBSYSTEM_ID_MASK                                                                       0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PMI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PMI_CAP_LIST__CAP_ID__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF0_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                       0x8
+#define BIF_CFG_DEV0_EPF0_PMI_CAP_LIST__CAP_ID_MASK                                                           0x00FFL
+#define BIF_CFG_DEV0_EPF0_PMI_CAP_LIST__NEXT_PTR_MASK                                                         0xFF00L
+//BIF_CFG_DEV0_EPF0_PMI_CAP
+#define BIF_CFG_DEV0_EPF0_PMI_CAP__VERSION__SHIFT                                                             0x0
+#define BIF_CFG_DEV0_EPF0_PMI_CAP__PME_CLOCK__SHIFT                                                           0x3
+#define BIF_CFG_DEV0_EPF0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                                 0x4
+#define BIF_CFG_DEV0_EPF0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                   0x5
+#define BIF_CFG_DEV0_EPF0_PMI_CAP__AUX_CURRENT__SHIFT                                                         0x6
+#define BIF_CFG_DEV0_EPF0_PMI_CAP__D1_SUPPORT__SHIFT                                                          0x9
+#define BIF_CFG_DEV0_EPF0_PMI_CAP__D2_SUPPORT__SHIFT                                                          0xa
+#define BIF_CFG_DEV0_EPF0_PMI_CAP__PME_SUPPORT__SHIFT                                                         0xb
+#define BIF_CFG_DEV0_EPF0_PMI_CAP__VERSION_MASK                                                               0x0007L
+#define BIF_CFG_DEV0_EPF0_PMI_CAP__PME_CLOCK_MASK                                                             0x0008L
+#define BIF_CFG_DEV0_EPF0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                   0x0010L
+#define BIF_CFG_DEV0_EPF0_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                     0x0020L
+#define BIF_CFG_DEV0_EPF0_PMI_CAP__AUX_CURRENT_MASK                                                           0x01C0L
+#define BIF_CFG_DEV0_EPF0_PMI_CAP__D1_SUPPORT_MASK                                                            0x0200L
+#define BIF_CFG_DEV0_EPF0_PMI_CAP__D2_SUPPORT_MASK                                                            0x0400L
+#define BIF_CFG_DEV0_EPF0_PMI_CAP__PME_SUPPORT_MASK                                                           0xF800L
+//BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                               0x3
+#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PME_EN__SHIFT                                                      0x8
+#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                                 0x9
+#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                  0xd
+#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                  0xf
+#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                               0x16
+#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                  0x17
+#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                    0x18
+#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__POWER_STATE_MASK                                                   0x00000003L
+#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                                 0x00000008L
+#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PME_EN_MASK                                                        0x00000100L
+#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                   0x00001E00L
+#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                    0x00006000L
+#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PME_STATUS_MASK                                                    0x00008000L
+#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                                 0x00400000L
+#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                    0x00800000L
+#define BIF_CFG_DEV0_EPF0_PMI_STATUS_CNTL__PMI_DATA_MASK                                                      0xFF000000L
+//BIF_CFG_DEV0_EPF0_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_CAP_LIST__CAP_ID__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                      0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_CAP_LIST__CAP_ID_MASK                                                          0x00FFL
+#define BIF_CFG_DEV0_EPF0_PCIE_CAP_LIST__NEXT_PTR_MASK                                                        0xFF00L
+//BIF_CFG_DEV0_EPF0_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_CAP__VERSION__SHIFT                                                            0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_CAP__DEVICE_TYPE__SHIFT                                                        0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                    0x9
+#define BIF_CFG_DEV0_EPF0_PCIE_CAP__FLIT_MODE_SUPPORT__SHIFT                                                  0xf
+#define BIF_CFG_DEV0_EPF0_PCIE_CAP__VERSION_MASK                                                              0x000FL
+#define BIF_CFG_DEV0_EPF0_PCIE_CAP__DEVICE_TYPE_MASK                                                          0x00F0L
+#define BIF_CFG_DEV0_EPF0_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                     0x0100L
+#define BIF_CFG_DEV0_EPF0_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                      0x3E00L
+#define BIF_CFG_DEV0_EPF0_PCIE_CAP__FLIT_MODE_SUPPORT_MASK                                                    0x8000L
+//BIF_CFG_DEV0_EPF0_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                     0x3
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                     0x5
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                           0x6
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                            0x9
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                         0xf
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT                                         0x10
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__RX_MPS_FIXED__SHIFT                                                     0x11
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                        0x12
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                        0x1a
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                      0x1c
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__MIXED_MPS_SUPPORTED__SHIFT                                              0x1d
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__TEE_IO_SUPPORT__SHIFT                                                   0x1e
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                                0x00000007L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__PHANTOM_FUNC_MASK                                                       0x00000018L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__EXTENDED_TAG_MASK                                                       0x00000020L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                             0x000001C0L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                              0x00000E00L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                           0x00008000L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK                                           0x00010000L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__RX_MPS_FIXED_MASK                                                       0x00020000L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                          0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                          0x0C000000L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__FLR_CAPABLE_MASK                                                        0x10000000L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__MIXED_MPS_SUPPORTED_MASK                                                0x20000000L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP__TEE_IO_SUPPORT_MASK                                                     0x40000000L
+//BIF_CFG_DEV0_EPF0_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                                0x1
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                    0x2
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                   0x3
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                  0x4
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                                0x5
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                                 0x8
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                                 0x9
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                                 0xa
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                     0xb
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                           0xc
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__INITIATE_FLR__SHIFT                                                    0xf
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__CORR_ERR_EN_MASK                                                       0x0001L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                  0x0002L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                      0x0004L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__USR_REPORT_EN_MASK                                                     0x0008L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                    0x0010L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                  0x00E0L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                   0x0100L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                   0x0200L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                   0x0400L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                       0x0800L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                             0x7000L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL__INITIATE_FLR_MASK                                                      0x8000L
+//BIF_CFG_DEV0_EPF0_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__CORR_ERR__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                                 0x1
+#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__FATAL_ERR__SHIFT                                                     0x2
+#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__USR_DETECTED__SHIFT                                                  0x3
+#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__AUX_PWR__SHIFT                                                       0x4
+#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                             0x5
+#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                                 0x6
+#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__CORR_ERR_MASK                                                        0x0001L
+#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                   0x0002L
+#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__FATAL_ERR_MASK                                                       0x0004L
+#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__USR_DETECTED_MASK                                                    0x0008L
+#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__AUX_PWR_MASK                                                         0x0010L
+#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                               0x0020L
+#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                   0x0040L
+//BIF_CFG_DEV0_EPF0_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                       0x4
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                        0x5
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                      0x6
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                      0x7
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                          0x9
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                       0xa
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                   0xb
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                              0xc
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                   0xe
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                                 0x10
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                                 0x11
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                  0x12
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                    0x14
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                    0x15
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                        0x16
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                  0x18
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                   0x1a
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                   0x1f
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                       0x0000000FL
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                         0x00000010L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                          0x00000020L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                        0x00000040L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                        0x00000080L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                        0x00000100L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                            0x00000200L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                         0x00000400L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                     0x00000800L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                                0x00003000L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                     0x0000C000L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                   0x00010000L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                   0x00020000L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                    0x000C0000L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                      0x00100000L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                      0x00200000L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                          0x00C00000L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                    0x03000000L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                     0x04000000L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                     0x80000000L
+//BIF_CFG_DEV0_EPF0_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                                0x4
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                            0x6
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                       0x7
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                             0x8
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                          0x9
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN__SHIFT                                                         0xa
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                   0xb
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                   0xc
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__OBFF_EN__SHIFT                                                        0xd
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                    0xf
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                                0x000FL
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                  0x0010L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                                0x0020L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                              0x0040L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                         0x0080L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                               0x0100L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                            0x0200L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__LTR_EN_MASK                                                           0x0400L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                     0x0800L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                     0x1000L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__OBFF_EN_MASK                                                          0x6000L
+#define BIF_CFG_DEV0_EPF0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                      0x8000L
+//BIF_CFG_DEV0_EPF0_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS2__RESERVED__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_DEVICE_STATUS2__RESERVED_MASK                                                       0xFFFFL
+//BIF_CFG_DEV0_EPF0_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_MSI_CAP_LIST__CAP_ID__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF0_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                       0x8
+#define BIF_CFG_DEV0_EPF0_MSI_CAP_LIST__CAP_ID_MASK                                                           0x00FFL
+#define BIF_CFG_DEV0_EPF0_MSI_CAP_LIST__NEXT_PTR_MASK                                                         0xFF00L
+//BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EN__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                  0x1
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                   0x4
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                      0x7
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT                                           0x9
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT                                            0xa
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EN_MASK                                                           0x0001L
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                    0x000EL
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                     0x0070L
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_64BIT_MASK                                                        0x0080L
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                        0x0100L
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK                                             0x0200L
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK                                              0x0400L
+//BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                             0x2
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                               0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_DATA__MSI_DATA__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_DATA__MSI_DATA_MASK                                                         0xFFFFL
+//BIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK                                                 0xFFFFL
+//BIF_CFG_DEV0_EPF0_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_MSI_MASK__MSI_MASK__SHIFT                                                           0x0
+#define BIF_CFG_DEV0_EPF0_MSI_MASK__MSI_MASK_MASK                                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF0_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                   0xFFFFL
+//BIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK                                           0xFFFFL
+//BIF_CFG_DEV0_EPF0_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_MSI_MASK_64__MSI_MASK_64__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_MSI_MASK_64__MSI_MASK_64_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_MSI_PENDING__MSI_PENDING__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_MSI_PENDING__MSI_PENDING_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF0_MSI_PENDING_64__MSI_PENDING_64_MASK                                                 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_MSIX_CAP_LIST__CAP_ID__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_EPF0_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                      0x8
+#define BIF_CFG_DEV0_EPF0_MSIX_CAP_LIST__CAP_ID_MASK                                                          0x00FFL
+#define BIF_CFG_DEV0_EPF0_MSIX_CAP_LIST__NEXT_PTR_MASK                                                        0xFF00L
+//BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                                0xe
+#define BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                       0xf
+#define BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                                 0x07FFL
+#define BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                                  0x4000L
+#define BIF_CFG_DEV0_EPF0_MSIX_MSG_CNTL__MSIX_EN_MASK                                                         0x8000L
+//BIF_CFG_DEV0_EPF0_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                                0x3
+#define BIF_CFG_DEV0_EPF0_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                                     0x00000007L
+#define BIF_CFG_DEV0_EPF0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                                  0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                                    0x3
+#define BIF_CFG_DEV0_EPF0_MSIX_PBA__MSIX_PBA_BIR_MASK                                                         0x00000007L
+#define BIF_CFG_DEV0_EPF0_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                      0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_PCIE_NULL2_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_NULL2_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_NULL2_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_NULL2_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_NULL2_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_NULL2_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_NULL2_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                       0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                      0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                         0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                        0xFFF00000L
+//BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                       0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                    0x5
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                       0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                        0xd
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                   0xe
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                                 0xf
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                      0x11
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                       0x12
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                      0x13
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                                0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                                 0x15
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                                0x16
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                                0x17
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                       0x18
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                        0x19
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                   0x1a
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__DMWR_REQUEST_EGRESS_BLOCKED_STATUS__SHIFT                   0x1b
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__IDE_CHECK_FAILED_STATUS__SHIFT                              0x1c
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__MISROUTED_IDE_TLP_STATUS__SHIFT                             0x1d
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__PCRC_CHECK_FAILED_STATUS__SHIFT                             0x1e
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                         0x00000010L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                      0x00000020L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                         0x00001000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                          0x00002000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                     0x00004000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                   0x00008000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                       0x00010000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                        0x00020000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                         0x00040000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                        0x00080000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                  0x00100000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                   0x00200000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                  0x00400000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                  0x00800000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                         0x01000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                          0x02000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                     0x04000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__DMWR_REQUEST_EGRESS_BLOCKED_STATUS_MASK                     0x08000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__IDE_CHECK_FAILED_STATUS_MASK                                0x10000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__MISROUTED_IDE_TLP_STATUS_MASK                               0x20000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_STATUS__PCRC_CHECK_FAILED_STATUS_MASK                               0x40000000L
+//BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                           0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                        0x5
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                           0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                            0xd
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                       0xe
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                     0xf
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                         0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                          0x11
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                           0x12
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                          0x13
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                    0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                     0x15
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                    0x16
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                    0x17
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                           0x18
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                            0x19
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                       0x1a
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__DMWR_REQUEST_EGRESS_BLOCKED_MASK__SHIFT                       0x1b
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__IDE_CHECK_FAILED_MASK__SHIFT                                  0x1c
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__MISROUTED_IDE_TLP_MASK__SHIFT                                 0x1d
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__PCRC_CHECK_FAILED_MASK__SHIFT                                 0x1e
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                             0x00000010L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                          0x00000020L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                             0x00001000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                              0x00002000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                         0x00004000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                       0x00008000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                           0x00010000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                            0x00020000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                             0x00040000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                            0x00080000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                      0x00100000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                       0x00200000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                      0x00400000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                      0x00800000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                             0x01000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                              0x02000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                         0x04000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__DMWR_REQUEST_EGRESS_BLOCKED_MASK_MASK                         0x08000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__IDE_CHECK_FAILED_MASK_MASK                                    0x10000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__MISROUTED_IDE_TLP_MASK_MASK                                   0x20000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_MASK__PCRC_CHECK_FAILED_MASK_MASK                                   0x40000000L
+//BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                   0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                                0x5
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                   0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                    0xd
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                               0xe
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                             0xf
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                                 0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                  0x11
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                   0x12
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                  0x13
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                            0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                             0x15
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                            0x16
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                            0x17
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                   0x18
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                    0x19
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT               0x1a
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__DMWR_REQUEST_EGRESS_BLOCKED_SEVERITY__SHIFT               0x1b
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__IDE_CHECK_FAILED_SEVERITY__SHIFT                          0x1c
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__MISROUTED_IDE_TLP_SEVERITY__SHIFT                         0x1d
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__PCRC_CHECK_FAILED_SEVERITY__SHIFT                         0x1e
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                     0x00000010L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                  0x00000020L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                     0x00001000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                      0x00002000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                                 0x00004000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                               0x00008000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                   0x00010000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                    0x00020000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                     0x00040000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                    0x00080000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                              0x00100000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                               0x00200000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                              0x00400000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                              0x00800000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                     0x01000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                      0x02000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK                 0x04000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__DMWR_REQUEST_EGRESS_BLOCKED_SEVERITY_MASK                 0x08000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__IDE_CHECK_FAILED_SEVERITY_MASK                            0x10000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__MISROUTED_IDE_TLP_SEVERITY_MASK                           0x20000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_UNCORR_ERR_SEVERITY__PCRC_CHECK_FAILED_SEVERITY_MASK                           0x40000000L
+//BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                         0x6
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                        0x7
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                             0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                            0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                           0xd
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                    0xe
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                                    0xf
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                           0x00000001L
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                           0x00000040L
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                          0x00000080L
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                               0x00000100L
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                              0x00001000L
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                             0x00002000L
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                      0x00004000L
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                      0x00008000L
+//BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                             0x6
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                            0x7
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                                 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                                0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                               0xd
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                        0xe
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                        0xf
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                               0x00000001L
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                               0x00000040L
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                              0x00000080L
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                   0x00000100L
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                  0x00001000L
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                                 0x00002000L
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                          0x00004000L
+#define BIF_CFG_DEV0_EPF0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                          0x00008000L
+//BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT                                          0x5
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT                                           0x6
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                        0x7
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                         0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                    0x9
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                     0xa
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                                0xb
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT                        0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__HEADER_LOG_SIZE__SHIFT                                       0xd
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_WAS_FLIT_MODE__SHIFT                              0x12
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_SIZE__SHIFT                                       0x13
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                           0x0000001FL
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK                                            0x00000020L
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK                                             0x00000040L
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                          0x00000080L
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                           0x00000100L
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                      0x00000200L
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                       0x00000400L
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                                  0x00000800L
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK                          0x00001000L
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__HEADER_LOG_SIZE_MASK                                         0x0003E000L
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_WAS_FLIT_MODE_MASK                                0x00040000L
+#define BIF_CFG_DEV0_EPF0_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_SIZE_MASK                                         0x00F80000L
+//BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG0__TLP_HDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG1__TLP_HDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG2__TLP_HDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG3__TLP_HDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG4
+#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG4__TLP_HDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG4__TLP_HDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG5
+#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG5__TLP_HDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG5__TLP_HDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG6
+#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG6__TLP_HDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG6__TLP_HDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG7
+#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG7__TLP_HDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG7__TLP_HDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG8
+#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG8__TLP_HDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG8__TLP_HDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG9
+#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG9__TLP_HDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG9__TLP_HDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG10
+#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG10__TLP_HDR__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG10__TLP_HDR_MASK                                                        0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG11
+#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG11__TLP_HDR__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG11__TLP_HDR_MASK                                                        0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG12
+#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG12__TLP_HDR__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG12__TLP_HDR_MASK                                                        0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG13
+#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG13__TLP_HDR__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_HDR_LOG13__TLP_HDR_MASK                                                        0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT                                    0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT                                   0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK                                       0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK                                      0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK                                     0xFFF00000L
+//BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW1
+#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK                                      0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW2
+#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK                                      0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
+//BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                           0x1
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                           0x2
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                        0x3
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                            0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                             0x5
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                          0x6
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__ENHANCED_CAPABILITY__SHIFT                                            0x7
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                                0x0001L
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                             0x0002L
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                             0x0004L
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                          0x0008L
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                              0x0010L
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                               0x0020L
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                            0x0040L
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__ENHANCED_CAPABILITY_MASK                                              0x0080L
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                       0x1
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                       0x2
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                    0x3
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                        0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                         0x5
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                      0x6
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN__SHIFT                                        0x7
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL__SHIFT                                 0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL__SHIFT                                 0xa
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL__SHIFT                               0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                            0x0001L
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                         0x0002L
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                         0x0004L
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                      0x0008L
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                          0x0010L
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                           0x0020L
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                        0x0040L
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN_MASK                                          0x0080L
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL_MASK                                   0x0300L
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL_MASK                                   0x0C00L
+#define BIF_CFG_DEV0_EPF0_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL_MASK                                 0x1000L
+//BIF_CFG_DEV0_EPF0_PCIE_RTR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
+//BIF_CFG_DEV0_EPF0_RTR_DATA1
+#define BIF_CFG_DEV0_EPF0_RTR_DATA1__RESET_TIME__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_EPF0_RTR_DATA1__DLUP_TIME__SHIFT                                                         0xc
+#define BIF_CFG_DEV0_EPF0_RTR_DATA1__RTR_VALID__SHIFT                                                         0x1f
+#define BIF_CFG_DEV0_EPF0_RTR_DATA1__RESET_TIME_MASK                                                          0x00000FFFL
+#define BIF_CFG_DEV0_EPF0_RTR_DATA1__DLUP_TIME_MASK                                                           0x00FFF000L
+#define BIF_CFG_DEV0_EPF0_RTR_DATA1__RTR_VALID_MASK                                                           0x80000000L
+//BIF_CFG_DEV0_EPF0_RTR_DATA2
+#define BIF_CFG_DEV0_EPF0_RTR_DATA2__FLR_TIME__SHIFT                                                          0x0
+#define BIF_CFG_DEV0_EPF0_RTR_DATA2__D3HOTD0_TIME__SHIFT                                                      0xc
+#define BIF_CFG_DEV0_EPF0_RTR_DATA2__FLR_TIME_MASK                                                            0x00000FFFL
+#define BIF_CFG_DEV0_EPF0_RTR_DATA2__D3HOTD0_TIME_MASK                                                        0x00FFF000L
+//PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT                                                           0x0
+#define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT                                                          0x10
+#define PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                         0x14
+#define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK                                                             0x0000FFFFL
+#define PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK                                                            0x000F0000L
+#define PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK                                                           0xFFF00000L
+//PCIE_PWR_BUDGET_DATA_SELECT
+#define PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT                                                       0x0
+#define PCIE_PWR_BUDGET_DATA_SELECT__EXTENDED_PWR_BUDGET_ENABLE__SHIFT                                        0x10
+#define PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK                                                         0x000000FFL
+#define PCIE_PWR_BUDGET_DATA_SELECT__EXTENDED_PWR_BUDGET_ENABLE_MASK                                          0x00010000L
+//PCIE_PWR_BUDGET_DATA
+#define PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT                                                               0x0
+#define PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT                                                               0x8
+#define PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT                                                             0xa
+#define PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT                                                                 0xd
+#define PCIE_PWR_BUDGET_DATA__TYPE__SHIFT                                                                     0xf
+#define PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT                                                               0x12
+#define PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK                                                                 0x000000FFL
+#define PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK                                                                 0x00000300L
+#define PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK                                                               0x00001C00L
+#define PCIE_PWR_BUDGET_DATA__PM_STATE_MASK                                                                   0x00006000L
+#define PCIE_PWR_BUDGET_DATA__TYPE_MASK                                                                       0x00038000L
+#define PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK                                                                 0x001C0000L
+//PCIE_PWR_BUDGET_CAP
+#define PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT                                                          0x0
+#define PCIE_PWR_BUDGET_CAP__EXTENDED_PWR_BUDGET_SUPPORT__SHIFT                                               0x1
+#define PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK                                                            0x01L
+#define PCIE_PWR_BUDGET_CAP__EXTENDED_PWR_BUDGET_SUPPORT_MASK                                                 0x02L
+//PCIE_DPA_ENH_CAP_LIST
+#define PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT                                                                  0x0
+#define PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT                                                                 0x10
+#define PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                                0x14
+#define PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK                                                                    0x0000FFFFL
+#define PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK                                                                   0x000F0000L
+#define PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK                                                                  0xFFF00000L
+//PCIE_DPA_CAP
+#define PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT                                                                     0x0
+#define PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT                                                                   0x8
+#define PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT                                                                  0xc
+#define PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT                                                                  0x10
+#define PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT                                                                  0x18
+#define PCIE_DPA_CAP__SUBSTATE_MAX_MASK                                                                       0x0000001FL
+#define PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK                                                                     0x00000300L
+#define PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK                                                                    0x00003000L
+#define PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK                                                                    0x00FF0000L
+#define PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK                                                                    0xFF000000L
+//PCIE_DPA_LATENCY_INDICATOR
+#define PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT                                           0x0
+#define PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK                                             0x000000FFL
+//PCIE_DPA_STATUS
+#define PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT                                                               0x0
+#define PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT                                                         0x8
+#define PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK                                                                 0x001FL
+#define PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK                                                           0x0100L
+//PCIE_DPA_CNTL
+#define PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT                                                                   0x0
+#define PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK                                                                     0x001FL
+//PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                                              0x0
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                                                0xFFL
+//PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                                              0x0
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                                                0xFFL
+//PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                                              0x0
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                                                0xFFL
+//PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                                              0x0
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                                                0xFFL
+//PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                                              0x0
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                                                0xFFL
+//PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                                              0x0
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                                                0xFFL
+//PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                                              0x0
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                                                0xFFL
+//PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                                              0x0
+#define PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                                                0xFFL
+//PCIE_LTR_ENH_CAP_LIST
+#define PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT                                                                  0x0
+#define PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT                                                                 0x10
+#define PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                                0x14
+#define PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK                                                                    0x0000FFFFL
+#define PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK                                                                   0x000F0000L
+#define PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK                                                                  0xFFF00000L
+//PCIE_LTR_CAP
+#define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT                                                          0x0
+#define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT                                                          0xa
+#define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT                                                         0x10
+#define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT                                                         0x1a
+#define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK                                                            0x000003FFL
+#define PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK                                                            0x00001C00L
+#define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK                                                           0x03FF0000L
+#define PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK                                                           0x1C000000L
+//BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
+//BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                        0x1
+#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                              0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                         0x0001L
+#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                          0x0002L
+#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                                0xFF00L
+//BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                        0x1
+#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                            0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                         0x0001L
+#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                          0x0002L
+#define BIF_CFG_DEV0_EPF0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                              0x0070L
+//PCIE_BAR_ENH_CAP_LIST
+#define PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT                                                                  0x0
+#define PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT                                                                 0x10
+#define PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                                0x14
+#define PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK                                                                    0x0000FFFFL
+#define PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK                                                                   0x000F0000L
+#define PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK                                                                  0xFFF00000L
+//PCIE_BAR1_CAP
+#define PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT                                                              0x4
+#define PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK                                                                0xFFFFFFF0L
+//PCIE_BAR1_CNTL
+#define PCIE_BAR1_CNTL__BAR_INDEX__SHIFT                                                                      0x0
+#define PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT                                                                  0x5
+#define PCIE_BAR1_CNTL__BAR_SIZE__SHIFT                                                                       0x8
+#define PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                                       0x10
+#define PCIE_BAR1_CNTL__BAR_INDEX_MASK                                                                        0x00000007L
+#define PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK                                                                    0x000000E0L
+#define PCIE_BAR1_CNTL__BAR_SIZE_MASK                                                                         0x00003F00L
+#define PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                                         0xFFFF0000L
+//PCIE_BAR2_CAP
+#define PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT                                                              0x4
+#define PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK                                                                0xFFFFFFF0L
+//PCIE_BAR2_CNTL
+#define PCIE_BAR2_CNTL__BAR_INDEX__SHIFT                                                                      0x0
+#define PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT                                                                  0x5
+#define PCIE_BAR2_CNTL__BAR_SIZE__SHIFT                                                                       0x8
+#define PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                                       0x10
+#define PCIE_BAR2_CNTL__BAR_INDEX_MASK                                                                        0x00000007L
+#define PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK                                                                    0x000000E0L
+#define PCIE_BAR2_CNTL__BAR_SIZE_MASK                                                                         0x00003F00L
+#define PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                                         0xFFFF0000L
+//PCIE_BAR3_CAP
+#define PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT                                                              0x4
+#define PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK                                                                0xFFFFFFF0L
+//PCIE_BAR3_CNTL
+#define PCIE_BAR3_CNTL__BAR_INDEX__SHIFT                                                                      0x0
+#define PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT                                                                  0x5
+#define PCIE_BAR3_CNTL__BAR_SIZE__SHIFT                                                                       0x8
+#define PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                                       0x10
+#define PCIE_BAR3_CNTL__BAR_INDEX_MASK                                                                        0x00000007L
+#define PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK                                                                    0x000000E0L
+#define PCIE_BAR3_CNTL__BAR_SIZE_MASK                                                                         0x00003F00L
+#define PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                                         0xFFFF0000L
+//PCIE_BAR4_CAP
+#define PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT                                                              0x4
+#define PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK                                                                0xFFFFFFF0L
+//PCIE_BAR4_CNTL
+#define PCIE_BAR4_CNTL__BAR_INDEX__SHIFT                                                                      0x0
+#define PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT                                                                  0x5
+#define PCIE_BAR4_CNTL__BAR_SIZE__SHIFT                                                                       0x8
+#define PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                                       0x10
+#define PCIE_BAR4_CNTL__BAR_INDEX_MASK                                                                        0x00000007L
+#define PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK                                                                    0x000000E0L
+#define PCIE_BAR4_CNTL__BAR_SIZE_MASK                                                                         0x00003F00L
+#define PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                                         0xFFFF0000L
+//PCIE_BAR5_CAP
+#define PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT                                                              0x4
+#define PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK                                                                0xFFFFFFF0L
+//PCIE_BAR5_CNTL
+#define PCIE_BAR5_CNTL__BAR_INDEX__SHIFT                                                                      0x0
+#define PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT                                                                  0x5
+#define PCIE_BAR5_CNTL__BAR_SIZE__SHIFT                                                                       0x8
+#define PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                                       0x10
+#define PCIE_BAR5_CNTL__BAR_INDEX_MASK                                                                        0x00000007L
+#define PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK                                                                    0x000000E0L
+#define PCIE_BAR5_CNTL__BAR_SIZE_MASK                                                                         0x00003F00L
+#define PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                                         0xFFFF0000L
+//PCIE_BAR6_CAP
+#define PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT                                                              0x4
+#define PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK                                                                0xFFFFFFF0L
+//PCIE_BAR6_CNTL
+#define PCIE_BAR6_CNTL__BAR_INDEX__SHIFT                                                                      0x0
+#define PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT                                                                  0x5
+#define PCIE_BAR6_CNTL__BAR_SIZE__SHIFT                                                                       0x8
+#define PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                                       0x10
+#define PCIE_BAR6_CNTL__BAR_INDEX_MASK                                                                        0x00000007L
+#define PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK                                                                    0x000000E0L
+#define PCIE_BAR6_CNTL__BAR_SIZE_MASK                                                                         0x00003F00L
+#define PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                                         0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
+//BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT                                           0x5
+#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT                                    0x6
+#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED__SHIFT                                     0x7
+#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__TEE_EXCLUSIVE_ATTR_SUPPORTED__SHIFT                                   0x9
+#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK                                               0x001FL
+#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK                                             0x0020L
+#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK                                      0x0040L
+#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED_MASK                                       0x0080L
+#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CAP__TEE_EXCLUSIVE_ATTR_SUPPORTED_MASK                                     0x0200L
+//BIF_CFG_DEV0_EPF0_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CNTL__STU__SHIFT                                                           0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CNTL__TEE_EXCLUSIVE_ATTR_ENABLE__SHIFT                                     0xa
+#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT                                                    0xf
+#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CNTL__STU_MASK                                                             0x001FL
+#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CNTL__TEE_EXCLUSIVE_ATTR_ENABLE_MASK                                       0x0400L
+#define BIF_CFG_DEV0_EPF0_PCIE_ATS_CNTL__ATC_ENABLE_MASK                                                      0x8000L
+//PCIE_PAGE_REQ_ENH_CAP_LIST
+#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT                                                             0x0
+#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT                                                            0x10
+#define PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                           0x14
+#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK                                                               0x0000FFFFL
+#define PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK                                                              0x000F0000L
+#define PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK                                                             0xFFF00000L
+//PCIE_PAGE_REQ_CNTL
+#define PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT                                                                 0x0
+#define PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT                                                                  0x1
+#define PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK                                                                   0x0001L
+#define PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK                                                                    0x0002L
+//PCIE_PAGE_REQ_STATUS
+#define PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT                                                         0x0
+#define PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT                                            0x1
+#define PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT                                                                  0x8
+#define PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT                                              0xf
+#define PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK                                                           0x0001L
+#define PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK                                              0x0002L
+#define PCIE_PAGE_REQ_STATUS__STOPPED_MASK                                                                    0x0100L
+#define PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK                                                0x8000L
+//PCIE_OUTSTAND_PAGE_REQ_CAPACITY
+#define PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT                                    0x0
+#define PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK                                      0xFFFFFFFFL
+//PCIE_OUTSTAND_PAGE_REQ_ALLOC
+#define PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT                                          0x0
+#define PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK                                            0xFFFFFFFFL
+//PCIE_PASID_ENH_CAP_LIST
+#define PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT                                                                0x0
+#define PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT                                                               0x10
+#define PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                              0x14
+#define PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK                                                                  0x0000FFFFL
+#define PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK                                                                 0x000F0000L
+#define PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK                                                                0xFFF00000L
+//PCIE_PASID_CAP
+#define PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT                                                 0x1
+#define PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT                                                      0x2
+#define PCIE_PASID_CAP__TRANSLATED_REQ_WITH_PASID_SUPPORTED__SHIFT                                            0x3
+#define PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT                                                                0x8
+#define PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK                                                   0x0002L
+#define PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK                                                        0x0004L
+#define PCIE_PASID_CAP__TRANSLATED_REQ_WITH_PASID_SUPPORTED_MASK                                              0x0008L
+#define PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK                                                                  0x1F00L
+//PCIE_PASID_CNTL
+#define PCIE_PASID_CNTL__PASID_ENABLE__SHIFT                                                                  0x0
+#define PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT                                                   0x1
+#define PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT                                              0x2
+#define PCIE_PASID_CNTL__TRANSLATED_REQ_WITH_PASID_ENABLE__SHIFT                                              0x3
+#define PCIE_PASID_CNTL__PASID_ENABLE_MASK                                                                    0x0001L
+#define PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK                                                     0x0002L
+#define PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK                                                0x0004L
+#define PCIE_PASID_CNTL__TRANSLATED_REQ_WITH_PASID_ENABLE_MASK                                                0x0008L
+//PCIE_SRIOV_ENH_CAP_LIST
+#define PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT                                                                0x0
+#define PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT                                                               0x10
+#define PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                              0x14
+#define PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK                                                                  0x0000FFFFL
+#define PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK                                                                 0x000F0000L
+#define PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK                                                                0xFFF00000L
+//PCIE_SRIOV_CAP
+#define PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT                                                         0x0
+#define PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT                                              0x1
+#define PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                                       0x2
+#define PCIE_SRIOV_CAP__SRIOV_VF_14_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                                        0x3
+#define PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT                                                0x15
+#define PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK                                                           0x00000001L
+#define PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK                                                0x00000002L
+#define PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                         0x00000004L
+#define PCIE_SRIOV_CAP__SRIOV_VF_14_BIT_TAG_REQUESTER_SUPPORTED_MASK                                          0x00000008L
+#define PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK                                                  0xFFE00000L
+//PCIE_SRIOV_CONTROL
+#define PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT                                                            0x0
+#define PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT                                                  0x1
+#define PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT                                             0x2
+#define PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT                                                               0x3
+#define PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT                                                    0x4
+#define PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                      0x5
+#define PCIE_SRIOV_CONTROL__SRIOV_VF_14_BIT_TAG_REQUESTER_ENABLE__SHIFT                                       0x6
+#define PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK                                                              0x0001L
+#define PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK                                                    0x0002L
+#define PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK                                               0x0004L
+#define PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK                                                                 0x0008L
+#define PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK                                                      0x0010L
+#define PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                        0x0020L
+#define PCIE_SRIOV_CONTROL__SRIOV_VF_14_BIT_TAG_REQUESTER_ENABLE_MASK                                         0x0040L
+//PCIE_SRIOV_STATUS
+#define PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT                                                   0x0
+#define PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK                                                     0x0001L
+//PCIE_SRIOV_INITIAL_VFS
+#define PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT                                                      0x0
+#define PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK                                                        0xFFFFL
+//PCIE_SRIOV_TOTAL_VFS
+#define PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT                                                          0x0
+#define PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK                                                            0xFFFFL
+//PCIE_SRIOV_NUM_VFS
+#define PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT                                                              0x0
+#define PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK                                                                0xFFFFL
+//PCIE_SRIOV_FUNC_DEP_LINK
+#define PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT                                                  0x0
+#define PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK                                                    0xFFL
+//PCIE_SRIOV_FIRST_VF_OFFSET
+#define PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT                                              0x0
+#define PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK                                                0xFFFFL
+//PCIE_SRIOV_VF_STRIDE
+#define PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT                                                          0x0
+#define PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK                                                            0xFFFFL
+//PCIE_SRIOV_VF_DEVICE_ID
+#define PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT                                                    0x0
+#define PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK                                                      0xFFFFL
+//PCIE_SRIOV_SUPPORTED_PAGE_SIZE
+#define PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT                                      0x0
+#define PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK                                        0xFFFFFFFFL
+//PCIE_SRIOV_SYSTEM_PAGE_SIZE
+#define PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT                                            0x0
+#define PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK                                              0xFFFFFFFFL
+//PCIE_SRIOV_VF_BASE_ADDR_0
+#define PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT                                                        0x0
+#define PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK                                                          0xFFFFFFFFL
+//PCIE_SRIOV_VF_BASE_ADDR_1
+#define PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT                                                        0x0
+#define PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK                                                          0xFFFFFFFFL
+//PCIE_SRIOV_VF_BASE_ADDR_2
+#define PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT                                                        0x0
+#define PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK                                                          0xFFFFFFFFL
+//PCIE_SRIOV_VF_BASE_ADDR_3
+#define PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT                                                        0x0
+#define PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK                                                          0xFFFFFFFFL
+//PCIE_SRIOV_VF_BASE_ADDR_4
+#define PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT                                                        0x0
+#define PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK                                                          0xFFFFFFFFL
+//PCIE_SRIOV_VF_BASE_ADDR_5
+#define PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT                                                        0x0
+#define PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK                                                          0xFFFFFFFFL
+//PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET
+#define PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR__SHIFT                       0x0
+#define PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT              0x3
+#define PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR_MASK                         0x00000007L
+#define PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK                0xFFFFFFF8L
+//PCIE_VF_RESIZE_BAR_ENH_CAP_LIST
+#define PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT                                                        0x0
+#define PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT                                                       0x10
+#define PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                      0x14
+#define PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID_MASK                                                          0x0000FFFFL
+#define PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER_MASK                                                         0x000F0000L
+#define PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK                                                        0xFFF00000L
+//PCIE_VF_RESIZE_BAR1_CAP
+#define PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT                                                 0x4
+#define PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED_MASK                                                   0xFFFFFFF0L
+//PCIE_VF_RESIZE_BAR1_CNTL
+#define PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX__SHIFT                                                         0x0
+#define PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM__SHIFT                                                     0x5
+#define PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE__SHIFT                                                          0x8
+#define PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT                                          0x10
+#define PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX_MASK                                                           0x00000007L
+#define PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM_MASK                                                       0x000000E0L
+#define PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_MASK                                                            0x00003F00L
+#define PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK                                            0xFFFF0000L
+//PCIE_VF_RESIZE_BAR2_CAP
+#define PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT                                                 0x4
+#define PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED_MASK                                                   0xFFFFFFF0L
+//PCIE_VF_RESIZE_BAR2_CNTL
+#define PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX__SHIFT                                                         0x0
+#define PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM__SHIFT                                                     0x5
+#define PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE__SHIFT                                                          0x8
+#define PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT                                          0x10
+#define PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX_MASK                                                           0x00000007L
+#define PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM_MASK                                                       0x000000E0L
+#define PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_MASK                                                            0x00003F00L
+#define PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK                                            0xFFFF0000L
+//PCIE_VF_RESIZE_BAR3_CAP
+#define PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT                                                 0x4
+#define PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED_MASK                                                   0xFFFFFFF0L
+//PCIE_VF_RESIZE_BAR3_CNTL
+#define PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX__SHIFT                                                         0x0
+#define PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM__SHIFT                                                     0x5
+#define PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE__SHIFT                                                          0x8
+#define PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT                                          0x10
+#define PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX_MASK                                                           0x00000007L
+#define PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM_MASK                                                       0x000000E0L
+#define PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_MASK                                                            0x00003F00L
+#define PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK                                            0xFFFF0000L
+//PCIE_VF_RESIZE_BAR4_CAP
+#define PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT                                                 0x4
+#define PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED_MASK                                                   0xFFFFFFF0L
+//PCIE_VF_RESIZE_BAR4_CNTL
+#define PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX__SHIFT                                                         0x0
+#define PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM__SHIFT                                                     0x5
+#define PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE__SHIFT                                                          0x8
+#define PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT                                          0x10
+#define PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX_MASK                                                           0x00000007L
+#define PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM_MASK                                                       0x000000E0L
+#define PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_MASK                                                            0x00003F00L
+#define PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK                                            0xFFFF0000L
+//PCIE_VF_RESIZE_BAR5_CAP
+#define PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT                                                 0x4
+#define PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED_MASK                                                   0xFFFFFFF0L
+//PCIE_VF_RESIZE_BAR5_CNTL
+#define PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX__SHIFT                                                         0x0
+#define PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM__SHIFT                                                     0x5
+#define PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE__SHIFT                                                          0x8
+#define PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT                                          0x10
+#define PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX_MASK                                                           0x00000007L
+#define PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM_MASK                                                       0x000000E0L
+#define PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_MASK                                                            0x00003F00L
+#define PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK                                            0xFFFF0000L
+//PCIE_VF_RESIZE_BAR6_CAP
+#define PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT                                                 0x4
+#define PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED_MASK                                                   0xFFFFFFF0L
+//PCIE_VF_RESIZE_BAR6_CNTL
+#define PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX__SHIFT                                                         0x0
+#define PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM__SHIFT                                                     0x5
+#define PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE__SHIFT                                                          0x8
+#define PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT                                          0x10
+#define PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX_MASK                                                           0x00000007L
+#define PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM_MASK                                                       0x000000E0L
+#define PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_MASK                                                            0x00003F00L
+#define PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK                                            0xFFFF0000L
+//PCIE_DOE_ENH_CAP_LIST
+#define PCIE_DOE_ENH_CAP_LIST__CAP_ID__SHIFT                                                                  0x0
+#define PCIE_DOE_ENH_CAP_LIST__CAP_VER__SHIFT                                                                 0x10
+#define PCIE_DOE_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                                0x14
+#define PCIE_DOE_ENH_CAP_LIST__CAP_ID_MASK                                                                    0x0000FFFFL
+#define PCIE_DOE_ENH_CAP_LIST__CAP_VER_MASK                                                                   0x000F0000L
+#define PCIE_DOE_ENH_CAP_LIST__NEXT_PTR_MASK                                                                  0xFFF00000L
+//PCIE_DOE_CAP
+#define PCIE_DOE_CAP__INTR_SUPPORT__SHIFT                                                                     0x0
+#define PCIE_DOE_CAP__DOE_INTR_MSG_NUM__SHIFT                                                                 0x1
+#define PCIE_DOE_CAP__DOE_ATT_SUPPORT__SHIFT                                                                  0xc
+#define PCIE_DOE_CAP__DOE_ASYNC_SUPPORT__SHIFT                                                                0xd
+#define PCIE_DOE_CAP__INTR_SUPPORT_MASK                                                                       0x00000001L
+#define PCIE_DOE_CAP__DOE_INTR_MSG_NUM_MASK                                                                   0x00000FFEL
+#define PCIE_DOE_CAP__DOE_ATT_SUPPORT_MASK                                                                    0x00001000L
+#define PCIE_DOE_CAP__DOE_ASYNC_SUPPORT_MASK                                                                  0x00002000L
+//PCIE_DOE_CNTL
+#define PCIE_DOE_CNTL__DOE_ABORT__SHIFT                                                                       0x0
+#define PCIE_DOE_CNTL__DOE_INTR_EN__SHIFT                                                                     0x1
+#define PCIE_DOE_CNTL__DOE_ATT_NOT_NEED__SHIFT                                                                0x2
+#define PCIE_DOE_CNTL__DOE_ASYNC_MSG_EN__SHIFT                                                                0x3
+#define PCIE_DOE_CNTL__DOE_GO__SHIFT                                                                          0x1f
+#define PCIE_DOE_CNTL__DOE_ABORT_MASK                                                                         0x00000001L
+#define PCIE_DOE_CNTL__DOE_INTR_EN_MASK                                                                       0x00000002L
+#define PCIE_DOE_CNTL__DOE_ATT_NOT_NEED_MASK                                                                  0x00000004L
+#define PCIE_DOE_CNTL__DOE_ASYNC_MSG_EN_MASK                                                                  0x00000008L
+#define PCIE_DOE_CNTL__DOE_GO_MASK                                                                            0x80000000L
+//PCIE_DOE_STS
+#define PCIE_DOE_STS__DOE_BUSY__SHIFT                                                                         0x0
+#define PCIE_DOE_STS__DOE_INTR_STS__SHIFT                                                                     0x1
+#define PCIE_DOE_STS__DOE_ERR__SHIFT                                                                          0x2
+#define PCIE_DOE_STS__DOE_ASYNC_MSG_STS__SHIFT                                                                0x3
+#define PCIE_DOE_STS__DOE_AT_ATTENTION__SHIFT                                                                 0x4
+#define PCIE_DOE_STS__DOE_OBJ_RDY__SHIFT                                                                      0x1f
+#define PCIE_DOE_STS__DOE_BUSY_MASK                                                                           0x00000001L
+#define PCIE_DOE_STS__DOE_INTR_STS_MASK                                                                       0x00000002L
+#define PCIE_DOE_STS__DOE_ERR_MASK                                                                            0x00000004L
+#define PCIE_DOE_STS__DOE_ASYNC_MSG_STS_MASK                                                                  0x00000008L
+#define PCIE_DOE_STS__DOE_AT_ATTENTION_MASK                                                                   0x00000010L
+#define PCIE_DOE_STS__DOE_OBJ_RDY_MASK                                                                        0x80000000L
+//PCIE_DOE_WMBOX
+#define PCIE_DOE_WMBOX__DOE_WMBOX__SHIFT                                                                      0x0
+#define PCIE_DOE_WMBOX__DOE_WMBOX_MASK                                                                        0xFFFFFFFFL
+//PCIE_DOE_RMBOX
+#define PCIE_DOE_RMBOX__DOE_RMBOX__SHIFT                                                                      0x0
+#define PCIE_DOE_RMBOX__DOE_RMBOX_MASK                                                                        0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV
+#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__SHIFT                                               0x0
+#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__SHIFT                                              0x10
+#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__SHIFT                                             0x14
+#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID_MASK                                                 0x0000FFFFL
+#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER_MASK                                                0x000F0000L
+#define PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR_MASK                                               0xFFF00000L
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID__SHIFT                                                       0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV__SHIFT                                                      0x10
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH__SHIFT                                                   0x14
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID_MASK                                                         0x0000FFFFL
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV_MASK                                                        0x000F0000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH_MASK                                                     0xFFF00000L
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN__SHIFT                                            0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM__SHIFT                                           0x10
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN_MASK                                              0x00000001L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM_MASK                                             0xFFFF0000L
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN__SHIFT                      0x18
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN__SHIFT                    0x19
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN_MASK                        0x01000000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN_MASK                      0x02000000L
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS__SHIFT                  0x18
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS__SHIFT                0x19
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS_MASK                    0x01000000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS_MASK                  0x02000000L
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR__SHIFT                                     0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__FUNCTION_ID__SHIFT                                     0x8
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR_MASK                                       0x0001L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__FUNCTION_ID_MASK                                       0xFF00L
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX__SHIFT                                        0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA__SHIFT                                    0x8
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID__SHIFT                                   0xf
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA__SHIFT                                    0x10
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK__SHIFT                                     0x18
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX_MASK                                          0x000000FFL
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA_MASK                                      0x00000F00L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID_MASK                                     0x00008000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA_MASK                                      0x000F0000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK_MASK                                       0x01000000L
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK__SHIFT                                     0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID__SHIFT                                   0x1
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK__SHIFT                                     0x2
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID__SHIFT                                   0x3
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK__SHIFT                                     0x4
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID__SHIFT                                   0x5
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK__SHIFT                                     0x6
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID__SHIFT                                   0x7
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK__SHIFT                                     0x8
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID__SHIFT                                   0x9
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK__SHIFT                                     0xa
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID__SHIFT                                   0xb
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK__SHIFT                                     0xc
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID__SHIFT                                   0xd
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK__SHIFT                                     0xe
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID__SHIFT                                   0xf
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK__SHIFT                                     0x10
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID__SHIFT                                   0x11
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK__SHIFT                                     0x12
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID__SHIFT                                   0x13
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK__SHIFT                                    0x14
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID__SHIFT                                  0x15
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK__SHIFT                                    0x16
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID__SHIFT                                  0x17
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK__SHIFT                                    0x18
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID__SHIFT                                  0x19
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK__SHIFT                                    0x1a
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID__SHIFT                                  0x1b
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK__SHIFT                                    0x1c
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID__SHIFT                                  0x1d
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK__SHIFT                                    0x1e
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID__SHIFT                                  0x1f
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK_MASK                                       0x00000001L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID_MASK                                     0x00000002L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK_MASK                                       0x00000004L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID_MASK                                     0x00000008L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK_MASK                                       0x00000010L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID_MASK                                     0x00000020L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK_MASK                                       0x00000040L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID_MASK                                     0x00000080L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK_MASK                                       0x00000100L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID_MASK                                     0x00000200L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK_MASK                                       0x00000400L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID_MASK                                     0x00000800L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK_MASK                                       0x00001000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID_MASK                                     0x00002000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK_MASK                                       0x00004000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID_MASK                                     0x00008000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK_MASK                                       0x00010000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID_MASK                                     0x00020000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK_MASK                                       0x00040000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID_MASK                                     0x00080000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK_MASK                                      0x00100000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID_MASK                                    0x00200000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK_MASK                                      0x00400000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID_MASK                                    0x00800000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK_MASK                                      0x01000000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID_MASK                                    0x02000000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK_MASK                                      0x04000000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID_MASK                                    0x08000000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK_MASK                                      0x10000000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID_MASK                                    0x20000000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK_MASK                                      0x40000000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID_MASK                                    0x80000000L
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_TRN_ACK__SHIFT                                    0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_RCV_VALID__SHIFT                                  0x1
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_TRN_ACK__SHIFT                                    0x2
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_RCV_VALID__SHIFT                                  0x3
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_TRN_ACK__SHIFT                                    0x4
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_RCV_VALID__SHIFT                                  0x5
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_TRN_ACK__SHIFT                                    0x6
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_RCV_VALID__SHIFT                                  0x7
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_TRN_ACK__SHIFT                                    0x8
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_RCV_VALID__SHIFT                                  0x9
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_TRN_ACK__SHIFT                                    0xa
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_RCV_VALID__SHIFT                                  0xb
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_TRN_ACK__SHIFT                                    0xc
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_RCV_VALID__SHIFT                                  0xd
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_TRN_ACK__SHIFT                                    0xe
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_RCV_VALID__SHIFT                                  0xf
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_TRN_ACK__SHIFT                                    0x10
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_RCV_VALID__SHIFT                                  0x11
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_TRN_ACK__SHIFT                                    0x12
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_RCV_VALID__SHIFT                                  0x13
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_TRN_ACK__SHIFT                                    0x14
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_RCV_VALID__SHIFT                                  0x15
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_TRN_ACK__SHIFT                                    0x16
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_RCV_VALID__SHIFT                                  0x17
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_TRN_ACK__SHIFT                                    0x18
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_RCV_VALID__SHIFT                                  0x19
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_TRN_ACK__SHIFT                                    0x1a
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_RCV_VALID__SHIFT                                  0x1b
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_TRN_ACK__SHIFT                                    0x1c
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_RCV_VALID__SHIFT                                  0x1d
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK__SHIFT                                      0x1e
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID__SHIFT                                    0x1f
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_TRN_ACK_MASK                                      0x00000001L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_RCV_VALID_MASK                                    0x00000002L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_TRN_ACK_MASK                                      0x00000004L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_RCV_VALID_MASK                                    0x00000008L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_TRN_ACK_MASK                                      0x00000010L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_RCV_VALID_MASK                                    0x00000020L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_TRN_ACK_MASK                                      0x00000040L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_RCV_VALID_MASK                                    0x00000080L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_TRN_ACK_MASK                                      0x00000100L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_RCV_VALID_MASK                                    0x00000200L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_TRN_ACK_MASK                                      0x00000400L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_RCV_VALID_MASK                                    0x00000800L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_TRN_ACK_MASK                                      0x00001000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_RCV_VALID_MASK                                    0x00002000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_TRN_ACK_MASK                                      0x00004000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_RCV_VALID_MASK                                    0x00008000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_TRN_ACK_MASK                                      0x00010000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_RCV_VALID_MASK                                    0x00020000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_TRN_ACK_MASK                                      0x00040000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_RCV_VALID_MASK                                    0x00080000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_TRN_ACK_MASK                                      0x00100000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_RCV_VALID_MASK                                    0x00200000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_TRN_ACK_MASK                                      0x00400000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_RCV_VALID_MASK                                    0x00800000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_TRN_ACK_MASK                                      0x01000000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_RCV_VALID_MASK                                    0x02000000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_TRN_ACK_MASK                                      0x04000000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_RCV_VALID_MASK                                    0x08000000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_TRN_ACK_MASK                                      0x10000000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_RCV_VALID_MASK                                    0x20000000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK_MASK                                        0x40000000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID_MASK                                      0x80000000L
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE__SHIFT                                   0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED__SHIFT                                    0x10
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE_MASK                                     0x0000FFFFL
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED_MASK                                      0xFFFF0000L
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__LFB_REGION__SHIFT                                             0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__MAX_REGION__SHIFT                                             0x4
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__LFB_REGION_MASK                                               0x0000000FL
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__MAX_REGION_MASK                                               0x000000F0L
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_VF__SHIFT                  0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_PF__SHIFT                  0x1f
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_VF_MASK                    0x7FFFFFFFL
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_PF_MASK                    0x80000000L
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS0__SCH0_OFFSET__SHIFT                                          0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS0__SCH1_OFFSET__SHIFT                                          0x8
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS0__SCH2_OFFSET__SHIFT                                          0x10
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS0__SCH3_OFFSET__SHIFT                                          0x18
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS0__SCH0_OFFSET_MASK                                            0x000000FFL
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS0__SCH1_OFFSET_MASK                                            0x0000FF00L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS0__SCH2_OFFSET_MASK                                            0x00FF0000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS0__SCH3_OFFSET_MASK                                            0xFF000000L
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__SCH4_OFFSET__SHIFT                                          0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__SCH5_OFFSET__SHIFT                                          0x8
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__SCH6_OFFSET__SHIFT                                          0x10
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__SCH7_OFFSET__SHIFT                                          0x18
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__SCH4_OFFSET_MASK                                            0x000000FFL
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__SCH5_OFFSET_MASK                                            0x0000FF00L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__SCH6_OFFSET_MASK                                            0x00FF0000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__SCH7_OFFSET_MASK                                            0xFF000000L
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__SCH8_OFFSET__SHIFT                                          0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__SCH9_OFFSET__SHIFT                                          0x8
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__SCH10_OFFSET__SHIFT                                         0x10
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__SCH11_OFFSET__SHIFT                                         0x18
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__SCH8_OFFSET_MASK                                            0x000000FFL
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__SCH9_OFFSET_MASK                                            0x0000FF00L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__SCH10_OFFSET_MASK                                           0x00FF0000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__SCH11_OFFSET_MASK                                           0xFF000000L
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__SCH12_OFFSET__SHIFT                                         0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__SCH13_OFFSET__SHIFT                                         0x8
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__SCH14_OFFSET__SHIFT                                         0x10
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__SCH15_OFFSET__SHIFT                                         0x18
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__SCH12_OFFSET_MASK                                           0x000000FFL
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__SCH13_OFFSET_MASK                                           0x0000FF00L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__SCH14_OFFSET_MASK                                           0x00FF0000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__SCH15_OFFSET_MASK                                           0xFF000000L
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__SCH16_OFFSET__SHIFT                                         0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__SCH17_OFFSET__SHIFT                                         0x8
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__SCH18_OFFSET__SHIFT                                         0x10
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__SCH19_OFFSET__SHIFT                                         0x18
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__SCH16_OFFSET_MASK                                           0x000000FFL
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__SCH17_OFFSET_MASK                                           0x0000FF00L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__SCH18_OFFSET_MASK                                           0x00FF0000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__SCH19_OFFSET_MASK                                           0xFF000000L
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW0__DW0__SHIFT                                                  0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW0__DW0_MASK                                                    0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW1
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW1__DW1__SHIFT                                                  0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW1__DW1_MASK                                                    0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW2
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW2__DW2__SHIFT                                                  0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW2__DW2_MASK                                                    0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW3
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW3__DW3__SHIFT                                                  0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW3__DW3_MASK                                                    0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW4
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW4__DW4__SHIFT                                                  0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW4__DW4_MASK                                                    0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW5
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW5__DW5__SHIFT                                                  0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW5__DW5_MASK                                                    0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW6
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW6__DW6__SHIFT                                                  0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW6__DW6_MASK                                                    0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW7
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW7__DW7__SHIFT                                                  0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW7__DW7_MASK                                                    0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW8
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW8__DW8__SHIFT                                                  0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW8__DW8_MASK                                                    0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW0__DW0__SHIFT                                                  0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW0__DW0_MASK                                                    0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW1
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW1__DW1__SHIFT                                                  0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW1__DW1_MASK                                                    0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW2
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW2__DW2__SHIFT                                                  0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW2__DW2_MASK                                                    0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW3
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW3__DW3__SHIFT                                                  0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW3__DW3_MASK                                                    0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW4
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW4__DW4__SHIFT                                                  0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW4__DW4_MASK                                                    0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW5
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW5__DW5__SHIFT                                                  0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW5__DW5_MASK                                                    0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW6
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW6__DW6__SHIFT                                                  0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW6__DW6_MASK                                                    0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW7
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW7__DW7__SHIFT                                                  0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW7__DW7_MASK                                                    0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW8
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW8__DW8__SHIFT                                                  0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW8__DW8_MASK                                                    0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW0__DW0__SHIFT                                                  0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW0__DW0_MASK                                                    0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW1
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW1__DW1__SHIFT                                                  0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW1__DW1_MASK                                                    0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW2
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW2__DW2__SHIFT                                                  0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW2__DW2_MASK                                                    0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW3
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW3__DW3__SHIFT                                                  0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW3__DW3_MASK                                                    0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW4
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW4__DW4__SHIFT                                                  0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW4__DW4_MASK                                                    0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW5
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW5__DW5__SHIFT                                                  0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW5__DW5_MASK                                                    0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW6
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW6__DW6__SHIFT                                                  0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW6__DW6_MASK                                                    0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW7
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW7__DW7__SHIFT                                                  0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW7__DW7_MASK                                                    0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW8
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW8__DW8__SHIFT                                                  0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW8__DW8_MASK                                                    0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW0__DW0__SHIFT                                                  0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW0__DW0_MASK                                                    0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW1
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW1__DW1__SHIFT                                                  0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW1__DW1_MASK                                                    0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW2
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW2__DW2__SHIFT                                                  0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW2__DW2_MASK                                                    0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW3
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW3__DW3__SHIFT                                                  0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW3__DW3_MASK                                                    0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW4
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW4__DW4__SHIFT                                                  0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW4__DW4_MASK                                                    0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW5
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW5__DW5__SHIFT                                                  0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW5__DW5_MASK                                                    0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW6
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW6__DW6__SHIFT                                                  0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW6__DW6_MASK                                                    0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW7
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW7__DW7__SHIFT                                                  0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW7__DW7_MASK                                                    0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW8
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW8__DW8__SHIFT                                                  0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW8__DW8_MASK                                                    0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW0__DW0__SHIFT                                                  0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW0__DW0_MASK                                                    0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW1
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW1__DW1__SHIFT                                                  0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW1__DW1_MASK                                                    0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW2
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW2__DW2__SHIFT                                                  0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW2__DW2_MASK                                                    0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW3
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW3__DW3__SHIFT                                                  0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW3__DW3_MASK                                                    0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW4
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW4__DW4__SHIFT                                                  0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW4__DW4_MASK                                                    0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW5
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW5__DW5__SHIFT                                                  0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW5__DW5_MASK                                                    0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW6
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW6__DW6__SHIFT                                                  0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW6__DW6_MASK                                                    0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW7
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW7__DW7__SHIFT                                                  0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW7__DW7_MASK                                                    0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW8
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW8__DW8__SHIFT                                                  0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW8__DW8_MASK                                                    0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW0__DW0__SHIFT                                                  0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW0__DW0_MASK                                                    0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW1
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW1__DW1__SHIFT                                                  0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW1__DW1_MASK                                                    0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW2
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW2__DW2__SHIFT                                                  0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW2__DW2_MASK                                                    0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW3
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW3__DW3__SHIFT                                                  0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW3__DW3_MASK                                                    0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW4
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW4__DW4__SHIFT                                                  0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW4__DW4_MASK                                                    0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW5
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW5__DW5__SHIFT                                                  0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW5__DW5_MASK                                                    0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW6
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW6__DW6__SHIFT                                                  0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW6__DW6_MASK                                                    0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW7
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW7__DW7__SHIFT                                                  0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW7__DW7_MASK                                                    0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW8
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW8__DW8__SHIFT                                                  0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW8__DW8_MASK                                                    0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW0__DW0__SHIFT                                                  0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW0__DW0_MASK                                                    0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW1
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW1__DW1__SHIFT                                                  0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW1__DW1_MASK                                                    0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW2
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW2__DW2__SHIFT                                                  0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW2__DW2_MASK                                                    0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW3
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW3__DW3__SHIFT                                                  0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW3__DW3_MASK                                                    0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW4
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW4__DW4__SHIFT                                                  0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW4__DW4_MASK                                                    0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW5
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW5__DW5__SHIFT                                                  0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW5__DW5_MASK                                                    0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW6
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW6__DW6__SHIFT                                                  0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW6__DW6_MASK                                                    0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW7
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW7__DW7__SHIFT                                                  0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW7__DW7_MASK                                                    0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW8
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW8__DW8__SHIFT                                                  0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW8__DW8_MASK                                                    0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW0__DW0__SHIFT                                                  0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW0__DW0_MASK                                                    0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW1
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW1__DW1__SHIFT                                                  0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW1__DW1_MASK                                                    0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW2
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW2__DW2__SHIFT                                                  0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW2__DW2_MASK                                                    0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW3
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW3__DW3__SHIFT                                                  0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW3__DW3_MASK                                                    0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW4
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW4__DW4__SHIFT                                                  0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW4__DW4_MASK                                                    0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW5
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW5__DW5__SHIFT                                                  0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW5__DW5_MASK                                                    0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW6
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW6__DW6__SHIFT                                                  0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW6__DW6_MASK                                                    0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW7
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW7__DW7__SHIFT                                                  0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW7__DW7_MASK                                                    0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW8
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW8__DW8__SHIFT                                                  0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW8__DW8_MASK                                                    0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW0__DW0__SHIFT                                                  0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW0__DW0_MASK                                                    0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW1
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW1__DW1__SHIFT                                                  0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW1__DW1_MASK                                                    0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW2
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW2__DW2__SHIFT                                                  0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW2__DW2_MASK                                                    0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW3
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW3__DW3__SHIFT                                                  0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW3__DW3_MASK                                                    0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW4
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW4__DW4__SHIFT                                                  0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW4__DW4_MASK                                                    0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW5
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW5__DW5__SHIFT                                                  0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW5__DW5_MASK                                                    0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW6
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW6__DW6__SHIFT                                                  0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW6__DW6_MASK                                                    0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW7
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW7__DW7__SHIFT                                                  0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW7__DW7_MASK                                                    0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW8
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW8__DW8__SHIFT                                                  0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW8__DW8_MASK                                                    0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW0__DW0__SHIFT                                                  0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW0__DW0_MASK                                                    0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW1
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW1__DW1__SHIFT                                                  0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW1__DW1_MASK                                                    0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW2
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW2__DW2__SHIFT                                                  0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW2__DW2_MASK                                                    0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW3
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW3__DW3__SHIFT                                                  0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW3__DW3_MASK                                                    0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW4
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW4__DW4__SHIFT                                                  0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW4__DW4_MASK                                                    0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW5
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW5__DW5__SHIFT                                                  0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW5__DW5_MASK                                                    0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW6
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW6__DW6__SHIFT                                                  0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW6__DW6_MASK                                                    0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW7
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW7__DW7__SHIFT                                                  0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW7__DW7_MASK                                                    0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW8
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW8__DW8__SHIFT                                                  0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW8__DW8_MASK                                                    0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW0__DW0__SHIFT                                                 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW0__DW0_MASK                                                   0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW1
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW1__DW1__SHIFT                                                 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW1__DW1_MASK                                                   0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW2
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW2__DW2__SHIFT                                                 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW2__DW2_MASK                                                   0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW3
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW3__DW3__SHIFT                                                 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW3__DW3_MASK                                                   0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW4
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW4__DW4__SHIFT                                                 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW4__DW4_MASK                                                   0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW5
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW5__DW5__SHIFT                                                 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW5__DW5_MASK                                                   0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW6
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW6__DW6__SHIFT                                                 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW6__DW6_MASK                                                   0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW7
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW7__DW7__SHIFT                                                 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW7__DW7_MASK                                                   0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW8
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW8__DW8__SHIFT                                                 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW8__DW8_MASK                                                   0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW0__DW0__SHIFT                                                 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW0__DW0_MASK                                                   0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW1
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW1__DW1__SHIFT                                                 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW1__DW1_MASK                                                   0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW2
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW2__DW2__SHIFT                                                 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW2__DW2_MASK                                                   0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW3
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW3__DW3__SHIFT                                                 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW3__DW3_MASK                                                   0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW4
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW4__DW4__SHIFT                                                 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW4__DW4_MASK                                                   0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW5
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW5__DW5__SHIFT                                                 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW5__DW5_MASK                                                   0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW6
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW6__DW6__SHIFT                                                 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW6__DW6_MASK                                                   0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW7
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW7__DW7__SHIFT                                                 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW7__DW7_MASK                                                   0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW8
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW8__DW8__SHIFT                                                 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW8__DW8_MASK                                                   0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW0__DW0__SHIFT                                                 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW0__DW0_MASK                                                   0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW1
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW1__DW1__SHIFT                                                 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW1__DW1_MASK                                                   0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW2
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW2__DW2__SHIFT                                                 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW2__DW2_MASK                                                   0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW3
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW3__DW3__SHIFT                                                 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW3__DW3_MASK                                                   0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW4
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW4__DW4__SHIFT                                                 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW4__DW4_MASK                                                   0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW5
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW5__DW5__SHIFT                                                 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW5__DW5_MASK                                                   0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW6
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW6__DW6__SHIFT                                                 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW6__DW6_MASK                                                   0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW7
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW7__DW7__SHIFT                                                 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW7__DW7_MASK                                                   0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW8
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW8__DW8__SHIFT                                                 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW8__DW8_MASK                                                   0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW0__DW0__SHIFT                                                 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW0__DW0_MASK                                                   0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW1
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW1__DW1__SHIFT                                                 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW1__DW1_MASK                                                   0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW2
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW2__DW2__SHIFT                                                 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW2__DW2_MASK                                                   0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW3
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW3__DW3__SHIFT                                                 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW3__DW3_MASK                                                   0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW4
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW4__DW4__SHIFT                                                 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW4__DW4_MASK                                                   0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW5
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW5__DW5__SHIFT                                                 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW5__DW5_MASK                                                   0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW6
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW6__DW6__SHIFT                                                 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW6__DW6_MASK                                                   0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW7
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW7__DW7__SHIFT                                                 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW7__DW7_MASK                                                   0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW8
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW8__DW8__SHIFT                                                 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW8__DW8_MASK                                                   0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW0__DW0__SHIFT                                                 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW0__DW0_MASK                                                   0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW1
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW1__DW1__SHIFT                                                 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW1__DW1_MASK                                                   0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW2
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW2__DW2__SHIFT                                                 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW2__DW2_MASK                                                   0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW3
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW3__DW3__SHIFT                                                 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW3__DW3_MASK                                                   0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW4
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW4__DW4__SHIFT                                                 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW4__DW4_MASK                                                   0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW5
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW5__DW5__SHIFT                                                 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW5__DW5_MASK                                                   0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW6
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW6__DW6__SHIFT                                                 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW6__DW6_MASK                                                   0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW7
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW7__DW7__SHIFT                                                 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW7__DW7_MASK                                                   0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW8
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW8__DW8__SHIFT                                                 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW8__DW8_MASK                                                   0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW0__DW0__SHIFT                                                 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW0__DW0_MASK                                                   0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW1
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW1__DW1__SHIFT                                                 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW1__DW1_MASK                                                   0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW2
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW2__DW2__SHIFT                                                 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW2__DW2_MASK                                                   0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW3
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW3__DW3__SHIFT                                                 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW3__DW3_MASK                                                   0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW4
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW4__DW4__SHIFT                                                 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW4__DW4_MASK                                                   0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW5
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW5__DW5__SHIFT                                                 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW5__DW5_MASK                                                   0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW6
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW6__DW6__SHIFT                                                 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW6__DW6_MASK                                                   0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW7
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW7__DW7__SHIFT                                                 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW7__DW7_MASK                                                   0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW8
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW8__DW8__SHIFT                                                 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW8__DW8_MASK                                                   0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW0__DW0__SHIFT                                                 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW0__DW0_MASK                                                   0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW1
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW1__DW1__SHIFT                                                 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW1__DW1_MASK                                                   0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW2
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW2__DW2__SHIFT                                                 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW2__DW2_MASK                                                   0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW3
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW3__DW3__SHIFT                                                 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW3__DW3_MASK                                                   0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW4
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW4__DW4__SHIFT                                                 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW4__DW4_MASK                                                   0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW5
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW5__DW5__SHIFT                                                 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW5__DW5_MASK                                                   0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW6
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW6__DW6__SHIFT                                                 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW6__DW6_MASK                                                   0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW7
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW7__DW7__SHIFT                                                 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW7__DW7_MASK                                                   0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW8
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW8__DW8__SHIFT                                                 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW8__DW8_MASK                                                   0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW0__DW0__SHIFT                                                 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW0__DW0_MASK                                                   0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW1
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW1__DW1__SHIFT                                                 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW1__DW1_MASK                                                   0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW2
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW2__DW2__SHIFT                                                 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW2__DW2_MASK                                                   0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW3
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW3__DW3__SHIFT                                                 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW3__DW3_MASK                                                   0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW4
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW4__DW4__SHIFT                                                 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW4__DW4_MASK                                                   0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW5
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW5__DW5__SHIFT                                                 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW5__DW5_MASK                                                   0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW6
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW6__DW6__SHIFT                                                 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW6__DW6_MASK                                                   0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW7
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW7__DW7__SHIFT                                                 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW7__DW7_MASK                                                   0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW8
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW8__DW8__SHIFT                                                 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW8__DW8_MASK                                                   0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW0__DW0__SHIFT                                                 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW0__DW0_MASK                                                   0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW1
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW1__DW1__SHIFT                                                 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW1__DW1_MASK                                                   0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW2
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW2__DW2__SHIFT                                                 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW2__DW2_MASK                                                   0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW3
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW3__DW3__SHIFT                                                 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW3__DW3_MASK                                                   0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW4
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW4__DW4__SHIFT                                                 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW4__DW4_MASK                                                   0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW5
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW5__DW5__SHIFT                                                 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW5__DW5_MASK                                                   0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW6
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW6__DW6__SHIFT                                                 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW6__DW6_MASK                                                   0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW7
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW7__DW7__SHIFT                                                 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW7__DW7_MASK                                                   0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW8
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW8__DW8__SHIFT                                                 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW8__DW8_MASK                                                   0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW0__DW0__SHIFT                                                 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW0__DW0_MASK                                                   0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW1
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW1__DW1__SHIFT                                                 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW1__DW1_MASK                                                   0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW2
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW2__DW2__SHIFT                                                 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW2__DW2_MASK                                                   0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW3
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW3__DW3__SHIFT                                                 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW3__DW3_MASK                                                   0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW4
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW4__DW4__SHIFT                                                 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW4__DW4_MASK                                                   0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW5
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW5__DW5__SHIFT                                                 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW5__DW5_MASK                                                   0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW6
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW6__DW6__SHIFT                                                 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW6__DW6_MASK                                                   0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW7
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW7__DW7__SHIFT                                                 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW7__DW7_MASK                                                   0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW8
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW8__DW8__SHIFT                                                 0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW8__DW8_MASK                                                   0xFFFFFFFFL
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_0_CMD_COMPLETE_INTR_EN__SHIFT                0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_0_HANG_SELF_RECOVERED_INTR_EN__SHIFT         0x1
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_0_HANG_NEED_FLR_INTR_EN__SHIFT               0x2
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_0_VM_BUSY_TRANSITION_INTR_EN__SHIFT          0x3
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_1_CMD_COMPLETE_INTR_EN__SHIFT                0x4
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_1_HANG_SELF_RECOVERED_INTR_EN__SHIFT         0x5
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_1_HANG_NEED_FLR_INTR_EN__SHIFT               0x6
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_1_VM_BUSY_TRANSITION_INTR_EN__SHIFT          0x7
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_2_CMD_COMPLETE_INTR_EN__SHIFT                0x8
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_2_HANG_SELF_RECOVERED_INTR_EN__SHIFT         0x9
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_2_HANG_NEED_FLR_INTR_EN__SHIFT               0xa
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_2_VM_BUSY_TRANSITION_INTR_EN__SHIFT          0xb
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_3_CMD_COMPLETE_INTR_EN__SHIFT                0xc
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_3_HANG_SELF_RECOVERED_INTR_EN__SHIFT         0xd
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_3_HANG_NEED_FLR_INTR_EN__SHIFT               0xe
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_3_VM_BUSY_TRANSITION_INTR_EN__SHIFT          0xf
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_4_CMD_COMPLETE_INTR_EN__SHIFT                0x10
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_4_HANG_SELF_RECOVERED_INTR_EN__SHIFT         0x11
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_4_HANG_NEED_FLR_INTR_EN__SHIFT               0x12
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_4_VM_BUSY_TRANSITION_INTR_EN__SHIFT          0x13
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_5_CMD_COMPLETE_INTR_EN__SHIFT                0x14
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_5_HANG_SELF_RECOVERED_INTR_EN__SHIFT         0x15
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_5_HANG_NEED_FLR_INTR_EN__SHIFT               0x16
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_5_VM_BUSY_TRANSITION_INTR_EN__SHIFT          0x17
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_6_CMD_COMPLETE_INTR_EN__SHIFT                0x18
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_6_HANG_SELF_RECOVERED_INTR_EN__SHIFT         0x19
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_6_HANG_NEED_FLR_INTR_EN__SHIFT               0x1a
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_6_VM_BUSY_TRANSITION_INTR_EN__SHIFT          0x1b
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_7_CMD_COMPLETE_INTR_EN__SHIFT                0x1c
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_7_HANG_SELF_RECOVERED_INTR_EN__SHIFT         0x1d
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_7_HANG_NEED_FLR_INTR_EN__SHIFT               0x1e
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_7_VM_BUSY_TRANSITION_INTR_EN__SHIFT          0x1f
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_0_CMD_COMPLETE_INTR_EN_MASK                  0x00000001L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_0_HANG_SELF_RECOVERED_INTR_EN_MASK           0x00000002L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_0_HANG_NEED_FLR_INTR_EN_MASK                 0x00000004L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_0_VM_BUSY_TRANSITION_INTR_EN_MASK            0x00000008L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_1_CMD_COMPLETE_INTR_EN_MASK                  0x00000010L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_1_HANG_SELF_RECOVERED_INTR_EN_MASK           0x00000020L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_1_HANG_NEED_FLR_INTR_EN_MASK                 0x00000040L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_1_VM_BUSY_TRANSITION_INTR_EN_MASK            0x00000080L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_2_CMD_COMPLETE_INTR_EN_MASK                  0x00000100L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_2_HANG_SELF_RECOVERED_INTR_EN_MASK           0x00000200L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_2_HANG_NEED_FLR_INTR_EN_MASK                 0x00000400L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_2_VM_BUSY_TRANSITION_INTR_EN_MASK            0x00000800L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_3_CMD_COMPLETE_INTR_EN_MASK                  0x00001000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_3_HANG_SELF_RECOVERED_INTR_EN_MASK           0x00002000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_3_HANG_NEED_FLR_INTR_EN_MASK                 0x00004000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_3_VM_BUSY_TRANSITION_INTR_EN_MASK            0x00008000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_4_CMD_COMPLETE_INTR_EN_MASK                  0x00010000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_4_HANG_SELF_RECOVERED_INTR_EN_MASK           0x00020000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_4_HANG_NEED_FLR_INTR_EN_MASK                 0x00040000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_4_VM_BUSY_TRANSITION_INTR_EN_MASK            0x00080000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_5_CMD_COMPLETE_INTR_EN_MASK                  0x00100000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_5_HANG_SELF_RECOVERED_INTR_EN_MASK           0x00200000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_5_HANG_NEED_FLR_INTR_EN_MASK                 0x00400000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_5_VM_BUSY_TRANSITION_INTR_EN_MASK            0x00800000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_6_CMD_COMPLETE_INTR_EN_MASK                  0x01000000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_6_HANG_SELF_RECOVERED_INTR_EN_MASK           0x02000000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_6_HANG_NEED_FLR_INTR_EN_MASK                 0x04000000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_6_VM_BUSY_TRANSITION_INTR_EN_MASK            0x08000000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_7_CMD_COMPLETE_INTR_EN_MASK                  0x10000000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_7_HANG_SELF_RECOVERED_INTR_EN_MASK           0x20000000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_7_HANG_NEED_FLR_INTR_EN_MASK                 0x40000000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_7_VM_BUSY_TRANSITION_INTR_EN_MASK            0x80000000L
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_8_CMD_COMPLETE_INTR_EN__SHIFT               0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_8_HANG_SELF_RECOVERED_INTR_EN__SHIFT        0x1
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_8_HANG_NEED_FLR_INTR_EN__SHIFT              0x2
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_8_VM_BUSY_TRANSITION_INTR_EN__SHIFT         0x3
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_9_CMD_COMPLETE_INTR_EN__SHIFT               0x4
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_9_HANG_SELF_RECOVERED_INTR_EN__SHIFT        0x5
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_9_HANG_NEED_FLR_INTR_EN__SHIFT              0x6
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_9_VM_BUSY_TRANSITION_INTR_EN__SHIFT         0x7
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_10_CMD_COMPLETE_INTR_EN__SHIFT              0x8
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_10_HANG_SELF_RECOVERED_INTR_EN__SHIFT       0x9
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_10_HANG_NEED_FLR_INTR_EN__SHIFT             0xa
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_10_VM_BUSY_TRANSITION_INTR_EN__SHIFT        0xb
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_11_CMD_COMPLETE_INTR_EN__SHIFT              0xc
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_11_HANG_SELF_RECOVERED_INTR_EN__SHIFT       0xd
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_11_HANG_NEED_FLR_INTR_EN__SHIFT             0xe
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_11_VM_BUSY_TRANSITION_INTR_EN__SHIFT        0xf
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_12_CMD_COMPLETE_INTR_EN__SHIFT              0x10
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_12_HANG_SELF_RECOVERED_INTR_EN__SHIFT       0x11
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_12_HANG_NEED_FLR_INTR_EN__SHIFT             0x12
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_12_VM_BUSY_TRANSITION_INTR_EN__SHIFT        0x13
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_13_CMD_COMPLETE_INTR_EN__SHIFT              0x14
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_13_HANG_SELF_RECOVERED_INTR_EN__SHIFT       0x15
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_13_HANG_NEED_FLR_INTR_EN__SHIFT             0x16
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_13_VM_BUSY_TRANSITION_INTR_EN__SHIFT        0x17
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_14_CMD_COMPLETE_INTR_EN__SHIFT              0x18
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_14_HANG_SELF_RECOVERED_INTR_EN__SHIFT       0x19
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_14_HANG_NEED_FLR_INTR_EN__SHIFT             0x1a
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_14_VM_BUSY_TRANSITION_INTR_EN__SHIFT        0x1b
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_15_CMD_COMPLETE_INTR_EN__SHIFT              0x1c
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_15_HANG_SELF_RECOVERED_INTR_EN__SHIFT       0x1d
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_15_HANG_NEED_FLR_INTR_EN__SHIFT             0x1e
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_15_VM_BUSY_TRANSITION_INTR_EN__SHIFT        0x1f
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_8_CMD_COMPLETE_INTR_EN_MASK                 0x00000001L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_8_HANG_SELF_RECOVERED_INTR_EN_MASK          0x00000002L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_8_HANG_NEED_FLR_INTR_EN_MASK                0x00000004L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_8_VM_BUSY_TRANSITION_INTR_EN_MASK           0x00000008L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_9_CMD_COMPLETE_INTR_EN_MASK                 0x00000010L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_9_HANG_SELF_RECOVERED_INTR_EN_MASK          0x00000020L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_9_HANG_NEED_FLR_INTR_EN_MASK                0x00000040L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_9_VM_BUSY_TRANSITION_INTR_EN_MASK           0x00000080L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_10_CMD_COMPLETE_INTR_EN_MASK                0x00000100L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_10_HANG_SELF_RECOVERED_INTR_EN_MASK         0x00000200L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_10_HANG_NEED_FLR_INTR_EN_MASK               0x00000400L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_10_VM_BUSY_TRANSITION_INTR_EN_MASK          0x00000800L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_11_CMD_COMPLETE_INTR_EN_MASK                0x00001000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_11_HANG_SELF_RECOVERED_INTR_EN_MASK         0x00002000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_11_HANG_NEED_FLR_INTR_EN_MASK               0x00004000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_11_VM_BUSY_TRANSITION_INTR_EN_MASK          0x00008000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_12_CMD_COMPLETE_INTR_EN_MASK                0x00010000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_12_HANG_SELF_RECOVERED_INTR_EN_MASK         0x00020000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_12_HANG_NEED_FLR_INTR_EN_MASK               0x00040000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_12_VM_BUSY_TRANSITION_INTR_EN_MASK          0x00080000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_13_CMD_COMPLETE_INTR_EN_MASK                0x00100000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_13_HANG_SELF_RECOVERED_INTR_EN_MASK         0x00200000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_13_HANG_NEED_FLR_INTR_EN_MASK               0x00400000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_13_VM_BUSY_TRANSITION_INTR_EN_MASK          0x00800000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_14_CMD_COMPLETE_INTR_EN_MASK                0x01000000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_14_HANG_SELF_RECOVERED_INTR_EN_MASK         0x02000000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_14_HANG_NEED_FLR_INTR_EN_MASK               0x04000000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_14_VM_BUSY_TRANSITION_INTR_EN_MASK          0x08000000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_15_CMD_COMPLETE_INTR_EN_MASK                0x10000000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_15_HANG_SELF_RECOVERED_INTR_EN_MASK         0x20000000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_15_HANG_NEED_FLR_INTR_EN_MASK               0x40000000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_15_VM_BUSY_TRANSITION_INTR_EN_MASK          0x80000000L
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_16_CMD_COMPLETE_INTR_EN__SHIFT             0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_16_HANG_SELF_RECOVERED_INTR_EN__SHIFT      0x1
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_16_HANG_NEED_FLR_INTR_EN__SHIFT            0x2
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_16_VM_BUSY_TRANSITION_INTR_EN__SHIFT       0x3
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_17_CMD_COMPLETE_INTR_EN__SHIFT             0x4
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_17_HANG_SELF_RECOVERED_INTR_EN__SHIFT      0x5
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_17_HANG_NEED_FLR_INTR_EN__SHIFT            0x6
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_17_VM_BUSY_TRANSITION_INTR_EN__SHIFT       0x7
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_18_CMD_COMPLETE_INTR_EN__SHIFT             0x8
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_18_HANG_SELF_RECOVERED_INTR_EN__SHIFT      0x9
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_18_HANG_NEED_FLR_INTR_EN__SHIFT            0xa
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_18_VM_BUSY_TRANSITION_INTR_EN__SHIFT       0xb
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_19_CMD_COMPLETE_INTR_EN__SHIFT             0xc
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_19_HANG_SELF_RECOVERED_INTR_EN__SHIFT      0xd
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_19_HANG_NEED_FLR_INTR_EN__SHIFT            0xe
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_19_VM_BUSY_TRANSITION_INTR_EN__SHIFT       0xf
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_20_CMD_COMPLETE_INTR_EN__SHIFT             0x10
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_20_HANG_SELF_RECOVERED_INTR_EN__SHIFT      0x11
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_20_HANG_NEED_FLR_INTR_EN__SHIFT            0x12
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_20_VM_BUSY_TRANSITION_INTR_EN__SHIFT       0x13
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_21_CMD_COMPLETE_INTR_EN__SHIFT             0x14
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_21_HANG_SELF_RECOVERED_INTR_EN__SHIFT      0x15
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_21_HANG_NEED_FLR_INTR_EN__SHIFT            0x16
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_21_VM_BUSY_TRANSITION_INTR_EN__SHIFT       0x17
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_22_CMD_COMPLETE_INTR_EN__SHIFT             0x18
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_22_HANG_SELF_RECOVERED_INTR_EN__SHIFT      0x19
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_22_HANG_NEED_FLR_INTR_EN__SHIFT            0x1a
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_22_VM_BUSY_TRANSITION_INTR_EN__SHIFT       0x1b
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_23_CMD_COMPLETE_INTR_EN__SHIFT             0x1c
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_23_HANG_SELF_RECOVERED_INTR_EN__SHIFT      0x1d
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_23_HANG_NEED_FLR_INTR_EN__SHIFT            0x1e
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_23_VM_BUSY_TRANSITION_INTR_EN__SHIFT       0x1f
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_16_CMD_COMPLETE_INTR_EN_MASK               0x00000001L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_16_HANG_SELF_RECOVERED_INTR_EN_MASK        0x00000002L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_16_HANG_NEED_FLR_INTR_EN_MASK              0x00000004L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_16_VM_BUSY_TRANSITION_INTR_EN_MASK         0x00000008L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_17_CMD_COMPLETE_INTR_EN_MASK               0x00000010L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_17_HANG_SELF_RECOVERED_INTR_EN_MASK        0x00000020L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_17_HANG_NEED_FLR_INTR_EN_MASK              0x00000040L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_17_VM_BUSY_TRANSITION_INTR_EN_MASK         0x00000080L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_18_CMD_COMPLETE_INTR_EN_MASK               0x00000100L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_18_HANG_SELF_RECOVERED_INTR_EN_MASK        0x00000200L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_18_HANG_NEED_FLR_INTR_EN_MASK              0x00000400L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_18_VM_BUSY_TRANSITION_INTR_EN_MASK         0x00000800L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_19_CMD_COMPLETE_INTR_EN_MASK               0x00001000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_19_HANG_SELF_RECOVERED_INTR_EN_MASK        0x00002000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_19_HANG_NEED_FLR_INTR_EN_MASK              0x00004000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_19_VM_BUSY_TRANSITION_INTR_EN_MASK         0x00008000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_20_CMD_COMPLETE_INTR_EN_MASK               0x00010000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_20_HANG_SELF_RECOVERED_INTR_EN_MASK        0x00020000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_20_HANG_NEED_FLR_INTR_EN_MASK              0x00040000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_20_VM_BUSY_TRANSITION_INTR_EN_MASK         0x00080000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_21_CMD_COMPLETE_INTR_EN_MASK               0x00100000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_21_HANG_SELF_RECOVERED_INTR_EN_MASK        0x00200000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_21_HANG_NEED_FLR_INTR_EN_MASK              0x00400000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_21_VM_BUSY_TRANSITION_INTR_EN_MASK         0x00800000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_22_CMD_COMPLETE_INTR_EN_MASK               0x01000000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_22_HANG_SELF_RECOVERED_INTR_EN_MASK        0x02000000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_22_HANG_NEED_FLR_INTR_EN_MASK              0x04000000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_22_VM_BUSY_TRANSITION_INTR_EN_MASK         0x08000000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_23_CMD_COMPLETE_INTR_EN_MASK               0x10000000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_23_HANG_SELF_RECOVERED_INTR_EN_MASK        0x20000000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_23_HANG_NEED_FLR_INTR_EN_MASK              0x40000000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_23_VM_BUSY_TRANSITION_INTR_EN_MASK         0x80000000L
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_24_CMD_COMPLETE_INTR_EN__SHIFT             0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_24_HANG_SELF_RECOVERED_INTR_EN__SHIFT      0x1
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_24_HANG_NEED_FLR_INTR_EN__SHIFT            0x2
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_24_VM_BUSY_TRANSITION_INTR_EN__SHIFT       0x3
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_25_CMD_COMPLETE_INTR_EN__SHIFT             0x4
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_25_HANG_SELF_RECOVERED_INTR_EN__SHIFT      0x5
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_25_HANG_NEED_FLR_INTR_EN__SHIFT            0x6
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_25_VM_BUSY_TRANSITION_INTR_EN__SHIFT       0x7
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_26_CMD_COMPLETE_INTR_EN__SHIFT             0x8
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_26_HANG_SELF_RECOVERED_INTR_EN__SHIFT      0x9
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_26_HANG_NEED_FLR_INTR_EN__SHIFT            0xa
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_26_VM_BUSY_TRANSITION_INTR_EN__SHIFT       0xb
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_27_CMD_COMPLETE_INTR_EN__SHIFT             0xc
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_27_HANG_SELF_RECOVERED_INTR_EN__SHIFT      0xd
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_27_HANG_NEED_FLR_INTR_EN__SHIFT            0xe
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_27_VM_BUSY_TRANSITION_INTR_EN__SHIFT       0xf
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_28_CMD_COMPLETE_INTR_EN__SHIFT             0x10
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_28_HANG_SELF_RECOVERED_INTR_EN__SHIFT      0x11
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_28_HANG_NEED_FLR_INTR_EN__SHIFT            0x12
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_28_VM_BUSY_TRANSITION_INTR_EN__SHIFT       0x13
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_29_CMD_COMPLETE_INTR_EN__SHIFT             0x14
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_29_HANG_SELF_RECOVERED_INTR_EN__SHIFT      0x15
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_29_HANG_NEED_FLR_INTR_EN__SHIFT            0x16
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_29_VM_BUSY_TRANSITION_INTR_EN__SHIFT       0x17
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_30_CMD_COMPLETE_INTR_EN__SHIFT             0x18
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_30_HANG_SELF_RECOVERED_INTR_EN__SHIFT      0x19
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_30_HANG_NEED_FLR_INTR_EN__SHIFT            0x1a
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_30_VM_BUSY_TRANSITION_INTR_EN__SHIFT       0x1b
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_31_CMD_COMPLETE_INTR_EN__SHIFT             0x1c
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_31_HANG_SELF_RECOVERED_INTR_EN__SHIFT      0x1d
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_31_HANG_NEED_FLR_INTR_EN__SHIFT            0x1e
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_31_VM_BUSY_TRANSITION_INTR_EN__SHIFT       0x1f
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_24_CMD_COMPLETE_INTR_EN_MASK               0x00000001L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_24_HANG_SELF_RECOVERED_INTR_EN_MASK        0x00000002L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_24_HANG_NEED_FLR_INTR_EN_MASK              0x00000004L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_24_VM_BUSY_TRANSITION_INTR_EN_MASK         0x00000008L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_25_CMD_COMPLETE_INTR_EN_MASK               0x00000010L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_25_HANG_SELF_RECOVERED_INTR_EN_MASK        0x00000020L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_25_HANG_NEED_FLR_INTR_EN_MASK              0x00000040L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_25_VM_BUSY_TRANSITION_INTR_EN_MASK         0x00000080L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_26_CMD_COMPLETE_INTR_EN_MASK               0x00000100L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_26_HANG_SELF_RECOVERED_INTR_EN_MASK        0x00000200L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_26_HANG_NEED_FLR_INTR_EN_MASK              0x00000400L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_26_VM_BUSY_TRANSITION_INTR_EN_MASK         0x00000800L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_27_CMD_COMPLETE_INTR_EN_MASK               0x00001000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_27_HANG_SELF_RECOVERED_INTR_EN_MASK        0x00002000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_27_HANG_NEED_FLR_INTR_EN_MASK              0x00004000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_27_VM_BUSY_TRANSITION_INTR_EN_MASK         0x00008000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_28_CMD_COMPLETE_INTR_EN_MASK               0x00010000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_28_HANG_SELF_RECOVERED_INTR_EN_MASK        0x00020000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_28_HANG_NEED_FLR_INTR_EN_MASK              0x00040000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_28_VM_BUSY_TRANSITION_INTR_EN_MASK         0x00080000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_29_CMD_COMPLETE_INTR_EN_MASK               0x00100000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_29_HANG_SELF_RECOVERED_INTR_EN_MASK        0x00200000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_29_HANG_NEED_FLR_INTR_EN_MASK              0x00400000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_29_VM_BUSY_TRANSITION_INTR_EN_MASK         0x00800000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_30_CMD_COMPLETE_INTR_EN_MASK               0x01000000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_30_HANG_SELF_RECOVERED_INTR_EN_MASK        0x02000000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_30_HANG_NEED_FLR_INTR_EN_MASK              0x04000000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_30_VM_BUSY_TRANSITION_INTR_EN_MASK         0x08000000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_31_CMD_COMPLETE_INTR_EN_MASK               0x10000000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_31_HANG_SELF_RECOVERED_INTR_EN_MASK        0x20000000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_31_HANG_NEED_FLR_INTR_EN_MASK              0x40000000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_31_VM_BUSY_TRANSITION_INTR_EN_MASK         0x80000000L
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_0_CMD_COMPLETE_INTR_STATUS__SHIFT            0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_0_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT     0x1
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_0_HANG_NEED_FLR_INTR_STATUS__SHIFT           0x2
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_0_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT      0x3
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_1_CMD_COMPLETE_INTR_STATUS__SHIFT            0x4
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_1_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT     0x5
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_1_HANG_NEED_FLR_INTR_STATUS__SHIFT           0x6
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_1_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT      0x7
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_2_CMD_COMPLETE_INTR_STATUS__SHIFT            0x8
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_2_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT     0x9
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_2_HANG_NEED_FLR_INTR_STATUS__SHIFT           0xa
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_2_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT      0xb
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_3_CMD_COMPLETE_INTR_STATUS__SHIFT            0xc
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_3_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT     0xd
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_3_HANG_NEED_FLR_INTR_STATUS__SHIFT           0xe
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_3_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT      0xf
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_4_CMD_COMPLETE_INTR_STATUS__SHIFT            0x10
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_4_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT     0x11
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_4_HANG_NEED_FLR_INTR_STATUS__SHIFT           0x12
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_4_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT      0x13
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_5_CMD_COMPLETE_INTR_STATUS__SHIFT            0x14
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_5_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT     0x15
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_5_HANG_NEED_FLR_INTR_STATUS__SHIFT           0x16
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_5_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT      0x17
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_6_CMD_COMPLETE_INTR_STATUS__SHIFT            0x18
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_6_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT     0x19
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_6_HANG_NEED_FLR_INTR_STATUS__SHIFT           0x1a
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_6_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT      0x1b
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_7_CMD_COMPLETE_INTR_STATUS__SHIFT            0x1c
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_7_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT     0x1d
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_7_HANG_NEED_FLR_INTR_STATUS__SHIFT           0x1e
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_7_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT      0x1f
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_0_CMD_COMPLETE_INTR_STATUS_MASK              0x00000001L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_0_HANG_SELF_RECOVERED_INTR_STATUS_MASK       0x00000002L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_0_HANG_NEED_FLR_INTR_STATUS_MASK             0x00000004L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_0_VM_BUSY_TRANSITION_INTR_STATUS_MASK        0x00000008L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_1_CMD_COMPLETE_INTR_STATUS_MASK              0x00000010L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_1_HANG_SELF_RECOVERED_INTR_STATUS_MASK       0x00000020L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_1_HANG_NEED_FLR_INTR_STATUS_MASK             0x00000040L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_1_VM_BUSY_TRANSITION_INTR_STATUS_MASK        0x00000080L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_2_CMD_COMPLETE_INTR_STATUS_MASK              0x00000100L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_2_HANG_SELF_RECOVERED_INTR_STATUS_MASK       0x00000200L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_2_HANG_NEED_FLR_INTR_STATUS_MASK             0x00000400L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_2_VM_BUSY_TRANSITION_INTR_STATUS_MASK        0x00000800L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_3_CMD_COMPLETE_INTR_STATUS_MASK              0x00001000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_3_HANG_SELF_RECOVERED_INTR_STATUS_MASK       0x00002000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_3_HANG_NEED_FLR_INTR_STATUS_MASK             0x00004000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_3_VM_BUSY_TRANSITION_INTR_STATUS_MASK        0x00008000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_4_CMD_COMPLETE_INTR_STATUS_MASK              0x00010000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_4_HANG_SELF_RECOVERED_INTR_STATUS_MASK       0x00020000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_4_HANG_NEED_FLR_INTR_STATUS_MASK             0x00040000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_4_VM_BUSY_TRANSITION_INTR_STATUS_MASK        0x00080000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_5_CMD_COMPLETE_INTR_STATUS_MASK              0x00100000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_5_HANG_SELF_RECOVERED_INTR_STATUS_MASK       0x00200000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_5_HANG_NEED_FLR_INTR_STATUS_MASK             0x00400000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_5_VM_BUSY_TRANSITION_INTR_STATUS_MASK        0x00800000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_6_CMD_COMPLETE_INTR_STATUS_MASK              0x01000000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_6_HANG_SELF_RECOVERED_INTR_STATUS_MASK       0x02000000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_6_HANG_NEED_FLR_INTR_STATUS_MASK             0x04000000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_6_VM_BUSY_TRANSITION_INTR_STATUS_MASK        0x08000000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_7_CMD_COMPLETE_INTR_STATUS_MASK              0x10000000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_7_HANG_SELF_RECOVERED_INTR_STATUS_MASK       0x20000000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_7_HANG_NEED_FLR_INTR_STATUS_MASK             0x40000000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_7_VM_BUSY_TRANSITION_INTR_STATUS_MASK        0x80000000L
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_8_CMD_COMPLETE_INTR_STATUS__SHIFT           0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_8_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT    0x1
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_8_HANG_NEED_FLR_INTR_STATUS__SHIFT          0x2
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_8_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT     0x3
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_9_CMD_COMPLETE_INTR_STATUS__SHIFT           0x4
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_9_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT    0x5
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_9_HANG_NEED_FLR_INTR_STATUS__SHIFT          0x6
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_9_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT     0x7
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_10_CMD_COMPLETE_INTR_STATUS__SHIFT          0x8
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_10_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT   0x9
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_10_HANG_NEED_FLR_INTR_STATUS__SHIFT         0xa
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_10_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT    0xb
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_11_CMD_COMPLETE_INTR_STATUS__SHIFT          0xc
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_11_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT   0xd
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_11_HANG_NEED_FLR_INTR_STATUS__SHIFT         0xe
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_11_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT    0xf
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_12_CMD_COMPLETE_INTR_STATUS__SHIFT          0x10
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_12_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT   0x11
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_12_HANG_NEED_FLR_INTR_STATUS__SHIFT         0x12
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_12_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT    0x13
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_13_CMD_COMPLETE_INTR_STATUS__SHIFT          0x14
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_13_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT   0x15
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_13_HANG_NEED_FLR_INTR_STATUS__SHIFT         0x16
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_13_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT    0x17
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_14_CMD_COMPLETE_INTR_STATUS__SHIFT          0x18
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_14_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT   0x19
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_14_HANG_NEED_FLR_INTR_STATUS__SHIFT         0x1a
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_14_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT    0x1b
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_15_CMD_COMPLETE_INTR_STATUS__SHIFT          0x1c
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_15_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT   0x1d
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_15_HANG_NEED_FLR_INTR_STATUS__SHIFT         0x1e
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_15_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT    0x1f
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_8_CMD_COMPLETE_INTR_STATUS_MASK             0x00000001L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_8_HANG_SELF_RECOVERED_INTR_STATUS_MASK      0x00000002L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_8_HANG_NEED_FLR_INTR_STATUS_MASK            0x00000004L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_8_VM_BUSY_TRANSITION_INTR_STATUS_MASK       0x00000008L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_9_CMD_COMPLETE_INTR_STATUS_MASK             0x00000010L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_9_HANG_SELF_RECOVERED_INTR_STATUS_MASK      0x00000020L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_9_HANG_NEED_FLR_INTR_STATUS_MASK            0x00000040L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_9_VM_BUSY_TRANSITION_INTR_STATUS_MASK       0x00000080L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_10_CMD_COMPLETE_INTR_STATUS_MASK            0x00000100L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_10_HANG_SELF_RECOVERED_INTR_STATUS_MASK     0x00000200L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_10_HANG_NEED_FLR_INTR_STATUS_MASK           0x00000400L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_10_VM_BUSY_TRANSITION_INTR_STATUS_MASK      0x00000800L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_11_CMD_COMPLETE_INTR_STATUS_MASK            0x00001000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_11_HANG_SELF_RECOVERED_INTR_STATUS_MASK     0x00002000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_11_HANG_NEED_FLR_INTR_STATUS_MASK           0x00004000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_11_VM_BUSY_TRANSITION_INTR_STATUS_MASK      0x00008000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_12_CMD_COMPLETE_INTR_STATUS_MASK            0x00010000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_12_HANG_SELF_RECOVERED_INTR_STATUS_MASK     0x00020000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_12_HANG_NEED_FLR_INTR_STATUS_MASK           0x00040000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_12_VM_BUSY_TRANSITION_INTR_STATUS_MASK      0x00080000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_13_CMD_COMPLETE_INTR_STATUS_MASK            0x00100000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_13_HANG_SELF_RECOVERED_INTR_STATUS_MASK     0x00200000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_13_HANG_NEED_FLR_INTR_STATUS_MASK           0x00400000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_13_VM_BUSY_TRANSITION_INTR_STATUS_MASK      0x00800000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_14_CMD_COMPLETE_INTR_STATUS_MASK            0x01000000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_14_HANG_SELF_RECOVERED_INTR_STATUS_MASK     0x02000000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_14_HANG_NEED_FLR_INTR_STATUS_MASK           0x04000000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_14_VM_BUSY_TRANSITION_INTR_STATUS_MASK      0x08000000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_15_CMD_COMPLETE_INTR_STATUS_MASK            0x10000000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_15_HANG_SELF_RECOVERED_INTR_STATUS_MASK     0x20000000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_15_HANG_NEED_FLR_INTR_STATUS_MASK           0x40000000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_15_VM_BUSY_TRANSITION_INTR_STATUS_MASK      0x80000000L
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_16_CMD_COMPLETE_INTR_STATUS__SHIFT         0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_16_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT  0x1
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_16_HANG_NEED_FLR_INTR_STATUS__SHIFT        0x2
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_16_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT   0x3
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_17_CMD_COMPLETE_INTR_STATUS__SHIFT         0x4
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_17_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT  0x5
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_17_HANG_NEED_FLR_INTR_STATUS__SHIFT        0x6
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_17_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT   0x7
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_18_CMD_COMPLETE_INTR_STATUS__SHIFT         0x8
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_18_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT  0x9
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_18_HANG_NEED_FLR_INTR_STATUS__SHIFT        0xa
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_18_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT   0xb
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_19_CMD_COMPLETE_INTR_STATUS__SHIFT         0xc
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_19_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT  0xd
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_19_HANG_NEED_FLR_INTR_STATUS__SHIFT        0xe
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_19_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT   0xf
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_20_CMD_COMPLETE_INTR_STATUS__SHIFT         0x10
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_20_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT  0x11
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_20_HANG_NEED_FLR_INTR_STATUS__SHIFT        0x12
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_20_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT   0x13
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_21_CMD_COMPLETE_INTR_STATUS__SHIFT         0x14
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_21_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT  0x15
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_21_HANG_NEED_FLR_INTR_STATUS__SHIFT        0x16
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_21_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT   0x17
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_22_CMD_COMPLETE_INTR_STATUS__SHIFT         0x18
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_22_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT  0x19
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_22_HANG_NEED_FLR_INTR_STATUS__SHIFT        0x1a
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_22_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT   0x1b
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_23_CMD_COMPLETE_INTR_STATUS__SHIFT         0x1c
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_23_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT  0x1d
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_23_HANG_NEED_FLR_INTR_STATUS__SHIFT        0x1e
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_23_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT   0x1f
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_16_CMD_COMPLETE_INTR_STATUS_MASK           0x00000001L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_16_HANG_SELF_RECOVERED_INTR_STATUS_MASK    0x00000002L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_16_HANG_NEED_FLR_INTR_STATUS_MASK          0x00000004L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_16_VM_BUSY_TRANSITION_INTR_STATUS_MASK     0x00000008L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_17_CMD_COMPLETE_INTR_STATUS_MASK           0x00000010L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_17_HANG_SELF_RECOVERED_INTR_STATUS_MASK    0x00000020L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_17_HANG_NEED_FLR_INTR_STATUS_MASK          0x00000040L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_17_VM_BUSY_TRANSITION_INTR_STATUS_MASK     0x00000080L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_18_CMD_COMPLETE_INTR_STATUS_MASK           0x00000100L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_18_HANG_SELF_RECOVERED_INTR_STATUS_MASK    0x00000200L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_18_HANG_NEED_FLR_INTR_STATUS_MASK          0x00000400L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_18_VM_BUSY_TRANSITION_INTR_STATUS_MASK     0x00000800L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_19_CMD_COMPLETE_INTR_STATUS_MASK           0x00001000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_19_HANG_SELF_RECOVERED_INTR_STATUS_MASK    0x00002000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_19_HANG_NEED_FLR_INTR_STATUS_MASK          0x00004000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_19_VM_BUSY_TRANSITION_INTR_STATUS_MASK     0x00008000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_20_CMD_COMPLETE_INTR_STATUS_MASK           0x00010000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_20_HANG_SELF_RECOVERED_INTR_STATUS_MASK    0x00020000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_20_HANG_NEED_FLR_INTR_STATUS_MASK          0x00040000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_20_VM_BUSY_TRANSITION_INTR_STATUS_MASK     0x00080000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_21_CMD_COMPLETE_INTR_STATUS_MASK           0x00100000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_21_HANG_SELF_RECOVERED_INTR_STATUS_MASK    0x00200000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_21_HANG_NEED_FLR_INTR_STATUS_MASK          0x00400000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_21_VM_BUSY_TRANSITION_INTR_STATUS_MASK     0x00800000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_22_CMD_COMPLETE_INTR_STATUS_MASK           0x01000000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_22_HANG_SELF_RECOVERED_INTR_STATUS_MASK    0x02000000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_22_HANG_NEED_FLR_INTR_STATUS_MASK          0x04000000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_22_VM_BUSY_TRANSITION_INTR_STATUS_MASK     0x08000000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_23_CMD_COMPLETE_INTR_STATUS_MASK           0x10000000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_23_HANG_SELF_RECOVERED_INTR_STATUS_MASK    0x20000000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_23_HANG_NEED_FLR_INTR_STATUS_MASK          0x40000000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_23_VM_BUSY_TRANSITION_INTR_STATUS_MASK     0x80000000L
+//PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_24_CMD_COMPLETE_INTR_STATUS__SHIFT         0x0
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_24_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT  0x1
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_24_HANG_NEED_FLR_INTR_STATUS__SHIFT        0x2
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_24_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT   0x3
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_25_CMD_COMPLETE_INTR_STATUS__SHIFT         0x4
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_25_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT  0x5
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_25_HANG_NEED_FLR_INTR_STATUS__SHIFT        0x6
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_25_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT   0x7
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_26_CMD_COMPLETE_INTR_STATUS__SHIFT         0x8
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_26_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT  0x9
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_26_HANG_NEED_FLR_INTR_STATUS__SHIFT        0xa
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_26_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT   0xb
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_27_CMD_COMPLETE_INTR_STATUS__SHIFT         0xc
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_27_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT  0xd
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_27_HANG_NEED_FLR_INTR_STATUS__SHIFT        0xe
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_27_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT   0xf
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_28_CMD_COMPLETE_INTR_STATUS__SHIFT         0x10
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_28_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT  0x11
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_28_HANG_NEED_FLR_INTR_STATUS__SHIFT        0x12
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_28_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT   0x13
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_29_CMD_COMPLETE_INTR_STATUS__SHIFT         0x14
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_29_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT  0x15
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_29_HANG_NEED_FLR_INTR_STATUS__SHIFT        0x16
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_29_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT   0x17
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_30_CMD_COMPLETE_INTR_STATUS__SHIFT         0x18
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_30_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT  0x19
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_30_HANG_NEED_FLR_INTR_STATUS__SHIFT        0x1a
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_30_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT   0x1b
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_31_CMD_COMPLETE_INTR_STATUS__SHIFT         0x1c
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_31_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT  0x1d
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_31_HANG_NEED_FLR_INTR_STATUS__SHIFT        0x1e
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_31_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT   0x1f
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_24_CMD_COMPLETE_INTR_STATUS_MASK           0x00000001L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_24_HANG_SELF_RECOVERED_INTR_STATUS_MASK    0x00000002L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_24_HANG_NEED_FLR_INTR_STATUS_MASK          0x00000004L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_24_VM_BUSY_TRANSITION_INTR_STATUS_MASK     0x00000008L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_25_CMD_COMPLETE_INTR_STATUS_MASK           0x00000010L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_25_HANG_SELF_RECOVERED_INTR_STATUS_MASK    0x00000020L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_25_HANG_NEED_FLR_INTR_STATUS_MASK          0x00000040L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_25_VM_BUSY_TRANSITION_INTR_STATUS_MASK     0x00000080L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_26_CMD_COMPLETE_INTR_STATUS_MASK           0x00000100L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_26_HANG_SELF_RECOVERED_INTR_STATUS_MASK    0x00000200L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_26_HANG_NEED_FLR_INTR_STATUS_MASK          0x00000400L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_26_VM_BUSY_TRANSITION_INTR_STATUS_MASK     0x00000800L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_27_CMD_COMPLETE_INTR_STATUS_MASK           0x00001000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_27_HANG_SELF_RECOVERED_INTR_STATUS_MASK    0x00002000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_27_HANG_NEED_FLR_INTR_STATUS_MASK          0x00004000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_27_VM_BUSY_TRANSITION_INTR_STATUS_MASK     0x00008000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_28_CMD_COMPLETE_INTR_STATUS_MASK           0x00010000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_28_HANG_SELF_RECOVERED_INTR_STATUS_MASK    0x00020000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_28_HANG_NEED_FLR_INTR_STATUS_MASK          0x00040000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_28_VM_BUSY_TRANSITION_INTR_STATUS_MASK     0x00080000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_29_CMD_COMPLETE_INTR_STATUS_MASK           0x00100000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_29_HANG_SELF_RECOVERED_INTR_STATUS_MASK    0x00200000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_29_HANG_NEED_FLR_INTR_STATUS_MASK          0x00400000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_29_VM_BUSY_TRANSITION_INTR_STATUS_MASK     0x00800000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_30_CMD_COMPLETE_INTR_STATUS_MASK           0x01000000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_30_HANG_SELF_RECOVERED_INTR_STATUS_MASK    0x02000000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_30_HANG_NEED_FLR_INTR_STATUS_MASK          0x04000000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_30_VM_BUSY_TRANSITION_INTR_STATUS_MASK     0x08000000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_31_CMD_COMPLETE_INTR_STATUS_MASK           0x10000000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_31_HANG_SELF_RECOVERED_INTR_STATUS_MASK    0x20000000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_31_HANG_NEED_FLR_INTR_STATUS_MASK          0x40000000L
+#define PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_31_VM_BUSY_TRANSITION_INTR_STATUS_MASK     0x80000000L
+
+
+// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_bifcfgpciedecp
+//BIF_CFG_DEV0_EPF0_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_SPEED__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_WIDTH__SHIFT                                                         0x4
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__PM_SUPPORT__SHIFT                                                         0xa
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                   0xc
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                    0xf
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                             0x12
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                        0x13
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                        0x14
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                           0x15
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                        0x16
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__PORT_NUMBER__SHIFT                                                        0x18
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_SPEED_MASK                                                           0x0000000FL
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_WIDTH_MASK                                                           0x000003F0L
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__PM_SUPPORT_MASK                                                           0x00000C00L
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                     0x00007000L
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__L1_EXIT_LATENCY_MASK                                                      0x00038000L
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                               0x00040000L
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                          0x00080000L
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                          0x00100000L
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                             0x00200000L
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                          0x00400000L
+#define BIF_CFG_DEV0_EPF0_LINK_CAP__PORT_NUMBER_MASK                                                          0xFF000000L
+//BIF_CFG_DEV0_EPF0_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__PM_CONTROL__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT                                      0x2
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                                 0x3
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_DIS__SHIFT                                                          0x4
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__RETRAIN_LINK__SHIFT                                                      0x5
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                  0x6
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                     0x7
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                         0x8
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                       0x9
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                         0xa
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                         0xb
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__SRIS_CLOCKING__SHIFT                                                     0xc
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__FLIT_MODE_DISABLE__SHIFT                                                 0xd
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                             0xe
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__PM_CONTROL_MASK                                                          0x0003L
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK                                        0x0004L
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                   0x0008L
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_DIS_MASK                                                            0x0010L
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__RETRAIN_LINK_MASK                                                        0x0020L
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                    0x0040L
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__EXTENDED_SYNC_MASK                                                       0x0080L
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                           0x0100L
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                         0x0200L
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                           0x0400L
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                           0x0800L
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__SRIS_CLOCKING_MASK                                                       0x1000L
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__FLIT_MODE_DISABLE_MASK                                                   0x2000L
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                               0xC000L
+//BIF_CFG_DEV0_EPF0_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                           0x4
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_TRAINING__SHIFT                                                   0xb
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                  0xc
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS__DL_ACTIVE__SHIFT                                                       0xd
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                       0xe
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                       0xf
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                                0x000FL
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                             0x03F0L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_TRAINING_MASK                                                     0x0800L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                    0x1000L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS__DL_ACTIVE_MASK                                                         0x2000L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                         0x4000L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                         0x8000L
+//BIF_CFG_DEV0_EPF0_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                              0x1
+#define BIF_CFG_DEV0_EPF0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                               0x8
+#define BIF_CFG_DEV0_EPF0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT                                          0x9
+#define BIF_CFG_DEV0_EPF0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                          0x10
+#define BIF_CFG_DEV0_EPF0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                         0x17
+#define BIF_CFG_DEV0_EPF0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                         0x18
+#define BIF_CFG_DEV0_EPF0_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                     0x1f
+#define BIF_CFG_DEV0_EPF0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                                0x000000FEL
+#define BIF_CFG_DEV0_EPF0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                                 0x00000100L
+#define BIF_CFG_DEV0_EPF0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK                                            0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                            0x007F0000L
+#define BIF_CFG_DEV0_EPF0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                           0x00800000L
+#define BIF_CFG_DEV0_EPF0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                           0x01000000L
+#define BIF_CFG_DEV0_EPF0_LINK_CAP2__DRS_SUPPORTED_MASK                                                       0x80000000L
+//BIF_CFG_DEV0_EPF0_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                                 0x4
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                      0x5
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                            0x6
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                      0x7
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                             0xa
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                   0xb
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                            0xc
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                  0x000FL
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                   0x0010L
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                        0x0020L
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                              0x0040L
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__XMIT_MARGIN_MASK                                                        0x0380L
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                               0x0400L
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                     0x0800L
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                              0xF000L
+//BIF_CFG_DEV0_EPF0_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                      0x1
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                                0x2
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                                0x3
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                                0x4
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                  0x5
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                              0x6
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                              0x7
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                           0x8
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__FLIT_MODE_STATUS__SHIFT                                               0xa
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                  0xc
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                           0xf
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                             0x0001L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                        0x0002L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                  0x0004L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                  0x0008L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                  0x0010L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                    0x0020L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                                0x0040L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                                0x0080L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                             0x0300L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__FLIT_MODE_STATUS_MASK                                                 0x0400L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                    0x7000L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                             0x8000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                  0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                      0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                     0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                    0xFFF00000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                           0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                        0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                             0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                          0xFFF00000L
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                                 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                                 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT                                         0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT                                        0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK                                            0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK                                           0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK                                          0xFFF00000L
+//BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3
+#define BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT                                0x1
+#define BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT                                     0x9
+#define BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK                                          0x00000001L
+#define BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK                                  0x00000002L
+#define BIF_CFG_DEV0_EPF0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK                                       0x0000FE00L
+//BIF_CFG_DEV0_EPF0_PCIE_LANE_ERROR_STATUS
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT                               0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK                                 0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
+//BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
+//BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
+//BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
+//BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
+//BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
+//BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
+//BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
+//BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
+//BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
+//BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                  0x000FL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x0070L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                    0x0F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x7000L
+//BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                  0x000FL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x0070L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                    0x0F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x7000L
+//BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                  0x000FL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x0070L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                    0x0F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x7000L
+//BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                  0x000FL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x0070L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                    0x0F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x7000L
+//BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                  0x000FL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x0070L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                    0x0F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x7000L
+//BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0xc
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                  0x000FL
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x0070L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                    0x0F00L
+#define BIF_CFG_DEV0_EPF0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x7000L
+//BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT                                          0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                         0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK                                             0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK                                            0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK                                           0xFFF00000L
+//BIF_CFG_DEV0_EPF0_LINK_CAP_16GT
+#define BIF_CFG_DEV0_EPF0_LINK_CAP_16GT__RESERVED__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF0_LINK_CAP_16GT__RESERVED_MASK                                                        0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_LINK_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL_16GT__RESERVED__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL_16GT__RESERVED_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT                                 0x0
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT                           0x1
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT                           0x2
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT                           0x3
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT                             0x4
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK                                   0x00000001L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK                             0x00000002L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK                             0x00000004L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK                             0x00000008L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK                               0x00000010L
+//BIF_CFG_DEV0_EPF0_LOCAL_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_EPF0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT         0x0
+#define BIF_CFG_DEV0_EPF0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK           0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_RTM1_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_EPF0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT           0x0
+#define BIF_CFG_DEV0_EPF0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK             0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_RTM2_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_EPF0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT           0x0
+#define BIF_CFG_DEV0_EPF0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK             0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT                     0x0
+#define BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT                     0x4
+#define BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK                       0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK                       0xF0L
+//BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT                     0x0
+#define BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT                     0x4
+#define BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK                       0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK                       0xF0L
+//BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT                     0x0
+#define BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT                     0x4
+#define BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK                       0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK                       0xF0L
+//BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT                     0x0
+#define BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT                     0x4
+#define BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK                       0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK                       0xF0L
+//BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT                     0x0
+#define BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT                     0x4
+#define BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK                       0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK                       0xF0L
+//BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT                     0x0
+#define BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT                     0x4
+#define BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK                       0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK                       0xF0L
+//BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT                     0x0
+#define BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT                     0x4
+#define BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK                       0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK                       0xF0L
+//BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT                     0x0
+#define BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT                     0x4
+#define BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK                       0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK                       0xF0L
+//BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT                     0x0
+#define BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT                     0x4
+#define BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK                       0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK                       0xF0L
+//BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT                     0x0
+#define BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT                     0x4
+#define BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK                       0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK                       0xF0L
+//BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV0_EPF0_PCIE_PHY_32GT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_ID__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_VER__SHIFT                                          0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_PHY_32GT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                         0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_ID_MASK                                             0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_VER_MASK                                            0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_PHY_32GT_ENH_CAP_LIST__NEXT_PTR_MASK                                           0xFFF00000L
+//BIF_CFG_DEV0_EPF0_LINK_CAP_32GT
+#define BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__EQ_BYPASS_TO_HIGHEST_RATE_SUPPORTED__SHIFT                           0x0
+#define BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__NO_EQ_NEEDED_SUPPORTED__SHIFT                                        0x1
+#define BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE0_SUPPORTED__SHIFT                             0x8
+#define BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE1_SUPPORTED__SHIFT                             0x9
+#define BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE2_SUPPORTED__SHIFT                             0xa
+#define BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES__SHIFT                              0xb
+#define BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__EQ_BYPASS_TO_HIGHEST_RATE_SUPPORTED_MASK                             0x00000001L
+#define BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__NO_EQ_NEEDED_SUPPORTED_MASK                                          0x00000002L
+#define BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE0_SUPPORTED_MASK                               0x00000100L
+#define BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE1_SUPPORTED_MASK                               0x00000200L
+#define BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE2_SUPPORTED_MASK                               0x00000400L
+#define BIF_CFG_DEV0_EPF0_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES_MASK                                0x0000F800L
+//BIF_CFG_DEV0_EPF0_LINK_CNTL_32GT
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL_32GT__EQ_BYPASS_TO_HIGHEST_RATE_DIS__SHIFT                                0x0
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL_32GT__NO_EQ_NEEDED_DIS__SHIFT                                             0x1
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SEL__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL_32GT__EQ_BYPASS_TO_HIGHEST_RATE_DIS_MASK                                  0x00000001L
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL_32GT__NO_EQ_NEEDED_DIS_MASK                                               0x00000002L
+#define BIF_CFG_DEV0_EPF0_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SEL_MASK                                     0x00000700L
+//BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT__SHIFT                                 0x0
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT__SHIFT                           0x1
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT__SHIFT                           0x2
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT__SHIFT                           0x3
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT__SHIFT                             0x4
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED__SHIFT                                       0x5
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOR_CNTL__SHIFT                       0x6
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST__SHIFT                                0x9
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__NO_EQ_NEEDED_RECEIVED__SHIFT                                      0xa
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT_MASK                                   0x00000001L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT_MASK                             0x00000002L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT_MASK                             0x00000004L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT_MASK                             0x00000008L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT_MASK                               0x00000010L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED_MASK                                         0x00000020L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOR_CNTL_MASK                         0x000000C0L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON_MASK                                     0x00000100L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST_MASK                                  0x00000200L
+#define BIF_CFG_DEV0_EPF0_LINK_STATUS_32GT__NO_EQ_NEEDED_RECEIVED_MASK                                        0x00000400L
+//BIF_CFG_DEV0_EPF0_RECEIVED_MODIFIED_TS_DATA1
+#define BIF_CFG_DEV0_EPF0_RECEIVED_MODIFIED_TS_DATA1__USAGE_MODE__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF0_RECEIVED_MODIFIED_TS_DATA1__INFOR1__SHIFT                                           0x3
+#define BIF_CFG_DEV0_EPF0_RECEIVED_MODIFIED_TS_DATA1__VENDORID__SHIFT                                         0x10
+#define BIF_CFG_DEV0_EPF0_RECEIVED_MODIFIED_TS_DATA1__USAGE_MODE_MASK                                         0x00000007L
+#define BIF_CFG_DEV0_EPF0_RECEIVED_MODIFIED_TS_DATA1__INFOR1_MASK                                             0x0000FFF8L
+#define BIF_CFG_DEV0_EPF0_RECEIVED_MODIFIED_TS_DATA1__VENDORID_MASK                                           0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_RECEIVED_MODIFIED_TS_DATA2
+#define BIF_CFG_DEV0_EPF0_RECEIVED_MODIFIED_TS_DATA2__INFOR2__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_RECEIVED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS__SHIFT            0x18
+#define BIF_CFG_DEV0_EPF0_RECEIVED_MODIFIED_TS_DATA2__INFOR2_MASK                                             0x00FFFFFFL
+#define BIF_CFG_DEV0_EPF0_RECEIVED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS_MASK              0x03000000L
+//BIF_CFG_DEV0_EPF0_TRANSMITTED_MODIFIED_TS_DATA1
+#define BIF_CFG_DEV0_EPF0_TRANSMITTED_MODIFIED_TS_DATA1__USAGE_MODE__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF0_TRANSMITTED_MODIFIED_TS_DATA1__INFOR1__SHIFT                                        0x3
+#define BIF_CFG_DEV0_EPF0_TRANSMITTED_MODIFIED_TS_DATA1__VENDORID__SHIFT                                      0x10
+#define BIF_CFG_DEV0_EPF0_TRANSMITTED_MODIFIED_TS_DATA1__USAGE_MODE_MASK                                      0x00000007L
+#define BIF_CFG_DEV0_EPF0_TRANSMITTED_MODIFIED_TS_DATA1__INFOR1_MASK                                          0x0000FFF8L
+#define BIF_CFG_DEV0_EPF0_TRANSMITTED_MODIFIED_TS_DATA1__VENDORID_MASK                                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_TRANSMITTED_MODIFIED_TS_DATA2
+#define BIF_CFG_DEV0_EPF0_TRANSMITTED_MODIFIED_TS_DATA2__INFOR2__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF0_TRANSMITTED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS__SHIFT         0x18
+#define BIF_CFG_DEV0_EPF0_TRANSMITTED_MODIFIED_TS_DATA2__INFOR2_MASK                                          0x00FFFFFFL
+#define BIF_CFG_DEV0_EPF0_TRANSMITTED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS_MASK           0x03000000L
+//BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_32GT
+#define BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_DSP_32GT_TX_PRESET__SHIFT                     0x0
+#define BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_USP_32GT_TX_PRESET__SHIFT                     0x4
+#define BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_DSP_32GT_TX_PRESET_MASK                       0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_USP_32GT_TX_PRESET_MASK                       0xF0L
+//BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_32GT
+#define BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_DSP_32GT_TX_PRESET__SHIFT                     0x0
+#define BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_USP_32GT_TX_PRESET__SHIFT                     0x4
+#define BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_DSP_32GT_TX_PRESET_MASK                       0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_USP_32GT_TX_PRESET_MASK                       0xF0L
+//BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_32GT
+#define BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_DSP_32GT_TX_PRESET__SHIFT                     0x0
+#define BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_USP_32GT_TX_PRESET__SHIFT                     0x4
+#define BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_DSP_32GT_TX_PRESET_MASK                       0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_USP_32GT_TX_PRESET_MASK                       0xF0L
+//BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_32GT
+#define BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_DSP_32GT_TX_PRESET__SHIFT                     0x0
+#define BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_USP_32GT_TX_PRESET__SHIFT                     0x4
+#define BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_DSP_32GT_TX_PRESET_MASK                       0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_USP_32GT_TX_PRESET_MASK                       0xF0L
+//BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_32GT
+#define BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_DSP_32GT_TX_PRESET__SHIFT                     0x0
+#define BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_USP_32GT_TX_PRESET__SHIFT                     0x4
+#define BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_DSP_32GT_TX_PRESET_MASK                       0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_USP_32GT_TX_PRESET_MASK                       0xF0L
+//BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_32GT
+#define BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_DSP_32GT_TX_PRESET__SHIFT                     0x0
+#define BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_USP_32GT_TX_PRESET__SHIFT                     0x4
+#define BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_DSP_32GT_TX_PRESET_MASK                       0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_USP_32GT_TX_PRESET_MASK                       0xF0L
+//BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_32GT
+#define BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_DSP_32GT_TX_PRESET__SHIFT                     0x0
+#define BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_USP_32GT_TX_PRESET__SHIFT                     0x4
+#define BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_DSP_32GT_TX_PRESET_MASK                       0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_USP_32GT_TX_PRESET_MASK                       0xF0L
+//BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_32GT
+#define BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_DSP_32GT_TX_PRESET__SHIFT                     0x0
+#define BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_USP_32GT_TX_PRESET__SHIFT                     0x4
+#define BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_DSP_32GT_TX_PRESET_MASK                       0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_USP_32GT_TX_PRESET_MASK                       0xF0L
+//BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_32GT
+#define BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_DSP_32GT_TX_PRESET__SHIFT                     0x0
+#define BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_USP_32GT_TX_PRESET__SHIFT                     0x4
+#define BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_DSP_32GT_TX_PRESET_MASK                       0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_USP_32GT_TX_PRESET_MASK                       0xF0L
+//BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_32GT
+#define BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_DSP_32GT_TX_PRESET__SHIFT                     0x0
+#define BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_USP_32GT_TX_PRESET__SHIFT                     0x4
+#define BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_DSP_32GT_TX_PRESET_MASK                       0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_USP_32GT_TX_PRESET_MASK                       0xF0L
+//BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_32GT
+#define BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_DSP_32GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_USP_32GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_DSP_32GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_USP_32GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_32GT
+#define BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_DSP_32GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_USP_32GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_DSP_32GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_USP_32GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_32GT
+#define BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_DSP_32GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_USP_32GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_DSP_32GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_USP_32GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_32GT
+#define BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_DSP_32GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_USP_32GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_DSP_32GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_USP_32GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_32GT
+#define BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_DSP_32GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_USP_32GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_DSP_32GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_USP_32GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_32GT
+#define BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_DSP_32GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_USP_32GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_DSP_32GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV0_EPF0_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_USP_32GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV0_EPF0_PCIE_AP_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_AP_ENH_CAP_LIST__CAP_ID__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_AP_ENH_CAP_LIST__CAP_VER__SHIFT                                                0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_AP_ENH_CAP_LIST__NEXT_PTR__SHIFT                                               0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_AP_ENH_CAP_LIST__CAP_ID_MASK                                                   0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_AP_ENH_CAP_LIST__CAP_VER_MASK                                                  0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_AP_ENH_CAP_LIST__NEXT_PTR_MASK                                                 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_AP_CAP
+#define BIF_CFG_DEV0_EPF0_AP_CAP__COUNT__SHIFT                                                                0x0
+#define BIF_CFG_DEV0_EPF0_AP_CAP__SEL_EN_SUPPORTED__SHIFT                                                     0x8
+#define BIF_CFG_DEV0_EPF0_AP_CAP__COUNT_MASK                                                                  0x000000FFL
+#define BIF_CFG_DEV0_EPF0_AP_CAP__SEL_EN_SUPPORTED_MASK                                                       0x00000100L
+//BIF_CFG_DEV0_EPF0_AP_CNTL
+#define BIF_CFG_DEV0_EPF0_AP_CNTL__INX_SEL__SHIFT                                                             0x0
+#define BIF_CFG_DEV0_EPF0_AP_CNTL__NEGO_GLOBAL_EN__SHIFT                                                      0x8
+#define BIF_CFG_DEV0_EPF0_AP_CNTL__INX_SEL_MASK                                                               0x000000FFL
+#define BIF_CFG_DEV0_EPF0_AP_CNTL__NEGO_GLOBAL_EN_MASK                                                        0x00000100L
+//BIF_CFG_DEV0_EPF0_AP_DATA1
+#define BIF_CFG_DEV0_EPF0_AP_DATA1__USAGE_INFOR__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_EPF0_AP_DATA1__DETAILS__SHIFT                                                            0x5
+#define BIF_CFG_DEV0_EPF0_AP_DATA1__VENDORID__SHIFT                                                           0x10
+#define BIF_CFG_DEV0_EPF0_AP_DATA1__USAGE_INFOR_MASK                                                          0x00000007L
+#define BIF_CFG_DEV0_EPF0_AP_DATA1__DETAILS_MASK                                                              0x0000FFE0L
+#define BIF_CFG_DEV0_EPF0_AP_DATA1__VENDORID_MASK                                                             0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_AP_DATA2
+#define BIF_CFG_DEV0_EPF0_AP_DATA2__MODIFIED_TS_INFOR2__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF0_AP_DATA2__MODIFIED_TS_INFOR2_MASK                                                   0x00FFFFFFL
+//BIF_CFG_DEV0_EPF0_AP_SEL_EN_MASK
+#define BIF_CFG_DEV0_EPF0_AP_SEL_EN_MASK__PCIE__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF0_AP_SEL_EN_MASK__OTHERS__SHIFT                                                       0x1
+#define BIF_CFG_DEV0_EPF0_AP_SEL_EN_MASK__PCIE_MASK                                                           0x00000001L
+#define BIF_CFG_DEV0_EPF0_AP_SEL_EN_MASK__OTHERS_MASK                                                         0xFFFFFFFEL
+//BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT                                         0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT                                        0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK                                            0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK                                           0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK                                          0xFFF00000L
+//BIF_CFG_DEV0_EPF0_MARGINING_PORT_CAP
+#define BIF_CFG_DEV0_EPF0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT                                  0x0
+#define BIF_CFG_DEV0_EPF0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK                                    0x0001L
+//BIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS
+#define BIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT                              0x1
+#define BIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS__MARGINING_READY_MASK                                         0x0001L
+#define BIF_CFG_DEV0_EPF0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK                                0x0002L
+//BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT                           0x0
+#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT                               0x3
+#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT                               0x6
+#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT                            0x8
+#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK                             0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK                                 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK                                 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK                              0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
+#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT                      0x3
+#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT                      0x6
+#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
+#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK                        0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK                        0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT                           0x0
+#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT                               0x3
+#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT                               0x6
+#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT                            0x8
+#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK                             0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK                                 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK                                 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK                              0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
+#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT                      0x3
+#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT                      0x6
+#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
+#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK                        0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK                        0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT                           0x0
+#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT                               0x3
+#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT                               0x6
+#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT                            0x8
+#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK                             0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK                                 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK                                 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK                              0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
+#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT                      0x3
+#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT                      0x6
+#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
+#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK                        0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK                        0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT                           0x0
+#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT                               0x3
+#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT                               0x6
+#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT                            0x8
+#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK                             0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK                                 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK                                 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK                              0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
+#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT                      0x3
+#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT                      0x6
+#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
+#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK                        0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK                        0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT                           0x0
+#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT                               0x3
+#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT                               0x6
+#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT                            0x8
+#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK                             0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK                                 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK                                 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK                              0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
+#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT                      0x3
+#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT                      0x6
+#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
+#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK                        0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK                        0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT                           0x0
+#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT                               0x3
+#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT                               0x6
+#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT                            0x8
+#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK                             0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK                                 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK                                 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK                              0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
+#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT                      0x3
+#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT                      0x6
+#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
+#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK                        0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK                        0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT                           0x0
+#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT                               0x3
+#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT                               0x6
+#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT                            0x8
+#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK                             0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK                                 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK                                 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK                              0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
+#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT                      0x3
+#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT                      0x6
+#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
+#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK                        0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK                        0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT                           0x0
+#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT                               0x3
+#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT                               0x6
+#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT                            0x8
+#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK                             0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK                                 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK                                 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK                              0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
+#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT                      0x3
+#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT                      0x6
+#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
+#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK                        0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK                        0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT                           0x0
+#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT                               0x3
+#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT                               0x6
+#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT                            0x8
+#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK                             0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK                                 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK                                 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK                              0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
+#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT                      0x3
+#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT                      0x6
+#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
+#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK                        0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK                        0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT                           0x0
+#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT                               0x3
+#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT                               0x6
+#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT                            0x8
+#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK                             0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK                                 0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK                                 0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK                              0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
+#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT                      0x3
+#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT                      0x6
+#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
+#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK                        0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK                        0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV0_EPF0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV0_EPF0_PCIE_NULL1_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_NULL1_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_NULL1_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_NULL1_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_NULL1_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_NULL1_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_NULL1_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT                                                0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                               0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK                                                   0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK                                                  0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK                                                 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1
+#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT                             0x4
+#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT                                               0x8
+#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT                             0xa
+#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK                                            0x00000007L
+#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK                               0x00000070L
+#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK                                                 0x00000300L
+#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK                               0x00000C00L
+//BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2
+#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT                                   0x18
+#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK                                              0x000000FFL
+#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK                                     0xFF000000L
+//BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT                                             0x1
+#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK                                           0x0001L
+#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK                                               0x000EL
+//BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_STATUS
+#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK                                       0x0001L
+//BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                    0xf
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                        0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                                 0x18
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK                                            0x000000FFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                      0x00008000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                          0x007F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                   0xFF000000L
+//BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                      0x1
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                  0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                      0x11
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT                                                0x18
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT                                            0x1f
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                          0x00000001L
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                        0x000000FEL
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                    0x00010000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                        0x000E0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK                                                  0x07000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK                                              0x80000000L
+//BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                             0x1
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                                0x0001L
+#define BIF_CFG_DEV0_EPF0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                               0x0002L
+//BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                    0xf
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                        0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                                 0x18
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK                                            0x000000FFL
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                      0x00008000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                          0x003F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                   0xFF000000L
+//BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                      0x1
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                  0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                      0x11
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT                                                0x18
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT                                            0x1f
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                          0x00000001L
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                        0x000000FEL
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                    0x00010000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                        0x000E0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK                                                  0x07000000L
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK                                              0x80000000L
+//BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                             0x1
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                                0x0001L
+#define BIF_CFG_DEV0_EPF0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                               0x0002L
+//BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
+#define BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
+#define BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
+//BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP
+#define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT                                   0x1f
+#define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK                                     0x007FFFFFL
+#define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK                                     0x80000000L
+//BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS
+#define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT                               0x0
+#define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT                         0x1f
+#define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK                                 0x007FFFFFL
+#define BIF_CFG_DEV0_EPF0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK                           0x80000000L
+//BIF_CFG_DEV0_EPF0_IDE_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_IDE_ENH_CAP_LIST__CAP_ID__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_IDE_ENH_CAP_LIST__CAP_VER__SHIFT                                                    0x10
+#define BIF_CFG_DEV0_EPF0_IDE_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                   0x14
+#define BIF_CFG_DEV0_EPF0_IDE_ENH_CAP_LIST__CAP_ID_MASK                                                       0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_IDE_ENH_CAP_LIST__CAP_VER_MASK                                                      0x000F0000L
+#define BIF_CFG_DEV0_EPF0_IDE_ENH_CAP_LIST__NEXT_PTR_MASK                                                     0xFFF00000L
+//BIF_CFG_DEV0_EPF0_IDE_CAP
+#define BIF_CFG_DEV0_EPF0_IDE_CAP__IDE_CAP_LINK_IDE_STREAM_SUPPORTED__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF0_IDE_CAP__IDE_CAP_SELECTIVE_IDE_STREAM_SUPPORTED__SHIFT                              0x1
+#define BIF_CFG_DEV0_EPF0_IDE_CAP__IDE_CAP_FLOW_THROUGH_IDE_STREAM_SUPPORTED__SHIFT                           0x2
+#define BIF_CFG_DEV0_EPF0_IDE_CAP__IDE_CAP_PARTIAL_HDR_ENCRYPTION_SUPPORTED__SHIFT                            0x3
+#define BIF_CFG_DEV0_EPF0_IDE_CAP__IDE_CAP_AGGREGATION_SUPPORTED__SHIFT                                       0x4
+#define BIF_CFG_DEV0_EPF0_IDE_CAP__IDE_CAP_PCRC_SUPPORTED__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF0_IDE_CAP__IDE_CAP_IDE_KM_PROTOCOL_SUPPORTED__SHIFT                                   0x6
+#define BIF_CFG_DEV0_EPF0_IDE_CAP__IDE_CAP_SELECTIVE_IDE_FOR_CFG_REQ_SUPPORTED__SHIFT                         0x7
+#define BIF_CFG_DEV0_EPF0_IDE_CAP__IDE_CAP_SUPPORTED_ALGORITHMS__SHIFT                                        0x8
+#define BIF_CFG_DEV0_EPF0_IDE_CAP__IDE_CAP_NUM_OF_TCS_SUPPORTED_FOR_LINK_IDE__SHIFT                           0xd
+#define BIF_CFG_DEV0_EPF0_IDE_CAP__IDE_CAP_NUM_OF_SELECTIVE_IDE_STREAMS_SUPPORTED__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF0_IDE_CAP__IDE_CAP_TEE_LIMITED_SUPPORTED__SHIFT                                       0x18
+#define BIF_CFG_DEV0_EPF0_IDE_CAP__IDE_CAP_XT_SUPPORTED__SHIFT                                                0x19
+#define BIF_CFG_DEV0_EPF0_IDE_CAP__IDE_CAP_LINK_IDE_STREAM_SUPPORTED_MASK                                     0x00000001L
+#define BIF_CFG_DEV0_EPF0_IDE_CAP__IDE_CAP_SELECTIVE_IDE_STREAM_SUPPORTED_MASK                                0x00000002L
+#define BIF_CFG_DEV0_EPF0_IDE_CAP__IDE_CAP_FLOW_THROUGH_IDE_STREAM_SUPPORTED_MASK                             0x00000004L
+#define BIF_CFG_DEV0_EPF0_IDE_CAP__IDE_CAP_PARTIAL_HDR_ENCRYPTION_SUPPORTED_MASK                              0x00000008L
+#define BIF_CFG_DEV0_EPF0_IDE_CAP__IDE_CAP_AGGREGATION_SUPPORTED_MASK                                         0x00000010L
+#define BIF_CFG_DEV0_EPF0_IDE_CAP__IDE_CAP_PCRC_SUPPORTED_MASK                                                0x00000020L
+#define BIF_CFG_DEV0_EPF0_IDE_CAP__IDE_CAP_IDE_KM_PROTOCOL_SUPPORTED_MASK                                     0x00000040L
+#define BIF_CFG_DEV0_EPF0_IDE_CAP__IDE_CAP_SELECTIVE_IDE_FOR_CFG_REQ_SUPPORTED_MASK                           0x00000080L
+#define BIF_CFG_DEV0_EPF0_IDE_CAP__IDE_CAP_SUPPORTED_ALGORITHMS_MASK                                          0x00001F00L
+#define BIF_CFG_DEV0_EPF0_IDE_CAP__IDE_CAP_NUM_OF_TCS_SUPPORTED_FOR_LINK_IDE_MASK                             0x0000E000L
+#define BIF_CFG_DEV0_EPF0_IDE_CAP__IDE_CAP_NUM_OF_SELECTIVE_IDE_STREAMS_SUPPORTED_MASK                        0x00FF0000L
+#define BIF_CFG_DEV0_EPF0_IDE_CAP__IDE_CAP_TEE_LIMITED_SUPPORTED_MASK                                         0x01000000L
+#define BIF_CFG_DEV0_EPF0_IDE_CAP__IDE_CAP_XT_SUPPORTED_MASK                                                  0x02000000L
+//BIF_CFG_DEV0_EPF0_IDE_CNTL
+#define BIF_CFG_DEV0_EPF0_IDE_CNTL__IDE_CNTL_FLOW_THROUGH_IDE_STREAM_ENABLED__SHIFT                           0x2
+#define BIF_CFG_DEV0_EPF0_IDE_CNTL__IDE_CNTL_FLOW_THROUGH_IDE_STREAM_ENABLED_MASK                             0x00000004L
+//BIF_CFG_DEV0_EPF0_LINK_IDE_STREAM_0_CNTL
+#define BIF_CFG_DEV0_EPF0_LINK_IDE_STREAM_0_CNTL__LINK_IDE_STREAM_ENABLE__SHIFT                               0x0
+#define BIF_CFG_DEV0_EPF0_LINK_IDE_STREAM_0_CNTL__XT_ENABLE__SHIFT                                            0x1
+#define BIF_CFG_DEV0_EPF0_LINK_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT                              0x2
+#define BIF_CFG_DEV0_EPF0_LINK_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_PR__SHIFT                               0x4
+#define BIF_CFG_DEV0_EPF0_LINK_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT                              0x6
+#define BIF_CFG_DEV0_EPF0_LINK_IDE_STREAM_0_CNTL__PCRC_ENABLE__SHIFT                                          0x8
+#define BIF_CFG_DEV0_EPF0_LINK_IDE_STREAM_0_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT                             0xa
+#define BIF_CFG_DEV0_EPF0_LINK_IDE_STREAM_0_CNTL__SELECTED_ALGORITHM__SHIFT                                   0xe
+#define BIF_CFG_DEV0_EPF0_LINK_IDE_STREAM_0_CNTL__TC__SHIFT                                                   0x13
+#define BIF_CFG_DEV0_EPF0_LINK_IDE_STREAM_0_CNTL__STREAM_ID__SHIFT                                            0x18
+#define BIF_CFG_DEV0_EPF0_LINK_IDE_STREAM_0_CNTL__LINK_IDE_STREAM_ENABLE_MASK                                 0x00000001L
+#define BIF_CFG_DEV0_EPF0_LINK_IDE_STREAM_0_CNTL__XT_ENABLE_MASK                                              0x00000002L
+#define BIF_CFG_DEV0_EPF0_LINK_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_NPR_MASK                                0x0000000CL
+#define BIF_CFG_DEV0_EPF0_LINK_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_PR_MASK                                 0x00000030L
+#define BIF_CFG_DEV0_EPF0_LINK_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_CPL_MASK                                0x000000C0L
+#define BIF_CFG_DEV0_EPF0_LINK_IDE_STREAM_0_CNTL__PCRC_ENABLE_MASK                                            0x00000100L
+#define BIF_CFG_DEV0_EPF0_LINK_IDE_STREAM_0_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK                               0x00003C00L
+#define BIF_CFG_DEV0_EPF0_LINK_IDE_STREAM_0_CNTL__SELECTED_ALGORITHM_MASK                                     0x0007C000L
+#define BIF_CFG_DEV0_EPF0_LINK_IDE_STREAM_0_CNTL__TC_MASK                                                     0x00380000L
+#define BIF_CFG_DEV0_EPF0_LINK_IDE_STREAM_0_CNTL__STREAM_ID_MASK                                              0xFF000000L
+//BIF_CFG_DEV0_EPF0_LINK_IDE_STREAM_0_STATUS
+#define BIF_CFG_DEV0_EPF0_LINK_IDE_STREAM_0_STATUS__LINK_IDE_STREAM_STATE__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_LINK_IDE_STREAM_0_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT                              0x1f
+#define BIF_CFG_DEV0_EPF0_LINK_IDE_STREAM_0_STATUS__LINK_IDE_STREAM_STATE_MASK                                0x0000000FL
+#define BIF_CFG_DEV0_EPF0_LINK_IDE_STREAM_0_STATUS__RECEIVED_IDE_FAIL_MSG_MASK                                0x80000000L
+//BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CAP
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT                    0x0
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK                      0x0000000FL
+//BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CNTL
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT                     0x0
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CNTL__XT_ENABLE__SHIFT                                       0x1
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT                         0x2
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_PR__SHIFT                          0x4
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT                         0x6
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CNTL__PCRC_ENABLE__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT                    0x9
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT                        0xa
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CNTL__SELECTED_ALGORITHM__SHIFT                              0xe
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CNTL__TC__SHIFT                                              0x13
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CNTL__DEFAULT_STREAM__SHIFT                                  0x16
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CNTL__TEE_LIMITED_STREAM__SHIFT                              0x17
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CNTL__STREAM_ID__SHIFT                                       0x18
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK                       0x00000001L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CNTL__XT_ENABLE_MASK                                         0x00000002L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_NPR_MASK                           0x0000000CL
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_PR_MASK                            0x00000030L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_CPL_MASK                           0x000000C0L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CNTL__PCRC_ENABLE_MASK                                       0x00000100L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK                      0x00000200L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK                          0x00003C00L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CNTL__SELECTED_ALGORITHM_MASK                                0x0007C000L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CNTL__TC_MASK                                                0x00380000L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CNTL__DEFAULT_STREAM_MASK                                    0x00400000L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CNTL__TEE_LIMITED_STREAM_MASK                                0x00800000L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_CNTL__STREAM_ID_MASK                                         0xFF000000L
+//BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_STATUS
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT                    0x0
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT                         0x1f
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK                      0x0000000FL
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_0_STATUS__RECEIVED_IDE_FAIL_MSG_MASK                           0x80000000L
+//BIF_CFG_DEV0_EPF0_IDE_0_RID_ASSOCIATION_REG1
+#define BIF_CFG_DEV0_EPF0_IDE_0_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT                                        0x8
+#define BIF_CFG_DEV0_EPF0_IDE_0_RID_ASSOCIATION_REG1__RID_LIMIT_MASK                                          0x00FFFF00L
+//BIF_CFG_DEV0_EPF0_IDE_0_RID_ASSOCIATION_REG2
+#define BIF_CFG_DEV0_EPF0_IDE_0_RID_ASSOCIATION_REG2__VALID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF0_IDE_0_RID_ASSOCIATION_REG2__RID_BASE__SHIFT                                         0x8
+#define BIF_CFG_DEV0_EPF0_IDE_0_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT                                     0x18
+#define BIF_CFG_DEV0_EPF0_IDE_0_RID_ASSOCIATION_REG2__VALID_MASK                                              0x00000001L
+#define BIF_CFG_DEV0_EPF0_IDE_0_RID_ASSOCIATION_REG2__RID_BASE_MASK                                           0x00FFFF00L
+#define BIF_CFG_DEV0_EPF0_IDE_0_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK                                       0xFF000000L
+//BIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_0_REG1
+#define BIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT                                0x8
+#define BIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT                               0x14
+#define BIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_0_REG1__VALID_MASK                                           0x00000001L
+#define BIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK                                  0x000FFF00L
+#define BIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK                                 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_0_REG2
+#define BIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT                               0x0
+#define BIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK                                 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_0_REG3
+#define BIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT                                0x0
+#define BIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK                                  0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_1_REG1
+#define BIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT                                0x8
+#define BIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT                               0x14
+#define BIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_1_REG1__VALID_MASK                                           0x00000001L
+#define BIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK                                  0x000FFF00L
+#define BIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK                                 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_1_REG2
+#define BIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT                               0x0
+#define BIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK                                 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_1_REG3
+#define BIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT                                0x0
+#define BIF_CFG_DEV0_EPF0_IDE_0_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK                                  0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CAP
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT                    0x0
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK                      0x0000000FL
+//BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CNTL
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT                     0x0
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CNTL__XT_ENABLE__SHIFT                                       0x1
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT                         0x2
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CNTL__TX_AGGREGATION_MODE_PR__SHIFT                          0x4
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT                         0x6
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CNTL__PCRC_ENABLE__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT                    0x9
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT                        0xa
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CNTL__SELECTED_ALGORITHM__SHIFT                              0xe
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CNTL__TC__SHIFT                                              0x13
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CNTL__DEFAULT_STREAM__SHIFT                                  0x16
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CNTL__TEE_LIMITED_STREAM__SHIFT                              0x17
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CNTL__STREAM_ID__SHIFT                                       0x18
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK                       0x00000001L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CNTL__XT_ENABLE_MASK                                         0x00000002L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CNTL__TX_AGGREGATION_MODE_NPR_MASK                           0x0000000CL
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CNTL__TX_AGGREGATION_MODE_PR_MASK                            0x00000030L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CNTL__TX_AGGREGATION_MODE_CPL_MASK                           0x000000C0L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CNTL__PCRC_ENABLE_MASK                                       0x00000100L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK                      0x00000200L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK                          0x00003C00L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CNTL__SELECTED_ALGORITHM_MASK                                0x0007C000L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CNTL__TC_MASK                                                0x00380000L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CNTL__DEFAULT_STREAM_MASK                                    0x00400000L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CNTL__TEE_LIMITED_STREAM_MASK                                0x00800000L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_CNTL__STREAM_ID_MASK                                         0xFF000000L
+//BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_STATUS
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT                    0x0
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT                         0x1f
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK                      0x0000000FL
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_1_STATUS__RECEIVED_IDE_FAIL_MSG_MASK                           0x80000000L
+//BIF_CFG_DEV0_EPF0_IDE_1_RID_ASSOCIATION_REG1
+#define BIF_CFG_DEV0_EPF0_IDE_1_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT                                        0x8
+#define BIF_CFG_DEV0_EPF0_IDE_1_RID_ASSOCIATION_REG1__RID_LIMIT_MASK                                          0x00FFFF00L
+//BIF_CFG_DEV0_EPF0_IDE_1_RID_ASSOCIATION_REG2
+#define BIF_CFG_DEV0_EPF0_IDE_1_RID_ASSOCIATION_REG2__VALID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF0_IDE_1_RID_ASSOCIATION_REG2__RID_BASE__SHIFT                                         0x8
+#define BIF_CFG_DEV0_EPF0_IDE_1_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT                                     0x18
+#define BIF_CFG_DEV0_EPF0_IDE_1_RID_ASSOCIATION_REG2__VALID_MASK                                              0x00000001L
+#define BIF_CFG_DEV0_EPF0_IDE_1_RID_ASSOCIATION_REG2__RID_BASE_MASK                                           0x00FFFF00L
+#define BIF_CFG_DEV0_EPF0_IDE_1_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK                                       0xFF000000L
+//BIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_0_REG1
+#define BIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT                                0x8
+#define BIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT                               0x14
+#define BIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_0_REG1__VALID_MASK                                           0x00000001L
+#define BIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK                                  0x000FFF00L
+#define BIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK                                 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_0_REG2
+#define BIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT                               0x0
+#define BIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK                                 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_0_REG3
+#define BIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT                                0x0
+#define BIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK                                  0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_1_REG1
+#define BIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT                                0x8
+#define BIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT                               0x14
+#define BIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_1_REG1__VALID_MASK                                           0x00000001L
+#define BIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK                                  0x000FFF00L
+#define BIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK                                 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_1_REG2
+#define BIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT                               0x0
+#define BIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK                                 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_1_REG3
+#define BIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT                                0x0
+#define BIF_CFG_DEV0_EPF0_IDE_1_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK                                  0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CAP
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT                    0x0
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK                      0x0000000FL
+//BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CNTL
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT                     0x0
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CNTL__XT_ENABLE__SHIFT                                       0x1
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT                         0x2
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CNTL__TX_AGGREGATION_MODE_PR__SHIFT                          0x4
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT                         0x6
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CNTL__PCRC_ENABLE__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT                    0x9
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT                        0xa
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CNTL__SELECTED_ALGORITHM__SHIFT                              0xe
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CNTL__TC__SHIFT                                              0x13
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CNTL__DEFAULT_STREAM__SHIFT                                  0x16
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CNTL__TEE_LIMITED_STREAM__SHIFT                              0x17
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CNTL__STREAM_ID__SHIFT                                       0x18
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK                       0x00000001L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CNTL__XT_ENABLE_MASK                                         0x00000002L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CNTL__TX_AGGREGATION_MODE_NPR_MASK                           0x0000000CL
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CNTL__TX_AGGREGATION_MODE_PR_MASK                            0x00000030L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CNTL__TX_AGGREGATION_MODE_CPL_MASK                           0x000000C0L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CNTL__PCRC_ENABLE_MASK                                       0x00000100L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK                      0x00000200L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK                          0x00003C00L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CNTL__SELECTED_ALGORITHM_MASK                                0x0007C000L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CNTL__TC_MASK                                                0x00380000L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CNTL__DEFAULT_STREAM_MASK                                    0x00400000L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CNTL__TEE_LIMITED_STREAM_MASK                                0x00800000L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_CNTL__STREAM_ID_MASK                                         0xFF000000L
+//BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_STATUS
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT                    0x0
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT                         0x1f
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK                      0x0000000FL
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_2_STATUS__RECEIVED_IDE_FAIL_MSG_MASK                           0x80000000L
+//BIF_CFG_DEV0_EPF0_IDE_2_RID_ASSOCIATION_REG1
+#define BIF_CFG_DEV0_EPF0_IDE_2_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT                                        0x8
+#define BIF_CFG_DEV0_EPF0_IDE_2_RID_ASSOCIATION_REG1__RID_LIMIT_MASK                                          0x00FFFF00L
+//BIF_CFG_DEV0_EPF0_IDE_2_RID_ASSOCIATION_REG2
+#define BIF_CFG_DEV0_EPF0_IDE_2_RID_ASSOCIATION_REG2__VALID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF0_IDE_2_RID_ASSOCIATION_REG2__RID_BASE__SHIFT                                         0x8
+#define BIF_CFG_DEV0_EPF0_IDE_2_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT                                     0x18
+#define BIF_CFG_DEV0_EPF0_IDE_2_RID_ASSOCIATION_REG2__VALID_MASK                                              0x00000001L
+#define BIF_CFG_DEV0_EPF0_IDE_2_RID_ASSOCIATION_REG2__RID_BASE_MASK                                           0x00FFFF00L
+#define BIF_CFG_DEV0_EPF0_IDE_2_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK                                       0xFF000000L
+//BIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_0_REG1
+#define BIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT                                0x8
+#define BIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT                               0x14
+#define BIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_0_REG1__VALID_MASK                                           0x00000001L
+#define BIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK                                  0x000FFF00L
+#define BIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK                                 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_0_REG2
+#define BIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT                               0x0
+#define BIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK                                 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_0_REG3
+#define BIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT                                0x0
+#define BIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK                                  0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_1_REG1
+#define BIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT                                0x8
+#define BIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT                               0x14
+#define BIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_1_REG1__VALID_MASK                                           0x00000001L
+#define BIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK                                  0x000FFF00L
+#define BIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK                                 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_1_REG2
+#define BIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT                               0x0
+#define BIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK                                 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_1_REG3
+#define BIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT                                0x0
+#define BIF_CFG_DEV0_EPF0_IDE_2_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK                                  0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CAP
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT                    0x0
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK                      0x0000000FL
+//BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CNTL
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT                     0x0
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CNTL__XT_ENABLE__SHIFT                                       0x1
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT                         0x2
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CNTL__TX_AGGREGATION_MODE_PR__SHIFT                          0x4
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT                         0x6
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CNTL__PCRC_ENABLE__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT                    0x9
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT                        0xa
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CNTL__SELECTED_ALGORITHM__SHIFT                              0xe
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CNTL__TC__SHIFT                                              0x13
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CNTL__DEFAULT_STREAM__SHIFT                                  0x16
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CNTL__TEE_LIMITED_STREAM__SHIFT                              0x17
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CNTL__STREAM_ID__SHIFT                                       0x18
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK                       0x00000001L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CNTL__XT_ENABLE_MASK                                         0x00000002L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CNTL__TX_AGGREGATION_MODE_NPR_MASK                           0x0000000CL
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CNTL__TX_AGGREGATION_MODE_PR_MASK                            0x00000030L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CNTL__TX_AGGREGATION_MODE_CPL_MASK                           0x000000C0L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CNTL__PCRC_ENABLE_MASK                                       0x00000100L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK                      0x00000200L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK                          0x00003C00L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CNTL__SELECTED_ALGORITHM_MASK                                0x0007C000L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CNTL__TC_MASK                                                0x00380000L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CNTL__DEFAULT_STREAM_MASK                                    0x00400000L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CNTL__TEE_LIMITED_STREAM_MASK                                0x00800000L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_CNTL__STREAM_ID_MASK                                         0xFF000000L
+//BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_STATUS
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT                    0x0
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT                         0x1f
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK                      0x0000000FL
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_3_STATUS__RECEIVED_IDE_FAIL_MSG_MASK                           0x80000000L
+//BIF_CFG_DEV0_EPF0_IDE_3_RID_ASSOCIATION_REG1
+#define BIF_CFG_DEV0_EPF0_IDE_3_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT                                        0x8
+#define BIF_CFG_DEV0_EPF0_IDE_3_RID_ASSOCIATION_REG1__RID_LIMIT_MASK                                          0x00FFFF00L
+//BIF_CFG_DEV0_EPF0_IDE_3_RID_ASSOCIATION_REG2
+#define BIF_CFG_DEV0_EPF0_IDE_3_RID_ASSOCIATION_REG2__VALID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF0_IDE_3_RID_ASSOCIATION_REG2__RID_BASE__SHIFT                                         0x8
+#define BIF_CFG_DEV0_EPF0_IDE_3_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT                                     0x18
+#define BIF_CFG_DEV0_EPF0_IDE_3_RID_ASSOCIATION_REG2__VALID_MASK                                              0x00000001L
+#define BIF_CFG_DEV0_EPF0_IDE_3_RID_ASSOCIATION_REG2__RID_BASE_MASK                                           0x00FFFF00L
+#define BIF_CFG_DEV0_EPF0_IDE_3_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK                                       0xFF000000L
+//BIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_0_REG1
+#define BIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT                                0x8
+#define BIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT                               0x14
+#define BIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_0_REG1__VALID_MASK                                           0x00000001L
+#define BIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK                                  0x000FFF00L
+#define BIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK                                 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_0_REG2
+#define BIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT                               0x0
+#define BIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK                                 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_0_REG3
+#define BIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT                                0x0
+#define BIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK                                  0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_1_REG1
+#define BIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT                                0x8
+#define BIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT                               0x14
+#define BIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_1_REG1__VALID_MASK                                           0x00000001L
+#define BIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK                                  0x000FFF00L
+#define BIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK                                 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_1_REG2
+#define BIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT                               0x0
+#define BIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK                                 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_1_REG3
+#define BIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT                                0x0
+#define BIF_CFG_DEV0_EPF0_IDE_3_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK                                  0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CAP
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT                    0x0
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK                      0x0000000FL
+//BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CNTL
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT                     0x0
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CNTL__XT_ENABLE__SHIFT                                       0x1
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT                         0x2
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CNTL__TX_AGGREGATION_MODE_PR__SHIFT                          0x4
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT                         0x6
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CNTL__PCRC_ENABLE__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT                    0x9
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT                        0xa
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CNTL__SELECTED_ALGORITHM__SHIFT                              0xe
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CNTL__TC__SHIFT                                              0x13
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CNTL__DEFAULT_STREAM__SHIFT                                  0x16
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CNTL__TEE_LIMITED_STREAM__SHIFT                              0x17
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CNTL__STREAM_ID__SHIFT                                       0x18
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK                       0x00000001L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CNTL__XT_ENABLE_MASK                                         0x00000002L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CNTL__TX_AGGREGATION_MODE_NPR_MASK                           0x0000000CL
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CNTL__TX_AGGREGATION_MODE_PR_MASK                            0x00000030L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CNTL__TX_AGGREGATION_MODE_CPL_MASK                           0x000000C0L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CNTL__PCRC_ENABLE_MASK                                       0x00000100L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK                      0x00000200L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK                          0x00003C00L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CNTL__SELECTED_ALGORITHM_MASK                                0x0007C000L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CNTL__TC_MASK                                                0x00380000L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CNTL__DEFAULT_STREAM_MASK                                    0x00400000L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CNTL__TEE_LIMITED_STREAM_MASK                                0x00800000L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_CNTL__STREAM_ID_MASK                                         0xFF000000L
+//BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_STATUS
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT                    0x0
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT                         0x1f
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK                      0x0000000FL
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_4_STATUS__RECEIVED_IDE_FAIL_MSG_MASK                           0x80000000L
+//BIF_CFG_DEV0_EPF0_IDE_4_RID_ASSOCIATION_REG1
+#define BIF_CFG_DEV0_EPF0_IDE_4_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT                                        0x8
+#define BIF_CFG_DEV0_EPF0_IDE_4_RID_ASSOCIATION_REG1__RID_LIMIT_MASK                                          0x00FFFF00L
+//BIF_CFG_DEV0_EPF0_IDE_4_RID_ASSOCIATION_REG2
+#define BIF_CFG_DEV0_EPF0_IDE_4_RID_ASSOCIATION_REG2__VALID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF0_IDE_4_RID_ASSOCIATION_REG2__RID_BASE__SHIFT                                         0x8
+#define BIF_CFG_DEV0_EPF0_IDE_4_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT                                     0x18
+#define BIF_CFG_DEV0_EPF0_IDE_4_RID_ASSOCIATION_REG2__VALID_MASK                                              0x00000001L
+#define BIF_CFG_DEV0_EPF0_IDE_4_RID_ASSOCIATION_REG2__RID_BASE_MASK                                           0x00FFFF00L
+#define BIF_CFG_DEV0_EPF0_IDE_4_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK                                       0xFF000000L
+//BIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_0_REG1
+#define BIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT                                0x8
+#define BIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT                               0x14
+#define BIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_0_REG1__VALID_MASK                                           0x00000001L
+#define BIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK                                  0x000FFF00L
+#define BIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK                                 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_0_REG2
+#define BIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT                               0x0
+#define BIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK                                 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_0_REG3
+#define BIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT                                0x0
+#define BIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK                                  0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_1_REG1
+#define BIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT                                0x8
+#define BIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT                               0x14
+#define BIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_1_REG1__VALID_MASK                                           0x00000001L
+#define BIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK                                  0x000FFF00L
+#define BIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK                                 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_1_REG2
+#define BIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT                               0x0
+#define BIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK                                 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_1_REG3
+#define BIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT                                0x0
+#define BIF_CFG_DEV0_EPF0_IDE_4_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK                                  0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CAP
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT                    0x0
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK                      0x0000000FL
+//BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CNTL
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT                     0x0
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CNTL__XT_ENABLE__SHIFT                                       0x1
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT                         0x2
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CNTL__TX_AGGREGATION_MODE_PR__SHIFT                          0x4
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT                         0x6
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CNTL__PCRC_ENABLE__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT                    0x9
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT                        0xa
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CNTL__SELECTED_ALGORITHM__SHIFT                              0xe
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CNTL__TC__SHIFT                                              0x13
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CNTL__DEFAULT_STREAM__SHIFT                                  0x16
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CNTL__TEE_LIMITED_STREAM__SHIFT                              0x17
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CNTL__STREAM_ID__SHIFT                                       0x18
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK                       0x00000001L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CNTL__XT_ENABLE_MASK                                         0x00000002L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CNTL__TX_AGGREGATION_MODE_NPR_MASK                           0x0000000CL
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CNTL__TX_AGGREGATION_MODE_PR_MASK                            0x00000030L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CNTL__TX_AGGREGATION_MODE_CPL_MASK                           0x000000C0L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CNTL__PCRC_ENABLE_MASK                                       0x00000100L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK                      0x00000200L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK                          0x00003C00L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CNTL__SELECTED_ALGORITHM_MASK                                0x0007C000L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CNTL__TC_MASK                                                0x00380000L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CNTL__DEFAULT_STREAM_MASK                                    0x00400000L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CNTL__TEE_LIMITED_STREAM_MASK                                0x00800000L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_CNTL__STREAM_ID_MASK                                         0xFF000000L
+//BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_STATUS
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT                    0x0
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT                         0x1f
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK                      0x0000000FL
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_5_STATUS__RECEIVED_IDE_FAIL_MSG_MASK                           0x80000000L
+//BIF_CFG_DEV0_EPF0_IDE_5_RID_ASSOCIATION_REG1
+#define BIF_CFG_DEV0_EPF0_IDE_5_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT                                        0x8
+#define BIF_CFG_DEV0_EPF0_IDE_5_RID_ASSOCIATION_REG1__RID_LIMIT_MASK                                          0x00FFFF00L
+//BIF_CFG_DEV0_EPF0_IDE_5_RID_ASSOCIATION_REG2
+#define BIF_CFG_DEV0_EPF0_IDE_5_RID_ASSOCIATION_REG2__VALID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF0_IDE_5_RID_ASSOCIATION_REG2__RID_BASE__SHIFT                                         0x8
+#define BIF_CFG_DEV0_EPF0_IDE_5_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT                                     0x18
+#define BIF_CFG_DEV0_EPF0_IDE_5_RID_ASSOCIATION_REG2__VALID_MASK                                              0x00000001L
+#define BIF_CFG_DEV0_EPF0_IDE_5_RID_ASSOCIATION_REG2__RID_BASE_MASK                                           0x00FFFF00L
+#define BIF_CFG_DEV0_EPF0_IDE_5_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK                                       0xFF000000L
+//BIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_0_REG1
+#define BIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT                                0x8
+#define BIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT                               0x14
+#define BIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_0_REG1__VALID_MASK                                           0x00000001L
+#define BIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK                                  0x000FFF00L
+#define BIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK                                 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_0_REG2
+#define BIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT                               0x0
+#define BIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK                                 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_0_REG3
+#define BIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT                                0x0
+#define BIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK                                  0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_1_REG1
+#define BIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT                                0x8
+#define BIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT                               0x14
+#define BIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_1_REG1__VALID_MASK                                           0x00000001L
+#define BIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK                                  0x000FFF00L
+#define BIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK                                 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_1_REG2
+#define BIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT                               0x0
+#define BIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK                                 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_1_REG3
+#define BIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT                                0x0
+#define BIF_CFG_DEV0_EPF0_IDE_5_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK                                  0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CAP
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT                    0x0
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK                      0x0000000FL
+//BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CNTL
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT                     0x0
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CNTL__XT_ENABLE__SHIFT                                       0x1
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT                         0x2
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CNTL__TX_AGGREGATION_MODE_PR__SHIFT                          0x4
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT                         0x6
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CNTL__PCRC_ENABLE__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT                    0x9
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT                        0xa
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CNTL__SELECTED_ALGORITHM__SHIFT                              0xe
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CNTL__TC__SHIFT                                              0x13
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CNTL__DEFAULT_STREAM__SHIFT                                  0x16
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CNTL__TEE_LIMITED_STREAM__SHIFT                              0x17
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CNTL__STREAM_ID__SHIFT                                       0x18
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK                       0x00000001L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CNTL__XT_ENABLE_MASK                                         0x00000002L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CNTL__TX_AGGREGATION_MODE_NPR_MASK                           0x0000000CL
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CNTL__TX_AGGREGATION_MODE_PR_MASK                            0x00000030L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CNTL__TX_AGGREGATION_MODE_CPL_MASK                           0x000000C0L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CNTL__PCRC_ENABLE_MASK                                       0x00000100L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK                      0x00000200L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK                          0x00003C00L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CNTL__SELECTED_ALGORITHM_MASK                                0x0007C000L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CNTL__TC_MASK                                                0x00380000L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CNTL__DEFAULT_STREAM_MASK                                    0x00400000L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CNTL__TEE_LIMITED_STREAM_MASK                                0x00800000L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_CNTL__STREAM_ID_MASK                                         0xFF000000L
+//BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_STATUS
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT                    0x0
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT                         0x1f
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK                      0x0000000FL
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_6_STATUS__RECEIVED_IDE_FAIL_MSG_MASK                           0x80000000L
+//BIF_CFG_DEV0_EPF0_IDE_6_RID_ASSOCIATION_REG1
+#define BIF_CFG_DEV0_EPF0_IDE_6_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT                                        0x8
+#define BIF_CFG_DEV0_EPF0_IDE_6_RID_ASSOCIATION_REG1__RID_LIMIT_MASK                                          0x00FFFF00L
+//BIF_CFG_DEV0_EPF0_IDE_6_RID_ASSOCIATION_REG2
+#define BIF_CFG_DEV0_EPF0_IDE_6_RID_ASSOCIATION_REG2__VALID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF0_IDE_6_RID_ASSOCIATION_REG2__RID_BASE__SHIFT                                         0x8
+#define BIF_CFG_DEV0_EPF0_IDE_6_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT                                     0x18
+#define BIF_CFG_DEV0_EPF0_IDE_6_RID_ASSOCIATION_REG2__VALID_MASK                                              0x00000001L
+#define BIF_CFG_DEV0_EPF0_IDE_6_RID_ASSOCIATION_REG2__RID_BASE_MASK                                           0x00FFFF00L
+#define BIF_CFG_DEV0_EPF0_IDE_6_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK                                       0xFF000000L
+//BIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_0_REG1
+#define BIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT                                0x8
+#define BIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT                               0x14
+#define BIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_0_REG1__VALID_MASK                                           0x00000001L
+#define BIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK                                  0x000FFF00L
+#define BIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK                                 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_0_REG2
+#define BIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT                               0x0
+#define BIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK                                 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_0_REG3
+#define BIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT                                0x0
+#define BIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK                                  0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_1_REG1
+#define BIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT                                0x8
+#define BIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT                               0x14
+#define BIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_1_REG1__VALID_MASK                                           0x00000001L
+#define BIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK                                  0x000FFF00L
+#define BIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK                                 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_1_REG2
+#define BIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT                               0x0
+#define BIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK                                 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_1_REG3
+#define BIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT                                0x0
+#define BIF_CFG_DEV0_EPF0_IDE_6_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK                                  0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CAP
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT                    0x0
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK                      0x0000000FL
+//BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CNTL
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT                     0x0
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CNTL__XT_ENABLE__SHIFT                                       0x1
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT                         0x2
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CNTL__TX_AGGREGATION_MODE_PR__SHIFT                          0x4
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT                         0x6
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CNTL__PCRC_ENABLE__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT                    0x9
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT                        0xa
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CNTL__SELECTED_ALGORITHM__SHIFT                              0xe
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CNTL__TC__SHIFT                                              0x13
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CNTL__DEFAULT_STREAM__SHIFT                                  0x16
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CNTL__TEE_LIMITED_STREAM__SHIFT                              0x17
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CNTL__STREAM_ID__SHIFT                                       0x18
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK                       0x00000001L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CNTL__XT_ENABLE_MASK                                         0x00000002L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CNTL__TX_AGGREGATION_MODE_NPR_MASK                           0x0000000CL
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CNTL__TX_AGGREGATION_MODE_PR_MASK                            0x00000030L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CNTL__TX_AGGREGATION_MODE_CPL_MASK                           0x000000C0L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CNTL__PCRC_ENABLE_MASK                                       0x00000100L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK                      0x00000200L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK                          0x00003C00L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CNTL__SELECTED_ALGORITHM_MASK                                0x0007C000L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CNTL__TC_MASK                                                0x00380000L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CNTL__DEFAULT_STREAM_MASK                                    0x00400000L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CNTL__TEE_LIMITED_STREAM_MASK                                0x00800000L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_CNTL__STREAM_ID_MASK                                         0xFF000000L
+//BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_STATUS
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT                    0x0
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT                         0x1f
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK                      0x0000000FL
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_7_STATUS__RECEIVED_IDE_FAIL_MSG_MASK                           0x80000000L
+//BIF_CFG_DEV0_EPF0_IDE_7_RID_ASSOCIATION_REG1
+#define BIF_CFG_DEV0_EPF0_IDE_7_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT                                        0x8
+#define BIF_CFG_DEV0_EPF0_IDE_7_RID_ASSOCIATION_REG1__RID_LIMIT_MASK                                          0x00FFFF00L
+//BIF_CFG_DEV0_EPF0_IDE_7_RID_ASSOCIATION_REG2
+#define BIF_CFG_DEV0_EPF0_IDE_7_RID_ASSOCIATION_REG2__VALID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF0_IDE_7_RID_ASSOCIATION_REG2__RID_BASE__SHIFT                                         0x8
+#define BIF_CFG_DEV0_EPF0_IDE_7_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT                                     0x18
+#define BIF_CFG_DEV0_EPF0_IDE_7_RID_ASSOCIATION_REG2__VALID_MASK                                              0x00000001L
+#define BIF_CFG_DEV0_EPF0_IDE_7_RID_ASSOCIATION_REG2__RID_BASE_MASK                                           0x00FFFF00L
+#define BIF_CFG_DEV0_EPF0_IDE_7_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK                                       0xFF000000L
+//BIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_0_REG1
+#define BIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT                                0x8
+#define BIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT                               0x14
+#define BIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_0_REG1__VALID_MASK                                           0x00000001L
+#define BIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK                                  0x000FFF00L
+#define BIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK                                 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_0_REG2
+#define BIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT                               0x0
+#define BIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK                                 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_0_REG3
+#define BIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT                                0x0
+#define BIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK                                  0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_1_REG1
+#define BIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT                                0x8
+#define BIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT                               0x14
+#define BIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_1_REG1__VALID_MASK                                           0x00000001L
+#define BIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK                                  0x000FFF00L
+#define BIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK                                 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_1_REG2
+#define BIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT                               0x0
+#define BIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK                                 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_1_REG3
+#define BIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT                                0x0
+#define BIF_CFG_DEV0_EPF0_IDE_7_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK                                  0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CAP
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT                    0x0
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK                      0x0000000FL
+//BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CNTL
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT                     0x0
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CNTL__XT_ENABLE__SHIFT                                       0x1
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT                         0x2
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CNTL__TX_AGGREGATION_MODE_PR__SHIFT                          0x4
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT                         0x6
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CNTL__PCRC_ENABLE__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT                    0x9
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT                        0xa
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CNTL__SELECTED_ALGORITHM__SHIFT                              0xe
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CNTL__TC__SHIFT                                              0x13
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CNTL__DEFAULT_STREAM__SHIFT                                  0x16
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CNTL__TEE_LIMITED_STREAM__SHIFT                              0x17
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CNTL__STREAM_ID__SHIFT                                       0x18
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK                       0x00000001L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CNTL__XT_ENABLE_MASK                                         0x00000002L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CNTL__TX_AGGREGATION_MODE_NPR_MASK                           0x0000000CL
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CNTL__TX_AGGREGATION_MODE_PR_MASK                            0x00000030L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CNTL__TX_AGGREGATION_MODE_CPL_MASK                           0x000000C0L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CNTL__PCRC_ENABLE_MASK                                       0x00000100L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK                      0x00000200L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK                          0x00003C00L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CNTL__SELECTED_ALGORITHM_MASK                                0x0007C000L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CNTL__TC_MASK                                                0x00380000L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CNTL__DEFAULT_STREAM_MASK                                    0x00400000L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CNTL__TEE_LIMITED_STREAM_MASK                                0x00800000L
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_CNTL__STREAM_ID_MASK                                         0xFF000000L
+//BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_STATUS
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT                    0x0
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT                         0x1f
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK                      0x0000000FL
+#define BIF_CFG_DEV0_EPF0_SELECTIVE_IDE_STREAM_8_STATUS__RECEIVED_IDE_FAIL_MSG_MASK                           0x80000000L
+//BIF_CFG_DEV0_EPF0_IDE_8_RID_ASSOCIATION_REG1
+#define BIF_CFG_DEV0_EPF0_IDE_8_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT                                        0x8
+#define BIF_CFG_DEV0_EPF0_IDE_8_RID_ASSOCIATION_REG1__RID_LIMIT_MASK                                          0x00FFFF00L
+//BIF_CFG_DEV0_EPF0_IDE_8_RID_ASSOCIATION_REG2
+#define BIF_CFG_DEV0_EPF0_IDE_8_RID_ASSOCIATION_REG2__VALID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF0_IDE_8_RID_ASSOCIATION_REG2__RID_BASE__SHIFT                                         0x8
+#define BIF_CFG_DEV0_EPF0_IDE_8_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT                                     0x18
+#define BIF_CFG_DEV0_EPF0_IDE_8_RID_ASSOCIATION_REG2__VALID_MASK                                              0x00000001L
+#define BIF_CFG_DEV0_EPF0_IDE_8_RID_ASSOCIATION_REG2__RID_BASE_MASK                                           0x00FFFF00L
+#define BIF_CFG_DEV0_EPF0_IDE_8_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK                                       0xFF000000L
+//BIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_0_REG1
+#define BIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT                                0x8
+#define BIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT                               0x14
+#define BIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_0_REG1__VALID_MASK                                           0x00000001L
+#define BIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK                                  0x000FFF00L
+#define BIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK                                 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_0_REG2
+#define BIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT                               0x0
+#define BIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK                                 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_0_REG3
+#define BIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT                                0x0
+#define BIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK                                  0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_1_REG1
+#define BIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT                                0x8
+#define BIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT                               0x14
+#define BIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_1_REG1__VALID_MASK                                           0x00000001L
+#define BIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK                                  0x000FFF00L
+#define BIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK                                 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_1_REG2
+#define BIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT                               0x0
+#define BIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK                                 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_1_REG3
+#define BIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT                                0x0
+#define BIF_CFG_DEV0_EPF0_IDE_8_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK                                  0xFFFFFFFFL
+
+
+// addressBlock: nbif0_nbif0_bif_cfg_dev0_rc_bifcfgdecp
+//BIF_CFG_DEV0_RC0_VENDOR_ID
+#define BIF_CFG_DEV0_RC0_VENDOR_ID__VENDOR_ID__SHIFT                                                          0x0
+#define BIF_CFG_DEV0_RC0_VENDOR_ID__VENDOR_ID_MASK                                                            0xFFFFL
+//BIF_CFG_DEV0_RC0_DEVICE_ID
+#define BIF_CFG_DEV0_RC0_DEVICE_ID__DEVICE_ID__SHIFT                                                          0x0
+#define BIF_CFG_DEV0_RC0_DEVICE_ID__DEVICE_ID_MASK                                                            0xFFFFL
+//BIF_CFG_DEV0_RC0_COMMAND
+#define BIF_CFG_DEV0_RC0_COMMAND__IOEN_DN__SHIFT                                                              0x0
+#define BIF_CFG_DEV0_RC0_COMMAND__MEMEN_DN__SHIFT                                                             0x1
+#define BIF_CFG_DEV0_RC0_COMMAND__BUS_MASTER_EN__SHIFT                                                        0x2
+#define BIF_CFG_DEV0_RC0_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                     0x3
+#define BIF_CFG_DEV0_RC0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                              0x4
+#define BIF_CFG_DEV0_RC0_COMMAND__PAL_SNOOP_EN__SHIFT                                                         0x5
+#define BIF_CFG_DEV0_RC0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                                0x6
+#define BIF_CFG_DEV0_RC0_COMMAND__AD_STEPPING__SHIFT                                                          0x7
+#define BIF_CFG_DEV0_RC0_COMMAND__SERR_EN__SHIFT                                                              0x8
+#define BIF_CFG_DEV0_RC0_COMMAND__FAST_B2B_EN__SHIFT                                                          0x9
+#define BIF_CFG_DEV0_RC0_COMMAND__INT_DIS__SHIFT                                                              0xa
+#define BIF_CFG_DEV0_RC0_COMMAND__IOEN_DN_MASK                                                                0x0001L
+#define BIF_CFG_DEV0_RC0_COMMAND__MEMEN_DN_MASK                                                               0x0002L
+#define BIF_CFG_DEV0_RC0_COMMAND__BUS_MASTER_EN_MASK                                                          0x0004L
+#define BIF_CFG_DEV0_RC0_COMMAND__SPECIAL_CYCLE_EN_MASK                                                       0x0008L
+#define BIF_CFG_DEV0_RC0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                                0x0010L
+#define BIF_CFG_DEV0_RC0_COMMAND__PAL_SNOOP_EN_MASK                                                           0x0020L
+#define BIF_CFG_DEV0_RC0_COMMAND__PARITY_ERROR_RESPONSE_MASK                                                  0x0040L
+#define BIF_CFG_DEV0_RC0_COMMAND__AD_STEPPING_MASK                                                            0x0080L
+#define BIF_CFG_DEV0_RC0_COMMAND__SERR_EN_MASK                                                                0x0100L
+#define BIF_CFG_DEV0_RC0_COMMAND__FAST_B2B_EN_MASK                                                            0x0200L
+#define BIF_CFG_DEV0_RC0_COMMAND__INT_DIS_MASK                                                                0x0400L
+//BIF_CFG_DEV0_RC0_STATUS
+#define BIF_CFG_DEV0_RC0_STATUS__IMMEDIATE_READINESS__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_RC0_STATUS__INT_STATUS__SHIFT                                                            0x3
+#define BIF_CFG_DEV0_RC0_STATUS__CAP_LIST__SHIFT                                                              0x4
+#define BIF_CFG_DEV0_RC0_STATUS__PCI_66_CAP__SHIFT                                                            0x5
+#define BIF_CFG_DEV0_RC0_STATUS__FAST_BACK_CAPABLE__SHIFT                                                     0x7
+#define BIF_CFG_DEV0_RC0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                              0x8
+#define BIF_CFG_DEV0_RC0_STATUS__DEVSEL_TIMING__SHIFT                                                         0x9
+#define BIF_CFG_DEV0_RC0_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                   0xb
+#define BIF_CFG_DEV0_RC0_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                                 0xc
+#define BIF_CFG_DEV0_RC0_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                                 0xd
+#define BIF_CFG_DEV0_RC0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                                 0xe
+#define BIF_CFG_DEV0_RC0_STATUS__PARITY_ERROR_DETECTED__SHIFT                                                 0xf
+#define BIF_CFG_DEV0_RC0_STATUS__IMMEDIATE_READINESS_MASK                                                     0x0001L
+#define BIF_CFG_DEV0_RC0_STATUS__INT_STATUS_MASK                                                              0x0008L
+#define BIF_CFG_DEV0_RC0_STATUS__CAP_LIST_MASK                                                                0x0010L
+#define BIF_CFG_DEV0_RC0_STATUS__PCI_66_CAP_MASK                                                              0x0020L
+#define BIF_CFG_DEV0_RC0_STATUS__FAST_BACK_CAPABLE_MASK                                                       0x0080L
+#define BIF_CFG_DEV0_RC0_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                                0x0100L
+#define BIF_CFG_DEV0_RC0_STATUS__DEVSEL_TIMING_MASK                                                           0x0600L
+#define BIF_CFG_DEV0_RC0_STATUS__SIGNAL_TARGET_ABORT_MASK                                                     0x0800L
+#define BIF_CFG_DEV0_RC0_STATUS__RECEIVED_TARGET_ABORT_MASK                                                   0x1000L
+#define BIF_CFG_DEV0_RC0_STATUS__RECEIVED_MASTER_ABORT_MASK                                                   0x2000L
+#define BIF_CFG_DEV0_RC0_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                   0x4000L
+#define BIF_CFG_DEV0_RC0_STATUS__PARITY_ERROR_DETECTED_MASK                                                   0x8000L
+//BIF_CFG_DEV0_RC0_REVISION_ID
+#define BIF_CFG_DEV0_RC0_REVISION_ID__MINOR_REV_ID__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_RC0_REVISION_ID__MAJOR_REV_ID__SHIFT                                                     0x4
+#define BIF_CFG_DEV0_RC0_REVISION_ID__MINOR_REV_ID_MASK                                                       0x0FL
+#define BIF_CFG_DEV0_RC0_REVISION_ID__MAJOR_REV_ID_MASK                                                       0xF0L
+//BIF_CFG_DEV0_RC0_PROG_INTERFACE
+#define BIF_CFG_DEV0_RC0_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                                0x0
+#define BIF_CFG_DEV0_RC0_PROG_INTERFACE__PROG_INTERFACE_MASK                                                  0xFFL
+//BIF_CFG_DEV0_RC0_SUB_CLASS
+#define BIF_CFG_DEV0_RC0_SUB_CLASS__SUB_CLASS__SHIFT                                                          0x0
+#define BIF_CFG_DEV0_RC0_SUB_CLASS__SUB_CLASS_MASK                                                            0xFFL
+//BIF_CFG_DEV0_RC0_BASE_CLASS
+#define BIF_CFG_DEV0_RC0_BASE_CLASS__BASE_CLASS__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_RC0_BASE_CLASS__BASE_CLASS_MASK                                                          0xFFL
+//BIF_CFG_DEV0_RC0_CACHE_LINE
+#define BIF_CFG_DEV0_RC0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_RC0_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                     0xFFL
+//BIF_CFG_DEV0_RC0_LATENCY
+#define BIF_CFG_DEV0_RC0_LATENCY__LATENCY_TIMER__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_RC0_LATENCY__LATENCY_TIMER_MASK                                                          0xFFL
+//BIF_CFG_DEV0_RC0_HEADER
+#define BIF_CFG_DEV0_RC0_HEADER__HEADER_TYPE__SHIFT                                                           0x0
+#define BIF_CFG_DEV0_RC0_HEADER__DEVICE_TYPE__SHIFT                                                           0x7
+#define BIF_CFG_DEV0_RC0_HEADER__HEADER_TYPE_MASK                                                             0x7FL
+#define BIF_CFG_DEV0_RC0_HEADER__DEVICE_TYPE_MASK                                                             0x80L
+//BIF_CFG_DEV0_RC0_BIST
+#define BIF_CFG_DEV0_RC0_BIST__BIST_COMP__SHIFT                                                               0x0
+#define BIF_CFG_DEV0_RC0_BIST__BIST_STRT__SHIFT                                                               0x6
+#define BIF_CFG_DEV0_RC0_BIST__BIST_CAP__SHIFT                                                                0x7
+#define BIF_CFG_DEV0_RC0_BIST__BIST_COMP_MASK                                                                 0x0FL
+#define BIF_CFG_DEV0_RC0_BIST__BIST_STRT_MASK                                                                 0x40L
+#define BIF_CFG_DEV0_RC0_BIST__BIST_CAP_MASK                                                                  0x80L
+//BIF_CFG_DEV0_RC0_BASE_ADDR_1
+#define BIF_CFG_DEV0_RC0_BASE_ADDR_1__BASE_ADDR__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_RC0_BASE_ADDR_1__BASE_ADDR_MASK                                                          0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_BASE_ADDR_2
+#define BIF_CFG_DEV0_RC0_BASE_ADDR_2__BASE_ADDR__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_RC0_BASE_ADDR_2__BASE_ADDR_MASK                                                          0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY
+#define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT                                           0x0
+#define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT                                         0x8
+#define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT                                           0x10
+#define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT                               0x18
+#define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK                                             0x000000FFL
+#define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK                                           0x0000FF00L
+#define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK                                             0x00FF0000L
+#define BIF_CFG_DEV0_RC0_SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK                                 0xFF000000L
+//BIF_CFG_DEV0_RC0_IO_BASE_LIMIT
+#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_BASE__SHIFT                                                        0x4
+#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT                                                  0x8
+#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_LIMIT__SHIFT                                                       0xc
+#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_BASE_TYPE_MASK                                                     0x000FL
+#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_BASE_MASK                                                          0x00F0L
+#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK                                                    0x0F00L
+#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT__IO_LIMIT_MASK                                                         0xF000L
+//BIF_CFG_DEV0_RC0_SECONDARY_STATUS
+#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__PCI_66_CAP__SHIFT                                                  0x5
+#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT                                           0x7
+#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                    0x8
+#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__DEVSEL_TIMING__SHIFT                                               0x9
+#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                         0xb
+#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                       0xc
+#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                       0xd
+#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT                                       0xe
+#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT                                       0xf
+#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__PCI_66_CAP_MASK                                                    0x0020L
+#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK                                             0x0080L
+#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                      0x0100L
+#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__DEVSEL_TIMING_MASK                                                 0x0600L
+#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK                                           0x0800L
+#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK                                         0x1000L
+#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK                                         0x2000L
+#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK                                         0x4000L
+#define BIF_CFG_DEV0_RC0_SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK                                         0x8000L
+//BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT
+#define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT                                                0x4
+#define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT                                                0x10
+#define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT                                               0x14
+#define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK                                                   0x0000000FL
+#define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_BASE_31_20_MASK                                                  0x0000FFF0L
+#define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK                                                  0x000F0000L
+#define BIF_CFG_DEV0_RC0_MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK                                                 0xFFF00000L
+//BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT
+#define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT                                           0x0
+#define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT                                          0x4
+#define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT                                          0x10
+#define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT                                         0x14
+#define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK                                             0x0000000FL
+#define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK                                            0x0000FFF0L
+#define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK                                            0x000F0000L
+#define BIF_CFG_DEV0_RC0_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK                                           0xFFF00000L
+//BIF_CFG_DEV0_RC0_PREF_BASE_UPPER
+#define BIF_CFG_DEV0_RC0_PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT                                              0x0
+#define BIF_CFG_DEV0_RC0_PREF_BASE_UPPER__PREF_BASE_UPPER_MASK                                                0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_PREF_LIMIT_UPPER
+#define BIF_CFG_DEV0_RC0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT                                            0x0
+#define BIF_CFG_DEV0_RC0_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK                                              0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI
+#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT                                               0x0
+#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT                                              0x10
+#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK                                                 0x0000FFFFL
+#define BIF_CFG_DEV0_RC0_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK                                                0xFFFF0000L
+//BIF_CFG_DEV0_RC0_CAP_PTR
+#define BIF_CFG_DEV0_RC0_CAP_PTR__CAP_PTR__SHIFT                                                              0x0
+#define BIF_CFG_DEV0_RC0_CAP_PTR__CAP_PTR_MASK                                                                0xFFL
+//BIF_CFG_DEV0_RC0_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_RC0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_RC0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT                                          0x1
+#define BIF_CFG_DEV0_RC0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT                                         0x4
+#define BIF_CFG_DEV0_RC0_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                      0xb
+#define BIF_CFG_DEV0_RC0_ROM_BASE_ADDR__ROM_ENABLE_MASK                                                       0x00000001L
+#define BIF_CFG_DEV0_RC0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK                                            0x0000000EL
+#define BIF_CFG_DEV0_RC0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK                                           0x000000F0L
+#define BIF_CFG_DEV0_RC0_ROM_BASE_ADDR__BASE_ADDR_MASK                                                        0xFFFFF800L
+//BIF_CFG_DEV0_RC0_INTERRUPT_LINE
+#define BIF_CFG_DEV0_RC0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                                0x0
+#define BIF_CFG_DEV0_RC0_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                                  0xFFL
+//BIF_CFG_DEV0_RC0_INTERRUPT_PIN
+#define BIF_CFG_DEV0_RC0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_RC0_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                    0xFFL
+//BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL
+#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT                                           0x0
+#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__SERR_EN__SHIFT                                                      0x1
+#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__ISA_EN__SHIFT                                                       0x2
+#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__VGA_EN__SHIFT                                                       0x3
+#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT                                                      0x4
+#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT                                            0x5
+#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT                                          0x6
+#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT                                                  0x7
+#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT                                        0x8
+#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT                                      0x9
+#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT                                         0xa
+#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT                                    0xb
+#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK                                             0x0001L
+#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__SERR_EN_MASK                                                        0x0002L
+#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__ISA_EN_MASK                                                         0x0004L
+#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__VGA_EN_MASK                                                         0x0008L
+#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__VGA_DEC_MASK                                                        0x0010L
+#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK                                              0x0020L
+#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK                                            0x0040L
+#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK                                                    0x0080L
+#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK                                          0x0100L
+#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK                                        0x0200L
+#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK                                           0x0400L
+#define BIF_CFG_DEV0_RC0_IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK                                      0x0800L
+//BIF_CFG_DEV0_RC0_EXT_BRIDGE_CNTL
+#define BIF_CFG_DEV0_RC0_EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT                                                0x0
+#define BIF_CFG_DEV0_RC0_EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK                                                  0x01L
+//BIF_CFG_DEV0_RC0_PMI_CAP_LIST
+#define BIF_CFG_DEV0_RC0_PMI_CAP_LIST__CAP_ID__SHIFT                                                          0x0
+#define BIF_CFG_DEV0_RC0_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                        0x8
+#define BIF_CFG_DEV0_RC0_PMI_CAP_LIST__CAP_ID_MASK                                                            0x00FFL
+#define BIF_CFG_DEV0_RC0_PMI_CAP_LIST__NEXT_PTR_MASK                                                          0xFF00L
+//BIF_CFG_DEV0_RC0_PMI_CAP
+#define BIF_CFG_DEV0_RC0_PMI_CAP__VERSION__SHIFT                                                              0x0
+#define BIF_CFG_DEV0_RC0_PMI_CAP__PME_CLOCK__SHIFT                                                            0x3
+#define BIF_CFG_DEV0_RC0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                                  0x4
+#define BIF_CFG_DEV0_RC0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                    0x5
+#define BIF_CFG_DEV0_RC0_PMI_CAP__AUX_CURRENT__SHIFT                                                          0x6
+#define BIF_CFG_DEV0_RC0_PMI_CAP__D1_SUPPORT__SHIFT                                                           0x9
+#define BIF_CFG_DEV0_RC0_PMI_CAP__D2_SUPPORT__SHIFT                                                           0xa
+#define BIF_CFG_DEV0_RC0_PMI_CAP__PME_SUPPORT__SHIFT                                                          0xb
+#define BIF_CFG_DEV0_RC0_PMI_CAP__VERSION_MASK                                                                0x0007L
+#define BIF_CFG_DEV0_RC0_PMI_CAP__PME_CLOCK_MASK                                                              0x0008L
+#define BIF_CFG_DEV0_RC0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                    0x0010L
+#define BIF_CFG_DEV0_RC0_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                      0x0020L
+#define BIF_CFG_DEV0_RC0_PMI_CAP__AUX_CURRENT_MASK                                                            0x01C0L
+#define BIF_CFG_DEV0_RC0_PMI_CAP__D1_SUPPORT_MASK                                                             0x0200L
+#define BIF_CFG_DEV0_RC0_PMI_CAP__D2_SUPPORT_MASK                                                             0x0400L
+#define BIF_CFG_DEV0_RC0_PMI_CAP__PME_SUPPORT_MASK                                                            0xF800L
+//BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                                0x3
+#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PME_EN__SHIFT                                                       0x8
+#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                                  0x9
+#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                   0xd
+#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                   0xf
+#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                                0x16
+#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                   0x17
+#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                     0x18
+#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__POWER_STATE_MASK                                                    0x00000003L
+#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                                  0x00000008L
+#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PME_EN_MASK                                                         0x00000100L
+#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                    0x00001E00L
+#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                     0x00006000L
+#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PME_STATUS_MASK                                                     0x00008000L
+#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                                  0x00400000L
+#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                     0x00800000L
+#define BIF_CFG_DEV0_RC0_PMI_STATUS_CNTL__PMI_DATA_MASK                                                       0xFF000000L
+//BIF_CFG_DEV0_RC0_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_RC0_PCIE_CAP_LIST__CAP_ID__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_RC0_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                       0x8
+#define BIF_CFG_DEV0_RC0_PCIE_CAP_LIST__CAP_ID_MASK                                                           0x00FFL
+#define BIF_CFG_DEV0_RC0_PCIE_CAP_LIST__NEXT_PTR_MASK                                                         0xFF00L
+//BIF_CFG_DEV0_RC0_PCIE_CAP
+#define BIF_CFG_DEV0_RC0_PCIE_CAP__VERSION__SHIFT                                                             0x0
+#define BIF_CFG_DEV0_RC0_PCIE_CAP__DEVICE_TYPE__SHIFT                                                         0x4
+#define BIF_CFG_DEV0_RC0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                    0x8
+#define BIF_CFG_DEV0_RC0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                     0x9
+#define BIF_CFG_DEV0_RC0_PCIE_CAP__FLIT_MODE_SUPPORT__SHIFT                                                   0xf
+#define BIF_CFG_DEV0_RC0_PCIE_CAP__VERSION_MASK                                                               0x000FL
+#define BIF_CFG_DEV0_RC0_PCIE_CAP__DEVICE_TYPE_MASK                                                           0x00F0L
+#define BIF_CFG_DEV0_RC0_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                      0x0100L
+#define BIF_CFG_DEV0_RC0_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                       0x3E00L
+#define BIF_CFG_DEV0_RC0_PCIE_CAP__FLIT_MODE_SUPPORT_MASK                                                     0x8000L
+//BIF_CFG_DEV0_RC0_DEVICE_CAP
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                               0x0
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                      0x3
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                      0x5
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                            0x6
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                             0x9
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                          0xf
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT                                          0x10
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP__RX_MPS_FIXED__SHIFT                                                      0x11
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                         0x12
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                         0x1a
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                       0x1c
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP__MIXED_MPS_SUPPORTED__SHIFT                                               0x1d
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                                 0x00000007L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP__PHANTOM_FUNC_MASK                                                        0x00000018L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP__EXTENDED_TAG_MASK                                                        0x00000020L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                              0x000001C0L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                               0x00000E00L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                            0x00008000L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK                                            0x00010000L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP__RX_MPS_FIXED_MASK                                                        0x00020000L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                           0x03FC0000L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                           0x0C000000L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP__FLR_CAPABLE_MASK                                                         0x10000000L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP__MIXED_MPS_SUPPORTED_MASK                                                 0x20000000L
+//BIF_CFG_DEV0_RC0_DEVICE_CNTL
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                                 0x1
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                     0x2
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                    0x3
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                   0x4
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                                 0x5
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                                  0x8
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                                  0x9
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                                  0xa
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                      0xb
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                            0xc
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT                                              0xf
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__CORR_ERR_EN_MASK                                                        0x0001L
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                   0x0002L
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                       0x0004L
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__USR_REPORT_EN_MASK                                                      0x0008L
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                     0x0010L
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                   0x00E0L
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                    0x0100L
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                    0x0200L
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                    0x0400L
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                        0x0800L
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                              0x7000L
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK                                                0x8000L
+//BIF_CFG_DEV0_RC0_DEVICE_STATUS
+#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__CORR_ERR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                                  0x1
+#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__FATAL_ERR__SHIFT                                                      0x2
+#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__USR_DETECTED__SHIFT                                                   0x3
+#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__AUX_PWR__SHIFT                                                        0x4
+#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                              0x5
+#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                                  0x6
+#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__CORR_ERR_MASK                                                         0x0001L
+#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                    0x0002L
+#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__FATAL_ERR_MASK                                                        0x0004L
+#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__USR_DETECTED_MASK                                                     0x0008L
+#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__AUX_PWR_MASK                                                          0x0010L
+#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                                0x0020L
+#define BIF_CFG_DEV0_RC0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                    0x0040L
+//BIF_CFG_DEV0_RC0_LINK_CAP
+#define BIF_CFG_DEV0_RC0_LINK_CAP__LINK_SPEED__SHIFT                                                          0x0
+#define BIF_CFG_DEV0_RC0_LINK_CAP__LINK_WIDTH__SHIFT                                                          0x4
+#define BIF_CFG_DEV0_RC0_LINK_CAP__PM_SUPPORT__SHIFT                                                          0xa
+#define BIF_CFG_DEV0_RC0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                    0xc
+#define BIF_CFG_DEV0_RC0_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                     0xf
+#define BIF_CFG_DEV0_RC0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                              0x12
+#define BIF_CFG_DEV0_RC0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                         0x13
+#define BIF_CFG_DEV0_RC0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                         0x14
+#define BIF_CFG_DEV0_RC0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                            0x15
+#define BIF_CFG_DEV0_RC0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                         0x16
+#define BIF_CFG_DEV0_RC0_LINK_CAP__PORT_NUMBER__SHIFT                                                         0x18
+#define BIF_CFG_DEV0_RC0_LINK_CAP__LINK_SPEED_MASK                                                            0x0000000FL
+#define BIF_CFG_DEV0_RC0_LINK_CAP__LINK_WIDTH_MASK                                                            0x000003F0L
+#define BIF_CFG_DEV0_RC0_LINK_CAP__PM_SUPPORT_MASK                                                            0x00000C00L
+#define BIF_CFG_DEV0_RC0_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                      0x00007000L
+#define BIF_CFG_DEV0_RC0_LINK_CAP__L1_EXIT_LATENCY_MASK                                                       0x00038000L
+#define BIF_CFG_DEV0_RC0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                                0x00040000L
+#define BIF_CFG_DEV0_RC0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                           0x00080000L
+#define BIF_CFG_DEV0_RC0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                           0x00100000L
+#define BIF_CFG_DEV0_RC0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                              0x00200000L
+#define BIF_CFG_DEV0_RC0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                           0x00400000L
+#define BIF_CFG_DEV0_RC0_LINK_CAP__PORT_NUMBER_MASK                                                           0xFF000000L
+//BIF_CFG_DEV0_RC0_LINK_CNTL
+#define BIF_CFG_DEV0_RC0_LINK_CNTL__PM_CONTROL__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_RC0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT                                       0x2
+#define BIF_CFG_DEV0_RC0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                                  0x3
+#define BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_DIS__SHIFT                                                           0x4
+#define BIF_CFG_DEV0_RC0_LINK_CNTL__RETRAIN_LINK__SHIFT                                                       0x5
+#define BIF_CFG_DEV0_RC0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                   0x6
+#define BIF_CFG_DEV0_RC0_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                      0x7
+#define BIF_CFG_DEV0_RC0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                          0x8
+#define BIF_CFG_DEV0_RC0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                        0x9
+#define BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                          0xa
+#define BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                          0xb
+#define BIF_CFG_DEV0_RC0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                              0xe
+#define BIF_CFG_DEV0_RC0_LINK_CNTL__PM_CONTROL_MASK                                                           0x0003L
+#define BIF_CFG_DEV0_RC0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK                                         0x0004L
+#define BIF_CFG_DEV0_RC0_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                    0x0008L
+#define BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_DIS_MASK                                                             0x0010L
+#define BIF_CFG_DEV0_RC0_LINK_CNTL__RETRAIN_LINK_MASK                                                         0x0020L
+#define BIF_CFG_DEV0_RC0_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                     0x0040L
+#define BIF_CFG_DEV0_RC0_LINK_CNTL__EXTENDED_SYNC_MASK                                                        0x0080L
+#define BIF_CFG_DEV0_RC0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                            0x0100L
+#define BIF_CFG_DEV0_RC0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                          0x0200L
+#define BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                            0x0400L
+#define BIF_CFG_DEV0_RC0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                            0x0800L
+#define BIF_CFG_DEV0_RC0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                                0xC000L
+//BIF_CFG_DEV0_RC0_LINK_STATUS
+#define BIF_CFG_DEV0_RC0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                               0x0
+#define BIF_CFG_DEV0_RC0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                            0x4
+#define BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_TRAINING__SHIFT                                                    0xb
+#define BIF_CFG_DEV0_RC0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                   0xc
+#define BIF_CFG_DEV0_RC0_LINK_STATUS__DL_ACTIVE__SHIFT                                                        0xd
+#define BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                        0xe
+#define BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                        0xf
+#define BIF_CFG_DEV0_RC0_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                                 0x000FL
+#define BIF_CFG_DEV0_RC0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                              0x03F0L
+#define BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_TRAINING_MASK                                                      0x0800L
+#define BIF_CFG_DEV0_RC0_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                     0x1000L
+#define BIF_CFG_DEV0_RC0_LINK_STATUS__DL_ACTIVE_MASK                                                          0x2000L
+#define BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                          0x4000L
+#define BIF_CFG_DEV0_RC0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                          0x8000L
+//BIF_CFG_DEV0_RC0_SLOT_CAP
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT                                              0x1
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT                                                  0x2
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT                                              0x3
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT                                               0x4
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__HOTPLUG_SURPRISE__SHIFT                                                    0x5
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__HOTPLUG_CAPABLE__SHIFT                                                     0x6
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT                                                0x7
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT                                                0xf
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT                                       0x11
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT                                      0x12
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT                                                   0x13
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__ATTN_BUTTON_PRESENT_MASK                                                   0x00000001L
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK                                                0x00000002L
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__MRL_SENSOR_PRESENT_MASK                                                    0x00000004L
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK                                                0x00000008L
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__PWR_INDICATOR_PRESENT_MASK                                                 0x00000010L
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__HOTPLUG_SURPRISE_MASK                                                      0x00000020L
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__HOTPLUG_CAPABLE_MASK                                                       0x00000040L
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK                                                  0x00007F80L
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK                                                  0x00018000L
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK                                         0x00020000L
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK                                        0x00040000L
+#define BIF_CFG_DEV0_RC0_SLOT_CAP__PHYSICAL_SLOT_NUM_MASK                                                     0xFFF80000L
+//BIF_CFG_DEV0_RC0_SLOT_CNTL
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT                                             0x0
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT                                              0x1
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT                                              0x2
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT                                         0x3
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT                                          0x4
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT                                                    0x5
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT                                                0x6
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT                                                 0x8
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT                                                0xa
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT                                         0xb
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT                                                0xc
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT                                        0xd
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__INBAND_PD_DISABLE__SHIFT                                                  0xe
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK                                               0x0001L
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK                                                0x0002L
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK                                                0x0004L
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK                                           0x0008L
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK                                            0x0010L
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__HOTPLUG_INTR_EN_MASK                                                      0x0020L
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK                                                  0x00C0L
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_INDICATOR_CNTL_MASK                                                   0x0300L
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK                                                  0x0400L
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK                                           0x0800L
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__DL_STATE_CHANGED_EN_MASK                                                  0x1000L
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK                                          0x2000L
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL__INBAND_PD_DISABLE_MASK                                                    0x4000L
+//BIF_CFG_DEV0_RC0_SLOT_STATUS
+#define BIF_CFG_DEV0_RC0_SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT                                              0x0
+#define BIF_CFG_DEV0_RC0_SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT                                               0x1
+#define BIF_CFG_DEV0_RC0_SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT                                               0x2
+#define BIF_CFG_DEV0_RC0_SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT                                          0x3
+#define BIF_CFG_DEV0_RC0_SLOT_STATUS__COMMAND_COMPLETED__SHIFT                                                0x4
+#define BIF_CFG_DEV0_RC0_SLOT_STATUS__MRL_SENSOR_STATE__SHIFT                                                 0x5
+#define BIF_CFG_DEV0_RC0_SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT                                            0x6
+#define BIF_CFG_DEV0_RC0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT                                     0x7
+#define BIF_CFG_DEV0_RC0_SLOT_STATUS__DL_STATE_CHANGED__SHIFT                                                 0x8
+#define BIF_CFG_DEV0_RC0_SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK                                                0x0001L
+#define BIF_CFG_DEV0_RC0_SLOT_STATUS__PWR_FAULT_DETECTED_MASK                                                 0x0002L
+#define BIF_CFG_DEV0_RC0_SLOT_STATUS__MRL_SENSOR_CHANGED_MASK                                                 0x0004L
+#define BIF_CFG_DEV0_RC0_SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK                                            0x0008L
+#define BIF_CFG_DEV0_RC0_SLOT_STATUS__COMMAND_COMPLETED_MASK                                                  0x0010L
+#define BIF_CFG_DEV0_RC0_SLOT_STATUS__MRL_SENSOR_STATE_MASK                                                   0x0020L
+#define BIF_CFG_DEV0_RC0_SLOT_STATUS__PRESENCE_DETECT_STATE_MASK                                              0x0040L
+#define BIF_CFG_DEV0_RC0_SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK                                       0x0080L
+#define BIF_CFG_DEV0_RC0_SLOT_STATUS__DL_STATE_CHANGED_MASK                                                   0x0100L
+//BIF_CFG_DEV0_RC0_ROOT_CNTL
+#define BIF_CFG_DEV0_RC0_ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT                                                0x0
+#define BIF_CFG_DEV0_RC0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT                                            0x1
+#define BIF_CFG_DEV0_RC0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT                                               0x2
+#define BIF_CFG_DEV0_RC0_ROOT_CNTL__PM_INTERRUPT_EN__SHIFT                                                    0x3
+#define BIF_CFG_DEV0_RC0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT                                         0x4
+#define BIF_CFG_DEV0_RC0_ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK                                                  0x0001L
+#define BIF_CFG_DEV0_RC0_ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK                                              0x0002L
+#define BIF_CFG_DEV0_RC0_ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK                                                 0x0004L
+#define BIF_CFG_DEV0_RC0_ROOT_CNTL__PM_INTERRUPT_EN_MASK                                                      0x0008L
+#define BIF_CFG_DEV0_RC0_ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK                                           0x0010L
+//BIF_CFG_DEV0_RC0_ROOT_CAP
+#define BIF_CFG_DEV0_RC0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT                                             0x0
+#define BIF_CFG_DEV0_RC0_ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK                                               0x0001L
+//BIF_CFG_DEV0_RC0_ROOT_STATUS
+#define BIF_CFG_DEV0_RC0_ROOT_STATUS__PME_REQUESTOR_ID__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_RC0_ROOT_STATUS__PME_STATUS__SHIFT                                                       0x10
+#define BIF_CFG_DEV0_RC0_ROOT_STATUS__PME_PENDING__SHIFT                                                      0x11
+#define BIF_CFG_DEV0_RC0_ROOT_STATUS__PME_REQUESTOR_ID_MASK                                                   0x0000FFFFL
+#define BIF_CFG_DEV0_RC0_ROOT_STATUS__PME_STATUS_MASK                                                         0x00010000L
+#define BIF_CFG_DEV0_RC0_ROOT_STATUS__PME_PENDING_MASK                                                        0x00020000L
+//BIF_CFG_DEV0_RC0_DEVICE_CAP2
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                      0x0
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                        0x4
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                         0x5
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                       0x6
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                       0x7
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                       0x8
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                           0x9
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                        0xa
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                    0xb
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                               0xc
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                    0xe
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                                  0x10
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                                  0x11
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                   0x12
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                     0x14
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                     0x15
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                         0x16
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                   0x18
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                    0x1a
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                    0x1f
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                        0x0000000FL
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                          0x00000010L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                           0x00000020L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                         0x00000040L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                         0x00000080L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                         0x00000100L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                             0x00000200L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                          0x00000400L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                      0x00000800L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                                 0x00003000L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                      0x0000C000L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                    0x00010000L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                    0x00020000L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                     0x000C0000L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                       0x00100000L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                       0x00200000L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                           0x00C00000L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                     0x03000000L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                      0x04000000L
+#define BIF_CFG_DEV0_RC0_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                      0x80000000L
+//BIF_CFG_DEV0_RC0_DEVICE_CNTL2
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                               0x0
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                                 0x4
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                               0x5
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                             0x6
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                        0x7
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                              0x8
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                           0x9
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__LTR_EN__SHIFT                                                          0xa
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                    0xb
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                    0xc
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__OBFF_EN__SHIFT                                                         0xd
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                     0xf
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                                 0x000FL
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                   0x0010L
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                                 0x0020L
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                               0x0040L
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                          0x0080L
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                                0x0100L
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                             0x0200L
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__LTR_EN_MASK                                                            0x0400L
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                      0x0800L
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                      0x1000L
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__OBFF_EN_MASK                                                           0x6000L
+#define BIF_CFG_DEV0_RC0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                       0x8000L
+//BIF_CFG_DEV0_RC0_DEVICE_STATUS2
+#define BIF_CFG_DEV0_RC0_DEVICE_STATUS2__RESERVED__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_RC0_DEVICE_STATUS2__RESERVED_MASK                                                        0xFFFFL
+//BIF_CFG_DEV0_RC0_LINK_CAP2
+#define BIF_CFG_DEV0_RC0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                               0x1
+#define BIF_CFG_DEV0_RC0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                                0x8
+#define BIF_CFG_DEV0_RC0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT                                           0x9
+#define BIF_CFG_DEV0_RC0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                           0x10
+#define BIF_CFG_DEV0_RC0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                          0x17
+#define BIF_CFG_DEV0_RC0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                          0x18
+#define BIF_CFG_DEV0_RC0_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                      0x1f
+#define BIF_CFG_DEV0_RC0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                                 0x000000FEL
+#define BIF_CFG_DEV0_RC0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                                  0x00000100L
+#define BIF_CFG_DEV0_RC0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK                                             0x0000FE00L
+#define BIF_CFG_DEV0_RC0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                             0x007F0000L
+#define BIF_CFG_DEV0_RC0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                            0x00800000L
+#define BIF_CFG_DEV0_RC0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                            0x01000000L
+#define BIF_CFG_DEV0_RC0_LINK_CAP2__DRS_SUPPORTED_MASK                                                        0x80000000L
+//BIF_CFG_DEV0_RC0_LINK_CNTL2
+#define BIF_CFG_DEV0_RC0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_RC0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                                  0x4
+#define BIF_CFG_DEV0_RC0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                       0x5
+#define BIF_CFG_DEV0_RC0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                             0x6
+#define BIF_CFG_DEV0_RC0_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                       0x7
+#define BIF_CFG_DEV0_RC0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                              0xa
+#define BIF_CFG_DEV0_RC0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                    0xb
+#define BIF_CFG_DEV0_RC0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                             0xc
+#define BIF_CFG_DEV0_RC0_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                   0x000FL
+#define BIF_CFG_DEV0_RC0_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                    0x0010L
+#define BIF_CFG_DEV0_RC0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                         0x0020L
+#define BIF_CFG_DEV0_RC0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                               0x0040L
+#define BIF_CFG_DEV0_RC0_LINK_CNTL2__XMIT_MARGIN_MASK                                                         0x0380L
+#define BIF_CFG_DEV0_RC0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                                0x0400L
+#define BIF_CFG_DEV0_RC0_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                      0x0800L
+#define BIF_CFG_DEV0_RC0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                               0xF000L
+//BIF_CFG_DEV0_RC0_LINK_STATUS2
+#define BIF_CFG_DEV0_RC0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                            0x0
+#define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                       0x1
+#define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                                 0x2
+#define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                                 0x3
+#define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                                 0x4
+#define BIF_CFG_DEV0_RC0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                   0x5
+#define BIF_CFG_DEV0_RC0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                               0x6
+#define BIF_CFG_DEV0_RC0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                               0x7
+#define BIF_CFG_DEV0_RC0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                            0x8
+#define BIF_CFG_DEV0_RC0_LINK_STATUS2__FLIT_MODE_STATUS__SHIFT                                                0xa
+#define BIF_CFG_DEV0_RC0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                   0xc
+#define BIF_CFG_DEV0_RC0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                            0xf
+#define BIF_CFG_DEV0_RC0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                              0x0001L
+#define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                         0x0002L
+#define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                   0x0004L
+#define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                   0x0008L
+#define BIF_CFG_DEV0_RC0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                   0x0010L
+#define BIF_CFG_DEV0_RC0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                     0x0020L
+#define BIF_CFG_DEV0_RC0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                                 0x0040L
+#define BIF_CFG_DEV0_RC0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                                 0x0080L
+#define BIF_CFG_DEV0_RC0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                              0x0300L
+#define BIF_CFG_DEV0_RC0_LINK_STATUS2__FLIT_MODE_STATUS_MASK                                                  0x0400L
+#define BIF_CFG_DEV0_RC0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                     0x7000L
+#define BIF_CFG_DEV0_RC0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                              0x8000L
+//BIF_CFG_DEV0_RC0_SLOT_CAP2
+#define BIF_CFG_DEV0_RC0_SLOT_CAP2__INBAND_PD_DISABLE_SUPPORTED__SHIFT                                        0x0
+#define BIF_CFG_DEV0_RC0_SLOT_CAP2__INBAND_PD_DISABLE_SUPPORTED_MASK                                          0x00000001L
+//BIF_CFG_DEV0_RC0_SLOT_CNTL2
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL2__RESERVED__SHIFT                                                          0x0
+#define BIF_CFG_DEV0_RC0_SLOT_CNTL2__RESERVED_MASK                                                            0xFFFFL
+//BIF_CFG_DEV0_RC0_SLOT_STATUS2
+#define BIF_CFG_DEV0_RC0_SLOT_STATUS2__RESERVED__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_RC0_SLOT_STATUS2__RESERVED_MASK                                                          0xFFFFL
+//BIF_CFG_DEV0_RC0_MSI_CAP_LIST
+#define BIF_CFG_DEV0_RC0_MSI_CAP_LIST__CAP_ID__SHIFT                                                          0x0
+#define BIF_CFG_DEV0_RC0_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                        0x8
+#define BIF_CFG_DEV0_RC0_MSI_CAP_LIST__CAP_ID_MASK                                                            0x00FFL
+#define BIF_CFG_DEV0_RC0_MSI_CAP_LIST__NEXT_PTR_MASK                                                          0xFF00L
+//BIF_CFG_DEV0_RC0_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_EN__SHIFT                                                          0x0
+#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                   0x1
+#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                    0x4
+#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                       0x7
+#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                       0x8
+#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT                                            0x9
+#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT                                             0xa
+#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_EN_MASK                                                            0x0001L
+#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                     0x000EL
+#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                      0x0070L
+#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_64BIT_MASK                                                         0x0080L
+#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                         0x0100L
+#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK                                              0x0200L
+#define BIF_CFG_DEV0_RC0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK                                               0x0400L
+//BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                              0x2
+#define BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                                0xFFFFFFFCL
+//BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                              0x0
+#define BIF_CFG_DEV0_RC0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                                0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_MSI_MSG_DATA
+#define BIF_CFG_DEV0_RC0_MSI_MSG_DATA__MSI_DATA__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_RC0_MSI_MSG_DATA__MSI_DATA_MASK                                                          0xFFFFL
+//BIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT                                                0x0
+#define BIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK                                                  0xFFFFL
+//BIF_CFG_DEV0_RC0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_RC0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_RC0_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                    0xFFFFL
+//BIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT                                          0x0
+#define BIF_CFG_DEV0_RC0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK                                            0xFFFFL
+//BIF_CFG_DEV0_RC0_SSID_CAP_LIST
+#define BIF_CFG_DEV0_RC0_SSID_CAP_LIST__CAP_ID__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_RC0_SSID_CAP_LIST__NEXT_PTR__SHIFT                                                       0x8
+#define BIF_CFG_DEV0_RC0_SSID_CAP_LIST__CAP_ID_MASK                                                           0x00FFL
+#define BIF_CFG_DEV0_RC0_SSID_CAP_LIST__NEXT_PTR_MASK                                                         0xFF00L
+//BIF_CFG_DEV0_RC0_SSID_CAP
+#define BIF_CFG_DEV0_RC0_SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_RC0_SSID_CAP__SUBSYSTEM_ID__SHIFT                                                        0x10
+#define BIF_CFG_DEV0_RC0_SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK                                                   0x0000FFFFL
+#define BIF_CFG_DEV0_RC0_SSID_CAP__SUBSYSTEM_ID_MASK                                                          0xFFFF0000L
+//BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                     0x0
+#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                    0x10
+#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                   0x14
+#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                       0x0000FFFFL
+#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                      0x000F0000L
+#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                     0xFFF00000L
+//BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                             0x0
+#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                            0x10
+#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                         0x14
+#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                               0x0000FFFFL
+#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                              0x000F0000L
+#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                           0xFFF00000L
+//BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                                0x0
+#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                                  0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                                0x0
+#define BIF_CFG_DEV0_RC0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                                  0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT                                           0x0
+#define BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT                                          0x10
+#define BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT                                         0x14
+#define BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK                                             0x0000FFFFL
+#define BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK                                            0x000F0000L
+#define BIF_CFG_DEV0_RC0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK                                           0xFFF00000L
+//BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3
+#define BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT                                         0x0
+#define BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT                                 0x1
+#define BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT                                      0x9
+#define BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK                                           0x00000001L
+#define BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK                                   0x00000002L
+#define BIF_CFG_DEV0_RC0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK                                        0x0000FE00L
+//BIF_CFG_DEV0_RC0_PCIE_LANE_ERROR_STATUS
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT                                0x0
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK                                  0x0000FFFFL
+//BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
+//BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
+//BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
+//BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
+//BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
+//BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
+//BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
+//BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
+//BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
+//BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
+//BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
+//BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
+//BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
+//BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
+//BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
+//BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0x4
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x8
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0xc
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                   0x000FL
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x0070L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                     0x0F00L
+#define BIF_CFG_DEV0_RC0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x7000L
+//BIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
+#define BIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
+#define BIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
+#define BIF_CFG_DEV0_RC0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
+//BIF_CFG_DEV0_RC0_LINK_CAP_16GT
+#define BIF_CFG_DEV0_RC0_LINK_CAP_16GT__RESERVED__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_RC0_LINK_CAP_16GT__RESERVED_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_LINK_CNTL_16GT
+#define BIF_CFG_DEV0_RC0_LINK_CNTL_16GT__RESERVED__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_RC0_LINK_CNTL_16GT__RESERVED_MASK                                                        0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_LINK_STATUS_16GT
+#define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT                                  0x0
+#define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT                            0x1
+#define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT                            0x2
+#define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT                            0x3
+#define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT                              0x4
+#define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK                                    0x00000001L
+#define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK                              0x00000002L
+#define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK                              0x00000004L
+#define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK                              0x00000008L
+#define BIF_CFG_DEV0_RC0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK                                0x00000010L
+//BIF_CFG_DEV0_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT          0x0
+#define BIF_CFG_DEV0_RC0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK            0x0000FFFFL
+//BIF_CFG_DEV0_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT            0x0
+#define BIF_CFG_DEV0_RC0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK              0x0000FFFFL
+//BIF_CFG_DEV0_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT            0x0
+#define BIF_CFG_DEV0_RC0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK              0x0000FFFFL
+//BIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT                      0x0
+#define BIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT                      0x4
+#define BIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK                        0x0FL
+#define BIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK                        0xF0L
+//BIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT                      0x0
+#define BIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT                      0x4
+#define BIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK                        0x0FL
+#define BIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK                        0xF0L
+//BIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT                      0x0
+#define BIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT                      0x4
+#define BIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK                        0x0FL
+#define BIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK                        0xF0L
+//BIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT                      0x0
+#define BIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT                      0x4
+#define BIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK                        0x0FL
+#define BIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK                        0xF0L
+//BIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT                      0x0
+#define BIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT                      0x4
+#define BIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK                        0x0FL
+#define BIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK                        0xF0L
+//BIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT                      0x0
+#define BIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT                      0x4
+#define BIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK                        0x0FL
+#define BIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK                        0xF0L
+//BIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT                      0x0
+#define BIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT                      0x4
+#define BIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK                        0x0FL
+#define BIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK                        0xF0L
+//BIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT                      0x0
+#define BIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT                      0x4
+#define BIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK                        0x0FL
+#define BIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK                        0xF0L
+//BIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT                      0x0
+#define BIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT                      0x4
+#define BIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK                        0x0FL
+#define BIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK                        0xF0L
+//BIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT                      0x0
+#define BIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT                      0x4
+#define BIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK                        0x0FL
+#define BIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK                        0xF0L
+//BIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT                    0x0
+#define BIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT                    0x4
+#define BIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK                      0x0FL
+#define BIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK                      0xF0L
+//BIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT                    0x0
+#define BIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT                    0x4
+#define BIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK                      0x0FL
+#define BIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK                      0xF0L
+//BIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT                    0x0
+#define BIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT                    0x4
+#define BIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK                      0x0FL
+#define BIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK                      0xF0L
+//BIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT                    0x0
+#define BIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT                    0x4
+#define BIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK                      0x0FL
+#define BIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK                      0xF0L
+//BIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT                    0x0
+#define BIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT                    0x4
+#define BIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK                      0x0FL
+#define BIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK                      0xF0L
+//BIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT                    0x0
+#define BIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT                    0x4
+#define BIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK                      0x0FL
+#define BIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK                      0xF0L
+//BIF_CFG_DEV0_RC0_PCIE_PHY_32GT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC0_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_RC0_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
+#define BIF_CFG_DEV0_RC0_PCIE_PHY_32GT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
+#define BIF_CFG_DEV0_RC0_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV0_RC0_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
+#define BIF_CFG_DEV0_RC0_PCIE_PHY_32GT_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
+//BIF_CFG_DEV0_RC0_LINK_CAP_32GT
+#define BIF_CFG_DEV0_RC0_LINK_CAP_32GT__EQ_BYPASS_TO_HIGHEST_RATE_SUPPORTED__SHIFT                            0x0
+#define BIF_CFG_DEV0_RC0_LINK_CAP_32GT__NO_EQ_NEEDED_SUPPORTED__SHIFT                                         0x1
+#define BIF_CFG_DEV0_RC0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE0_SUPPORTED__SHIFT                              0x8
+#define BIF_CFG_DEV0_RC0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE1_SUPPORTED__SHIFT                              0x9
+#define BIF_CFG_DEV0_RC0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE2_SUPPORTED__SHIFT                              0xa
+#define BIF_CFG_DEV0_RC0_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES__SHIFT                               0xb
+#define BIF_CFG_DEV0_RC0_LINK_CAP_32GT__EQ_BYPASS_TO_HIGHEST_RATE_SUPPORTED_MASK                              0x00000001L
+#define BIF_CFG_DEV0_RC0_LINK_CAP_32GT__NO_EQ_NEEDED_SUPPORTED_MASK                                           0x00000002L
+#define BIF_CFG_DEV0_RC0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE0_SUPPORTED_MASK                                0x00000100L
+#define BIF_CFG_DEV0_RC0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE1_SUPPORTED_MASK                                0x00000200L
+#define BIF_CFG_DEV0_RC0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE2_SUPPORTED_MASK                                0x00000400L
+#define BIF_CFG_DEV0_RC0_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES_MASK                                 0x0000F800L
+//BIF_CFG_DEV0_RC0_LINK_CNTL_32GT
+#define BIF_CFG_DEV0_RC0_LINK_CNTL_32GT__EQ_BYPASS_TO_HIGHEST_RATE_DIS__SHIFT                                 0x0
+#define BIF_CFG_DEV0_RC0_LINK_CNTL_32GT__NO_EQ_NEEDED_DIS__SHIFT                                              0x1
+#define BIF_CFG_DEV0_RC0_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SEL__SHIFT                                    0x8
+#define BIF_CFG_DEV0_RC0_LINK_CNTL_32GT__EQ_BYPASS_TO_HIGHEST_RATE_DIS_MASK                                   0x00000001L
+#define BIF_CFG_DEV0_RC0_LINK_CNTL_32GT__NO_EQ_NEEDED_DIS_MASK                                                0x00000002L
+#define BIF_CFG_DEV0_RC0_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SEL_MASK                                      0x00000700L
+//BIF_CFG_DEV0_RC0_LINK_STATUS_32GT
+#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT__SHIFT                                  0x0
+#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT__SHIFT                            0x1
+#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT__SHIFT                            0x2
+#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT__SHIFT                            0x3
+#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT__SHIFT                              0x4
+#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED__SHIFT                                        0x5
+#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOR_CNTL__SHIFT                        0x6
+#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON__SHIFT                                    0x8
+#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST__SHIFT                                 0x9
+#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__NO_EQ_NEEDED_RECEIVED__SHIFT                                       0xa
+#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT_MASK                                    0x00000001L
+#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT_MASK                              0x00000002L
+#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT_MASK                              0x00000004L
+#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT_MASK                              0x00000008L
+#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT_MASK                                0x00000010L
+#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED_MASK                                          0x00000020L
+#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOR_CNTL_MASK                          0x000000C0L
+#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON_MASK                                      0x00000100L
+#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST_MASK                                   0x00000200L
+#define BIF_CFG_DEV0_RC0_LINK_STATUS_32GT__NO_EQ_NEEDED_RECEIVED_MASK                                         0x00000400L
+//BIF_CFG_DEV0_RC0_RECEIVED_MODIFIED_TS_DATA1
+#define BIF_CFG_DEV0_RC0_RECEIVED_MODIFIED_TS_DATA1__USAGE_MODE__SHIFT                                        0x0
+#define BIF_CFG_DEV0_RC0_RECEIVED_MODIFIED_TS_DATA1__INFOR1__SHIFT                                            0x3
+#define BIF_CFG_DEV0_RC0_RECEIVED_MODIFIED_TS_DATA1__VENDORID__SHIFT                                          0x10
+#define BIF_CFG_DEV0_RC0_RECEIVED_MODIFIED_TS_DATA1__USAGE_MODE_MASK                                          0x00000007L
+#define BIF_CFG_DEV0_RC0_RECEIVED_MODIFIED_TS_DATA1__INFOR1_MASK                                              0x0000FFF8L
+#define BIF_CFG_DEV0_RC0_RECEIVED_MODIFIED_TS_DATA1__VENDORID_MASK                                            0xFFFF0000L
+//BIF_CFG_DEV0_RC0_RECEIVED_MODIFIED_TS_DATA2
+#define BIF_CFG_DEV0_RC0_RECEIVED_MODIFIED_TS_DATA2__INFOR2__SHIFT                                            0x0
+#define BIF_CFG_DEV0_RC0_RECEIVED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS__SHIFT             0x18
+#define BIF_CFG_DEV0_RC0_RECEIVED_MODIFIED_TS_DATA2__INFOR2_MASK                                              0x00FFFFFFL
+#define BIF_CFG_DEV0_RC0_RECEIVED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS_MASK               0x03000000L
+//BIF_CFG_DEV0_RC0_TRANSMITTED_MODIFIED_TS_DATA1
+#define BIF_CFG_DEV0_RC0_TRANSMITTED_MODIFIED_TS_DATA1__USAGE_MODE__SHIFT                                     0x0
+#define BIF_CFG_DEV0_RC0_TRANSMITTED_MODIFIED_TS_DATA1__INFOR1__SHIFT                                         0x3
+#define BIF_CFG_DEV0_RC0_TRANSMITTED_MODIFIED_TS_DATA1__VENDORID__SHIFT                                       0x10
+#define BIF_CFG_DEV0_RC0_TRANSMITTED_MODIFIED_TS_DATA1__USAGE_MODE_MASK                                       0x00000007L
+#define BIF_CFG_DEV0_RC0_TRANSMITTED_MODIFIED_TS_DATA1__INFOR1_MASK                                           0x0000FFF8L
+#define BIF_CFG_DEV0_RC0_TRANSMITTED_MODIFIED_TS_DATA1__VENDORID_MASK                                         0xFFFF0000L
+//BIF_CFG_DEV0_RC0_TRANSMITTED_MODIFIED_TS_DATA2
+#define BIF_CFG_DEV0_RC0_TRANSMITTED_MODIFIED_TS_DATA2__INFOR2__SHIFT                                         0x0
+#define BIF_CFG_DEV0_RC0_TRANSMITTED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS__SHIFT          0x18
+#define BIF_CFG_DEV0_RC0_TRANSMITTED_MODIFIED_TS_DATA2__INFOR2_MASK                                           0x00FFFFFFL
+#define BIF_CFG_DEV0_RC0_TRANSMITTED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS_MASK            0x03000000L
+//BIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_32GT
+#define BIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_DSP_32GT_TX_PRESET__SHIFT                      0x0
+#define BIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_USP_32GT_TX_PRESET__SHIFT                      0x4
+#define BIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_DSP_32GT_TX_PRESET_MASK                        0x0FL
+#define BIF_CFG_DEV0_RC0_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_USP_32GT_TX_PRESET_MASK                        0xF0L
+//BIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_32GT
+#define BIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_DSP_32GT_TX_PRESET__SHIFT                      0x0
+#define BIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_USP_32GT_TX_PRESET__SHIFT                      0x4
+#define BIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_DSP_32GT_TX_PRESET_MASK                        0x0FL
+#define BIF_CFG_DEV0_RC0_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_USP_32GT_TX_PRESET_MASK                        0xF0L
+//BIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_32GT
+#define BIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_DSP_32GT_TX_PRESET__SHIFT                      0x0
+#define BIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_USP_32GT_TX_PRESET__SHIFT                      0x4
+#define BIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_DSP_32GT_TX_PRESET_MASK                        0x0FL
+#define BIF_CFG_DEV0_RC0_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_USP_32GT_TX_PRESET_MASK                        0xF0L
+//BIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_32GT
+#define BIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_DSP_32GT_TX_PRESET__SHIFT                      0x0
+#define BIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_USP_32GT_TX_PRESET__SHIFT                      0x4
+#define BIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_DSP_32GT_TX_PRESET_MASK                        0x0FL
+#define BIF_CFG_DEV0_RC0_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_USP_32GT_TX_PRESET_MASK                        0xF0L
+//BIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_32GT
+#define BIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_DSP_32GT_TX_PRESET__SHIFT                      0x0
+#define BIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_USP_32GT_TX_PRESET__SHIFT                      0x4
+#define BIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_DSP_32GT_TX_PRESET_MASK                        0x0FL
+#define BIF_CFG_DEV0_RC0_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_USP_32GT_TX_PRESET_MASK                        0xF0L
+//BIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_32GT
+#define BIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_DSP_32GT_TX_PRESET__SHIFT                      0x0
+#define BIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_USP_32GT_TX_PRESET__SHIFT                      0x4
+#define BIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_DSP_32GT_TX_PRESET_MASK                        0x0FL
+#define BIF_CFG_DEV0_RC0_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_USP_32GT_TX_PRESET_MASK                        0xF0L
+//BIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_32GT
+#define BIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_DSP_32GT_TX_PRESET__SHIFT                      0x0
+#define BIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_USP_32GT_TX_PRESET__SHIFT                      0x4
+#define BIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_DSP_32GT_TX_PRESET_MASK                        0x0FL
+#define BIF_CFG_DEV0_RC0_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_USP_32GT_TX_PRESET_MASK                        0xF0L
+//BIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_32GT
+#define BIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_DSP_32GT_TX_PRESET__SHIFT                      0x0
+#define BIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_USP_32GT_TX_PRESET__SHIFT                      0x4
+#define BIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_DSP_32GT_TX_PRESET_MASK                        0x0FL
+#define BIF_CFG_DEV0_RC0_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_USP_32GT_TX_PRESET_MASK                        0xF0L
+//BIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_32GT
+#define BIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_DSP_32GT_TX_PRESET__SHIFT                      0x0
+#define BIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_USP_32GT_TX_PRESET__SHIFT                      0x4
+#define BIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_DSP_32GT_TX_PRESET_MASK                        0x0FL
+#define BIF_CFG_DEV0_RC0_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_USP_32GT_TX_PRESET_MASK                        0xF0L
+//BIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_32GT
+#define BIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_DSP_32GT_TX_PRESET__SHIFT                      0x0
+#define BIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_USP_32GT_TX_PRESET__SHIFT                      0x4
+#define BIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_DSP_32GT_TX_PRESET_MASK                        0x0FL
+#define BIF_CFG_DEV0_RC0_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_USP_32GT_TX_PRESET_MASK                        0xF0L
+//BIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_32GT
+#define BIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_DSP_32GT_TX_PRESET__SHIFT                    0x0
+#define BIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_USP_32GT_TX_PRESET__SHIFT                    0x4
+#define BIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_DSP_32GT_TX_PRESET_MASK                      0x0FL
+#define BIF_CFG_DEV0_RC0_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_USP_32GT_TX_PRESET_MASK                      0xF0L
+//BIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_32GT
+#define BIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_DSP_32GT_TX_PRESET__SHIFT                    0x0
+#define BIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_USP_32GT_TX_PRESET__SHIFT                    0x4
+#define BIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_DSP_32GT_TX_PRESET_MASK                      0x0FL
+#define BIF_CFG_DEV0_RC0_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_USP_32GT_TX_PRESET_MASK                      0xF0L
+//BIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_32GT
+#define BIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_DSP_32GT_TX_PRESET__SHIFT                    0x0
+#define BIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_USP_32GT_TX_PRESET__SHIFT                    0x4
+#define BIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_DSP_32GT_TX_PRESET_MASK                      0x0FL
+#define BIF_CFG_DEV0_RC0_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_USP_32GT_TX_PRESET_MASK                      0xF0L
+//BIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_32GT
+#define BIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_DSP_32GT_TX_PRESET__SHIFT                    0x0
+#define BIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_USP_32GT_TX_PRESET__SHIFT                    0x4
+#define BIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_DSP_32GT_TX_PRESET_MASK                      0x0FL
+#define BIF_CFG_DEV0_RC0_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_USP_32GT_TX_PRESET_MASK                      0xF0L
+//BIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_32GT
+#define BIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_DSP_32GT_TX_PRESET__SHIFT                    0x0
+#define BIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_USP_32GT_TX_PRESET__SHIFT                    0x4
+#define BIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_DSP_32GT_TX_PRESET_MASK                      0x0FL
+#define BIF_CFG_DEV0_RC0_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_USP_32GT_TX_PRESET_MASK                      0xF0L
+//BIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_32GT
+#define BIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_DSP_32GT_TX_PRESET__SHIFT                    0x0
+#define BIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_USP_32GT_TX_PRESET__SHIFT                    0x4
+#define BIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_DSP_32GT_TX_PRESET_MASK                      0x0FL
+#define BIF_CFG_DEV0_RC0_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_USP_32GT_TX_PRESET_MASK                      0xF0L
+//BIF_CFG_DEV0_RC0_PCIE_AP_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC0_PCIE_AP_ENH_CAP_LIST__CAP_ID__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_RC0_PCIE_AP_ENH_CAP_LIST__CAP_VER__SHIFT                                                 0x10
+#define BIF_CFG_DEV0_RC0_PCIE_AP_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                0x14
+#define BIF_CFG_DEV0_RC0_PCIE_AP_ENH_CAP_LIST__CAP_ID_MASK                                                    0x0000FFFFL
+#define BIF_CFG_DEV0_RC0_PCIE_AP_ENH_CAP_LIST__CAP_VER_MASK                                                   0x000F0000L
+#define BIF_CFG_DEV0_RC0_PCIE_AP_ENH_CAP_LIST__NEXT_PTR_MASK                                                  0xFFF00000L
+//BIF_CFG_DEV0_RC0_AP_CAP
+#define BIF_CFG_DEV0_RC0_AP_CAP__COUNT__SHIFT                                                                 0x0
+#define BIF_CFG_DEV0_RC0_AP_CAP__SEL_EN_SUPPORTED__SHIFT                                                      0x8
+#define BIF_CFG_DEV0_RC0_AP_CAP__COUNT_MASK                                                                   0x000000FFL
+#define BIF_CFG_DEV0_RC0_AP_CAP__SEL_EN_SUPPORTED_MASK                                                        0x00000100L
+//BIF_CFG_DEV0_RC0_AP_CNTL
+#define BIF_CFG_DEV0_RC0_AP_CNTL__INX_SEL__SHIFT                                                              0x0
+#define BIF_CFG_DEV0_RC0_AP_CNTL__NEGO_GLOBAL_EN__SHIFT                                                       0x8
+#define BIF_CFG_DEV0_RC0_AP_CNTL__INX_SEL_MASK                                                                0x000000FFL
+#define BIF_CFG_DEV0_RC0_AP_CNTL__NEGO_GLOBAL_EN_MASK                                                         0x00000100L
+//BIF_CFG_DEV0_RC0_AP_DATA1
+#define BIF_CFG_DEV0_RC0_AP_DATA1__USAGE_INFOR__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_RC0_AP_DATA1__DETAILS__SHIFT                                                             0x5
+#define BIF_CFG_DEV0_RC0_AP_DATA1__VENDORID__SHIFT                                                            0x10
+#define BIF_CFG_DEV0_RC0_AP_DATA1__USAGE_INFOR_MASK                                                           0x00000007L
+#define BIF_CFG_DEV0_RC0_AP_DATA1__DETAILS_MASK                                                               0x0000FFE0L
+#define BIF_CFG_DEV0_RC0_AP_DATA1__VENDORID_MASK                                                              0xFFFF0000L
+//BIF_CFG_DEV0_RC0_AP_DATA2
+#define BIF_CFG_DEV0_RC0_AP_DATA2__MODIFIED_TS_INFOR2__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_RC0_AP_DATA2__MODIFIED_TS_INFOR2_MASK                                                    0x00FFFFFFL
+//BIF_CFG_DEV0_RC0_AP_SEL_EN_MASK
+#define BIF_CFG_DEV0_RC0_AP_SEL_EN_MASK__PCIE__SHIFT                                                          0x0
+#define BIF_CFG_DEV0_RC0_AP_SEL_EN_MASK__OTHERS__SHIFT                                                        0x1
+#define BIF_CFG_DEV0_RC0_AP_SEL_EN_MASK__PCIE_MASK                                                            0x00000001L
+#define BIF_CFG_DEV0_RC0_AP_SEL_EN_MASK__OTHERS_MASK                                                          0xFFFFFFFEL
+//BIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT                                           0x0
+#define BIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT                                          0x10
+#define BIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT                                         0x14
+#define BIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK                                             0x0000FFFFL
+#define BIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK                                            0x000F0000L
+#define BIF_CFG_DEV0_RC0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK                                           0xFFF00000L
+//BIF_CFG_DEV0_RC0_MARGINING_PORT_CAP
+#define BIF_CFG_DEV0_RC0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT                                   0x0
+#define BIF_CFG_DEV0_RC0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK                                     0x0001L
+//BIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS
+#define BIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT                                        0x0
+#define BIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT                               0x1
+#define BIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS__MARGINING_READY_MASK                                          0x0001L
+#define BIF_CFG_DEV0_RC0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK                                 0x0002L
+//BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT                            0x0
+#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT                                0x3
+#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT                                0x6
+#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT                             0x8
+#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK                              0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK                                  0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK                                  0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK                               0xFF00L
+//BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
+#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT                       0x3
+#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT                       0x6
+#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
+#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK                         0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK                         0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
+//BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT                            0x0
+#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT                                0x3
+#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT                                0x6
+#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT                             0x8
+#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK                              0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK                                  0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK                                  0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK                               0xFF00L
+//BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
+#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT                       0x3
+#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT                       0x6
+#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
+#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK                         0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK                         0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
+//BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT                            0x0
+#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT                                0x3
+#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT                                0x6
+#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT                             0x8
+#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK                              0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK                                  0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK                                  0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK                               0xFF00L
+//BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
+#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT                       0x3
+#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT                       0x6
+#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
+#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK                         0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK                         0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
+//BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT                            0x0
+#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT                                0x3
+#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT                                0x6
+#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT                             0x8
+#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK                              0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK                                  0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK                                  0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK                               0xFF00L
+//BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
+#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT                       0x3
+#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT                       0x6
+#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
+#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK                         0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK                         0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
+//BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT                            0x0
+#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT                                0x3
+#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT                                0x6
+#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT                             0x8
+#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK                              0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK                                  0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK                                  0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK                               0xFF00L
+//BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
+#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT                       0x3
+#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT                       0x6
+#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
+#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK                         0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK                         0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
+//BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT                            0x0
+#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT                                0x3
+#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT                                0x6
+#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT                             0x8
+#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK                              0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK                                  0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK                                  0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK                               0xFF00L
+//BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
+#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT                       0x3
+#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT                       0x6
+#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
+#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK                         0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK                         0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
+//BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT                            0x0
+#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT                                0x3
+#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT                                0x6
+#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT                             0x8
+#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK                              0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK                                  0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK                                  0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK                               0xFF00L
+//BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
+#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT                       0x3
+#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT                       0x6
+#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
+#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK                         0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK                         0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
+//BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT                            0x0
+#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT                                0x3
+#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT                                0x6
+#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT                             0x8
+#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK                              0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK                                  0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK                                  0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK                               0xFF00L
+//BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
+#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT                       0x3
+#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT                       0x6
+#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
+#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK                         0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK                         0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
+//BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT                            0x0
+#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT                                0x3
+#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT                                0x6
+#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT                             0x8
+#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK                              0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK                                  0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK                                  0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK                               0xFF00L
+//BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
+#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT                       0x3
+#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT                       0x6
+#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
+#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK                         0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK                         0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
+//BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT                            0x0
+#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT                                0x3
+#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT                                0x6
+#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT                             0x8
+#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK                              0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK                                  0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK                                  0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK                               0xFF00L
+//BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT                   0x0
+#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT                       0x3
+#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT                       0x6
+#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT                    0x8
+#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK                     0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK                         0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK                         0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK                      0xFF00L
+//BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT                          0x0
+#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT                              0x3
+#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT                              0x6
+#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT                           0x8
+#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK                            0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK                                0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK                                0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK                             0xFF00L
+//BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT                 0x0
+#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT                     0x3
+#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT                     0x6
+#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT                  0x8
+#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK                   0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK                       0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK                       0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK                    0xFF00L
+//BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT                          0x0
+#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT                              0x3
+#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT                              0x6
+#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT                           0x8
+#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK                            0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK                                0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK                                0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK                             0xFF00L
+//BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT                 0x0
+#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT                     0x3
+#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT                     0x6
+#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT                  0x8
+#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK                   0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK                       0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK                       0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK                    0xFF00L
+//BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT                          0x0
+#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT                              0x3
+#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT                              0x6
+#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT                           0x8
+#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK                            0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK                                0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK                                0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK                             0xFF00L
+//BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT                 0x0
+#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT                     0x3
+#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT                     0x6
+#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT                  0x8
+#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK                   0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK                       0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK                       0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK                    0xFF00L
+//BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT                          0x0
+#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT                              0x3
+#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT                              0x6
+#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT                           0x8
+#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK                            0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK                                0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK                                0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK                             0xFF00L
+//BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT                 0x0
+#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT                     0x3
+#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT                     0x6
+#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT                  0x8
+#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK                   0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK                       0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK                       0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK                    0xFF00L
+//BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT                          0x0
+#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT                              0x3
+#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT                              0x6
+#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT                           0x8
+#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK                            0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK                                0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK                                0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK                             0xFF00L
+//BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT                 0x0
+#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT                     0x3
+#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT                     0x6
+#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT                  0x8
+#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK                   0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK                       0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK                       0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK                    0xFF00L
+//BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT                          0x0
+#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT                              0x3
+#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT                              0x6
+#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT                           0x8
+#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK                            0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK                                0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK                                0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK                             0xFF00L
+//BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT                 0x0
+#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT                     0x3
+#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT                     0x6
+#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT                  0x8
+#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK                   0x0007L
+#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK                       0x0038L
+#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK                       0x0040L
+#define BIF_CFG_DEV0_RC0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK                    0xFF00L
+//BIF_CFG_DEV0_RC0_PCIE_NULL1_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC0_PCIE_NULL1_ENH_CAP_LIST__CAP_ID__SHIFT                                               0x0
+#define BIF_CFG_DEV0_RC0_PCIE_NULL1_ENH_CAP_LIST__CAP_VER__SHIFT                                              0x10
+#define BIF_CFG_DEV0_RC0_PCIE_NULL1_ENH_CAP_LIST__NEXT_PTR__SHIFT                                             0x14
+#define BIF_CFG_DEV0_RC0_PCIE_NULL1_ENH_CAP_LIST__CAP_ID_MASK                                                 0x0000FFFFL
+#define BIF_CFG_DEV0_RC0_PCIE_NULL1_ENH_CAP_LIST__CAP_VER_MASK                                                0x000F0000L
+#define BIF_CFG_DEV0_RC0_PCIE_NULL1_ENH_CAP_LIST__NEXT_PTR_MASK                                               0xFFF00000L
+//BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT                                                 0x10
+#define BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                0x14
+#define BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK                                                    0x0000FFFFL
+#define BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK                                                   0x000F0000L
+#define BIF_CFG_DEV0_RC0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK                                                  0xFFF00000L
+//BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1
+#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT                                           0x0
+#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT                              0x4
+#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT                                                0x8
+#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT                              0xa
+#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK                                             0x00000007L
+#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK                                0x00000070L
+#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK                                                  0x00000300L
+#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK                                0x00000C00L
+//BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2
+#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT                                             0x0
+#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT                                    0x18
+#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK                                               0x000000FFL
+#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK                                      0xFF000000L
+//BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL
+#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT                                          0x0
+#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT                                              0x1
+#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK                                            0x0001L
+#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK                                                0x000EL
+//BIF_CFG_DEV0_RC0_PCIE_PORT_VC_STATUS
+#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT                                      0x0
+#define BIF_CFG_DEV0_RC0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK                                        0x0001L
+//BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                           0x0
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                     0xf
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                         0x10
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                                  0x18
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK                                             0x000000FFL
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                       0x00008000L
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                           0x007F0000L
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                    0xFF000000L
+//BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                         0x0
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                       0x1
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                   0x10
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                       0x11
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT                                                 0x18
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT                                             0x1f
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                           0x00000001L
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                         0x000000FEL
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                     0x00010000L
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                         0x000E0000L
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK                                                   0x07000000L
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK                                               0x80000000L
+//BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                               0x0
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                              0x1
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                                 0x0001L
+#define BIF_CFG_DEV0_RC0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                                0x0002L
+//BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                           0x0
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                     0xf
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                         0x10
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                                  0x18
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK                                             0x000000FFL
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                       0x00008000L
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                           0x003F0000L
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                    0xFF000000L
+//BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                         0x0
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                       0x1
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                   0x10
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                       0x11
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT                                                 0x18
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT                                             0x1f
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                           0x00000001L
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                         0x000000FEL
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                     0x00010000L
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                         0x000E0000L
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK                                                   0x07000000L
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK                                               0x80000000L
+//BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                               0x0
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                              0x1
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                                 0x0001L
+#define BIF_CFG_DEV0_RC0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                                0x0002L
+//BIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT                                                0x10
+#define BIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT                                               0x14
+#define BIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK                                                   0x0000FFFFL
+#define BIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK                                                  0x000F0000L
+#define BIF_CFG_DEV0_RC0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK                                                 0xFFF00000L
+//BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP
+#define BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT                                    0x0
+#define BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT                                    0x1f
+#define BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK                                      0x007FFFFFL
+#define BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK                                      0x80000000L
+//BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS
+#define BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT                                0x0
+#define BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT                          0x1f
+#define BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK                                  0x007FFFFFL
+#define BIF_CFG_DEV0_RC0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK                            0x80000000L
+//BIF_CFG_DEV0_RC0_PCIE_NULL2_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC0_PCIE_NULL2_ENH_CAP_LIST__CAP_ID__SHIFT                                               0x0
+#define BIF_CFG_DEV0_RC0_PCIE_NULL2_ENH_CAP_LIST__CAP_VER__SHIFT                                              0x10
+#define BIF_CFG_DEV0_RC0_PCIE_NULL2_ENH_CAP_LIST__NEXT_PTR__SHIFT                                             0x14
+#define BIF_CFG_DEV0_RC0_PCIE_NULL2_ENH_CAP_LIST__CAP_ID_MASK                                                 0x0000FFFFL
+#define BIF_CFG_DEV0_RC0_PCIE_NULL2_ENH_CAP_LIST__CAP_VER_MASK                                                0x000F0000L
+#define BIF_CFG_DEV0_RC0_PCIE_NULL2_ENH_CAP_LIST__NEXT_PTR_MASK                                               0xFFF00000L
+//BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
+#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
+#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
+#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
+#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
+#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
+//BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                        0x4
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                     0x5
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                        0xc
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                         0xd
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                    0xe
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                                  0xf
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                      0x10
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                       0x11
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                        0x12
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                       0x13
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                                 0x14
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                                  0x15
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                                 0x16
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                                 0x17
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                        0x18
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                         0x19
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                    0x1a
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__DMWR_REQUEST_EGRESS_BLOCKED_STATUS__SHIFT                    0x1b
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__IDE_CHECK_FAILED_STATUS__SHIFT                               0x1c
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__MISROUTED_IDE_TLP_STATUS__SHIFT                              0x1d
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__PCRC_CHECK_FAILED_STATUS__SHIFT                              0x1e
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                          0x00000010L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                       0x00000020L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                          0x00001000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                           0x00002000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                      0x00004000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                    0x00008000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                        0x00010000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                         0x00020000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                          0x00040000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                         0x00080000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                   0x00100000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                    0x00200000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                   0x00400000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                   0x00800000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                          0x01000000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                           0x02000000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                      0x04000000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__DMWR_REQUEST_EGRESS_BLOCKED_STATUS_MASK                      0x08000000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__IDE_CHECK_FAILED_STATUS_MASK                                 0x10000000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__MISROUTED_IDE_TLP_STATUS_MASK                                0x20000000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_STATUS__PCRC_CHECK_FAILED_STATUS_MASK                                0x40000000L
+//BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                            0x4
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                         0x5
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                            0xc
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                             0xd
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                        0xe
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                      0xf
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                          0x10
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                           0x11
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                            0x12
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                           0x13
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                     0x14
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                      0x15
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                     0x16
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                     0x17
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                            0x18
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                             0x19
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                        0x1a
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__DMWR_REQUEST_EGRESS_BLOCKED_MASK__SHIFT                        0x1b
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__IDE_CHECK_FAILED_MASK__SHIFT                                   0x1c
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__MISROUTED_IDE_TLP_MASK__SHIFT                                  0x1d
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__PCRC_CHECK_FAILED_MASK__SHIFT                                  0x1e
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                              0x00000010L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                           0x00000020L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                              0x00001000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                               0x00002000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                          0x00004000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                        0x00008000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                            0x00010000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                             0x00020000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                              0x00040000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                             0x00080000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                       0x00100000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                        0x00200000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                       0x00400000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                       0x00800000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                              0x01000000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                               0x02000000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                          0x04000000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__DMWR_REQUEST_EGRESS_BLOCKED_MASK_MASK                          0x08000000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__IDE_CHECK_FAILED_MASK_MASK                                     0x10000000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__MISROUTED_IDE_TLP_MASK_MASK                                    0x20000000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_MASK__PCRC_CHECK_FAILED_MASK_MASK                                    0x40000000L
+//BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                    0x4
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                                 0x5
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                    0xc
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                     0xd
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                                0xe
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                              0xf
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                                  0x10
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                   0x11
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                    0x12
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                   0x13
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                             0x14
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                              0x15
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                             0x16
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                             0x17
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                    0x18
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                     0x19
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT                0x1a
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__DMWR_REQUEST_EGRESS_BLOCKED_SEVERITY__SHIFT                0x1b
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__IDE_CHECK_FAILED_SEVERITY__SHIFT                           0x1c
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__MISROUTED_IDE_TLP_SEVERITY__SHIFT                          0x1d
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__PCRC_CHECK_FAILED_SEVERITY__SHIFT                          0x1e
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                      0x00000010L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                   0x00000020L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                      0x00001000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                       0x00002000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                                  0x00004000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                                0x00008000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                    0x00010000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                     0x00020000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                      0x00040000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                     0x00080000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                               0x00100000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                                0x00200000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                               0x00400000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                               0x00800000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                      0x01000000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                       0x02000000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK                  0x04000000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__DMWR_REQUEST_EGRESS_BLOCKED_SEVERITY_MASK                  0x08000000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__IDE_CHECK_FAILED_SEVERITY_MASK                             0x10000000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__MISROUTED_IDE_TLP_SEVERITY_MASK                            0x20000000L
+#define BIF_CFG_DEV0_RC0_PCIE_UNCORR_ERR_SEVERITY__PCRC_CHECK_FAILED_SEVERITY_MASK                            0x40000000L
+//BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                          0x0
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                          0x6
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                         0x7
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                              0x8
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                             0xc
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                            0xd
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                     0xe
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                                     0xf
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                            0x00000001L
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                            0x00000040L
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                           0x00000080L
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                                0x00000100L
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                               0x00001000L
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                              0x00002000L
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                       0x00004000L
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                       0x00008000L
+//BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                              0x0
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                              0x6
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                             0x7
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                                  0x8
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                                 0xc
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                                0xd
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                         0xe
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                         0xf
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                                0x00000001L
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                                0x00000040L
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                               0x00000080L
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                    0x00000100L
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                   0x00001000L
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                                  0x00002000L
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                           0x00004000L
+#define BIF_CFG_DEV0_RC0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                           0x00008000L
+//BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                          0x0
+#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT                                           0x5
+#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT                                            0x6
+#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                         0x7
+#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                          0x8
+#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                     0x9
+#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                      0xa
+#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                                 0xb
+#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT                         0xc
+#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__HEADER_LOG_SIZE__SHIFT                                        0xd
+#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_WAS_FLIT_MODE__SHIFT                               0x12
+#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_SIZE__SHIFT                                        0x13
+#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                            0x0000001FL
+#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK                                             0x00000020L
+#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK                                              0x00000040L
+#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                           0x00000080L
+#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                            0x00000100L
+#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                       0x00000200L
+#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                        0x00000400L
+#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                                   0x00000800L
+#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK                           0x00001000L
+#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__HEADER_LOG_SIZE_MASK                                          0x0003E000L
+#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_WAS_FLIT_MODE_MASK                                 0x00040000L
+#define BIF_CFG_DEV0_RC0_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_SIZE_MASK                                          0x00F80000L
+//BIF_CFG_DEV0_RC0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG0__TLP_HDR_MASK                                                          0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG1__TLP_HDR_MASK                                                          0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG2__TLP_HDR_MASK                                                          0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG3__TLP_HDR_MASK                                                          0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD
+#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT                                            0x0
+#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT                                        0x1
+#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT                                           0x2
+#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK                                              0x00000001L
+#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK                                          0x00000002L
+#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK                                             0x00000004L
+//BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS
+#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT                                           0x0
+#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT                                      0x1
+#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT                                 0x2
+#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT                            0x3
+#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT                               0x4
+#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT                                 0x5
+#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT                                    0x6
+#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ERR_COR_SUBCLASS__SHIFT                                        0x7
+#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT                                     0x1b
+#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK                                             0x00000001L
+#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK                                        0x00000002L
+#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK                                   0x00000004L
+#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK                              0x00000008L
+#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK                                 0x00000010L
+#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK                                   0x00000020L
+#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK                                      0x00000040L
+#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ERR_COR_SUBCLASS_MASK                                          0x00000180L
+#define BIF_CFG_DEV0_RC0_PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK                                       0xF8000000L
+//BIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID
+#define BIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT                                    0x10
+#define BIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_RC0_PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK                                      0xFFFF0000L
+//BIF_CFG_DEV0_RC0_PCIE_HDR_LOG4
+#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG4__TLP_HDR__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG4__TLP_HDR_MASK                                                          0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                              0x0
+#define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                                0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_PCIE_HDR_LOG5
+#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG5__TLP_HDR__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG5__TLP_HDR_MASK                                                          0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                              0x0
+#define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                                0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_PCIE_HDR_LOG6
+#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG6__TLP_HDR__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG6__TLP_HDR_MASK                                                          0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                              0x0
+#define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                                0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_PCIE_HDR_LOG7
+#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG7__TLP_HDR__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG7__TLP_HDR_MASK                                                          0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                              0x0
+#define BIF_CFG_DEV0_RC0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                                0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_PCIE_HDR_LOG8
+#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG8__TLP_HDR__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG8__TLP_HDR_MASK                                                          0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_PCIE_HDR_LOG9
+#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG9__TLP_HDR__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG9__TLP_HDR_MASK                                                          0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_PCIE_HDR_LOG10
+#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG10__TLP_HDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG10__TLP_HDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_PCIE_HDR_LOG11
+#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG11__TLP_HDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG11__TLP_HDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_PCIE_HDR_LOG12
+#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG12__TLP_HDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG12__TLP_HDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_PCIE_HDR_LOG13
+#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG13__TLP_HDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_RC0_PCIE_HDR_LOG13__TLP_HDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT                                      0x0
+#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT                                     0x10
+#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT                                    0x14
+#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK                                        0x0000FFFFL
+#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK                                       0x000F0000L
+#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK                                      0xFFF00000L
+//BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW1
+#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT                                     0x0
+#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW2
+#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT                                     0x0
+#define BIF_CFG_DEV0_RC0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                                0x10
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                               0x14
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                   0x0000FFFFL
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                                  0x000F0000L
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                                 0xFFF00000L
+//BIF_CFG_DEV0_RC0_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                               0x0
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                            0x1
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                            0x2
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                         0x3
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                             0x4
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                              0x5
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                           0x6
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__ENHANCED_CAPABILITY__SHIFT                                             0x7
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                      0x8
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                                 0x0001L
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                              0x0002L
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                              0x0004L
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                           0x0008L
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                               0x0010L
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                                0x0020L
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                             0x0040L
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__ENHANCED_CAPABILITY_MASK                                               0x0080L
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                        0xFF00L
+//BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                           0x0
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                        0x1
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                        0x2
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                     0x3
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                         0x4
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                          0x5
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                       0x6
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN__SHIFT                                         0x7
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL__SHIFT                                  0x8
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL__SHIFT                                  0xa
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL__SHIFT                                0xc
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                             0x0001L
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                          0x0002L
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                          0x0004L
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                       0x0008L
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                           0x0010L
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                            0x0020L
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                         0x0040L
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN_MASK                                           0x0080L
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL_MASK                                    0x0300L
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL_MASK                                    0x0C00L
+#define BIF_CFG_DEV0_RC0_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL_MASK                                  0x1000L
+//BIF_CFG_DEV0_RC0_PCIE_RTR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_RC0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT                                                0x10
+#define BIF_CFG_DEV0_RC0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                               0x14
+#define BIF_CFG_DEV0_RC0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK                                                   0x0000FFFFL
+#define BIF_CFG_DEV0_RC0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK                                                  0x000F0000L
+#define BIF_CFG_DEV0_RC0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK                                                 0xFFF00000L
+//BIF_CFG_DEV0_RC0_RTR_DATA1
+#define BIF_CFG_DEV0_RC0_RTR_DATA1__RESET_TIME__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_RC0_RTR_DATA1__DLUP_TIME__SHIFT                                                          0xc
+#define BIF_CFG_DEV0_RC0_RTR_DATA1__RTR_VALID__SHIFT                                                          0x1f
+#define BIF_CFG_DEV0_RC0_RTR_DATA1__RESET_TIME_MASK                                                           0x00000FFFL
+#define BIF_CFG_DEV0_RC0_RTR_DATA1__DLUP_TIME_MASK                                                            0x00FFF000L
+#define BIF_CFG_DEV0_RC0_RTR_DATA1__RTR_VALID_MASK                                                            0x80000000L
+//BIF_CFG_DEV0_RC0_RTR_DATA2
+#define BIF_CFG_DEV0_RC0_RTR_DATA2__FLR_TIME__SHIFT                                                           0x0
+#define BIF_CFG_DEV0_RC0_RTR_DATA2__D3HOTD0_TIME__SHIFT                                                       0xc
+#define BIF_CFG_DEV0_RC0_RTR_DATA2__FLR_TIME_MASK                                                             0x00000FFFL
+#define BIF_CFG_DEV0_RC0_RTR_DATA2__D3HOTD0_TIME_MASK                                                         0x00FFF000L
+//BIF_CFG_DEV0_RC0_IDE_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC0_IDE_ENH_CAP_LIST__CAP_ID__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_RC0_IDE_ENH_CAP_LIST__CAP_VER__SHIFT                                                     0x10
+#define BIF_CFG_DEV0_RC0_IDE_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                    0x14
+#define BIF_CFG_DEV0_RC0_IDE_ENH_CAP_LIST__CAP_ID_MASK                                                        0x0000FFFFL
+#define BIF_CFG_DEV0_RC0_IDE_ENH_CAP_LIST__CAP_VER_MASK                                                       0x000F0000L
+#define BIF_CFG_DEV0_RC0_IDE_ENH_CAP_LIST__NEXT_PTR_MASK                                                      0xFFF00000L
+//BIF_CFG_DEV0_RC0_IDE_CAP
+#define BIF_CFG_DEV0_RC0_IDE_CAP__IDE_CAP_LINK_IDE_STREAM_SUPPORTED__SHIFT                                    0x0
+#define BIF_CFG_DEV0_RC0_IDE_CAP__IDE_CAP_SELECTIVE_IDE_STREAM_SUPPORTED__SHIFT                               0x1
+#define BIF_CFG_DEV0_RC0_IDE_CAP__IDE_CAP_FLOW_THROUGH_IDE_STREAM_SUPPORTED__SHIFT                            0x2
+#define BIF_CFG_DEV0_RC0_IDE_CAP__IDE_CAP_PARTIAL_HDR_ENCRYPTION_SUPPORTED__SHIFT                             0x3
+#define BIF_CFG_DEV0_RC0_IDE_CAP__IDE_CAP_AGGREGATION_SUPPORTED__SHIFT                                        0x4
+#define BIF_CFG_DEV0_RC0_IDE_CAP__IDE_CAP_PCRC_SUPPORTED__SHIFT                                               0x5
+#define BIF_CFG_DEV0_RC0_IDE_CAP__IDE_CAP_IDE_KM_PROTOCOL_SUPPORTED__SHIFT                                    0x6
+#define BIF_CFG_DEV0_RC0_IDE_CAP__IDE_CAP_SELECTIVE_IDE_FOR_CFG_REQ_SUPPORTED__SHIFT                          0x7
+#define BIF_CFG_DEV0_RC0_IDE_CAP__IDE_CAP_SUPPORTED_ALGORITHMS__SHIFT                                         0x8
+#define BIF_CFG_DEV0_RC0_IDE_CAP__IDE_CAP_NUM_OF_TCS_SUPPORTED_FOR_LINK_IDE__SHIFT                            0xd
+#define BIF_CFG_DEV0_RC0_IDE_CAP__IDE_CAP_NUM_OF_SELECTIVE_IDE_STREAMS_SUPPORTED__SHIFT                       0x10
+#define BIF_CFG_DEV0_RC0_IDE_CAP__IDE_CAP_TEE_LIMITED_SUPPORTED__SHIFT                                        0x18
+#define BIF_CFG_DEV0_RC0_IDE_CAP__IDE_CAP_XT_SUPPORTED__SHIFT                                                 0x19
+#define BIF_CFG_DEV0_RC0_IDE_CAP__IDE_CAP_LINK_IDE_STREAM_SUPPORTED_MASK                                      0x00000001L
+#define BIF_CFG_DEV0_RC0_IDE_CAP__IDE_CAP_SELECTIVE_IDE_STREAM_SUPPORTED_MASK                                 0x00000002L
+#define BIF_CFG_DEV0_RC0_IDE_CAP__IDE_CAP_FLOW_THROUGH_IDE_STREAM_SUPPORTED_MASK                              0x00000004L
+#define BIF_CFG_DEV0_RC0_IDE_CAP__IDE_CAP_PARTIAL_HDR_ENCRYPTION_SUPPORTED_MASK                               0x00000008L
+#define BIF_CFG_DEV0_RC0_IDE_CAP__IDE_CAP_AGGREGATION_SUPPORTED_MASK                                          0x00000010L
+#define BIF_CFG_DEV0_RC0_IDE_CAP__IDE_CAP_PCRC_SUPPORTED_MASK                                                 0x00000020L
+#define BIF_CFG_DEV0_RC0_IDE_CAP__IDE_CAP_IDE_KM_PROTOCOL_SUPPORTED_MASK                                      0x00000040L
+#define BIF_CFG_DEV0_RC0_IDE_CAP__IDE_CAP_SELECTIVE_IDE_FOR_CFG_REQ_SUPPORTED_MASK                            0x00000080L
+#define BIF_CFG_DEV0_RC0_IDE_CAP__IDE_CAP_SUPPORTED_ALGORITHMS_MASK                                           0x00001F00L
+#define BIF_CFG_DEV0_RC0_IDE_CAP__IDE_CAP_NUM_OF_TCS_SUPPORTED_FOR_LINK_IDE_MASK                              0x0000E000L
+#define BIF_CFG_DEV0_RC0_IDE_CAP__IDE_CAP_NUM_OF_SELECTIVE_IDE_STREAMS_SUPPORTED_MASK                         0x00FF0000L
+#define BIF_CFG_DEV0_RC0_IDE_CAP__IDE_CAP_TEE_LIMITED_SUPPORTED_MASK                                          0x01000000L
+#define BIF_CFG_DEV0_RC0_IDE_CAP__IDE_CAP_XT_SUPPORTED_MASK                                                   0x02000000L
+//BIF_CFG_DEV0_RC0_IDE_CNTL
+#define BIF_CFG_DEV0_RC0_IDE_CNTL__IDE_CNTL_FLOW_THROUGH_IDE_STREAM_ENABLED__SHIFT                            0x2
+#define BIF_CFG_DEV0_RC0_IDE_CNTL__IDE_CNTL_FLOW_THROUGH_IDE_STREAM_ENABLED_MASK                              0x00000004L
+//BIF_CFG_DEV0_RC0_LINK_IDE_STREAM_0_CNTL
+#define BIF_CFG_DEV0_RC0_LINK_IDE_STREAM_0_CNTL__LINK_IDE_STREAM_ENABLE__SHIFT                                0x0
+#define BIF_CFG_DEV0_RC0_LINK_IDE_STREAM_0_CNTL__XT_ENABLE__SHIFT                                             0x1
+#define BIF_CFG_DEV0_RC0_LINK_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT                               0x2
+#define BIF_CFG_DEV0_RC0_LINK_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_PR__SHIFT                                0x4
+#define BIF_CFG_DEV0_RC0_LINK_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT                               0x6
+#define BIF_CFG_DEV0_RC0_LINK_IDE_STREAM_0_CNTL__PCRC_ENABLE__SHIFT                                           0x8
+#define BIF_CFG_DEV0_RC0_LINK_IDE_STREAM_0_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT                              0xa
+#define BIF_CFG_DEV0_RC0_LINK_IDE_STREAM_0_CNTL__SELECTED_ALGORITHM__SHIFT                                    0xe
+#define BIF_CFG_DEV0_RC0_LINK_IDE_STREAM_0_CNTL__TC__SHIFT                                                    0x13
+#define BIF_CFG_DEV0_RC0_LINK_IDE_STREAM_0_CNTL__STREAM_ID__SHIFT                                             0x18
+#define BIF_CFG_DEV0_RC0_LINK_IDE_STREAM_0_CNTL__LINK_IDE_STREAM_ENABLE_MASK                                  0x00000001L
+#define BIF_CFG_DEV0_RC0_LINK_IDE_STREAM_0_CNTL__XT_ENABLE_MASK                                               0x00000002L
+#define BIF_CFG_DEV0_RC0_LINK_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_NPR_MASK                                 0x0000000CL
+#define BIF_CFG_DEV0_RC0_LINK_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_PR_MASK                                  0x00000030L
+#define BIF_CFG_DEV0_RC0_LINK_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_CPL_MASK                                 0x000000C0L
+#define BIF_CFG_DEV0_RC0_LINK_IDE_STREAM_0_CNTL__PCRC_ENABLE_MASK                                             0x00000100L
+#define BIF_CFG_DEV0_RC0_LINK_IDE_STREAM_0_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK                                0x00003C00L
+#define BIF_CFG_DEV0_RC0_LINK_IDE_STREAM_0_CNTL__SELECTED_ALGORITHM_MASK                                      0x0007C000L
+#define BIF_CFG_DEV0_RC0_LINK_IDE_STREAM_0_CNTL__TC_MASK                                                      0x00380000L
+#define BIF_CFG_DEV0_RC0_LINK_IDE_STREAM_0_CNTL__STREAM_ID_MASK                                               0xFF000000L
+//BIF_CFG_DEV0_RC0_LINK_IDE_STREAM_0_STATUS
+#define BIF_CFG_DEV0_RC0_LINK_IDE_STREAM_0_STATUS__LINK_IDE_STREAM_STATE__SHIFT                               0x0
+#define BIF_CFG_DEV0_RC0_LINK_IDE_STREAM_0_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT                               0x1f
+#define BIF_CFG_DEV0_RC0_LINK_IDE_STREAM_0_STATUS__LINK_IDE_STREAM_STATE_MASK                                 0x0000000FL
+#define BIF_CFG_DEV0_RC0_LINK_IDE_STREAM_0_STATUS__RECEIVED_IDE_FAIL_MSG_MASK                                 0x80000000L
+//BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CAP
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT                     0x0
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK                       0x0000000FL
+//BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CNTL
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT                      0x0
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CNTL__XT_ENABLE__SHIFT                                        0x1
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT                          0x2
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_PR__SHIFT                           0x4
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT                          0x6
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CNTL__PCRC_ENABLE__SHIFT                                      0x8
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT                     0x9
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT                         0xa
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CNTL__SELECTED_ALGORITHM__SHIFT                               0xe
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CNTL__TC__SHIFT                                               0x13
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CNTL__DEFAULT_STREAM__SHIFT                                   0x16
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CNTL__TEE_LIMITED_STREAM__SHIFT                               0x17
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CNTL__STREAM_ID__SHIFT                                        0x18
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK                        0x00000001L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CNTL__XT_ENABLE_MASK                                          0x00000002L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_NPR_MASK                            0x0000000CL
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_PR_MASK                             0x00000030L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_CPL_MASK                            0x000000C0L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CNTL__PCRC_ENABLE_MASK                                        0x00000100L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK                       0x00000200L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK                           0x00003C00L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CNTL__SELECTED_ALGORITHM_MASK                                 0x0007C000L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CNTL__TC_MASK                                                 0x00380000L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CNTL__DEFAULT_STREAM_MASK                                     0x00400000L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CNTL__TEE_LIMITED_STREAM_MASK                                 0x00800000L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_CNTL__STREAM_ID_MASK                                          0xFF000000L
+//BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_STATUS
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT                     0x0
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT                          0x1f
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK                       0x0000000FL
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_0_STATUS__RECEIVED_IDE_FAIL_MSG_MASK                            0x80000000L
+//BIF_CFG_DEV0_RC0_IDE_0_RID_ASSOCIATION_REG1
+#define BIF_CFG_DEV0_RC0_IDE_0_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT                                         0x8
+#define BIF_CFG_DEV0_RC0_IDE_0_RID_ASSOCIATION_REG1__RID_LIMIT_MASK                                           0x00FFFF00L
+//BIF_CFG_DEV0_RC0_IDE_0_RID_ASSOCIATION_REG2
+#define BIF_CFG_DEV0_RC0_IDE_0_RID_ASSOCIATION_REG2__VALID__SHIFT                                             0x0
+#define BIF_CFG_DEV0_RC0_IDE_0_RID_ASSOCIATION_REG2__RID_BASE__SHIFT                                          0x8
+#define BIF_CFG_DEV0_RC0_IDE_0_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT                                      0x18
+#define BIF_CFG_DEV0_RC0_IDE_0_RID_ASSOCIATION_REG2__VALID_MASK                                               0x00000001L
+#define BIF_CFG_DEV0_RC0_IDE_0_RID_ASSOCIATION_REG2__RID_BASE_MASK                                            0x00FFFF00L
+#define BIF_CFG_DEV0_RC0_IDE_0_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK                                        0xFF000000L
+//BIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_0_REG1
+#define BIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT                                 0x8
+#define BIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT                                0x14
+#define BIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_0_REG1__VALID_MASK                                            0x00000001L
+#define BIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK                                   0x000FFF00L
+#define BIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK                                  0xFFF00000L
+//BIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_0_REG2
+#define BIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT                                0x0
+#define BIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK                                  0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_0_REG3
+#define BIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT                                 0x0
+#define BIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK                                   0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_1_REG1
+#define BIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT                                 0x8
+#define BIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT                                0x14
+#define BIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_1_REG1__VALID_MASK                                            0x00000001L
+#define BIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK                                   0x000FFF00L
+#define BIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK                                  0xFFF00000L
+//BIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_1_REG2
+#define BIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT                                0x0
+#define BIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK                                  0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_1_REG3
+#define BIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT                                 0x0
+#define BIF_CFG_DEV0_RC0_IDE_0_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK                                   0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CAP
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT                     0x0
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK                       0x0000000FL
+//BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CNTL
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT                      0x0
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CNTL__XT_ENABLE__SHIFT                                        0x1
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT                          0x2
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CNTL__TX_AGGREGATION_MODE_PR__SHIFT                           0x4
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT                          0x6
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CNTL__PCRC_ENABLE__SHIFT                                      0x8
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT                     0x9
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT                         0xa
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CNTL__SELECTED_ALGORITHM__SHIFT                               0xe
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CNTL__TC__SHIFT                                               0x13
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CNTL__DEFAULT_STREAM__SHIFT                                   0x16
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CNTL__TEE_LIMITED_STREAM__SHIFT                               0x17
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CNTL__STREAM_ID__SHIFT                                        0x18
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK                        0x00000001L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CNTL__XT_ENABLE_MASK                                          0x00000002L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CNTL__TX_AGGREGATION_MODE_NPR_MASK                            0x0000000CL
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CNTL__TX_AGGREGATION_MODE_PR_MASK                             0x00000030L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CNTL__TX_AGGREGATION_MODE_CPL_MASK                            0x000000C0L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CNTL__PCRC_ENABLE_MASK                                        0x00000100L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK                       0x00000200L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK                           0x00003C00L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CNTL__SELECTED_ALGORITHM_MASK                                 0x0007C000L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CNTL__TC_MASK                                                 0x00380000L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CNTL__DEFAULT_STREAM_MASK                                     0x00400000L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CNTL__TEE_LIMITED_STREAM_MASK                                 0x00800000L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_CNTL__STREAM_ID_MASK                                          0xFF000000L
+//BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_STATUS
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT                     0x0
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT                          0x1f
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK                       0x0000000FL
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_1_STATUS__RECEIVED_IDE_FAIL_MSG_MASK                            0x80000000L
+//BIF_CFG_DEV0_RC0_IDE_1_RID_ASSOCIATION_REG1
+#define BIF_CFG_DEV0_RC0_IDE_1_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT                                         0x8
+#define BIF_CFG_DEV0_RC0_IDE_1_RID_ASSOCIATION_REG1__RID_LIMIT_MASK                                           0x00FFFF00L
+//BIF_CFG_DEV0_RC0_IDE_1_RID_ASSOCIATION_REG2
+#define BIF_CFG_DEV0_RC0_IDE_1_RID_ASSOCIATION_REG2__VALID__SHIFT                                             0x0
+#define BIF_CFG_DEV0_RC0_IDE_1_RID_ASSOCIATION_REG2__RID_BASE__SHIFT                                          0x8
+#define BIF_CFG_DEV0_RC0_IDE_1_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT                                      0x18
+#define BIF_CFG_DEV0_RC0_IDE_1_RID_ASSOCIATION_REG2__VALID_MASK                                               0x00000001L
+#define BIF_CFG_DEV0_RC0_IDE_1_RID_ASSOCIATION_REG2__RID_BASE_MASK                                            0x00FFFF00L
+#define BIF_CFG_DEV0_RC0_IDE_1_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK                                        0xFF000000L
+//BIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_0_REG1
+#define BIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT                                 0x8
+#define BIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT                                0x14
+#define BIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_0_REG1__VALID_MASK                                            0x00000001L
+#define BIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK                                   0x000FFF00L
+#define BIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK                                  0xFFF00000L
+//BIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_0_REG2
+#define BIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT                                0x0
+#define BIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK                                  0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_0_REG3
+#define BIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT                                 0x0
+#define BIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK                                   0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_1_REG1
+#define BIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT                                 0x8
+#define BIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT                                0x14
+#define BIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_1_REG1__VALID_MASK                                            0x00000001L
+#define BIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK                                   0x000FFF00L
+#define BIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK                                  0xFFF00000L
+//BIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_1_REG2
+#define BIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT                                0x0
+#define BIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK                                  0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_1_REG3
+#define BIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT                                 0x0
+#define BIF_CFG_DEV0_RC0_IDE_1_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK                                   0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CAP
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT                     0x0
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK                       0x0000000FL
+//BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CNTL
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT                      0x0
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CNTL__XT_ENABLE__SHIFT                                        0x1
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT                          0x2
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CNTL__TX_AGGREGATION_MODE_PR__SHIFT                           0x4
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT                          0x6
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CNTL__PCRC_ENABLE__SHIFT                                      0x8
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT                     0x9
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT                         0xa
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CNTL__SELECTED_ALGORITHM__SHIFT                               0xe
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CNTL__TC__SHIFT                                               0x13
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CNTL__DEFAULT_STREAM__SHIFT                                   0x16
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CNTL__TEE_LIMITED_STREAM__SHIFT                               0x17
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CNTL__STREAM_ID__SHIFT                                        0x18
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK                        0x00000001L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CNTL__XT_ENABLE_MASK                                          0x00000002L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CNTL__TX_AGGREGATION_MODE_NPR_MASK                            0x0000000CL
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CNTL__TX_AGGREGATION_MODE_PR_MASK                             0x00000030L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CNTL__TX_AGGREGATION_MODE_CPL_MASK                            0x000000C0L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CNTL__PCRC_ENABLE_MASK                                        0x00000100L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK                       0x00000200L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK                           0x00003C00L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CNTL__SELECTED_ALGORITHM_MASK                                 0x0007C000L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CNTL__TC_MASK                                                 0x00380000L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CNTL__DEFAULT_STREAM_MASK                                     0x00400000L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CNTL__TEE_LIMITED_STREAM_MASK                                 0x00800000L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_CNTL__STREAM_ID_MASK                                          0xFF000000L
+//BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_STATUS
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT                     0x0
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT                          0x1f
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK                       0x0000000FL
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_2_STATUS__RECEIVED_IDE_FAIL_MSG_MASK                            0x80000000L
+//BIF_CFG_DEV0_RC0_IDE_2_RID_ASSOCIATION_REG1
+#define BIF_CFG_DEV0_RC0_IDE_2_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT                                         0x8
+#define BIF_CFG_DEV0_RC0_IDE_2_RID_ASSOCIATION_REG1__RID_LIMIT_MASK                                           0x00FFFF00L
+//BIF_CFG_DEV0_RC0_IDE_2_RID_ASSOCIATION_REG2
+#define BIF_CFG_DEV0_RC0_IDE_2_RID_ASSOCIATION_REG2__VALID__SHIFT                                             0x0
+#define BIF_CFG_DEV0_RC0_IDE_2_RID_ASSOCIATION_REG2__RID_BASE__SHIFT                                          0x8
+#define BIF_CFG_DEV0_RC0_IDE_2_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT                                      0x18
+#define BIF_CFG_DEV0_RC0_IDE_2_RID_ASSOCIATION_REG2__VALID_MASK                                               0x00000001L
+#define BIF_CFG_DEV0_RC0_IDE_2_RID_ASSOCIATION_REG2__RID_BASE_MASK                                            0x00FFFF00L
+#define BIF_CFG_DEV0_RC0_IDE_2_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK                                        0xFF000000L
+//BIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_0_REG1
+#define BIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT                                 0x8
+#define BIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT                                0x14
+#define BIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_0_REG1__VALID_MASK                                            0x00000001L
+#define BIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK                                   0x000FFF00L
+#define BIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK                                  0xFFF00000L
+//BIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_0_REG2
+#define BIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT                                0x0
+#define BIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK                                  0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_0_REG3
+#define BIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT                                 0x0
+#define BIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK                                   0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_1_REG1
+#define BIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT                                 0x8
+#define BIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT                                0x14
+#define BIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_1_REG1__VALID_MASK                                            0x00000001L
+#define BIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK                                   0x000FFF00L
+#define BIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK                                  0xFFF00000L
+//BIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_1_REG2
+#define BIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT                                0x0
+#define BIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK                                  0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_1_REG3
+#define BIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT                                 0x0
+#define BIF_CFG_DEV0_RC0_IDE_2_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK                                   0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CAP
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT                     0x0
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK                       0x0000000FL
+//BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CNTL
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT                      0x0
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CNTL__XT_ENABLE__SHIFT                                        0x1
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT                          0x2
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CNTL__TX_AGGREGATION_MODE_PR__SHIFT                           0x4
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT                          0x6
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CNTL__PCRC_ENABLE__SHIFT                                      0x8
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT                     0x9
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT                         0xa
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CNTL__SELECTED_ALGORITHM__SHIFT                               0xe
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CNTL__TC__SHIFT                                               0x13
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CNTL__DEFAULT_STREAM__SHIFT                                   0x16
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CNTL__TEE_LIMITED_STREAM__SHIFT                               0x17
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CNTL__STREAM_ID__SHIFT                                        0x18
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK                        0x00000001L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CNTL__XT_ENABLE_MASK                                          0x00000002L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CNTL__TX_AGGREGATION_MODE_NPR_MASK                            0x0000000CL
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CNTL__TX_AGGREGATION_MODE_PR_MASK                             0x00000030L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CNTL__TX_AGGREGATION_MODE_CPL_MASK                            0x000000C0L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CNTL__PCRC_ENABLE_MASK                                        0x00000100L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK                       0x00000200L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK                           0x00003C00L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CNTL__SELECTED_ALGORITHM_MASK                                 0x0007C000L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CNTL__TC_MASK                                                 0x00380000L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CNTL__DEFAULT_STREAM_MASK                                     0x00400000L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CNTL__TEE_LIMITED_STREAM_MASK                                 0x00800000L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_CNTL__STREAM_ID_MASK                                          0xFF000000L
+//BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_STATUS
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT                     0x0
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT                          0x1f
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK                       0x0000000FL
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_3_STATUS__RECEIVED_IDE_FAIL_MSG_MASK                            0x80000000L
+//BIF_CFG_DEV0_RC0_IDE_3_RID_ASSOCIATION_REG1
+#define BIF_CFG_DEV0_RC0_IDE_3_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT                                         0x8
+#define BIF_CFG_DEV0_RC0_IDE_3_RID_ASSOCIATION_REG1__RID_LIMIT_MASK                                           0x00FFFF00L
+//BIF_CFG_DEV0_RC0_IDE_3_RID_ASSOCIATION_REG2
+#define BIF_CFG_DEV0_RC0_IDE_3_RID_ASSOCIATION_REG2__VALID__SHIFT                                             0x0
+#define BIF_CFG_DEV0_RC0_IDE_3_RID_ASSOCIATION_REG2__RID_BASE__SHIFT                                          0x8
+#define BIF_CFG_DEV0_RC0_IDE_3_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT                                      0x18
+#define BIF_CFG_DEV0_RC0_IDE_3_RID_ASSOCIATION_REG2__VALID_MASK                                               0x00000001L
+#define BIF_CFG_DEV0_RC0_IDE_3_RID_ASSOCIATION_REG2__RID_BASE_MASK                                            0x00FFFF00L
+#define BIF_CFG_DEV0_RC0_IDE_3_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK                                        0xFF000000L
+//BIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_0_REG1
+#define BIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT                                 0x8
+#define BIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT                                0x14
+#define BIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_0_REG1__VALID_MASK                                            0x00000001L
+#define BIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK                                   0x000FFF00L
+#define BIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK                                  0xFFF00000L
+//BIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_0_REG2
+#define BIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT                                0x0
+#define BIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK                                  0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_0_REG3
+#define BIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT                                 0x0
+#define BIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK                                   0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_1_REG1
+#define BIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT                                 0x8
+#define BIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT                                0x14
+#define BIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_1_REG1__VALID_MASK                                            0x00000001L
+#define BIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK                                   0x000FFF00L
+#define BIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK                                  0xFFF00000L
+//BIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_1_REG2
+#define BIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT                                0x0
+#define BIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK                                  0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_1_REG3
+#define BIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT                                 0x0
+#define BIF_CFG_DEV0_RC0_IDE_3_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK                                   0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CAP
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT                     0x0
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK                       0x0000000FL
+//BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CNTL
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT                      0x0
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CNTL__XT_ENABLE__SHIFT                                        0x1
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT                          0x2
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CNTL__TX_AGGREGATION_MODE_PR__SHIFT                           0x4
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT                          0x6
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CNTL__PCRC_ENABLE__SHIFT                                      0x8
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT                     0x9
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT                         0xa
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CNTL__SELECTED_ALGORITHM__SHIFT                               0xe
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CNTL__TC__SHIFT                                               0x13
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CNTL__DEFAULT_STREAM__SHIFT                                   0x16
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CNTL__TEE_LIMITED_STREAM__SHIFT                               0x17
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CNTL__STREAM_ID__SHIFT                                        0x18
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK                        0x00000001L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CNTL__XT_ENABLE_MASK                                          0x00000002L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CNTL__TX_AGGREGATION_MODE_NPR_MASK                            0x0000000CL
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CNTL__TX_AGGREGATION_MODE_PR_MASK                             0x00000030L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CNTL__TX_AGGREGATION_MODE_CPL_MASK                            0x000000C0L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CNTL__PCRC_ENABLE_MASK                                        0x00000100L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK                       0x00000200L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK                           0x00003C00L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CNTL__SELECTED_ALGORITHM_MASK                                 0x0007C000L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CNTL__TC_MASK                                                 0x00380000L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CNTL__DEFAULT_STREAM_MASK                                     0x00400000L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CNTL__TEE_LIMITED_STREAM_MASK                                 0x00800000L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_CNTL__STREAM_ID_MASK                                          0xFF000000L
+//BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_STATUS
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT                     0x0
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT                          0x1f
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK                       0x0000000FL
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_4_STATUS__RECEIVED_IDE_FAIL_MSG_MASK                            0x80000000L
+//BIF_CFG_DEV0_RC0_IDE_4_RID_ASSOCIATION_REG1
+#define BIF_CFG_DEV0_RC0_IDE_4_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT                                         0x8
+#define BIF_CFG_DEV0_RC0_IDE_4_RID_ASSOCIATION_REG1__RID_LIMIT_MASK                                           0x00FFFF00L
+//BIF_CFG_DEV0_RC0_IDE_4_RID_ASSOCIATION_REG2
+#define BIF_CFG_DEV0_RC0_IDE_4_RID_ASSOCIATION_REG2__VALID__SHIFT                                             0x0
+#define BIF_CFG_DEV0_RC0_IDE_4_RID_ASSOCIATION_REG2__RID_BASE__SHIFT                                          0x8
+#define BIF_CFG_DEV0_RC0_IDE_4_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT                                      0x18
+#define BIF_CFG_DEV0_RC0_IDE_4_RID_ASSOCIATION_REG2__VALID_MASK                                               0x00000001L
+#define BIF_CFG_DEV0_RC0_IDE_4_RID_ASSOCIATION_REG2__RID_BASE_MASK                                            0x00FFFF00L
+#define BIF_CFG_DEV0_RC0_IDE_4_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK                                        0xFF000000L
+//BIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_0_REG1
+#define BIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT                                 0x8
+#define BIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT                                0x14
+#define BIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_0_REG1__VALID_MASK                                            0x00000001L
+#define BIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK                                   0x000FFF00L
+#define BIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK                                  0xFFF00000L
+//BIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_0_REG2
+#define BIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT                                0x0
+#define BIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK                                  0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_0_REG3
+#define BIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT                                 0x0
+#define BIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK                                   0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_1_REG1
+#define BIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT                                 0x8
+#define BIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT                                0x14
+#define BIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_1_REG1__VALID_MASK                                            0x00000001L
+#define BIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK                                   0x000FFF00L
+#define BIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK                                  0xFFF00000L
+//BIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_1_REG2
+#define BIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT                                0x0
+#define BIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK                                  0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_1_REG3
+#define BIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT                                 0x0
+#define BIF_CFG_DEV0_RC0_IDE_4_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK                                   0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CAP
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT                     0x0
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK                       0x0000000FL
+//BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CNTL
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT                      0x0
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CNTL__XT_ENABLE__SHIFT                                        0x1
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT                          0x2
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CNTL__TX_AGGREGATION_MODE_PR__SHIFT                           0x4
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT                          0x6
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CNTL__PCRC_ENABLE__SHIFT                                      0x8
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT                     0x9
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT                         0xa
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CNTL__SELECTED_ALGORITHM__SHIFT                               0xe
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CNTL__TC__SHIFT                                               0x13
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CNTL__DEFAULT_STREAM__SHIFT                                   0x16
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CNTL__TEE_LIMITED_STREAM__SHIFT                               0x17
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CNTL__STREAM_ID__SHIFT                                        0x18
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK                        0x00000001L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CNTL__XT_ENABLE_MASK                                          0x00000002L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CNTL__TX_AGGREGATION_MODE_NPR_MASK                            0x0000000CL
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CNTL__TX_AGGREGATION_MODE_PR_MASK                             0x00000030L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CNTL__TX_AGGREGATION_MODE_CPL_MASK                            0x000000C0L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CNTL__PCRC_ENABLE_MASK                                        0x00000100L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK                       0x00000200L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK                           0x00003C00L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CNTL__SELECTED_ALGORITHM_MASK                                 0x0007C000L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CNTL__TC_MASK                                                 0x00380000L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CNTL__DEFAULT_STREAM_MASK                                     0x00400000L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CNTL__TEE_LIMITED_STREAM_MASK                                 0x00800000L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_CNTL__STREAM_ID_MASK                                          0xFF000000L
+//BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_STATUS
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT                     0x0
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT                          0x1f
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK                       0x0000000FL
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_5_STATUS__RECEIVED_IDE_FAIL_MSG_MASK                            0x80000000L
+//BIF_CFG_DEV0_RC0_IDE_5_RID_ASSOCIATION_REG1
+#define BIF_CFG_DEV0_RC0_IDE_5_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT                                         0x8
+#define BIF_CFG_DEV0_RC0_IDE_5_RID_ASSOCIATION_REG1__RID_LIMIT_MASK                                           0x00FFFF00L
+//BIF_CFG_DEV0_RC0_IDE_5_RID_ASSOCIATION_REG2
+#define BIF_CFG_DEV0_RC0_IDE_5_RID_ASSOCIATION_REG2__VALID__SHIFT                                             0x0
+#define BIF_CFG_DEV0_RC0_IDE_5_RID_ASSOCIATION_REG2__RID_BASE__SHIFT                                          0x8
+#define BIF_CFG_DEV0_RC0_IDE_5_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT                                      0x18
+#define BIF_CFG_DEV0_RC0_IDE_5_RID_ASSOCIATION_REG2__VALID_MASK                                               0x00000001L
+#define BIF_CFG_DEV0_RC0_IDE_5_RID_ASSOCIATION_REG2__RID_BASE_MASK                                            0x00FFFF00L
+#define BIF_CFG_DEV0_RC0_IDE_5_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK                                        0xFF000000L
+//BIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_0_REG1
+#define BIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT                                 0x8
+#define BIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT                                0x14
+#define BIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_0_REG1__VALID_MASK                                            0x00000001L
+#define BIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK                                   0x000FFF00L
+#define BIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK                                  0xFFF00000L
+//BIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_0_REG2
+#define BIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT                                0x0
+#define BIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK                                  0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_0_REG3
+#define BIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT                                 0x0
+#define BIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK                                   0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_1_REG1
+#define BIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT                                 0x8
+#define BIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT                                0x14
+#define BIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_1_REG1__VALID_MASK                                            0x00000001L
+#define BIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK                                   0x000FFF00L
+#define BIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK                                  0xFFF00000L
+//BIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_1_REG2
+#define BIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT                                0x0
+#define BIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK                                  0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_1_REG3
+#define BIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT                                 0x0
+#define BIF_CFG_DEV0_RC0_IDE_5_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK                                   0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CAP
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT                     0x0
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK                       0x0000000FL
+//BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CNTL
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT                      0x0
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CNTL__XT_ENABLE__SHIFT                                        0x1
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT                          0x2
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CNTL__TX_AGGREGATION_MODE_PR__SHIFT                           0x4
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT                          0x6
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CNTL__PCRC_ENABLE__SHIFT                                      0x8
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT                     0x9
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT                         0xa
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CNTL__SELECTED_ALGORITHM__SHIFT                               0xe
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CNTL__TC__SHIFT                                               0x13
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CNTL__DEFAULT_STREAM__SHIFT                                   0x16
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CNTL__TEE_LIMITED_STREAM__SHIFT                               0x17
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CNTL__STREAM_ID__SHIFT                                        0x18
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK                        0x00000001L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CNTL__XT_ENABLE_MASK                                          0x00000002L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CNTL__TX_AGGREGATION_MODE_NPR_MASK                            0x0000000CL
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CNTL__TX_AGGREGATION_MODE_PR_MASK                             0x00000030L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CNTL__TX_AGGREGATION_MODE_CPL_MASK                            0x000000C0L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CNTL__PCRC_ENABLE_MASK                                        0x00000100L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK                       0x00000200L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK                           0x00003C00L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CNTL__SELECTED_ALGORITHM_MASK                                 0x0007C000L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CNTL__TC_MASK                                                 0x00380000L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CNTL__DEFAULT_STREAM_MASK                                     0x00400000L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CNTL__TEE_LIMITED_STREAM_MASK                                 0x00800000L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_CNTL__STREAM_ID_MASK                                          0xFF000000L
+//BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_STATUS
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT                     0x0
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT                          0x1f
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK                       0x0000000FL
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_6_STATUS__RECEIVED_IDE_FAIL_MSG_MASK                            0x80000000L
+//BIF_CFG_DEV0_RC0_IDE_6_RID_ASSOCIATION_REG1
+#define BIF_CFG_DEV0_RC0_IDE_6_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT                                         0x8
+#define BIF_CFG_DEV0_RC0_IDE_6_RID_ASSOCIATION_REG1__RID_LIMIT_MASK                                           0x00FFFF00L
+//BIF_CFG_DEV0_RC0_IDE_6_RID_ASSOCIATION_REG2
+#define BIF_CFG_DEV0_RC0_IDE_6_RID_ASSOCIATION_REG2__VALID__SHIFT                                             0x0
+#define BIF_CFG_DEV0_RC0_IDE_6_RID_ASSOCIATION_REG2__RID_BASE__SHIFT                                          0x8
+#define BIF_CFG_DEV0_RC0_IDE_6_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT                                      0x18
+#define BIF_CFG_DEV0_RC0_IDE_6_RID_ASSOCIATION_REG2__VALID_MASK                                               0x00000001L
+#define BIF_CFG_DEV0_RC0_IDE_6_RID_ASSOCIATION_REG2__RID_BASE_MASK                                            0x00FFFF00L
+#define BIF_CFG_DEV0_RC0_IDE_6_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK                                        0xFF000000L
+//BIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_0_REG1
+#define BIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT                                 0x8
+#define BIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT                                0x14
+#define BIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_0_REG1__VALID_MASK                                            0x00000001L
+#define BIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK                                   0x000FFF00L
+#define BIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK                                  0xFFF00000L
+//BIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_0_REG2
+#define BIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT                                0x0
+#define BIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK                                  0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_0_REG3
+#define BIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT                                 0x0
+#define BIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK                                   0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_1_REG1
+#define BIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT                                 0x8
+#define BIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT                                0x14
+#define BIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_1_REG1__VALID_MASK                                            0x00000001L
+#define BIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK                                   0x000FFF00L
+#define BIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK                                  0xFFF00000L
+//BIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_1_REG2
+#define BIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT                                0x0
+#define BIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK                                  0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_1_REG3
+#define BIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT                                 0x0
+#define BIF_CFG_DEV0_RC0_IDE_6_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK                                   0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CAP
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT                     0x0
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK                       0x0000000FL
+//BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CNTL
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT                      0x0
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CNTL__XT_ENABLE__SHIFT                                        0x1
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT                          0x2
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CNTL__TX_AGGREGATION_MODE_PR__SHIFT                           0x4
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT                          0x6
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CNTL__PCRC_ENABLE__SHIFT                                      0x8
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT                     0x9
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT                         0xa
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CNTL__SELECTED_ALGORITHM__SHIFT                               0xe
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CNTL__TC__SHIFT                                               0x13
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CNTL__DEFAULT_STREAM__SHIFT                                   0x16
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CNTL__TEE_LIMITED_STREAM__SHIFT                               0x17
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CNTL__STREAM_ID__SHIFT                                        0x18
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK                        0x00000001L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CNTL__XT_ENABLE_MASK                                          0x00000002L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CNTL__TX_AGGREGATION_MODE_NPR_MASK                            0x0000000CL
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CNTL__TX_AGGREGATION_MODE_PR_MASK                             0x00000030L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CNTL__TX_AGGREGATION_MODE_CPL_MASK                            0x000000C0L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CNTL__PCRC_ENABLE_MASK                                        0x00000100L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK                       0x00000200L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK                           0x00003C00L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CNTL__SELECTED_ALGORITHM_MASK                                 0x0007C000L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CNTL__TC_MASK                                                 0x00380000L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CNTL__DEFAULT_STREAM_MASK                                     0x00400000L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CNTL__TEE_LIMITED_STREAM_MASK                                 0x00800000L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_CNTL__STREAM_ID_MASK                                          0xFF000000L
+//BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_STATUS
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT                     0x0
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT                          0x1f
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK                       0x0000000FL
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_7_STATUS__RECEIVED_IDE_FAIL_MSG_MASK                            0x80000000L
+//BIF_CFG_DEV0_RC0_IDE_7_RID_ASSOCIATION_REG1
+#define BIF_CFG_DEV0_RC0_IDE_7_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT                                         0x8
+#define BIF_CFG_DEV0_RC0_IDE_7_RID_ASSOCIATION_REG1__RID_LIMIT_MASK                                           0x00FFFF00L
+//BIF_CFG_DEV0_RC0_IDE_7_RID_ASSOCIATION_REG2
+#define BIF_CFG_DEV0_RC0_IDE_7_RID_ASSOCIATION_REG2__VALID__SHIFT                                             0x0
+#define BIF_CFG_DEV0_RC0_IDE_7_RID_ASSOCIATION_REG2__RID_BASE__SHIFT                                          0x8
+#define BIF_CFG_DEV0_RC0_IDE_7_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT                                      0x18
+#define BIF_CFG_DEV0_RC0_IDE_7_RID_ASSOCIATION_REG2__VALID_MASK                                               0x00000001L
+#define BIF_CFG_DEV0_RC0_IDE_7_RID_ASSOCIATION_REG2__RID_BASE_MASK                                            0x00FFFF00L
+#define BIF_CFG_DEV0_RC0_IDE_7_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK                                        0xFF000000L
+//BIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_0_REG1
+#define BIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT                                 0x8
+#define BIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT                                0x14
+#define BIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_0_REG1__VALID_MASK                                            0x00000001L
+#define BIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK                                   0x000FFF00L
+#define BIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK                                  0xFFF00000L
+//BIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_0_REG2
+#define BIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT                                0x0
+#define BIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK                                  0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_0_REG3
+#define BIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT                                 0x0
+#define BIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK                                   0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_1_REG1
+#define BIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT                                 0x8
+#define BIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT                                0x14
+#define BIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_1_REG1__VALID_MASK                                            0x00000001L
+#define BIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK                                   0x000FFF00L
+#define BIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK                                  0xFFF00000L
+//BIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_1_REG2
+#define BIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT                                0x0
+#define BIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK                                  0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_1_REG3
+#define BIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT                                 0x0
+#define BIF_CFG_DEV0_RC0_IDE_7_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK                                   0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CAP
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT                     0x0
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK                       0x0000000FL
+//BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CNTL
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT                      0x0
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CNTL__XT_ENABLE__SHIFT                                        0x1
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT                          0x2
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CNTL__TX_AGGREGATION_MODE_PR__SHIFT                           0x4
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT                          0x6
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CNTL__PCRC_ENABLE__SHIFT                                      0x8
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT                     0x9
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT                         0xa
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CNTL__SELECTED_ALGORITHM__SHIFT                               0xe
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CNTL__TC__SHIFT                                               0x13
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CNTL__DEFAULT_STREAM__SHIFT                                   0x16
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CNTL__TEE_LIMITED_STREAM__SHIFT                               0x17
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CNTL__STREAM_ID__SHIFT                                        0x18
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK                        0x00000001L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CNTL__XT_ENABLE_MASK                                          0x00000002L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CNTL__TX_AGGREGATION_MODE_NPR_MASK                            0x0000000CL
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CNTL__TX_AGGREGATION_MODE_PR_MASK                             0x00000030L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CNTL__TX_AGGREGATION_MODE_CPL_MASK                            0x000000C0L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CNTL__PCRC_ENABLE_MASK                                        0x00000100L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK                       0x00000200L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK                           0x00003C00L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CNTL__SELECTED_ALGORITHM_MASK                                 0x0007C000L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CNTL__TC_MASK                                                 0x00380000L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CNTL__DEFAULT_STREAM_MASK                                     0x00400000L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CNTL__TEE_LIMITED_STREAM_MASK                                 0x00800000L
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_CNTL__STREAM_ID_MASK                                          0xFF000000L
+//BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_STATUS
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT                     0x0
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT                          0x1f
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK                       0x0000000FL
+#define BIF_CFG_DEV0_RC0_SELECTIVE_IDE_STREAM_8_STATUS__RECEIVED_IDE_FAIL_MSG_MASK                            0x80000000L
+//BIF_CFG_DEV0_RC0_IDE_8_RID_ASSOCIATION_REG1
+#define BIF_CFG_DEV0_RC0_IDE_8_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT                                         0x8
+#define BIF_CFG_DEV0_RC0_IDE_8_RID_ASSOCIATION_REG1__RID_LIMIT_MASK                                           0x00FFFF00L
+//BIF_CFG_DEV0_RC0_IDE_8_RID_ASSOCIATION_REG2
+#define BIF_CFG_DEV0_RC0_IDE_8_RID_ASSOCIATION_REG2__VALID__SHIFT                                             0x0
+#define BIF_CFG_DEV0_RC0_IDE_8_RID_ASSOCIATION_REG2__RID_BASE__SHIFT                                          0x8
+#define BIF_CFG_DEV0_RC0_IDE_8_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT                                      0x18
+#define BIF_CFG_DEV0_RC0_IDE_8_RID_ASSOCIATION_REG2__VALID_MASK                                               0x00000001L
+#define BIF_CFG_DEV0_RC0_IDE_8_RID_ASSOCIATION_REG2__RID_BASE_MASK                                            0x00FFFF00L
+#define BIF_CFG_DEV0_RC0_IDE_8_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK                                        0xFF000000L
+//BIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_0_REG1
+#define BIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT                                 0x8
+#define BIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT                                0x14
+#define BIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_0_REG1__VALID_MASK                                            0x00000001L
+#define BIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK                                   0x000FFF00L
+#define BIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK                                  0xFFF00000L
+//BIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_0_REG2
+#define BIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT                                0x0
+#define BIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK                                  0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_0_REG3
+#define BIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT                                 0x0
+#define BIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK                                   0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_1_REG1
+#define BIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT                                 0x8
+#define BIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT                                0x14
+#define BIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_1_REG1__VALID_MASK                                            0x00000001L
+#define BIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK                                   0x000FFF00L
+#define BIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK                                  0xFFF00000L
+//BIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_1_REG2
+#define BIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT                                0x0
+#define BIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK                                  0xFFFFFFFFL
+//BIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_1_REG3
+#define BIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT                                 0x0
+#define BIF_CFG_DEV0_RC0_IDE_8_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK                                   0xFFFFFFFFL
+
+
+// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_0_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_0_VENDOR_ID__VENDOR_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF0_0_VENDOR_ID__VENDOR_ID_MASK                                                         0xFFFFL
+//BIF_CFG_DEV0_EPF0_0_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_ID__DEVICE_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_ID__DEVICE_ID_MASK                                                         0xFFFFL
+//BIF_CFG_DEV0_EPF0_0_COMMAND
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__IO_ACCESS_EN__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__MEM_ACCESS_EN__SHIFT                                                     0x1
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__BUS_MASTER_EN__SHIFT                                                     0x2
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                  0x3
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                           0x4
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__PAL_SNOOP_EN__SHIFT                                                      0x5
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                             0x6
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__AD_STEPPING__SHIFT                                                       0x7
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__SERR_EN__SHIFT                                                           0x8
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__FAST_B2B_EN__SHIFT                                                       0x9
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__INT_DIS__SHIFT                                                           0xa
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__IO_ACCESS_EN_MASK                                                        0x0001L
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__MEM_ACCESS_EN_MASK                                                       0x0002L
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__BUS_MASTER_EN_MASK                                                       0x0004L
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__SPECIAL_CYCLE_EN_MASK                                                    0x0008L
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                             0x0010L
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__PAL_SNOOP_EN_MASK                                                        0x0020L
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__PARITY_ERROR_RESPONSE_MASK                                               0x0040L
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__AD_STEPPING_MASK                                                         0x0080L
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__SERR_EN_MASK                                                             0x0100L
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__FAST_B2B_EN_MASK                                                         0x0200L
+#define BIF_CFG_DEV0_EPF0_0_COMMAND__INT_DIS_MASK                                                             0x0400L
+//BIF_CFG_DEV0_EPF0_0_STATUS
+#define BIF_CFG_DEV0_EPF0_0_STATUS__IMMEDIATE_READINESS__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF0_0_STATUS__INT_STATUS__SHIFT                                                         0x3
+#define BIF_CFG_DEV0_EPF0_0_STATUS__CAP_LIST__SHIFT                                                           0x4
+#define BIF_CFG_DEV0_EPF0_0_STATUS__PCI_66_CAP__SHIFT                                                         0x5
+#define BIF_CFG_DEV0_EPF0_0_STATUS__FAST_BACK_CAPABLE__SHIFT                                                  0x7
+#define BIF_CFG_DEV0_EPF0_0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                           0x8
+#define BIF_CFG_DEV0_EPF0_0_STATUS__DEVSEL_TIMING__SHIFT                                                      0x9
+#define BIF_CFG_DEV0_EPF0_0_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                0xb
+#define BIF_CFG_DEV0_EPF0_0_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                              0xc
+#define BIF_CFG_DEV0_EPF0_0_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                              0xd
+#define BIF_CFG_DEV0_EPF0_0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                              0xe
+#define BIF_CFG_DEV0_EPF0_0_STATUS__PARITY_ERROR_DETECTED__SHIFT                                              0xf
+#define BIF_CFG_DEV0_EPF0_0_STATUS__IMMEDIATE_READINESS_MASK                                                  0x0001L
+#define BIF_CFG_DEV0_EPF0_0_STATUS__INT_STATUS_MASK                                                           0x0008L
+#define BIF_CFG_DEV0_EPF0_0_STATUS__CAP_LIST_MASK                                                             0x0010L
+#define BIF_CFG_DEV0_EPF0_0_STATUS__PCI_66_CAP_MASK                                                           0x0020L
+#define BIF_CFG_DEV0_EPF0_0_STATUS__FAST_BACK_CAPABLE_MASK                                                    0x0080L
+#define BIF_CFG_DEV0_EPF0_0_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                             0x0100L
+#define BIF_CFG_DEV0_EPF0_0_STATUS__DEVSEL_TIMING_MASK                                                        0x0600L
+#define BIF_CFG_DEV0_EPF0_0_STATUS__SIGNAL_TARGET_ABORT_MASK                                                  0x0800L
+#define BIF_CFG_DEV0_EPF0_0_STATUS__RECEIVED_TARGET_ABORT_MASK                                                0x1000L
+#define BIF_CFG_DEV0_EPF0_0_STATUS__RECEIVED_MASTER_ABORT_MASK                                                0x2000L
+#define BIF_CFG_DEV0_EPF0_0_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                0x4000L
+#define BIF_CFG_DEV0_EPF0_0_STATUS__PARITY_ERROR_DETECTED_MASK                                                0x8000L
+//BIF_CFG_DEV0_EPF0_0_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_0_REVISION_ID__MINOR_REV_ID__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF0_0_REVISION_ID__MAJOR_REV_ID__SHIFT                                                  0x4
+#define BIF_CFG_DEV0_EPF0_0_REVISION_ID__MINOR_REV_ID_MASK                                                    0x0FL
+#define BIF_CFG_DEV0_EPF0_0_REVISION_ID__MAJOR_REV_ID_MASK                                                    0xF0L
+//BIF_CFG_DEV0_EPF0_0_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_0_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PROG_INTERFACE__PROG_INTERFACE_MASK                                               0xFFL
+//BIF_CFG_DEV0_EPF0_0_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_0_SUB_CLASS__SUB_CLASS__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF0_0_SUB_CLASS__SUB_CLASS_MASK                                                         0xFFL
+//BIF_CFG_DEV0_EPF0_0_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_0_BASE_CLASS__BASE_CLASS__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_0_BASE_CLASS__BASE_CLASS_MASK                                                       0xFFL
+//BIF_CFG_DEV0_EPF0_0_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF0_0_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                  0xFFL
+//BIF_CFG_DEV0_EPF0_0_LATENCY
+#define BIF_CFG_DEV0_EPF0_0_LATENCY__LATENCY_TIMER__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_0_LATENCY__LATENCY_TIMER_MASK                                                       0xFFL
+//BIF_CFG_DEV0_EPF0_0_HEADER
+#define BIF_CFG_DEV0_EPF0_0_HEADER__HEADER_TYPE__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_EPF0_0_HEADER__DEVICE_TYPE__SHIFT                                                        0x7
+#define BIF_CFG_DEV0_EPF0_0_HEADER__HEADER_TYPE_MASK                                                          0x7FL
+#define BIF_CFG_DEV0_EPF0_0_HEADER__DEVICE_TYPE_MASK                                                          0x80L
+//BIF_CFG_DEV0_EPF0_0_BIST
+#define BIF_CFG_DEV0_EPF0_0_BIST__BIST_COMP__SHIFT                                                            0x0
+#define BIF_CFG_DEV0_EPF0_0_BIST__BIST_STRT__SHIFT                                                            0x6
+#define BIF_CFG_DEV0_EPF0_0_BIST__BIST_CAP__SHIFT                                                             0x7
+#define BIF_CFG_DEV0_EPF0_0_BIST__BIST_COMP_MASK                                                              0x0FL
+#define BIF_CFG_DEV0_EPF0_0_BIST__BIST_STRT_MASK                                                              0x40L
+#define BIF_CFG_DEV0_EPF0_0_BIST__BIST_CAP_MASK                                                               0x80L
+//BIF_CFG_DEV0_EPF0_0_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_1__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_1__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_2__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_2__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_3__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_3__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_4__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_4__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_5__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_5__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_6__BASE_ADDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_0_BASE_ADDR_6__BASE_ADDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                                   0x10
+#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT                                       0x1
+#define BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT                                      0x4
+#define BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                   0xb
+#define BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__ROM_ENABLE_MASK                                                    0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK                                         0x0000000EL
+#define BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK                                        0x000000F0L
+#define BIF_CFG_DEV0_EPF0_0_ROM_BASE_ADDR__BASE_ADDR_MASK                                                     0xFFFFF800L
+//BIF_CFG_DEV0_EPF0_0_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_0_CAP_PTR__CAP_PTR__SHIFT                                                           0x0
+#define BIF_CFG_DEV0_EPF0_0_CAP_PTR__CAP_PTR_MASK                                                             0xFFL
+//BIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF0_0_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                               0xFFL
+//BIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF0_0_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                 0xFFL
+//BIF_CFG_DEV0_EPF0_0_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_0_MIN_GRANT__MIN_GNT__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF0_0_MIN_GRANT__MIN_GNT_MASK                                                           0xFFL
+//BIF_CFG_DEV0_EPF0_0_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_0_MAX_LATENCY__MAX_LAT__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF0_0_MAX_LATENCY__MAX_LAT_MASK                                                         0xFFL
+//BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__CAP_ID__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__NEXT_PTR__SHIFT                                                  0x8
+#define BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__LENGTH__SHIFT                                                    0x10
+#define BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__CAP_ID_MASK                                                      0x000000FFL
+#define BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__NEXT_PTR_MASK                                                    0x0000FF00L
+#define BIF_CFG_DEV0_EPF0_0_VENDOR_CAP_LIST__LENGTH_MASK                                                      0x00FF0000L
+//BIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W
+#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT                                                 0x10
+#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK                                            0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_ADAPTER_ID_W__SUBSYSTEM_ID_MASK                                                   0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
+//BIF_CFG_DEV0_EPF0_0_PMI_CAP
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__VERSION__SHIFT                                                           0x0
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__PME_CLOCK__SHIFT                                                         0x3
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                               0x4
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                 0x5
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__AUX_CURRENT__SHIFT                                                       0x6
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__D1_SUPPORT__SHIFT                                                        0x9
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__D2_SUPPORT__SHIFT                                                        0xa
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__PME_SUPPORT__SHIFT                                                       0xb
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__VERSION_MASK                                                             0x0007L
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__PME_CLOCK_MASK                                                           0x0008L
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                 0x0010L
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                   0x0020L
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__AUX_CURRENT_MASK                                                         0x01C0L
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__D1_SUPPORT_MASK                                                          0x0200L
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__D2_SUPPORT_MASK                                                          0x0400L
+#define BIF_CFG_DEV0_EPF0_0_PMI_CAP__PME_SUPPORT_MASK                                                         0xF800L
+//BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                             0x3
+#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PME_EN__SHIFT                                                    0x8
+#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                               0x9
+#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                0xd
+#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                0xf
+#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                             0x16
+#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                0x17
+#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                  0x18
+#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__POWER_STATE_MASK                                                 0x00000003L
+#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                               0x00000008L
+#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PME_EN_MASK                                                      0x00000100L
+#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                 0x00001E00L
+#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                  0x00006000L
+#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PME_STATUS_MASK                                                  0x00008000L
+#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                               0x00400000L
+#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                  0x00800000L
+#define BIF_CFG_DEV0_EPF0_0_PMI_STATUS_CNTL__PMI_DATA_MASK                                                    0xFF000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST__CAP_ID__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
+//BIF_CFG_DEV0_EPF0_0_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__VERSION__SHIFT                                                          0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__DEVICE_TYPE__SHIFT                                                      0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                  0x9
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__FLIT_MODE_SUPPORT__SHIFT                                                0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__VERSION_MASK                                                            0x000FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__DEVICE_TYPE_MASK                                                        0x00F0L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                   0x0100L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                    0x3E00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CAP__FLIT_MODE_SUPPORT_MASK                                                  0x8000L
+//BIF_CFG_DEV0_EPF0_0_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                   0x3
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                   0x5
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                         0x6
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                          0x9
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                       0xf
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT                                       0x10
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__RX_MPS_FIXED__SHIFT                                                   0x11
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                      0x12
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                      0x1a
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                    0x1c
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__MIXED_MPS_SUPPORTED__SHIFT                                            0x1d
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__TEE_IO_SUPPORT__SHIFT                                                 0x1e
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                              0x00000007L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__PHANTOM_FUNC_MASK                                                     0x00000018L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__EXTENDED_TAG_MASK                                                     0x00000020L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                           0x000001C0L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                            0x00000E00L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                         0x00008000L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK                                         0x00010000L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__RX_MPS_FIXED_MASK                                                     0x00020000L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                        0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                        0x0C000000L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__FLR_CAPABLE_MASK                                                      0x10000000L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__MIXED_MPS_SUPPORTED_MASK                                              0x20000000L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP__TEE_IO_SUPPORT_MASK                                                   0x40000000L
+//BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                              0x1
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                  0x2
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                 0x3
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                0x4
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                               0x8
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                               0x9
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                               0xa
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                   0xb
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                         0xc
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__INITIATE_FLR__SHIFT                                                  0xf
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__CORR_ERR_EN_MASK                                                     0x0001L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                0x0002L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                    0x0004L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__USR_REPORT_EN_MASK                                                   0x0008L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                  0x0010L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                0x00E0L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                 0x0100L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                 0x0200L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                 0x0400L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                     0x0800L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                           0x7000L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL__INITIATE_FLR_MASK                                                    0x8000L
+//BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__CORR_ERR__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                               0x1
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__FATAL_ERR__SHIFT                                                   0x2
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__USR_DETECTED__SHIFT                                                0x3
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__AUX_PWR__SHIFT                                                     0x4
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                           0x5
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                               0x6
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__CORR_ERR_MASK                                                      0x0001L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                 0x0002L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__FATAL_ERR_MASK                                                     0x0004L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__USR_DETECTED_MASK                                                  0x0008L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__AUX_PWR_MASK                                                       0x0010L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                             0x0020L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                 0x0040L
+//BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                     0x4
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                      0x5
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                    0x6
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                    0x7
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                        0x9
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                     0xa
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                 0xb
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                            0xc
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                 0xe
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                               0x10
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                               0x11
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                0x12
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                  0x14
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                  0x15
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                      0x16
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                0x18
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                 0x1a
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                 0x1f
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                     0x0000000FL
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                       0x00000010L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                        0x00000020L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                      0x00000040L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                      0x00000080L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                      0x00000100L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                          0x00000200L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                       0x00000400L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                   0x00000800L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                              0x00003000L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                   0x0000C000L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                 0x00010000L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                 0x00020000L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                  0x000C0000L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                    0x00100000L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                    0x00200000L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                        0x00C00000L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                  0x03000000L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                   0x04000000L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                   0x80000000L
+//BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                              0x4
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                            0x5
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                          0x6
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                     0x7
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                           0x8
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                        0x9
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__LTR_EN__SHIFT                                                       0xa
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                 0xb
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                 0xc
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__OBFF_EN__SHIFT                                                      0xd
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                  0xf
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                              0x000FL
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                0x0010L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                              0x0020L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                            0x0040L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                       0x0080L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                             0x0100L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                          0x0200L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__LTR_EN_MASK                                                         0x0400L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                   0x0800L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                   0x1000L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__OBFF_EN_MASK                                                        0x6000L
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                    0x8000L
+//BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2__RESERVED__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_0_DEVICE_STATUS2__RESERVED_MASK                                                     0xFFFFL
+//BIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST__CAP_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                     0x8
+#define BIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST__CAP_ID_MASK                                                         0x00FFL
+#define BIF_CFG_DEV0_EPF0_0_MSI_CAP_LIST__NEXT_PTR_MASK                                                       0xFF00L
+//BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EN__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                0x1
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                 0x4
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                    0x7
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                    0x8
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT                                         0x9
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT                                          0xa
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EN_MASK                                                         0x0001L
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                  0x000EL
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                   0x0070L
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_64BIT_MASK                                                      0x0080L
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                      0x0100L
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK                                           0x0200L
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK                                            0x0400L
+//BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                           0x2
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA__MSI_DATA__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA__MSI_DATA_MASK                                                       0xFFFFL
+//BIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK                                               0xFFFFL
+//BIF_CFG_DEV0_EPF0_0_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_0_MSI_MASK__MSI_MASK__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF0_0_MSI_MASK__MSI_MASK_MASK                                                           0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF0_0_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                 0xFFFFL
+//BIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF0_0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK                                         0xFFFFL
+//BIF_CFG_DEV0_EPF0_0_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_0_MSI_MASK_64__MSI_MASK_64__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_0_MSI_MASK_64__MSI_MASK_64_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_0_MSI_PENDING__MSI_PENDING__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_0_MSI_PENDING__MSI_PENDING_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_0_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF0_0_MSI_PENDING_64__MSI_PENDING_64_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST__CAP_ID__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
+#define BIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST__CAP_ID_MASK                                                        0x00FFL
+#define BIF_CFG_DEV0_EPF0_0_MSIX_CAP_LIST__NEXT_PTR_MASK                                                      0xFF00L
+//BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                              0xe
+#define BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                     0xf
+#define BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                               0x07FFL
+#define BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                                0x4000L
+#define BIF_CFG_DEV0_EPF0_0_MSIX_MSG_CNTL__MSIX_EN_MASK                                                       0x8000L
+//BIF_CFG_DEV0_EPF0_0_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF0_0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                              0x3
+#define BIF_CFG_DEV0_EPF0_0_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                                   0x00000007L
+#define BIF_CFG_DEV0_EPF0_0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                                0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_0_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_0_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                                  0x3
+#define BIF_CFG_DEV0_EPF0_0_MSIX_PBA__MSIX_PBA_BIR_MASK                                                       0x00000007L
+#define BIF_CFG_DEV0_EPF0_0_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                    0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_0_PCIE_NULL2_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_NULL2_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_NULL2_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_NULL2_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_NULL2_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_NULL2_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_NULL2_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                    0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                       0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                      0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                     0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                  0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                     0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                      0xd
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                 0xe
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                               0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                    0x11
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                     0x12
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                    0x13
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                              0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                               0x15
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                              0x16
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                              0x17
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                     0x18
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                      0x19
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                 0x1a
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__DMWR_REQUEST_EGRESS_BLOCKED_STATUS__SHIFT                 0x1b
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__IDE_CHECK_FAILED_STATUS__SHIFT                            0x1c
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__MISROUTED_IDE_TLP_STATUS__SHIFT                           0x1d
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__PCRC_CHECK_FAILED_STATUS__SHIFT                           0x1e
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                       0x00000010L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                    0x00000020L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                       0x00001000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                        0x00002000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                   0x00004000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                 0x00008000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                     0x00010000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                      0x00020000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                       0x00040000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                      0x00080000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                0x00100000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                 0x00200000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                0x00400000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                0x00800000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                       0x01000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                        0x02000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                   0x04000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__DMWR_REQUEST_EGRESS_BLOCKED_STATUS_MASK                   0x08000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__IDE_CHECK_FAILED_STATUS_MASK                              0x10000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__MISROUTED_IDE_TLP_STATUS_MASK                             0x20000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_STATUS__PCRC_CHECK_FAILED_STATUS_MASK                             0x40000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                         0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                      0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                         0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                          0xd
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                     0xe
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                   0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                       0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                        0x11
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                         0x12
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                        0x13
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                  0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                   0x15
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                  0x16
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                  0x17
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                         0x18
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                          0x19
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                     0x1a
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__DMWR_REQUEST_EGRESS_BLOCKED_MASK__SHIFT                     0x1b
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__IDE_CHECK_FAILED_MASK__SHIFT                                0x1c
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__MISROUTED_IDE_TLP_MASK__SHIFT                               0x1d
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__PCRC_CHECK_FAILED_MASK__SHIFT                               0x1e
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                           0x00000010L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                        0x00000020L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                           0x00001000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                            0x00002000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                       0x00004000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                     0x00008000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                         0x00010000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                          0x00020000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                           0x00040000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                          0x00080000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                    0x00100000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                     0x00200000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                    0x00400000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                    0x00800000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                           0x01000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                            0x02000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                       0x04000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__DMWR_REQUEST_EGRESS_BLOCKED_MASK_MASK                       0x08000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__IDE_CHECK_FAILED_MASK_MASK                                  0x10000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__MISROUTED_IDE_TLP_MASK_MASK                                 0x20000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_MASK__PCRC_CHECK_FAILED_MASK_MASK                                 0x40000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                              0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                 0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                  0xd
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                             0xe
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                           0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                               0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                0x11
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                 0x12
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                0x13
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                          0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                           0x15
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                          0x16
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                          0x17
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                 0x18
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                  0x19
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT             0x1a
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__DMWR_REQUEST_EGRESS_BLOCKED_SEVERITY__SHIFT             0x1b
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__IDE_CHECK_FAILED_SEVERITY__SHIFT                        0x1c
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MISROUTED_IDE_TLP_SEVERITY__SHIFT                       0x1d
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__PCRC_CHECK_FAILED_SEVERITY__SHIFT                       0x1e
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                   0x00000010L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                0x00000020L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                   0x00001000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                    0x00002000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                               0x00004000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                             0x00008000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                 0x00010000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                  0x00020000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                   0x00040000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                  0x00080000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                            0x00100000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                             0x00200000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                            0x00400000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                            0x00800000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                   0x01000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                    0x02000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK               0x04000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__DMWR_REQUEST_EGRESS_BLOCKED_SEVERITY_MASK               0x08000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__IDE_CHECK_FAILED_SEVERITY_MASK                          0x10000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__MISROUTED_IDE_TLP_SEVERITY_MASK                         0x20000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_UNCORR_ERR_SEVERITY__PCRC_CHECK_FAILED_SEVERITY_MASK                         0x40000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                       0x6
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                      0x7
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                           0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                          0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                         0xd
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                  0xe
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                                  0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                         0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                         0x00000040L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                        0x00000080L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                             0x00000100L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                            0x00001000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                           0x00002000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                    0x00004000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                    0x00008000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                           0x6
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                          0x7
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                               0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                              0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                             0xd
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                      0xe
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                      0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                             0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                             0x00000040L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                            0x00000080L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                 0x00000100L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                0x00001000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                               0x00002000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                        0x00004000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                        0x00008000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT                                        0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT                                         0x6
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                      0x7
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                       0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                  0x9
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                   0xa
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                              0xb
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT                      0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__HEADER_LOG_SIZE__SHIFT                                     0xd
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_WAS_FLIT_MODE__SHIFT                            0x12
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_SIZE__SHIFT                                     0x13
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                         0x0000001FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK                                          0x00000020L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK                                           0x00000040L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                        0x00000080L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                         0x00000100L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                    0x00000200L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                     0x00000400L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                                0x00000800L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK                        0x00001000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__HEADER_LOG_SIZE_MASK                                       0x0003E000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_WAS_FLIT_MODE_MASK                              0x00040000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_SIZE_MASK                                       0x00F80000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG0__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG1__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG2__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG3__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG4__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG4__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG5__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG5__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG6
+#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG6__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG6__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG7
+#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG7__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG7__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG8__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG8__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG9
+#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG9__TLP_HDR__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG9__TLP_HDR_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG10__TLP_HDR__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG10__TLP_HDR_MASK                                                      0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG11
+#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG11__TLP_HDR__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG11__TLP_HDR_MASK                                                      0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG12
+#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG12__TLP_HDR__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG12__TLP_HDR_MASK                                                      0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG13
+#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG13__TLP_HDR__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_HDR_LOG13__TLP_HDR_MASK                                                      0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT                                  0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT                                 0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK                                     0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK                                    0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK                                   0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT                                  0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK                                    0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT                                  0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK                                    0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                         0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                         0x2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                      0x3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                           0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                        0x6
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__ENHANCED_CAPABILITY__SHIFT                                          0x7
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                              0x0001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                           0x0002L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                           0x0004L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                        0x0008L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                            0x0010L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                             0x0020L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                          0x0040L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__ENHANCED_CAPABILITY_MASK                                            0x0080L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                     0xFF00L
+//BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                     0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                     0x2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                  0x3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                      0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                       0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                    0x6
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN__SHIFT                                      0x7
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL__SHIFT                               0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL__SHIFT                               0xa
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL__SHIFT                             0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                          0x0001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                       0x0002L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                       0x0004L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                    0x0008L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                        0x0010L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                         0x0020L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                      0x0040L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN_MASK                                        0x0080L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL_MASK                                 0x0300L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL_MASK                                 0x0C00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL_MASK                               0x1000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_RTR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_RTR_DATA1
+#define BIF_CFG_DEV0_EPF0_0_RTR_DATA1__RESET_TIME__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF0_0_RTR_DATA1__DLUP_TIME__SHIFT                                                       0xc
+#define BIF_CFG_DEV0_EPF0_0_RTR_DATA1__RTR_VALID__SHIFT                                                       0x1f
+#define BIF_CFG_DEV0_EPF0_0_RTR_DATA1__RESET_TIME_MASK                                                        0x00000FFFL
+#define BIF_CFG_DEV0_EPF0_0_RTR_DATA1__DLUP_TIME_MASK                                                         0x00FFF000L
+#define BIF_CFG_DEV0_EPF0_0_RTR_DATA1__RTR_VALID_MASK                                                         0x80000000L
+//BIF_CFG_DEV0_EPF0_0_RTR_DATA2
+#define BIF_CFG_DEV0_EPF0_0_RTR_DATA2__FLR_TIME__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_EPF0_0_RTR_DATA2__D3HOTD0_TIME__SHIFT                                                    0xc
+#define BIF_CFG_DEV0_EPF0_0_RTR_DATA2__FLR_TIME_MASK                                                          0x00000FFFL
+#define BIF_CFG_DEV0_EPF0_0_RTR_DATA2__D3HOTD0_TIME_MASK                                                      0x00FFF000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT                                      0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT                                     0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK                                         0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK                                        0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK                                       0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT__EXTENDED_PWR_BUDGET_ENABLE__SHIFT                    0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK                                     0x000000FFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA_SELECT__EXTENDED_PWR_BUDGET_ENABLE_MASK                      0x00010000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT                                           0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT                                         0xa
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT                                             0xd
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT                                                 0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT                                           0x12
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK                                             0x000000FFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK                                             0x00000300L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK                                           0x00001C00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK                                               0x00006000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__TYPE_MASK                                                   0x00038000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK                                             0x001C0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP__EXTENDED_PWR_BUDGET_SUPPORT__SHIFT                           0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK                                        0x01L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PWR_BUDGET_CAP__EXTENDED_PWR_BUDGET_SUPPORT_MASK                             0x02L
+//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT                                               0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT                                              0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT                                              0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT                                              0x18
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__SUBSTATE_MAX_MASK                                                   0x0000001FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK                                                 0x00000300L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK                                                0x00003000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK                                                0x00FF0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK                                                0xFF000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT                       0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK                         0x000000FFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK                                             0x001FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK                                       0x0100L
+//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK                                                 0x001FL
+//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                            0xFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE__SHIFT                                      0xa
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE__SHIFT                                     0x1a
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_VALUE_MASK                                        0x000003FFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_S_LATENCY_SCALE_MASK                                        0x00001C00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_VALUE_MASK                                       0x03FF0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LTR_CAP__LTR_MAX_NS_LATENCY_SCALE_MASK                                       0x1C000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                      0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                            0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                       0x0001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                        0x0002L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                              0xFF00L
+//BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                      0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                       0x0001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                        0x0002L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                            0x0070L
+//BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK                                            0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_INDEX_MASK                                                    0x00000007L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK                                                0x000000E0L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE_MASK                                                     0x00003F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT                                         0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT                                  0x6
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED__SHIFT                                   0x7
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__TEE_EXCLUSIVE_ATTR_SUPPORTED__SHIFT                                 0x9
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK                                             0x001FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK                                           0x0020L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK                                    0x0040L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED_MASK                                     0x0080L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CAP__TEE_EXCLUSIVE_ATTR_SUPPORTED_MASK                                   0x0200L
+//BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL__STU__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL__TEE_EXCLUSIVE_ATTR_ENABLE__SHIFT                                   0xa
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT                                                  0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL__STU_MASK                                                           0x001FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL__TEE_EXCLUSIVE_ATTR_ENABLE_MASK                                     0x0400L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_ATS_CNTL__ATC_ENABLE_MASK                                                    0x8000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL__PRI_ENABLE__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL__PRI_RESET__SHIFT                                              0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL__PRI_ENABLE_MASK                                               0x0001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_CNTL__PRI_RESET_MASK                                                0x0002L
+//BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX__SHIFT                        0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__STOPPED__SHIFT                                              0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED__SHIFT                          0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__RESPONSE_FAILURE_MASK                                       0x0001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__UNEXPECTED_PAGE_REQ_GRP_INDEX_MASK                          0x0002L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__STOPPED_MASK                                                0x0100L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PAGE_REQ_STATUS__PRG_RESPONSE_PASID_REQUIRED_MASK                            0x8000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY
+#define BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_CAPACITY__OUTSTAND_PAGE_REQ_CAPACITY_MASK                  0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC
+#define BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_OUTSTAND_PAGE_REQ_ALLOC__OUTSTAND_PAGE_REQ_ALLOC_MASK                        0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT                             0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT                                  0x2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__TRANSLATED_REQ_WITH_PASID_SUPPORTED__SHIFT                        0x3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT                                            0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK                               0x0002L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK                                    0x0004L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__TRANSLATED_REQ_WITH_PASID_SUPPORTED_MASK                          0x0008L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK                                              0x1F00L
+//BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT                               0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT                          0x2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__TRANSLATED_REQ_WITH_PASID_ENABLE__SHIFT                          0x3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_ENABLE_MASK                                                0x0001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK                                 0x0002L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK                            0x0004L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PASID_CNTL__TRANSLATED_REQ_WITH_PASID_ENABLE_MASK                            0x0008L
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT                          0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                   0x2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_14_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                    0x3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT                            0x15
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK                                       0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK                            0x00000002L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                     0x00000004L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_14_BIT_TAG_REQUESTER_SUPPORTED_MASK                      0x00000008L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK                              0xFFE00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT                              0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT                         0x2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT                                           0x3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT                                0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                  0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_14_BIT_TAG_REQUESTER_ENABLE__SHIFT                   0x6
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK                                          0x0001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK                                0x0002L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK                           0x0004L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK                                             0x0008L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK                                  0x0010L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE_MASK                    0x0020L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_CONTROL__SRIOV_VF_14_BIT_TAG_REQUESTER_ENABLE_MASK                     0x0040L
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT                               0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK                                 0x0001L
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT                                  0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK                                    0xFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK                                        0xFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK                                            0xFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK                                0xFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK                            0xFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK                                        0xFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT                                0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK                                  0xFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT                  0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK                    0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK                          0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK                                      0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK                                      0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK                                      0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK                                      0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK                                      0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK                                      0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR__SHIFT   0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT  0x3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR_MASK     0x00000007L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK  0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                  0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID_MASK                                      0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER_MASK                                     0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK                                    0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT                             0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED_MASK                               0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM__SHIFT                                 0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX_MASK                                       0x00000007L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM_MASK                                   0x000000E0L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_MASK                                        0x00003F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT                             0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED_MASK                               0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM__SHIFT                                 0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX_MASK                                       0x00000007L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM_MASK                                   0x000000E0L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_MASK                                        0x00003F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT                             0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED_MASK                               0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM__SHIFT                                 0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX_MASK                                       0x00000007L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM_MASK                                   0x000000E0L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_MASK                                        0x00003F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT                             0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED_MASK                               0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM__SHIFT                                 0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX_MASK                                       0x00000007L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM_MASK                                   0x000000E0L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_MASK                                        0x00003F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT                             0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED_MASK                               0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM__SHIFT                                 0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX_MASK                                       0x00000007L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM_MASK                                   0x000000E0L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_MASK                                        0x00003F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT                             0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED_MASK                               0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM__SHIFT                                 0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX_MASK                                       0x00000007L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM_MASK                                   0x000000E0L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_MASK                                        0x00003F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK                        0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_DOE_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_DOE_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_CAP__INTR_SUPPORT__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_CAP__DOE_INTR_MSG_NUM__SHIFT                                             0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_CAP__DOE_ATT_SUPPORT__SHIFT                                              0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_CAP__DOE_ASYNC_SUPPORT__SHIFT                                            0xd
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_CAP__INTR_SUPPORT_MASK                                                   0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_CAP__DOE_INTR_MSG_NUM_MASK                                               0x00000FFEL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_CAP__DOE_ATT_SUPPORT_MASK                                                0x00001000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_CAP__DOE_ASYNC_SUPPORT_MASK                                              0x00002000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_DOE_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_CNTL__DOE_ABORT__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_CNTL__DOE_INTR_EN__SHIFT                                                 0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_CNTL__DOE_ATT_NOT_NEED__SHIFT                                            0x2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_CNTL__DOE_ASYNC_MSG_EN__SHIFT                                            0x3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_CNTL__DOE_GO__SHIFT                                                      0x1f
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_CNTL__DOE_ABORT_MASK                                                     0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_CNTL__DOE_INTR_EN_MASK                                                   0x00000002L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_CNTL__DOE_ATT_NOT_NEED_MASK                                              0x00000004L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_CNTL__DOE_ASYNC_MSG_EN_MASK                                              0x00000008L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_CNTL__DOE_GO_MASK                                                        0x80000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_DOE_STS
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_STS__DOE_BUSY__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_STS__DOE_INTR_STS__SHIFT                                                 0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_STS__DOE_ERR__SHIFT                                                      0x2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_STS__DOE_ASYNC_MSG_STS__SHIFT                                            0x3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_STS__DOE_AT_ATTENTION__SHIFT                                             0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_STS__DOE_OBJ_RDY__SHIFT                                                  0x1f
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_STS__DOE_BUSY_MASK                                                       0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_STS__DOE_INTR_STS_MASK                                                   0x00000002L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_STS__DOE_ERR_MASK                                                        0x00000004L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_STS__DOE_ASYNC_MSG_STS_MASK                                              0x00000008L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_STS__DOE_AT_ATTENTION_MASK                                               0x00000010L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_STS__DOE_OBJ_RDY_MASK                                                    0x80000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_DOE_WMBOX
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_WMBOX__DOE_WMBOX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_WMBOX__DOE_WMBOX_MASK                                                    0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_DOE_RMBOX
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_RMBOX__DOE_RMBOX__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DOE_RMBOX__DOE_RMBOX_MASK                                                    0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID__SHIFT                           0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER__SHIFT                          0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR__SHIFT                         0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_ID_MASK                             0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__CAP_VER_MASK                            0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST_GPUIOV__NEXT_PTR_MASK                           0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV__SHIFT                                  0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH__SHIFT                               0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_ID_MASK                                     0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_REV_MASK                                    0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV__VSEC_LENGTH_MASK                                 0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN__SHIFT                        0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM__SHIFT                       0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_EN_MASK                          0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SRIOV_SHADOW__VF_NUM_MASK                         0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN__SHIFT  0x18
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN__SHIFT  0x19
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_TRN_ACK_INTR_EN_MASK    0x01000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_ENABLE__HVVM_MAILBOX_RCV_VALID_INTR_EN_MASK  0x02000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS__SHIFT  0x18
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS__SHIFT  0x19
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_TRN_ACK_INTR_STATUS_MASK  0x01000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_INTR_STATUS__HVVM_MAILBOX_RCV_VALID_INTR_STATUS_MASK  0x02000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR__SHIFT                 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__FUNCTION_ID__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__SOFT_PF_FLR_MASK                   0x0001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_RESET_CONTROL__FUNCTION_ID_MASK                   0xFF00L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX__SHIFT                    0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA__SHIFT                0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID__SHIFT               0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA__SHIFT                0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK__SHIFT                 0x18
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__VF_INDEX_MASK                      0x000000FFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_DATA_MASK                  0x00000F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__TRN_MSG_VALID_MASK                 0x00008000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_DATA_MASK                  0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW0__RCV_MSG_ACK_MASK                   0x01000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK__SHIFT                 0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID__SHIFT               0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK__SHIFT                 0x2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID__SHIFT               0x3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK__SHIFT                 0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID__SHIFT               0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK__SHIFT                 0x6
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID__SHIFT               0x7
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID__SHIFT               0x9
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK__SHIFT                 0xa
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID__SHIFT               0xb
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK__SHIFT                 0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID__SHIFT               0xd
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK__SHIFT                 0xe
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID__SHIFT               0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK__SHIFT                 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID__SHIFT               0x11
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK__SHIFT                 0x12
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID__SHIFT               0x13
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK__SHIFT                0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID__SHIFT              0x15
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK__SHIFT                0x16
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID__SHIFT              0x17
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK__SHIFT                0x18
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID__SHIFT              0x19
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK__SHIFT                0x1a
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID__SHIFT              0x1b
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK__SHIFT                0x1c
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID__SHIFT              0x1d
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK__SHIFT                0x1e
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID__SHIFT              0x1f
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_TRN_ACK_MASK                   0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF0_RCV_VALID_MASK                 0x00000002L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_TRN_ACK_MASK                   0x00000004L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF1_RCV_VALID_MASK                 0x00000008L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_TRN_ACK_MASK                   0x00000010L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF2_RCV_VALID_MASK                 0x00000020L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_TRN_ACK_MASK                   0x00000040L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF3_RCV_VALID_MASK                 0x00000080L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_TRN_ACK_MASK                   0x00000100L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF4_RCV_VALID_MASK                 0x00000200L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_TRN_ACK_MASK                   0x00000400L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF5_RCV_VALID_MASK                 0x00000800L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_TRN_ACK_MASK                   0x00001000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF6_RCV_VALID_MASK                 0x00002000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_TRN_ACK_MASK                   0x00004000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF7_RCV_VALID_MASK                 0x00008000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_TRN_ACK_MASK                   0x00010000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF8_RCV_VALID_MASK                 0x00020000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_TRN_ACK_MASK                   0x00040000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF9_RCV_VALID_MASK                 0x00080000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_TRN_ACK_MASK                  0x00100000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF10_RCV_VALID_MASK                0x00200000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_TRN_ACK_MASK                  0x00400000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF11_RCV_VALID_MASK                0x00800000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_TRN_ACK_MASK                  0x01000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF12_RCV_VALID_MASK                0x02000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_TRN_ACK_MASK                  0x04000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF13_RCV_VALID_MASK                0x08000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_TRN_ACK_MASK                  0x10000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF14_RCV_VALID_MASK                0x20000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_TRN_ACK_MASK                  0x40000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW1__VF15_RCV_VALID_MASK                0x80000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_TRN_ACK__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_RCV_VALID__SHIFT              0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_TRN_ACK__SHIFT                0x2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_RCV_VALID__SHIFT              0x3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_TRN_ACK__SHIFT                0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_RCV_VALID__SHIFT              0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_TRN_ACK__SHIFT                0x6
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_RCV_VALID__SHIFT              0x7
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_TRN_ACK__SHIFT                0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_RCV_VALID__SHIFT              0x9
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_TRN_ACK__SHIFT                0xa
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_RCV_VALID__SHIFT              0xb
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_TRN_ACK__SHIFT                0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_RCV_VALID__SHIFT              0xd
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_TRN_ACK__SHIFT                0xe
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_RCV_VALID__SHIFT              0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_TRN_ACK__SHIFT                0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_RCV_VALID__SHIFT              0x11
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_TRN_ACK__SHIFT                0x12
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_RCV_VALID__SHIFT              0x13
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_TRN_ACK__SHIFT                0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_RCV_VALID__SHIFT              0x15
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_TRN_ACK__SHIFT                0x16
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_RCV_VALID__SHIFT              0x17
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_TRN_ACK__SHIFT                0x18
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_RCV_VALID__SHIFT              0x19
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_TRN_ACK__SHIFT                0x1a
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_RCV_VALID__SHIFT              0x1b
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_TRN_ACK__SHIFT                0x1c
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_RCV_VALID__SHIFT              0x1d
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK__SHIFT                  0x1e
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID__SHIFT                0x1f
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_TRN_ACK_MASK                  0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF16_RCV_VALID_MASK                0x00000002L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_TRN_ACK_MASK                  0x00000004L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF17_RCV_VALID_MASK                0x00000008L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_TRN_ACK_MASK                  0x00000010L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF18_RCV_VALID_MASK                0x00000020L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_TRN_ACK_MASK                  0x00000040L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF19_RCV_VALID_MASK                0x00000080L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_TRN_ACK_MASK                  0x00000100L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF20_RCV_VALID_MASK                0x00000200L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_TRN_ACK_MASK                  0x00000400L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF21_RCV_VALID_MASK                0x00000800L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_TRN_ACK_MASK                  0x00001000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF22_RCV_VALID_MASK                0x00002000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_TRN_ACK_MASK                  0x00004000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF23_RCV_VALID_MASK                0x00008000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_TRN_ACK_MASK                  0x00010000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF24_RCV_VALID_MASK                0x00020000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_TRN_ACK_MASK                  0x00040000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF25_RCV_VALID_MASK                0x00080000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_TRN_ACK_MASK                  0x00100000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF26_RCV_VALID_MASK                0x00200000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_TRN_ACK_MASK                  0x00400000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF27_RCV_VALID_MASK                0x00800000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_TRN_ACK_MASK                  0x01000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF28_RCV_VALID_MASK                0x02000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_TRN_ACK_MASK                  0x04000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF29_RCV_VALID_MASK                0x08000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_TRN_ACK_MASK                  0x10000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__VF30_RCV_VALID_MASK                0x20000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_TRN_ACK_MASK                    0x40000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_HVVM_MBOX_DW2__PF_RCV_VALID_MASK                  0x80000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE__SHIFT               0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED__SHIFT                0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_AVAILABLE_MASK                 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_TOTAL_FB__TOTAL_FB_CONSUMED_MASK                  0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__LFB_REGION__SHIFT                         0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__MAX_REGION__SHIFT                         0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__LFB_REGION_MASK                           0x0000000FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_REGION__MAX_REGION_MASK                           0x000000F0L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_VF__SHIFT  0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_PF__SHIFT  0x1f
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_VF_MASK  0x7FFFFFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_P2P_OVER_XGMI_ENABLE__P2P_OVER_XGMI_ENABLE_PF_MASK  0x80000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS0__SCH0_OFFSET__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS0__SCH1_OFFSET__SHIFT                      0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS0__SCH2_OFFSET__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS0__SCH3_OFFSET__SHIFT                      0x18
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS0__SCH0_OFFSET_MASK                        0x000000FFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS0__SCH1_OFFSET_MASK                        0x0000FF00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS0__SCH2_OFFSET_MASK                        0x00FF0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS0__SCH3_OFFSET_MASK                        0xFF000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__SCH4_OFFSET__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__SCH5_OFFSET__SHIFT                      0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__SCH6_OFFSET__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__SCH7_OFFSET__SHIFT                      0x18
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__SCH4_OFFSET_MASK                        0x000000FFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__SCH5_OFFSET_MASK                        0x0000FF00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__SCH6_OFFSET_MASK                        0x00FF0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS1__SCH7_OFFSET_MASK                        0xFF000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__SCH8_OFFSET__SHIFT                      0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__SCH9_OFFSET__SHIFT                      0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__SCH10_OFFSET__SHIFT                     0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__SCH11_OFFSET__SHIFT                     0x18
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__SCH8_OFFSET_MASK                        0x000000FFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__SCH9_OFFSET_MASK                        0x0000FF00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__SCH10_OFFSET_MASK                       0x00FF0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS2__SCH11_OFFSET_MASK                       0xFF000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__SCH12_OFFSET__SHIFT                     0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__SCH13_OFFSET__SHIFT                     0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__SCH14_OFFSET__SHIFT                     0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__SCH15_OFFSET__SHIFT                     0x18
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__SCH12_OFFSET_MASK                       0x000000FFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__SCH13_OFFSET_MASK                       0x0000FF00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__SCH14_OFFSET_MASK                       0x00FF0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS3__SCH15_OFFSET_MASK                       0xFF000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__SCH16_OFFSET__SHIFT                     0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__SCH17_OFFSET__SHIFT                     0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__SCH18_OFFSET__SHIFT                     0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__SCH19_OFFSET__SHIFT                     0x18
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__SCH16_OFFSET_MASK                       0x000000FFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__SCH17_OFFSET_MASK                       0x0000FF00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__SCH18_OFFSET_MASK                       0x00FF0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_OFFSETS4__SCH19_OFFSET_MASK                       0xFF000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW0__DW0__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW0__DW0_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW1__DW1__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW1__DW1_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW2__DW2__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW2__DW2_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW3__DW3__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW3__DW3_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW4__DW4__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW4__DW4_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW5__DW5__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW5__DW5_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW6
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW6__DW6__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW6__DW6_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW7
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW7__DW7__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW7__DW7_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW8__DW8__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH0_DW8__DW8_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW0__DW0__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW0__DW0_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW1__DW1__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW1__DW1_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW2__DW2__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW2__DW2_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW3__DW3__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW3__DW3_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW4__DW4__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW4__DW4_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW5__DW5__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW5__DW5_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW6
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW6__DW6__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW6__DW6_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW7
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW7__DW7__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW7__DW7_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW8__DW8__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH1_DW8__DW8_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW0__DW0__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW0__DW0_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW1__DW1__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW1__DW1_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW2__DW2__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW2__DW2_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW3__DW3__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW3__DW3_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW4__DW4__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW4__DW4_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW5__DW5__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW5__DW5_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW6
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW6__DW6__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW6__DW6_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW7
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW7__DW7__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW7__DW7_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW8__DW8__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH2_DW8__DW8_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW0__DW0__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW0__DW0_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW1__DW1__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW1__DW1_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW2__DW2__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW2__DW2_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW3__DW3__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW3__DW3_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW4__DW4__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW4__DW4_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW5__DW5__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW5__DW5_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW6
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW6__DW6__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW6__DW6_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW7
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW7__DW7__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW7__DW7_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW8__DW8__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH3_DW8__DW8_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW0__DW0__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW0__DW0_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW1__DW1__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW1__DW1_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW2__DW2__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW2__DW2_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW3__DW3__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW3__DW3_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW4__DW4__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW4__DW4_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW5__DW5__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW5__DW5_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW6
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW6__DW6__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW6__DW6_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW7
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW7__DW7__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW7__DW7_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW8__DW8__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH4_DW8__DW8_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW0__DW0__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW0__DW0_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW1__DW1__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW1__DW1_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW2__DW2__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW2__DW2_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW3__DW3__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW3__DW3_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW4__DW4__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW4__DW4_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW5__DW5__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW5__DW5_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW6
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW6__DW6__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW6__DW6_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW7
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW7__DW7__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW7__DW7_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW8__DW8__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH5_DW8__DW8_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW0__DW0__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW0__DW0_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW1__DW1__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW1__DW1_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW2__DW2__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW2__DW2_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW3__DW3__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW3__DW3_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW4__DW4__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW4__DW4_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW5__DW5__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW5__DW5_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW6
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW6__DW6__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW6__DW6_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW7
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW7__DW7__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW7__DW7_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW8__DW8__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH6_DW8__DW8_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW0__DW0__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW0__DW0_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW1__DW1__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW1__DW1_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW2__DW2__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW2__DW2_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW3__DW3__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW3__DW3_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW4__DW4__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW4__DW4_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW5__DW5__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW5__DW5_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW6
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW6__DW6__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW6__DW6_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW7
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW7__DW7__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW7__DW7_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW8__DW8__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH7_DW8__DW8_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW0__DW0__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW0__DW0_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW1__DW1__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW1__DW1_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW2__DW2__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW2__DW2_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW3__DW3__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW3__DW3_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW4__DW4__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW4__DW4_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW5__DW5__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW5__DW5_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW6
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW6__DW6__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW6__DW6_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW7
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW7__DW7__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW7__DW7_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW8__DW8__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH8_DW8__DW8_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW0__DW0__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW0__DW0_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW1__DW1__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW1__DW1_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW2__DW2__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW2__DW2_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW3__DW3__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW3__DW3_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW4__DW4__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW4__DW4_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW5__DW5__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW5__DW5_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW6
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW6__DW6__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW6__DW6_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW7
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW7__DW7__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW7__DW7_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW8__DW8__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH9_DW8__DW8_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW0__DW0__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW0__DW0_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW1__DW1__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW1__DW1_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW2__DW2__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW2__DW2_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW3__DW3__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW3__DW3_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW4__DW4__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW4__DW4_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW5__DW5__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW5__DW5_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW6
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW6__DW6__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW6__DW6_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW7
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW7__DW7__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW7__DW7_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW8__DW8__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH10_DW8__DW8_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW0__DW0__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW0__DW0_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW1__DW1__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW1__DW1_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW2__DW2__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW2__DW2_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW3__DW3__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW3__DW3_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW4__DW4__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW4__DW4_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW5__DW5__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW5__DW5_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW6
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW6__DW6__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW6__DW6_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW7
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW7__DW7__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW7__DW7_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW8__DW8__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH11_DW8__DW8_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW0__DW0__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW0__DW0_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW1__DW1__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW1__DW1_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW2__DW2__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW2__DW2_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW3__DW3__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW3__DW3_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW4__DW4__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW4__DW4_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW5__DW5__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW5__DW5_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW6
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW6__DW6__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW6__DW6_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW7
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW7__DW7__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW7__DW7_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW8__DW8__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH12_DW8__DW8_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW0__DW0__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW0__DW0_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW1__DW1__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW1__DW1_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW2__DW2__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW2__DW2_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW3__DW3__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW3__DW3_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW4__DW4__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW4__DW4_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW5__DW5__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW5__DW5_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW6
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW6__DW6__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW6__DW6_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW7
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW7__DW7__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW7__DW7_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW8__DW8__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH13_DW8__DW8_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW0__DW0__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW0__DW0_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW1__DW1__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW1__DW1_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW2__DW2__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW2__DW2_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW3__DW3__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW3__DW3_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW4__DW4__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW4__DW4_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW5__DW5__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW5__DW5_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW6
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW6__DW6__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW6__DW6_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW7
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW7__DW7__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW7__DW7_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW8__DW8__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH14_DW8__DW8_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW0__DW0__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW0__DW0_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW1__DW1__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW1__DW1_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW2__DW2__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW2__DW2_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW3__DW3__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW3__DW3_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW4__DW4__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW4__DW4_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW5__DW5__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW5__DW5_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW6
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW6__DW6__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW6__DW6_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW7
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW7__DW7__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW7__DW7_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW8__DW8__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH15_DW8__DW8_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW0__DW0__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW0__DW0_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW1__DW1__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW1__DW1_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW2__DW2__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW2__DW2_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW3__DW3__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW3__DW3_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW4__DW4__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW4__DW4_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW5__DW5__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW5__DW5_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW6
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW6__DW6__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW6__DW6_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW7
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW7__DW7__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW7__DW7_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW8__DW8__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH16_DW8__DW8_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW0__DW0__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW0__DW0_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW1__DW1__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW1__DW1_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW2__DW2__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW2__DW2_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW3__DW3__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW3__DW3_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW4__DW4__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW4__DW4_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW5__DW5__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW5__DW5_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW6
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW6__DW6__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW6__DW6_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW7
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW7__DW7__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW7__DW7_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW8__DW8__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH17_DW8__DW8_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW0__DW0__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW0__DW0_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW1__DW1__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW1__DW1_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW2__DW2__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW2__DW2_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW3__DW3__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW3__DW3_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW4__DW4__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW4__DW4_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW5__DW5__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW5__DW5_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW6
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW6__DW6__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW6__DW6_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW7
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW7__DW7__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW7__DW7_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW8__DW8__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH18_DW8__DW8_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW0__DW0__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW0__DW0_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW1__DW1__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW1__DW1_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW2__DW2__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW2__DW2_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW3__DW3__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW3__DW3_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW4__DW4__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW4__DW4_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW5__DW5__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW5__DW5_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW6
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW6__DW6__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW6__DW6_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW7
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW7__DW7__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW7__DW7_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW8__DW8__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_SCH19_DW8__DW8_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_0_CMD_COMPLETE_INTR_EN__SHIFT  0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_0_HANG_SELF_RECOVERED_INTR_EN__SHIFT  0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_0_HANG_NEED_FLR_INTR_EN__SHIFT  0x2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_0_VM_BUSY_TRANSITION_INTR_EN__SHIFT  0x3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_1_CMD_COMPLETE_INTR_EN__SHIFT  0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_1_HANG_SELF_RECOVERED_INTR_EN__SHIFT  0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_1_HANG_NEED_FLR_INTR_EN__SHIFT  0x6
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_1_VM_BUSY_TRANSITION_INTR_EN__SHIFT  0x7
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_2_CMD_COMPLETE_INTR_EN__SHIFT  0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_2_HANG_SELF_RECOVERED_INTR_EN__SHIFT  0x9
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_2_HANG_NEED_FLR_INTR_EN__SHIFT  0xa
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_2_VM_BUSY_TRANSITION_INTR_EN__SHIFT  0xb
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_3_CMD_COMPLETE_INTR_EN__SHIFT  0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_3_HANG_SELF_RECOVERED_INTR_EN__SHIFT  0xd
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_3_HANG_NEED_FLR_INTR_EN__SHIFT  0xe
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_3_VM_BUSY_TRANSITION_INTR_EN__SHIFT  0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_4_CMD_COMPLETE_INTR_EN__SHIFT  0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_4_HANG_SELF_RECOVERED_INTR_EN__SHIFT  0x11
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_4_HANG_NEED_FLR_INTR_EN__SHIFT  0x12
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_4_VM_BUSY_TRANSITION_INTR_EN__SHIFT  0x13
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_5_CMD_COMPLETE_INTR_EN__SHIFT  0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_5_HANG_SELF_RECOVERED_INTR_EN__SHIFT  0x15
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_5_HANG_NEED_FLR_INTR_EN__SHIFT  0x16
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_5_VM_BUSY_TRANSITION_INTR_EN__SHIFT  0x17
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_6_CMD_COMPLETE_INTR_EN__SHIFT  0x18
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_6_HANG_SELF_RECOVERED_INTR_EN__SHIFT  0x19
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_6_HANG_NEED_FLR_INTR_EN__SHIFT  0x1a
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_6_VM_BUSY_TRANSITION_INTR_EN__SHIFT  0x1b
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_7_CMD_COMPLETE_INTR_EN__SHIFT  0x1c
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_7_HANG_SELF_RECOVERED_INTR_EN__SHIFT  0x1d
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_7_HANG_NEED_FLR_INTR_EN__SHIFT  0x1e
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_7_VM_BUSY_TRANSITION_INTR_EN__SHIFT  0x1f
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_0_CMD_COMPLETE_INTR_EN_MASK  0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_0_HANG_SELF_RECOVERED_INTR_EN_MASK  0x00000002L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_0_HANG_NEED_FLR_INTR_EN_MASK  0x00000004L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_0_VM_BUSY_TRANSITION_INTR_EN_MASK  0x00000008L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_1_CMD_COMPLETE_INTR_EN_MASK  0x00000010L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_1_HANG_SELF_RECOVERED_INTR_EN_MASK  0x00000020L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_1_HANG_NEED_FLR_INTR_EN_MASK  0x00000040L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_1_VM_BUSY_TRANSITION_INTR_EN_MASK  0x00000080L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_2_CMD_COMPLETE_INTR_EN_MASK  0x00000100L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_2_HANG_SELF_RECOVERED_INTR_EN_MASK  0x00000200L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_2_HANG_NEED_FLR_INTR_EN_MASK  0x00000400L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_2_VM_BUSY_TRANSITION_INTR_EN_MASK  0x00000800L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_3_CMD_COMPLETE_INTR_EN_MASK  0x00001000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_3_HANG_SELF_RECOVERED_INTR_EN_MASK  0x00002000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_3_HANG_NEED_FLR_INTR_EN_MASK  0x00004000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_3_VM_BUSY_TRANSITION_INTR_EN_MASK  0x00008000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_4_CMD_COMPLETE_INTR_EN_MASK  0x00010000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_4_HANG_SELF_RECOVERED_INTR_EN_MASK  0x00020000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_4_HANG_NEED_FLR_INTR_EN_MASK  0x00040000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_4_VM_BUSY_TRANSITION_INTR_EN_MASK  0x00080000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_5_CMD_COMPLETE_INTR_EN_MASK  0x00100000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_5_HANG_SELF_RECOVERED_INTR_EN_MASK  0x00200000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_5_HANG_NEED_FLR_INTR_EN_MASK  0x00400000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_5_VM_BUSY_TRANSITION_INTR_EN_MASK  0x00800000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_6_CMD_COMPLETE_INTR_EN_MASK  0x01000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_6_HANG_SELF_RECOVERED_INTR_EN_MASK  0x02000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_6_HANG_NEED_FLR_INTR_EN_MASK  0x04000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_6_VM_BUSY_TRANSITION_INTR_EN_MASK  0x08000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_7_CMD_COMPLETE_INTR_EN_MASK  0x10000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_7_HANG_SELF_RECOVERED_INTR_EN_MASK  0x20000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_7_HANG_NEED_FLR_INTR_EN_MASK  0x40000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_ENABLE__ENG_7_VM_BUSY_TRANSITION_INTR_EN_MASK  0x80000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_8_CMD_COMPLETE_INTR_EN__SHIFT  0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_8_HANG_SELF_RECOVERED_INTR_EN__SHIFT  0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_8_HANG_NEED_FLR_INTR_EN__SHIFT  0x2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_8_VM_BUSY_TRANSITION_INTR_EN__SHIFT  0x3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_9_CMD_COMPLETE_INTR_EN__SHIFT  0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_9_HANG_SELF_RECOVERED_INTR_EN__SHIFT  0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_9_HANG_NEED_FLR_INTR_EN__SHIFT  0x6
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_9_VM_BUSY_TRANSITION_INTR_EN__SHIFT  0x7
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_10_CMD_COMPLETE_INTR_EN__SHIFT  0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_10_HANG_SELF_RECOVERED_INTR_EN__SHIFT  0x9
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_10_HANG_NEED_FLR_INTR_EN__SHIFT  0xa
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_10_VM_BUSY_TRANSITION_INTR_EN__SHIFT  0xb
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_11_CMD_COMPLETE_INTR_EN__SHIFT  0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_11_HANG_SELF_RECOVERED_INTR_EN__SHIFT  0xd
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_11_HANG_NEED_FLR_INTR_EN__SHIFT  0xe
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_11_VM_BUSY_TRANSITION_INTR_EN__SHIFT  0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_12_CMD_COMPLETE_INTR_EN__SHIFT  0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_12_HANG_SELF_RECOVERED_INTR_EN__SHIFT  0x11
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_12_HANG_NEED_FLR_INTR_EN__SHIFT  0x12
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_12_VM_BUSY_TRANSITION_INTR_EN__SHIFT  0x13
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_13_CMD_COMPLETE_INTR_EN__SHIFT  0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_13_HANG_SELF_RECOVERED_INTR_EN__SHIFT  0x15
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_13_HANG_NEED_FLR_INTR_EN__SHIFT  0x16
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_13_VM_BUSY_TRANSITION_INTR_EN__SHIFT  0x17
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_14_CMD_COMPLETE_INTR_EN__SHIFT  0x18
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_14_HANG_SELF_RECOVERED_INTR_EN__SHIFT  0x19
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_14_HANG_NEED_FLR_INTR_EN__SHIFT  0x1a
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_14_VM_BUSY_TRANSITION_INTR_EN__SHIFT  0x1b
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_15_CMD_COMPLETE_INTR_EN__SHIFT  0x1c
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_15_HANG_SELF_RECOVERED_INTR_EN__SHIFT  0x1d
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_15_HANG_NEED_FLR_INTR_EN__SHIFT  0x1e
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_15_VM_BUSY_TRANSITION_INTR_EN__SHIFT  0x1f
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_8_CMD_COMPLETE_INTR_EN_MASK  0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_8_HANG_SELF_RECOVERED_INTR_EN_MASK  0x00000002L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_8_HANG_NEED_FLR_INTR_EN_MASK  0x00000004L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_8_VM_BUSY_TRANSITION_INTR_EN_MASK  0x00000008L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_9_CMD_COMPLETE_INTR_EN_MASK  0x00000010L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_9_HANG_SELF_RECOVERED_INTR_EN_MASK  0x00000020L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_9_HANG_NEED_FLR_INTR_EN_MASK  0x00000040L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_9_VM_BUSY_TRANSITION_INTR_EN_MASK  0x00000080L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_10_CMD_COMPLETE_INTR_EN_MASK  0x00000100L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_10_HANG_SELF_RECOVERED_INTR_EN_MASK  0x00000200L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_10_HANG_NEED_FLR_INTR_EN_MASK  0x00000400L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_10_VM_BUSY_TRANSITION_INTR_EN_MASK  0x00000800L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_11_CMD_COMPLETE_INTR_EN_MASK  0x00001000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_11_HANG_SELF_RECOVERED_INTR_EN_MASK  0x00002000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_11_HANG_NEED_FLR_INTR_EN_MASK  0x00004000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_11_VM_BUSY_TRANSITION_INTR_EN_MASK  0x00008000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_12_CMD_COMPLETE_INTR_EN_MASK  0x00010000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_12_HANG_SELF_RECOVERED_INTR_EN_MASK  0x00020000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_12_HANG_NEED_FLR_INTR_EN_MASK  0x00040000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_12_VM_BUSY_TRANSITION_INTR_EN_MASK  0x00080000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_13_CMD_COMPLETE_INTR_EN_MASK  0x00100000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_13_HANG_SELF_RECOVERED_INTR_EN_MASK  0x00200000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_13_HANG_NEED_FLR_INTR_EN_MASK  0x00400000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_13_VM_BUSY_TRANSITION_INTR_EN_MASK  0x00800000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_14_CMD_COMPLETE_INTR_EN_MASK  0x01000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_14_HANG_SELF_RECOVERED_INTR_EN_MASK  0x02000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_14_HANG_NEED_FLR_INTR_EN_MASK  0x04000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_14_VM_BUSY_TRANSITION_INTR_EN_MASK  0x08000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_15_CMD_COMPLETE_INTR_EN_MASK  0x10000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_15_HANG_SELF_RECOVERED_INTR_EN_MASK  0x20000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_15_HANG_NEED_FLR_INTR_EN_MASK  0x40000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_ENABLE__ENG_15_VM_BUSY_TRANSITION_INTR_EN_MASK  0x80000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_16_CMD_COMPLETE_INTR_EN__SHIFT  0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_16_HANG_SELF_RECOVERED_INTR_EN__SHIFT  0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_16_HANG_NEED_FLR_INTR_EN__SHIFT  0x2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_16_VM_BUSY_TRANSITION_INTR_EN__SHIFT  0x3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_17_CMD_COMPLETE_INTR_EN__SHIFT  0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_17_HANG_SELF_RECOVERED_INTR_EN__SHIFT  0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_17_HANG_NEED_FLR_INTR_EN__SHIFT  0x6
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_17_VM_BUSY_TRANSITION_INTR_EN__SHIFT  0x7
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_18_CMD_COMPLETE_INTR_EN__SHIFT  0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_18_HANG_SELF_RECOVERED_INTR_EN__SHIFT  0x9
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_18_HANG_NEED_FLR_INTR_EN__SHIFT  0xa
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_18_VM_BUSY_TRANSITION_INTR_EN__SHIFT  0xb
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_19_CMD_COMPLETE_INTR_EN__SHIFT  0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_19_HANG_SELF_RECOVERED_INTR_EN__SHIFT  0xd
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_19_HANG_NEED_FLR_INTR_EN__SHIFT  0xe
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_19_VM_BUSY_TRANSITION_INTR_EN__SHIFT  0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_20_CMD_COMPLETE_INTR_EN__SHIFT  0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_20_HANG_SELF_RECOVERED_INTR_EN__SHIFT  0x11
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_20_HANG_NEED_FLR_INTR_EN__SHIFT  0x12
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_20_VM_BUSY_TRANSITION_INTR_EN__SHIFT  0x13
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_21_CMD_COMPLETE_INTR_EN__SHIFT  0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_21_HANG_SELF_RECOVERED_INTR_EN__SHIFT  0x15
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_21_HANG_NEED_FLR_INTR_EN__SHIFT  0x16
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_21_VM_BUSY_TRANSITION_INTR_EN__SHIFT  0x17
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_22_CMD_COMPLETE_INTR_EN__SHIFT  0x18
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_22_HANG_SELF_RECOVERED_INTR_EN__SHIFT  0x19
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_22_HANG_NEED_FLR_INTR_EN__SHIFT  0x1a
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_22_VM_BUSY_TRANSITION_INTR_EN__SHIFT  0x1b
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_23_CMD_COMPLETE_INTR_EN__SHIFT  0x1c
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_23_HANG_SELF_RECOVERED_INTR_EN__SHIFT  0x1d
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_23_HANG_NEED_FLR_INTR_EN__SHIFT  0x1e
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_23_VM_BUSY_TRANSITION_INTR_EN__SHIFT  0x1f
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_16_CMD_COMPLETE_INTR_EN_MASK  0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_16_HANG_SELF_RECOVERED_INTR_EN_MASK  0x00000002L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_16_HANG_NEED_FLR_INTR_EN_MASK  0x00000004L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_16_VM_BUSY_TRANSITION_INTR_EN_MASK  0x00000008L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_17_CMD_COMPLETE_INTR_EN_MASK  0x00000010L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_17_HANG_SELF_RECOVERED_INTR_EN_MASK  0x00000020L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_17_HANG_NEED_FLR_INTR_EN_MASK  0x00000040L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_17_VM_BUSY_TRANSITION_INTR_EN_MASK  0x00000080L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_18_CMD_COMPLETE_INTR_EN_MASK  0x00000100L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_18_HANG_SELF_RECOVERED_INTR_EN_MASK  0x00000200L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_18_HANG_NEED_FLR_INTR_EN_MASK  0x00000400L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_18_VM_BUSY_TRANSITION_INTR_EN_MASK  0x00000800L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_19_CMD_COMPLETE_INTR_EN_MASK  0x00001000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_19_HANG_SELF_RECOVERED_INTR_EN_MASK  0x00002000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_19_HANG_NEED_FLR_INTR_EN_MASK  0x00004000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_19_VM_BUSY_TRANSITION_INTR_EN_MASK  0x00008000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_20_CMD_COMPLETE_INTR_EN_MASK  0x00010000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_20_HANG_SELF_RECOVERED_INTR_EN_MASK  0x00020000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_20_HANG_NEED_FLR_INTR_EN_MASK  0x00040000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_20_VM_BUSY_TRANSITION_INTR_EN_MASK  0x00080000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_21_CMD_COMPLETE_INTR_EN_MASK  0x00100000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_21_HANG_SELF_RECOVERED_INTR_EN_MASK  0x00200000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_21_HANG_NEED_FLR_INTR_EN_MASK  0x00400000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_21_VM_BUSY_TRANSITION_INTR_EN_MASK  0x00800000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_22_CMD_COMPLETE_INTR_EN_MASK  0x01000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_22_HANG_SELF_RECOVERED_INTR_EN_MASK  0x02000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_22_HANG_NEED_FLR_INTR_EN_MASK  0x04000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_22_VM_BUSY_TRANSITION_INTR_EN_MASK  0x08000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_23_CMD_COMPLETE_INTR_EN_MASK  0x10000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_23_HANG_SELF_RECOVERED_INTR_EN_MASK  0x20000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_23_HANG_NEED_FLR_INTR_EN_MASK  0x40000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_ENABLE__ENG_23_VM_BUSY_TRANSITION_INTR_EN_MASK  0x80000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_24_CMD_COMPLETE_INTR_EN__SHIFT  0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_24_HANG_SELF_RECOVERED_INTR_EN__SHIFT  0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_24_HANG_NEED_FLR_INTR_EN__SHIFT  0x2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_24_VM_BUSY_TRANSITION_INTR_EN__SHIFT  0x3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_25_CMD_COMPLETE_INTR_EN__SHIFT  0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_25_HANG_SELF_RECOVERED_INTR_EN__SHIFT  0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_25_HANG_NEED_FLR_INTR_EN__SHIFT  0x6
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_25_VM_BUSY_TRANSITION_INTR_EN__SHIFT  0x7
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_26_CMD_COMPLETE_INTR_EN__SHIFT  0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_26_HANG_SELF_RECOVERED_INTR_EN__SHIFT  0x9
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_26_HANG_NEED_FLR_INTR_EN__SHIFT  0xa
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_26_VM_BUSY_TRANSITION_INTR_EN__SHIFT  0xb
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_27_CMD_COMPLETE_INTR_EN__SHIFT  0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_27_HANG_SELF_RECOVERED_INTR_EN__SHIFT  0xd
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_27_HANG_NEED_FLR_INTR_EN__SHIFT  0xe
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_27_VM_BUSY_TRANSITION_INTR_EN__SHIFT  0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_28_CMD_COMPLETE_INTR_EN__SHIFT  0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_28_HANG_SELF_RECOVERED_INTR_EN__SHIFT  0x11
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_28_HANG_NEED_FLR_INTR_EN__SHIFT  0x12
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_28_VM_BUSY_TRANSITION_INTR_EN__SHIFT  0x13
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_29_CMD_COMPLETE_INTR_EN__SHIFT  0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_29_HANG_SELF_RECOVERED_INTR_EN__SHIFT  0x15
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_29_HANG_NEED_FLR_INTR_EN__SHIFT  0x16
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_29_VM_BUSY_TRANSITION_INTR_EN__SHIFT  0x17
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_30_CMD_COMPLETE_INTR_EN__SHIFT  0x18
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_30_HANG_SELF_RECOVERED_INTR_EN__SHIFT  0x19
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_30_HANG_NEED_FLR_INTR_EN__SHIFT  0x1a
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_30_VM_BUSY_TRANSITION_INTR_EN__SHIFT  0x1b
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_31_CMD_COMPLETE_INTR_EN__SHIFT  0x1c
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_31_HANG_SELF_RECOVERED_INTR_EN__SHIFT  0x1d
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_31_HANG_NEED_FLR_INTR_EN__SHIFT  0x1e
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_31_VM_BUSY_TRANSITION_INTR_EN__SHIFT  0x1f
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_24_CMD_COMPLETE_INTR_EN_MASK  0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_24_HANG_SELF_RECOVERED_INTR_EN_MASK  0x00000002L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_24_HANG_NEED_FLR_INTR_EN_MASK  0x00000004L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_24_VM_BUSY_TRANSITION_INTR_EN_MASK  0x00000008L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_25_CMD_COMPLETE_INTR_EN_MASK  0x00000010L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_25_HANG_SELF_RECOVERED_INTR_EN_MASK  0x00000020L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_25_HANG_NEED_FLR_INTR_EN_MASK  0x00000040L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_25_VM_BUSY_TRANSITION_INTR_EN_MASK  0x00000080L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_26_CMD_COMPLETE_INTR_EN_MASK  0x00000100L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_26_HANG_SELF_RECOVERED_INTR_EN_MASK  0x00000200L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_26_HANG_NEED_FLR_INTR_EN_MASK  0x00000400L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_26_VM_BUSY_TRANSITION_INTR_EN_MASK  0x00000800L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_27_CMD_COMPLETE_INTR_EN_MASK  0x00001000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_27_HANG_SELF_RECOVERED_INTR_EN_MASK  0x00002000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_27_HANG_NEED_FLR_INTR_EN_MASK  0x00004000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_27_VM_BUSY_TRANSITION_INTR_EN_MASK  0x00008000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_28_CMD_COMPLETE_INTR_EN_MASK  0x00010000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_28_HANG_SELF_RECOVERED_INTR_EN_MASK  0x00020000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_28_HANG_NEED_FLR_INTR_EN_MASK  0x00040000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_28_VM_BUSY_TRANSITION_INTR_EN_MASK  0x00080000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_29_CMD_COMPLETE_INTR_EN_MASK  0x00100000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_29_HANG_SELF_RECOVERED_INTR_EN_MASK  0x00200000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_29_HANG_NEED_FLR_INTR_EN_MASK  0x00400000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_29_VM_BUSY_TRANSITION_INTR_EN_MASK  0x00800000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_30_CMD_COMPLETE_INTR_EN_MASK  0x01000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_30_HANG_SELF_RECOVERED_INTR_EN_MASK  0x02000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_30_HANG_NEED_FLR_INTR_EN_MASK  0x04000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_30_VM_BUSY_TRANSITION_INTR_EN_MASK  0x08000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_31_CMD_COMPLETE_INTR_EN_MASK  0x10000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_31_HANG_SELF_RECOVERED_INTR_EN_MASK  0x20000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_31_HANG_NEED_FLR_INTR_EN_MASK  0x40000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_ENABLE__ENG_31_VM_BUSY_TRANSITION_INTR_EN_MASK  0x80000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_0_CMD_COMPLETE_INTR_STATUS__SHIFT  0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_0_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT  0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_0_HANG_NEED_FLR_INTR_STATUS__SHIFT  0x2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_0_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT  0x3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_1_CMD_COMPLETE_INTR_STATUS__SHIFT  0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_1_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT  0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_1_HANG_NEED_FLR_INTR_STATUS__SHIFT  0x6
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_1_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT  0x7
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_2_CMD_COMPLETE_INTR_STATUS__SHIFT  0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_2_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT  0x9
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_2_HANG_NEED_FLR_INTR_STATUS__SHIFT  0xa
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_2_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT  0xb
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_3_CMD_COMPLETE_INTR_STATUS__SHIFT  0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_3_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT  0xd
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_3_HANG_NEED_FLR_INTR_STATUS__SHIFT  0xe
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_3_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT  0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_4_CMD_COMPLETE_INTR_STATUS__SHIFT  0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_4_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT  0x11
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_4_HANG_NEED_FLR_INTR_STATUS__SHIFT  0x12
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_4_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT  0x13
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_5_CMD_COMPLETE_INTR_STATUS__SHIFT  0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_5_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT  0x15
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_5_HANG_NEED_FLR_INTR_STATUS__SHIFT  0x16
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_5_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT  0x17
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_6_CMD_COMPLETE_INTR_STATUS__SHIFT  0x18
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_6_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT  0x19
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_6_HANG_NEED_FLR_INTR_STATUS__SHIFT  0x1a
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_6_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT  0x1b
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_7_CMD_COMPLETE_INTR_STATUS__SHIFT  0x1c
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_7_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT  0x1d
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_7_HANG_NEED_FLR_INTR_STATUS__SHIFT  0x1e
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_7_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT  0x1f
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_0_CMD_COMPLETE_INTR_STATUS_MASK  0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_0_HANG_SELF_RECOVERED_INTR_STATUS_MASK  0x00000002L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_0_HANG_NEED_FLR_INTR_STATUS_MASK  0x00000004L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_0_VM_BUSY_TRANSITION_INTR_STATUS_MASK  0x00000008L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_1_CMD_COMPLETE_INTR_STATUS_MASK  0x00000010L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_1_HANG_SELF_RECOVERED_INTR_STATUS_MASK  0x00000020L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_1_HANG_NEED_FLR_INTR_STATUS_MASK  0x00000040L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_1_VM_BUSY_TRANSITION_INTR_STATUS_MASK  0x00000080L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_2_CMD_COMPLETE_INTR_STATUS_MASK  0x00000100L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_2_HANG_SELF_RECOVERED_INTR_STATUS_MASK  0x00000200L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_2_HANG_NEED_FLR_INTR_STATUS_MASK  0x00000400L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_2_VM_BUSY_TRANSITION_INTR_STATUS_MASK  0x00000800L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_3_CMD_COMPLETE_INTR_STATUS_MASK  0x00001000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_3_HANG_SELF_RECOVERED_INTR_STATUS_MASK  0x00002000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_3_HANG_NEED_FLR_INTR_STATUS_MASK  0x00004000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_3_VM_BUSY_TRANSITION_INTR_STATUS_MASK  0x00008000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_4_CMD_COMPLETE_INTR_STATUS_MASK  0x00010000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_4_HANG_SELF_RECOVERED_INTR_STATUS_MASK  0x00020000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_4_HANG_NEED_FLR_INTR_STATUS_MASK  0x00040000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_4_VM_BUSY_TRANSITION_INTR_STATUS_MASK  0x00080000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_5_CMD_COMPLETE_INTR_STATUS_MASK  0x00100000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_5_HANG_SELF_RECOVERED_INTR_STATUS_MASK  0x00200000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_5_HANG_NEED_FLR_INTR_STATUS_MASK  0x00400000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_5_VM_BUSY_TRANSITION_INTR_STATUS_MASK  0x00800000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_6_CMD_COMPLETE_INTR_STATUS_MASK  0x01000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_6_HANG_SELF_RECOVERED_INTR_STATUS_MASK  0x02000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_6_HANG_NEED_FLR_INTR_STATUS_MASK  0x04000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_6_VM_BUSY_TRANSITION_INTR_STATUS_MASK  0x08000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_7_CMD_COMPLETE_INTR_STATUS_MASK  0x10000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_7_HANG_SELF_RECOVERED_INTR_STATUS_MASK  0x20000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_7_HANG_NEED_FLR_INTR_STATUS_MASK  0x40000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_0_7_INTR_STATUS__ENG_7_VM_BUSY_TRANSITION_INTR_STATUS_MASK  0x80000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_8_CMD_COMPLETE_INTR_STATUS__SHIFT  0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_8_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT  0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_8_HANG_NEED_FLR_INTR_STATUS__SHIFT  0x2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_8_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT  0x3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_9_CMD_COMPLETE_INTR_STATUS__SHIFT  0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_9_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT  0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_9_HANG_NEED_FLR_INTR_STATUS__SHIFT  0x6
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_9_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT  0x7
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_10_CMD_COMPLETE_INTR_STATUS__SHIFT  0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_10_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT  0x9
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_10_HANG_NEED_FLR_INTR_STATUS__SHIFT  0xa
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_10_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT  0xb
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_11_CMD_COMPLETE_INTR_STATUS__SHIFT  0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_11_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT  0xd
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_11_HANG_NEED_FLR_INTR_STATUS__SHIFT  0xe
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_11_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT  0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_12_CMD_COMPLETE_INTR_STATUS__SHIFT  0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_12_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT  0x11
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_12_HANG_NEED_FLR_INTR_STATUS__SHIFT  0x12
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_12_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT  0x13
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_13_CMD_COMPLETE_INTR_STATUS__SHIFT  0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_13_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT  0x15
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_13_HANG_NEED_FLR_INTR_STATUS__SHIFT  0x16
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_13_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT  0x17
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_14_CMD_COMPLETE_INTR_STATUS__SHIFT  0x18
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_14_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT  0x19
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_14_HANG_NEED_FLR_INTR_STATUS__SHIFT  0x1a
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_14_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT  0x1b
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_15_CMD_COMPLETE_INTR_STATUS__SHIFT  0x1c
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_15_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT  0x1d
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_15_HANG_NEED_FLR_INTR_STATUS__SHIFT  0x1e
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_15_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT  0x1f
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_8_CMD_COMPLETE_INTR_STATUS_MASK  0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_8_HANG_SELF_RECOVERED_INTR_STATUS_MASK  0x00000002L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_8_HANG_NEED_FLR_INTR_STATUS_MASK  0x00000004L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_8_VM_BUSY_TRANSITION_INTR_STATUS_MASK  0x00000008L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_9_CMD_COMPLETE_INTR_STATUS_MASK  0x00000010L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_9_HANG_SELF_RECOVERED_INTR_STATUS_MASK  0x00000020L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_9_HANG_NEED_FLR_INTR_STATUS_MASK  0x00000040L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_9_VM_BUSY_TRANSITION_INTR_STATUS_MASK  0x00000080L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_10_CMD_COMPLETE_INTR_STATUS_MASK  0x00000100L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_10_HANG_SELF_RECOVERED_INTR_STATUS_MASK  0x00000200L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_10_HANG_NEED_FLR_INTR_STATUS_MASK  0x00000400L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_10_VM_BUSY_TRANSITION_INTR_STATUS_MASK  0x00000800L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_11_CMD_COMPLETE_INTR_STATUS_MASK  0x00001000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_11_HANG_SELF_RECOVERED_INTR_STATUS_MASK  0x00002000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_11_HANG_NEED_FLR_INTR_STATUS_MASK  0x00004000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_11_VM_BUSY_TRANSITION_INTR_STATUS_MASK  0x00008000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_12_CMD_COMPLETE_INTR_STATUS_MASK  0x00010000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_12_HANG_SELF_RECOVERED_INTR_STATUS_MASK  0x00020000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_12_HANG_NEED_FLR_INTR_STATUS_MASK  0x00040000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_12_VM_BUSY_TRANSITION_INTR_STATUS_MASK  0x00080000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_13_CMD_COMPLETE_INTR_STATUS_MASK  0x00100000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_13_HANG_SELF_RECOVERED_INTR_STATUS_MASK  0x00200000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_13_HANG_NEED_FLR_INTR_STATUS_MASK  0x00400000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_13_VM_BUSY_TRANSITION_INTR_STATUS_MASK  0x00800000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_14_CMD_COMPLETE_INTR_STATUS_MASK  0x01000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_14_HANG_SELF_RECOVERED_INTR_STATUS_MASK  0x02000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_14_HANG_NEED_FLR_INTR_STATUS_MASK  0x04000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_14_VM_BUSY_TRANSITION_INTR_STATUS_MASK  0x08000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_15_CMD_COMPLETE_INTR_STATUS_MASK  0x10000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_15_HANG_SELF_RECOVERED_INTR_STATUS_MASK  0x20000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_15_HANG_NEED_FLR_INTR_STATUS_MASK  0x40000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_8_15_INTR_STATUS__ENG_15_VM_BUSY_TRANSITION_INTR_STATUS_MASK  0x80000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_16_CMD_COMPLETE_INTR_STATUS__SHIFT  0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_16_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT  0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_16_HANG_NEED_FLR_INTR_STATUS__SHIFT  0x2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_16_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT  0x3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_17_CMD_COMPLETE_INTR_STATUS__SHIFT  0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_17_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT  0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_17_HANG_NEED_FLR_INTR_STATUS__SHIFT  0x6
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_17_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT  0x7
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_18_CMD_COMPLETE_INTR_STATUS__SHIFT  0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_18_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT  0x9
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_18_HANG_NEED_FLR_INTR_STATUS__SHIFT  0xa
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_18_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT  0xb
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_19_CMD_COMPLETE_INTR_STATUS__SHIFT  0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_19_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT  0xd
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_19_HANG_NEED_FLR_INTR_STATUS__SHIFT  0xe
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_19_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT  0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_20_CMD_COMPLETE_INTR_STATUS__SHIFT  0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_20_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT  0x11
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_20_HANG_NEED_FLR_INTR_STATUS__SHIFT  0x12
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_20_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT  0x13
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_21_CMD_COMPLETE_INTR_STATUS__SHIFT  0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_21_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT  0x15
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_21_HANG_NEED_FLR_INTR_STATUS__SHIFT  0x16
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_21_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT  0x17
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_22_CMD_COMPLETE_INTR_STATUS__SHIFT  0x18
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_22_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT  0x19
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_22_HANG_NEED_FLR_INTR_STATUS__SHIFT  0x1a
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_22_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT  0x1b
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_23_CMD_COMPLETE_INTR_STATUS__SHIFT  0x1c
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_23_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT  0x1d
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_23_HANG_NEED_FLR_INTR_STATUS__SHIFT  0x1e
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_23_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT  0x1f
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_16_CMD_COMPLETE_INTR_STATUS_MASK  0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_16_HANG_SELF_RECOVERED_INTR_STATUS_MASK  0x00000002L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_16_HANG_NEED_FLR_INTR_STATUS_MASK  0x00000004L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_16_VM_BUSY_TRANSITION_INTR_STATUS_MASK  0x00000008L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_17_CMD_COMPLETE_INTR_STATUS_MASK  0x00000010L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_17_HANG_SELF_RECOVERED_INTR_STATUS_MASK  0x00000020L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_17_HANG_NEED_FLR_INTR_STATUS_MASK  0x00000040L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_17_VM_BUSY_TRANSITION_INTR_STATUS_MASK  0x00000080L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_18_CMD_COMPLETE_INTR_STATUS_MASK  0x00000100L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_18_HANG_SELF_RECOVERED_INTR_STATUS_MASK  0x00000200L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_18_HANG_NEED_FLR_INTR_STATUS_MASK  0x00000400L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_18_VM_BUSY_TRANSITION_INTR_STATUS_MASK  0x00000800L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_19_CMD_COMPLETE_INTR_STATUS_MASK  0x00001000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_19_HANG_SELF_RECOVERED_INTR_STATUS_MASK  0x00002000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_19_HANG_NEED_FLR_INTR_STATUS_MASK  0x00004000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_19_VM_BUSY_TRANSITION_INTR_STATUS_MASK  0x00008000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_20_CMD_COMPLETE_INTR_STATUS_MASK  0x00010000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_20_HANG_SELF_RECOVERED_INTR_STATUS_MASK  0x00020000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_20_HANG_NEED_FLR_INTR_STATUS_MASK  0x00040000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_20_VM_BUSY_TRANSITION_INTR_STATUS_MASK  0x00080000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_21_CMD_COMPLETE_INTR_STATUS_MASK  0x00100000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_21_HANG_SELF_RECOVERED_INTR_STATUS_MASK  0x00200000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_21_HANG_NEED_FLR_INTR_STATUS_MASK  0x00400000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_21_VM_BUSY_TRANSITION_INTR_STATUS_MASK  0x00800000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_22_CMD_COMPLETE_INTR_STATUS_MASK  0x01000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_22_HANG_SELF_RECOVERED_INTR_STATUS_MASK  0x02000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_22_HANG_NEED_FLR_INTR_STATUS_MASK  0x04000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_22_VM_BUSY_TRANSITION_INTR_STATUS_MASK  0x08000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_23_CMD_COMPLETE_INTR_STATUS_MASK  0x10000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_23_HANG_SELF_RECOVERED_INTR_STATUS_MASK  0x20000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_23_HANG_NEED_FLR_INTR_STATUS_MASK  0x40000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_16_23_INTR_STATUS__ENG_23_VM_BUSY_TRANSITION_INTR_STATUS_MASK  0x80000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_24_CMD_COMPLETE_INTR_STATUS__SHIFT  0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_24_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT  0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_24_HANG_NEED_FLR_INTR_STATUS__SHIFT  0x2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_24_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT  0x3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_25_CMD_COMPLETE_INTR_STATUS__SHIFT  0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_25_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT  0x5
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_25_HANG_NEED_FLR_INTR_STATUS__SHIFT  0x6
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_25_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT  0x7
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_26_CMD_COMPLETE_INTR_STATUS__SHIFT  0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_26_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT  0x9
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_26_HANG_NEED_FLR_INTR_STATUS__SHIFT  0xa
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_26_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT  0xb
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_27_CMD_COMPLETE_INTR_STATUS__SHIFT  0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_27_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT  0xd
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_27_HANG_NEED_FLR_INTR_STATUS__SHIFT  0xe
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_27_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT  0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_28_CMD_COMPLETE_INTR_STATUS__SHIFT  0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_28_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT  0x11
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_28_HANG_NEED_FLR_INTR_STATUS__SHIFT  0x12
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_28_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT  0x13
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_29_CMD_COMPLETE_INTR_STATUS__SHIFT  0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_29_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT  0x15
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_29_HANG_NEED_FLR_INTR_STATUS__SHIFT  0x16
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_29_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT  0x17
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_30_CMD_COMPLETE_INTR_STATUS__SHIFT  0x18
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_30_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT  0x19
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_30_HANG_NEED_FLR_INTR_STATUS__SHIFT  0x1a
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_30_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT  0x1b
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_31_CMD_COMPLETE_INTR_STATUS__SHIFT  0x1c
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_31_HANG_SELF_RECOVERED_INTR_STATUS__SHIFT  0x1d
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_31_HANG_NEED_FLR_INTR_STATUS__SHIFT  0x1e
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_31_VM_BUSY_TRANSITION_INTR_STATUS__SHIFT  0x1f
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_24_CMD_COMPLETE_INTR_STATUS_MASK  0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_24_HANG_SELF_RECOVERED_INTR_STATUS_MASK  0x00000002L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_24_HANG_NEED_FLR_INTR_STATUS_MASK  0x00000004L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_24_VM_BUSY_TRANSITION_INTR_STATUS_MASK  0x00000008L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_25_CMD_COMPLETE_INTR_STATUS_MASK  0x00000010L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_25_HANG_SELF_RECOVERED_INTR_STATUS_MASK  0x00000020L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_25_HANG_NEED_FLR_INTR_STATUS_MASK  0x00000040L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_25_VM_BUSY_TRANSITION_INTR_STATUS_MASK  0x00000080L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_26_CMD_COMPLETE_INTR_STATUS_MASK  0x00000100L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_26_HANG_SELF_RECOVERED_INTR_STATUS_MASK  0x00000200L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_26_HANG_NEED_FLR_INTR_STATUS_MASK  0x00000400L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_26_VM_BUSY_TRANSITION_INTR_STATUS_MASK  0x00000800L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_27_CMD_COMPLETE_INTR_STATUS_MASK  0x00001000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_27_HANG_SELF_RECOVERED_INTR_STATUS_MASK  0x00002000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_27_HANG_NEED_FLR_INTR_STATUS_MASK  0x00004000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_27_VM_BUSY_TRANSITION_INTR_STATUS_MASK  0x00008000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_28_CMD_COMPLETE_INTR_STATUS_MASK  0x00010000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_28_HANG_SELF_RECOVERED_INTR_STATUS_MASK  0x00020000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_28_HANG_NEED_FLR_INTR_STATUS_MASK  0x00040000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_28_VM_BUSY_TRANSITION_INTR_STATUS_MASK  0x00080000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_29_CMD_COMPLETE_INTR_STATUS_MASK  0x00100000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_29_HANG_SELF_RECOVERED_INTR_STATUS_MASK  0x00200000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_29_HANG_NEED_FLR_INTR_STATUS_MASK  0x00400000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_29_VM_BUSY_TRANSITION_INTR_STATUS_MASK  0x00800000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_30_CMD_COMPLETE_INTR_STATUS_MASK  0x01000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_30_HANG_SELF_RECOVERED_INTR_STATUS_MASK  0x02000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_30_HANG_NEED_FLR_INTR_STATUS_MASK  0x04000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_30_VM_BUSY_TRANSITION_INTR_STATUS_MASK  0x08000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_31_CMD_COMPLETE_INTR_STATUS_MASK  0x10000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_31_HANG_SELF_RECOVERED_INTR_STATUS_MASK  0x20000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_31_HANG_NEED_FLR_INTR_STATUS_MASK  0x40000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR_GPUIOV_ENG_24_31_INTR_STATUS__ENG_31_VM_BUSY_TRANSITION_INTR_STATUS_MASK  0x80000000L
+
+
+// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_bifcfgpciedecp
+//BIF_CFG_DEV0_EPF0_0_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_SPEED__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_WIDTH__SHIFT                                                       0x4
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__PM_SUPPORT__SHIFT                                                       0xa
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                 0xc
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                  0xf
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                           0x12
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                      0x13
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                      0x14
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                         0x15
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                      0x16
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__PORT_NUMBER__SHIFT                                                      0x18
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_SPEED_MASK                                                         0x0000000FL
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_WIDTH_MASK                                                         0x000003F0L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__PM_SUPPORT_MASK                                                         0x00000C00L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                   0x00007000L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__L1_EXIT_LATENCY_MASK                                                    0x00038000L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                             0x00040000L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                        0x00080000L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                        0x00100000L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                           0x00200000L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                        0x00400000L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP__PORT_NUMBER_MASK                                                        0xFF000000L
+//BIF_CFG_DEV0_EPF0_0_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__PM_CONTROL__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT                                    0x2
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                               0x3
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_DIS__SHIFT                                                        0x4
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__RETRAIN_LINK__SHIFT                                                    0x5
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                0x6
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                   0x7
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                       0x8
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                     0x9
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                       0xa
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                       0xb
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__SRIS_CLOCKING__SHIFT                                                   0xc
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__FLIT_MODE_DISABLE__SHIFT                                               0xd
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                           0xe
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__PM_CONTROL_MASK                                                        0x0003L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK                                      0x0004L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                 0x0008L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_DIS_MASK                                                          0x0010L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__RETRAIN_LINK_MASK                                                      0x0020L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                  0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__EXTENDED_SYNC_MASK                                                     0x0080L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                         0x0100L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                       0x0200L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                         0x0400L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                         0x0800L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__SRIS_CLOCKING_MASK                                                     0x1000L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__FLIT_MODE_DISABLE_MASK                                                 0x2000L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                             0xC000L
+//BIF_CFG_DEV0_EPF0_0_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                         0x4
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_TRAINING__SHIFT                                                 0xb
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                0xc
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__DL_ACTIVE__SHIFT                                                     0xd
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                     0xe
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                     0xf
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                              0x000FL
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                           0x03F0L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_TRAINING_MASK                                                   0x0800L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                  0x1000L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__DL_ACTIVE_MASK                                                       0x2000L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                       0x4000L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                       0x8000L
+//BIF_CFG_DEV0_EPF0_0_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                            0x1
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                             0x8
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT                                        0x9
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                        0x10
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                       0x17
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                       0x18
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                   0x1f
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                              0x000000FEL
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                               0x00000100L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK                                          0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                          0x007F0000L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                         0x00800000L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                         0x01000000L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP2__DRS_SUPPORTED_MASK                                                     0x80000000L
+//BIF_CFG_DEV0_EPF0_0_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                               0x4
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                    0x5
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                          0x6
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                    0x7
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                           0xa
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                 0xb
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                          0xc
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                0x000FL
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                 0x0010L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                      0x0020L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                            0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__XMIT_MARGIN_MASK                                                      0x0380L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                             0x0400L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                   0x0800L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                            0xF000L
+//BIF_CFG_DEV0_EPF0_0_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                    0x1
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                              0x2
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                              0x3
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                              0x4
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                0x5
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                            0x6
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                            0x7
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                         0x8
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__FLIT_MODE_STATUS__SHIFT                                             0xa
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                0xc
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                         0xf
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                           0x0001L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                      0x0002L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                0x0004L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                0x0008L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                0x0010L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                  0x0020L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                              0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                              0x0080L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                           0x0300L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__FLIT_MODE_STATUS_MASK                                               0x0400L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                  0x7000L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                           0x8000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                  0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                 0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                    0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                   0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                  0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                         0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                      0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                            0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                           0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                        0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT                                       0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT                                      0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK                                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK                                         0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK                                        0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT                              0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT                                   0x9
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK                                        0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK                                0x00000002L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK                                     0x0000FE00L
+//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK                               0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT               0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT          0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT            0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                 0x000FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK            0x0070L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                   0x0F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK              0x7000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT         0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                0x000FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK           0x0070L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                  0x0F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x7000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT         0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                0x000FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK           0x0070L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                  0x0F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x7000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT         0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                0x000FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK           0x0070L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                  0x0F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x7000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT         0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                0x000FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK           0x0070L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                  0x0F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x7000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT         0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                0x000FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK           0x0070L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                  0x0F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x7000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT         0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT           0xc
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                0x000FL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK           0x0070L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                  0x0F00L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK             0x7000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_LINK_CAP_16GT
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP_16GT__RESERVED__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP_16GT__RESERVED_MASK                                                      0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_LINK_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL_16GT__RESERVED__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL_16GT__RESERVED_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT                               0x0
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT                         0x1
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT                         0x2
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT                         0x3
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT                           0x4
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK                                 0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK                           0x00000002L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK                           0x00000004L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK                           0x00000008L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK                             0x00000010L
+//BIF_CFG_DEV0_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT       0x0
+#define BIF_CFG_DEV0_EPF0_0_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK         0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT         0x0
+#define BIF_CFG_DEV0_EPF0_0_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK           0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT         0x0
+#define BIF_CFG_DEV0_EPF0_0_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK           0x0000FFFFL
+//BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT                 0x4
+#define BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK                   0x0FL
+#define BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK                   0xF0L
+//BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT                 0x4
+#define BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK                   0x0FL
+#define BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK                   0xF0L
+//BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT                 0x4
+#define BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK                   0x0FL
+#define BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK                   0xF0L
+//BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT                 0x4
+#define BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK                   0x0FL
+#define BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK                   0xF0L
+//BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT                 0x4
+#define BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK                   0x0FL
+#define BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK                   0xF0L
+//BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT                 0x4
+#define BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK                   0x0FL
+#define BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK                   0xF0L
+//BIF_CFG_DEV0_EPF0_0_PCIE_PHY_32GT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_32GT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PHY_32GT_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__EQ_BYPASS_TO_HIGHEST_RATE_SUPPORTED__SHIFT                         0x0
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__NO_EQ_NEEDED_SUPPORTED__SHIFT                                      0x1
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE0_SUPPORTED__SHIFT                           0x8
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE1_SUPPORTED__SHIFT                           0x9
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE2_SUPPORTED__SHIFT                           0xa
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES__SHIFT                            0xb
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__EQ_BYPASS_TO_HIGHEST_RATE_SUPPORTED_MASK                           0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__NO_EQ_NEEDED_SUPPORTED_MASK                                        0x00000002L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE0_SUPPORTED_MASK                             0x00000100L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE1_SUPPORTED_MASK                             0x00000200L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE2_SUPPORTED_MASK                             0x00000400L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES_MASK                              0x0000F800L
+//BIF_CFG_DEV0_EPF0_0_LINK_CNTL_32GT
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL_32GT__EQ_BYPASS_TO_HIGHEST_RATE_DIS__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL_32GT__NO_EQ_NEEDED_DIS__SHIFT                                           0x1
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SEL__SHIFT                                 0x8
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL_32GT__EQ_BYPASS_TO_HIGHEST_RATE_DIS_MASK                                0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL_32GT__NO_EQ_NEEDED_DIS_MASK                                             0x00000002L
+#define BIF_CFG_DEV0_EPF0_0_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SEL_MASK                                   0x00000700L
+//BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT__SHIFT                               0x0
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT__SHIFT                         0x1
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT__SHIFT                         0x2
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT__SHIFT                         0x3
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT__SHIFT                           0x4
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED__SHIFT                                     0x5
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOR_CNTL__SHIFT                     0x6
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON__SHIFT                                 0x8
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST__SHIFT                              0x9
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__NO_EQ_NEEDED_RECEIVED__SHIFT                                    0xa
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT_MASK                                 0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT_MASK                           0x00000002L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT_MASK                           0x00000004L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT_MASK                           0x00000008L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT_MASK                             0x00000010L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED_MASK                                       0x00000020L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOR_CNTL_MASK                       0x000000C0L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON_MASK                                   0x00000100L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST_MASK                                0x00000200L
+#define BIF_CFG_DEV0_EPF0_0_LINK_STATUS_32GT__NO_EQ_NEEDED_RECEIVED_MASK                                      0x00000400L
+//BIF_CFG_DEV0_EPF0_0_RECEIVED_MODIFIED_TS_DATA1
+#define BIF_CFG_DEV0_EPF0_0_RECEIVED_MODIFIED_TS_DATA1__USAGE_MODE__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF0_0_RECEIVED_MODIFIED_TS_DATA1__INFOR1__SHIFT                                         0x3
+#define BIF_CFG_DEV0_EPF0_0_RECEIVED_MODIFIED_TS_DATA1__VENDORID__SHIFT                                       0x10
+#define BIF_CFG_DEV0_EPF0_0_RECEIVED_MODIFIED_TS_DATA1__USAGE_MODE_MASK                                       0x00000007L
+#define BIF_CFG_DEV0_EPF0_0_RECEIVED_MODIFIED_TS_DATA1__INFOR1_MASK                                           0x0000FFF8L
+#define BIF_CFG_DEV0_EPF0_0_RECEIVED_MODIFIED_TS_DATA1__VENDORID_MASK                                         0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_RECEIVED_MODIFIED_TS_DATA2
+#define BIF_CFG_DEV0_EPF0_0_RECEIVED_MODIFIED_TS_DATA2__INFOR2__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_0_RECEIVED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS__SHIFT          0x18
+#define BIF_CFG_DEV0_EPF0_0_RECEIVED_MODIFIED_TS_DATA2__INFOR2_MASK                                           0x00FFFFFFL
+#define BIF_CFG_DEV0_EPF0_0_RECEIVED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS_MASK            0x03000000L
+//BIF_CFG_DEV0_EPF0_0_TRANSMITTED_MODIFIED_TS_DATA1
+#define BIF_CFG_DEV0_EPF0_0_TRANSMITTED_MODIFIED_TS_DATA1__USAGE_MODE__SHIFT                                  0x0
+#define BIF_CFG_DEV0_EPF0_0_TRANSMITTED_MODIFIED_TS_DATA1__INFOR1__SHIFT                                      0x3
+#define BIF_CFG_DEV0_EPF0_0_TRANSMITTED_MODIFIED_TS_DATA1__VENDORID__SHIFT                                    0x10
+#define BIF_CFG_DEV0_EPF0_0_TRANSMITTED_MODIFIED_TS_DATA1__USAGE_MODE_MASK                                    0x00000007L
+#define BIF_CFG_DEV0_EPF0_0_TRANSMITTED_MODIFIED_TS_DATA1__INFOR1_MASK                                        0x0000FFF8L
+#define BIF_CFG_DEV0_EPF0_0_TRANSMITTED_MODIFIED_TS_DATA1__VENDORID_MASK                                      0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_TRANSMITTED_MODIFIED_TS_DATA2
+#define BIF_CFG_DEV0_EPF0_0_TRANSMITTED_MODIFIED_TS_DATA2__INFOR2__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF0_0_TRANSMITTED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS__SHIFT       0x18
+#define BIF_CFG_DEV0_EPF0_0_TRANSMITTED_MODIFIED_TS_DATA2__INFOR2_MASK                                        0x00FFFFFFL
+#define BIF_CFG_DEV0_EPF0_0_TRANSMITTED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS_MASK         0x03000000L
+//BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_32GT
+#define BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_DSP_32GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_USP_32GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_DSP_32GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV0_EPF0_0_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_USP_32GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_32GT
+#define BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_DSP_32GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_USP_32GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_DSP_32GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV0_EPF0_0_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_USP_32GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_32GT
+#define BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_DSP_32GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_USP_32GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_DSP_32GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV0_EPF0_0_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_USP_32GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_32GT
+#define BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_DSP_32GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_USP_32GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_DSP_32GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV0_EPF0_0_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_USP_32GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_32GT
+#define BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_DSP_32GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_USP_32GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_DSP_32GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV0_EPF0_0_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_USP_32GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_32GT
+#define BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_DSP_32GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_USP_32GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_DSP_32GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV0_EPF0_0_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_USP_32GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_32GT
+#define BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_DSP_32GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_USP_32GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_DSP_32GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV0_EPF0_0_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_USP_32GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_32GT
+#define BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_DSP_32GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_USP_32GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_DSP_32GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV0_EPF0_0_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_USP_32GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_32GT
+#define BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_DSP_32GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_USP_32GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_DSP_32GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV0_EPF0_0_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_USP_32GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_32GT
+#define BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_DSP_32GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_USP_32GT_TX_PRESET__SHIFT                   0x4
+#define BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_DSP_32GT_TX_PRESET_MASK                     0x0FL
+#define BIF_CFG_DEV0_EPF0_0_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_USP_32GT_TX_PRESET_MASK                     0xF0L
+//BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_32GT
+#define BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_DSP_32GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_USP_32GT_TX_PRESET__SHIFT                 0x4
+#define BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_DSP_32GT_TX_PRESET_MASK                   0x0FL
+#define BIF_CFG_DEV0_EPF0_0_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_USP_32GT_TX_PRESET_MASK                   0xF0L
+//BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_32GT
+#define BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_DSP_32GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_USP_32GT_TX_PRESET__SHIFT                 0x4
+#define BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_DSP_32GT_TX_PRESET_MASK                   0x0FL
+#define BIF_CFG_DEV0_EPF0_0_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_USP_32GT_TX_PRESET_MASK                   0xF0L
+//BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_32GT
+#define BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_DSP_32GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_USP_32GT_TX_PRESET__SHIFT                 0x4
+#define BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_DSP_32GT_TX_PRESET_MASK                   0x0FL
+#define BIF_CFG_DEV0_EPF0_0_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_USP_32GT_TX_PRESET_MASK                   0xF0L
+//BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_32GT
+#define BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_DSP_32GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_USP_32GT_TX_PRESET__SHIFT                 0x4
+#define BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_DSP_32GT_TX_PRESET_MASK                   0x0FL
+#define BIF_CFG_DEV0_EPF0_0_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_USP_32GT_TX_PRESET_MASK                   0xF0L
+//BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_32GT
+#define BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_DSP_32GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_USP_32GT_TX_PRESET__SHIFT                 0x4
+#define BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_DSP_32GT_TX_PRESET_MASK                   0x0FL
+#define BIF_CFG_DEV0_EPF0_0_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_USP_32GT_TX_PRESET_MASK                   0xF0L
+//BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_32GT
+#define BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_DSP_32GT_TX_PRESET__SHIFT                 0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_USP_32GT_TX_PRESET__SHIFT                 0x4
+#define BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_DSP_32GT_TX_PRESET_MASK                   0x0FL
+#define BIF_CFG_DEV0_EPF0_0_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_USP_32GT_TX_PRESET_MASK                   0xF0L
+//BIF_CFG_DEV0_EPF0_0_PCIE_AP_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_AP_ENH_CAP_LIST__CAP_ID__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_AP_ENH_CAP_LIST__CAP_VER__SHIFT                                              0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_AP_ENH_CAP_LIST__NEXT_PTR__SHIFT                                             0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_AP_ENH_CAP_LIST__CAP_ID_MASK                                                 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_AP_ENH_CAP_LIST__CAP_VER_MASK                                                0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_AP_ENH_CAP_LIST__NEXT_PTR_MASK                                               0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_AP_CAP
+#define BIF_CFG_DEV0_EPF0_0_AP_CAP__COUNT__SHIFT                                                              0x0
+#define BIF_CFG_DEV0_EPF0_0_AP_CAP__SEL_EN_SUPPORTED__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF0_0_AP_CAP__COUNT_MASK                                                                0x000000FFL
+#define BIF_CFG_DEV0_EPF0_0_AP_CAP__SEL_EN_SUPPORTED_MASK                                                     0x00000100L
+//BIF_CFG_DEV0_EPF0_0_AP_CNTL
+#define BIF_CFG_DEV0_EPF0_0_AP_CNTL__INX_SEL__SHIFT                                                           0x0
+#define BIF_CFG_DEV0_EPF0_0_AP_CNTL__NEGO_GLOBAL_EN__SHIFT                                                    0x8
+#define BIF_CFG_DEV0_EPF0_0_AP_CNTL__INX_SEL_MASK                                                             0x000000FFL
+#define BIF_CFG_DEV0_EPF0_0_AP_CNTL__NEGO_GLOBAL_EN_MASK                                                      0x00000100L
+//BIF_CFG_DEV0_EPF0_0_AP_DATA1
+#define BIF_CFG_DEV0_EPF0_0_AP_DATA1__USAGE_INFOR__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF0_0_AP_DATA1__DETAILS__SHIFT                                                          0x5
+#define BIF_CFG_DEV0_EPF0_0_AP_DATA1__VENDORID__SHIFT                                                         0x10
+#define BIF_CFG_DEV0_EPF0_0_AP_DATA1__USAGE_INFOR_MASK                                                        0x00000007L
+#define BIF_CFG_DEV0_EPF0_0_AP_DATA1__DETAILS_MASK                                                            0x0000FFE0L
+#define BIF_CFG_DEV0_EPF0_0_AP_DATA1__VENDORID_MASK                                                           0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_0_AP_DATA2
+#define BIF_CFG_DEV0_EPF0_0_AP_DATA2__MODIFIED_TS_INFOR2__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF0_0_AP_DATA2__MODIFIED_TS_INFOR2_MASK                                                 0x00FFFFFFL
+//BIF_CFG_DEV0_EPF0_0_AP_SEL_EN_MASK
+#define BIF_CFG_DEV0_EPF0_0_AP_SEL_EN_MASK__PCIE__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF0_0_AP_SEL_EN_MASK__OTHERS__SHIFT                                                     0x1
+#define BIF_CFG_DEV0_EPF0_0_AP_SEL_EN_MASK__PCIE_MASK                                                         0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_AP_SEL_EN_MASK__OTHERS_MASK                                                       0xFFFFFFFEL
+//BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT                                       0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT                                      0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK                                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK                                         0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK                                        0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_CAP
+#define BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT                                0x0
+#define BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK                                  0x0001L
+//BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS
+#define BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT                            0x1
+#define BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS__MARGINING_READY_MASK                                       0x0001L
+#define BIF_CFG_DEV0_EPF0_0_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK                              0x0002L
+//BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT                         0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT                             0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT                             0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT                          0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK                           0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK                               0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK                               0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK                            0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT                0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT                    0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT                    0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT                 0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK                  0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK                      0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK                      0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK                   0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT                       0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT                           0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT                           0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT                        0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK                         0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK                             0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK                             0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK                          0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT              0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT                  0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT                  0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT               0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK                0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK                    0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK                    0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK                 0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT                       0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT                           0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT                           0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT                        0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK                         0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK                             0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK                             0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK                          0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT              0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT                  0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT                  0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT               0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK                0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK                    0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK                    0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK                 0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT                       0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT                           0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT                           0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT                        0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK                         0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK                             0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK                             0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK                          0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT              0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT                  0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT                  0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT               0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK                0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK                    0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK                    0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK                 0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT                       0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT                           0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT                           0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT                        0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK                         0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK                             0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK                             0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK                          0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT              0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT                  0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT                  0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT               0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK                0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK                    0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK                    0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK                 0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT                       0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT                           0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT                           0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT                        0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK                         0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK                             0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK                             0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK                          0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT              0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT                  0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT                  0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT               0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK                0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK                    0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK                    0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK                 0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT                       0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT                           0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT                           0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT                        0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK                         0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK                             0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK                             0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK                          0xFF00L
+//BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT              0x0
+#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT                  0x3
+#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT                  0x6
+#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT               0x8
+#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK                0x0007L
+#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK                    0x0038L
+#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK                    0x0040L
+#define BIF_CFG_DEV0_EPF0_0_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK                 0xFF00L
+//BIF_CFG_DEV0_EPF0_0_PCIE_NULL1_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_NULL1_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_NULL1_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_NULL1_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_NULL1_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_NULL1_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_NULL1_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT                                              0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                             0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK                                                 0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK                                                0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK                                               0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT                           0x4
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT                                             0x8
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT                           0xa
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK                                          0x00000007L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK                             0x00000070L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK                                               0x00000300L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK                             0x00000C00L
+//BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT                                 0x18
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK                                            0x000000FFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK                                   0xFF000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT                                           0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK                                         0x0001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK                                             0x000EL
+//BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK                                     0x0001L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                  0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                      0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                               0x18
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK                                          0x000000FFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                    0x00008000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                        0x007F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                 0xFF000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                    0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                    0x11
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT                                              0x18
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT                                          0x1f
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                        0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                      0x000000FEL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                  0x00010000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                      0x000E0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK                                                0x07000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK                                            0x80000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                           0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                              0x0001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                             0x0002L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                  0xf
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                      0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                               0x18
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK                                          0x000000FFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                    0x00008000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                        0x003F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                 0xFF000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                    0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                    0x11
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT                                              0x18
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT                                          0x1f
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                        0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                      0x000000FEL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                  0x00010000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                      0x000E0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK                                                0x07000000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK                                            0x80000000L
+//BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                           0x1
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                              0x0001L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                             0x0002L
+//BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP
+#define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT                                 0x0
+#define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT                                 0x1f
+#define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK                                   0x007FFFFFL
+#define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK                                   0x80000000L
+//BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS
+#define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT                       0x1f
+#define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK                               0x007FFFFFL
+#define BIF_CFG_DEV0_EPF0_0_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK                         0x80000000L
+//BIF_CFG_DEV0_EPF0_0_IDE_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_0_IDE_ENH_CAP_LIST__CAP_ID__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_0_IDE_ENH_CAP_LIST__CAP_VER__SHIFT                                                  0x10
+#define BIF_CFG_DEV0_EPF0_0_IDE_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                 0x14
+#define BIF_CFG_DEV0_EPF0_0_IDE_ENH_CAP_LIST__CAP_ID_MASK                                                     0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_0_IDE_ENH_CAP_LIST__CAP_VER_MASK                                                    0x000F0000L
+#define BIF_CFG_DEV0_EPF0_0_IDE_ENH_CAP_LIST__NEXT_PTR_MASK                                                   0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_IDE_CAP
+#define BIF_CFG_DEV0_EPF0_0_IDE_CAP__IDE_CAP_LINK_IDE_STREAM_SUPPORTED__SHIFT                                 0x0
+#define BIF_CFG_DEV0_EPF0_0_IDE_CAP__IDE_CAP_SELECTIVE_IDE_STREAM_SUPPORTED__SHIFT                            0x1
+#define BIF_CFG_DEV0_EPF0_0_IDE_CAP__IDE_CAP_FLOW_THROUGH_IDE_STREAM_SUPPORTED__SHIFT                         0x2
+#define BIF_CFG_DEV0_EPF0_0_IDE_CAP__IDE_CAP_PARTIAL_HDR_ENCRYPTION_SUPPORTED__SHIFT                          0x3
+#define BIF_CFG_DEV0_EPF0_0_IDE_CAP__IDE_CAP_AGGREGATION_SUPPORTED__SHIFT                                     0x4
+#define BIF_CFG_DEV0_EPF0_0_IDE_CAP__IDE_CAP_PCRC_SUPPORTED__SHIFT                                            0x5
+#define BIF_CFG_DEV0_EPF0_0_IDE_CAP__IDE_CAP_IDE_KM_PROTOCOL_SUPPORTED__SHIFT                                 0x6
+#define BIF_CFG_DEV0_EPF0_0_IDE_CAP__IDE_CAP_SELECTIVE_IDE_FOR_CFG_REQ_SUPPORTED__SHIFT                       0x7
+#define BIF_CFG_DEV0_EPF0_0_IDE_CAP__IDE_CAP_SUPPORTED_ALGORITHMS__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF0_0_IDE_CAP__IDE_CAP_NUM_OF_TCS_SUPPORTED_FOR_LINK_IDE__SHIFT                         0xd
+#define BIF_CFG_DEV0_EPF0_0_IDE_CAP__IDE_CAP_NUM_OF_SELECTIVE_IDE_STREAMS_SUPPORTED__SHIFT                    0x10
+#define BIF_CFG_DEV0_EPF0_0_IDE_CAP__IDE_CAP_TEE_LIMITED_SUPPORTED__SHIFT                                     0x18
+#define BIF_CFG_DEV0_EPF0_0_IDE_CAP__IDE_CAP_XT_SUPPORTED__SHIFT                                              0x19
+#define BIF_CFG_DEV0_EPF0_0_IDE_CAP__IDE_CAP_LINK_IDE_STREAM_SUPPORTED_MASK                                   0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_IDE_CAP__IDE_CAP_SELECTIVE_IDE_STREAM_SUPPORTED_MASK                              0x00000002L
+#define BIF_CFG_DEV0_EPF0_0_IDE_CAP__IDE_CAP_FLOW_THROUGH_IDE_STREAM_SUPPORTED_MASK                           0x00000004L
+#define BIF_CFG_DEV0_EPF0_0_IDE_CAP__IDE_CAP_PARTIAL_HDR_ENCRYPTION_SUPPORTED_MASK                            0x00000008L
+#define BIF_CFG_DEV0_EPF0_0_IDE_CAP__IDE_CAP_AGGREGATION_SUPPORTED_MASK                                       0x00000010L
+#define BIF_CFG_DEV0_EPF0_0_IDE_CAP__IDE_CAP_PCRC_SUPPORTED_MASK                                              0x00000020L
+#define BIF_CFG_DEV0_EPF0_0_IDE_CAP__IDE_CAP_IDE_KM_PROTOCOL_SUPPORTED_MASK                                   0x00000040L
+#define BIF_CFG_DEV0_EPF0_0_IDE_CAP__IDE_CAP_SELECTIVE_IDE_FOR_CFG_REQ_SUPPORTED_MASK                         0x00000080L
+#define BIF_CFG_DEV0_EPF0_0_IDE_CAP__IDE_CAP_SUPPORTED_ALGORITHMS_MASK                                        0x00001F00L
+#define BIF_CFG_DEV0_EPF0_0_IDE_CAP__IDE_CAP_NUM_OF_TCS_SUPPORTED_FOR_LINK_IDE_MASK                           0x0000E000L
+#define BIF_CFG_DEV0_EPF0_0_IDE_CAP__IDE_CAP_NUM_OF_SELECTIVE_IDE_STREAMS_SUPPORTED_MASK                      0x00FF0000L
+#define BIF_CFG_DEV0_EPF0_0_IDE_CAP__IDE_CAP_TEE_LIMITED_SUPPORTED_MASK                                       0x01000000L
+#define BIF_CFG_DEV0_EPF0_0_IDE_CAP__IDE_CAP_XT_SUPPORTED_MASK                                                0x02000000L
+//BIF_CFG_DEV0_EPF0_0_IDE_CNTL
+#define BIF_CFG_DEV0_EPF0_0_IDE_CNTL__IDE_CNTL_FLOW_THROUGH_IDE_STREAM_ENABLED__SHIFT                         0x2
+#define BIF_CFG_DEV0_EPF0_0_IDE_CNTL__IDE_CNTL_FLOW_THROUGH_IDE_STREAM_ENABLED_MASK                           0x00000004L
+//BIF_CFG_DEV0_EPF0_0_LINK_IDE_STREAM_0_CNTL
+#define BIF_CFG_DEV0_EPF0_0_LINK_IDE_STREAM_0_CNTL__LINK_IDE_STREAM_ENABLE__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_LINK_IDE_STREAM_0_CNTL__XT_ENABLE__SHIFT                                          0x1
+#define BIF_CFG_DEV0_EPF0_0_LINK_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT                            0x2
+#define BIF_CFG_DEV0_EPF0_0_LINK_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_PR__SHIFT                             0x4
+#define BIF_CFG_DEV0_EPF0_0_LINK_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT                            0x6
+#define BIF_CFG_DEV0_EPF0_0_LINK_IDE_STREAM_0_CNTL__PCRC_ENABLE__SHIFT                                        0x8
+#define BIF_CFG_DEV0_EPF0_0_LINK_IDE_STREAM_0_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT                           0xa
+#define BIF_CFG_DEV0_EPF0_0_LINK_IDE_STREAM_0_CNTL__SELECTED_ALGORITHM__SHIFT                                 0xe
+#define BIF_CFG_DEV0_EPF0_0_LINK_IDE_STREAM_0_CNTL__TC__SHIFT                                                 0x13
+#define BIF_CFG_DEV0_EPF0_0_LINK_IDE_STREAM_0_CNTL__STREAM_ID__SHIFT                                          0x18
+#define BIF_CFG_DEV0_EPF0_0_LINK_IDE_STREAM_0_CNTL__LINK_IDE_STREAM_ENABLE_MASK                               0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_LINK_IDE_STREAM_0_CNTL__XT_ENABLE_MASK                                            0x00000002L
+#define BIF_CFG_DEV0_EPF0_0_LINK_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_NPR_MASK                              0x0000000CL
+#define BIF_CFG_DEV0_EPF0_0_LINK_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_PR_MASK                               0x00000030L
+#define BIF_CFG_DEV0_EPF0_0_LINK_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_CPL_MASK                              0x000000C0L
+#define BIF_CFG_DEV0_EPF0_0_LINK_IDE_STREAM_0_CNTL__PCRC_ENABLE_MASK                                          0x00000100L
+#define BIF_CFG_DEV0_EPF0_0_LINK_IDE_STREAM_0_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK                             0x00003C00L
+#define BIF_CFG_DEV0_EPF0_0_LINK_IDE_STREAM_0_CNTL__SELECTED_ALGORITHM_MASK                                   0x0007C000L
+#define BIF_CFG_DEV0_EPF0_0_LINK_IDE_STREAM_0_CNTL__TC_MASK                                                   0x00380000L
+#define BIF_CFG_DEV0_EPF0_0_LINK_IDE_STREAM_0_CNTL__STREAM_ID_MASK                                            0xFF000000L
+//BIF_CFG_DEV0_EPF0_0_LINK_IDE_STREAM_0_STATUS
+#define BIF_CFG_DEV0_EPF0_0_LINK_IDE_STREAM_0_STATUS__LINK_IDE_STREAM_STATE__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF0_0_LINK_IDE_STREAM_0_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT                            0x1f
+#define BIF_CFG_DEV0_EPF0_0_LINK_IDE_STREAM_0_STATUS__LINK_IDE_STREAM_STATE_MASK                              0x0000000FL
+#define BIF_CFG_DEV0_EPF0_0_LINK_IDE_STREAM_0_STATUS__RECEIVED_IDE_FAIL_MSG_MASK                              0x80000000L
+//BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CAP
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT                  0x0
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK                    0x0000000FL
+//BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CNTL
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CNTL__XT_ENABLE__SHIFT                                     0x1
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT                       0x2
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_PR__SHIFT                        0x4
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT                       0x6
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CNTL__PCRC_ENABLE__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT                  0x9
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT                      0xa
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CNTL__SELECTED_ALGORITHM__SHIFT                            0xe
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CNTL__TC__SHIFT                                            0x13
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CNTL__DEFAULT_STREAM__SHIFT                                0x16
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CNTL__TEE_LIMITED_STREAM__SHIFT                            0x17
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CNTL__STREAM_ID__SHIFT                                     0x18
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK                     0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CNTL__XT_ENABLE_MASK                                       0x00000002L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_NPR_MASK                         0x0000000CL
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_PR_MASK                          0x00000030L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_CPL_MASK                         0x000000C0L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CNTL__PCRC_ENABLE_MASK                                     0x00000100L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK                    0x00000200L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK                        0x00003C00L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CNTL__SELECTED_ALGORITHM_MASK                              0x0007C000L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CNTL__TC_MASK                                              0x00380000L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CNTL__DEFAULT_STREAM_MASK                                  0x00400000L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CNTL__TEE_LIMITED_STREAM_MASK                              0x00800000L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_CNTL__STREAM_ID_MASK                                       0xFF000000L
+//BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_STATUS
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT                  0x0
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT                       0x1f
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK                    0x0000000FL
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_0_STATUS__RECEIVED_IDE_FAIL_MSG_MASK                         0x80000000L
+//BIF_CFG_DEV0_EPF0_0_IDE_0_RID_ASSOCIATION_REG1
+#define BIF_CFG_DEV0_EPF0_0_IDE_0_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF0_0_IDE_0_RID_ASSOCIATION_REG1__RID_LIMIT_MASK                                        0x00FFFF00L
+//BIF_CFG_DEV0_EPF0_0_IDE_0_RID_ASSOCIATION_REG2
+#define BIF_CFG_DEV0_EPF0_0_IDE_0_RID_ASSOCIATION_REG2__VALID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF0_0_IDE_0_RID_ASSOCIATION_REG2__RID_BASE__SHIFT                                       0x8
+#define BIF_CFG_DEV0_EPF0_0_IDE_0_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT                                   0x18
+#define BIF_CFG_DEV0_EPF0_0_IDE_0_RID_ASSOCIATION_REG2__VALID_MASK                                            0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_IDE_0_RID_ASSOCIATION_REG2__RID_BASE_MASK                                         0x00FFFF00L
+#define BIF_CFG_DEV0_EPF0_0_IDE_0_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK                                     0xFF000000L
+//BIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_0_REG1
+#define BIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT                              0x8
+#define BIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT                             0x14
+#define BIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_0_REG1__VALID_MASK                                         0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK                                0x000FFF00L
+#define BIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK                               0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_0_REG2
+#define BIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_0_REG3
+#define BIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_1_REG1
+#define BIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT                              0x8
+#define BIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT                             0x14
+#define BIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_1_REG1__VALID_MASK                                         0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK                                0x000FFF00L
+#define BIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK                               0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_1_REG2
+#define BIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_1_REG3
+#define BIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_IDE_0_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CAP
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT                  0x0
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK                    0x0000000FL
+//BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CNTL
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CNTL__XT_ENABLE__SHIFT                                     0x1
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT                       0x2
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CNTL__TX_AGGREGATION_MODE_PR__SHIFT                        0x4
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT                       0x6
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CNTL__PCRC_ENABLE__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT                  0x9
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT                      0xa
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CNTL__SELECTED_ALGORITHM__SHIFT                            0xe
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CNTL__TC__SHIFT                                            0x13
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CNTL__DEFAULT_STREAM__SHIFT                                0x16
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CNTL__TEE_LIMITED_STREAM__SHIFT                            0x17
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CNTL__STREAM_ID__SHIFT                                     0x18
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK                     0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CNTL__XT_ENABLE_MASK                                       0x00000002L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CNTL__TX_AGGREGATION_MODE_NPR_MASK                         0x0000000CL
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CNTL__TX_AGGREGATION_MODE_PR_MASK                          0x00000030L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CNTL__TX_AGGREGATION_MODE_CPL_MASK                         0x000000C0L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CNTL__PCRC_ENABLE_MASK                                     0x00000100L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK                    0x00000200L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK                        0x00003C00L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CNTL__SELECTED_ALGORITHM_MASK                              0x0007C000L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CNTL__TC_MASK                                              0x00380000L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CNTL__DEFAULT_STREAM_MASK                                  0x00400000L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CNTL__TEE_LIMITED_STREAM_MASK                              0x00800000L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_CNTL__STREAM_ID_MASK                                       0xFF000000L
+//BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_STATUS
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT                  0x0
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT                       0x1f
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK                    0x0000000FL
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_1_STATUS__RECEIVED_IDE_FAIL_MSG_MASK                         0x80000000L
+//BIF_CFG_DEV0_EPF0_0_IDE_1_RID_ASSOCIATION_REG1
+#define BIF_CFG_DEV0_EPF0_0_IDE_1_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF0_0_IDE_1_RID_ASSOCIATION_REG1__RID_LIMIT_MASK                                        0x00FFFF00L
+//BIF_CFG_DEV0_EPF0_0_IDE_1_RID_ASSOCIATION_REG2
+#define BIF_CFG_DEV0_EPF0_0_IDE_1_RID_ASSOCIATION_REG2__VALID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF0_0_IDE_1_RID_ASSOCIATION_REG2__RID_BASE__SHIFT                                       0x8
+#define BIF_CFG_DEV0_EPF0_0_IDE_1_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT                                   0x18
+#define BIF_CFG_DEV0_EPF0_0_IDE_1_RID_ASSOCIATION_REG2__VALID_MASK                                            0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_IDE_1_RID_ASSOCIATION_REG2__RID_BASE_MASK                                         0x00FFFF00L
+#define BIF_CFG_DEV0_EPF0_0_IDE_1_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK                                     0xFF000000L
+//BIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_0_REG1
+#define BIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT                              0x8
+#define BIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT                             0x14
+#define BIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_0_REG1__VALID_MASK                                         0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK                                0x000FFF00L
+#define BIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK                               0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_0_REG2
+#define BIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_0_REG3
+#define BIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_1_REG1
+#define BIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT                              0x8
+#define BIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT                             0x14
+#define BIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_1_REG1__VALID_MASK                                         0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK                                0x000FFF00L
+#define BIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK                               0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_1_REG2
+#define BIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_1_REG3
+#define BIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_IDE_1_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CAP
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT                  0x0
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK                    0x0000000FL
+//BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CNTL
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CNTL__XT_ENABLE__SHIFT                                     0x1
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT                       0x2
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CNTL__TX_AGGREGATION_MODE_PR__SHIFT                        0x4
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT                       0x6
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CNTL__PCRC_ENABLE__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT                  0x9
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT                      0xa
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CNTL__SELECTED_ALGORITHM__SHIFT                            0xe
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CNTL__TC__SHIFT                                            0x13
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CNTL__DEFAULT_STREAM__SHIFT                                0x16
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CNTL__TEE_LIMITED_STREAM__SHIFT                            0x17
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CNTL__STREAM_ID__SHIFT                                     0x18
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK                     0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CNTL__XT_ENABLE_MASK                                       0x00000002L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CNTL__TX_AGGREGATION_MODE_NPR_MASK                         0x0000000CL
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CNTL__TX_AGGREGATION_MODE_PR_MASK                          0x00000030L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CNTL__TX_AGGREGATION_MODE_CPL_MASK                         0x000000C0L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CNTL__PCRC_ENABLE_MASK                                     0x00000100L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK                    0x00000200L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK                        0x00003C00L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CNTL__SELECTED_ALGORITHM_MASK                              0x0007C000L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CNTL__TC_MASK                                              0x00380000L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CNTL__DEFAULT_STREAM_MASK                                  0x00400000L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CNTL__TEE_LIMITED_STREAM_MASK                              0x00800000L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_CNTL__STREAM_ID_MASK                                       0xFF000000L
+//BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_STATUS
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT                  0x0
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT                       0x1f
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK                    0x0000000FL
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_2_STATUS__RECEIVED_IDE_FAIL_MSG_MASK                         0x80000000L
+//BIF_CFG_DEV0_EPF0_0_IDE_2_RID_ASSOCIATION_REG1
+#define BIF_CFG_DEV0_EPF0_0_IDE_2_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF0_0_IDE_2_RID_ASSOCIATION_REG1__RID_LIMIT_MASK                                        0x00FFFF00L
+//BIF_CFG_DEV0_EPF0_0_IDE_2_RID_ASSOCIATION_REG2
+#define BIF_CFG_DEV0_EPF0_0_IDE_2_RID_ASSOCIATION_REG2__VALID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF0_0_IDE_2_RID_ASSOCIATION_REG2__RID_BASE__SHIFT                                       0x8
+#define BIF_CFG_DEV0_EPF0_0_IDE_2_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT                                   0x18
+#define BIF_CFG_DEV0_EPF0_0_IDE_2_RID_ASSOCIATION_REG2__VALID_MASK                                            0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_IDE_2_RID_ASSOCIATION_REG2__RID_BASE_MASK                                         0x00FFFF00L
+#define BIF_CFG_DEV0_EPF0_0_IDE_2_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK                                     0xFF000000L
+//BIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_0_REG1
+#define BIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT                              0x8
+#define BIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT                             0x14
+#define BIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_0_REG1__VALID_MASK                                         0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK                                0x000FFF00L
+#define BIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK                               0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_0_REG2
+#define BIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_0_REG3
+#define BIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_1_REG1
+#define BIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT                              0x8
+#define BIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT                             0x14
+#define BIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_1_REG1__VALID_MASK                                         0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK                                0x000FFF00L
+#define BIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK                               0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_1_REG2
+#define BIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_1_REG3
+#define BIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_IDE_2_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CAP
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT                  0x0
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK                    0x0000000FL
+//BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CNTL
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CNTL__XT_ENABLE__SHIFT                                     0x1
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT                       0x2
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CNTL__TX_AGGREGATION_MODE_PR__SHIFT                        0x4
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT                       0x6
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CNTL__PCRC_ENABLE__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT                  0x9
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT                      0xa
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CNTL__SELECTED_ALGORITHM__SHIFT                            0xe
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CNTL__TC__SHIFT                                            0x13
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CNTL__DEFAULT_STREAM__SHIFT                                0x16
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CNTL__TEE_LIMITED_STREAM__SHIFT                            0x17
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CNTL__STREAM_ID__SHIFT                                     0x18
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK                     0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CNTL__XT_ENABLE_MASK                                       0x00000002L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CNTL__TX_AGGREGATION_MODE_NPR_MASK                         0x0000000CL
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CNTL__TX_AGGREGATION_MODE_PR_MASK                          0x00000030L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CNTL__TX_AGGREGATION_MODE_CPL_MASK                         0x000000C0L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CNTL__PCRC_ENABLE_MASK                                     0x00000100L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK                    0x00000200L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK                        0x00003C00L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CNTL__SELECTED_ALGORITHM_MASK                              0x0007C000L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CNTL__TC_MASK                                              0x00380000L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CNTL__DEFAULT_STREAM_MASK                                  0x00400000L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CNTL__TEE_LIMITED_STREAM_MASK                              0x00800000L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_CNTL__STREAM_ID_MASK                                       0xFF000000L
+//BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_STATUS
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT                  0x0
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT                       0x1f
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK                    0x0000000FL
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_3_STATUS__RECEIVED_IDE_FAIL_MSG_MASK                         0x80000000L
+//BIF_CFG_DEV0_EPF0_0_IDE_3_RID_ASSOCIATION_REG1
+#define BIF_CFG_DEV0_EPF0_0_IDE_3_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF0_0_IDE_3_RID_ASSOCIATION_REG1__RID_LIMIT_MASK                                        0x00FFFF00L
+//BIF_CFG_DEV0_EPF0_0_IDE_3_RID_ASSOCIATION_REG2
+#define BIF_CFG_DEV0_EPF0_0_IDE_3_RID_ASSOCIATION_REG2__VALID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF0_0_IDE_3_RID_ASSOCIATION_REG2__RID_BASE__SHIFT                                       0x8
+#define BIF_CFG_DEV0_EPF0_0_IDE_3_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT                                   0x18
+#define BIF_CFG_DEV0_EPF0_0_IDE_3_RID_ASSOCIATION_REG2__VALID_MASK                                            0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_IDE_3_RID_ASSOCIATION_REG2__RID_BASE_MASK                                         0x00FFFF00L
+#define BIF_CFG_DEV0_EPF0_0_IDE_3_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK                                     0xFF000000L
+//BIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_0_REG1
+#define BIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT                              0x8
+#define BIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT                             0x14
+#define BIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_0_REG1__VALID_MASK                                         0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK                                0x000FFF00L
+#define BIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK                               0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_0_REG2
+#define BIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_0_REG3
+#define BIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_1_REG1
+#define BIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT                              0x8
+#define BIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT                             0x14
+#define BIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_1_REG1__VALID_MASK                                         0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK                                0x000FFF00L
+#define BIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK                               0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_1_REG2
+#define BIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_1_REG3
+#define BIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_IDE_3_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CAP
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT                  0x0
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK                    0x0000000FL
+//BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CNTL
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CNTL__XT_ENABLE__SHIFT                                     0x1
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT                       0x2
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CNTL__TX_AGGREGATION_MODE_PR__SHIFT                        0x4
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT                       0x6
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CNTL__PCRC_ENABLE__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT                  0x9
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT                      0xa
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CNTL__SELECTED_ALGORITHM__SHIFT                            0xe
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CNTL__TC__SHIFT                                            0x13
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CNTL__DEFAULT_STREAM__SHIFT                                0x16
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CNTL__TEE_LIMITED_STREAM__SHIFT                            0x17
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CNTL__STREAM_ID__SHIFT                                     0x18
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK                     0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CNTL__XT_ENABLE_MASK                                       0x00000002L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CNTL__TX_AGGREGATION_MODE_NPR_MASK                         0x0000000CL
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CNTL__TX_AGGREGATION_MODE_PR_MASK                          0x00000030L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CNTL__TX_AGGREGATION_MODE_CPL_MASK                         0x000000C0L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CNTL__PCRC_ENABLE_MASK                                     0x00000100L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK                    0x00000200L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK                        0x00003C00L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CNTL__SELECTED_ALGORITHM_MASK                              0x0007C000L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CNTL__TC_MASK                                              0x00380000L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CNTL__DEFAULT_STREAM_MASK                                  0x00400000L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CNTL__TEE_LIMITED_STREAM_MASK                              0x00800000L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_CNTL__STREAM_ID_MASK                                       0xFF000000L
+//BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_STATUS
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT                  0x0
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT                       0x1f
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK                    0x0000000FL
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_4_STATUS__RECEIVED_IDE_FAIL_MSG_MASK                         0x80000000L
+//BIF_CFG_DEV0_EPF0_0_IDE_4_RID_ASSOCIATION_REG1
+#define BIF_CFG_DEV0_EPF0_0_IDE_4_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF0_0_IDE_4_RID_ASSOCIATION_REG1__RID_LIMIT_MASK                                        0x00FFFF00L
+//BIF_CFG_DEV0_EPF0_0_IDE_4_RID_ASSOCIATION_REG2
+#define BIF_CFG_DEV0_EPF0_0_IDE_4_RID_ASSOCIATION_REG2__VALID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF0_0_IDE_4_RID_ASSOCIATION_REG2__RID_BASE__SHIFT                                       0x8
+#define BIF_CFG_DEV0_EPF0_0_IDE_4_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT                                   0x18
+#define BIF_CFG_DEV0_EPF0_0_IDE_4_RID_ASSOCIATION_REG2__VALID_MASK                                            0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_IDE_4_RID_ASSOCIATION_REG2__RID_BASE_MASK                                         0x00FFFF00L
+#define BIF_CFG_DEV0_EPF0_0_IDE_4_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK                                     0xFF000000L
+//BIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_0_REG1
+#define BIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT                              0x8
+#define BIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT                             0x14
+#define BIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_0_REG1__VALID_MASK                                         0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK                                0x000FFF00L
+#define BIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK                               0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_0_REG2
+#define BIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_0_REG3
+#define BIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_1_REG1
+#define BIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT                              0x8
+#define BIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT                             0x14
+#define BIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_1_REG1__VALID_MASK                                         0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK                                0x000FFF00L
+#define BIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK                               0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_1_REG2
+#define BIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_1_REG3
+#define BIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_IDE_4_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CAP
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT                  0x0
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK                    0x0000000FL
+//BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CNTL
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CNTL__XT_ENABLE__SHIFT                                     0x1
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT                       0x2
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CNTL__TX_AGGREGATION_MODE_PR__SHIFT                        0x4
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT                       0x6
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CNTL__PCRC_ENABLE__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT                  0x9
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT                      0xa
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CNTL__SELECTED_ALGORITHM__SHIFT                            0xe
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CNTL__TC__SHIFT                                            0x13
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CNTL__DEFAULT_STREAM__SHIFT                                0x16
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CNTL__TEE_LIMITED_STREAM__SHIFT                            0x17
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CNTL__STREAM_ID__SHIFT                                     0x18
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK                     0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CNTL__XT_ENABLE_MASK                                       0x00000002L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CNTL__TX_AGGREGATION_MODE_NPR_MASK                         0x0000000CL
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CNTL__TX_AGGREGATION_MODE_PR_MASK                          0x00000030L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CNTL__TX_AGGREGATION_MODE_CPL_MASK                         0x000000C0L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CNTL__PCRC_ENABLE_MASK                                     0x00000100L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK                    0x00000200L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK                        0x00003C00L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CNTL__SELECTED_ALGORITHM_MASK                              0x0007C000L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CNTL__TC_MASK                                              0x00380000L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CNTL__DEFAULT_STREAM_MASK                                  0x00400000L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CNTL__TEE_LIMITED_STREAM_MASK                              0x00800000L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_CNTL__STREAM_ID_MASK                                       0xFF000000L
+//BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_STATUS
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT                  0x0
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT                       0x1f
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK                    0x0000000FL
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_5_STATUS__RECEIVED_IDE_FAIL_MSG_MASK                         0x80000000L
+//BIF_CFG_DEV0_EPF0_0_IDE_5_RID_ASSOCIATION_REG1
+#define BIF_CFG_DEV0_EPF0_0_IDE_5_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF0_0_IDE_5_RID_ASSOCIATION_REG1__RID_LIMIT_MASK                                        0x00FFFF00L
+//BIF_CFG_DEV0_EPF0_0_IDE_5_RID_ASSOCIATION_REG2
+#define BIF_CFG_DEV0_EPF0_0_IDE_5_RID_ASSOCIATION_REG2__VALID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF0_0_IDE_5_RID_ASSOCIATION_REG2__RID_BASE__SHIFT                                       0x8
+#define BIF_CFG_DEV0_EPF0_0_IDE_5_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT                                   0x18
+#define BIF_CFG_DEV0_EPF0_0_IDE_5_RID_ASSOCIATION_REG2__VALID_MASK                                            0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_IDE_5_RID_ASSOCIATION_REG2__RID_BASE_MASK                                         0x00FFFF00L
+#define BIF_CFG_DEV0_EPF0_0_IDE_5_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK                                     0xFF000000L
+//BIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_0_REG1
+#define BIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT                              0x8
+#define BIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT                             0x14
+#define BIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_0_REG1__VALID_MASK                                         0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK                                0x000FFF00L
+#define BIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK                               0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_0_REG2
+#define BIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_0_REG3
+#define BIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_1_REG1
+#define BIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT                              0x8
+#define BIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT                             0x14
+#define BIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_1_REG1__VALID_MASK                                         0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK                                0x000FFF00L
+#define BIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK                               0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_1_REG2
+#define BIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_1_REG3
+#define BIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_IDE_5_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CAP
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT                  0x0
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK                    0x0000000FL
+//BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CNTL
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CNTL__XT_ENABLE__SHIFT                                     0x1
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT                       0x2
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CNTL__TX_AGGREGATION_MODE_PR__SHIFT                        0x4
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT                       0x6
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CNTL__PCRC_ENABLE__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT                  0x9
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT                      0xa
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CNTL__SELECTED_ALGORITHM__SHIFT                            0xe
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CNTL__TC__SHIFT                                            0x13
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CNTL__DEFAULT_STREAM__SHIFT                                0x16
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CNTL__TEE_LIMITED_STREAM__SHIFT                            0x17
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CNTL__STREAM_ID__SHIFT                                     0x18
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK                     0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CNTL__XT_ENABLE_MASK                                       0x00000002L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CNTL__TX_AGGREGATION_MODE_NPR_MASK                         0x0000000CL
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CNTL__TX_AGGREGATION_MODE_PR_MASK                          0x00000030L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CNTL__TX_AGGREGATION_MODE_CPL_MASK                         0x000000C0L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CNTL__PCRC_ENABLE_MASK                                     0x00000100L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK                    0x00000200L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK                        0x00003C00L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CNTL__SELECTED_ALGORITHM_MASK                              0x0007C000L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CNTL__TC_MASK                                              0x00380000L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CNTL__DEFAULT_STREAM_MASK                                  0x00400000L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CNTL__TEE_LIMITED_STREAM_MASK                              0x00800000L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_CNTL__STREAM_ID_MASK                                       0xFF000000L
+//BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_STATUS
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT                  0x0
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT                       0x1f
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK                    0x0000000FL
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_6_STATUS__RECEIVED_IDE_FAIL_MSG_MASK                         0x80000000L
+//BIF_CFG_DEV0_EPF0_0_IDE_6_RID_ASSOCIATION_REG1
+#define BIF_CFG_DEV0_EPF0_0_IDE_6_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF0_0_IDE_6_RID_ASSOCIATION_REG1__RID_LIMIT_MASK                                        0x00FFFF00L
+//BIF_CFG_DEV0_EPF0_0_IDE_6_RID_ASSOCIATION_REG2
+#define BIF_CFG_DEV0_EPF0_0_IDE_6_RID_ASSOCIATION_REG2__VALID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF0_0_IDE_6_RID_ASSOCIATION_REG2__RID_BASE__SHIFT                                       0x8
+#define BIF_CFG_DEV0_EPF0_0_IDE_6_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT                                   0x18
+#define BIF_CFG_DEV0_EPF0_0_IDE_6_RID_ASSOCIATION_REG2__VALID_MASK                                            0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_IDE_6_RID_ASSOCIATION_REG2__RID_BASE_MASK                                         0x00FFFF00L
+#define BIF_CFG_DEV0_EPF0_0_IDE_6_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK                                     0xFF000000L
+//BIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_0_REG1
+#define BIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT                              0x8
+#define BIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT                             0x14
+#define BIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_0_REG1__VALID_MASK                                         0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK                                0x000FFF00L
+#define BIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK                               0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_0_REG2
+#define BIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_0_REG3
+#define BIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_1_REG1
+#define BIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT                              0x8
+#define BIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT                             0x14
+#define BIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_1_REG1__VALID_MASK                                         0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK                                0x000FFF00L
+#define BIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK                               0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_1_REG2
+#define BIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_1_REG3
+#define BIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_IDE_6_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CAP
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT                  0x0
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK                    0x0000000FL
+//BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CNTL
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CNTL__XT_ENABLE__SHIFT                                     0x1
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT                       0x2
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CNTL__TX_AGGREGATION_MODE_PR__SHIFT                        0x4
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT                       0x6
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CNTL__PCRC_ENABLE__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT                  0x9
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT                      0xa
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CNTL__SELECTED_ALGORITHM__SHIFT                            0xe
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CNTL__TC__SHIFT                                            0x13
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CNTL__DEFAULT_STREAM__SHIFT                                0x16
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CNTL__TEE_LIMITED_STREAM__SHIFT                            0x17
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CNTL__STREAM_ID__SHIFT                                     0x18
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK                     0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CNTL__XT_ENABLE_MASK                                       0x00000002L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CNTL__TX_AGGREGATION_MODE_NPR_MASK                         0x0000000CL
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CNTL__TX_AGGREGATION_MODE_PR_MASK                          0x00000030L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CNTL__TX_AGGREGATION_MODE_CPL_MASK                         0x000000C0L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CNTL__PCRC_ENABLE_MASK                                     0x00000100L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK                    0x00000200L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK                        0x00003C00L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CNTL__SELECTED_ALGORITHM_MASK                              0x0007C000L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CNTL__TC_MASK                                              0x00380000L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CNTL__DEFAULT_STREAM_MASK                                  0x00400000L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CNTL__TEE_LIMITED_STREAM_MASK                              0x00800000L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_CNTL__STREAM_ID_MASK                                       0xFF000000L
+//BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_STATUS
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT                  0x0
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT                       0x1f
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK                    0x0000000FL
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_7_STATUS__RECEIVED_IDE_FAIL_MSG_MASK                         0x80000000L
+//BIF_CFG_DEV0_EPF0_0_IDE_7_RID_ASSOCIATION_REG1
+#define BIF_CFG_DEV0_EPF0_0_IDE_7_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF0_0_IDE_7_RID_ASSOCIATION_REG1__RID_LIMIT_MASK                                        0x00FFFF00L
+//BIF_CFG_DEV0_EPF0_0_IDE_7_RID_ASSOCIATION_REG2
+#define BIF_CFG_DEV0_EPF0_0_IDE_7_RID_ASSOCIATION_REG2__VALID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF0_0_IDE_7_RID_ASSOCIATION_REG2__RID_BASE__SHIFT                                       0x8
+#define BIF_CFG_DEV0_EPF0_0_IDE_7_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT                                   0x18
+#define BIF_CFG_DEV0_EPF0_0_IDE_7_RID_ASSOCIATION_REG2__VALID_MASK                                            0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_IDE_7_RID_ASSOCIATION_REG2__RID_BASE_MASK                                         0x00FFFF00L
+#define BIF_CFG_DEV0_EPF0_0_IDE_7_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK                                     0xFF000000L
+//BIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_0_REG1
+#define BIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT                              0x8
+#define BIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT                             0x14
+#define BIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_0_REG1__VALID_MASK                                         0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK                                0x000FFF00L
+#define BIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK                               0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_0_REG2
+#define BIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_0_REG3
+#define BIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_1_REG1
+#define BIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT                              0x8
+#define BIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT                             0x14
+#define BIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_1_REG1__VALID_MASK                                         0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK                                0x000FFF00L
+#define BIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK                               0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_1_REG2
+#define BIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_1_REG3
+#define BIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_IDE_7_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CAP
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT                  0x0
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK                    0x0000000FL
+//BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CNTL
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT                   0x0
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CNTL__XT_ENABLE__SHIFT                                     0x1
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT                       0x2
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CNTL__TX_AGGREGATION_MODE_PR__SHIFT                        0x4
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT                       0x6
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CNTL__PCRC_ENABLE__SHIFT                                   0x8
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT                  0x9
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT                      0xa
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CNTL__SELECTED_ALGORITHM__SHIFT                            0xe
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CNTL__TC__SHIFT                                            0x13
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CNTL__DEFAULT_STREAM__SHIFT                                0x16
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CNTL__TEE_LIMITED_STREAM__SHIFT                            0x17
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CNTL__STREAM_ID__SHIFT                                     0x18
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK                     0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CNTL__XT_ENABLE_MASK                                       0x00000002L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CNTL__TX_AGGREGATION_MODE_NPR_MASK                         0x0000000CL
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CNTL__TX_AGGREGATION_MODE_PR_MASK                          0x00000030L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CNTL__TX_AGGREGATION_MODE_CPL_MASK                         0x000000C0L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CNTL__PCRC_ENABLE_MASK                                     0x00000100L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK                    0x00000200L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK                        0x00003C00L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CNTL__SELECTED_ALGORITHM_MASK                              0x0007C000L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CNTL__TC_MASK                                              0x00380000L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CNTL__DEFAULT_STREAM_MASK                                  0x00400000L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CNTL__TEE_LIMITED_STREAM_MASK                              0x00800000L
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_CNTL__STREAM_ID_MASK                                       0xFF000000L
+//BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_STATUS
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT                  0x0
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT                       0x1f
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK                    0x0000000FL
+#define BIF_CFG_DEV0_EPF0_0_SELECTIVE_IDE_STREAM_8_STATUS__RECEIVED_IDE_FAIL_MSG_MASK                         0x80000000L
+//BIF_CFG_DEV0_EPF0_0_IDE_8_RID_ASSOCIATION_REG1
+#define BIF_CFG_DEV0_EPF0_0_IDE_8_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF0_0_IDE_8_RID_ASSOCIATION_REG1__RID_LIMIT_MASK                                        0x00FFFF00L
+//BIF_CFG_DEV0_EPF0_0_IDE_8_RID_ASSOCIATION_REG2
+#define BIF_CFG_DEV0_EPF0_0_IDE_8_RID_ASSOCIATION_REG2__VALID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF0_0_IDE_8_RID_ASSOCIATION_REG2__RID_BASE__SHIFT                                       0x8
+#define BIF_CFG_DEV0_EPF0_0_IDE_8_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT                                   0x18
+#define BIF_CFG_DEV0_EPF0_0_IDE_8_RID_ASSOCIATION_REG2__VALID_MASK                                            0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_IDE_8_RID_ASSOCIATION_REG2__RID_BASE_MASK                                         0x00FFFF00L
+#define BIF_CFG_DEV0_EPF0_0_IDE_8_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK                                     0xFF000000L
+//BIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_0_REG1
+#define BIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT                              0x8
+#define BIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT                             0x14
+#define BIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_0_REG1__VALID_MASK                                         0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK                                0x000FFF00L
+#define BIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK                               0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_0_REG2
+#define BIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_0_REG3
+#define BIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK                                0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_1_REG1
+#define BIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT                              0x8
+#define BIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT                             0x14
+#define BIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_1_REG1__VALID_MASK                                         0x00000001L
+#define BIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK                                0x000FFF00L
+#define BIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK                               0xFFF00000L
+//BIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_1_REG2
+#define BIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT                             0x0
+#define BIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_1_REG3
+#define BIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_0_IDE_8_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK                                0xFFFFFFFFL
+
+
+// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_vf0_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF0_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF0_VENDOR_ID__VENDOR_ID__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_VF0_VENDOR_ID__VENDOR_ID_MASK                                                       0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_ID__DEVICE_ID__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_ID__DEVICE_ID_MASK                                                       0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__IO_ACCESS_EN__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__MEM_ACCESS_EN__SHIFT                                                   0x1
+#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__BUS_MASTER_EN__SHIFT                                                   0x2
+#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                0x3
+#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                         0x4
+#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__PAL_SNOOP_EN__SHIFT                                                    0x5
+#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                           0x6
+#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__AD_STEPPING__SHIFT                                                     0x7
+#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__SERR_EN__SHIFT                                                         0x8
+#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__FAST_B2B_EN__SHIFT                                                     0x9
+#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__INT_DIS__SHIFT                                                         0xa
+#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__IO_ACCESS_EN_MASK                                                      0x0001L
+#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__MEM_ACCESS_EN_MASK                                                     0x0002L
+#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__BUS_MASTER_EN_MASK                                                     0x0004L
+#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__SPECIAL_CYCLE_EN_MASK                                                  0x0008L
+#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                           0x0010L
+#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__PAL_SNOOP_EN_MASK                                                      0x0020L
+#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__PARITY_ERROR_RESPONSE_MASK                                             0x0040L
+#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__AD_STEPPING_MASK                                                       0x0080L
+#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__SERR_EN_MASK                                                           0x0100L
+#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__FAST_B2B_EN_MASK                                                       0x0200L
+#define BIF_CFG_DEV0_EPF0_VF0_COMMAND__INT_DIS_MASK                                                           0x0400L
+//BIF_CFG_DEV0_EPF0_VF0_STATUS
+#define BIF_CFG_DEV0_EPF0_VF0_STATUS__IMMEDIATE_READINESS__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF0_VF0_STATUS__INT_STATUS__SHIFT                                                       0x3
+#define BIF_CFG_DEV0_EPF0_VF0_STATUS__CAP_LIST__SHIFT                                                         0x4
+#define BIF_CFG_DEV0_EPF0_VF0_STATUS__PCI_66_CAP__SHIFT                                                       0x5
+#define BIF_CFG_DEV0_EPF0_VF0_STATUS__FAST_BACK_CAPABLE__SHIFT                                                0x7
+#define BIF_CFG_DEV0_EPF0_VF0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                         0x8
+#define BIF_CFG_DEV0_EPF0_VF0_STATUS__DEVSEL_TIMING__SHIFT                                                    0x9
+#define BIF_CFG_DEV0_EPF0_VF0_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                              0xb
+#define BIF_CFG_DEV0_EPF0_VF0_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                            0xc
+#define BIF_CFG_DEV0_EPF0_VF0_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                            0xd
+#define BIF_CFG_DEV0_EPF0_VF0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                            0xe
+#define BIF_CFG_DEV0_EPF0_VF0_STATUS__PARITY_ERROR_DETECTED__SHIFT                                            0xf
+#define BIF_CFG_DEV0_EPF0_VF0_STATUS__IMMEDIATE_READINESS_MASK                                                0x0001L
+#define BIF_CFG_DEV0_EPF0_VF0_STATUS__INT_STATUS_MASK                                                         0x0008L
+#define BIF_CFG_DEV0_EPF0_VF0_STATUS__CAP_LIST_MASK                                                           0x0010L
+#define BIF_CFG_DEV0_EPF0_VF0_STATUS__PCI_66_CAP_MASK                                                         0x0020L
+#define BIF_CFG_DEV0_EPF0_VF0_STATUS__FAST_BACK_CAPABLE_MASK                                                  0x0080L
+#define BIF_CFG_DEV0_EPF0_VF0_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                           0x0100L
+#define BIF_CFG_DEV0_EPF0_VF0_STATUS__DEVSEL_TIMING_MASK                                                      0x0600L
+#define BIF_CFG_DEV0_EPF0_VF0_STATUS__SIGNAL_TARGET_ABORT_MASK                                                0x0800L
+#define BIF_CFG_DEV0_EPF0_VF0_STATUS__RECEIVED_TARGET_ABORT_MASK                                              0x1000L
+#define BIF_CFG_DEV0_EPF0_VF0_STATUS__RECEIVED_MASTER_ABORT_MASK                                              0x2000L
+#define BIF_CFG_DEV0_EPF0_VF0_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                              0x4000L
+#define BIF_CFG_DEV0_EPF0_VF0_STATUS__PARITY_ERROR_DETECTED_MASK                                              0x8000L
+//BIF_CFG_DEV0_EPF0_VF0_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF0_REVISION_ID__MINOR_REV_ID__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF0_VF0_REVISION_ID__MAJOR_REV_ID__SHIFT                                                0x4
+#define BIF_CFG_DEV0_EPF0_VF0_REVISION_ID__MINOR_REV_ID_MASK                                                  0x0FL
+#define BIF_CFG_DEV0_EPF0_VF0_REVISION_ID__MAJOR_REV_ID_MASK                                                  0xF0L
+//BIF_CFG_DEV0_EPF0_VF0_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF0_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_VF0_PROG_INTERFACE__PROG_INTERFACE_MASK                                             0xFFL
+//BIF_CFG_DEV0_EPF0_VF0_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF0_SUB_CLASS__SUB_CLASS__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_VF0_SUB_CLASS__SUB_CLASS_MASK                                                       0xFFL
+//BIF_CFG_DEV0_EPF0_VF0_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF0_BASE_CLASS__BASE_CLASS__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF0_BASE_CLASS__BASE_CLASS_MASK                                                     0xFFL
+//BIF_CFG_DEV0_EPF0_VF0_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF0_VF0_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                0xFFL
+//BIF_CFG_DEV0_EPF0_VF0_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF0_LATENCY__LATENCY_TIMER__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF0_LATENCY__LATENCY_TIMER_MASK                                                     0xFFL
+//BIF_CFG_DEV0_EPF0_VF0_HEADER
+#define BIF_CFG_DEV0_EPF0_VF0_HEADER__HEADER_TYPE__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF0_VF0_HEADER__DEVICE_TYPE__SHIFT                                                      0x7
+#define BIF_CFG_DEV0_EPF0_VF0_HEADER__HEADER_TYPE_MASK                                                        0x7FL
+#define BIF_CFG_DEV0_EPF0_VF0_HEADER__DEVICE_TYPE_MASK                                                        0x80L
+//BIF_CFG_DEV0_EPF0_VF0_BIST
+#define BIF_CFG_DEV0_EPF0_VF0_BIST__BIST_COMP__SHIFT                                                          0x0
+#define BIF_CFG_DEV0_EPF0_VF0_BIST__BIST_STRT__SHIFT                                                          0x6
+#define BIF_CFG_DEV0_EPF0_VF0_BIST__BIST_CAP__SHIFT                                                           0x7
+#define BIF_CFG_DEV0_EPF0_VF0_BIST__BIST_COMP_MASK                                                            0x0FL
+#define BIF_CFG_DEV0_EPF0_VF0_BIST__BIST_STRT_MASK                                                            0x40L
+#define BIF_CFG_DEV0_EPF0_VF0_BIST__BIST_CAP_MASK                                                             0x80L
+//BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_1__BASE_ADDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_1__BASE_ADDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_2__BASE_ADDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_2__BASE_ADDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_3__BASE_ADDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_3__BASE_ADDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_4__BASE_ADDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_4__BASE_ADDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_5__BASE_ADDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_5__BASE_ADDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_6__BASE_ADDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF0_BASE_ADDR_6__BASE_ADDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_VF0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK                                           0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                                 0x10
+#define BIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                            0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF0_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                   0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT                                     0x1
+#define BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT                                    0x4
+#define BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                 0xb
+#define BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR__ROM_ENABLE_MASK                                                  0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK                                       0x0000000EL
+#define BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK                                      0x000000F0L
+#define BIF_CFG_DEV0_EPF0_VF0_ROM_BASE_ADDR__BASE_ADDR_MASK                                                   0xFFFFF800L
+//BIF_CFG_DEV0_EPF0_VF0_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF0_CAP_PTR__CAP_PTR__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF0_VF0_CAP_PTR__CAP_PTR_MASK                                                           0xFFL
+//BIF_CFG_DEV0_EPF0_VF0_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_VF0_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                             0xFFL
+//BIF_CFG_DEV0_EPF0_VF0_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF0_VF0_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                               0xFFL
+//BIF_CFG_DEV0_EPF0_VF0_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF0_MIN_GRANT__MIN_GNT__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF0_VF0_MIN_GRANT__MIN_GNT_MASK                                                         0xFFL
+//BIF_CFG_DEV0_EPF0_VF0_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF0_MAX_LATENCY__MAX_LAT__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_VF0_MAX_LATENCY__MAX_LAT_MASK                                                       0xFFL
+//BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST__CAP_ID__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                  0x8
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST__CAP_ID_MASK                                                      0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP_LIST__NEXT_PTR_MASK                                                    0xFF00L
+//BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__VERSION__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__DEVICE_TYPE__SHIFT                                                    0x4
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                               0x8
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                0x9
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__FLIT_MODE_SUPPORT__SHIFT                                              0xf
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__VERSION_MASK                                                          0x000FL
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__DEVICE_TYPE_MASK                                                      0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                  0x3E00L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CAP__FLIT_MODE_SUPPORT_MASK                                                0x8000L
+//BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                 0x3
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                 0x5
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                       0x6
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                        0x9
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                     0xf
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__RX_MPS_FIXED__SHIFT                                                 0x11
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                    0x12
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                    0x1a
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                  0x1c
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__MIXED_MPS_SUPPORTED__SHIFT                                          0x1d
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__TEE_IO_SUPPORT__SHIFT                                               0x1e
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                            0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__PHANTOM_FUNC_MASK                                                   0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__EXTENDED_TAG_MASK                                                   0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                         0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                          0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                       0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK                                       0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__RX_MPS_FIXED_MASK                                                   0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                      0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                      0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__FLR_CAPABLE_MASK                                                    0x10000000L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__MIXED_MPS_SUPPORTED_MASK                                            0x20000000L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP__TEE_IO_SUPPORT_MASK                                                 0x40000000L
+//BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                            0x1
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                0x2
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                               0x3
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                              0x4
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                            0x5
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                             0x8
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                             0x9
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                             0xa
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                 0xb
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                       0xc
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__INITIATE_FLR__SHIFT                                                0xf
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__CORR_ERR_EN_MASK                                                   0x0001L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                              0x0002L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                  0x0004L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__USR_REPORT_EN_MASK                                                 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                0x0010L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                              0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                               0x0100L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                               0x0200L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                               0x0400L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                   0x0800L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                         0x7000L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL__INITIATE_FLR_MASK                                                  0x8000L
+//BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__CORR_ERR__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                             0x1
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__FATAL_ERR__SHIFT                                                 0x2
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__USR_DETECTED__SHIFT                                              0x3
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__AUX_PWR__SHIFT                                                   0x4
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                         0x5
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                             0x6
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__CORR_ERR_MASK                                                    0x0001L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__NON_FATAL_ERR_MASK                                               0x0002L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__FATAL_ERR_MASK                                                   0x0004L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__USR_DETECTED_MASK                                                0x0008L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__AUX_PWR_MASK                                                     0x0010L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                           0x0020L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                               0x0040L
+//BIF_CFG_DEV0_EPF0_VF0_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__LINK_SPEED__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__LINK_WIDTH__SHIFT                                                     0x4
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__PM_SUPPORT__SHIFT                                                     0xa
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                               0xc
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                0xf
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                         0x12
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                    0x13
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                    0x14
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                       0x15
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                    0x16
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__PORT_NUMBER__SHIFT                                                    0x18
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__LINK_SPEED_MASK                                                       0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__LINK_WIDTH_MASK                                                       0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__PM_SUPPORT_MASK                                                       0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__L1_EXIT_LATENCY_MASK                                                  0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                           0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                      0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                      0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                         0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                      0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP__PORT_NUMBER_MASK                                                      0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__PM_CONTROL__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT                                  0x2
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                             0x3
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__LINK_DIS__SHIFT                                                      0x4
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__RETRAIN_LINK__SHIFT                                                  0x5
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                              0x6
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                 0x7
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                   0x9
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                     0xa
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                     0xb
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__SRIS_CLOCKING__SHIFT                                                 0xc
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__FLIT_MODE_DISABLE__SHIFT                                             0xd
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                         0xe
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__PM_CONTROL_MASK                                                      0x0003L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK                                    0x0004L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                               0x0008L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__LINK_DIS_MASK                                                        0x0010L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__RETRAIN_LINK_MASK                                                    0x0020L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                0x0040L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__EXTENDED_SYNC_MASK                                                   0x0080L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                       0x0100L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                     0x0200L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                       0x0400L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                       0x0800L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__SRIS_CLOCKING_MASK                                                   0x1000L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__FLIT_MODE_DISABLE_MASK                                               0x2000L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                           0xC000L
+//BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                       0x4
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__LINK_TRAINING__SHIFT                                               0xb
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                              0xc
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__DL_ACTIVE__SHIFT                                                   0xd
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                   0xe
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                   0xf
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                            0x000FL
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                         0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__LINK_TRAINING_MASK                                                 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                0x1000L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__DL_ACTIVE_MASK                                                     0x2000L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                     0x4000L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                     0x8000L
+//BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                   0x4
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                    0x5
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                  0x6
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                  0x7
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                  0x8
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                      0x9
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                   0xa
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                               0xb
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                          0xc
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                               0xe
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                             0x10
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                             0x11
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                              0x12
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                0x14
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                0x15
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                    0x16
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                              0x18
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                               0x1a
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                               0x1f
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                   0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                     0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                      0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                    0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                    0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                    0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                        0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                     0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                            0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                               0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                               0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                  0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                  0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                      0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                            0x4
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                          0x5
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                        0x6
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                   0x7
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                         0x8
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                      0x9
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__LTR_EN__SHIFT                                                     0xa
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                               0xb
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                               0xc
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__OBFF_EN__SHIFT                                                    0xd
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                0xf
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                            0x000FL
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                              0x0010L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                            0x0020L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                          0x0040L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                     0x0080L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                           0x0100L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                        0x0200L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__LTR_EN_MASK                                                       0x0400L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__OBFF_EN_MASK                                                      0x6000L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                  0x8000L
+//BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS2__RESERVED__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS2__RESERVED_MASK                                                   0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                          0x1
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                           0x8
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT                                      0x9
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                      0x10
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                     0x17
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                     0x18
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                 0x1f
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                            0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                             0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK                                        0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                        0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                       0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                       0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CAP2__DRS_SUPPORTED_MASK                                                   0x80000000L
+//BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                             0x4
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                  0x5
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                        0x6
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                  0x7
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                         0xa
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                               0xb
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                        0xc
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                              0x000FL
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                               0x0010L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                    0x0020L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                          0x0040L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__XMIT_MARGIN_MASK                                                    0x0380L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                           0x0400L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                          0xF000L
+//BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                  0x1
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                            0x2
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                            0x3
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                            0x4
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                              0x5
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                          0x6
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                          0x7
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                       0x8
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__FLIT_MODE_STATUS__SHIFT                                           0xa
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                              0xc
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                       0xf
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                         0x0001L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                    0x0002L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                              0x0004L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                              0x0008L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                              0x0010L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                0x0020L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                            0x0040L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                            0x0080L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                         0x0300L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__FLIT_MODE_STATUS_MASK                                             0x0400L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                0x7000L
+#define BIF_CFG_DEV0_EPF0_VF0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                         0x8000L
+//BIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST__CAP_ID__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST__CAP_ID_MASK                                                       0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_CAP_LIST__NEXT_PTR_MASK                                                     0xFF00L
+//BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_EN__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                              0x1
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                               0x4
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                  0x7
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                  0x8
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT                                       0x9
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT                                        0xa
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_EN_MASK                                                       0x0001L
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                0x000EL
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_64BIT_MASK                                                    0x0080L
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                    0x0100L
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK                                         0x0200L
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK                                          0x0400L
+//BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                         0x2
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                           0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                           0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA__MSI_DATA__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA__MSI_DATA_MASK                                                     0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK                                             0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_MASK__MSI_MASK__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_MASK__MSI_MASK_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                               0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK                                       0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_MASK_64__MSI_MASK_64__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_MASK_64__MSI_MASK_64_MASK                                                   0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_PENDING__MSI_PENDING__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_PENDING__MSI_PENDING_MASK                                                   0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_VF0_MSI_PENDING_64__MSI_PENDING_64_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST__CAP_ID__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                  0x8
+#define BIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST__CAP_ID_MASK                                                      0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF0_MSIX_CAP_LIST__NEXT_PTR_MASK                                                    0xFF00L
+//BIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                            0xe
+#define BIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                   0xf
+#define BIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                             0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                              0x4000L
+#define BIF_CFG_DEV0_EPF0_VF0_MSIX_MSG_CNTL__MSIX_EN_MASK                                                     0x8000L
+//BIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                            0x3
+#define BIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                                 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                              0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF0_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF0_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                                0x3
+#define BIF_CFG_DEV0_EPF0_VF0_MSIX_PBA__MSIX_PBA_BIR_MASK                                                     0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF0_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                  0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                0x0
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                               0x10
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                              0x14
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                  0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                       0x10
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                    0x14
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                         0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                      0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_PCIE_DEVICE3_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_DEVICE3_ENH_CAP_LIST__CAP_ID__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_DEVICE3_ENH_CAP_LIST__CAP_VER__SHIFT                                       0x10
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_DEVICE3_ENH_CAP_LIST__NEXT_PTR__SHIFT                                      0x14
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_DEVICE3_ENH_CAP_LIST__CAP_ID_MASK                                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_DEVICE3_ENH_CAP_LIST__CAP_VER_MASK                                         0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_DEVICE3_ENH_CAP_LIST__NEXT_PTR_MASK                                        0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP3
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP3__DMWR_REQUEST_ROUTING_SUPPORTED__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_COMPLETER_SUPPORTED__SHIFT                   0x1
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_REQUESTER_SUPPORTED__SHIFT                   0x2
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP3__RECEIVER_L0P_SUPPORTED__SHIFT                                      0x3
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP3__PORT_L0P_EXIT_LATENCY__SHIFT                                       0x4
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP3__RETIMER_L0P_EXIT_LATENCY__SHIFT                                    0x7
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP3__DMWR_REQUEST_ROUTING_SUPPORTED_MASK                                0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_COMPLETER_SUPPORTED_MASK                     0x00000002L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_REQUESTER_SUPPORTED_MASK                     0x00000004L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP3__RECEIVER_L0P_SUPPORTED_MASK                                        0x00000008L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP3__PORT_L0P_EXIT_LATENCY_MASK                                         0x00000070L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CAP3__RETIMER_L0P_EXIT_LATENCY_MASK                                      0x00000380L
+//BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL3
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL3__DMWR_REQUEST_ENABLE__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL3__DMWR_EGRESS_BLOCKING__SHIFT                                       0x1
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL3__DEVICE_CNTL3_14BIT_TAG_REQUESTER_ENABLE__SHIFT                    0x2
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL3__L0P_ENABLE__SHIFT                                                 0x3
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL3__TARGET_LINK_WIDTH__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL3__DMWR_REQUEST_ENABLE_MASK                                          0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL3__DMWR_EGRESS_BLOCKING_MASK                                         0x00000002L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL3__DEVICE_CNTL3_14BIT_TAG_REQUESTER_ENABLE_MASK                      0x00000004L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL3__L0P_ENABLE_MASK                                                   0x00000008L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_CNTL3__TARGET_LINK_WIDTH_MASK                                            0x00000070L
+//BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS3
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS3__INITIAL_LINK_WIDTH__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS3__SEGMENT_CAPTURED__SHIFT                                         0x3
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS3__REMOTE_L0P_SUPPORTED__SHIFT                                     0x4
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS3__INITIAL_LINK_WIDTH_MASK                                         0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS3__SEGMENT_CAPTURED_MASK                                           0x00000008L
+#define BIF_CFG_DEV0_EPF0_VF0_DEVICE_STATUS3__REMOTE_L0P_SUPPORTED_MASK                                       0x00000010L
+//BIF_CFG_DEV0_EPF0_VF0_PCIE_NULL1_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_NULL1_ENH_CAP_LIST__CAP_ID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_NULL1_ENH_CAP_LIST__CAP_VER__SHIFT                                         0x10
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_NULL1_ENH_CAP_LIST__NEXT_PTR__SHIFT                                        0x14
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_NULL1_ENH_CAP_LIST__CAP_ID_MASK                                            0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_NULL1_ENH_CAP_LIST__CAP_VER_MASK                                           0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_NULL1_ENH_CAP_LIST__NEXT_PTR_MASK                                          0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF0_PCIE_NULL2_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_NULL2_ENH_CAP_LIST__CAP_ID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_NULL2_ENH_CAP_LIST__CAP_VER__SHIFT                                         0x10
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_NULL2_ENH_CAP_LIST__NEXT_PTR__SHIFT                                        0x14
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_NULL2_ENH_CAP_LIST__CAP_ID_MASK                                            0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_NULL2_ENH_CAP_LIST__CAP_VER_MASK                                           0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_NULL2_ENH_CAP_LIST__NEXT_PTR_MASK                                          0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                  0x14
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                      0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                     0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                    0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                   0x4
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                0x5
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                   0xc
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                    0xd
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                               0xe
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                             0xf
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                 0x10
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                  0x11
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                   0x12
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                  0x13
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                            0x14
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                             0x15
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                            0x16
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                            0x17
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                   0x18
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                    0x19
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT               0x1a
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__DMWR_REQUEST_EGRESS_BLOCKED_STATUS__SHIFT               0x1b
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__IDE_CHECK_FAILED_STATUS__SHIFT                          0x1c
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__MISROUTED_IDE_TLP_STATUS__SHIFT                         0x1d
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__PCRC_CHECK_FAILED_STATUS__SHIFT                         0x1e
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                     0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                  0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                     0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                      0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                               0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                   0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                    0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                     0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                    0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                              0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                               0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                              0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                              0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                     0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                      0x02000000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__DMWR_REQUEST_EGRESS_BLOCKED_STATUS_MASK                 0x08000000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__IDE_CHECK_FAILED_STATUS_MASK                            0x10000000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__MISROUTED_IDE_TLP_STATUS_MASK                           0x20000000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_STATUS__PCRC_CHECK_FAILED_STATUS_MASK                           0x40000000L
+//BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                       0x4
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                    0x5
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                       0xc
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                        0xd
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                   0xe
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                 0xf
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                      0x11
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                       0x12
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                      0x13
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                0x14
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                 0x15
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                0x16
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                0x17
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                       0x18
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                        0x19
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                   0x1a
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__DMWR_REQUEST_EGRESS_BLOCKED_MASK__SHIFT                   0x1b
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__IDE_CHECK_FAILED_MASK__SHIFT                              0x1c
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__MISROUTED_IDE_TLP_MASK__SHIFT                             0x1d
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__PCRC_CHECK_FAILED_MASK__SHIFT                             0x1e
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                         0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                      0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                         0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                          0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                     0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                   0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                       0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                        0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                         0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                        0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                  0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                   0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                  0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                  0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                         0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                          0x02000000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                     0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__DMWR_REQUEST_EGRESS_BLOCKED_MASK_MASK                     0x08000000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__IDE_CHECK_FAILED_MASK_MASK                                0x10000000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__MISROUTED_IDE_TLP_MASK_MASK                               0x20000000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_MASK__PCRC_CHECK_FAILED_MASK_MASK                               0x40000000L
+//BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                               0x4
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                            0x5
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                               0xc
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                0xd
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                           0xe
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                         0xf
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                             0x10
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                              0x11
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                               0x12
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                              0x13
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                        0x14
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                         0x15
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                        0x16
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                        0x17
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT               0x18
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                0x19
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT           0x1a
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__DMWR_REQUEST_EGRESS_BLOCKED_SEVERITY__SHIFT           0x1b
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__IDE_CHECK_FAILED_SEVERITY__SHIFT                      0x1c
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__MISROUTED_IDE_TLP_SEVERITY__SHIFT                     0x1d
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__PCRC_CHECK_FAILED_SEVERITY__SHIFT                     0x1e
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                              0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                  0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                             0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                           0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                               0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                          0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                           0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                          0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                          0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                  0x02000000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK             0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__DMWR_REQUEST_EGRESS_BLOCKED_SEVERITY_MASK             0x08000000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__IDE_CHECK_FAILED_SEVERITY_MASK                        0x10000000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__MISROUTED_IDE_TLP_SEVERITY_MASK                       0x20000000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_UNCORR_ERR_SEVERITY__PCRC_CHECK_FAILED_SEVERITY_MASK                       0x40000000L
+//BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                     0x6
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                    0x7
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                         0x8
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                        0xc
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                       0xd
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                0xe
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                                0xf
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                       0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                       0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                      0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                           0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                          0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                         0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                  0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                  0x00008000L
+//BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                         0x6
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                        0x7
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                             0x8
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                            0xc
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                           0xd
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                    0xe
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                    0xf
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                           0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                           0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                          0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                               0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                              0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                             0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                      0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                      0x00008000L
+//BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT                                      0x5
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT                                       0x6
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                    0x7
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                0x9
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                 0xa
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                            0xb
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT                    0xc
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__HEADER_LOG_SIZE__SHIFT                                   0xd
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_WAS_FLIT_MODE__SHIFT                          0x12
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_SIZE__SHIFT                                   0x13
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                       0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK                                        0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK                                         0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                      0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                       0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                  0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                   0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                              0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK                      0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__HEADER_LOG_SIZE_MASK                                     0x0003E000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_WAS_FLIT_MODE_MASK                            0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_SIZE_MASK                                     0x00F80000L
+//BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG0__TLP_HDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG1__TLP_HDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG2__TLP_HDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG3__TLP_HDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG4
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG4__TLP_HDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG4__TLP_HDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                           0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG5
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG5__TLP_HDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG5__TLP_HDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                           0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG6
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG6__TLP_HDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG6__TLP_HDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                           0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG7
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG7__TLP_HDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG7__TLP_HDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                           0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG8
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG8__TLP_HDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG8__TLP_HDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG9
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG9__TLP_HDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG9__TLP_HDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG10
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG10__TLP_HDR__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG10__TLP_HDR_MASK                                                    0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG11
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG11__TLP_HDR__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG11__TLP_HDR_MASK                                                    0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG12
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG12__TLP_HDR__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG12__TLP_HDR_MASK                                                    0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG13
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG13__TLP_HDR__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_HDR_LOG13__TLP_HDR_MASK                                                    0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF0_PCIE_RTR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF0_RTR_DATA1
+#define BIF_CFG_DEV0_EPF0_VF0_RTR_DATA1__RESET_TIME__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF0_VF0_RTR_DATA1__DLUP_TIME__SHIFT                                                     0xc
+#define BIF_CFG_DEV0_EPF0_VF0_RTR_DATA1__RTR_VALID__SHIFT                                                     0x1f
+#define BIF_CFG_DEV0_EPF0_VF0_RTR_DATA1__RESET_TIME_MASK                                                      0x00000FFFL
+#define BIF_CFG_DEV0_EPF0_VF0_RTR_DATA1__DLUP_TIME_MASK                                                       0x00FFF000L
+#define BIF_CFG_DEV0_EPF0_VF0_RTR_DATA1__RTR_VALID_MASK                                                       0x80000000L
+//BIF_CFG_DEV0_EPF0_VF0_RTR_DATA2
+#define BIF_CFG_DEV0_EPF0_VF0_RTR_DATA2__FLR_TIME__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF0_VF0_RTR_DATA2__D3HOTD0_TIME__SHIFT                                                  0xc
+#define BIF_CFG_DEV0_EPF0_VF0_RTR_DATA2__FLR_TIME_MASK                                                        0x00000FFFL
+#define BIF_CFG_DEV0_EPF0_VF0_RTR_DATA2__D3HOTD0_TIME_MASK                                                    0x00FFF000L
+//BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                    0x1
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                          0x8
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                     0x0001L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                      0x0002L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                            0xFF00L
+//BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                    0x1
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                        0x4
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                     0x0001L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                      0x0002L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                          0x0070L
+//BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT                                       0x5
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT                                0x6
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED__SHIFT                                 0x7
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP__TEE_EXCLUSIVE_ATTR_SUPPORTED__SHIFT                               0x9
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK                                           0x001FL
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK                                         0x0020L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK                                  0x0040L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED_MASK                                   0x0080L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CAP__TEE_EXCLUSIVE_ATTR_SUPPORTED_MASK                                 0x0200L
+//BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CNTL__STU__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CNTL__TEE_EXCLUSIVE_ATTR_ENABLE__SHIFT                                 0xa
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT                                                0xf
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CNTL__STU_MASK                                                         0x001FL
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CNTL__TEE_EXCLUSIVE_ATTR_ENABLE_MASK                                   0x0400L
+#define BIF_CFG_DEV0_EPF0_VF0_PCIE_ATS_CNTL__ATC_ENABLE_MASK                                                  0x8000L
+
+
+// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_vf1_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF1_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF1_VENDOR_ID__VENDOR_ID__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_VF1_VENDOR_ID__VENDOR_ID_MASK                                                       0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_ID__DEVICE_ID__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_ID__DEVICE_ID_MASK                                                       0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__IO_ACCESS_EN__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__MEM_ACCESS_EN__SHIFT                                                   0x1
+#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__BUS_MASTER_EN__SHIFT                                                   0x2
+#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                0x3
+#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                         0x4
+#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__PAL_SNOOP_EN__SHIFT                                                    0x5
+#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                           0x6
+#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__AD_STEPPING__SHIFT                                                     0x7
+#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__SERR_EN__SHIFT                                                         0x8
+#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__FAST_B2B_EN__SHIFT                                                     0x9
+#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__INT_DIS__SHIFT                                                         0xa
+#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__IO_ACCESS_EN_MASK                                                      0x0001L
+#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__MEM_ACCESS_EN_MASK                                                     0x0002L
+#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__BUS_MASTER_EN_MASK                                                     0x0004L
+#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__SPECIAL_CYCLE_EN_MASK                                                  0x0008L
+#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                           0x0010L
+#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__PAL_SNOOP_EN_MASK                                                      0x0020L
+#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__PARITY_ERROR_RESPONSE_MASK                                             0x0040L
+#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__AD_STEPPING_MASK                                                       0x0080L
+#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__SERR_EN_MASK                                                           0x0100L
+#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__FAST_B2B_EN_MASK                                                       0x0200L
+#define BIF_CFG_DEV0_EPF0_VF1_COMMAND__INT_DIS_MASK                                                           0x0400L
+//BIF_CFG_DEV0_EPF0_VF1_STATUS
+#define BIF_CFG_DEV0_EPF0_VF1_STATUS__IMMEDIATE_READINESS__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF0_VF1_STATUS__INT_STATUS__SHIFT                                                       0x3
+#define BIF_CFG_DEV0_EPF0_VF1_STATUS__CAP_LIST__SHIFT                                                         0x4
+#define BIF_CFG_DEV0_EPF0_VF1_STATUS__PCI_66_CAP__SHIFT                                                       0x5
+#define BIF_CFG_DEV0_EPF0_VF1_STATUS__FAST_BACK_CAPABLE__SHIFT                                                0x7
+#define BIF_CFG_DEV0_EPF0_VF1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                         0x8
+#define BIF_CFG_DEV0_EPF0_VF1_STATUS__DEVSEL_TIMING__SHIFT                                                    0x9
+#define BIF_CFG_DEV0_EPF0_VF1_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                              0xb
+#define BIF_CFG_DEV0_EPF0_VF1_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                            0xc
+#define BIF_CFG_DEV0_EPF0_VF1_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                            0xd
+#define BIF_CFG_DEV0_EPF0_VF1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                            0xe
+#define BIF_CFG_DEV0_EPF0_VF1_STATUS__PARITY_ERROR_DETECTED__SHIFT                                            0xf
+#define BIF_CFG_DEV0_EPF0_VF1_STATUS__IMMEDIATE_READINESS_MASK                                                0x0001L
+#define BIF_CFG_DEV0_EPF0_VF1_STATUS__INT_STATUS_MASK                                                         0x0008L
+#define BIF_CFG_DEV0_EPF0_VF1_STATUS__CAP_LIST_MASK                                                           0x0010L
+#define BIF_CFG_DEV0_EPF0_VF1_STATUS__PCI_66_CAP_MASK                                                         0x0020L
+#define BIF_CFG_DEV0_EPF0_VF1_STATUS__FAST_BACK_CAPABLE_MASK                                                  0x0080L
+#define BIF_CFG_DEV0_EPF0_VF1_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                           0x0100L
+#define BIF_CFG_DEV0_EPF0_VF1_STATUS__DEVSEL_TIMING_MASK                                                      0x0600L
+#define BIF_CFG_DEV0_EPF0_VF1_STATUS__SIGNAL_TARGET_ABORT_MASK                                                0x0800L
+#define BIF_CFG_DEV0_EPF0_VF1_STATUS__RECEIVED_TARGET_ABORT_MASK                                              0x1000L
+#define BIF_CFG_DEV0_EPF0_VF1_STATUS__RECEIVED_MASTER_ABORT_MASK                                              0x2000L
+#define BIF_CFG_DEV0_EPF0_VF1_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                              0x4000L
+#define BIF_CFG_DEV0_EPF0_VF1_STATUS__PARITY_ERROR_DETECTED_MASK                                              0x8000L
+//BIF_CFG_DEV0_EPF0_VF1_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF1_REVISION_ID__MINOR_REV_ID__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF0_VF1_REVISION_ID__MAJOR_REV_ID__SHIFT                                                0x4
+#define BIF_CFG_DEV0_EPF0_VF1_REVISION_ID__MINOR_REV_ID_MASK                                                  0x0FL
+#define BIF_CFG_DEV0_EPF0_VF1_REVISION_ID__MAJOR_REV_ID_MASK                                                  0xF0L
+//BIF_CFG_DEV0_EPF0_VF1_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF1_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_VF1_PROG_INTERFACE__PROG_INTERFACE_MASK                                             0xFFL
+//BIF_CFG_DEV0_EPF0_VF1_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF1_SUB_CLASS__SUB_CLASS__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_VF1_SUB_CLASS__SUB_CLASS_MASK                                                       0xFFL
+//BIF_CFG_DEV0_EPF0_VF1_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF1_BASE_CLASS__BASE_CLASS__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF1_BASE_CLASS__BASE_CLASS_MASK                                                     0xFFL
+//BIF_CFG_DEV0_EPF0_VF1_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF0_VF1_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                0xFFL
+//BIF_CFG_DEV0_EPF0_VF1_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF1_LATENCY__LATENCY_TIMER__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF1_LATENCY__LATENCY_TIMER_MASK                                                     0xFFL
+//BIF_CFG_DEV0_EPF0_VF1_HEADER
+#define BIF_CFG_DEV0_EPF0_VF1_HEADER__HEADER_TYPE__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF0_VF1_HEADER__DEVICE_TYPE__SHIFT                                                      0x7
+#define BIF_CFG_DEV0_EPF0_VF1_HEADER__HEADER_TYPE_MASK                                                        0x7FL
+#define BIF_CFG_DEV0_EPF0_VF1_HEADER__DEVICE_TYPE_MASK                                                        0x80L
+//BIF_CFG_DEV0_EPF0_VF1_BIST
+#define BIF_CFG_DEV0_EPF0_VF1_BIST__BIST_COMP__SHIFT                                                          0x0
+#define BIF_CFG_DEV0_EPF0_VF1_BIST__BIST_STRT__SHIFT                                                          0x6
+#define BIF_CFG_DEV0_EPF0_VF1_BIST__BIST_CAP__SHIFT                                                           0x7
+#define BIF_CFG_DEV0_EPF0_VF1_BIST__BIST_COMP_MASK                                                            0x0FL
+#define BIF_CFG_DEV0_EPF0_VF1_BIST__BIST_STRT_MASK                                                            0x40L
+#define BIF_CFG_DEV0_EPF0_VF1_BIST__BIST_CAP_MASK                                                             0x80L
+//BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_1__BASE_ADDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_1__BASE_ADDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_2__BASE_ADDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_2__BASE_ADDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_3__BASE_ADDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_3__BASE_ADDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_4__BASE_ADDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_4__BASE_ADDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_5__BASE_ADDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_5__BASE_ADDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_6__BASE_ADDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF1_BASE_ADDR_6__BASE_ADDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_VF1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK                                           0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                                 0x10
+#define BIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                            0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF1_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                   0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR__ROM_ENABLE__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT                                     0x1
+#define BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT                                    0x4
+#define BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                 0xb
+#define BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR__ROM_ENABLE_MASK                                                  0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK                                       0x0000000EL
+#define BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK                                      0x000000F0L
+#define BIF_CFG_DEV0_EPF0_VF1_ROM_BASE_ADDR__BASE_ADDR_MASK                                                   0xFFFFF800L
+//BIF_CFG_DEV0_EPF0_VF1_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF1_CAP_PTR__CAP_PTR__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF0_VF1_CAP_PTR__CAP_PTR_MASK                                                           0xFFL
+//BIF_CFG_DEV0_EPF0_VF1_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_VF1_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                             0xFFL
+//BIF_CFG_DEV0_EPF0_VF1_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF0_VF1_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                               0xFFL
+//BIF_CFG_DEV0_EPF0_VF1_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF1_MIN_GRANT__MIN_GNT__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF0_VF1_MIN_GRANT__MIN_GNT_MASK                                                         0xFFL
+//BIF_CFG_DEV0_EPF0_VF1_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF1_MAX_LATENCY__MAX_LAT__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_VF1_MAX_LATENCY__MAX_LAT_MASK                                                       0xFFL
+//BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST__CAP_ID__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                  0x8
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST__CAP_ID_MASK                                                      0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP_LIST__NEXT_PTR_MASK                                                    0xFF00L
+//BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__VERSION__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__DEVICE_TYPE__SHIFT                                                    0x4
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                               0x8
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                0x9
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__FLIT_MODE_SUPPORT__SHIFT                                              0xf
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__VERSION_MASK                                                          0x000FL
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__DEVICE_TYPE_MASK                                                      0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                  0x3E00L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CAP__FLIT_MODE_SUPPORT_MASK                                                0x8000L
+//BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                 0x3
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                 0x5
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                       0x6
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                        0x9
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                     0xf
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__RX_MPS_FIXED__SHIFT                                                 0x11
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                    0x12
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                    0x1a
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                  0x1c
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__MIXED_MPS_SUPPORTED__SHIFT                                          0x1d
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__TEE_IO_SUPPORT__SHIFT                                               0x1e
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                            0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__PHANTOM_FUNC_MASK                                                   0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__EXTENDED_TAG_MASK                                                   0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                         0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                          0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                       0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK                                       0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__RX_MPS_FIXED_MASK                                                   0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                      0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                      0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__FLR_CAPABLE_MASK                                                    0x10000000L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__MIXED_MPS_SUPPORTED_MASK                                            0x20000000L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP__TEE_IO_SUPPORT_MASK                                                 0x40000000L
+//BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                            0x1
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                0x2
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                               0x3
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                              0x4
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                            0x5
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                             0x8
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                             0x9
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                             0xa
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                 0xb
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                       0xc
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__INITIATE_FLR__SHIFT                                                0xf
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__CORR_ERR_EN_MASK                                                   0x0001L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                              0x0002L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                  0x0004L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__USR_REPORT_EN_MASK                                                 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                0x0010L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                              0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                               0x0100L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                               0x0200L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                               0x0400L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                   0x0800L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                         0x7000L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL__INITIATE_FLR_MASK                                                  0x8000L
+//BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__CORR_ERR__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                             0x1
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__FATAL_ERR__SHIFT                                                 0x2
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__USR_DETECTED__SHIFT                                              0x3
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__AUX_PWR__SHIFT                                                   0x4
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                         0x5
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                             0x6
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__CORR_ERR_MASK                                                    0x0001L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__NON_FATAL_ERR_MASK                                               0x0002L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__FATAL_ERR_MASK                                                   0x0004L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__USR_DETECTED_MASK                                                0x0008L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__AUX_PWR_MASK                                                     0x0010L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                           0x0020L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                               0x0040L
+//BIF_CFG_DEV0_EPF0_VF1_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__LINK_SPEED__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__LINK_WIDTH__SHIFT                                                     0x4
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__PM_SUPPORT__SHIFT                                                     0xa
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                               0xc
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                0xf
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                         0x12
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                    0x13
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                    0x14
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                       0x15
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                    0x16
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__PORT_NUMBER__SHIFT                                                    0x18
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__LINK_SPEED_MASK                                                       0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__LINK_WIDTH_MASK                                                       0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__PM_SUPPORT_MASK                                                       0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__L1_EXIT_LATENCY_MASK                                                  0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                           0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                      0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                      0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                         0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                      0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP__PORT_NUMBER_MASK                                                      0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__PM_CONTROL__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT                                  0x2
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                             0x3
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__LINK_DIS__SHIFT                                                      0x4
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__RETRAIN_LINK__SHIFT                                                  0x5
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                              0x6
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                 0x7
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                   0x9
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                     0xa
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                     0xb
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__SRIS_CLOCKING__SHIFT                                                 0xc
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__FLIT_MODE_DISABLE__SHIFT                                             0xd
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                         0xe
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__PM_CONTROL_MASK                                                      0x0003L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK                                    0x0004L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                               0x0008L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__LINK_DIS_MASK                                                        0x0010L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__RETRAIN_LINK_MASK                                                    0x0020L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                0x0040L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__EXTENDED_SYNC_MASK                                                   0x0080L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                       0x0100L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                     0x0200L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                       0x0400L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                       0x0800L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__SRIS_CLOCKING_MASK                                                   0x1000L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__FLIT_MODE_DISABLE_MASK                                               0x2000L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                           0xC000L
+//BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                       0x4
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__LINK_TRAINING__SHIFT                                               0xb
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                              0xc
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__DL_ACTIVE__SHIFT                                                   0xd
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                   0xe
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                   0xf
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                            0x000FL
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                         0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__LINK_TRAINING_MASK                                                 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                0x1000L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__DL_ACTIVE_MASK                                                     0x2000L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                     0x4000L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                     0x8000L
+//BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                   0x4
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                    0x5
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                  0x6
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                  0x7
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                  0x8
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                      0x9
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                   0xa
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                               0xb
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                          0xc
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                               0xe
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                             0x10
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                             0x11
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                              0x12
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                0x14
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                0x15
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                    0x16
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                              0x18
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                               0x1a
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                               0x1f
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                   0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                     0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                      0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                    0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                    0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                    0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                        0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                     0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                            0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                               0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                               0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                  0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                  0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                      0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                            0x4
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                          0x5
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                        0x6
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                   0x7
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                         0x8
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                      0x9
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__LTR_EN__SHIFT                                                     0xa
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                               0xb
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                               0xc
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__OBFF_EN__SHIFT                                                    0xd
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                0xf
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                            0x000FL
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                              0x0010L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                            0x0020L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                          0x0040L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                     0x0080L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                           0x0100L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                        0x0200L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__LTR_EN_MASK                                                       0x0400L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__OBFF_EN_MASK                                                      0x6000L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                  0x8000L
+//BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS2__RESERVED__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS2__RESERVED_MASK                                                   0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                          0x1
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                           0x8
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT                                      0x9
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                      0x10
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                     0x17
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                     0x18
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                 0x1f
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                            0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                             0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK                                        0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                        0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                       0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                       0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CAP2__DRS_SUPPORTED_MASK                                                   0x80000000L
+//BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                             0x4
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                  0x5
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                        0x6
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                  0x7
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                         0xa
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                               0xb
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                        0xc
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                              0x000FL
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                               0x0010L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                    0x0020L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                          0x0040L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__XMIT_MARGIN_MASK                                                    0x0380L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                           0x0400L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                          0xF000L
+//BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                  0x1
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                            0x2
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                            0x3
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                            0x4
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                              0x5
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                          0x6
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                          0x7
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                       0x8
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__FLIT_MODE_STATUS__SHIFT                                           0xa
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                              0xc
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                       0xf
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                         0x0001L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                    0x0002L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                              0x0004L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                              0x0008L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                              0x0010L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                0x0020L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                            0x0040L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                            0x0080L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                         0x0300L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__FLIT_MODE_STATUS_MASK                                             0x0400L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                0x7000L
+#define BIF_CFG_DEV0_EPF0_VF1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                         0x8000L
+//BIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST__CAP_ID__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST__CAP_ID_MASK                                                       0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_CAP_LIST__NEXT_PTR_MASK                                                     0xFF00L
+//BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_EN__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                              0x1
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                               0x4
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                  0x7
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                  0x8
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT                                       0x9
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT                                        0xa
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_EN_MASK                                                       0x0001L
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                0x000EL
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_64BIT_MASK                                                    0x0080L
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                    0x0100L
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK                                         0x0200L
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK                                          0x0400L
+//BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                         0x2
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                           0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                           0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA__MSI_DATA__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA__MSI_DATA_MASK                                                     0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK                                             0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_MASK__MSI_MASK__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_MASK__MSI_MASK_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                               0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK                                       0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_MASK_64__MSI_MASK_64__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_MASK_64__MSI_MASK_64_MASK                                                   0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_PENDING__MSI_PENDING__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_PENDING__MSI_PENDING_MASK                                                   0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_VF1_MSI_PENDING_64__MSI_PENDING_64_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST__CAP_ID__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                  0x8
+#define BIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST__CAP_ID_MASK                                                      0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF1_MSIX_CAP_LIST__NEXT_PTR_MASK                                                    0xFF00L
+//BIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                            0xe
+#define BIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                   0xf
+#define BIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                             0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                              0x4000L
+#define BIF_CFG_DEV0_EPF0_VF1_MSIX_MSG_CNTL__MSIX_EN_MASK                                                     0x8000L
+//BIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                            0x3
+#define BIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                                 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                              0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF1_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF1_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                                0x3
+#define BIF_CFG_DEV0_EPF0_VF1_MSIX_PBA__MSIX_PBA_BIR_MASK                                                     0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF1_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                  0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                0x0
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                               0x10
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                              0x14
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                  0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                       0x10
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                    0x14
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                         0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                      0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_PCIE_DEVICE3_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_DEVICE3_ENH_CAP_LIST__CAP_ID__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_DEVICE3_ENH_CAP_LIST__CAP_VER__SHIFT                                       0x10
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_DEVICE3_ENH_CAP_LIST__NEXT_PTR__SHIFT                                      0x14
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_DEVICE3_ENH_CAP_LIST__CAP_ID_MASK                                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_DEVICE3_ENH_CAP_LIST__CAP_VER_MASK                                         0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_DEVICE3_ENH_CAP_LIST__NEXT_PTR_MASK                                        0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP3
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP3__DMWR_REQUEST_ROUTING_SUPPORTED__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_COMPLETER_SUPPORTED__SHIFT                   0x1
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_REQUESTER_SUPPORTED__SHIFT                   0x2
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP3__RECEIVER_L0P_SUPPORTED__SHIFT                                      0x3
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP3__PORT_L0P_EXIT_LATENCY__SHIFT                                       0x4
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP3__RETIMER_L0P_EXIT_LATENCY__SHIFT                                    0x7
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP3__DMWR_REQUEST_ROUTING_SUPPORTED_MASK                                0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_COMPLETER_SUPPORTED_MASK                     0x00000002L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_REQUESTER_SUPPORTED_MASK                     0x00000004L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP3__RECEIVER_L0P_SUPPORTED_MASK                                        0x00000008L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP3__PORT_L0P_EXIT_LATENCY_MASK                                         0x00000070L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CAP3__RETIMER_L0P_EXIT_LATENCY_MASK                                      0x00000380L
+//BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL3
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL3__DMWR_REQUEST_ENABLE__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL3__DMWR_EGRESS_BLOCKING__SHIFT                                       0x1
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL3__DEVICE_CNTL3_14BIT_TAG_REQUESTER_ENABLE__SHIFT                    0x2
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL3__L0P_ENABLE__SHIFT                                                 0x3
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL3__TARGET_LINK_WIDTH__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL3__DMWR_REQUEST_ENABLE_MASK                                          0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL3__DMWR_EGRESS_BLOCKING_MASK                                         0x00000002L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL3__DEVICE_CNTL3_14BIT_TAG_REQUESTER_ENABLE_MASK                      0x00000004L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL3__L0P_ENABLE_MASK                                                   0x00000008L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_CNTL3__TARGET_LINK_WIDTH_MASK                                            0x00000070L
+//BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS3
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS3__INITIAL_LINK_WIDTH__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS3__SEGMENT_CAPTURED__SHIFT                                         0x3
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS3__REMOTE_L0P_SUPPORTED__SHIFT                                     0x4
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS3__INITIAL_LINK_WIDTH_MASK                                         0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS3__SEGMENT_CAPTURED_MASK                                           0x00000008L
+#define BIF_CFG_DEV0_EPF0_VF1_DEVICE_STATUS3__REMOTE_L0P_SUPPORTED_MASK                                       0x00000010L
+//BIF_CFG_DEV0_EPF0_VF1_PCIE_NULL1_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_NULL1_ENH_CAP_LIST__CAP_ID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_NULL1_ENH_CAP_LIST__CAP_VER__SHIFT                                         0x10
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_NULL1_ENH_CAP_LIST__NEXT_PTR__SHIFT                                        0x14
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_NULL1_ENH_CAP_LIST__CAP_ID_MASK                                            0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_NULL1_ENH_CAP_LIST__CAP_VER_MASK                                           0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_NULL1_ENH_CAP_LIST__NEXT_PTR_MASK                                          0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF1_PCIE_NULL2_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_NULL2_ENH_CAP_LIST__CAP_ID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_NULL2_ENH_CAP_LIST__CAP_VER__SHIFT                                         0x10
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_NULL2_ENH_CAP_LIST__NEXT_PTR__SHIFT                                        0x14
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_NULL2_ENH_CAP_LIST__CAP_ID_MASK                                            0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_NULL2_ENH_CAP_LIST__CAP_VER_MASK                                           0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_NULL2_ENH_CAP_LIST__NEXT_PTR_MASK                                          0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                  0x14
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                      0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                     0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                    0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                   0x4
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                0x5
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                   0xc
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                    0xd
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                               0xe
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                             0xf
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                 0x10
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                  0x11
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                   0x12
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                  0x13
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                            0x14
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                             0x15
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                            0x16
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                            0x17
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                   0x18
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                    0x19
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT               0x1a
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__DMWR_REQUEST_EGRESS_BLOCKED_STATUS__SHIFT               0x1b
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__IDE_CHECK_FAILED_STATUS__SHIFT                          0x1c
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__MISROUTED_IDE_TLP_STATUS__SHIFT                         0x1d
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__PCRC_CHECK_FAILED_STATUS__SHIFT                         0x1e
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                     0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                  0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                     0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                      0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                               0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                   0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                    0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                     0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                    0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                              0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                               0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                              0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                              0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                     0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                      0x02000000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__DMWR_REQUEST_EGRESS_BLOCKED_STATUS_MASK                 0x08000000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__IDE_CHECK_FAILED_STATUS_MASK                            0x10000000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__MISROUTED_IDE_TLP_STATUS_MASK                           0x20000000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_STATUS__PCRC_CHECK_FAILED_STATUS_MASK                           0x40000000L
+//BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                       0x4
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                    0x5
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                       0xc
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                        0xd
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                   0xe
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                 0xf
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                      0x11
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                       0x12
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                      0x13
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                0x14
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                 0x15
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                0x16
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                0x17
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                       0x18
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                        0x19
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                   0x1a
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__DMWR_REQUEST_EGRESS_BLOCKED_MASK__SHIFT                   0x1b
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__IDE_CHECK_FAILED_MASK__SHIFT                              0x1c
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__MISROUTED_IDE_TLP_MASK__SHIFT                             0x1d
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__PCRC_CHECK_FAILED_MASK__SHIFT                             0x1e
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                         0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                      0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                         0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                          0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                     0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                   0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                       0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                        0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                         0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                        0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                  0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                   0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                  0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                  0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                         0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                          0x02000000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                     0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__DMWR_REQUEST_EGRESS_BLOCKED_MASK_MASK                     0x08000000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__IDE_CHECK_FAILED_MASK_MASK                                0x10000000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__MISROUTED_IDE_TLP_MASK_MASK                               0x20000000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_MASK__PCRC_CHECK_FAILED_MASK_MASK                               0x40000000L
+//BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                               0x4
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                            0x5
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                               0xc
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                0xd
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                           0xe
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                         0xf
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                             0x10
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                              0x11
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                               0x12
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                              0x13
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                        0x14
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                         0x15
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                        0x16
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                        0x17
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT               0x18
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                0x19
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT           0x1a
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__DMWR_REQUEST_EGRESS_BLOCKED_SEVERITY__SHIFT           0x1b
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__IDE_CHECK_FAILED_SEVERITY__SHIFT                      0x1c
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__MISROUTED_IDE_TLP_SEVERITY__SHIFT                     0x1d
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__PCRC_CHECK_FAILED_SEVERITY__SHIFT                     0x1e
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                              0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                  0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                             0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                           0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                               0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                          0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                           0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                          0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                          0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                  0x02000000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK             0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__DMWR_REQUEST_EGRESS_BLOCKED_SEVERITY_MASK             0x08000000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__IDE_CHECK_FAILED_SEVERITY_MASK                        0x10000000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__MISROUTED_IDE_TLP_SEVERITY_MASK                       0x20000000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_UNCORR_ERR_SEVERITY__PCRC_CHECK_FAILED_SEVERITY_MASK                       0x40000000L
+//BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                     0x6
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                    0x7
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                         0x8
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                        0xc
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                       0xd
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                0xe
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                                0xf
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                       0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                       0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                      0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                           0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                          0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                         0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                  0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                  0x00008000L
+//BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                         0x6
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                        0x7
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                             0x8
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                            0xc
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                           0xd
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                    0xe
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                    0xf
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                           0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                           0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                          0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                               0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                              0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                             0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                      0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                      0x00008000L
+//BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT                                      0x5
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT                                       0x6
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                    0x7
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                0x9
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                 0xa
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                            0xb
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT                    0xc
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__HEADER_LOG_SIZE__SHIFT                                   0xd
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_WAS_FLIT_MODE__SHIFT                          0x12
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_SIZE__SHIFT                                   0x13
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                       0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK                                        0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK                                         0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                      0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                       0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                  0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                   0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                              0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK                      0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__HEADER_LOG_SIZE_MASK                                     0x0003E000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_WAS_FLIT_MODE_MASK                            0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_SIZE_MASK                                     0x00F80000L
+//BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG0__TLP_HDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG1__TLP_HDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG2__TLP_HDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG3__TLP_HDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG4
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG4__TLP_HDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG4__TLP_HDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                           0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG5
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG5__TLP_HDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG5__TLP_HDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                           0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG6
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG6__TLP_HDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG6__TLP_HDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                           0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG7
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG7__TLP_HDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG7__TLP_HDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                           0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG8
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG8__TLP_HDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG8__TLP_HDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG9
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG9__TLP_HDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG9__TLP_HDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG10
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG10__TLP_HDR__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG10__TLP_HDR_MASK                                                    0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG11
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG11__TLP_HDR__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG11__TLP_HDR_MASK                                                    0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG12
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG12__TLP_HDR__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG12__TLP_HDR_MASK                                                    0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG13
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG13__TLP_HDR__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_HDR_LOG13__TLP_HDR_MASK                                                    0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF1_PCIE_RTR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF1_RTR_DATA1
+#define BIF_CFG_DEV0_EPF0_VF1_RTR_DATA1__RESET_TIME__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF0_VF1_RTR_DATA1__DLUP_TIME__SHIFT                                                     0xc
+#define BIF_CFG_DEV0_EPF0_VF1_RTR_DATA1__RTR_VALID__SHIFT                                                     0x1f
+#define BIF_CFG_DEV0_EPF0_VF1_RTR_DATA1__RESET_TIME_MASK                                                      0x00000FFFL
+#define BIF_CFG_DEV0_EPF0_VF1_RTR_DATA1__DLUP_TIME_MASK                                                       0x00FFF000L
+#define BIF_CFG_DEV0_EPF0_VF1_RTR_DATA1__RTR_VALID_MASK                                                       0x80000000L
+//BIF_CFG_DEV0_EPF0_VF1_RTR_DATA2
+#define BIF_CFG_DEV0_EPF0_VF1_RTR_DATA2__FLR_TIME__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF0_VF1_RTR_DATA2__D3HOTD0_TIME__SHIFT                                                  0xc
+#define BIF_CFG_DEV0_EPF0_VF1_RTR_DATA2__FLR_TIME_MASK                                                        0x00000FFFL
+#define BIF_CFG_DEV0_EPF0_VF1_RTR_DATA2__D3HOTD0_TIME_MASK                                                    0x00FFF000L
+//BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                    0x1
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                          0x8
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                     0x0001L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                      0x0002L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                            0xFF00L
+//BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                    0x1
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                        0x4
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                     0x0001L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                      0x0002L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                          0x0070L
+//BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT                                       0x5
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT                                0x6
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED__SHIFT                                 0x7
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP__TEE_EXCLUSIVE_ATTR_SUPPORTED__SHIFT                               0x9
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK                                           0x001FL
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK                                         0x0020L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK                                  0x0040L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED_MASK                                   0x0080L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CAP__TEE_EXCLUSIVE_ATTR_SUPPORTED_MASK                                 0x0200L
+//BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CNTL__STU__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CNTL__TEE_EXCLUSIVE_ATTR_ENABLE__SHIFT                                 0xa
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT                                                0xf
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CNTL__STU_MASK                                                         0x001FL
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CNTL__TEE_EXCLUSIVE_ATTR_ENABLE_MASK                                   0x0400L
+#define BIF_CFG_DEV0_EPF0_VF1_PCIE_ATS_CNTL__ATC_ENABLE_MASK                                                  0x8000L
+
+
+// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_vf2_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF2_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF2_VENDOR_ID__VENDOR_ID__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_VF2_VENDOR_ID__VENDOR_ID_MASK                                                       0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_ID__DEVICE_ID__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_ID__DEVICE_ID_MASK                                                       0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__IO_ACCESS_EN__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__MEM_ACCESS_EN__SHIFT                                                   0x1
+#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__BUS_MASTER_EN__SHIFT                                                   0x2
+#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                0x3
+#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                         0x4
+#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__PAL_SNOOP_EN__SHIFT                                                    0x5
+#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                           0x6
+#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__AD_STEPPING__SHIFT                                                     0x7
+#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__SERR_EN__SHIFT                                                         0x8
+#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__FAST_B2B_EN__SHIFT                                                     0x9
+#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__INT_DIS__SHIFT                                                         0xa
+#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__IO_ACCESS_EN_MASK                                                      0x0001L
+#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__MEM_ACCESS_EN_MASK                                                     0x0002L
+#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__BUS_MASTER_EN_MASK                                                     0x0004L
+#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__SPECIAL_CYCLE_EN_MASK                                                  0x0008L
+#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                           0x0010L
+#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__PAL_SNOOP_EN_MASK                                                      0x0020L
+#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__PARITY_ERROR_RESPONSE_MASK                                             0x0040L
+#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__AD_STEPPING_MASK                                                       0x0080L
+#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__SERR_EN_MASK                                                           0x0100L
+#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__FAST_B2B_EN_MASK                                                       0x0200L
+#define BIF_CFG_DEV0_EPF0_VF2_COMMAND__INT_DIS_MASK                                                           0x0400L
+//BIF_CFG_DEV0_EPF0_VF2_STATUS
+#define BIF_CFG_DEV0_EPF0_VF2_STATUS__IMMEDIATE_READINESS__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF0_VF2_STATUS__INT_STATUS__SHIFT                                                       0x3
+#define BIF_CFG_DEV0_EPF0_VF2_STATUS__CAP_LIST__SHIFT                                                         0x4
+#define BIF_CFG_DEV0_EPF0_VF2_STATUS__PCI_66_CAP__SHIFT                                                       0x5
+#define BIF_CFG_DEV0_EPF0_VF2_STATUS__FAST_BACK_CAPABLE__SHIFT                                                0x7
+#define BIF_CFG_DEV0_EPF0_VF2_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                         0x8
+#define BIF_CFG_DEV0_EPF0_VF2_STATUS__DEVSEL_TIMING__SHIFT                                                    0x9
+#define BIF_CFG_DEV0_EPF0_VF2_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                              0xb
+#define BIF_CFG_DEV0_EPF0_VF2_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                            0xc
+#define BIF_CFG_DEV0_EPF0_VF2_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                            0xd
+#define BIF_CFG_DEV0_EPF0_VF2_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                            0xe
+#define BIF_CFG_DEV0_EPF0_VF2_STATUS__PARITY_ERROR_DETECTED__SHIFT                                            0xf
+#define BIF_CFG_DEV0_EPF0_VF2_STATUS__IMMEDIATE_READINESS_MASK                                                0x0001L
+#define BIF_CFG_DEV0_EPF0_VF2_STATUS__INT_STATUS_MASK                                                         0x0008L
+#define BIF_CFG_DEV0_EPF0_VF2_STATUS__CAP_LIST_MASK                                                           0x0010L
+#define BIF_CFG_DEV0_EPF0_VF2_STATUS__PCI_66_CAP_MASK                                                         0x0020L
+#define BIF_CFG_DEV0_EPF0_VF2_STATUS__FAST_BACK_CAPABLE_MASK                                                  0x0080L
+#define BIF_CFG_DEV0_EPF0_VF2_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                           0x0100L
+#define BIF_CFG_DEV0_EPF0_VF2_STATUS__DEVSEL_TIMING_MASK                                                      0x0600L
+#define BIF_CFG_DEV0_EPF0_VF2_STATUS__SIGNAL_TARGET_ABORT_MASK                                                0x0800L
+#define BIF_CFG_DEV0_EPF0_VF2_STATUS__RECEIVED_TARGET_ABORT_MASK                                              0x1000L
+#define BIF_CFG_DEV0_EPF0_VF2_STATUS__RECEIVED_MASTER_ABORT_MASK                                              0x2000L
+#define BIF_CFG_DEV0_EPF0_VF2_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                              0x4000L
+#define BIF_CFG_DEV0_EPF0_VF2_STATUS__PARITY_ERROR_DETECTED_MASK                                              0x8000L
+//BIF_CFG_DEV0_EPF0_VF2_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF2_REVISION_ID__MINOR_REV_ID__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF0_VF2_REVISION_ID__MAJOR_REV_ID__SHIFT                                                0x4
+#define BIF_CFG_DEV0_EPF0_VF2_REVISION_ID__MINOR_REV_ID_MASK                                                  0x0FL
+#define BIF_CFG_DEV0_EPF0_VF2_REVISION_ID__MAJOR_REV_ID_MASK                                                  0xF0L
+//BIF_CFG_DEV0_EPF0_VF2_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF2_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_VF2_PROG_INTERFACE__PROG_INTERFACE_MASK                                             0xFFL
+//BIF_CFG_DEV0_EPF0_VF2_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF2_SUB_CLASS__SUB_CLASS__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_VF2_SUB_CLASS__SUB_CLASS_MASK                                                       0xFFL
+//BIF_CFG_DEV0_EPF0_VF2_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF2_BASE_CLASS__BASE_CLASS__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF2_BASE_CLASS__BASE_CLASS_MASK                                                     0xFFL
+//BIF_CFG_DEV0_EPF0_VF2_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF2_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF0_VF2_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                0xFFL
+//BIF_CFG_DEV0_EPF0_VF2_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF2_LATENCY__LATENCY_TIMER__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF2_LATENCY__LATENCY_TIMER_MASK                                                     0xFFL
+//BIF_CFG_DEV0_EPF0_VF2_HEADER
+#define BIF_CFG_DEV0_EPF0_VF2_HEADER__HEADER_TYPE__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF0_VF2_HEADER__DEVICE_TYPE__SHIFT                                                      0x7
+#define BIF_CFG_DEV0_EPF0_VF2_HEADER__HEADER_TYPE_MASK                                                        0x7FL
+#define BIF_CFG_DEV0_EPF0_VF2_HEADER__DEVICE_TYPE_MASK                                                        0x80L
+//BIF_CFG_DEV0_EPF0_VF2_BIST
+#define BIF_CFG_DEV0_EPF0_VF2_BIST__BIST_COMP__SHIFT                                                          0x0
+#define BIF_CFG_DEV0_EPF0_VF2_BIST__BIST_STRT__SHIFT                                                          0x6
+#define BIF_CFG_DEV0_EPF0_VF2_BIST__BIST_CAP__SHIFT                                                           0x7
+#define BIF_CFG_DEV0_EPF0_VF2_BIST__BIST_COMP_MASK                                                            0x0FL
+#define BIF_CFG_DEV0_EPF0_VF2_BIST__BIST_STRT_MASK                                                            0x40L
+#define BIF_CFG_DEV0_EPF0_VF2_BIST__BIST_CAP_MASK                                                             0x80L
+//BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_1__BASE_ADDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_1__BASE_ADDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_2__BASE_ADDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_2__BASE_ADDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_3__BASE_ADDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_3__BASE_ADDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_4__BASE_ADDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_4__BASE_ADDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_5__BASE_ADDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_5__BASE_ADDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_6__BASE_ADDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF2_BASE_ADDR_6__BASE_ADDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF2_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_VF2_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK                                           0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                                 0x10
+#define BIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                            0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF2_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                   0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR__ROM_ENABLE__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT                                     0x1
+#define BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT                                    0x4
+#define BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                 0xb
+#define BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR__ROM_ENABLE_MASK                                                  0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK                                       0x0000000EL
+#define BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK                                      0x000000F0L
+#define BIF_CFG_DEV0_EPF0_VF2_ROM_BASE_ADDR__BASE_ADDR_MASK                                                   0xFFFFF800L
+//BIF_CFG_DEV0_EPF0_VF2_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF2_CAP_PTR__CAP_PTR__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF0_VF2_CAP_PTR__CAP_PTR_MASK                                                           0xFFL
+//BIF_CFG_DEV0_EPF0_VF2_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF2_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_VF2_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                             0xFFL
+//BIF_CFG_DEV0_EPF0_VF2_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF2_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF0_VF2_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                               0xFFL
+//BIF_CFG_DEV0_EPF0_VF2_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF2_MIN_GRANT__MIN_GNT__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF0_VF2_MIN_GRANT__MIN_GNT_MASK                                                         0xFFL
+//BIF_CFG_DEV0_EPF0_VF2_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF2_MAX_LATENCY__MAX_LAT__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_VF2_MAX_LATENCY__MAX_LAT_MASK                                                       0xFFL
+//BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST__CAP_ID__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                  0x8
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST__CAP_ID_MASK                                                      0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP_LIST__NEXT_PTR_MASK                                                    0xFF00L
+//BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__VERSION__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__DEVICE_TYPE__SHIFT                                                    0x4
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                               0x8
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                0x9
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__FLIT_MODE_SUPPORT__SHIFT                                              0xf
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__VERSION_MASK                                                          0x000FL
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__DEVICE_TYPE_MASK                                                      0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                  0x3E00L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CAP__FLIT_MODE_SUPPORT_MASK                                                0x8000L
+//BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                 0x3
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                 0x5
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                       0x6
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                        0x9
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                     0xf
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__RX_MPS_FIXED__SHIFT                                                 0x11
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                    0x12
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                    0x1a
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                  0x1c
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__MIXED_MPS_SUPPORTED__SHIFT                                          0x1d
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__TEE_IO_SUPPORT__SHIFT                                               0x1e
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                            0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__PHANTOM_FUNC_MASK                                                   0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__EXTENDED_TAG_MASK                                                   0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                         0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                          0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                       0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK                                       0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__RX_MPS_FIXED_MASK                                                   0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                      0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                      0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__FLR_CAPABLE_MASK                                                    0x10000000L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__MIXED_MPS_SUPPORTED_MASK                                            0x20000000L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP__TEE_IO_SUPPORT_MASK                                                 0x40000000L
+//BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                            0x1
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                0x2
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                               0x3
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                              0x4
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                            0x5
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                             0x8
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                             0x9
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                             0xa
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                 0xb
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                       0xc
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__INITIATE_FLR__SHIFT                                                0xf
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__CORR_ERR_EN_MASK                                                   0x0001L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                              0x0002L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                  0x0004L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__USR_REPORT_EN_MASK                                                 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                0x0010L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                              0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                               0x0100L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                               0x0200L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                               0x0400L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                   0x0800L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                         0x7000L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL__INITIATE_FLR_MASK                                                  0x8000L
+//BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__CORR_ERR__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                             0x1
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__FATAL_ERR__SHIFT                                                 0x2
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__USR_DETECTED__SHIFT                                              0x3
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__AUX_PWR__SHIFT                                                   0x4
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                         0x5
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                             0x6
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__CORR_ERR_MASK                                                    0x0001L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__NON_FATAL_ERR_MASK                                               0x0002L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__FATAL_ERR_MASK                                                   0x0004L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__USR_DETECTED_MASK                                                0x0008L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__AUX_PWR_MASK                                                     0x0010L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                           0x0020L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                               0x0040L
+//BIF_CFG_DEV0_EPF0_VF2_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__LINK_SPEED__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__LINK_WIDTH__SHIFT                                                     0x4
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__PM_SUPPORT__SHIFT                                                     0xa
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                               0xc
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                0xf
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                         0x12
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                    0x13
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                    0x14
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                       0x15
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                    0x16
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__PORT_NUMBER__SHIFT                                                    0x18
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__LINK_SPEED_MASK                                                       0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__LINK_WIDTH_MASK                                                       0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__PM_SUPPORT_MASK                                                       0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__L1_EXIT_LATENCY_MASK                                                  0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                           0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                      0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                      0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                         0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                      0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP__PORT_NUMBER_MASK                                                      0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__PM_CONTROL__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT                                  0x2
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                             0x3
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__LINK_DIS__SHIFT                                                      0x4
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__RETRAIN_LINK__SHIFT                                                  0x5
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                              0x6
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                 0x7
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                   0x9
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                     0xa
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                     0xb
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__SRIS_CLOCKING__SHIFT                                                 0xc
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__FLIT_MODE_DISABLE__SHIFT                                             0xd
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                         0xe
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__PM_CONTROL_MASK                                                      0x0003L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK                                    0x0004L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                               0x0008L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__LINK_DIS_MASK                                                        0x0010L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__RETRAIN_LINK_MASK                                                    0x0020L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                0x0040L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__EXTENDED_SYNC_MASK                                                   0x0080L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                       0x0100L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                     0x0200L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                       0x0400L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                       0x0800L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__SRIS_CLOCKING_MASK                                                   0x1000L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__FLIT_MODE_DISABLE_MASK                                               0x2000L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                           0xC000L
+//BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                       0x4
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__LINK_TRAINING__SHIFT                                               0xb
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                              0xc
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__DL_ACTIVE__SHIFT                                                   0xd
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                   0xe
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                   0xf
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                            0x000FL
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                         0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__LINK_TRAINING_MASK                                                 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                0x1000L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__DL_ACTIVE_MASK                                                     0x2000L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                     0x4000L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                     0x8000L
+//BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                   0x4
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                    0x5
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                  0x6
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                  0x7
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                  0x8
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                      0x9
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                   0xa
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                               0xb
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                          0xc
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                               0xe
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                             0x10
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                             0x11
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                              0x12
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                0x14
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                0x15
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                    0x16
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                              0x18
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                               0x1a
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                               0x1f
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                   0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                     0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                      0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                    0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                    0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                    0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                        0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                     0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                            0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                               0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                               0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                  0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                  0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                      0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                            0x4
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                          0x5
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                        0x6
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                   0x7
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                         0x8
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                      0x9
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__LTR_EN__SHIFT                                                     0xa
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                               0xb
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                               0xc
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__OBFF_EN__SHIFT                                                    0xd
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                0xf
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                            0x000FL
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                              0x0010L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                            0x0020L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                          0x0040L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                     0x0080L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                           0x0100L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                        0x0200L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__LTR_EN_MASK                                                       0x0400L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__OBFF_EN_MASK                                                      0x6000L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                  0x8000L
+//BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS2__RESERVED__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS2__RESERVED_MASK                                                   0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                          0x1
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                           0x8
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT                                      0x9
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                      0x10
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                     0x17
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                     0x18
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                 0x1f
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                            0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                             0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK                                        0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                        0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                       0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                       0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CAP2__DRS_SUPPORTED_MASK                                                   0x80000000L
+//BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                             0x4
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                  0x5
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                        0x6
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                  0x7
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                         0xa
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                               0xb
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                        0xc
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                              0x000FL
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                               0x0010L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                    0x0020L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                          0x0040L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__XMIT_MARGIN_MASK                                                    0x0380L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                           0x0400L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                          0xF000L
+//BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                  0x1
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                            0x2
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                            0x3
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                            0x4
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                              0x5
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                          0x6
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                          0x7
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                       0x8
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__FLIT_MODE_STATUS__SHIFT                                           0xa
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                              0xc
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                       0xf
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                         0x0001L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                    0x0002L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                              0x0004L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                              0x0008L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                              0x0010L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                0x0020L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                            0x0040L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                            0x0080L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                         0x0300L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__FLIT_MODE_STATUS_MASK                                             0x0400L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                0x7000L
+#define BIF_CFG_DEV0_EPF0_VF2_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                         0x8000L
+//BIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST__CAP_ID__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST__CAP_ID_MASK                                                       0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_CAP_LIST__NEXT_PTR_MASK                                                     0xFF00L
+//BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_EN__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                              0x1
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                               0x4
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                  0x7
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                  0x8
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT                                       0x9
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT                                        0xa
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_EN_MASK                                                       0x0001L
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                0x000EL
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_64BIT_MASK                                                    0x0080L
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                    0x0100L
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK                                         0x0200L
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK                                          0x0400L
+//BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                         0x2
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                           0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                           0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA__MSI_DATA__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA__MSI_DATA_MASK                                                     0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK                                             0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_MASK__MSI_MASK__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_MASK__MSI_MASK_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                               0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK                                       0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_MASK_64__MSI_MASK_64__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_MASK_64__MSI_MASK_64_MASK                                                   0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_PENDING__MSI_PENDING__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_PENDING__MSI_PENDING_MASK                                                   0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_VF2_MSI_PENDING_64__MSI_PENDING_64_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST__CAP_ID__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                  0x8
+#define BIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST__CAP_ID_MASK                                                      0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF2_MSIX_CAP_LIST__NEXT_PTR_MASK                                                    0xFF00L
+//BIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                            0xe
+#define BIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                   0xf
+#define BIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                             0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                              0x4000L
+#define BIF_CFG_DEV0_EPF0_VF2_MSIX_MSG_CNTL__MSIX_EN_MASK                                                     0x8000L
+//BIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                            0x3
+#define BIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                                 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF2_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                              0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF2_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF2_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF2_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                                0x3
+#define BIF_CFG_DEV0_EPF0_VF2_MSIX_PBA__MSIX_PBA_BIR_MASK                                                     0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF2_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                  0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                0x0
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                               0x10
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                              0x14
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                  0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                       0x10
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                    0x14
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                         0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                      0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_PCIE_DEVICE3_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_DEVICE3_ENH_CAP_LIST__CAP_ID__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_DEVICE3_ENH_CAP_LIST__CAP_VER__SHIFT                                       0x10
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_DEVICE3_ENH_CAP_LIST__NEXT_PTR__SHIFT                                      0x14
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_DEVICE3_ENH_CAP_LIST__CAP_ID_MASK                                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_DEVICE3_ENH_CAP_LIST__CAP_VER_MASK                                         0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_DEVICE3_ENH_CAP_LIST__NEXT_PTR_MASK                                        0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP3
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP3__DMWR_REQUEST_ROUTING_SUPPORTED__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_COMPLETER_SUPPORTED__SHIFT                   0x1
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_REQUESTER_SUPPORTED__SHIFT                   0x2
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP3__RECEIVER_L0P_SUPPORTED__SHIFT                                      0x3
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP3__PORT_L0P_EXIT_LATENCY__SHIFT                                       0x4
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP3__RETIMER_L0P_EXIT_LATENCY__SHIFT                                    0x7
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP3__DMWR_REQUEST_ROUTING_SUPPORTED_MASK                                0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_COMPLETER_SUPPORTED_MASK                     0x00000002L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_REQUESTER_SUPPORTED_MASK                     0x00000004L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP3__RECEIVER_L0P_SUPPORTED_MASK                                        0x00000008L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP3__PORT_L0P_EXIT_LATENCY_MASK                                         0x00000070L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CAP3__RETIMER_L0P_EXIT_LATENCY_MASK                                      0x00000380L
+//BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL3
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL3__DMWR_REQUEST_ENABLE__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL3__DMWR_EGRESS_BLOCKING__SHIFT                                       0x1
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL3__DEVICE_CNTL3_14BIT_TAG_REQUESTER_ENABLE__SHIFT                    0x2
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL3__L0P_ENABLE__SHIFT                                                 0x3
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL3__TARGET_LINK_WIDTH__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL3__DMWR_REQUEST_ENABLE_MASK                                          0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL3__DMWR_EGRESS_BLOCKING_MASK                                         0x00000002L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL3__DEVICE_CNTL3_14BIT_TAG_REQUESTER_ENABLE_MASK                      0x00000004L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL3__L0P_ENABLE_MASK                                                   0x00000008L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_CNTL3__TARGET_LINK_WIDTH_MASK                                            0x00000070L
+//BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS3
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS3__INITIAL_LINK_WIDTH__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS3__SEGMENT_CAPTURED__SHIFT                                         0x3
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS3__REMOTE_L0P_SUPPORTED__SHIFT                                     0x4
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS3__INITIAL_LINK_WIDTH_MASK                                         0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS3__SEGMENT_CAPTURED_MASK                                           0x00000008L
+#define BIF_CFG_DEV0_EPF0_VF2_DEVICE_STATUS3__REMOTE_L0P_SUPPORTED_MASK                                       0x00000010L
+//BIF_CFG_DEV0_EPF0_VF2_PCIE_NULL1_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_NULL1_ENH_CAP_LIST__CAP_ID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_NULL1_ENH_CAP_LIST__CAP_VER__SHIFT                                         0x10
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_NULL1_ENH_CAP_LIST__NEXT_PTR__SHIFT                                        0x14
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_NULL1_ENH_CAP_LIST__CAP_ID_MASK                                            0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_NULL1_ENH_CAP_LIST__CAP_VER_MASK                                           0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_NULL1_ENH_CAP_LIST__NEXT_PTR_MASK                                          0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF2_PCIE_NULL2_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_NULL2_ENH_CAP_LIST__CAP_ID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_NULL2_ENH_CAP_LIST__CAP_VER__SHIFT                                         0x10
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_NULL2_ENH_CAP_LIST__NEXT_PTR__SHIFT                                        0x14
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_NULL2_ENH_CAP_LIST__CAP_ID_MASK                                            0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_NULL2_ENH_CAP_LIST__CAP_VER_MASK                                           0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_NULL2_ENH_CAP_LIST__NEXT_PTR_MASK                                          0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                  0x14
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                      0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                     0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                    0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                   0x4
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                0x5
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                   0xc
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                    0xd
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                               0xe
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                             0xf
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                 0x10
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                  0x11
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                   0x12
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                  0x13
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                            0x14
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                             0x15
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                            0x16
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                            0x17
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                   0x18
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                    0x19
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT               0x1a
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__DMWR_REQUEST_EGRESS_BLOCKED_STATUS__SHIFT               0x1b
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__IDE_CHECK_FAILED_STATUS__SHIFT                          0x1c
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__MISROUTED_IDE_TLP_STATUS__SHIFT                         0x1d
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__PCRC_CHECK_FAILED_STATUS__SHIFT                         0x1e
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                     0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                  0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                     0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                      0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                               0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                   0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                    0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                     0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                    0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                              0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                               0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                              0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                              0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                     0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                      0x02000000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__DMWR_REQUEST_EGRESS_BLOCKED_STATUS_MASK                 0x08000000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__IDE_CHECK_FAILED_STATUS_MASK                            0x10000000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__MISROUTED_IDE_TLP_STATUS_MASK                           0x20000000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_STATUS__PCRC_CHECK_FAILED_STATUS_MASK                           0x40000000L
+//BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                       0x4
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                    0x5
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                       0xc
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                        0xd
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                   0xe
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                 0xf
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                      0x11
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                       0x12
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                      0x13
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                0x14
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                 0x15
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                0x16
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                0x17
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                       0x18
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                        0x19
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                   0x1a
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__DMWR_REQUEST_EGRESS_BLOCKED_MASK__SHIFT                   0x1b
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__IDE_CHECK_FAILED_MASK__SHIFT                              0x1c
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__MISROUTED_IDE_TLP_MASK__SHIFT                             0x1d
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__PCRC_CHECK_FAILED_MASK__SHIFT                             0x1e
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                         0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                      0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                         0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                          0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                     0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                   0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                       0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                        0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                         0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                        0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                  0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                   0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                  0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                  0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                         0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                          0x02000000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                     0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__DMWR_REQUEST_EGRESS_BLOCKED_MASK_MASK                     0x08000000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__IDE_CHECK_FAILED_MASK_MASK                                0x10000000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__MISROUTED_IDE_TLP_MASK_MASK                               0x20000000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_MASK__PCRC_CHECK_FAILED_MASK_MASK                               0x40000000L
+//BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                               0x4
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                            0x5
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                               0xc
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                0xd
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                           0xe
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                         0xf
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                             0x10
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                              0x11
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                               0x12
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                              0x13
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                        0x14
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                         0x15
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                        0x16
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                        0x17
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT               0x18
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                0x19
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT           0x1a
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__DMWR_REQUEST_EGRESS_BLOCKED_SEVERITY__SHIFT           0x1b
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__IDE_CHECK_FAILED_SEVERITY__SHIFT                      0x1c
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__MISROUTED_IDE_TLP_SEVERITY__SHIFT                     0x1d
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__PCRC_CHECK_FAILED_SEVERITY__SHIFT                     0x1e
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                              0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                  0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                             0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                           0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                               0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                          0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                           0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                          0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                          0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                  0x02000000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK             0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__DMWR_REQUEST_EGRESS_BLOCKED_SEVERITY_MASK             0x08000000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__IDE_CHECK_FAILED_SEVERITY_MASK                        0x10000000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__MISROUTED_IDE_TLP_SEVERITY_MASK                       0x20000000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_UNCORR_ERR_SEVERITY__PCRC_CHECK_FAILED_SEVERITY_MASK                       0x40000000L
+//BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                     0x6
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                    0x7
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                         0x8
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                        0xc
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                       0xd
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                0xe
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                                0xf
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                       0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                       0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                      0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                           0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                          0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                         0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                  0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                  0x00008000L
+//BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                         0x6
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                        0x7
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                             0x8
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                            0xc
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                           0xd
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                    0xe
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                    0xf
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                           0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                           0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                          0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                               0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                              0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                             0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                      0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                      0x00008000L
+//BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT                                      0x5
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT                                       0x6
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                    0x7
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                0x9
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                 0xa
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                            0xb
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT                    0xc
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__HEADER_LOG_SIZE__SHIFT                                   0xd
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_WAS_FLIT_MODE__SHIFT                          0x12
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_SIZE__SHIFT                                   0x13
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                       0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK                                        0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK                                         0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                      0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                       0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                  0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                   0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                              0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK                      0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__HEADER_LOG_SIZE_MASK                                     0x0003E000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_WAS_FLIT_MODE_MASK                            0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_SIZE_MASK                                     0x00F80000L
+//BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG0__TLP_HDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG1__TLP_HDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG2__TLP_HDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG3__TLP_HDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG4
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG4__TLP_HDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG4__TLP_HDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                           0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG5
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG5__TLP_HDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG5__TLP_HDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                           0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG6
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG6__TLP_HDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG6__TLP_HDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                           0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG7
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG7__TLP_HDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG7__TLP_HDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                           0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG8
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG8__TLP_HDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG8__TLP_HDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG9
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG9__TLP_HDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG9__TLP_HDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG10
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG10__TLP_HDR__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG10__TLP_HDR_MASK                                                    0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG11
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG11__TLP_HDR__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG11__TLP_HDR_MASK                                                    0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG12
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG12__TLP_HDR__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG12__TLP_HDR_MASK                                                    0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG13
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG13__TLP_HDR__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_HDR_LOG13__TLP_HDR_MASK                                                    0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF2_PCIE_RTR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF2_RTR_DATA1
+#define BIF_CFG_DEV0_EPF0_VF2_RTR_DATA1__RESET_TIME__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF0_VF2_RTR_DATA1__DLUP_TIME__SHIFT                                                     0xc
+#define BIF_CFG_DEV0_EPF0_VF2_RTR_DATA1__RTR_VALID__SHIFT                                                     0x1f
+#define BIF_CFG_DEV0_EPF0_VF2_RTR_DATA1__RESET_TIME_MASK                                                      0x00000FFFL
+#define BIF_CFG_DEV0_EPF0_VF2_RTR_DATA1__DLUP_TIME_MASK                                                       0x00FFF000L
+#define BIF_CFG_DEV0_EPF0_VF2_RTR_DATA1__RTR_VALID_MASK                                                       0x80000000L
+//BIF_CFG_DEV0_EPF0_VF2_RTR_DATA2
+#define BIF_CFG_DEV0_EPF0_VF2_RTR_DATA2__FLR_TIME__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF0_VF2_RTR_DATA2__D3HOTD0_TIME__SHIFT                                                  0xc
+#define BIF_CFG_DEV0_EPF0_VF2_RTR_DATA2__FLR_TIME_MASK                                                        0x00000FFFL
+#define BIF_CFG_DEV0_EPF0_VF2_RTR_DATA2__D3HOTD0_TIME_MASK                                                    0x00FFF000L
+//BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                    0x1
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                          0x8
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                     0x0001L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                      0x0002L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                            0xFF00L
+//BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                    0x1
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                        0x4
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                     0x0001L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                      0x0002L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                          0x0070L
+//BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT                                       0x5
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT                                0x6
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED__SHIFT                                 0x7
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP__TEE_EXCLUSIVE_ATTR_SUPPORTED__SHIFT                               0x9
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK                                           0x001FL
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK                                         0x0020L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK                                  0x0040L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED_MASK                                   0x0080L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CAP__TEE_EXCLUSIVE_ATTR_SUPPORTED_MASK                                 0x0200L
+//BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CNTL__STU__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CNTL__TEE_EXCLUSIVE_ATTR_ENABLE__SHIFT                                 0xa
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT                                                0xf
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CNTL__STU_MASK                                                         0x001FL
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CNTL__TEE_EXCLUSIVE_ATTR_ENABLE_MASK                                   0x0400L
+#define BIF_CFG_DEV0_EPF0_VF2_PCIE_ATS_CNTL__ATC_ENABLE_MASK                                                  0x8000L
+
+
+// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_vf3_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF3_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF3_VENDOR_ID__VENDOR_ID__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_VF3_VENDOR_ID__VENDOR_ID_MASK                                                       0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_ID__DEVICE_ID__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_ID__DEVICE_ID_MASK                                                       0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__IO_ACCESS_EN__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__MEM_ACCESS_EN__SHIFT                                                   0x1
+#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__BUS_MASTER_EN__SHIFT                                                   0x2
+#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                0x3
+#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                         0x4
+#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__PAL_SNOOP_EN__SHIFT                                                    0x5
+#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                           0x6
+#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__AD_STEPPING__SHIFT                                                     0x7
+#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__SERR_EN__SHIFT                                                         0x8
+#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__FAST_B2B_EN__SHIFT                                                     0x9
+#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__INT_DIS__SHIFT                                                         0xa
+#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__IO_ACCESS_EN_MASK                                                      0x0001L
+#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__MEM_ACCESS_EN_MASK                                                     0x0002L
+#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__BUS_MASTER_EN_MASK                                                     0x0004L
+#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__SPECIAL_CYCLE_EN_MASK                                                  0x0008L
+#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                           0x0010L
+#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__PAL_SNOOP_EN_MASK                                                      0x0020L
+#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__PARITY_ERROR_RESPONSE_MASK                                             0x0040L
+#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__AD_STEPPING_MASK                                                       0x0080L
+#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__SERR_EN_MASK                                                           0x0100L
+#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__FAST_B2B_EN_MASK                                                       0x0200L
+#define BIF_CFG_DEV0_EPF0_VF3_COMMAND__INT_DIS_MASK                                                           0x0400L
+//BIF_CFG_DEV0_EPF0_VF3_STATUS
+#define BIF_CFG_DEV0_EPF0_VF3_STATUS__IMMEDIATE_READINESS__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF0_VF3_STATUS__INT_STATUS__SHIFT                                                       0x3
+#define BIF_CFG_DEV0_EPF0_VF3_STATUS__CAP_LIST__SHIFT                                                         0x4
+#define BIF_CFG_DEV0_EPF0_VF3_STATUS__PCI_66_CAP__SHIFT                                                       0x5
+#define BIF_CFG_DEV0_EPF0_VF3_STATUS__FAST_BACK_CAPABLE__SHIFT                                                0x7
+#define BIF_CFG_DEV0_EPF0_VF3_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                         0x8
+#define BIF_CFG_DEV0_EPF0_VF3_STATUS__DEVSEL_TIMING__SHIFT                                                    0x9
+#define BIF_CFG_DEV0_EPF0_VF3_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                              0xb
+#define BIF_CFG_DEV0_EPF0_VF3_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                            0xc
+#define BIF_CFG_DEV0_EPF0_VF3_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                            0xd
+#define BIF_CFG_DEV0_EPF0_VF3_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                            0xe
+#define BIF_CFG_DEV0_EPF0_VF3_STATUS__PARITY_ERROR_DETECTED__SHIFT                                            0xf
+#define BIF_CFG_DEV0_EPF0_VF3_STATUS__IMMEDIATE_READINESS_MASK                                                0x0001L
+#define BIF_CFG_DEV0_EPF0_VF3_STATUS__INT_STATUS_MASK                                                         0x0008L
+#define BIF_CFG_DEV0_EPF0_VF3_STATUS__CAP_LIST_MASK                                                           0x0010L
+#define BIF_CFG_DEV0_EPF0_VF3_STATUS__PCI_66_CAP_MASK                                                         0x0020L
+#define BIF_CFG_DEV0_EPF0_VF3_STATUS__FAST_BACK_CAPABLE_MASK                                                  0x0080L
+#define BIF_CFG_DEV0_EPF0_VF3_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                           0x0100L
+#define BIF_CFG_DEV0_EPF0_VF3_STATUS__DEVSEL_TIMING_MASK                                                      0x0600L
+#define BIF_CFG_DEV0_EPF0_VF3_STATUS__SIGNAL_TARGET_ABORT_MASK                                                0x0800L
+#define BIF_CFG_DEV0_EPF0_VF3_STATUS__RECEIVED_TARGET_ABORT_MASK                                              0x1000L
+#define BIF_CFG_DEV0_EPF0_VF3_STATUS__RECEIVED_MASTER_ABORT_MASK                                              0x2000L
+#define BIF_CFG_DEV0_EPF0_VF3_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                              0x4000L
+#define BIF_CFG_DEV0_EPF0_VF3_STATUS__PARITY_ERROR_DETECTED_MASK                                              0x8000L
+//BIF_CFG_DEV0_EPF0_VF3_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF3_REVISION_ID__MINOR_REV_ID__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF0_VF3_REVISION_ID__MAJOR_REV_ID__SHIFT                                                0x4
+#define BIF_CFG_DEV0_EPF0_VF3_REVISION_ID__MINOR_REV_ID_MASK                                                  0x0FL
+#define BIF_CFG_DEV0_EPF0_VF3_REVISION_ID__MAJOR_REV_ID_MASK                                                  0xF0L
+//BIF_CFG_DEV0_EPF0_VF3_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF3_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_VF3_PROG_INTERFACE__PROG_INTERFACE_MASK                                             0xFFL
+//BIF_CFG_DEV0_EPF0_VF3_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF3_SUB_CLASS__SUB_CLASS__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_VF3_SUB_CLASS__SUB_CLASS_MASK                                                       0xFFL
+//BIF_CFG_DEV0_EPF0_VF3_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF3_BASE_CLASS__BASE_CLASS__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF3_BASE_CLASS__BASE_CLASS_MASK                                                     0xFFL
+//BIF_CFG_DEV0_EPF0_VF3_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF3_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF0_VF3_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                0xFFL
+//BIF_CFG_DEV0_EPF0_VF3_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF3_LATENCY__LATENCY_TIMER__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF3_LATENCY__LATENCY_TIMER_MASK                                                     0xFFL
+//BIF_CFG_DEV0_EPF0_VF3_HEADER
+#define BIF_CFG_DEV0_EPF0_VF3_HEADER__HEADER_TYPE__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF0_VF3_HEADER__DEVICE_TYPE__SHIFT                                                      0x7
+#define BIF_CFG_DEV0_EPF0_VF3_HEADER__HEADER_TYPE_MASK                                                        0x7FL
+#define BIF_CFG_DEV0_EPF0_VF3_HEADER__DEVICE_TYPE_MASK                                                        0x80L
+//BIF_CFG_DEV0_EPF0_VF3_BIST
+#define BIF_CFG_DEV0_EPF0_VF3_BIST__BIST_COMP__SHIFT                                                          0x0
+#define BIF_CFG_DEV0_EPF0_VF3_BIST__BIST_STRT__SHIFT                                                          0x6
+#define BIF_CFG_DEV0_EPF0_VF3_BIST__BIST_CAP__SHIFT                                                           0x7
+#define BIF_CFG_DEV0_EPF0_VF3_BIST__BIST_COMP_MASK                                                            0x0FL
+#define BIF_CFG_DEV0_EPF0_VF3_BIST__BIST_STRT_MASK                                                            0x40L
+#define BIF_CFG_DEV0_EPF0_VF3_BIST__BIST_CAP_MASK                                                             0x80L
+//BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_1__BASE_ADDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_1__BASE_ADDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_2__BASE_ADDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_2__BASE_ADDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_3__BASE_ADDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_3__BASE_ADDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_4__BASE_ADDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_4__BASE_ADDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_5__BASE_ADDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_5__BASE_ADDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_6__BASE_ADDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF3_BASE_ADDR_6__BASE_ADDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF3_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_VF3_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK                                           0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                                 0x10
+#define BIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                            0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF3_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                   0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR__ROM_ENABLE__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT                                     0x1
+#define BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT                                    0x4
+#define BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                 0xb
+#define BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR__ROM_ENABLE_MASK                                                  0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK                                       0x0000000EL
+#define BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK                                      0x000000F0L
+#define BIF_CFG_DEV0_EPF0_VF3_ROM_BASE_ADDR__BASE_ADDR_MASK                                                   0xFFFFF800L
+//BIF_CFG_DEV0_EPF0_VF3_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF3_CAP_PTR__CAP_PTR__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF0_VF3_CAP_PTR__CAP_PTR_MASK                                                           0xFFL
+//BIF_CFG_DEV0_EPF0_VF3_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF3_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_VF3_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                             0xFFL
+//BIF_CFG_DEV0_EPF0_VF3_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF3_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF0_VF3_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                               0xFFL
+//BIF_CFG_DEV0_EPF0_VF3_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF3_MIN_GRANT__MIN_GNT__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF0_VF3_MIN_GRANT__MIN_GNT_MASK                                                         0xFFL
+//BIF_CFG_DEV0_EPF0_VF3_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF3_MAX_LATENCY__MAX_LAT__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_VF3_MAX_LATENCY__MAX_LAT_MASK                                                       0xFFL
+//BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST__CAP_ID__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                  0x8
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST__CAP_ID_MASK                                                      0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP_LIST__NEXT_PTR_MASK                                                    0xFF00L
+//BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__VERSION__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__DEVICE_TYPE__SHIFT                                                    0x4
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                               0x8
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                0x9
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__FLIT_MODE_SUPPORT__SHIFT                                              0xf
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__VERSION_MASK                                                          0x000FL
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__DEVICE_TYPE_MASK                                                      0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                  0x3E00L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CAP__FLIT_MODE_SUPPORT_MASK                                                0x8000L
+//BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                 0x3
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                 0x5
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                       0x6
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                        0x9
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                     0xf
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__RX_MPS_FIXED__SHIFT                                                 0x11
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                    0x12
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                    0x1a
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                  0x1c
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__MIXED_MPS_SUPPORTED__SHIFT                                          0x1d
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__TEE_IO_SUPPORT__SHIFT                                               0x1e
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                            0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__PHANTOM_FUNC_MASK                                                   0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__EXTENDED_TAG_MASK                                                   0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                         0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                          0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                       0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK                                       0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__RX_MPS_FIXED_MASK                                                   0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                      0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                      0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__FLR_CAPABLE_MASK                                                    0x10000000L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__MIXED_MPS_SUPPORTED_MASK                                            0x20000000L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP__TEE_IO_SUPPORT_MASK                                                 0x40000000L
+//BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                            0x1
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                0x2
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                               0x3
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                              0x4
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                            0x5
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                             0x8
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                             0x9
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                             0xa
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                 0xb
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                       0xc
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__INITIATE_FLR__SHIFT                                                0xf
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__CORR_ERR_EN_MASK                                                   0x0001L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                              0x0002L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                  0x0004L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__USR_REPORT_EN_MASK                                                 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                0x0010L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                              0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                               0x0100L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                               0x0200L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                               0x0400L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                   0x0800L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                         0x7000L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL__INITIATE_FLR_MASK                                                  0x8000L
+//BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__CORR_ERR__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                             0x1
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__FATAL_ERR__SHIFT                                                 0x2
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__USR_DETECTED__SHIFT                                              0x3
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__AUX_PWR__SHIFT                                                   0x4
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                         0x5
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                             0x6
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__CORR_ERR_MASK                                                    0x0001L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__NON_FATAL_ERR_MASK                                               0x0002L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__FATAL_ERR_MASK                                                   0x0004L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__USR_DETECTED_MASK                                                0x0008L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__AUX_PWR_MASK                                                     0x0010L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                           0x0020L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                               0x0040L
+//BIF_CFG_DEV0_EPF0_VF3_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__LINK_SPEED__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__LINK_WIDTH__SHIFT                                                     0x4
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__PM_SUPPORT__SHIFT                                                     0xa
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                               0xc
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                0xf
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                         0x12
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                    0x13
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                    0x14
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                       0x15
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                    0x16
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__PORT_NUMBER__SHIFT                                                    0x18
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__LINK_SPEED_MASK                                                       0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__LINK_WIDTH_MASK                                                       0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__PM_SUPPORT_MASK                                                       0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__L1_EXIT_LATENCY_MASK                                                  0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                           0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                      0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                      0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                         0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                      0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP__PORT_NUMBER_MASK                                                      0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__PM_CONTROL__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT                                  0x2
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                             0x3
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__LINK_DIS__SHIFT                                                      0x4
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__RETRAIN_LINK__SHIFT                                                  0x5
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                              0x6
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                 0x7
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                   0x9
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                     0xa
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                     0xb
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__SRIS_CLOCKING__SHIFT                                                 0xc
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__FLIT_MODE_DISABLE__SHIFT                                             0xd
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                         0xe
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__PM_CONTROL_MASK                                                      0x0003L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK                                    0x0004L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                               0x0008L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__LINK_DIS_MASK                                                        0x0010L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__RETRAIN_LINK_MASK                                                    0x0020L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                0x0040L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__EXTENDED_SYNC_MASK                                                   0x0080L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                       0x0100L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                     0x0200L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                       0x0400L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                       0x0800L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__SRIS_CLOCKING_MASK                                                   0x1000L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__FLIT_MODE_DISABLE_MASK                                               0x2000L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                           0xC000L
+//BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                       0x4
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__LINK_TRAINING__SHIFT                                               0xb
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                              0xc
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__DL_ACTIVE__SHIFT                                                   0xd
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                   0xe
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                   0xf
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                            0x000FL
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                         0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__LINK_TRAINING_MASK                                                 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                0x1000L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__DL_ACTIVE_MASK                                                     0x2000L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                     0x4000L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                     0x8000L
+//BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                   0x4
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                    0x5
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                  0x6
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                  0x7
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                  0x8
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                      0x9
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                   0xa
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                               0xb
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                          0xc
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                               0xe
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                             0x10
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                             0x11
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                              0x12
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                0x14
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                0x15
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                    0x16
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                              0x18
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                               0x1a
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                               0x1f
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                   0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                     0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                      0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                    0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                    0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                    0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                        0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                     0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                            0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                               0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                               0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                  0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                  0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                      0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                            0x4
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                          0x5
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                        0x6
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                   0x7
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                         0x8
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                      0x9
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__LTR_EN__SHIFT                                                     0xa
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                               0xb
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                               0xc
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__OBFF_EN__SHIFT                                                    0xd
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                0xf
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                            0x000FL
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                              0x0010L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                            0x0020L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                          0x0040L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                     0x0080L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                           0x0100L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                        0x0200L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__LTR_EN_MASK                                                       0x0400L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__OBFF_EN_MASK                                                      0x6000L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                  0x8000L
+//BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS2__RESERVED__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS2__RESERVED_MASK                                                   0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                          0x1
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                           0x8
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT                                      0x9
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                      0x10
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                     0x17
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                     0x18
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                 0x1f
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                            0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                             0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK                                        0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                        0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                       0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                       0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CAP2__DRS_SUPPORTED_MASK                                                   0x80000000L
+//BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                             0x4
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                  0x5
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                        0x6
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                  0x7
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                         0xa
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                               0xb
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                        0xc
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                              0x000FL
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                               0x0010L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                    0x0020L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                          0x0040L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__XMIT_MARGIN_MASK                                                    0x0380L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                           0x0400L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                          0xF000L
+//BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                  0x1
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                            0x2
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                            0x3
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                            0x4
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                              0x5
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                          0x6
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                          0x7
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                       0x8
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__FLIT_MODE_STATUS__SHIFT                                           0xa
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                              0xc
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                       0xf
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                         0x0001L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                    0x0002L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                              0x0004L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                              0x0008L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                              0x0010L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                0x0020L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                            0x0040L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                            0x0080L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                         0x0300L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__FLIT_MODE_STATUS_MASK                                             0x0400L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                0x7000L
+#define BIF_CFG_DEV0_EPF0_VF3_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                         0x8000L
+//BIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST__CAP_ID__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST__CAP_ID_MASK                                                       0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_CAP_LIST__NEXT_PTR_MASK                                                     0xFF00L
+//BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_EN__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                              0x1
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                               0x4
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                  0x7
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                  0x8
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT                                       0x9
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT                                        0xa
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_EN_MASK                                                       0x0001L
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                0x000EL
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_64BIT_MASK                                                    0x0080L
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                    0x0100L
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK                                         0x0200L
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK                                          0x0400L
+//BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                         0x2
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                           0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                           0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA__MSI_DATA__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA__MSI_DATA_MASK                                                     0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK                                             0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_MASK__MSI_MASK__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_MASK__MSI_MASK_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                               0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK                                       0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_MASK_64__MSI_MASK_64__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_MASK_64__MSI_MASK_64_MASK                                                   0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_PENDING__MSI_PENDING__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_PENDING__MSI_PENDING_MASK                                                   0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_VF3_MSI_PENDING_64__MSI_PENDING_64_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST__CAP_ID__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                  0x8
+#define BIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST__CAP_ID_MASK                                                      0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF3_MSIX_CAP_LIST__NEXT_PTR_MASK                                                    0xFF00L
+//BIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                            0xe
+#define BIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                   0xf
+#define BIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                             0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                              0x4000L
+#define BIF_CFG_DEV0_EPF0_VF3_MSIX_MSG_CNTL__MSIX_EN_MASK                                                     0x8000L
+//BIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                            0x3
+#define BIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                                 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF3_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                              0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF3_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF3_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF3_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                                0x3
+#define BIF_CFG_DEV0_EPF0_VF3_MSIX_PBA__MSIX_PBA_BIR_MASK                                                     0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF3_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                  0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                0x0
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                               0x10
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                              0x14
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                  0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                       0x10
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                    0x14
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                         0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                      0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_PCIE_DEVICE3_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_DEVICE3_ENH_CAP_LIST__CAP_ID__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_DEVICE3_ENH_CAP_LIST__CAP_VER__SHIFT                                       0x10
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_DEVICE3_ENH_CAP_LIST__NEXT_PTR__SHIFT                                      0x14
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_DEVICE3_ENH_CAP_LIST__CAP_ID_MASK                                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_DEVICE3_ENH_CAP_LIST__CAP_VER_MASK                                         0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_DEVICE3_ENH_CAP_LIST__NEXT_PTR_MASK                                        0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP3
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP3__DMWR_REQUEST_ROUTING_SUPPORTED__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_COMPLETER_SUPPORTED__SHIFT                   0x1
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_REQUESTER_SUPPORTED__SHIFT                   0x2
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP3__RECEIVER_L0P_SUPPORTED__SHIFT                                      0x3
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP3__PORT_L0P_EXIT_LATENCY__SHIFT                                       0x4
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP3__RETIMER_L0P_EXIT_LATENCY__SHIFT                                    0x7
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP3__DMWR_REQUEST_ROUTING_SUPPORTED_MASK                                0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_COMPLETER_SUPPORTED_MASK                     0x00000002L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_REQUESTER_SUPPORTED_MASK                     0x00000004L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP3__RECEIVER_L0P_SUPPORTED_MASK                                        0x00000008L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP3__PORT_L0P_EXIT_LATENCY_MASK                                         0x00000070L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CAP3__RETIMER_L0P_EXIT_LATENCY_MASK                                      0x00000380L
+//BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL3
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL3__DMWR_REQUEST_ENABLE__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL3__DMWR_EGRESS_BLOCKING__SHIFT                                       0x1
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL3__DEVICE_CNTL3_14BIT_TAG_REQUESTER_ENABLE__SHIFT                    0x2
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL3__L0P_ENABLE__SHIFT                                                 0x3
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL3__TARGET_LINK_WIDTH__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL3__DMWR_REQUEST_ENABLE_MASK                                          0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL3__DMWR_EGRESS_BLOCKING_MASK                                         0x00000002L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL3__DEVICE_CNTL3_14BIT_TAG_REQUESTER_ENABLE_MASK                      0x00000004L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL3__L0P_ENABLE_MASK                                                   0x00000008L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_CNTL3__TARGET_LINK_WIDTH_MASK                                            0x00000070L
+//BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS3
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS3__INITIAL_LINK_WIDTH__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS3__SEGMENT_CAPTURED__SHIFT                                         0x3
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS3__REMOTE_L0P_SUPPORTED__SHIFT                                     0x4
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS3__INITIAL_LINK_WIDTH_MASK                                         0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS3__SEGMENT_CAPTURED_MASK                                           0x00000008L
+#define BIF_CFG_DEV0_EPF0_VF3_DEVICE_STATUS3__REMOTE_L0P_SUPPORTED_MASK                                       0x00000010L
+//BIF_CFG_DEV0_EPF0_VF3_PCIE_NULL1_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_NULL1_ENH_CAP_LIST__CAP_ID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_NULL1_ENH_CAP_LIST__CAP_VER__SHIFT                                         0x10
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_NULL1_ENH_CAP_LIST__NEXT_PTR__SHIFT                                        0x14
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_NULL1_ENH_CAP_LIST__CAP_ID_MASK                                            0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_NULL1_ENH_CAP_LIST__CAP_VER_MASK                                           0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_NULL1_ENH_CAP_LIST__NEXT_PTR_MASK                                          0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF3_PCIE_NULL2_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_NULL2_ENH_CAP_LIST__CAP_ID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_NULL2_ENH_CAP_LIST__CAP_VER__SHIFT                                         0x10
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_NULL2_ENH_CAP_LIST__NEXT_PTR__SHIFT                                        0x14
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_NULL2_ENH_CAP_LIST__CAP_ID_MASK                                            0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_NULL2_ENH_CAP_LIST__CAP_VER_MASK                                           0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_NULL2_ENH_CAP_LIST__NEXT_PTR_MASK                                          0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                  0x14
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                      0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                     0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                    0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                   0x4
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                0x5
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                   0xc
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                    0xd
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                               0xe
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                             0xf
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                 0x10
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                  0x11
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                   0x12
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                  0x13
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                            0x14
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                             0x15
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                            0x16
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                            0x17
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                   0x18
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                    0x19
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT               0x1a
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__DMWR_REQUEST_EGRESS_BLOCKED_STATUS__SHIFT               0x1b
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__IDE_CHECK_FAILED_STATUS__SHIFT                          0x1c
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__MISROUTED_IDE_TLP_STATUS__SHIFT                         0x1d
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__PCRC_CHECK_FAILED_STATUS__SHIFT                         0x1e
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                     0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                  0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                     0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                      0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                               0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                   0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                    0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                     0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                    0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                              0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                               0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                              0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                              0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                     0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                      0x02000000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__DMWR_REQUEST_EGRESS_BLOCKED_STATUS_MASK                 0x08000000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__IDE_CHECK_FAILED_STATUS_MASK                            0x10000000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__MISROUTED_IDE_TLP_STATUS_MASK                           0x20000000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_STATUS__PCRC_CHECK_FAILED_STATUS_MASK                           0x40000000L
+//BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                       0x4
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                    0x5
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                       0xc
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                        0xd
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                   0xe
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                 0xf
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                      0x11
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                       0x12
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                      0x13
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                0x14
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                 0x15
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                0x16
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                0x17
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                       0x18
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                        0x19
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                   0x1a
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__DMWR_REQUEST_EGRESS_BLOCKED_MASK__SHIFT                   0x1b
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__IDE_CHECK_FAILED_MASK__SHIFT                              0x1c
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__MISROUTED_IDE_TLP_MASK__SHIFT                             0x1d
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__PCRC_CHECK_FAILED_MASK__SHIFT                             0x1e
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                         0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                      0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                         0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                          0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                     0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                   0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                       0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                        0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                         0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                        0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                  0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                   0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                  0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                  0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                         0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                          0x02000000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                     0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__DMWR_REQUEST_EGRESS_BLOCKED_MASK_MASK                     0x08000000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__IDE_CHECK_FAILED_MASK_MASK                                0x10000000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__MISROUTED_IDE_TLP_MASK_MASK                               0x20000000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_MASK__PCRC_CHECK_FAILED_MASK_MASK                               0x40000000L
+//BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                               0x4
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                            0x5
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                               0xc
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                0xd
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                           0xe
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                         0xf
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                             0x10
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                              0x11
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                               0x12
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                              0x13
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                        0x14
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                         0x15
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                        0x16
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                        0x17
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT               0x18
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                0x19
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT           0x1a
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__DMWR_REQUEST_EGRESS_BLOCKED_SEVERITY__SHIFT           0x1b
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__IDE_CHECK_FAILED_SEVERITY__SHIFT                      0x1c
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__MISROUTED_IDE_TLP_SEVERITY__SHIFT                     0x1d
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__PCRC_CHECK_FAILED_SEVERITY__SHIFT                     0x1e
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                              0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                  0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                             0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                           0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                               0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                          0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                           0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                          0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                          0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                  0x02000000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK             0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__DMWR_REQUEST_EGRESS_BLOCKED_SEVERITY_MASK             0x08000000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__IDE_CHECK_FAILED_SEVERITY_MASK                        0x10000000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__MISROUTED_IDE_TLP_SEVERITY_MASK                       0x20000000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_UNCORR_ERR_SEVERITY__PCRC_CHECK_FAILED_SEVERITY_MASK                       0x40000000L
+//BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                     0x6
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                    0x7
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                         0x8
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                        0xc
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                       0xd
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                0xe
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                                0xf
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                       0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                       0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                      0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                           0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                          0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                         0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                  0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                  0x00008000L
+//BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                         0x6
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                        0x7
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                             0x8
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                            0xc
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                           0xd
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                    0xe
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                    0xf
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                           0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                           0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                          0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                               0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                              0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                             0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                      0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                      0x00008000L
+//BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT                                      0x5
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT                                       0x6
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                    0x7
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                0x9
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                 0xa
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                            0xb
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT                    0xc
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__HEADER_LOG_SIZE__SHIFT                                   0xd
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_WAS_FLIT_MODE__SHIFT                          0x12
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_SIZE__SHIFT                                   0x13
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                       0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK                                        0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK                                         0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                      0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                       0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                  0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                   0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                              0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK                      0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__HEADER_LOG_SIZE_MASK                                     0x0003E000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_WAS_FLIT_MODE_MASK                            0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_SIZE_MASK                                     0x00F80000L
+//BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG0__TLP_HDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG1__TLP_HDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG2__TLP_HDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG3__TLP_HDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG4
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG4__TLP_HDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG4__TLP_HDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                           0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG5
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG5__TLP_HDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG5__TLP_HDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                           0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG6
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG6__TLP_HDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG6__TLP_HDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                           0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG7
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG7__TLP_HDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG7__TLP_HDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                           0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG8
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG8__TLP_HDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG8__TLP_HDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG9
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG9__TLP_HDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG9__TLP_HDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG10
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG10__TLP_HDR__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG10__TLP_HDR_MASK                                                    0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG11
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG11__TLP_HDR__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG11__TLP_HDR_MASK                                                    0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG12
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG12__TLP_HDR__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG12__TLP_HDR_MASK                                                    0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG13
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG13__TLP_HDR__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_HDR_LOG13__TLP_HDR_MASK                                                    0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF3_PCIE_RTR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF3_RTR_DATA1
+#define BIF_CFG_DEV0_EPF0_VF3_RTR_DATA1__RESET_TIME__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF0_VF3_RTR_DATA1__DLUP_TIME__SHIFT                                                     0xc
+#define BIF_CFG_DEV0_EPF0_VF3_RTR_DATA1__RTR_VALID__SHIFT                                                     0x1f
+#define BIF_CFG_DEV0_EPF0_VF3_RTR_DATA1__RESET_TIME_MASK                                                      0x00000FFFL
+#define BIF_CFG_DEV0_EPF0_VF3_RTR_DATA1__DLUP_TIME_MASK                                                       0x00FFF000L
+#define BIF_CFG_DEV0_EPF0_VF3_RTR_DATA1__RTR_VALID_MASK                                                       0x80000000L
+//BIF_CFG_DEV0_EPF0_VF3_RTR_DATA2
+#define BIF_CFG_DEV0_EPF0_VF3_RTR_DATA2__FLR_TIME__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF0_VF3_RTR_DATA2__D3HOTD0_TIME__SHIFT                                                  0xc
+#define BIF_CFG_DEV0_EPF0_VF3_RTR_DATA2__FLR_TIME_MASK                                                        0x00000FFFL
+#define BIF_CFG_DEV0_EPF0_VF3_RTR_DATA2__D3HOTD0_TIME_MASK                                                    0x00FFF000L
+//BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                    0x1
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                          0x8
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                     0x0001L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                      0x0002L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                            0xFF00L
+//BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                    0x1
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                        0x4
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                     0x0001L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                      0x0002L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                          0x0070L
+//BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT                                       0x5
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT                                0x6
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED__SHIFT                                 0x7
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP__TEE_EXCLUSIVE_ATTR_SUPPORTED__SHIFT                               0x9
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK                                           0x001FL
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK                                         0x0020L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK                                  0x0040L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED_MASK                                   0x0080L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CAP__TEE_EXCLUSIVE_ATTR_SUPPORTED_MASK                                 0x0200L
+//BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CNTL__STU__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CNTL__TEE_EXCLUSIVE_ATTR_ENABLE__SHIFT                                 0xa
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT                                                0xf
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CNTL__STU_MASK                                                         0x001FL
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CNTL__TEE_EXCLUSIVE_ATTR_ENABLE_MASK                                   0x0400L
+#define BIF_CFG_DEV0_EPF0_VF3_PCIE_ATS_CNTL__ATC_ENABLE_MASK                                                  0x8000L
+
+
+// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_vf4_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF4_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF4_VENDOR_ID__VENDOR_ID__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_VF4_VENDOR_ID__VENDOR_ID_MASK                                                       0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_ID__DEVICE_ID__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_ID__DEVICE_ID_MASK                                                       0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__IO_ACCESS_EN__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__MEM_ACCESS_EN__SHIFT                                                   0x1
+#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__BUS_MASTER_EN__SHIFT                                                   0x2
+#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                0x3
+#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                         0x4
+#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__PAL_SNOOP_EN__SHIFT                                                    0x5
+#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                           0x6
+#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__AD_STEPPING__SHIFT                                                     0x7
+#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__SERR_EN__SHIFT                                                         0x8
+#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__FAST_B2B_EN__SHIFT                                                     0x9
+#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__INT_DIS__SHIFT                                                         0xa
+#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__IO_ACCESS_EN_MASK                                                      0x0001L
+#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__MEM_ACCESS_EN_MASK                                                     0x0002L
+#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__BUS_MASTER_EN_MASK                                                     0x0004L
+#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__SPECIAL_CYCLE_EN_MASK                                                  0x0008L
+#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                           0x0010L
+#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__PAL_SNOOP_EN_MASK                                                      0x0020L
+#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__PARITY_ERROR_RESPONSE_MASK                                             0x0040L
+#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__AD_STEPPING_MASK                                                       0x0080L
+#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__SERR_EN_MASK                                                           0x0100L
+#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__FAST_B2B_EN_MASK                                                       0x0200L
+#define BIF_CFG_DEV0_EPF0_VF4_COMMAND__INT_DIS_MASK                                                           0x0400L
+//BIF_CFG_DEV0_EPF0_VF4_STATUS
+#define BIF_CFG_DEV0_EPF0_VF4_STATUS__IMMEDIATE_READINESS__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF0_VF4_STATUS__INT_STATUS__SHIFT                                                       0x3
+#define BIF_CFG_DEV0_EPF0_VF4_STATUS__CAP_LIST__SHIFT                                                         0x4
+#define BIF_CFG_DEV0_EPF0_VF4_STATUS__PCI_66_CAP__SHIFT                                                       0x5
+#define BIF_CFG_DEV0_EPF0_VF4_STATUS__FAST_BACK_CAPABLE__SHIFT                                                0x7
+#define BIF_CFG_DEV0_EPF0_VF4_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                         0x8
+#define BIF_CFG_DEV0_EPF0_VF4_STATUS__DEVSEL_TIMING__SHIFT                                                    0x9
+#define BIF_CFG_DEV0_EPF0_VF4_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                              0xb
+#define BIF_CFG_DEV0_EPF0_VF4_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                            0xc
+#define BIF_CFG_DEV0_EPF0_VF4_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                            0xd
+#define BIF_CFG_DEV0_EPF0_VF4_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                            0xe
+#define BIF_CFG_DEV0_EPF0_VF4_STATUS__PARITY_ERROR_DETECTED__SHIFT                                            0xf
+#define BIF_CFG_DEV0_EPF0_VF4_STATUS__IMMEDIATE_READINESS_MASK                                                0x0001L
+#define BIF_CFG_DEV0_EPF0_VF4_STATUS__INT_STATUS_MASK                                                         0x0008L
+#define BIF_CFG_DEV0_EPF0_VF4_STATUS__CAP_LIST_MASK                                                           0x0010L
+#define BIF_CFG_DEV0_EPF0_VF4_STATUS__PCI_66_CAP_MASK                                                         0x0020L
+#define BIF_CFG_DEV0_EPF0_VF4_STATUS__FAST_BACK_CAPABLE_MASK                                                  0x0080L
+#define BIF_CFG_DEV0_EPF0_VF4_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                           0x0100L
+#define BIF_CFG_DEV0_EPF0_VF4_STATUS__DEVSEL_TIMING_MASK                                                      0x0600L
+#define BIF_CFG_DEV0_EPF0_VF4_STATUS__SIGNAL_TARGET_ABORT_MASK                                                0x0800L
+#define BIF_CFG_DEV0_EPF0_VF4_STATUS__RECEIVED_TARGET_ABORT_MASK                                              0x1000L
+#define BIF_CFG_DEV0_EPF0_VF4_STATUS__RECEIVED_MASTER_ABORT_MASK                                              0x2000L
+#define BIF_CFG_DEV0_EPF0_VF4_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                              0x4000L
+#define BIF_CFG_DEV0_EPF0_VF4_STATUS__PARITY_ERROR_DETECTED_MASK                                              0x8000L
+//BIF_CFG_DEV0_EPF0_VF4_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF4_REVISION_ID__MINOR_REV_ID__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF0_VF4_REVISION_ID__MAJOR_REV_ID__SHIFT                                                0x4
+#define BIF_CFG_DEV0_EPF0_VF4_REVISION_ID__MINOR_REV_ID_MASK                                                  0x0FL
+#define BIF_CFG_DEV0_EPF0_VF4_REVISION_ID__MAJOR_REV_ID_MASK                                                  0xF0L
+//BIF_CFG_DEV0_EPF0_VF4_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF4_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_VF4_PROG_INTERFACE__PROG_INTERFACE_MASK                                             0xFFL
+//BIF_CFG_DEV0_EPF0_VF4_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF4_SUB_CLASS__SUB_CLASS__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_VF4_SUB_CLASS__SUB_CLASS_MASK                                                       0xFFL
+//BIF_CFG_DEV0_EPF0_VF4_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF4_BASE_CLASS__BASE_CLASS__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF4_BASE_CLASS__BASE_CLASS_MASK                                                     0xFFL
+//BIF_CFG_DEV0_EPF0_VF4_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF4_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF0_VF4_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                0xFFL
+//BIF_CFG_DEV0_EPF0_VF4_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF4_LATENCY__LATENCY_TIMER__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF4_LATENCY__LATENCY_TIMER_MASK                                                     0xFFL
+//BIF_CFG_DEV0_EPF0_VF4_HEADER
+#define BIF_CFG_DEV0_EPF0_VF4_HEADER__HEADER_TYPE__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF0_VF4_HEADER__DEVICE_TYPE__SHIFT                                                      0x7
+#define BIF_CFG_DEV0_EPF0_VF4_HEADER__HEADER_TYPE_MASK                                                        0x7FL
+#define BIF_CFG_DEV0_EPF0_VF4_HEADER__DEVICE_TYPE_MASK                                                        0x80L
+//BIF_CFG_DEV0_EPF0_VF4_BIST
+#define BIF_CFG_DEV0_EPF0_VF4_BIST__BIST_COMP__SHIFT                                                          0x0
+#define BIF_CFG_DEV0_EPF0_VF4_BIST__BIST_STRT__SHIFT                                                          0x6
+#define BIF_CFG_DEV0_EPF0_VF4_BIST__BIST_CAP__SHIFT                                                           0x7
+#define BIF_CFG_DEV0_EPF0_VF4_BIST__BIST_COMP_MASK                                                            0x0FL
+#define BIF_CFG_DEV0_EPF0_VF4_BIST__BIST_STRT_MASK                                                            0x40L
+#define BIF_CFG_DEV0_EPF0_VF4_BIST__BIST_CAP_MASK                                                             0x80L
+//BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_1__BASE_ADDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_1__BASE_ADDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_2__BASE_ADDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_2__BASE_ADDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_3__BASE_ADDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_3__BASE_ADDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_4__BASE_ADDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_4__BASE_ADDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_5__BASE_ADDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_5__BASE_ADDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_6__BASE_ADDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF4_BASE_ADDR_6__BASE_ADDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF4_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_VF4_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK                                           0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                                 0x10
+#define BIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                            0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF4_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                   0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR__ROM_ENABLE__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT                                     0x1
+#define BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT                                    0x4
+#define BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                 0xb
+#define BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR__ROM_ENABLE_MASK                                                  0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK                                       0x0000000EL
+#define BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK                                      0x000000F0L
+#define BIF_CFG_DEV0_EPF0_VF4_ROM_BASE_ADDR__BASE_ADDR_MASK                                                   0xFFFFF800L
+//BIF_CFG_DEV0_EPF0_VF4_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF4_CAP_PTR__CAP_PTR__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF0_VF4_CAP_PTR__CAP_PTR_MASK                                                           0xFFL
+//BIF_CFG_DEV0_EPF0_VF4_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF4_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_VF4_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                             0xFFL
+//BIF_CFG_DEV0_EPF0_VF4_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF4_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF0_VF4_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                               0xFFL
+//BIF_CFG_DEV0_EPF0_VF4_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF4_MIN_GRANT__MIN_GNT__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF0_VF4_MIN_GRANT__MIN_GNT_MASK                                                         0xFFL
+//BIF_CFG_DEV0_EPF0_VF4_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF4_MAX_LATENCY__MAX_LAT__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_VF4_MAX_LATENCY__MAX_LAT_MASK                                                       0xFFL
+//BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST__CAP_ID__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                  0x8
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST__CAP_ID_MASK                                                      0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP_LIST__NEXT_PTR_MASK                                                    0xFF00L
+//BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__VERSION__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__DEVICE_TYPE__SHIFT                                                    0x4
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                               0x8
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                0x9
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__FLIT_MODE_SUPPORT__SHIFT                                              0xf
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__VERSION_MASK                                                          0x000FL
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__DEVICE_TYPE_MASK                                                      0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                  0x3E00L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CAP__FLIT_MODE_SUPPORT_MASK                                                0x8000L
+//BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                 0x3
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                 0x5
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                       0x6
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                        0x9
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                     0xf
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__RX_MPS_FIXED__SHIFT                                                 0x11
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                    0x12
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                    0x1a
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                  0x1c
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__MIXED_MPS_SUPPORTED__SHIFT                                          0x1d
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__TEE_IO_SUPPORT__SHIFT                                               0x1e
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                            0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__PHANTOM_FUNC_MASK                                                   0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__EXTENDED_TAG_MASK                                                   0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                         0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                          0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                       0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK                                       0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__RX_MPS_FIXED_MASK                                                   0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                      0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                      0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__FLR_CAPABLE_MASK                                                    0x10000000L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__MIXED_MPS_SUPPORTED_MASK                                            0x20000000L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP__TEE_IO_SUPPORT_MASK                                                 0x40000000L
+//BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                            0x1
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                0x2
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                               0x3
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                              0x4
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                            0x5
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                             0x8
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                             0x9
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                             0xa
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                 0xb
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                       0xc
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__INITIATE_FLR__SHIFT                                                0xf
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__CORR_ERR_EN_MASK                                                   0x0001L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                              0x0002L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                  0x0004L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__USR_REPORT_EN_MASK                                                 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                0x0010L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                              0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                               0x0100L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                               0x0200L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                               0x0400L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                   0x0800L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                         0x7000L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL__INITIATE_FLR_MASK                                                  0x8000L
+//BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__CORR_ERR__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                             0x1
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__FATAL_ERR__SHIFT                                                 0x2
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__USR_DETECTED__SHIFT                                              0x3
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__AUX_PWR__SHIFT                                                   0x4
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                         0x5
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                             0x6
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__CORR_ERR_MASK                                                    0x0001L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__NON_FATAL_ERR_MASK                                               0x0002L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__FATAL_ERR_MASK                                                   0x0004L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__USR_DETECTED_MASK                                                0x0008L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__AUX_PWR_MASK                                                     0x0010L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                           0x0020L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                               0x0040L
+//BIF_CFG_DEV0_EPF0_VF4_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__LINK_SPEED__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__LINK_WIDTH__SHIFT                                                     0x4
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__PM_SUPPORT__SHIFT                                                     0xa
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                               0xc
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                0xf
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                         0x12
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                    0x13
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                    0x14
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                       0x15
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                    0x16
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__PORT_NUMBER__SHIFT                                                    0x18
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__LINK_SPEED_MASK                                                       0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__LINK_WIDTH_MASK                                                       0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__PM_SUPPORT_MASK                                                       0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__L1_EXIT_LATENCY_MASK                                                  0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                           0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                      0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                      0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                         0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                      0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP__PORT_NUMBER_MASK                                                      0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__PM_CONTROL__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT                                  0x2
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                             0x3
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__LINK_DIS__SHIFT                                                      0x4
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__RETRAIN_LINK__SHIFT                                                  0x5
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                              0x6
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                 0x7
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                   0x9
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                     0xa
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                     0xb
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__SRIS_CLOCKING__SHIFT                                                 0xc
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__FLIT_MODE_DISABLE__SHIFT                                             0xd
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                         0xe
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__PM_CONTROL_MASK                                                      0x0003L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK                                    0x0004L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                               0x0008L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__LINK_DIS_MASK                                                        0x0010L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__RETRAIN_LINK_MASK                                                    0x0020L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                0x0040L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__EXTENDED_SYNC_MASK                                                   0x0080L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                       0x0100L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                     0x0200L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                       0x0400L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                       0x0800L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__SRIS_CLOCKING_MASK                                                   0x1000L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__FLIT_MODE_DISABLE_MASK                                               0x2000L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                           0xC000L
+//BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                       0x4
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__LINK_TRAINING__SHIFT                                               0xb
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                              0xc
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__DL_ACTIVE__SHIFT                                                   0xd
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                   0xe
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                   0xf
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                            0x000FL
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                         0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__LINK_TRAINING_MASK                                                 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                0x1000L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__DL_ACTIVE_MASK                                                     0x2000L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                     0x4000L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                     0x8000L
+//BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                   0x4
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                    0x5
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                  0x6
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                  0x7
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                  0x8
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                      0x9
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                   0xa
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                               0xb
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                          0xc
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                               0xe
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                             0x10
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                             0x11
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                              0x12
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                0x14
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                0x15
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                    0x16
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                              0x18
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                               0x1a
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                               0x1f
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                   0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                     0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                      0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                    0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                    0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                    0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                        0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                     0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                            0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                               0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                               0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                  0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                  0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                      0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                            0x4
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                          0x5
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                        0x6
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                   0x7
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                         0x8
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                      0x9
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__LTR_EN__SHIFT                                                     0xa
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                               0xb
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                               0xc
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__OBFF_EN__SHIFT                                                    0xd
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                0xf
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                            0x000FL
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                              0x0010L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                            0x0020L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                          0x0040L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                     0x0080L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                           0x0100L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                        0x0200L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__LTR_EN_MASK                                                       0x0400L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__OBFF_EN_MASK                                                      0x6000L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                  0x8000L
+//BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS2__RESERVED__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS2__RESERVED_MASK                                                   0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                          0x1
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                           0x8
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT                                      0x9
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                      0x10
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                     0x17
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                     0x18
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                 0x1f
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                            0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                             0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK                                        0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                        0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                       0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                       0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CAP2__DRS_SUPPORTED_MASK                                                   0x80000000L
+//BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                             0x4
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                  0x5
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                        0x6
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                  0x7
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                         0xa
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                               0xb
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                        0xc
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                              0x000FL
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                               0x0010L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                    0x0020L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                          0x0040L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__XMIT_MARGIN_MASK                                                    0x0380L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                           0x0400L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                          0xF000L
+//BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                  0x1
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                            0x2
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                            0x3
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                            0x4
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                              0x5
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                          0x6
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                          0x7
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                       0x8
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__FLIT_MODE_STATUS__SHIFT                                           0xa
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                              0xc
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                       0xf
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                         0x0001L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                    0x0002L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                              0x0004L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                              0x0008L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                              0x0010L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                0x0020L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                            0x0040L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                            0x0080L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                         0x0300L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__FLIT_MODE_STATUS_MASK                                             0x0400L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                0x7000L
+#define BIF_CFG_DEV0_EPF0_VF4_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                         0x8000L
+//BIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST__CAP_ID__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST__CAP_ID_MASK                                                       0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_CAP_LIST__NEXT_PTR_MASK                                                     0xFF00L
+//BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_EN__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                              0x1
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                               0x4
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                  0x7
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                  0x8
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT                                       0x9
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT                                        0xa
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_EN_MASK                                                       0x0001L
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                0x000EL
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_64BIT_MASK                                                    0x0080L
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                    0x0100L
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK                                         0x0200L
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK                                          0x0400L
+//BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                         0x2
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                           0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                           0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA__MSI_DATA__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA__MSI_DATA_MASK                                                     0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK                                             0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_MASK__MSI_MASK__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_MASK__MSI_MASK_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                               0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK                                       0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_MASK_64__MSI_MASK_64__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_MASK_64__MSI_MASK_64_MASK                                                   0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_PENDING__MSI_PENDING__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_PENDING__MSI_PENDING_MASK                                                   0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_VF4_MSI_PENDING_64__MSI_PENDING_64_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST__CAP_ID__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                  0x8
+#define BIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST__CAP_ID_MASK                                                      0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF4_MSIX_CAP_LIST__NEXT_PTR_MASK                                                    0xFF00L
+//BIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                            0xe
+#define BIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                   0xf
+#define BIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                             0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                              0x4000L
+#define BIF_CFG_DEV0_EPF0_VF4_MSIX_MSG_CNTL__MSIX_EN_MASK                                                     0x8000L
+//BIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                            0x3
+#define BIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                                 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF4_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                              0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF4_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF4_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF4_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                                0x3
+#define BIF_CFG_DEV0_EPF0_VF4_MSIX_PBA__MSIX_PBA_BIR_MASK                                                     0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF4_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                  0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                0x0
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                               0x10
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                              0x14
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                  0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                       0x10
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                    0x14
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                         0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                      0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_PCIE_DEVICE3_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_DEVICE3_ENH_CAP_LIST__CAP_ID__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_DEVICE3_ENH_CAP_LIST__CAP_VER__SHIFT                                       0x10
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_DEVICE3_ENH_CAP_LIST__NEXT_PTR__SHIFT                                      0x14
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_DEVICE3_ENH_CAP_LIST__CAP_ID_MASK                                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_DEVICE3_ENH_CAP_LIST__CAP_VER_MASK                                         0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_DEVICE3_ENH_CAP_LIST__NEXT_PTR_MASK                                        0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP3
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP3__DMWR_REQUEST_ROUTING_SUPPORTED__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_COMPLETER_SUPPORTED__SHIFT                   0x1
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_REQUESTER_SUPPORTED__SHIFT                   0x2
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP3__RECEIVER_L0P_SUPPORTED__SHIFT                                      0x3
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP3__PORT_L0P_EXIT_LATENCY__SHIFT                                       0x4
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP3__RETIMER_L0P_EXIT_LATENCY__SHIFT                                    0x7
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP3__DMWR_REQUEST_ROUTING_SUPPORTED_MASK                                0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_COMPLETER_SUPPORTED_MASK                     0x00000002L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_REQUESTER_SUPPORTED_MASK                     0x00000004L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP3__RECEIVER_L0P_SUPPORTED_MASK                                        0x00000008L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP3__PORT_L0P_EXIT_LATENCY_MASK                                         0x00000070L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CAP3__RETIMER_L0P_EXIT_LATENCY_MASK                                      0x00000380L
+//BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL3
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL3__DMWR_REQUEST_ENABLE__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL3__DMWR_EGRESS_BLOCKING__SHIFT                                       0x1
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL3__DEVICE_CNTL3_14BIT_TAG_REQUESTER_ENABLE__SHIFT                    0x2
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL3__L0P_ENABLE__SHIFT                                                 0x3
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL3__TARGET_LINK_WIDTH__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL3__DMWR_REQUEST_ENABLE_MASK                                          0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL3__DMWR_EGRESS_BLOCKING_MASK                                         0x00000002L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL3__DEVICE_CNTL3_14BIT_TAG_REQUESTER_ENABLE_MASK                      0x00000004L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL3__L0P_ENABLE_MASK                                                   0x00000008L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_CNTL3__TARGET_LINK_WIDTH_MASK                                            0x00000070L
+//BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS3
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS3__INITIAL_LINK_WIDTH__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS3__SEGMENT_CAPTURED__SHIFT                                         0x3
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS3__REMOTE_L0P_SUPPORTED__SHIFT                                     0x4
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS3__INITIAL_LINK_WIDTH_MASK                                         0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS3__SEGMENT_CAPTURED_MASK                                           0x00000008L
+#define BIF_CFG_DEV0_EPF0_VF4_DEVICE_STATUS3__REMOTE_L0P_SUPPORTED_MASK                                       0x00000010L
+//BIF_CFG_DEV0_EPF0_VF4_PCIE_NULL1_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_NULL1_ENH_CAP_LIST__CAP_ID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_NULL1_ENH_CAP_LIST__CAP_VER__SHIFT                                         0x10
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_NULL1_ENH_CAP_LIST__NEXT_PTR__SHIFT                                        0x14
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_NULL1_ENH_CAP_LIST__CAP_ID_MASK                                            0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_NULL1_ENH_CAP_LIST__CAP_VER_MASK                                           0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_NULL1_ENH_CAP_LIST__NEXT_PTR_MASK                                          0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF4_PCIE_NULL2_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_NULL2_ENH_CAP_LIST__CAP_ID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_NULL2_ENH_CAP_LIST__CAP_VER__SHIFT                                         0x10
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_NULL2_ENH_CAP_LIST__NEXT_PTR__SHIFT                                        0x14
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_NULL2_ENH_CAP_LIST__CAP_ID_MASK                                            0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_NULL2_ENH_CAP_LIST__CAP_VER_MASK                                           0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_NULL2_ENH_CAP_LIST__NEXT_PTR_MASK                                          0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                  0x14
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                      0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                     0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                    0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                   0x4
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                0x5
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                   0xc
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                    0xd
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                               0xe
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                             0xf
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                 0x10
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                  0x11
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                   0x12
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                  0x13
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                            0x14
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                             0x15
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                            0x16
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                            0x17
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                   0x18
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                    0x19
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT               0x1a
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__DMWR_REQUEST_EGRESS_BLOCKED_STATUS__SHIFT               0x1b
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__IDE_CHECK_FAILED_STATUS__SHIFT                          0x1c
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__MISROUTED_IDE_TLP_STATUS__SHIFT                         0x1d
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__PCRC_CHECK_FAILED_STATUS__SHIFT                         0x1e
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                     0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                  0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                     0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                      0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                               0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                   0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                    0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                     0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                    0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                              0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                               0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                              0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                              0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                     0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                      0x02000000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__DMWR_REQUEST_EGRESS_BLOCKED_STATUS_MASK                 0x08000000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__IDE_CHECK_FAILED_STATUS_MASK                            0x10000000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__MISROUTED_IDE_TLP_STATUS_MASK                           0x20000000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_STATUS__PCRC_CHECK_FAILED_STATUS_MASK                           0x40000000L
+//BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                       0x4
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                    0x5
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                       0xc
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                        0xd
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                   0xe
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                 0xf
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                      0x11
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                       0x12
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                      0x13
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                0x14
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                 0x15
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                0x16
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                0x17
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                       0x18
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                        0x19
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                   0x1a
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__DMWR_REQUEST_EGRESS_BLOCKED_MASK__SHIFT                   0x1b
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__IDE_CHECK_FAILED_MASK__SHIFT                              0x1c
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__MISROUTED_IDE_TLP_MASK__SHIFT                             0x1d
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__PCRC_CHECK_FAILED_MASK__SHIFT                             0x1e
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                         0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                      0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                         0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                          0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                     0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                   0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                       0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                        0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                         0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                        0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                  0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                   0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                  0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                  0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                         0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                          0x02000000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                     0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__DMWR_REQUEST_EGRESS_BLOCKED_MASK_MASK                     0x08000000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__IDE_CHECK_FAILED_MASK_MASK                                0x10000000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__MISROUTED_IDE_TLP_MASK_MASK                               0x20000000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_MASK__PCRC_CHECK_FAILED_MASK_MASK                               0x40000000L
+//BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                               0x4
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                            0x5
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                               0xc
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                0xd
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                           0xe
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                         0xf
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                             0x10
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                              0x11
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                               0x12
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                              0x13
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                        0x14
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                         0x15
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                        0x16
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                        0x17
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT               0x18
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                0x19
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT           0x1a
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__DMWR_REQUEST_EGRESS_BLOCKED_SEVERITY__SHIFT           0x1b
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__IDE_CHECK_FAILED_SEVERITY__SHIFT                      0x1c
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__MISROUTED_IDE_TLP_SEVERITY__SHIFT                     0x1d
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__PCRC_CHECK_FAILED_SEVERITY__SHIFT                     0x1e
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                              0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                  0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                             0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                           0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                               0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                          0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                           0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                          0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                          0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                  0x02000000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK             0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__DMWR_REQUEST_EGRESS_BLOCKED_SEVERITY_MASK             0x08000000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__IDE_CHECK_FAILED_SEVERITY_MASK                        0x10000000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__MISROUTED_IDE_TLP_SEVERITY_MASK                       0x20000000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_UNCORR_ERR_SEVERITY__PCRC_CHECK_FAILED_SEVERITY_MASK                       0x40000000L
+//BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                     0x6
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                    0x7
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                         0x8
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                        0xc
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                       0xd
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                0xe
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                                0xf
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                       0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                       0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                      0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                           0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                          0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                         0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                  0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                  0x00008000L
+//BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                         0x6
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                        0x7
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                             0x8
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                            0xc
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                           0xd
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                    0xe
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                    0xf
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                           0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                           0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                          0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                               0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                              0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                             0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                      0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                      0x00008000L
+//BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT                                      0x5
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT                                       0x6
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                    0x7
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                0x9
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                 0xa
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                            0xb
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT                    0xc
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__HEADER_LOG_SIZE__SHIFT                                   0xd
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_WAS_FLIT_MODE__SHIFT                          0x12
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_SIZE__SHIFT                                   0x13
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                       0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK                                        0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK                                         0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                      0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                       0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                  0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                   0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                              0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK                      0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__HEADER_LOG_SIZE_MASK                                     0x0003E000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_WAS_FLIT_MODE_MASK                            0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_SIZE_MASK                                     0x00F80000L
+//BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG0__TLP_HDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG1__TLP_HDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG2__TLP_HDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG3__TLP_HDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG4
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG4__TLP_HDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG4__TLP_HDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                           0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG5
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG5__TLP_HDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG5__TLP_HDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                           0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG6
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG6__TLP_HDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG6__TLP_HDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                           0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG7
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG7__TLP_HDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG7__TLP_HDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                           0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG8
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG8__TLP_HDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG8__TLP_HDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG9
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG9__TLP_HDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG9__TLP_HDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG10
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG10__TLP_HDR__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG10__TLP_HDR_MASK                                                    0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG11
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG11__TLP_HDR__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG11__TLP_HDR_MASK                                                    0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG12
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG12__TLP_HDR__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG12__TLP_HDR_MASK                                                    0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG13
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG13__TLP_HDR__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_HDR_LOG13__TLP_HDR_MASK                                                    0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF4_PCIE_RTR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF4_RTR_DATA1
+#define BIF_CFG_DEV0_EPF0_VF4_RTR_DATA1__RESET_TIME__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF0_VF4_RTR_DATA1__DLUP_TIME__SHIFT                                                     0xc
+#define BIF_CFG_DEV0_EPF0_VF4_RTR_DATA1__RTR_VALID__SHIFT                                                     0x1f
+#define BIF_CFG_DEV0_EPF0_VF4_RTR_DATA1__RESET_TIME_MASK                                                      0x00000FFFL
+#define BIF_CFG_DEV0_EPF0_VF4_RTR_DATA1__DLUP_TIME_MASK                                                       0x00FFF000L
+#define BIF_CFG_DEV0_EPF0_VF4_RTR_DATA1__RTR_VALID_MASK                                                       0x80000000L
+//BIF_CFG_DEV0_EPF0_VF4_RTR_DATA2
+#define BIF_CFG_DEV0_EPF0_VF4_RTR_DATA2__FLR_TIME__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF0_VF4_RTR_DATA2__D3HOTD0_TIME__SHIFT                                                  0xc
+#define BIF_CFG_DEV0_EPF0_VF4_RTR_DATA2__FLR_TIME_MASK                                                        0x00000FFFL
+#define BIF_CFG_DEV0_EPF0_VF4_RTR_DATA2__D3HOTD0_TIME_MASK                                                    0x00FFF000L
+//BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                    0x1
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                          0x8
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                     0x0001L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                      0x0002L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                            0xFF00L
+//BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                    0x1
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                        0x4
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                     0x0001L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                      0x0002L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                          0x0070L
+//BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT                                       0x5
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT                                0x6
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED__SHIFT                                 0x7
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP__TEE_EXCLUSIVE_ATTR_SUPPORTED__SHIFT                               0x9
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK                                           0x001FL
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK                                         0x0020L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK                                  0x0040L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED_MASK                                   0x0080L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CAP__TEE_EXCLUSIVE_ATTR_SUPPORTED_MASK                                 0x0200L
+//BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CNTL__STU__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CNTL__TEE_EXCLUSIVE_ATTR_ENABLE__SHIFT                                 0xa
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT                                                0xf
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CNTL__STU_MASK                                                         0x001FL
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CNTL__TEE_EXCLUSIVE_ATTR_ENABLE_MASK                                   0x0400L
+#define BIF_CFG_DEV0_EPF0_VF4_PCIE_ATS_CNTL__ATC_ENABLE_MASK                                                  0x8000L
+
+
+// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_vf5_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF5_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF5_VENDOR_ID__VENDOR_ID__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_VF5_VENDOR_ID__VENDOR_ID_MASK                                                       0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_ID__DEVICE_ID__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_ID__DEVICE_ID_MASK                                                       0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__IO_ACCESS_EN__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__MEM_ACCESS_EN__SHIFT                                                   0x1
+#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__BUS_MASTER_EN__SHIFT                                                   0x2
+#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                0x3
+#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                         0x4
+#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__PAL_SNOOP_EN__SHIFT                                                    0x5
+#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                           0x6
+#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__AD_STEPPING__SHIFT                                                     0x7
+#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__SERR_EN__SHIFT                                                         0x8
+#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__FAST_B2B_EN__SHIFT                                                     0x9
+#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__INT_DIS__SHIFT                                                         0xa
+#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__IO_ACCESS_EN_MASK                                                      0x0001L
+#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__MEM_ACCESS_EN_MASK                                                     0x0002L
+#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__BUS_MASTER_EN_MASK                                                     0x0004L
+#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__SPECIAL_CYCLE_EN_MASK                                                  0x0008L
+#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                           0x0010L
+#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__PAL_SNOOP_EN_MASK                                                      0x0020L
+#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__PARITY_ERROR_RESPONSE_MASK                                             0x0040L
+#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__AD_STEPPING_MASK                                                       0x0080L
+#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__SERR_EN_MASK                                                           0x0100L
+#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__FAST_B2B_EN_MASK                                                       0x0200L
+#define BIF_CFG_DEV0_EPF0_VF5_COMMAND__INT_DIS_MASK                                                           0x0400L
+//BIF_CFG_DEV0_EPF0_VF5_STATUS
+#define BIF_CFG_DEV0_EPF0_VF5_STATUS__IMMEDIATE_READINESS__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF0_VF5_STATUS__INT_STATUS__SHIFT                                                       0x3
+#define BIF_CFG_DEV0_EPF0_VF5_STATUS__CAP_LIST__SHIFT                                                         0x4
+#define BIF_CFG_DEV0_EPF0_VF5_STATUS__PCI_66_CAP__SHIFT                                                       0x5
+#define BIF_CFG_DEV0_EPF0_VF5_STATUS__FAST_BACK_CAPABLE__SHIFT                                                0x7
+#define BIF_CFG_DEV0_EPF0_VF5_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                         0x8
+#define BIF_CFG_DEV0_EPF0_VF5_STATUS__DEVSEL_TIMING__SHIFT                                                    0x9
+#define BIF_CFG_DEV0_EPF0_VF5_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                              0xb
+#define BIF_CFG_DEV0_EPF0_VF5_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                            0xc
+#define BIF_CFG_DEV0_EPF0_VF5_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                            0xd
+#define BIF_CFG_DEV0_EPF0_VF5_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                            0xe
+#define BIF_CFG_DEV0_EPF0_VF5_STATUS__PARITY_ERROR_DETECTED__SHIFT                                            0xf
+#define BIF_CFG_DEV0_EPF0_VF5_STATUS__IMMEDIATE_READINESS_MASK                                                0x0001L
+#define BIF_CFG_DEV0_EPF0_VF5_STATUS__INT_STATUS_MASK                                                         0x0008L
+#define BIF_CFG_DEV0_EPF0_VF5_STATUS__CAP_LIST_MASK                                                           0x0010L
+#define BIF_CFG_DEV0_EPF0_VF5_STATUS__PCI_66_CAP_MASK                                                         0x0020L
+#define BIF_CFG_DEV0_EPF0_VF5_STATUS__FAST_BACK_CAPABLE_MASK                                                  0x0080L
+#define BIF_CFG_DEV0_EPF0_VF5_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                           0x0100L
+#define BIF_CFG_DEV0_EPF0_VF5_STATUS__DEVSEL_TIMING_MASK                                                      0x0600L
+#define BIF_CFG_DEV0_EPF0_VF5_STATUS__SIGNAL_TARGET_ABORT_MASK                                                0x0800L
+#define BIF_CFG_DEV0_EPF0_VF5_STATUS__RECEIVED_TARGET_ABORT_MASK                                              0x1000L
+#define BIF_CFG_DEV0_EPF0_VF5_STATUS__RECEIVED_MASTER_ABORT_MASK                                              0x2000L
+#define BIF_CFG_DEV0_EPF0_VF5_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                              0x4000L
+#define BIF_CFG_DEV0_EPF0_VF5_STATUS__PARITY_ERROR_DETECTED_MASK                                              0x8000L
+//BIF_CFG_DEV0_EPF0_VF5_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF5_REVISION_ID__MINOR_REV_ID__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF0_VF5_REVISION_ID__MAJOR_REV_ID__SHIFT                                                0x4
+#define BIF_CFG_DEV0_EPF0_VF5_REVISION_ID__MINOR_REV_ID_MASK                                                  0x0FL
+#define BIF_CFG_DEV0_EPF0_VF5_REVISION_ID__MAJOR_REV_ID_MASK                                                  0xF0L
+//BIF_CFG_DEV0_EPF0_VF5_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF5_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_VF5_PROG_INTERFACE__PROG_INTERFACE_MASK                                             0xFFL
+//BIF_CFG_DEV0_EPF0_VF5_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF5_SUB_CLASS__SUB_CLASS__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_VF5_SUB_CLASS__SUB_CLASS_MASK                                                       0xFFL
+//BIF_CFG_DEV0_EPF0_VF5_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF5_BASE_CLASS__BASE_CLASS__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF5_BASE_CLASS__BASE_CLASS_MASK                                                     0xFFL
+//BIF_CFG_DEV0_EPF0_VF5_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF5_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF0_VF5_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                0xFFL
+//BIF_CFG_DEV0_EPF0_VF5_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF5_LATENCY__LATENCY_TIMER__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF5_LATENCY__LATENCY_TIMER_MASK                                                     0xFFL
+//BIF_CFG_DEV0_EPF0_VF5_HEADER
+#define BIF_CFG_DEV0_EPF0_VF5_HEADER__HEADER_TYPE__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF0_VF5_HEADER__DEVICE_TYPE__SHIFT                                                      0x7
+#define BIF_CFG_DEV0_EPF0_VF5_HEADER__HEADER_TYPE_MASK                                                        0x7FL
+#define BIF_CFG_DEV0_EPF0_VF5_HEADER__DEVICE_TYPE_MASK                                                        0x80L
+//BIF_CFG_DEV0_EPF0_VF5_BIST
+#define BIF_CFG_DEV0_EPF0_VF5_BIST__BIST_COMP__SHIFT                                                          0x0
+#define BIF_CFG_DEV0_EPF0_VF5_BIST__BIST_STRT__SHIFT                                                          0x6
+#define BIF_CFG_DEV0_EPF0_VF5_BIST__BIST_CAP__SHIFT                                                           0x7
+#define BIF_CFG_DEV0_EPF0_VF5_BIST__BIST_COMP_MASK                                                            0x0FL
+#define BIF_CFG_DEV0_EPF0_VF5_BIST__BIST_STRT_MASK                                                            0x40L
+#define BIF_CFG_DEV0_EPF0_VF5_BIST__BIST_CAP_MASK                                                             0x80L
+//BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_1__BASE_ADDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_1__BASE_ADDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_2__BASE_ADDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_2__BASE_ADDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_3__BASE_ADDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_3__BASE_ADDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_4__BASE_ADDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_4__BASE_ADDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_5__BASE_ADDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_5__BASE_ADDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_6__BASE_ADDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF5_BASE_ADDR_6__BASE_ADDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF5_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_VF5_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK                                           0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                                 0x10
+#define BIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                            0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF5_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                   0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR__ROM_ENABLE__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT                                     0x1
+#define BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT                                    0x4
+#define BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                 0xb
+#define BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR__ROM_ENABLE_MASK                                                  0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK                                       0x0000000EL
+#define BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK                                      0x000000F0L
+#define BIF_CFG_DEV0_EPF0_VF5_ROM_BASE_ADDR__BASE_ADDR_MASK                                                   0xFFFFF800L
+//BIF_CFG_DEV0_EPF0_VF5_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF5_CAP_PTR__CAP_PTR__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF0_VF5_CAP_PTR__CAP_PTR_MASK                                                           0xFFL
+//BIF_CFG_DEV0_EPF0_VF5_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF5_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_VF5_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                             0xFFL
+//BIF_CFG_DEV0_EPF0_VF5_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF5_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF0_VF5_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                               0xFFL
+//BIF_CFG_DEV0_EPF0_VF5_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF5_MIN_GRANT__MIN_GNT__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF0_VF5_MIN_GRANT__MIN_GNT_MASK                                                         0xFFL
+//BIF_CFG_DEV0_EPF0_VF5_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF5_MAX_LATENCY__MAX_LAT__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_VF5_MAX_LATENCY__MAX_LAT_MASK                                                       0xFFL
+//BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST__CAP_ID__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                  0x8
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST__CAP_ID_MASK                                                      0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP_LIST__NEXT_PTR_MASK                                                    0xFF00L
+//BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__VERSION__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__DEVICE_TYPE__SHIFT                                                    0x4
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                               0x8
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                0x9
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__FLIT_MODE_SUPPORT__SHIFT                                              0xf
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__VERSION_MASK                                                          0x000FL
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__DEVICE_TYPE_MASK                                                      0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                  0x3E00L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CAP__FLIT_MODE_SUPPORT_MASK                                                0x8000L
+//BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                 0x3
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                 0x5
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                       0x6
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                        0x9
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                     0xf
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__RX_MPS_FIXED__SHIFT                                                 0x11
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                    0x12
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                    0x1a
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                  0x1c
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__MIXED_MPS_SUPPORTED__SHIFT                                          0x1d
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__TEE_IO_SUPPORT__SHIFT                                               0x1e
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                            0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__PHANTOM_FUNC_MASK                                                   0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__EXTENDED_TAG_MASK                                                   0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                         0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                          0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                       0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK                                       0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__RX_MPS_FIXED_MASK                                                   0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                      0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                      0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__FLR_CAPABLE_MASK                                                    0x10000000L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__MIXED_MPS_SUPPORTED_MASK                                            0x20000000L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP__TEE_IO_SUPPORT_MASK                                                 0x40000000L
+//BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                            0x1
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                0x2
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                               0x3
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                              0x4
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                            0x5
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                             0x8
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                             0x9
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                             0xa
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                 0xb
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                       0xc
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__INITIATE_FLR__SHIFT                                                0xf
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__CORR_ERR_EN_MASK                                                   0x0001L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                              0x0002L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                  0x0004L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__USR_REPORT_EN_MASK                                                 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                0x0010L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                              0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                               0x0100L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                               0x0200L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                               0x0400L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                   0x0800L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                         0x7000L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL__INITIATE_FLR_MASK                                                  0x8000L
+//BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__CORR_ERR__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                             0x1
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__FATAL_ERR__SHIFT                                                 0x2
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__USR_DETECTED__SHIFT                                              0x3
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__AUX_PWR__SHIFT                                                   0x4
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                         0x5
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                             0x6
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__CORR_ERR_MASK                                                    0x0001L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__NON_FATAL_ERR_MASK                                               0x0002L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__FATAL_ERR_MASK                                                   0x0004L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__USR_DETECTED_MASK                                                0x0008L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__AUX_PWR_MASK                                                     0x0010L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                           0x0020L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                               0x0040L
+//BIF_CFG_DEV0_EPF0_VF5_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__LINK_SPEED__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__LINK_WIDTH__SHIFT                                                     0x4
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__PM_SUPPORT__SHIFT                                                     0xa
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                               0xc
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                0xf
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                         0x12
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                    0x13
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                    0x14
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                       0x15
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                    0x16
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__PORT_NUMBER__SHIFT                                                    0x18
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__LINK_SPEED_MASK                                                       0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__LINK_WIDTH_MASK                                                       0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__PM_SUPPORT_MASK                                                       0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__L1_EXIT_LATENCY_MASK                                                  0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                           0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                      0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                      0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                         0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                      0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP__PORT_NUMBER_MASK                                                      0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__PM_CONTROL__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT                                  0x2
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                             0x3
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__LINK_DIS__SHIFT                                                      0x4
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__RETRAIN_LINK__SHIFT                                                  0x5
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                              0x6
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                 0x7
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                   0x9
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                     0xa
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                     0xb
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__SRIS_CLOCKING__SHIFT                                                 0xc
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__FLIT_MODE_DISABLE__SHIFT                                             0xd
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                         0xe
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__PM_CONTROL_MASK                                                      0x0003L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK                                    0x0004L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                               0x0008L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__LINK_DIS_MASK                                                        0x0010L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__RETRAIN_LINK_MASK                                                    0x0020L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                0x0040L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__EXTENDED_SYNC_MASK                                                   0x0080L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                       0x0100L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                     0x0200L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                       0x0400L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                       0x0800L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__SRIS_CLOCKING_MASK                                                   0x1000L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__FLIT_MODE_DISABLE_MASK                                               0x2000L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                           0xC000L
+//BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                       0x4
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__LINK_TRAINING__SHIFT                                               0xb
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                              0xc
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__DL_ACTIVE__SHIFT                                                   0xd
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                   0xe
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                   0xf
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                            0x000FL
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                         0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__LINK_TRAINING_MASK                                                 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                0x1000L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__DL_ACTIVE_MASK                                                     0x2000L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                     0x4000L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                     0x8000L
+//BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                   0x4
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                    0x5
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                  0x6
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                  0x7
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                  0x8
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                      0x9
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                   0xa
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                               0xb
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                          0xc
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                               0xe
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                             0x10
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                             0x11
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                              0x12
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                0x14
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                0x15
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                    0x16
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                              0x18
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                               0x1a
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                               0x1f
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                   0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                     0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                      0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                    0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                    0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                    0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                        0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                     0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                            0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                               0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                               0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                  0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                  0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                      0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                            0x4
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                          0x5
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                        0x6
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                   0x7
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                         0x8
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                      0x9
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__LTR_EN__SHIFT                                                     0xa
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                               0xb
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                               0xc
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__OBFF_EN__SHIFT                                                    0xd
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                0xf
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                            0x000FL
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                              0x0010L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                            0x0020L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                          0x0040L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                     0x0080L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                           0x0100L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                        0x0200L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__LTR_EN_MASK                                                       0x0400L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__OBFF_EN_MASK                                                      0x6000L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                  0x8000L
+//BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS2__RESERVED__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS2__RESERVED_MASK                                                   0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                          0x1
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                           0x8
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT                                      0x9
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                      0x10
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                     0x17
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                     0x18
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                 0x1f
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                            0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                             0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK                                        0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                        0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                       0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                       0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CAP2__DRS_SUPPORTED_MASK                                                   0x80000000L
+//BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                             0x4
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                  0x5
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                        0x6
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                  0x7
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                         0xa
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                               0xb
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                        0xc
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                              0x000FL
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                               0x0010L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                    0x0020L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                          0x0040L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__XMIT_MARGIN_MASK                                                    0x0380L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                           0x0400L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                          0xF000L
+//BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                  0x1
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                            0x2
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                            0x3
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                            0x4
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                              0x5
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                          0x6
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                          0x7
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                       0x8
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__FLIT_MODE_STATUS__SHIFT                                           0xa
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                              0xc
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                       0xf
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                         0x0001L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                    0x0002L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                              0x0004L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                              0x0008L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                              0x0010L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                0x0020L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                            0x0040L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                            0x0080L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                         0x0300L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__FLIT_MODE_STATUS_MASK                                             0x0400L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                0x7000L
+#define BIF_CFG_DEV0_EPF0_VF5_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                         0x8000L
+//BIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST__CAP_ID__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST__CAP_ID_MASK                                                       0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_CAP_LIST__NEXT_PTR_MASK                                                     0xFF00L
+//BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_EN__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                              0x1
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                               0x4
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                  0x7
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                  0x8
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT                                       0x9
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT                                        0xa
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_EN_MASK                                                       0x0001L
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                0x000EL
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_64BIT_MASK                                                    0x0080L
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                    0x0100L
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK                                         0x0200L
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK                                          0x0400L
+//BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                         0x2
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                           0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                           0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA__MSI_DATA__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA__MSI_DATA_MASK                                                     0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK                                             0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_MASK__MSI_MASK__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_MASK__MSI_MASK_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                               0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK                                       0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_MASK_64__MSI_MASK_64__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_MASK_64__MSI_MASK_64_MASK                                                   0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_PENDING__MSI_PENDING__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_PENDING__MSI_PENDING_MASK                                                   0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_VF5_MSI_PENDING_64__MSI_PENDING_64_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST__CAP_ID__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                  0x8
+#define BIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST__CAP_ID_MASK                                                      0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF5_MSIX_CAP_LIST__NEXT_PTR_MASK                                                    0xFF00L
+//BIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                            0xe
+#define BIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                   0xf
+#define BIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                             0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                              0x4000L
+#define BIF_CFG_DEV0_EPF0_VF5_MSIX_MSG_CNTL__MSIX_EN_MASK                                                     0x8000L
+//BIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                            0x3
+#define BIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                                 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF5_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                              0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF5_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF5_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF5_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                                0x3
+#define BIF_CFG_DEV0_EPF0_VF5_MSIX_PBA__MSIX_PBA_BIR_MASK                                                     0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF5_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                  0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                0x0
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                               0x10
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                              0x14
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                  0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                       0x10
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                    0x14
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                         0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                      0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_PCIE_DEVICE3_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_DEVICE3_ENH_CAP_LIST__CAP_ID__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_DEVICE3_ENH_CAP_LIST__CAP_VER__SHIFT                                       0x10
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_DEVICE3_ENH_CAP_LIST__NEXT_PTR__SHIFT                                      0x14
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_DEVICE3_ENH_CAP_LIST__CAP_ID_MASK                                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_DEVICE3_ENH_CAP_LIST__CAP_VER_MASK                                         0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_DEVICE3_ENH_CAP_LIST__NEXT_PTR_MASK                                        0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP3
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP3__DMWR_REQUEST_ROUTING_SUPPORTED__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_COMPLETER_SUPPORTED__SHIFT                   0x1
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_REQUESTER_SUPPORTED__SHIFT                   0x2
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP3__RECEIVER_L0P_SUPPORTED__SHIFT                                      0x3
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP3__PORT_L0P_EXIT_LATENCY__SHIFT                                       0x4
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP3__RETIMER_L0P_EXIT_LATENCY__SHIFT                                    0x7
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP3__DMWR_REQUEST_ROUTING_SUPPORTED_MASK                                0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_COMPLETER_SUPPORTED_MASK                     0x00000002L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_REQUESTER_SUPPORTED_MASK                     0x00000004L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP3__RECEIVER_L0P_SUPPORTED_MASK                                        0x00000008L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP3__PORT_L0P_EXIT_LATENCY_MASK                                         0x00000070L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CAP3__RETIMER_L0P_EXIT_LATENCY_MASK                                      0x00000380L
+//BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL3
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL3__DMWR_REQUEST_ENABLE__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL3__DMWR_EGRESS_BLOCKING__SHIFT                                       0x1
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL3__DEVICE_CNTL3_14BIT_TAG_REQUESTER_ENABLE__SHIFT                    0x2
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL3__L0P_ENABLE__SHIFT                                                 0x3
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL3__TARGET_LINK_WIDTH__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL3__DMWR_REQUEST_ENABLE_MASK                                          0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL3__DMWR_EGRESS_BLOCKING_MASK                                         0x00000002L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL3__DEVICE_CNTL3_14BIT_TAG_REQUESTER_ENABLE_MASK                      0x00000004L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL3__L0P_ENABLE_MASK                                                   0x00000008L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_CNTL3__TARGET_LINK_WIDTH_MASK                                            0x00000070L
+//BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS3
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS3__INITIAL_LINK_WIDTH__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS3__SEGMENT_CAPTURED__SHIFT                                         0x3
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS3__REMOTE_L0P_SUPPORTED__SHIFT                                     0x4
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS3__INITIAL_LINK_WIDTH_MASK                                         0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS3__SEGMENT_CAPTURED_MASK                                           0x00000008L
+#define BIF_CFG_DEV0_EPF0_VF5_DEVICE_STATUS3__REMOTE_L0P_SUPPORTED_MASK                                       0x00000010L
+//BIF_CFG_DEV0_EPF0_VF5_PCIE_NULL1_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_NULL1_ENH_CAP_LIST__CAP_ID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_NULL1_ENH_CAP_LIST__CAP_VER__SHIFT                                         0x10
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_NULL1_ENH_CAP_LIST__NEXT_PTR__SHIFT                                        0x14
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_NULL1_ENH_CAP_LIST__CAP_ID_MASK                                            0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_NULL1_ENH_CAP_LIST__CAP_VER_MASK                                           0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_NULL1_ENH_CAP_LIST__NEXT_PTR_MASK                                          0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF5_PCIE_NULL2_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_NULL2_ENH_CAP_LIST__CAP_ID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_NULL2_ENH_CAP_LIST__CAP_VER__SHIFT                                         0x10
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_NULL2_ENH_CAP_LIST__NEXT_PTR__SHIFT                                        0x14
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_NULL2_ENH_CAP_LIST__CAP_ID_MASK                                            0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_NULL2_ENH_CAP_LIST__CAP_VER_MASK                                           0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_NULL2_ENH_CAP_LIST__NEXT_PTR_MASK                                          0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                  0x14
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                      0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                     0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                    0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                   0x4
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                0x5
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                   0xc
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                    0xd
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                               0xe
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                             0xf
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                 0x10
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                  0x11
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                   0x12
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                  0x13
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                            0x14
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                             0x15
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                            0x16
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                            0x17
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                   0x18
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                    0x19
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT               0x1a
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__DMWR_REQUEST_EGRESS_BLOCKED_STATUS__SHIFT               0x1b
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__IDE_CHECK_FAILED_STATUS__SHIFT                          0x1c
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__MISROUTED_IDE_TLP_STATUS__SHIFT                         0x1d
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__PCRC_CHECK_FAILED_STATUS__SHIFT                         0x1e
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                     0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                  0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                     0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                      0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                               0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                   0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                    0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                     0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                    0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                              0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                               0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                              0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                              0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                     0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                      0x02000000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__DMWR_REQUEST_EGRESS_BLOCKED_STATUS_MASK                 0x08000000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__IDE_CHECK_FAILED_STATUS_MASK                            0x10000000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__MISROUTED_IDE_TLP_STATUS_MASK                           0x20000000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_STATUS__PCRC_CHECK_FAILED_STATUS_MASK                           0x40000000L
+//BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                       0x4
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                    0x5
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                       0xc
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                        0xd
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                   0xe
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                 0xf
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                      0x11
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                       0x12
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                      0x13
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                0x14
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                 0x15
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                0x16
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                0x17
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                       0x18
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                        0x19
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                   0x1a
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__DMWR_REQUEST_EGRESS_BLOCKED_MASK__SHIFT                   0x1b
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__IDE_CHECK_FAILED_MASK__SHIFT                              0x1c
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__MISROUTED_IDE_TLP_MASK__SHIFT                             0x1d
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__PCRC_CHECK_FAILED_MASK__SHIFT                             0x1e
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                         0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                      0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                         0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                          0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                     0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                   0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                       0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                        0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                         0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                        0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                  0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                   0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                  0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                  0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                         0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                          0x02000000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                     0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__DMWR_REQUEST_EGRESS_BLOCKED_MASK_MASK                     0x08000000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__IDE_CHECK_FAILED_MASK_MASK                                0x10000000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__MISROUTED_IDE_TLP_MASK_MASK                               0x20000000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_MASK__PCRC_CHECK_FAILED_MASK_MASK                               0x40000000L
+//BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                               0x4
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                            0x5
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                               0xc
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                0xd
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                           0xe
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                         0xf
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                             0x10
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                              0x11
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                               0x12
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                              0x13
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                        0x14
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                         0x15
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                        0x16
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                        0x17
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT               0x18
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                0x19
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT           0x1a
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__DMWR_REQUEST_EGRESS_BLOCKED_SEVERITY__SHIFT           0x1b
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__IDE_CHECK_FAILED_SEVERITY__SHIFT                      0x1c
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__MISROUTED_IDE_TLP_SEVERITY__SHIFT                     0x1d
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__PCRC_CHECK_FAILED_SEVERITY__SHIFT                     0x1e
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                              0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                  0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                             0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                           0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                               0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                          0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                           0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                          0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                          0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                  0x02000000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK             0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__DMWR_REQUEST_EGRESS_BLOCKED_SEVERITY_MASK             0x08000000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__IDE_CHECK_FAILED_SEVERITY_MASK                        0x10000000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__MISROUTED_IDE_TLP_SEVERITY_MASK                       0x20000000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_UNCORR_ERR_SEVERITY__PCRC_CHECK_FAILED_SEVERITY_MASK                       0x40000000L
+//BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                     0x6
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                    0x7
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                         0x8
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                        0xc
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                       0xd
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                0xe
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                                0xf
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                       0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                       0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                      0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                           0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                          0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                         0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                  0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                  0x00008000L
+//BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                         0x6
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                        0x7
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                             0x8
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                            0xc
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                           0xd
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                    0xe
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                    0xf
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                           0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                           0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                          0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                               0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                              0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                             0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                      0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                      0x00008000L
+//BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT                                      0x5
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT                                       0x6
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                    0x7
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                0x9
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                 0xa
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                            0xb
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT                    0xc
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__HEADER_LOG_SIZE__SHIFT                                   0xd
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_WAS_FLIT_MODE__SHIFT                          0x12
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_SIZE__SHIFT                                   0x13
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                       0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK                                        0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK                                         0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                      0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                       0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                  0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                   0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                              0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK                      0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__HEADER_LOG_SIZE_MASK                                     0x0003E000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_WAS_FLIT_MODE_MASK                            0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_SIZE_MASK                                     0x00F80000L
+//BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG0__TLP_HDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG1__TLP_HDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG2__TLP_HDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG3__TLP_HDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG4
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG4__TLP_HDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG4__TLP_HDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                           0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG5
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG5__TLP_HDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG5__TLP_HDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                           0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG6
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG6__TLP_HDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG6__TLP_HDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                           0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG7
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG7__TLP_HDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG7__TLP_HDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                           0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG8
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG8__TLP_HDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG8__TLP_HDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG9
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG9__TLP_HDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG9__TLP_HDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG10
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG10__TLP_HDR__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG10__TLP_HDR_MASK                                                    0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG11
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG11__TLP_HDR__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG11__TLP_HDR_MASK                                                    0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG12
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG12__TLP_HDR__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG12__TLP_HDR_MASK                                                    0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG13
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG13__TLP_HDR__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_HDR_LOG13__TLP_HDR_MASK                                                    0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF5_PCIE_RTR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF5_RTR_DATA1
+#define BIF_CFG_DEV0_EPF0_VF5_RTR_DATA1__RESET_TIME__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF0_VF5_RTR_DATA1__DLUP_TIME__SHIFT                                                     0xc
+#define BIF_CFG_DEV0_EPF0_VF5_RTR_DATA1__RTR_VALID__SHIFT                                                     0x1f
+#define BIF_CFG_DEV0_EPF0_VF5_RTR_DATA1__RESET_TIME_MASK                                                      0x00000FFFL
+#define BIF_CFG_DEV0_EPF0_VF5_RTR_DATA1__DLUP_TIME_MASK                                                       0x00FFF000L
+#define BIF_CFG_DEV0_EPF0_VF5_RTR_DATA1__RTR_VALID_MASK                                                       0x80000000L
+//BIF_CFG_DEV0_EPF0_VF5_RTR_DATA2
+#define BIF_CFG_DEV0_EPF0_VF5_RTR_DATA2__FLR_TIME__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF0_VF5_RTR_DATA2__D3HOTD0_TIME__SHIFT                                                  0xc
+#define BIF_CFG_DEV0_EPF0_VF5_RTR_DATA2__FLR_TIME_MASK                                                        0x00000FFFL
+#define BIF_CFG_DEV0_EPF0_VF5_RTR_DATA2__D3HOTD0_TIME_MASK                                                    0x00FFF000L
+//BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                    0x1
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                          0x8
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                     0x0001L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                      0x0002L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                            0xFF00L
+//BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                    0x1
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                        0x4
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                     0x0001L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                      0x0002L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                          0x0070L
+//BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT                                       0x5
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT                                0x6
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED__SHIFT                                 0x7
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP__TEE_EXCLUSIVE_ATTR_SUPPORTED__SHIFT                               0x9
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK                                           0x001FL
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK                                         0x0020L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK                                  0x0040L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED_MASK                                   0x0080L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CAP__TEE_EXCLUSIVE_ATTR_SUPPORTED_MASK                                 0x0200L
+//BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CNTL__STU__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CNTL__TEE_EXCLUSIVE_ATTR_ENABLE__SHIFT                                 0xa
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT                                                0xf
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CNTL__STU_MASK                                                         0x001FL
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CNTL__TEE_EXCLUSIVE_ATTR_ENABLE_MASK                                   0x0400L
+#define BIF_CFG_DEV0_EPF0_VF5_PCIE_ATS_CNTL__ATC_ENABLE_MASK                                                  0x8000L
+
+
+// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_vf6_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF6_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF6_VENDOR_ID__VENDOR_ID__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_VF6_VENDOR_ID__VENDOR_ID_MASK                                                       0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_ID__DEVICE_ID__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_ID__DEVICE_ID_MASK                                                       0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__IO_ACCESS_EN__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__MEM_ACCESS_EN__SHIFT                                                   0x1
+#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__BUS_MASTER_EN__SHIFT                                                   0x2
+#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                0x3
+#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                         0x4
+#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__PAL_SNOOP_EN__SHIFT                                                    0x5
+#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                           0x6
+#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__AD_STEPPING__SHIFT                                                     0x7
+#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__SERR_EN__SHIFT                                                         0x8
+#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__FAST_B2B_EN__SHIFT                                                     0x9
+#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__INT_DIS__SHIFT                                                         0xa
+#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__IO_ACCESS_EN_MASK                                                      0x0001L
+#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__MEM_ACCESS_EN_MASK                                                     0x0002L
+#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__BUS_MASTER_EN_MASK                                                     0x0004L
+#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__SPECIAL_CYCLE_EN_MASK                                                  0x0008L
+#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                           0x0010L
+#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__PAL_SNOOP_EN_MASK                                                      0x0020L
+#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__PARITY_ERROR_RESPONSE_MASK                                             0x0040L
+#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__AD_STEPPING_MASK                                                       0x0080L
+#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__SERR_EN_MASK                                                           0x0100L
+#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__FAST_B2B_EN_MASK                                                       0x0200L
+#define BIF_CFG_DEV0_EPF0_VF6_COMMAND__INT_DIS_MASK                                                           0x0400L
+//BIF_CFG_DEV0_EPF0_VF6_STATUS
+#define BIF_CFG_DEV0_EPF0_VF6_STATUS__IMMEDIATE_READINESS__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF0_VF6_STATUS__INT_STATUS__SHIFT                                                       0x3
+#define BIF_CFG_DEV0_EPF0_VF6_STATUS__CAP_LIST__SHIFT                                                         0x4
+#define BIF_CFG_DEV0_EPF0_VF6_STATUS__PCI_66_CAP__SHIFT                                                       0x5
+#define BIF_CFG_DEV0_EPF0_VF6_STATUS__FAST_BACK_CAPABLE__SHIFT                                                0x7
+#define BIF_CFG_DEV0_EPF0_VF6_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                         0x8
+#define BIF_CFG_DEV0_EPF0_VF6_STATUS__DEVSEL_TIMING__SHIFT                                                    0x9
+#define BIF_CFG_DEV0_EPF0_VF6_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                              0xb
+#define BIF_CFG_DEV0_EPF0_VF6_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                            0xc
+#define BIF_CFG_DEV0_EPF0_VF6_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                            0xd
+#define BIF_CFG_DEV0_EPF0_VF6_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                            0xe
+#define BIF_CFG_DEV0_EPF0_VF6_STATUS__PARITY_ERROR_DETECTED__SHIFT                                            0xf
+#define BIF_CFG_DEV0_EPF0_VF6_STATUS__IMMEDIATE_READINESS_MASK                                                0x0001L
+#define BIF_CFG_DEV0_EPF0_VF6_STATUS__INT_STATUS_MASK                                                         0x0008L
+#define BIF_CFG_DEV0_EPF0_VF6_STATUS__CAP_LIST_MASK                                                           0x0010L
+#define BIF_CFG_DEV0_EPF0_VF6_STATUS__PCI_66_CAP_MASK                                                         0x0020L
+#define BIF_CFG_DEV0_EPF0_VF6_STATUS__FAST_BACK_CAPABLE_MASK                                                  0x0080L
+#define BIF_CFG_DEV0_EPF0_VF6_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                           0x0100L
+#define BIF_CFG_DEV0_EPF0_VF6_STATUS__DEVSEL_TIMING_MASK                                                      0x0600L
+#define BIF_CFG_DEV0_EPF0_VF6_STATUS__SIGNAL_TARGET_ABORT_MASK                                                0x0800L
+#define BIF_CFG_DEV0_EPF0_VF6_STATUS__RECEIVED_TARGET_ABORT_MASK                                              0x1000L
+#define BIF_CFG_DEV0_EPF0_VF6_STATUS__RECEIVED_MASTER_ABORT_MASK                                              0x2000L
+#define BIF_CFG_DEV0_EPF0_VF6_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                              0x4000L
+#define BIF_CFG_DEV0_EPF0_VF6_STATUS__PARITY_ERROR_DETECTED_MASK                                              0x8000L
+//BIF_CFG_DEV0_EPF0_VF6_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF6_REVISION_ID__MINOR_REV_ID__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF0_VF6_REVISION_ID__MAJOR_REV_ID__SHIFT                                                0x4
+#define BIF_CFG_DEV0_EPF0_VF6_REVISION_ID__MINOR_REV_ID_MASK                                                  0x0FL
+#define BIF_CFG_DEV0_EPF0_VF6_REVISION_ID__MAJOR_REV_ID_MASK                                                  0xF0L
+//BIF_CFG_DEV0_EPF0_VF6_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF6_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_VF6_PROG_INTERFACE__PROG_INTERFACE_MASK                                             0xFFL
+//BIF_CFG_DEV0_EPF0_VF6_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF6_SUB_CLASS__SUB_CLASS__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_VF6_SUB_CLASS__SUB_CLASS_MASK                                                       0xFFL
+//BIF_CFG_DEV0_EPF0_VF6_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF6_BASE_CLASS__BASE_CLASS__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF6_BASE_CLASS__BASE_CLASS_MASK                                                     0xFFL
+//BIF_CFG_DEV0_EPF0_VF6_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF6_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF0_VF6_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                0xFFL
+//BIF_CFG_DEV0_EPF0_VF6_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF6_LATENCY__LATENCY_TIMER__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF6_LATENCY__LATENCY_TIMER_MASK                                                     0xFFL
+//BIF_CFG_DEV0_EPF0_VF6_HEADER
+#define BIF_CFG_DEV0_EPF0_VF6_HEADER__HEADER_TYPE__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF0_VF6_HEADER__DEVICE_TYPE__SHIFT                                                      0x7
+#define BIF_CFG_DEV0_EPF0_VF6_HEADER__HEADER_TYPE_MASK                                                        0x7FL
+#define BIF_CFG_DEV0_EPF0_VF6_HEADER__DEVICE_TYPE_MASK                                                        0x80L
+//BIF_CFG_DEV0_EPF0_VF6_BIST
+#define BIF_CFG_DEV0_EPF0_VF6_BIST__BIST_COMP__SHIFT                                                          0x0
+#define BIF_CFG_DEV0_EPF0_VF6_BIST__BIST_STRT__SHIFT                                                          0x6
+#define BIF_CFG_DEV0_EPF0_VF6_BIST__BIST_CAP__SHIFT                                                           0x7
+#define BIF_CFG_DEV0_EPF0_VF6_BIST__BIST_COMP_MASK                                                            0x0FL
+#define BIF_CFG_DEV0_EPF0_VF6_BIST__BIST_STRT_MASK                                                            0x40L
+#define BIF_CFG_DEV0_EPF0_VF6_BIST__BIST_CAP_MASK                                                             0x80L
+//BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_1__BASE_ADDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_1__BASE_ADDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_2__BASE_ADDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_2__BASE_ADDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_3__BASE_ADDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_3__BASE_ADDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_4__BASE_ADDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_4__BASE_ADDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_5__BASE_ADDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_5__BASE_ADDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_6__BASE_ADDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF6_BASE_ADDR_6__BASE_ADDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF6_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_VF6_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK                                           0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                                 0x10
+#define BIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                            0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF6_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                   0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR__ROM_ENABLE__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT                                     0x1
+#define BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT                                    0x4
+#define BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                 0xb
+#define BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR__ROM_ENABLE_MASK                                                  0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK                                       0x0000000EL
+#define BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK                                      0x000000F0L
+#define BIF_CFG_DEV0_EPF0_VF6_ROM_BASE_ADDR__BASE_ADDR_MASK                                                   0xFFFFF800L
+//BIF_CFG_DEV0_EPF0_VF6_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF6_CAP_PTR__CAP_PTR__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF0_VF6_CAP_PTR__CAP_PTR_MASK                                                           0xFFL
+//BIF_CFG_DEV0_EPF0_VF6_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF6_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_VF6_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                             0xFFL
+//BIF_CFG_DEV0_EPF0_VF6_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF6_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF0_VF6_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                               0xFFL
+//BIF_CFG_DEV0_EPF0_VF6_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF6_MIN_GRANT__MIN_GNT__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF0_VF6_MIN_GRANT__MIN_GNT_MASK                                                         0xFFL
+//BIF_CFG_DEV0_EPF0_VF6_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF6_MAX_LATENCY__MAX_LAT__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_VF6_MAX_LATENCY__MAX_LAT_MASK                                                       0xFFL
+//BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST__CAP_ID__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                  0x8
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST__CAP_ID_MASK                                                      0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP_LIST__NEXT_PTR_MASK                                                    0xFF00L
+//BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__VERSION__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__DEVICE_TYPE__SHIFT                                                    0x4
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                               0x8
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                0x9
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__FLIT_MODE_SUPPORT__SHIFT                                              0xf
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__VERSION_MASK                                                          0x000FL
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__DEVICE_TYPE_MASK                                                      0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                  0x3E00L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CAP__FLIT_MODE_SUPPORT_MASK                                                0x8000L
+//BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                 0x3
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                 0x5
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                       0x6
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                        0x9
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                     0xf
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__RX_MPS_FIXED__SHIFT                                                 0x11
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                    0x12
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                    0x1a
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                  0x1c
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__MIXED_MPS_SUPPORTED__SHIFT                                          0x1d
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__TEE_IO_SUPPORT__SHIFT                                               0x1e
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                            0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__PHANTOM_FUNC_MASK                                                   0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__EXTENDED_TAG_MASK                                                   0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                         0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                          0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                       0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK                                       0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__RX_MPS_FIXED_MASK                                                   0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                      0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                      0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__FLR_CAPABLE_MASK                                                    0x10000000L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__MIXED_MPS_SUPPORTED_MASK                                            0x20000000L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP__TEE_IO_SUPPORT_MASK                                                 0x40000000L
+//BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                            0x1
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                0x2
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                               0x3
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                              0x4
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                            0x5
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                             0x8
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                             0x9
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                             0xa
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                 0xb
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                       0xc
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__INITIATE_FLR__SHIFT                                                0xf
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__CORR_ERR_EN_MASK                                                   0x0001L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                              0x0002L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                  0x0004L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__USR_REPORT_EN_MASK                                                 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                0x0010L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                              0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                               0x0100L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                               0x0200L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                               0x0400L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                   0x0800L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                         0x7000L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL__INITIATE_FLR_MASK                                                  0x8000L
+//BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__CORR_ERR__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                             0x1
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__FATAL_ERR__SHIFT                                                 0x2
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__USR_DETECTED__SHIFT                                              0x3
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__AUX_PWR__SHIFT                                                   0x4
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                         0x5
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                             0x6
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__CORR_ERR_MASK                                                    0x0001L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__NON_FATAL_ERR_MASK                                               0x0002L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__FATAL_ERR_MASK                                                   0x0004L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__USR_DETECTED_MASK                                                0x0008L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__AUX_PWR_MASK                                                     0x0010L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                           0x0020L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                               0x0040L
+//BIF_CFG_DEV0_EPF0_VF6_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__LINK_SPEED__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__LINK_WIDTH__SHIFT                                                     0x4
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__PM_SUPPORT__SHIFT                                                     0xa
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                               0xc
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                0xf
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                         0x12
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                    0x13
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                    0x14
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                       0x15
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                    0x16
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__PORT_NUMBER__SHIFT                                                    0x18
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__LINK_SPEED_MASK                                                       0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__LINK_WIDTH_MASK                                                       0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__PM_SUPPORT_MASK                                                       0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__L1_EXIT_LATENCY_MASK                                                  0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                           0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                      0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                      0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                         0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                      0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP__PORT_NUMBER_MASK                                                      0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__PM_CONTROL__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT                                  0x2
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                             0x3
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__LINK_DIS__SHIFT                                                      0x4
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__RETRAIN_LINK__SHIFT                                                  0x5
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                              0x6
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                 0x7
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                   0x9
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                     0xa
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                     0xb
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__SRIS_CLOCKING__SHIFT                                                 0xc
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__FLIT_MODE_DISABLE__SHIFT                                             0xd
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                         0xe
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__PM_CONTROL_MASK                                                      0x0003L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK                                    0x0004L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                               0x0008L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__LINK_DIS_MASK                                                        0x0010L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__RETRAIN_LINK_MASK                                                    0x0020L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                0x0040L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__EXTENDED_SYNC_MASK                                                   0x0080L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                       0x0100L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                     0x0200L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                       0x0400L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                       0x0800L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__SRIS_CLOCKING_MASK                                                   0x1000L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__FLIT_MODE_DISABLE_MASK                                               0x2000L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                           0xC000L
+//BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                       0x4
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__LINK_TRAINING__SHIFT                                               0xb
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                              0xc
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__DL_ACTIVE__SHIFT                                                   0xd
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                   0xe
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                   0xf
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                            0x000FL
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                         0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__LINK_TRAINING_MASK                                                 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                0x1000L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__DL_ACTIVE_MASK                                                     0x2000L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                     0x4000L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                     0x8000L
+//BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                   0x4
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                    0x5
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                  0x6
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                  0x7
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                  0x8
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                      0x9
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                   0xa
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                               0xb
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                          0xc
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                               0xe
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                             0x10
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                             0x11
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                              0x12
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                0x14
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                0x15
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                    0x16
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                              0x18
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                               0x1a
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                               0x1f
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                   0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                     0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                      0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                    0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                    0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                    0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                        0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                     0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                            0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                               0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                               0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                  0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                  0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                      0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                            0x4
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                          0x5
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                        0x6
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                   0x7
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                         0x8
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                      0x9
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__LTR_EN__SHIFT                                                     0xa
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                               0xb
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                               0xc
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__OBFF_EN__SHIFT                                                    0xd
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                0xf
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                            0x000FL
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                              0x0010L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                            0x0020L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                          0x0040L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                     0x0080L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                           0x0100L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                        0x0200L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__LTR_EN_MASK                                                       0x0400L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__OBFF_EN_MASK                                                      0x6000L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                  0x8000L
+//BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS2__RESERVED__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS2__RESERVED_MASK                                                   0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                          0x1
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                           0x8
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT                                      0x9
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                      0x10
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                     0x17
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                     0x18
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                 0x1f
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                            0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                             0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK                                        0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                        0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                       0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                       0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CAP2__DRS_SUPPORTED_MASK                                                   0x80000000L
+//BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                             0x4
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                  0x5
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                        0x6
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                  0x7
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                         0xa
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                               0xb
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                        0xc
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                              0x000FL
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                               0x0010L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                    0x0020L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                          0x0040L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__XMIT_MARGIN_MASK                                                    0x0380L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                           0x0400L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                          0xF000L
+//BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                  0x1
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                            0x2
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                            0x3
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                            0x4
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                              0x5
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                          0x6
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                          0x7
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                       0x8
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__FLIT_MODE_STATUS__SHIFT                                           0xa
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                              0xc
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                       0xf
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                         0x0001L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                    0x0002L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                              0x0004L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                              0x0008L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                              0x0010L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                0x0020L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                            0x0040L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                            0x0080L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                         0x0300L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__FLIT_MODE_STATUS_MASK                                             0x0400L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                0x7000L
+#define BIF_CFG_DEV0_EPF0_VF6_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                         0x8000L
+//BIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST__CAP_ID__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST__CAP_ID_MASK                                                       0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_CAP_LIST__NEXT_PTR_MASK                                                     0xFF00L
+//BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_EN__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                              0x1
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                               0x4
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                  0x7
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                  0x8
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT                                       0x9
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT                                        0xa
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_EN_MASK                                                       0x0001L
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                0x000EL
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_64BIT_MASK                                                    0x0080L
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                    0x0100L
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK                                         0x0200L
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK                                          0x0400L
+//BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                         0x2
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                           0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                           0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA__MSI_DATA__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA__MSI_DATA_MASK                                                     0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK                                             0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_MASK__MSI_MASK__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_MASK__MSI_MASK_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                               0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK                                       0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_MASK_64__MSI_MASK_64__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_MASK_64__MSI_MASK_64_MASK                                                   0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_PENDING__MSI_PENDING__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_PENDING__MSI_PENDING_MASK                                                   0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_VF6_MSI_PENDING_64__MSI_PENDING_64_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST__CAP_ID__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                  0x8
+#define BIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST__CAP_ID_MASK                                                      0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF6_MSIX_CAP_LIST__NEXT_PTR_MASK                                                    0xFF00L
+//BIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                            0xe
+#define BIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                   0xf
+#define BIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                             0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                              0x4000L
+#define BIF_CFG_DEV0_EPF0_VF6_MSIX_MSG_CNTL__MSIX_EN_MASK                                                     0x8000L
+//BIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                            0x3
+#define BIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                                 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF6_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                              0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF6_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF6_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF6_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                                0x3
+#define BIF_CFG_DEV0_EPF0_VF6_MSIX_PBA__MSIX_PBA_BIR_MASK                                                     0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF6_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                  0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                0x0
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                               0x10
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                              0x14
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                  0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                       0x10
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                    0x14
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                         0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                      0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_PCIE_DEVICE3_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_DEVICE3_ENH_CAP_LIST__CAP_ID__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_DEVICE3_ENH_CAP_LIST__CAP_VER__SHIFT                                       0x10
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_DEVICE3_ENH_CAP_LIST__NEXT_PTR__SHIFT                                      0x14
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_DEVICE3_ENH_CAP_LIST__CAP_ID_MASK                                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_DEVICE3_ENH_CAP_LIST__CAP_VER_MASK                                         0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_DEVICE3_ENH_CAP_LIST__NEXT_PTR_MASK                                        0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP3
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP3__DMWR_REQUEST_ROUTING_SUPPORTED__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_COMPLETER_SUPPORTED__SHIFT                   0x1
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_REQUESTER_SUPPORTED__SHIFT                   0x2
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP3__RECEIVER_L0P_SUPPORTED__SHIFT                                      0x3
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP3__PORT_L0P_EXIT_LATENCY__SHIFT                                       0x4
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP3__RETIMER_L0P_EXIT_LATENCY__SHIFT                                    0x7
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP3__DMWR_REQUEST_ROUTING_SUPPORTED_MASK                                0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_COMPLETER_SUPPORTED_MASK                     0x00000002L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_REQUESTER_SUPPORTED_MASK                     0x00000004L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP3__RECEIVER_L0P_SUPPORTED_MASK                                        0x00000008L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP3__PORT_L0P_EXIT_LATENCY_MASK                                         0x00000070L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CAP3__RETIMER_L0P_EXIT_LATENCY_MASK                                      0x00000380L
+//BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL3
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL3__DMWR_REQUEST_ENABLE__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL3__DMWR_EGRESS_BLOCKING__SHIFT                                       0x1
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL3__DEVICE_CNTL3_14BIT_TAG_REQUESTER_ENABLE__SHIFT                    0x2
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL3__L0P_ENABLE__SHIFT                                                 0x3
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL3__TARGET_LINK_WIDTH__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL3__DMWR_REQUEST_ENABLE_MASK                                          0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL3__DMWR_EGRESS_BLOCKING_MASK                                         0x00000002L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL3__DEVICE_CNTL3_14BIT_TAG_REQUESTER_ENABLE_MASK                      0x00000004L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL3__L0P_ENABLE_MASK                                                   0x00000008L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_CNTL3__TARGET_LINK_WIDTH_MASK                                            0x00000070L
+//BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS3
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS3__INITIAL_LINK_WIDTH__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS3__SEGMENT_CAPTURED__SHIFT                                         0x3
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS3__REMOTE_L0P_SUPPORTED__SHIFT                                     0x4
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS3__INITIAL_LINK_WIDTH_MASK                                         0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS3__SEGMENT_CAPTURED_MASK                                           0x00000008L
+#define BIF_CFG_DEV0_EPF0_VF6_DEVICE_STATUS3__REMOTE_L0P_SUPPORTED_MASK                                       0x00000010L
+//BIF_CFG_DEV0_EPF0_VF6_PCIE_NULL1_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_NULL1_ENH_CAP_LIST__CAP_ID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_NULL1_ENH_CAP_LIST__CAP_VER__SHIFT                                         0x10
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_NULL1_ENH_CAP_LIST__NEXT_PTR__SHIFT                                        0x14
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_NULL1_ENH_CAP_LIST__CAP_ID_MASK                                            0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_NULL1_ENH_CAP_LIST__CAP_VER_MASK                                           0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_NULL1_ENH_CAP_LIST__NEXT_PTR_MASK                                          0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF6_PCIE_NULL2_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_NULL2_ENH_CAP_LIST__CAP_ID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_NULL2_ENH_CAP_LIST__CAP_VER__SHIFT                                         0x10
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_NULL2_ENH_CAP_LIST__NEXT_PTR__SHIFT                                        0x14
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_NULL2_ENH_CAP_LIST__CAP_ID_MASK                                            0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_NULL2_ENH_CAP_LIST__CAP_VER_MASK                                           0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_NULL2_ENH_CAP_LIST__NEXT_PTR_MASK                                          0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                  0x14
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                      0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                     0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                    0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                   0x4
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                0x5
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                   0xc
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                    0xd
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                               0xe
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                             0xf
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                 0x10
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                  0x11
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                   0x12
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                  0x13
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                            0x14
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                             0x15
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                            0x16
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                            0x17
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                   0x18
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                    0x19
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT               0x1a
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__DMWR_REQUEST_EGRESS_BLOCKED_STATUS__SHIFT               0x1b
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__IDE_CHECK_FAILED_STATUS__SHIFT                          0x1c
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__MISROUTED_IDE_TLP_STATUS__SHIFT                         0x1d
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__PCRC_CHECK_FAILED_STATUS__SHIFT                         0x1e
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                     0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                  0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                     0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                      0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                               0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                   0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                    0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                     0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                    0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                              0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                               0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                              0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                              0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                     0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                      0x02000000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__DMWR_REQUEST_EGRESS_BLOCKED_STATUS_MASK                 0x08000000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__IDE_CHECK_FAILED_STATUS_MASK                            0x10000000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__MISROUTED_IDE_TLP_STATUS_MASK                           0x20000000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_STATUS__PCRC_CHECK_FAILED_STATUS_MASK                           0x40000000L
+//BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                       0x4
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                    0x5
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                       0xc
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                        0xd
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                   0xe
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                 0xf
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                      0x11
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                       0x12
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                      0x13
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                0x14
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                 0x15
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                0x16
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                0x17
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                       0x18
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                        0x19
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                   0x1a
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__DMWR_REQUEST_EGRESS_BLOCKED_MASK__SHIFT                   0x1b
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__IDE_CHECK_FAILED_MASK__SHIFT                              0x1c
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__MISROUTED_IDE_TLP_MASK__SHIFT                             0x1d
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__PCRC_CHECK_FAILED_MASK__SHIFT                             0x1e
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                         0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                      0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                         0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                          0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                     0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                   0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                       0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                        0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                         0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                        0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                  0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                   0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                  0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                  0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                         0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                          0x02000000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                     0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__DMWR_REQUEST_EGRESS_BLOCKED_MASK_MASK                     0x08000000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__IDE_CHECK_FAILED_MASK_MASK                                0x10000000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__MISROUTED_IDE_TLP_MASK_MASK                               0x20000000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_MASK__PCRC_CHECK_FAILED_MASK_MASK                               0x40000000L
+//BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                               0x4
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                            0x5
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                               0xc
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                0xd
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                           0xe
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                         0xf
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                             0x10
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                              0x11
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                               0x12
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                              0x13
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                        0x14
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                         0x15
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                        0x16
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                        0x17
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT               0x18
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                0x19
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT           0x1a
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__DMWR_REQUEST_EGRESS_BLOCKED_SEVERITY__SHIFT           0x1b
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__IDE_CHECK_FAILED_SEVERITY__SHIFT                      0x1c
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__MISROUTED_IDE_TLP_SEVERITY__SHIFT                     0x1d
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__PCRC_CHECK_FAILED_SEVERITY__SHIFT                     0x1e
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                              0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                  0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                             0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                           0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                               0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                          0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                           0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                          0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                          0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                  0x02000000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK             0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__DMWR_REQUEST_EGRESS_BLOCKED_SEVERITY_MASK             0x08000000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__IDE_CHECK_FAILED_SEVERITY_MASK                        0x10000000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__MISROUTED_IDE_TLP_SEVERITY_MASK                       0x20000000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_UNCORR_ERR_SEVERITY__PCRC_CHECK_FAILED_SEVERITY_MASK                       0x40000000L
+//BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                     0x6
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                    0x7
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                         0x8
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                        0xc
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                       0xd
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                0xe
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                                0xf
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                       0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                       0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                      0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                           0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                          0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                         0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                  0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                  0x00008000L
+//BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                         0x6
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                        0x7
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                             0x8
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                            0xc
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                           0xd
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                    0xe
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                    0xf
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                           0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                           0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                          0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                               0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                              0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                             0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                      0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                      0x00008000L
+//BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT                                      0x5
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT                                       0x6
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                    0x7
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                0x9
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                 0xa
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                            0xb
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT                    0xc
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__HEADER_LOG_SIZE__SHIFT                                   0xd
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_WAS_FLIT_MODE__SHIFT                          0x12
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_SIZE__SHIFT                                   0x13
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                       0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK                                        0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK                                         0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                      0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                       0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                  0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                   0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                              0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK                      0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__HEADER_LOG_SIZE_MASK                                     0x0003E000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_WAS_FLIT_MODE_MASK                            0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_SIZE_MASK                                     0x00F80000L
+//BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG0__TLP_HDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG1__TLP_HDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG2__TLP_HDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG3__TLP_HDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG4
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG4__TLP_HDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG4__TLP_HDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                           0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG5
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG5__TLP_HDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG5__TLP_HDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                           0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG6
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG6__TLP_HDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG6__TLP_HDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                           0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG7
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG7__TLP_HDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG7__TLP_HDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                           0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG8
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG8__TLP_HDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG8__TLP_HDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG9
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG9__TLP_HDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG9__TLP_HDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG10
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG10__TLP_HDR__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG10__TLP_HDR_MASK                                                    0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG11
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG11__TLP_HDR__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG11__TLP_HDR_MASK                                                    0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG12
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG12__TLP_HDR__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG12__TLP_HDR_MASK                                                    0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG13
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG13__TLP_HDR__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_HDR_LOG13__TLP_HDR_MASK                                                    0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF6_PCIE_RTR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF6_RTR_DATA1
+#define BIF_CFG_DEV0_EPF0_VF6_RTR_DATA1__RESET_TIME__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF0_VF6_RTR_DATA1__DLUP_TIME__SHIFT                                                     0xc
+#define BIF_CFG_DEV0_EPF0_VF6_RTR_DATA1__RTR_VALID__SHIFT                                                     0x1f
+#define BIF_CFG_DEV0_EPF0_VF6_RTR_DATA1__RESET_TIME_MASK                                                      0x00000FFFL
+#define BIF_CFG_DEV0_EPF0_VF6_RTR_DATA1__DLUP_TIME_MASK                                                       0x00FFF000L
+#define BIF_CFG_DEV0_EPF0_VF6_RTR_DATA1__RTR_VALID_MASK                                                       0x80000000L
+//BIF_CFG_DEV0_EPF0_VF6_RTR_DATA2
+#define BIF_CFG_DEV0_EPF0_VF6_RTR_DATA2__FLR_TIME__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF0_VF6_RTR_DATA2__D3HOTD0_TIME__SHIFT                                                  0xc
+#define BIF_CFG_DEV0_EPF0_VF6_RTR_DATA2__FLR_TIME_MASK                                                        0x00000FFFL
+#define BIF_CFG_DEV0_EPF0_VF6_RTR_DATA2__D3HOTD0_TIME_MASK                                                    0x00FFF000L
+//BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                    0x1
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                          0x8
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                     0x0001L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                      0x0002L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                            0xFF00L
+//BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                    0x1
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                        0x4
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                     0x0001L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                      0x0002L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                          0x0070L
+//BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT                                       0x5
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT                                0x6
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED__SHIFT                                 0x7
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP__TEE_EXCLUSIVE_ATTR_SUPPORTED__SHIFT                               0x9
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK                                           0x001FL
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK                                         0x0020L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK                                  0x0040L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED_MASK                                   0x0080L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CAP__TEE_EXCLUSIVE_ATTR_SUPPORTED_MASK                                 0x0200L
+//BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CNTL__STU__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CNTL__TEE_EXCLUSIVE_ATTR_ENABLE__SHIFT                                 0xa
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT                                                0xf
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CNTL__STU_MASK                                                         0x001FL
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CNTL__TEE_EXCLUSIVE_ATTR_ENABLE_MASK                                   0x0400L
+#define BIF_CFG_DEV0_EPF0_VF6_PCIE_ATS_CNTL__ATC_ENABLE_MASK                                                  0x8000L
+
+
+// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf0_vf7_bifcfgdecp
+//BIF_CFG_DEV0_EPF0_VF7_VENDOR_ID
+#define BIF_CFG_DEV0_EPF0_VF7_VENDOR_ID__VENDOR_ID__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_VF7_VENDOR_ID__VENDOR_ID_MASK                                                       0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_DEVICE_ID
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_ID__DEVICE_ID__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_ID__DEVICE_ID_MASK                                                       0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_COMMAND
+#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__IO_ACCESS_EN__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__MEM_ACCESS_EN__SHIFT                                                   0x1
+#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__BUS_MASTER_EN__SHIFT                                                   0x2
+#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                0x3
+#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                         0x4
+#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__PAL_SNOOP_EN__SHIFT                                                    0x5
+#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                           0x6
+#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__AD_STEPPING__SHIFT                                                     0x7
+#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__SERR_EN__SHIFT                                                         0x8
+#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__FAST_B2B_EN__SHIFT                                                     0x9
+#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__INT_DIS__SHIFT                                                         0xa
+#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__IO_ACCESS_EN_MASK                                                      0x0001L
+#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__MEM_ACCESS_EN_MASK                                                     0x0002L
+#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__BUS_MASTER_EN_MASK                                                     0x0004L
+#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__SPECIAL_CYCLE_EN_MASK                                                  0x0008L
+#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                           0x0010L
+#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__PAL_SNOOP_EN_MASK                                                      0x0020L
+#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__PARITY_ERROR_RESPONSE_MASK                                             0x0040L
+#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__AD_STEPPING_MASK                                                       0x0080L
+#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__SERR_EN_MASK                                                           0x0100L
+#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__FAST_B2B_EN_MASK                                                       0x0200L
+#define BIF_CFG_DEV0_EPF0_VF7_COMMAND__INT_DIS_MASK                                                           0x0400L
+//BIF_CFG_DEV0_EPF0_VF7_STATUS
+#define BIF_CFG_DEV0_EPF0_VF7_STATUS__IMMEDIATE_READINESS__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF0_VF7_STATUS__INT_STATUS__SHIFT                                                       0x3
+#define BIF_CFG_DEV0_EPF0_VF7_STATUS__CAP_LIST__SHIFT                                                         0x4
+#define BIF_CFG_DEV0_EPF0_VF7_STATUS__PCI_66_CAP__SHIFT                                                       0x5
+#define BIF_CFG_DEV0_EPF0_VF7_STATUS__FAST_BACK_CAPABLE__SHIFT                                                0x7
+#define BIF_CFG_DEV0_EPF0_VF7_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                         0x8
+#define BIF_CFG_DEV0_EPF0_VF7_STATUS__DEVSEL_TIMING__SHIFT                                                    0x9
+#define BIF_CFG_DEV0_EPF0_VF7_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                              0xb
+#define BIF_CFG_DEV0_EPF0_VF7_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                            0xc
+#define BIF_CFG_DEV0_EPF0_VF7_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                            0xd
+#define BIF_CFG_DEV0_EPF0_VF7_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                            0xe
+#define BIF_CFG_DEV0_EPF0_VF7_STATUS__PARITY_ERROR_DETECTED__SHIFT                                            0xf
+#define BIF_CFG_DEV0_EPF0_VF7_STATUS__IMMEDIATE_READINESS_MASK                                                0x0001L
+#define BIF_CFG_DEV0_EPF0_VF7_STATUS__INT_STATUS_MASK                                                         0x0008L
+#define BIF_CFG_DEV0_EPF0_VF7_STATUS__CAP_LIST_MASK                                                           0x0010L
+#define BIF_CFG_DEV0_EPF0_VF7_STATUS__PCI_66_CAP_MASK                                                         0x0020L
+#define BIF_CFG_DEV0_EPF0_VF7_STATUS__FAST_BACK_CAPABLE_MASK                                                  0x0080L
+#define BIF_CFG_DEV0_EPF0_VF7_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                           0x0100L
+#define BIF_CFG_DEV0_EPF0_VF7_STATUS__DEVSEL_TIMING_MASK                                                      0x0600L
+#define BIF_CFG_DEV0_EPF0_VF7_STATUS__SIGNAL_TARGET_ABORT_MASK                                                0x0800L
+#define BIF_CFG_DEV0_EPF0_VF7_STATUS__RECEIVED_TARGET_ABORT_MASK                                              0x1000L
+#define BIF_CFG_DEV0_EPF0_VF7_STATUS__RECEIVED_MASTER_ABORT_MASK                                              0x2000L
+#define BIF_CFG_DEV0_EPF0_VF7_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                              0x4000L
+#define BIF_CFG_DEV0_EPF0_VF7_STATUS__PARITY_ERROR_DETECTED_MASK                                              0x8000L
+//BIF_CFG_DEV0_EPF0_VF7_REVISION_ID
+#define BIF_CFG_DEV0_EPF0_VF7_REVISION_ID__MINOR_REV_ID__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF0_VF7_REVISION_ID__MAJOR_REV_ID__SHIFT                                                0x4
+#define BIF_CFG_DEV0_EPF0_VF7_REVISION_ID__MINOR_REV_ID_MASK                                                  0x0FL
+#define BIF_CFG_DEV0_EPF0_VF7_REVISION_ID__MAJOR_REV_ID_MASK                                                  0xF0L
+//BIF_CFG_DEV0_EPF0_VF7_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF0_VF7_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_VF7_PROG_INTERFACE__PROG_INTERFACE_MASK                                             0xFFL
+//BIF_CFG_DEV0_EPF0_VF7_SUB_CLASS
+#define BIF_CFG_DEV0_EPF0_VF7_SUB_CLASS__SUB_CLASS__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_VF7_SUB_CLASS__SUB_CLASS_MASK                                                       0xFFL
+//BIF_CFG_DEV0_EPF0_VF7_BASE_CLASS
+#define BIF_CFG_DEV0_EPF0_VF7_BASE_CLASS__BASE_CLASS__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF7_BASE_CLASS__BASE_CLASS_MASK                                                     0xFFL
+//BIF_CFG_DEV0_EPF0_VF7_CACHE_LINE
+#define BIF_CFG_DEV0_EPF0_VF7_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF0_VF7_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                0xFFL
+//BIF_CFG_DEV0_EPF0_VF7_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF7_LATENCY__LATENCY_TIMER__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF7_LATENCY__LATENCY_TIMER_MASK                                                     0xFFL
+//BIF_CFG_DEV0_EPF0_VF7_HEADER
+#define BIF_CFG_DEV0_EPF0_VF7_HEADER__HEADER_TYPE__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF0_VF7_HEADER__DEVICE_TYPE__SHIFT                                                      0x7
+#define BIF_CFG_DEV0_EPF0_VF7_HEADER__HEADER_TYPE_MASK                                                        0x7FL
+#define BIF_CFG_DEV0_EPF0_VF7_HEADER__DEVICE_TYPE_MASK                                                        0x80L
+//BIF_CFG_DEV0_EPF0_VF7_BIST
+#define BIF_CFG_DEV0_EPF0_VF7_BIST__BIST_COMP__SHIFT                                                          0x0
+#define BIF_CFG_DEV0_EPF0_VF7_BIST__BIST_STRT__SHIFT                                                          0x6
+#define BIF_CFG_DEV0_EPF0_VF7_BIST__BIST_CAP__SHIFT                                                           0x7
+#define BIF_CFG_DEV0_EPF0_VF7_BIST__BIST_COMP_MASK                                                            0x0FL
+#define BIF_CFG_DEV0_EPF0_VF7_BIST__BIST_STRT_MASK                                                            0x40L
+#define BIF_CFG_DEV0_EPF0_VF7_BIST__BIST_CAP_MASK                                                             0x80L
+//BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_1__BASE_ADDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_1__BASE_ADDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_2__BASE_ADDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_2__BASE_ADDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_3__BASE_ADDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_3__BASE_ADDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_4__BASE_ADDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_4__BASE_ADDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_5__BASE_ADDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_5__BASE_ADDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_6__BASE_ADDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF7_BASE_ADDR_6__BASE_ADDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF0_VF7_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_VF7_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK                                           0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                                 0x10
+#define BIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                            0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF7_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                   0xFFFF0000L
+//BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR__ROM_ENABLE__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT                                     0x1
+#define BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT                                    0x4
+#define BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                 0xb
+#define BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR__ROM_ENABLE_MASK                                                  0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK                                       0x0000000EL
+#define BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK                                      0x000000F0L
+#define BIF_CFG_DEV0_EPF0_VF7_ROM_BASE_ADDR__BASE_ADDR_MASK                                                   0xFFFFF800L
+//BIF_CFG_DEV0_EPF0_VF7_CAP_PTR
+#define BIF_CFG_DEV0_EPF0_VF7_CAP_PTR__CAP_PTR__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF0_VF7_CAP_PTR__CAP_PTR_MASK                                                           0xFFL
+//BIF_CFG_DEV0_EPF0_VF7_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF0_VF7_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_VF7_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                             0xFFL
+//BIF_CFG_DEV0_EPF0_VF7_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF0_VF7_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF0_VF7_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                               0xFFL
+//BIF_CFG_DEV0_EPF0_VF7_MIN_GRANT
+#define BIF_CFG_DEV0_EPF0_VF7_MIN_GRANT__MIN_GNT__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF0_VF7_MIN_GRANT__MIN_GNT_MASK                                                         0xFFL
+//BIF_CFG_DEV0_EPF0_VF7_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF0_VF7_MAX_LATENCY__MAX_LAT__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_VF7_MAX_LATENCY__MAX_LAT_MASK                                                       0xFFL
+//BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST__CAP_ID__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                  0x8
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST__CAP_ID_MASK                                                      0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP_LIST__NEXT_PTR_MASK                                                    0xFF00L
+//BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__VERSION__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__DEVICE_TYPE__SHIFT                                                    0x4
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                               0x8
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                0x9
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__FLIT_MODE_SUPPORT__SHIFT                                              0xf
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__VERSION_MASK                                                          0x000FL
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__DEVICE_TYPE_MASK                                                      0x00F0L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                 0x0100L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                  0x3E00L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CAP__FLIT_MODE_SUPPORT_MASK                                                0x8000L
+//BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                 0x3
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                 0x5
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                       0x6
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                        0x9
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                     0xf
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__RX_MPS_FIXED__SHIFT                                                 0x11
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                    0x12
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                    0x1a
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                  0x1c
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__MIXED_MPS_SUPPORTED__SHIFT                                          0x1d
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__TEE_IO_SUPPORT__SHIFT                                               0x1e
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                            0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__PHANTOM_FUNC_MASK                                                   0x00000018L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__EXTENDED_TAG_MASK                                                   0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                         0x000001C0L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                          0x00000E00L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                       0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK                                       0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__RX_MPS_FIXED_MASK                                                   0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                      0x03FC0000L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                      0x0C000000L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__FLR_CAPABLE_MASK                                                    0x10000000L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__MIXED_MPS_SUPPORTED_MASK                                            0x20000000L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP__TEE_IO_SUPPORT_MASK                                                 0x40000000L
+//BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                            0x1
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                0x2
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                               0x3
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                              0x4
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                            0x5
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                             0x8
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                             0x9
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                             0xa
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                 0xb
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                       0xc
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__INITIATE_FLR__SHIFT                                                0xf
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__CORR_ERR_EN_MASK                                                   0x0001L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                              0x0002L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                  0x0004L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__USR_REPORT_EN_MASK                                                 0x0008L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                0x0010L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                              0x00E0L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                               0x0100L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                               0x0200L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                               0x0400L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                   0x0800L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                         0x7000L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL__INITIATE_FLR_MASK                                                  0x8000L
+//BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__CORR_ERR__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                             0x1
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__FATAL_ERR__SHIFT                                                 0x2
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__USR_DETECTED__SHIFT                                              0x3
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__AUX_PWR__SHIFT                                                   0x4
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                         0x5
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                             0x6
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__CORR_ERR_MASK                                                    0x0001L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__NON_FATAL_ERR_MASK                                               0x0002L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__FATAL_ERR_MASK                                                   0x0004L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__USR_DETECTED_MASK                                                0x0008L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__AUX_PWR_MASK                                                     0x0010L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                           0x0020L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                               0x0040L
+//BIF_CFG_DEV0_EPF0_VF7_LINK_CAP
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__LINK_SPEED__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__LINK_WIDTH__SHIFT                                                     0x4
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__PM_SUPPORT__SHIFT                                                     0xa
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                               0xc
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                0xf
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                         0x12
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                    0x13
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                    0x14
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                       0x15
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                    0x16
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__PORT_NUMBER__SHIFT                                                    0x18
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__LINK_SPEED_MASK                                                       0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__LINK_WIDTH_MASK                                                       0x000003F0L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__PM_SUPPORT_MASK                                                       0x00000C00L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                 0x00007000L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__L1_EXIT_LATENCY_MASK                                                  0x00038000L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                           0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                      0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                      0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                         0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                      0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP__PORT_NUMBER_MASK                                                      0xFF000000L
+//BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__PM_CONTROL__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT                                  0x2
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                             0x3
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__LINK_DIS__SHIFT                                                      0x4
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__RETRAIN_LINK__SHIFT                                                  0x5
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                              0x6
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                 0x7
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                   0x9
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                     0xa
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                     0xb
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__SRIS_CLOCKING__SHIFT                                                 0xc
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__FLIT_MODE_DISABLE__SHIFT                                             0xd
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                         0xe
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__PM_CONTROL_MASK                                                      0x0003L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK                                    0x0004L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                               0x0008L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__LINK_DIS_MASK                                                        0x0010L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__RETRAIN_LINK_MASK                                                    0x0020L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                0x0040L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__EXTENDED_SYNC_MASK                                                   0x0080L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                       0x0100L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                     0x0200L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                       0x0400L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                       0x0800L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__SRIS_CLOCKING_MASK                                                   0x1000L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__FLIT_MODE_DISABLE_MASK                                               0x2000L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                           0xC000L
+//BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                       0x4
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__LINK_TRAINING__SHIFT                                               0xb
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                              0xc
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__DL_ACTIVE__SHIFT                                                   0xd
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                   0xe
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                   0xf
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                            0x000FL
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                         0x03F0L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__LINK_TRAINING_MASK                                                 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                0x1000L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__DL_ACTIVE_MASK                                                     0x2000L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                     0x4000L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                     0x8000L
+//BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                   0x4
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                    0x5
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                  0x6
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                  0x7
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                  0x8
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                      0x9
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                   0xa
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                               0xb
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                          0xc
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                               0xe
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                             0x10
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                             0x11
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                              0x12
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                0x14
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                0x15
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                    0x16
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                              0x18
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                               0x1a
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                               0x1f
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                   0x0000000FL
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                     0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                      0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                    0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                    0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                    0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                        0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                     0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                 0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                            0x00003000L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                 0x0000C000L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                               0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                               0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                0x000C0000L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                  0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                  0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                      0x00C00000L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                0x03000000L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                 0x80000000L
+//BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                            0x4
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                          0x5
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                        0x6
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                   0x7
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                         0x8
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                      0x9
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__LTR_EN__SHIFT                                                     0xa
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                               0xb
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                               0xc
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__OBFF_EN__SHIFT                                                    0xd
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                0xf
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                            0x000FL
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                              0x0010L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                            0x0020L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                          0x0040L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                     0x0080L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                           0x0100L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                        0x0200L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__LTR_EN_MASK                                                       0x0400L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                 0x1000L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__OBFF_EN_MASK                                                      0x6000L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                  0x8000L
+//BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS2__RESERVED__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS2__RESERVED_MASK                                                   0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                          0x1
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                           0x8
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT                                      0x9
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                      0x10
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                     0x17
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                     0x18
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                 0x1f
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                            0x000000FEL
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                             0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK                                        0x0000FE00L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                        0x007F0000L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                       0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                       0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CAP2__DRS_SUPPORTED_MASK                                                   0x80000000L
+//BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                             0x4
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                  0x5
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                        0x6
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                  0x7
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                         0xa
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                               0xb
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                        0xc
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                              0x000FL
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                               0x0010L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                    0x0020L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                          0x0040L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__XMIT_MARGIN_MASK                                                    0x0380L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                           0x0400L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                 0x0800L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                          0xF000L
+//BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                  0x1
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                            0x2
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                            0x3
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                            0x4
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                              0x5
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                          0x6
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                          0x7
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                       0x8
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__FLIT_MODE_STATUS__SHIFT                                           0xa
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                              0xc
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                       0xf
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                         0x0001L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                    0x0002L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                              0x0004L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                              0x0008L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                              0x0010L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                0x0020L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                            0x0040L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                            0x0080L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                         0x0300L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__FLIT_MODE_STATUS_MASK                                             0x0400L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                0x7000L
+#define BIF_CFG_DEV0_EPF0_VF7_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                         0x8000L
+//BIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST__CAP_ID__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST__CAP_ID_MASK                                                       0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_CAP_LIST__NEXT_PTR_MASK                                                     0xFF00L
+//BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_EN__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                              0x1
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                               0x4
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                  0x7
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                  0x8
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT                                       0x9
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT                                        0xa
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_EN_MASK                                                       0x0001L
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                0x000EL
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                 0x0070L
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_64BIT_MASK                                                    0x0080L
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                    0x0100L
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK                                         0x0200L
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK                                          0x0400L
+//BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                         0x2
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                           0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                           0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA__MSI_DATA__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA__MSI_DATA_MASK                                                     0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK                                             0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_MSI_MASK
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_MASK__MSI_MASK__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_MASK__MSI_MASK_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                               0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK                                       0xFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_MASK_64__MSI_MASK_64__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_MASK_64__MSI_MASK_64_MASK                                                   0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_MSI_PENDING
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_PENDING__MSI_PENDING__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_PENDING__MSI_PENDING_MASK                                                   0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_VF7_MSI_PENDING_64__MSI_PENDING_64_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST__CAP_ID__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                  0x8
+#define BIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST__CAP_ID_MASK                                                      0x00FFL
+#define BIF_CFG_DEV0_EPF0_VF7_MSIX_CAP_LIST__NEXT_PTR_MASK                                                    0xFF00L
+//BIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                            0xe
+#define BIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                   0xf
+#define BIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                             0x07FFL
+#define BIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                              0x4000L
+#define BIF_CFG_DEV0_EPF0_VF7_MSIX_MSG_CNTL__MSIX_EN_MASK                                                     0x8000L
+//BIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                            0x3
+#define BIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                                 0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF7_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                              0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF7_MSIX_PBA
+#define BIF_CFG_DEV0_EPF0_VF7_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF7_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                                0x3
+#define BIF_CFG_DEV0_EPF0_VF7_MSIX_PBA__MSIX_PBA_BIR_MASK                                                     0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF7_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                  0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                0x0
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                               0x10
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                              0x14
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                  0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                 0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                       0x10
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                    0x14
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                         0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                      0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_PCIE_DEVICE3_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_DEVICE3_ENH_CAP_LIST__CAP_ID__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_DEVICE3_ENH_CAP_LIST__CAP_VER__SHIFT                                       0x10
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_DEVICE3_ENH_CAP_LIST__NEXT_PTR__SHIFT                                      0x14
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_DEVICE3_ENH_CAP_LIST__CAP_ID_MASK                                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_DEVICE3_ENH_CAP_LIST__CAP_VER_MASK                                         0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_DEVICE3_ENH_CAP_LIST__NEXT_PTR_MASK                                        0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP3
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP3__DMWR_REQUEST_ROUTING_SUPPORTED__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_COMPLETER_SUPPORTED__SHIFT                   0x1
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_REQUESTER_SUPPORTED__SHIFT                   0x2
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP3__RECEIVER_L0P_SUPPORTED__SHIFT                                      0x3
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP3__PORT_L0P_EXIT_LATENCY__SHIFT                                       0x4
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP3__RETIMER_L0P_EXIT_LATENCY__SHIFT                                    0x7
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP3__DMWR_REQUEST_ROUTING_SUPPORTED_MASK                                0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_COMPLETER_SUPPORTED_MASK                     0x00000002L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_REQUESTER_SUPPORTED_MASK                     0x00000004L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP3__RECEIVER_L0P_SUPPORTED_MASK                                        0x00000008L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP3__PORT_L0P_EXIT_LATENCY_MASK                                         0x00000070L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CAP3__RETIMER_L0P_EXIT_LATENCY_MASK                                      0x00000380L
+//BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL3
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL3__DMWR_REQUEST_ENABLE__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL3__DMWR_EGRESS_BLOCKING__SHIFT                                       0x1
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL3__DEVICE_CNTL3_14BIT_TAG_REQUESTER_ENABLE__SHIFT                    0x2
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL3__L0P_ENABLE__SHIFT                                                 0x3
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL3__TARGET_LINK_WIDTH__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL3__DMWR_REQUEST_ENABLE_MASK                                          0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL3__DMWR_EGRESS_BLOCKING_MASK                                         0x00000002L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL3__DEVICE_CNTL3_14BIT_TAG_REQUESTER_ENABLE_MASK                      0x00000004L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL3__L0P_ENABLE_MASK                                                   0x00000008L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_CNTL3__TARGET_LINK_WIDTH_MASK                                            0x00000070L
+//BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS3
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS3__INITIAL_LINK_WIDTH__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS3__SEGMENT_CAPTURED__SHIFT                                         0x3
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS3__REMOTE_L0P_SUPPORTED__SHIFT                                     0x4
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS3__INITIAL_LINK_WIDTH_MASK                                         0x00000007L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS3__SEGMENT_CAPTURED_MASK                                           0x00000008L
+#define BIF_CFG_DEV0_EPF0_VF7_DEVICE_STATUS3__REMOTE_L0P_SUPPORTED_MASK                                       0x00000010L
+//BIF_CFG_DEV0_EPF0_VF7_PCIE_NULL1_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_NULL1_ENH_CAP_LIST__CAP_ID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_NULL1_ENH_CAP_LIST__CAP_VER__SHIFT                                         0x10
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_NULL1_ENH_CAP_LIST__NEXT_PTR__SHIFT                                        0x14
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_NULL1_ENH_CAP_LIST__CAP_ID_MASK                                            0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_NULL1_ENH_CAP_LIST__CAP_VER_MASK                                           0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_NULL1_ENH_CAP_LIST__NEXT_PTR_MASK                                          0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF7_PCIE_NULL2_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_NULL2_ENH_CAP_LIST__CAP_ID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_NULL2_ENH_CAP_LIST__CAP_VER__SHIFT                                         0x10
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_NULL2_ENH_CAP_LIST__NEXT_PTR__SHIFT                                        0x14
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_NULL2_ENH_CAP_LIST__CAP_ID_MASK                                            0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_NULL2_ENH_CAP_LIST__CAP_VER_MASK                                           0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_NULL2_ENH_CAP_LIST__NEXT_PTR_MASK                                          0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                  0x14
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                      0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                     0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                    0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                   0x4
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                0x5
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                   0xc
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                    0xd
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                               0xe
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                             0xf
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                 0x10
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                  0x11
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                   0x12
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                  0x13
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                            0x14
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                             0x15
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                            0x16
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                            0x17
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                   0x18
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                    0x19
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT               0x1a
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__DMWR_REQUEST_EGRESS_BLOCKED_STATUS__SHIFT               0x1b
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__IDE_CHECK_FAILED_STATUS__SHIFT                          0x1c
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__MISROUTED_IDE_TLP_STATUS__SHIFT                         0x1d
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__PCRC_CHECK_FAILED_STATUS__SHIFT                         0x1e
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                     0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                  0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                     0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                      0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                 0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                               0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                   0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                    0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                     0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                    0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                              0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                               0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                              0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                              0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                     0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                      0x02000000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                 0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__DMWR_REQUEST_EGRESS_BLOCKED_STATUS_MASK                 0x08000000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__IDE_CHECK_FAILED_STATUS_MASK                            0x10000000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__MISROUTED_IDE_TLP_STATUS_MASK                           0x20000000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_STATUS__PCRC_CHECK_FAILED_STATUS_MASK                           0x40000000L
+//BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                       0x4
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                    0x5
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                       0xc
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                        0xd
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                   0xe
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                 0xf
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                      0x11
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                       0x12
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                      0x13
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                0x14
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                 0x15
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                0x16
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                0x17
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                       0x18
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                        0x19
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                   0x1a
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__DMWR_REQUEST_EGRESS_BLOCKED_MASK__SHIFT                   0x1b
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__IDE_CHECK_FAILED_MASK__SHIFT                              0x1c
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__MISROUTED_IDE_TLP_MASK__SHIFT                             0x1d
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__PCRC_CHECK_FAILED_MASK__SHIFT                             0x1e
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                         0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                      0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                         0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                          0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                     0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                   0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                       0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                        0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                         0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                        0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                  0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                   0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                  0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                  0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                         0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                          0x02000000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                     0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__DMWR_REQUEST_EGRESS_BLOCKED_MASK_MASK                     0x08000000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__IDE_CHECK_FAILED_MASK_MASK                                0x10000000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__MISROUTED_IDE_TLP_MASK_MASK                               0x20000000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_MASK__PCRC_CHECK_FAILED_MASK_MASK                               0x40000000L
+//BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                               0x4
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                            0x5
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                               0xc
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                0xd
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                           0xe
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                         0xf
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                             0x10
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                              0x11
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                               0x12
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                              0x13
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                        0x14
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                         0x15
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                        0x16
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                        0x17
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT               0x18
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                0x19
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT           0x1a
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__DMWR_REQUEST_EGRESS_BLOCKED_SEVERITY__SHIFT           0x1b
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__IDE_CHECK_FAILED_SEVERITY__SHIFT                      0x1c
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__MISROUTED_IDE_TLP_SEVERITY__SHIFT                     0x1d
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__PCRC_CHECK_FAILED_SEVERITY__SHIFT                     0x1e
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                 0x00000010L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                              0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                 0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                  0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                             0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                           0x00008000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                               0x00010000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                0x00020000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                 0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                0x00080000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                          0x00100000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                           0x00200000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                          0x00400000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                          0x00800000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                 0x01000000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                  0x02000000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK             0x04000000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__DMWR_REQUEST_EGRESS_BLOCKED_SEVERITY_MASK             0x08000000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__IDE_CHECK_FAILED_SEVERITY_MASK                        0x10000000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__MISROUTED_IDE_TLP_SEVERITY_MASK                       0x20000000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_UNCORR_ERR_SEVERITY__PCRC_CHECK_FAILED_SEVERITY_MASK                       0x40000000L
+//BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                     0x6
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                    0x7
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                         0x8
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                        0xc
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                       0xd
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                0xe
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                                0xf
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                       0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                       0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                      0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                           0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                          0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                         0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                  0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                  0x00008000L
+//BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                         0x6
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                        0x7
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                             0x8
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                            0xc
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                           0xd
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                    0xe
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                    0xf
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                           0x00000001L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                           0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                          0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                               0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                              0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                             0x00002000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                      0x00004000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                      0x00008000L
+//BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT                                      0x5
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT                                       0x6
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                    0x7
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                0x9
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                 0xa
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                            0xb
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT                    0xc
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__HEADER_LOG_SIZE__SHIFT                                   0xd
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_WAS_FLIT_MODE__SHIFT                          0x12
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_SIZE__SHIFT                                   0x13
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                       0x0000001FL
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK                                        0x00000020L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK                                         0x00000040L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                      0x00000080L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                       0x00000100L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                  0x00000200L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                   0x00000400L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                              0x00000800L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK                      0x00001000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__HEADER_LOG_SIZE_MASK                                     0x0003E000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_WAS_FLIT_MODE_MASK                            0x00040000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_SIZE_MASK                                     0x00F80000L
+//BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG0__TLP_HDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG1__TLP_HDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG2__TLP_HDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG3__TLP_HDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG4
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG4__TLP_HDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG4__TLP_HDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                           0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG5
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG5__TLP_HDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG5__TLP_HDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                           0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG6
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG6__TLP_HDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG6__TLP_HDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                           0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG7
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG7__TLP_HDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG7__TLP_HDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                           0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG8
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG8__TLP_HDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG8__TLP_HDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG9
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG9__TLP_HDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG9__TLP_HDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG10
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG10__TLP_HDR__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG10__TLP_HDR_MASK                                                    0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG11
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG11__TLP_HDR__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG11__TLP_HDR_MASK                                                    0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG12
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG12__TLP_HDR__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG12__TLP_HDR_MASK                                                    0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG13
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG13__TLP_HDR__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_HDR_LOG13__TLP_HDR_MASK                                                    0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF0_VF7_PCIE_RTR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF7_RTR_DATA1
+#define BIF_CFG_DEV0_EPF0_VF7_RTR_DATA1__RESET_TIME__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF0_VF7_RTR_DATA1__DLUP_TIME__SHIFT                                                     0xc
+#define BIF_CFG_DEV0_EPF0_VF7_RTR_DATA1__RTR_VALID__SHIFT                                                     0x1f
+#define BIF_CFG_DEV0_EPF0_VF7_RTR_DATA1__RESET_TIME_MASK                                                      0x00000FFFL
+#define BIF_CFG_DEV0_EPF0_VF7_RTR_DATA1__DLUP_TIME_MASK                                                       0x00FFF000L
+#define BIF_CFG_DEV0_EPF0_VF7_RTR_DATA1__RTR_VALID_MASK                                                       0x80000000L
+//BIF_CFG_DEV0_EPF0_VF7_RTR_DATA2
+#define BIF_CFG_DEV0_EPF0_VF7_RTR_DATA2__FLR_TIME__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF0_VF7_RTR_DATA2__D3HOTD0_TIME__SHIFT                                                  0xc
+#define BIF_CFG_DEV0_EPF0_VF7_RTR_DATA2__FLR_TIME_MASK                                                        0x00000FFFL
+#define BIF_CFG_DEV0_EPF0_VF7_RTR_DATA2__D3HOTD0_TIME_MASK                                                    0x00FFF000L
+//BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                    0x1
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                          0x8
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                     0x0001L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                      0x0002L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                            0xFF00L
+//BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                    0x1
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                        0x4
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                     0x0001L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                      0x0002L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                          0x0070L
+//BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
+//BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST__SHIFT                                       0x5
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED__SHIFT                                0x6
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED__SHIFT                                 0x7
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP__TEE_EXCLUSIVE_ATTR_SUPPORTED__SHIFT                               0x9
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP__INVALIDATE_Q_DEPTH_MASK                                           0x001FL
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP__PAGE_ALIGNED_REQUEST_MASK                                         0x0020L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP__GLOBAL_INVALIDATE_SUPPORTED_MASK                                  0x0040L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP__RELAXED_ORDERING_SUPPORTED_MASK                                   0x0080L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CAP__TEE_EXCLUSIVE_ATTR_SUPPORTED_MASK                                 0x0200L
+//BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CNTL
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CNTL__STU__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CNTL__TEE_EXCLUSIVE_ATTR_ENABLE__SHIFT                                 0xa
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CNTL__ATC_ENABLE__SHIFT                                                0xf
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CNTL__STU_MASK                                                         0x001FL
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CNTL__TEE_EXCLUSIVE_ATTR_ENABLE_MASK                                   0x0400L
+#define BIF_CFG_DEV0_EPF0_VF7_PCIE_ATS_CNTL__ATC_ENABLE_MASK                                                  0x8000L
+
+
+// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf0_BIFPFVFDEC1
+//BIF_BX_DEV0_EPF0_VF0_0_BIF_BME_STATUS
+#define BIF_BX_DEV0_EPF0_VF0_0_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT                                          0x0
+#define BIF_BX_DEV0_EPF0_VF0_0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT                                    0x10
+#define BIF_BX_DEV0_EPF0_VF0_0_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK                                            0x00000001L
+#define BIF_BX_DEV0_EPF0_VF0_0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK                                      0x00010000L
+//BIF_BX_DEV0_EPF0_VF0_0_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_DEV0_EPF0_VF0_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT                                    0x0
+#define BIF_BX_DEV0_EPF0_VF0_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT                                 0x1
+#define BIF_BX_DEV0_EPF0_VF0_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT                                    0x2
+#define BIF_BX_DEV0_EPF0_VF0_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT                                        0x3
+#define BIF_BX_DEV0_EPF0_VF0_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT                              0x10
+#define BIF_BX_DEV0_EPF0_VF0_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT                           0x11
+#define BIF_BX_DEV0_EPF0_VF0_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT                              0x12
+#define BIF_BX_DEV0_EPF0_VF0_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT                                  0x13
+#define BIF_BX_DEV0_EPF0_VF0_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK                                      0x00000001L
+#define BIF_BX_DEV0_EPF0_VF0_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK                                   0x00000002L
+#define BIF_BX_DEV0_EPF0_VF0_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK                                      0x00000004L
+#define BIF_BX_DEV0_EPF0_VF0_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK                                          0x00000008L
+#define BIF_BX_DEV0_EPF0_VF0_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK                                0x00010000L
+#define BIF_BX_DEV0_EPF0_VF0_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK                             0x00020000L
+#define BIF_BX_DEV0_EPF0_VF0_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK                                0x00040000L
+#define BIF_BX_DEV0_EPF0_VF0_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK                                    0x00080000L
+//BIF_BX_DEV0_EPF0_VF0_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_DEV0_EPF0_VF0_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT  0x0
+#define BIF_BX_DEV0_EPF0_VF0_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK  0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF0_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_DEV0_EPF0_VF0_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT  0x0
+#define BIF_BX_DEV0_EPF0_VF0_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK  0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF0_0_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_DEV0_EPF0_VF0_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT          0x0
+#define BIF_BX_DEV0_EPF0_VF0_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT        0x1
+#define BIF_BX_DEV0_EPF0_VF0_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT        0x8
+#define BIF_BX_DEV0_EPF0_VF0_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK            0x00000001L
+#define BIF_BX_DEV0_EPF0_VF0_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK          0x00000002L
+#define BIF_BX_DEV0_EPF0_VF0_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK          0x000FFF00L
+//BIF_BX_DEV0_EPF0_VF0_0_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF0_0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT                        0x0
+#define BIF_BX_DEV0_EPF0_VF0_0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK                          0x00000001L
+//BIF_BX_DEV0_EPF0_VF0_0_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF0_0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT                        0x0
+#define BIF_BX_DEV0_EPF0_VF0_0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK                          0x00000001L
+//BIF_BX_DEV0_EPF0_VF0_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL
+#define BIF_BX_DEV0_EPF0_VF0_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT              0x0
+#define BIF_BX_DEV0_EPF0_VF0_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK                0x00000001L
+//BIF_BX_DEV0_EPF0_VF0_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL
+#define BIF_BX_DEV0_EPF0_VF0_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT    0x0
+#define BIF_BX_DEV0_EPF0_VF0_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK      0x00000001L
+//BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__CP0__SHIFT                                                  0x0
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__CP1__SHIFT                                                  0x1
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__CP2__SHIFT                                                  0x2
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__CP3__SHIFT                                                  0x3
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__CP4__SHIFT                                                  0x4
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__CP5__SHIFT                                                  0x5
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__CP6__SHIFT                                                  0x6
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__CP7__SHIFT                                                  0x7
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__CP8__SHIFT                                                  0x8
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__CP9__SHIFT                                                  0x9
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT                                                0xa
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT                                                0xb
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT                                            0xc
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT                                            0xd
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT                                            0xe
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT                                            0xf
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT                                            0x10
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT                                            0x11
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT                                            0x12
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT                                            0x13
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT                                            0x14
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT                                            0x15
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT                                           0x16
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT                                           0x17
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT                                           0x18
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT                                           0x19
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT                                           0x1a
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT                                           0x1b
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT                                           0x1c
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT                                           0x1d
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT                                           0x1e
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT                                           0x1f
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__CP0_MASK                                                    0x00000001L
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__CP1_MASK                                                    0x00000002L
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__CP2_MASK                                                    0x00000004L
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__CP3_MASK                                                    0x00000008L
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__CP4_MASK                                                    0x00000010L
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__CP5_MASK                                                    0x00000020L
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__CP6_MASK                                                    0x00000040L
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__CP7_MASK                                                    0x00000080L
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__CP8_MASK                                                    0x00000100L
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__CP9_MASK                                                    0x00000200L
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__SDMA0_MASK                                                  0x00000400L
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__SDMA1_MASK                                                  0x00000800L
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK                                              0x00001000L
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK                                              0x00002000L
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK                                              0x00004000L
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK                                              0x00008000L
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK                                              0x00010000L
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK                                              0x00020000L
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK                                              0x00040000L
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK                                              0x00080000L
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK                                              0x00100000L
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK                                              0x00200000L
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK                                             0x00400000L
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK                                             0x00800000L
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK                                             0x01000000L
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK                                             0x02000000L
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK                                             0x04000000L
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK                                             0x08000000L
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK                                             0x10000000L
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK                                             0x20000000L
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK                                             0x40000000L
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK                                             0x80000000L
+//BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__CP0__SHIFT                                                 0x0
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__CP1__SHIFT                                                 0x1
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__CP2__SHIFT                                                 0x2
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__CP3__SHIFT                                                 0x3
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__CP4__SHIFT                                                 0x4
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__CP5__SHIFT                                                 0x5
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__CP6__SHIFT                                                 0x6
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__CP7__SHIFT                                                 0x7
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__CP8__SHIFT                                                 0x8
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__CP9__SHIFT                                                 0x9
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT                                               0xa
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT                                               0xb
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT                                           0xc
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT                                           0xd
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT                                           0xe
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT                                           0xf
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT                                           0x10
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT                                           0x11
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT                                           0x12
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT                                           0x13
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT                                           0x14
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT                                           0x15
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT                                          0x16
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT                                          0x17
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT                                          0x18
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT                                          0x19
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT                                          0x1a
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT                                          0x1b
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT                                          0x1c
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT                                          0x1d
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT                                          0x1e
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT                                          0x1f
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__CP0_MASK                                                   0x00000001L
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__CP1_MASK                                                   0x00000002L
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__CP2_MASK                                                   0x00000004L
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__CP3_MASK                                                   0x00000008L
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__CP4_MASK                                                   0x00000010L
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__CP5_MASK                                                   0x00000020L
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__CP6_MASK                                                   0x00000040L
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__CP7_MASK                                                   0x00000080L
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__CP8_MASK                                                   0x00000100L
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__CP9_MASK                                                   0x00000200L
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__SDMA0_MASK                                                 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__SDMA1_MASK                                                 0x00000800L
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK                                             0x00001000L
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK                                             0x00002000L
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK                                             0x00004000L
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK                                             0x00008000L
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK                                             0x00010000L
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK                                             0x00020000L
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK                                             0x00040000L
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK                                             0x00080000L
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK                                             0x00100000L
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK                                             0x00200000L
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK                                            0x00400000L
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK                                            0x00800000L
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK                                            0x01000000L
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK                                            0x02000000L
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK                                            0x04000000L
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK                                            0x08000000L
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK                                            0x10000000L
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK                                            0x20000000L
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK                                            0x40000000L
+#define BIF_BX_DEV0_EPF0_VF0_0_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK                                            0x80000000L
+//BIF_BX_DEV0_EPF0_VF0_0_BIF_TRANS_PENDING
+#define BIF_BX_DEV0_EPF0_VF0_0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT                                0x0
+#define BIF_BX_DEV0_EPF0_VF0_0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT                                0x1
+#define BIF_BX_DEV0_EPF0_VF0_0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK                                  0x00000001L
+#define BIF_BX_DEV0_EPF0_VF0_0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK                                  0x00000002L
+//BIF_BX_DEV0_EPF0_VF0_0_NBIF_GFX_ADDR_LUT_BYPASS
+#define BIF_BX_DEV0_EPF0_VF0_0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT                                    0x0
+#define BIF_BX_DEV0_EPF0_VF0_0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK                                      0x00000001L
+//BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_CONTROL
+#define BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT                                          0x0
+#define BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT                                            0x1
+#define BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT                                          0x8
+#define BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT                                            0x9
+#define BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_CONTROL__TRN_MSG_VALID_MASK                                            0x00000001L
+#define BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_CONTROL__TRN_MSG_ACK_MASK                                              0x00000002L
+#define BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_CONTROL__RCV_MSG_VALID_MASK                                            0x00000100L
+#define BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_CONTROL__RCV_MSG_ACK_MASK                                              0x00000200L
+//BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_INT_CNTL
+#define BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT                                          0x0
+#define BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT                                            0x1
+#define BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_INT_CNTL__VALID_INT_EN_MASK                                            0x00000001L
+#define BIF_BX_DEV0_EPF0_VF0_0_MAILBOX_INT_CNTL__ACK_INT_EN_MASK                                              0x00000002L
+//BIF_BX_DEV0_EPF0_VF0_0_BIF_VMHV_MAILBOX
+#define BIF_BX_DEV0_EPF0_VF0_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT                          0x0
+#define BIF_BX_DEV0_EPF0_VF0_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT                        0x1
+#define BIF_BX_DEV0_EPF0_VF0_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT                             0x8
+#define BIF_BX_DEV0_EPF0_VF0_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT                            0xf
+#define BIF_BX_DEV0_EPF0_VF0_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT                             0x10
+#define BIF_BX_DEV0_EPF0_VF0_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT                            0x17
+#define BIF_BX_DEV0_EPF0_VF0_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT                              0x18
+#define BIF_BX_DEV0_EPF0_VF0_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT                              0x19
+#define BIF_BX_DEV0_EPF0_VF0_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK                            0x00000001L
+#define BIF_BX_DEV0_EPF0_VF0_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK                          0x00000002L
+#define BIF_BX_DEV0_EPF0_VF0_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK                               0x00000F00L
+#define BIF_BX_DEV0_EPF0_VF0_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK                              0x00008000L
+#define BIF_BX_DEV0_EPF0_VF0_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK                               0x000F0000L
+#define BIF_BX_DEV0_EPF0_VF0_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK                              0x00800000L
+#define BIF_BX_DEV0_EPF0_VF0_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK                                0x01000000L
+#define BIF_BX_DEV0_EPF0_VF0_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK                                0x02000000L
+//BIF_BX_DEV0_EPF0_VF0_0_PARTITION_COMPUTE_CAP
+#define BIF_BX_DEV0_EPF0_VF0_0_PARTITION_COMPUTE_CAP__SPX_SUPPORT__SHIFT                                      0x0
+#define BIF_BX_DEV0_EPF0_VF0_0_PARTITION_COMPUTE_CAP__DPX_SUPPORT__SHIFT                                      0x1
+#define BIF_BX_DEV0_EPF0_VF0_0_PARTITION_COMPUTE_CAP__TPX_SUPPORT__SHIFT                                      0x2
+#define BIF_BX_DEV0_EPF0_VF0_0_PARTITION_COMPUTE_CAP__QPX_SUPPORT__SHIFT                                      0x3
+#define BIF_BX_DEV0_EPF0_VF0_0_PARTITION_COMPUTE_CAP__CPX_SUPPORT__SHIFT                                      0x4
+#define BIF_BX_DEV0_EPF0_VF0_0_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY__SHIFT                                 0xa
+#define BIF_BX_DEV0_EPF0_VF0_0_PARTITION_COMPUTE_CAP__SPX_SUPPORT_MASK                                        0x00000001L
+#define BIF_BX_DEV0_EPF0_VF0_0_PARTITION_COMPUTE_CAP__DPX_SUPPORT_MASK                                        0x00000002L
+#define BIF_BX_DEV0_EPF0_VF0_0_PARTITION_COMPUTE_CAP__TPX_SUPPORT_MASK                                        0x00000004L
+#define BIF_BX_DEV0_EPF0_VF0_0_PARTITION_COMPUTE_CAP__QPX_SUPPORT_MASK                                        0x00000008L
+#define BIF_BX_DEV0_EPF0_VF0_0_PARTITION_COMPUTE_CAP__CPX_SUPPORT_MASK                                        0x00000010L
+#define BIF_BX_DEV0_EPF0_VF0_0_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY_MASK                                   0x0003FC00L
+//BIF_BX_DEV0_EPF0_VF0_0_PARTITION_MEM_CAP
+#define BIF_BX_DEV0_EPF0_VF0_0_PARTITION_MEM_CAP__NPS1_SUPPORT__SHIFT                                         0x0
+#define BIF_BX_DEV0_EPF0_VF0_0_PARTITION_MEM_CAP__NPS2_SUPPORT__SHIFT                                         0x1
+#define BIF_BX_DEV0_EPF0_VF0_0_PARTITION_MEM_CAP__NPS3_SUPPORT__SHIFT                                         0x2
+#define BIF_BX_DEV0_EPF0_VF0_0_PARTITION_MEM_CAP__NPS4_SUPPORT__SHIFT                                         0x3
+#define BIF_BX_DEV0_EPF0_VF0_0_PARTITION_MEM_CAP__NPS6_SUPPORT__SHIFT                                         0x5
+#define BIF_BX_DEV0_EPF0_VF0_0_PARTITION_MEM_CAP__NPS8_SUPPORT__SHIFT                                         0x7
+#define BIF_BX_DEV0_EPF0_VF0_0_PARTITION_MEM_CAP__NPS1_SUPPORT_MASK                                           0x00000001L
+#define BIF_BX_DEV0_EPF0_VF0_0_PARTITION_MEM_CAP__NPS2_SUPPORT_MASK                                           0x00000002L
+#define BIF_BX_DEV0_EPF0_VF0_0_PARTITION_MEM_CAP__NPS3_SUPPORT_MASK                                           0x00000004L
+#define BIF_BX_DEV0_EPF0_VF0_0_PARTITION_MEM_CAP__NPS4_SUPPORT_MASK                                           0x00000008L
+#define BIF_BX_DEV0_EPF0_VF0_0_PARTITION_MEM_CAP__NPS6_SUPPORT_MASK                                           0x00000020L
+#define BIF_BX_DEV0_EPF0_VF0_0_PARTITION_MEM_CAP__NPS8_SUPPORT_MASK                                           0x00000080L
+//BIF_BX_DEV0_EPF0_VF0_0_PARTITION_COMPUTE_STATUS
+#define BIF_BX_DEV0_EPF0_VF0_0_PARTITION_COMPUTE_STATUS__PARTITION_MODE__SHIFT                                0x4
+#define BIF_BX_DEV0_EPF0_VF0_0_PARTITION_COMPUTE_STATUS__PARTITION_MODE_MASK                                  0x000000F0L
+//BIF_BX_DEV0_EPF0_VF0_0_PARTITION_MEM_STATUS
+#define BIF_BX_DEV0_EPF0_VF0_0_PARTITION_MEM_STATUS__CHANGE_STATUS__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF0_0_PARTITION_MEM_STATUS__NPS_MODE__SHIFT                                          0x4
+#define BIF_BX_DEV0_EPF0_VF0_0_PARTITION_MEM_STATUS__CHANGE_STATUS_MASK                                       0x0000000FL
+#define BIF_BX_DEV0_EPF0_VF0_0_PARTITION_MEM_STATUS__NPS_MODE_MASK                                            0x00000FF0L
+
+
+// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf0_SYSPFVFDEC
+//BIF_BX_DEV0_EPF0_VF0_0_MM_INDEX
+#define BIF_BX_DEV0_EPF0_VF0_0_MM_INDEX__MM_OFFSET__SHIFT                                                     0x0
+#define BIF_BX_DEV0_EPF0_VF0_0_MM_INDEX__MM_APER__SHIFT                                                       0x1f
+#define BIF_BX_DEV0_EPF0_VF0_0_MM_INDEX__MM_OFFSET_MASK                                                       0x7FFFFFFFL
+#define BIF_BX_DEV0_EPF0_VF0_0_MM_INDEX__MM_APER_MASK                                                         0x80000000L
+//BIF_BX_DEV0_EPF0_VF0_0_MM_DATA
+#define BIF_BX_DEV0_EPF0_VF0_0_MM_DATA__MM_DATA__SHIFT                                                        0x0
+#define BIF_BX_DEV0_EPF0_VF0_0_MM_DATA__MM_DATA_MASK                                                          0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF0_0_MM_INDEX_HI
+#define BIF_BX_DEV0_EPF0_VF0_0_MM_INDEX_HI__MM_OFFSET_HI__SHIFT                                               0x0
+#define BIF_BX_DEV0_EPF0_VF0_0_MM_INDEX_HI__MM_OFFSET_HI_MASK                                                 0xFFFFFFFFL
+
+
+// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf0_BIFPFVFDEC1:1
+//BIF_BX_DEV0_EPF0_VF0_1_BIF_BME_STATUS
+#define BIF_BX_DEV0_EPF0_VF0_1_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT                                          0x0
+#define BIF_BX_DEV0_EPF0_VF0_1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT                                    0x10
+#define BIF_BX_DEV0_EPF0_VF0_1_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK                                            0x00000001L
+#define BIF_BX_DEV0_EPF0_VF0_1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK                                      0x00010000L
+//BIF_BX_DEV0_EPF0_VF0_1_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_DEV0_EPF0_VF0_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT                                    0x0
+#define BIF_BX_DEV0_EPF0_VF0_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT                                 0x1
+#define BIF_BX_DEV0_EPF0_VF0_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT                                    0x2
+#define BIF_BX_DEV0_EPF0_VF0_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT                                        0x3
+#define BIF_BX_DEV0_EPF0_VF0_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT                              0x10
+#define BIF_BX_DEV0_EPF0_VF0_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT                           0x11
+#define BIF_BX_DEV0_EPF0_VF0_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT                              0x12
+#define BIF_BX_DEV0_EPF0_VF0_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT                                  0x13
+#define BIF_BX_DEV0_EPF0_VF0_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK                                      0x00000001L
+#define BIF_BX_DEV0_EPF0_VF0_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK                                   0x00000002L
+#define BIF_BX_DEV0_EPF0_VF0_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK                                      0x00000004L
+#define BIF_BX_DEV0_EPF0_VF0_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK                                          0x00000008L
+#define BIF_BX_DEV0_EPF0_VF0_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK                                0x00010000L
+#define BIF_BX_DEV0_EPF0_VF0_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK                             0x00020000L
+#define BIF_BX_DEV0_EPF0_VF0_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK                                0x00040000L
+#define BIF_BX_DEV0_EPF0_VF0_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK                                    0x00080000L
+//BIF_BX_DEV0_EPF0_VF0_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_DEV0_EPF0_VF0_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT  0x0
+#define BIF_BX_DEV0_EPF0_VF0_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK  0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF0_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_DEV0_EPF0_VF0_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT  0x0
+#define BIF_BX_DEV0_EPF0_VF0_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK  0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF0_1_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_DEV0_EPF0_VF0_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT          0x0
+#define BIF_BX_DEV0_EPF0_VF0_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT        0x1
+#define BIF_BX_DEV0_EPF0_VF0_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT        0x8
+#define BIF_BX_DEV0_EPF0_VF0_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK            0x00000001L
+#define BIF_BX_DEV0_EPF0_VF0_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK          0x00000002L
+#define BIF_BX_DEV0_EPF0_VF0_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK          0x000FFF00L
+//BIF_BX_DEV0_EPF0_VF0_1_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF0_1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT                        0x0
+#define BIF_BX_DEV0_EPF0_VF0_1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK                          0x00000001L
+//BIF_BX_DEV0_EPF0_VF0_1_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF0_1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT                        0x0
+#define BIF_BX_DEV0_EPF0_VF0_1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK                          0x00000001L
+//BIF_BX_DEV0_EPF0_VF0_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL
+#define BIF_BX_DEV0_EPF0_VF0_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT              0x0
+#define BIF_BX_DEV0_EPF0_VF0_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK                0x00000001L
+//BIF_BX_DEV0_EPF0_VF0_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL
+#define BIF_BX_DEV0_EPF0_VF0_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT    0x0
+#define BIF_BX_DEV0_EPF0_VF0_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK      0x00000001L
+//BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__CP0__SHIFT                                                  0x0
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__CP1__SHIFT                                                  0x1
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__CP2__SHIFT                                                  0x2
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__CP3__SHIFT                                                  0x3
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__CP4__SHIFT                                                  0x4
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__CP5__SHIFT                                                  0x5
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__CP6__SHIFT                                                  0x6
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__CP7__SHIFT                                                  0x7
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__CP8__SHIFT                                                  0x8
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__CP9__SHIFT                                                  0x9
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT                                                0xa
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT                                                0xb
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT                                            0xc
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT                                            0xd
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT                                            0xe
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT                                            0xf
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT                                            0x10
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT                                            0x11
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT                                            0x12
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT                                            0x13
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT                                            0x14
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT                                            0x15
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT                                           0x16
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT                                           0x17
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT                                           0x18
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT                                           0x19
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT                                           0x1a
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT                                           0x1b
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT                                           0x1c
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT                                           0x1d
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT                                           0x1e
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT                                           0x1f
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__CP0_MASK                                                    0x00000001L
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__CP1_MASK                                                    0x00000002L
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__CP2_MASK                                                    0x00000004L
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__CP3_MASK                                                    0x00000008L
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__CP4_MASK                                                    0x00000010L
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__CP5_MASK                                                    0x00000020L
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__CP6_MASK                                                    0x00000040L
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__CP7_MASK                                                    0x00000080L
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__CP8_MASK                                                    0x00000100L
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__CP9_MASK                                                    0x00000200L
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__SDMA0_MASK                                                  0x00000400L
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__SDMA1_MASK                                                  0x00000800L
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK                                              0x00001000L
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK                                              0x00002000L
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK                                              0x00004000L
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK                                              0x00008000L
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK                                              0x00010000L
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK                                              0x00020000L
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK                                              0x00040000L
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK                                              0x00080000L
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK                                              0x00100000L
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK                                              0x00200000L
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK                                             0x00400000L
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK                                             0x00800000L
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK                                             0x01000000L
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK                                             0x02000000L
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK                                             0x04000000L
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK                                             0x08000000L
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK                                             0x10000000L
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK                                             0x20000000L
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK                                             0x40000000L
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK                                             0x80000000L
+//BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__CP0__SHIFT                                                 0x0
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__CP1__SHIFT                                                 0x1
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__CP2__SHIFT                                                 0x2
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__CP3__SHIFT                                                 0x3
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__CP4__SHIFT                                                 0x4
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__CP5__SHIFT                                                 0x5
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__CP6__SHIFT                                                 0x6
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__CP7__SHIFT                                                 0x7
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__CP8__SHIFT                                                 0x8
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__CP9__SHIFT                                                 0x9
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT                                               0xa
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT                                               0xb
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT                                           0xc
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT                                           0xd
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT                                           0xe
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT                                           0xf
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT                                           0x10
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT                                           0x11
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT                                           0x12
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT                                           0x13
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT                                           0x14
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT                                           0x15
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT                                          0x16
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT                                          0x17
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT                                          0x18
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT                                          0x19
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT                                          0x1a
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT                                          0x1b
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT                                          0x1c
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT                                          0x1d
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT                                          0x1e
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT                                          0x1f
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__CP0_MASK                                                   0x00000001L
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__CP1_MASK                                                   0x00000002L
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__CP2_MASK                                                   0x00000004L
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__CP3_MASK                                                   0x00000008L
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__CP4_MASK                                                   0x00000010L
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__CP5_MASK                                                   0x00000020L
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__CP6_MASK                                                   0x00000040L
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__CP7_MASK                                                   0x00000080L
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__CP8_MASK                                                   0x00000100L
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__CP9_MASK                                                   0x00000200L
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__SDMA0_MASK                                                 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__SDMA1_MASK                                                 0x00000800L
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK                                             0x00001000L
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK                                             0x00002000L
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK                                             0x00004000L
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK                                             0x00008000L
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK                                             0x00010000L
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK                                             0x00020000L
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK                                             0x00040000L
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK                                             0x00080000L
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK                                             0x00100000L
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK                                             0x00200000L
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK                                            0x00400000L
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK                                            0x00800000L
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK                                            0x01000000L
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK                                            0x02000000L
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK                                            0x04000000L
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK                                            0x08000000L
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK                                            0x10000000L
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK                                            0x20000000L
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK                                            0x40000000L
+#define BIF_BX_DEV0_EPF0_VF0_1_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK                                            0x80000000L
+//BIF_BX_DEV0_EPF0_VF0_1_BIF_TRANS_PENDING
+#define BIF_BX_DEV0_EPF0_VF0_1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT                                0x0
+#define BIF_BX_DEV0_EPF0_VF0_1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT                                0x1
+#define BIF_BX_DEV0_EPF0_VF0_1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK                                  0x00000001L
+#define BIF_BX_DEV0_EPF0_VF0_1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK                                  0x00000002L
+//BIF_BX_DEV0_EPF0_VF0_1_NBIF_GFX_ADDR_LUT_BYPASS
+#define BIF_BX_DEV0_EPF0_VF0_1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT                                    0x0
+#define BIF_BX_DEV0_EPF0_VF0_1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK                                      0x00000001L
+//BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_CONTROL
+#define BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT                                          0x0
+#define BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT                                            0x1
+#define BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT                                          0x8
+#define BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT                                            0x9
+#define BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_CONTROL__TRN_MSG_VALID_MASK                                            0x00000001L
+#define BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_CONTROL__TRN_MSG_ACK_MASK                                              0x00000002L
+#define BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_CONTROL__RCV_MSG_VALID_MASK                                            0x00000100L
+#define BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_CONTROL__RCV_MSG_ACK_MASK                                              0x00000200L
+//BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_INT_CNTL
+#define BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT                                          0x0
+#define BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT                                            0x1
+#define BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_INT_CNTL__VALID_INT_EN_MASK                                            0x00000001L
+#define BIF_BX_DEV0_EPF0_VF0_1_MAILBOX_INT_CNTL__ACK_INT_EN_MASK                                              0x00000002L
+//BIF_BX_DEV0_EPF0_VF0_1_BIF_VMHV_MAILBOX
+#define BIF_BX_DEV0_EPF0_VF0_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT                          0x0
+#define BIF_BX_DEV0_EPF0_VF0_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT                        0x1
+#define BIF_BX_DEV0_EPF0_VF0_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT                             0x8
+#define BIF_BX_DEV0_EPF0_VF0_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT                            0xf
+#define BIF_BX_DEV0_EPF0_VF0_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT                             0x10
+#define BIF_BX_DEV0_EPF0_VF0_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT                            0x17
+#define BIF_BX_DEV0_EPF0_VF0_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT                              0x18
+#define BIF_BX_DEV0_EPF0_VF0_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT                              0x19
+#define BIF_BX_DEV0_EPF0_VF0_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK                            0x00000001L
+#define BIF_BX_DEV0_EPF0_VF0_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK                          0x00000002L
+#define BIF_BX_DEV0_EPF0_VF0_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK                               0x00000F00L
+#define BIF_BX_DEV0_EPF0_VF0_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK                              0x00008000L
+#define BIF_BX_DEV0_EPF0_VF0_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK                               0x000F0000L
+#define BIF_BX_DEV0_EPF0_VF0_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK                              0x00800000L
+#define BIF_BX_DEV0_EPF0_VF0_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK                                0x01000000L
+#define BIF_BX_DEV0_EPF0_VF0_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK                                0x02000000L
+//BIF_BX_DEV0_EPF0_VF0_1_PARTITION_COMPUTE_CAP
+#define BIF_BX_DEV0_EPF0_VF0_1_PARTITION_COMPUTE_CAP__SPX_SUPPORT__SHIFT                                      0x0
+#define BIF_BX_DEV0_EPF0_VF0_1_PARTITION_COMPUTE_CAP__DPX_SUPPORT__SHIFT                                      0x1
+#define BIF_BX_DEV0_EPF0_VF0_1_PARTITION_COMPUTE_CAP__TPX_SUPPORT__SHIFT                                      0x2
+#define BIF_BX_DEV0_EPF0_VF0_1_PARTITION_COMPUTE_CAP__QPX_SUPPORT__SHIFT                                      0x3
+#define BIF_BX_DEV0_EPF0_VF0_1_PARTITION_COMPUTE_CAP__CPX_SUPPORT__SHIFT                                      0x4
+#define BIF_BX_DEV0_EPF0_VF0_1_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY__SHIFT                                 0xa
+#define BIF_BX_DEV0_EPF0_VF0_1_PARTITION_COMPUTE_CAP__SPX_SUPPORT_MASK                                        0x00000001L
+#define BIF_BX_DEV0_EPF0_VF0_1_PARTITION_COMPUTE_CAP__DPX_SUPPORT_MASK                                        0x00000002L
+#define BIF_BX_DEV0_EPF0_VF0_1_PARTITION_COMPUTE_CAP__TPX_SUPPORT_MASK                                        0x00000004L
+#define BIF_BX_DEV0_EPF0_VF0_1_PARTITION_COMPUTE_CAP__QPX_SUPPORT_MASK                                        0x00000008L
+#define BIF_BX_DEV0_EPF0_VF0_1_PARTITION_COMPUTE_CAP__CPX_SUPPORT_MASK                                        0x00000010L
+#define BIF_BX_DEV0_EPF0_VF0_1_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY_MASK                                   0x0003FC00L
+//BIF_BX_DEV0_EPF0_VF0_1_PARTITION_MEM_CAP
+#define BIF_BX_DEV0_EPF0_VF0_1_PARTITION_MEM_CAP__NPS1_SUPPORT__SHIFT                                         0x0
+#define BIF_BX_DEV0_EPF0_VF0_1_PARTITION_MEM_CAP__NPS2_SUPPORT__SHIFT                                         0x1
+#define BIF_BX_DEV0_EPF0_VF0_1_PARTITION_MEM_CAP__NPS3_SUPPORT__SHIFT                                         0x2
+#define BIF_BX_DEV0_EPF0_VF0_1_PARTITION_MEM_CAP__NPS4_SUPPORT__SHIFT                                         0x3
+#define BIF_BX_DEV0_EPF0_VF0_1_PARTITION_MEM_CAP__NPS6_SUPPORT__SHIFT                                         0x5
+#define BIF_BX_DEV0_EPF0_VF0_1_PARTITION_MEM_CAP__NPS8_SUPPORT__SHIFT                                         0x7
+#define BIF_BX_DEV0_EPF0_VF0_1_PARTITION_MEM_CAP__NPS1_SUPPORT_MASK                                           0x00000001L
+#define BIF_BX_DEV0_EPF0_VF0_1_PARTITION_MEM_CAP__NPS2_SUPPORT_MASK                                           0x00000002L
+#define BIF_BX_DEV0_EPF0_VF0_1_PARTITION_MEM_CAP__NPS3_SUPPORT_MASK                                           0x00000004L
+#define BIF_BX_DEV0_EPF0_VF0_1_PARTITION_MEM_CAP__NPS4_SUPPORT_MASK                                           0x00000008L
+#define BIF_BX_DEV0_EPF0_VF0_1_PARTITION_MEM_CAP__NPS6_SUPPORT_MASK                                           0x00000020L
+#define BIF_BX_DEV0_EPF0_VF0_1_PARTITION_MEM_CAP__NPS8_SUPPORT_MASK                                           0x00000080L
+//BIF_BX_DEV0_EPF0_VF0_1_PARTITION_COMPUTE_STATUS
+#define BIF_BX_DEV0_EPF0_VF0_1_PARTITION_COMPUTE_STATUS__PARTITION_MODE__SHIFT                                0x4
+#define BIF_BX_DEV0_EPF0_VF0_1_PARTITION_COMPUTE_STATUS__PARTITION_MODE_MASK                                  0x000000F0L
+//BIF_BX_DEV0_EPF0_VF0_1_PARTITION_MEM_STATUS
+#define BIF_BX_DEV0_EPF0_VF0_1_PARTITION_MEM_STATUS__CHANGE_STATUS__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF0_1_PARTITION_MEM_STATUS__NPS_MODE__SHIFT                                          0x4
+#define BIF_BX_DEV0_EPF0_VF0_1_PARTITION_MEM_STATUS__CHANGE_STATUS_MASK                                       0x0000000FL
+#define BIF_BX_DEV0_EPF0_VF0_1_PARTITION_MEM_STATUS__NPS_MODE_MASK                                            0x00000FF0L
+
+
+// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf0_SYSPFVFDEC:1
+//BIF_BX_DEV0_EPF0_VF0_1_MM_INDEX
+#define BIF_BX_DEV0_EPF0_VF0_1_MM_INDEX__MM_OFFSET__SHIFT                                                     0x0
+#define BIF_BX_DEV0_EPF0_VF0_1_MM_INDEX__MM_APER__SHIFT                                                       0x1f
+#define BIF_BX_DEV0_EPF0_VF0_1_MM_INDEX__MM_OFFSET_MASK                                                       0x7FFFFFFFL
+#define BIF_BX_DEV0_EPF0_VF0_1_MM_INDEX__MM_APER_MASK                                                         0x80000000L
+//BIF_BX_DEV0_EPF0_VF0_1_MM_DATA
+#define BIF_BX_DEV0_EPF0_VF0_1_MM_DATA__MM_DATA__SHIFT                                                        0x0
+#define BIF_BX_DEV0_EPF0_VF0_1_MM_DATA__MM_DATA_MASK                                                          0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF0_1_MM_INDEX_HI
+#define BIF_BX_DEV0_EPF0_VF0_1_MM_INDEX_HI__MM_OFFSET_HI__SHIFT                                               0x0
+#define BIF_BX_DEV0_EPF0_VF0_1_MM_INDEX_HI__MM_OFFSET_HI_MASK                                                 0xFFFFFFFFL
+
+
+// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf0_BIFPFVFDEC1
+//RCC_DEV0_EPF0_VF0_RCC_ERR_LOG
+#define RCC_DEV0_EPF0_VF0_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT                              0x0
+#define RCC_DEV0_EPF0_VF0_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT                                     0x1
+#define RCC_DEV0_EPF0_VF0_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK                                0x00000001L
+#define RCC_DEV0_EPF0_VF0_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK                                       0x00000002L
+//RCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN
+#define RCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT                                   0x0
+#define RCC_DEV0_EPF0_VF0_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK                                     0x00000001L
+//RCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE
+#define RCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_VF0_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED
+#define RCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT                                         0x0
+#define RCC_DEV0_EPF0_VF0_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK                                           0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER
+#define RCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT                                     0x0
+#define RCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT                                          0x1f
+#define RCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK                                       0x00000001L
+#define RCC_DEV0_EPF0_VF0_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK                                            0x80000000L
+
+
+// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf0_BIFDEC2
+//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT                                           0x2
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT                                              0x0
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK                                                0x00000001L
+//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT                                           0x2
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT                                              0x0
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK                                                0x00000001L
+//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT                                           0x2
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT                                              0x0
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK                                                0x00000001L
+//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_LO
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT                                           0x2
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_HI
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_MSG_DATA
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_CONTROL
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT                                              0x0
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK                                                0x00000001L
+//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT4_ADDR_LO
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT4_ADDR_LO__MSG_ADDR_LO__SHIFT                                           0x2
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT4_ADDR_LO__MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT4_ADDR_HI
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT4_ADDR_HI__MSG_ADDR_HI__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT4_ADDR_HI__MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT4_MSG_DATA
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT4_MSG_DATA__MSG_DATA__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT4_MSG_DATA__MSG_DATA_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT4_CONTROL
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT4_CONTROL__MASK_BIT__SHIFT                                              0x0
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT4_CONTROL__MASK_BIT_MASK                                                0x00000001L
+//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT5_ADDR_LO
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT5_ADDR_LO__MSG_ADDR_LO__SHIFT                                           0x2
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT5_ADDR_LO__MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT5_ADDR_HI
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT5_ADDR_HI__MSG_ADDR_HI__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT5_ADDR_HI__MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT5_MSG_DATA
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT5_MSG_DATA__MSG_DATA__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT5_MSG_DATA__MSG_DATA_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT5_CONTROL
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT5_CONTROL__MASK_BIT__SHIFT                                              0x0
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT5_CONTROL__MASK_BIT_MASK                                                0x00000001L
+//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT6_ADDR_LO
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT6_ADDR_LO__MSG_ADDR_LO__SHIFT                                           0x2
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT6_ADDR_LO__MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT6_ADDR_HI
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT6_ADDR_HI__MSG_ADDR_HI__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT6_ADDR_HI__MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT6_MSG_DATA
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT6_MSG_DATA__MSG_DATA__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT6_MSG_DATA__MSG_DATA_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT6_CONTROL
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT6_CONTROL__MASK_BIT__SHIFT                                              0x0
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT6_CONTROL__MASK_BIT_MASK                                                0x00000001L
+//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT7_ADDR_LO
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT7_ADDR_LO__MSG_ADDR_LO__SHIFT                                           0x2
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT7_ADDR_LO__MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT7_ADDR_HI
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT7_ADDR_HI__MSG_ADDR_HI__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT7_ADDR_HI__MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT7_MSG_DATA
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT7_MSG_DATA__MSG_DATA__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT7_MSG_DATA__MSG_DATA_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT7_CONTROL
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT7_CONTROL__MASK_BIT__SHIFT                                              0x0
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT7_CONTROL__MASK_BIT_MASK                                                0x00000001L
+//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT8_ADDR_LO
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT8_ADDR_LO__MSG_ADDR_LO__SHIFT                                           0x2
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT8_ADDR_LO__MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT8_ADDR_HI
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT8_ADDR_HI__MSG_ADDR_HI__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT8_ADDR_HI__MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT8_MSG_DATA
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT8_MSG_DATA__MSG_DATA__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT8_MSG_DATA__MSG_DATA_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF0_GFXMSIX_VECT8_CONTROL
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT8_CONTROL__MASK_BIT__SHIFT                                              0x0
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_VECT8_CONTROL__MASK_BIT_MASK                                                0x00000001L
+//RCC_DEV0_EPF0_VF0_GFXMSIX_PBA
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT                                             0x1
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK                                               0x00000001L
+#define RCC_DEV0_EPF0_VF0_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK                                               0x00000002L
+
+
+// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf1_BIFPFVFDEC1
+//BIF_BX_DEV0_EPF0_VF1_0_BIF_BME_STATUS
+#define BIF_BX_DEV0_EPF0_VF1_0_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT                                          0x0
+#define BIF_BX_DEV0_EPF0_VF1_0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT                                    0x10
+#define BIF_BX_DEV0_EPF0_VF1_0_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK                                            0x00000001L
+#define BIF_BX_DEV0_EPF0_VF1_0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK                                      0x00010000L
+//BIF_BX_DEV0_EPF0_VF1_0_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_DEV0_EPF0_VF1_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT                                    0x0
+#define BIF_BX_DEV0_EPF0_VF1_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT                                 0x1
+#define BIF_BX_DEV0_EPF0_VF1_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT                                    0x2
+#define BIF_BX_DEV0_EPF0_VF1_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT                                        0x3
+#define BIF_BX_DEV0_EPF0_VF1_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT                              0x10
+#define BIF_BX_DEV0_EPF0_VF1_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT                           0x11
+#define BIF_BX_DEV0_EPF0_VF1_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT                              0x12
+#define BIF_BX_DEV0_EPF0_VF1_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT                                  0x13
+#define BIF_BX_DEV0_EPF0_VF1_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK                                      0x00000001L
+#define BIF_BX_DEV0_EPF0_VF1_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK                                   0x00000002L
+#define BIF_BX_DEV0_EPF0_VF1_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK                                      0x00000004L
+#define BIF_BX_DEV0_EPF0_VF1_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK                                          0x00000008L
+#define BIF_BX_DEV0_EPF0_VF1_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK                                0x00010000L
+#define BIF_BX_DEV0_EPF0_VF1_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK                             0x00020000L
+#define BIF_BX_DEV0_EPF0_VF1_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK                                0x00040000L
+#define BIF_BX_DEV0_EPF0_VF1_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK                                    0x00080000L
+//BIF_BX_DEV0_EPF0_VF1_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_DEV0_EPF0_VF1_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT  0x0
+#define BIF_BX_DEV0_EPF0_VF1_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK  0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF1_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_DEV0_EPF0_VF1_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT  0x0
+#define BIF_BX_DEV0_EPF0_VF1_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK  0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF1_0_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_DEV0_EPF0_VF1_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT          0x0
+#define BIF_BX_DEV0_EPF0_VF1_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT        0x1
+#define BIF_BX_DEV0_EPF0_VF1_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT        0x8
+#define BIF_BX_DEV0_EPF0_VF1_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK            0x00000001L
+#define BIF_BX_DEV0_EPF0_VF1_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK          0x00000002L
+#define BIF_BX_DEV0_EPF0_VF1_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK          0x000FFF00L
+//BIF_BX_DEV0_EPF0_VF1_0_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF1_0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT                        0x0
+#define BIF_BX_DEV0_EPF0_VF1_0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK                          0x00000001L
+//BIF_BX_DEV0_EPF0_VF1_0_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF1_0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT                        0x0
+#define BIF_BX_DEV0_EPF0_VF1_0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK                          0x00000001L
+//BIF_BX_DEV0_EPF0_VF1_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL
+#define BIF_BX_DEV0_EPF0_VF1_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT              0x0
+#define BIF_BX_DEV0_EPF0_VF1_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK                0x00000001L
+//BIF_BX_DEV0_EPF0_VF1_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL
+#define BIF_BX_DEV0_EPF0_VF1_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT    0x0
+#define BIF_BX_DEV0_EPF0_VF1_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK      0x00000001L
+//BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__CP0__SHIFT                                                  0x0
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__CP1__SHIFT                                                  0x1
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__CP2__SHIFT                                                  0x2
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__CP3__SHIFT                                                  0x3
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__CP4__SHIFT                                                  0x4
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__CP5__SHIFT                                                  0x5
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__CP6__SHIFT                                                  0x6
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__CP7__SHIFT                                                  0x7
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__CP8__SHIFT                                                  0x8
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__CP9__SHIFT                                                  0x9
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT                                                0xa
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT                                                0xb
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT                                            0xc
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT                                            0xd
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT                                            0xe
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT                                            0xf
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT                                            0x10
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT                                            0x11
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT                                            0x12
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT                                            0x13
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT                                            0x14
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT                                            0x15
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT                                           0x16
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT                                           0x17
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT                                           0x18
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT                                           0x19
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT                                           0x1a
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT                                           0x1b
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT                                           0x1c
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT                                           0x1d
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT                                           0x1e
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT                                           0x1f
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__CP0_MASK                                                    0x00000001L
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__CP1_MASK                                                    0x00000002L
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__CP2_MASK                                                    0x00000004L
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__CP3_MASK                                                    0x00000008L
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__CP4_MASK                                                    0x00000010L
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__CP5_MASK                                                    0x00000020L
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__CP6_MASK                                                    0x00000040L
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__CP7_MASK                                                    0x00000080L
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__CP8_MASK                                                    0x00000100L
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__CP9_MASK                                                    0x00000200L
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__SDMA0_MASK                                                  0x00000400L
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__SDMA1_MASK                                                  0x00000800L
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK                                              0x00001000L
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK                                              0x00002000L
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK                                              0x00004000L
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK                                              0x00008000L
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK                                              0x00010000L
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK                                              0x00020000L
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK                                              0x00040000L
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK                                              0x00080000L
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK                                              0x00100000L
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK                                              0x00200000L
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK                                             0x00400000L
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK                                             0x00800000L
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK                                             0x01000000L
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK                                             0x02000000L
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK                                             0x04000000L
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK                                             0x08000000L
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK                                             0x10000000L
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK                                             0x20000000L
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK                                             0x40000000L
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK                                             0x80000000L
+//BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__CP0__SHIFT                                                 0x0
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__CP1__SHIFT                                                 0x1
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__CP2__SHIFT                                                 0x2
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__CP3__SHIFT                                                 0x3
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__CP4__SHIFT                                                 0x4
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__CP5__SHIFT                                                 0x5
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__CP6__SHIFT                                                 0x6
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__CP7__SHIFT                                                 0x7
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__CP8__SHIFT                                                 0x8
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__CP9__SHIFT                                                 0x9
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT                                               0xa
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT                                               0xb
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT                                           0xc
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT                                           0xd
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT                                           0xe
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT                                           0xf
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT                                           0x10
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT                                           0x11
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT                                           0x12
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT                                           0x13
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT                                           0x14
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT                                           0x15
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT                                          0x16
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT                                          0x17
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT                                          0x18
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT                                          0x19
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT                                          0x1a
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT                                          0x1b
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT                                          0x1c
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT                                          0x1d
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT                                          0x1e
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT                                          0x1f
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__CP0_MASK                                                   0x00000001L
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__CP1_MASK                                                   0x00000002L
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__CP2_MASK                                                   0x00000004L
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__CP3_MASK                                                   0x00000008L
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__CP4_MASK                                                   0x00000010L
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__CP5_MASK                                                   0x00000020L
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__CP6_MASK                                                   0x00000040L
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__CP7_MASK                                                   0x00000080L
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__CP8_MASK                                                   0x00000100L
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__CP9_MASK                                                   0x00000200L
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__SDMA0_MASK                                                 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__SDMA1_MASK                                                 0x00000800L
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK                                             0x00001000L
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK                                             0x00002000L
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK                                             0x00004000L
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK                                             0x00008000L
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK                                             0x00010000L
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK                                             0x00020000L
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK                                             0x00040000L
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK                                             0x00080000L
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK                                             0x00100000L
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK                                             0x00200000L
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK                                            0x00400000L
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK                                            0x00800000L
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK                                            0x01000000L
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK                                            0x02000000L
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK                                            0x04000000L
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK                                            0x08000000L
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK                                            0x10000000L
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK                                            0x20000000L
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK                                            0x40000000L
+#define BIF_BX_DEV0_EPF0_VF1_0_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK                                            0x80000000L
+//BIF_BX_DEV0_EPF0_VF1_0_BIF_TRANS_PENDING
+#define BIF_BX_DEV0_EPF0_VF1_0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT                                0x0
+#define BIF_BX_DEV0_EPF0_VF1_0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT                                0x1
+#define BIF_BX_DEV0_EPF0_VF1_0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK                                  0x00000001L
+#define BIF_BX_DEV0_EPF0_VF1_0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK                                  0x00000002L
+//BIF_BX_DEV0_EPF0_VF1_0_NBIF_GFX_ADDR_LUT_BYPASS
+#define BIF_BX_DEV0_EPF0_VF1_0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT                                    0x0
+#define BIF_BX_DEV0_EPF0_VF1_0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK                                      0x00000001L
+//BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_CONTROL
+#define BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT                                          0x0
+#define BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT                                            0x1
+#define BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT                                          0x8
+#define BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT                                            0x9
+#define BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_CONTROL__TRN_MSG_VALID_MASK                                            0x00000001L
+#define BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_CONTROL__TRN_MSG_ACK_MASK                                              0x00000002L
+#define BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_CONTROL__RCV_MSG_VALID_MASK                                            0x00000100L
+#define BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_CONTROL__RCV_MSG_ACK_MASK                                              0x00000200L
+//BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_INT_CNTL
+#define BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT                                          0x0
+#define BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT                                            0x1
+#define BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_INT_CNTL__VALID_INT_EN_MASK                                            0x00000001L
+#define BIF_BX_DEV0_EPF0_VF1_0_MAILBOX_INT_CNTL__ACK_INT_EN_MASK                                              0x00000002L
+//BIF_BX_DEV0_EPF0_VF1_0_BIF_VMHV_MAILBOX
+#define BIF_BX_DEV0_EPF0_VF1_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT                          0x0
+#define BIF_BX_DEV0_EPF0_VF1_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT                        0x1
+#define BIF_BX_DEV0_EPF0_VF1_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT                             0x8
+#define BIF_BX_DEV0_EPF0_VF1_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT                            0xf
+#define BIF_BX_DEV0_EPF0_VF1_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT                             0x10
+#define BIF_BX_DEV0_EPF0_VF1_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT                            0x17
+#define BIF_BX_DEV0_EPF0_VF1_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT                              0x18
+#define BIF_BX_DEV0_EPF0_VF1_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT                              0x19
+#define BIF_BX_DEV0_EPF0_VF1_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK                            0x00000001L
+#define BIF_BX_DEV0_EPF0_VF1_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK                          0x00000002L
+#define BIF_BX_DEV0_EPF0_VF1_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK                               0x00000F00L
+#define BIF_BX_DEV0_EPF0_VF1_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK                              0x00008000L
+#define BIF_BX_DEV0_EPF0_VF1_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK                               0x000F0000L
+#define BIF_BX_DEV0_EPF0_VF1_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK                              0x00800000L
+#define BIF_BX_DEV0_EPF0_VF1_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK                                0x01000000L
+#define BIF_BX_DEV0_EPF0_VF1_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK                                0x02000000L
+//BIF_BX_DEV0_EPF0_VF1_0_PARTITION_COMPUTE_CAP
+#define BIF_BX_DEV0_EPF0_VF1_0_PARTITION_COMPUTE_CAP__SPX_SUPPORT__SHIFT                                      0x0
+#define BIF_BX_DEV0_EPF0_VF1_0_PARTITION_COMPUTE_CAP__DPX_SUPPORT__SHIFT                                      0x1
+#define BIF_BX_DEV0_EPF0_VF1_0_PARTITION_COMPUTE_CAP__TPX_SUPPORT__SHIFT                                      0x2
+#define BIF_BX_DEV0_EPF0_VF1_0_PARTITION_COMPUTE_CAP__QPX_SUPPORT__SHIFT                                      0x3
+#define BIF_BX_DEV0_EPF0_VF1_0_PARTITION_COMPUTE_CAP__CPX_SUPPORT__SHIFT                                      0x4
+#define BIF_BX_DEV0_EPF0_VF1_0_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY__SHIFT                                 0xa
+#define BIF_BX_DEV0_EPF0_VF1_0_PARTITION_COMPUTE_CAP__SPX_SUPPORT_MASK                                        0x00000001L
+#define BIF_BX_DEV0_EPF0_VF1_0_PARTITION_COMPUTE_CAP__DPX_SUPPORT_MASK                                        0x00000002L
+#define BIF_BX_DEV0_EPF0_VF1_0_PARTITION_COMPUTE_CAP__TPX_SUPPORT_MASK                                        0x00000004L
+#define BIF_BX_DEV0_EPF0_VF1_0_PARTITION_COMPUTE_CAP__QPX_SUPPORT_MASK                                        0x00000008L
+#define BIF_BX_DEV0_EPF0_VF1_0_PARTITION_COMPUTE_CAP__CPX_SUPPORT_MASK                                        0x00000010L
+#define BIF_BX_DEV0_EPF0_VF1_0_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY_MASK                                   0x0003FC00L
+//BIF_BX_DEV0_EPF0_VF1_0_PARTITION_MEM_CAP
+#define BIF_BX_DEV0_EPF0_VF1_0_PARTITION_MEM_CAP__NPS1_SUPPORT__SHIFT                                         0x0
+#define BIF_BX_DEV0_EPF0_VF1_0_PARTITION_MEM_CAP__NPS2_SUPPORT__SHIFT                                         0x1
+#define BIF_BX_DEV0_EPF0_VF1_0_PARTITION_MEM_CAP__NPS3_SUPPORT__SHIFT                                         0x2
+#define BIF_BX_DEV0_EPF0_VF1_0_PARTITION_MEM_CAP__NPS4_SUPPORT__SHIFT                                         0x3
+#define BIF_BX_DEV0_EPF0_VF1_0_PARTITION_MEM_CAP__NPS6_SUPPORT__SHIFT                                         0x5
+#define BIF_BX_DEV0_EPF0_VF1_0_PARTITION_MEM_CAP__NPS8_SUPPORT__SHIFT                                         0x7
+#define BIF_BX_DEV0_EPF0_VF1_0_PARTITION_MEM_CAP__NPS1_SUPPORT_MASK                                           0x00000001L
+#define BIF_BX_DEV0_EPF0_VF1_0_PARTITION_MEM_CAP__NPS2_SUPPORT_MASK                                           0x00000002L
+#define BIF_BX_DEV0_EPF0_VF1_0_PARTITION_MEM_CAP__NPS3_SUPPORT_MASK                                           0x00000004L
+#define BIF_BX_DEV0_EPF0_VF1_0_PARTITION_MEM_CAP__NPS4_SUPPORT_MASK                                           0x00000008L
+#define BIF_BX_DEV0_EPF0_VF1_0_PARTITION_MEM_CAP__NPS6_SUPPORT_MASK                                           0x00000020L
+#define BIF_BX_DEV0_EPF0_VF1_0_PARTITION_MEM_CAP__NPS8_SUPPORT_MASK                                           0x00000080L
+//BIF_BX_DEV0_EPF0_VF1_0_PARTITION_COMPUTE_STATUS
+#define BIF_BX_DEV0_EPF0_VF1_0_PARTITION_COMPUTE_STATUS__PARTITION_MODE__SHIFT                                0x4
+#define BIF_BX_DEV0_EPF0_VF1_0_PARTITION_COMPUTE_STATUS__PARTITION_MODE_MASK                                  0x000000F0L
+//BIF_BX_DEV0_EPF0_VF1_0_PARTITION_MEM_STATUS
+#define BIF_BX_DEV0_EPF0_VF1_0_PARTITION_MEM_STATUS__CHANGE_STATUS__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF1_0_PARTITION_MEM_STATUS__NPS_MODE__SHIFT                                          0x4
+#define BIF_BX_DEV0_EPF0_VF1_0_PARTITION_MEM_STATUS__CHANGE_STATUS_MASK                                       0x0000000FL
+#define BIF_BX_DEV0_EPF0_VF1_0_PARTITION_MEM_STATUS__NPS_MODE_MASK                                            0x00000FF0L
+
+
+// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf1_SYSPFVFDEC
+//BIF_BX_DEV0_EPF0_VF1_0_MM_INDEX
+#define BIF_BX_DEV0_EPF0_VF1_0_MM_INDEX__MM_OFFSET__SHIFT                                                     0x0
+#define BIF_BX_DEV0_EPF0_VF1_0_MM_INDEX__MM_APER__SHIFT                                                       0x1f
+#define BIF_BX_DEV0_EPF0_VF1_0_MM_INDEX__MM_OFFSET_MASK                                                       0x7FFFFFFFL
+#define BIF_BX_DEV0_EPF0_VF1_0_MM_INDEX__MM_APER_MASK                                                         0x80000000L
+//BIF_BX_DEV0_EPF0_VF1_0_MM_DATA
+#define BIF_BX_DEV0_EPF0_VF1_0_MM_DATA__MM_DATA__SHIFT                                                        0x0
+#define BIF_BX_DEV0_EPF0_VF1_0_MM_DATA__MM_DATA_MASK                                                          0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF1_0_MM_INDEX_HI
+#define BIF_BX_DEV0_EPF0_VF1_0_MM_INDEX_HI__MM_OFFSET_HI__SHIFT                                               0x0
+#define BIF_BX_DEV0_EPF0_VF1_0_MM_INDEX_HI__MM_OFFSET_HI_MASK                                                 0xFFFFFFFFL
+
+
+// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf1_BIFPFVFDEC1:1
+//BIF_BX_DEV0_EPF0_VF1_1_BIF_BME_STATUS
+#define BIF_BX_DEV0_EPF0_VF1_1_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT                                          0x0
+#define BIF_BX_DEV0_EPF0_VF1_1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT                                    0x10
+#define BIF_BX_DEV0_EPF0_VF1_1_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK                                            0x00000001L
+#define BIF_BX_DEV0_EPF0_VF1_1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK                                      0x00010000L
+//BIF_BX_DEV0_EPF0_VF1_1_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_DEV0_EPF0_VF1_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT                                    0x0
+#define BIF_BX_DEV0_EPF0_VF1_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT                                 0x1
+#define BIF_BX_DEV0_EPF0_VF1_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT                                    0x2
+#define BIF_BX_DEV0_EPF0_VF1_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT                                        0x3
+#define BIF_BX_DEV0_EPF0_VF1_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT                              0x10
+#define BIF_BX_DEV0_EPF0_VF1_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT                           0x11
+#define BIF_BX_DEV0_EPF0_VF1_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT                              0x12
+#define BIF_BX_DEV0_EPF0_VF1_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT                                  0x13
+#define BIF_BX_DEV0_EPF0_VF1_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK                                      0x00000001L
+#define BIF_BX_DEV0_EPF0_VF1_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK                                   0x00000002L
+#define BIF_BX_DEV0_EPF0_VF1_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK                                      0x00000004L
+#define BIF_BX_DEV0_EPF0_VF1_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK                                          0x00000008L
+#define BIF_BX_DEV0_EPF0_VF1_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK                                0x00010000L
+#define BIF_BX_DEV0_EPF0_VF1_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK                             0x00020000L
+#define BIF_BX_DEV0_EPF0_VF1_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK                                0x00040000L
+#define BIF_BX_DEV0_EPF0_VF1_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK                                    0x00080000L
+//BIF_BX_DEV0_EPF0_VF1_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_DEV0_EPF0_VF1_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT  0x0
+#define BIF_BX_DEV0_EPF0_VF1_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK  0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF1_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_DEV0_EPF0_VF1_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT  0x0
+#define BIF_BX_DEV0_EPF0_VF1_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK  0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF1_1_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_DEV0_EPF0_VF1_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT          0x0
+#define BIF_BX_DEV0_EPF0_VF1_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT        0x1
+#define BIF_BX_DEV0_EPF0_VF1_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT        0x8
+#define BIF_BX_DEV0_EPF0_VF1_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK            0x00000001L
+#define BIF_BX_DEV0_EPF0_VF1_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK          0x00000002L
+#define BIF_BX_DEV0_EPF0_VF1_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK          0x000FFF00L
+//BIF_BX_DEV0_EPF0_VF1_1_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF1_1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT                        0x0
+#define BIF_BX_DEV0_EPF0_VF1_1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK                          0x00000001L
+//BIF_BX_DEV0_EPF0_VF1_1_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF1_1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT                        0x0
+#define BIF_BX_DEV0_EPF0_VF1_1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK                          0x00000001L
+//BIF_BX_DEV0_EPF0_VF1_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL
+#define BIF_BX_DEV0_EPF0_VF1_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT              0x0
+#define BIF_BX_DEV0_EPF0_VF1_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK                0x00000001L
+//BIF_BX_DEV0_EPF0_VF1_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL
+#define BIF_BX_DEV0_EPF0_VF1_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT    0x0
+#define BIF_BX_DEV0_EPF0_VF1_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK      0x00000001L
+//BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__CP0__SHIFT                                                  0x0
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__CP1__SHIFT                                                  0x1
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__CP2__SHIFT                                                  0x2
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__CP3__SHIFT                                                  0x3
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__CP4__SHIFT                                                  0x4
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__CP5__SHIFT                                                  0x5
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__CP6__SHIFT                                                  0x6
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__CP7__SHIFT                                                  0x7
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__CP8__SHIFT                                                  0x8
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__CP9__SHIFT                                                  0x9
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT                                                0xa
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT                                                0xb
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT                                            0xc
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT                                            0xd
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT                                            0xe
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT                                            0xf
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT                                            0x10
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT                                            0x11
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT                                            0x12
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT                                            0x13
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT                                            0x14
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT                                            0x15
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT                                           0x16
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT                                           0x17
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT                                           0x18
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT                                           0x19
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT                                           0x1a
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT                                           0x1b
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT                                           0x1c
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT                                           0x1d
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT                                           0x1e
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT                                           0x1f
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__CP0_MASK                                                    0x00000001L
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__CP1_MASK                                                    0x00000002L
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__CP2_MASK                                                    0x00000004L
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__CP3_MASK                                                    0x00000008L
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__CP4_MASK                                                    0x00000010L
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__CP5_MASK                                                    0x00000020L
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__CP6_MASK                                                    0x00000040L
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__CP7_MASK                                                    0x00000080L
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__CP8_MASK                                                    0x00000100L
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__CP9_MASK                                                    0x00000200L
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__SDMA0_MASK                                                  0x00000400L
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__SDMA1_MASK                                                  0x00000800L
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK                                              0x00001000L
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK                                              0x00002000L
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK                                              0x00004000L
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK                                              0x00008000L
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK                                              0x00010000L
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK                                              0x00020000L
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK                                              0x00040000L
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK                                              0x00080000L
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK                                              0x00100000L
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK                                              0x00200000L
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK                                             0x00400000L
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK                                             0x00800000L
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK                                             0x01000000L
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK                                             0x02000000L
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK                                             0x04000000L
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK                                             0x08000000L
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK                                             0x10000000L
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK                                             0x20000000L
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK                                             0x40000000L
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK                                             0x80000000L
+//BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__CP0__SHIFT                                                 0x0
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__CP1__SHIFT                                                 0x1
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__CP2__SHIFT                                                 0x2
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__CP3__SHIFT                                                 0x3
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__CP4__SHIFT                                                 0x4
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__CP5__SHIFT                                                 0x5
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__CP6__SHIFT                                                 0x6
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__CP7__SHIFT                                                 0x7
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__CP8__SHIFT                                                 0x8
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__CP9__SHIFT                                                 0x9
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT                                               0xa
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT                                               0xb
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT                                           0xc
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT                                           0xd
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT                                           0xe
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT                                           0xf
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT                                           0x10
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT                                           0x11
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT                                           0x12
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT                                           0x13
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT                                           0x14
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT                                           0x15
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT                                          0x16
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT                                          0x17
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT                                          0x18
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT                                          0x19
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT                                          0x1a
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT                                          0x1b
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT                                          0x1c
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT                                          0x1d
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT                                          0x1e
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT                                          0x1f
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__CP0_MASK                                                   0x00000001L
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__CP1_MASK                                                   0x00000002L
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__CP2_MASK                                                   0x00000004L
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__CP3_MASK                                                   0x00000008L
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__CP4_MASK                                                   0x00000010L
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__CP5_MASK                                                   0x00000020L
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__CP6_MASK                                                   0x00000040L
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__CP7_MASK                                                   0x00000080L
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__CP8_MASK                                                   0x00000100L
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__CP9_MASK                                                   0x00000200L
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__SDMA0_MASK                                                 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__SDMA1_MASK                                                 0x00000800L
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK                                             0x00001000L
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK                                             0x00002000L
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK                                             0x00004000L
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK                                             0x00008000L
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK                                             0x00010000L
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK                                             0x00020000L
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK                                             0x00040000L
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK                                             0x00080000L
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK                                             0x00100000L
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK                                             0x00200000L
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK                                            0x00400000L
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK                                            0x00800000L
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK                                            0x01000000L
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK                                            0x02000000L
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK                                            0x04000000L
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK                                            0x08000000L
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK                                            0x10000000L
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK                                            0x20000000L
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK                                            0x40000000L
+#define BIF_BX_DEV0_EPF0_VF1_1_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK                                            0x80000000L
+//BIF_BX_DEV0_EPF0_VF1_1_BIF_TRANS_PENDING
+#define BIF_BX_DEV0_EPF0_VF1_1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT                                0x0
+#define BIF_BX_DEV0_EPF0_VF1_1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT                                0x1
+#define BIF_BX_DEV0_EPF0_VF1_1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK                                  0x00000001L
+#define BIF_BX_DEV0_EPF0_VF1_1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK                                  0x00000002L
+//BIF_BX_DEV0_EPF0_VF1_1_NBIF_GFX_ADDR_LUT_BYPASS
+#define BIF_BX_DEV0_EPF0_VF1_1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT                                    0x0
+#define BIF_BX_DEV0_EPF0_VF1_1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK                                      0x00000001L
+//BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_CONTROL
+#define BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT                                          0x0
+#define BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT                                            0x1
+#define BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT                                          0x8
+#define BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT                                            0x9
+#define BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_CONTROL__TRN_MSG_VALID_MASK                                            0x00000001L
+#define BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_CONTROL__TRN_MSG_ACK_MASK                                              0x00000002L
+#define BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_CONTROL__RCV_MSG_VALID_MASK                                            0x00000100L
+#define BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_CONTROL__RCV_MSG_ACK_MASK                                              0x00000200L
+//BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_INT_CNTL
+#define BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT                                          0x0
+#define BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT                                            0x1
+#define BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_INT_CNTL__VALID_INT_EN_MASK                                            0x00000001L
+#define BIF_BX_DEV0_EPF0_VF1_1_MAILBOX_INT_CNTL__ACK_INT_EN_MASK                                              0x00000002L
+//BIF_BX_DEV0_EPF0_VF1_1_BIF_VMHV_MAILBOX
+#define BIF_BX_DEV0_EPF0_VF1_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT                          0x0
+#define BIF_BX_DEV0_EPF0_VF1_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT                        0x1
+#define BIF_BX_DEV0_EPF0_VF1_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT                             0x8
+#define BIF_BX_DEV0_EPF0_VF1_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT                            0xf
+#define BIF_BX_DEV0_EPF0_VF1_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT                             0x10
+#define BIF_BX_DEV0_EPF0_VF1_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT                            0x17
+#define BIF_BX_DEV0_EPF0_VF1_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT                              0x18
+#define BIF_BX_DEV0_EPF0_VF1_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT                              0x19
+#define BIF_BX_DEV0_EPF0_VF1_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK                            0x00000001L
+#define BIF_BX_DEV0_EPF0_VF1_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK                          0x00000002L
+#define BIF_BX_DEV0_EPF0_VF1_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK                               0x00000F00L
+#define BIF_BX_DEV0_EPF0_VF1_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK                              0x00008000L
+#define BIF_BX_DEV0_EPF0_VF1_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK                               0x000F0000L
+#define BIF_BX_DEV0_EPF0_VF1_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK                              0x00800000L
+#define BIF_BX_DEV0_EPF0_VF1_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK                                0x01000000L
+#define BIF_BX_DEV0_EPF0_VF1_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK                                0x02000000L
+//BIF_BX_DEV0_EPF0_VF1_1_PARTITION_COMPUTE_CAP
+#define BIF_BX_DEV0_EPF0_VF1_1_PARTITION_COMPUTE_CAP__SPX_SUPPORT__SHIFT                                      0x0
+#define BIF_BX_DEV0_EPF0_VF1_1_PARTITION_COMPUTE_CAP__DPX_SUPPORT__SHIFT                                      0x1
+#define BIF_BX_DEV0_EPF0_VF1_1_PARTITION_COMPUTE_CAP__TPX_SUPPORT__SHIFT                                      0x2
+#define BIF_BX_DEV0_EPF0_VF1_1_PARTITION_COMPUTE_CAP__QPX_SUPPORT__SHIFT                                      0x3
+#define BIF_BX_DEV0_EPF0_VF1_1_PARTITION_COMPUTE_CAP__CPX_SUPPORT__SHIFT                                      0x4
+#define BIF_BX_DEV0_EPF0_VF1_1_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY__SHIFT                                 0xa
+#define BIF_BX_DEV0_EPF0_VF1_1_PARTITION_COMPUTE_CAP__SPX_SUPPORT_MASK                                        0x00000001L
+#define BIF_BX_DEV0_EPF0_VF1_1_PARTITION_COMPUTE_CAP__DPX_SUPPORT_MASK                                        0x00000002L
+#define BIF_BX_DEV0_EPF0_VF1_1_PARTITION_COMPUTE_CAP__TPX_SUPPORT_MASK                                        0x00000004L
+#define BIF_BX_DEV0_EPF0_VF1_1_PARTITION_COMPUTE_CAP__QPX_SUPPORT_MASK                                        0x00000008L
+#define BIF_BX_DEV0_EPF0_VF1_1_PARTITION_COMPUTE_CAP__CPX_SUPPORT_MASK                                        0x00000010L
+#define BIF_BX_DEV0_EPF0_VF1_1_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY_MASK                                   0x0003FC00L
+//BIF_BX_DEV0_EPF0_VF1_1_PARTITION_MEM_CAP
+#define BIF_BX_DEV0_EPF0_VF1_1_PARTITION_MEM_CAP__NPS1_SUPPORT__SHIFT                                         0x0
+#define BIF_BX_DEV0_EPF0_VF1_1_PARTITION_MEM_CAP__NPS2_SUPPORT__SHIFT                                         0x1
+#define BIF_BX_DEV0_EPF0_VF1_1_PARTITION_MEM_CAP__NPS3_SUPPORT__SHIFT                                         0x2
+#define BIF_BX_DEV0_EPF0_VF1_1_PARTITION_MEM_CAP__NPS4_SUPPORT__SHIFT                                         0x3
+#define BIF_BX_DEV0_EPF0_VF1_1_PARTITION_MEM_CAP__NPS6_SUPPORT__SHIFT                                         0x5
+#define BIF_BX_DEV0_EPF0_VF1_1_PARTITION_MEM_CAP__NPS8_SUPPORT__SHIFT                                         0x7
+#define BIF_BX_DEV0_EPF0_VF1_1_PARTITION_MEM_CAP__NPS1_SUPPORT_MASK                                           0x00000001L
+#define BIF_BX_DEV0_EPF0_VF1_1_PARTITION_MEM_CAP__NPS2_SUPPORT_MASK                                           0x00000002L
+#define BIF_BX_DEV0_EPF0_VF1_1_PARTITION_MEM_CAP__NPS3_SUPPORT_MASK                                           0x00000004L
+#define BIF_BX_DEV0_EPF0_VF1_1_PARTITION_MEM_CAP__NPS4_SUPPORT_MASK                                           0x00000008L
+#define BIF_BX_DEV0_EPF0_VF1_1_PARTITION_MEM_CAP__NPS6_SUPPORT_MASK                                           0x00000020L
+#define BIF_BX_DEV0_EPF0_VF1_1_PARTITION_MEM_CAP__NPS8_SUPPORT_MASK                                           0x00000080L
+//BIF_BX_DEV0_EPF0_VF1_1_PARTITION_COMPUTE_STATUS
+#define BIF_BX_DEV0_EPF0_VF1_1_PARTITION_COMPUTE_STATUS__PARTITION_MODE__SHIFT                                0x4
+#define BIF_BX_DEV0_EPF0_VF1_1_PARTITION_COMPUTE_STATUS__PARTITION_MODE_MASK                                  0x000000F0L
+//BIF_BX_DEV0_EPF0_VF1_1_PARTITION_MEM_STATUS
+#define BIF_BX_DEV0_EPF0_VF1_1_PARTITION_MEM_STATUS__CHANGE_STATUS__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF1_1_PARTITION_MEM_STATUS__NPS_MODE__SHIFT                                          0x4
+#define BIF_BX_DEV0_EPF0_VF1_1_PARTITION_MEM_STATUS__CHANGE_STATUS_MASK                                       0x0000000FL
+#define BIF_BX_DEV0_EPF0_VF1_1_PARTITION_MEM_STATUS__NPS_MODE_MASK                                            0x00000FF0L
+
+
+// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf1_SYSPFVFDEC:1
+//BIF_BX_DEV0_EPF0_VF1_1_MM_INDEX
+#define BIF_BX_DEV0_EPF0_VF1_1_MM_INDEX__MM_OFFSET__SHIFT                                                     0x0
+#define BIF_BX_DEV0_EPF0_VF1_1_MM_INDEX__MM_APER__SHIFT                                                       0x1f
+#define BIF_BX_DEV0_EPF0_VF1_1_MM_INDEX__MM_OFFSET_MASK                                                       0x7FFFFFFFL
+#define BIF_BX_DEV0_EPF0_VF1_1_MM_INDEX__MM_APER_MASK                                                         0x80000000L
+//BIF_BX_DEV0_EPF0_VF1_1_MM_DATA
+#define BIF_BX_DEV0_EPF0_VF1_1_MM_DATA__MM_DATA__SHIFT                                                        0x0
+#define BIF_BX_DEV0_EPF0_VF1_1_MM_DATA__MM_DATA_MASK                                                          0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF1_1_MM_INDEX_HI
+#define BIF_BX_DEV0_EPF0_VF1_1_MM_INDEX_HI__MM_OFFSET_HI__SHIFT                                               0x0
+#define BIF_BX_DEV0_EPF0_VF1_1_MM_INDEX_HI__MM_OFFSET_HI_MASK                                                 0xFFFFFFFFL
+
+
+// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf1_BIFPFVFDEC1
+//RCC_DEV0_EPF0_VF1_RCC_ERR_LOG
+#define RCC_DEV0_EPF0_VF1_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT                              0x0
+#define RCC_DEV0_EPF0_VF1_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT                                     0x1
+#define RCC_DEV0_EPF0_VF1_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK                                0x00000001L
+#define RCC_DEV0_EPF0_VF1_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK                                       0x00000002L
+//RCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN
+#define RCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT                                   0x0
+#define RCC_DEV0_EPF0_VF1_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK                                     0x00000001L
+//RCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE
+#define RCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_VF1_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED
+#define RCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT                                         0x0
+#define RCC_DEV0_EPF0_VF1_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK                                           0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER
+#define RCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT                                     0x0
+#define RCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT                                          0x1f
+#define RCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK                                       0x00000001L
+#define RCC_DEV0_EPF0_VF1_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK                                            0x80000000L
+
+
+// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf1_BIFDEC2
+//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT                                           0x2
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT                                              0x0
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK                                                0x00000001L
+//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT                                           0x2
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT                                              0x0
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK                                                0x00000001L
+//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT                                           0x2
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT                                              0x0
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK                                                0x00000001L
+//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_LO
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT                                           0x2
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_HI
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_MSG_DATA
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_CONTROL
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT                                              0x0
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK                                                0x00000001L
+//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT4_ADDR_LO
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT4_ADDR_LO__MSG_ADDR_LO__SHIFT                                           0x2
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT4_ADDR_LO__MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT4_ADDR_HI
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT4_ADDR_HI__MSG_ADDR_HI__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT4_ADDR_HI__MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT4_MSG_DATA
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT4_MSG_DATA__MSG_DATA__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT4_MSG_DATA__MSG_DATA_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT4_CONTROL
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT4_CONTROL__MASK_BIT__SHIFT                                              0x0
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT4_CONTROL__MASK_BIT_MASK                                                0x00000001L
+//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT5_ADDR_LO
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT5_ADDR_LO__MSG_ADDR_LO__SHIFT                                           0x2
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT5_ADDR_LO__MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT5_ADDR_HI
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT5_ADDR_HI__MSG_ADDR_HI__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT5_ADDR_HI__MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT5_MSG_DATA
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT5_MSG_DATA__MSG_DATA__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT5_MSG_DATA__MSG_DATA_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT5_CONTROL
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT5_CONTROL__MASK_BIT__SHIFT                                              0x0
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT5_CONTROL__MASK_BIT_MASK                                                0x00000001L
+//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT6_ADDR_LO
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT6_ADDR_LO__MSG_ADDR_LO__SHIFT                                           0x2
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT6_ADDR_LO__MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT6_ADDR_HI
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT6_ADDR_HI__MSG_ADDR_HI__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT6_ADDR_HI__MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT6_MSG_DATA
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT6_MSG_DATA__MSG_DATA__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT6_MSG_DATA__MSG_DATA_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT6_CONTROL
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT6_CONTROL__MASK_BIT__SHIFT                                              0x0
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT6_CONTROL__MASK_BIT_MASK                                                0x00000001L
+//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT7_ADDR_LO
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT7_ADDR_LO__MSG_ADDR_LO__SHIFT                                           0x2
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT7_ADDR_LO__MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT7_ADDR_HI
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT7_ADDR_HI__MSG_ADDR_HI__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT7_ADDR_HI__MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT7_MSG_DATA
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT7_MSG_DATA__MSG_DATA__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT7_MSG_DATA__MSG_DATA_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT7_CONTROL
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT7_CONTROL__MASK_BIT__SHIFT                                              0x0
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT7_CONTROL__MASK_BIT_MASK                                                0x00000001L
+//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT8_ADDR_LO
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT8_ADDR_LO__MSG_ADDR_LO__SHIFT                                           0x2
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT8_ADDR_LO__MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT8_ADDR_HI
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT8_ADDR_HI__MSG_ADDR_HI__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT8_ADDR_HI__MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT8_MSG_DATA
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT8_MSG_DATA__MSG_DATA__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT8_MSG_DATA__MSG_DATA_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF1_GFXMSIX_VECT8_CONTROL
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT8_CONTROL__MASK_BIT__SHIFT                                              0x0
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_VECT8_CONTROL__MASK_BIT_MASK                                                0x00000001L
+//RCC_DEV0_EPF0_VF1_GFXMSIX_PBA
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT                                             0x1
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK                                               0x00000001L
+#define RCC_DEV0_EPF0_VF1_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK                                               0x00000002L
+
+
+// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf2_BIFPFVFDEC1
+//BIF_BX_DEV0_EPF0_VF2_0_BIF_BME_STATUS
+#define BIF_BX_DEV0_EPF0_VF2_0_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT                                          0x0
+#define BIF_BX_DEV0_EPF0_VF2_0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT                                    0x10
+#define BIF_BX_DEV0_EPF0_VF2_0_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK                                            0x00000001L
+#define BIF_BX_DEV0_EPF0_VF2_0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK                                      0x00010000L
+//BIF_BX_DEV0_EPF0_VF2_0_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_DEV0_EPF0_VF2_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT                                    0x0
+#define BIF_BX_DEV0_EPF0_VF2_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT                                 0x1
+#define BIF_BX_DEV0_EPF0_VF2_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT                                    0x2
+#define BIF_BX_DEV0_EPF0_VF2_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT                                        0x3
+#define BIF_BX_DEV0_EPF0_VF2_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT                              0x10
+#define BIF_BX_DEV0_EPF0_VF2_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT                           0x11
+#define BIF_BX_DEV0_EPF0_VF2_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT                              0x12
+#define BIF_BX_DEV0_EPF0_VF2_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT                                  0x13
+#define BIF_BX_DEV0_EPF0_VF2_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK                                      0x00000001L
+#define BIF_BX_DEV0_EPF0_VF2_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK                                   0x00000002L
+#define BIF_BX_DEV0_EPF0_VF2_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK                                      0x00000004L
+#define BIF_BX_DEV0_EPF0_VF2_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK                                          0x00000008L
+#define BIF_BX_DEV0_EPF0_VF2_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK                                0x00010000L
+#define BIF_BX_DEV0_EPF0_VF2_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK                             0x00020000L
+#define BIF_BX_DEV0_EPF0_VF2_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK                                0x00040000L
+#define BIF_BX_DEV0_EPF0_VF2_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK                                    0x00080000L
+//BIF_BX_DEV0_EPF0_VF2_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_DEV0_EPF0_VF2_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT  0x0
+#define BIF_BX_DEV0_EPF0_VF2_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK  0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF2_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_DEV0_EPF0_VF2_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT  0x0
+#define BIF_BX_DEV0_EPF0_VF2_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK  0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF2_0_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_DEV0_EPF0_VF2_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT          0x0
+#define BIF_BX_DEV0_EPF0_VF2_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT        0x1
+#define BIF_BX_DEV0_EPF0_VF2_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT        0x8
+#define BIF_BX_DEV0_EPF0_VF2_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK            0x00000001L
+#define BIF_BX_DEV0_EPF0_VF2_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK          0x00000002L
+#define BIF_BX_DEV0_EPF0_VF2_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK          0x000FFF00L
+//BIF_BX_DEV0_EPF0_VF2_0_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF2_0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT                        0x0
+#define BIF_BX_DEV0_EPF0_VF2_0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK                          0x00000001L
+//BIF_BX_DEV0_EPF0_VF2_0_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF2_0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT                        0x0
+#define BIF_BX_DEV0_EPF0_VF2_0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK                          0x00000001L
+//BIF_BX_DEV0_EPF0_VF2_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL
+#define BIF_BX_DEV0_EPF0_VF2_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT              0x0
+#define BIF_BX_DEV0_EPF0_VF2_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK                0x00000001L
+//BIF_BX_DEV0_EPF0_VF2_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL
+#define BIF_BX_DEV0_EPF0_VF2_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT    0x0
+#define BIF_BX_DEV0_EPF0_VF2_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK      0x00000001L
+//BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__CP0__SHIFT                                                  0x0
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__CP1__SHIFT                                                  0x1
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__CP2__SHIFT                                                  0x2
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__CP3__SHIFT                                                  0x3
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__CP4__SHIFT                                                  0x4
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__CP5__SHIFT                                                  0x5
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__CP6__SHIFT                                                  0x6
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__CP7__SHIFT                                                  0x7
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__CP8__SHIFT                                                  0x8
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__CP9__SHIFT                                                  0x9
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT                                                0xa
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT                                                0xb
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT                                            0xc
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT                                            0xd
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT                                            0xe
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT                                            0xf
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT                                            0x10
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT                                            0x11
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT                                            0x12
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT                                            0x13
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT                                            0x14
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT                                            0x15
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT                                           0x16
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT                                           0x17
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT                                           0x18
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT                                           0x19
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT                                           0x1a
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT                                           0x1b
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT                                           0x1c
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT                                           0x1d
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT                                           0x1e
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT                                           0x1f
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__CP0_MASK                                                    0x00000001L
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__CP1_MASK                                                    0x00000002L
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__CP2_MASK                                                    0x00000004L
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__CP3_MASK                                                    0x00000008L
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__CP4_MASK                                                    0x00000010L
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__CP5_MASK                                                    0x00000020L
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__CP6_MASK                                                    0x00000040L
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__CP7_MASK                                                    0x00000080L
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__CP8_MASK                                                    0x00000100L
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__CP9_MASK                                                    0x00000200L
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__SDMA0_MASK                                                  0x00000400L
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__SDMA1_MASK                                                  0x00000800L
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK                                              0x00001000L
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK                                              0x00002000L
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK                                              0x00004000L
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK                                              0x00008000L
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK                                              0x00010000L
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK                                              0x00020000L
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK                                              0x00040000L
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK                                              0x00080000L
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK                                              0x00100000L
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK                                              0x00200000L
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK                                             0x00400000L
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK                                             0x00800000L
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK                                             0x01000000L
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK                                             0x02000000L
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK                                             0x04000000L
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK                                             0x08000000L
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK                                             0x10000000L
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK                                             0x20000000L
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK                                             0x40000000L
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK                                             0x80000000L
+//BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__CP0__SHIFT                                                 0x0
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__CP1__SHIFT                                                 0x1
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__CP2__SHIFT                                                 0x2
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__CP3__SHIFT                                                 0x3
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__CP4__SHIFT                                                 0x4
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__CP5__SHIFT                                                 0x5
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__CP6__SHIFT                                                 0x6
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__CP7__SHIFT                                                 0x7
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__CP8__SHIFT                                                 0x8
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__CP9__SHIFT                                                 0x9
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT                                               0xa
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT                                               0xb
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT                                           0xc
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT                                           0xd
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT                                           0xe
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT                                           0xf
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT                                           0x10
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT                                           0x11
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT                                           0x12
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT                                           0x13
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT                                           0x14
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT                                           0x15
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT                                          0x16
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT                                          0x17
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT                                          0x18
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT                                          0x19
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT                                          0x1a
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT                                          0x1b
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT                                          0x1c
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT                                          0x1d
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT                                          0x1e
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT                                          0x1f
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__CP0_MASK                                                   0x00000001L
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__CP1_MASK                                                   0x00000002L
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__CP2_MASK                                                   0x00000004L
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__CP3_MASK                                                   0x00000008L
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__CP4_MASK                                                   0x00000010L
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__CP5_MASK                                                   0x00000020L
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__CP6_MASK                                                   0x00000040L
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__CP7_MASK                                                   0x00000080L
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__CP8_MASK                                                   0x00000100L
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__CP9_MASK                                                   0x00000200L
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__SDMA0_MASK                                                 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__SDMA1_MASK                                                 0x00000800L
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK                                             0x00001000L
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK                                             0x00002000L
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK                                             0x00004000L
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK                                             0x00008000L
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK                                             0x00010000L
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK                                             0x00020000L
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK                                             0x00040000L
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK                                             0x00080000L
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK                                             0x00100000L
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK                                             0x00200000L
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK                                            0x00400000L
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK                                            0x00800000L
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK                                            0x01000000L
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK                                            0x02000000L
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK                                            0x04000000L
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK                                            0x08000000L
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK                                            0x10000000L
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK                                            0x20000000L
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK                                            0x40000000L
+#define BIF_BX_DEV0_EPF0_VF2_0_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK                                            0x80000000L
+//BIF_BX_DEV0_EPF0_VF2_0_BIF_TRANS_PENDING
+#define BIF_BX_DEV0_EPF0_VF2_0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT                                0x0
+#define BIF_BX_DEV0_EPF0_VF2_0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT                                0x1
+#define BIF_BX_DEV0_EPF0_VF2_0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK                                  0x00000001L
+#define BIF_BX_DEV0_EPF0_VF2_0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK                                  0x00000002L
+//BIF_BX_DEV0_EPF0_VF2_0_NBIF_GFX_ADDR_LUT_BYPASS
+#define BIF_BX_DEV0_EPF0_VF2_0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT                                    0x0
+#define BIF_BX_DEV0_EPF0_VF2_0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK                                      0x00000001L
+//BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_CONTROL
+#define BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT                                          0x0
+#define BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT                                            0x1
+#define BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT                                          0x8
+#define BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT                                            0x9
+#define BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_CONTROL__TRN_MSG_VALID_MASK                                            0x00000001L
+#define BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_CONTROL__TRN_MSG_ACK_MASK                                              0x00000002L
+#define BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_CONTROL__RCV_MSG_VALID_MASK                                            0x00000100L
+#define BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_CONTROL__RCV_MSG_ACK_MASK                                              0x00000200L
+//BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_INT_CNTL
+#define BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT                                          0x0
+#define BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT                                            0x1
+#define BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_INT_CNTL__VALID_INT_EN_MASK                                            0x00000001L
+#define BIF_BX_DEV0_EPF0_VF2_0_MAILBOX_INT_CNTL__ACK_INT_EN_MASK                                              0x00000002L
+//BIF_BX_DEV0_EPF0_VF2_0_BIF_VMHV_MAILBOX
+#define BIF_BX_DEV0_EPF0_VF2_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT                          0x0
+#define BIF_BX_DEV0_EPF0_VF2_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT                        0x1
+#define BIF_BX_DEV0_EPF0_VF2_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT                             0x8
+#define BIF_BX_DEV0_EPF0_VF2_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT                            0xf
+#define BIF_BX_DEV0_EPF0_VF2_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT                             0x10
+#define BIF_BX_DEV0_EPF0_VF2_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT                            0x17
+#define BIF_BX_DEV0_EPF0_VF2_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT                              0x18
+#define BIF_BX_DEV0_EPF0_VF2_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT                              0x19
+#define BIF_BX_DEV0_EPF0_VF2_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK                            0x00000001L
+#define BIF_BX_DEV0_EPF0_VF2_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK                          0x00000002L
+#define BIF_BX_DEV0_EPF0_VF2_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK                               0x00000F00L
+#define BIF_BX_DEV0_EPF0_VF2_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK                              0x00008000L
+#define BIF_BX_DEV0_EPF0_VF2_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK                               0x000F0000L
+#define BIF_BX_DEV0_EPF0_VF2_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK                              0x00800000L
+#define BIF_BX_DEV0_EPF0_VF2_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK                                0x01000000L
+#define BIF_BX_DEV0_EPF0_VF2_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK                                0x02000000L
+//BIF_BX_DEV0_EPF0_VF2_0_PARTITION_COMPUTE_CAP
+#define BIF_BX_DEV0_EPF0_VF2_0_PARTITION_COMPUTE_CAP__SPX_SUPPORT__SHIFT                                      0x0
+#define BIF_BX_DEV0_EPF0_VF2_0_PARTITION_COMPUTE_CAP__DPX_SUPPORT__SHIFT                                      0x1
+#define BIF_BX_DEV0_EPF0_VF2_0_PARTITION_COMPUTE_CAP__TPX_SUPPORT__SHIFT                                      0x2
+#define BIF_BX_DEV0_EPF0_VF2_0_PARTITION_COMPUTE_CAP__QPX_SUPPORT__SHIFT                                      0x3
+#define BIF_BX_DEV0_EPF0_VF2_0_PARTITION_COMPUTE_CAP__CPX_SUPPORT__SHIFT                                      0x4
+#define BIF_BX_DEV0_EPF0_VF2_0_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY__SHIFT                                 0xa
+#define BIF_BX_DEV0_EPF0_VF2_0_PARTITION_COMPUTE_CAP__SPX_SUPPORT_MASK                                        0x00000001L
+#define BIF_BX_DEV0_EPF0_VF2_0_PARTITION_COMPUTE_CAP__DPX_SUPPORT_MASK                                        0x00000002L
+#define BIF_BX_DEV0_EPF0_VF2_0_PARTITION_COMPUTE_CAP__TPX_SUPPORT_MASK                                        0x00000004L
+#define BIF_BX_DEV0_EPF0_VF2_0_PARTITION_COMPUTE_CAP__QPX_SUPPORT_MASK                                        0x00000008L
+#define BIF_BX_DEV0_EPF0_VF2_0_PARTITION_COMPUTE_CAP__CPX_SUPPORT_MASK                                        0x00000010L
+#define BIF_BX_DEV0_EPF0_VF2_0_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY_MASK                                   0x0003FC00L
+//BIF_BX_DEV0_EPF0_VF2_0_PARTITION_MEM_CAP
+#define BIF_BX_DEV0_EPF0_VF2_0_PARTITION_MEM_CAP__NPS1_SUPPORT__SHIFT                                         0x0
+#define BIF_BX_DEV0_EPF0_VF2_0_PARTITION_MEM_CAP__NPS2_SUPPORT__SHIFT                                         0x1
+#define BIF_BX_DEV0_EPF0_VF2_0_PARTITION_MEM_CAP__NPS3_SUPPORT__SHIFT                                         0x2
+#define BIF_BX_DEV0_EPF0_VF2_0_PARTITION_MEM_CAP__NPS4_SUPPORT__SHIFT                                         0x3
+#define BIF_BX_DEV0_EPF0_VF2_0_PARTITION_MEM_CAP__NPS6_SUPPORT__SHIFT                                         0x5
+#define BIF_BX_DEV0_EPF0_VF2_0_PARTITION_MEM_CAP__NPS8_SUPPORT__SHIFT                                         0x7
+#define BIF_BX_DEV0_EPF0_VF2_0_PARTITION_MEM_CAP__NPS1_SUPPORT_MASK                                           0x00000001L
+#define BIF_BX_DEV0_EPF0_VF2_0_PARTITION_MEM_CAP__NPS2_SUPPORT_MASK                                           0x00000002L
+#define BIF_BX_DEV0_EPF0_VF2_0_PARTITION_MEM_CAP__NPS3_SUPPORT_MASK                                           0x00000004L
+#define BIF_BX_DEV0_EPF0_VF2_0_PARTITION_MEM_CAP__NPS4_SUPPORT_MASK                                           0x00000008L
+#define BIF_BX_DEV0_EPF0_VF2_0_PARTITION_MEM_CAP__NPS6_SUPPORT_MASK                                           0x00000020L
+#define BIF_BX_DEV0_EPF0_VF2_0_PARTITION_MEM_CAP__NPS8_SUPPORT_MASK                                           0x00000080L
+//BIF_BX_DEV0_EPF0_VF2_0_PARTITION_COMPUTE_STATUS
+#define BIF_BX_DEV0_EPF0_VF2_0_PARTITION_COMPUTE_STATUS__PARTITION_MODE__SHIFT                                0x4
+#define BIF_BX_DEV0_EPF0_VF2_0_PARTITION_COMPUTE_STATUS__PARTITION_MODE_MASK                                  0x000000F0L
+//BIF_BX_DEV0_EPF0_VF2_0_PARTITION_MEM_STATUS
+#define BIF_BX_DEV0_EPF0_VF2_0_PARTITION_MEM_STATUS__CHANGE_STATUS__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF2_0_PARTITION_MEM_STATUS__NPS_MODE__SHIFT                                          0x4
+#define BIF_BX_DEV0_EPF0_VF2_0_PARTITION_MEM_STATUS__CHANGE_STATUS_MASK                                       0x0000000FL
+#define BIF_BX_DEV0_EPF0_VF2_0_PARTITION_MEM_STATUS__NPS_MODE_MASK                                            0x00000FF0L
+
+
+// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf2_SYSPFVFDEC
+//BIF_BX_DEV0_EPF0_VF2_0_MM_INDEX
+#define BIF_BX_DEV0_EPF0_VF2_0_MM_INDEX__MM_OFFSET__SHIFT                                                     0x0
+#define BIF_BX_DEV0_EPF0_VF2_0_MM_INDEX__MM_APER__SHIFT                                                       0x1f
+#define BIF_BX_DEV0_EPF0_VF2_0_MM_INDEX__MM_OFFSET_MASK                                                       0x7FFFFFFFL
+#define BIF_BX_DEV0_EPF0_VF2_0_MM_INDEX__MM_APER_MASK                                                         0x80000000L
+//BIF_BX_DEV0_EPF0_VF2_0_MM_DATA
+#define BIF_BX_DEV0_EPF0_VF2_0_MM_DATA__MM_DATA__SHIFT                                                        0x0
+#define BIF_BX_DEV0_EPF0_VF2_0_MM_DATA__MM_DATA_MASK                                                          0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF2_0_MM_INDEX_HI
+#define BIF_BX_DEV0_EPF0_VF2_0_MM_INDEX_HI__MM_OFFSET_HI__SHIFT                                               0x0
+#define BIF_BX_DEV0_EPF0_VF2_0_MM_INDEX_HI__MM_OFFSET_HI_MASK                                                 0xFFFFFFFFL
+
+
+// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf2_BIFPFVFDEC1:1
+//BIF_BX_DEV0_EPF0_VF2_1_BIF_BME_STATUS
+#define BIF_BX_DEV0_EPF0_VF2_1_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT                                          0x0
+#define BIF_BX_DEV0_EPF0_VF2_1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT                                    0x10
+#define BIF_BX_DEV0_EPF0_VF2_1_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK                                            0x00000001L
+#define BIF_BX_DEV0_EPF0_VF2_1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK                                      0x00010000L
+//BIF_BX_DEV0_EPF0_VF2_1_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_DEV0_EPF0_VF2_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT                                    0x0
+#define BIF_BX_DEV0_EPF0_VF2_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT                                 0x1
+#define BIF_BX_DEV0_EPF0_VF2_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT                                    0x2
+#define BIF_BX_DEV0_EPF0_VF2_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT                                        0x3
+#define BIF_BX_DEV0_EPF0_VF2_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT                              0x10
+#define BIF_BX_DEV0_EPF0_VF2_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT                           0x11
+#define BIF_BX_DEV0_EPF0_VF2_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT                              0x12
+#define BIF_BX_DEV0_EPF0_VF2_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT                                  0x13
+#define BIF_BX_DEV0_EPF0_VF2_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK                                      0x00000001L
+#define BIF_BX_DEV0_EPF0_VF2_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK                                   0x00000002L
+#define BIF_BX_DEV0_EPF0_VF2_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK                                      0x00000004L
+#define BIF_BX_DEV0_EPF0_VF2_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK                                          0x00000008L
+#define BIF_BX_DEV0_EPF0_VF2_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK                                0x00010000L
+#define BIF_BX_DEV0_EPF0_VF2_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK                             0x00020000L
+#define BIF_BX_DEV0_EPF0_VF2_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK                                0x00040000L
+#define BIF_BX_DEV0_EPF0_VF2_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK                                    0x00080000L
+//BIF_BX_DEV0_EPF0_VF2_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_DEV0_EPF0_VF2_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT  0x0
+#define BIF_BX_DEV0_EPF0_VF2_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK  0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF2_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_DEV0_EPF0_VF2_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT  0x0
+#define BIF_BX_DEV0_EPF0_VF2_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK  0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF2_1_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_DEV0_EPF0_VF2_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT          0x0
+#define BIF_BX_DEV0_EPF0_VF2_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT        0x1
+#define BIF_BX_DEV0_EPF0_VF2_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT        0x8
+#define BIF_BX_DEV0_EPF0_VF2_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK            0x00000001L
+#define BIF_BX_DEV0_EPF0_VF2_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK          0x00000002L
+#define BIF_BX_DEV0_EPF0_VF2_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK          0x000FFF00L
+//BIF_BX_DEV0_EPF0_VF2_1_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF2_1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT                        0x0
+#define BIF_BX_DEV0_EPF0_VF2_1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK                          0x00000001L
+//BIF_BX_DEV0_EPF0_VF2_1_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF2_1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT                        0x0
+#define BIF_BX_DEV0_EPF0_VF2_1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK                          0x00000001L
+//BIF_BX_DEV0_EPF0_VF2_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL
+#define BIF_BX_DEV0_EPF0_VF2_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT              0x0
+#define BIF_BX_DEV0_EPF0_VF2_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK                0x00000001L
+//BIF_BX_DEV0_EPF0_VF2_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL
+#define BIF_BX_DEV0_EPF0_VF2_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT    0x0
+#define BIF_BX_DEV0_EPF0_VF2_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK      0x00000001L
+//BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__CP0__SHIFT                                                  0x0
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__CP1__SHIFT                                                  0x1
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__CP2__SHIFT                                                  0x2
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__CP3__SHIFT                                                  0x3
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__CP4__SHIFT                                                  0x4
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__CP5__SHIFT                                                  0x5
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__CP6__SHIFT                                                  0x6
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__CP7__SHIFT                                                  0x7
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__CP8__SHIFT                                                  0x8
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__CP9__SHIFT                                                  0x9
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT                                                0xa
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT                                                0xb
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT                                            0xc
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT                                            0xd
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT                                            0xe
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT                                            0xf
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT                                            0x10
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT                                            0x11
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT                                            0x12
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT                                            0x13
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT                                            0x14
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT                                            0x15
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT                                           0x16
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT                                           0x17
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT                                           0x18
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT                                           0x19
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT                                           0x1a
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT                                           0x1b
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT                                           0x1c
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT                                           0x1d
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT                                           0x1e
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT                                           0x1f
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__CP0_MASK                                                    0x00000001L
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__CP1_MASK                                                    0x00000002L
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__CP2_MASK                                                    0x00000004L
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__CP3_MASK                                                    0x00000008L
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__CP4_MASK                                                    0x00000010L
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__CP5_MASK                                                    0x00000020L
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__CP6_MASK                                                    0x00000040L
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__CP7_MASK                                                    0x00000080L
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__CP8_MASK                                                    0x00000100L
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__CP9_MASK                                                    0x00000200L
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__SDMA0_MASK                                                  0x00000400L
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__SDMA1_MASK                                                  0x00000800L
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK                                              0x00001000L
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK                                              0x00002000L
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK                                              0x00004000L
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK                                              0x00008000L
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK                                              0x00010000L
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK                                              0x00020000L
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK                                              0x00040000L
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK                                              0x00080000L
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK                                              0x00100000L
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK                                              0x00200000L
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK                                             0x00400000L
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK                                             0x00800000L
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK                                             0x01000000L
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK                                             0x02000000L
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK                                             0x04000000L
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK                                             0x08000000L
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK                                             0x10000000L
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK                                             0x20000000L
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK                                             0x40000000L
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK                                             0x80000000L
+//BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__CP0__SHIFT                                                 0x0
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__CP1__SHIFT                                                 0x1
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__CP2__SHIFT                                                 0x2
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__CP3__SHIFT                                                 0x3
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__CP4__SHIFT                                                 0x4
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__CP5__SHIFT                                                 0x5
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__CP6__SHIFT                                                 0x6
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__CP7__SHIFT                                                 0x7
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__CP8__SHIFT                                                 0x8
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__CP9__SHIFT                                                 0x9
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT                                               0xa
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT                                               0xb
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT                                           0xc
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT                                           0xd
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT                                           0xe
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT                                           0xf
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT                                           0x10
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT                                           0x11
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT                                           0x12
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT                                           0x13
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT                                           0x14
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT                                           0x15
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT                                          0x16
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT                                          0x17
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT                                          0x18
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT                                          0x19
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT                                          0x1a
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT                                          0x1b
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT                                          0x1c
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT                                          0x1d
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT                                          0x1e
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT                                          0x1f
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__CP0_MASK                                                   0x00000001L
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__CP1_MASK                                                   0x00000002L
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__CP2_MASK                                                   0x00000004L
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__CP3_MASK                                                   0x00000008L
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__CP4_MASK                                                   0x00000010L
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__CP5_MASK                                                   0x00000020L
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__CP6_MASK                                                   0x00000040L
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__CP7_MASK                                                   0x00000080L
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__CP8_MASK                                                   0x00000100L
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__CP9_MASK                                                   0x00000200L
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__SDMA0_MASK                                                 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__SDMA1_MASK                                                 0x00000800L
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK                                             0x00001000L
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK                                             0x00002000L
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK                                             0x00004000L
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK                                             0x00008000L
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK                                             0x00010000L
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK                                             0x00020000L
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK                                             0x00040000L
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK                                             0x00080000L
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK                                             0x00100000L
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK                                             0x00200000L
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK                                            0x00400000L
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK                                            0x00800000L
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK                                            0x01000000L
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK                                            0x02000000L
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK                                            0x04000000L
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK                                            0x08000000L
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK                                            0x10000000L
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK                                            0x20000000L
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK                                            0x40000000L
+#define BIF_BX_DEV0_EPF0_VF2_1_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK                                            0x80000000L
+//BIF_BX_DEV0_EPF0_VF2_1_BIF_TRANS_PENDING
+#define BIF_BX_DEV0_EPF0_VF2_1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT                                0x0
+#define BIF_BX_DEV0_EPF0_VF2_1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT                                0x1
+#define BIF_BX_DEV0_EPF0_VF2_1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK                                  0x00000001L
+#define BIF_BX_DEV0_EPF0_VF2_1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK                                  0x00000002L
+//BIF_BX_DEV0_EPF0_VF2_1_NBIF_GFX_ADDR_LUT_BYPASS
+#define BIF_BX_DEV0_EPF0_VF2_1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT                                    0x0
+#define BIF_BX_DEV0_EPF0_VF2_1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK                                      0x00000001L
+//BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_CONTROL
+#define BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT                                          0x0
+#define BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT                                            0x1
+#define BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT                                          0x8
+#define BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT                                            0x9
+#define BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_CONTROL__TRN_MSG_VALID_MASK                                            0x00000001L
+#define BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_CONTROL__TRN_MSG_ACK_MASK                                              0x00000002L
+#define BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_CONTROL__RCV_MSG_VALID_MASK                                            0x00000100L
+#define BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_CONTROL__RCV_MSG_ACK_MASK                                              0x00000200L
+//BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_INT_CNTL
+#define BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT                                          0x0
+#define BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT                                            0x1
+#define BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_INT_CNTL__VALID_INT_EN_MASK                                            0x00000001L
+#define BIF_BX_DEV0_EPF0_VF2_1_MAILBOX_INT_CNTL__ACK_INT_EN_MASK                                              0x00000002L
+//BIF_BX_DEV0_EPF0_VF2_1_BIF_VMHV_MAILBOX
+#define BIF_BX_DEV0_EPF0_VF2_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT                          0x0
+#define BIF_BX_DEV0_EPF0_VF2_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT                        0x1
+#define BIF_BX_DEV0_EPF0_VF2_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT                             0x8
+#define BIF_BX_DEV0_EPF0_VF2_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT                            0xf
+#define BIF_BX_DEV0_EPF0_VF2_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT                             0x10
+#define BIF_BX_DEV0_EPF0_VF2_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT                            0x17
+#define BIF_BX_DEV0_EPF0_VF2_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT                              0x18
+#define BIF_BX_DEV0_EPF0_VF2_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT                              0x19
+#define BIF_BX_DEV0_EPF0_VF2_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK                            0x00000001L
+#define BIF_BX_DEV0_EPF0_VF2_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK                          0x00000002L
+#define BIF_BX_DEV0_EPF0_VF2_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK                               0x00000F00L
+#define BIF_BX_DEV0_EPF0_VF2_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK                              0x00008000L
+#define BIF_BX_DEV0_EPF0_VF2_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK                               0x000F0000L
+#define BIF_BX_DEV0_EPF0_VF2_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK                              0x00800000L
+#define BIF_BX_DEV0_EPF0_VF2_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK                                0x01000000L
+#define BIF_BX_DEV0_EPF0_VF2_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK                                0x02000000L
+//BIF_BX_DEV0_EPF0_VF2_1_PARTITION_COMPUTE_CAP
+#define BIF_BX_DEV0_EPF0_VF2_1_PARTITION_COMPUTE_CAP__SPX_SUPPORT__SHIFT                                      0x0
+#define BIF_BX_DEV0_EPF0_VF2_1_PARTITION_COMPUTE_CAP__DPX_SUPPORT__SHIFT                                      0x1
+#define BIF_BX_DEV0_EPF0_VF2_1_PARTITION_COMPUTE_CAP__TPX_SUPPORT__SHIFT                                      0x2
+#define BIF_BX_DEV0_EPF0_VF2_1_PARTITION_COMPUTE_CAP__QPX_SUPPORT__SHIFT                                      0x3
+#define BIF_BX_DEV0_EPF0_VF2_1_PARTITION_COMPUTE_CAP__CPX_SUPPORT__SHIFT                                      0x4
+#define BIF_BX_DEV0_EPF0_VF2_1_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY__SHIFT                                 0xa
+#define BIF_BX_DEV0_EPF0_VF2_1_PARTITION_COMPUTE_CAP__SPX_SUPPORT_MASK                                        0x00000001L
+#define BIF_BX_DEV0_EPF0_VF2_1_PARTITION_COMPUTE_CAP__DPX_SUPPORT_MASK                                        0x00000002L
+#define BIF_BX_DEV0_EPF0_VF2_1_PARTITION_COMPUTE_CAP__TPX_SUPPORT_MASK                                        0x00000004L
+#define BIF_BX_DEV0_EPF0_VF2_1_PARTITION_COMPUTE_CAP__QPX_SUPPORT_MASK                                        0x00000008L
+#define BIF_BX_DEV0_EPF0_VF2_1_PARTITION_COMPUTE_CAP__CPX_SUPPORT_MASK                                        0x00000010L
+#define BIF_BX_DEV0_EPF0_VF2_1_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY_MASK                                   0x0003FC00L
+//BIF_BX_DEV0_EPF0_VF2_1_PARTITION_MEM_CAP
+#define BIF_BX_DEV0_EPF0_VF2_1_PARTITION_MEM_CAP__NPS1_SUPPORT__SHIFT                                         0x0
+#define BIF_BX_DEV0_EPF0_VF2_1_PARTITION_MEM_CAP__NPS2_SUPPORT__SHIFT                                         0x1
+#define BIF_BX_DEV0_EPF0_VF2_1_PARTITION_MEM_CAP__NPS3_SUPPORT__SHIFT                                         0x2
+#define BIF_BX_DEV0_EPF0_VF2_1_PARTITION_MEM_CAP__NPS4_SUPPORT__SHIFT                                         0x3
+#define BIF_BX_DEV0_EPF0_VF2_1_PARTITION_MEM_CAP__NPS6_SUPPORT__SHIFT                                         0x5
+#define BIF_BX_DEV0_EPF0_VF2_1_PARTITION_MEM_CAP__NPS8_SUPPORT__SHIFT                                         0x7
+#define BIF_BX_DEV0_EPF0_VF2_1_PARTITION_MEM_CAP__NPS1_SUPPORT_MASK                                           0x00000001L
+#define BIF_BX_DEV0_EPF0_VF2_1_PARTITION_MEM_CAP__NPS2_SUPPORT_MASK                                           0x00000002L
+#define BIF_BX_DEV0_EPF0_VF2_1_PARTITION_MEM_CAP__NPS3_SUPPORT_MASK                                           0x00000004L
+#define BIF_BX_DEV0_EPF0_VF2_1_PARTITION_MEM_CAP__NPS4_SUPPORT_MASK                                           0x00000008L
+#define BIF_BX_DEV0_EPF0_VF2_1_PARTITION_MEM_CAP__NPS6_SUPPORT_MASK                                           0x00000020L
+#define BIF_BX_DEV0_EPF0_VF2_1_PARTITION_MEM_CAP__NPS8_SUPPORT_MASK                                           0x00000080L
+//BIF_BX_DEV0_EPF0_VF2_1_PARTITION_COMPUTE_STATUS
+#define BIF_BX_DEV0_EPF0_VF2_1_PARTITION_COMPUTE_STATUS__PARTITION_MODE__SHIFT                                0x4
+#define BIF_BX_DEV0_EPF0_VF2_1_PARTITION_COMPUTE_STATUS__PARTITION_MODE_MASK                                  0x000000F0L
+//BIF_BX_DEV0_EPF0_VF2_1_PARTITION_MEM_STATUS
+#define BIF_BX_DEV0_EPF0_VF2_1_PARTITION_MEM_STATUS__CHANGE_STATUS__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF2_1_PARTITION_MEM_STATUS__NPS_MODE__SHIFT                                          0x4
+#define BIF_BX_DEV0_EPF0_VF2_1_PARTITION_MEM_STATUS__CHANGE_STATUS_MASK                                       0x0000000FL
+#define BIF_BX_DEV0_EPF0_VF2_1_PARTITION_MEM_STATUS__NPS_MODE_MASK                                            0x00000FF0L
+
+
+// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf2_SYSPFVFDEC:1
+//BIF_BX_DEV0_EPF0_VF2_1_MM_INDEX
+#define BIF_BX_DEV0_EPF0_VF2_1_MM_INDEX__MM_OFFSET__SHIFT                                                     0x0
+#define BIF_BX_DEV0_EPF0_VF2_1_MM_INDEX__MM_APER__SHIFT                                                       0x1f
+#define BIF_BX_DEV0_EPF0_VF2_1_MM_INDEX__MM_OFFSET_MASK                                                       0x7FFFFFFFL
+#define BIF_BX_DEV0_EPF0_VF2_1_MM_INDEX__MM_APER_MASK                                                         0x80000000L
+//BIF_BX_DEV0_EPF0_VF2_1_MM_DATA
+#define BIF_BX_DEV0_EPF0_VF2_1_MM_DATA__MM_DATA__SHIFT                                                        0x0
+#define BIF_BX_DEV0_EPF0_VF2_1_MM_DATA__MM_DATA_MASK                                                          0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF2_1_MM_INDEX_HI
+#define BIF_BX_DEV0_EPF0_VF2_1_MM_INDEX_HI__MM_OFFSET_HI__SHIFT                                               0x0
+#define BIF_BX_DEV0_EPF0_VF2_1_MM_INDEX_HI__MM_OFFSET_HI_MASK                                                 0xFFFFFFFFL
+
+
+// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf2_BIFPFVFDEC1
+//RCC_DEV0_EPF0_VF2_RCC_ERR_LOG
+#define RCC_DEV0_EPF0_VF2_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT                              0x0
+#define RCC_DEV0_EPF0_VF2_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT                                     0x1
+#define RCC_DEV0_EPF0_VF2_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK                                0x00000001L
+#define RCC_DEV0_EPF0_VF2_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK                                       0x00000002L
+//RCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN
+#define RCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT                                   0x0
+#define RCC_DEV0_EPF0_VF2_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK                                     0x00000001L
+//RCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE
+#define RCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_VF2_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED
+#define RCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT                                         0x0
+#define RCC_DEV0_EPF0_VF2_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK                                           0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER
+#define RCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT                                     0x0
+#define RCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT                                          0x1f
+#define RCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK                                       0x00000001L
+#define RCC_DEV0_EPF0_VF2_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK                                            0x80000000L
+
+
+// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf2_BIFDEC2
+//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT                                           0x2
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT                                              0x0
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK                                                0x00000001L
+//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT                                           0x2
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT                                              0x0
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK                                                0x00000001L
+//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT                                           0x2
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT                                              0x0
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK                                                0x00000001L
+//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_LO
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT                                           0x2
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_HI
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_MSG_DATA
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_CONTROL
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT                                              0x0
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK                                                0x00000001L
+//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT4_ADDR_LO
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT4_ADDR_LO__MSG_ADDR_LO__SHIFT                                           0x2
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT4_ADDR_LO__MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT4_ADDR_HI
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT4_ADDR_HI__MSG_ADDR_HI__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT4_ADDR_HI__MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT4_MSG_DATA
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT4_MSG_DATA__MSG_DATA__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT4_MSG_DATA__MSG_DATA_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT4_CONTROL
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT4_CONTROL__MASK_BIT__SHIFT                                              0x0
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT4_CONTROL__MASK_BIT_MASK                                                0x00000001L
+//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT5_ADDR_LO
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT5_ADDR_LO__MSG_ADDR_LO__SHIFT                                           0x2
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT5_ADDR_LO__MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT5_ADDR_HI
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT5_ADDR_HI__MSG_ADDR_HI__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT5_ADDR_HI__MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT5_MSG_DATA
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT5_MSG_DATA__MSG_DATA__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT5_MSG_DATA__MSG_DATA_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT5_CONTROL
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT5_CONTROL__MASK_BIT__SHIFT                                              0x0
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT5_CONTROL__MASK_BIT_MASK                                                0x00000001L
+//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT6_ADDR_LO
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT6_ADDR_LO__MSG_ADDR_LO__SHIFT                                           0x2
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT6_ADDR_LO__MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT6_ADDR_HI
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT6_ADDR_HI__MSG_ADDR_HI__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT6_ADDR_HI__MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT6_MSG_DATA
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT6_MSG_DATA__MSG_DATA__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT6_MSG_DATA__MSG_DATA_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT6_CONTROL
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT6_CONTROL__MASK_BIT__SHIFT                                              0x0
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT6_CONTROL__MASK_BIT_MASK                                                0x00000001L
+//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT7_ADDR_LO
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT7_ADDR_LO__MSG_ADDR_LO__SHIFT                                           0x2
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT7_ADDR_LO__MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT7_ADDR_HI
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT7_ADDR_HI__MSG_ADDR_HI__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT7_ADDR_HI__MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT7_MSG_DATA
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT7_MSG_DATA__MSG_DATA__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT7_MSG_DATA__MSG_DATA_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT7_CONTROL
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT7_CONTROL__MASK_BIT__SHIFT                                              0x0
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT7_CONTROL__MASK_BIT_MASK                                                0x00000001L
+//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT8_ADDR_LO
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT8_ADDR_LO__MSG_ADDR_LO__SHIFT                                           0x2
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT8_ADDR_LO__MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT8_ADDR_HI
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT8_ADDR_HI__MSG_ADDR_HI__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT8_ADDR_HI__MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT8_MSG_DATA
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT8_MSG_DATA__MSG_DATA__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT8_MSG_DATA__MSG_DATA_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF2_GFXMSIX_VECT8_CONTROL
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT8_CONTROL__MASK_BIT__SHIFT                                              0x0
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_VECT8_CONTROL__MASK_BIT_MASK                                                0x00000001L
+//RCC_DEV0_EPF0_VF2_GFXMSIX_PBA
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT                                             0x1
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK                                               0x00000001L
+#define RCC_DEV0_EPF0_VF2_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK                                               0x00000002L
+
+
+// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf3_BIFPFVFDEC1
+//BIF_BX_DEV0_EPF0_VF3_0_BIF_BME_STATUS
+#define BIF_BX_DEV0_EPF0_VF3_0_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT                                          0x0
+#define BIF_BX_DEV0_EPF0_VF3_0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT                                    0x10
+#define BIF_BX_DEV0_EPF0_VF3_0_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK                                            0x00000001L
+#define BIF_BX_DEV0_EPF0_VF3_0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK                                      0x00010000L
+//BIF_BX_DEV0_EPF0_VF3_0_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_DEV0_EPF0_VF3_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT                                    0x0
+#define BIF_BX_DEV0_EPF0_VF3_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT                                 0x1
+#define BIF_BX_DEV0_EPF0_VF3_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT                                    0x2
+#define BIF_BX_DEV0_EPF0_VF3_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT                                        0x3
+#define BIF_BX_DEV0_EPF0_VF3_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT                              0x10
+#define BIF_BX_DEV0_EPF0_VF3_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT                           0x11
+#define BIF_BX_DEV0_EPF0_VF3_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT                              0x12
+#define BIF_BX_DEV0_EPF0_VF3_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT                                  0x13
+#define BIF_BX_DEV0_EPF0_VF3_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK                                      0x00000001L
+#define BIF_BX_DEV0_EPF0_VF3_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK                                   0x00000002L
+#define BIF_BX_DEV0_EPF0_VF3_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK                                      0x00000004L
+#define BIF_BX_DEV0_EPF0_VF3_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK                                          0x00000008L
+#define BIF_BX_DEV0_EPF0_VF3_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK                                0x00010000L
+#define BIF_BX_DEV0_EPF0_VF3_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK                             0x00020000L
+#define BIF_BX_DEV0_EPF0_VF3_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK                                0x00040000L
+#define BIF_BX_DEV0_EPF0_VF3_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK                                    0x00080000L
+//BIF_BX_DEV0_EPF0_VF3_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_DEV0_EPF0_VF3_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT  0x0
+#define BIF_BX_DEV0_EPF0_VF3_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK  0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF3_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_DEV0_EPF0_VF3_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT  0x0
+#define BIF_BX_DEV0_EPF0_VF3_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK  0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF3_0_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_DEV0_EPF0_VF3_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT          0x0
+#define BIF_BX_DEV0_EPF0_VF3_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT        0x1
+#define BIF_BX_DEV0_EPF0_VF3_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT        0x8
+#define BIF_BX_DEV0_EPF0_VF3_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK            0x00000001L
+#define BIF_BX_DEV0_EPF0_VF3_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK          0x00000002L
+#define BIF_BX_DEV0_EPF0_VF3_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK          0x000FFF00L
+//BIF_BX_DEV0_EPF0_VF3_0_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF3_0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT                        0x0
+#define BIF_BX_DEV0_EPF0_VF3_0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK                          0x00000001L
+//BIF_BX_DEV0_EPF0_VF3_0_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF3_0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT                        0x0
+#define BIF_BX_DEV0_EPF0_VF3_0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK                          0x00000001L
+//BIF_BX_DEV0_EPF0_VF3_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL
+#define BIF_BX_DEV0_EPF0_VF3_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT              0x0
+#define BIF_BX_DEV0_EPF0_VF3_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK                0x00000001L
+//BIF_BX_DEV0_EPF0_VF3_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL
+#define BIF_BX_DEV0_EPF0_VF3_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT    0x0
+#define BIF_BX_DEV0_EPF0_VF3_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK      0x00000001L
+//BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__CP0__SHIFT                                                  0x0
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__CP1__SHIFT                                                  0x1
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__CP2__SHIFT                                                  0x2
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__CP3__SHIFT                                                  0x3
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__CP4__SHIFT                                                  0x4
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__CP5__SHIFT                                                  0x5
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__CP6__SHIFT                                                  0x6
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__CP7__SHIFT                                                  0x7
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__CP8__SHIFT                                                  0x8
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__CP9__SHIFT                                                  0x9
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT                                                0xa
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT                                                0xb
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT                                            0xc
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT                                            0xd
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT                                            0xe
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT                                            0xf
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT                                            0x10
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT                                            0x11
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT                                            0x12
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT                                            0x13
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT                                            0x14
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT                                            0x15
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT                                           0x16
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT                                           0x17
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT                                           0x18
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT                                           0x19
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT                                           0x1a
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT                                           0x1b
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT                                           0x1c
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT                                           0x1d
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT                                           0x1e
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT                                           0x1f
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__CP0_MASK                                                    0x00000001L
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__CP1_MASK                                                    0x00000002L
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__CP2_MASK                                                    0x00000004L
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__CP3_MASK                                                    0x00000008L
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__CP4_MASK                                                    0x00000010L
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__CP5_MASK                                                    0x00000020L
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__CP6_MASK                                                    0x00000040L
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__CP7_MASK                                                    0x00000080L
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__CP8_MASK                                                    0x00000100L
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__CP9_MASK                                                    0x00000200L
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__SDMA0_MASK                                                  0x00000400L
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__SDMA1_MASK                                                  0x00000800L
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK                                              0x00001000L
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK                                              0x00002000L
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK                                              0x00004000L
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK                                              0x00008000L
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK                                              0x00010000L
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK                                              0x00020000L
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK                                              0x00040000L
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK                                              0x00080000L
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK                                              0x00100000L
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK                                              0x00200000L
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK                                             0x00400000L
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK                                             0x00800000L
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK                                             0x01000000L
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK                                             0x02000000L
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK                                             0x04000000L
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK                                             0x08000000L
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK                                             0x10000000L
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK                                             0x20000000L
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK                                             0x40000000L
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK                                             0x80000000L
+//BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__CP0__SHIFT                                                 0x0
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__CP1__SHIFT                                                 0x1
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__CP2__SHIFT                                                 0x2
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__CP3__SHIFT                                                 0x3
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__CP4__SHIFT                                                 0x4
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__CP5__SHIFT                                                 0x5
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__CP6__SHIFT                                                 0x6
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__CP7__SHIFT                                                 0x7
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__CP8__SHIFT                                                 0x8
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__CP9__SHIFT                                                 0x9
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT                                               0xa
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT                                               0xb
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT                                           0xc
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT                                           0xd
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT                                           0xe
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT                                           0xf
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT                                           0x10
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT                                           0x11
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT                                           0x12
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT                                           0x13
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT                                           0x14
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT                                           0x15
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT                                          0x16
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT                                          0x17
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT                                          0x18
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT                                          0x19
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT                                          0x1a
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT                                          0x1b
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT                                          0x1c
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT                                          0x1d
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT                                          0x1e
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT                                          0x1f
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__CP0_MASK                                                   0x00000001L
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__CP1_MASK                                                   0x00000002L
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__CP2_MASK                                                   0x00000004L
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__CP3_MASK                                                   0x00000008L
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__CP4_MASK                                                   0x00000010L
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__CP5_MASK                                                   0x00000020L
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__CP6_MASK                                                   0x00000040L
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__CP7_MASK                                                   0x00000080L
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__CP8_MASK                                                   0x00000100L
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__CP9_MASK                                                   0x00000200L
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__SDMA0_MASK                                                 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__SDMA1_MASK                                                 0x00000800L
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK                                             0x00001000L
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK                                             0x00002000L
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK                                             0x00004000L
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK                                             0x00008000L
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK                                             0x00010000L
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK                                             0x00020000L
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK                                             0x00040000L
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK                                             0x00080000L
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK                                             0x00100000L
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK                                             0x00200000L
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK                                            0x00400000L
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK                                            0x00800000L
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK                                            0x01000000L
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK                                            0x02000000L
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK                                            0x04000000L
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK                                            0x08000000L
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK                                            0x10000000L
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK                                            0x20000000L
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK                                            0x40000000L
+#define BIF_BX_DEV0_EPF0_VF3_0_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK                                            0x80000000L
+//BIF_BX_DEV0_EPF0_VF3_0_BIF_TRANS_PENDING
+#define BIF_BX_DEV0_EPF0_VF3_0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT                                0x0
+#define BIF_BX_DEV0_EPF0_VF3_0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT                                0x1
+#define BIF_BX_DEV0_EPF0_VF3_0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK                                  0x00000001L
+#define BIF_BX_DEV0_EPF0_VF3_0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK                                  0x00000002L
+//BIF_BX_DEV0_EPF0_VF3_0_NBIF_GFX_ADDR_LUT_BYPASS
+#define BIF_BX_DEV0_EPF0_VF3_0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT                                    0x0
+#define BIF_BX_DEV0_EPF0_VF3_0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK                                      0x00000001L
+//BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_CONTROL
+#define BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT                                          0x0
+#define BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT                                            0x1
+#define BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT                                          0x8
+#define BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT                                            0x9
+#define BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_CONTROL__TRN_MSG_VALID_MASK                                            0x00000001L
+#define BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_CONTROL__TRN_MSG_ACK_MASK                                              0x00000002L
+#define BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_CONTROL__RCV_MSG_VALID_MASK                                            0x00000100L
+#define BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_CONTROL__RCV_MSG_ACK_MASK                                              0x00000200L
+//BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_INT_CNTL
+#define BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT                                          0x0
+#define BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT                                            0x1
+#define BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_INT_CNTL__VALID_INT_EN_MASK                                            0x00000001L
+#define BIF_BX_DEV0_EPF0_VF3_0_MAILBOX_INT_CNTL__ACK_INT_EN_MASK                                              0x00000002L
+//BIF_BX_DEV0_EPF0_VF3_0_BIF_VMHV_MAILBOX
+#define BIF_BX_DEV0_EPF0_VF3_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT                          0x0
+#define BIF_BX_DEV0_EPF0_VF3_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT                        0x1
+#define BIF_BX_DEV0_EPF0_VF3_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT                             0x8
+#define BIF_BX_DEV0_EPF0_VF3_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT                            0xf
+#define BIF_BX_DEV0_EPF0_VF3_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT                             0x10
+#define BIF_BX_DEV0_EPF0_VF3_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT                            0x17
+#define BIF_BX_DEV0_EPF0_VF3_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT                              0x18
+#define BIF_BX_DEV0_EPF0_VF3_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT                              0x19
+#define BIF_BX_DEV0_EPF0_VF3_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK                            0x00000001L
+#define BIF_BX_DEV0_EPF0_VF3_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK                          0x00000002L
+#define BIF_BX_DEV0_EPF0_VF3_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK                               0x00000F00L
+#define BIF_BX_DEV0_EPF0_VF3_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK                              0x00008000L
+#define BIF_BX_DEV0_EPF0_VF3_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK                               0x000F0000L
+#define BIF_BX_DEV0_EPF0_VF3_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK                              0x00800000L
+#define BIF_BX_DEV0_EPF0_VF3_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK                                0x01000000L
+#define BIF_BX_DEV0_EPF0_VF3_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK                                0x02000000L
+//BIF_BX_DEV0_EPF0_VF3_0_PARTITION_COMPUTE_CAP
+#define BIF_BX_DEV0_EPF0_VF3_0_PARTITION_COMPUTE_CAP__SPX_SUPPORT__SHIFT                                      0x0
+#define BIF_BX_DEV0_EPF0_VF3_0_PARTITION_COMPUTE_CAP__DPX_SUPPORT__SHIFT                                      0x1
+#define BIF_BX_DEV0_EPF0_VF3_0_PARTITION_COMPUTE_CAP__TPX_SUPPORT__SHIFT                                      0x2
+#define BIF_BX_DEV0_EPF0_VF3_0_PARTITION_COMPUTE_CAP__QPX_SUPPORT__SHIFT                                      0x3
+#define BIF_BX_DEV0_EPF0_VF3_0_PARTITION_COMPUTE_CAP__CPX_SUPPORT__SHIFT                                      0x4
+#define BIF_BX_DEV0_EPF0_VF3_0_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY__SHIFT                                 0xa
+#define BIF_BX_DEV0_EPF0_VF3_0_PARTITION_COMPUTE_CAP__SPX_SUPPORT_MASK                                        0x00000001L
+#define BIF_BX_DEV0_EPF0_VF3_0_PARTITION_COMPUTE_CAP__DPX_SUPPORT_MASK                                        0x00000002L
+#define BIF_BX_DEV0_EPF0_VF3_0_PARTITION_COMPUTE_CAP__TPX_SUPPORT_MASK                                        0x00000004L
+#define BIF_BX_DEV0_EPF0_VF3_0_PARTITION_COMPUTE_CAP__QPX_SUPPORT_MASK                                        0x00000008L
+#define BIF_BX_DEV0_EPF0_VF3_0_PARTITION_COMPUTE_CAP__CPX_SUPPORT_MASK                                        0x00000010L
+#define BIF_BX_DEV0_EPF0_VF3_0_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY_MASK                                   0x0003FC00L
+//BIF_BX_DEV0_EPF0_VF3_0_PARTITION_MEM_CAP
+#define BIF_BX_DEV0_EPF0_VF3_0_PARTITION_MEM_CAP__NPS1_SUPPORT__SHIFT                                         0x0
+#define BIF_BX_DEV0_EPF0_VF3_0_PARTITION_MEM_CAP__NPS2_SUPPORT__SHIFT                                         0x1
+#define BIF_BX_DEV0_EPF0_VF3_0_PARTITION_MEM_CAP__NPS3_SUPPORT__SHIFT                                         0x2
+#define BIF_BX_DEV0_EPF0_VF3_0_PARTITION_MEM_CAP__NPS4_SUPPORT__SHIFT                                         0x3
+#define BIF_BX_DEV0_EPF0_VF3_0_PARTITION_MEM_CAP__NPS6_SUPPORT__SHIFT                                         0x5
+#define BIF_BX_DEV0_EPF0_VF3_0_PARTITION_MEM_CAP__NPS8_SUPPORT__SHIFT                                         0x7
+#define BIF_BX_DEV0_EPF0_VF3_0_PARTITION_MEM_CAP__NPS1_SUPPORT_MASK                                           0x00000001L
+#define BIF_BX_DEV0_EPF0_VF3_0_PARTITION_MEM_CAP__NPS2_SUPPORT_MASK                                           0x00000002L
+#define BIF_BX_DEV0_EPF0_VF3_0_PARTITION_MEM_CAP__NPS3_SUPPORT_MASK                                           0x00000004L
+#define BIF_BX_DEV0_EPF0_VF3_0_PARTITION_MEM_CAP__NPS4_SUPPORT_MASK                                           0x00000008L
+#define BIF_BX_DEV0_EPF0_VF3_0_PARTITION_MEM_CAP__NPS6_SUPPORT_MASK                                           0x00000020L
+#define BIF_BX_DEV0_EPF0_VF3_0_PARTITION_MEM_CAP__NPS8_SUPPORT_MASK                                           0x00000080L
+//BIF_BX_DEV0_EPF0_VF3_0_PARTITION_COMPUTE_STATUS
+#define BIF_BX_DEV0_EPF0_VF3_0_PARTITION_COMPUTE_STATUS__PARTITION_MODE__SHIFT                                0x4
+#define BIF_BX_DEV0_EPF0_VF3_0_PARTITION_COMPUTE_STATUS__PARTITION_MODE_MASK                                  0x000000F0L
+//BIF_BX_DEV0_EPF0_VF3_0_PARTITION_MEM_STATUS
+#define BIF_BX_DEV0_EPF0_VF3_0_PARTITION_MEM_STATUS__CHANGE_STATUS__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF3_0_PARTITION_MEM_STATUS__NPS_MODE__SHIFT                                          0x4
+#define BIF_BX_DEV0_EPF0_VF3_0_PARTITION_MEM_STATUS__CHANGE_STATUS_MASK                                       0x0000000FL
+#define BIF_BX_DEV0_EPF0_VF3_0_PARTITION_MEM_STATUS__NPS_MODE_MASK                                            0x00000FF0L
+
+
+// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf3_SYSPFVFDEC
+//BIF_BX_DEV0_EPF0_VF3_0_MM_INDEX
+#define BIF_BX_DEV0_EPF0_VF3_0_MM_INDEX__MM_OFFSET__SHIFT                                                     0x0
+#define BIF_BX_DEV0_EPF0_VF3_0_MM_INDEX__MM_APER__SHIFT                                                       0x1f
+#define BIF_BX_DEV0_EPF0_VF3_0_MM_INDEX__MM_OFFSET_MASK                                                       0x7FFFFFFFL
+#define BIF_BX_DEV0_EPF0_VF3_0_MM_INDEX__MM_APER_MASK                                                         0x80000000L
+//BIF_BX_DEV0_EPF0_VF3_0_MM_DATA
+#define BIF_BX_DEV0_EPF0_VF3_0_MM_DATA__MM_DATA__SHIFT                                                        0x0
+#define BIF_BX_DEV0_EPF0_VF3_0_MM_DATA__MM_DATA_MASK                                                          0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF3_0_MM_INDEX_HI
+#define BIF_BX_DEV0_EPF0_VF3_0_MM_INDEX_HI__MM_OFFSET_HI__SHIFT                                               0x0
+#define BIF_BX_DEV0_EPF0_VF3_0_MM_INDEX_HI__MM_OFFSET_HI_MASK                                                 0xFFFFFFFFL
+
+
+// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf3_BIFPFVFDEC1:1
+//BIF_BX_DEV0_EPF0_VF3_1_BIF_BME_STATUS
+#define BIF_BX_DEV0_EPF0_VF3_1_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT                                          0x0
+#define BIF_BX_DEV0_EPF0_VF3_1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT                                    0x10
+#define BIF_BX_DEV0_EPF0_VF3_1_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK                                            0x00000001L
+#define BIF_BX_DEV0_EPF0_VF3_1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK                                      0x00010000L
+//BIF_BX_DEV0_EPF0_VF3_1_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_DEV0_EPF0_VF3_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT                                    0x0
+#define BIF_BX_DEV0_EPF0_VF3_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT                                 0x1
+#define BIF_BX_DEV0_EPF0_VF3_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT                                    0x2
+#define BIF_BX_DEV0_EPF0_VF3_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT                                        0x3
+#define BIF_BX_DEV0_EPF0_VF3_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT                              0x10
+#define BIF_BX_DEV0_EPF0_VF3_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT                           0x11
+#define BIF_BX_DEV0_EPF0_VF3_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT                              0x12
+#define BIF_BX_DEV0_EPF0_VF3_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT                                  0x13
+#define BIF_BX_DEV0_EPF0_VF3_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK                                      0x00000001L
+#define BIF_BX_DEV0_EPF0_VF3_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK                                   0x00000002L
+#define BIF_BX_DEV0_EPF0_VF3_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK                                      0x00000004L
+#define BIF_BX_DEV0_EPF0_VF3_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK                                          0x00000008L
+#define BIF_BX_DEV0_EPF0_VF3_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK                                0x00010000L
+#define BIF_BX_DEV0_EPF0_VF3_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK                             0x00020000L
+#define BIF_BX_DEV0_EPF0_VF3_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK                                0x00040000L
+#define BIF_BX_DEV0_EPF0_VF3_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK                                    0x00080000L
+//BIF_BX_DEV0_EPF0_VF3_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_DEV0_EPF0_VF3_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT  0x0
+#define BIF_BX_DEV0_EPF0_VF3_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK  0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF3_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_DEV0_EPF0_VF3_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT  0x0
+#define BIF_BX_DEV0_EPF0_VF3_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK  0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF3_1_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_DEV0_EPF0_VF3_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT          0x0
+#define BIF_BX_DEV0_EPF0_VF3_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT        0x1
+#define BIF_BX_DEV0_EPF0_VF3_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT        0x8
+#define BIF_BX_DEV0_EPF0_VF3_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK            0x00000001L
+#define BIF_BX_DEV0_EPF0_VF3_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK          0x00000002L
+#define BIF_BX_DEV0_EPF0_VF3_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK          0x000FFF00L
+//BIF_BX_DEV0_EPF0_VF3_1_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF3_1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT                        0x0
+#define BIF_BX_DEV0_EPF0_VF3_1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK                          0x00000001L
+//BIF_BX_DEV0_EPF0_VF3_1_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF3_1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT                        0x0
+#define BIF_BX_DEV0_EPF0_VF3_1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK                          0x00000001L
+//BIF_BX_DEV0_EPF0_VF3_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL
+#define BIF_BX_DEV0_EPF0_VF3_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT              0x0
+#define BIF_BX_DEV0_EPF0_VF3_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK                0x00000001L
+//BIF_BX_DEV0_EPF0_VF3_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL
+#define BIF_BX_DEV0_EPF0_VF3_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT    0x0
+#define BIF_BX_DEV0_EPF0_VF3_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK      0x00000001L
+//BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__CP0__SHIFT                                                  0x0
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__CP1__SHIFT                                                  0x1
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__CP2__SHIFT                                                  0x2
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__CP3__SHIFT                                                  0x3
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__CP4__SHIFT                                                  0x4
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__CP5__SHIFT                                                  0x5
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__CP6__SHIFT                                                  0x6
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__CP7__SHIFT                                                  0x7
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__CP8__SHIFT                                                  0x8
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__CP9__SHIFT                                                  0x9
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT                                                0xa
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT                                                0xb
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT                                            0xc
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT                                            0xd
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT                                            0xe
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT                                            0xf
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT                                            0x10
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT                                            0x11
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT                                            0x12
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT                                            0x13
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT                                            0x14
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT                                            0x15
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT                                           0x16
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT                                           0x17
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT                                           0x18
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT                                           0x19
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT                                           0x1a
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT                                           0x1b
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT                                           0x1c
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT                                           0x1d
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT                                           0x1e
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT                                           0x1f
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__CP0_MASK                                                    0x00000001L
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__CP1_MASK                                                    0x00000002L
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__CP2_MASK                                                    0x00000004L
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__CP3_MASK                                                    0x00000008L
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__CP4_MASK                                                    0x00000010L
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__CP5_MASK                                                    0x00000020L
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__CP6_MASK                                                    0x00000040L
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__CP7_MASK                                                    0x00000080L
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__CP8_MASK                                                    0x00000100L
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__CP9_MASK                                                    0x00000200L
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__SDMA0_MASK                                                  0x00000400L
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__SDMA1_MASK                                                  0x00000800L
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK                                              0x00001000L
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK                                              0x00002000L
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK                                              0x00004000L
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK                                              0x00008000L
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK                                              0x00010000L
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK                                              0x00020000L
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK                                              0x00040000L
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK                                              0x00080000L
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK                                              0x00100000L
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK                                              0x00200000L
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK                                             0x00400000L
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK                                             0x00800000L
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK                                             0x01000000L
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK                                             0x02000000L
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK                                             0x04000000L
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK                                             0x08000000L
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK                                             0x10000000L
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK                                             0x20000000L
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK                                             0x40000000L
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK                                             0x80000000L
+//BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__CP0__SHIFT                                                 0x0
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__CP1__SHIFT                                                 0x1
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__CP2__SHIFT                                                 0x2
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__CP3__SHIFT                                                 0x3
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__CP4__SHIFT                                                 0x4
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__CP5__SHIFT                                                 0x5
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__CP6__SHIFT                                                 0x6
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__CP7__SHIFT                                                 0x7
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__CP8__SHIFT                                                 0x8
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__CP9__SHIFT                                                 0x9
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT                                               0xa
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT                                               0xb
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT                                           0xc
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT                                           0xd
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT                                           0xe
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT                                           0xf
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT                                           0x10
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT                                           0x11
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT                                           0x12
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT                                           0x13
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT                                           0x14
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT                                           0x15
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT                                          0x16
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT                                          0x17
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT                                          0x18
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT                                          0x19
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT                                          0x1a
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT                                          0x1b
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT                                          0x1c
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT                                          0x1d
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT                                          0x1e
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT                                          0x1f
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__CP0_MASK                                                   0x00000001L
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__CP1_MASK                                                   0x00000002L
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__CP2_MASK                                                   0x00000004L
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__CP3_MASK                                                   0x00000008L
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__CP4_MASK                                                   0x00000010L
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__CP5_MASK                                                   0x00000020L
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__CP6_MASK                                                   0x00000040L
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__CP7_MASK                                                   0x00000080L
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__CP8_MASK                                                   0x00000100L
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__CP9_MASK                                                   0x00000200L
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__SDMA0_MASK                                                 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__SDMA1_MASK                                                 0x00000800L
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK                                             0x00001000L
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK                                             0x00002000L
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK                                             0x00004000L
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK                                             0x00008000L
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK                                             0x00010000L
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK                                             0x00020000L
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK                                             0x00040000L
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK                                             0x00080000L
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK                                             0x00100000L
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK                                             0x00200000L
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK                                            0x00400000L
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK                                            0x00800000L
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK                                            0x01000000L
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK                                            0x02000000L
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK                                            0x04000000L
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK                                            0x08000000L
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK                                            0x10000000L
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK                                            0x20000000L
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK                                            0x40000000L
+#define BIF_BX_DEV0_EPF0_VF3_1_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK                                            0x80000000L
+//BIF_BX_DEV0_EPF0_VF3_1_BIF_TRANS_PENDING
+#define BIF_BX_DEV0_EPF0_VF3_1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT                                0x0
+#define BIF_BX_DEV0_EPF0_VF3_1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT                                0x1
+#define BIF_BX_DEV0_EPF0_VF3_1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK                                  0x00000001L
+#define BIF_BX_DEV0_EPF0_VF3_1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK                                  0x00000002L
+//BIF_BX_DEV0_EPF0_VF3_1_NBIF_GFX_ADDR_LUT_BYPASS
+#define BIF_BX_DEV0_EPF0_VF3_1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT                                    0x0
+#define BIF_BX_DEV0_EPF0_VF3_1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK                                      0x00000001L
+//BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_CONTROL
+#define BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT                                          0x0
+#define BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT                                            0x1
+#define BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT                                          0x8
+#define BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT                                            0x9
+#define BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_CONTROL__TRN_MSG_VALID_MASK                                            0x00000001L
+#define BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_CONTROL__TRN_MSG_ACK_MASK                                              0x00000002L
+#define BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_CONTROL__RCV_MSG_VALID_MASK                                            0x00000100L
+#define BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_CONTROL__RCV_MSG_ACK_MASK                                              0x00000200L
+//BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_INT_CNTL
+#define BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT                                          0x0
+#define BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT                                            0x1
+#define BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_INT_CNTL__VALID_INT_EN_MASK                                            0x00000001L
+#define BIF_BX_DEV0_EPF0_VF3_1_MAILBOX_INT_CNTL__ACK_INT_EN_MASK                                              0x00000002L
+//BIF_BX_DEV0_EPF0_VF3_1_BIF_VMHV_MAILBOX
+#define BIF_BX_DEV0_EPF0_VF3_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT                          0x0
+#define BIF_BX_DEV0_EPF0_VF3_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT                        0x1
+#define BIF_BX_DEV0_EPF0_VF3_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT                             0x8
+#define BIF_BX_DEV0_EPF0_VF3_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT                            0xf
+#define BIF_BX_DEV0_EPF0_VF3_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT                             0x10
+#define BIF_BX_DEV0_EPF0_VF3_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT                            0x17
+#define BIF_BX_DEV0_EPF0_VF3_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT                              0x18
+#define BIF_BX_DEV0_EPF0_VF3_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT                              0x19
+#define BIF_BX_DEV0_EPF0_VF3_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK                            0x00000001L
+#define BIF_BX_DEV0_EPF0_VF3_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK                          0x00000002L
+#define BIF_BX_DEV0_EPF0_VF3_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK                               0x00000F00L
+#define BIF_BX_DEV0_EPF0_VF3_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK                              0x00008000L
+#define BIF_BX_DEV0_EPF0_VF3_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK                               0x000F0000L
+#define BIF_BX_DEV0_EPF0_VF3_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK                              0x00800000L
+#define BIF_BX_DEV0_EPF0_VF3_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK                                0x01000000L
+#define BIF_BX_DEV0_EPF0_VF3_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK                                0x02000000L
+//BIF_BX_DEV0_EPF0_VF3_1_PARTITION_COMPUTE_CAP
+#define BIF_BX_DEV0_EPF0_VF3_1_PARTITION_COMPUTE_CAP__SPX_SUPPORT__SHIFT                                      0x0
+#define BIF_BX_DEV0_EPF0_VF3_1_PARTITION_COMPUTE_CAP__DPX_SUPPORT__SHIFT                                      0x1
+#define BIF_BX_DEV0_EPF0_VF3_1_PARTITION_COMPUTE_CAP__TPX_SUPPORT__SHIFT                                      0x2
+#define BIF_BX_DEV0_EPF0_VF3_1_PARTITION_COMPUTE_CAP__QPX_SUPPORT__SHIFT                                      0x3
+#define BIF_BX_DEV0_EPF0_VF3_1_PARTITION_COMPUTE_CAP__CPX_SUPPORT__SHIFT                                      0x4
+#define BIF_BX_DEV0_EPF0_VF3_1_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY__SHIFT                                 0xa
+#define BIF_BX_DEV0_EPF0_VF3_1_PARTITION_COMPUTE_CAP__SPX_SUPPORT_MASK                                        0x00000001L
+#define BIF_BX_DEV0_EPF0_VF3_1_PARTITION_COMPUTE_CAP__DPX_SUPPORT_MASK                                        0x00000002L
+#define BIF_BX_DEV0_EPF0_VF3_1_PARTITION_COMPUTE_CAP__TPX_SUPPORT_MASK                                        0x00000004L
+#define BIF_BX_DEV0_EPF0_VF3_1_PARTITION_COMPUTE_CAP__QPX_SUPPORT_MASK                                        0x00000008L
+#define BIF_BX_DEV0_EPF0_VF3_1_PARTITION_COMPUTE_CAP__CPX_SUPPORT_MASK                                        0x00000010L
+#define BIF_BX_DEV0_EPF0_VF3_1_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY_MASK                                   0x0003FC00L
+//BIF_BX_DEV0_EPF0_VF3_1_PARTITION_MEM_CAP
+#define BIF_BX_DEV0_EPF0_VF3_1_PARTITION_MEM_CAP__NPS1_SUPPORT__SHIFT                                         0x0
+#define BIF_BX_DEV0_EPF0_VF3_1_PARTITION_MEM_CAP__NPS2_SUPPORT__SHIFT                                         0x1
+#define BIF_BX_DEV0_EPF0_VF3_1_PARTITION_MEM_CAP__NPS3_SUPPORT__SHIFT                                         0x2
+#define BIF_BX_DEV0_EPF0_VF3_1_PARTITION_MEM_CAP__NPS4_SUPPORT__SHIFT                                         0x3
+#define BIF_BX_DEV0_EPF0_VF3_1_PARTITION_MEM_CAP__NPS6_SUPPORT__SHIFT                                         0x5
+#define BIF_BX_DEV0_EPF0_VF3_1_PARTITION_MEM_CAP__NPS8_SUPPORT__SHIFT                                         0x7
+#define BIF_BX_DEV0_EPF0_VF3_1_PARTITION_MEM_CAP__NPS1_SUPPORT_MASK                                           0x00000001L
+#define BIF_BX_DEV0_EPF0_VF3_1_PARTITION_MEM_CAP__NPS2_SUPPORT_MASK                                           0x00000002L
+#define BIF_BX_DEV0_EPF0_VF3_1_PARTITION_MEM_CAP__NPS3_SUPPORT_MASK                                           0x00000004L
+#define BIF_BX_DEV0_EPF0_VF3_1_PARTITION_MEM_CAP__NPS4_SUPPORT_MASK                                           0x00000008L
+#define BIF_BX_DEV0_EPF0_VF3_1_PARTITION_MEM_CAP__NPS6_SUPPORT_MASK                                           0x00000020L
+#define BIF_BX_DEV0_EPF0_VF3_1_PARTITION_MEM_CAP__NPS8_SUPPORT_MASK                                           0x00000080L
+//BIF_BX_DEV0_EPF0_VF3_1_PARTITION_COMPUTE_STATUS
+#define BIF_BX_DEV0_EPF0_VF3_1_PARTITION_COMPUTE_STATUS__PARTITION_MODE__SHIFT                                0x4
+#define BIF_BX_DEV0_EPF0_VF3_1_PARTITION_COMPUTE_STATUS__PARTITION_MODE_MASK                                  0x000000F0L
+//BIF_BX_DEV0_EPF0_VF3_1_PARTITION_MEM_STATUS
+#define BIF_BX_DEV0_EPF0_VF3_1_PARTITION_MEM_STATUS__CHANGE_STATUS__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF3_1_PARTITION_MEM_STATUS__NPS_MODE__SHIFT                                          0x4
+#define BIF_BX_DEV0_EPF0_VF3_1_PARTITION_MEM_STATUS__CHANGE_STATUS_MASK                                       0x0000000FL
+#define BIF_BX_DEV0_EPF0_VF3_1_PARTITION_MEM_STATUS__NPS_MODE_MASK                                            0x00000FF0L
+
+
+// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf3_SYSPFVFDEC:1
+//BIF_BX_DEV0_EPF0_VF3_1_MM_INDEX
+#define BIF_BX_DEV0_EPF0_VF3_1_MM_INDEX__MM_OFFSET__SHIFT                                                     0x0
+#define BIF_BX_DEV0_EPF0_VF3_1_MM_INDEX__MM_APER__SHIFT                                                       0x1f
+#define BIF_BX_DEV0_EPF0_VF3_1_MM_INDEX__MM_OFFSET_MASK                                                       0x7FFFFFFFL
+#define BIF_BX_DEV0_EPF0_VF3_1_MM_INDEX__MM_APER_MASK                                                         0x80000000L
+//BIF_BX_DEV0_EPF0_VF3_1_MM_DATA
+#define BIF_BX_DEV0_EPF0_VF3_1_MM_DATA__MM_DATA__SHIFT                                                        0x0
+#define BIF_BX_DEV0_EPF0_VF3_1_MM_DATA__MM_DATA_MASK                                                          0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF3_1_MM_INDEX_HI
+#define BIF_BX_DEV0_EPF0_VF3_1_MM_INDEX_HI__MM_OFFSET_HI__SHIFT                                               0x0
+#define BIF_BX_DEV0_EPF0_VF3_1_MM_INDEX_HI__MM_OFFSET_HI_MASK                                                 0xFFFFFFFFL
+
+
+// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf3_BIFPFVFDEC1
+//RCC_DEV0_EPF0_VF3_RCC_ERR_LOG
+#define RCC_DEV0_EPF0_VF3_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT                              0x0
+#define RCC_DEV0_EPF0_VF3_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT                                     0x1
+#define RCC_DEV0_EPF0_VF3_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK                                0x00000001L
+#define RCC_DEV0_EPF0_VF3_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK                                       0x00000002L
+//RCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN
+#define RCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT                                   0x0
+#define RCC_DEV0_EPF0_VF3_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK                                     0x00000001L
+//RCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE
+#define RCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_VF3_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED
+#define RCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT                                         0x0
+#define RCC_DEV0_EPF0_VF3_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK                                           0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER
+#define RCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT                                     0x0
+#define RCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT                                          0x1f
+#define RCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK                                       0x00000001L
+#define RCC_DEV0_EPF0_VF3_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK                                            0x80000000L
+
+
+// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf3_BIFDEC2
+//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT                                           0x2
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT                                              0x0
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK                                                0x00000001L
+//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT                                           0x2
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT                                              0x0
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK                                                0x00000001L
+//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT                                           0x2
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT                                              0x0
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK                                                0x00000001L
+//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_LO
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT                                           0x2
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_HI
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_MSG_DATA
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_CONTROL
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT                                              0x0
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK                                                0x00000001L
+//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT4_ADDR_LO
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT4_ADDR_LO__MSG_ADDR_LO__SHIFT                                           0x2
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT4_ADDR_LO__MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT4_ADDR_HI
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT4_ADDR_HI__MSG_ADDR_HI__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT4_ADDR_HI__MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT4_MSG_DATA
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT4_MSG_DATA__MSG_DATA__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT4_MSG_DATA__MSG_DATA_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT4_CONTROL
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT4_CONTROL__MASK_BIT__SHIFT                                              0x0
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT4_CONTROL__MASK_BIT_MASK                                                0x00000001L
+//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT5_ADDR_LO
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT5_ADDR_LO__MSG_ADDR_LO__SHIFT                                           0x2
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT5_ADDR_LO__MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT5_ADDR_HI
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT5_ADDR_HI__MSG_ADDR_HI__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT5_ADDR_HI__MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT5_MSG_DATA
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT5_MSG_DATA__MSG_DATA__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT5_MSG_DATA__MSG_DATA_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT5_CONTROL
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT5_CONTROL__MASK_BIT__SHIFT                                              0x0
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT5_CONTROL__MASK_BIT_MASK                                                0x00000001L
+//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT6_ADDR_LO
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT6_ADDR_LO__MSG_ADDR_LO__SHIFT                                           0x2
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT6_ADDR_LO__MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT6_ADDR_HI
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT6_ADDR_HI__MSG_ADDR_HI__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT6_ADDR_HI__MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT6_MSG_DATA
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT6_MSG_DATA__MSG_DATA__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT6_MSG_DATA__MSG_DATA_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT6_CONTROL
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT6_CONTROL__MASK_BIT__SHIFT                                              0x0
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT6_CONTROL__MASK_BIT_MASK                                                0x00000001L
+//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT7_ADDR_LO
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT7_ADDR_LO__MSG_ADDR_LO__SHIFT                                           0x2
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT7_ADDR_LO__MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT7_ADDR_HI
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT7_ADDR_HI__MSG_ADDR_HI__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT7_ADDR_HI__MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT7_MSG_DATA
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT7_MSG_DATA__MSG_DATA__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT7_MSG_DATA__MSG_DATA_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT7_CONTROL
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT7_CONTROL__MASK_BIT__SHIFT                                              0x0
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT7_CONTROL__MASK_BIT_MASK                                                0x00000001L
+//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT8_ADDR_LO
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT8_ADDR_LO__MSG_ADDR_LO__SHIFT                                           0x2
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT8_ADDR_LO__MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT8_ADDR_HI
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT8_ADDR_HI__MSG_ADDR_HI__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT8_ADDR_HI__MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT8_MSG_DATA
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT8_MSG_DATA__MSG_DATA__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT8_MSG_DATA__MSG_DATA_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF3_GFXMSIX_VECT8_CONTROL
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT8_CONTROL__MASK_BIT__SHIFT                                              0x0
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_VECT8_CONTROL__MASK_BIT_MASK                                                0x00000001L
+//RCC_DEV0_EPF0_VF3_GFXMSIX_PBA
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT                                             0x1
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK                                               0x00000001L
+#define RCC_DEV0_EPF0_VF3_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK                                               0x00000002L
+
+
+// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf4_BIFPFVFDEC1
+//BIF_BX_DEV0_EPF0_VF4_0_BIF_BME_STATUS
+#define BIF_BX_DEV0_EPF0_VF4_0_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT                                          0x0
+#define BIF_BX_DEV0_EPF0_VF4_0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT                                    0x10
+#define BIF_BX_DEV0_EPF0_VF4_0_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK                                            0x00000001L
+#define BIF_BX_DEV0_EPF0_VF4_0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK                                      0x00010000L
+//BIF_BX_DEV0_EPF0_VF4_0_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_DEV0_EPF0_VF4_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT                                    0x0
+#define BIF_BX_DEV0_EPF0_VF4_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT                                 0x1
+#define BIF_BX_DEV0_EPF0_VF4_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT                                    0x2
+#define BIF_BX_DEV0_EPF0_VF4_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT                                        0x3
+#define BIF_BX_DEV0_EPF0_VF4_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT                              0x10
+#define BIF_BX_DEV0_EPF0_VF4_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT                           0x11
+#define BIF_BX_DEV0_EPF0_VF4_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT                              0x12
+#define BIF_BX_DEV0_EPF0_VF4_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT                                  0x13
+#define BIF_BX_DEV0_EPF0_VF4_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK                                      0x00000001L
+#define BIF_BX_DEV0_EPF0_VF4_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK                                   0x00000002L
+#define BIF_BX_DEV0_EPF0_VF4_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK                                      0x00000004L
+#define BIF_BX_DEV0_EPF0_VF4_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK                                          0x00000008L
+#define BIF_BX_DEV0_EPF0_VF4_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK                                0x00010000L
+#define BIF_BX_DEV0_EPF0_VF4_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK                             0x00020000L
+#define BIF_BX_DEV0_EPF0_VF4_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK                                0x00040000L
+#define BIF_BX_DEV0_EPF0_VF4_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK                                    0x00080000L
+//BIF_BX_DEV0_EPF0_VF4_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_DEV0_EPF0_VF4_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT  0x0
+#define BIF_BX_DEV0_EPF0_VF4_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK  0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF4_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_DEV0_EPF0_VF4_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT  0x0
+#define BIF_BX_DEV0_EPF0_VF4_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK  0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF4_0_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_DEV0_EPF0_VF4_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT          0x0
+#define BIF_BX_DEV0_EPF0_VF4_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT        0x1
+#define BIF_BX_DEV0_EPF0_VF4_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT        0x8
+#define BIF_BX_DEV0_EPF0_VF4_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK            0x00000001L
+#define BIF_BX_DEV0_EPF0_VF4_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK          0x00000002L
+#define BIF_BX_DEV0_EPF0_VF4_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK          0x000FFF00L
+//BIF_BX_DEV0_EPF0_VF4_0_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF4_0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT                        0x0
+#define BIF_BX_DEV0_EPF0_VF4_0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK                          0x00000001L
+//BIF_BX_DEV0_EPF0_VF4_0_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF4_0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT                        0x0
+#define BIF_BX_DEV0_EPF0_VF4_0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK                          0x00000001L
+//BIF_BX_DEV0_EPF0_VF4_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL
+#define BIF_BX_DEV0_EPF0_VF4_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT              0x0
+#define BIF_BX_DEV0_EPF0_VF4_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK                0x00000001L
+//BIF_BX_DEV0_EPF0_VF4_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL
+#define BIF_BX_DEV0_EPF0_VF4_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT    0x0
+#define BIF_BX_DEV0_EPF0_VF4_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK      0x00000001L
+//BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__CP0__SHIFT                                                  0x0
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__CP1__SHIFT                                                  0x1
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__CP2__SHIFT                                                  0x2
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__CP3__SHIFT                                                  0x3
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__CP4__SHIFT                                                  0x4
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__CP5__SHIFT                                                  0x5
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__CP6__SHIFT                                                  0x6
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__CP7__SHIFT                                                  0x7
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__CP8__SHIFT                                                  0x8
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__CP9__SHIFT                                                  0x9
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT                                                0xa
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT                                                0xb
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT                                            0xc
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT                                            0xd
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT                                            0xe
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT                                            0xf
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT                                            0x10
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT                                            0x11
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT                                            0x12
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT                                            0x13
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT                                            0x14
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT                                            0x15
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT                                           0x16
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT                                           0x17
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT                                           0x18
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT                                           0x19
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT                                           0x1a
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT                                           0x1b
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT                                           0x1c
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT                                           0x1d
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT                                           0x1e
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT                                           0x1f
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__CP0_MASK                                                    0x00000001L
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__CP1_MASK                                                    0x00000002L
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__CP2_MASK                                                    0x00000004L
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__CP3_MASK                                                    0x00000008L
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__CP4_MASK                                                    0x00000010L
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__CP5_MASK                                                    0x00000020L
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__CP6_MASK                                                    0x00000040L
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__CP7_MASK                                                    0x00000080L
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__CP8_MASK                                                    0x00000100L
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__CP9_MASK                                                    0x00000200L
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__SDMA0_MASK                                                  0x00000400L
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__SDMA1_MASK                                                  0x00000800L
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK                                              0x00001000L
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK                                              0x00002000L
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK                                              0x00004000L
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK                                              0x00008000L
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK                                              0x00010000L
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK                                              0x00020000L
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK                                              0x00040000L
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK                                              0x00080000L
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK                                              0x00100000L
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK                                              0x00200000L
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK                                             0x00400000L
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK                                             0x00800000L
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK                                             0x01000000L
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK                                             0x02000000L
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK                                             0x04000000L
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK                                             0x08000000L
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK                                             0x10000000L
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK                                             0x20000000L
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK                                             0x40000000L
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK                                             0x80000000L
+//BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__CP0__SHIFT                                                 0x0
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__CP1__SHIFT                                                 0x1
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__CP2__SHIFT                                                 0x2
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__CP3__SHIFT                                                 0x3
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__CP4__SHIFT                                                 0x4
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__CP5__SHIFT                                                 0x5
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__CP6__SHIFT                                                 0x6
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__CP7__SHIFT                                                 0x7
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__CP8__SHIFT                                                 0x8
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__CP9__SHIFT                                                 0x9
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT                                               0xa
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT                                               0xb
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT                                           0xc
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT                                           0xd
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT                                           0xe
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT                                           0xf
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT                                           0x10
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT                                           0x11
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT                                           0x12
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT                                           0x13
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT                                           0x14
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT                                           0x15
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT                                          0x16
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT                                          0x17
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT                                          0x18
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT                                          0x19
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT                                          0x1a
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT                                          0x1b
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT                                          0x1c
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT                                          0x1d
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT                                          0x1e
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT                                          0x1f
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__CP0_MASK                                                   0x00000001L
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__CP1_MASK                                                   0x00000002L
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__CP2_MASK                                                   0x00000004L
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__CP3_MASK                                                   0x00000008L
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__CP4_MASK                                                   0x00000010L
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__CP5_MASK                                                   0x00000020L
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__CP6_MASK                                                   0x00000040L
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__CP7_MASK                                                   0x00000080L
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__CP8_MASK                                                   0x00000100L
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__CP9_MASK                                                   0x00000200L
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__SDMA0_MASK                                                 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__SDMA1_MASK                                                 0x00000800L
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK                                             0x00001000L
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK                                             0x00002000L
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK                                             0x00004000L
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK                                             0x00008000L
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK                                             0x00010000L
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK                                             0x00020000L
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK                                             0x00040000L
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK                                             0x00080000L
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK                                             0x00100000L
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK                                             0x00200000L
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK                                            0x00400000L
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK                                            0x00800000L
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK                                            0x01000000L
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK                                            0x02000000L
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK                                            0x04000000L
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK                                            0x08000000L
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK                                            0x10000000L
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK                                            0x20000000L
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK                                            0x40000000L
+#define BIF_BX_DEV0_EPF0_VF4_0_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK                                            0x80000000L
+//BIF_BX_DEV0_EPF0_VF4_0_BIF_TRANS_PENDING
+#define BIF_BX_DEV0_EPF0_VF4_0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT                                0x0
+#define BIF_BX_DEV0_EPF0_VF4_0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT                                0x1
+#define BIF_BX_DEV0_EPF0_VF4_0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK                                  0x00000001L
+#define BIF_BX_DEV0_EPF0_VF4_0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK                                  0x00000002L
+//BIF_BX_DEV0_EPF0_VF4_0_NBIF_GFX_ADDR_LUT_BYPASS
+#define BIF_BX_DEV0_EPF0_VF4_0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT                                    0x0
+#define BIF_BX_DEV0_EPF0_VF4_0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK                                      0x00000001L
+//BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_CONTROL
+#define BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT                                          0x0
+#define BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT                                            0x1
+#define BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT                                          0x8
+#define BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT                                            0x9
+#define BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_CONTROL__TRN_MSG_VALID_MASK                                            0x00000001L
+#define BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_CONTROL__TRN_MSG_ACK_MASK                                              0x00000002L
+#define BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_CONTROL__RCV_MSG_VALID_MASK                                            0x00000100L
+#define BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_CONTROL__RCV_MSG_ACK_MASK                                              0x00000200L
+//BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_INT_CNTL
+#define BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT                                          0x0
+#define BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT                                            0x1
+#define BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_INT_CNTL__VALID_INT_EN_MASK                                            0x00000001L
+#define BIF_BX_DEV0_EPF0_VF4_0_MAILBOX_INT_CNTL__ACK_INT_EN_MASK                                              0x00000002L
+//BIF_BX_DEV0_EPF0_VF4_0_BIF_VMHV_MAILBOX
+#define BIF_BX_DEV0_EPF0_VF4_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT                          0x0
+#define BIF_BX_DEV0_EPF0_VF4_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT                        0x1
+#define BIF_BX_DEV0_EPF0_VF4_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT                             0x8
+#define BIF_BX_DEV0_EPF0_VF4_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT                            0xf
+#define BIF_BX_DEV0_EPF0_VF4_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT                             0x10
+#define BIF_BX_DEV0_EPF0_VF4_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT                            0x17
+#define BIF_BX_DEV0_EPF0_VF4_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT                              0x18
+#define BIF_BX_DEV0_EPF0_VF4_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT                              0x19
+#define BIF_BX_DEV0_EPF0_VF4_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK                            0x00000001L
+#define BIF_BX_DEV0_EPF0_VF4_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK                          0x00000002L
+#define BIF_BX_DEV0_EPF0_VF4_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK                               0x00000F00L
+#define BIF_BX_DEV0_EPF0_VF4_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK                              0x00008000L
+#define BIF_BX_DEV0_EPF0_VF4_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK                               0x000F0000L
+#define BIF_BX_DEV0_EPF0_VF4_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK                              0x00800000L
+#define BIF_BX_DEV0_EPF0_VF4_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK                                0x01000000L
+#define BIF_BX_DEV0_EPF0_VF4_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK                                0x02000000L
+//BIF_BX_DEV0_EPF0_VF4_0_PARTITION_COMPUTE_CAP
+#define BIF_BX_DEV0_EPF0_VF4_0_PARTITION_COMPUTE_CAP__SPX_SUPPORT__SHIFT                                      0x0
+#define BIF_BX_DEV0_EPF0_VF4_0_PARTITION_COMPUTE_CAP__DPX_SUPPORT__SHIFT                                      0x1
+#define BIF_BX_DEV0_EPF0_VF4_0_PARTITION_COMPUTE_CAP__TPX_SUPPORT__SHIFT                                      0x2
+#define BIF_BX_DEV0_EPF0_VF4_0_PARTITION_COMPUTE_CAP__QPX_SUPPORT__SHIFT                                      0x3
+#define BIF_BX_DEV0_EPF0_VF4_0_PARTITION_COMPUTE_CAP__CPX_SUPPORT__SHIFT                                      0x4
+#define BIF_BX_DEV0_EPF0_VF4_0_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY__SHIFT                                 0xa
+#define BIF_BX_DEV0_EPF0_VF4_0_PARTITION_COMPUTE_CAP__SPX_SUPPORT_MASK                                        0x00000001L
+#define BIF_BX_DEV0_EPF0_VF4_0_PARTITION_COMPUTE_CAP__DPX_SUPPORT_MASK                                        0x00000002L
+#define BIF_BX_DEV0_EPF0_VF4_0_PARTITION_COMPUTE_CAP__TPX_SUPPORT_MASK                                        0x00000004L
+#define BIF_BX_DEV0_EPF0_VF4_0_PARTITION_COMPUTE_CAP__QPX_SUPPORT_MASK                                        0x00000008L
+#define BIF_BX_DEV0_EPF0_VF4_0_PARTITION_COMPUTE_CAP__CPX_SUPPORT_MASK                                        0x00000010L
+#define BIF_BX_DEV0_EPF0_VF4_0_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY_MASK                                   0x0003FC00L
+//BIF_BX_DEV0_EPF0_VF4_0_PARTITION_MEM_CAP
+#define BIF_BX_DEV0_EPF0_VF4_0_PARTITION_MEM_CAP__NPS1_SUPPORT__SHIFT                                         0x0
+#define BIF_BX_DEV0_EPF0_VF4_0_PARTITION_MEM_CAP__NPS2_SUPPORT__SHIFT                                         0x1
+#define BIF_BX_DEV0_EPF0_VF4_0_PARTITION_MEM_CAP__NPS3_SUPPORT__SHIFT                                         0x2
+#define BIF_BX_DEV0_EPF0_VF4_0_PARTITION_MEM_CAP__NPS4_SUPPORT__SHIFT                                         0x3
+#define BIF_BX_DEV0_EPF0_VF4_0_PARTITION_MEM_CAP__NPS6_SUPPORT__SHIFT                                         0x5
+#define BIF_BX_DEV0_EPF0_VF4_0_PARTITION_MEM_CAP__NPS8_SUPPORT__SHIFT                                         0x7
+#define BIF_BX_DEV0_EPF0_VF4_0_PARTITION_MEM_CAP__NPS1_SUPPORT_MASK                                           0x00000001L
+#define BIF_BX_DEV0_EPF0_VF4_0_PARTITION_MEM_CAP__NPS2_SUPPORT_MASK                                           0x00000002L
+#define BIF_BX_DEV0_EPF0_VF4_0_PARTITION_MEM_CAP__NPS3_SUPPORT_MASK                                           0x00000004L
+#define BIF_BX_DEV0_EPF0_VF4_0_PARTITION_MEM_CAP__NPS4_SUPPORT_MASK                                           0x00000008L
+#define BIF_BX_DEV0_EPF0_VF4_0_PARTITION_MEM_CAP__NPS6_SUPPORT_MASK                                           0x00000020L
+#define BIF_BX_DEV0_EPF0_VF4_0_PARTITION_MEM_CAP__NPS8_SUPPORT_MASK                                           0x00000080L
+//BIF_BX_DEV0_EPF0_VF4_0_PARTITION_COMPUTE_STATUS
+#define BIF_BX_DEV0_EPF0_VF4_0_PARTITION_COMPUTE_STATUS__PARTITION_MODE__SHIFT                                0x4
+#define BIF_BX_DEV0_EPF0_VF4_0_PARTITION_COMPUTE_STATUS__PARTITION_MODE_MASK                                  0x000000F0L
+//BIF_BX_DEV0_EPF0_VF4_0_PARTITION_MEM_STATUS
+#define BIF_BX_DEV0_EPF0_VF4_0_PARTITION_MEM_STATUS__CHANGE_STATUS__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF4_0_PARTITION_MEM_STATUS__NPS_MODE__SHIFT                                          0x4
+#define BIF_BX_DEV0_EPF0_VF4_0_PARTITION_MEM_STATUS__CHANGE_STATUS_MASK                                       0x0000000FL
+#define BIF_BX_DEV0_EPF0_VF4_0_PARTITION_MEM_STATUS__NPS_MODE_MASK                                            0x00000FF0L
+
+
+// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf4_SYSPFVFDEC
+//BIF_BX_DEV0_EPF0_VF4_0_MM_INDEX
+#define BIF_BX_DEV0_EPF0_VF4_0_MM_INDEX__MM_OFFSET__SHIFT                                                     0x0
+#define BIF_BX_DEV0_EPF0_VF4_0_MM_INDEX__MM_APER__SHIFT                                                       0x1f
+#define BIF_BX_DEV0_EPF0_VF4_0_MM_INDEX__MM_OFFSET_MASK                                                       0x7FFFFFFFL
+#define BIF_BX_DEV0_EPF0_VF4_0_MM_INDEX__MM_APER_MASK                                                         0x80000000L
+//BIF_BX_DEV0_EPF0_VF4_0_MM_DATA
+#define BIF_BX_DEV0_EPF0_VF4_0_MM_DATA__MM_DATA__SHIFT                                                        0x0
+#define BIF_BX_DEV0_EPF0_VF4_0_MM_DATA__MM_DATA_MASK                                                          0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF4_0_MM_INDEX_HI
+#define BIF_BX_DEV0_EPF0_VF4_0_MM_INDEX_HI__MM_OFFSET_HI__SHIFT                                               0x0
+#define BIF_BX_DEV0_EPF0_VF4_0_MM_INDEX_HI__MM_OFFSET_HI_MASK                                                 0xFFFFFFFFL
+
+
+// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf4_BIFPFVFDEC1:1
+//BIF_BX_DEV0_EPF0_VF4_1_BIF_BME_STATUS
+#define BIF_BX_DEV0_EPF0_VF4_1_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT                                          0x0
+#define BIF_BX_DEV0_EPF0_VF4_1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT                                    0x10
+#define BIF_BX_DEV0_EPF0_VF4_1_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK                                            0x00000001L
+#define BIF_BX_DEV0_EPF0_VF4_1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK                                      0x00010000L
+//BIF_BX_DEV0_EPF0_VF4_1_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_DEV0_EPF0_VF4_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT                                    0x0
+#define BIF_BX_DEV0_EPF0_VF4_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT                                 0x1
+#define BIF_BX_DEV0_EPF0_VF4_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT                                    0x2
+#define BIF_BX_DEV0_EPF0_VF4_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT                                        0x3
+#define BIF_BX_DEV0_EPF0_VF4_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT                              0x10
+#define BIF_BX_DEV0_EPF0_VF4_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT                           0x11
+#define BIF_BX_DEV0_EPF0_VF4_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT                              0x12
+#define BIF_BX_DEV0_EPF0_VF4_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT                                  0x13
+#define BIF_BX_DEV0_EPF0_VF4_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK                                      0x00000001L
+#define BIF_BX_DEV0_EPF0_VF4_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK                                   0x00000002L
+#define BIF_BX_DEV0_EPF0_VF4_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK                                      0x00000004L
+#define BIF_BX_DEV0_EPF0_VF4_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK                                          0x00000008L
+#define BIF_BX_DEV0_EPF0_VF4_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK                                0x00010000L
+#define BIF_BX_DEV0_EPF0_VF4_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK                             0x00020000L
+#define BIF_BX_DEV0_EPF0_VF4_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK                                0x00040000L
+#define BIF_BX_DEV0_EPF0_VF4_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK                                    0x00080000L
+//BIF_BX_DEV0_EPF0_VF4_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_DEV0_EPF0_VF4_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT  0x0
+#define BIF_BX_DEV0_EPF0_VF4_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK  0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF4_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_DEV0_EPF0_VF4_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT  0x0
+#define BIF_BX_DEV0_EPF0_VF4_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK  0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF4_1_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_DEV0_EPF0_VF4_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT          0x0
+#define BIF_BX_DEV0_EPF0_VF4_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT        0x1
+#define BIF_BX_DEV0_EPF0_VF4_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT        0x8
+#define BIF_BX_DEV0_EPF0_VF4_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK            0x00000001L
+#define BIF_BX_DEV0_EPF0_VF4_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK          0x00000002L
+#define BIF_BX_DEV0_EPF0_VF4_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK          0x000FFF00L
+//BIF_BX_DEV0_EPF0_VF4_1_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF4_1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT                        0x0
+#define BIF_BX_DEV0_EPF0_VF4_1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK                          0x00000001L
+//BIF_BX_DEV0_EPF0_VF4_1_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF4_1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT                        0x0
+#define BIF_BX_DEV0_EPF0_VF4_1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK                          0x00000001L
+//BIF_BX_DEV0_EPF0_VF4_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL
+#define BIF_BX_DEV0_EPF0_VF4_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT              0x0
+#define BIF_BX_DEV0_EPF0_VF4_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK                0x00000001L
+//BIF_BX_DEV0_EPF0_VF4_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL
+#define BIF_BX_DEV0_EPF0_VF4_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT    0x0
+#define BIF_BX_DEV0_EPF0_VF4_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK      0x00000001L
+//BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__CP0__SHIFT                                                  0x0
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__CP1__SHIFT                                                  0x1
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__CP2__SHIFT                                                  0x2
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__CP3__SHIFT                                                  0x3
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__CP4__SHIFT                                                  0x4
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__CP5__SHIFT                                                  0x5
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__CP6__SHIFT                                                  0x6
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__CP7__SHIFT                                                  0x7
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__CP8__SHIFT                                                  0x8
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__CP9__SHIFT                                                  0x9
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT                                                0xa
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT                                                0xb
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT                                            0xc
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT                                            0xd
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT                                            0xe
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT                                            0xf
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT                                            0x10
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT                                            0x11
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT                                            0x12
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT                                            0x13
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT                                            0x14
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT                                            0x15
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT                                           0x16
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT                                           0x17
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT                                           0x18
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT                                           0x19
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT                                           0x1a
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT                                           0x1b
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT                                           0x1c
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT                                           0x1d
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT                                           0x1e
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT                                           0x1f
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__CP0_MASK                                                    0x00000001L
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__CP1_MASK                                                    0x00000002L
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__CP2_MASK                                                    0x00000004L
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__CP3_MASK                                                    0x00000008L
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__CP4_MASK                                                    0x00000010L
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__CP5_MASK                                                    0x00000020L
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__CP6_MASK                                                    0x00000040L
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__CP7_MASK                                                    0x00000080L
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__CP8_MASK                                                    0x00000100L
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__CP9_MASK                                                    0x00000200L
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__SDMA0_MASK                                                  0x00000400L
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__SDMA1_MASK                                                  0x00000800L
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK                                              0x00001000L
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK                                              0x00002000L
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK                                              0x00004000L
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK                                              0x00008000L
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK                                              0x00010000L
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK                                              0x00020000L
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK                                              0x00040000L
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK                                              0x00080000L
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK                                              0x00100000L
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK                                              0x00200000L
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK                                             0x00400000L
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK                                             0x00800000L
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK                                             0x01000000L
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK                                             0x02000000L
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK                                             0x04000000L
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK                                             0x08000000L
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK                                             0x10000000L
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK                                             0x20000000L
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK                                             0x40000000L
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK                                             0x80000000L
+//BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__CP0__SHIFT                                                 0x0
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__CP1__SHIFT                                                 0x1
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__CP2__SHIFT                                                 0x2
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__CP3__SHIFT                                                 0x3
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__CP4__SHIFT                                                 0x4
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__CP5__SHIFT                                                 0x5
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__CP6__SHIFT                                                 0x6
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__CP7__SHIFT                                                 0x7
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__CP8__SHIFT                                                 0x8
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__CP9__SHIFT                                                 0x9
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT                                               0xa
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT                                               0xb
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT                                           0xc
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT                                           0xd
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT                                           0xe
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT                                           0xf
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT                                           0x10
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT                                           0x11
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT                                           0x12
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT                                           0x13
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT                                           0x14
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT                                           0x15
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT                                          0x16
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT                                          0x17
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT                                          0x18
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT                                          0x19
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT                                          0x1a
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT                                          0x1b
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT                                          0x1c
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT                                          0x1d
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT                                          0x1e
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT                                          0x1f
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__CP0_MASK                                                   0x00000001L
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__CP1_MASK                                                   0x00000002L
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__CP2_MASK                                                   0x00000004L
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__CP3_MASK                                                   0x00000008L
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__CP4_MASK                                                   0x00000010L
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__CP5_MASK                                                   0x00000020L
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__CP6_MASK                                                   0x00000040L
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__CP7_MASK                                                   0x00000080L
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__CP8_MASK                                                   0x00000100L
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__CP9_MASK                                                   0x00000200L
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__SDMA0_MASK                                                 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__SDMA1_MASK                                                 0x00000800L
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK                                             0x00001000L
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK                                             0x00002000L
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK                                             0x00004000L
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK                                             0x00008000L
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK                                             0x00010000L
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK                                             0x00020000L
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK                                             0x00040000L
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK                                             0x00080000L
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK                                             0x00100000L
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK                                             0x00200000L
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK                                            0x00400000L
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK                                            0x00800000L
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK                                            0x01000000L
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK                                            0x02000000L
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK                                            0x04000000L
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK                                            0x08000000L
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK                                            0x10000000L
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK                                            0x20000000L
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK                                            0x40000000L
+#define BIF_BX_DEV0_EPF0_VF4_1_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK                                            0x80000000L
+//BIF_BX_DEV0_EPF0_VF4_1_BIF_TRANS_PENDING
+#define BIF_BX_DEV0_EPF0_VF4_1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT                                0x0
+#define BIF_BX_DEV0_EPF0_VF4_1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT                                0x1
+#define BIF_BX_DEV0_EPF0_VF4_1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK                                  0x00000001L
+#define BIF_BX_DEV0_EPF0_VF4_1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK                                  0x00000002L
+//BIF_BX_DEV0_EPF0_VF4_1_NBIF_GFX_ADDR_LUT_BYPASS
+#define BIF_BX_DEV0_EPF0_VF4_1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT                                    0x0
+#define BIF_BX_DEV0_EPF0_VF4_1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK                                      0x00000001L
+//BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_CONTROL
+#define BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT                                          0x0
+#define BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT                                            0x1
+#define BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT                                          0x8
+#define BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT                                            0x9
+#define BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_CONTROL__TRN_MSG_VALID_MASK                                            0x00000001L
+#define BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_CONTROL__TRN_MSG_ACK_MASK                                              0x00000002L
+#define BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_CONTROL__RCV_MSG_VALID_MASK                                            0x00000100L
+#define BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_CONTROL__RCV_MSG_ACK_MASK                                              0x00000200L
+//BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_INT_CNTL
+#define BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT                                          0x0
+#define BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT                                            0x1
+#define BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_INT_CNTL__VALID_INT_EN_MASK                                            0x00000001L
+#define BIF_BX_DEV0_EPF0_VF4_1_MAILBOX_INT_CNTL__ACK_INT_EN_MASK                                              0x00000002L
+//BIF_BX_DEV0_EPF0_VF4_1_BIF_VMHV_MAILBOX
+#define BIF_BX_DEV0_EPF0_VF4_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT                          0x0
+#define BIF_BX_DEV0_EPF0_VF4_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT                        0x1
+#define BIF_BX_DEV0_EPF0_VF4_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT                             0x8
+#define BIF_BX_DEV0_EPF0_VF4_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT                            0xf
+#define BIF_BX_DEV0_EPF0_VF4_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT                             0x10
+#define BIF_BX_DEV0_EPF0_VF4_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT                            0x17
+#define BIF_BX_DEV0_EPF0_VF4_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT                              0x18
+#define BIF_BX_DEV0_EPF0_VF4_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT                              0x19
+#define BIF_BX_DEV0_EPF0_VF4_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK                            0x00000001L
+#define BIF_BX_DEV0_EPF0_VF4_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK                          0x00000002L
+#define BIF_BX_DEV0_EPF0_VF4_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK                               0x00000F00L
+#define BIF_BX_DEV0_EPF0_VF4_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK                              0x00008000L
+#define BIF_BX_DEV0_EPF0_VF4_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK                               0x000F0000L
+#define BIF_BX_DEV0_EPF0_VF4_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK                              0x00800000L
+#define BIF_BX_DEV0_EPF0_VF4_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK                                0x01000000L
+#define BIF_BX_DEV0_EPF0_VF4_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK                                0x02000000L
+//BIF_BX_DEV0_EPF0_VF4_1_PARTITION_COMPUTE_CAP
+#define BIF_BX_DEV0_EPF0_VF4_1_PARTITION_COMPUTE_CAP__SPX_SUPPORT__SHIFT                                      0x0
+#define BIF_BX_DEV0_EPF0_VF4_1_PARTITION_COMPUTE_CAP__DPX_SUPPORT__SHIFT                                      0x1
+#define BIF_BX_DEV0_EPF0_VF4_1_PARTITION_COMPUTE_CAP__TPX_SUPPORT__SHIFT                                      0x2
+#define BIF_BX_DEV0_EPF0_VF4_1_PARTITION_COMPUTE_CAP__QPX_SUPPORT__SHIFT                                      0x3
+#define BIF_BX_DEV0_EPF0_VF4_1_PARTITION_COMPUTE_CAP__CPX_SUPPORT__SHIFT                                      0x4
+#define BIF_BX_DEV0_EPF0_VF4_1_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY__SHIFT                                 0xa
+#define BIF_BX_DEV0_EPF0_VF4_1_PARTITION_COMPUTE_CAP__SPX_SUPPORT_MASK                                        0x00000001L
+#define BIF_BX_DEV0_EPF0_VF4_1_PARTITION_COMPUTE_CAP__DPX_SUPPORT_MASK                                        0x00000002L
+#define BIF_BX_DEV0_EPF0_VF4_1_PARTITION_COMPUTE_CAP__TPX_SUPPORT_MASK                                        0x00000004L
+#define BIF_BX_DEV0_EPF0_VF4_1_PARTITION_COMPUTE_CAP__QPX_SUPPORT_MASK                                        0x00000008L
+#define BIF_BX_DEV0_EPF0_VF4_1_PARTITION_COMPUTE_CAP__CPX_SUPPORT_MASK                                        0x00000010L
+#define BIF_BX_DEV0_EPF0_VF4_1_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY_MASK                                   0x0003FC00L
+//BIF_BX_DEV0_EPF0_VF4_1_PARTITION_MEM_CAP
+#define BIF_BX_DEV0_EPF0_VF4_1_PARTITION_MEM_CAP__NPS1_SUPPORT__SHIFT                                         0x0
+#define BIF_BX_DEV0_EPF0_VF4_1_PARTITION_MEM_CAP__NPS2_SUPPORT__SHIFT                                         0x1
+#define BIF_BX_DEV0_EPF0_VF4_1_PARTITION_MEM_CAP__NPS3_SUPPORT__SHIFT                                         0x2
+#define BIF_BX_DEV0_EPF0_VF4_1_PARTITION_MEM_CAP__NPS4_SUPPORT__SHIFT                                         0x3
+#define BIF_BX_DEV0_EPF0_VF4_1_PARTITION_MEM_CAP__NPS6_SUPPORT__SHIFT                                         0x5
+#define BIF_BX_DEV0_EPF0_VF4_1_PARTITION_MEM_CAP__NPS8_SUPPORT__SHIFT                                         0x7
+#define BIF_BX_DEV0_EPF0_VF4_1_PARTITION_MEM_CAP__NPS1_SUPPORT_MASK                                           0x00000001L
+#define BIF_BX_DEV0_EPF0_VF4_1_PARTITION_MEM_CAP__NPS2_SUPPORT_MASK                                           0x00000002L
+#define BIF_BX_DEV0_EPF0_VF4_1_PARTITION_MEM_CAP__NPS3_SUPPORT_MASK                                           0x00000004L
+#define BIF_BX_DEV0_EPF0_VF4_1_PARTITION_MEM_CAP__NPS4_SUPPORT_MASK                                           0x00000008L
+#define BIF_BX_DEV0_EPF0_VF4_1_PARTITION_MEM_CAP__NPS6_SUPPORT_MASK                                           0x00000020L
+#define BIF_BX_DEV0_EPF0_VF4_1_PARTITION_MEM_CAP__NPS8_SUPPORT_MASK                                           0x00000080L
+//BIF_BX_DEV0_EPF0_VF4_1_PARTITION_COMPUTE_STATUS
+#define BIF_BX_DEV0_EPF0_VF4_1_PARTITION_COMPUTE_STATUS__PARTITION_MODE__SHIFT                                0x4
+#define BIF_BX_DEV0_EPF0_VF4_1_PARTITION_COMPUTE_STATUS__PARTITION_MODE_MASK                                  0x000000F0L
+//BIF_BX_DEV0_EPF0_VF4_1_PARTITION_MEM_STATUS
+#define BIF_BX_DEV0_EPF0_VF4_1_PARTITION_MEM_STATUS__CHANGE_STATUS__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF4_1_PARTITION_MEM_STATUS__NPS_MODE__SHIFT                                          0x4
+#define BIF_BX_DEV0_EPF0_VF4_1_PARTITION_MEM_STATUS__CHANGE_STATUS_MASK                                       0x0000000FL
+#define BIF_BX_DEV0_EPF0_VF4_1_PARTITION_MEM_STATUS__NPS_MODE_MASK                                            0x00000FF0L
+
+
+// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf4_SYSPFVFDEC:1
+//BIF_BX_DEV0_EPF0_VF4_1_MM_INDEX
+#define BIF_BX_DEV0_EPF0_VF4_1_MM_INDEX__MM_OFFSET__SHIFT                                                     0x0
+#define BIF_BX_DEV0_EPF0_VF4_1_MM_INDEX__MM_APER__SHIFT                                                       0x1f
+#define BIF_BX_DEV0_EPF0_VF4_1_MM_INDEX__MM_OFFSET_MASK                                                       0x7FFFFFFFL
+#define BIF_BX_DEV0_EPF0_VF4_1_MM_INDEX__MM_APER_MASK                                                         0x80000000L
+//BIF_BX_DEV0_EPF0_VF4_1_MM_DATA
+#define BIF_BX_DEV0_EPF0_VF4_1_MM_DATA__MM_DATA__SHIFT                                                        0x0
+#define BIF_BX_DEV0_EPF0_VF4_1_MM_DATA__MM_DATA_MASK                                                          0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF4_1_MM_INDEX_HI
+#define BIF_BX_DEV0_EPF0_VF4_1_MM_INDEX_HI__MM_OFFSET_HI__SHIFT                                               0x0
+#define BIF_BX_DEV0_EPF0_VF4_1_MM_INDEX_HI__MM_OFFSET_HI_MASK                                                 0xFFFFFFFFL
+
+
+// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf4_BIFPFVFDEC1
+//RCC_DEV0_EPF0_VF4_RCC_ERR_LOG
+#define RCC_DEV0_EPF0_VF4_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT                              0x0
+#define RCC_DEV0_EPF0_VF4_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT                                     0x1
+#define RCC_DEV0_EPF0_VF4_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK                                0x00000001L
+#define RCC_DEV0_EPF0_VF4_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK                                       0x00000002L
+//RCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN
+#define RCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT                                   0x0
+#define RCC_DEV0_EPF0_VF4_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK                                     0x00000001L
+//RCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE
+#define RCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_VF4_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED
+#define RCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT                                         0x0
+#define RCC_DEV0_EPF0_VF4_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK                                           0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER
+#define RCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT                                     0x0
+#define RCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT                                          0x1f
+#define RCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK                                       0x00000001L
+#define RCC_DEV0_EPF0_VF4_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK                                            0x80000000L
+
+
+// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf4_BIFDEC2
+//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT                                           0x2
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT                                              0x0
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK                                                0x00000001L
+//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT                                           0x2
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT                                              0x0
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK                                                0x00000001L
+//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT                                           0x2
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT                                              0x0
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK                                                0x00000001L
+//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_LO
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT                                           0x2
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_HI
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_MSG_DATA
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_CONTROL
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT                                              0x0
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK                                                0x00000001L
+//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT4_ADDR_LO
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT4_ADDR_LO__MSG_ADDR_LO__SHIFT                                           0x2
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT4_ADDR_LO__MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT4_ADDR_HI
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT4_ADDR_HI__MSG_ADDR_HI__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT4_ADDR_HI__MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT4_MSG_DATA
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT4_MSG_DATA__MSG_DATA__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT4_MSG_DATA__MSG_DATA_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT4_CONTROL
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT4_CONTROL__MASK_BIT__SHIFT                                              0x0
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT4_CONTROL__MASK_BIT_MASK                                                0x00000001L
+//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT5_ADDR_LO
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT5_ADDR_LO__MSG_ADDR_LO__SHIFT                                           0x2
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT5_ADDR_LO__MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT5_ADDR_HI
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT5_ADDR_HI__MSG_ADDR_HI__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT5_ADDR_HI__MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT5_MSG_DATA
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT5_MSG_DATA__MSG_DATA__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT5_MSG_DATA__MSG_DATA_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT5_CONTROL
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT5_CONTROL__MASK_BIT__SHIFT                                              0x0
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT5_CONTROL__MASK_BIT_MASK                                                0x00000001L
+//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT6_ADDR_LO
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT6_ADDR_LO__MSG_ADDR_LO__SHIFT                                           0x2
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT6_ADDR_LO__MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT6_ADDR_HI
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT6_ADDR_HI__MSG_ADDR_HI__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT6_ADDR_HI__MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT6_MSG_DATA
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT6_MSG_DATA__MSG_DATA__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT6_MSG_DATA__MSG_DATA_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT6_CONTROL
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT6_CONTROL__MASK_BIT__SHIFT                                              0x0
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT6_CONTROL__MASK_BIT_MASK                                                0x00000001L
+//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT7_ADDR_LO
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT7_ADDR_LO__MSG_ADDR_LO__SHIFT                                           0x2
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT7_ADDR_LO__MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT7_ADDR_HI
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT7_ADDR_HI__MSG_ADDR_HI__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT7_ADDR_HI__MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT7_MSG_DATA
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT7_MSG_DATA__MSG_DATA__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT7_MSG_DATA__MSG_DATA_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT7_CONTROL
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT7_CONTROL__MASK_BIT__SHIFT                                              0x0
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT7_CONTROL__MASK_BIT_MASK                                                0x00000001L
+//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT8_ADDR_LO
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT8_ADDR_LO__MSG_ADDR_LO__SHIFT                                           0x2
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT8_ADDR_LO__MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT8_ADDR_HI
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT8_ADDR_HI__MSG_ADDR_HI__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT8_ADDR_HI__MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT8_MSG_DATA
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT8_MSG_DATA__MSG_DATA__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT8_MSG_DATA__MSG_DATA_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF4_GFXMSIX_VECT8_CONTROL
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT8_CONTROL__MASK_BIT__SHIFT                                              0x0
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_VECT8_CONTROL__MASK_BIT_MASK                                                0x00000001L
+//RCC_DEV0_EPF0_VF4_GFXMSIX_PBA
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT                                             0x1
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK                                               0x00000001L
+#define RCC_DEV0_EPF0_VF4_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK                                               0x00000002L
+
+
+// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf5_BIFPFVFDEC1
+//BIF_BX_DEV0_EPF0_VF5_0_BIF_BME_STATUS
+#define BIF_BX_DEV0_EPF0_VF5_0_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT                                          0x0
+#define BIF_BX_DEV0_EPF0_VF5_0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT                                    0x10
+#define BIF_BX_DEV0_EPF0_VF5_0_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK                                            0x00000001L
+#define BIF_BX_DEV0_EPF0_VF5_0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK                                      0x00010000L
+//BIF_BX_DEV0_EPF0_VF5_0_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_DEV0_EPF0_VF5_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT                                    0x0
+#define BIF_BX_DEV0_EPF0_VF5_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT                                 0x1
+#define BIF_BX_DEV0_EPF0_VF5_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT                                    0x2
+#define BIF_BX_DEV0_EPF0_VF5_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT                                        0x3
+#define BIF_BX_DEV0_EPF0_VF5_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT                              0x10
+#define BIF_BX_DEV0_EPF0_VF5_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT                           0x11
+#define BIF_BX_DEV0_EPF0_VF5_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT                              0x12
+#define BIF_BX_DEV0_EPF0_VF5_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT                                  0x13
+#define BIF_BX_DEV0_EPF0_VF5_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK                                      0x00000001L
+#define BIF_BX_DEV0_EPF0_VF5_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK                                   0x00000002L
+#define BIF_BX_DEV0_EPF0_VF5_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK                                      0x00000004L
+#define BIF_BX_DEV0_EPF0_VF5_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK                                          0x00000008L
+#define BIF_BX_DEV0_EPF0_VF5_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK                                0x00010000L
+#define BIF_BX_DEV0_EPF0_VF5_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK                             0x00020000L
+#define BIF_BX_DEV0_EPF0_VF5_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK                                0x00040000L
+#define BIF_BX_DEV0_EPF0_VF5_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK                                    0x00080000L
+//BIF_BX_DEV0_EPF0_VF5_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_DEV0_EPF0_VF5_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT  0x0
+#define BIF_BX_DEV0_EPF0_VF5_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK  0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF5_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_DEV0_EPF0_VF5_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT  0x0
+#define BIF_BX_DEV0_EPF0_VF5_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK  0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF5_0_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_DEV0_EPF0_VF5_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT          0x0
+#define BIF_BX_DEV0_EPF0_VF5_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT        0x1
+#define BIF_BX_DEV0_EPF0_VF5_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT        0x8
+#define BIF_BX_DEV0_EPF0_VF5_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK            0x00000001L
+#define BIF_BX_DEV0_EPF0_VF5_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK          0x00000002L
+#define BIF_BX_DEV0_EPF0_VF5_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK          0x000FFF00L
+//BIF_BX_DEV0_EPF0_VF5_0_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF5_0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT                        0x0
+#define BIF_BX_DEV0_EPF0_VF5_0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK                          0x00000001L
+//BIF_BX_DEV0_EPF0_VF5_0_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF5_0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT                        0x0
+#define BIF_BX_DEV0_EPF0_VF5_0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK                          0x00000001L
+//BIF_BX_DEV0_EPF0_VF5_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL
+#define BIF_BX_DEV0_EPF0_VF5_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT              0x0
+#define BIF_BX_DEV0_EPF0_VF5_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK                0x00000001L
+//BIF_BX_DEV0_EPF0_VF5_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL
+#define BIF_BX_DEV0_EPF0_VF5_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT    0x0
+#define BIF_BX_DEV0_EPF0_VF5_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK      0x00000001L
+//BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__CP0__SHIFT                                                  0x0
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__CP1__SHIFT                                                  0x1
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__CP2__SHIFT                                                  0x2
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__CP3__SHIFT                                                  0x3
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__CP4__SHIFT                                                  0x4
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__CP5__SHIFT                                                  0x5
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__CP6__SHIFT                                                  0x6
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__CP7__SHIFT                                                  0x7
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__CP8__SHIFT                                                  0x8
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__CP9__SHIFT                                                  0x9
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT                                                0xa
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT                                                0xb
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT                                            0xc
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT                                            0xd
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT                                            0xe
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT                                            0xf
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT                                            0x10
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT                                            0x11
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT                                            0x12
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT                                            0x13
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT                                            0x14
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT                                            0x15
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT                                           0x16
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT                                           0x17
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT                                           0x18
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT                                           0x19
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT                                           0x1a
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT                                           0x1b
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT                                           0x1c
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT                                           0x1d
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT                                           0x1e
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT                                           0x1f
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__CP0_MASK                                                    0x00000001L
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__CP1_MASK                                                    0x00000002L
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__CP2_MASK                                                    0x00000004L
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__CP3_MASK                                                    0x00000008L
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__CP4_MASK                                                    0x00000010L
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__CP5_MASK                                                    0x00000020L
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__CP6_MASK                                                    0x00000040L
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__CP7_MASK                                                    0x00000080L
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__CP8_MASK                                                    0x00000100L
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__CP9_MASK                                                    0x00000200L
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__SDMA0_MASK                                                  0x00000400L
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__SDMA1_MASK                                                  0x00000800L
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK                                              0x00001000L
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK                                              0x00002000L
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK                                              0x00004000L
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK                                              0x00008000L
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK                                              0x00010000L
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK                                              0x00020000L
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK                                              0x00040000L
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK                                              0x00080000L
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK                                              0x00100000L
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK                                              0x00200000L
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK                                             0x00400000L
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK                                             0x00800000L
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK                                             0x01000000L
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK                                             0x02000000L
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK                                             0x04000000L
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK                                             0x08000000L
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK                                             0x10000000L
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK                                             0x20000000L
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK                                             0x40000000L
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK                                             0x80000000L
+//BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__CP0__SHIFT                                                 0x0
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__CP1__SHIFT                                                 0x1
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__CP2__SHIFT                                                 0x2
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__CP3__SHIFT                                                 0x3
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__CP4__SHIFT                                                 0x4
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__CP5__SHIFT                                                 0x5
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__CP6__SHIFT                                                 0x6
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__CP7__SHIFT                                                 0x7
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__CP8__SHIFT                                                 0x8
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__CP9__SHIFT                                                 0x9
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT                                               0xa
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT                                               0xb
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT                                           0xc
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT                                           0xd
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT                                           0xe
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT                                           0xf
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT                                           0x10
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT                                           0x11
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT                                           0x12
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT                                           0x13
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT                                           0x14
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT                                           0x15
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT                                          0x16
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT                                          0x17
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT                                          0x18
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT                                          0x19
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT                                          0x1a
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT                                          0x1b
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT                                          0x1c
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT                                          0x1d
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT                                          0x1e
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT                                          0x1f
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__CP0_MASK                                                   0x00000001L
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__CP1_MASK                                                   0x00000002L
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__CP2_MASK                                                   0x00000004L
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__CP3_MASK                                                   0x00000008L
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__CP4_MASK                                                   0x00000010L
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__CP5_MASK                                                   0x00000020L
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__CP6_MASK                                                   0x00000040L
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__CP7_MASK                                                   0x00000080L
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__CP8_MASK                                                   0x00000100L
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__CP9_MASK                                                   0x00000200L
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__SDMA0_MASK                                                 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__SDMA1_MASK                                                 0x00000800L
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK                                             0x00001000L
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK                                             0x00002000L
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK                                             0x00004000L
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK                                             0x00008000L
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK                                             0x00010000L
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK                                             0x00020000L
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK                                             0x00040000L
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK                                             0x00080000L
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK                                             0x00100000L
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK                                             0x00200000L
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK                                            0x00400000L
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK                                            0x00800000L
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK                                            0x01000000L
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK                                            0x02000000L
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK                                            0x04000000L
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK                                            0x08000000L
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK                                            0x10000000L
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK                                            0x20000000L
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK                                            0x40000000L
+#define BIF_BX_DEV0_EPF0_VF5_0_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK                                            0x80000000L
+//BIF_BX_DEV0_EPF0_VF5_0_BIF_TRANS_PENDING
+#define BIF_BX_DEV0_EPF0_VF5_0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT                                0x0
+#define BIF_BX_DEV0_EPF0_VF5_0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT                                0x1
+#define BIF_BX_DEV0_EPF0_VF5_0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK                                  0x00000001L
+#define BIF_BX_DEV0_EPF0_VF5_0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK                                  0x00000002L
+//BIF_BX_DEV0_EPF0_VF5_0_NBIF_GFX_ADDR_LUT_BYPASS
+#define BIF_BX_DEV0_EPF0_VF5_0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT                                    0x0
+#define BIF_BX_DEV0_EPF0_VF5_0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK                                      0x00000001L
+//BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_CONTROL
+#define BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT                                          0x0
+#define BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT                                            0x1
+#define BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT                                          0x8
+#define BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT                                            0x9
+#define BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_CONTROL__TRN_MSG_VALID_MASK                                            0x00000001L
+#define BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_CONTROL__TRN_MSG_ACK_MASK                                              0x00000002L
+#define BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_CONTROL__RCV_MSG_VALID_MASK                                            0x00000100L
+#define BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_CONTROL__RCV_MSG_ACK_MASK                                              0x00000200L
+//BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_INT_CNTL
+#define BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT                                          0x0
+#define BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT                                            0x1
+#define BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_INT_CNTL__VALID_INT_EN_MASK                                            0x00000001L
+#define BIF_BX_DEV0_EPF0_VF5_0_MAILBOX_INT_CNTL__ACK_INT_EN_MASK                                              0x00000002L
+//BIF_BX_DEV0_EPF0_VF5_0_BIF_VMHV_MAILBOX
+#define BIF_BX_DEV0_EPF0_VF5_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT                          0x0
+#define BIF_BX_DEV0_EPF0_VF5_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT                        0x1
+#define BIF_BX_DEV0_EPF0_VF5_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT                             0x8
+#define BIF_BX_DEV0_EPF0_VF5_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT                            0xf
+#define BIF_BX_DEV0_EPF0_VF5_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT                             0x10
+#define BIF_BX_DEV0_EPF0_VF5_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT                            0x17
+#define BIF_BX_DEV0_EPF0_VF5_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT                              0x18
+#define BIF_BX_DEV0_EPF0_VF5_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT                              0x19
+#define BIF_BX_DEV0_EPF0_VF5_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK                            0x00000001L
+#define BIF_BX_DEV0_EPF0_VF5_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK                          0x00000002L
+#define BIF_BX_DEV0_EPF0_VF5_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK                               0x00000F00L
+#define BIF_BX_DEV0_EPF0_VF5_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK                              0x00008000L
+#define BIF_BX_DEV0_EPF0_VF5_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK                               0x000F0000L
+#define BIF_BX_DEV0_EPF0_VF5_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK                              0x00800000L
+#define BIF_BX_DEV0_EPF0_VF5_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK                                0x01000000L
+#define BIF_BX_DEV0_EPF0_VF5_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK                                0x02000000L
+//BIF_BX_DEV0_EPF0_VF5_0_PARTITION_COMPUTE_CAP
+#define BIF_BX_DEV0_EPF0_VF5_0_PARTITION_COMPUTE_CAP__SPX_SUPPORT__SHIFT                                      0x0
+#define BIF_BX_DEV0_EPF0_VF5_0_PARTITION_COMPUTE_CAP__DPX_SUPPORT__SHIFT                                      0x1
+#define BIF_BX_DEV0_EPF0_VF5_0_PARTITION_COMPUTE_CAP__TPX_SUPPORT__SHIFT                                      0x2
+#define BIF_BX_DEV0_EPF0_VF5_0_PARTITION_COMPUTE_CAP__QPX_SUPPORT__SHIFT                                      0x3
+#define BIF_BX_DEV0_EPF0_VF5_0_PARTITION_COMPUTE_CAP__CPX_SUPPORT__SHIFT                                      0x4
+#define BIF_BX_DEV0_EPF0_VF5_0_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY__SHIFT                                 0xa
+#define BIF_BX_DEV0_EPF0_VF5_0_PARTITION_COMPUTE_CAP__SPX_SUPPORT_MASK                                        0x00000001L
+#define BIF_BX_DEV0_EPF0_VF5_0_PARTITION_COMPUTE_CAP__DPX_SUPPORT_MASK                                        0x00000002L
+#define BIF_BX_DEV0_EPF0_VF5_0_PARTITION_COMPUTE_CAP__TPX_SUPPORT_MASK                                        0x00000004L
+#define BIF_BX_DEV0_EPF0_VF5_0_PARTITION_COMPUTE_CAP__QPX_SUPPORT_MASK                                        0x00000008L
+#define BIF_BX_DEV0_EPF0_VF5_0_PARTITION_COMPUTE_CAP__CPX_SUPPORT_MASK                                        0x00000010L
+#define BIF_BX_DEV0_EPF0_VF5_0_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY_MASK                                   0x0003FC00L
+//BIF_BX_DEV0_EPF0_VF5_0_PARTITION_MEM_CAP
+#define BIF_BX_DEV0_EPF0_VF5_0_PARTITION_MEM_CAP__NPS1_SUPPORT__SHIFT                                         0x0
+#define BIF_BX_DEV0_EPF0_VF5_0_PARTITION_MEM_CAP__NPS2_SUPPORT__SHIFT                                         0x1
+#define BIF_BX_DEV0_EPF0_VF5_0_PARTITION_MEM_CAP__NPS3_SUPPORT__SHIFT                                         0x2
+#define BIF_BX_DEV0_EPF0_VF5_0_PARTITION_MEM_CAP__NPS4_SUPPORT__SHIFT                                         0x3
+#define BIF_BX_DEV0_EPF0_VF5_0_PARTITION_MEM_CAP__NPS6_SUPPORT__SHIFT                                         0x5
+#define BIF_BX_DEV0_EPF0_VF5_0_PARTITION_MEM_CAP__NPS8_SUPPORT__SHIFT                                         0x7
+#define BIF_BX_DEV0_EPF0_VF5_0_PARTITION_MEM_CAP__NPS1_SUPPORT_MASK                                           0x00000001L
+#define BIF_BX_DEV0_EPF0_VF5_0_PARTITION_MEM_CAP__NPS2_SUPPORT_MASK                                           0x00000002L
+#define BIF_BX_DEV0_EPF0_VF5_0_PARTITION_MEM_CAP__NPS3_SUPPORT_MASK                                           0x00000004L
+#define BIF_BX_DEV0_EPF0_VF5_0_PARTITION_MEM_CAP__NPS4_SUPPORT_MASK                                           0x00000008L
+#define BIF_BX_DEV0_EPF0_VF5_0_PARTITION_MEM_CAP__NPS6_SUPPORT_MASK                                           0x00000020L
+#define BIF_BX_DEV0_EPF0_VF5_0_PARTITION_MEM_CAP__NPS8_SUPPORT_MASK                                           0x00000080L
+//BIF_BX_DEV0_EPF0_VF5_0_PARTITION_COMPUTE_STATUS
+#define BIF_BX_DEV0_EPF0_VF5_0_PARTITION_COMPUTE_STATUS__PARTITION_MODE__SHIFT                                0x4
+#define BIF_BX_DEV0_EPF0_VF5_0_PARTITION_COMPUTE_STATUS__PARTITION_MODE_MASK                                  0x000000F0L
+//BIF_BX_DEV0_EPF0_VF5_0_PARTITION_MEM_STATUS
+#define BIF_BX_DEV0_EPF0_VF5_0_PARTITION_MEM_STATUS__CHANGE_STATUS__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF5_0_PARTITION_MEM_STATUS__NPS_MODE__SHIFT                                          0x4
+#define BIF_BX_DEV0_EPF0_VF5_0_PARTITION_MEM_STATUS__CHANGE_STATUS_MASK                                       0x0000000FL
+#define BIF_BX_DEV0_EPF0_VF5_0_PARTITION_MEM_STATUS__NPS_MODE_MASK                                            0x00000FF0L
+
+
+// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf5_SYSPFVFDEC
+//BIF_BX_DEV0_EPF0_VF5_0_MM_INDEX
+#define BIF_BX_DEV0_EPF0_VF5_0_MM_INDEX__MM_OFFSET__SHIFT                                                     0x0
+#define BIF_BX_DEV0_EPF0_VF5_0_MM_INDEX__MM_APER__SHIFT                                                       0x1f
+#define BIF_BX_DEV0_EPF0_VF5_0_MM_INDEX__MM_OFFSET_MASK                                                       0x7FFFFFFFL
+#define BIF_BX_DEV0_EPF0_VF5_0_MM_INDEX__MM_APER_MASK                                                         0x80000000L
+//BIF_BX_DEV0_EPF0_VF5_0_MM_DATA
+#define BIF_BX_DEV0_EPF0_VF5_0_MM_DATA__MM_DATA__SHIFT                                                        0x0
+#define BIF_BX_DEV0_EPF0_VF5_0_MM_DATA__MM_DATA_MASK                                                          0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF5_0_MM_INDEX_HI
+#define BIF_BX_DEV0_EPF0_VF5_0_MM_INDEX_HI__MM_OFFSET_HI__SHIFT                                               0x0
+#define BIF_BX_DEV0_EPF0_VF5_0_MM_INDEX_HI__MM_OFFSET_HI_MASK                                                 0xFFFFFFFFL
+
+
+// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf5_BIFPFVFDEC1:1
+//BIF_BX_DEV0_EPF0_VF5_1_BIF_BME_STATUS
+#define BIF_BX_DEV0_EPF0_VF5_1_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT                                          0x0
+#define BIF_BX_DEV0_EPF0_VF5_1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT                                    0x10
+#define BIF_BX_DEV0_EPF0_VF5_1_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK                                            0x00000001L
+#define BIF_BX_DEV0_EPF0_VF5_1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK                                      0x00010000L
+//BIF_BX_DEV0_EPF0_VF5_1_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_DEV0_EPF0_VF5_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT                                    0x0
+#define BIF_BX_DEV0_EPF0_VF5_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT                                 0x1
+#define BIF_BX_DEV0_EPF0_VF5_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT                                    0x2
+#define BIF_BX_DEV0_EPF0_VF5_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT                                        0x3
+#define BIF_BX_DEV0_EPF0_VF5_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT                              0x10
+#define BIF_BX_DEV0_EPF0_VF5_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT                           0x11
+#define BIF_BX_DEV0_EPF0_VF5_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT                              0x12
+#define BIF_BX_DEV0_EPF0_VF5_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT                                  0x13
+#define BIF_BX_DEV0_EPF0_VF5_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK                                      0x00000001L
+#define BIF_BX_DEV0_EPF0_VF5_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK                                   0x00000002L
+#define BIF_BX_DEV0_EPF0_VF5_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK                                      0x00000004L
+#define BIF_BX_DEV0_EPF0_VF5_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK                                          0x00000008L
+#define BIF_BX_DEV0_EPF0_VF5_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK                                0x00010000L
+#define BIF_BX_DEV0_EPF0_VF5_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK                             0x00020000L
+#define BIF_BX_DEV0_EPF0_VF5_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK                                0x00040000L
+#define BIF_BX_DEV0_EPF0_VF5_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK                                    0x00080000L
+//BIF_BX_DEV0_EPF0_VF5_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_DEV0_EPF0_VF5_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT  0x0
+#define BIF_BX_DEV0_EPF0_VF5_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK  0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF5_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_DEV0_EPF0_VF5_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT  0x0
+#define BIF_BX_DEV0_EPF0_VF5_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK  0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF5_1_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_DEV0_EPF0_VF5_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT          0x0
+#define BIF_BX_DEV0_EPF0_VF5_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT        0x1
+#define BIF_BX_DEV0_EPF0_VF5_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT        0x8
+#define BIF_BX_DEV0_EPF0_VF5_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK            0x00000001L
+#define BIF_BX_DEV0_EPF0_VF5_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK          0x00000002L
+#define BIF_BX_DEV0_EPF0_VF5_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK          0x000FFF00L
+//BIF_BX_DEV0_EPF0_VF5_1_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF5_1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT                        0x0
+#define BIF_BX_DEV0_EPF0_VF5_1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK                          0x00000001L
+//BIF_BX_DEV0_EPF0_VF5_1_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF5_1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT                        0x0
+#define BIF_BX_DEV0_EPF0_VF5_1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK                          0x00000001L
+//BIF_BX_DEV0_EPF0_VF5_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL
+#define BIF_BX_DEV0_EPF0_VF5_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT              0x0
+#define BIF_BX_DEV0_EPF0_VF5_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK                0x00000001L
+//BIF_BX_DEV0_EPF0_VF5_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL
+#define BIF_BX_DEV0_EPF0_VF5_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT    0x0
+#define BIF_BX_DEV0_EPF0_VF5_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK      0x00000001L
+//BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__CP0__SHIFT                                                  0x0
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__CP1__SHIFT                                                  0x1
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__CP2__SHIFT                                                  0x2
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__CP3__SHIFT                                                  0x3
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__CP4__SHIFT                                                  0x4
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__CP5__SHIFT                                                  0x5
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__CP6__SHIFT                                                  0x6
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__CP7__SHIFT                                                  0x7
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__CP8__SHIFT                                                  0x8
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__CP9__SHIFT                                                  0x9
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT                                                0xa
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT                                                0xb
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT                                            0xc
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT                                            0xd
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT                                            0xe
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT                                            0xf
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT                                            0x10
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT                                            0x11
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT                                            0x12
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT                                            0x13
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT                                            0x14
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT                                            0x15
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT                                           0x16
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT                                           0x17
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT                                           0x18
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT                                           0x19
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT                                           0x1a
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT                                           0x1b
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT                                           0x1c
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT                                           0x1d
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT                                           0x1e
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT                                           0x1f
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__CP0_MASK                                                    0x00000001L
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__CP1_MASK                                                    0x00000002L
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__CP2_MASK                                                    0x00000004L
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__CP3_MASK                                                    0x00000008L
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__CP4_MASK                                                    0x00000010L
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__CP5_MASK                                                    0x00000020L
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__CP6_MASK                                                    0x00000040L
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__CP7_MASK                                                    0x00000080L
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__CP8_MASK                                                    0x00000100L
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__CP9_MASK                                                    0x00000200L
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__SDMA0_MASK                                                  0x00000400L
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__SDMA1_MASK                                                  0x00000800L
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK                                              0x00001000L
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK                                              0x00002000L
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK                                              0x00004000L
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK                                              0x00008000L
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK                                              0x00010000L
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK                                              0x00020000L
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK                                              0x00040000L
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK                                              0x00080000L
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK                                              0x00100000L
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK                                              0x00200000L
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK                                             0x00400000L
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK                                             0x00800000L
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK                                             0x01000000L
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK                                             0x02000000L
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK                                             0x04000000L
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK                                             0x08000000L
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK                                             0x10000000L
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK                                             0x20000000L
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK                                             0x40000000L
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK                                             0x80000000L
+//BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__CP0__SHIFT                                                 0x0
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__CP1__SHIFT                                                 0x1
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__CP2__SHIFT                                                 0x2
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__CP3__SHIFT                                                 0x3
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__CP4__SHIFT                                                 0x4
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__CP5__SHIFT                                                 0x5
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__CP6__SHIFT                                                 0x6
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__CP7__SHIFT                                                 0x7
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__CP8__SHIFT                                                 0x8
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__CP9__SHIFT                                                 0x9
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT                                               0xa
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT                                               0xb
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT                                           0xc
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT                                           0xd
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT                                           0xe
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT                                           0xf
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT                                           0x10
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT                                           0x11
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT                                           0x12
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT                                           0x13
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT                                           0x14
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT                                           0x15
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT                                          0x16
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT                                          0x17
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT                                          0x18
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT                                          0x19
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT                                          0x1a
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT                                          0x1b
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT                                          0x1c
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT                                          0x1d
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT                                          0x1e
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT                                          0x1f
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__CP0_MASK                                                   0x00000001L
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__CP1_MASK                                                   0x00000002L
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__CP2_MASK                                                   0x00000004L
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__CP3_MASK                                                   0x00000008L
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__CP4_MASK                                                   0x00000010L
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__CP5_MASK                                                   0x00000020L
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__CP6_MASK                                                   0x00000040L
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__CP7_MASK                                                   0x00000080L
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__CP8_MASK                                                   0x00000100L
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__CP9_MASK                                                   0x00000200L
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__SDMA0_MASK                                                 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__SDMA1_MASK                                                 0x00000800L
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK                                             0x00001000L
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK                                             0x00002000L
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK                                             0x00004000L
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK                                             0x00008000L
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK                                             0x00010000L
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK                                             0x00020000L
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK                                             0x00040000L
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK                                             0x00080000L
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK                                             0x00100000L
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK                                             0x00200000L
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK                                            0x00400000L
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK                                            0x00800000L
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK                                            0x01000000L
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK                                            0x02000000L
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK                                            0x04000000L
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK                                            0x08000000L
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK                                            0x10000000L
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK                                            0x20000000L
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK                                            0x40000000L
+#define BIF_BX_DEV0_EPF0_VF5_1_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK                                            0x80000000L
+//BIF_BX_DEV0_EPF0_VF5_1_BIF_TRANS_PENDING
+#define BIF_BX_DEV0_EPF0_VF5_1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT                                0x0
+#define BIF_BX_DEV0_EPF0_VF5_1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT                                0x1
+#define BIF_BX_DEV0_EPF0_VF5_1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK                                  0x00000001L
+#define BIF_BX_DEV0_EPF0_VF5_1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK                                  0x00000002L
+//BIF_BX_DEV0_EPF0_VF5_1_NBIF_GFX_ADDR_LUT_BYPASS
+#define BIF_BX_DEV0_EPF0_VF5_1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT                                    0x0
+#define BIF_BX_DEV0_EPF0_VF5_1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK                                      0x00000001L
+//BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_CONTROL
+#define BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT                                          0x0
+#define BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT                                            0x1
+#define BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT                                          0x8
+#define BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT                                            0x9
+#define BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_CONTROL__TRN_MSG_VALID_MASK                                            0x00000001L
+#define BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_CONTROL__TRN_MSG_ACK_MASK                                              0x00000002L
+#define BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_CONTROL__RCV_MSG_VALID_MASK                                            0x00000100L
+#define BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_CONTROL__RCV_MSG_ACK_MASK                                              0x00000200L
+//BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_INT_CNTL
+#define BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT                                          0x0
+#define BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT                                            0x1
+#define BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_INT_CNTL__VALID_INT_EN_MASK                                            0x00000001L
+#define BIF_BX_DEV0_EPF0_VF5_1_MAILBOX_INT_CNTL__ACK_INT_EN_MASK                                              0x00000002L
+//BIF_BX_DEV0_EPF0_VF5_1_BIF_VMHV_MAILBOX
+#define BIF_BX_DEV0_EPF0_VF5_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT                          0x0
+#define BIF_BX_DEV0_EPF0_VF5_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT                        0x1
+#define BIF_BX_DEV0_EPF0_VF5_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT                             0x8
+#define BIF_BX_DEV0_EPF0_VF5_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT                            0xf
+#define BIF_BX_DEV0_EPF0_VF5_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT                             0x10
+#define BIF_BX_DEV0_EPF0_VF5_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT                            0x17
+#define BIF_BX_DEV0_EPF0_VF5_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT                              0x18
+#define BIF_BX_DEV0_EPF0_VF5_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT                              0x19
+#define BIF_BX_DEV0_EPF0_VF5_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK                            0x00000001L
+#define BIF_BX_DEV0_EPF0_VF5_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK                          0x00000002L
+#define BIF_BX_DEV0_EPF0_VF5_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK                               0x00000F00L
+#define BIF_BX_DEV0_EPF0_VF5_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK                              0x00008000L
+#define BIF_BX_DEV0_EPF0_VF5_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK                               0x000F0000L
+#define BIF_BX_DEV0_EPF0_VF5_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK                              0x00800000L
+#define BIF_BX_DEV0_EPF0_VF5_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK                                0x01000000L
+#define BIF_BX_DEV0_EPF0_VF5_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK                                0x02000000L
+//BIF_BX_DEV0_EPF0_VF5_1_PARTITION_COMPUTE_CAP
+#define BIF_BX_DEV0_EPF0_VF5_1_PARTITION_COMPUTE_CAP__SPX_SUPPORT__SHIFT                                      0x0
+#define BIF_BX_DEV0_EPF0_VF5_1_PARTITION_COMPUTE_CAP__DPX_SUPPORT__SHIFT                                      0x1
+#define BIF_BX_DEV0_EPF0_VF5_1_PARTITION_COMPUTE_CAP__TPX_SUPPORT__SHIFT                                      0x2
+#define BIF_BX_DEV0_EPF0_VF5_1_PARTITION_COMPUTE_CAP__QPX_SUPPORT__SHIFT                                      0x3
+#define BIF_BX_DEV0_EPF0_VF5_1_PARTITION_COMPUTE_CAP__CPX_SUPPORT__SHIFT                                      0x4
+#define BIF_BX_DEV0_EPF0_VF5_1_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY__SHIFT                                 0xa
+#define BIF_BX_DEV0_EPF0_VF5_1_PARTITION_COMPUTE_CAP__SPX_SUPPORT_MASK                                        0x00000001L
+#define BIF_BX_DEV0_EPF0_VF5_1_PARTITION_COMPUTE_CAP__DPX_SUPPORT_MASK                                        0x00000002L
+#define BIF_BX_DEV0_EPF0_VF5_1_PARTITION_COMPUTE_CAP__TPX_SUPPORT_MASK                                        0x00000004L
+#define BIF_BX_DEV0_EPF0_VF5_1_PARTITION_COMPUTE_CAP__QPX_SUPPORT_MASK                                        0x00000008L
+#define BIF_BX_DEV0_EPF0_VF5_1_PARTITION_COMPUTE_CAP__CPX_SUPPORT_MASK                                        0x00000010L
+#define BIF_BX_DEV0_EPF0_VF5_1_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY_MASK                                   0x0003FC00L
+//BIF_BX_DEV0_EPF0_VF5_1_PARTITION_MEM_CAP
+#define BIF_BX_DEV0_EPF0_VF5_1_PARTITION_MEM_CAP__NPS1_SUPPORT__SHIFT                                         0x0
+#define BIF_BX_DEV0_EPF0_VF5_1_PARTITION_MEM_CAP__NPS2_SUPPORT__SHIFT                                         0x1
+#define BIF_BX_DEV0_EPF0_VF5_1_PARTITION_MEM_CAP__NPS3_SUPPORT__SHIFT                                         0x2
+#define BIF_BX_DEV0_EPF0_VF5_1_PARTITION_MEM_CAP__NPS4_SUPPORT__SHIFT                                         0x3
+#define BIF_BX_DEV0_EPF0_VF5_1_PARTITION_MEM_CAP__NPS6_SUPPORT__SHIFT                                         0x5
+#define BIF_BX_DEV0_EPF0_VF5_1_PARTITION_MEM_CAP__NPS8_SUPPORT__SHIFT                                         0x7
+#define BIF_BX_DEV0_EPF0_VF5_1_PARTITION_MEM_CAP__NPS1_SUPPORT_MASK                                           0x00000001L
+#define BIF_BX_DEV0_EPF0_VF5_1_PARTITION_MEM_CAP__NPS2_SUPPORT_MASK                                           0x00000002L
+#define BIF_BX_DEV0_EPF0_VF5_1_PARTITION_MEM_CAP__NPS3_SUPPORT_MASK                                           0x00000004L
+#define BIF_BX_DEV0_EPF0_VF5_1_PARTITION_MEM_CAP__NPS4_SUPPORT_MASK                                           0x00000008L
+#define BIF_BX_DEV0_EPF0_VF5_1_PARTITION_MEM_CAP__NPS6_SUPPORT_MASK                                           0x00000020L
+#define BIF_BX_DEV0_EPF0_VF5_1_PARTITION_MEM_CAP__NPS8_SUPPORT_MASK                                           0x00000080L
+//BIF_BX_DEV0_EPF0_VF5_1_PARTITION_COMPUTE_STATUS
+#define BIF_BX_DEV0_EPF0_VF5_1_PARTITION_COMPUTE_STATUS__PARTITION_MODE__SHIFT                                0x4
+#define BIF_BX_DEV0_EPF0_VF5_1_PARTITION_COMPUTE_STATUS__PARTITION_MODE_MASK                                  0x000000F0L
+//BIF_BX_DEV0_EPF0_VF5_1_PARTITION_MEM_STATUS
+#define BIF_BX_DEV0_EPF0_VF5_1_PARTITION_MEM_STATUS__CHANGE_STATUS__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF5_1_PARTITION_MEM_STATUS__NPS_MODE__SHIFT                                          0x4
+#define BIF_BX_DEV0_EPF0_VF5_1_PARTITION_MEM_STATUS__CHANGE_STATUS_MASK                                       0x0000000FL
+#define BIF_BX_DEV0_EPF0_VF5_1_PARTITION_MEM_STATUS__NPS_MODE_MASK                                            0x00000FF0L
+
+
+// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf5_SYSPFVFDEC:1
+//BIF_BX_DEV0_EPF0_VF5_1_MM_INDEX
+#define BIF_BX_DEV0_EPF0_VF5_1_MM_INDEX__MM_OFFSET__SHIFT                                                     0x0
+#define BIF_BX_DEV0_EPF0_VF5_1_MM_INDEX__MM_APER__SHIFT                                                       0x1f
+#define BIF_BX_DEV0_EPF0_VF5_1_MM_INDEX__MM_OFFSET_MASK                                                       0x7FFFFFFFL
+#define BIF_BX_DEV0_EPF0_VF5_1_MM_INDEX__MM_APER_MASK                                                         0x80000000L
+//BIF_BX_DEV0_EPF0_VF5_1_MM_DATA
+#define BIF_BX_DEV0_EPF0_VF5_1_MM_DATA__MM_DATA__SHIFT                                                        0x0
+#define BIF_BX_DEV0_EPF0_VF5_1_MM_DATA__MM_DATA_MASK                                                          0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF5_1_MM_INDEX_HI
+#define BIF_BX_DEV0_EPF0_VF5_1_MM_INDEX_HI__MM_OFFSET_HI__SHIFT                                               0x0
+#define BIF_BX_DEV0_EPF0_VF5_1_MM_INDEX_HI__MM_OFFSET_HI_MASK                                                 0xFFFFFFFFL
+
+
+// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf5_BIFPFVFDEC1
+//RCC_DEV0_EPF0_VF5_RCC_ERR_LOG
+#define RCC_DEV0_EPF0_VF5_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT                              0x0
+#define RCC_DEV0_EPF0_VF5_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT                                     0x1
+#define RCC_DEV0_EPF0_VF5_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK                                0x00000001L
+#define RCC_DEV0_EPF0_VF5_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK                                       0x00000002L
+//RCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN
+#define RCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT                                   0x0
+#define RCC_DEV0_EPF0_VF5_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK                                     0x00000001L
+//RCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE
+#define RCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_VF5_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED
+#define RCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT                                         0x0
+#define RCC_DEV0_EPF0_VF5_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK                                           0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER
+#define RCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT                                     0x0
+#define RCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT                                          0x1f
+#define RCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK                                       0x00000001L
+#define RCC_DEV0_EPF0_VF5_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK                                            0x80000000L
+
+
+// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf5_BIFDEC2
+//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT                                           0x2
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT                                              0x0
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK                                                0x00000001L
+//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT                                           0x2
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT                                              0x0
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK                                                0x00000001L
+//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT                                           0x2
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT                                              0x0
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK                                                0x00000001L
+//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_LO
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT                                           0x2
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_HI
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_MSG_DATA
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_CONTROL
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT                                              0x0
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK                                                0x00000001L
+//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT4_ADDR_LO
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT4_ADDR_LO__MSG_ADDR_LO__SHIFT                                           0x2
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT4_ADDR_LO__MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT4_ADDR_HI
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT4_ADDR_HI__MSG_ADDR_HI__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT4_ADDR_HI__MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT4_MSG_DATA
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT4_MSG_DATA__MSG_DATA__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT4_MSG_DATA__MSG_DATA_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT4_CONTROL
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT4_CONTROL__MASK_BIT__SHIFT                                              0x0
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT4_CONTROL__MASK_BIT_MASK                                                0x00000001L
+//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT5_ADDR_LO
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT5_ADDR_LO__MSG_ADDR_LO__SHIFT                                           0x2
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT5_ADDR_LO__MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT5_ADDR_HI
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT5_ADDR_HI__MSG_ADDR_HI__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT5_ADDR_HI__MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT5_MSG_DATA
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT5_MSG_DATA__MSG_DATA__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT5_MSG_DATA__MSG_DATA_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT5_CONTROL
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT5_CONTROL__MASK_BIT__SHIFT                                              0x0
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT5_CONTROL__MASK_BIT_MASK                                                0x00000001L
+//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT6_ADDR_LO
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT6_ADDR_LO__MSG_ADDR_LO__SHIFT                                           0x2
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT6_ADDR_LO__MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT6_ADDR_HI
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT6_ADDR_HI__MSG_ADDR_HI__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT6_ADDR_HI__MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT6_MSG_DATA
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT6_MSG_DATA__MSG_DATA__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT6_MSG_DATA__MSG_DATA_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT6_CONTROL
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT6_CONTROL__MASK_BIT__SHIFT                                              0x0
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT6_CONTROL__MASK_BIT_MASK                                                0x00000001L
+//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT7_ADDR_LO
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT7_ADDR_LO__MSG_ADDR_LO__SHIFT                                           0x2
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT7_ADDR_LO__MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT7_ADDR_HI
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT7_ADDR_HI__MSG_ADDR_HI__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT7_ADDR_HI__MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT7_MSG_DATA
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT7_MSG_DATA__MSG_DATA__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT7_MSG_DATA__MSG_DATA_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT7_CONTROL
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT7_CONTROL__MASK_BIT__SHIFT                                              0x0
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT7_CONTROL__MASK_BIT_MASK                                                0x00000001L
+//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT8_ADDR_LO
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT8_ADDR_LO__MSG_ADDR_LO__SHIFT                                           0x2
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT8_ADDR_LO__MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT8_ADDR_HI
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT8_ADDR_HI__MSG_ADDR_HI__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT8_ADDR_HI__MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT8_MSG_DATA
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT8_MSG_DATA__MSG_DATA__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT8_MSG_DATA__MSG_DATA_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF5_GFXMSIX_VECT8_CONTROL
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT8_CONTROL__MASK_BIT__SHIFT                                              0x0
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_VECT8_CONTROL__MASK_BIT_MASK                                                0x00000001L
+//RCC_DEV0_EPF0_VF5_GFXMSIX_PBA
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT                                             0x1
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK                                               0x00000001L
+#define RCC_DEV0_EPF0_VF5_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK                                               0x00000002L
+
+
+// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf6_BIFPFVFDEC1
+//BIF_BX_DEV0_EPF0_VF6_0_BIF_BME_STATUS
+#define BIF_BX_DEV0_EPF0_VF6_0_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT                                          0x0
+#define BIF_BX_DEV0_EPF0_VF6_0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT                                    0x10
+#define BIF_BX_DEV0_EPF0_VF6_0_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK                                            0x00000001L
+#define BIF_BX_DEV0_EPF0_VF6_0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK                                      0x00010000L
+//BIF_BX_DEV0_EPF0_VF6_0_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_DEV0_EPF0_VF6_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT                                    0x0
+#define BIF_BX_DEV0_EPF0_VF6_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT                                 0x1
+#define BIF_BX_DEV0_EPF0_VF6_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT                                    0x2
+#define BIF_BX_DEV0_EPF0_VF6_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT                                        0x3
+#define BIF_BX_DEV0_EPF0_VF6_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT                              0x10
+#define BIF_BX_DEV0_EPF0_VF6_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT                           0x11
+#define BIF_BX_DEV0_EPF0_VF6_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT                              0x12
+#define BIF_BX_DEV0_EPF0_VF6_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT                                  0x13
+#define BIF_BX_DEV0_EPF0_VF6_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK                                      0x00000001L
+#define BIF_BX_DEV0_EPF0_VF6_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK                                   0x00000002L
+#define BIF_BX_DEV0_EPF0_VF6_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK                                      0x00000004L
+#define BIF_BX_DEV0_EPF0_VF6_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK                                          0x00000008L
+#define BIF_BX_DEV0_EPF0_VF6_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK                                0x00010000L
+#define BIF_BX_DEV0_EPF0_VF6_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK                             0x00020000L
+#define BIF_BX_DEV0_EPF0_VF6_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK                                0x00040000L
+#define BIF_BX_DEV0_EPF0_VF6_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK                                    0x00080000L
+//BIF_BX_DEV0_EPF0_VF6_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_DEV0_EPF0_VF6_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT  0x0
+#define BIF_BX_DEV0_EPF0_VF6_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK  0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF6_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_DEV0_EPF0_VF6_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT  0x0
+#define BIF_BX_DEV0_EPF0_VF6_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK  0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF6_0_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_DEV0_EPF0_VF6_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT          0x0
+#define BIF_BX_DEV0_EPF0_VF6_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT        0x1
+#define BIF_BX_DEV0_EPF0_VF6_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT        0x8
+#define BIF_BX_DEV0_EPF0_VF6_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK            0x00000001L
+#define BIF_BX_DEV0_EPF0_VF6_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK          0x00000002L
+#define BIF_BX_DEV0_EPF0_VF6_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK          0x000FFF00L
+//BIF_BX_DEV0_EPF0_VF6_0_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF6_0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT                        0x0
+#define BIF_BX_DEV0_EPF0_VF6_0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK                          0x00000001L
+//BIF_BX_DEV0_EPF0_VF6_0_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF6_0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT                        0x0
+#define BIF_BX_DEV0_EPF0_VF6_0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK                          0x00000001L
+//BIF_BX_DEV0_EPF0_VF6_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL
+#define BIF_BX_DEV0_EPF0_VF6_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT              0x0
+#define BIF_BX_DEV0_EPF0_VF6_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK                0x00000001L
+//BIF_BX_DEV0_EPF0_VF6_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL
+#define BIF_BX_DEV0_EPF0_VF6_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT    0x0
+#define BIF_BX_DEV0_EPF0_VF6_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK      0x00000001L
+//BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__CP0__SHIFT                                                  0x0
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__CP1__SHIFT                                                  0x1
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__CP2__SHIFT                                                  0x2
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__CP3__SHIFT                                                  0x3
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__CP4__SHIFT                                                  0x4
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__CP5__SHIFT                                                  0x5
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__CP6__SHIFT                                                  0x6
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__CP7__SHIFT                                                  0x7
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__CP8__SHIFT                                                  0x8
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__CP9__SHIFT                                                  0x9
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT                                                0xa
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT                                                0xb
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT                                            0xc
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT                                            0xd
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT                                            0xe
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT                                            0xf
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT                                            0x10
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT                                            0x11
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT                                            0x12
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT                                            0x13
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT                                            0x14
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT                                            0x15
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT                                           0x16
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT                                           0x17
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT                                           0x18
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT                                           0x19
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT                                           0x1a
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT                                           0x1b
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT                                           0x1c
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT                                           0x1d
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT                                           0x1e
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT                                           0x1f
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__CP0_MASK                                                    0x00000001L
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__CP1_MASK                                                    0x00000002L
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__CP2_MASK                                                    0x00000004L
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__CP3_MASK                                                    0x00000008L
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__CP4_MASK                                                    0x00000010L
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__CP5_MASK                                                    0x00000020L
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__CP6_MASK                                                    0x00000040L
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__CP7_MASK                                                    0x00000080L
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__CP8_MASK                                                    0x00000100L
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__CP9_MASK                                                    0x00000200L
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__SDMA0_MASK                                                  0x00000400L
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__SDMA1_MASK                                                  0x00000800L
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK                                              0x00001000L
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK                                              0x00002000L
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK                                              0x00004000L
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK                                              0x00008000L
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK                                              0x00010000L
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK                                              0x00020000L
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK                                              0x00040000L
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK                                              0x00080000L
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK                                              0x00100000L
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK                                              0x00200000L
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK                                             0x00400000L
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK                                             0x00800000L
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK                                             0x01000000L
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK                                             0x02000000L
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK                                             0x04000000L
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK                                             0x08000000L
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK                                             0x10000000L
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK                                             0x20000000L
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK                                             0x40000000L
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK                                             0x80000000L
+//BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__CP0__SHIFT                                                 0x0
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__CP1__SHIFT                                                 0x1
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__CP2__SHIFT                                                 0x2
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__CP3__SHIFT                                                 0x3
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__CP4__SHIFT                                                 0x4
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__CP5__SHIFT                                                 0x5
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__CP6__SHIFT                                                 0x6
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__CP7__SHIFT                                                 0x7
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__CP8__SHIFT                                                 0x8
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__CP9__SHIFT                                                 0x9
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT                                               0xa
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT                                               0xb
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT                                           0xc
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT                                           0xd
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT                                           0xe
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT                                           0xf
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT                                           0x10
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT                                           0x11
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT                                           0x12
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT                                           0x13
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT                                           0x14
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT                                           0x15
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT                                          0x16
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT                                          0x17
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT                                          0x18
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT                                          0x19
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT                                          0x1a
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT                                          0x1b
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT                                          0x1c
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT                                          0x1d
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT                                          0x1e
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT                                          0x1f
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__CP0_MASK                                                   0x00000001L
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__CP1_MASK                                                   0x00000002L
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__CP2_MASK                                                   0x00000004L
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__CP3_MASK                                                   0x00000008L
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__CP4_MASK                                                   0x00000010L
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__CP5_MASK                                                   0x00000020L
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__CP6_MASK                                                   0x00000040L
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__CP7_MASK                                                   0x00000080L
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__CP8_MASK                                                   0x00000100L
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__CP9_MASK                                                   0x00000200L
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__SDMA0_MASK                                                 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__SDMA1_MASK                                                 0x00000800L
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK                                             0x00001000L
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK                                             0x00002000L
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK                                             0x00004000L
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK                                             0x00008000L
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK                                             0x00010000L
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK                                             0x00020000L
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK                                             0x00040000L
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK                                             0x00080000L
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK                                             0x00100000L
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK                                             0x00200000L
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK                                            0x00400000L
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK                                            0x00800000L
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK                                            0x01000000L
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK                                            0x02000000L
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK                                            0x04000000L
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK                                            0x08000000L
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK                                            0x10000000L
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK                                            0x20000000L
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK                                            0x40000000L
+#define BIF_BX_DEV0_EPF0_VF6_0_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK                                            0x80000000L
+//BIF_BX_DEV0_EPF0_VF6_0_BIF_TRANS_PENDING
+#define BIF_BX_DEV0_EPF0_VF6_0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT                                0x0
+#define BIF_BX_DEV0_EPF0_VF6_0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT                                0x1
+#define BIF_BX_DEV0_EPF0_VF6_0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK                                  0x00000001L
+#define BIF_BX_DEV0_EPF0_VF6_0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK                                  0x00000002L
+//BIF_BX_DEV0_EPF0_VF6_0_NBIF_GFX_ADDR_LUT_BYPASS
+#define BIF_BX_DEV0_EPF0_VF6_0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT                                    0x0
+#define BIF_BX_DEV0_EPF0_VF6_0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK                                      0x00000001L
+//BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_CONTROL
+#define BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT                                          0x0
+#define BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT                                            0x1
+#define BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT                                          0x8
+#define BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT                                            0x9
+#define BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_CONTROL__TRN_MSG_VALID_MASK                                            0x00000001L
+#define BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_CONTROL__TRN_MSG_ACK_MASK                                              0x00000002L
+#define BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_CONTROL__RCV_MSG_VALID_MASK                                            0x00000100L
+#define BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_CONTROL__RCV_MSG_ACK_MASK                                              0x00000200L
+//BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_INT_CNTL
+#define BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT                                          0x0
+#define BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT                                            0x1
+#define BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_INT_CNTL__VALID_INT_EN_MASK                                            0x00000001L
+#define BIF_BX_DEV0_EPF0_VF6_0_MAILBOX_INT_CNTL__ACK_INT_EN_MASK                                              0x00000002L
+//BIF_BX_DEV0_EPF0_VF6_0_BIF_VMHV_MAILBOX
+#define BIF_BX_DEV0_EPF0_VF6_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT                          0x0
+#define BIF_BX_DEV0_EPF0_VF6_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT                        0x1
+#define BIF_BX_DEV0_EPF0_VF6_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT                             0x8
+#define BIF_BX_DEV0_EPF0_VF6_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT                            0xf
+#define BIF_BX_DEV0_EPF0_VF6_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT                             0x10
+#define BIF_BX_DEV0_EPF0_VF6_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT                            0x17
+#define BIF_BX_DEV0_EPF0_VF6_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT                              0x18
+#define BIF_BX_DEV0_EPF0_VF6_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT                              0x19
+#define BIF_BX_DEV0_EPF0_VF6_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK                            0x00000001L
+#define BIF_BX_DEV0_EPF0_VF6_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK                          0x00000002L
+#define BIF_BX_DEV0_EPF0_VF6_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK                               0x00000F00L
+#define BIF_BX_DEV0_EPF0_VF6_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK                              0x00008000L
+#define BIF_BX_DEV0_EPF0_VF6_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK                               0x000F0000L
+#define BIF_BX_DEV0_EPF0_VF6_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK                              0x00800000L
+#define BIF_BX_DEV0_EPF0_VF6_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK                                0x01000000L
+#define BIF_BX_DEV0_EPF0_VF6_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK                                0x02000000L
+//BIF_BX_DEV0_EPF0_VF6_0_PARTITION_COMPUTE_CAP
+#define BIF_BX_DEV0_EPF0_VF6_0_PARTITION_COMPUTE_CAP__SPX_SUPPORT__SHIFT                                      0x0
+#define BIF_BX_DEV0_EPF0_VF6_0_PARTITION_COMPUTE_CAP__DPX_SUPPORT__SHIFT                                      0x1
+#define BIF_BX_DEV0_EPF0_VF6_0_PARTITION_COMPUTE_CAP__TPX_SUPPORT__SHIFT                                      0x2
+#define BIF_BX_DEV0_EPF0_VF6_0_PARTITION_COMPUTE_CAP__QPX_SUPPORT__SHIFT                                      0x3
+#define BIF_BX_DEV0_EPF0_VF6_0_PARTITION_COMPUTE_CAP__CPX_SUPPORT__SHIFT                                      0x4
+#define BIF_BX_DEV0_EPF0_VF6_0_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY__SHIFT                                 0xa
+#define BIF_BX_DEV0_EPF0_VF6_0_PARTITION_COMPUTE_CAP__SPX_SUPPORT_MASK                                        0x00000001L
+#define BIF_BX_DEV0_EPF0_VF6_0_PARTITION_COMPUTE_CAP__DPX_SUPPORT_MASK                                        0x00000002L
+#define BIF_BX_DEV0_EPF0_VF6_0_PARTITION_COMPUTE_CAP__TPX_SUPPORT_MASK                                        0x00000004L
+#define BIF_BX_DEV0_EPF0_VF6_0_PARTITION_COMPUTE_CAP__QPX_SUPPORT_MASK                                        0x00000008L
+#define BIF_BX_DEV0_EPF0_VF6_0_PARTITION_COMPUTE_CAP__CPX_SUPPORT_MASK                                        0x00000010L
+#define BIF_BX_DEV0_EPF0_VF6_0_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY_MASK                                   0x0003FC00L
+//BIF_BX_DEV0_EPF0_VF6_0_PARTITION_MEM_CAP
+#define BIF_BX_DEV0_EPF0_VF6_0_PARTITION_MEM_CAP__NPS1_SUPPORT__SHIFT                                         0x0
+#define BIF_BX_DEV0_EPF0_VF6_0_PARTITION_MEM_CAP__NPS2_SUPPORT__SHIFT                                         0x1
+#define BIF_BX_DEV0_EPF0_VF6_0_PARTITION_MEM_CAP__NPS3_SUPPORT__SHIFT                                         0x2
+#define BIF_BX_DEV0_EPF0_VF6_0_PARTITION_MEM_CAP__NPS4_SUPPORT__SHIFT                                         0x3
+#define BIF_BX_DEV0_EPF0_VF6_0_PARTITION_MEM_CAP__NPS6_SUPPORT__SHIFT                                         0x5
+#define BIF_BX_DEV0_EPF0_VF6_0_PARTITION_MEM_CAP__NPS8_SUPPORT__SHIFT                                         0x7
+#define BIF_BX_DEV0_EPF0_VF6_0_PARTITION_MEM_CAP__NPS1_SUPPORT_MASK                                           0x00000001L
+#define BIF_BX_DEV0_EPF0_VF6_0_PARTITION_MEM_CAP__NPS2_SUPPORT_MASK                                           0x00000002L
+#define BIF_BX_DEV0_EPF0_VF6_0_PARTITION_MEM_CAP__NPS3_SUPPORT_MASK                                           0x00000004L
+#define BIF_BX_DEV0_EPF0_VF6_0_PARTITION_MEM_CAP__NPS4_SUPPORT_MASK                                           0x00000008L
+#define BIF_BX_DEV0_EPF0_VF6_0_PARTITION_MEM_CAP__NPS6_SUPPORT_MASK                                           0x00000020L
+#define BIF_BX_DEV0_EPF0_VF6_0_PARTITION_MEM_CAP__NPS8_SUPPORT_MASK                                           0x00000080L
+//BIF_BX_DEV0_EPF0_VF6_0_PARTITION_COMPUTE_STATUS
+#define BIF_BX_DEV0_EPF0_VF6_0_PARTITION_COMPUTE_STATUS__PARTITION_MODE__SHIFT                                0x4
+#define BIF_BX_DEV0_EPF0_VF6_0_PARTITION_COMPUTE_STATUS__PARTITION_MODE_MASK                                  0x000000F0L
+//BIF_BX_DEV0_EPF0_VF6_0_PARTITION_MEM_STATUS
+#define BIF_BX_DEV0_EPF0_VF6_0_PARTITION_MEM_STATUS__CHANGE_STATUS__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF6_0_PARTITION_MEM_STATUS__NPS_MODE__SHIFT                                          0x4
+#define BIF_BX_DEV0_EPF0_VF6_0_PARTITION_MEM_STATUS__CHANGE_STATUS_MASK                                       0x0000000FL
+#define BIF_BX_DEV0_EPF0_VF6_0_PARTITION_MEM_STATUS__NPS_MODE_MASK                                            0x00000FF0L
+
+
+// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf6_SYSPFVFDEC
+//BIF_BX_DEV0_EPF0_VF6_0_MM_INDEX
+#define BIF_BX_DEV0_EPF0_VF6_0_MM_INDEX__MM_OFFSET__SHIFT                                                     0x0
+#define BIF_BX_DEV0_EPF0_VF6_0_MM_INDEX__MM_APER__SHIFT                                                       0x1f
+#define BIF_BX_DEV0_EPF0_VF6_0_MM_INDEX__MM_OFFSET_MASK                                                       0x7FFFFFFFL
+#define BIF_BX_DEV0_EPF0_VF6_0_MM_INDEX__MM_APER_MASK                                                         0x80000000L
+//BIF_BX_DEV0_EPF0_VF6_0_MM_DATA
+#define BIF_BX_DEV0_EPF0_VF6_0_MM_DATA__MM_DATA__SHIFT                                                        0x0
+#define BIF_BX_DEV0_EPF0_VF6_0_MM_DATA__MM_DATA_MASK                                                          0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF6_0_MM_INDEX_HI
+#define BIF_BX_DEV0_EPF0_VF6_0_MM_INDEX_HI__MM_OFFSET_HI__SHIFT                                               0x0
+#define BIF_BX_DEV0_EPF0_VF6_0_MM_INDEX_HI__MM_OFFSET_HI_MASK                                                 0xFFFFFFFFL
+
+
+// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf6_BIFPFVFDEC1:1
+//BIF_BX_DEV0_EPF0_VF6_1_BIF_BME_STATUS
+#define BIF_BX_DEV0_EPF0_VF6_1_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT                                          0x0
+#define BIF_BX_DEV0_EPF0_VF6_1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT                                    0x10
+#define BIF_BX_DEV0_EPF0_VF6_1_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK                                            0x00000001L
+#define BIF_BX_DEV0_EPF0_VF6_1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK                                      0x00010000L
+//BIF_BX_DEV0_EPF0_VF6_1_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_DEV0_EPF0_VF6_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT                                    0x0
+#define BIF_BX_DEV0_EPF0_VF6_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT                                 0x1
+#define BIF_BX_DEV0_EPF0_VF6_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT                                    0x2
+#define BIF_BX_DEV0_EPF0_VF6_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT                                        0x3
+#define BIF_BX_DEV0_EPF0_VF6_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT                              0x10
+#define BIF_BX_DEV0_EPF0_VF6_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT                           0x11
+#define BIF_BX_DEV0_EPF0_VF6_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT                              0x12
+#define BIF_BX_DEV0_EPF0_VF6_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT                                  0x13
+#define BIF_BX_DEV0_EPF0_VF6_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK                                      0x00000001L
+#define BIF_BX_DEV0_EPF0_VF6_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK                                   0x00000002L
+#define BIF_BX_DEV0_EPF0_VF6_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK                                      0x00000004L
+#define BIF_BX_DEV0_EPF0_VF6_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK                                          0x00000008L
+#define BIF_BX_DEV0_EPF0_VF6_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK                                0x00010000L
+#define BIF_BX_DEV0_EPF0_VF6_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK                             0x00020000L
+#define BIF_BX_DEV0_EPF0_VF6_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK                                0x00040000L
+#define BIF_BX_DEV0_EPF0_VF6_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK                                    0x00080000L
+//BIF_BX_DEV0_EPF0_VF6_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_DEV0_EPF0_VF6_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT  0x0
+#define BIF_BX_DEV0_EPF0_VF6_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK  0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF6_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_DEV0_EPF0_VF6_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT  0x0
+#define BIF_BX_DEV0_EPF0_VF6_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK  0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF6_1_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_DEV0_EPF0_VF6_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT          0x0
+#define BIF_BX_DEV0_EPF0_VF6_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT        0x1
+#define BIF_BX_DEV0_EPF0_VF6_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT        0x8
+#define BIF_BX_DEV0_EPF0_VF6_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK            0x00000001L
+#define BIF_BX_DEV0_EPF0_VF6_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK          0x00000002L
+#define BIF_BX_DEV0_EPF0_VF6_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK          0x000FFF00L
+//BIF_BX_DEV0_EPF0_VF6_1_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF6_1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT                        0x0
+#define BIF_BX_DEV0_EPF0_VF6_1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK                          0x00000001L
+//BIF_BX_DEV0_EPF0_VF6_1_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF6_1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT                        0x0
+#define BIF_BX_DEV0_EPF0_VF6_1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK                          0x00000001L
+//BIF_BX_DEV0_EPF0_VF6_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL
+#define BIF_BX_DEV0_EPF0_VF6_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT              0x0
+#define BIF_BX_DEV0_EPF0_VF6_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK                0x00000001L
+//BIF_BX_DEV0_EPF0_VF6_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL
+#define BIF_BX_DEV0_EPF0_VF6_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT    0x0
+#define BIF_BX_DEV0_EPF0_VF6_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK      0x00000001L
+//BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__CP0__SHIFT                                                  0x0
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__CP1__SHIFT                                                  0x1
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__CP2__SHIFT                                                  0x2
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__CP3__SHIFT                                                  0x3
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__CP4__SHIFT                                                  0x4
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__CP5__SHIFT                                                  0x5
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__CP6__SHIFT                                                  0x6
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__CP7__SHIFT                                                  0x7
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__CP8__SHIFT                                                  0x8
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__CP9__SHIFT                                                  0x9
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT                                                0xa
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT                                                0xb
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT                                            0xc
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT                                            0xd
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT                                            0xe
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT                                            0xf
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT                                            0x10
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT                                            0x11
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT                                            0x12
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT                                            0x13
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT                                            0x14
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT                                            0x15
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT                                           0x16
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT                                           0x17
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT                                           0x18
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT                                           0x19
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT                                           0x1a
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT                                           0x1b
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT                                           0x1c
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT                                           0x1d
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT                                           0x1e
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT                                           0x1f
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__CP0_MASK                                                    0x00000001L
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__CP1_MASK                                                    0x00000002L
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__CP2_MASK                                                    0x00000004L
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__CP3_MASK                                                    0x00000008L
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__CP4_MASK                                                    0x00000010L
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__CP5_MASK                                                    0x00000020L
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__CP6_MASK                                                    0x00000040L
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__CP7_MASK                                                    0x00000080L
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__CP8_MASK                                                    0x00000100L
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__CP9_MASK                                                    0x00000200L
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__SDMA0_MASK                                                  0x00000400L
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__SDMA1_MASK                                                  0x00000800L
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK                                              0x00001000L
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK                                              0x00002000L
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK                                              0x00004000L
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK                                              0x00008000L
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK                                              0x00010000L
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK                                              0x00020000L
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK                                              0x00040000L
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK                                              0x00080000L
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK                                              0x00100000L
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK                                              0x00200000L
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK                                             0x00400000L
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK                                             0x00800000L
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK                                             0x01000000L
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK                                             0x02000000L
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK                                             0x04000000L
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK                                             0x08000000L
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK                                             0x10000000L
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK                                             0x20000000L
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK                                             0x40000000L
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK                                             0x80000000L
+//BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__CP0__SHIFT                                                 0x0
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__CP1__SHIFT                                                 0x1
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__CP2__SHIFT                                                 0x2
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__CP3__SHIFT                                                 0x3
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__CP4__SHIFT                                                 0x4
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__CP5__SHIFT                                                 0x5
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__CP6__SHIFT                                                 0x6
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__CP7__SHIFT                                                 0x7
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__CP8__SHIFT                                                 0x8
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__CP9__SHIFT                                                 0x9
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT                                               0xa
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT                                               0xb
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT                                           0xc
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT                                           0xd
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT                                           0xe
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT                                           0xf
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT                                           0x10
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT                                           0x11
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT                                           0x12
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT                                           0x13
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT                                           0x14
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT                                           0x15
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT                                          0x16
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT                                          0x17
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT                                          0x18
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT                                          0x19
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT                                          0x1a
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT                                          0x1b
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT                                          0x1c
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT                                          0x1d
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT                                          0x1e
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT                                          0x1f
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__CP0_MASK                                                   0x00000001L
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__CP1_MASK                                                   0x00000002L
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__CP2_MASK                                                   0x00000004L
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__CP3_MASK                                                   0x00000008L
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__CP4_MASK                                                   0x00000010L
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__CP5_MASK                                                   0x00000020L
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__CP6_MASK                                                   0x00000040L
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__CP7_MASK                                                   0x00000080L
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__CP8_MASK                                                   0x00000100L
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__CP9_MASK                                                   0x00000200L
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__SDMA0_MASK                                                 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__SDMA1_MASK                                                 0x00000800L
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK                                             0x00001000L
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK                                             0x00002000L
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK                                             0x00004000L
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK                                             0x00008000L
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK                                             0x00010000L
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK                                             0x00020000L
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK                                             0x00040000L
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK                                             0x00080000L
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK                                             0x00100000L
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK                                             0x00200000L
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK                                            0x00400000L
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK                                            0x00800000L
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK                                            0x01000000L
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK                                            0x02000000L
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK                                            0x04000000L
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK                                            0x08000000L
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK                                            0x10000000L
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK                                            0x20000000L
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK                                            0x40000000L
+#define BIF_BX_DEV0_EPF0_VF6_1_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK                                            0x80000000L
+//BIF_BX_DEV0_EPF0_VF6_1_BIF_TRANS_PENDING
+#define BIF_BX_DEV0_EPF0_VF6_1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT                                0x0
+#define BIF_BX_DEV0_EPF0_VF6_1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT                                0x1
+#define BIF_BX_DEV0_EPF0_VF6_1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK                                  0x00000001L
+#define BIF_BX_DEV0_EPF0_VF6_1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK                                  0x00000002L
+//BIF_BX_DEV0_EPF0_VF6_1_NBIF_GFX_ADDR_LUT_BYPASS
+#define BIF_BX_DEV0_EPF0_VF6_1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT                                    0x0
+#define BIF_BX_DEV0_EPF0_VF6_1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK                                      0x00000001L
+//BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_CONTROL
+#define BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT                                          0x0
+#define BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT                                            0x1
+#define BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT                                          0x8
+#define BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT                                            0x9
+#define BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_CONTROL__TRN_MSG_VALID_MASK                                            0x00000001L
+#define BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_CONTROL__TRN_MSG_ACK_MASK                                              0x00000002L
+#define BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_CONTROL__RCV_MSG_VALID_MASK                                            0x00000100L
+#define BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_CONTROL__RCV_MSG_ACK_MASK                                              0x00000200L
+//BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_INT_CNTL
+#define BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT                                          0x0
+#define BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT                                            0x1
+#define BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_INT_CNTL__VALID_INT_EN_MASK                                            0x00000001L
+#define BIF_BX_DEV0_EPF0_VF6_1_MAILBOX_INT_CNTL__ACK_INT_EN_MASK                                              0x00000002L
+//BIF_BX_DEV0_EPF0_VF6_1_BIF_VMHV_MAILBOX
+#define BIF_BX_DEV0_EPF0_VF6_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT                          0x0
+#define BIF_BX_DEV0_EPF0_VF6_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT                        0x1
+#define BIF_BX_DEV0_EPF0_VF6_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT                             0x8
+#define BIF_BX_DEV0_EPF0_VF6_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT                            0xf
+#define BIF_BX_DEV0_EPF0_VF6_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT                             0x10
+#define BIF_BX_DEV0_EPF0_VF6_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT                            0x17
+#define BIF_BX_DEV0_EPF0_VF6_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT                              0x18
+#define BIF_BX_DEV0_EPF0_VF6_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT                              0x19
+#define BIF_BX_DEV0_EPF0_VF6_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK                            0x00000001L
+#define BIF_BX_DEV0_EPF0_VF6_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK                          0x00000002L
+#define BIF_BX_DEV0_EPF0_VF6_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK                               0x00000F00L
+#define BIF_BX_DEV0_EPF0_VF6_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK                              0x00008000L
+#define BIF_BX_DEV0_EPF0_VF6_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK                               0x000F0000L
+#define BIF_BX_DEV0_EPF0_VF6_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK                              0x00800000L
+#define BIF_BX_DEV0_EPF0_VF6_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK                                0x01000000L
+#define BIF_BX_DEV0_EPF0_VF6_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK                                0x02000000L
+//BIF_BX_DEV0_EPF0_VF6_1_PARTITION_COMPUTE_CAP
+#define BIF_BX_DEV0_EPF0_VF6_1_PARTITION_COMPUTE_CAP__SPX_SUPPORT__SHIFT                                      0x0
+#define BIF_BX_DEV0_EPF0_VF6_1_PARTITION_COMPUTE_CAP__DPX_SUPPORT__SHIFT                                      0x1
+#define BIF_BX_DEV0_EPF0_VF6_1_PARTITION_COMPUTE_CAP__TPX_SUPPORT__SHIFT                                      0x2
+#define BIF_BX_DEV0_EPF0_VF6_1_PARTITION_COMPUTE_CAP__QPX_SUPPORT__SHIFT                                      0x3
+#define BIF_BX_DEV0_EPF0_VF6_1_PARTITION_COMPUTE_CAP__CPX_SUPPORT__SHIFT                                      0x4
+#define BIF_BX_DEV0_EPF0_VF6_1_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY__SHIFT                                 0xa
+#define BIF_BX_DEV0_EPF0_VF6_1_PARTITION_COMPUTE_CAP__SPX_SUPPORT_MASK                                        0x00000001L
+#define BIF_BX_DEV0_EPF0_VF6_1_PARTITION_COMPUTE_CAP__DPX_SUPPORT_MASK                                        0x00000002L
+#define BIF_BX_DEV0_EPF0_VF6_1_PARTITION_COMPUTE_CAP__TPX_SUPPORT_MASK                                        0x00000004L
+#define BIF_BX_DEV0_EPF0_VF6_1_PARTITION_COMPUTE_CAP__QPX_SUPPORT_MASK                                        0x00000008L
+#define BIF_BX_DEV0_EPF0_VF6_1_PARTITION_COMPUTE_CAP__CPX_SUPPORT_MASK                                        0x00000010L
+#define BIF_BX_DEV0_EPF0_VF6_1_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY_MASK                                   0x0003FC00L
+//BIF_BX_DEV0_EPF0_VF6_1_PARTITION_MEM_CAP
+#define BIF_BX_DEV0_EPF0_VF6_1_PARTITION_MEM_CAP__NPS1_SUPPORT__SHIFT                                         0x0
+#define BIF_BX_DEV0_EPF0_VF6_1_PARTITION_MEM_CAP__NPS2_SUPPORT__SHIFT                                         0x1
+#define BIF_BX_DEV0_EPF0_VF6_1_PARTITION_MEM_CAP__NPS3_SUPPORT__SHIFT                                         0x2
+#define BIF_BX_DEV0_EPF0_VF6_1_PARTITION_MEM_CAP__NPS4_SUPPORT__SHIFT                                         0x3
+#define BIF_BX_DEV0_EPF0_VF6_1_PARTITION_MEM_CAP__NPS6_SUPPORT__SHIFT                                         0x5
+#define BIF_BX_DEV0_EPF0_VF6_1_PARTITION_MEM_CAP__NPS8_SUPPORT__SHIFT                                         0x7
+#define BIF_BX_DEV0_EPF0_VF6_1_PARTITION_MEM_CAP__NPS1_SUPPORT_MASK                                           0x00000001L
+#define BIF_BX_DEV0_EPF0_VF6_1_PARTITION_MEM_CAP__NPS2_SUPPORT_MASK                                           0x00000002L
+#define BIF_BX_DEV0_EPF0_VF6_1_PARTITION_MEM_CAP__NPS3_SUPPORT_MASK                                           0x00000004L
+#define BIF_BX_DEV0_EPF0_VF6_1_PARTITION_MEM_CAP__NPS4_SUPPORT_MASK                                           0x00000008L
+#define BIF_BX_DEV0_EPF0_VF6_1_PARTITION_MEM_CAP__NPS6_SUPPORT_MASK                                           0x00000020L
+#define BIF_BX_DEV0_EPF0_VF6_1_PARTITION_MEM_CAP__NPS8_SUPPORT_MASK                                           0x00000080L
+//BIF_BX_DEV0_EPF0_VF6_1_PARTITION_COMPUTE_STATUS
+#define BIF_BX_DEV0_EPF0_VF6_1_PARTITION_COMPUTE_STATUS__PARTITION_MODE__SHIFT                                0x4
+#define BIF_BX_DEV0_EPF0_VF6_1_PARTITION_COMPUTE_STATUS__PARTITION_MODE_MASK                                  0x000000F0L
+//BIF_BX_DEV0_EPF0_VF6_1_PARTITION_MEM_STATUS
+#define BIF_BX_DEV0_EPF0_VF6_1_PARTITION_MEM_STATUS__CHANGE_STATUS__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF6_1_PARTITION_MEM_STATUS__NPS_MODE__SHIFT                                          0x4
+#define BIF_BX_DEV0_EPF0_VF6_1_PARTITION_MEM_STATUS__CHANGE_STATUS_MASK                                       0x0000000FL
+#define BIF_BX_DEV0_EPF0_VF6_1_PARTITION_MEM_STATUS__NPS_MODE_MASK                                            0x00000FF0L
+
+
+// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf6_SYSPFVFDEC:1
+//BIF_BX_DEV0_EPF0_VF6_1_MM_INDEX
+#define BIF_BX_DEV0_EPF0_VF6_1_MM_INDEX__MM_OFFSET__SHIFT                                                     0x0
+#define BIF_BX_DEV0_EPF0_VF6_1_MM_INDEX__MM_APER__SHIFT                                                       0x1f
+#define BIF_BX_DEV0_EPF0_VF6_1_MM_INDEX__MM_OFFSET_MASK                                                       0x7FFFFFFFL
+#define BIF_BX_DEV0_EPF0_VF6_1_MM_INDEX__MM_APER_MASK                                                         0x80000000L
+//BIF_BX_DEV0_EPF0_VF6_1_MM_DATA
+#define BIF_BX_DEV0_EPF0_VF6_1_MM_DATA__MM_DATA__SHIFT                                                        0x0
+#define BIF_BX_DEV0_EPF0_VF6_1_MM_DATA__MM_DATA_MASK                                                          0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF6_1_MM_INDEX_HI
+#define BIF_BX_DEV0_EPF0_VF6_1_MM_INDEX_HI__MM_OFFSET_HI__SHIFT                                               0x0
+#define BIF_BX_DEV0_EPF0_VF6_1_MM_INDEX_HI__MM_OFFSET_HI_MASK                                                 0xFFFFFFFFL
+
+
+// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf6_BIFPFVFDEC1
+//RCC_DEV0_EPF0_VF6_RCC_ERR_LOG
+#define RCC_DEV0_EPF0_VF6_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT                              0x0
+#define RCC_DEV0_EPF0_VF6_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT                                     0x1
+#define RCC_DEV0_EPF0_VF6_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK                                0x00000001L
+#define RCC_DEV0_EPF0_VF6_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK                                       0x00000002L
+//RCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN
+#define RCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT                                   0x0
+#define RCC_DEV0_EPF0_VF6_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK                                     0x00000001L
+//RCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE
+#define RCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_VF6_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED
+#define RCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT                                         0x0
+#define RCC_DEV0_EPF0_VF6_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK                                           0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER
+#define RCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT                                     0x0
+#define RCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT                                          0x1f
+#define RCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK                                       0x00000001L
+#define RCC_DEV0_EPF0_VF6_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK                                            0x80000000L
+
+
+// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf6_BIFDEC2
+//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT                                           0x2
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT                                              0x0
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK                                                0x00000001L
+//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT                                           0x2
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT                                              0x0
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK                                                0x00000001L
+//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT                                           0x2
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT                                              0x0
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK                                                0x00000001L
+//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_LO
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT                                           0x2
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_HI
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_MSG_DATA
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_CONTROL
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT                                              0x0
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK                                                0x00000001L
+//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT4_ADDR_LO
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT4_ADDR_LO__MSG_ADDR_LO__SHIFT                                           0x2
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT4_ADDR_LO__MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT4_ADDR_HI
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT4_ADDR_HI__MSG_ADDR_HI__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT4_ADDR_HI__MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT4_MSG_DATA
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT4_MSG_DATA__MSG_DATA__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT4_MSG_DATA__MSG_DATA_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT4_CONTROL
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT4_CONTROL__MASK_BIT__SHIFT                                              0x0
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT4_CONTROL__MASK_BIT_MASK                                                0x00000001L
+//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT5_ADDR_LO
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT5_ADDR_LO__MSG_ADDR_LO__SHIFT                                           0x2
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT5_ADDR_LO__MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT5_ADDR_HI
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT5_ADDR_HI__MSG_ADDR_HI__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT5_ADDR_HI__MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT5_MSG_DATA
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT5_MSG_DATA__MSG_DATA__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT5_MSG_DATA__MSG_DATA_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT5_CONTROL
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT5_CONTROL__MASK_BIT__SHIFT                                              0x0
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT5_CONTROL__MASK_BIT_MASK                                                0x00000001L
+//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT6_ADDR_LO
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT6_ADDR_LO__MSG_ADDR_LO__SHIFT                                           0x2
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT6_ADDR_LO__MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT6_ADDR_HI
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT6_ADDR_HI__MSG_ADDR_HI__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT6_ADDR_HI__MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT6_MSG_DATA
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT6_MSG_DATA__MSG_DATA__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT6_MSG_DATA__MSG_DATA_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT6_CONTROL
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT6_CONTROL__MASK_BIT__SHIFT                                              0x0
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT6_CONTROL__MASK_BIT_MASK                                                0x00000001L
+//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT7_ADDR_LO
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT7_ADDR_LO__MSG_ADDR_LO__SHIFT                                           0x2
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT7_ADDR_LO__MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT7_ADDR_HI
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT7_ADDR_HI__MSG_ADDR_HI__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT7_ADDR_HI__MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT7_MSG_DATA
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT7_MSG_DATA__MSG_DATA__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT7_MSG_DATA__MSG_DATA_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT7_CONTROL
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT7_CONTROL__MASK_BIT__SHIFT                                              0x0
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT7_CONTROL__MASK_BIT_MASK                                                0x00000001L
+//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT8_ADDR_LO
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT8_ADDR_LO__MSG_ADDR_LO__SHIFT                                           0x2
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT8_ADDR_LO__MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT8_ADDR_HI
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT8_ADDR_HI__MSG_ADDR_HI__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT8_ADDR_HI__MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT8_MSG_DATA
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT8_MSG_DATA__MSG_DATA__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT8_MSG_DATA__MSG_DATA_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF6_GFXMSIX_VECT8_CONTROL
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT8_CONTROL__MASK_BIT__SHIFT                                              0x0
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_VECT8_CONTROL__MASK_BIT_MASK                                                0x00000001L
+//RCC_DEV0_EPF0_VF6_GFXMSIX_PBA
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT                                             0x1
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK                                               0x00000001L
+#define RCC_DEV0_EPF0_VF6_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK                                               0x00000002L
+
+
+// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf7_BIFPFVFDEC1
+//BIF_BX_DEV0_EPF0_VF7_0_BIF_BME_STATUS
+#define BIF_BX_DEV0_EPF0_VF7_0_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT                                          0x0
+#define BIF_BX_DEV0_EPF0_VF7_0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT                                    0x10
+#define BIF_BX_DEV0_EPF0_VF7_0_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK                                            0x00000001L
+#define BIF_BX_DEV0_EPF0_VF7_0_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK                                      0x00010000L
+//BIF_BX_DEV0_EPF0_VF7_0_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_DEV0_EPF0_VF7_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT                                    0x0
+#define BIF_BX_DEV0_EPF0_VF7_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT                                 0x1
+#define BIF_BX_DEV0_EPF0_VF7_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT                                    0x2
+#define BIF_BX_DEV0_EPF0_VF7_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT                                        0x3
+#define BIF_BX_DEV0_EPF0_VF7_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT                              0x10
+#define BIF_BX_DEV0_EPF0_VF7_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT                           0x11
+#define BIF_BX_DEV0_EPF0_VF7_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT                              0x12
+#define BIF_BX_DEV0_EPF0_VF7_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT                                  0x13
+#define BIF_BX_DEV0_EPF0_VF7_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK                                      0x00000001L
+#define BIF_BX_DEV0_EPF0_VF7_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK                                   0x00000002L
+#define BIF_BX_DEV0_EPF0_VF7_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK                                      0x00000004L
+#define BIF_BX_DEV0_EPF0_VF7_0_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK                                          0x00000008L
+#define BIF_BX_DEV0_EPF0_VF7_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK                                0x00010000L
+#define BIF_BX_DEV0_EPF0_VF7_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK                             0x00020000L
+#define BIF_BX_DEV0_EPF0_VF7_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK                                0x00040000L
+#define BIF_BX_DEV0_EPF0_VF7_0_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK                                    0x00080000L
+//BIF_BX_DEV0_EPF0_VF7_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_DEV0_EPF0_VF7_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT  0x0
+#define BIF_BX_DEV0_EPF0_VF7_0_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK  0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF7_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_DEV0_EPF0_VF7_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT  0x0
+#define BIF_BX_DEV0_EPF0_VF7_0_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK  0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF7_0_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_DEV0_EPF0_VF7_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT          0x0
+#define BIF_BX_DEV0_EPF0_VF7_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT        0x1
+#define BIF_BX_DEV0_EPF0_VF7_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT        0x8
+#define BIF_BX_DEV0_EPF0_VF7_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK            0x00000001L
+#define BIF_BX_DEV0_EPF0_VF7_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK          0x00000002L
+#define BIF_BX_DEV0_EPF0_VF7_0_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK          0x000FFF00L
+//BIF_BX_DEV0_EPF0_VF7_0_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF7_0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT                        0x0
+#define BIF_BX_DEV0_EPF0_VF7_0_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK                          0x00000001L
+//BIF_BX_DEV0_EPF0_VF7_0_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF7_0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT                        0x0
+#define BIF_BX_DEV0_EPF0_VF7_0_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK                          0x00000001L
+//BIF_BX_DEV0_EPF0_VF7_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL
+#define BIF_BX_DEV0_EPF0_VF7_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT              0x0
+#define BIF_BX_DEV0_EPF0_VF7_0_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK                0x00000001L
+//BIF_BX_DEV0_EPF0_VF7_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL
+#define BIF_BX_DEV0_EPF0_VF7_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT    0x0
+#define BIF_BX_DEV0_EPF0_VF7_0_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK      0x00000001L
+//BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__CP0__SHIFT                                                  0x0
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__CP1__SHIFT                                                  0x1
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__CP2__SHIFT                                                  0x2
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__CP3__SHIFT                                                  0x3
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__CP4__SHIFT                                                  0x4
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__CP5__SHIFT                                                  0x5
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__CP6__SHIFT                                                  0x6
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__CP7__SHIFT                                                  0x7
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__CP8__SHIFT                                                  0x8
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__CP9__SHIFT                                                  0x9
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT                                                0xa
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT                                                0xb
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT                                            0xc
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT                                            0xd
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT                                            0xe
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT                                            0xf
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT                                            0x10
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT                                            0x11
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT                                            0x12
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT                                            0x13
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT                                            0x14
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT                                            0x15
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT                                           0x16
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT                                           0x17
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT                                           0x18
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT                                           0x19
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT                                           0x1a
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT                                           0x1b
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT                                           0x1c
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT                                           0x1d
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT                                           0x1e
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT                                           0x1f
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__CP0_MASK                                                    0x00000001L
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__CP1_MASK                                                    0x00000002L
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__CP2_MASK                                                    0x00000004L
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__CP3_MASK                                                    0x00000008L
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__CP4_MASK                                                    0x00000010L
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__CP5_MASK                                                    0x00000020L
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__CP6_MASK                                                    0x00000040L
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__CP7_MASK                                                    0x00000080L
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__CP8_MASK                                                    0x00000100L
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__CP9_MASK                                                    0x00000200L
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__SDMA0_MASK                                                  0x00000400L
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__SDMA1_MASK                                                  0x00000800L
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK                                              0x00001000L
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK                                              0x00002000L
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK                                              0x00004000L
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK                                              0x00008000L
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK                                              0x00010000L
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK                                              0x00020000L
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK                                              0x00040000L
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK                                              0x00080000L
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK                                              0x00100000L
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK                                              0x00200000L
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK                                             0x00400000L
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK                                             0x00800000L
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK                                             0x01000000L
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK                                             0x02000000L
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK                                             0x04000000L
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK                                             0x08000000L
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK                                             0x10000000L
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK                                             0x20000000L
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK                                             0x40000000L
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK                                             0x80000000L
+//BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__CP0__SHIFT                                                 0x0
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__CP1__SHIFT                                                 0x1
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__CP2__SHIFT                                                 0x2
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__CP3__SHIFT                                                 0x3
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__CP4__SHIFT                                                 0x4
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__CP5__SHIFT                                                 0x5
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__CP6__SHIFT                                                 0x6
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__CP7__SHIFT                                                 0x7
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__CP8__SHIFT                                                 0x8
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__CP9__SHIFT                                                 0x9
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT                                               0xa
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT                                               0xb
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT                                           0xc
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT                                           0xd
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT                                           0xe
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT                                           0xf
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT                                           0x10
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT                                           0x11
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT                                           0x12
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT                                           0x13
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT                                           0x14
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT                                           0x15
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT                                          0x16
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT                                          0x17
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT                                          0x18
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT                                          0x19
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT                                          0x1a
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT                                          0x1b
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT                                          0x1c
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT                                          0x1d
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT                                          0x1e
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT                                          0x1f
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__CP0_MASK                                                   0x00000001L
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__CP1_MASK                                                   0x00000002L
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__CP2_MASK                                                   0x00000004L
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__CP3_MASK                                                   0x00000008L
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__CP4_MASK                                                   0x00000010L
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__CP5_MASK                                                   0x00000020L
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__CP6_MASK                                                   0x00000040L
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__CP7_MASK                                                   0x00000080L
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__CP8_MASK                                                   0x00000100L
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__CP9_MASK                                                   0x00000200L
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__SDMA0_MASK                                                 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__SDMA1_MASK                                                 0x00000800L
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK                                             0x00001000L
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK                                             0x00002000L
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK                                             0x00004000L
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK                                             0x00008000L
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK                                             0x00010000L
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK                                             0x00020000L
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK                                             0x00040000L
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK                                             0x00080000L
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK                                             0x00100000L
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK                                             0x00200000L
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK                                            0x00400000L
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK                                            0x00800000L
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK                                            0x01000000L
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK                                            0x02000000L
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK                                            0x04000000L
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK                                            0x08000000L
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK                                            0x10000000L
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK                                            0x20000000L
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK                                            0x40000000L
+#define BIF_BX_DEV0_EPF0_VF7_0_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK                                            0x80000000L
+//BIF_BX_DEV0_EPF0_VF7_0_BIF_TRANS_PENDING
+#define BIF_BX_DEV0_EPF0_VF7_0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT                                0x0
+#define BIF_BX_DEV0_EPF0_VF7_0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT                                0x1
+#define BIF_BX_DEV0_EPF0_VF7_0_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK                                  0x00000001L
+#define BIF_BX_DEV0_EPF0_VF7_0_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK                                  0x00000002L
+//BIF_BX_DEV0_EPF0_VF7_0_NBIF_GFX_ADDR_LUT_BYPASS
+#define BIF_BX_DEV0_EPF0_VF7_0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT                                    0x0
+#define BIF_BX_DEV0_EPF0_VF7_0_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK                                      0x00000001L
+//BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_CONTROL
+#define BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT                                          0x0
+#define BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT                                            0x1
+#define BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT                                          0x8
+#define BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT                                            0x9
+#define BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_CONTROL__TRN_MSG_VALID_MASK                                            0x00000001L
+#define BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_CONTROL__TRN_MSG_ACK_MASK                                              0x00000002L
+#define BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_CONTROL__RCV_MSG_VALID_MASK                                            0x00000100L
+#define BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_CONTROL__RCV_MSG_ACK_MASK                                              0x00000200L
+//BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_INT_CNTL
+#define BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT                                          0x0
+#define BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT                                            0x1
+#define BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_INT_CNTL__VALID_INT_EN_MASK                                            0x00000001L
+#define BIF_BX_DEV0_EPF0_VF7_0_MAILBOX_INT_CNTL__ACK_INT_EN_MASK                                              0x00000002L
+//BIF_BX_DEV0_EPF0_VF7_0_BIF_VMHV_MAILBOX
+#define BIF_BX_DEV0_EPF0_VF7_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT                          0x0
+#define BIF_BX_DEV0_EPF0_VF7_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT                        0x1
+#define BIF_BX_DEV0_EPF0_VF7_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT                             0x8
+#define BIF_BX_DEV0_EPF0_VF7_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT                            0xf
+#define BIF_BX_DEV0_EPF0_VF7_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT                             0x10
+#define BIF_BX_DEV0_EPF0_VF7_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT                            0x17
+#define BIF_BX_DEV0_EPF0_VF7_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT                              0x18
+#define BIF_BX_DEV0_EPF0_VF7_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT                              0x19
+#define BIF_BX_DEV0_EPF0_VF7_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK                            0x00000001L
+#define BIF_BX_DEV0_EPF0_VF7_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK                          0x00000002L
+#define BIF_BX_DEV0_EPF0_VF7_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK                               0x00000F00L
+#define BIF_BX_DEV0_EPF0_VF7_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK                              0x00008000L
+#define BIF_BX_DEV0_EPF0_VF7_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK                               0x000F0000L
+#define BIF_BX_DEV0_EPF0_VF7_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK                              0x00800000L
+#define BIF_BX_DEV0_EPF0_VF7_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK                                0x01000000L
+#define BIF_BX_DEV0_EPF0_VF7_0_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK                                0x02000000L
+//BIF_BX_DEV0_EPF0_VF7_0_PARTITION_COMPUTE_CAP
+#define BIF_BX_DEV0_EPF0_VF7_0_PARTITION_COMPUTE_CAP__SPX_SUPPORT__SHIFT                                      0x0
+#define BIF_BX_DEV0_EPF0_VF7_0_PARTITION_COMPUTE_CAP__DPX_SUPPORT__SHIFT                                      0x1
+#define BIF_BX_DEV0_EPF0_VF7_0_PARTITION_COMPUTE_CAP__TPX_SUPPORT__SHIFT                                      0x2
+#define BIF_BX_DEV0_EPF0_VF7_0_PARTITION_COMPUTE_CAP__QPX_SUPPORT__SHIFT                                      0x3
+#define BIF_BX_DEV0_EPF0_VF7_0_PARTITION_COMPUTE_CAP__CPX_SUPPORT__SHIFT                                      0x4
+#define BIF_BX_DEV0_EPF0_VF7_0_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY__SHIFT                                 0xa
+#define BIF_BX_DEV0_EPF0_VF7_0_PARTITION_COMPUTE_CAP__SPX_SUPPORT_MASK                                        0x00000001L
+#define BIF_BX_DEV0_EPF0_VF7_0_PARTITION_COMPUTE_CAP__DPX_SUPPORT_MASK                                        0x00000002L
+#define BIF_BX_DEV0_EPF0_VF7_0_PARTITION_COMPUTE_CAP__TPX_SUPPORT_MASK                                        0x00000004L
+#define BIF_BX_DEV0_EPF0_VF7_0_PARTITION_COMPUTE_CAP__QPX_SUPPORT_MASK                                        0x00000008L
+#define BIF_BX_DEV0_EPF0_VF7_0_PARTITION_COMPUTE_CAP__CPX_SUPPORT_MASK                                        0x00000010L
+#define BIF_BX_DEV0_EPF0_VF7_0_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY_MASK                                   0x0003FC00L
+//BIF_BX_DEV0_EPF0_VF7_0_PARTITION_MEM_CAP
+#define BIF_BX_DEV0_EPF0_VF7_0_PARTITION_MEM_CAP__NPS1_SUPPORT__SHIFT                                         0x0
+#define BIF_BX_DEV0_EPF0_VF7_0_PARTITION_MEM_CAP__NPS2_SUPPORT__SHIFT                                         0x1
+#define BIF_BX_DEV0_EPF0_VF7_0_PARTITION_MEM_CAP__NPS3_SUPPORT__SHIFT                                         0x2
+#define BIF_BX_DEV0_EPF0_VF7_0_PARTITION_MEM_CAP__NPS4_SUPPORT__SHIFT                                         0x3
+#define BIF_BX_DEV0_EPF0_VF7_0_PARTITION_MEM_CAP__NPS6_SUPPORT__SHIFT                                         0x5
+#define BIF_BX_DEV0_EPF0_VF7_0_PARTITION_MEM_CAP__NPS8_SUPPORT__SHIFT                                         0x7
+#define BIF_BX_DEV0_EPF0_VF7_0_PARTITION_MEM_CAP__NPS1_SUPPORT_MASK                                           0x00000001L
+#define BIF_BX_DEV0_EPF0_VF7_0_PARTITION_MEM_CAP__NPS2_SUPPORT_MASK                                           0x00000002L
+#define BIF_BX_DEV0_EPF0_VF7_0_PARTITION_MEM_CAP__NPS3_SUPPORT_MASK                                           0x00000004L
+#define BIF_BX_DEV0_EPF0_VF7_0_PARTITION_MEM_CAP__NPS4_SUPPORT_MASK                                           0x00000008L
+#define BIF_BX_DEV0_EPF0_VF7_0_PARTITION_MEM_CAP__NPS6_SUPPORT_MASK                                           0x00000020L
+#define BIF_BX_DEV0_EPF0_VF7_0_PARTITION_MEM_CAP__NPS8_SUPPORT_MASK                                           0x00000080L
+//BIF_BX_DEV0_EPF0_VF7_0_PARTITION_COMPUTE_STATUS
+#define BIF_BX_DEV0_EPF0_VF7_0_PARTITION_COMPUTE_STATUS__PARTITION_MODE__SHIFT                                0x4
+#define BIF_BX_DEV0_EPF0_VF7_0_PARTITION_COMPUTE_STATUS__PARTITION_MODE_MASK                                  0x000000F0L
+//BIF_BX_DEV0_EPF0_VF7_0_PARTITION_MEM_STATUS
+#define BIF_BX_DEV0_EPF0_VF7_0_PARTITION_MEM_STATUS__CHANGE_STATUS__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF7_0_PARTITION_MEM_STATUS__NPS_MODE__SHIFT                                          0x4
+#define BIF_BX_DEV0_EPF0_VF7_0_PARTITION_MEM_STATUS__CHANGE_STATUS_MASK                                       0x0000000FL
+#define BIF_BX_DEV0_EPF0_VF7_0_PARTITION_MEM_STATUS__NPS_MODE_MASK                                            0x00000FF0L
+
+
+// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf7_SYSPFVFDEC
+//BIF_BX_DEV0_EPF0_VF7_0_MM_INDEX
+#define BIF_BX_DEV0_EPF0_VF7_0_MM_INDEX__MM_OFFSET__SHIFT                                                     0x0
+#define BIF_BX_DEV0_EPF0_VF7_0_MM_INDEX__MM_APER__SHIFT                                                       0x1f
+#define BIF_BX_DEV0_EPF0_VF7_0_MM_INDEX__MM_OFFSET_MASK                                                       0x7FFFFFFFL
+#define BIF_BX_DEV0_EPF0_VF7_0_MM_INDEX__MM_APER_MASK                                                         0x80000000L
+//BIF_BX_DEV0_EPF0_VF7_0_MM_DATA
+#define BIF_BX_DEV0_EPF0_VF7_0_MM_DATA__MM_DATA__SHIFT                                                        0x0
+#define BIF_BX_DEV0_EPF0_VF7_0_MM_DATA__MM_DATA_MASK                                                          0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF7_0_MM_INDEX_HI
+#define BIF_BX_DEV0_EPF0_VF7_0_MM_INDEX_HI__MM_OFFSET_HI__SHIFT                                               0x0
+#define BIF_BX_DEV0_EPF0_VF7_0_MM_INDEX_HI__MM_OFFSET_HI_MASK                                                 0xFFFFFFFFL
+
+
+// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf7_BIFPFVFDEC1:1
+//BIF_BX_DEV0_EPF0_VF7_1_BIF_BME_STATUS
+#define BIF_BX_DEV0_EPF0_VF7_1_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT                                          0x0
+#define BIF_BX_DEV0_EPF0_VF7_1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT                                    0x10
+#define BIF_BX_DEV0_EPF0_VF7_1_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK                                            0x00000001L
+#define BIF_BX_DEV0_EPF0_VF7_1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK                                      0x00010000L
+//BIF_BX_DEV0_EPF0_VF7_1_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_DEV0_EPF0_VF7_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT                                    0x0
+#define BIF_BX_DEV0_EPF0_VF7_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT                                 0x1
+#define BIF_BX_DEV0_EPF0_VF7_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT                                    0x2
+#define BIF_BX_DEV0_EPF0_VF7_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT                                        0x3
+#define BIF_BX_DEV0_EPF0_VF7_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT                              0x10
+#define BIF_BX_DEV0_EPF0_VF7_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT                           0x11
+#define BIF_BX_DEV0_EPF0_VF7_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT                              0x12
+#define BIF_BX_DEV0_EPF0_VF7_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT                                  0x13
+#define BIF_BX_DEV0_EPF0_VF7_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK                                      0x00000001L
+#define BIF_BX_DEV0_EPF0_VF7_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK                                   0x00000002L
+#define BIF_BX_DEV0_EPF0_VF7_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK                                      0x00000004L
+#define BIF_BX_DEV0_EPF0_VF7_1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK                                          0x00000008L
+#define BIF_BX_DEV0_EPF0_VF7_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK                                0x00010000L
+#define BIF_BX_DEV0_EPF0_VF7_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK                             0x00020000L
+#define BIF_BX_DEV0_EPF0_VF7_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK                                0x00040000L
+#define BIF_BX_DEV0_EPF0_VF7_1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK                                    0x00080000L
+//BIF_BX_DEV0_EPF0_VF7_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_DEV0_EPF0_VF7_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT  0x0
+#define BIF_BX_DEV0_EPF0_VF7_1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK  0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF7_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_DEV0_EPF0_VF7_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT  0x0
+#define BIF_BX_DEV0_EPF0_VF7_1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK  0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF7_1_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_DEV0_EPF0_VF7_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT          0x0
+#define BIF_BX_DEV0_EPF0_VF7_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT        0x1
+#define BIF_BX_DEV0_EPF0_VF7_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT        0x8
+#define BIF_BX_DEV0_EPF0_VF7_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK            0x00000001L
+#define BIF_BX_DEV0_EPF0_VF7_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK          0x00000002L
+#define BIF_BX_DEV0_EPF0_VF7_1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK          0x000FFF00L
+//BIF_BX_DEV0_EPF0_VF7_1_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF7_1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT                        0x0
+#define BIF_BX_DEV0_EPF0_VF7_1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK                          0x00000001L
+//BIF_BX_DEV0_EPF0_VF7_1_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_DEV0_EPF0_VF7_1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT                        0x0
+#define BIF_BX_DEV0_EPF0_VF7_1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK                          0x00000001L
+//BIF_BX_DEV0_EPF0_VF7_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL
+#define BIF_BX_DEV0_EPF0_VF7_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT              0x0
+#define BIF_BX_DEV0_EPF0_VF7_1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK                0x00000001L
+//BIF_BX_DEV0_EPF0_VF7_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL
+#define BIF_BX_DEV0_EPF0_VF7_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT    0x0
+#define BIF_BX_DEV0_EPF0_VF7_1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK      0x00000001L
+//BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__CP0__SHIFT                                                  0x0
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__CP1__SHIFT                                                  0x1
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__CP2__SHIFT                                                  0x2
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__CP3__SHIFT                                                  0x3
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__CP4__SHIFT                                                  0x4
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__CP5__SHIFT                                                  0x5
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__CP6__SHIFT                                                  0x6
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__CP7__SHIFT                                                  0x7
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__CP8__SHIFT                                                  0x8
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__CP9__SHIFT                                                  0x9
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT                                                0xa
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT                                                0xb
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT                                            0xc
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT                                            0xd
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT                                            0xe
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT                                            0xf
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT                                            0x10
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT                                            0x11
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT                                            0x12
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT                                            0x13
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT                                            0x14
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT                                            0x15
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT                                           0x16
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT                                           0x17
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT                                           0x18
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT                                           0x19
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT                                           0x1a
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT                                           0x1b
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT                                           0x1c
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT                                           0x1d
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT                                           0x1e
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT                                           0x1f
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__CP0_MASK                                                    0x00000001L
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__CP1_MASK                                                    0x00000002L
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__CP2_MASK                                                    0x00000004L
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__CP3_MASK                                                    0x00000008L
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__CP4_MASK                                                    0x00000010L
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__CP5_MASK                                                    0x00000020L
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__CP6_MASK                                                    0x00000040L
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__CP7_MASK                                                    0x00000080L
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__CP8_MASK                                                    0x00000100L
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__CP9_MASK                                                    0x00000200L
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__SDMA0_MASK                                                  0x00000400L
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__SDMA1_MASK                                                  0x00000800L
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK                                              0x00001000L
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK                                              0x00002000L
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK                                              0x00004000L
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK                                              0x00008000L
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK                                              0x00010000L
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK                                              0x00020000L
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK                                              0x00040000L
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK                                              0x00080000L
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK                                              0x00100000L
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK                                              0x00200000L
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK                                             0x00400000L
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK                                             0x00800000L
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK                                             0x01000000L
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK                                             0x02000000L
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK                                             0x04000000L
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK                                             0x08000000L
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK                                             0x10000000L
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK                                             0x20000000L
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK                                             0x40000000L
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK                                             0x80000000L
+//BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__CP0__SHIFT                                                 0x0
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__CP1__SHIFT                                                 0x1
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__CP2__SHIFT                                                 0x2
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__CP3__SHIFT                                                 0x3
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__CP4__SHIFT                                                 0x4
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__CP5__SHIFT                                                 0x5
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__CP6__SHIFT                                                 0x6
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__CP7__SHIFT                                                 0x7
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__CP8__SHIFT                                                 0x8
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__CP9__SHIFT                                                 0x9
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT                                               0xa
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT                                               0xb
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT                                           0xc
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT                                           0xd
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT                                           0xe
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT                                           0xf
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT                                           0x10
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT                                           0x11
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT                                           0x12
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT                                           0x13
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT                                           0x14
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT                                           0x15
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT                                          0x16
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT                                          0x17
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT                                          0x18
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT                                          0x19
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT                                          0x1a
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT                                          0x1b
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT                                          0x1c
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT                                          0x1d
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT                                          0x1e
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT                                          0x1f
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__CP0_MASK                                                   0x00000001L
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__CP1_MASK                                                   0x00000002L
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__CP2_MASK                                                   0x00000004L
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__CP3_MASK                                                   0x00000008L
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__CP4_MASK                                                   0x00000010L
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__CP5_MASK                                                   0x00000020L
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__CP6_MASK                                                   0x00000040L
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__CP7_MASK                                                   0x00000080L
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__CP8_MASK                                                   0x00000100L
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__CP9_MASK                                                   0x00000200L
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__SDMA0_MASK                                                 0x00000400L
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__SDMA1_MASK                                                 0x00000800L
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK                                             0x00001000L
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK                                             0x00002000L
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK                                             0x00004000L
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK                                             0x00008000L
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK                                             0x00010000L
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK                                             0x00020000L
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK                                             0x00040000L
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK                                             0x00080000L
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK                                             0x00100000L
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK                                             0x00200000L
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK                                            0x00400000L
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK                                            0x00800000L
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK                                            0x01000000L
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK                                            0x02000000L
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK                                            0x04000000L
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK                                            0x08000000L
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK                                            0x10000000L
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK                                            0x20000000L
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK                                            0x40000000L
+#define BIF_BX_DEV0_EPF0_VF7_1_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK                                            0x80000000L
+//BIF_BX_DEV0_EPF0_VF7_1_BIF_TRANS_PENDING
+#define BIF_BX_DEV0_EPF0_VF7_1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT                                0x0
+#define BIF_BX_DEV0_EPF0_VF7_1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT                                0x1
+#define BIF_BX_DEV0_EPF0_VF7_1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK                                  0x00000001L
+#define BIF_BX_DEV0_EPF0_VF7_1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK                                  0x00000002L
+//BIF_BX_DEV0_EPF0_VF7_1_NBIF_GFX_ADDR_LUT_BYPASS
+#define BIF_BX_DEV0_EPF0_VF7_1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT                                    0x0
+#define BIF_BX_DEV0_EPF0_VF7_1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK                                      0x00000001L
+//BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK                                       0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_CONTROL
+#define BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT                                          0x0
+#define BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT                                            0x1
+#define BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT                                          0x8
+#define BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT                                            0x9
+#define BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_CONTROL__TRN_MSG_VALID_MASK                                            0x00000001L
+#define BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_CONTROL__TRN_MSG_ACK_MASK                                              0x00000002L
+#define BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_CONTROL__RCV_MSG_VALID_MASK                                            0x00000100L
+#define BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_CONTROL__RCV_MSG_ACK_MASK                                              0x00000200L
+//BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_INT_CNTL
+#define BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT                                          0x0
+#define BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT                                            0x1
+#define BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_INT_CNTL__VALID_INT_EN_MASK                                            0x00000001L
+#define BIF_BX_DEV0_EPF0_VF7_1_MAILBOX_INT_CNTL__ACK_INT_EN_MASK                                              0x00000002L
+//BIF_BX_DEV0_EPF0_VF7_1_BIF_VMHV_MAILBOX
+#define BIF_BX_DEV0_EPF0_VF7_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT                          0x0
+#define BIF_BX_DEV0_EPF0_VF7_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT                        0x1
+#define BIF_BX_DEV0_EPF0_VF7_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT                             0x8
+#define BIF_BX_DEV0_EPF0_VF7_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT                            0xf
+#define BIF_BX_DEV0_EPF0_VF7_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT                             0x10
+#define BIF_BX_DEV0_EPF0_VF7_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT                            0x17
+#define BIF_BX_DEV0_EPF0_VF7_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT                              0x18
+#define BIF_BX_DEV0_EPF0_VF7_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT                              0x19
+#define BIF_BX_DEV0_EPF0_VF7_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK                            0x00000001L
+#define BIF_BX_DEV0_EPF0_VF7_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK                          0x00000002L
+#define BIF_BX_DEV0_EPF0_VF7_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK                               0x00000F00L
+#define BIF_BX_DEV0_EPF0_VF7_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK                              0x00008000L
+#define BIF_BX_DEV0_EPF0_VF7_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK                               0x000F0000L
+#define BIF_BX_DEV0_EPF0_VF7_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK                              0x00800000L
+#define BIF_BX_DEV0_EPF0_VF7_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK                                0x01000000L
+#define BIF_BX_DEV0_EPF0_VF7_1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK                                0x02000000L
+//BIF_BX_DEV0_EPF0_VF7_1_PARTITION_COMPUTE_CAP
+#define BIF_BX_DEV0_EPF0_VF7_1_PARTITION_COMPUTE_CAP__SPX_SUPPORT__SHIFT                                      0x0
+#define BIF_BX_DEV0_EPF0_VF7_1_PARTITION_COMPUTE_CAP__DPX_SUPPORT__SHIFT                                      0x1
+#define BIF_BX_DEV0_EPF0_VF7_1_PARTITION_COMPUTE_CAP__TPX_SUPPORT__SHIFT                                      0x2
+#define BIF_BX_DEV0_EPF0_VF7_1_PARTITION_COMPUTE_CAP__QPX_SUPPORT__SHIFT                                      0x3
+#define BIF_BX_DEV0_EPF0_VF7_1_PARTITION_COMPUTE_CAP__CPX_SUPPORT__SHIFT                                      0x4
+#define BIF_BX_DEV0_EPF0_VF7_1_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY__SHIFT                                 0xa
+#define BIF_BX_DEV0_EPF0_VF7_1_PARTITION_COMPUTE_CAP__SPX_SUPPORT_MASK                                        0x00000001L
+#define BIF_BX_DEV0_EPF0_VF7_1_PARTITION_COMPUTE_CAP__DPX_SUPPORT_MASK                                        0x00000002L
+#define BIF_BX_DEV0_EPF0_VF7_1_PARTITION_COMPUTE_CAP__TPX_SUPPORT_MASK                                        0x00000004L
+#define BIF_BX_DEV0_EPF0_VF7_1_PARTITION_COMPUTE_CAP__QPX_SUPPORT_MASK                                        0x00000008L
+#define BIF_BX_DEV0_EPF0_VF7_1_PARTITION_COMPUTE_CAP__CPX_SUPPORT_MASK                                        0x00000010L
+#define BIF_BX_DEV0_EPF0_VF7_1_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY_MASK                                   0x0003FC00L
+//BIF_BX_DEV0_EPF0_VF7_1_PARTITION_MEM_CAP
+#define BIF_BX_DEV0_EPF0_VF7_1_PARTITION_MEM_CAP__NPS1_SUPPORT__SHIFT                                         0x0
+#define BIF_BX_DEV0_EPF0_VF7_1_PARTITION_MEM_CAP__NPS2_SUPPORT__SHIFT                                         0x1
+#define BIF_BX_DEV0_EPF0_VF7_1_PARTITION_MEM_CAP__NPS3_SUPPORT__SHIFT                                         0x2
+#define BIF_BX_DEV0_EPF0_VF7_1_PARTITION_MEM_CAP__NPS4_SUPPORT__SHIFT                                         0x3
+#define BIF_BX_DEV0_EPF0_VF7_1_PARTITION_MEM_CAP__NPS6_SUPPORT__SHIFT                                         0x5
+#define BIF_BX_DEV0_EPF0_VF7_1_PARTITION_MEM_CAP__NPS8_SUPPORT__SHIFT                                         0x7
+#define BIF_BX_DEV0_EPF0_VF7_1_PARTITION_MEM_CAP__NPS1_SUPPORT_MASK                                           0x00000001L
+#define BIF_BX_DEV0_EPF0_VF7_1_PARTITION_MEM_CAP__NPS2_SUPPORT_MASK                                           0x00000002L
+#define BIF_BX_DEV0_EPF0_VF7_1_PARTITION_MEM_CAP__NPS3_SUPPORT_MASK                                           0x00000004L
+#define BIF_BX_DEV0_EPF0_VF7_1_PARTITION_MEM_CAP__NPS4_SUPPORT_MASK                                           0x00000008L
+#define BIF_BX_DEV0_EPF0_VF7_1_PARTITION_MEM_CAP__NPS6_SUPPORT_MASK                                           0x00000020L
+#define BIF_BX_DEV0_EPF0_VF7_1_PARTITION_MEM_CAP__NPS8_SUPPORT_MASK                                           0x00000080L
+//BIF_BX_DEV0_EPF0_VF7_1_PARTITION_COMPUTE_STATUS
+#define BIF_BX_DEV0_EPF0_VF7_1_PARTITION_COMPUTE_STATUS__PARTITION_MODE__SHIFT                                0x4
+#define BIF_BX_DEV0_EPF0_VF7_1_PARTITION_COMPUTE_STATUS__PARTITION_MODE_MASK                                  0x000000F0L
+//BIF_BX_DEV0_EPF0_VF7_1_PARTITION_MEM_STATUS
+#define BIF_BX_DEV0_EPF0_VF7_1_PARTITION_MEM_STATUS__CHANGE_STATUS__SHIFT                                     0x0
+#define BIF_BX_DEV0_EPF0_VF7_1_PARTITION_MEM_STATUS__NPS_MODE__SHIFT                                          0x4
+#define BIF_BX_DEV0_EPF0_VF7_1_PARTITION_MEM_STATUS__CHANGE_STATUS_MASK                                       0x0000000FL
+#define BIF_BX_DEV0_EPF0_VF7_1_PARTITION_MEM_STATUS__NPS_MODE_MASK                                            0x00000FF0L
+
+
+// addressBlock: nbif0_nbif0_bif_bx_dev0_epf0_vf7_SYSPFVFDEC:1
+//BIF_BX_DEV0_EPF0_VF7_1_MM_INDEX
+#define BIF_BX_DEV0_EPF0_VF7_1_MM_INDEX__MM_OFFSET__SHIFT                                                     0x0
+#define BIF_BX_DEV0_EPF0_VF7_1_MM_INDEX__MM_APER__SHIFT                                                       0x1f
+#define BIF_BX_DEV0_EPF0_VF7_1_MM_INDEX__MM_OFFSET_MASK                                                       0x7FFFFFFFL
+#define BIF_BX_DEV0_EPF0_VF7_1_MM_INDEX__MM_APER_MASK                                                         0x80000000L
+//BIF_BX_DEV0_EPF0_VF7_1_MM_DATA
+#define BIF_BX_DEV0_EPF0_VF7_1_MM_DATA__MM_DATA__SHIFT                                                        0x0
+#define BIF_BX_DEV0_EPF0_VF7_1_MM_DATA__MM_DATA_MASK                                                          0xFFFFFFFFL
+//BIF_BX_DEV0_EPF0_VF7_1_MM_INDEX_HI
+#define BIF_BX_DEV0_EPF0_VF7_1_MM_INDEX_HI__MM_OFFSET_HI__SHIFT                                               0x0
+#define BIF_BX_DEV0_EPF0_VF7_1_MM_INDEX_HI__MM_OFFSET_HI_MASK                                                 0xFFFFFFFFL
+
+
+// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf7_BIFPFVFDEC1
+//RCC_DEV0_EPF0_VF7_RCC_ERR_LOG
+#define RCC_DEV0_EPF0_VF7_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS__SHIFT                              0x0
+#define RCC_DEV0_EPF0_VF7_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS__SHIFT                                     0x1
+#define RCC_DEV0_EPF0_VF7_RCC_ERR_LOG__INVALID_REG_ACCESS_IN_SRIOV_STATUS_MASK                                0x00000001L
+#define RCC_DEV0_EPF0_VF7_RCC_ERR_LOG__DOORBELL_READ_ACCESS_STATUS_MASK                                       0x00000002L
+//RCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN
+#define RCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN__SHIFT                                   0x0
+#define RCC_DEV0_EPF0_VF7_RCC_DOORBELL_APER_EN__BIF_DOORBELL_APER_EN_MASK                                     0x00000001L
+//RCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE
+#define RCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_VF7_RCC_CONFIG_MEMSIZE__CONFIG_MEMSIZE_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED
+#define RCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED__CONFIG_RESERVED__SHIFT                                         0x0
+#define RCC_DEV0_EPF0_VF7_RCC_CONFIG_RESERVED__CONFIG_RESERVED_MASK                                           0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER
+#define RCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER__SHIFT                                     0x0
+#define RCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE__SHIFT                                          0x1f
+#define RCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER__FUNC_IDENTIFIER_MASK                                       0x00000001L
+#define RCC_DEV0_EPF0_VF7_RCC_IOV_FUNC_IDENTIFIER__IOV_ENABLE_MASK                                            0x80000000L
+
+
+// addressBlock: nbif0_nbif0_rcc_dev0_epf0_vf7_BIFDEC2
+//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO__SHIFT                                           0x2
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_LO__MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_ADDR_HI__MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA__MSG_DATA__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_MSG_DATA__MSG_DATA_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL__MASK_BIT__SHIFT                                              0x0
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT0_CONTROL__MASK_BIT_MASK                                                0x00000001L
+//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO__SHIFT                                           0x2
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_LO__MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_ADDR_HI__MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA__MSG_DATA__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_MSG_DATA__MSG_DATA_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL__MASK_BIT__SHIFT                                              0x0
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT1_CONTROL__MASK_BIT_MASK                                                0x00000001L
+//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO__SHIFT                                           0x2
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_LO__MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_ADDR_HI__MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA__MSG_DATA__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_MSG_DATA__MSG_DATA_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL__MASK_BIT__SHIFT                                              0x0
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT2_CONTROL__MASK_BIT_MASK                                                0x00000001L
+//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_LO
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO__SHIFT                                           0x2
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_LO__MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_HI
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_ADDR_HI__MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_MSG_DATA
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_MSG_DATA__MSG_DATA__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_MSG_DATA__MSG_DATA_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_CONTROL
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_CONTROL__MASK_BIT__SHIFT                                              0x0
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT3_CONTROL__MASK_BIT_MASK                                                0x00000001L
+//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT4_ADDR_LO
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT4_ADDR_LO__MSG_ADDR_LO__SHIFT                                           0x2
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT4_ADDR_LO__MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT4_ADDR_HI
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT4_ADDR_HI__MSG_ADDR_HI__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT4_ADDR_HI__MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT4_MSG_DATA
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT4_MSG_DATA__MSG_DATA__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT4_MSG_DATA__MSG_DATA_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT4_CONTROL
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT4_CONTROL__MASK_BIT__SHIFT                                              0x0
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT4_CONTROL__MASK_BIT_MASK                                                0x00000001L
+//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT5_ADDR_LO
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT5_ADDR_LO__MSG_ADDR_LO__SHIFT                                           0x2
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT5_ADDR_LO__MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT5_ADDR_HI
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT5_ADDR_HI__MSG_ADDR_HI__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT5_ADDR_HI__MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT5_MSG_DATA
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT5_MSG_DATA__MSG_DATA__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT5_MSG_DATA__MSG_DATA_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT5_CONTROL
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT5_CONTROL__MASK_BIT__SHIFT                                              0x0
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT5_CONTROL__MASK_BIT_MASK                                                0x00000001L
+//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT6_ADDR_LO
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT6_ADDR_LO__MSG_ADDR_LO__SHIFT                                           0x2
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT6_ADDR_LO__MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT6_ADDR_HI
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT6_ADDR_HI__MSG_ADDR_HI__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT6_ADDR_HI__MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT6_MSG_DATA
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT6_MSG_DATA__MSG_DATA__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT6_MSG_DATA__MSG_DATA_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT6_CONTROL
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT6_CONTROL__MASK_BIT__SHIFT                                              0x0
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT6_CONTROL__MASK_BIT_MASK                                                0x00000001L
+//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT7_ADDR_LO
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT7_ADDR_LO__MSG_ADDR_LO__SHIFT                                           0x2
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT7_ADDR_LO__MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT7_ADDR_HI
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT7_ADDR_HI__MSG_ADDR_HI__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT7_ADDR_HI__MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT7_MSG_DATA
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT7_MSG_DATA__MSG_DATA__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT7_MSG_DATA__MSG_DATA_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT7_CONTROL
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT7_CONTROL__MASK_BIT__SHIFT                                              0x0
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT7_CONTROL__MASK_BIT_MASK                                                0x00000001L
+//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT8_ADDR_LO
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT8_ADDR_LO__MSG_ADDR_LO__SHIFT                                           0x2
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT8_ADDR_LO__MSG_ADDR_LO_MASK                                             0xFFFFFFFCL
+//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT8_ADDR_HI
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT8_ADDR_HI__MSG_ADDR_HI__SHIFT                                           0x0
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT8_ADDR_HI__MSG_ADDR_HI_MASK                                             0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT8_MSG_DATA
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT8_MSG_DATA__MSG_DATA__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT8_MSG_DATA__MSG_DATA_MASK                                               0xFFFFFFFFL
+//RCC_DEV0_EPF0_VF7_GFXMSIX_VECT8_CONTROL
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT8_CONTROL__MASK_BIT__SHIFT                                              0x0
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_VECT8_CONTROL__MASK_BIT_MASK                                                0x00000001L
+//RCC_DEV0_EPF0_VF7_GFXMSIX_PBA
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_PBA__MSIX_PENDING_BITS_0__SHIFT                                             0x0
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_PBA__MSIX_PENDING_BITS_1__SHIFT                                             0x1
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_PBA__MSIX_PENDING_BITS_0_MASK                                               0x00000001L
+#define RCC_DEV0_EPF0_VF7_GFXMSIX_PBA__MSIX_PENDING_BITS_1_MASK                                               0x00000002L
+
+
+// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf1_bifcfgdecp
+//BIF_CFG_DEV0_EPF1_VENDOR_ID
+#define BIF_CFG_DEV0_EPF1_VENDOR_ID__VENDOR_ID__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF1_VENDOR_ID__VENDOR_ID_MASK                                                           0xFFFFL
+//BIF_CFG_DEV0_EPF1_DEVICE_ID
+#define BIF_CFG_DEV0_EPF1_DEVICE_ID__DEVICE_ID__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF1_DEVICE_ID__DEVICE_ID_MASK                                                           0xFFFFL
+//BIF_CFG_DEV0_EPF1_COMMAND
+#define BIF_CFG_DEV0_EPF1_COMMAND__IO_ACCESS_EN__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_EPF1_COMMAND__MEM_ACCESS_EN__SHIFT                                                       0x1
+#define BIF_CFG_DEV0_EPF1_COMMAND__BUS_MASTER_EN__SHIFT                                                       0x2
+#define BIF_CFG_DEV0_EPF1_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                    0x3
+#define BIF_CFG_DEV0_EPF1_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                             0x4
+#define BIF_CFG_DEV0_EPF1_COMMAND__PAL_SNOOP_EN__SHIFT                                                        0x5
+#define BIF_CFG_DEV0_EPF1_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                               0x6
+#define BIF_CFG_DEV0_EPF1_COMMAND__AD_STEPPING__SHIFT                                                         0x7
+#define BIF_CFG_DEV0_EPF1_COMMAND__SERR_EN__SHIFT                                                             0x8
+#define BIF_CFG_DEV0_EPF1_COMMAND__FAST_B2B_EN__SHIFT                                                         0x9
+#define BIF_CFG_DEV0_EPF1_COMMAND__INT_DIS__SHIFT                                                             0xa
+#define BIF_CFG_DEV0_EPF1_COMMAND__IO_ACCESS_EN_MASK                                                          0x0001L
+#define BIF_CFG_DEV0_EPF1_COMMAND__MEM_ACCESS_EN_MASK                                                         0x0002L
+#define BIF_CFG_DEV0_EPF1_COMMAND__BUS_MASTER_EN_MASK                                                         0x0004L
+#define BIF_CFG_DEV0_EPF1_COMMAND__SPECIAL_CYCLE_EN_MASK                                                      0x0008L
+#define BIF_CFG_DEV0_EPF1_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                               0x0010L
+#define BIF_CFG_DEV0_EPF1_COMMAND__PAL_SNOOP_EN_MASK                                                          0x0020L
+#define BIF_CFG_DEV0_EPF1_COMMAND__PARITY_ERROR_RESPONSE_MASK                                                 0x0040L
+#define BIF_CFG_DEV0_EPF1_COMMAND__AD_STEPPING_MASK                                                           0x0080L
+#define BIF_CFG_DEV0_EPF1_COMMAND__SERR_EN_MASK                                                               0x0100L
+#define BIF_CFG_DEV0_EPF1_COMMAND__FAST_B2B_EN_MASK                                                           0x0200L
+#define BIF_CFG_DEV0_EPF1_COMMAND__INT_DIS_MASK                                                               0x0400L
+//BIF_CFG_DEV0_EPF1_STATUS
+#define BIF_CFG_DEV0_EPF1_STATUS__IMMEDIATE_READINESS__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF1_STATUS__INT_STATUS__SHIFT                                                           0x3
+#define BIF_CFG_DEV0_EPF1_STATUS__CAP_LIST__SHIFT                                                             0x4
+#define BIF_CFG_DEV0_EPF1_STATUS__PCI_66_CAP__SHIFT                                                           0x5
+#define BIF_CFG_DEV0_EPF1_STATUS__FAST_BACK_CAPABLE__SHIFT                                                    0x7
+#define BIF_CFG_DEV0_EPF1_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                             0x8
+#define BIF_CFG_DEV0_EPF1_STATUS__DEVSEL_TIMING__SHIFT                                                        0x9
+#define BIF_CFG_DEV0_EPF1_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                  0xb
+#define BIF_CFG_DEV0_EPF1_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                                0xc
+#define BIF_CFG_DEV0_EPF1_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                                0xd
+#define BIF_CFG_DEV0_EPF1_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                                0xe
+#define BIF_CFG_DEV0_EPF1_STATUS__PARITY_ERROR_DETECTED__SHIFT                                                0xf
+#define BIF_CFG_DEV0_EPF1_STATUS__IMMEDIATE_READINESS_MASK                                                    0x0001L
+#define BIF_CFG_DEV0_EPF1_STATUS__INT_STATUS_MASK                                                             0x0008L
+#define BIF_CFG_DEV0_EPF1_STATUS__CAP_LIST_MASK                                                               0x0010L
+#define BIF_CFG_DEV0_EPF1_STATUS__PCI_66_CAP_MASK                                                             0x0020L
+#define BIF_CFG_DEV0_EPF1_STATUS__FAST_BACK_CAPABLE_MASK                                                      0x0080L
+#define BIF_CFG_DEV0_EPF1_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                               0x0100L
+#define BIF_CFG_DEV0_EPF1_STATUS__DEVSEL_TIMING_MASK                                                          0x0600L
+#define BIF_CFG_DEV0_EPF1_STATUS__SIGNAL_TARGET_ABORT_MASK                                                    0x0800L
+#define BIF_CFG_DEV0_EPF1_STATUS__RECEIVED_TARGET_ABORT_MASK                                                  0x1000L
+#define BIF_CFG_DEV0_EPF1_STATUS__RECEIVED_MASTER_ABORT_MASK                                                  0x2000L
+#define BIF_CFG_DEV0_EPF1_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                  0x4000L
+#define BIF_CFG_DEV0_EPF1_STATUS__PARITY_ERROR_DETECTED_MASK                                                  0x8000L
+//BIF_CFG_DEV0_EPF1_REVISION_ID
+#define BIF_CFG_DEV0_EPF1_REVISION_ID__MINOR_REV_ID__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF1_REVISION_ID__MAJOR_REV_ID__SHIFT                                                    0x4
+#define BIF_CFG_DEV0_EPF1_REVISION_ID__MINOR_REV_ID_MASK                                                      0x0FL
+#define BIF_CFG_DEV0_EPF1_REVISION_ID__MAJOR_REV_ID_MASK                                                      0xF0L
+//BIF_CFG_DEV0_EPF1_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF1_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF1_PROG_INTERFACE__PROG_INTERFACE_MASK                                                 0xFFL
+//BIF_CFG_DEV0_EPF1_SUB_CLASS
+#define BIF_CFG_DEV0_EPF1_SUB_CLASS__SUB_CLASS__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF1_SUB_CLASS__SUB_CLASS_MASK                                                           0xFFL
+//BIF_CFG_DEV0_EPF1_BASE_CLASS
+#define BIF_CFG_DEV0_EPF1_BASE_CLASS__BASE_CLASS__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF1_BASE_CLASS__BASE_CLASS_MASK                                                         0xFFL
+//BIF_CFG_DEV0_EPF1_CACHE_LINE
+#define BIF_CFG_DEV0_EPF1_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF1_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                    0xFFL
+//BIF_CFG_DEV0_EPF1_LATENCY
+#define BIF_CFG_DEV0_EPF1_LATENCY__LATENCY_TIMER__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF1_LATENCY__LATENCY_TIMER_MASK                                                         0xFFL
+//BIF_CFG_DEV0_EPF1_HEADER
+#define BIF_CFG_DEV0_EPF1_HEADER__HEADER_TYPE__SHIFT                                                          0x0
+#define BIF_CFG_DEV0_EPF1_HEADER__DEVICE_TYPE__SHIFT                                                          0x7
+#define BIF_CFG_DEV0_EPF1_HEADER__HEADER_TYPE_MASK                                                            0x7FL
+#define BIF_CFG_DEV0_EPF1_HEADER__DEVICE_TYPE_MASK                                                            0x80L
+//BIF_CFG_DEV0_EPF1_BIST
+#define BIF_CFG_DEV0_EPF1_BIST__BIST_COMP__SHIFT                                                              0x0
+#define BIF_CFG_DEV0_EPF1_BIST__BIST_STRT__SHIFT                                                              0x6
+#define BIF_CFG_DEV0_EPF1_BIST__BIST_CAP__SHIFT                                                               0x7
+#define BIF_CFG_DEV0_EPF1_BIST__BIST_COMP_MASK                                                                0x0FL
+#define BIF_CFG_DEV0_EPF1_BIST__BIST_STRT_MASK                                                                0x40L
+#define BIF_CFG_DEV0_EPF1_BIST__BIST_CAP_MASK                                                                 0x80L
+//BIF_CFG_DEV0_EPF1_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF1_BASE_ADDR_1__BASE_ADDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF1_BASE_ADDR_1__BASE_ADDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF1_BASE_ADDR_2__BASE_ADDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF1_BASE_ADDR_2__BASE_ADDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF1_BASE_ADDR_3__BASE_ADDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF1_BASE_ADDR_3__BASE_ADDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF1_BASE_ADDR_4__BASE_ADDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF1_BASE_ADDR_4__BASE_ADDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF1_BASE_ADDR_5__BASE_ADDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF1_BASE_ADDR_5__BASE_ADDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF1_BASE_ADDR_6__BASE_ADDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF1_BASE_ADDR_6__BASE_ADDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF1_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF1_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                                     0x10
+#define BIF_CFG_DEV0_EPF1_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                       0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__ROM_ENABLE__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT                                         0x1
+#define BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT                                        0x4
+#define BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                     0xb
+#define BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__ROM_ENABLE_MASK                                                      0x00000001L
+#define BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK                                           0x0000000EL
+#define BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK                                          0x000000F0L
+#define BIF_CFG_DEV0_EPF1_ROM_BASE_ADDR__BASE_ADDR_MASK                                                       0xFFFFF800L
+//BIF_CFG_DEV0_EPF1_CAP_PTR
+#define BIF_CFG_DEV0_EPF1_CAP_PTR__CAP_PTR__SHIFT                                                             0x0
+#define BIF_CFG_DEV0_EPF1_CAP_PTR__CAP_PTR_MASK                                                               0xFFL
+//BIF_CFG_DEV0_EPF1_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF1_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF1_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                                 0xFFL
+//BIF_CFG_DEV0_EPF1_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF1_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF1_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                   0xFFL
+//BIF_CFG_DEV0_EPF1_MIN_GRANT
+#define BIF_CFG_DEV0_EPF1_MIN_GRANT__MIN_GNT__SHIFT                                                           0x0
+#define BIF_CFG_DEV0_EPF1_MIN_GRANT__MIN_GNT_MASK                                                             0xFFL
+//BIF_CFG_DEV0_EPF1_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF1_MAX_LATENCY__MAX_LAT__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF1_MAX_LATENCY__MAX_LAT_MASK                                                           0xFFL
+//BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__CAP_ID__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__NEXT_PTR__SHIFT                                                    0x8
+#define BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__LENGTH__SHIFT                                                      0x10
+#define BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__CAP_ID_MASK                                                        0x000000FFL
+#define BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__NEXT_PTR_MASK                                                      0x0000FF00L
+#define BIF_CFG_DEV0_EPF1_VENDOR_CAP_LIST__LENGTH_MASK                                                        0x00FF0000L
+//BIF_CFG_DEV0_EPF1_ADAPTER_ID_W
+#define BIF_CFG_DEV0_EPF1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF1_ADAPTER_ID_W__SUBSYSTEM_ID__SHIFT                                                   0x10
+#define BIF_CFG_DEV0_EPF1_ADAPTER_ID_W__SUBSYSTEM_VENDOR_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_ADAPTER_ID_W__SUBSYSTEM_ID_MASK                                                     0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PMI_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PMI_CAP_LIST__CAP_ID__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF1_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                       0x8
+#define BIF_CFG_DEV0_EPF1_PMI_CAP_LIST__CAP_ID_MASK                                                           0x00FFL
+#define BIF_CFG_DEV0_EPF1_PMI_CAP_LIST__NEXT_PTR_MASK                                                         0xFF00L
+//BIF_CFG_DEV0_EPF1_PMI_CAP
+#define BIF_CFG_DEV0_EPF1_PMI_CAP__VERSION__SHIFT                                                             0x0
+#define BIF_CFG_DEV0_EPF1_PMI_CAP__PME_CLOCK__SHIFT                                                           0x3
+#define BIF_CFG_DEV0_EPF1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                                 0x4
+#define BIF_CFG_DEV0_EPF1_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                   0x5
+#define BIF_CFG_DEV0_EPF1_PMI_CAP__AUX_CURRENT__SHIFT                                                         0x6
+#define BIF_CFG_DEV0_EPF1_PMI_CAP__D1_SUPPORT__SHIFT                                                          0x9
+#define BIF_CFG_DEV0_EPF1_PMI_CAP__D2_SUPPORT__SHIFT                                                          0xa
+#define BIF_CFG_DEV0_EPF1_PMI_CAP__PME_SUPPORT__SHIFT                                                         0xb
+#define BIF_CFG_DEV0_EPF1_PMI_CAP__VERSION_MASK                                                               0x0007L
+#define BIF_CFG_DEV0_EPF1_PMI_CAP__PME_CLOCK_MASK                                                             0x0008L
+#define BIF_CFG_DEV0_EPF1_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                   0x0010L
+#define BIF_CFG_DEV0_EPF1_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                     0x0020L
+#define BIF_CFG_DEV0_EPF1_PMI_CAP__AUX_CURRENT_MASK                                                           0x01C0L
+#define BIF_CFG_DEV0_EPF1_PMI_CAP__D1_SUPPORT_MASK                                                            0x0200L
+#define BIF_CFG_DEV0_EPF1_PMI_CAP__D2_SUPPORT_MASK                                                            0x0400L
+#define BIF_CFG_DEV0_EPF1_PMI_CAP__PME_SUPPORT_MASK                                                           0xF800L
+//BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                               0x3
+#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PME_EN__SHIFT                                                      0x8
+#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                                 0x9
+#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                  0xd
+#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                  0xf
+#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                               0x16
+#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                  0x17
+#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                    0x18
+#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__POWER_STATE_MASK                                                   0x00000003L
+#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                                 0x00000008L
+#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PME_EN_MASK                                                        0x00000100L
+#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                   0x00001E00L
+#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                    0x00006000L
+#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PME_STATUS_MASK                                                    0x00008000L
+#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                                 0x00400000L
+#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                    0x00800000L
+#define BIF_CFG_DEV0_EPF1_PMI_STATUS_CNTL__PMI_DATA_MASK                                                      0xFF000000L
+//SBRN
+#define SBRN__SBRN__SHIFT                                                                                     0x0
+#define SBRN__SBRN_MASK                                                                                       0xFFL
+//FLADJ
+#define FLADJ__FLADJ__SHIFT                                                                                   0x0
+#define FLADJ__NFC__SHIFT                                                                                     0x6
+#define FLADJ__FLADJ_MASK                                                                                     0x3FL
+#define FLADJ__NFC_MASK                                                                                       0x40L
+//BIF_CFG_DEV0_EPF1_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PCIE_CAP_LIST__CAP_ID__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                      0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_CAP_LIST__CAP_ID_MASK                                                          0x00FFL
+#define BIF_CFG_DEV0_EPF1_PCIE_CAP_LIST__NEXT_PTR_MASK                                                        0xFF00L
+//BIF_CFG_DEV0_EPF1_PCIE_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_CAP__VERSION__SHIFT                                                            0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_CAP__DEVICE_TYPE__SHIFT                                                        0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                    0x9
+#define BIF_CFG_DEV0_EPF1_PCIE_CAP__FLIT_MODE_SUPPORT__SHIFT                                                  0xf
+#define BIF_CFG_DEV0_EPF1_PCIE_CAP__VERSION_MASK                                                              0x000FL
+#define BIF_CFG_DEV0_EPF1_PCIE_CAP__DEVICE_TYPE_MASK                                                          0x00F0L
+#define BIF_CFG_DEV0_EPF1_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                     0x0100L
+#define BIF_CFG_DEV0_EPF1_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                      0x3E00L
+#define BIF_CFG_DEV0_EPF1_PCIE_CAP__FLIT_MODE_SUPPORT_MASK                                                    0x8000L
+//BIF_CFG_DEV0_EPF1_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                     0x3
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                     0x5
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                           0x6
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                            0x9
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                         0xf
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT                                         0x10
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__RX_MPS_FIXED__SHIFT                                                     0x11
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                        0x12
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                        0x1a
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                      0x1c
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__MIXED_MPS_SUPPORTED__SHIFT                                              0x1d
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__TEE_IO_SUPPORT__SHIFT                                                   0x1e
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                                0x00000007L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__PHANTOM_FUNC_MASK                                                       0x00000018L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__EXTENDED_TAG_MASK                                                       0x00000020L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                             0x000001C0L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                              0x00000E00L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                           0x00008000L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK                                           0x00010000L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__RX_MPS_FIXED_MASK                                                       0x00020000L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                          0x03FC0000L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                          0x0C000000L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__FLR_CAPABLE_MASK                                                        0x10000000L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__MIXED_MPS_SUPPORTED_MASK                                                0x20000000L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP__TEE_IO_SUPPORT_MASK                                                     0x40000000L
+//BIF_CFG_DEV0_EPF1_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                                0x1
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                    0x2
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                   0x3
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                  0x4
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                                0x5
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                                 0x8
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                                 0x9
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                                 0xa
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                     0xb
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                           0xc
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__INITIATE_FLR__SHIFT                                                    0xf
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__CORR_ERR_EN_MASK                                                       0x0001L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                  0x0002L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                      0x0004L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__USR_REPORT_EN_MASK                                                     0x0008L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                    0x0010L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                  0x00E0L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                   0x0100L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                   0x0200L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                   0x0400L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                       0x0800L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                             0x7000L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL__INITIATE_FLR_MASK                                                      0x8000L
+//BIF_CFG_DEV0_EPF1_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__CORR_ERR__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                                 0x1
+#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__FATAL_ERR__SHIFT                                                     0x2
+#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__USR_DETECTED__SHIFT                                                  0x3
+#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__AUX_PWR__SHIFT                                                       0x4
+#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                             0x5
+#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                                 0x6
+#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__CORR_ERR_MASK                                                        0x0001L
+#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                   0x0002L
+#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__FATAL_ERR_MASK                                                       0x0004L
+#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__USR_DETECTED_MASK                                                    0x0008L
+#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__AUX_PWR_MASK                                                         0x0010L
+#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                               0x0020L
+#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                   0x0040L
+//BIF_CFG_DEV0_EPF1_LINK_CAP
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_SPEED__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_WIDTH__SHIFT                                                         0x4
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__PM_SUPPORT__SHIFT                                                         0xa
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                   0xc
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                    0xf
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                             0x12
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                        0x13
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                        0x14
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                           0x15
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                        0x16
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__PORT_NUMBER__SHIFT                                                        0x18
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_SPEED_MASK                                                           0x0000000FL
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_WIDTH_MASK                                                           0x000003F0L
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__PM_SUPPORT_MASK                                                           0x00000C00L
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                     0x00007000L
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__L1_EXIT_LATENCY_MASK                                                      0x00038000L
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                               0x00040000L
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                          0x00080000L
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                          0x00100000L
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                             0x00200000L
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                          0x00400000L
+#define BIF_CFG_DEV0_EPF1_LINK_CAP__PORT_NUMBER_MASK                                                          0xFF000000L
+//BIF_CFG_DEV0_EPF1_LINK_CNTL
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__PM_CONTROL__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT                                      0x2
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                                 0x3
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_DIS__SHIFT                                                          0x4
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__RETRAIN_LINK__SHIFT                                                      0x5
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                  0x6
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                     0x7
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                         0x8
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                       0x9
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                         0xa
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                         0xb
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__SRIS_CLOCKING__SHIFT                                                     0xc
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__FLIT_MODE_DISABLE__SHIFT                                                 0xd
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                             0xe
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__PM_CONTROL_MASK                                                          0x0003L
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK                                        0x0004L
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                   0x0008L
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_DIS_MASK                                                            0x0010L
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__RETRAIN_LINK_MASK                                                        0x0020L
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                    0x0040L
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__EXTENDED_SYNC_MASK                                                       0x0080L
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                           0x0100L
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                         0x0200L
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                           0x0400L
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                           0x0800L
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__SRIS_CLOCKING_MASK                                                       0x1000L
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__FLIT_MODE_DISABLE_MASK                                                   0x2000L
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                               0xC000L
+//BIF_CFG_DEV0_EPF1_LINK_STATUS
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                           0x4
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_TRAINING__SHIFT                                                   0xb
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                  0xc
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS__DL_ACTIVE__SHIFT                                                       0xd
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                       0xe
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                       0xf
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                                0x000FL
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                             0x03F0L
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_TRAINING_MASK                                                     0x0800L
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                    0x1000L
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS__DL_ACTIVE_MASK                                                         0x2000L
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                         0x4000L
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                         0x8000L
+//BIF_CFG_DEV0_EPF1_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                       0x4
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                        0x5
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                      0x6
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                      0x7
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                          0x9
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                       0xa
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                   0xb
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                              0xc
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                   0xe
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                                 0x10
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                                 0x11
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                  0x12
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                    0x14
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                    0x15
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                        0x16
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                  0x18
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                   0x1a
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                   0x1f
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                       0x0000000FL
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                         0x00000010L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                          0x00000020L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                        0x00000040L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                        0x00000080L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                        0x00000100L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                            0x00000200L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                         0x00000400L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                     0x00000800L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                                0x00003000L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                     0x0000C000L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                   0x00010000L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                   0x00020000L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                    0x000C0000L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                      0x00100000L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                      0x00200000L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                          0x00C00000L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                    0x03000000L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                     0x04000000L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                     0x80000000L
+//BIF_CFG_DEV0_EPF1_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                                0x4
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                              0x5
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                            0x6
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                       0x7
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                             0x8
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                          0x9
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__LTR_EN__SHIFT                                                         0xa
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                   0xb
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                   0xc
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__OBFF_EN__SHIFT                                                        0xd
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                    0xf
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                                0x000FL
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                  0x0010L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                                0x0020L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                              0x0040L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                         0x0080L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                               0x0100L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                            0x0200L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__LTR_EN_MASK                                                           0x0400L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                     0x0800L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                     0x1000L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__OBFF_EN_MASK                                                          0x6000L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                      0x8000L
+//BIF_CFG_DEV0_EPF1_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS2__RESERVED__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS2__RESERVED_MASK                                                       0xFFFFL
+//BIF_CFG_DEV0_EPF1_LINK_CAP2
+#define BIF_CFG_DEV0_EPF1_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                              0x1
+#define BIF_CFG_DEV0_EPF1_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                               0x8
+#define BIF_CFG_DEV0_EPF1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT                                          0x9
+#define BIF_CFG_DEV0_EPF1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                          0x10
+#define BIF_CFG_DEV0_EPF1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                         0x17
+#define BIF_CFG_DEV0_EPF1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                         0x18
+#define BIF_CFG_DEV0_EPF1_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                     0x1f
+#define BIF_CFG_DEV0_EPF1_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                                0x000000FEL
+#define BIF_CFG_DEV0_EPF1_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                                 0x00000100L
+#define BIF_CFG_DEV0_EPF1_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK                                            0x0000FE00L
+#define BIF_CFG_DEV0_EPF1_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                            0x007F0000L
+#define BIF_CFG_DEV0_EPF1_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                           0x00800000L
+#define BIF_CFG_DEV0_EPF1_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                           0x01000000L
+#define BIF_CFG_DEV0_EPF1_LINK_CAP2__DRS_SUPPORTED_MASK                                                       0x80000000L
+//BIF_CFG_DEV0_EPF1_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                                 0x4
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                      0x5
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                            0x6
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                      0x7
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                             0xa
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                   0xb
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                            0xc
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                  0x000FL
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                   0x0010L
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                        0x0020L
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                              0x0040L
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__XMIT_MARGIN_MASK                                                        0x0380L
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                               0x0400L
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                     0x0800L
+#define BIF_CFG_DEV0_EPF1_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                              0xF000L
+//BIF_CFG_DEV0_EPF1_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                      0x1
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                                0x2
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                                0x3
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                                0x4
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                  0x5
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                              0x6
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                              0x7
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                           0x8
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__FLIT_MODE_STATUS__SHIFT                                               0xa
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                  0xc
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                           0xf
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                             0x0001L
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                        0x0002L
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                  0x0004L
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                  0x0008L
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                  0x0010L
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                    0x0020L
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                                0x0040L
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                                0x0080L
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                             0x0300L
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__FLIT_MODE_STATUS_MASK                                                 0x0400L
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                    0x7000L
+#define BIF_CFG_DEV0_EPF1_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                             0x8000L
+//BIF_CFG_DEV0_EPF1_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_MSI_CAP_LIST__CAP_ID__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF1_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                       0x8
+#define BIF_CFG_DEV0_EPF1_MSI_CAP_LIST__CAP_ID_MASK                                                           0x00FFL
+#define BIF_CFG_DEV0_EPF1_MSI_CAP_LIST__NEXT_PTR_MASK                                                         0xFF00L
+//BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EN__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                  0x1
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                   0x4
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                      0x7
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                      0x8
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT                                           0x9
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT                                            0xa
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EN_MASK                                                           0x0001L
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                    0x000EL
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                     0x0070L
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_64BIT_MASK                                                        0x0080L
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                        0x0100L
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK                                             0x0200L
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK                                              0x0400L
+//BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                             0x2
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                               0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_DATA__MSI_DATA__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_DATA__MSI_DATA_MASK                                                         0xFFFFL
+//BIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK                                                 0xFFFFL
+//BIF_CFG_DEV0_EPF1_MSI_MASK
+#define BIF_CFG_DEV0_EPF1_MSI_MASK__MSI_MASK__SHIFT                                                           0x0
+#define BIF_CFG_DEV0_EPF1_MSI_MASK__MSI_MASK_MASK                                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF1_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                   0xFFFFL
+//BIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF1_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK                                           0xFFFFL
+//BIF_CFG_DEV0_EPF1_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF1_MSI_MASK_64__MSI_MASK_64__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF1_MSI_MASK_64__MSI_MASK_64_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_MSI_PENDING
+#define BIF_CFG_DEV0_EPF1_MSI_PENDING__MSI_PENDING__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF1_MSI_PENDING__MSI_PENDING_MASK                                                       0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF1_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF1_MSI_PENDING_64__MSI_PENDING_64_MASK                                                 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_MSIX_CAP_LIST__CAP_ID__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_EPF1_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                      0x8
+#define BIF_CFG_DEV0_EPF1_MSIX_CAP_LIST__CAP_ID_MASK                                                          0x00FFL
+#define BIF_CFG_DEV0_EPF1_MSIX_CAP_LIST__NEXT_PTR_MASK                                                        0xFF00L
+//BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                                0xe
+#define BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                       0xf
+#define BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                                 0x07FFL
+#define BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                                  0x4000L
+#define BIF_CFG_DEV0_EPF1_MSIX_MSG_CNTL__MSIX_EN_MASK                                                         0x8000L
+//BIF_CFG_DEV0_EPF1_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF1_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF1_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                                0x3
+#define BIF_CFG_DEV0_EPF1_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                                     0x00000007L
+#define BIF_CFG_DEV0_EPF1_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                                  0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF1_MSIX_PBA
+#define BIF_CFG_DEV0_EPF1_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF1_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                                    0x3
+#define BIF_CFG_DEV0_EPF1_MSIX_PBA__MSIX_PBA_BIR_MASK                                                         0x00000007L
+#define BIF_CFG_DEV0_EPF1_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                      0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                  0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                      0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                     0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                    0xFFF00000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                           0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                        0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                             0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                          0xFFF00000L
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                                 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                                 0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_DEVICE3_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PCIE_DEVICE3_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_DEVICE3_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_DEVICE3_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_DEVICE3_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_DEVICE3_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_DEVICE3_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
+//BIF_CFG_DEV0_EPF1_DEVICE_CAP3
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP3__DMWR_REQUEST_ROUTING_SUPPORTED__SHIFT                                  0x0
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_COMPLETER_SUPPORTED__SHIFT                       0x1
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_REQUESTER_SUPPORTED__SHIFT                       0x2
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP3__RECEIVER_L0P_SUPPORTED__SHIFT                                          0x3
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP3__PORT_L0P_EXIT_LATENCY__SHIFT                                           0x4
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP3__RETIMER_L0P_EXIT_LATENCY__SHIFT                                        0x7
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP3__DMWR_REQUEST_ROUTING_SUPPORTED_MASK                                    0x00000001L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_COMPLETER_SUPPORTED_MASK                         0x00000002L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_REQUESTER_SUPPORTED_MASK                         0x00000004L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP3__RECEIVER_L0P_SUPPORTED_MASK                                            0x00000008L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP3__PORT_L0P_EXIT_LATENCY_MASK                                             0x00000070L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CAP3__RETIMER_L0P_EXIT_LATENCY_MASK                                          0x00000380L
+//BIF_CFG_DEV0_EPF1_DEVICE_CNTL3
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL3__DMWR_REQUEST_ENABLE__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL3__DMWR_EGRESS_BLOCKING__SHIFT                                           0x1
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL3__DEVICE_CNTL3_14BIT_TAG_REQUESTER_ENABLE__SHIFT                        0x2
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL3__L0P_ENABLE__SHIFT                                                     0x3
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL3__TARGET_LINK_WIDTH__SHIFT                                              0x4
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL3__DMWR_REQUEST_ENABLE_MASK                                              0x00000001L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL3__DMWR_EGRESS_BLOCKING_MASK                                             0x00000002L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL3__DEVICE_CNTL3_14BIT_TAG_REQUESTER_ENABLE_MASK                          0x00000004L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL3__L0P_ENABLE_MASK                                                       0x00000008L
+#define BIF_CFG_DEV0_EPF1_DEVICE_CNTL3__TARGET_LINK_WIDTH_MASK                                                0x00000070L
+//BIF_CFG_DEV0_EPF1_DEVICE_STATUS3
+#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS3__INITIAL_LINK_WIDTH__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS3__SEGMENT_CAPTURED__SHIFT                                             0x3
+#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS3__REMOTE_L0P_SUPPORTED__SHIFT                                         0x4
+#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS3__INITIAL_LINK_WIDTH_MASK                                             0x00000007L
+#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS3__SEGMENT_CAPTURED_MASK                                               0x00000008L
+#define BIF_CFG_DEV0_EPF1_DEVICE_STATUS3__REMOTE_L0P_SUPPORTED_MASK                                           0x00000010L
+//BIF_CFG_DEV0_EPF1_PCIE_NULL1_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PCIE_NULL1_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_NULL1_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_NULL1_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_NULL1_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_NULL1_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_NULL1_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF1_PCIE_NULL2_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PCIE_NULL2_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_NULL2_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_NULL2_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_NULL2_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_NULL2_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_NULL2_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                       0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                      0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                         0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                        0xFFF00000L
+//BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                       0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                    0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                       0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                        0xd
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                   0xe
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                                 0xf
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                      0x11
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                       0x12
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                      0x13
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                                0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                                 0x15
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                                0x16
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                                0x17
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                       0x18
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                        0x19
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                   0x1a
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__DMWR_REQUEST_EGRESS_BLOCKED_STATUS__SHIFT                   0x1b
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__IDE_CHECK_FAILED_STATUS__SHIFT                              0x1c
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__MISROUTED_IDE_TLP_STATUS__SHIFT                             0x1d
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__PCRC_CHECK_FAILED_STATUS__SHIFT                             0x1e
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                         0x00000010L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                      0x00000020L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                         0x00001000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                          0x00002000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                     0x00004000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                   0x00008000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                       0x00010000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                        0x00020000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                         0x00040000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                        0x00080000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                  0x00100000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                   0x00200000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                  0x00400000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                  0x00800000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                         0x01000000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                          0x02000000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                     0x04000000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__DMWR_REQUEST_EGRESS_BLOCKED_STATUS_MASK                     0x08000000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__IDE_CHECK_FAILED_STATUS_MASK                                0x10000000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__MISROUTED_IDE_TLP_STATUS_MASK                               0x20000000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_STATUS__PCRC_CHECK_FAILED_STATUS_MASK                               0x40000000L
+//BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                           0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                        0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                           0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                            0xd
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                       0xe
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                     0xf
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                         0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                          0x11
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                           0x12
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                          0x13
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                    0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                     0x15
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                    0x16
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                    0x17
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                           0x18
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                            0x19
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                       0x1a
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__DMWR_REQUEST_EGRESS_BLOCKED_MASK__SHIFT                       0x1b
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__IDE_CHECK_FAILED_MASK__SHIFT                                  0x1c
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__MISROUTED_IDE_TLP_MASK__SHIFT                                 0x1d
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__PCRC_CHECK_FAILED_MASK__SHIFT                                 0x1e
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                             0x00000010L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                          0x00000020L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                             0x00001000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                              0x00002000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                         0x00004000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                       0x00008000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                           0x00010000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                            0x00020000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                             0x00040000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                            0x00080000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                      0x00100000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                       0x00200000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                      0x00400000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                      0x00800000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                             0x01000000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                              0x02000000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                         0x04000000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__DMWR_REQUEST_EGRESS_BLOCKED_MASK_MASK                         0x08000000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__IDE_CHECK_FAILED_MASK_MASK                                    0x10000000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__MISROUTED_IDE_TLP_MASK_MASK                                   0x20000000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_MASK__PCRC_CHECK_FAILED_MASK_MASK                                   0x40000000L
+//BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                   0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                                0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                   0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                    0xd
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                               0xe
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                             0xf
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                                 0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                  0x11
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                   0x12
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                  0x13
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                            0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                             0x15
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                            0x16
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                            0x17
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                   0x18
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                    0x19
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT               0x1a
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__DMWR_REQUEST_EGRESS_BLOCKED_SEVERITY__SHIFT               0x1b
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__IDE_CHECK_FAILED_SEVERITY__SHIFT                          0x1c
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__MISROUTED_IDE_TLP_SEVERITY__SHIFT                         0x1d
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__PCRC_CHECK_FAILED_SEVERITY__SHIFT                         0x1e
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                     0x00000010L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                  0x00000020L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                     0x00001000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                      0x00002000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                                 0x00004000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                               0x00008000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                   0x00010000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                    0x00020000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                     0x00040000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                    0x00080000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                              0x00100000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                               0x00200000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                              0x00400000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                              0x00800000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                     0x01000000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                      0x02000000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK                 0x04000000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__DMWR_REQUEST_EGRESS_BLOCKED_SEVERITY_MASK                 0x08000000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__IDE_CHECK_FAILED_SEVERITY_MASK                            0x10000000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__MISROUTED_IDE_TLP_SEVERITY_MASK                           0x20000000L
+#define BIF_CFG_DEV0_EPF1_PCIE_UNCORR_ERR_SEVERITY__PCRC_CHECK_FAILED_SEVERITY_MASK                           0x40000000L
+//BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                         0x6
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                        0x7
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                             0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                            0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                           0xd
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                    0xe
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                                    0xf
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                           0x00000001L
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                           0x00000040L
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                          0x00000080L
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                               0x00000100L
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                              0x00001000L
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                             0x00002000L
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                      0x00004000L
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                      0x00008000L
+//BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                             0x6
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                            0x7
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                                 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                                0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                               0xd
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                        0xe
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                        0xf
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                               0x00000001L
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                               0x00000040L
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                              0x00000080L
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                   0x00000100L
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                  0x00001000L
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                                 0x00002000L
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                          0x00004000L
+#define BIF_CFG_DEV0_EPF1_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                          0x00008000L
+//BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT                                          0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT                                           0x6
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                        0x7
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                         0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                    0x9
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                     0xa
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                                0xb
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT                        0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__HEADER_LOG_SIZE__SHIFT                                       0xd
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_WAS_FLIT_MODE__SHIFT                              0x12
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_SIZE__SHIFT                                       0x13
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                           0x0000001FL
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK                                            0x00000020L
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK                                             0x00000040L
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                          0x00000080L
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                           0x00000100L
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                      0x00000200L
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                       0x00000400L
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                                  0x00000800L
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK                          0x00001000L
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__HEADER_LOG_SIZE_MASK                                         0x0003E000L
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_WAS_FLIT_MODE_MASK                                0x00040000L
+#define BIF_CFG_DEV0_EPF1_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_SIZE_MASK                                         0x00F80000L
+//BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG0__TLP_HDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG1__TLP_HDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG2__TLP_HDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG3__TLP_HDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG4
+#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG4__TLP_HDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG4__TLP_HDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG5
+#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG5__TLP_HDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG5__TLP_HDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG6
+#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG6__TLP_HDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG6__TLP_HDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG7
+#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG7__TLP_HDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG7__TLP_HDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                               0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG8
+#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG8__TLP_HDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG8__TLP_HDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG9
+#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG9__TLP_HDR__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG9__TLP_HDR_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG10
+#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG10__TLP_HDR__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG10__TLP_HDR_MASK                                                        0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG11
+#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG11__TLP_HDR__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG11__TLP_HDR_MASK                                                        0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG12
+#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG12__TLP_HDR__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG12__TLP_HDR_MASK                                                        0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG13
+#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG13__TLP_HDR__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_HDR_LOG13__TLP_HDR_MASK                                                        0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
+//BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                           0x1
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                           0x2
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                        0x3
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                            0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                             0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                          0x6
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__ENHANCED_CAPABILITY__SHIFT                                            0x7
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                                0x0001L
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                             0x0002L
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                             0x0004L
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                          0x0008L
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                              0x0010L
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                               0x0020L
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                            0x0040L
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__ENHANCED_CAPABILITY_MASK                                              0x0080L
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                       0xFF00L
+//BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                       0x1
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                       0x2
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                    0x3
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                        0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                         0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                      0x6
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN__SHIFT                                        0x7
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL__SHIFT                                 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL__SHIFT                                 0xa
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL__SHIFT                               0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                            0x0001L
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                         0x0002L
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                         0x0004L
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                      0x0008L
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                          0x0010L
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                           0x0020L
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                        0x0040L
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN_MASK                                          0x0080L
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL_MASK                                   0x0300L
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL_MASK                                   0x0C00L
+#define BIF_CFG_DEV0_EPF1_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL_MASK                                 0x1000L
+//BIF_CFG_DEV0_EPF1_PCIE_RTR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
+//BIF_CFG_DEV0_EPF1_RTR_DATA1
+#define BIF_CFG_DEV0_EPF1_RTR_DATA1__RESET_TIME__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_EPF1_RTR_DATA1__DLUP_TIME__SHIFT                                                         0xc
+#define BIF_CFG_DEV0_EPF1_RTR_DATA1__RTR_VALID__SHIFT                                                         0x1f
+#define BIF_CFG_DEV0_EPF1_RTR_DATA1__RESET_TIME_MASK                                                          0x00000FFFL
+#define BIF_CFG_DEV0_EPF1_RTR_DATA1__DLUP_TIME_MASK                                                           0x00FFF000L
+#define BIF_CFG_DEV0_EPF1_RTR_DATA1__RTR_VALID_MASK                                                           0x80000000L
+//BIF_CFG_DEV0_EPF1_RTR_DATA2
+#define BIF_CFG_DEV0_EPF1_RTR_DATA2__FLR_TIME__SHIFT                                                          0x0
+#define BIF_CFG_DEV0_EPF1_RTR_DATA2__D3HOTD0_TIME__SHIFT                                                      0xc
+#define BIF_CFG_DEV0_EPF1_RTR_DATA2__FLR_TIME_MASK                                                            0x00000FFFL
+#define BIF_CFG_DEV0_EPF1_RTR_DATA2__D3HOTD0_TIME_MASK                                                        0x00FFF000L
+//BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER__SHIFT                                        0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR__SHIFT                                       0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_ID_MASK                                           0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__CAP_VER_MASK                                          0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_ENH_CAP_LIST__NEXT_PTR_MASK                                         0xFFF00000L
+//BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_SELECT
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_SELECT__EXTENDED_PWR_BUDGET_ENABLE__SHIFT                      0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_SELECT__DATA_SELECT_MASK                                       0x000000FFL
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA_SELECT__EXTENDED_PWR_BUDGET_ENABLE_MASK                        0x00010000L
+//BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__BASE_POWER__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__DATA_SCALE__SHIFT                                             0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE__SHIFT                                           0xa
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__PM_STATE__SHIFT                                               0xd
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__TYPE__SHIFT                                                   0xf
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__POWER_RAIL__SHIFT                                             0x12
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__BASE_POWER_MASK                                               0x000000FFL
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__DATA_SCALE_MASK                                               0x00000300L
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__PM_SUB_STATE_MASK                                             0x00001C00L
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__PM_STATE_MASK                                                 0x00006000L
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__TYPE_MASK                                                     0x00038000L
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_DATA__POWER_RAIL_MASK                                               0x001C0000L
+//BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_CAP__EXTENDED_PWR_BUDGET_SUPPORT__SHIFT                             0x1
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_CAP__SYSTEM_ALLOCATED_MASK                                          0x01L
+#define BIF_CFG_DEV0_EPF1_PCIE_PWR_BUDGET_CAP__EXTENDED_PWR_BUDGET_SUPPORT_MASK                               0x02L
+//BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
+//BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__SUBSTATE_MAX__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_UNIT__SHIFT                                                 0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__PWR_ALLOC_SCALE__SHIFT                                                0xc
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_VAL_0__SHIFT                                                0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_VAL_1__SHIFT                                                0x18
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__SUBSTATE_MAX_MASK                                                     0x0000001FL
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_UNIT_MASK                                                   0x00000300L
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__PWR_ALLOC_SCALE_MASK                                                  0x00003000L
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_VAL_0_MASK                                                  0x00FF0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CAP__TRANS_LAT_VAL_1_MASK                                                  0xFF000000L
+//BIF_CFG_DEV0_EPF1_PCIE_DPA_LATENCY_INDICATOR
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT                         0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK                           0x000000FFL
+//BIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS__SUBSTATE_STATUS__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED__SHIFT                                       0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS__SUBSTATE_STATUS_MASK                                               0x001FL
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_STATUS__SUBSTATE_CNTL_ENABLED_MASK                                         0x0100L
+//BIF_CFG_DEV0_EPF1_PCIE_DPA_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CNTL__SUBSTATE_CNTL__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_CNTL__SUBSTATE_CNTL_MASK                                                   0x001FL
+//BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
+//BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
+//BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
+//BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
+//BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
+//BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
+//BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
+//BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                              0xFFL
+//BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
+//BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                        0x1
+#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                              0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                         0x0001L
+#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                          0x0002L
+#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                                0xFF00L
+//BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                        0x1
+#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                            0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                         0x0001L
+#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                          0x0002L
+#define BIF_CFG_DEV0_EPF1_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                              0x0070L
+//BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
+//BIF_CFG_DEV0_EPF1_PCIE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_INDEX__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_SIZE__SHIFT                                                     0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_INDEX_MASK                                                      0x00000007L
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR1_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_INDEX__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_SIZE__SHIFT                                                     0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_INDEX_MASK                                                      0x00000007L
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR2_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_INDEX__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_SIZE__SHIFT                                                     0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_INDEX_MASK                                                      0x00000007L
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR3_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_INDEX__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_SIZE__SHIFT                                                     0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_INDEX_MASK                                                      0x00000007L
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR4_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_INDEX__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_SIZE__SHIFT                                                     0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_INDEX_MASK                                                      0x00000007L
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR5_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED__SHIFT                                            0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CAP__BAR_SIZE_SUPPORTED_MASK                                              0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_INDEX__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM__SHIFT                                                0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_SIZE__SHIFT                                                     0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_INDEX_MASK                                                      0x00000007L
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_TOTAL_NUM_MASK                                                  0x000000E0L
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_SIZE_MASK                                                       0x00003F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_BAR6_CNTL__BAR_SIZE_SUPPORTED_UPPER_MASK                                       0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_PASID_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED__SHIFT                               0x1
+#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED__SHIFT                                    0x2
+#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__TRANSLATED_REQ_WITH_PASID_SUPPORTED__SHIFT                          0x3
+#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__MAX_PASID_WIDTH__SHIFT                                              0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__PASID_EXE_PERMISSION_SUPPORTED_MASK                                 0x0002L
+#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__PASID_PRIV_MODE_SUPPORTED_MASK                                      0x0004L
+#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__TRANSLATED_REQ_WITH_PASID_SUPPORTED_MASK                            0x0008L
+#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CAP__MAX_PASID_WIDTH_MASK                                                0x1F00L
+//BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_ENABLE__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE__SHIFT                                 0x1
+#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE__SHIFT                            0x2
+#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__TRANSLATED_REQ_WITH_PASID_ENABLE__SHIFT                            0x3
+#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_ENABLE_MASK                                                  0x0001L
+#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_EXE_PERMISSION_ENABLE_MASK                                   0x0002L
+#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__PASID_PRIV_MODE_SUPPORTED_ENABLE_MASK                              0x0004L
+#define BIF_CFG_DEV0_EPF1_PCIE_PASID_CNTL__TRANSLATED_REQ_WITH_PASID_ENABLE_MASK                              0x0008L
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER__SHIFT                                             0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR__SHIFT                                            0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST__CAP_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST__CAP_VER_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_ENH_CAP_LIST__NEXT_PTR_MASK                                              0xFFF00000L
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED__SHIFT                            0x1
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                     0x2
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_VF_14_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                      0x3
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM__SHIFT                              0x15
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_CAP_MASK                                         0x00000001L
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_ARI_CAP_HIERARCHY_PRESERVED_MASK                              0x00000002L
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_VF_TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                       0x00000004L
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_VF_14_BIT_TAG_REQUESTER_SUPPORTED_MASK                        0x00000008L
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CAP__SRIOV_VF_MIGRATION_INTR_MSG_NUM_MASK                                0xFFE00000L
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE__SHIFT                                0x1
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE__SHIFT                           0x2
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE__SHIFT                                             0x3
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY__SHIFT                                  0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                    0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_14_BIT_TAG_REQUESTER_ENABLE__SHIFT                     0x6
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_ENABLE_MASK                                            0x0001L
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_ENABLE_MASK                                  0x0002L
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_MIGRATION_INTR_ENABLE_MASK                             0x0004L
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_MSE_MASK                                               0x0008L
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_ARI_CAP_HIERARCHY_MASK                                    0x0010L
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_TEN_BIT_TAG_REQUESTER_ENABLE_MASK                      0x0020L
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_CONTROL__SRIOV_VF_14_BIT_TAG_REQUESTER_ENABLE_MASK                       0x0040L
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_STATUS
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS__SHIFT                                 0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_STATUS__SRIOV_VF_MIGRATION_STATUS_MASK                                   0x0001L
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_INITIAL_VFS
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_INITIAL_VFS__SRIOV_INITIAL_VFS_MASK                                      0xFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_TOTAL_VFS
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_TOTAL_VFS__SRIOV_TOTAL_VFS_MASK                                          0xFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_NUM_VFS
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_NUM_VFS__SRIOV_NUM_VFS_MASK                                              0xFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_FUNC_DEP_LINK
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK__SHIFT                                0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_FUNC_DEP_LINK__SRIOV_FUNC_DEP_LINK_MASK                                  0xFFL
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_FIRST_VF_OFFSET
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET__SHIFT                            0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_FIRST_VF_OFFSET__SRIOV_FIRST_VF_OFFSET_MASK                              0xFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_STRIDE
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_STRIDE__SRIOV_VF_STRIDE_MASK                                          0xFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_DEVICE_ID
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID__SHIFT                                  0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_DEVICE_ID__SRIOV_VF_DEVICE_ID_MASK                                    0xFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE__SHIFT                    0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_SUPPORTED_PAGE_SIZE__SRIOV_SUPPORTED_PAGE_SIZE_MASK                      0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_SYSTEM_PAGE_SIZE
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE__SHIFT                          0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_SYSTEM_PAGE_SIZE__SRIOV_SYSTEM_PAGE_SIZE_MASK                            0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_0__VF_BASE_ADDR_MASK                                        0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_1__VF_BASE_ADDR_MASK                                        0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_2__VF_BASE_ADDR_MASK                                        0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_3__VF_BASE_ADDR_MASK                                        0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_4__VF_BASE_ADDR_MASK                                        0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_BASE_ADDR_5__VF_BASE_ADDR_MASK                                        0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR__SHIFT     0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SHIFT  0x3
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_BIR_MASK       0x00000007L
+#define BIF_CFG_DEV0_EPF1_PCIE_SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET__SRIOV_VF_MIGRATION_STATE_ARRAY_OFFSET_MASK  0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID__SHIFT                                      0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                    0x14
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_ID_MASK                                        0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__CAP_VER_MASK                                       0x000F0000L
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR_ENH_CAP_LIST__NEXT_PTR_MASK                                      0xFFF00000L
+//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT                               0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CAP__VF_BAR_SIZE_SUPPORTED_MASK                                 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM__SHIFT                                   0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE__SHIFT                                        0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT                        0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_INDEX_MASK                                         0x00000007L
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_TOTAL_NUM_MASK                                     0x000000E0L
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_MASK                                          0x00003F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR1_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK                          0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT                               0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CAP__VF_BAR_SIZE_SUPPORTED_MASK                                 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM__SHIFT                                   0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE__SHIFT                                        0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT                        0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_INDEX_MASK                                         0x00000007L
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_TOTAL_NUM_MASK                                     0x000000E0L
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_MASK                                          0x00003F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR2_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK                          0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT                               0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CAP__VF_BAR_SIZE_SUPPORTED_MASK                                 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM__SHIFT                                   0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE__SHIFT                                        0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT                        0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_INDEX_MASK                                         0x00000007L
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_TOTAL_NUM_MASK                                     0x000000E0L
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_MASK                                          0x00003F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR3_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK                          0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT                               0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CAP__VF_BAR_SIZE_SUPPORTED_MASK                                 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM__SHIFT                                   0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE__SHIFT                                        0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT                        0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_INDEX_MASK                                         0x00000007L
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_TOTAL_NUM_MASK                                     0x000000E0L
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_MASK                                          0x00003F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR4_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK                          0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT                               0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CAP__VF_BAR_SIZE_SUPPORTED_MASK                                 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM__SHIFT                                   0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE__SHIFT                                        0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT                        0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_INDEX_MASK                                         0x00000007L
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_TOTAL_NUM_MASK                                     0x000000E0L
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_MASK                                          0x00003F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR5_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK                          0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CAP
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED__SHIFT                               0x4
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CAP__VF_BAR_SIZE_SUPPORTED_MASK                                 0xFFFFFFF0L
+//BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM__SHIFT                                   0x5
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE__SHIFT                                        0x8
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER__SHIFT                        0x10
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_INDEX_MASK                                         0x00000007L
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_TOTAL_NUM_MASK                                     0x000000E0L
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_MASK                                          0x00003F00L
+#define BIF_CFG_DEV0_EPF1_PCIE_VF_RESIZE_BAR6_CNTL__VF_BAR_SIZE_SUPPORTED_UPPER_MASK                          0xFFFF0000L
+
+
+// addressBlock: nbif0_nbif0_bif_cfg_dev0_epf1_vf0_bifcfgdecp
+//BIF_CFG_DEV0_EPF1_VF0_VENDOR_ID
+#define BIF_CFG_DEV0_EPF1_VF0_VENDOR_ID__VENDOR_ID__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF1_VF0_VENDOR_ID__VENDOR_ID_MASK                                                       0xFFFFL
+//BIF_CFG_DEV0_EPF1_VF0_DEVICE_ID
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_ID__DEVICE_ID__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_ID__DEVICE_ID_MASK                                                       0xFFFFL
+//BIF_CFG_DEV0_EPF1_VF0_COMMAND
+#define BIF_CFG_DEV0_EPF1_VF0_COMMAND__IO_ACCESS_EN__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF1_VF0_COMMAND__MEM_ACCESS_EN__SHIFT                                                   0x1
+#define BIF_CFG_DEV0_EPF1_VF0_COMMAND__BUS_MASTER_EN__SHIFT                                                   0x2
+#define BIF_CFG_DEV0_EPF1_VF0_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                0x3
+#define BIF_CFG_DEV0_EPF1_VF0_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                         0x4
+#define BIF_CFG_DEV0_EPF1_VF0_COMMAND__PAL_SNOOP_EN__SHIFT                                                    0x5
+#define BIF_CFG_DEV0_EPF1_VF0_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                           0x6
+#define BIF_CFG_DEV0_EPF1_VF0_COMMAND__AD_STEPPING__SHIFT                                                     0x7
+#define BIF_CFG_DEV0_EPF1_VF0_COMMAND__SERR_EN__SHIFT                                                         0x8
+#define BIF_CFG_DEV0_EPF1_VF0_COMMAND__FAST_B2B_EN__SHIFT                                                     0x9
+#define BIF_CFG_DEV0_EPF1_VF0_COMMAND__INT_DIS__SHIFT                                                         0xa
+#define BIF_CFG_DEV0_EPF1_VF0_COMMAND__IO_ACCESS_EN_MASK                                                      0x0001L
+#define BIF_CFG_DEV0_EPF1_VF0_COMMAND__MEM_ACCESS_EN_MASK                                                     0x0002L
+#define BIF_CFG_DEV0_EPF1_VF0_COMMAND__BUS_MASTER_EN_MASK                                                     0x0004L
+#define BIF_CFG_DEV0_EPF1_VF0_COMMAND__SPECIAL_CYCLE_EN_MASK                                                  0x0008L
+#define BIF_CFG_DEV0_EPF1_VF0_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                           0x0010L
+#define BIF_CFG_DEV0_EPF1_VF0_COMMAND__PAL_SNOOP_EN_MASK                                                      0x0020L
+#define BIF_CFG_DEV0_EPF1_VF0_COMMAND__PARITY_ERROR_RESPONSE_MASK                                             0x0040L
+#define BIF_CFG_DEV0_EPF1_VF0_COMMAND__AD_STEPPING_MASK                                                       0x0080L
+#define BIF_CFG_DEV0_EPF1_VF0_COMMAND__SERR_EN_MASK                                                           0x0100L
+#define BIF_CFG_DEV0_EPF1_VF0_COMMAND__FAST_B2B_EN_MASK                                                       0x0200L
+#define BIF_CFG_DEV0_EPF1_VF0_COMMAND__INT_DIS_MASK                                                           0x0400L
+//BIF_CFG_DEV0_EPF1_VF0_STATUS
+#define BIF_CFG_DEV0_EPF1_VF0_STATUS__IMMEDIATE_READINESS__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF1_VF0_STATUS__INT_STATUS__SHIFT                                                       0x3
+#define BIF_CFG_DEV0_EPF1_VF0_STATUS__CAP_LIST__SHIFT                                                         0x4
+#define BIF_CFG_DEV0_EPF1_VF0_STATUS__PCI_66_CAP__SHIFT                                                       0x5
+#define BIF_CFG_DEV0_EPF1_VF0_STATUS__FAST_BACK_CAPABLE__SHIFT                                                0x7
+#define BIF_CFG_DEV0_EPF1_VF0_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                         0x8
+#define BIF_CFG_DEV0_EPF1_VF0_STATUS__DEVSEL_TIMING__SHIFT                                                    0x9
+#define BIF_CFG_DEV0_EPF1_VF0_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                              0xb
+#define BIF_CFG_DEV0_EPF1_VF0_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                            0xc
+#define BIF_CFG_DEV0_EPF1_VF0_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                            0xd
+#define BIF_CFG_DEV0_EPF1_VF0_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                            0xe
+#define BIF_CFG_DEV0_EPF1_VF0_STATUS__PARITY_ERROR_DETECTED__SHIFT                                            0xf
+#define BIF_CFG_DEV0_EPF1_VF0_STATUS__IMMEDIATE_READINESS_MASK                                                0x0001L
+#define BIF_CFG_DEV0_EPF1_VF0_STATUS__INT_STATUS_MASK                                                         0x0008L
+#define BIF_CFG_DEV0_EPF1_VF0_STATUS__CAP_LIST_MASK                                                           0x0010L
+#define BIF_CFG_DEV0_EPF1_VF0_STATUS__PCI_66_CAP_MASK                                                         0x0020L
+#define BIF_CFG_DEV0_EPF1_VF0_STATUS__FAST_BACK_CAPABLE_MASK                                                  0x0080L
+#define BIF_CFG_DEV0_EPF1_VF0_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                           0x0100L
+#define BIF_CFG_DEV0_EPF1_VF0_STATUS__DEVSEL_TIMING_MASK                                                      0x0600L
+#define BIF_CFG_DEV0_EPF1_VF0_STATUS__SIGNAL_TARGET_ABORT_MASK                                                0x0800L
+#define BIF_CFG_DEV0_EPF1_VF0_STATUS__RECEIVED_TARGET_ABORT_MASK                                              0x1000L
+#define BIF_CFG_DEV0_EPF1_VF0_STATUS__RECEIVED_MASTER_ABORT_MASK                                              0x2000L
+#define BIF_CFG_DEV0_EPF1_VF0_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                              0x4000L
+#define BIF_CFG_DEV0_EPF1_VF0_STATUS__PARITY_ERROR_DETECTED_MASK                                              0x8000L
+//BIF_CFG_DEV0_EPF1_VF0_REVISION_ID
+#define BIF_CFG_DEV0_EPF1_VF0_REVISION_ID__MINOR_REV_ID__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF1_VF0_REVISION_ID__MAJOR_REV_ID__SHIFT                                                0x4
+#define BIF_CFG_DEV0_EPF1_VF0_REVISION_ID__MINOR_REV_ID_MASK                                                  0x0FL
+#define BIF_CFG_DEV0_EPF1_VF0_REVISION_ID__MAJOR_REV_ID_MASK                                                  0xF0L
+//BIF_CFG_DEV0_EPF1_VF0_PROG_INTERFACE
+#define BIF_CFG_DEV0_EPF1_VF0_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF1_VF0_PROG_INTERFACE__PROG_INTERFACE_MASK                                             0xFFL
+//BIF_CFG_DEV0_EPF1_VF0_SUB_CLASS
+#define BIF_CFG_DEV0_EPF1_VF0_SUB_CLASS__SUB_CLASS__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF1_VF0_SUB_CLASS__SUB_CLASS_MASK                                                       0xFFL
+//BIF_CFG_DEV0_EPF1_VF0_BASE_CLASS
+#define BIF_CFG_DEV0_EPF1_VF0_BASE_CLASS__BASE_CLASS__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF1_VF0_BASE_CLASS__BASE_CLASS_MASK                                                     0xFFL
+//BIF_CFG_DEV0_EPF1_VF0_CACHE_LINE
+#define BIF_CFG_DEV0_EPF1_VF0_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                              0x0
+#define BIF_CFG_DEV0_EPF1_VF0_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                0xFFL
+//BIF_CFG_DEV0_EPF1_VF0_LATENCY
+#define BIF_CFG_DEV0_EPF1_VF0_LATENCY__LATENCY_TIMER__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF1_VF0_LATENCY__LATENCY_TIMER_MASK                                                     0xFFL
+//BIF_CFG_DEV0_EPF1_VF0_HEADER
+#define BIF_CFG_DEV0_EPF1_VF0_HEADER__HEADER_TYPE__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF1_VF0_HEADER__DEVICE_TYPE__SHIFT                                                      0x7
+#define BIF_CFG_DEV0_EPF1_VF0_HEADER__HEADER_TYPE_MASK                                                        0x7FL
+#define BIF_CFG_DEV0_EPF1_VF0_HEADER__DEVICE_TYPE_MASK                                                        0x80L
+//BIF_CFG_DEV0_EPF1_VF0_BIST
+#define BIF_CFG_DEV0_EPF1_VF0_BIST__BIST_COMP__SHIFT                                                          0x0
+#define BIF_CFG_DEV0_EPF1_VF0_BIST__BIST_STRT__SHIFT                                                          0x6
+#define BIF_CFG_DEV0_EPF1_VF0_BIST__BIST_CAP__SHIFT                                                           0x7
+#define BIF_CFG_DEV0_EPF1_VF0_BIST__BIST_COMP_MASK                                                            0x0FL
+#define BIF_CFG_DEV0_EPF1_VF0_BIST__BIST_STRT_MASK                                                            0x40L
+#define BIF_CFG_DEV0_EPF1_VF0_BIST__BIST_CAP_MASK                                                             0x80L
+//BIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_1
+#define BIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_1__BASE_ADDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_1__BASE_ADDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_2
+#define BIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_2__BASE_ADDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_2__BASE_ADDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_3
+#define BIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_3__BASE_ADDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_3__BASE_ADDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_4
+#define BIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_4__BASE_ADDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_4__BASE_ADDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_5
+#define BIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_5__BASE_ADDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_5__BASE_ADDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_6
+#define BIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_6__BASE_ADDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF1_VF0_BASE_ADDR_6__BASE_ADDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_VF0_CARDBUS_CIS_PTR
+#define BIF_CFG_DEV0_EPF1_VF0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF1_VF0_CARDBUS_CIS_PTR__CARDBUS_CIS_PTR_MASK                                           0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_VF0_ADAPTER_ID
+#define BIF_CFG_DEV0_EPF1_VF0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF1_VF0_ADAPTER_ID__SUBSYSTEM_ID__SHIFT                                                 0x10
+#define BIF_CFG_DEV0_EPF1_VF0_ADAPTER_ID__SUBSYSTEM_VENDOR_ID_MASK                                            0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_VF0_ADAPTER_ID__SUBSYSTEM_ID_MASK                                                   0xFFFF0000L
+//BIF_CFG_DEV0_EPF1_VF0_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_EPF1_VF0_ROM_BASE_ADDR__ROM_ENABLE__SHIFT                                                0x0
+#define BIF_CFG_DEV0_EPF1_VF0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT                                     0x1
+#define BIF_CFG_DEV0_EPF1_VF0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT                                    0x4
+#define BIF_CFG_DEV0_EPF1_VF0_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                 0xb
+#define BIF_CFG_DEV0_EPF1_VF0_ROM_BASE_ADDR__ROM_ENABLE_MASK                                                  0x00000001L
+#define BIF_CFG_DEV0_EPF1_VF0_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK                                       0x0000000EL
+#define BIF_CFG_DEV0_EPF1_VF0_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK                                      0x000000F0L
+#define BIF_CFG_DEV0_EPF1_VF0_ROM_BASE_ADDR__BASE_ADDR_MASK                                                   0xFFFFF800L
+//BIF_CFG_DEV0_EPF1_VF0_CAP_PTR
+#define BIF_CFG_DEV0_EPF1_VF0_CAP_PTR__CAP_PTR__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_EPF1_VF0_CAP_PTR__CAP_PTR_MASK                                                           0xFFL
+//BIF_CFG_DEV0_EPF1_VF0_INTERRUPT_LINE
+#define BIF_CFG_DEV0_EPF1_VF0_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF1_VF0_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                             0xFFL
+//BIF_CFG_DEV0_EPF1_VF0_INTERRUPT_PIN
+#define BIF_CFG_DEV0_EPF1_VF0_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF1_VF0_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                               0xFFL
+//BIF_CFG_DEV0_EPF1_VF0_MIN_GRANT
+#define BIF_CFG_DEV0_EPF1_VF0_MIN_GRANT__MIN_GNT__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF1_VF0_MIN_GRANT__MIN_GNT_MASK                                                         0xFFL
+//BIF_CFG_DEV0_EPF1_VF0_MAX_LATENCY
+#define BIF_CFG_DEV0_EPF1_VF0_MAX_LATENCY__MAX_LAT__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF1_VF0_MAX_LATENCY__MAX_LAT_MASK                                                       0xFFL
+//BIF_CFG_DEV0_EPF1_VF0_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CAP_LIST__CAP_ID__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                  0x8
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CAP_LIST__CAP_ID_MASK                                                      0x00FFL
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CAP_LIST__NEXT_PTR_MASK                                                    0xFF00L
+//BIF_CFG_DEV0_EPF1_VF0_PCIE_CAP
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CAP__VERSION__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CAP__DEVICE_TYPE__SHIFT                                                    0x4
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                               0x8
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                0x9
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CAP__FLIT_MODE_SUPPORT__SHIFT                                              0xf
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CAP__VERSION_MASK                                                          0x000FL
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CAP__DEVICE_TYPE_MASK                                                      0x00F0L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                 0x0100L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                  0x3E00L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CAP__FLIT_MODE_SUPPORT_MASK                                                0x8000L
+//BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                 0x3
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                 0x5
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                       0x6
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                        0x9
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                     0xf
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP__RX_MPS_FIXED__SHIFT                                                 0x11
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                    0x12
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                    0x1a
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                  0x1c
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP__MIXED_MPS_SUPPORTED__SHIFT                                          0x1d
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP__TEE_IO_SUPPORT__SHIFT                                               0x1e
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                            0x00000007L
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP__PHANTOM_FUNC_MASK                                                   0x00000018L
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP__EXTENDED_TAG_MASK                                                   0x00000020L
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                         0x000001C0L
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                          0x00000E00L
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                       0x00008000L
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK                                       0x00010000L
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP__RX_MPS_FIXED_MASK                                                   0x00020000L
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                      0x03FC0000L
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                      0x0C000000L
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP__FLR_CAPABLE_MASK                                                    0x10000000L
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP__MIXED_MPS_SUPPORTED_MASK                                            0x20000000L
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP__TEE_IO_SUPPORT_MASK                                                 0x40000000L
+//BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                            0x1
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                0x2
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                               0x3
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                              0x4
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                            0x5
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                             0x8
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                             0x9
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                             0xa
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                 0xb
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                       0xc
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL__INITIATE_FLR__SHIFT                                                0xf
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL__CORR_ERR_EN_MASK                                                   0x0001L
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                              0x0002L
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                  0x0004L
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL__USR_REPORT_EN_MASK                                                 0x0008L
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                0x0010L
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                              0x00E0L
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                               0x0100L
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                               0x0200L
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                               0x0400L
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                   0x0800L
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                         0x7000L
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL__INITIATE_FLR_MASK                                                  0x8000L
+//BIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS__CORR_ERR__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                             0x1
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS__FATAL_ERR__SHIFT                                                 0x2
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS__USR_DETECTED__SHIFT                                              0x3
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS__AUX_PWR__SHIFT                                                   0x4
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                         0x5
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                             0x6
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS__CORR_ERR_MASK                                                    0x0001L
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS__NON_FATAL_ERR_MASK                                               0x0002L
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS__FATAL_ERR_MASK                                                   0x0004L
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS__USR_DETECTED_MASK                                                0x0008L
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS__AUX_PWR_MASK                                                     0x0010L
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                           0x0020L
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                               0x0040L
+//BIF_CFG_DEV0_EPF1_VF0_LINK_CAP
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP__LINK_SPEED__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP__LINK_WIDTH__SHIFT                                                     0x4
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP__PM_SUPPORT__SHIFT                                                     0xa
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                               0xc
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                0xf
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                         0x12
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                    0x13
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                    0x14
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                       0x15
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                    0x16
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP__PORT_NUMBER__SHIFT                                                    0x18
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP__LINK_SPEED_MASK                                                       0x0000000FL
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP__LINK_WIDTH_MASK                                                       0x000003F0L
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP__PM_SUPPORT_MASK                                                       0x00000C00L
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                 0x00007000L
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP__L1_EXIT_LATENCY_MASK                                                  0x00038000L
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                           0x00040000L
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                      0x00080000L
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                      0x00100000L
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                         0x00200000L
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                      0x00400000L
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP__PORT_NUMBER_MASK                                                      0xFF000000L
+//BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL__PM_CONTROL__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT                                  0x2
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                             0x3
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL__LINK_DIS__SHIFT                                                      0x4
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL__RETRAIN_LINK__SHIFT                                                  0x5
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                              0x6
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                 0x7
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                   0x9
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                     0xa
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                     0xb
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL__SRIS_CLOCKING__SHIFT                                                 0xc
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL__FLIT_MODE_DISABLE__SHIFT                                             0xd
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                         0xe
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL__PM_CONTROL_MASK                                                      0x0003L
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK                                    0x0004L
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                               0x0008L
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL__LINK_DIS_MASK                                                        0x0010L
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL__RETRAIN_LINK_MASK                                                    0x0020L
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                0x0040L
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL__EXTENDED_SYNC_MASK                                                   0x0080L
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                       0x0100L
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                     0x0200L
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                       0x0400L
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                       0x0800L
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL__SRIS_CLOCKING_MASK                                                   0x1000L
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL__FLIT_MODE_DISABLE_MASK                                               0x2000L
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                           0xC000L
+//BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                       0x4
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS__LINK_TRAINING__SHIFT                                               0xb
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                              0xc
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS__DL_ACTIVE__SHIFT                                                   0xd
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                   0xe
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                   0xf
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                            0x000FL
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                         0x03F0L
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS__LINK_TRAINING_MASK                                                 0x0800L
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                0x1000L
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS__DL_ACTIVE_MASK                                                     0x2000L
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                     0x4000L
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                     0x8000L
+//BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                 0x0
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                   0x4
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                    0x5
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                  0x6
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                  0x7
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                  0x8
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                      0x9
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                   0xa
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                               0xb
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                          0xc
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                               0xe
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                             0x10
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                             0x11
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                              0x12
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                0x14
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                0x15
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                    0x16
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                              0x18
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                               0x1a
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                               0x1f
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                   0x0000000FL
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                     0x00000010L
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                      0x00000020L
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                    0x00000040L
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                    0x00000080L
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                    0x00000100L
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                        0x00000200L
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                     0x00000400L
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                 0x00000800L
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                            0x00003000L
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                 0x0000C000L
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                               0x00010000L
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                               0x00020000L
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                0x000C0000L
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                  0x00100000L
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                  0x00200000L
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                      0x00C00000L
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                0x03000000L
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                 0x04000000L
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                 0x80000000L
+//BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL2
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                            0x4
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                          0x5
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                        0x6
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                   0x7
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                         0x8
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                      0x9
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL2__LTR_EN__SHIFT                                                     0xa
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                               0xb
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                               0xc
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL2__OBFF_EN__SHIFT                                                    0xd
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                0xf
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                            0x000FL
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                              0x0010L
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                            0x0020L
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                          0x0040L
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                     0x0080L
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                           0x0100L
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                        0x0200L
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL2__LTR_EN_MASK                                                       0x0400L
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                 0x0800L
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                 0x1000L
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL2__OBFF_EN_MASK                                                      0x6000L
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                  0x8000L
+//BIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS2
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS2__RESERVED__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS2__RESERVED_MASK                                                   0xFFFFL
+//BIF_CFG_DEV0_EPF1_VF0_LINK_CAP2
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                          0x1
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                           0x8
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT                                      0x9
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                      0x10
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                     0x17
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                     0x18
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                 0x1f
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                            0x000000FEL
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                             0x00000100L
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK                                        0x0000FE00L
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                        0x007F0000L
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                       0x00800000L
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                       0x01000000L
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_CAP2__DRS_SUPPORTED_MASK                                                   0x80000000L
+//BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL2
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                             0x4
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                  0x5
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                        0x6
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                  0x7
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                         0xa
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                               0xb
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                        0xc
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                              0x000FL
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                               0x0010L
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                    0x0020L
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                          0x0040L
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL2__XMIT_MARGIN_MASK                                                    0x0380L
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                           0x0400L
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                 0x0800L
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                          0xF000L
+//BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS2
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                  0x1
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                            0x2
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                            0x3
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                            0x4
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                              0x5
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                          0x6
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                          0x7
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                       0x8
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS2__FLIT_MODE_STATUS__SHIFT                                           0xa
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                              0xc
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                       0xf
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                         0x0001L
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                    0x0002L
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                              0x0004L
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                              0x0008L
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                              0x0010L
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                0x0020L
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                            0x0040L
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                            0x0080L
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                         0x0300L
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS2__FLIT_MODE_STATUS_MASK                                             0x0400L
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                0x7000L
+#define BIF_CFG_DEV0_EPF1_VF0_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                         0x8000L
+//BIF_CFG_DEV0_EPF1_VF0_MSI_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_VF0_MSI_CAP_LIST__CAP_ID__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF1_VF0_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_EPF1_VF0_MSI_CAP_LIST__CAP_ID_MASK                                                       0x00FFL
+#define BIF_CFG_DEV0_EPF1_VF0_MSI_CAP_LIST__NEXT_PTR_MASK                                                     0xFF00L
+//BIF_CFG_DEV0_EPF1_VF0_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_EPF1_VF0_MSI_MSG_CNTL__MSI_EN__SHIFT                                                     0x0
+#define BIF_CFG_DEV0_EPF1_VF0_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                              0x1
+#define BIF_CFG_DEV0_EPF1_VF0_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                               0x4
+#define BIF_CFG_DEV0_EPF1_VF0_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                  0x7
+#define BIF_CFG_DEV0_EPF1_VF0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                  0x8
+#define BIF_CFG_DEV0_EPF1_VF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT                                       0x9
+#define BIF_CFG_DEV0_EPF1_VF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT                                        0xa
+#define BIF_CFG_DEV0_EPF1_VF0_MSI_MSG_CNTL__MSI_EN_MASK                                                       0x0001L
+#define BIF_CFG_DEV0_EPF1_VF0_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                0x000EL
+#define BIF_CFG_DEV0_EPF1_VF0_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                 0x0070L
+#define BIF_CFG_DEV0_EPF1_VF0_MSI_MSG_CNTL__MSI_64BIT_MASK                                                    0x0080L
+#define BIF_CFG_DEV0_EPF1_VF0_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                    0x0100L
+#define BIF_CFG_DEV0_EPF1_VF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK                                         0x0200L
+#define BIF_CFG_DEV0_EPF1_VF0_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK                                          0x0400L
+//BIF_CFG_DEV0_EPF1_VF0_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_EPF1_VF0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                         0x2
+#define BIF_CFG_DEV0_EPF1_VF0_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                           0xFFFFFFFCL
+//BIF_CFG_DEV0_EPF1_VF0_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_EPF1_VF0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF1_VF0_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                           0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_VF0_MSI_MSG_DATA
+#define BIF_CFG_DEV0_EPF1_VF0_MSI_MSG_DATA__MSI_DATA__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF1_VF0_MSI_MSG_DATA__MSI_DATA_MASK                                                     0xFFFFL
+//BIF_CFG_DEV0_EPF1_VF0_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV0_EPF1_VF0_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF1_VF0_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK                                             0xFFFFL
+//BIF_CFG_DEV0_EPF1_VF0_MSI_MASK
+#define BIF_CFG_DEV0_EPF1_VF0_MSI_MASK__MSI_MASK__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_EPF1_VF0_MSI_MASK__MSI_MASK_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_VF0_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF1_VF0_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                             0x0
+#define BIF_CFG_DEV0_EPF1_VF0_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                               0xFFFFL
+//BIF_CFG_DEV0_EPF1_VF0_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV0_EPF1_VF0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF1_VF0_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK                                       0xFFFFL
+//BIF_CFG_DEV0_EPF1_VF0_MSI_MASK_64
+#define BIF_CFG_DEV0_EPF1_VF0_MSI_MASK_64__MSI_MASK_64__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF1_VF0_MSI_MASK_64__MSI_MASK_64_MASK                                                   0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_VF0_MSI_PENDING
+#define BIF_CFG_DEV0_EPF1_VF0_MSI_PENDING__MSI_PENDING__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_EPF1_VF0_MSI_PENDING__MSI_PENDING_MASK                                                   0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_VF0_MSI_PENDING_64
+#define BIF_CFG_DEV0_EPF1_VF0_MSI_PENDING_64__MSI_PENDING_64__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF1_VF0_MSI_PENDING_64__MSI_PENDING_64_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_VF0_MSIX_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_VF0_MSIX_CAP_LIST__CAP_ID__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF1_VF0_MSIX_CAP_LIST__NEXT_PTR__SHIFT                                                  0x8
+#define BIF_CFG_DEV0_EPF1_VF0_MSIX_CAP_LIST__CAP_ID_MASK                                                      0x00FFL
+#define BIF_CFG_DEV0_EPF1_VF0_MSIX_CAP_LIST__NEXT_PTR_MASK                                                    0xFF00L
+//BIF_CFG_DEV0_EPF1_VF0_MSIX_MSG_CNTL
+#define BIF_CFG_DEV0_EPF1_VF0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF1_VF0_MSIX_MSG_CNTL__MSIX_FUNC_MASK__SHIFT                                            0xe
+#define BIF_CFG_DEV0_EPF1_VF0_MSIX_MSG_CNTL__MSIX_EN__SHIFT                                                   0xf
+#define BIF_CFG_DEV0_EPF1_VF0_MSIX_MSG_CNTL__MSIX_TABLE_SIZE_MASK                                             0x07FFL
+#define BIF_CFG_DEV0_EPF1_VF0_MSIX_MSG_CNTL__MSIX_FUNC_MASK_MASK                                              0x4000L
+#define BIF_CFG_DEV0_EPF1_VF0_MSIX_MSG_CNTL__MSIX_EN_MASK                                                     0x8000L
+//BIF_CFG_DEV0_EPF1_VF0_MSIX_TABLE
+#define BIF_CFG_DEV0_EPF1_VF0_MSIX_TABLE__MSIX_TABLE_BIR__SHIFT                                               0x0
+#define BIF_CFG_DEV0_EPF1_VF0_MSIX_TABLE__MSIX_TABLE_OFFSET__SHIFT                                            0x3
+#define BIF_CFG_DEV0_EPF1_VF0_MSIX_TABLE__MSIX_TABLE_BIR_MASK                                                 0x00000007L
+#define BIF_CFG_DEV0_EPF1_VF0_MSIX_TABLE__MSIX_TABLE_OFFSET_MASK                                              0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF1_VF0_MSIX_PBA
+#define BIF_CFG_DEV0_EPF1_VF0_MSIX_PBA__MSIX_PBA_BIR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF1_VF0_MSIX_PBA__MSIX_PBA_OFFSET__SHIFT                                                0x3
+#define BIF_CFG_DEV0_EPF1_VF0_MSIX_PBA__MSIX_PBA_BIR_MASK                                                     0x00000007L
+#define BIF_CFG_DEV0_EPF1_VF0_MSIX_PBA__MSIX_PBA_OFFSET_MASK                                                  0xFFFFFFF8L
+//BIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                0x0
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                               0x10
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                              0x14
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                  0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                 0x000F0000L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                0xFFF00000L
+//BIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                       0x10
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                    0x14
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                         0x000F0000L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                      0xFFF00000L
+//BIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                           0x0
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                             0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_VF0_PCIE_DEVICE3_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_DEVICE3_ENH_CAP_LIST__CAP_ID__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_DEVICE3_ENH_CAP_LIST__CAP_VER__SHIFT                                       0x10
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_DEVICE3_ENH_CAP_LIST__NEXT_PTR__SHIFT                                      0x14
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_DEVICE3_ENH_CAP_LIST__CAP_ID_MASK                                          0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_DEVICE3_ENH_CAP_LIST__CAP_VER_MASK                                         0x000F0000L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_DEVICE3_ENH_CAP_LIST__NEXT_PTR_MASK                                        0xFFF00000L
+//BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP3
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP3__DMWR_REQUEST_ROUTING_SUPPORTED__SHIFT                              0x0
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_COMPLETER_SUPPORTED__SHIFT                   0x1
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_REQUESTER_SUPPORTED__SHIFT                   0x2
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP3__RECEIVER_L0P_SUPPORTED__SHIFT                                      0x3
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP3__PORT_L0P_EXIT_LATENCY__SHIFT                                       0x4
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP3__RETIMER_L0P_EXIT_LATENCY__SHIFT                                    0x7
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP3__DMWR_REQUEST_ROUTING_SUPPORTED_MASK                                0x00000001L
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_COMPLETER_SUPPORTED_MASK                     0x00000002L
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP3__DEVICE_CAP3_14BIT_TAG_REQUESTER_SUPPORTED_MASK                     0x00000004L
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP3__RECEIVER_L0P_SUPPORTED_MASK                                        0x00000008L
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP3__PORT_L0P_EXIT_LATENCY_MASK                                         0x00000070L
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CAP3__RETIMER_L0P_EXIT_LATENCY_MASK                                      0x00000380L
+//BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL3
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL3__DMWR_REQUEST_ENABLE__SHIFT                                        0x0
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL3__DMWR_EGRESS_BLOCKING__SHIFT                                       0x1
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL3__DEVICE_CNTL3_14BIT_TAG_REQUESTER_ENABLE__SHIFT                    0x2
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL3__L0P_ENABLE__SHIFT                                                 0x3
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL3__TARGET_LINK_WIDTH__SHIFT                                          0x4
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL3__DMWR_REQUEST_ENABLE_MASK                                          0x00000001L
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL3__DMWR_EGRESS_BLOCKING_MASK                                         0x00000002L
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL3__DEVICE_CNTL3_14BIT_TAG_REQUESTER_ENABLE_MASK                      0x00000004L
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL3__L0P_ENABLE_MASK                                                   0x00000008L
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_CNTL3__TARGET_LINK_WIDTH_MASK                                            0x00000070L
+//BIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS3
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS3__INITIAL_LINK_WIDTH__SHIFT                                       0x0
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS3__SEGMENT_CAPTURED__SHIFT                                         0x3
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS3__REMOTE_L0P_SUPPORTED__SHIFT                                     0x4
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS3__INITIAL_LINK_WIDTH_MASK                                         0x00000007L
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS3__SEGMENT_CAPTURED_MASK                                           0x00000008L
+#define BIF_CFG_DEV0_EPF1_VF0_DEVICE_STATUS3__REMOTE_L0P_SUPPORTED_MASK                                       0x00000010L
+//BIF_CFG_DEV0_EPF1_VF0_PCIE_NULL1_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_NULL1_ENH_CAP_LIST__CAP_ID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_NULL1_ENH_CAP_LIST__CAP_VER__SHIFT                                         0x10
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_NULL1_ENH_CAP_LIST__NEXT_PTR__SHIFT                                        0x14
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_NULL1_ENH_CAP_LIST__CAP_ID_MASK                                            0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_NULL1_ENH_CAP_LIST__CAP_VER_MASK                                           0x000F0000L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_NULL1_ENH_CAP_LIST__NEXT_PTR_MASK                                          0xFFF00000L
+//BIF_CFG_DEV0_EPF1_VF0_PCIE_NULL2_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_NULL2_ENH_CAP_LIST__CAP_ID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_NULL2_ENH_CAP_LIST__CAP_VER__SHIFT                                         0x10
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_NULL2_ENH_CAP_LIST__NEXT_PTR__SHIFT                                        0x14
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_NULL2_ENH_CAP_LIST__CAP_ID_MASK                                            0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_NULL2_ENH_CAP_LIST__CAP_VER_MASK                                           0x000F0000L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_NULL2_ENH_CAP_LIST__NEXT_PTR_MASK                                          0xFFF00000L
+//BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                    0x0
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                   0x10
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                  0x14
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                      0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                     0x000F0000L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                    0xFFF00000L
+//BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                   0x4
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                0x5
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                   0xc
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                    0xd
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                               0xe
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                             0xf
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                 0x10
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                  0x11
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                   0x12
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                  0x13
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                            0x14
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                             0x15
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                            0x16
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                            0x17
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                   0x18
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                    0x19
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT               0x1a
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__DMWR_REQUEST_EGRESS_BLOCKED_STATUS__SHIFT               0x1b
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__IDE_CHECK_FAILED_STATUS__SHIFT                          0x1c
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__MISROUTED_IDE_TLP_STATUS__SHIFT                         0x1d
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__PCRC_CHECK_FAILED_STATUS__SHIFT                         0x1e
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                     0x00000010L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                  0x00000020L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                     0x00001000L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                      0x00002000L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                 0x00004000L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                               0x00008000L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                   0x00010000L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                    0x00020000L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                     0x00040000L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                    0x00080000L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                              0x00100000L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                               0x00200000L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                              0x00400000L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                              0x00800000L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                     0x01000000L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                      0x02000000L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                 0x04000000L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__DMWR_REQUEST_EGRESS_BLOCKED_STATUS_MASK                 0x08000000L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__IDE_CHECK_FAILED_STATUS_MASK                            0x10000000L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__MISROUTED_IDE_TLP_STATUS_MASK                           0x20000000L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_STATUS__PCRC_CHECK_FAILED_STATUS_MASK                           0x40000000L
+//BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                       0x4
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                    0x5
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                       0xc
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                        0xd
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                   0xe
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                 0xf
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                     0x10
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                      0x11
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                       0x12
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                      0x13
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                0x14
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                 0x15
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                0x16
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                0x17
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                       0x18
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                        0x19
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                   0x1a
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__DMWR_REQUEST_EGRESS_BLOCKED_MASK__SHIFT                   0x1b
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__IDE_CHECK_FAILED_MASK__SHIFT                              0x1c
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__MISROUTED_IDE_TLP_MASK__SHIFT                             0x1d
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__PCRC_CHECK_FAILED_MASK__SHIFT                             0x1e
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                         0x00000010L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                      0x00000020L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                         0x00001000L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                          0x00002000L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                     0x00004000L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                   0x00008000L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                       0x00010000L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                        0x00020000L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                         0x00040000L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                        0x00080000L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                  0x00100000L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                   0x00200000L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                  0x00400000L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                  0x00800000L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                         0x01000000L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                          0x02000000L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                     0x04000000L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__DMWR_REQUEST_EGRESS_BLOCKED_MASK_MASK                     0x08000000L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__IDE_CHECK_FAILED_MASK_MASK                                0x10000000L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__MISROUTED_IDE_TLP_MASK_MASK                               0x20000000L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_MASK__PCRC_CHECK_FAILED_MASK_MASK                               0x40000000L
+//BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                               0x4
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                            0x5
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                               0xc
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                0xd
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                           0xe
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                         0xf
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                             0x10
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                              0x11
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                               0x12
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                              0x13
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                        0x14
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                         0x15
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                        0x16
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                        0x17
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT               0x18
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                0x19
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT           0x1a
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__DMWR_REQUEST_EGRESS_BLOCKED_SEVERITY__SHIFT           0x1b
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__IDE_CHECK_FAILED_SEVERITY__SHIFT                      0x1c
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__MISROUTED_IDE_TLP_SEVERITY__SHIFT                     0x1d
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__PCRC_CHECK_FAILED_SEVERITY__SHIFT                     0x1e
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                 0x00000010L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                              0x00000020L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                 0x00001000L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                  0x00002000L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                             0x00004000L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                           0x00008000L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                               0x00010000L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                0x00020000L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                 0x00040000L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                0x00080000L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                          0x00100000L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                           0x00200000L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                          0x00400000L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                          0x00800000L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                 0x01000000L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                  0x02000000L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK             0x04000000L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__DMWR_REQUEST_EGRESS_BLOCKED_SEVERITY_MASK             0x08000000L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__IDE_CHECK_FAILED_SEVERITY_MASK                        0x10000000L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__MISROUTED_IDE_TLP_SEVERITY_MASK                       0x20000000L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_UNCORR_ERR_SEVERITY__PCRC_CHECK_FAILED_SEVERITY_MASK                       0x40000000L
+//BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                     0x6
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                    0x7
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                         0x8
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                        0xc
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                       0xd
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                0xe
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                                0xf
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                       0x00000001L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                       0x00000040L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                      0x00000080L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                           0x00000100L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                          0x00001000L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                         0x00002000L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                  0x00004000L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                  0x00008000L
+//BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                         0x6
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                        0x7
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                             0x8
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                            0xc
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                           0xd
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                    0xe
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                    0xf
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                           0x00000001L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                           0x00000040L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                          0x00000080L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                               0x00000100L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                              0x00001000L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                             0x00002000L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                      0x00004000L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                      0x00008000L
+//BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                     0x0
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT                                      0x5
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT                                       0x6
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                    0x7
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                     0x8
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                0x9
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                 0xa
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                            0xb
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT                    0xc
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_CAP_CNTL__HEADER_LOG_SIZE__SHIFT                                   0xd
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_WAS_FLIT_MODE__SHIFT                          0x12
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_SIZE__SHIFT                                   0x13
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                       0x0000001FL
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK                                        0x00000020L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK                                         0x00000040L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                      0x00000080L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                       0x00000100L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                  0x00000200L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                   0x00000400L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                              0x00000800L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK                      0x00001000L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_CAP_CNTL__HEADER_LOG_SIZE_MASK                                     0x0003E000L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_WAS_FLIT_MODE_MASK                            0x00040000L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_SIZE_MASK                                     0x00F80000L
+//BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG0__TLP_HDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG1__TLP_HDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG2__TLP_HDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG3__TLP_HDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG4
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG4__TLP_HDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG4__TLP_HDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_VF0_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                           0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG5
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG5__TLP_HDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG5__TLP_HDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_VF0_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                           0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG6
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG6__TLP_HDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG6__TLP_HDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_VF0_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                           0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG7
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG7__TLP_HDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG7__TLP_HDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_VF0_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                         0x0
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                           0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG8
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG8__TLP_HDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG8__TLP_HDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG9
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG9__TLP_HDR__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG9__TLP_HDR_MASK                                                     0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG10
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG10__TLP_HDR__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG10__TLP_HDR_MASK                                                    0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG11
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG11__TLP_HDR__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG11__TLP_HDR_MASK                                                    0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG12
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG12__TLP_HDR__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG12__TLP_HDR_MASK                                                    0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG13
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG13__TLP_HDR__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_HDR_LOG13__TLP_HDR_MASK                                                    0xFFFFFFFFL
+//BIF_CFG_DEV0_EPF1_VF0_PCIE_RTR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
+//BIF_CFG_DEV0_EPF1_VF0_RTR_DATA1
+#define BIF_CFG_DEV0_EPF1_VF0_RTR_DATA1__RESET_TIME__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_EPF1_VF0_RTR_DATA1__DLUP_TIME__SHIFT                                                     0xc
+#define BIF_CFG_DEV0_EPF1_VF0_RTR_DATA1__RTR_VALID__SHIFT                                                     0x1f
+#define BIF_CFG_DEV0_EPF1_VF0_RTR_DATA1__RESET_TIME_MASK                                                      0x00000FFFL
+#define BIF_CFG_DEV0_EPF1_VF0_RTR_DATA1__DLUP_TIME_MASK                                                       0x00FFF000L
+#define BIF_CFG_DEV0_EPF1_VF0_RTR_DATA1__RTR_VALID_MASK                                                       0x80000000L
+//BIF_CFG_DEV0_EPF1_VF0_RTR_DATA2
+#define BIF_CFG_DEV0_EPF1_VF0_RTR_DATA2__FLR_TIME__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_EPF1_VF0_RTR_DATA2__D3HOTD0_TIME__SHIFT                                                  0xc
+#define BIF_CFG_DEV0_EPF1_VF0_RTR_DATA2__FLR_TIME_MASK                                                        0x00000FFFL
+#define BIF_CFG_DEV0_EPF1_VF0_RTR_DATA2__D3HOTD0_TIME_MASK                                                    0x00FFF000L
+//BIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_ENH_CAP_LIST
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
+//BIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_CAP
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP__SHIFT                                    0x1
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM__SHIFT                                          0x8
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_CAP__ARI_MFVC_FUNC_GROUPS_CAP_MASK                                     0x0001L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_CAP__ARI_ACS_FUNC_GROUPS_CAP_MASK                                      0x0002L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_CAP__ARI_NEXT_FUNC_NUM_MASK                                            0xFF00L
+//BIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_CNTL
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN__SHIFT                                   0x0
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN__SHIFT                                    0x1
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP__SHIFT                                        0x4
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_CNTL__ARI_MFVC_FUNC_GROUPS_EN_MASK                                     0x0001L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_CNTL__ARI_ACS_FUNC_GROUPS_EN_MASK                                      0x0002L
+#define BIF_CFG_DEV0_EPF1_VF0_PCIE_ARI_CNTL__ARI_FUNCTION_GROUP_MASK                                          0x0070L
+
+
+// addressBlock: nbif0_nbif0_rcc_dev0_RCCPORTDEC
+//RCC_DEV0_1_RCC_VDM_SUPPORT
+#define RCC_DEV0_1_RCC_VDM_SUPPORT__MCTP_SUPPORT__SHIFT                                                       0x0
+#define RCC_DEV0_1_RCC_VDM_SUPPORT__AMPTP_SUPPORT__SHIFT                                                      0x1
+#define RCC_DEV0_1_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT__SHIFT                                                  0x2
+#define RCC_DEV0_1_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE__SHIFT                                        0x3
+#define RCC_DEV0_1_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE__SHIFT                                    0x4
+#define RCC_DEV0_1_RCC_VDM_SUPPORT__MCTP_SUPPORT_MASK                                                         0x00000001L
+#define RCC_DEV0_1_RCC_VDM_SUPPORT__AMPTP_SUPPORT_MASK                                                        0x00000002L
+#define RCC_DEV0_1_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT_MASK                                                    0x00000004L
+#define RCC_DEV0_1_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE_MASK                                          0x00000008L
+#define RCC_DEV0_1_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE_MASK                                      0x00000010L
+//RCC_DEV0_1_RCC_BUS_CNTL
+#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS__SHIFT                                                            0x2
+#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS__SHIFT                                                           0x3
+#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_BM_DIS__SHIFT                                                            0x4
+#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS_DN__SHIFT                                                         0x5
+#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS_DN__SHIFT                                                        0x6
+#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS_UP__SHIFT                                                         0x7
+#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS_UP__SHIFT                                                        0x8
+#define RCC_DEV0_1_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT__SHIFT                                                 0xc
+#define RCC_DEV0_1_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC__SHIFT                                           0xd
+#define RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR__SHIFT                                          0x10
+#define RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR__SHIFT                                          0x11
+#define RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR__SHIFT                                          0x12
+#define RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR__SHIFT                                          0x13
+#define RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR__SHIFT                                          0x14
+#define RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR__SHIFT                                          0x15
+#define RCC_DEV0_1_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE__SHIFT                                                 0x18
+#define RCC_DEV0_1_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE__SHIFT                                                 0x19
+#define RCC_DEV0_1_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE__SHIFT                                            0x1c
+#define RCC_DEV0_1_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE__SHIFT                                            0x1d
+#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS_MASK                                                              0x00000004L
+#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS_MASK                                                             0x00000008L
+#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_BM_DIS_MASK                                                              0x00000010L
+#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS_DN_MASK                                                           0x00000020L
+#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS_DN_MASK                                                          0x00000040L
+#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_IO_DIS_UP_MASK                                                           0x00000080L
+#define RCC_DEV0_1_RCC_BUS_CNTL__PMI_MEM_DIS_UP_MASK                                                          0x00000100L
+#define RCC_DEV0_1_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT_MASK                                                   0x00001000L
+#define RCC_DEV0_1_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC_MASK                                             0x00002000L
+#define RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR_MASK                                            0x00010000L
+#define RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR_MASK                                            0x00020000L
+#define RCC_DEV0_1_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR_MASK                                            0x00040000L
+#define RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR_MASK                                            0x00080000L
+#define RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR_MASK                                            0x00100000L
+#define RCC_DEV0_1_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR_MASK                                            0x00200000L
+#define RCC_DEV0_1_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE_MASK                                                   0x01000000L
+#define RCC_DEV0_1_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE_MASK                                                   0x0E000000L
+#define RCC_DEV0_1_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE_MASK                                              0x10000000L
+#define RCC_DEV0_1_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE_MASK                                              0xE0000000L
+//RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS__SHIFT                                   0x7
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__SHIFT                                 0x8
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR__SHIFT                                    0x9
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR__SHIFT                                    0xa
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR__SHIFT                                 0xb
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR__SHIFT                                  0xc
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR__SHIFT                                      0xd
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS__SHIFT                      0xe
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS__SHIFT                         0xf
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS__SHIFT                                 0x10
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS__SHIFT                           0x11
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN__SHIFT                               0x12
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS__SHIFT                     0x13
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS_MASK                                     0x00000080L
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN_MASK                                   0x00000100L
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR_MASK                                      0x00000200L
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR_MASK                                      0x00000400L
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR_MASK                                   0x00000800L
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR_MASK                                    0x00001000L
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR_MASK                                        0x00002000L
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS_MASK                        0x00004000L
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS_MASK                           0x00008000L
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS_MASK                                   0x00010000L
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS_MASK                             0x00020000L
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN_MASK                                 0x00040000L
+#define RCC_DEV0_1_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS_MASK                       0x00080000L
+//RCC_DEV0_1_RCC_DEV0_LINK_CNTL
+#define RCC_DEV0_1_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT__SHIFT                                                  0x0
+#define RCC_DEV0_1_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY__SHIFT                                                 0x8
+#define RCC_DEV0_1_RCC_DEV0_LINK_CNTL__SWUS_SRB_RST_TLS_DIS__SHIFT                                            0x10
+#define RCC_DEV0_1_RCC_DEV0_LINK_CNTL__SWUS_LDN_RST_TLS_DIS__SHIFT                                            0x11
+#define RCC_DEV0_1_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT_MASK                                                    0x00000001L
+#define RCC_DEV0_1_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY_MASK                                                   0x00000100L
+#define RCC_DEV0_1_RCC_DEV0_LINK_CNTL__SWUS_SRB_RST_TLS_DIS_MASK                                              0x00010000L
+#define RCC_DEV0_1_RCC_DEV0_LINK_CNTL__SWUS_LDN_RST_TLS_DIS_MASK                                              0x00020000L
+//RCC_DEV0_1_RCC_CMN_LINK_CNTL
+#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS__SHIFT                                             0x0
+#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS__SHIFT                                              0x1
+#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS__SHIFT                                             0x2
+#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN__SHIFT                                          0x3
+#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER__SHIFT                                             0x10
+#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS_MASK                                               0x00000001L
+#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS_MASK                                                0x00000002L
+#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS_MASK                                               0x00000004L
+#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN_MASK                                            0x00000008L
+#define RCC_DEV0_1_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER_MASK                                               0xFFFF0000L
+//RCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE
+#define RCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS__SHIFT                                            0x0
+#define RCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV__SHIFT                                            0x8
+#define RCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE__EP_REQID_SEG__SHIFT                                            0x10
+#define RCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS_MASK                                              0x000000FFL
+#define RCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV_MASK                                              0x00001F00L
+#define RCC_DEV0_1_RCC_EP_REQUESTERID_RESTORE__EP_REQID_SEG_MASK                                              0x00FF0000L
+//RCC_DEV0_1_RCC_LTR_LSWITCH_CNTL
+#define RCC_DEV0_1_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE__SHIFT                                         0x0
+#define RCC_DEV0_1_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE_MASK                                           0x000003FFL
+//RCC_DEV0_1_RCC_MH_ARB_CNTL
+#define RCC_DEV0_1_RCC_MH_ARB_CNTL__MH_ARB_MODE__SHIFT                                                        0x0
+#define RCC_DEV0_1_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY__SHIFT                                                0x1
+#define RCC_DEV0_1_RCC_MH_ARB_CNTL__MH_ARB_MODE_MASK                                                          0x00000001L
+#define RCC_DEV0_1_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY_MASK                                                  0x0000FFFEL
+//RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED__SHIFT                                 0x0
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING__SHIFT                              0x1
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE__SHIFT                                0x2
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER__SHIFT                                 0x3
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD__SHIFT                           0x4
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS__SHIFT                                  0x5
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET__SHIFT                                 0xb
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS__SHIFT                                 0x12
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET__SHIFT                                0x19
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED_MASK                                   0x00000001L
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING_MASK                                0x00000002L
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE_MASK                                  0x00000004L
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER_MASK                                   0x00000008L
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD_MASK                             0x00000010L
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS_MASK                                    0x000007E0L
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET_MASK                                   0x0003F800L
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS_MASK                                   0x01FC0000L
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET_MASK                                  0xFE000000L
+//RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE__SHIFT                             0x0
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING__SHIFT                              0x6
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES__SHIFT                                         0xc
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT__SHIFT                                      0x11
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE_MASK                               0x0000003FL
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING_MASK                                0x00000FC0L
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES_MASK                                           0x0001F000L
+#define RCC_DEV0_1_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT_MASK                                        0x00FE0000L
+
+
+// addressBlock: nbif0_nbif0_rcc_ep_dev0_RCCPORTDEC
+//RCC_EP_DEV0_1_EP_PCIE_SCRATCH
+#define RCC_EP_DEV0_1_EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT                                                    0x0
+#define RCC_EP_DEV0_1_EP_PCIE_SCRATCH__PCIE_SCRATCH_MASK                                                      0xFFFFFFFFL
+//RCC_EP_DEV0_1_EP_PCIE_CNTL
+#define RCC_EP_DEV0_1_EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT                                                  0x7
+#define RCC_EP_DEV0_1_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT                                            0x8
+#define RCC_EP_DEV0_1_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT                                               0x1e
+#define RCC_EP_DEV0_1_EP_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK                                                    0x00000080L
+#define RCC_EP_DEV0_1_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK                                              0x00000100L
+#define RCC_EP_DEV0_1_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK                                                 0x40000000L
+//RCC_EP_DEV0_1_EP_PCIE_INT_CNTL
+#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT                                                0x0
+#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT                                           0x1
+#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT                                               0x2
+#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT                                            0x3
+#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT                                                0x4
+#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT                                         0x6
+#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK                                                  0x00000001L
+#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK                                             0x00000002L
+#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK                                                 0x00000004L
+#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK                                              0x00000008L
+#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK                                                  0x00000010L
+#define RCC_EP_DEV0_1_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK                                           0x00000040L
+//RCC_EP_DEV0_1_EP_PCIE_INT_STATUS
+#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT                                          0x0
+#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT                                     0x1
+#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT                                         0x2
+#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT                                      0x3
+#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT                                          0x4
+#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT                                   0x6
+#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0__SHIFT                                0x7
+#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK                                            0x00000001L
+#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK                                       0x00000002L
+#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK                                           0x00000004L
+#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK                                        0x00000008L
+#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK                                            0x00000010L
+#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK                                     0x00000040L
+#define RCC_EP_DEV0_1_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0_MASK                                  0x00000080L
+//RCC_EP_DEV0_1_EP_PCIE_RX_CNTL2
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT                                   0x0
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK                                     0x00000001L
+//RCC_EP_DEV0_1_EP_PCIE_BUS_CNTL
+#define RCC_EP_DEV0_1_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT                                              0x7
+#define RCC_EP_DEV0_1_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK                                                0x00000080L
+//RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL
+#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT                                       0x0
+#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT                                  0x1
+#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT                                  0x2
+#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT                                  0x3
+#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT                                  0x4
+#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN6_HIDDEN_REG__SHIFT                                  0x5
+#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK                                         0x00000001L
+#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK                                    0x00000002L
+#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK                                    0x00000004L
+#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK                                    0x00000008L
+#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK                                    0x00000010L
+#define RCC_EP_DEV0_1_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN6_HIDDEN_REG_MASK                                    0x00000020L
+//RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT                                      0x0
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT                                       0x3
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT                                      0x6
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT                                     0x7
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT                                      0xa
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT                                     0xd
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT                               0xe
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT                                 0xf
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT                                            0x10
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN__SHIFT                                   0x11
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK                                        0x00000007L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK                                         0x00000038L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK                                        0x00000040L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK                                       0x00000380L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK                                        0x00001C00L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK                                       0x00002000L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK                                 0x00004000L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK                                   0x00008000L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK                                              0x00010000L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN_MASK                                     0x00020000L
+//RCC_EP_DEV0_1_EP_PCIE_STRAP_MISC
+#define RCC_EP_DEV0_1_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT                                           0x1d
+#define RCC_EP_DEV0_1_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK                                             0x20000000L
+//RCC_EP_DEV0_1_EP_PCIE_STRAP_MISC2
+#define RCC_EP_DEV0_1_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT                                         0x4
+#define RCC_EP_DEV0_1_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED_MASK                                           0x00000010L
+//RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT                                               0x8
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT                                              0xc
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT                                              0x10
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT                                              0x18
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK                                                 0x00000300L
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK                                                0x00003000L
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK                                                0x00FF0000L
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK                                                0xFF000000L
+//RCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT                       0x0
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK                         0xFFL
+//RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT                                             0x0
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT                                         0x8
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK                                               0x001FL
+#define RCC_EP_DEV0_1_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK                                           0x0100L
+//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_1_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_1_EP_PCIE_PME_CONTROL
+#define RCC_EP_DEV0_1_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT                                           0x0
+#define RCC_EP_DEV0_1_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER_MASK                                             0x1FL
+//RCC_EP_DEV0_1_EP_PCIEP_RESERVED
+#define RCC_EP_DEV0_1_EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT                                                0x0
+#define RCC_EP_DEV0_1_EP_PCIEP_RESERVED__PCIEP_RESERVED_MASK                                                  0xFFFFFFFFL
+//RCC_EP_DEV0_1_EP_PCIE_TX_CNTL
+#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT                                                 0xa
+#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT                                                  0xc
+#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT                                                   0x18
+#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT                                                   0x19
+#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT                                                   0x1a
+#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK                                                   0x00000C00L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK                                                    0x00003000L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK                                                     0x01000000L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK                                                     0x02000000L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK                                                     0x04000000L
+//RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID
+#define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT                                0x0
+#define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT                                  0x3
+#define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT                                     0x8
+#define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK                                  0x00000007L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK                                    0x000000F8L
+#define RCC_EP_DEV0_1_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK                                       0x0000FF00L
+//RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT                                              0x0
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT                                            0x8
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT                                       0x11
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT                               0x12
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT                                   0x18
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT                                   0x19
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT                                   0x1a
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED__SHIFT                                   0x1b
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED__SHIFT                                   0x1c
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED__SHIFT                                   0x1d
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED__SHIFT                                   0x1e
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED__SHIFT                                   0x1f
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK                                                0x00000001L
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK                                              0x00000700L
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK                                         0x00020000L
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK                                 0x00040000L
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK                                     0x01000000L
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK                                     0x02000000L
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK                                     0x04000000L
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED_MASK                                     0x08000000L
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED_MASK                                     0x10000000L
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED_MASK                                     0x20000000L
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED_MASK                                     0x40000000L
+#define RCC_EP_DEV0_1_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED_MASK                                     0x80000000L
+//RCC_EP_DEV0_1_EP_PCIE_RX_CNTL
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT                                       0x8
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT                                                0x9
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT                                         0x14
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT                                       0x15
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT                                         0x16
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT                                      0x18
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT                                          0x19
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT                                                      0x1a
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK                                         0x00000100L
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK                                                  0x00000200L
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK                                           0x00100000L
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK                                         0x00200000L
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK                                           0x00400000L
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK                                        0x01000000L
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK                                            0x02000000L
+#define RCC_EP_DEV0_1_EP_PCIE_RX_CNTL__RX_TPH_DIS_MASK                                                        0x04000000L
+//RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL
+#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT                                          0x0
+#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT                                          0x1
+#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT                                          0x2
+#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP__SHIFT                                          0x3
+#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN6_EN_STRAP__SHIFT                                          0x4
+#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK                                            0x00000001L
+#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK                                            0x00000002L
+#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK                                            0x00000004L
+#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP_MASK                                            0x00000008L
+#define RCC_EP_DEV0_1_EP_PCIE_LC_SPEED_CNTL__LC_GEN6_EN_STRAP_MASK                                            0x00000010L
+//RCC_EP_DEV0_1_EP_PCIE_DEVICE_CNTL3
+#define RCC_EP_DEV0_1_EP_PCIE_DEVICE_CNTL3__SHADOW_F0_DEVICE_CNTL3_14BIT_TAG_REQUESTER_ENABLE__SHIFT          0x2
+#define RCC_EP_DEV0_1_EP_PCIE_DEVICE_CNTL3__SHADOW_F0_DEVICE_CNTL3_14BIT_TAG_REQUESTER_ENABLE_MASK            0x00000004L
+
+
+// addressBlock: nbif0_nbif0_rcc_dwn_dev0_RCCPORTDEC
+//RCC_DWN_DEV0_1_DN_PCIE_RESERVED
+#define RCC_DWN_DEV0_1_DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT                                                 0x0
+#define RCC_DWN_DEV0_1_DN_PCIE_RESERVED__PCIE_RESERVED_MASK                                                   0xFFFFFFFFL
+//RCC_DWN_DEV0_1_DN_PCIE_SCRATCH
+#define RCC_DWN_DEV0_1_DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT                                                   0x0
+#define RCC_DWN_DEV0_1_DN_PCIE_SCRATCH__PCIE_SCRATCH_MASK                                                     0xFFFFFFFFL
+//RCC_DWN_DEV0_1_DN_PCIE_CNTL
+#define RCC_DWN_DEV0_1_DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT                                                    0x0
+#define RCC_DWN_DEV0_1_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT                                              0x7
+#define RCC_DWN_DEV0_1_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT                                              0x1e
+#define RCC_DWN_DEV0_1_DN_PCIE_CNTL__HWINIT_WR_LOCK_MASK                                                      0x00000001L
+#define RCC_DWN_DEV0_1_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN_MASK                                                0x00000080L
+#define RCC_DWN_DEV0_1_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK                                                0x40000000L
+//RCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL
+#define RCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT                                0x19
+#define RCC_DWN_DEV0_1_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK                                  0x06000000L
+//RCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2
+#define RCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT                                               0x1c
+#define RCC_DWN_DEV0_1_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK                                                 0x70000000L
+//RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL
+#define RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT                                             0x7
+#define RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT                                   0x8
+#define RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK                                               0x00000080L
+#define RCC_DWN_DEV0_1_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN_MASK                                     0x00000100L
+//RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL
+#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT                                      0x0
+#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT                                 0x1
+#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT                                 0x2
+#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT                                 0x3
+#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT                                 0x4
+#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN6_HIDDEN_REG__SHIFT                                 0x5
+#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK                                        0x00000001L
+#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK                                   0x00000002L
+#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK                                   0x00000004L
+#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK                                   0x00000008L
+#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK                                   0x00000010L
+#define RCC_DWN_DEV0_1_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN6_HIDDEN_REG_MASK                                   0x00000020L
+//RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0
+#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_EN__SHIFT                                                   0x0
+#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT                                                0x11
+#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__SHIFT                                        0x15
+#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_EN_MASK                                                     0x00000001L
+#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN_MASK                                                  0x00020000L
+#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP_MASK                                          0x00E00000L
+//RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC
+#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT                                             0x18
+#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT                                          0x1d
+#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK                                               0x01000000L
+#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK                                            0x20000000L
+//RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC2
+#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT                                    0x2
+#define RCC_DWN_DEV0_1_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK                                      0x00000004L
+
+
+// addressBlock: nbif0_nbif0_rcc_dwnp_dev0_RCCPORTDEC
+//RCC_DWNP_DEV0_1_PCIE_ERR_CNTL
+#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT                                               0x0
+#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT                                             0x8
+#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT                                    0xb
+#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT                                        0x11
+#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR__SHIFT                                               0x12
+#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR__SHIFT                                           0x13
+#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR__SHIFT                                              0x14
+#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK                                                 0x00000001L
+#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK                                               0x00000700L
+#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK                                      0x00000800L
+#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK                                          0x00020000L
+#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR_MASK                                                 0x00040000L
+#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR_MASK                                             0x00080000L
+#define RCC_DWNP_DEV0_1_PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR_MASK                                                0x00100000L
+//RCC_DWNP_DEV0_1_PCIE_RX_CNTL
+#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT                                        0x8
+#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT                                              0x9
+#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT                                          0x14
+#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT                                     0x15
+#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT                                           0x1b
+#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK                                          0x00000100L
+#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN_MASK                                                0x00000200L
+#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK                                            0x00100000L
+#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN_MASK                                       0x00200000L
+#define RCC_DWNP_DEV0_1_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK                                             0x08000000L
+//RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL
+#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT                                           0x0
+#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT                                           0x1
+#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT                                           0x2
+#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP__SHIFT                                           0x3
+#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN6_EN_STRAP__SHIFT                                           0x4
+#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK                                             0x00000001L
+#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK                                             0x00000002L
+#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK                                             0x00000004L
+#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP_MASK                                             0x00000008L
+#define RCC_DWNP_DEV0_1_PCIE_LC_SPEED_CNTL__LC_GEN6_EN_STRAP_MASK                                             0x00000010L
+//RCC_DWNP_DEV0_1_PCIE_LC_CNTL2
+#define RCC_DWNP_DEV0_1_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS__SHIFT                               0x0
+#define RCC_DWNP_DEV0_1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT                                     0x1b
+#define RCC_DWNP_DEV0_1_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS_MASK                                 0x00000001L
+#define RCC_DWNP_DEV0_1_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK                                       0x08000000L
+//RCC_DWNP_DEV0_1_PCIEP_STRAP_MISC
+#define RCC_DWNP_DEV0_1_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN__SHIFT                                          0xa
+#define RCC_DWNP_DEV0_1_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN_MASK                                            0x00000400L
+//RCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP
+#define RCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT                                     0x0
+#define RCC_DWNP_DEV0_1_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP_MASK                                       0xFFFFFFFFL
+
+
+// addressBlock: nbif0_nbif0_rcc_pfc_amdgfx_RCCPFCDEC
+//RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL
+#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE__SHIFT                                           0x0
+#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE__SHIFT                                           0xa
+#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT__SHIFT                                             0xf
+#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE__SHIFT                                        0x10
+#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE__SHIFT                                        0x1a
+#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT__SHIFT                                          0x1f
+#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_VALUE_MASK                                             0x000003FFL
+#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_LATENCY_SCALE_MASK                                             0x00001C00L
+#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__SNOOP_REQUIREMENT_MASK                                               0x00008000L
+#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_VALUE_MASK                                          0x03FF0000L
+#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_LATENCY_SCALE_MASK                                          0x1C000000L
+#define RCC_PFC_AMDGFX_RCC_PFC_LTR_CNTL__NONSNOOP_REQUIREMENT_MASK                                            0x80000000L
+//RCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE
+#define RCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN__SHIFT                                         0x0
+#define RCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS__SHIFT                                     0x8
+#define RCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE__PME_SENT_FLAG__SHIFT                                              0x9
+#define RCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_EN_MASK                                           0x00000001L
+#define RCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE__PME_RESTORE_PME_STATUS_MASK                                       0x00000100L
+#define RCC_PFC_AMDGFX_RCC_PFC_PME_RESTORE__PME_SENT_FLAG_MASK                                                0x00000200L
+//RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS__SHIFT                                0x0
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS__SHIFT                            0x1
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS__SHIFT                          0x2
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS__SHIFT                              0x3
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS__SHIFT                                0x4
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS__SHIFT                               0x5
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS__SHIFT                         0x6
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS__SHIFT                  0x7
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_PSN_ERR_STATUS_MASK                                  0x00000001L
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_TIMEOUT_STATUS_MASK                              0x00000002L
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_CPL_ABORT_ERR_STATUS_MASK                            0x00000004L
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNEXP_CPL_STATUS_MASK                                0x00000008L
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_MAL_TLP_STATUS_MASK                                  0x00000010L
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_ECRC_ERR_STATUS_MASK                                 0x00000020L
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_UNSUPP_REQ_ERR_STATUS_MASK                           0x00000040L
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_0__RESTORE_ADVISORY_NONFATAL_ERR_STATUS_MASK                    0x00000080L
+//RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_1
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0__SHIFT                                     0x0
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_1__RESTORE_TLP_HDR_0_MASK                                       0xFFFFFFFFL
+//RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_2
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1__SHIFT                                     0x0
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_2__RESTORE_TLP_HDR_1_MASK                                       0xFFFFFFFFL
+//RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_3
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2__SHIFT                                     0x0
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_3__RESTORE_TLP_HDR_2_MASK                                       0xFFFFFFFFL
+//RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_4
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3__SHIFT                                     0x0
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_4__RESTORE_TLP_HDR_3_MASK                                       0xFFFFFFFFL
+//RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_5
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX__SHIFT                                    0x0
+#define RCC_PFC_AMDGFX_RCC_PFC_STICKY_RESTORE_5__RESTORE_TLP_PREFIX_MASK                                      0xFFFFFFFFL
+//RCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL
+#define RCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE__SHIFT                                       0x0
+#define RCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE__SHIFT                                0x3
+#define RCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL__AUX_CURRENT_OVERRIDE_MASK                                         0x00000007L
+#define RCC_PFC_AMDGFX_RCC_PFC_AUXPWR_CNTL__AUX_POWER_DETECTED_OVERRIDE_MASK                                  0x00000008L
+//RCC_PFC_AMDGFX_RCC_PFC_MISC_CNTL
+#define RCC_PFC_AMDGFX_RCC_PFC_MISC_CNTL__BURST_EN__SHIFT                                                     0x0
+#define RCC_PFC_AMDGFX_RCC_PFC_MISC_CNTL__BURST_EN_MASK                                                       0x00000007L
+//RCC_PFC_AMDGFX_RCC_NFC
+#define RCC_PFC_AMDGFX_RCC_NFC__NFC_PFV__SHIFT                                                                0x0
+#define RCC_PFC_AMDGFX_RCC_NFC__NFC_PFV_MASK                                                                  0x00000001L
+
+
+// addressBlock: nbif0_nbif0_rcc_shadow_reg_shadowdec
+//SHADOW_COMMAND
+#define SHADOW_COMMAND__IOEN_UP__SHIFT                                                                        0x0
+#define SHADOW_COMMAND__MEMEN_UP__SHIFT                                                                       0x1
+#define SHADOW_COMMAND__IOEN_UP_MASK                                                                          0x0001L
+#define SHADOW_COMMAND__MEMEN_UP_MASK                                                                         0x0002L
+//SHADOW_BASE_ADDR_1
+#define SHADOW_BASE_ADDR_1__BAR1_UP__SHIFT                                                                    0x0
+#define SHADOW_BASE_ADDR_1__BAR1_UP_MASK                                                                      0xFFFFFFFFL
+//SHADOW_BASE_ADDR_2
+#define SHADOW_BASE_ADDR_2__BAR2_UP__SHIFT                                                                    0x0
+#define SHADOW_BASE_ADDR_2__BAR2_UP_MASK                                                                      0xFFFFFFFFL
+//SHADOW_SUB_BUS_NUMBER_LATENCY
+#define SHADOW_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_UP__SHIFT                                                0x8
+#define SHADOW_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_UP__SHIFT                                                  0x10
+#define SHADOW_SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_UP_MASK                                                  0x0000FF00L
+#define SHADOW_SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_UP_MASK                                                    0x00FF0000L
+//SHADOW_IO_BASE_LIMIT
+#define SHADOW_IO_BASE_LIMIT__IO_BASE_UP__SHIFT                                                               0x4
+#define SHADOW_IO_BASE_LIMIT__IO_LIMIT_UP__SHIFT                                                              0xc
+#define SHADOW_IO_BASE_LIMIT__IO_BASE_UP_MASK                                                                 0x00F0L
+#define SHADOW_IO_BASE_LIMIT__IO_LIMIT_UP_MASK                                                                0xF000L
+//SHADOW_MEM_BASE_LIMIT
+#define SHADOW_MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT                                                           0x0
+#define SHADOW_MEM_BASE_LIMIT__MEM_BASE_31_20_UP__SHIFT                                                       0x4
+#define SHADOW_MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT                                                          0x10
+#define SHADOW_MEM_BASE_LIMIT__MEM_LIMIT_31_20_UP__SHIFT                                                      0x14
+#define SHADOW_MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK                                                             0x0000000FL
+#define SHADOW_MEM_BASE_LIMIT__MEM_BASE_31_20_UP_MASK                                                         0x0000FFF0L
+#define SHADOW_MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK                                                            0x000F0000L
+#define SHADOW_MEM_BASE_LIMIT__MEM_LIMIT_31_20_UP_MASK                                                        0xFFF00000L
+//SHADOW_PREF_BASE_LIMIT
+#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT                                                     0x0
+#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_UP__SHIFT                                                 0x4
+#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT                                                    0x10
+#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_UP__SHIFT                                                0x14
+#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK                                                       0x0000000FL
+#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_UP_MASK                                                   0x0000FFF0L
+#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK                                                      0x000F0000L
+#define SHADOW_PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_UP_MASK                                                  0xFFF00000L
+//SHADOW_PREF_BASE_UPPER
+#define SHADOW_PREF_BASE_UPPER__PREF_BASE_UPPER_UP__SHIFT                                                     0x0
+#define SHADOW_PREF_BASE_UPPER__PREF_BASE_UPPER_UP_MASK                                                       0xFFFFFFFFL
+//SHADOW_PREF_LIMIT_UPPER
+#define SHADOW_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_UP__SHIFT                                                   0x0
+#define SHADOW_PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_UP_MASK                                                     0xFFFFFFFFL
+//SHADOW_IO_BASE_LIMIT_HI
+#define SHADOW_IO_BASE_LIMIT_HI__IO_BASE_31_16_UP__SHIFT                                                      0x0
+#define SHADOW_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_UP__SHIFT                                                     0x10
+#define SHADOW_IO_BASE_LIMIT_HI__IO_BASE_31_16_UP_MASK                                                        0x0000FFFFL
+#define SHADOW_IO_BASE_LIMIT_HI__IO_LIMIT_31_16_UP_MASK                                                       0xFFFF0000L
+//SHADOW_IRQ_BRIDGE_CNTL
+#define SHADOW_IRQ_BRIDGE_CNTL__ISA_EN_UP__SHIFT                                                              0x2
+#define SHADOW_IRQ_BRIDGE_CNTL__VGA_EN_UP__SHIFT                                                              0x3
+#define SHADOW_IRQ_BRIDGE_CNTL__VGA_DEC_UP__SHIFT                                                             0x4
+#define SHADOW_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_UP__SHIFT                                                 0x6
+#define SHADOW_IRQ_BRIDGE_CNTL__ISA_EN_UP_MASK                                                                0x0004L
+#define SHADOW_IRQ_BRIDGE_CNTL__VGA_EN_UP_MASK                                                                0x0008L
+#define SHADOW_IRQ_BRIDGE_CNTL__VGA_DEC_UP_MASK                                                               0x0010L
+#define SHADOW_IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_UP_MASK                                                   0x0040L
+//SUC_INDEX
+#define SUC_INDEX__SUC_INDEX__SHIFT                                                                           0x0
+#define SUC_INDEX__SUC_INDEX_MASK                                                                             0xFFFFFFFFL
+//SUC_DATA
+#define SUC_DATA__SUC_DATA__SHIFT                                                                             0x0
+#define SUC_DATA__SUC_DATA_MASK                                                                               0xFFFFFFFFL
+
+
+// addressBlock: nbif0_nbif0_bif_swus_SUMDEC
+//SUM_INDEX
+#define SUM_INDEX__SUM_INDEX__SHIFT                                                                           0x0
+#define SUM_INDEX__SUM_INDEX_MASK                                                                             0xFFFFFFFFL
+//SUM_DATA
+#define SUM_DATA__SUM_DATA__SHIFT                                                                             0x0
+#define SUM_DATA__SUM_DATA_MASK                                                                               0xFFFFFFFFL
+//SUM_INDEX_HI
+#define SUM_INDEX_HI__SUM_INDEX_HI__SHIFT                                                                     0x0
+#define SUM_INDEX_HI__SUM_INDEX_HI_MASK                                                                       0x0000FFFFL
+
+
+// addressBlock: nbif0_nbif0_rcc_strap_rcc_strap_internal
+//RCC_STRAP1_RCC_DEV0_PORT_STRAP0
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0__SHIFT                                       0x0
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0__SHIFT                                          0x10
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0__SHIFT                                          0x11
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0__SHIFT                                          0x12
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0__SHIFT                                0x13
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_NEGO_GLOBAL_EN_DEV0__SHIFT                                     0x14
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0__SHIFT                                   0x15
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0__SHIFT                            0x18
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0__SHIFT                             0x19
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0__SHIFT                             0x1c
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0__SHIFT                                      0x1f
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0_MASK                                         0x0000FFFFL
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0_MASK                                            0x00010000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0_MASK                                            0x00020000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0_MASK                                            0x00040000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0_MASK                                  0x00080000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_NEGO_GLOBAL_EN_DEV0_MASK                                       0x00100000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0_MASK                                     0x00E00000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0_MASK                              0x01000000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0_MASK                               0x0E000000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0_MASK                               0x70000000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0_MASK                                        0x80000000L
+//RCC_STRAP1_RCC_DEV0_PORT_STRAP1
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0__SHIFT                                       0x0
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0__SHIFT                                   0x10
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0_MASK                                         0x0000FFFFL
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0_MASK                                     0xFFFF0000L
+//RCC_STRAP1_RCC_DEV0_PORT_STRAP2
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0__SHIFT                                 0x0
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0__SHIFT                                          0x1
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0__SHIFT                                      0x2
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0__SHIFT                                          0x3
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0__SHIFT                                      0x4
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0__SHIFT                                        0x5
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0__SHIFT                             0x7
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0__SHIFT                                0x8
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0__SHIFT                                    0x9
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0__SHIFT                              0xc
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0__SHIFT                      0xd
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0__SHIFT                                    0xe
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0__SHIFT                                            0xf
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0__SHIFT                                    0x10
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0__SHIFT                                    0x11
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0__SHIFT                             0x14
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0__SHIFT                                   0x17
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0__SHIFT                              0x1a
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0__SHIFT                                    0x1d
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0_MASK                                   0x00000001L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0_MASK                                            0x00000002L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0_MASK                                        0x00000004L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0_MASK                                            0x00000008L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0_MASK                                        0x00000010L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0_MASK                                          0x00000020L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0_MASK                               0x00000080L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0_MASK                                  0x00000100L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0_MASK                                      0x00000E00L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0_MASK                                0x00001000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0_MASK                        0x00002000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0_MASK                                      0x00004000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0_MASK                                              0x00008000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0_MASK                                      0x00010000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0_MASK                                      0x00020000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0_MASK                               0x00700000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0_MASK                                     0x03800000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0_MASK                                0x1C000000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0_MASK                                      0xE0000000L
+//RCC_STRAP1_RCC_DEV0_PORT_STRAP3
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0__SHIFT                     0x0
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0__SHIFT                                             0x1
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0__SHIFT                                          0x2
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0__SHIFT                                0x3
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0__SHIFT                                          0x6
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0__SHIFT                                  0x7
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0__SHIFT                                   0x8
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0__SHIFT                                     0x9
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT  0xb
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0__SHIFT  0xe
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT  0x12
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0__SHIFT  0x15
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0__SHIFT                                         0x19
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0__SHIFT                                      0x1b
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0__SHIFT                                       0x1d
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0__SHIFT                                         0x1f
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0_MASK                       0x00000001L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0_MASK                                               0x00000002L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0_MASK                                            0x00000004L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0_MASK                                  0x00000038L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0_MASK                                            0x00000040L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0_MASK                                    0x00000080L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0_MASK                                     0x00000100L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0_MASK                                       0x00000600L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK  0x00003800L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0_MASK  0x0003C000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK  0x001C0000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0_MASK  0x01E00000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0_MASK                                           0x06000000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0_MASK                                        0x18000000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0_MASK                                         0x20000000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0_MASK                                           0x80000000L
+//RCC_STRAP1_RCC_DEV0_PORT_STRAP4
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0__SHIFT                              0x0
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0__SHIFT                              0x8
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0__SHIFT                              0x10
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0__SHIFT                              0x18
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0_MASK                                0x000000FFL
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0_MASK                                0x0000FF00L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0_MASK                                0x00FF0000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0_MASK                                0xFF000000L
+//RCC_STRAP1_RCC_DEV0_PORT_STRAP5
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0__SHIFT                              0x0
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0__SHIFT                              0x8
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0__SHIFT                        0x10
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0__SHIFT                                 0x11
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0__SHIFT                                  0x12
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0__SHIFT                                           0x13
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0__SHIFT                                           0x14
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0__SHIFT                                        0x15
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0__SHIFT                                0x16
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0__SHIFT                           0x17
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0__SHIFT                        0x18
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0__SHIFT                        0x19
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0__SHIFT                     0x1a
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0__SHIFT                         0x1b
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0__SHIFT                          0x1c
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0__SHIFT                       0x1d
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV0__SHIFT                                         0x1e
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0__SHIFT                                            0x1f
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0_MASK                                0x000000FFL
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0_MASK                                0x0000FF00L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0_MASK                          0x00010000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0_MASK                                   0x00020000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0_MASK                                    0x00040000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0_MASK                                             0x00080000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0_MASK                                             0x00100000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0_MASK                                          0x00200000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0_MASK                                  0x00400000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0_MASK                             0x00800000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0_MASK                          0x01000000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0_MASK                          0x02000000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0_MASK                       0x04000000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0_MASK                           0x08000000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0_MASK                            0x10000000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0_MASK                         0x20000000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV0_MASK                                           0x40000000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0_MASK                                              0x80000000L
+//RCC_STRAP1_RCC_DEV0_PORT_STRAP6
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0__SHIFT                                         0x0
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0__SHIFT                         0x1
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV0__SHIFT                                    0x2
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0__SHIFT                          0x3
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0__SHIFT                          0x4
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0__SHIFT                      0x5
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT                      0x6
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT                   0x7
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0__SHIFT     0x8
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0__SHIFT     0xc
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0__SHIFT                              0x10
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV0__SHIFT                            0x12
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV0__SHIFT                     0x13
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_GEN5_COMPLIANCE_DEV0__SHIFT                                    0x14
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_TARGET_LINK_SPEED_DEV0__SHIFT                                  0x15
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0__SHIFT     0x18
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0__SHIFT     0x1c
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0_MASK                                           0x00000001L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0_MASK                           0x00000002L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV0_MASK                                      0x00000004L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0_MASK                            0x00000008L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0_MASK                            0x00000010L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0_MASK                        0x00000020L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK                        0x00000040L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK                     0x00000080L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0_MASK       0x00000F00L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0_MASK       0x0000F000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0_MASK                                0x00030000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV0_MASK                              0x00040000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV0_MASK                       0x00080000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_GEN5_COMPLIANCE_DEV0_MASK                                      0x00100000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_TARGET_LINK_SPEED_DEV0_MASK                                    0x00E00000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0_MASK       0x0F000000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0_MASK       0xF0000000L
+//RCC_STRAP1_RCC_DEV0_PORT_STRAP7
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0__SHIFT                                        0x0
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0__SHIFT                                    0x8
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0__SHIFT                                    0xc
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0__SHIFT                                          0x10
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0__SHIFT                                          0x18
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0__SHIFT                                          0x1d
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0_MASK                                          0x000000FFL
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0_MASK                                      0x00000F00L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0_MASK                                      0x0000F000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0_MASK                                            0x00FF0000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0_MASK                                            0x1F000000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0_MASK                                            0xE0000000L
+//RCC_STRAP1_RCC_DEV0_PORT_STRAP8
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0__SHIFT                              0x0
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0__SHIFT                              0x8
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0__SHIFT                              0x10
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0__SHIFT                              0x18
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0_MASK                                0x000000FFL
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0_MASK                                0x0000FF00L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0_MASK                                0x00FF0000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0_MASK                                0xFF000000L
+//RCC_STRAP1_RCC_DEV0_PORT_STRAP9
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0__SHIFT                              0x0
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0__SHIFT                              0x8
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV0__SHIFT                                       0x10
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0_MASK                                0x000000FFL
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0_MASK                                0x0000FF00L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV0_MASK                                         0xFFFF0000L
+//RCC_STRAP1_RCC_DEV0_PORT_STRAP10
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DEV0__SHIFT                              0x0
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DN_DEV0__SHIFT                           0x1
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE1_SUPPORTED_DEV0__SHIFT                  0x2
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE2_SUPPORTED_DEV0__SHIFT                  0x3
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODEING_ON_DEV0__SHIFT                         0x4
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODE_REQUEST_DEV0__SHIFT                       0x5
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_MODIFIED_TS_INFOR1_DEV0__SHIFT                                0x6
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_GEN6_COMPLIANCE_DEV0__SHIFT                                   0x14
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_MAX_E2E_TLP_PREFIXES_DEV0__SHIFT                              0x18
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_MAX_E2E_TLP_PREFIXES_DN_DEV0__SHIFT                           0x1a
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DEV0_MASK                                0x00000001L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DN_DEV0_MASK                             0x00000002L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE1_SUPPORTED_DEV0_MASK                    0x00000004L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE2_SUPPORTED_DEV0_MASK                    0x00000008L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODEING_ON_DEV0_MASK                           0x00000010L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODE_REQUEST_DEV0_MASK                         0x00000020L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_MODIFIED_TS_INFOR1_DEV0_MASK                                  0x0007FFC0L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_GEN6_COMPLIANCE_DEV0_MASK                                     0x00100000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_MAX_E2E_TLP_PREFIXES_DEV0_MASK                                0x03000000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP10__STRAP_MAX_E2E_TLP_PREFIXES_DN_DEV0_MASK                             0x0C000000L
+//RCC_STRAP1_RCC_DEV0_PORT_STRAP11
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_MODIFIED_TS_VENDOR_ID_DEV0__SHIFT                             0x0
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_RTR_RESET_TIME_DN_DEV0__SHIFT                                 0x10
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_RTR_VALID_DN_DEV0__SHIFT                                      0x1c
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_RTR_EN_DN_DEV0__SHIFT                                         0x1d
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_SDPVW_REG_UPDATE_EN_DEV0__SHIFT                               0x1e
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_VF_14BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT                  0x1f
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_MODIFIED_TS_VENDOR_ID_DEV0_MASK                               0x0000FFFFL
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_RTR_RESET_TIME_DN_DEV0_MASK                                   0x0FFF0000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_RTR_VALID_DN_DEV0_MASK                                        0x10000000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_RTR_EN_DN_DEV0_MASK                                           0x20000000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_SDPVW_REG_UPDATE_EN_DEV0_MASK                                 0x40000000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP11__STRAP_VF_14BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK                    0x80000000L
+//RCC_STRAP1_RCC_DEV0_PORT_STRAP12
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP12__STRAP_MODIFIED_TS_INFOR2_DEV0__SHIFT                                0x0
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP12__STRAP_14BIT_TAG_COMPLETER_SUPPORTED_DEV0__SHIFT                     0x18
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP12__STRAP_14BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT                     0x19
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP12__STRAP_RECEIVER_L0P_SUPPORTED_DEV0__SHIFT                            0x1a
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP12__STRAP_PORT_L0P_EXIT_LATENCY_DEV0__SHIFT                             0x1b
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP12__STRAP_MODIFIED_TS_INFOR2_DEV0_MASK                                  0x00FFFFFFL
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP12__STRAP_14BIT_TAG_COMPLETER_SUPPORTED_DEV0_MASK                       0x01000000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP12__STRAP_14BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK                       0x02000000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP12__STRAP_RECEIVER_L0P_SUPPORTED_DEV0_MASK                              0x04000000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP12__STRAP_PORT_L0P_EXIT_LATENCY_DEV0_MASK                               0x38000000L
+//RCC_STRAP1_RCC_DEV0_PORT_STRAP13
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_COUNT_DEV0__SHIFT                          0x0
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_SELECTIVE_ENABLE_SUPPORTED_DEV0__SHIFT     0x8
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_DETAILS_DEV0__SHIFT                        0x9
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP13__STRAP_RTR_D3HOTD0_TIME_DN_DEV0__SHIFT                               0x14
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_COUNT_DEV0_MASK                            0x000000FFL
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_SELECTIVE_ENABLE_SUPPORTED_DEV0_MASK       0x00000100L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_DETAILS_DEV0_MASK                          0x000FFE00L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP13__STRAP_RTR_D3HOTD0_TIME_DN_DEV0_MASK                                 0xFFF00000L
+//RCC_STRAP1_RCC_DEV0_PORT_STRAP14
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_CTO_LOGGING_SUPPORT_DEV0__SHIFT                               0x0
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_ACS_ENH_CAPABILITY_DN_DEV0__SHIFT                             0x1
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_COMMAND_COMPLETED_DEV0__SHIFT                                 0x2
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_ERR_COR_SUBCLASS_CAPABLE_DEV0__SHIFT                          0x3
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_DOE_EN_UP_DEV0__SHIFT                                         0x4
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_RX_MPS_FIXED_DEV0__SHIFT                                      0x5
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_RX_MPS_FIXED_DN_DEV0__SHIFT                                   0x6
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_IDE_EN_DEV0__SHIFT                                            0x7
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_RETIMER_L0P_EXIT_LATENCY_DEV0__SHIFT                          0x9
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_DEVICE3_EN_DN_DEV0__SHIFT                                     0xc
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_IDE_EN_DN_DEV0__SHIFT                                         0xd
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_CTO_LOGGING_SUPPORT_DEV0_MASK                                 0x00000001L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_ACS_ENH_CAPABILITY_DN_DEV0_MASK                               0x00000002L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_COMMAND_COMPLETED_DEV0_MASK                                   0x00000004L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_ERR_COR_SUBCLASS_CAPABLE_DEV0_MASK                            0x00000008L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_DOE_EN_UP_DEV0_MASK                                           0x00000010L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_RX_MPS_FIXED_DEV0_MASK                                        0x00000020L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_RX_MPS_FIXED_DN_DEV0_MASK                                     0x00000040L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_IDE_EN_DEV0_MASK                                              0x00000080L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_RETIMER_L0P_EXIT_LATENCY_DEV0_MASK                            0x00000E00L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_DEVICE3_EN_DN_DEV0_MASK                                       0x00001000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP14__STRAP_IDE_EN_DN_DEV0_MASK                                           0x00002000L
+//RCC_STRAP1_RCC_DEV0_PORT_STRAP15
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP15__STRAP_DSN_CODE_L_DN_DEV0__SHIFT                                     0x0
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP15__STRAP_DSN_CODE_L_DN_DEV0_MASK                                       0xFFFFFFFFL
+//RCC_STRAP1_RCC_DEV0_PORT_STRAP16
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP16__STRAP_DSN_CODE_H_DN_DEV0__SHIFT                                     0x0
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP16__STRAP_DSN_CODE_H_DN_DEV0_MASK                                       0xFFFFFFFFL
+//RCC_STRAP1_RCC_DEV0_PORT_STRAP17
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP17__STRAP_LINK_IDE_STREAM_SUPPORTED_DEV0__SHIFT                         0x0
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP17__STRAP_SELECTIVE_IDE_STREAM_SUPPORTED_DEV0__SHIFT                    0x1
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP17__STRAP_FLOW_THROUGH_IDE_STREAM_SUPPORTED_DEV0__SHIFT                 0x2
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP17__STRAP_PARTIAL_HDR_ENCRYPTION_SUPPORTED_DEV0__SHIFT                  0x3
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP17__STRAP_AGGREGATION_SUPPORTED_DEV0__SHIFT                             0x4
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP17__STRAP_PCRC_SUPPORTED_DEV0__SHIFT                                    0x5
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP17__STRAP_IDE_KM_PROTOCOL_SUPPORTED_DEV0__SHIFT                         0x6
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP17__STRAP_SELECTIVE_IDE_FOR_CFG_REQ_SUPPORTED_DEV0__SHIFT               0x7
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP17__STRAP_NUM_OF_TCS_SUPPORTED_FOR_LINK_IDE_DEV0__SHIFT                 0xd
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP17__STRAP_NUM_OF_SELECTIVE_IDE_STREAMS_SUPPORTED_DEV0__SHIFT            0x10
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP17__STRAP_TEE_LIMITED_SUPPORTED_DEV0__SHIFT                             0x18
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP17__STRAP_XT_SUPPORTED_DEV0__SHIFT                                      0x19
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP17__STRAP_LINK_IDE_STREAM_SUPPORTED_DEV0_MASK                           0x00000001L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP17__STRAP_SELECTIVE_IDE_STREAM_SUPPORTED_DEV0_MASK                      0x00000002L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP17__STRAP_FLOW_THROUGH_IDE_STREAM_SUPPORTED_DEV0_MASK                   0x00000004L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP17__STRAP_PARTIAL_HDR_ENCRYPTION_SUPPORTED_DEV0_MASK                    0x00000008L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP17__STRAP_AGGREGATION_SUPPORTED_DEV0_MASK                               0x00000010L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP17__STRAP_PCRC_SUPPORTED_DEV0_MASK                                      0x00000020L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP17__STRAP_IDE_KM_PROTOCOL_SUPPORTED_DEV0_MASK                           0x00000040L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP17__STRAP_SELECTIVE_IDE_FOR_CFG_REQ_SUPPORTED_DEV0_MASK                 0x00000080L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP17__STRAP_NUM_OF_TCS_SUPPORTED_FOR_LINK_IDE_DEV0_MASK                   0x0000E000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP17__STRAP_NUM_OF_SELECTIVE_IDE_STREAMS_SUPPORTED_DEV0_MASK              0x00FF0000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP17__STRAP_TEE_LIMITED_SUPPORTED_DEV0_MASK                               0x01000000L
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP17__STRAP_XT_SUPPORTED_DEV0_MASK                                        0x02000000L
+//RCC_STRAP1_RCC_DEV0_PORT_STRAP18
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP18__STRAP_NUM_ADDR_ASSOCIATION_REG_BLKS_DEV0__SHIFT                     0x0
+#define RCC_STRAP1_RCC_DEV0_PORT_STRAP18__STRAP_NUM_ADDR_ASSOCIATION_REG_BLKS_DEV0_MASK                       0x0000000FL
+//RCC_DEV1_PORT_STRAP0
+//RCC_DEV1_PORT_STRAP1
+//RCC_DEV1_PORT_STRAP2
+//RCC_DEV1_PORT_STRAP3
+//RCC_DEV1_PORT_STRAP4
+//RCC_DEV1_PORT_STRAP5
+//RCC_DEV1_PORT_STRAP6
+//RCC_DEV1_PORT_STRAP7
+//RCC_DEV1_PORT_STRAP8
+//RCC_DEV1_PORT_STRAP9
+//RCC_DEV1_PORT_STRAP10
+//RCC_DEV1_PORT_STRAP11
+//RCC_DEV1_PORT_STRAP12
+//RCC_DEV1_PORT_STRAP13
+//RCC_DEV1_PORT_STRAP14
+//RCC_DEV1_PORT_STRAP15
+//RCC_DEV1_PORT_STRAP16
+//RCC_DEV2_PORT_STRAP0
+//RCC_DEV2_PORT_STRAP1
+//RCC_DEV2_PORT_STRAP2
+//RCC_DEV2_PORT_STRAP3
+//RCC_DEV2_PORT_STRAP4
+//RCC_DEV2_PORT_STRAP5
+//RCC_DEV2_PORT_STRAP6
+//RCC_DEV2_PORT_STRAP7
+//RCC_DEV2_PORT_STRAP8
+//RCC_DEV2_PORT_STRAP9
+//RCC_DEV2_PORT_STRAP10
+//RCC_DEV2_PORT_STRAP11
+//RCC_DEV2_PORT_STRAP12
+//RCC_DEV2_PORT_STRAP13
+//RCC_DEV2_PORT_STRAP14
+//RCC_DEV2_PORT_STRAP15
+//RCC_DEV2_PORT_STRAP16
+//RCC_STRAP1_RCC_BIF_STRAP0
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_GEN4_DIS__SHIFT                                                      0x0
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_EXPANSION_ROM_VALIDATION_SUPPORT__SHIFT                              0x1
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_PX_CAPABLE__SHIFT                                                    0x7
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3__SHIFT                                                 0x8
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN__SHIFT                                  0x9
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR__SHIFT                                         0xa
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN__SHIFT                                     0xb
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR__SHIFT                                              0xc
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR__SHIFT                                             0xd
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_AUD_PIN__SHIFT                                                       0x12
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN__SHIFT                                               0x14
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIF_GFX_IOBAR_DIS_AND_REGBAR_64BIT_EN__SHIFT                         0x15
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_GPUIOV_EN__SHIFT                                                     0x16
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_OVERRIDE__SHIFT                                          0x17
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_GEN3_DIS__SHIFT                                                      0x18
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4__SHIFT                                                 0x19
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_QUICKSIM_START__SHIFT                                                0x1a
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING__SHIFT                                     0x1b
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_IGNORE_LOCAL_PREFIX_UR_SWUS__SHIFT                                   0x1c
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN__SHIFT                                      0x1d
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE__SHIFT                                                   0x1e
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN__SHIFT                                            0x1f
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_GEN4_DIS_MASK                                                        0x00000001L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_EXPANSION_ROM_VALIDATION_SUPPORT_MASK                                0x00000002L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK                                                      0x00000080L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3_MASK                                                   0x00000100L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN_MASK                                    0x00000200L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR_MASK                                           0x00000400L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN_MASK                                       0x00000800L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR_MASK                                                0x00001000L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR_MASK                                               0x00002000L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_AUD_PIN_MASK                                                         0x000C0000L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN_MASK                                                 0x00100000L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIF_GFX_IOBAR_DIS_AND_REGBAR_64BIT_EN_MASK                           0x00200000L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_GPUIOV_EN_MASK                                                       0x00400000L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_OVERRIDE_MASK                                            0x00800000L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_GEN3_DIS_MASK                                                        0x01000000L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4_MASK                                                   0x02000000L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_QUICKSIM_START_MASK                                                  0x04000000L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING_MASK                                       0x08000000L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_IGNORE_LOCAL_PREFIX_UR_SWUS_MASK                                     0x10000000L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN_MASK                                        0x20000000L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE_MASK                                                     0x40000000L
+#define RCC_STRAP1_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN_MASK                                              0x80000000L
+//RCC_STRAP1_RCC_BIF_STRAP1
+#define RCC_STRAP1_RCC_BIF_STRAP1__FUSESTRAP_VALID__SHIFT                                                     0x0
+#define RCC_STRAP1_RCC_BIF_STRAP1__ROMSTRAP_VALID__SHIFT                                                      0x1
+#define RCC_STRAP1_RCC_BIF_STRAP1__WRITE_DISABLE__SHIFT                                                       0x2
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN__SHIFT                                      0x3
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_FLIT_MODE_SUPPORT__SHIFT                                             0x4
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS__SHIFT                                     0x5
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE__SHIFT                                       0x6
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGINING_READY__SHIFT                                               0x7
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN__SHIFT                                                  0x8
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN__SHIFT                                                 0x9
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE__SHIFT                                                  0xa
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE__SHIFT                                        0xc
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_HWREV_LSB2__SHIFT                                                    0xd
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWREV_LSB2__SHIFT                                                    0xf
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY__SHIFT                                             0x11
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS__SHIFT                                             0x12
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_DLF_EN__SHIFT                                                        0x13
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_PHY_16GT_EN__SHIFT                                                   0x14
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGIN_EN__SHIFT                                                     0x15
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN__SHIFT                                             0x16
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN__SHIFT                                     0x17
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE__SHIFT                                             0x1a
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_GSI_SMN_POSTWR_MULTI_EN__SHIFT                                       0x1b
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_DLF_EN_EP__SHIFT                                                     0x1d
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_AP_EN__SHIFT                                                         0x1e
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_AP_EN_DN__SHIFT                                                      0x1f
+#define RCC_STRAP1_RCC_BIF_STRAP1__FUSESTRAP_VALID_MASK                                                       0x00000001L
+#define RCC_STRAP1_RCC_BIF_STRAP1__ROMSTRAP_VALID_MASK                                                        0x00000002L
+#define RCC_STRAP1_RCC_BIF_STRAP1__WRITE_DISABLE_MASK                                                         0x00000004L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN_MASK                                        0x00000008L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_FLIT_MODE_SUPPORT_MASK                                               0x00000010L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS_MASK                                       0x00000020L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE_MASK                                         0x00000040L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGINING_READY_MASK                                                 0x00000080L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN_MASK                                                    0x00000100L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN_MASK                                                   0x00000200L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE_MASK                                                    0x00000C00L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE_MASK                                          0x00001000L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_HWREV_LSB2_MASK                                                      0x00006000L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_SWREV_LSB2_MASK                                                      0x00018000L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY_MASK                                               0x00020000L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS_MASK                                               0x00040000L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_DLF_EN_MASK                                                          0x00080000L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_PHY_16GT_EN_MASK                                                     0x00100000L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_MARGIN_EN_MASK                                                       0x00200000L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN_MASK                                               0x00400000L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN_MASK                                       0x00800000L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE_MASK                                               0x04000000L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_GSI_SMN_POSTWR_MULTI_EN_MASK                                         0x18000000L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_DLF_EN_EP_MASK                                                       0x20000000L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_AP_EN_MASK                                                           0x40000000L
+#define RCC_STRAP1_RCC_BIF_STRAP1__STRAP_AP_EN_DN_MASK                                                        0x80000000L
+//RCC_STRAP1_RCC_BIF_STRAP2
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE__SHIFT                                     0x0
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SWUS_SPT__SHIFT                                                      0x1
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SWDS_SPT__SHIFT                                                      0x2
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS__SHIFT                                            0x3
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS__SHIFT                                            0x4
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA__SHIFT                                        0x5
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA__SHIFT                                      0x6
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS__SHIFT                                 0x8
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS__SHIFT                                        0x9
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN__SHIFT                                   0xa
+#define RCC_STRAP1_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2__SHIFT                                                 0xd
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS__SHIFT                                             0xe
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN__SHIFT                                 0xf
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE__SHIFT                                         0x10
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS__SHIFT                                        0x18
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_ARI_EN_UP__SHIFT                                                     0x19
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_VLINK_PMETO_LDN_EXIT_BY_LNKRST_DIS__SHIFT                            0x1f
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE_MASK                                       0x00000001L
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SWUS_SPT_MASK                                                        0x00000002L
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SWDS_SPT_MASK                                                        0x00000004L
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS_MASK                                              0x00000008L
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS_MASK                                              0x00000010L
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA_MASK                                          0x00000020L
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA_MASK                                        0x00000040L
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS_MASK                                   0x00000100L
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS_MASK                                          0x00000200L
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN_MASK                                     0x00000C00L
+#define RCC_STRAP1_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2_MASK                                                   0x00002000L
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK                                               0x00004000L
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN_MASK                                   0x00008000L
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE_MASK                                           0x00FF0000L
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS_MASK                                          0x01000000L
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_ARI_EN_UP_MASK                                                       0x02000000L
+#define RCC_STRAP1_RCC_BIF_STRAP2__STRAP_VLINK_PMETO_LDN_EXIT_BY_LNKRST_DIS_MASK                              0x80000000L
+//RCC_STRAP1_RCC_BIF_STRAP3
+#define RCC_STRAP1_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT                                         0x0
+#define RCC_STRAP1_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT                                       0x10
+#define RCC_STRAP1_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK                                           0x0000FFFFL
+#define RCC_STRAP1_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK                                         0xFFFF0000L
+//RCC_STRAP1_RCC_BIF_STRAP4
+#define RCC_STRAP1_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER__SHIFT                                          0x0
+#define RCC_STRAP1_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER__SHIFT                                           0x10
+#define RCC_STRAP1_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER_MASK                                            0x0000FFFFL
+#define RCC_STRAP1_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER_MASK                                             0xFFFF0000L
+//RCC_STRAP1_RCC_BIF_STRAP5
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT                                         0x0
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN__SHIFT                                      0x10
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN__SHIFT                                   0x11
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS__SHIFT                                    0x12
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS__SHIFT                                        0x13
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS__SHIFT                                    0x14
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_REG_PROTECTION_DIS__SHIFT                                            0x15
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE__SHIFT                                         0x16
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE__SHIFT                          0x18
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                0x19
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                 0x1b
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER__SHIFT                                           0x1c
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_BIF_GFX_REG_APER_REMAPPING_EN__SHIFT                                 0x1f
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK                                           0x0000FFFFL
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN_MASK                                        0x00010000L
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN_MASK                                     0x00020000L
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS_MASK                                      0x00040000L
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS_MASK                                          0x00080000L
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS_MASK                                      0x00100000L
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_REG_PROTECTION_DIS_MASK                                              0x00200000L
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE_MASK                                           0x00C00000L
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE_MASK                            0x01000000L
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED_MASK                                  0x06000000L
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ_MASK                                   0x08000000L
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER_MASK                                             0x70000000L
+#define RCC_STRAP1_RCC_BIF_STRAP5__STRAP_BIF_GFX_REG_APER_REMAPPING_EN_MASK                                   0x80000000L
+//RCC_STRAP1_RCC_BIF_STRAP6
+#define RCC_STRAP1_RCC_BIF_STRAP6__STRAP_GEN5_DIS__SHIFT                                                      0x0
+#define RCC_STRAP1_RCC_BIF_STRAP6__STRAP_BIF_KILL_GEN5__SHIFT                                                 0x1
+#define RCC_STRAP1_RCC_BIF_STRAP6__STRAP_PHY_32GT_EN__SHIFT                                                   0x2
+#define RCC_STRAP1_RCC_BIF_STRAP6__STRAP_DOE_VERSION_SEL__SHIFT                                               0x3
+#define RCC_STRAP1_RCC_BIF_STRAP6__STRAP_PRODUCTION_MODE__SHIFT                                               0x5
+#define RCC_STRAP1_RCC_BIF_STRAP6__STRAP_MEM_AP_SIZE_PIN__SHIFT                                               0xa
+#define RCC_STRAP1_RCC_BIF_STRAP6__RESERVED_BIF_STRAP6__SHIFT                                                 0xf
+#define RCC_STRAP1_RCC_BIF_STRAP6__STRAP_GEN5_DIS_MASK                                                        0x00000001L
+#define RCC_STRAP1_RCC_BIF_STRAP6__STRAP_BIF_KILL_GEN5_MASK                                                   0x00000002L
+#define RCC_STRAP1_RCC_BIF_STRAP6__STRAP_PHY_32GT_EN_MASK                                                     0x00000004L
+#define RCC_STRAP1_RCC_BIF_STRAP6__STRAP_DOE_VERSION_SEL_MASK                                                 0x00000008L
+#define RCC_STRAP1_RCC_BIF_STRAP6__STRAP_PRODUCTION_MODE_MASK                                                 0x00000020L
+#define RCC_STRAP1_RCC_BIF_STRAP6__STRAP_MEM_AP_SIZE_PIN_MASK                                                 0x00007C00L
+#define RCC_STRAP1_RCC_BIF_STRAP6__RESERVED_BIF_STRAP6_MASK                                                   0xFFFF8000L
+//RCC_STRAP1_RCC_BIF_STRAP7
+#define RCC_STRAP1_RCC_BIF_STRAP7__STRAP_GEN6_DIS__SHIFT                                                      0x19
+#define RCC_STRAP1_RCC_BIF_STRAP7__STRAP_BIF_KILL_GEN6__SHIFT                                                 0x1a
+#define RCC_STRAP1_RCC_BIF_STRAP7__STRAP_GEN6_DIS_MASK                                                        0x02000000L
+#define RCC_STRAP1_RCC_BIF_STRAP7__STRAP_BIF_KILL_GEN6_MASK                                                   0x04000000L
+//RCC_STRAP1_RCC_BIF_STRAP8
+//RCC_STRAP1_RCC_BIF_STRAP9
+//RCC_STRAP1_RCC_BIF_STRAP10
+//RCC_STRAP1_RCC_BIF_STRAP11
+//RCC_STRAP1_RCC_BIF_STRAP12
+//RCC_STRAP1_RCC_BIF_STRAP13
+#define RCC_STRAP1_RCC_BIF_STRAP13__STRAP_PCIE_SMN_APER__SHIFT                                                0x0
+#define RCC_STRAP1_RCC_BIF_STRAP13__STRAP_PCIE_SMN_APER_MASK                                                  0x00000FFFL
+//RCC_STRAP1_RCC_DEV0_EPF0_STRAP0
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT                                       0x0
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT                                    0x10
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__SHIFT                                    0x14
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT                                      0x18
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__SHIFT                                         0x1c
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__SHIFT                           0x1d
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__SHIFT                                      0x1e
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__SHIFT                                      0x1f
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0_MASK                                         0x0000FFFFL
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0_MASK                                      0x000F0000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0_MASK                                      0x00F00000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK                                        0x0F000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0_MASK                                           0x10000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0_MASK                             0x20000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0_MASK                                        0x40000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0_MASK                                        0x80000000L
+//RCC_STRAP1_RCC_DEV0_EPF0_STRAP1
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0__SHIFT                              0x0
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0__SHIFT                       0x10
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0_MASK                                0x0000FFFFL
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0_MASK                         0xFFFF0000L
+//RCC_STRAP1_RCC_DEV0_EPF0_STRAP2
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0__SHIFT                                        0x0
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_RELAXED_ORDERING_SUPPORTED_DEV0_F0__SHIFT                      0x1
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_CAP_HIERARCHY_PRESERVED_DEV0_F0__SHIFT                     0x2
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_DEVICE3_EN_DEV0_F0__SHIFT                                      0x3
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_TEE_EXCLUSIVE_ATTR_SUPPORTED_DEV0_F0__SHIFT                    0x4
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0__SHIFT                                       0x6
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0__SHIFT                                   0x7
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0__SHIFT                                   0x8
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0__SHIFT                                 0x9
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0__SHIFT                          0xe
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0__SHIFT                                          0xf
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0__SHIFT                                          0x10
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0__SHIFT                                          0x11
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0__SHIFT                                          0x12
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0__SHIFT                                0x14
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0__SHIFT                                          0x15
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0__SHIFT                                          0x16
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0__SHIFT                                           0x17
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0__SHIFT                                   0x18
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0__SHIFT                                     0x1b
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0__SHIFT                                        0x1c
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0__SHIFT                  0x1d
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0__SHIFT               0x1e
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0__SHIFT                       0x1f
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0_MASK                                          0x00000001L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_RELAXED_ORDERING_SUPPORTED_DEV0_F0_MASK                        0x00000002L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_CAP_HIERARCHY_PRESERVED_DEV0_F0_MASK                       0x00000004L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_DEVICE3_EN_DEV0_F0_MASK                                        0x00000008L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_TEE_EXCLUSIVE_ATTR_SUPPORTED_DEV0_F0_MASK                      0x00000010L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0_MASK                                         0x00000040L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0_MASK                                     0x00000080L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0_MASK                                     0x00000100L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0_MASK                                   0x00003E00L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0_MASK                            0x00004000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0_MASK                                            0x00008000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0_MASK                                            0x00010000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0_MASK                                            0x00020000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0_MASK                                            0x00040000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0_MASK                                  0x00100000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0_MASK                                            0x00200000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0_MASK                                            0x00400000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0_MASK                                             0x00800000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0_MASK                                     0x07000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0_MASK                                       0x08000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0_MASK                                          0x10000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0_MASK                    0x20000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0_MASK                 0x40000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0_MASK                         0x80000000L
+//RCC_STRAP1_RCC_DEV0_EPF0_STRAP3
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0__SHIFT                                       0x0
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0__SHIFT                      0x10
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0__SHIFT                                          0x11
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0__SHIFT                                          0x12
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0__SHIFT                              0x13
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0__SHIFT                                         0x14
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0__SHIFT                                  0x15
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0__SHIFT                                         0x18
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_TRANSLATED_REQ_WITH_PASID_SUPPORTED_DEV0_F0__SHIFT             0x19
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0__SHIFT                        0x1a
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0__SHIFT                       0x1b
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0__SHIFT                                0x1c
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV0_F0__SHIFT                                       0x1d
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F0__SHIFT                               0x1e
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_RTR_EN_DEV0_F0__SHIFT                                          0x1f
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0_MASK                                         0x0000FFFFL
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0_MASK                        0x00010000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0_MASK                                            0x00020000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0_MASK                                            0x00040000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0_MASK                                0x00080000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0_MASK                                           0x00100000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0_MASK                                    0x00E00000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0_MASK                                           0x01000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_TRANSLATED_REQ_WITH_PASID_SUPPORTED_DEV0_F0_MASK               0x02000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0_MASK                          0x04000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0_MASK                         0x08000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0_MASK                                  0x10000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV0_F0_MASK                                         0x20000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F0_MASK                                 0x40000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP3__STRAP_RTR_EN_DEV0_F0_MASK                                            0x80000000L
+//RCC_STRAP1_RCC_DEV0_EPF0_STRAP4
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0__SHIFT                                 0x0
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_DOE_EN_DEV0_F0__SHIFT                                          0x12
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0__SHIFT                                 0x14
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0__SHIFT                                       0x15
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0__SHIFT                                          0x16
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0__SHIFT                                     0x17
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0__SHIFT                                   0x1c
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F0__SHIFT                                  0x1f
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0_MASK                                   0x000003FFL
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_DOE_EN_DEV0_F0_MASK                                            0x00040000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0_MASK                                   0x00100000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0_MASK                                         0x00200000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0_MASK                                            0x00400000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0_MASK                                       0x0F800000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0_MASK                                     0x70000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F0_MASK                                    0x80000000L
+//RCC_STRAP1_RCC_DEV0_EPF0_STRAP5
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0__SHIFT                                   0x0
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP5__STRAP_AUX_CURRENT_DEV0_F0__SHIFT                                     0x1b
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F0__SHIFT                            0x1e
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0_MASK                                     0x0000FFFFL
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP5__STRAP_AUX_CURRENT_DEV0_F0_MASK                                       0x38000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F0_MASK                              0x40000000L
+//RCC_STRAP1_RCC_DEV0_EPF0_STRAP8
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0__SHIFT                              0x0
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0__SHIFT                                0x3
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0__SHIFT                                     0x4
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0__SHIFT                                      0x7
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0__SHIFT                                   0x8
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0__SHIFT                                     0xd
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0__SHIFT                           0x10
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0__SHIFT                                  0x17
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0__SHIFT                                0x1b
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0__SHIFT                           0x1e
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0_MASK                                0x00000007L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0_MASK                                  0x00000008L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0_MASK                                       0x00000070L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0_MASK                                        0x00000080L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0_MASK                                     0x00000100L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0_MASK                                       0x0000E000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0_MASK                             0x00070000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0_MASK                                    0x03800000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0_MASK                                  0x38000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0_MASK                             0xC0000000L
+//RCC_STRAP1_RCC_DEV0_EPF0_STRAP9
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0__SHIFT                           0x0
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0__SHIFT                               0x12
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0__SHIFT                        0x13
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0__SHIFT                                 0x14
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_FB_ALWAYS_ON_DEV0_F0__SHIFT                                    0x15
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_FB_CPL_TYPE_SEL_DEV0_F0__SHIFT                                 0x16
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_GPUIOV_VSEC_REV_DEV0_F0__SHIFT                                 0x18
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_TEE_IO_SUPPORT_DEV0_F0__SHIFT                                  0x1c
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0_MASK                             0x0000FFFFL
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0_MASK                                 0x00040000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0_MASK                          0x00080000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0_MASK                                   0x00100000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_FB_ALWAYS_ON_DEV0_F0_MASK                                      0x00200000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_FB_CPL_TYPE_SEL_DEV0_F0_MASK                                   0x00C00000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_GPUIOV_VSEC_REV_DEV0_F0_MASK                                   0x0F000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP9__STRAP_TEE_IO_SUPPORT_DEV0_F0_MASK                                    0x10000000L
+//RCC_STRAP1_RCC_DEV0_EPF0_STRAP13
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0__SHIFT                                 0x0
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0__SHIFT                                 0x8
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0__SHIFT                                0x10
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_SRIOV_TOTAL_VFS_DEV0_F0__SHIFT                                0x18
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0_MASK                                   0x000000FFL
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0_MASK                                   0x0000FF00L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0_MASK                                  0x00FF0000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP13__STRAP_SRIOV_TOTAL_VFS_DEV0_F0_MASK                                  0xFF000000L
+//RCC_STRAP1_RCC_DEV0_EPF0_STRAP14
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP14__STRAP_VENDOR_ID_DEV0_F0__SHIFT                                      0x0
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP14__STRAP_VENDOR_ID_DEV0_F0_MASK                                        0x0000FFFFL
+//RCC_STRAP1_RCC_DEV0_EPF0_STRAP15
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F0__SHIFT                                 0x0
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F0__SHIFT                                  0xc
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_VALID_DEV0_F0__SHIFT                                      0x18
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_INVALIDATE_QUEUE_DEPTH_DEV0_F0__SHIFT                     0x19
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_PAGE_ALIGNED_REQUEST_DEV0_F0__SHIFT                       0x1e
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F0_MASK                                   0x00000FFFL
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F0_MASK                                    0x00FFF000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_VALID_DEV0_F0_MASK                                        0x01000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_INVALIDATE_QUEUE_DEPTH_DEV0_F0_MASK                       0x3E000000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_PAGE_ALIGNED_REQUEST_DEV0_F0_MASK                         0x40000000L
+//RCC_STRAP1_RCC_DEV0_EPF0_STRAP16
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F0__SHIFT                                   0x0
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F0__SHIFT                               0xc
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F0_MASK                                     0x00000FFFL
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F0_MASK                                 0x00FFF000L
+//RCC_STRAP1_RCC_DEV0_EPF0_STRAP17
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F0__SHIFT                              0x0
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_VALID_DEV0_F0__SHIFT                                   0xc
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F0__SHIFT                                0xd
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F0_MASK                                0x00000FFFL
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_VALID_DEV0_F0_MASK                                     0x00001000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F0_MASK                                  0x01FFE000L
+//RCC_STRAP1_RCC_DEV0_EPF0_STRAP18
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F0__SHIFT                            0x0
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP18__STRAP_SRIOV_FUNC_DEP_LINK_DEV0_F0__SHIFT                            0xc
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F0_MASK                              0x00000FFFL
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP18__STRAP_SRIOV_FUNC_DEP_LINK_DEV0_F0_MASK                              0x000FF000L
+//RCC_STRAP1_RCC_DEV0_EPF0_STRAP19
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP19__STRAP_SRIOV_FIRST_VF_OFFSET_DEV0_F0__SHIFT                          0x0
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP19__STRAP_SRIOV_VF_STRIDE_DEV0_F0__SHIFT                                0x10
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP19__STRAP_SRIOV_FIRST_VF_OFFSET_DEV0_F0_MASK                            0x0000FFFFL
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP19__STRAP_SRIOV_VF_STRIDE_DEV0_F0_MASK                                  0xFFFF0000L
+//RCC_STRAP1_RCC_DEV0_EPF0_STRAP22
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP22__STRAP_GPUIOV_VSEC_LENGTH_DEV0_F0__SHIFT                             0x0
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP22__STRAP_MEM_AP_SIZE_DEV0_F0__SHIFT                                    0xc
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP22__STRAP_VF_MEM_AP_SIZE_DEV0_F0__SHIFT                                 0x11
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP22__STRAP_PF_RESIZABLE_BAR_DEFAULT_SIZE_DEV0_F0__SHIFT                  0x16
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP22__STRAP_VF_RESIZABLE_BAR_DEFAULT_SIZE_DEV0_F0__SHIFT                  0x1b
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP22__STRAP_GPUIOV_VSEC_LENGTH_DEV0_F0_MASK                               0x00000FFFL
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP22__STRAP_MEM_AP_SIZE_DEV0_F0_MASK                                      0x0001F000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP22__STRAP_VF_MEM_AP_SIZE_DEV0_F0_MASK                                   0x003E0000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP22__STRAP_PF_RESIZABLE_BAR_DEFAULT_SIZE_DEV0_F0_MASK                    0x07C00000L
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP22__STRAP_VF_RESIZABLE_BAR_DEFAULT_SIZE_DEV0_F0_MASK                    0xF8000000L
+//RCC_STRAP1_RCC_DEV0_EPF0_STRAP23
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP23__STRAP_DSN_CODE_L_DEV0_F0__SHIFT                                     0x0
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP23__STRAP_DSN_CODE_L_DEV0_F0_MASK                                       0xFFFFFFFFL
+//RCC_STRAP1_RCC_DEV0_EPF0_STRAP24
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP24__STRAP_DSN_CODE_H_DEV0_F0__SHIFT                                     0x0
+#define RCC_STRAP1_RCC_DEV0_EPF0_STRAP24__STRAP_DSN_CODE_H_DEV0_F0_MASK                                       0xFFFFFFFFL
+//RCC_STRAP1_RCC_DEV0_EPF1_STRAP0
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1__SHIFT                                       0x0
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1__SHIFT                                    0x10
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1__SHIFT                                    0x14
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1__SHIFT                                         0x1c
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1__SHIFT                           0x1d
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1__SHIFT                                      0x1e
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1__SHIFT                                      0x1f
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1_MASK                                         0x0000FFFFL
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1_MASK                                      0x000F0000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1_MASK                                      0x00F00000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1_MASK                                           0x10000000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1_MASK                             0x20000000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1_MASK                                        0x40000000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1_MASK                                        0x80000000L
+//RCC_STRAP1_RCC_DEV0_EPF1_STRAP1
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F1__SHIFT                              0x0
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F1__SHIFT                       0x10
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F1_MASK                                0x0000FFFFL
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F1_MASK                         0xFFFF0000L
+//RCC_STRAP1_RCC_DEV0_EPF1_STRAP2
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_SRIOV_EN_DEV0_F1__SHIFT                                        0x0
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_ARI_CAP_HIERARCHY_PRESERVED_DEV0_F1__SHIFT                     0x2
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_DEVICE3_EN_DEV0_F1__SHIFT                                      0x3
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_TEE_EXCLUSIVE_ATTR_SUPPORTED_DEV0_F1__SHIFT                    0x4
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1__SHIFT                                   0x7
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1__SHIFT                                   0x8
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1__SHIFT                                 0x9
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1__SHIFT                          0xe
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1__SHIFT                                          0x10
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1__SHIFT                                          0x11
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1__SHIFT                                0x14
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1__SHIFT                                          0x15
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1__SHIFT                                   0x18
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F1__SHIFT                                     0x1b
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1__SHIFT                                        0x1c
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1__SHIFT                  0x1d
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1__SHIFT               0x1e
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1__SHIFT                       0x1f
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_SRIOV_EN_DEV0_F1_MASK                                          0x00000001L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_ARI_CAP_HIERARCHY_PRESERVED_DEV0_F1_MASK                       0x00000004L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_DEVICE3_EN_DEV0_F1_MASK                                        0x00000008L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_TEE_EXCLUSIVE_ATTR_SUPPORTED_DEV0_F1_MASK                      0x00000010L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1_MASK                                     0x00000080L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1_MASK                                     0x00000100L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1_MASK                                   0x00003E00L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1_MASK                            0x00004000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1_MASK                                            0x00010000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1_MASK                                            0x00020000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1_MASK                                  0x00100000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1_MASK                                            0x00200000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1_MASK                                     0x07000000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F1_MASK                                       0x08000000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1_MASK                                          0x10000000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1_MASK                    0x20000000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1_MASK                 0x40000000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1_MASK                         0x80000000L
+//RCC_STRAP1_RCC_DEV0_EPF1_STRAP3
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1__SHIFT                                       0x0
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1__SHIFT                      0x10
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1__SHIFT                                          0x11
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1__SHIFT                                          0x12
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1__SHIFT                              0x13
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1__SHIFT                                         0x14
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1__SHIFT                                         0x18
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_TRANSLATED_REQ_WITH_PASID_SUPPORTED_DEV0_F1__SHIFT             0x19
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1__SHIFT                        0x1a
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1__SHIFT                       0x1b
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F1__SHIFT                                0x1c
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV0_F1__SHIFT                                       0x1d
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F1__SHIFT                               0x1e
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_RTR_EN_DEV0_F1__SHIFT                                          0x1f
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1_MASK                                         0x0000FFFFL
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1_MASK                        0x00010000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1_MASK                                            0x00020000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1_MASK                                            0x00040000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1_MASK                                0x00080000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1_MASK                                           0x00100000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1_MASK                                           0x01000000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_TRANSLATED_REQ_WITH_PASID_SUPPORTED_DEV0_F1_MASK               0x02000000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1_MASK                          0x04000000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1_MASK                         0x08000000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F1_MASK                                  0x10000000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV0_F1_MASK                                         0x20000000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F1_MASK                                 0x40000000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP3__STRAP_RTR_EN_DEV0_F1_MASK                                            0x80000000L
+//RCC_STRAP1_RCC_DEV0_EPF1_STRAP4
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1__SHIFT                                 0x14
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1__SHIFT                                       0x15
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1__SHIFT                                          0x16
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1__SHIFT                                     0x17
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1__SHIFT                                   0x1c
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1__SHIFT                                  0x1f
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1_MASK                                   0x00100000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1_MASK                                         0x00200000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1_MASK                                            0x00400000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1_MASK                                       0x0F800000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1_MASK                                     0x70000000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1_MASK                                    0x80000000L
+//RCC_STRAP1_RCC_DEV0_EPF1_STRAP5
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1__SHIFT                                   0x0
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP5__STRAP_AUX_CURRENT_DEV0_F1__SHIFT                                     0x1b
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F1__SHIFT                            0x1e
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1_MASK                                     0x0000FFFFL
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP5__STRAP_AUX_CURRENT_DEV0_F1_MASK                                       0x38000000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F1_MASK                              0x40000000L
+//RCC_STRAP1_RCC_DEV0_EPF1_STRAP6
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1__SHIFT                                        0x0
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F1__SHIFT                           0x1
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1__SHIFT                                  0x2
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_EN_DEV0_F1__SHIFT                                        0x8
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F1__SHIFT                           0x9
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_64BAR_EN_DEV0_F1__SHIFT                                  0xa
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_EN_DEV0_F1__SHIFT                                        0x10
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F1__SHIFT                           0x11
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_64BAR_EN_DEV0_F1__SHIFT                                  0x12
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER3_EN_DEV0_F1__SHIFT                                        0x18
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV0_F1__SHIFT                           0x19
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER4_EN_DEV0_F1__SHIFT                                        0x1a
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER4_PREFETCHABLE_EN_DEV0_F1__SHIFT                           0x1b
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1_MASK                                          0x00000001L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F1_MASK                             0x00000002L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1_MASK                                    0x00000004L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_EN_DEV0_F1_MASK                                          0x00000100L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F1_MASK                             0x00000200L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_64BAR_EN_DEV0_F1_MASK                                    0x00000400L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_EN_DEV0_F1_MASK                                          0x00010000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F1_MASK                             0x00020000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_64BAR_EN_DEV0_F1_MASK                                    0x00040000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER3_EN_DEV0_F1_MASK                                          0x01000000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV0_F1_MASK                             0x02000000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER4_EN_DEV0_F1_MASK                                          0x04000000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP6__STRAP_APER4_PREFETCHABLE_EN_DEV0_F1_MASK                             0x08000000L
+//RCC_STRAP1_RCC_DEV0_EPF1_STRAP7
+//RCC_STRAP1_RCC_DEV0_EPF1_STRAP8
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F1__SHIFT                                0x1b
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F1__SHIFT                           0x1e
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F1_MASK                                  0x38000000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F1_MASK                             0xC0000000L
+//RCC_STRAP1_RCC_DEV0_EPF1_STRAP9
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F1__SHIFT                           0x0
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP9__STRAP_TEE_IO_SUPPORT_DEV0_F1__SHIFT                                  0x1c
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F1_MASK                             0x0000FFFFL
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP9__STRAP_TEE_IO_SUPPORT_DEV0_F1_MASK                                    0x10000000L
+//RCC_STRAP1_RCC_DEV0_EPF1_STRAP10
+//RCC_STRAP1_RCC_DEV0_EPF1_STRAP11
+//RCC_STRAP1_RCC_DEV0_EPF1_STRAP12
+//RCC_STRAP1_RCC_DEV0_EPF1_STRAP13
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F1__SHIFT                                 0x0
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F1__SHIFT                                 0x8
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F1__SHIFT                                0x10
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP13__STRAP_SRIOV_TOTAL_VFS_DEV0_F1__SHIFT                                0x18
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F1_MASK                                   0x000000FFL
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F1_MASK                                   0x0000FF00L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F1_MASK                                  0x00FF0000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP13__STRAP_SRIOV_TOTAL_VFS_DEV0_F1_MASK                                  0xFF000000L
+//RCC_STRAP1_RCC_DEV0_EPF1_STRAP14
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP14__STRAP_VENDOR_ID_DEV0_F1__SHIFT                                      0x0
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP14__STRAP_VENDOR_ID_DEV0_F1_MASK                                        0x0000FFFFL
+//RCC_STRAP1_RCC_DEV0_EPF1_STRAP15
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F1__SHIFT                                 0x0
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F1__SHIFT                                  0xc
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP15__STRAP_RTR_VALID_DEV0_F1__SHIFT                                      0x18
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F1_MASK                                   0x00000FFFL
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F1_MASK                                    0x00FFF000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP15__STRAP_RTR_VALID_DEV0_F1_MASK                                        0x01000000L
+//RCC_STRAP1_RCC_DEV0_EPF1_STRAP16
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F1__SHIFT                                   0x0
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F1__SHIFT                               0xc
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F1_MASK                                     0x00000FFFL
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F1_MASK                                 0x00FFF000L
+//RCC_STRAP1_RCC_DEV0_EPF1_STRAP17
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F1__SHIFT                              0x0
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP17__STRAP_RTR_VF_VALID_DEV0_F1__SHIFT                                   0xc
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F1__SHIFT                                0xd
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F1_MASK                                0x00000FFFL
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP17__STRAP_RTR_VF_VALID_DEV0_F1_MASK                                     0x00001000L
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F1_MASK                                  0x01FFE000L
+//RCC_STRAP1_RCC_DEV0_EPF1_STRAP18
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F1__SHIFT                            0x0
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP18__STRAP_SRIOV_FUNC_DEP_LINK_DEV0_F1__SHIFT                            0xc
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F1_MASK                              0x00000FFFL
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP18__STRAP_SRIOV_FUNC_DEP_LINK_DEV0_F1_MASK                              0x000FF000L
+//RCC_STRAP1_RCC_DEV0_EPF1_STRAP19
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP19__STRAP_SRIOV_FIRST_VF_OFFSET_DEV0_F1__SHIFT                          0x0
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP19__STRAP_SRIOV_VF_STRIDE_DEV0_F1__SHIFT                                0x10
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP19__STRAP_SRIOV_FIRST_VF_OFFSET_DEV0_F1_MASK                            0x0000FFFFL
+#define RCC_STRAP1_RCC_DEV0_EPF1_STRAP19__STRAP_SRIOV_VF_STRIDE_DEV0_F1_MASK                                  0xFFFF0000L
+//RCC_STRAP1_RCC_DEV0_EPF1_STRAP20
+//RCC_STRAP1_RCC_DEV0_EPF1_STRAP21
+//RCC_STRAP1_RCC_DEV0_EPF1_STRAP23
+//RCC_STRAP1_RCC_DEV0_EPF1_STRAP24
+//RCC_DEV0_EPF2_STRAP0
+//RCC_DEV0_EPF2_STRAP2
+//RCC_DEV0_EPF2_STRAP3
+//RCC_DEV0_EPF2_STRAP4
+//RCC_DEV0_EPF2_STRAP5
+//RCC_DEV0_EPF2_STRAP6
+//RCC_DEV0_EPF2_STRAP7
+//RCC_DEV0_EPF2_STRAP9
+//RCC_DEV0_EPF2_STRAP10
+//RCC_DEV0_EPF2_STRAP11
+//RCC_DEV0_EPF2_STRAP12
+//RCC_DEV0_EPF2_STRAP13
+//RCC_DEV0_EPF2_STRAP14
+//RCC_DEV0_EPF2_STRAP15
+//RCC_DEV0_EPF2_STRAP16
+//RCC_DEV0_EPF2_STRAP20
+//RCC_DEV0_EPF3_STRAP0
+//RCC_DEV0_EPF3_STRAP2
+//RCC_DEV0_EPF3_STRAP3
+//RCC_DEV0_EPF3_STRAP4
+//RCC_DEV0_EPF3_STRAP5
+//RCC_DEV0_EPF3_STRAP6
+//RCC_DEV0_EPF3_STRAP7
+//RCC_DEV0_EPF3_STRAP9
+//RCC_DEV0_EPF3_STRAP10
+//RCC_DEV0_EPF3_STRAP11
+//RCC_DEV0_EPF3_STRAP12
+//RCC_DEV0_EPF3_STRAP13
+//RCC_DEV0_EPF3_STRAP14
+//RCC_DEV0_EPF3_STRAP15
+//RCC_DEV0_EPF3_STRAP16
+//RCC_DEV0_EPF3_STRAP20
+//RCC_DEV0_EPF4_STRAP0
+//RCC_DEV0_EPF4_STRAP2
+//RCC_DEV0_EPF4_STRAP3
+//RCC_DEV0_EPF4_STRAP4
+//RCC_DEV0_EPF4_STRAP5
+//RCC_DEV0_EPF4_STRAP6
+//RCC_DEV0_EPF4_STRAP7
+//RCC_DEV0_EPF4_STRAP9
+//RCC_DEV0_EPF4_STRAP13
+//RCC_DEV0_EPF4_STRAP14
+//RCC_DEV0_EPF4_STRAP15
+//RCC_DEV0_EPF4_STRAP16
+//RCC_DEV0_EPF5_STRAP0
+//RCC_DEV0_EPF5_STRAP2
+//RCC_DEV0_EPF5_STRAP3
+//RCC_DEV0_EPF5_STRAP4
+//RCC_DEV0_EPF5_STRAP5
+//RCC_DEV0_EPF5_STRAP6
+//RCC_DEV0_EPF5_STRAP7
+//RCC_DEV0_EPF5_STRAP9
+//RCC_DEV0_EPF5_STRAP13
+//RCC_DEV0_EPF5_STRAP14
+//RCC_DEV0_EPF5_STRAP15
+//RCC_DEV0_EPF5_STRAP16
+//RCC_DEV0_EPF6_STRAP0
+//RCC_DEV0_EPF6_STRAP2
+//RCC_DEV0_EPF6_STRAP3
+//RCC_DEV0_EPF6_STRAP4
+//RCC_DEV0_EPF6_STRAP5
+//RCC_DEV0_EPF6_STRAP6
+//RCC_DEV0_EPF6_STRAP7
+//RCC_DEV0_EPF6_STRAP9
+//RCC_DEV0_EPF6_STRAP13
+//RCC_DEV0_EPF6_STRAP14
+//RCC_DEV0_EPF6_STRAP15
+//RCC_DEV0_EPF6_STRAP16
+//RCC_DEV0_EPF7_STRAP0
+//RCC_DEV0_EPF7_STRAP2
+//RCC_DEV0_EPF7_STRAP3
+//RCC_DEV0_EPF7_STRAP4
+//RCC_DEV0_EPF7_STRAP5
+//RCC_DEV0_EPF7_STRAP6
+//RCC_DEV0_EPF7_STRAP9
+//RCC_DEV0_EPF7_STRAP13
+//RCC_DEV0_EPF7_STRAP14
+//RCC_DEV0_EPF7_STRAP15
+//RCC_DEV0_EPF7_STRAP16
+//RCC_DEV1_EPF0_STRAP0
+//RCC_DEV1_EPF0_STRAP2
+//RCC_DEV1_EPF0_STRAP3
+//RCC_DEV1_EPF0_STRAP4
+//RCC_DEV1_EPF0_STRAP5
+//RCC_DEV1_EPF0_STRAP6
+//RCC_DEV1_EPF0_STRAP9
+//RCC_DEV1_EPF0_STRAP13
+//RCC_DEV1_EPF0_STRAP14
+//RCC_DEV1_EPF0_STRAP15
+//RCC_DEV1_EPF0_STRAP16
+//RCC_DEV1_EPF1_STRAP0
+//RCC_DEV1_EPF1_STRAP1
+//RCC_DEV1_EPF1_STRAP2
+//RCC_DEV1_EPF1_STRAP3
+//RCC_DEV1_EPF1_STRAP4
+//RCC_DEV1_EPF1_STRAP5
+//RCC_DEV1_EPF1_STRAP6
+//RCC_DEV1_EPF1_STRAP7
+//RCC_DEV1_EPF1_STRAP8
+//RCC_DEV1_EPF1_STRAP9
+//RCC_DEV1_EPF1_STRAP13
+//RCC_DEV1_EPF1_STRAP14
+//RCC_DEV1_EPF1_STRAP15
+//RCC_DEV1_EPF1_STRAP16
+//RCC_DEV1_EPF1_STRAP17
+//RCC_DEV1_EPF1_STRAP18
+//RCC_DEV1_EPF1_STRAP19
+//RCC_DEV1_EPF1_STRAP20
+//RCC_DEV1_EPF1_STRAP21
+//RCC_DEV1_EPF2_STRAP0
+//RCC_DEV1_EPF2_STRAP1
+//RCC_DEV1_EPF2_STRAP2
+//RCC_DEV1_EPF2_STRAP3
+//RCC_DEV1_EPF2_STRAP4
+//RCC_DEV1_EPF2_STRAP5
+//RCC_DEV1_EPF2_STRAP6
+//RCC_DEV1_EPF2_STRAP7
+//RCC_DEV1_EPF2_STRAP8
+//RCC_DEV1_EPF2_STRAP9
+//RCC_DEV1_EPF2_STRAP13
+//RCC_DEV1_EPF2_STRAP14
+//RCC_DEV1_EPF2_STRAP15
+//RCC_DEV1_EPF2_STRAP16
+//RCC_DEV1_EPF2_STRAP17
+//RCC_DEV1_EPF2_STRAP18
+//RCC_DEV1_EPF2_STRAP19
+//RCC_DEV1_EPF2_STRAP20
+//RCC_DEV1_EPF2_STRAP21
+//RCC_DEV1_EPF3_STRAP0
+//RCC_DEV1_EPF3_STRAP2
+//RCC_DEV1_EPF3_STRAP3
+//RCC_DEV1_EPF3_STRAP4
+//RCC_DEV1_EPF3_STRAP5
+//RCC_DEV1_EPF3_STRAP6
+//RCC_DEV1_EPF3_STRAP7
+//RCC_DEV1_EPF3_STRAP13
+//RCC_DEV1_EPF3_STRAP14
+//RCC_DEV1_EPF3_STRAP15
+//RCC_DEV1_EPF3_STRAP16
+//RCC_DEV1_EPF4_STRAP6
+//RCC_DEV1_EPF5_STRAP6
+//RCC_DEV1_EPF6_STRAP6
+//RCC_DEV2_EPF0_STRAP0
+//RCC_DEV2_EPF0_STRAP2
+//RCC_DEV2_EPF0_STRAP3
+//RCC_DEV2_EPF0_STRAP4
+//RCC_DEV2_EPF0_STRAP5
+//RCC_DEV2_EPF0_STRAP6
+//RCC_DEV2_EPF0_STRAP7
+//RCC_DEV2_EPF0_STRAP13
+//RCC_DEV2_EPF0_STRAP14
+//RCC_DEV2_EPF0_STRAP15
+//RCC_DEV2_EPF0_STRAP16
+//RCC_DEV2_EPF0_STRAP18
+//RCC_DEV2_EPF0_STRAP25
+//RCC_DEV2_EPF0_STRAP26
+//RCC_DEV2_EPF1_STRAP0
+//RCC_DEV2_EPF1_STRAP2
+//RCC_DEV2_EPF1_STRAP3
+//RCC_DEV2_EPF1_STRAP4
+//RCC_DEV2_EPF1_STRAP5
+//RCC_DEV2_EPF1_STRAP6
+//RCC_DEV2_EPF1_STRAP7
+//RCC_DEV2_EPF1_STRAP13
+//RCC_DEV2_EPF1_STRAP14
+//RCC_DEV2_EPF1_STRAP15
+//RCC_DEV2_EPF1_STRAP16
+//RCC_DEV2_EPF2_STRAP0
+//RCC_DEV2_EPF2_STRAP2
+//RCC_DEV2_EPF2_STRAP3
+//RCC_DEV2_EPF2_STRAP4
+//RCC_DEV2_EPF2_STRAP5
+//RCC_DEV2_EPF2_STRAP6
+//RCC_DEV2_EPF2_STRAP7
+//RCC_DEV2_EPF2_STRAP13
+//RCC_DEV2_EPF2_STRAP14
+//RCC_DEV2_EPF2_STRAP15
+//RCC_DEV2_EPF2_STRAP16
+//RCC_DEV2_EPF3_STRAP0
+//RCC_DEV2_EPF3_STRAP2
+//RCC_DEV2_EPF3_STRAP3
+//RCC_DEV2_EPF3_STRAP4
+//RCC_DEV2_EPF3_STRAP5
+//RCC_DEV2_EPF3_STRAP6
+//RCC_DEV2_EPF3_STRAP7
+//RCC_DEV2_EPF3_STRAP13
+//RCC_DEV2_EPF3_STRAP14
+//RCC_DEV2_EPF3_STRAP15
+//RCC_DEV2_EPF3_STRAP16
+//RCC_DEV2_EPF4_STRAP0
+//RCC_DEV2_EPF4_STRAP2
+//RCC_DEV2_EPF4_STRAP3
+//RCC_DEV2_EPF4_STRAP4
+//RCC_DEV2_EPF4_STRAP5
+//RCC_DEV2_EPF4_STRAP6
+//RCC_DEV2_EPF4_STRAP7
+//RCC_DEV2_EPF4_STRAP13
+//RCC_DEV2_EPF4_STRAP14
+//RCC_DEV2_EPF4_STRAP15
+//RCC_DEV2_EPF4_STRAP16
+//RCC_DEV2_EPF5_STRAP0
+//RCC_DEV2_EPF5_STRAP2
+//RCC_DEV2_EPF5_STRAP3
+//RCC_DEV2_EPF5_STRAP4
+//RCC_DEV2_EPF5_STRAP5
+//RCC_DEV2_EPF5_STRAP6
+//RCC_DEV2_EPF5_STRAP7
+//RCC_DEV2_EPF5_STRAP13
+//RCC_DEV2_EPF5_STRAP14
+//RCC_DEV2_EPF5_STRAP15
+//RCC_DEV2_EPF5_STRAP16
+//RCC_DEV2_EPF6_STRAP0
+//RCC_DEV2_EPF6_STRAP2
+//RCC_DEV2_EPF6_STRAP3
+//RCC_DEV2_EPF6_STRAP4
+//RCC_DEV2_EPF6_STRAP5
+//RCC_DEV2_EPF6_STRAP6
+//RCC_DEV2_EPF6_STRAP7
+//RCC_DEV2_EPF6_STRAP13
+//RCC_DEV2_EPF6_STRAP14
+//RCC_DEV2_EPF6_STRAP15
+//RCC_DEV2_EPF6_STRAP16
+
+
+// addressBlock: nbif0_nbif0_bif_rst_bif_rst_regblk
+//HARD_RST_CTRL
+#define HARD_RST_CTRL__DSPT_CFG_RST_EN__SHIFT                                                                 0x0
+#define HARD_RST_CTRL__DSPT_CFG_STICKY_RST_EN__SHIFT                                                          0x1
+#define HARD_RST_CTRL__DSPT_PRV_RST_EN__SHIFT                                                                 0x2
+#define HARD_RST_CTRL__DSPT_PRV_STICKY_RST_EN__SHIFT                                                          0x3
+#define HARD_RST_CTRL__EP_CFG_RST_EN__SHIFT                                                                   0x4
+#define HARD_RST_CTRL__EP_CFG_STICKY_RST_EN__SHIFT                                                            0x5
+#define HARD_RST_CTRL__EP_PRV_RST_EN__SHIFT                                                                   0x6
+#define HARD_RST_CTRL__EP_PRV_STICKY_RST_EN__SHIFT                                                            0x7
+#define HARD_RST_CTRL__SDP_PORT_RESET_EN__SHIFT                                                               0x9
+#define HARD_RST_CTRL__SION_AON_RESET_EN__SHIFT                                                               0xa
+#define HARD_RST_CTRL__STRAP_RST_EN__SHIFT                                                                    0x17
+#define HARD_RST_CTRL__SWUS_SHADOW_RST_EN__SHIFT                                                              0x1c
+#define HARD_RST_CTRL__CORE_STICKY_RST_EN__SHIFT                                                              0x1d
+#define HARD_RST_CTRL__RELOAD_STRAP_EN__SHIFT                                                                 0x1e
+#define HARD_RST_CTRL__CORE_RST_EN__SHIFT                                                                     0x1f
+#define HARD_RST_CTRL__DSPT_CFG_RST_EN_MASK                                                                   0x00000001L
+#define HARD_RST_CTRL__DSPT_CFG_STICKY_RST_EN_MASK                                                            0x00000002L
+#define HARD_RST_CTRL__DSPT_PRV_RST_EN_MASK                                                                   0x00000004L
+#define HARD_RST_CTRL__DSPT_PRV_STICKY_RST_EN_MASK                                                            0x00000008L
+#define HARD_RST_CTRL__EP_CFG_RST_EN_MASK                                                                     0x00000010L
+#define HARD_RST_CTRL__EP_CFG_STICKY_RST_EN_MASK                                                              0x00000020L
+#define HARD_RST_CTRL__EP_PRV_RST_EN_MASK                                                                     0x00000040L
+#define HARD_RST_CTRL__EP_PRV_STICKY_RST_EN_MASK                                                              0x00000080L
+#define HARD_RST_CTRL__SDP_PORT_RESET_EN_MASK                                                                 0x00000200L
+#define HARD_RST_CTRL__SION_AON_RESET_EN_MASK                                                                 0x00000400L
+#define HARD_RST_CTRL__STRAP_RST_EN_MASK                                                                      0x00800000L
+#define HARD_RST_CTRL__SWUS_SHADOW_RST_EN_MASK                                                                0x10000000L
+#define HARD_RST_CTRL__CORE_STICKY_RST_EN_MASK                                                                0x20000000L
+#define HARD_RST_CTRL__RELOAD_STRAP_EN_MASK                                                                   0x40000000L
+#define HARD_RST_CTRL__CORE_RST_EN_MASK                                                                       0x80000000L
+//SELF_SOFT_RST
+#define SELF_SOFT_RST__DSPT0_CFG_RST__SHIFT                                                                   0x0
+#define SELF_SOFT_RST__DSPT0_CFG_STICKY_RST__SHIFT                                                            0x1
+#define SELF_SOFT_RST__DSPT0_PRV_RST__SHIFT                                                                   0x2
+#define SELF_SOFT_RST__DSPT0_PRV_STICKY_RST__SHIFT                                                            0x3
+#define SELF_SOFT_RST__EP0_CFG_RST__SHIFT                                                                     0x4
+#define SELF_SOFT_RST__EP0_CFG_STICKY_RST__SHIFT                                                              0x5
+#define SELF_SOFT_RST__EP0_PRV_RST__SHIFT                                                                     0x6
+#define SELF_SOFT_RST__EP0_PRV_STICKY_RST__SHIFT                                                              0x7
+#define SELF_SOFT_RST__PCIE_NBIF_HST_SDP_PORT_RST__SHIFT                                                      0x18
+#define SELF_SOFT_RST__SST_HST_SDP_PORT_RST__SHIFT                                                            0x19
+#define SELF_SOFT_RST__NBIF_PCIE_DMA_SDP_PORT_RST__SHIFT                                                      0x1a
+#define SELF_SOFT_RST__SST_DMA_SDP_PORT_RST__SHIFT                                                            0x1b
+#define SELF_SOFT_RST__SWUS_SHADOW_RST__SHIFT                                                                 0x1c
+#define SELF_SOFT_RST__CORE_STICKY_RST__SHIFT                                                                 0x1d
+#define SELF_SOFT_RST__RELOAD_STRAP__SHIFT                                                                    0x1e
+#define SELF_SOFT_RST__CORE_RST__SHIFT                                                                        0x1f
+#define SELF_SOFT_RST__DSPT0_CFG_RST_MASK                                                                     0x00000001L
+#define SELF_SOFT_RST__DSPT0_CFG_STICKY_RST_MASK                                                              0x00000002L
+#define SELF_SOFT_RST__DSPT0_PRV_RST_MASK                                                                     0x00000004L
+#define SELF_SOFT_RST__DSPT0_PRV_STICKY_RST_MASK                                                              0x00000008L
+#define SELF_SOFT_RST__EP0_CFG_RST_MASK                                                                       0x00000010L
+#define SELF_SOFT_RST__EP0_CFG_STICKY_RST_MASK                                                                0x00000020L
+#define SELF_SOFT_RST__EP0_PRV_RST_MASK                                                                       0x00000040L
+#define SELF_SOFT_RST__EP0_PRV_STICKY_RST_MASK                                                                0x00000080L
+#define SELF_SOFT_RST__PCIE_NBIF_HST_SDP_PORT_RST_MASK                                                        0x01000000L
+#define SELF_SOFT_RST__SST_HST_SDP_PORT_RST_MASK                                                              0x02000000L
+#define SELF_SOFT_RST__NBIF_PCIE_DMA_SDP_PORT_RST_MASK                                                        0x04000000L
+#define SELF_SOFT_RST__SST_DMA_SDP_PORT_RST_MASK                                                              0x08000000L
+#define SELF_SOFT_RST__SWUS_SHADOW_RST_MASK                                                                   0x10000000L
+#define SELF_SOFT_RST__CORE_STICKY_RST_MASK                                                                   0x20000000L
+#define SELF_SOFT_RST__RELOAD_STRAP_MASK                                                                      0x40000000L
+#define SELF_SOFT_RST__CORE_RST_MASK                                                                          0x80000000L
+//BIF_GFX_DRV_VPU_RST
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_RST__SHIFT                                                      0x0
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_FLR_EXC_RST__SHIFT                                              0x1
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_STICKY_RST__SHIFT                                               0x2
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_PRV_RST__SHIFT                                                      0x3
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_PRV_STICKY_RST__SHIFT                                               0x4
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_CFG_RST__SHIFT                                                      0x5
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_CFG_STICKY_RST__SHIFT                                               0x6
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_PRV_RST__SHIFT                                                      0x7
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_RST_MASK                                                        0x00000001L
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_FLR_EXC_RST_MASK                                                0x00000002L
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_CFG_STICKY_RST_MASK                                                 0x00000004L
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_PRV_RST_MASK                                                        0x00000008L
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_PF_PRV_STICKY_RST_MASK                                                 0x00000010L
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_CFG_RST_MASK                                                        0x00000020L
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_CFG_STICKY_RST_MASK                                                 0x00000040L
+#define BIF_GFX_DRV_VPU_RST__DRV_MODE1_VF_PRV_RST_MASK                                                        0x00000080L
+//BIF_RST_MISC_CTRL
+#define BIF_RST_MISC_CTRL__ERRSTATUS_KEPT_IN_PERSTB__SHIFT                                                    0x0
+#define BIF_RST_MISC_CTRL__DRV_RST_MODE__SHIFT                                                                0x2
+#define BIF_RST_MISC_CTRL__DRV_RST_CFG_MASK__SHIFT                                                            0x4
+#define BIF_RST_MISC_CTRL__DRV_RST_BITS_AUTO_CLEAR__SHIFT                                                     0x5
+#define BIF_RST_MISC_CTRL__FLR_RST_BIT_AUTO_CLEAR__SHIFT                                                      0x6
+#define BIF_RST_MISC_CTRL__STRAP_EP_LNK_RST_IOV_EN__SHIFT                                                     0x8
+#define BIF_RST_MISC_CTRL__LNK_RST_GRACE_MODE__SHIFT                                                          0x9
+#define BIF_RST_MISC_CTRL__LNK_RST_GRACE_TIMEOUT__SHIFT                                                       0xa
+#define BIF_RST_MISC_CTRL__LNK_RST_TIMER_SEL__SHIFT                                                           0xd
+#define BIF_RST_MISC_CTRL__LNK_RST_TIMER2_SEL__SHIFT                                                          0xf
+#define BIF_RST_MISC_CTRL__SRIOV_SAVE_VFS_ON_VFENABLE_CLR__SHIFT                                              0x11
+#define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_DIS__SHIFT                                                       0x17
+#define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_RSPSTS__SHIFT                                                    0x18
+#define BIF_RST_MISC_CTRL__HARD_RST_CTRL_SWUS_SHADOW_PRV_RST_EN__SHIFT                                        0x1a
+#define BIF_RST_MISC_CTRL__ERRSTATUS_KEPT_IN_PERSTB_MASK                                                      0x00000001L
+#define BIF_RST_MISC_CTRL__DRV_RST_MODE_MASK                                                                  0x0000000CL
+#define BIF_RST_MISC_CTRL__DRV_RST_CFG_MASK_MASK                                                              0x00000010L
+#define BIF_RST_MISC_CTRL__DRV_RST_BITS_AUTO_CLEAR_MASK                                                       0x00000020L
+#define BIF_RST_MISC_CTRL__FLR_RST_BIT_AUTO_CLEAR_MASK                                                        0x00000040L
+#define BIF_RST_MISC_CTRL__STRAP_EP_LNK_RST_IOV_EN_MASK                                                       0x00000100L
+#define BIF_RST_MISC_CTRL__LNK_RST_GRACE_MODE_MASK                                                            0x00000200L
+#define BIF_RST_MISC_CTRL__LNK_RST_GRACE_TIMEOUT_MASK                                                         0x00001C00L
+#define BIF_RST_MISC_CTRL__LNK_RST_TIMER_SEL_MASK                                                             0x00006000L
+#define BIF_RST_MISC_CTRL__LNK_RST_TIMER2_SEL_MASK                                                            0x00018000L
+#define BIF_RST_MISC_CTRL__SRIOV_SAVE_VFS_ON_VFENABLE_CLR_MASK                                                0x000E0000L
+#define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_DIS_MASK                                                         0x00800000L
+#define BIF_RST_MISC_CTRL__LNK_RST_DMA_DUMMY_RSPSTS_MASK                                                      0x03000000L
+#define BIF_RST_MISC_CTRL__HARD_RST_CTRL_SWUS_SHADOW_PRV_RST_EN_MASK                                          0x04000000L
+//BIF_RST_MISC_CTRL2
+#define BIF_RST_MISC_CTRL2__SWUS_LNK_RST_PROTECT__SHIFT                                                       0x0
+#define BIF_RST_MISC_CTRL2__SWDS_LNK_RST_PROTECT__SHIFT                                                       0x1
+#define BIF_RST_MISC_CTRL2__ENDP0_LNK_RST_PROTECT__SHIFT                                                      0x2
+#define BIF_RST_MISC_CTRL2__ALL_RST_PROTECT__SHIFT                                                            0xf
+#define BIF_RST_MISC_CTRL2__SWUS_LNK_RST_TRANS_IDLE__SHIFT                                                    0x10
+#define BIF_RST_MISC_CTRL2__SWDS_LNK_RST_TRANS_IDLE__SHIFT                                                    0x11
+#define BIF_RST_MISC_CTRL2__ENDP0_LNK_RST_TRANS_IDLE__SHIFT                                                   0x12
+#define BIF_RST_MISC_CTRL2__ALL_RST_PROTECT_DIS__SHIFT                                                        0x1e
+#define BIF_RST_MISC_CTRL2__ALL_RST_TRANS_IDLE__SHIFT                                                         0x1f
+#define BIF_RST_MISC_CTRL2__SWUS_LNK_RST_PROTECT_MASK                                                         0x00000001L
+#define BIF_RST_MISC_CTRL2__SWDS_LNK_RST_PROTECT_MASK                                                         0x00000002L
+#define BIF_RST_MISC_CTRL2__ENDP0_LNK_RST_PROTECT_MASK                                                        0x00000004L
+#define BIF_RST_MISC_CTRL2__ALL_RST_PROTECT_MASK                                                              0x00008000L
+#define BIF_RST_MISC_CTRL2__SWUS_LNK_RST_TRANS_IDLE_MASK                                                      0x00010000L
+#define BIF_RST_MISC_CTRL2__SWDS_LNK_RST_TRANS_IDLE_MASK                                                      0x00020000L
+#define BIF_RST_MISC_CTRL2__ENDP0_LNK_RST_TRANS_IDLE_MASK                                                     0x00040000L
+#define BIF_RST_MISC_CTRL2__ALL_RST_PROTECT_DIS_MASK                                                          0x40000000L
+#define BIF_RST_MISC_CTRL2__ALL_RST_TRANS_IDLE_MASK                                                           0x80000000L
+//BIF_RST_MISC_CTRL3
+#define BIF_RST_MISC_CTRL3__TIMER_SCALE__SHIFT                                                                0x0
+#define BIF_RST_MISC_CTRL3__PME_TURNOFF_TIMEOUT__SHIFT                                                        0x4
+#define BIF_RST_MISC_CTRL3__PME_TURNOFF_MODE__SHIFT                                                           0x6
+#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_HARD__SHIFT                                                    0x7
+#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SOFT__SHIFT                                                    0xa
+#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SELF__SHIFT                                                    0xd
+#define BIF_RST_MISC_CTRL3__TIMER_SCALE_MASK                                                                  0x0000000FL
+#define BIF_RST_MISC_CTRL3__PME_TURNOFF_TIMEOUT_MASK                                                          0x00000030L
+#define BIF_RST_MISC_CTRL3__PME_TURNOFF_MODE_MASK                                                             0x00000040L
+#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_HARD_MASK                                                      0x00000380L
+#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SOFT_MASK                                                      0x00001C00L
+#define BIF_RST_MISC_CTRL3__RELOAD_STRAP_DELAY_SELF_MASK                                                      0x0000E000L
+//DEV0_PF0_FLR_RST_CTRL
+#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_EN__SHIFT                                                               0x0
+#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                       0x1
+#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                        0x2
+#define DEV0_PF0_FLR_RST_CTRL__PF_PRV_EN__SHIFT                                                               0x3
+#define DEV0_PF0_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                        0x4
+#define DEV0_PF0_FLR_RST_CTRL__DEV0_PF0_FLR_RST_CTRL_VF_CFG_EN__SHIFT                                         0x5
+#define DEV0_PF0_FLR_RST_CTRL__DEV0_PF0_FLR_RST_CTRL_VF_CFG_STICKY_EN__SHIFT                                  0x6
+#define DEV0_PF0_FLR_RST_CTRL__DEV0_PF0_FLR_RST_CTRL_VF_PRV_EN__SHIFT                                         0x7
+#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_EN__SHIFT                                                          0x8
+#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_FLR_EXC_EN__SHIFT                                                  0x9
+#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_STICKY_EN__SHIFT                                                   0xa
+#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_EN__SHIFT                                                          0xb
+#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_STICKY_EN__SHIFT                                                   0xc
+#define DEV0_PF0_FLR_RST_CTRL__DEV0_PF0_FLR_RST_CTRL_VF_VF_CFG_EN__SHIFT                                      0xd
+#define DEV0_PF0_FLR_RST_CTRL__DEV0_PF0_FLR_RST_CTRL_VF_VF_CFG_STICKY_EN__SHIFT                               0xe
+#define DEV0_PF0_FLR_RST_CTRL__DEV0_PF0_FLR_RST_CTRL_VF_VF_PRV_EN__SHIFT                                      0xf
+#define DEV0_PF0_FLR_RST_CTRL__FLR_TWICE_EN__SHIFT                                                            0x10
+#define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT                                                          0x11
+#define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT                                                       0x12
+#define DEV0_PF0_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT                                                    0x17
+#define DEV0_PF0_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT                                                    0x19
+#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PFCOPY_PRV_EN__SHIFT                                                   0x1f
+#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_EN_MASK                                                                 0x00000001L
+#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                         0x00000002L
+#define DEV0_PF0_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                          0x00000004L
+#define DEV0_PF0_FLR_RST_CTRL__PF_PRV_EN_MASK                                                                 0x00000008L
+#define DEV0_PF0_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                          0x00000010L
+#define DEV0_PF0_FLR_RST_CTRL__DEV0_PF0_FLR_RST_CTRL_VF_CFG_EN_MASK                                           0x00000020L
+#define DEV0_PF0_FLR_RST_CTRL__DEV0_PF0_FLR_RST_CTRL_VF_CFG_STICKY_EN_MASK                                    0x00000040L
+#define DEV0_PF0_FLR_RST_CTRL__DEV0_PF0_FLR_RST_CTRL_VF_PRV_EN_MASK                                           0x00000080L
+#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_EN_MASK                                                            0x00000100L
+#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_FLR_EXC_EN_MASK                                                    0x00000200L
+#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_CFG_STICKY_EN_MASK                                                     0x00000400L
+#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_EN_MASK                                                            0x00000800L
+#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PRV_STICKY_EN_MASK                                                     0x00001000L
+#define DEV0_PF0_FLR_RST_CTRL__DEV0_PF0_FLR_RST_CTRL_VF_VF_CFG_EN_MASK                                        0x00002000L
+#define DEV0_PF0_FLR_RST_CTRL__DEV0_PF0_FLR_RST_CTRL_VF_VF_CFG_STICKY_EN_MASK                                 0x00004000L
+#define DEV0_PF0_FLR_RST_CTRL__DEV0_PF0_FLR_RST_CTRL_VF_VF_PRV_EN_MASK                                        0x00008000L
+#define DEV0_PF0_FLR_RST_CTRL__FLR_TWICE_EN_MASK                                                              0x00010000L
+#define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_MODE_MASK                                                            0x00020000L
+#define DEV0_PF0_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK                                                         0x001C0000L
+#define DEV0_PF0_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK                                                      0x01800000L
+#define DEV0_PF0_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK                                                      0x06000000L
+#define DEV0_PF0_FLR_RST_CTRL__SOFT_PF_PFCOPY_PRV_EN_MASK                                                     0x80000000L
+//DEV0_PF1_FLR_RST_CTRL
+#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_EN__SHIFT                                                               0x0
+#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                       0x1
+#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                        0x2
+#define DEV0_PF1_FLR_RST_CTRL__PF_PRV_EN__SHIFT                                                               0x3
+#define DEV0_PF1_FLR_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                        0x4
+#define DEV0_PF1_FLR_RST_CTRL__DEV0_PF1_FLR_RST_CTRL_VF_CFG_EN__SHIFT                                         0x5
+#define DEV0_PF1_FLR_RST_CTRL__DEV0_PF1_FLR_RST_CTRL_VF_CFG_STICKY_EN__SHIFT                                  0x6
+#define DEV0_PF1_FLR_RST_CTRL__DEV0_PF1_FLR_RST_CTRL_VF_PRV_EN__SHIFT                                         0x7
+#define DEV0_PF1_FLR_RST_CTRL__DEV0_PF1_FLR_RST_CTRL_VF_VF_CFG_EN__SHIFT                                      0xd
+#define DEV0_PF1_FLR_RST_CTRL__DEV0_PF1_FLR_RST_CTRL_VF_VF_CFG_STICKY_EN__SHIFT                               0xe
+#define DEV0_PF1_FLR_RST_CTRL__DEV0_PF1_FLR_RST_CTRL_VF_VF_PRV_EN__SHIFT                                      0xf
+#define DEV0_PF1_FLR_RST_CTRL__FLR_TWICE_EN__SHIFT                                                            0x10
+#define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_MODE__SHIFT                                                          0x11
+#define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_TIMEOUT__SHIFT                                                       0x12
+#define DEV0_PF1_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS__SHIFT                                                    0x17
+#define DEV0_PF1_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS__SHIFT                                                    0x19
+#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_EN_MASK                                                                 0x00000001L
+#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                         0x00000002L
+#define DEV0_PF1_FLR_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                          0x00000004L
+#define DEV0_PF1_FLR_RST_CTRL__PF_PRV_EN_MASK                                                                 0x00000008L
+#define DEV0_PF1_FLR_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                          0x00000010L
+#define DEV0_PF1_FLR_RST_CTRL__DEV0_PF1_FLR_RST_CTRL_VF_CFG_EN_MASK                                           0x00000020L
+#define DEV0_PF1_FLR_RST_CTRL__DEV0_PF1_FLR_RST_CTRL_VF_CFG_STICKY_EN_MASK                                    0x00000040L
+#define DEV0_PF1_FLR_RST_CTRL__DEV0_PF1_FLR_RST_CTRL_VF_PRV_EN_MASK                                           0x00000080L
+#define DEV0_PF1_FLR_RST_CTRL__DEV0_PF1_FLR_RST_CTRL_VF_VF_CFG_EN_MASK                                        0x00002000L
+#define DEV0_PF1_FLR_RST_CTRL__DEV0_PF1_FLR_RST_CTRL_VF_VF_CFG_STICKY_EN_MASK                                 0x00004000L
+#define DEV0_PF1_FLR_RST_CTRL__DEV0_PF1_FLR_RST_CTRL_VF_VF_PRV_EN_MASK                                        0x00008000L
+#define DEV0_PF1_FLR_RST_CTRL__FLR_TWICE_EN_MASK                                                              0x00010000L
+#define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_MODE_MASK                                                            0x00020000L
+#define DEV0_PF1_FLR_RST_CTRL__FLR_GRACE_TIMEOUT_MASK                                                         0x001C0000L
+#define DEV0_PF1_FLR_RST_CTRL__FLR_DMA_DUMMY_RSPSTS_MASK                                                      0x01800000L
+#define DEV0_PF1_FLR_RST_CTRL__FLR_HST_DUMMY_RSPSTS_MASK                                                      0x06000000L
+//BIF_INST_RESET_INTR_STS
+#define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_INTR_STS__SHIFT                                               0x0
+#define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_CFG_ONLY_INTR_STS__SHIFT                                      0x1
+#define BIF_INST_RESET_INTR_STS__DRV_RESET_M0_INTR_STS__SHIFT                                                 0x2
+#define BIF_INST_RESET_INTR_STS__DRV_RESET_M1_INTR_STS__SHIFT                                                 0x3
+#define BIF_INST_RESET_INTR_STS__DRV_RESET_M2_INTR_STS__SHIFT                                                 0x4
+#define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_INTR_STS_MASK                                                 0x00000001L
+#define BIF_INST_RESET_INTR_STS__EP0_LINK_RESET_CFG_ONLY_INTR_STS_MASK                                        0x00000002L
+#define BIF_INST_RESET_INTR_STS__DRV_RESET_M0_INTR_STS_MASK                                                   0x00000004L
+#define BIF_INST_RESET_INTR_STS__DRV_RESET_M1_INTR_STS_MASK                                                   0x00000008L
+#define BIF_INST_RESET_INTR_STS__DRV_RESET_M2_INTR_STS_MASK                                                   0x00000010L
+//BIF_PF_FLR_INTR_STS
+#define BIF_PF_FLR_INTR_STS__DEV0_PF0_FLR_INTR_STS__SHIFT                                                     0x0
+#define BIF_PF_FLR_INTR_STS__DEV0_PF1_FLR_INTR_STS__SHIFT                                                     0x1
+#define BIF_PF_FLR_INTR_STS__DEV0_PF0_FLR_INTR_STS_MASK                                                       0x00000001L
+#define BIF_PF_FLR_INTR_STS__DEV0_PF1_FLR_INTR_STS_MASK                                                       0x00000002L
+//BIF_D3HOTD0_INTR_STS
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF0_D3HOTD0_INTR_STS__SHIFT                                                0x0
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF1_D3HOTD0_INTR_STS__SHIFT                                                0x1
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF0_D3HOTD0_INTR_STS_MASK                                                  0x00000001L
+#define BIF_D3HOTD0_INTR_STS__DEV0_PF1_D3HOTD0_INTR_STS_MASK                                                  0x00000002L
+//BIF_POWER_INTR_STS
+#define BIF_POWER_INTR_STS__DEV0_PME_TURN_OFF_INTR_STS__SHIFT                                                 0x0
+#define BIF_POWER_INTR_STS__PORT0_DSTATE_INTR_STS__SHIFT                                                      0x10
+#define BIF_POWER_INTR_STS__DEV0_PME_TURN_OFF_INTR_STS_MASK                                                   0x00000001L
+#define BIF_POWER_INTR_STS__PORT0_DSTATE_INTR_STS_MASK                                                        0x00010000L
+//BIF_PF_DSTATE_INTR_STS
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF0_DSTATE_INTR_STS__SHIFT                                               0x0
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF1_DSTATE_INTR_STS__SHIFT                                               0x1
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF2_DSTATE_INTR_STS__SHIFT                                               0x2
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF3_DSTATE_INTR_STS__SHIFT                                               0x3
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF4_DSTATE_INTR_STS__SHIFT                                               0x4
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF5_DSTATE_INTR_STS__SHIFT                                               0x5
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF6_DSTATE_INTR_STS__SHIFT                                               0x6
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF7_DSTATE_INTR_STS__SHIFT                                               0x7
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF0_DSTATE_INTR_STS_MASK                                                 0x00000001L
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF1_DSTATE_INTR_STS_MASK                                                 0x00000002L
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF2_DSTATE_INTR_STS_MASK                                                 0x00000004L
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF3_DSTATE_INTR_STS_MASK                                                 0x00000008L
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF4_DSTATE_INTR_STS_MASK                                                 0x00000010L
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF5_DSTATE_INTR_STS_MASK                                                 0x00000020L
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF6_DSTATE_INTR_STS_MASK                                                 0x00000040L
+#define BIF_PF_DSTATE_INTR_STS__DEV0_PF7_DSTATE_INTR_STS_MASK                                                 0x00000080L
+//SELF_SOFT_RST_2
+#define SELF_SOFT_RST_2__DSPT3_CFG_RST__SHIFT                                                                 0x0
+#define SELF_SOFT_RST_2__DSPT3_CFG_STICKY_RST__SHIFT                                                          0x1
+#define SELF_SOFT_RST_2__DSPT3_PRV_RST__SHIFT                                                                 0x2
+#define SELF_SOFT_RST_2__DSPT3_PRV_STICKY_RST__SHIFT                                                          0x3
+#define SELF_SOFT_RST_2__EP3_CFG_RST__SHIFT                                                                   0x4
+#define SELF_SOFT_RST_2__EP3_CFG_STICKY_RST__SHIFT                                                            0x5
+#define SELF_SOFT_RST_2__EP3_PRV_RST__SHIFT                                                                   0x6
+#define SELF_SOFT_RST_2__EP3_PRV_STICKY_RST__SHIFT                                                            0x7
+#define SELF_SOFT_RST_2__GMISP0_SDP_PORT_RST__SHIFT                                                           0x18
+#define SELF_SOFT_RST_2__STRAP_RST__SHIFT                                                                     0x19
+#define SELF_SOFT_RST_2__SWUS_SHADOW_PRV_RST__SHIFT                                                           0x1a
+#define SELF_SOFT_RST_2__DSPT3_CFG_RST_MASK                                                                   0x00000001L
+#define SELF_SOFT_RST_2__DSPT3_CFG_STICKY_RST_MASK                                                            0x00000002L
+#define SELF_SOFT_RST_2__DSPT3_PRV_RST_MASK                                                                   0x00000004L
+#define SELF_SOFT_RST_2__DSPT3_PRV_STICKY_RST_MASK                                                            0x00000008L
+#define SELF_SOFT_RST_2__EP3_CFG_RST_MASK                                                                     0x00000010L
+#define SELF_SOFT_RST_2__EP3_CFG_STICKY_RST_MASK                                                              0x00000020L
+#define SELF_SOFT_RST_2__EP3_PRV_RST_MASK                                                                     0x00000040L
+#define SELF_SOFT_RST_2__EP3_PRV_STICKY_RST_MASK                                                              0x00000080L
+#define SELF_SOFT_RST_2__GMISP0_SDP_PORT_RST_MASK                                                             0x01000000L
+#define SELF_SOFT_RST_2__STRAP_RST_MASK                                                                       0x02000000L
+#define SELF_SOFT_RST_2__SWUS_SHADOW_PRV_RST_MASK                                                             0x04000000L
+//SION_SDP_PORT_RST
+#define SION_SDP_PORT_RST__SYSHUB_NBIFSION_SDP_PORT_RST__SHIFT                                                0x0
+#define SION_SDP_PORT_RST__NBIFSION_SYSHUB_SDP_PORT_RST__SHIFT                                                0x1
+#define SION_SDP_PORT_RST__BIF_NBIFSION_SDP_PORT_RST__SHIFT                                                   0x2
+#define SION_SDP_PORT_RST__ATDMA_NBIFSOIN_SDP_PORT_RST__SHIFT                                                 0x4
+#define SION_SDP_PORT_RST__INT_NBIFSION_SDP_PORT_RST__SHIFT                                                   0x5
+#define SION_SDP_PORT_RST__MP4SDP_SDP_PORT_RST__SHIFT                                                         0x6
+#define SION_SDP_PORT_RST__NBIFSOIN_ATHUB_SDP_PORT_RST__SHIFT                                                 0x7
+#define SION_SDP_PORT_RST__NTB_HST_SDP_PORT_RST__SHIFT                                                        0x8
+#define SION_SDP_PORT_RST__NTB_DMA_SDP_PORT_RST__SHIFT                                                        0x9
+#define SION_SDP_PORT_RST__ATHUB_HST_SDP_PORT_RST__SHIFT                                                      0xc
+#define SION_SDP_PORT_RST__SION_AON_RST__SHIFT                                                                0x18
+#define SION_SDP_PORT_RST__SYSHUB_NBIFSION_SDP_PORT_RST_MASK                                                  0x00000001L
+#define SION_SDP_PORT_RST__NBIFSION_SYSHUB_SDP_PORT_RST_MASK                                                  0x00000002L
+#define SION_SDP_PORT_RST__BIF_NBIFSION_SDP_PORT_RST_MASK                                                     0x00000004L
+#define SION_SDP_PORT_RST__ATDMA_NBIFSOIN_SDP_PORT_RST_MASK                                                   0x00000010L
+#define SION_SDP_PORT_RST__INT_NBIFSION_SDP_PORT_RST_MASK                                                     0x00000020L
+#define SION_SDP_PORT_RST__MP4SDP_SDP_PORT_RST_MASK                                                           0x00000040L
+#define SION_SDP_PORT_RST__NBIFSOIN_ATHUB_SDP_PORT_RST_MASK                                                   0x00000080L
+#define SION_SDP_PORT_RST__NTB_HST_SDP_PORT_RST_MASK                                                          0x00000100L
+#define SION_SDP_PORT_RST__NTB_DMA_SDP_PORT_RST_MASK                                                          0x00000200L
+#define SION_SDP_PORT_RST__ATHUB_HST_SDP_PORT_RST_MASK                                                        0x00001000L
+#define SION_SDP_PORT_RST__SION_AON_RST_MASK                                                                  0x01000000L
+//BIF_INST_RESET_INTR_MASK
+#define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_INTR_MASK__SHIFT                                             0x0
+#define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_CFG_ONLY_INTR_MASK__SHIFT                                    0x1
+#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M0_INTR_MASK__SHIFT                                               0x2
+#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M1_INTR_MASK__SHIFT                                               0x3
+#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M2_INTR_MASK__SHIFT                                               0x4
+#define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_INTR_MASK_MASK                                               0x00000001L
+#define BIF_INST_RESET_INTR_MASK__EP0_LINK_RESET_CFG_ONLY_INTR_MASK_MASK                                      0x00000002L
+#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M0_INTR_MASK_MASK                                                 0x00000004L
+#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M1_INTR_MASK_MASK                                                 0x00000008L
+#define BIF_INST_RESET_INTR_MASK__DRV_RESET_M2_INTR_MASK_MASK                                                 0x00000010L
+//BIF_PF_FLR_INTR_MASK
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF0_FLR_INTR_MASK__SHIFT                                                   0x0
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF1_FLR_INTR_MASK__SHIFT                                                   0x1
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF0_FLR_INTR_MASK_MASK                                                     0x00000001L
+#define BIF_PF_FLR_INTR_MASK__DEV0_PF1_FLR_INTR_MASK_MASK                                                     0x00000002L
+//BIF_D3HOTD0_INTR_MASK
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF0_D3HOTD0_INTR_MASK__SHIFT                                              0x0
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF1_D3HOTD0_INTR_MASK__SHIFT                                              0x1
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF0_D3HOTD0_INTR_MASK_MASK                                                0x00000001L
+#define BIF_D3HOTD0_INTR_MASK__DEV0_PF1_D3HOTD0_INTR_MASK_MASK                                                0x00000002L
+//BIF_POWER_INTR_MASK
+#define BIF_POWER_INTR_MASK__DEV0_PME_TURN_OFF_INTR_MASK__SHIFT                                               0x0
+#define BIF_POWER_INTR_MASK__PORT0_DSTATE_INTR_MASK__SHIFT                                                    0x10
+#define BIF_POWER_INTR_MASK__DEV0_PME_TURN_OFF_INTR_MASK_MASK                                                 0x00000001L
+#define BIF_POWER_INTR_MASK__PORT0_DSTATE_INTR_MASK_MASK                                                      0x00010000L
+//BIF_PF_DSTATE_INTR_MASK
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF0_DSTATE_INTR_MASK__SHIFT                                             0x0
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF1_DSTATE_INTR_MASK__SHIFT                                             0x1
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF2_DSTATE_INTR_MASK__SHIFT                                             0x2
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF3_DSTATE_INTR_MASK__SHIFT                                             0x3
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF4_DSTATE_INTR_MASK__SHIFT                                             0x4
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF5_DSTATE_INTR_MASK__SHIFT                                             0x5
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF6_DSTATE_INTR_MASK__SHIFT                                             0x6
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF7_DSTATE_INTR_MASK__SHIFT                                             0x7
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF0_DSTATE_INTR_MASK_MASK                                               0x00000001L
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF1_DSTATE_INTR_MASK_MASK                                               0x00000002L
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF2_DSTATE_INTR_MASK_MASK                                               0x00000004L
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF3_DSTATE_INTR_MASK_MASK                                               0x00000008L
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF4_DSTATE_INTR_MASK_MASK                                               0x00000010L
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF5_DSTATE_INTR_MASK_MASK                                               0x00000020L
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF6_DSTATE_INTR_MASK_MASK                                               0x00000040L
+#define BIF_PF_DSTATE_INTR_MASK__DEV0_PF7_DSTATE_INTR_MASK_MASK                                               0x00000080L
+//BIF_DEV0_PF0_VF_FLR_INTR_MASK
+#define BIF_DEV0_PF0_VF_FLR_INTR_MASK__DEV0_PF0_VF0_FLR_INTR_MASK__SHIFT                                      0x0
+#define BIF_DEV0_PF0_VF_FLR_INTR_MASK__DEV0_PF0_VF1_FLR_INTR_MASK__SHIFT                                      0x1
+#define BIF_DEV0_PF0_VF_FLR_INTR_MASK__DEV0_PF0_VF2_FLR_INTR_MASK__SHIFT                                      0x2
+#define BIF_DEV0_PF0_VF_FLR_INTR_MASK__DEV0_PF0_VF3_FLR_INTR_MASK__SHIFT                                      0x3
+#define BIF_DEV0_PF0_VF_FLR_INTR_MASK__DEV0_PF0_VF4_FLR_INTR_MASK__SHIFT                                      0x4
+#define BIF_DEV0_PF0_VF_FLR_INTR_MASK__DEV0_PF0_VF5_FLR_INTR_MASK__SHIFT                                      0x5
+#define BIF_DEV0_PF0_VF_FLR_INTR_MASK__DEV0_PF0_VF6_FLR_INTR_MASK__SHIFT                                      0x6
+#define BIF_DEV0_PF0_VF_FLR_INTR_MASK__DEV0_PF0_VF7_FLR_INTR_MASK__SHIFT                                      0x7
+#define BIF_DEV0_PF0_VF_FLR_INTR_MASK__DEV0_PF0_SOFTPF_FLR_INTR_MASK__SHIFT                                   0x1f
+#define BIF_DEV0_PF0_VF_FLR_INTR_MASK__DEV0_PF0_VF0_FLR_INTR_MASK_MASK                                        0x00000001L
+#define BIF_DEV0_PF0_VF_FLR_INTR_MASK__DEV0_PF0_VF1_FLR_INTR_MASK_MASK                                        0x00000002L
+#define BIF_DEV0_PF0_VF_FLR_INTR_MASK__DEV0_PF0_VF2_FLR_INTR_MASK_MASK                                        0x00000004L
+#define BIF_DEV0_PF0_VF_FLR_INTR_MASK__DEV0_PF0_VF3_FLR_INTR_MASK_MASK                                        0x00000008L
+#define BIF_DEV0_PF0_VF_FLR_INTR_MASK__DEV0_PF0_VF4_FLR_INTR_MASK_MASK                                        0x00000010L
+#define BIF_DEV0_PF0_VF_FLR_INTR_MASK__DEV0_PF0_VF5_FLR_INTR_MASK_MASK                                        0x00000020L
+#define BIF_DEV0_PF0_VF_FLR_INTR_MASK__DEV0_PF0_VF6_FLR_INTR_MASK_MASK                                        0x00000040L
+#define BIF_DEV0_PF0_VF_FLR_INTR_MASK__DEV0_PF0_VF7_FLR_INTR_MASK_MASK                                        0x00000080L
+#define BIF_DEV0_PF0_VF_FLR_INTR_MASK__DEV0_PF0_SOFTPF_FLR_INTR_MASK_MASK                                     0x80000000L
+//BIF_DEV0_PF1_VF_FLR_INTR_MASK
+#define BIF_DEV0_PF1_VF_FLR_INTR_MASK__DEV0_PF1_VF0_FLR_INTR_MASK__SHIFT                                      0x0
+#define BIF_DEV0_PF1_VF_FLR_INTR_MASK__DEV0_PF1_VF0_FLR_INTR_MASK_MASK                                        0x00000001L
+//BIF_PF_FLR_RST
+#define BIF_PF_FLR_RST__DEV0_PF0_FLR_RST__SHIFT                                                               0x0
+#define BIF_PF_FLR_RST__DEV0_PF1_FLR_RST__SHIFT                                                               0x1
+#define BIF_PF_FLR_RST__DEV0_PF0_FLR_RST_MASK                                                                 0x00000001L
+#define BIF_PF_FLR_RST__DEV0_PF1_FLR_RST_MASK                                                                 0x00000002L
+//BIF_PF_FLR_PROTECT
+#define BIF_PF_FLR_PROTECT__DEV0_PF0_FLR_PROTECT__SHIFT                                                       0x0
+#define BIF_PF_FLR_PROTECT__DEV0_PF1_FLR_PROTECT__SHIFT                                                       0x1
+#define BIF_PF_FLR_PROTECT__DEV0_PF2_FLR_PROTECT__SHIFT                                                       0x2
+#define BIF_PF_FLR_PROTECT__DEV0_PF3_FLR_PROTECT__SHIFT                                                       0x3
+#define BIF_PF_FLR_PROTECT__DEV0_PF4_FLR_PROTECT__SHIFT                                                       0x4
+#define BIF_PF_FLR_PROTECT__DEV0_PF5_FLR_PROTECT__SHIFT                                                       0x5
+#define BIF_PF_FLR_PROTECT__DEV0_PF6_FLR_PROTECT__SHIFT                                                       0x6
+#define BIF_PF_FLR_PROTECT__DEV0_PF7_FLR_PROTECT__SHIFT                                                       0x7
+#define BIF_PF_FLR_PROTECT__DEV0_PF0_TRANS_IDLE__SHIFT                                                        0x10
+#define BIF_PF_FLR_PROTECT__DEV0_PF1_TRANS_IDLE__SHIFT                                                        0x11
+#define BIF_PF_FLR_PROTECT__DEV0_PF2_TRANS_IDLE__SHIFT                                                        0x12
+#define BIF_PF_FLR_PROTECT__DEV0_PF3_TRANS_IDLE__SHIFT                                                        0x13
+#define BIF_PF_FLR_PROTECT__DEV0_PF4_TRANS_IDLE__SHIFT                                                        0x14
+#define BIF_PF_FLR_PROTECT__DEV0_PF5_TRANS_IDLE__SHIFT                                                        0x15
+#define BIF_PF_FLR_PROTECT__DEV0_PF6_TRANS_IDLE__SHIFT                                                        0x16
+#define BIF_PF_FLR_PROTECT__DEV0_PF7_TRANS_IDLE__SHIFT                                                        0x17
+#define BIF_PF_FLR_PROTECT__DEV0_PF0_FLR_PROTECT_MASK                                                         0x00000001L
+#define BIF_PF_FLR_PROTECT__DEV0_PF1_FLR_PROTECT_MASK                                                         0x00000002L
+#define BIF_PF_FLR_PROTECT__DEV0_PF2_FLR_PROTECT_MASK                                                         0x00000004L
+#define BIF_PF_FLR_PROTECT__DEV0_PF3_FLR_PROTECT_MASK                                                         0x00000008L
+#define BIF_PF_FLR_PROTECT__DEV0_PF4_FLR_PROTECT_MASK                                                         0x00000010L
+#define BIF_PF_FLR_PROTECT__DEV0_PF5_FLR_PROTECT_MASK                                                         0x00000020L
+#define BIF_PF_FLR_PROTECT__DEV0_PF6_FLR_PROTECT_MASK                                                         0x00000040L
+#define BIF_PF_FLR_PROTECT__DEV0_PF7_FLR_PROTECT_MASK                                                         0x00000080L
+#define BIF_PF_FLR_PROTECT__DEV0_PF0_TRANS_IDLE_MASK                                                          0x00010000L
+#define BIF_PF_FLR_PROTECT__DEV0_PF1_TRANS_IDLE_MASK                                                          0x00020000L
+#define BIF_PF_FLR_PROTECT__DEV0_PF2_TRANS_IDLE_MASK                                                          0x00040000L
+#define BIF_PF_FLR_PROTECT__DEV0_PF3_TRANS_IDLE_MASK                                                          0x00080000L
+#define BIF_PF_FLR_PROTECT__DEV0_PF4_TRANS_IDLE_MASK                                                          0x00100000L
+#define BIF_PF_FLR_PROTECT__DEV0_PF5_TRANS_IDLE_MASK                                                          0x00200000L
+#define BIF_PF_FLR_PROTECT__DEV0_PF6_TRANS_IDLE_MASK                                                          0x00400000L
+#define BIF_PF_FLR_PROTECT__DEV0_PF7_TRANS_IDLE_MASK                                                          0x00800000L
+//BIF_PF_FLR_PROTECT3
+#define BIF_PF_FLR_PROTECT3__DEV0_PF0_VF_FLR_CTRL__SHIFT                                                      0x0
+#define BIF_PF_FLR_PROTECT3__DEV0_PF1_VF_FLR_CTRL__SHIFT                                                      0x1
+#define BIF_PF_FLR_PROTECT3__DEV0_PF0_VF_FLR_CTRL_MASK                                                        0x00000001L
+#define BIF_PF_FLR_PROTECT3__DEV0_PF1_VF_FLR_CTRL_MASK                                                        0x00000002L
+//BIF_DEV0_PF0_DSTATE_VALUE
+#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_TGT_VALUE__SHIFT                                           0x0
+#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_NEED_D3TOD0_RESET__SHIFT                                   0x2
+#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_ACK_VALUE__SHIFT                                           0x10
+#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_TGT_VALUE_MASK                                             0x00000003L
+#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_NEED_D3TOD0_RESET_MASK                                     0x00000004L
+#define BIF_DEV0_PF0_DSTATE_VALUE__DEV0_PF0_DSTATE_ACK_VALUE_MASK                                             0x00030000L
+//BIF_DEV0_PF1_DSTATE_VALUE
+#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_TGT_VALUE__SHIFT                                           0x0
+#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_NEED_D3TOD0_RESET__SHIFT                                   0x2
+#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_ACK_VALUE__SHIFT                                           0x10
+#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_TGT_VALUE_MASK                                             0x00000003L
+#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_NEED_D3TOD0_RESET_MASK                                     0x00000004L
+#define BIF_DEV0_PF1_DSTATE_VALUE__DEV0_PF1_DSTATE_ACK_VALUE_MASK                                             0x00030000L
+//GFX_RST_CNTL_IND0
+#define GFX_RST_CNTL_IND0__GFX_RST_FINISH_INDICATION__SHIFT                                                   0x0
+#define GFX_RST_CNTL_IND0__SCRATCH_REG__SHIFT                                                                 0x1
+#define GFX_RST_CNTL_IND0__GFX_RST_FINISH_INDICATION_MASK                                                     0x00000001L
+#define GFX_RST_CNTL_IND0__SCRATCH_REG_MASK                                                                   0xFFFFFFFEL
+//GFX_RST_CNTL_SOFT_PF
+#define GFX_RST_CNTL_SOFT_PF__GFX_RST_FINISH_INDICATION__SHIFT                                                0x0
+#define GFX_RST_CNTL_SOFT_PF__SCRATCH_REG__SHIFT                                                              0x1
+#define GFX_RST_CNTL_SOFT_PF__GFX_RST_FINISH_INDICATION_MASK                                                  0x00000001L
+#define GFX_RST_CNTL_SOFT_PF__SCRATCH_REG_MASK                                                                0xFFFFFFFEL
+//GFX_RST_CNTL_IND1
+#define GFX_RST_CNTL_IND1__GFX_RST_FINISH_INDICATION__SHIFT                                                   0x0
+#define GFX_RST_CNTL_IND1__SCRATCH_REG__SHIFT                                                                 0x1
+#define GFX_RST_CNTL_IND1__GFX_RST_FINISH_INDICATION_MASK                                                     0x00000001L
+#define GFX_RST_CNTL_IND1__SCRATCH_REG_MASK                                                                   0xFFFFFFFEL
+//GFX_RST_CNTL_IND2
+#define GFX_RST_CNTL_IND2__GFX_RST_FINISH_INDICATION__SHIFT                                                   0x0
+#define GFX_RST_CNTL_IND2__SCRATCH_REG__SHIFT                                                                 0x1
+#define GFX_RST_CNTL_IND2__GFX_RST_FINISH_INDICATION_MASK                                                     0x00000001L
+#define GFX_RST_CNTL_IND2__SCRATCH_REG_MASK                                                                   0xFFFFFFFEL
+//GFX_RST_CNTL_IND3
+#define GFX_RST_CNTL_IND3__GFX_RST_FINISH_INDICATION__SHIFT                                                   0x0
+#define GFX_RST_CNTL_IND3__SCRATCH_REG__SHIFT                                                                 0x1
+#define GFX_RST_CNTL_IND3__GFX_RST_FINISH_INDICATION_MASK                                                     0x00000001L
+#define GFX_RST_CNTL_IND3__SCRATCH_REG_MASK                                                                   0xFFFFFFFEL
+//GFX_RST_CNTL_IND4
+#define GFX_RST_CNTL_IND4__GFX_RST_FINISH_INDICATION__SHIFT                                                   0x0
+#define GFX_RST_CNTL_IND4__SCRATCH_REG__SHIFT                                                                 0x1
+#define GFX_RST_CNTL_IND4__GFX_RST_FINISH_INDICATION_MASK                                                     0x00000001L
+#define GFX_RST_CNTL_IND4__SCRATCH_REG_MASK                                                                   0xFFFFFFFEL
+//GFX_RST_CNTL_IND5
+#define GFX_RST_CNTL_IND5__GFX_RST_FINISH_INDICATION__SHIFT                                                   0x0
+#define GFX_RST_CNTL_IND5__SCRATCH_REG__SHIFT                                                                 0x1
+#define GFX_RST_CNTL_IND5__GFX_RST_FINISH_INDICATION_MASK                                                     0x00000001L
+#define GFX_RST_CNTL_IND5__SCRATCH_REG_MASK                                                                   0xFFFFFFFEL
+//GFX_RST_CNTL_IND6
+#define GFX_RST_CNTL_IND6__GFX_RST_FINISH_INDICATION__SHIFT                                                   0x0
+#define GFX_RST_CNTL_IND6__SCRATCH_REG__SHIFT                                                                 0x1
+#define GFX_RST_CNTL_IND6__GFX_RST_FINISH_INDICATION_MASK                                                     0x00000001L
+#define GFX_RST_CNTL_IND6__SCRATCH_REG_MASK                                                                   0xFFFFFFFEL
+//GFX_RST_CNTL_IND7
+#define GFX_RST_CNTL_IND7__GFX_RST_FINISH_INDICATION__SHIFT                                                   0x0
+#define GFX_RST_CNTL_IND7__SCRATCH_REG__SHIFT                                                                 0x1
+#define GFX_RST_CNTL_IND7__GFX_RST_FINISH_INDICATION_MASK                                                     0x00000001L
+#define GFX_RST_CNTL_IND7__SCRATCH_REG_MASK                                                                   0xFFFFFFFEL
+//GFX_RST_CNTL_IND8
+#define GFX_RST_CNTL_IND8__GFX_RST_FINISH_INDICATION__SHIFT                                                   0x0
+#define GFX_RST_CNTL_IND8__SCRATCH_REG__SHIFT                                                                 0x1
+#define GFX_RST_CNTL_IND8__GFX_RST_FINISH_INDICATION_MASK                                                     0x00000001L
+#define GFX_RST_CNTL_IND8__SCRATCH_REG_MASK                                                                   0xFFFFFFFEL
+//DEV0_PF0_D3HOTD0_RST_CTRL
+#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT                                                           0x0
+#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                   0x1
+#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                    0x2
+#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT                                                           0x3
+#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                    0x4
+#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK                                                             0x00000001L
+#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                     0x00000002L
+#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                      0x00000004L
+#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK                                                             0x00000008L
+#define DEV0_PF0_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                      0x00000010L
+//DEV0_PF1_D3HOTD0_RST_CTRL
+#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_EN__SHIFT                                                           0x0
+#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN__SHIFT                                                   0x1
+#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN__SHIFT                                                    0x2
+#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_EN__SHIFT                                                           0x3
+#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN__SHIFT                                                    0x4
+#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_EN_MASK                                                             0x00000001L
+#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_FLR_EXC_EN_MASK                                                     0x00000002L
+#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_CFG_STICKY_EN_MASK                                                      0x00000004L
+#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_EN_MASK                                                             0x00000008L
+#define DEV0_PF1_D3HOTD0_RST_CTRL__PF_PRV_STICKY_EN_MASK                                                      0x00000010L
+//BIF_DEV0_PF0_VF_FLR_PROTECT
+#define BIF_DEV0_PF0_VF_FLR_PROTECT__DEV0_PF0_VF0_FLR_PROTECT__SHIFT                                          0x0
+#define BIF_DEV0_PF0_VF_FLR_PROTECT__DEV0_PF0_VF1_FLR_PROTECT__SHIFT                                          0x1
+#define BIF_DEV0_PF0_VF_FLR_PROTECT__DEV0_PF0_VF2_FLR_PROTECT__SHIFT                                          0x2
+#define BIF_DEV0_PF0_VF_FLR_PROTECT__DEV0_PF0_VF3_FLR_PROTECT__SHIFT                                          0x3
+#define BIF_DEV0_PF0_VF_FLR_PROTECT__DEV0_PF0_VF4_FLR_PROTECT__SHIFT                                          0x4
+#define BIF_DEV0_PF0_VF_FLR_PROTECT__DEV0_PF0_VF5_FLR_PROTECT__SHIFT                                          0x5
+#define BIF_DEV0_PF0_VF_FLR_PROTECT__DEV0_PF0_VF6_FLR_PROTECT__SHIFT                                          0x6
+#define BIF_DEV0_PF0_VF_FLR_PROTECT__DEV0_PF0_VF7_FLR_PROTECT__SHIFT                                          0x7
+#define BIF_DEV0_PF0_VF_FLR_PROTECT__DEV0_PF0_SOFTPF_FLR_PROTECT__SHIFT                                       0x1f
+#define BIF_DEV0_PF0_VF_FLR_PROTECT__DEV0_PF0_VF0_FLR_PROTECT_MASK                                            0x00000001L
+#define BIF_DEV0_PF0_VF_FLR_PROTECT__DEV0_PF0_VF1_FLR_PROTECT_MASK                                            0x00000002L
+#define BIF_DEV0_PF0_VF_FLR_PROTECT__DEV0_PF0_VF2_FLR_PROTECT_MASK                                            0x00000004L
+#define BIF_DEV0_PF0_VF_FLR_PROTECT__DEV0_PF0_VF3_FLR_PROTECT_MASK                                            0x00000008L
+#define BIF_DEV0_PF0_VF_FLR_PROTECT__DEV0_PF0_VF4_FLR_PROTECT_MASK                                            0x00000010L
+#define BIF_DEV0_PF0_VF_FLR_PROTECT__DEV0_PF0_VF5_FLR_PROTECT_MASK                                            0x00000020L
+#define BIF_DEV0_PF0_VF_FLR_PROTECT__DEV0_PF0_VF6_FLR_PROTECT_MASK                                            0x00000040L
+#define BIF_DEV0_PF0_VF_FLR_PROTECT__DEV0_PF0_VF7_FLR_PROTECT_MASK                                            0x00000080L
+#define BIF_DEV0_PF0_VF_FLR_PROTECT__DEV0_PF0_SOFTPF_FLR_PROTECT_MASK                                         0x80000000L
+//BIF_DEV0_PF1_VF_FLR_PROTECT
+#define BIF_DEV0_PF1_VF_FLR_PROTECT__DEV0_PF1_VF0_FLR_PROTECT__SHIFT                                          0x0
+#define BIF_DEV0_PF1_VF_FLR_PROTECT__DEV0_PF1_VF0_FLR_PROTECT_MASK                                            0x00000001L
+//BIF_SRIOVEN_SET_INTR_STS
+#define BIF_SRIOVEN_SET_INTR_STS__DEV0_PF0_SRIOVEN_SET_INTR_STS__SHIFT                                        0x0
+#define BIF_SRIOVEN_SET_INTR_STS__DEV0_PF1_SRIOVEN_SET_INTR_STS__SHIFT                                        0x1
+#define BIF_SRIOVEN_SET_INTR_STS__DEV0_PF0_SRIOVEN_SET_INTR_STS_MASK                                          0x00000001L
+#define BIF_SRIOVEN_SET_INTR_STS__DEV0_PF1_SRIOVEN_SET_INTR_STS_MASK                                          0x00000002L
+//BIF_SRIOVEN_CLR_INTR_STS
+#define BIF_SRIOVEN_CLR_INTR_STS__DEV0_PF0_SRIOVEN_CLR_INTR_STS__SHIFT                                        0x0
+#define BIF_SRIOVEN_CLR_INTR_STS__DEV0_PF1_SRIOVEN_CLR_INTR_STS__SHIFT                                        0x1
+#define BIF_SRIOVEN_CLR_INTR_STS__DEV0_PF0_SRIOVEN_CLR_INTR_STS_MASK                                          0x00000001L
+#define BIF_SRIOVEN_CLR_INTR_STS__DEV0_PF1_SRIOVEN_CLR_INTR_STS_MASK                                          0x00000002L
+//BIF_SRIOVEN_SET_INTR_MASK
+#define BIF_SRIOVEN_SET_INTR_MASK__DEV0_PF0_SRIOVEN_SET_INTR_MASK__SHIFT                                      0x0
+#define BIF_SRIOVEN_SET_INTR_MASK__DEV0_PF1_SRIOVEN_SET_INTR_MASK__SHIFT                                      0x1
+#define BIF_SRIOVEN_SET_INTR_MASK__DEV0_PF0_SRIOVEN_SET_INTR_MASK_MASK                                        0x00000001L
+#define BIF_SRIOVEN_SET_INTR_MASK__DEV0_PF1_SRIOVEN_SET_INTR_MASK_MASK                                        0x00000002L
+//BIF_SRIOVEN_CLR_INTR_MASK
+#define BIF_SRIOVEN_CLR_INTR_MASK__DEV0_PF0_SRIOVEN_CLR_INTR_MASK__SHIFT                                      0x0
+#define BIF_SRIOVEN_CLR_INTR_MASK__DEV0_PF1_SRIOVEN_CLR_INTR_MASK__SHIFT                                      0x1
+#define BIF_SRIOVEN_CLR_INTR_MASK__DEV0_PF0_SRIOVEN_CLR_INTR_MASK_MASK                                        0x00000001L
+#define BIF_SRIOVEN_CLR_INTR_MASK__DEV0_PF1_SRIOVEN_CLR_INTR_MASK_MASK                                        0x00000002L
+//BIF_PORT0_DSTATE_VALUE
+#define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_TGT_VALUE__SHIFT                                                 0x0
+#define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_ACK_VALUE__SHIFT                                                 0x10
+#define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_TGT_VALUE_MASK                                                   0x00000003L
+#define BIF_PORT0_DSTATE_VALUE__PORT0_DSTATE_ACK_VALUE_MASK                                                   0x00030000L
+//BIF_DEV0_PF0_RST_VF_FLR_IDLE
+#define BIF_DEV0_PF0_RST_VF_FLR_IDLE__DEV0_PF0_VF0_TRANS_IDLE__SHIFT                                          0x0
+#define BIF_DEV0_PF0_RST_VF_FLR_IDLE__DEV0_PF0_VF1_TRANS_IDLE__SHIFT                                          0x1
+#define BIF_DEV0_PF0_RST_VF_FLR_IDLE__DEV0_PF0_VF2_TRANS_IDLE__SHIFT                                          0x2
+#define BIF_DEV0_PF0_RST_VF_FLR_IDLE__DEV0_PF0_VF3_TRANS_IDLE__SHIFT                                          0x3
+#define BIF_DEV0_PF0_RST_VF_FLR_IDLE__DEV0_PF0_VF4_TRANS_IDLE__SHIFT                                          0x4
+#define BIF_DEV0_PF0_RST_VF_FLR_IDLE__DEV0_PF0_VF5_TRANS_IDLE__SHIFT                                          0x5
+#define BIF_DEV0_PF0_RST_VF_FLR_IDLE__DEV0_PF0_VF6_TRANS_IDLE__SHIFT                                          0x6
+#define BIF_DEV0_PF0_RST_VF_FLR_IDLE__DEV0_PF0_VF7_TRANS_IDLE__SHIFT                                          0x7
+#define BIF_DEV0_PF0_RST_VF_FLR_IDLE__SOFTPF_TRANS_IDLE__SHIFT                                                0x1f
+#define BIF_DEV0_PF0_RST_VF_FLR_IDLE__DEV0_PF0_VF0_TRANS_IDLE_MASK                                            0x00000001L
+#define BIF_DEV0_PF0_RST_VF_FLR_IDLE__DEV0_PF0_VF1_TRANS_IDLE_MASK                                            0x00000002L
+#define BIF_DEV0_PF0_RST_VF_FLR_IDLE__DEV0_PF0_VF2_TRANS_IDLE_MASK                                            0x00000004L
+#define BIF_DEV0_PF0_RST_VF_FLR_IDLE__DEV0_PF0_VF3_TRANS_IDLE_MASK                                            0x00000008L
+#define BIF_DEV0_PF0_RST_VF_FLR_IDLE__DEV0_PF0_VF4_TRANS_IDLE_MASK                                            0x00000010L
+#define BIF_DEV0_PF0_RST_VF_FLR_IDLE__DEV0_PF0_VF5_TRANS_IDLE_MASK                                            0x00000020L
+#define BIF_DEV0_PF0_RST_VF_FLR_IDLE__DEV0_PF0_VF6_TRANS_IDLE_MASK                                            0x00000040L
+#define BIF_DEV0_PF0_RST_VF_FLR_IDLE__DEV0_PF0_VF7_TRANS_IDLE_MASK                                            0x00000080L
+#define BIF_DEV0_PF0_RST_VF_FLR_IDLE__SOFTPF_TRANS_IDLE_MASK                                                  0x80000000L
+//BIF_DEV0_PF1_RST_VF_FLR_IDLE
+#define BIF_DEV0_PF1_RST_VF_FLR_IDLE__DEV0_PF1_VF0_TRANS_IDLE__SHIFT                                          0x0
+#define BIF_DEV0_PF1_RST_VF_FLR_IDLE__DEV0_PF1_VF0_TRANS_IDLE_MASK                                            0x00000001L
+//BIF_DEV0_PF0_VF_FLR_INTR_STS
+#define BIF_DEV0_PF0_VF_FLR_INTR_STS__DEV0_PF0_VF0_FLR_INTR_STS__SHIFT                                        0x0
+#define BIF_DEV0_PF0_VF_FLR_INTR_STS__DEV0_PF0_VF1_FLR_INTR_STS__SHIFT                                        0x1
+#define BIF_DEV0_PF0_VF_FLR_INTR_STS__DEV0_PF0_VF2_FLR_INTR_STS__SHIFT                                        0x2
+#define BIF_DEV0_PF0_VF_FLR_INTR_STS__DEV0_PF0_VF3_FLR_INTR_STS__SHIFT                                        0x3
+#define BIF_DEV0_PF0_VF_FLR_INTR_STS__DEV0_PF0_VF4_FLR_INTR_STS__SHIFT                                        0x4
+#define BIF_DEV0_PF0_VF_FLR_INTR_STS__DEV0_PF0_VF5_FLR_INTR_STS__SHIFT                                        0x5
+#define BIF_DEV0_PF0_VF_FLR_INTR_STS__DEV0_PF0_VF6_FLR_INTR_STS__SHIFT                                        0x6
+#define BIF_DEV0_PF0_VF_FLR_INTR_STS__DEV0_PF0_VF7_FLR_INTR_STS__SHIFT                                        0x7
+#define BIF_DEV0_PF0_VF_FLR_INTR_STS__DEV0_PF0_SOFTPF_FLR_INTR_STS__SHIFT                                     0x1f
+#define BIF_DEV0_PF0_VF_FLR_INTR_STS__DEV0_PF0_VF0_FLR_INTR_STS_MASK                                          0x00000001L
+#define BIF_DEV0_PF0_VF_FLR_INTR_STS__DEV0_PF0_VF1_FLR_INTR_STS_MASK                                          0x00000002L
+#define BIF_DEV0_PF0_VF_FLR_INTR_STS__DEV0_PF0_VF2_FLR_INTR_STS_MASK                                          0x00000004L
+#define BIF_DEV0_PF0_VF_FLR_INTR_STS__DEV0_PF0_VF3_FLR_INTR_STS_MASK                                          0x00000008L
+#define BIF_DEV0_PF0_VF_FLR_INTR_STS__DEV0_PF0_VF4_FLR_INTR_STS_MASK                                          0x00000010L
+#define BIF_DEV0_PF0_VF_FLR_INTR_STS__DEV0_PF0_VF5_FLR_INTR_STS_MASK                                          0x00000020L
+#define BIF_DEV0_PF0_VF_FLR_INTR_STS__DEV0_PF0_VF6_FLR_INTR_STS_MASK                                          0x00000040L
+#define BIF_DEV0_PF0_VF_FLR_INTR_STS__DEV0_PF0_VF7_FLR_INTR_STS_MASK                                          0x00000080L
+#define BIF_DEV0_PF0_VF_FLR_INTR_STS__DEV0_PF0_SOFTPF_FLR_INTR_STS_MASK                                       0x80000000L
+//BIF_DEV0_PF1_VF_FLR_INTR_STS
+#define BIF_DEV0_PF1_VF_FLR_INTR_STS__DEV0_PF1_VF0_FLR_INTR_STS__SHIFT                                        0x0
+#define BIF_DEV0_PF1_VF_FLR_INTR_STS__DEV0_PF1_VF0_FLR_INTR_STS_MASK                                          0x00000001L
+//BIF_DEV0_PF0_VF_FLR_RST
+#define BIF_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF0_FLR_RST__SHIFT                                                  0x0
+#define BIF_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF1_FLR_RST__SHIFT                                                  0x1
+#define BIF_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF2_FLR_RST__SHIFT                                                  0x2
+#define BIF_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF3_FLR_RST__SHIFT                                                  0x3
+#define BIF_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF4_FLR_RST__SHIFT                                                  0x4
+#define BIF_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF5_FLR_RST__SHIFT                                                  0x5
+#define BIF_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF6_FLR_RST__SHIFT                                                  0x6
+#define BIF_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF7_FLR_RST__SHIFT                                                  0x7
+#define BIF_DEV0_PF0_VF_FLR_RST__DEV0_PF0_SOFTPF_FLR_RST__SHIFT                                               0x1f
+#define BIF_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF0_FLR_RST_MASK                                                    0x00000001L
+#define BIF_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF1_FLR_RST_MASK                                                    0x00000002L
+#define BIF_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF2_FLR_RST_MASK                                                    0x00000004L
+#define BIF_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF3_FLR_RST_MASK                                                    0x00000008L
+#define BIF_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF4_FLR_RST_MASK                                                    0x00000010L
+#define BIF_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF5_FLR_RST_MASK                                                    0x00000020L
+#define BIF_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF6_FLR_RST_MASK                                                    0x00000040L
+#define BIF_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF7_FLR_RST_MASK                                                    0x00000080L
+#define BIF_DEV0_PF0_VF_FLR_RST__DEV0_PF0_SOFTPF_FLR_RST_MASK                                                 0x80000000L
+//BIF_DEV0_PF1_VF_FLR_RST
+#define BIF_DEV0_PF1_VF_FLR_RST__DEV0_PF1_VF0_FLR_RST__SHIFT                                                  0x0
+#define BIF_DEV0_PF1_VF_FLR_RST__DEV0_PF1_VF0_FLR_RST_MASK                                                    0x00000001L
+
+
+// addressBlock: nbif0_nbif0_bif_misc_bif_misc_regblk
+//DOE_PRV_CTRL0_DEV0F0
+#define DOE_PRV_CTRL0_DEV0F0__DOE_PRV_INT_MSG_NUMBER_DEV0F0__SHIFT                                            0x0
+#define DOE_PRV_CTRL0_DEV0F0__DOE_PRV_WRITE_THRESHOLD_DEV0F0__SHIFT                                           0xb
+#define DOE_PRV_CTRL0_DEV0F0__DOE_PRV_READ_THRESHOLD_DEV0F0__SHIFT                                            0x10
+#define DOE_PRV_CTRL0_DEV0F0__DOE_PRV_WOT_INTM_DEV0F0__SHIFT                                                  0x15
+#define DOE_PRV_CTRL0_DEV0F0__DOE_PRV_ROT_INTM_DEV0F0__SHIFT                                                  0x16
+#define DOE_PRV_CTRL0_DEV0F0__DOE_PRV_ABT_INTM_DEV0F0__SHIFT                                                  0x17
+#define DOE_PRV_CTRL0_DEV0F0__DOE_PRV_GO_INTM_DEV0F0__SHIFT                                                   0x18
+#define DOE_PRV_CTRL0_DEV0F0__DOE_PRV_PSN_INTM_DEV0F0__SHIFT                                                  0x19
+#define DOE_PRV_CTRL0_DEV0F0__DOE_PRV_RUDF_INTM_DEV0F0__SHIFT                                                 0x1a
+#define DOE_PRV_CTRL0_DEV0F0__DOE_PRV_INT_MSG_NUMBER_DEV0F0_MASK                                              0x000007FFL
+#define DOE_PRV_CTRL0_DEV0F0__DOE_PRV_WRITE_THRESHOLD_DEV0F0_MASK                                             0x0000F800L
+#define DOE_PRV_CTRL0_DEV0F0__DOE_PRV_READ_THRESHOLD_DEV0F0_MASK                                              0x001F0000L
+#define DOE_PRV_CTRL0_DEV0F0__DOE_PRV_WOT_INTM_DEV0F0_MASK                                                    0x00200000L
+#define DOE_PRV_CTRL0_DEV0F0__DOE_PRV_ROT_INTM_DEV0F0_MASK                                                    0x00400000L
+#define DOE_PRV_CTRL0_DEV0F0__DOE_PRV_ABT_INTM_DEV0F0_MASK                                                    0x00800000L
+#define DOE_PRV_CTRL0_DEV0F0__DOE_PRV_GO_INTM_DEV0F0_MASK                                                     0x01000000L
+#define DOE_PRV_CTRL0_DEV0F0__DOE_PRV_PSN_INTM_DEV0F0_MASK                                                    0x02000000L
+#define DOE_PRV_CTRL0_DEV0F0__DOE_PRV_RUDF_INTM_DEV0F0_MASK                                                   0x04000000L
+//DOE_PRV_CMD_DEV0F0
+#define DOE_PRV_CMD_DEV0F0__DOE_PRV_BUSY_CLR_ABORT_DEV0F0__SHIFT                                              0x0
+#define DOE_PRV_CMD_DEV0F0__DOE_PRV_ERR_SET_DEV0F0__SHIFT                                                     0x1
+#define DOE_PRV_CMD_DEV0F0__DOE_PRV_DATA_REMAIN_DEV0F0__SHIFT                                                 0x2
+#define DOE_PRV_CMD_DEV0F0__DOE_PRV_DOE_RST_DEV0F0__SHIFT                                                     0x8
+#define DOE_PRV_CMD_DEV0F0__DOE_PRV_BUSY_CLR_NORSP_DEV0F0__SHIFT                                              0x9
+#define DOE_PRV_CMD_DEV0F0__DOE_PRV_ASYNC_MSG_STS_DEV0F0__SHIFT                                               0xa
+#define DOE_PRV_CMD_DEV0F0__DOE_PRV_BUSY_CLR_ABORT_DEV0F0_MASK                                                0x00000001L
+#define DOE_PRV_CMD_DEV0F0__DOE_PRV_ERR_SET_DEV0F0_MASK                                                       0x00000002L
+#define DOE_PRV_CMD_DEV0F0__DOE_PRV_DATA_REMAIN_DEV0F0_MASK                                                   0x000000FCL
+#define DOE_PRV_CMD_DEV0F0__DOE_PRV_DOE_RST_DEV0F0_MASK                                                       0x00000100L
+#define DOE_PRV_CMD_DEV0F0__DOE_PRV_BUSY_CLR_NORSP_DEV0F0_MASK                                                0x00000200L
+#define DOE_PRV_CMD_DEV0F0__DOE_PRV_ASYNC_MSG_STS_DEV0F0_MASK                                                 0x00000400L
+//DOE_PRV_WDATA_DEV0F0
+#define DOE_PRV_WDATA_DEV0F0__DOE_PRV_DATA_PUSH_DEV0F0__SHIFT                                                 0x0
+#define DOE_PRV_WDATA_DEV0F0__DOE_PRV_DATA_PUSH_DEV0F0_MASK                                                   0xFFFFFFFFL
+//DOE_PRV_STS_DEV0F0
+#define DOE_PRV_STS_DEV0F0__DOE_PRV_WRITE_OVER_THRESHOLD_DEV0F0__SHIFT                                        0x0
+#define DOE_PRV_STS_DEV0F0__DOE_PRV_READ_UNDER_THRESHOLD_DEV0F0__SHIFT                                        0x1
+#define DOE_PRV_STS_DEV0F0__DOE_PRV_ABORT_DET_DEV0F0__SHIFT                                                   0x2
+#define DOE_PRV_STS_DEV0F0__DOE_PRV_GO_DET_DEV0F0__SHIFT                                                      0x3
+#define DOE_PRV_STS_DEV0F0__DOE_PRV_PSN_DET_DEV0F0__SHIFT                                                     0x4
+#define DOE_PRV_STS_DEV0F0__DOE_PRV_UNDERFLOW_DET_DEV0F0__SHIFT                                               0x5
+#define DOE_PRV_STS_DEV0F0__DOE_PRV_OCCUP_WMBOX_DEV0F0__SHIFT                                                 0x6
+#define DOE_PRV_STS_DEV0F0__DOE_PRV_VACA_RMBOX_DEV0F0__SHIFT                                                  0xc
+#define DOE_PRV_STS_DEV0F0__DOE_PRV_WRITE_OVER_THRESHOLD_DEV0F0_MASK                                          0x00000001L
+#define DOE_PRV_STS_DEV0F0__DOE_PRV_READ_UNDER_THRESHOLD_DEV0F0_MASK                                          0x00000002L
+#define DOE_PRV_STS_DEV0F0__DOE_PRV_ABORT_DET_DEV0F0_MASK                                                     0x00000004L
+#define DOE_PRV_STS_DEV0F0__DOE_PRV_GO_DET_DEV0F0_MASK                                                        0x00000008L
+#define DOE_PRV_STS_DEV0F0__DOE_PRV_PSN_DET_DEV0F0_MASK                                                       0x00000010L
+#define DOE_PRV_STS_DEV0F0__DOE_PRV_UNDERFLOW_DET_DEV0F0_MASK                                                 0x00000020L
+#define DOE_PRV_STS_DEV0F0__DOE_PRV_OCCUP_WMBOX_DEV0F0_MASK                                                   0x00000FC0L
+#define DOE_PRV_STS_DEV0F0__DOE_PRV_VACA_RMBOX_DEV0F0_MASK                                                    0x0003F000L
+//DOE_PRV_RDATA_DEV0F0
+#define DOE_PRV_RDATA_DEV0F0__DOE_PRV_RDATA_WMBOX_DEV0F0__SHIFT                                               0x0
+#define DOE_PRV_RDATA_DEV0F0__DOE_PRV_RDATA_WMBOX_DEV0F0_MASK                                                 0xFFFFFFFFL
+//NBIF_RC_INTR_CNTL
+#define NBIF_RC_INTR_CNTL__RC_ERR_INTR_TRIG_DEV0__SHIFT                                                       0x0
+#define NBIF_RC_INTR_CNTL__RC_ERR_INTR_TRIG_DEV0_MASK                                                         0x00000001L
+//BIF_DEV0_PF0_TDISP_CNTL
+#define BIF_DEV0_PF0_TDISP_CNTL__BIF_DEV0_PF0_TDISP_STATE__SHIFT                                              0x0
+#define BIF_DEV0_PF0_TDISP_CNTL__BIF_DEV0_PF0_LOCK_INTERFACE_REQUEST__SHIFT                                   0x4
+#define BIF_DEV0_PF0_TDISP_CNTL__BIF_DEV0_PF0_START_INTERFACE_REQUEST__SHIFT                                  0x5
+#define BIF_DEV0_PF0_TDISP_CNTL__BIF_DEV0_PF0_STOP_INTERFACE_REQUEST__SHIFT                                   0x7
+#define BIF_DEV0_PF0_TDISP_CNTL__BIF_DEV0_PF0_INTERFACE_ERROR__SHIFT                                          0x8
+#define BIF_DEV0_PF0_TDISP_CNTL__BIF_DEV0_PF0_TDISP_STATE_MASK                                                0x00000007L
+#define BIF_DEV0_PF0_TDISP_CNTL__BIF_DEV0_PF0_LOCK_INTERFACE_REQUEST_MASK                                     0x00000010L
+#define BIF_DEV0_PF0_TDISP_CNTL__BIF_DEV0_PF0_START_INTERFACE_REQUEST_MASK                                    0x00000020L
+#define BIF_DEV0_PF0_TDISP_CNTL__BIF_DEV0_PF0_STOP_INTERFACE_REQUEST_MASK                                     0x00000080L
+#define BIF_DEV0_PF0_TDISP_CNTL__BIF_DEV0_PF0_INTERFACE_ERROR_MASK                                            0x00000100L
+//BIF_DEV0_PF1_TDISP_CNTL
+#define BIF_DEV0_PF1_TDISP_CNTL__BIF_DEV0_PF1_TDISP_STATE__SHIFT                                              0x0
+#define BIF_DEV0_PF1_TDISP_CNTL__BIF_DEV0_PF1_LOCK_INTERFACE_REQUEST__SHIFT                                   0x4
+#define BIF_DEV0_PF1_TDISP_CNTL__BIF_DEV0_PF1_START_INTERFACE_REQUEST__SHIFT                                  0x5
+#define BIF_DEV0_PF1_TDISP_CNTL__BIF_DEV0_PF1_STOP_INTERFACE_REQUEST__SHIFT                                   0x7
+#define BIF_DEV0_PF1_TDISP_CNTL__BIF_DEV0_PF1_INTERFACE_ERROR__SHIFT                                          0x8
+#define BIF_DEV0_PF1_TDISP_CNTL__BIF_DEV0_PF1_TDISP_STATE_MASK                                                0x00000007L
+#define BIF_DEV0_PF1_TDISP_CNTL__BIF_DEV0_PF1_LOCK_INTERFACE_REQUEST_MASK                                     0x00000010L
+#define BIF_DEV0_PF1_TDISP_CNTL__BIF_DEV0_PF1_START_INTERFACE_REQUEST_MASK                                    0x00000020L
+#define BIF_DEV0_PF1_TDISP_CNTL__BIF_DEV0_PF1_STOP_INTERFACE_REQUEST_MASK                                     0x00000080L
+#define BIF_DEV0_PF1_TDISP_CNTL__BIF_DEV0_PF1_INTERFACE_ERROR_MASK                                            0x00000100L
+//BIF_DEV0_PF0_VF0_TDISP_CNTL
+#define BIF_DEV0_PF0_VF0_TDISP_CNTL__BIF_DEV0_PF0_VF0_TDISP_STATE__SHIFT                                      0x0
+#define BIF_DEV0_PF0_VF0_TDISP_CNTL__BIF_DEV0_PF0_VF0_LOCK_INTERFACE_REQUEST__SHIFT                           0x4
+#define BIF_DEV0_PF0_VF0_TDISP_CNTL__BIF_DEV0_PF0_VF0_START_INTERFACE_REQUEST__SHIFT                          0x5
+#define BIF_DEV0_PF0_VF0_TDISP_CNTL__BIF_DEV0_PF0_VF0_STOP_INTERFACE_REQUEST__SHIFT                           0x7
+#define BIF_DEV0_PF0_VF0_TDISP_CNTL__BIF_DEV0_PF0_VF0_INTERFACE_ERROR__SHIFT                                  0x8
+#define BIF_DEV0_PF0_VF0_TDISP_CNTL__BIF_DEV0_PF0_VF0_TDISP_STATE_MASK                                        0x00000007L
+#define BIF_DEV0_PF0_VF0_TDISP_CNTL__BIF_DEV0_PF0_VF0_LOCK_INTERFACE_REQUEST_MASK                             0x00000010L
+#define BIF_DEV0_PF0_VF0_TDISP_CNTL__BIF_DEV0_PF0_VF0_START_INTERFACE_REQUEST_MASK                            0x00000020L
+#define BIF_DEV0_PF0_VF0_TDISP_CNTL__BIF_DEV0_PF0_VF0_STOP_INTERFACE_REQUEST_MASK                             0x00000080L
+#define BIF_DEV0_PF0_VF0_TDISP_CNTL__BIF_DEV0_PF0_VF0_INTERFACE_ERROR_MASK                                    0x00000100L
+//BIF_DEV0_PF0_VF1_TDISP_CNTL
+#define BIF_DEV0_PF0_VF1_TDISP_CNTL__BIF_DEV0_PF0_VF1_TDISP_STATE__SHIFT                                      0x0
+#define BIF_DEV0_PF0_VF1_TDISP_CNTL__BIF_DEV0_PF0_VF1_LOCK_INTERFACE_REQUEST__SHIFT                           0x4
+#define BIF_DEV0_PF0_VF1_TDISP_CNTL__BIF_DEV0_PF0_VF1_START_INTERFACE_REQUEST__SHIFT                          0x5
+#define BIF_DEV0_PF0_VF1_TDISP_CNTL__BIF_DEV0_PF0_VF1_STOP_INTERFACE_REQUEST__SHIFT                           0x7
+#define BIF_DEV0_PF0_VF1_TDISP_CNTL__BIF_DEV0_PF0_VF1_INTERFACE_ERROR__SHIFT                                  0x8
+#define BIF_DEV0_PF0_VF1_TDISP_CNTL__BIF_DEV0_PF0_VF1_TDISP_STATE_MASK                                        0x00000007L
+#define BIF_DEV0_PF0_VF1_TDISP_CNTL__BIF_DEV0_PF0_VF1_LOCK_INTERFACE_REQUEST_MASK                             0x00000010L
+#define BIF_DEV0_PF0_VF1_TDISP_CNTL__BIF_DEV0_PF0_VF1_START_INTERFACE_REQUEST_MASK                            0x00000020L
+#define BIF_DEV0_PF0_VF1_TDISP_CNTL__BIF_DEV0_PF0_VF1_STOP_INTERFACE_REQUEST_MASK                             0x00000080L
+#define BIF_DEV0_PF0_VF1_TDISP_CNTL__BIF_DEV0_PF0_VF1_INTERFACE_ERROR_MASK                                    0x00000100L
+//BIF_DEV0_PF0_VF2_TDISP_CNTL
+#define BIF_DEV0_PF0_VF2_TDISP_CNTL__BIF_DEV0_PF0_VF2_TDISP_STATE__SHIFT                                      0x0
+#define BIF_DEV0_PF0_VF2_TDISP_CNTL__BIF_DEV0_PF0_VF2_LOCK_INTERFACE_REQUEST__SHIFT                           0x4
+#define BIF_DEV0_PF0_VF2_TDISP_CNTL__BIF_DEV0_PF0_VF2_START_INTERFACE_REQUEST__SHIFT                          0x5
+#define BIF_DEV0_PF0_VF2_TDISP_CNTL__BIF_DEV0_PF0_VF2_STOP_INTERFACE_REQUEST__SHIFT                           0x7
+#define BIF_DEV0_PF0_VF2_TDISP_CNTL__BIF_DEV0_PF0_VF2_INTERFACE_ERROR__SHIFT                                  0x8
+#define BIF_DEV0_PF0_VF2_TDISP_CNTL__BIF_DEV0_PF0_VF2_TDISP_STATE_MASK                                        0x00000007L
+#define BIF_DEV0_PF0_VF2_TDISP_CNTL__BIF_DEV0_PF0_VF2_LOCK_INTERFACE_REQUEST_MASK                             0x00000010L
+#define BIF_DEV0_PF0_VF2_TDISP_CNTL__BIF_DEV0_PF0_VF2_START_INTERFACE_REQUEST_MASK                            0x00000020L
+#define BIF_DEV0_PF0_VF2_TDISP_CNTL__BIF_DEV0_PF0_VF2_STOP_INTERFACE_REQUEST_MASK                             0x00000080L
+#define BIF_DEV0_PF0_VF2_TDISP_CNTL__BIF_DEV0_PF0_VF2_INTERFACE_ERROR_MASK                                    0x00000100L
+//BIF_DEV0_PF0_VF3_TDISP_CNTL
+#define BIF_DEV0_PF0_VF3_TDISP_CNTL__BIF_DEV0_PF0_VF3_TDISP_STATE__SHIFT                                      0x0
+#define BIF_DEV0_PF0_VF3_TDISP_CNTL__BIF_DEV0_PF0_VF3_LOCK_INTERFACE_REQUEST__SHIFT                           0x4
+#define BIF_DEV0_PF0_VF3_TDISP_CNTL__BIF_DEV0_PF0_VF3_START_INTERFACE_REQUEST__SHIFT                          0x5
+#define BIF_DEV0_PF0_VF3_TDISP_CNTL__BIF_DEV0_PF0_VF3_STOP_INTERFACE_REQUEST__SHIFT                           0x7
+#define BIF_DEV0_PF0_VF3_TDISP_CNTL__BIF_DEV0_PF0_VF3_INTERFACE_ERROR__SHIFT                                  0x8
+#define BIF_DEV0_PF0_VF3_TDISP_CNTL__BIF_DEV0_PF0_VF3_TDISP_STATE_MASK                                        0x00000007L
+#define BIF_DEV0_PF0_VF3_TDISP_CNTL__BIF_DEV0_PF0_VF3_LOCK_INTERFACE_REQUEST_MASK                             0x00000010L
+#define BIF_DEV0_PF0_VF3_TDISP_CNTL__BIF_DEV0_PF0_VF3_START_INTERFACE_REQUEST_MASK                            0x00000020L
+#define BIF_DEV0_PF0_VF3_TDISP_CNTL__BIF_DEV0_PF0_VF3_STOP_INTERFACE_REQUEST_MASK                             0x00000080L
+#define BIF_DEV0_PF0_VF3_TDISP_CNTL__BIF_DEV0_PF0_VF3_INTERFACE_ERROR_MASK                                    0x00000100L
+//BIF_DEV0_PF0_VF4_TDISP_CNTL
+#define BIF_DEV0_PF0_VF4_TDISP_CNTL__BIF_DEV0_PF0_VF4_TDISP_STATE__SHIFT                                      0x0
+#define BIF_DEV0_PF0_VF4_TDISP_CNTL__BIF_DEV0_PF0_VF4_LOCK_INTERFACE_REQUEST__SHIFT                           0x4
+#define BIF_DEV0_PF0_VF4_TDISP_CNTL__BIF_DEV0_PF0_VF4_START_INTERFACE_REQUEST__SHIFT                          0x5
+#define BIF_DEV0_PF0_VF4_TDISP_CNTL__BIF_DEV0_PF0_VF4_STOP_INTERFACE_REQUEST__SHIFT                           0x7
+#define BIF_DEV0_PF0_VF4_TDISP_CNTL__BIF_DEV0_PF0_VF4_INTERFACE_ERROR__SHIFT                                  0x8
+#define BIF_DEV0_PF0_VF4_TDISP_CNTL__BIF_DEV0_PF0_VF4_TDISP_STATE_MASK                                        0x00000007L
+#define BIF_DEV0_PF0_VF4_TDISP_CNTL__BIF_DEV0_PF0_VF4_LOCK_INTERFACE_REQUEST_MASK                             0x00000010L
+#define BIF_DEV0_PF0_VF4_TDISP_CNTL__BIF_DEV0_PF0_VF4_START_INTERFACE_REQUEST_MASK                            0x00000020L
+#define BIF_DEV0_PF0_VF4_TDISP_CNTL__BIF_DEV0_PF0_VF4_STOP_INTERFACE_REQUEST_MASK                             0x00000080L
+#define BIF_DEV0_PF0_VF4_TDISP_CNTL__BIF_DEV0_PF0_VF4_INTERFACE_ERROR_MASK                                    0x00000100L
+//BIF_DEV0_PF0_VF5_TDISP_CNTL
+#define BIF_DEV0_PF0_VF5_TDISP_CNTL__BIF_DEV0_PF0_VF5_TDISP_STATE__SHIFT                                      0x0
+#define BIF_DEV0_PF0_VF5_TDISP_CNTL__BIF_DEV0_PF0_VF5_LOCK_INTERFACE_REQUEST__SHIFT                           0x4
+#define BIF_DEV0_PF0_VF5_TDISP_CNTL__BIF_DEV0_PF0_VF5_START_INTERFACE_REQUEST__SHIFT                          0x5
+#define BIF_DEV0_PF0_VF5_TDISP_CNTL__BIF_DEV0_PF0_VF5_STOP_INTERFACE_REQUEST__SHIFT                           0x7
+#define BIF_DEV0_PF0_VF5_TDISP_CNTL__BIF_DEV0_PF0_VF5_INTERFACE_ERROR__SHIFT                                  0x8
+#define BIF_DEV0_PF0_VF5_TDISP_CNTL__BIF_DEV0_PF0_VF5_TDISP_STATE_MASK                                        0x00000007L
+#define BIF_DEV0_PF0_VF5_TDISP_CNTL__BIF_DEV0_PF0_VF5_LOCK_INTERFACE_REQUEST_MASK                             0x00000010L
+#define BIF_DEV0_PF0_VF5_TDISP_CNTL__BIF_DEV0_PF0_VF5_START_INTERFACE_REQUEST_MASK                            0x00000020L
+#define BIF_DEV0_PF0_VF5_TDISP_CNTL__BIF_DEV0_PF0_VF5_STOP_INTERFACE_REQUEST_MASK                             0x00000080L
+#define BIF_DEV0_PF0_VF5_TDISP_CNTL__BIF_DEV0_PF0_VF5_INTERFACE_ERROR_MASK                                    0x00000100L
+//BIF_DEV0_PF0_VF6_TDISP_CNTL
+#define BIF_DEV0_PF0_VF6_TDISP_CNTL__BIF_DEV0_PF0_VF6_TDISP_STATE__SHIFT                                      0x0
+#define BIF_DEV0_PF0_VF6_TDISP_CNTL__BIF_DEV0_PF0_VF6_LOCK_INTERFACE_REQUEST__SHIFT                           0x4
+#define BIF_DEV0_PF0_VF6_TDISP_CNTL__BIF_DEV0_PF0_VF6_START_INTERFACE_REQUEST__SHIFT                          0x5
+#define BIF_DEV0_PF0_VF6_TDISP_CNTL__BIF_DEV0_PF0_VF6_STOP_INTERFACE_REQUEST__SHIFT                           0x7
+#define BIF_DEV0_PF0_VF6_TDISP_CNTL__BIF_DEV0_PF0_VF6_INTERFACE_ERROR__SHIFT                                  0x8
+#define BIF_DEV0_PF0_VF6_TDISP_CNTL__BIF_DEV0_PF0_VF6_TDISP_STATE_MASK                                        0x00000007L
+#define BIF_DEV0_PF0_VF6_TDISP_CNTL__BIF_DEV0_PF0_VF6_LOCK_INTERFACE_REQUEST_MASK                             0x00000010L
+#define BIF_DEV0_PF0_VF6_TDISP_CNTL__BIF_DEV0_PF0_VF6_START_INTERFACE_REQUEST_MASK                            0x00000020L
+#define BIF_DEV0_PF0_VF6_TDISP_CNTL__BIF_DEV0_PF0_VF6_STOP_INTERFACE_REQUEST_MASK                             0x00000080L
+#define BIF_DEV0_PF0_VF6_TDISP_CNTL__BIF_DEV0_PF0_VF6_INTERFACE_ERROR_MASK                                    0x00000100L
+//BIF_DEV0_PF0_VF7_TDISP_CNTL
+#define BIF_DEV0_PF0_VF7_TDISP_CNTL__BIF_DEV0_PF0_VF7_TDISP_STATE__SHIFT                                      0x0
+#define BIF_DEV0_PF0_VF7_TDISP_CNTL__BIF_DEV0_PF0_VF7_LOCK_INTERFACE_REQUEST__SHIFT                           0x4
+#define BIF_DEV0_PF0_VF7_TDISP_CNTL__BIF_DEV0_PF0_VF7_START_INTERFACE_REQUEST__SHIFT                          0x5
+#define BIF_DEV0_PF0_VF7_TDISP_CNTL__BIF_DEV0_PF0_VF7_STOP_INTERFACE_REQUEST__SHIFT                           0x7
+#define BIF_DEV0_PF0_VF7_TDISP_CNTL__BIF_DEV0_PF0_VF7_INTERFACE_ERROR__SHIFT                                  0x8
+#define BIF_DEV0_PF0_VF7_TDISP_CNTL__BIF_DEV0_PF0_VF7_TDISP_STATE_MASK                                        0x00000007L
+#define BIF_DEV0_PF0_VF7_TDISP_CNTL__BIF_DEV0_PF0_VF7_LOCK_INTERFACE_REQUEST_MASK                             0x00000010L
+#define BIF_DEV0_PF0_VF7_TDISP_CNTL__BIF_DEV0_PF0_VF7_START_INTERFACE_REQUEST_MASK                            0x00000020L
+#define BIF_DEV0_PF0_VF7_TDISP_CNTL__BIF_DEV0_PF0_VF7_STOP_INTERFACE_REQUEST_MASK                             0x00000080L
+#define BIF_DEV0_PF0_VF7_TDISP_CNTL__BIF_DEV0_PF0_VF7_INTERFACE_ERROR_MASK                                    0x00000100L
+//BIF_DEV0_PF1_VF0_TDISP_CNTL
+#define BIF_DEV0_PF1_VF0_TDISP_CNTL__BIF_DEV0_PF1_VF0_TDISP_STATE__SHIFT                                      0x0
+#define BIF_DEV0_PF1_VF0_TDISP_CNTL__BIF_DEV0_PF1_VF0_LOCK_INTERFACE_REQUEST__SHIFT                           0x4
+#define BIF_DEV0_PF1_VF0_TDISP_CNTL__BIF_DEV0_PF1_VF0_START_INTERFACE_REQUEST__SHIFT                          0x5
+#define BIF_DEV0_PF1_VF0_TDISP_CNTL__BIF_DEV0_PF1_VF0_STOP_INTERFACE_REQUEST__SHIFT                           0x7
+#define BIF_DEV0_PF1_VF0_TDISP_CNTL__BIF_DEV0_PF1_VF0_INTERFACE_ERROR__SHIFT                                  0x8
+#define BIF_DEV0_PF1_VF0_TDISP_CNTL__BIF_DEV0_PF1_VF0_TDISP_STATE_MASK                                        0x00000007L
+#define BIF_DEV0_PF1_VF0_TDISP_CNTL__BIF_DEV0_PF1_VF0_LOCK_INTERFACE_REQUEST_MASK                             0x00000010L
+#define BIF_DEV0_PF1_VF0_TDISP_CNTL__BIF_DEV0_PF1_VF0_START_INTERFACE_REQUEST_MASK                            0x00000020L
+#define BIF_DEV0_PF1_VF0_TDISP_CNTL__BIF_DEV0_PF1_VF0_STOP_INTERFACE_REQUEST_MASK                             0x00000080L
+#define BIF_DEV0_PF1_VF0_TDISP_CNTL__BIF_DEV0_PF1_VF0_INTERFACE_ERROR_MASK                                    0x00000100L
+//BIF_TDISP_ERROR_DEV0_PF0_INST0
+#define BIF_TDISP_ERROR_DEV0_PF0_INST0__BIF_TDISP_ERROR_DEV0_PF0_INST0__SHIFT                                 0x0
+#define BIF_TDISP_ERROR_DEV0_PF0_INST0__BIF_TDISP_ERROR_DEV0_PF0_INST0_MASK                                   0xFFFFFFFFL
+//BIF_TDISP_ERROR_DEV0_PF1_INST0
+#define BIF_TDISP_ERROR_DEV0_PF1_INST0__BIF_TDISP_ERROR_DEV0_PF1_INST0__SHIFT                                 0x0
+#define BIF_TDISP_ERROR_DEV0_PF1_INST0__BIF_TDISP_ERROR_DEV0_PF1_INST0_MASK                                   0xFFFFFFFFL
+//BIF_TDISP_UNLOCKED_DEV0_PF0_INST0
+#define BIF_TDISP_UNLOCKED_DEV0_PF0_INST0__BIF_TDISP_UNLOCKED_DEV0_PF0_INST0__SHIFT                           0x0
+#define BIF_TDISP_UNLOCKED_DEV0_PF0_INST0__BIF_TDISP_UNLOCKED_DEV0_PF0_INST0_MASK                             0xFFFFFFFFL
+//BIF_TDISP_UNLOCKED_DEV0_PF1_INST0
+#define BIF_TDISP_UNLOCKED_DEV0_PF1_INST0__BIF_TDISP_UNLOCKED_DEV0_PF1_INST0__SHIFT                           0x0
+#define BIF_TDISP_UNLOCKED_DEV0_PF1_INST0__BIF_TDISP_UNLOCKED_DEV0_PF1_INST0_MASK                             0xFFFFFFFFL
+//BIF_TDISP_MISC_CNTL_DEV0
+#define BIF_TDISP_MISC_CNTL_DEV0__BIF_RC_CONFIG_MONITOR_EN_DEV0__SHIFT                                        0x0
+#define BIF_TDISP_MISC_CNTL_DEV0__TRIG_TO_ERR_NOT_IN_UNLOCK_FOR_VF_DEV0_PF0__SHIFT                            0x5
+#define BIF_TDISP_MISC_CNTL_DEV0__TRIG_TO_UNLOCK_NOT_IN_ERR_FOR_VF_DEV0_PF0__SHIFT                            0x6
+#define BIF_TDISP_MISC_CNTL_DEV0__TRIG_TO_ERR_FOR_VF_DEV0_PF0__SHIFT                                          0x7
+#define BIF_TDISP_MISC_CNTL_DEV0__TRIG_TO_UNLOCK_FOR_VF_DEV0_PF0__SHIFT                                       0x8
+#define BIF_TDISP_MISC_CNTL_DEV0__TRIG_TO_ERR_NOT_IN_UNLOCK_FOR_VF_DEV0_PF1__SHIFT                            0x9
+#define BIF_TDISP_MISC_CNTL_DEV0__TRIG_TO_UNLOCK_NOT_IN_ERR_FOR_VF_DEV0_PF1__SHIFT                            0xa
+#define BIF_TDISP_MISC_CNTL_DEV0__TRIG_TO_ERR_FOR_VF_DEV0_PF1__SHIFT                                          0xb
+#define BIF_TDISP_MISC_CNTL_DEV0__TRIG_TO_UNLOCK_FOR_VF_DEV0_PF1__SHIFT                                       0xc
+#define BIF_TDISP_MISC_CNTL_DEV0__BIF_RC_CONFIG_MONITOR_EN_DEV0_MASK                                          0x00000001L
+#define BIF_TDISP_MISC_CNTL_DEV0__TRIG_TO_ERR_NOT_IN_UNLOCK_FOR_VF_DEV0_PF0_MASK                              0x00000020L
+#define BIF_TDISP_MISC_CNTL_DEV0__TRIG_TO_UNLOCK_NOT_IN_ERR_FOR_VF_DEV0_PF0_MASK                              0x00000040L
+#define BIF_TDISP_MISC_CNTL_DEV0__TRIG_TO_ERR_FOR_VF_DEV0_PF0_MASK                                            0x00000080L
+#define BIF_TDISP_MISC_CNTL_DEV0__TRIG_TO_UNLOCK_FOR_VF_DEV0_PF0_MASK                                         0x00000100L
+#define BIF_TDISP_MISC_CNTL_DEV0__TRIG_TO_ERR_NOT_IN_UNLOCK_FOR_VF_DEV0_PF1_MASK                              0x00000200L
+#define BIF_TDISP_MISC_CNTL_DEV0__TRIG_TO_UNLOCK_NOT_IN_ERR_FOR_VF_DEV0_PF1_MASK                              0x00000400L
+#define BIF_TDISP_MISC_CNTL_DEV0__TRIG_TO_ERR_FOR_VF_DEV0_PF1_MASK                                            0x00000800L
+#define BIF_TDISP_MISC_CNTL_DEV0__TRIG_TO_UNLOCK_FOR_VF_DEV0_PF1_MASK                                         0x00001000L
+//BIF_TDISP_MISC_CNTL
+#define BIF_TDISP_MISC_CNTL__BIF_MSI_MSIX_IDE_TBIT_OVERRIDE__SHIFT                                            0x0
+#define BIF_TDISP_MISC_CNTL__REMOTE_TDISP_STATE_VECTOR_CLR__SHIFT                                             0x1
+#define BIF_TDISP_MISC_CNTL__NBIF_GMI_TDISP_REMOTE_TX_EN__SHIFT                                               0x3
+#define BIF_TDISP_MISC_CNTL__BIF_TRUSTED_IO_ERR_Intr_0_MASK__SHIFT                                            0x4
+#define BIF_TDISP_MISC_CNTL__DSPT_CFG_RST_TRIG_TO_UNLOCK_MASK__SHIFT                                          0xa
+#define BIF_TDISP_MISC_CNTL__EP_CFG_RST_TRIG_TO_UNLOCK_MASK__SHIFT                                            0xb
+#define BIF_TDISP_MISC_CNTL__TDISP_ERR_AER_DIS__SHIFT                                                         0xc
+#define BIF_TDISP_MISC_CNTL__TDISP_ERR_PRGR_AER_EN__SHIFT                                                     0xd
+#define BIF_TDISP_MISC_CNTL__BIF_TBIT_FOR_RUN_BIH_MEM__SHIFT                                                  0xe
+#define BIF_TDISP_MISC_CNTL__BIF_XT1_FOR_RUN_BIH_MEM__SHIFT                                                   0xf
+#define BIF_TDISP_MISC_CNTL__BIF_MSI_MSIX_IDE_TBIT_OVERRIDE_MASK                                              0x00000001L
+#define BIF_TDISP_MISC_CNTL__REMOTE_TDISP_STATE_VECTOR_CLR_MASK                                               0x00000002L
+#define BIF_TDISP_MISC_CNTL__NBIF_GMI_TDISP_REMOTE_TX_EN_MASK                                                 0x00000008L
+#define BIF_TDISP_MISC_CNTL__BIF_TRUSTED_IO_ERR_Intr_0_MASK_MASK                                              0x00000010L
+#define BIF_TDISP_MISC_CNTL__DSPT_CFG_RST_TRIG_TO_UNLOCK_MASK_MASK                                            0x00000400L
+#define BIF_TDISP_MISC_CNTL__EP_CFG_RST_TRIG_TO_UNLOCK_MASK_MASK                                              0x00000800L
+#define BIF_TDISP_MISC_CNTL__TDISP_ERR_AER_DIS_MASK                                                           0x00001000L
+#define BIF_TDISP_MISC_CNTL__TDISP_ERR_PRGR_AER_EN_MASK                                                       0x00002000L
+#define BIF_TDISP_MISC_CNTL__BIF_TBIT_FOR_RUN_BIH_MEM_MASK                                                    0x00004000L
+#define BIF_TDISP_MISC_CNTL__BIF_XT1_FOR_RUN_BIH_MEM_MASK                                                     0x00008000L
+//BIF_RCC_IDE_TDISP_CNTL
+#define BIF_RCC_IDE_TDISP_CNTL__BIF_RCC_IDE_TDISP_PRGR_CHECK_EN__SHIFT                                        0x0
+#define BIF_RCC_IDE_TDISP_CNTL__BIF_RCC_IDE_TDISP_PRGR_FOR_UNLOCK_CHECK_EN__SHIFT                             0x1
+#define BIF_RCC_IDE_TDISP_CNTL__BIF_RCC_IDE_CHECK_EN__SHIFT                                                   0x2
+#define BIF_RCC_IDE_TDISP_CNTL__BIF_RCC_IDE_TDISP_PRGR_CHECK_EN_MASK                                          0x00000001L
+#define BIF_RCC_IDE_TDISP_CNTL__BIF_RCC_IDE_TDISP_PRGR_FOR_UNLOCK_CHECK_EN_MASK                               0x00000002L
+#define BIF_RCC_IDE_TDISP_CNTL__BIF_RCC_IDE_CHECK_EN_MASK                                                     0x00000004L
+//BIF_DEV0_SELECTIVE_IDE_0_BOUND_PF0_31
+#define BIF_DEV0_SELECTIVE_IDE_0_BOUND_PF0_31__SELECTIVE_IDE_BOUND_PF__SHIFT                                  0x0
+#define BIF_DEV0_SELECTIVE_IDE_0_BOUND_PF0_31__SELECTIVE_IDE_BOUND_PF_MASK                                    0xFFFFFFFFL
+//BIF_DEV0_SELECTIVE_IDE_0_BOUND_PF0_VF0_31
+#define BIF_DEV0_SELECTIVE_IDE_0_BOUND_PF0_VF0_31__SELECTIVE_IDE_BOUND_VF__SHIFT                              0x0
+#define BIF_DEV0_SELECTIVE_IDE_0_BOUND_PF0_VF0_31__SELECTIVE_IDE_BOUND_VF_MASK                                0xFFFFFFFFL
+//BIF_DEV0_SELECTIVE_IDE_0_BOUND_PF1_VF0_31
+#define BIF_DEV0_SELECTIVE_IDE_0_BOUND_PF1_VF0_31__SELECTIVE_IDE_BOUND_VF__SHIFT                              0x0
+#define BIF_DEV0_SELECTIVE_IDE_0_BOUND_PF1_VF0_31__SELECTIVE_IDE_BOUND_VF_MASK                                0xFFFFFFFFL
+//BIF_DEV0_SELECTIVE_IDE_1_BOUND_PF0_31
+#define BIF_DEV0_SELECTIVE_IDE_1_BOUND_PF0_31__SELECTIVE_IDE_BOUND_PF__SHIFT                                  0x0
+#define BIF_DEV0_SELECTIVE_IDE_1_BOUND_PF0_31__SELECTIVE_IDE_BOUND_PF_MASK                                    0xFFFFFFFFL
+//BIF_DEV0_SELECTIVE_IDE_1_BOUND_PF0_VF0_31
+#define BIF_DEV0_SELECTIVE_IDE_1_BOUND_PF0_VF0_31__SELECTIVE_IDE_BOUND_VF__SHIFT                              0x0
+#define BIF_DEV0_SELECTIVE_IDE_1_BOUND_PF0_VF0_31__SELECTIVE_IDE_BOUND_VF_MASK                                0xFFFFFFFFL
+//BIF_DEV0_SELECTIVE_IDE_1_BOUND_PF1_VF0_31
+#define BIF_DEV0_SELECTIVE_IDE_1_BOUND_PF1_VF0_31__SELECTIVE_IDE_BOUND_VF__SHIFT                              0x0
+#define BIF_DEV0_SELECTIVE_IDE_1_BOUND_PF1_VF0_31__SELECTIVE_IDE_BOUND_VF_MASK                                0xFFFFFFFFL
+//BIF_DEV0_SELECTIVE_IDE_2_BOUND_PF0_31
+#define BIF_DEV0_SELECTIVE_IDE_2_BOUND_PF0_31__SELECTIVE_IDE_BOUND_PF__SHIFT                                  0x0
+#define BIF_DEV0_SELECTIVE_IDE_2_BOUND_PF0_31__SELECTIVE_IDE_BOUND_PF_MASK                                    0xFFFFFFFFL
+//BIF_DEV0_SELECTIVE_IDE_2_BOUND_PF0_VF0_31
+#define BIF_DEV0_SELECTIVE_IDE_2_BOUND_PF0_VF0_31__SELECTIVE_IDE_BOUND_VF__SHIFT                              0x0
+#define BIF_DEV0_SELECTIVE_IDE_2_BOUND_PF0_VF0_31__SELECTIVE_IDE_BOUND_VF_MASK                                0xFFFFFFFFL
+//BIF_DEV0_SELECTIVE_IDE_2_BOUND_PF1_VF0_31
+#define BIF_DEV0_SELECTIVE_IDE_2_BOUND_PF1_VF0_31__SELECTIVE_IDE_BOUND_VF__SHIFT                              0x0
+#define BIF_DEV0_SELECTIVE_IDE_2_BOUND_PF1_VF0_31__SELECTIVE_IDE_BOUND_VF_MASK                                0xFFFFFFFFL
+//BIF_DEV0_SELECTIVE_IDE_3_BOUND_PF0_31
+#define BIF_DEV0_SELECTIVE_IDE_3_BOUND_PF0_31__SELECTIVE_IDE_BOUND_PF__SHIFT                                  0x0
+#define BIF_DEV0_SELECTIVE_IDE_3_BOUND_PF0_31__SELECTIVE_IDE_BOUND_PF_MASK                                    0xFFFFFFFFL
+//BIF_DEV0_SELECTIVE_IDE_3_BOUND_PF0_VF0_31
+#define BIF_DEV0_SELECTIVE_IDE_3_BOUND_PF0_VF0_31__SELECTIVE_IDE_BOUND_VF__SHIFT                              0x0
+#define BIF_DEV0_SELECTIVE_IDE_3_BOUND_PF0_VF0_31__SELECTIVE_IDE_BOUND_VF_MASK                                0xFFFFFFFFL
+//BIF_DEV0_SELECTIVE_IDE_3_BOUND_PF1_VF0_31
+#define BIF_DEV0_SELECTIVE_IDE_3_BOUND_PF1_VF0_31__SELECTIVE_IDE_BOUND_VF__SHIFT                              0x0
+#define BIF_DEV0_SELECTIVE_IDE_3_BOUND_PF1_VF0_31__SELECTIVE_IDE_BOUND_VF_MASK                                0xFFFFFFFFL
+//BIF_DEV0_SELECTIVE_IDE_4_BOUND_PF0_31
+#define BIF_DEV0_SELECTIVE_IDE_4_BOUND_PF0_31__SELECTIVE_IDE_BOUND_PF__SHIFT                                  0x0
+#define BIF_DEV0_SELECTIVE_IDE_4_BOUND_PF0_31__SELECTIVE_IDE_BOUND_PF_MASK                                    0xFFFFFFFFL
+//BIF_DEV0_SELECTIVE_IDE_4_BOUND_PF0_VF0_31
+#define BIF_DEV0_SELECTIVE_IDE_4_BOUND_PF0_VF0_31__SELECTIVE_IDE_BOUND_VF__SHIFT                              0x0
+#define BIF_DEV0_SELECTIVE_IDE_4_BOUND_PF0_VF0_31__SELECTIVE_IDE_BOUND_VF_MASK                                0xFFFFFFFFL
+//BIF_DEV0_SELECTIVE_IDE_4_BOUND_PF1_VF0_31
+#define BIF_DEV0_SELECTIVE_IDE_4_BOUND_PF1_VF0_31__SELECTIVE_IDE_BOUND_VF__SHIFT                              0x0
+#define BIF_DEV0_SELECTIVE_IDE_4_BOUND_PF1_VF0_31__SELECTIVE_IDE_BOUND_VF_MASK                                0xFFFFFFFFL
+//BIF_DEV0_SELECTIVE_IDE_5_BOUND_PF0_31
+#define BIF_DEV0_SELECTIVE_IDE_5_BOUND_PF0_31__SELECTIVE_IDE_BOUND_PF__SHIFT                                  0x0
+#define BIF_DEV0_SELECTIVE_IDE_5_BOUND_PF0_31__SELECTIVE_IDE_BOUND_PF_MASK                                    0xFFFFFFFFL
+//BIF_DEV0_SELECTIVE_IDE_5_BOUND_PF0_VF0_31
+#define BIF_DEV0_SELECTIVE_IDE_5_BOUND_PF0_VF0_31__SELECTIVE_IDE_BOUND_VF__SHIFT                              0x0
+#define BIF_DEV0_SELECTIVE_IDE_5_BOUND_PF0_VF0_31__SELECTIVE_IDE_BOUND_VF_MASK                                0xFFFFFFFFL
+//BIF_DEV0_SELECTIVE_IDE_5_BOUND_PF1_VF0_31
+#define BIF_DEV0_SELECTIVE_IDE_5_BOUND_PF1_VF0_31__SELECTIVE_IDE_BOUND_VF__SHIFT                              0x0
+#define BIF_DEV0_SELECTIVE_IDE_5_BOUND_PF1_VF0_31__SELECTIVE_IDE_BOUND_VF_MASK                                0xFFFFFFFFL
+//BIF_DEV0_SELECTIVE_IDE_6_BOUND_PF0_31
+#define BIF_DEV0_SELECTIVE_IDE_6_BOUND_PF0_31__SELECTIVE_IDE_BOUND_PF__SHIFT                                  0x0
+#define BIF_DEV0_SELECTIVE_IDE_6_BOUND_PF0_31__SELECTIVE_IDE_BOUND_PF_MASK                                    0xFFFFFFFFL
+//BIF_DEV0_SELECTIVE_IDE_6_BOUND_PF0_VF0_31
+#define BIF_DEV0_SELECTIVE_IDE_6_BOUND_PF0_VF0_31__SELECTIVE_IDE_BOUND_VF__SHIFT                              0x0
+#define BIF_DEV0_SELECTIVE_IDE_6_BOUND_PF0_VF0_31__SELECTIVE_IDE_BOUND_VF_MASK                                0xFFFFFFFFL
+//BIF_DEV0_SELECTIVE_IDE_6_BOUND_PF1_VF0_31
+#define BIF_DEV0_SELECTIVE_IDE_6_BOUND_PF1_VF0_31__SELECTIVE_IDE_BOUND_VF__SHIFT                              0x0
+#define BIF_DEV0_SELECTIVE_IDE_6_BOUND_PF1_VF0_31__SELECTIVE_IDE_BOUND_VF_MASK                                0xFFFFFFFFL
+//BIF_DEV0_SELECTIVE_IDE_7_BOUND_PF0_31
+#define BIF_DEV0_SELECTIVE_IDE_7_BOUND_PF0_31__SELECTIVE_IDE_BOUND_PF__SHIFT                                  0x0
+#define BIF_DEV0_SELECTIVE_IDE_7_BOUND_PF0_31__SELECTIVE_IDE_BOUND_PF_MASK                                    0xFFFFFFFFL
+//BIF_DEV0_SELECTIVE_IDE_7_BOUND_PF0_VF0_31
+#define BIF_DEV0_SELECTIVE_IDE_7_BOUND_PF0_VF0_31__SELECTIVE_IDE_BOUND_VF__SHIFT                              0x0
+#define BIF_DEV0_SELECTIVE_IDE_7_BOUND_PF0_VF0_31__SELECTIVE_IDE_BOUND_VF_MASK                                0xFFFFFFFFL
+//BIF_DEV0_SELECTIVE_IDE_7_BOUND_PF1_VF0_31
+#define BIF_DEV0_SELECTIVE_IDE_7_BOUND_PF1_VF0_31__SELECTIVE_IDE_BOUND_VF__SHIFT                              0x0
+#define BIF_DEV0_SELECTIVE_IDE_7_BOUND_PF1_VF0_31__SELECTIVE_IDE_BOUND_VF_MASK                                0xFFFFFFFFL
+//BIF_DEV0_SELECTIVE_IDE_8_BOUND_PF0_31
+#define BIF_DEV0_SELECTIVE_IDE_8_BOUND_PF0_31__SELECTIVE_IDE_BOUND_PF__SHIFT                                  0x0
+#define BIF_DEV0_SELECTIVE_IDE_8_BOUND_PF0_31__SELECTIVE_IDE_BOUND_PF_MASK                                    0xFFFFFFFFL
+//BIF_DEV0_SELECTIVE_IDE_8_BOUND_PF0_VF0_31
+#define BIF_DEV0_SELECTIVE_IDE_8_BOUND_PF0_VF0_31__SELECTIVE_IDE_BOUND_VF__SHIFT                              0x0
+#define BIF_DEV0_SELECTIVE_IDE_8_BOUND_PF0_VF0_31__SELECTIVE_IDE_BOUND_VF_MASK                                0xFFFFFFFFL
+//BIF_DEV0_SELECTIVE_IDE_8_BOUND_PF1_VF0_31
+#define BIF_DEV0_SELECTIVE_IDE_8_BOUND_PF1_VF0_31__SELECTIVE_IDE_BOUND_VF__SHIFT                              0x0
+#define BIF_DEV0_SELECTIVE_IDE_8_BOUND_PF1_VF0_31__SELECTIVE_IDE_BOUND_VF_MASK                                0xFFFFFFFFL
+//BIF_SYSTEM_EN
+#define BIF_SYSTEM_EN__BIF_SYSTEM_EN_DEV0_F0__SHIFT                                                           0x0
+#define BIF_SYSTEM_EN__BIF_SYSTEM_EN_DEV0_F0_VF0__SHIFT                                                       0x1
+#define BIF_SYSTEM_EN__BIF_SYSTEM_EN_DEV0_F0_VF1__SHIFT                                                       0x2
+#define BIF_SYSTEM_EN__BIF_SYSTEM_EN_DEV0_F0_VF2__SHIFT                                                       0x3
+#define BIF_SYSTEM_EN__BIF_SYSTEM_EN_DEV0_F0_VF3__SHIFT                                                       0x4
+#define BIF_SYSTEM_EN__BIF_SYSTEM_EN_DEV0_F0_VF4__SHIFT                                                       0x5
+#define BIF_SYSTEM_EN__BIF_SYSTEM_EN_DEV0_F0_VF5__SHIFT                                                       0x6
+#define BIF_SYSTEM_EN__BIF_SYSTEM_EN_DEV0_F0_VF6__SHIFT                                                       0x7
+#define BIF_SYSTEM_EN__BIF_SYSTEM_EN_DEV0_F0_VF7__SHIFT                                                       0x8
+#define BIF_SYSTEM_EN__BIF_SYSTEM_EN_DEV0_F0_MASK                                                             0x00000001L
+#define BIF_SYSTEM_EN__BIF_SYSTEM_EN_DEV0_F0_VF0_MASK                                                         0x00000002L
+#define BIF_SYSTEM_EN__BIF_SYSTEM_EN_DEV0_F0_VF1_MASK                                                         0x00000004L
+#define BIF_SYSTEM_EN__BIF_SYSTEM_EN_DEV0_F0_VF2_MASK                                                         0x00000008L
+#define BIF_SYSTEM_EN__BIF_SYSTEM_EN_DEV0_F0_VF3_MASK                                                         0x00000010L
+#define BIF_SYSTEM_EN__BIF_SYSTEM_EN_DEV0_F0_VF4_MASK                                                         0x00000020L
+#define BIF_SYSTEM_EN__BIF_SYSTEM_EN_DEV0_F0_VF5_MASK                                                         0x00000040L
+#define BIF_SYSTEM_EN__BIF_SYSTEM_EN_DEV0_F0_VF6_MASK                                                         0x00000080L
+#define BIF_SYSTEM_EN__BIF_SYSTEM_EN_DEV0_F0_VF7_MASK                                                         0x00000100L
+//BIF_MASK_SYSTEM_EN
+#define BIF_MASK_SYSTEM_EN__BIF_SYSTEM_EN_MASK_DEV0_F0__SHIFT                                                 0x0
+#define BIF_MASK_SYSTEM_EN__BIF_SYSTEM_EN_MASK_DEV0_F0_VF0__SHIFT                                             0x1
+#define BIF_MASK_SYSTEM_EN__BIF_SYSTEM_EN_MASK_DEV0_F0_VF1__SHIFT                                             0x2
+#define BIF_MASK_SYSTEM_EN__BIF_SYSTEM_EN_MASK_DEV0_F0_VF2__SHIFT                                             0x3
+#define BIF_MASK_SYSTEM_EN__BIF_SYSTEM_EN_MASK_DEV0_F0_VF3__SHIFT                                             0x4
+#define BIF_MASK_SYSTEM_EN__BIF_SYSTEM_EN_MASK_DEV0_F0_VF4__SHIFT                                             0x5
+#define BIF_MASK_SYSTEM_EN__BIF_SYSTEM_EN_MASK_DEV0_F0_VF5__SHIFT                                             0x6
+#define BIF_MASK_SYSTEM_EN__BIF_SYSTEM_EN_MASK_DEV0_F0_VF6__SHIFT                                             0x7
+#define BIF_MASK_SYSTEM_EN__BIF_SYSTEM_EN_MASK_DEV0_F0_VF7__SHIFT                                             0x8
+#define BIF_MASK_SYSTEM_EN__BIF_SYSTEM_EN_MASK_DEV0_F0_MASK                                                   0x00000001L
+#define BIF_MASK_SYSTEM_EN__BIF_SYSTEM_EN_MASK_DEV0_F0_VF0_MASK                                               0x00000002L
+#define BIF_MASK_SYSTEM_EN__BIF_SYSTEM_EN_MASK_DEV0_F0_VF1_MASK                                               0x00000004L
+#define BIF_MASK_SYSTEM_EN__BIF_SYSTEM_EN_MASK_DEV0_F0_VF2_MASK                                               0x00000008L
+#define BIF_MASK_SYSTEM_EN__BIF_SYSTEM_EN_MASK_DEV0_F0_VF3_MASK                                               0x00000010L
+#define BIF_MASK_SYSTEM_EN__BIF_SYSTEM_EN_MASK_DEV0_F0_VF4_MASK                                               0x00000020L
+#define BIF_MASK_SYSTEM_EN__BIF_SYSTEM_EN_MASK_DEV0_F0_VF5_MASK                                               0x00000040L
+#define BIF_MASK_SYSTEM_EN__BIF_SYSTEM_EN_MASK_DEV0_F0_VF6_MASK                                               0x00000080L
+#define BIF_MASK_SYSTEM_EN__BIF_SYSTEM_EN_MASK_DEV0_F0_VF7_MASK                                               0x00000100L
+//GPUIOV_SCH0
+#define GPUIOV_SCH0__REMAP_ADDR__SHIFT                                                                        0x0
+#define GPUIOV_SCH0__REMAP_ADDR_MASK                                                                          0x001FFFFFL
+//GPUIOV_SCH1
+#define GPUIOV_SCH1__REMAP_ADDR__SHIFT                                                                        0x0
+#define GPUIOV_SCH1__REMAP_ADDR_MASK                                                                          0x001FFFFFL
+//GPUIOV_SCH2
+#define GPUIOV_SCH2__REMAP_ADDR__SHIFT                                                                        0x0
+#define GPUIOV_SCH2__REMAP_ADDR_MASK                                                                          0x001FFFFFL
+//GPUIOV_SCH3
+#define GPUIOV_SCH3__REMAP_ADDR__SHIFT                                                                        0x0
+#define GPUIOV_SCH3__REMAP_ADDR_MASK                                                                          0x001FFFFFL
+//GPUIOV_SCH4
+#define GPUIOV_SCH4__REMAP_ADDR__SHIFT                                                                        0x0
+#define GPUIOV_SCH4__REMAP_ADDR_MASK                                                                          0x001FFFFFL
+//GPUIOV_SCH5
+#define GPUIOV_SCH5__REMAP_ADDR__SHIFT                                                                        0x0
+#define GPUIOV_SCH5__REMAP_ADDR_MASK                                                                          0x001FFFFFL
+//GPUIOV_SCH6
+#define GPUIOV_SCH6__REMAP_ADDR__SHIFT                                                                        0x0
+#define GPUIOV_SCH6__REMAP_ADDR_MASK                                                                          0x001FFFFFL
+//GPUIOV_SCH7
+#define GPUIOV_SCH7__REMAP_ADDR__SHIFT                                                                        0x0
+#define GPUIOV_SCH7__REMAP_ADDR_MASK                                                                          0x001FFFFFL
+//GPUIOV_SCH8
+#define GPUIOV_SCH8__REMAP_ADDR__SHIFT                                                                        0x0
+#define GPUIOV_SCH8__REMAP_ADDR_MASK                                                                          0x001FFFFFL
+//GPUIOV_SCH9
+#define GPUIOV_SCH9__REMAP_ADDR__SHIFT                                                                        0x0
+#define GPUIOV_SCH9__REMAP_ADDR_MASK                                                                          0x001FFFFFL
+//GPUIOV_SCH10
+#define GPUIOV_SCH10__REMAP_ADDR__SHIFT                                                                       0x0
+#define GPUIOV_SCH10__REMAP_ADDR_MASK                                                                         0x001FFFFFL
+//GPUIOV_SCH11
+#define GPUIOV_SCH11__REMAP_ADDR__SHIFT                                                                       0x0
+#define GPUIOV_SCH11__REMAP_ADDR_MASK                                                                         0x001FFFFFL
+//GPUIOV_SCH12
+#define GPUIOV_SCH12__REMAP_ADDR__SHIFT                                                                       0x0
+#define GPUIOV_SCH12__REMAP_ADDR_MASK                                                                         0x001FFFFFL
+//GPUIOV_SCH13
+#define GPUIOV_SCH13__REMAP_ADDR__SHIFT                                                                       0x0
+#define GPUIOV_SCH13__REMAP_ADDR_MASK                                                                         0x001FFFFFL
+//GPUIOV_SCH14
+#define GPUIOV_SCH14__REMAP_ADDR__SHIFT                                                                       0x0
+#define GPUIOV_SCH14__REMAP_ADDR_MASK                                                                         0x001FFFFFL
+//GPUIOV_SCH15
+#define GPUIOV_SCH15__REMAP_ADDR__SHIFT                                                                       0x0
+#define GPUIOV_SCH15__REMAP_ADDR_MASK                                                                         0x001FFFFFL
+//GPUIOV_SCH16
+#define GPUIOV_SCH16__REMAP_ADDR__SHIFT                                                                       0x0
+#define GPUIOV_SCH16__REMAP_ADDR_MASK                                                                         0x001FFFFFL
+//GPUIOV_SCH17
+#define GPUIOV_SCH17__REMAP_ADDR__SHIFT                                                                       0x0
+#define GPUIOV_SCH17__REMAP_ADDR_MASK                                                                         0x001FFFFFL
+//GPUIOV_SCH18
+#define GPUIOV_SCH18__REMAP_ADDR__SHIFT                                                                       0x0
+#define GPUIOV_SCH18__REMAP_ADDR_MASK                                                                         0x001FFFFFL
+//GPUIOV_SCH19
+#define GPUIOV_SCH19__REMAP_ADDR__SHIFT                                                                       0x0
+#define GPUIOV_SCH19__REMAP_ADDR_MASK                                                                         0x001FFFFFL
+//GPUIOV_MMHUB_P2P_CNTL
+#define GPUIOV_MMHUB_P2P_CNTL__GPUIOV_MMHUB_P2P_ENABLE_REMAP_ADDR__SHIFT                                      0x0
+#define GPUIOV_MMHUB_P2P_CNTL__GPUIOV_MMHUB_P2P_ENABLE_REMAP_ADDR_MASK                                        0x000FFFFFL
+//BIF_AER_INTR_CTRL
+#define BIF_AER_INTR_CTRL__BIF_AER_INTR_MASK__SHIFT                                                           0x0
+#define BIF_AER_INTR_CTRL__BIF_AER_SMN_POSTED__SHIFT                                                          0x1
+#define BIF_AER_INTR_CTRL__BIF_AER_SMN_WDATA_SEL__SHIFT                                                       0x2
+#define BIF_AER_INTR_CTRL__BIF_AER_INTR_MASK_MASK                                                             0x00000001L
+#define BIF_AER_INTR_CTRL__BIF_AER_SMN_POSTED_MASK                                                            0x00000002L
+#define BIF_AER_INTR_CTRL__BIF_AER_SMN_WDATA_SEL_MASK                                                         0x00000004L
+//BIF_AER_INTR_STS
+#define BIF_AER_INTR_STS__BIF_AER_INTR_STS__SHIFT                                                             0x0
+#define BIF_AER_INTR_STS__BIF_AER_INTR_STS_MASK                                                               0x00000001L
+//BIF_PCIE_MSG_CTRL
+#define BIF_PCIE_MSG_CTRL__BIF_PCIE_MSG_VALID__SHIFT                                                          0x0
+#define BIF_PCIE_MSG_CTRL__BIF_PCIE_MSG_PORTID__SHIFT                                                         0x1
+#define BIF_PCIE_MSG_CTRL__BIF_PCIE_MSG_VF_VALID__SHIFT                                                       0x3
+#define BIF_PCIE_MSG_CTRL__BIF_PCIE_MSG_VFID__SHIFT                                                           0x4
+#define BIF_PCIE_MSG_CTRL__BIF_PCIE_MSG_VALID_MASK                                                            0x00000001L
+#define BIF_PCIE_MSG_CTRL__BIF_PCIE_MSG_PORTID_MASK                                                           0x00000006L
+#define BIF_PCIE_MSG_CTRL__BIF_PCIE_MSG_VF_VALID_MASK                                                         0x00000008L
+#define BIF_PCIE_MSG_CTRL__BIF_PCIE_MSG_VFID_MASK                                                             0x00003FF0L
+//BIF_PCIE_MSG_HEADER_DW0
+#define BIF_PCIE_MSG_HEADER_DW0__BIF_PCIE_MSG_HEADER_DW0__SHIFT                                               0x0
+#define BIF_PCIE_MSG_HEADER_DW0__BIF_PCIE_MSG_HEADER_DW0_MASK                                                 0xFFFFFFFFL
+//BIF_PCIE_MSG_HEADER_DW1
+#define BIF_PCIE_MSG_HEADER_DW1__BIF_PCIE_MSG_HEADER_DW1__SHIFT                                               0x0
+#define BIF_PCIE_MSG_HEADER_DW1__BIF_PCIE_MSG_HEADER_DW1_MASK                                                 0xFFFFFFFFL
+//BIF_PCIE_MSG_HEADER_DW2
+#define BIF_PCIE_MSG_HEADER_DW2__BIF_PCIE_MSG_HEADER_DW2__SHIFT                                               0x0
+#define BIF_PCIE_MSG_HEADER_DW2__BIF_PCIE_MSG_HEADER_DW2_MASK                                                 0xFFFFFFFFL
+//BIF_PCIE_MSG_HEADER_DW3
+#define BIF_PCIE_MSG_HEADER_DW3__BIF_PCIE_MSG_HEADER_DW3__SHIFT                                               0x0
+#define BIF_PCIE_MSG_HEADER_DW3__BIF_PCIE_MSG_HEADER_DW3_MASK                                                 0xFFFFFFFFL
+//BIF_PCIE_MSG_DATA_DW0
+#define BIF_PCIE_MSG_DATA_DW0__BIF_PCIE_MSG_DATA_DW0__SHIFT                                                   0x0
+#define BIF_PCIE_MSG_DATA_DW0__BIF_PCIE_MSG_DATA_DW0_MASK                                                     0xFFFFFFFFL
+//BIF_PCIE_MSG_DATA_DW1
+#define BIF_PCIE_MSG_DATA_DW1__BIF_PCIE_MSG_DATA_DW1__SHIFT                                                   0x0
+#define BIF_PCIE_MSG_DATA_DW1__BIF_PCIE_MSG_DATA_DW1_MASK                                                     0xFFFFFFFFL
+//BIF_PCIE_MSG_DATA_DW2
+#define BIF_PCIE_MSG_DATA_DW2__BIF_PCIE_MSG_DATA_DW2__SHIFT                                                   0x0
+#define BIF_PCIE_MSG_DATA_DW2__BIF_PCIE_MSG_DATA_DW2_MASK                                                     0xFFFFFFFFL
+//BIF_PCIE_MSG_DATA_DW3
+#define BIF_PCIE_MSG_DATA_DW3__BIF_PCIE_MSG_DATA_DW3__SHIFT                                                   0x0
+#define BIF_PCIE_MSG_DATA_DW3__BIF_PCIE_MSG_DATA_DW3_MASK                                                     0xFFFFFFFFL
+//BIFC_SEC_AER_SMN_CTRL0
+#define BIFC_SEC_AER_SMN_CTRL0__BIF_AER_INT_REQ_ADDR__SHIFT                                                   0x0
+#define BIFC_SEC_AER_SMN_CTRL0__BIF_AER_INT_REQ_APER_ID__SHIFT                                                0x14
+#define BIFC_SEC_AER_SMN_CTRL0__BIF_AER_INT_REQ_ADDR_MASK                                                     0x000FFFFFL
+#define BIFC_SEC_AER_SMN_CTRL0__BIF_AER_INT_REQ_APER_ID_MASK                                                  0xFFF00000L
+//BIFC_SEC_AER_SMN_CTRL1
+#define BIFC_SEC_AER_SMN_CTRL1__BIF_AER_INT_REQ_MCM_ADDR__SHIFT                                               0x0
+#define BIFC_SEC_AER_SMN_CTRL1__BIF_AER_SMN_SEC_SEL__SHIFT                                                    0x10
+#define BIFC_SEC_AER_SMN_CTRL1__BIF_AER_INT_REQ_MCM_ADDR_MASK                                                 0x0000FFFFL
+#define BIFC_SEC_AER_SMN_CTRL1__BIF_AER_SMN_SEC_SEL_MASK                                                      0x000F0000L
+//BIFC_SEC_AER_SMN_CTRL2
+#define BIFC_SEC_AER_SMN_CTRL2__BIF_AER_INT_REQ_WDATA__SHIFT                                                  0x0
+#define BIFC_SEC_AER_SMN_CTRL2__BIF_AER_INT_REQ_WDATA_MASK                                                    0xFFFFFFFFL
+//BIF_PCIE_ERR_CTRL0
+#define BIF_PCIE_ERR_CTRL0__BIF_PCIE_ERR_VF_NUM__SHIFT                                                        0x0
+#define BIF_PCIE_ERR_CTRL0__BIF_PCIE_ERR_VF__SHIFT                                                            0x7
+#define BIF_PCIE_ERR_CTRL0__BIF_PCIE_ERR_PF_NUM__SHIFT                                                        0x8
+#define BIF_PCIE_ERR_CTRL0__BIF_PCIE_ERR_VF_NUM_MASK                                                          0x0000007FL
+#define BIF_PCIE_ERR_CTRL0__BIF_PCIE_ERR_VF_MASK                                                              0x00000080L
+#define BIF_PCIE_ERR_CTRL0__BIF_PCIE_ERR_PF_NUM_MASK                                                          0x00000700L
+//BIF_PCIE_ERR_CTRL1
+#define BIF_PCIE_ERR_CTRL1__BIF_CORR_ERR_EN__SHIFT                                                            0x0
+#define BIF_PCIE_ERR_CTRL1__BIF_NON_FATAL_ERR_EN__SHIFT                                                       0x1
+#define BIF_PCIE_ERR_CTRL1__BIF_FATAL_ERR_EN__SHIFT                                                           0x2
+#define BIF_PCIE_ERR_CTRL1__BIF_USR_REPORT_EN__SHIFT                                                          0x3
+#define BIF_PCIE_ERR_CTRL1__BIF_SERR_EN__SHIFT                                                                0x4
+#define BIF_PCIE_ERR_CTRL1__BIF_MASTER_DATA_PARITY_ERROR__SHIFT                                               0x8
+#define BIF_PCIE_ERR_CTRL1__BIF_SIGNALED_SYSTEM_ERROR__SHIFT                                                  0x9
+#define BIF_PCIE_ERR_CTRL1__BIF_PARITY_ERROR_DETECTED__SHIFT                                                  0xa
+#define BIF_PCIE_ERR_CTRL1__BIF_PCIE_DEVICE_STATUS__SHIFT                                                     0x10
+#define BIF_PCIE_ERR_CTRL1__BIF_CORR_ERR_EN_MASK                                                              0x00000001L
+#define BIF_PCIE_ERR_CTRL1__BIF_NON_FATAL_ERR_EN_MASK                                                         0x00000002L
+#define BIF_PCIE_ERR_CTRL1__BIF_FATAL_ERR_EN_MASK                                                             0x00000004L
+#define BIF_PCIE_ERR_CTRL1__BIF_USR_REPORT_EN_MASK                                                            0x00000008L
+#define BIF_PCIE_ERR_CTRL1__BIF_SERR_EN_MASK                                                                  0x00000010L
+#define BIF_PCIE_ERR_CTRL1__BIF_MASTER_DATA_PARITY_ERROR_MASK                                                 0x00000100L
+#define BIF_PCIE_ERR_CTRL1__BIF_SIGNALED_SYSTEM_ERROR_MASK                                                    0x00000200L
+#define BIF_PCIE_ERR_CTRL1__BIF_PARITY_ERROR_DETECTED_MASK                                                    0x00000400L
+#define BIF_PCIE_ERR_CTRL1__BIF_PCIE_DEVICE_STATUS_MASK                                                       0xFFFF0000L
+//BIF_PCIE_ERR_CTRL2
+#define BIF_PCIE_ERR_CTRL2__BIF_AER_FEP__SHIFT                                                                0x0
+#define BIF_PCIE_ERR_CTRL2__BIF_AER_TLP_PREFIX_LOG_PRESENT__SHIFT                                             0xb
+#define BIF_PCIE_ERR_CTRL2__BIF_AER_LOGGED_TLP_SIZE__SHIFT                                                    0x13
+#define BIF_PCIE_ERR_CTRL2__BIF_AER_FEP_MASK                                                                  0x0000001FL
+#define BIF_PCIE_ERR_CTRL2__BIF_AER_TLP_PREFIX_LOG_PRESENT_MASK                                               0x00000800L
+#define BIF_PCIE_ERR_CTRL2__BIF_AER_LOGGED_TLP_SIZE_MASK                                                      0x00F80000L
+//BIF_AER_UNCORR_ERR_STATUS
+#define BIF_AER_UNCORR_ERR_STATUS__BIF_AER_UNCORR_ERR_STATUS__SHIFT                                           0x0
+#define BIF_AER_UNCORR_ERR_STATUS__BIF_AER_UNCORR_ERR_STATUS_MASK                                             0xFFFFFFFFL
+//BIF_AER_UNCORR_ERR_MASK
+#define BIF_AER_UNCORR_ERR_MASK__BIF_AER_UNCORR_ERR_MASK__SHIFT                                               0x0
+#define BIF_AER_UNCORR_ERR_MASK__BIF_AER_UNCORR_ERR_MASK_MASK                                                 0xFFFFFFFFL
+//BIF_AER_UNCORR_ERR_SEVERITY
+#define BIF_AER_UNCORR_ERR_SEVERITY__BIF_AER_UNCORR_ERR_SEVERITY__SHIFT                                       0x0
+#define BIF_AER_UNCORR_ERR_SEVERITY__BIF_AER_UNCORR_ERR_SEVERITY_MASK                                         0xFFFFFFFFL
+//BIF_AER_CORR_ERR_STATUS
+#define BIF_AER_CORR_ERR_STATUS__BIF_AER_CORR_ERR_STATUS__SHIFT                                               0x0
+#define BIF_AER_CORR_ERR_STATUS__BIF_AER_CORR_ERR_STATUS_MASK                                                 0xFFFFFFFFL
+//BIF_AER_CORR_ERR_MASK
+#define BIF_AER_CORR_ERR_MASK__BIF_AER_CORR_ERR_MASK__SHIFT                                                   0x0
+#define BIF_AER_CORR_ERR_MASK__BIF_AER_CORR_ERR_MASK_MASK                                                     0xFFFFFFFFL
+//RCC_EP_STICKY_RESTORE_0
+#define RCC_EP_STICKY_RESTORE_0__RESTORE_PCIE_TLP_HDR_0__SHIFT                                                0x0
+#define RCC_EP_STICKY_RESTORE_0__RESTORE_PCIE_TLP_HDR_0_MASK                                                  0xFFFFFFFFL
+//RCC_EP_STICKY_RESTORE_1
+#define RCC_EP_STICKY_RESTORE_1__RESTORE_PCIE_TLP_HDR_1__SHIFT                                                0x0
+#define RCC_EP_STICKY_RESTORE_1__RESTORE_PCIE_TLP_HDR_1_MASK                                                  0xFFFFFFFFL
+//RCC_EP_STICKY_RESTORE_2
+#define RCC_EP_STICKY_RESTORE_2__RESTORE_PCIE_TLP_HDR_2__SHIFT                                                0x0
+#define RCC_EP_STICKY_RESTORE_2__RESTORE_PCIE_TLP_HDR_2_MASK                                                  0xFFFFFFFFL
+//RCC_EP_STICKY_RESTORE_3
+#define RCC_EP_STICKY_RESTORE_3__RESTORE_PCIE_TLP_HDR_3__SHIFT                                                0x0
+#define RCC_EP_STICKY_RESTORE_3__RESTORE_PCIE_TLP_HDR_3_MASK                                                  0xFFFFFFFFL
+//RCC_EP_STICKY_RESTORE_4
+#define RCC_EP_STICKY_RESTORE_4__RESTORE_PCIE_TLP_HDR_4__SHIFT                                                0x0
+#define RCC_EP_STICKY_RESTORE_4__RESTORE_PCIE_TLP_HDR_4_MASK                                                  0xFFFFFFFFL
+//RCC_EP_STICKY_RESTORE_5
+#define RCC_EP_STICKY_RESTORE_5__RESTORE_PCIE_TLP_HDR_5__SHIFT                                                0x0
+#define RCC_EP_STICKY_RESTORE_5__RESTORE_PCIE_TLP_HDR_5_MASK                                                  0xFFFFFFFFL
+//RCC_EP_STICKY_RESTORE_6
+#define RCC_EP_STICKY_RESTORE_6__RESTORE_PCIE_TLP_HDR_6__SHIFT                                                0x0
+#define RCC_EP_STICKY_RESTORE_6__RESTORE_PCIE_TLP_HDR_6_MASK                                                  0xFFFFFFFFL
+//RCC_EP_STICKY_RESTORE_7
+#define RCC_EP_STICKY_RESTORE_7__RESTORE_PCIE_TLP_HDR_7__SHIFT                                                0x0
+#define RCC_EP_STICKY_RESTORE_7__RESTORE_PCIE_TLP_HDR_7_MASK                                                  0xFFFFFFFFL
+//RCC_EP_STICKY_RESTORE_8
+#define RCC_EP_STICKY_RESTORE_8__RESTORE_PCIE_TLP_HDR_8__SHIFT                                                0x0
+#define RCC_EP_STICKY_RESTORE_8__RESTORE_PCIE_TLP_HDR_8_MASK                                                  0xFFFFFFFFL
+//RCC_EP_STICKY_RESTORE_9
+#define RCC_EP_STICKY_RESTORE_9__RESTORE_PCIE_TLP_HDR_9__SHIFT                                                0x0
+#define RCC_EP_STICKY_RESTORE_9__RESTORE_PCIE_TLP_HDR_9_MASK                                                  0xFFFFFFFFL
+//RCC_EP_STICKY_RESTORE_10
+#define RCC_EP_STICKY_RESTORE_10__RESTORE_PCIE_TLP_HDR_10__SHIFT                                              0x0
+#define RCC_EP_STICKY_RESTORE_10__RESTORE_PCIE_TLP_HDR_10_MASK                                                0xFFFFFFFFL
+//RCC_EP_STICKY_RESTORE_11
+#define RCC_EP_STICKY_RESTORE_11__RESTORE_PCIE_TLP_HDR_11__SHIFT                                              0x0
+#define RCC_EP_STICKY_RESTORE_11__RESTORE_PCIE_TLP_HDR_11_MASK                                                0xFFFFFFFFL
+//RCC_EP_STICKY_RESTORE_12
+#define RCC_EP_STICKY_RESTORE_12__RESTORE_PCIE_TLP_HDR_12__SHIFT                                              0x0
+#define RCC_EP_STICKY_RESTORE_12__RESTORE_PCIE_TLP_HDR_12_MASK                                                0xFFFFFFFFL
+//RCC_EP_STICKY_RESTORE_13
+#define RCC_EP_STICKY_RESTORE_13__RESTORE_PCIE_TLP_HDR_13__SHIFT                                              0x0
+#define RCC_EP_STICKY_RESTORE_13__RESTORE_PCIE_TLP_HDR_13_MASK                                                0xFFFFFFFFL
+//BIF_DEVICE3_STATUS
+#define BIF_DEVICE3_STATUS__BIF_DEVICE3_INITIAL_LINK_WIDTH__SHIFT                                             0x0
+#define BIF_DEVICE3_STATUS__BIF_DEVICE3_SEGMENT_CAPTURED__SHIFT                                               0x3
+#define BIF_DEVICE3_STATUS__BIF_DEVICE3_REMOTE_L0P_SUPPORTED__SHIFT                                           0x4
+#define BIF_DEVICE3_STATUS__BIF_DEVICE3_INITIAL_LINK_WIDTH_MASK                                               0x00000007L
+#define BIF_DEVICE3_STATUS__BIF_DEVICE3_SEGMENT_CAPTURED_MASK                                                 0x00000008L
+#define BIF_DEVICE3_STATUS__BIF_DEVICE3_REMOTE_L0P_SUPPORTED_MASK                                             0x00000010L
+//BIFC_SEC_MCTP_SMN_CTRL0
+#define BIFC_SEC_MCTP_SMN_CTRL0__MCTP_INT_REQ_ADDR__SHIFT                                                     0x0
+#define BIFC_SEC_MCTP_SMN_CTRL0__MCTP_INT_REQ_APER_ID__SHIFT                                                  0x14
+#define BIFC_SEC_MCTP_SMN_CTRL0__MCTP_INT_REQ_ADDR_MASK                                                       0x000FFFFFL
+#define BIFC_SEC_MCTP_SMN_CTRL0__MCTP_INT_REQ_APER_ID_MASK                                                    0xFFF00000L
+//BIFC_SEC_MCTP_SMN_CTRL1
+#define BIFC_SEC_MCTP_SMN_CTRL1__MCTP_INT_REQ_MCM_ADDR__SHIFT                                                 0x0
+#define BIFC_SEC_MCTP_SMN_CTRL1__MCTP_SMN_SEC_SEL__SHIFT                                                      0x10
+#define BIFC_SEC_MCTP_SMN_CTRL1__MCTP_INT_REQ_MCM_ADDR_MASK                                                   0x0000FFFFL
+#define BIFC_SEC_MCTP_SMN_CTRL1__MCTP_SMN_SEC_SEL_MASK                                                        0x000F0000L
+//NBIF_MCTP_GENERIC_CNTL
+#define NBIF_MCTP_GENERIC_CNTL__NBIF_MCTP_SUPPORT__SHIFT                                                      0x0
+#define NBIF_MCTP_GENERIC_CNTL__NBIF_MCTP_ROUTING_CODE_CHECK__SHIFT                                           0x1
+#define NBIF_MCTP_GENERIC_CNTL__NBIF_MCTP_RBID_CPLID_CNTL__SHIFT                                              0x2
+#define NBIF_MCTP_GENERIC_CNTL__NBIF_MCTP_SUPPORT_MASK                                                        0x00000001L
+#define NBIF_MCTP_GENERIC_CNTL__NBIF_MCTP_ROUTING_CODE_CHECK_MASK                                             0x00000002L
+#define NBIF_MCTP_GENERIC_CNTL__NBIF_MCTP_RBID_CPLID_CNTL_MASK                                                0x00000004L
+//NBIF_MCTP_GENERIC_STATUS
+#define NBIF_MCTP_GENERIC_STATUS__NBIF_MCTP_ERR_FLAG__SHIFT                                                   0x0
+#define NBIF_MCTP_GENERIC_STATUS__NBIF_MCTP_RB_EMPTY_STATUS__SHIFT                                            0x1
+#define NBIF_MCTP_GENERIC_STATUS__NBIF_MCTP_RB_FULL_STATUS__SHIFT                                             0x2
+#define NBIF_MCTP_GENERIC_STATUS__NBIF_MCTP_ERR_FLAG_MASK                                                     0x00000001L
+#define NBIF_MCTP_GENERIC_STATUS__NBIF_MCTP_RB_EMPTY_STATUS_MASK                                              0x00000002L
+#define NBIF_MCTP_GENERIC_STATUS__NBIF_MCTP_RB_FULL_STATUS_MASK                                               0x00000004L
+//SDPVW_UPDATE_EN
+#define SDPVW_UPDATE_EN__SDPVW_UPDATE_EN__SHIFT                                                               0x0
+#define SDPVW_UPDATE_EN__SWUS_SECBUSRST_SET_EN__SHIFT                                                         0x1
+#define SDPVW_UPDATE_EN__SDPVW_UPDATE_EN_MASK                                                                 0x01L
+#define SDPVW_UPDATE_EN__SWUS_SECBUSRST_SET_EN_MASK                                                           0x02L
+//REGS_ROM_OFFSET_CTRL
+#define REGS_ROM_OFFSET_CTRL__ROM_OFFSET__SHIFT                                                               0x0
+#define REGS_ROM_OFFSET_CTRL__ROM_OFFSET_MASK                                                                 0x7FL
+//BIFL_SEC_RAS_POISON_DATA_DROP_CTRL
+#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF0_POISON_DATA_DROP_EN__SHIFT                     0x0
+#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF1_POISON_DATA_DROP_EN__SHIFT                     0x1
+#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF2_POISON_DATA_DROP_EN__SHIFT                     0x2
+#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF3_POISON_DATA_DROP_EN__SHIFT                     0x3
+#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF4_POISON_DATA_DROP_EN__SHIFT                     0x4
+#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF5_POISON_DATA_DROP_EN__SHIFT                     0x5
+#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF6_POISON_DATA_DROP_EN__SHIFT                     0x6
+#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF7_POISON_DATA_DROP_EN__SHIFT                     0x7
+#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF8_POISON_DATA_DROP_EN__SHIFT                     0x8
+#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF9_POISON_DATA_DROP_EN__SHIFT                     0x9
+#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF10_POISON_DATA_DROP_EN__SHIFT                    0xa
+#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF11_POISON_DATA_DROP_EN__SHIFT                    0xb
+#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF12_POISON_DATA_DROP_EN__SHIFT                    0xc
+#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF13_POISON_DATA_DROP_EN__SHIFT                    0xd
+#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF14_POISON_DATA_DROP_EN__SHIFT                    0xe
+#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF15_POISON_DATA_DROP_EN__SHIFT                    0xf
+#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF16_POISON_DATA_DROP_EN__SHIFT                    0x10
+#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF17_POISON_DATA_DROP_EN__SHIFT                    0x11
+#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF18_POISON_DATA_DROP_EN__SHIFT                    0x12
+#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF19_POISON_DATA_DROP_EN__SHIFT                    0x13
+#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF0_POISON_DATA_DROP_EN_MASK                       0x00000001L
+#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF1_POISON_DATA_DROP_EN_MASK                       0x00000002L
+#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF2_POISON_DATA_DROP_EN_MASK                       0x00000004L
+#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF3_POISON_DATA_DROP_EN_MASK                       0x00000008L
+#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF4_POISON_DATA_DROP_EN_MASK                       0x00000010L
+#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF5_POISON_DATA_DROP_EN_MASK                       0x00000020L
+#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF6_POISON_DATA_DROP_EN_MASK                       0x00000040L
+#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF7_POISON_DATA_DROP_EN_MASK                       0x00000080L
+#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF8_POISON_DATA_DROP_EN_MASK                       0x00000100L
+#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF9_POISON_DATA_DROP_EN_MASK                       0x00000200L
+#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF10_POISON_DATA_DROP_EN_MASK                      0x00000400L
+#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF11_POISON_DATA_DROP_EN_MASK                      0x00000800L
+#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF12_POISON_DATA_DROP_EN_MASK                      0x00001000L
+#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF13_POISON_DATA_DROP_EN_MASK                      0x00002000L
+#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF14_POISON_DATA_DROP_EN_MASK                      0x00004000L
+#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF15_POISON_DATA_DROP_EN_MASK                      0x00008000L
+#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF16_POISON_DATA_DROP_EN_MASK                      0x00010000L
+#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF17_POISON_DATA_DROP_EN_MASK                      0x00020000L
+#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF18_POISON_DATA_DROP_EN_MASK                      0x00040000L
+#define BIFL_SEC_RAS_POISON_DATA_DROP_CTRL__BIFL_SEC_RAS_LEAF19_POISON_DATA_DROP_EN_MASK                      0x00080000L
+//REGS_INDEX_DATA_PAIR_CTRL
+#define REGS_INDEX_DATA_PAIR_CTRL__MM_DATA_DIS__SHIFT                                                         0x0
+#define REGS_INDEX_DATA_PAIR_CTRL__SYSHUB_DATA_DIS__SHIFT                                                     0x1
+#define REGS_INDEX_DATA_PAIR_CTRL__PCIE_DATA_DIS__SHIFT                                                       0x2
+#define REGS_INDEX_DATA_PAIR_CTRL__PCIE_DATA2_DIS__SHIFT                                                      0x3
+#define REGS_INDEX_DATA_PAIR_CTRL__MM_DATA_DIS_MASK                                                           0x00000001L
+#define REGS_INDEX_DATA_PAIR_CTRL__SYSHUB_DATA_DIS_MASK                                                       0x00000002L
+#define REGS_INDEX_DATA_PAIR_CTRL__PCIE_DATA_DIS_MASK                                                         0x00000004L
+#define REGS_INDEX_DATA_PAIR_CTRL__PCIE_DATA2_DIS_MASK                                                        0x00000008L
+//BIFL_SEC_RAS_RESPONSE_DROP_CTRL
+#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF0_RESPONSE_DROP_EN__SHIFT                           0x0
+#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF1_RESPONSE_DROP_EN__SHIFT                           0x1
+#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF2_RESPONSE_DROP_EN__SHIFT                           0x2
+#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF3_RESPONSE_DROP_EN__SHIFT                           0x3
+#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF4_RESPONSE_DROP_EN__SHIFT                           0x4
+#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF5_RESPONSE_DROP_EN__SHIFT                           0x5
+#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF6_RESPONSE_DROP_EN__SHIFT                           0x6
+#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF7_RESPONSE_DROP_EN__SHIFT                           0x7
+#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF8_RESPONSE_DROP_EN__SHIFT                           0x8
+#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF9_RESPONSE_DROP_EN__SHIFT                           0x9
+#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF10_RESPONSE_DROP_EN__SHIFT                          0xa
+#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF11_RESPONSE_DROP_EN__SHIFT                          0xb
+#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF12_RESPONSE_DROP_EN__SHIFT                          0xc
+#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF13_RESPONSE_DROP_EN__SHIFT                          0xd
+#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF14_RESPONSE_DROP_EN__SHIFT                          0xe
+#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF15_RESPONSE_DROP_EN__SHIFT                          0xf
+#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF16_RESPONSE_DROP_EN__SHIFT                          0x10
+#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF17_RESPONSE_DROP_EN__SHIFT                          0x11
+#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF18_RESPONSE_DROP_EN__SHIFT                          0x12
+#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF19_RESPONSE_DROP_EN__SHIFT                          0x13
+#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF0_RESPONSE_DROP_EN_MASK                             0x00000001L
+#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF1_RESPONSE_DROP_EN_MASK                             0x00000002L
+#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF2_RESPONSE_DROP_EN_MASK                             0x00000004L
+#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF3_RESPONSE_DROP_EN_MASK                             0x00000008L
+#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF4_RESPONSE_DROP_EN_MASK                             0x00000010L
+#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF5_RESPONSE_DROP_EN_MASK                             0x00000020L
+#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF6_RESPONSE_DROP_EN_MASK                             0x00000040L
+#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF7_RESPONSE_DROP_EN_MASK                             0x00000080L
+#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF8_RESPONSE_DROP_EN_MASK                             0x00000100L
+#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF9_RESPONSE_DROP_EN_MASK                             0x00000200L
+#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF10_RESPONSE_DROP_EN_MASK                            0x00000400L
+#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF11_RESPONSE_DROP_EN_MASK                            0x00000800L
+#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF12_RESPONSE_DROP_EN_MASK                            0x00001000L
+#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF13_RESPONSE_DROP_EN_MASK                            0x00002000L
+#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF14_RESPONSE_DROP_EN_MASK                            0x00004000L
+#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF15_RESPONSE_DROP_EN_MASK                            0x00008000L
+#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF16_RESPONSE_DROP_EN_MASK                            0x00010000L
+#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF17_RESPONSE_DROP_EN_MASK                            0x00020000L
+#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF18_RESPONSE_DROP_EN_MASK                            0x00040000L
+#define BIFL_SEC_RAS_RESPONSE_DROP_CTRL__BIFL_SEC_RAS_LEAF19_RESPONSE_DROP_EN_MASK                            0x00080000L
+//BIFC_SEC_MCA_SMN_CTRL0
+#define BIFC_SEC_MCA_SMN_CTRL0__MCA_INT_REQ_ADDR__SHIFT                                                       0x0
+#define BIFC_SEC_MCA_SMN_CTRL0__MCA_INT_REQ_APER_ID__SHIFT                                                    0x14
+#define BIFC_SEC_MCA_SMN_CTRL0__MCA_INT_REQ_ADDR_MASK                                                         0x000FFFFFL
+#define BIFC_SEC_MCA_SMN_CTRL0__MCA_INT_REQ_APER_ID_MASK                                                      0xFFF00000L
+//BIFC_SEC_MCA_SMN_CTRL1
+#define BIFC_SEC_MCA_SMN_CTRL1__MCA_INT_REQ_MCM_ADDR__SHIFT                                                   0x0
+#define BIFC_SEC_MCA_SMN_CTRL1__MCA_SMN_SEC_SEL__SHIFT                                                        0x10
+#define BIFC_SEC_MCA_SMN_CTRL1__MCA_INT_REQ_MCM_ADDR_MASK                                                     0x0000FFFFL
+#define BIFC_SEC_MCA_SMN_CTRL1__MCA_SMN_SEC_SEL_MASK                                                          0x000F0000L
+//BIFL_SEC_RAS_POISON_DBUG_CTRL
+#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF0_CTRL_POISON_DBUG_EN__SHIFT                          0x0
+#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF1_CTRL_POISON_DBUG_EN__SHIFT                          0x1
+#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF2_CTRL_POISON_DBUG_EN__SHIFT                          0x2
+#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF3_CTRL_POISON_DBUG_EN__SHIFT                          0x3
+#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF4_CTRL_POISON_DBUG_EN__SHIFT                          0x4
+#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF5_CTRL_POISON_DBUG_EN__SHIFT                          0x5
+#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF6_CTRL_POISON_DBUG_EN__SHIFT                          0x6
+#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF7_CTRL_POISON_DBUG_EN__SHIFT                          0x7
+#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF8_CTRL_POISON_DBUG_EN__SHIFT                          0x8
+#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF9_CTRL_POISON_DBUG_EN__SHIFT                          0x9
+#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF10_CTRL_POISON_DBUG_EN__SHIFT                         0xa
+#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF11_CTRL_POISON_DBUG_EN__SHIFT                         0xb
+#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF12_CTRL_POISON_DBUG_EN__SHIFT                         0xc
+#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF13_CTRL_POISON_DBUG_EN__SHIFT                         0xd
+#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF14_CTRL_POISON_DBUG_EN__SHIFT                         0xe
+#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF15_CTRL_POISON_DBUG_EN__SHIFT                         0xf
+#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF16_CTRL_POISON_DBUG_EN__SHIFT                         0x10
+#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF17_CTRL_POISON_DBUG_EN__SHIFT                         0x11
+#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF18_CTRL_POISON_DBUG_EN__SHIFT                         0x12
+#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF19_CTRL_POISON_DBUG_EN__SHIFT                         0x13
+#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF0_CTRL_POISON_DBUG_EN_MASK                            0x00000001L
+#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF1_CTRL_POISON_DBUG_EN_MASK                            0x00000002L
+#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF2_CTRL_POISON_DBUG_EN_MASK                            0x00000004L
+#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF3_CTRL_POISON_DBUG_EN_MASK                            0x00000008L
+#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF4_CTRL_POISON_DBUG_EN_MASK                            0x00000010L
+#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF5_CTRL_POISON_DBUG_EN_MASK                            0x00000020L
+#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF6_CTRL_POISON_DBUG_EN_MASK                            0x00000040L
+#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF7_CTRL_POISON_DBUG_EN_MASK                            0x00000080L
+#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF8_CTRL_POISON_DBUG_EN_MASK                            0x00000100L
+#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF9_CTRL_POISON_DBUG_EN_MASK                            0x00000200L
+#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF10_CTRL_POISON_DBUG_EN_MASK                           0x00000400L
+#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF11_CTRL_POISON_DBUG_EN_MASK                           0x00000800L
+#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF12_CTRL_POISON_DBUG_EN_MASK                           0x00001000L
+#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF13_CTRL_POISON_DBUG_EN_MASK                           0x00002000L
+#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF14_CTRL_POISON_DBUG_EN_MASK                           0x00004000L
+#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF15_CTRL_POISON_DBUG_EN_MASK                           0x00008000L
+#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF16_CTRL_POISON_DBUG_EN_MASK                           0x00010000L
+#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF17_CTRL_POISON_DBUG_EN_MASK                           0x00020000L
+#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF18_CTRL_POISON_DBUG_EN_MASK                           0x00040000L
+#define BIFL_SEC_RAS_POISON_DBUG_CTRL__BIFL_SEC_RAS_LEAF19_CTRL_POISON_DBUG_EN_MASK                           0x00080000L
+//BIFL_SEC_RAS_PARITY_DBUG_CTRL
+#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF0_CTRL_PARITY_DBUG_EN__SHIFT                          0x0
+#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF1_CTRL_PARITY_DBUG_EN__SHIFT                          0x1
+#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF2_CTRL_PARITY_DBUG_EN__SHIFT                          0x2
+#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF3_CTRL_PARITY_DBUG_EN__SHIFT                          0x3
+#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF4_CTRL_PARITY_DBUG_EN__SHIFT                          0x4
+#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF5_CTRL_PARITY_DBUG_EN__SHIFT                          0x5
+#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF6_CTRL_PARITY_DBUG_EN__SHIFT                          0x6
+#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF7_CTRL_PARITY_DBUG_EN__SHIFT                          0x7
+#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF8_CTRL_PARITY_DBUG_EN__SHIFT                          0x8
+#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF9_CTRL_PARITY_DBUG_EN__SHIFT                          0x9
+#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF10_CTRL_PARITY_DBUG_EN__SHIFT                         0xa
+#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF11_CTRL_PARITY_DBUG_EN__SHIFT                         0xb
+#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF12_CTRL_PARITY_DBUG_EN__SHIFT                         0xc
+#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF13_CTRL_PARITY_DBUG_EN__SHIFT                         0xd
+#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF14_CTRL_PARITY_DBUG_EN__SHIFT                         0xe
+#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF15_CTRL_PARITY_DBUG_EN__SHIFT                         0xf
+#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF16_CTRL_PARITY_DBUG_EN__SHIFT                         0x10
+#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF17_CTRL_PARITY_DBUG_EN__SHIFT                         0x11
+#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF18_CTRL_PARITY_DBUG_EN__SHIFT                         0x12
+#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF19_CTRL_PARITY_DBUG_EN__SHIFT                         0x13
+#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF0_CTRL_PARITY_DBUG_EN_MASK                            0x00000001L
+#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF1_CTRL_PARITY_DBUG_EN_MASK                            0x00000002L
+#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF2_CTRL_PARITY_DBUG_EN_MASK                            0x00000004L
+#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF3_CTRL_PARITY_DBUG_EN_MASK                            0x00000008L
+#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF4_CTRL_PARITY_DBUG_EN_MASK                            0x00000010L
+#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF5_CTRL_PARITY_DBUG_EN_MASK                            0x00000020L
+#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF6_CTRL_PARITY_DBUG_EN_MASK                            0x00000040L
+#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF7_CTRL_PARITY_DBUG_EN_MASK                            0x00000080L
+#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF8_CTRL_PARITY_DBUG_EN_MASK                            0x00000100L
+#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF9_CTRL_PARITY_DBUG_EN_MASK                            0x00000200L
+#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF10_CTRL_PARITY_DBUG_EN_MASK                           0x00000400L
+#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF11_CTRL_PARITY_DBUG_EN_MASK                           0x00000800L
+#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF12_CTRL_PARITY_DBUG_EN_MASK                           0x00001000L
+#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF13_CTRL_PARITY_DBUG_EN_MASK                           0x00002000L
+#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF14_CTRL_PARITY_DBUG_EN_MASK                           0x00004000L
+#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF15_CTRL_PARITY_DBUG_EN_MASK                           0x00008000L
+#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF16_CTRL_PARITY_DBUG_EN_MASK                           0x00010000L
+#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF17_CTRL_PARITY_DBUG_EN_MASK                           0x00020000L
+#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF18_CTRL_PARITY_DBUG_EN_MASK                           0x00040000L
+#define BIFL_SEC_RAS_PARITY_DBUG_CTRL__BIFL_SEC_RAS_LEAF19_CTRL_PARITY_DBUG_EN_MASK                           0x00080000L
+//BIFL_SEC_RAS_NTB_DBUG_CTRL
+#define BIFL_SEC_RAS_NTB_DBUG_CTRL__BIFL_SEC_RAS_LEAF_NTB_CTRL_RCVERREVENT_DBUG_EN__SHIFT                     0x0
+#define BIFL_SEC_RAS_NTB_DBUG_CTRL__BIFL_SEC_RAS_LEAF_NTB_CTRL_RCVERREVENT_DBUG_EN_MASK                       0x00000001L
+//BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL
+#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF0_CTRL_RCVERREVENT_DBUG_EN__SHIFT                0x0
+#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF1_CTRL_RCVERREVENT_DBUG_EN__SHIFT                0x1
+#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF2_CTRL_RCVERREVENT_DBUG_EN__SHIFT                0x2
+#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF3_CTRL_RCVERREVENT_DBUG_EN__SHIFT                0x3
+#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF4_CTRL_RCVERREVENT_DBUG_EN__SHIFT                0x4
+#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF5_CTRL_RCVERREVENT_DBUG_EN__SHIFT                0x5
+#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF6_CTRL_RCVERREVENT_DBUG_EN__SHIFT                0x6
+#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF7_CTRL_RCVERREVENT_DBUG_EN__SHIFT                0x7
+#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF8_CTRL_RCVERREVENT_DBUG_EN__SHIFT                0x8
+#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF9_CTRL_RCVERREVENT_DBUG_EN__SHIFT                0x9
+#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF10_CTRL_RCVERREVENT_DBUG_EN__SHIFT               0xa
+#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF11_CTRL_RCVERREVENT_DBUG_EN__SHIFT               0xb
+#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF12_CTRL_RCVERREVENT_DBUG_EN__SHIFT               0xc
+#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF13_CTRL_RCVERREVENT_DBUG_EN__SHIFT               0xd
+#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF14_CTRL_RCVERREVENT_DBUG_EN__SHIFT               0xe
+#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF15_CTRL_RCVERREVENT_DBUG_EN__SHIFT               0xf
+#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF16_CTRL_RCVERREVENT_DBUG_EN__SHIFT               0x10
+#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF17_CTRL_RCVERREVENT_DBUG_EN__SHIFT               0x11
+#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF18_CTRL_RCVERREVENT_DBUG_EN__SHIFT               0x12
+#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF19_CTRL_RCVERREVENT_DBUG_EN__SHIFT               0x13
+#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF0_CTRL_RCVERREVENT_DBUG_EN_MASK                  0x00000001L
+#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF1_CTRL_RCVERREVENT_DBUG_EN_MASK                  0x00000002L
+#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF2_CTRL_RCVERREVENT_DBUG_EN_MASK                  0x00000004L
+#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF3_CTRL_RCVERREVENT_DBUG_EN_MASK                  0x00000008L
+#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF4_CTRL_RCVERREVENT_DBUG_EN_MASK                  0x00000010L
+#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF5_CTRL_RCVERREVENT_DBUG_EN_MASK                  0x00000020L
+#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF6_CTRL_RCVERREVENT_DBUG_EN_MASK                  0x00000040L
+#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF7_CTRL_RCVERREVENT_DBUG_EN_MASK                  0x00000080L
+#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF8_CTRL_RCVERREVENT_DBUG_EN_MASK                  0x00000100L
+#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF9_CTRL_RCVERREVENT_DBUG_EN_MASK                  0x00000200L
+#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF10_CTRL_RCVERREVENT_DBUG_EN_MASK                 0x00000400L
+#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF11_CTRL_RCVERREVENT_DBUG_EN_MASK                 0x00000800L
+#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF12_CTRL_RCVERREVENT_DBUG_EN_MASK                 0x00001000L
+#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF13_CTRL_RCVERREVENT_DBUG_EN_MASK                 0x00002000L
+#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF14_CTRL_RCVERREVENT_DBUG_EN_MASK                 0x00004000L
+#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF15_CTRL_RCVERREVENT_DBUG_EN_MASK                 0x00008000L
+#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF16_CTRL_RCVERREVENT_DBUG_EN_MASK                 0x00010000L
+#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF17_CTRL_RCVERREVENT_DBUG_EN_MASK                 0x00020000L
+#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF18_CTRL_RCVERREVENT_DBUG_EN_MASK                 0x00040000L
+#define BIFL_SEC_RAS_RCVERREVENT_DBUG_CTRL__BIFL_SEC_RAS_LEAF19_CTRL_RCVERREVENT_DBUG_EN_MASK                 0x00080000L
+//BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL
+#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF0_CTRL_TIMEOUT_DBUG_EN__SHIFT                        0x0
+#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF1_CTRL_TIMEOUT_DBUG_EN__SHIFT                        0x1
+#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF2_CTRL_TIMEOUT_DBUG_EN__SHIFT                        0x2
+#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF3_CTRL_TIMEOUT_DBUG_EN__SHIFT                        0x3
+#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF4_CTRL_TIMEOUT_DBUG_EN__SHIFT                        0x4
+#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF5_CTRL_TIMEOUT_DBUG_EN__SHIFT                        0x5
+#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF6_CTRL_TIMEOUT_DBUG_EN__SHIFT                        0x6
+#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF7_CTRL_TIMEOUT_DBUG_EN__SHIFT                        0x7
+#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF8_CTRL_TIMEOUT_DBUG_EN__SHIFT                        0x8
+#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF9_CTRL_TIMEOUT_DBUG_EN__SHIFT                        0x9
+#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF10_CTRL_TIMEOUT_DBUG_EN__SHIFT                       0xa
+#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF11_CTRL_TIMEOUT_DBUG_EN__SHIFT                       0xb
+#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF12_CTRL_TIMEOUT_DBUG_EN__SHIFT                       0xc
+#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF13_CTRL_TIMEOUT_DBUG_EN__SHIFT                       0xd
+#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF14_CTRL_TIMEOUT_DBUG_EN__SHIFT                       0xe
+#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF15_CTRL_TIMEOUT_DBUG_EN__SHIFT                       0xf
+#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF16_CTRL_TIMEOUT_DBUG_EN__SHIFT                       0x10
+#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF17_CTRL_TIMEOUT_DBUG_EN__SHIFT                       0x11
+#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF18_CTRL_TIMEOUT_DBUG_EN__SHIFT                       0x12
+#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF19_CTRL_TIMEOUT_DBUG_EN__SHIFT                       0x13
+#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF0_CTRL_TIMEOUT_DBUG_EN_MASK                          0x00000001L
+#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF1_CTRL_TIMEOUT_DBUG_EN_MASK                          0x00000002L
+#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF2_CTRL_TIMEOUT_DBUG_EN_MASK                          0x00000004L
+#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF3_CTRL_TIMEOUT_DBUG_EN_MASK                          0x00000008L
+#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF4_CTRL_TIMEOUT_DBUG_EN_MASK                          0x00000010L
+#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF5_CTRL_TIMEOUT_DBUG_EN_MASK                          0x00000020L
+#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF6_CTRL_TIMEOUT_DBUG_EN_MASK                          0x00000040L
+#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF7_CTRL_TIMEOUT_DBUG_EN_MASK                          0x00000080L
+#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF8_CTRL_TIMEOUT_DBUG_EN_MASK                          0x00000100L
+#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF9_CTRL_TIMEOUT_DBUG_EN_MASK                          0x00000200L
+#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF10_CTRL_TIMEOUT_DBUG_EN_MASK                         0x00000400L
+#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF11_CTRL_TIMEOUT_DBUG_EN_MASK                         0x00000800L
+#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF12_CTRL_TIMEOUT_DBUG_EN_MASK                         0x00001000L
+#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF13_CTRL_TIMEOUT_DBUG_EN_MASK                         0x00002000L
+#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF14_CTRL_TIMEOUT_DBUG_EN_MASK                         0x00004000L
+#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF15_CTRL_TIMEOUT_DBUG_EN_MASK                         0x00008000L
+#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF16_CTRL_TIMEOUT_DBUG_EN_MASK                         0x00010000L
+#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF17_CTRL_TIMEOUT_DBUG_EN_MASK                         0x00020000L
+#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF18_CTRL_TIMEOUT_DBUG_EN_MASK                         0x00040000L
+#define BIFL_SEC_RAS_TIMEOUT_DBUG_CTRL__BIFL_SEC_RAS_LEAF19_CTRL_TIMEOUT_DBUG_EN_MASK                         0x00080000L
+//BIFL_SEC_RAS_LEAF0_RRESP_POISON_CTRL
+#define BIFL_SEC_RAS_LEAF0_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF0_RRESP_POISON_EN__SHIFT                       0x0
+#define BIFL_SEC_RAS_LEAF0_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF0_RRESP_POISON_EN_MASK                         0x000000FFL
+//BIFL_SEC_RAS_LEAF0_RUSER_POISON_CTRL
+#define BIFL_SEC_RAS_LEAF0_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF0_RUSER_POISON_EN__SHIFT                       0x0
+#define BIFL_SEC_RAS_LEAF0_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF0_RUSER_POISON_EN_MASK                         0x000000FFL
+//BIFL_SEC_RAS_LEAF1_RRESP_POISON_CTRL
+#define BIFL_SEC_RAS_LEAF1_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF1_RRESP_POISON_EN__SHIFT                       0x0
+#define BIFL_SEC_RAS_LEAF1_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF1_RRESP_POISON_EN_MASK                         0x000000FFL
+//BIFL_SEC_RAS_LEAF1_RUSER_POISON_CTRL
+#define BIFL_SEC_RAS_LEAF1_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF1_RUSER_POISON_EN__SHIFT                       0x0
+#define BIFL_SEC_RAS_LEAF1_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF1_RUSER_POISON_EN_MASK                         0x000000FFL
+//BIFL_SEC_RAS_LEAF2_RRESP_POISON_CTRL
+#define BIFL_SEC_RAS_LEAF2_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF2_RRESP_POISON_EN__SHIFT                       0x0
+#define BIFL_SEC_RAS_LEAF2_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF2_RRESP_POISON_EN_MASK                         0x000000FFL
+//BIFL_SEC_RAS_LEAF2_RUSER_POISON_CTRL
+#define BIFL_SEC_RAS_LEAF2_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF2_RUSER_POISON_EN__SHIFT                       0x0
+#define BIFL_SEC_RAS_LEAF2_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF2_RUSER_POISON_EN_MASK                         0x000000FFL
+//BIFL_SEC_RAS_LEAF3_RRESP_POISON_CTRL
+#define BIFL_SEC_RAS_LEAF3_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF3_RRESP_POISON_EN__SHIFT                       0x0
+#define BIFL_SEC_RAS_LEAF3_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF3_RRESP_POISON_EN_MASK                         0x000000FFL
+//BIFL_SEC_RAS_LEAF3_RUSER_POISON_CTRL
+#define BIFL_SEC_RAS_LEAF3_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF3_RUSER_POISON_EN__SHIFT                       0x0
+#define BIFL_SEC_RAS_LEAF3_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF3_RUSER_POISON_EN_MASK                         0x000000FFL
+//BIFL_SEC_RAS_LEAF4_RRESP_POISON_CTRL
+#define BIFL_SEC_RAS_LEAF4_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF4_RRESP_POISON_EN__SHIFT                       0x0
+#define BIFL_SEC_RAS_LEAF4_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF4_RRESP_POISON_EN_MASK                         0x000000FFL
+//BIFL_SEC_RAS_LEAF4_RUSER_POISON_CTRL
+#define BIFL_SEC_RAS_LEAF4_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF4_RUSER_POISON_EN__SHIFT                       0x0
+#define BIFL_SEC_RAS_LEAF4_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF4_RUSER_POISON_EN_MASK                         0x000000FFL
+//BIFL_SEC_RAS_LEAF5_RRESP_POISON_CTRL
+#define BIFL_SEC_RAS_LEAF5_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF5_RRESP_POISON_EN__SHIFT                       0x0
+#define BIFL_SEC_RAS_LEAF5_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF5_RRESP_POISON_EN_MASK                         0x000000FFL
+//BIFL_SEC_RAS_LEAF5_RUSER_POISON_CTRL
+#define BIFL_SEC_RAS_LEAF5_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF5_RUSER_POISON_EN__SHIFT                       0x0
+#define BIFL_SEC_RAS_LEAF5_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF5_RUSER_POISON_EN_MASK                         0x000000FFL
+//BIFL_SEC_RAS_LEAF6_RRESP_POISON_CTRL
+#define BIFL_SEC_RAS_LEAF6_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF6_RRESP_POISON_EN__SHIFT                       0x0
+#define BIFL_SEC_RAS_LEAF6_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF6_RRESP_POISON_EN_MASK                         0x000000FFL
+//BIFL_SEC_RAS_LEAF6_RUSER_POISON_CTRL
+#define BIFL_SEC_RAS_LEAF6_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF6_RUSER_POISON_EN__SHIFT                       0x0
+#define BIFL_SEC_RAS_LEAF6_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF6_RUSER_POISON_EN_MASK                         0x000000FFL
+//BIFL_SEC_RAS_LEAF7_RRESP_POISON_CTRL
+#define BIFL_SEC_RAS_LEAF7_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF7_RRESP_POISON_EN__SHIFT                       0x0
+#define BIFL_SEC_RAS_LEAF7_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF7_RRESP_POISON_EN_MASK                         0x000000FFL
+//BIFL_SEC_RAS_LEAF7_RUSER_POISON_CTRL
+#define BIFL_SEC_RAS_LEAF7_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF7_RUSER_POISON_EN__SHIFT                       0x0
+#define BIFL_SEC_RAS_LEAF7_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF7_RUSER_POISON_EN_MASK                         0x000000FFL
+//BIFL_SEC_RAS_LEAF8_RRESP_POISON_CTRL
+#define BIFL_SEC_RAS_LEAF8_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF8_RRESP_POISON_EN__SHIFT                       0x0
+#define BIFL_SEC_RAS_LEAF8_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF8_RRESP_POISON_EN_MASK                         0x000000FFL
+//BIFL_SEC_RAS_LEAF8_RUSER_POISON_CTRL
+#define BIFL_SEC_RAS_LEAF8_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF8_RUSER_POISON_EN__SHIFT                       0x0
+#define BIFL_SEC_RAS_LEAF8_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF8_RUSER_POISON_EN_MASK                         0x000000FFL
+//BIFL_SEC_RAS_LEAF9_RRESP_POISON_CTRL
+#define BIFL_SEC_RAS_LEAF9_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF9_RRESP_POISON_EN__SHIFT                       0x0
+#define BIFL_SEC_RAS_LEAF9_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF9_RRESP_POISON_EN_MASK                         0x000000FFL
+//BIFL_SEC_RAS_LEAF9_RUSER_POISON_CTRL
+#define BIFL_SEC_RAS_LEAF9_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF9_RUSER_POISON_EN__SHIFT                       0x0
+#define BIFL_SEC_RAS_LEAF9_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF9_RUSER_POISON_EN_MASK                         0x000000FFL
+//BIFL_SEC_RAS_LEAF10_RRESP_POISON_CTRL
+#define BIFL_SEC_RAS_LEAF10_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF10_RRESP_POISON_EN__SHIFT                     0x0
+#define BIFL_SEC_RAS_LEAF10_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF10_RRESP_POISON_EN_MASK                       0x000000FFL
+//BIFL_SEC_RAS_LEAF10_RUSER_POISON_CTRL
+#define BIFL_SEC_RAS_LEAF10_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF10_RUSER_POISON_EN__SHIFT                     0x0
+#define BIFL_SEC_RAS_LEAF10_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF10_RUSER_POISON_EN_MASK                       0x000000FFL
+//BIFL_SEC_RAS_LEAF11_RRESP_POISON_CTRL
+#define BIFL_SEC_RAS_LEAF11_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF11_RRESP_POISON_EN__SHIFT                     0x0
+#define BIFL_SEC_RAS_LEAF11_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF11_RRESP_POISON_EN_MASK                       0x000000FFL
+//BIFL_SEC_RAS_LEAF11_RUSER_POISON_CTRL
+#define BIFL_SEC_RAS_LEAF11_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF11_RUSER_POISON_EN__SHIFT                     0x0
+#define BIFL_SEC_RAS_LEAF11_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF11_RUSER_POISON_EN_MASK                       0x000000FFL
+//BIFL_SEC_RAS_LEAF12_RRESP_POISON_CTRL
+#define BIFL_SEC_RAS_LEAF12_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF12_RRESP_POISON_EN__SHIFT                     0x0
+#define BIFL_SEC_RAS_LEAF12_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF12_RRESP_POISON_EN_MASK                       0x000000FFL
+//BIFL_SEC_RAS_LEAF12_RUSER_POISON_CTRL
+#define BIFL_SEC_RAS_LEAF12_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF12_RUSER_POISON_EN__SHIFT                     0x0
+#define BIFL_SEC_RAS_LEAF12_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF12_RUSER_POISON_EN_MASK                       0x000000FFL
+//BIFL_SEC_RAS_LEAF13_RRESP_POISON_CTRL
+#define BIFL_SEC_RAS_LEAF13_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF13_RRESP_POISON_EN__SHIFT                     0x0
+#define BIFL_SEC_RAS_LEAF13_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF13_RRESP_POISON_EN_MASK                       0x000000FFL
+//BIFL_SEC_RAS_LEAF13_RUSER_POISON_CTRL
+#define BIFL_SEC_RAS_LEAF13_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF13_RUSER_POISON_EN__SHIFT                     0x0
+#define BIFL_SEC_RAS_LEAF13_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF13_RUSER_POISON_EN_MASK                       0x000000FFL
+//BIFL_SEC_RAS_LEAF14_RRESP_POISON_CTRL
+#define BIFL_SEC_RAS_LEAF14_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF14_RRESP_POISON_EN__SHIFT                     0x0
+#define BIFL_SEC_RAS_LEAF14_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF14_RRESP_POISON_EN_MASK                       0x000000FFL
+//BIFL_SEC_RAS_LEAF14_RUSER_POISON_CTRL
+#define BIFL_SEC_RAS_LEAF14_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF14_RUSER_POISON_EN__SHIFT                     0x0
+#define BIFL_SEC_RAS_LEAF14_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF14_RUSER_POISON_EN_MASK                       0x000000FFL
+//BIFL_SEC_RAS_LEAF15_RRESP_POISON_CTRL
+#define BIFL_SEC_RAS_LEAF15_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF15_RRESP_POISON_EN__SHIFT                     0x0
+#define BIFL_SEC_RAS_LEAF15_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF15_RRESP_POISON_EN_MASK                       0x000000FFL
+//BIFL_SEC_RAS_LEAF15_RUSER_POISON_CTRL
+#define BIFL_SEC_RAS_LEAF15_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF15_RUSER_POISON_EN__SHIFT                     0x0
+#define BIFL_SEC_RAS_LEAF15_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF15_RUSER_POISON_EN_MASK                       0x000000FFL
+//BIFL_SEC_RAS_LEAF16_RRESP_POISON_CTRL
+#define BIFL_SEC_RAS_LEAF16_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF16_RRESP_POISON_EN__SHIFT                     0x0
+#define BIFL_SEC_RAS_LEAF16_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF16_RRESP_POISON_EN_MASK                       0x000000FFL
+//BIFL_SEC_RAS_LEAF16_RUSER_POISON_CTRL
+#define BIFL_SEC_RAS_LEAF16_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF16_RUSER_POISON_EN__SHIFT                     0x0
+#define BIFL_SEC_RAS_LEAF16_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF16_RUSER_POISON_EN_MASK                       0x000000FFL
+//BIFL_SEC_RAS_LEAF17_RRESP_POISON_CTRL
+#define BIFL_SEC_RAS_LEAF17_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF17_RRESP_POISON_EN__SHIFT                     0x0
+#define BIFL_SEC_RAS_LEAF17_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF17_RRESP_POISON_EN_MASK                       0x000000FFL
+//BIFL_SEC_RAS_LEAF17_RUSER_POISON_CTRL
+#define BIFL_SEC_RAS_LEAF17_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF17_RUSER_POISON_EN__SHIFT                     0x0
+#define BIFL_SEC_RAS_LEAF17_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF17_RUSER_POISON_EN_MASK                       0x000000FFL
+//BIFL_SEC_RAS_LEAF18_RRESP_POISON_CTRL
+#define BIFL_SEC_RAS_LEAF18_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF18_RRESP_POISON_EN__SHIFT                     0x0
+#define BIFL_SEC_RAS_LEAF18_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF18_RRESP_POISON_EN_MASK                       0x000000FFL
+//BIFL_SEC_RAS_LEAF18_RUSER_POISON_CTRL
+#define BIFL_SEC_RAS_LEAF18_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF18_RUSER_POISON_EN__SHIFT                     0x0
+#define BIFL_SEC_RAS_LEAF18_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF18_RUSER_POISON_EN_MASK                       0x000000FFL
+//BIFL_SEC_RAS_LEAF19_RRESP_POISON_CTRL
+#define BIFL_SEC_RAS_LEAF19_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF19_RRESP_POISON_EN__SHIFT                     0x0
+#define BIFL_SEC_RAS_LEAF19_RRESP_POISON_CTRL__BIFL_SEC_RAS_LEAF19_RRESP_POISON_EN_MASK                       0x000000FFL
+//BIFL_SEC_RAS_LEAF19_RUSER_POISON_CTRL
+#define BIFL_SEC_RAS_LEAF19_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF19_RUSER_POISON_EN__SHIFT                     0x0
+#define BIFL_SEC_RAS_LEAF19_RUSER_POISON_CTRL__BIFL_SEC_RAS_LEAF19_RUSER_POISON_EN_MASK                       0x000000FFL
+//NBIF_STRAP_BIOS_CNTL
+#define NBIF_STRAP_BIOS_CNTL__NBIF_STRAP_BIOS_EN__SHIFT                                                       0x0
+#define NBIF_STRAP_BIOS_CNTL__NBIF_STRAP_PCIE_ID_BIOS_EN__SHIFT                                               0x1
+#define NBIF_STRAP_BIOS_CNTL__NBIF_STRAP_BIOS_EN_MASK                                                         0x00000001L
+#define NBIF_STRAP_BIOS_CNTL__NBIF_STRAP_PCIE_ID_BIOS_EN_MASK                                                 0x00000002L
+//SMN_MST_NORMAL_SECURITY
+#define SMN_MST_NORMAL_SECURITY__SMN_MST_NORMAL_RECURITY_SEL__SHIFT                                           0x0
+#define SMN_MST_NORMAL_SECURITY__SMN_MST_NORMAL_RECURITY_SEL_MASK                                             0x0000000FL
+//OVERRIDE_TYPE_FOR_CHAIN_CTRL
+#define OVERRIDE_TYPE_FOR_CHAIN_CTRL__OVERRIDE_TYPE_FOR_CHAIN__SHIFT                                          0x0
+#define OVERRIDE_TYPE_FOR_CHAIN_CTRL__OVERRIDE_TYPE_FOR_CHAIN_MASK                                            0x00000001L
+//PROCESSING_HINT_SUPPORT_CNTL
+#define PROCESSING_HINT_SUPPORT_CNTL__PH_MASK_EN__SHIFT                                                       0x0
+#define PROCESSING_HINT_SUPPORT_CNTL__PH_MASK_EN_MASK                                                         0x00000001L
+//DEV0_PF0_VF0_MMIO0_FENCE
+#define DEV0_PF0_VF0_MMIO0_FENCE__WR_ENABLE__SHIFT                                                            0x0
+#define DEV0_PF0_VF0_MMIO0_FENCE__RD_ENABLE__SHIFT                                                            0x10
+#define DEV0_PF0_VF0_MMIO0_FENCE__WR_ENABLE_MASK                                                              0x0000FFFFL
+#define DEV0_PF0_VF0_MMIO0_FENCE__RD_ENABLE_MASK                                                              0xFFFF0000L
+//DEV0_PF0_VF1_MMIO0_FENCE
+#define DEV0_PF0_VF1_MMIO0_FENCE__WR_ENABLE__SHIFT                                                            0x0
+#define DEV0_PF0_VF1_MMIO0_FENCE__RD_ENABLE__SHIFT                                                            0x10
+#define DEV0_PF0_VF1_MMIO0_FENCE__WR_ENABLE_MASK                                                              0x0000FFFFL
+#define DEV0_PF0_VF1_MMIO0_FENCE__RD_ENABLE_MASK                                                              0xFFFF0000L
+//DEV0_PF0_VF2_MMIO0_FENCE
+#define DEV0_PF0_VF2_MMIO0_FENCE__WR_ENABLE__SHIFT                                                            0x0
+#define DEV0_PF0_VF2_MMIO0_FENCE__RD_ENABLE__SHIFT                                                            0x10
+#define DEV0_PF0_VF2_MMIO0_FENCE__WR_ENABLE_MASK                                                              0x0000FFFFL
+#define DEV0_PF0_VF2_MMIO0_FENCE__RD_ENABLE_MASK                                                              0xFFFF0000L
+//DEV0_PF0_VF3_MMIO0_FENCE
+#define DEV0_PF0_VF3_MMIO0_FENCE__WR_ENABLE__SHIFT                                                            0x0
+#define DEV0_PF0_VF3_MMIO0_FENCE__RD_ENABLE__SHIFT                                                            0x10
+#define DEV0_PF0_VF3_MMIO0_FENCE__WR_ENABLE_MASK                                                              0x0000FFFFL
+#define DEV0_PF0_VF3_MMIO0_FENCE__RD_ENABLE_MASK                                                              0xFFFF0000L
+//DEV0_PF0_VF4_MMIO0_FENCE
+#define DEV0_PF0_VF4_MMIO0_FENCE__WR_ENABLE__SHIFT                                                            0x0
+#define DEV0_PF0_VF4_MMIO0_FENCE__RD_ENABLE__SHIFT                                                            0x10
+#define DEV0_PF0_VF4_MMIO0_FENCE__WR_ENABLE_MASK                                                              0x0000FFFFL
+#define DEV0_PF0_VF4_MMIO0_FENCE__RD_ENABLE_MASK                                                              0xFFFF0000L
+//DEV0_PF0_VF5_MMIO0_FENCE
+#define DEV0_PF0_VF5_MMIO0_FENCE__WR_ENABLE__SHIFT                                                            0x0
+#define DEV0_PF0_VF5_MMIO0_FENCE__RD_ENABLE__SHIFT                                                            0x10
+#define DEV0_PF0_VF5_MMIO0_FENCE__WR_ENABLE_MASK                                                              0x0000FFFFL
+#define DEV0_PF0_VF5_MMIO0_FENCE__RD_ENABLE_MASK                                                              0xFFFF0000L
+//DEV0_PF0_VF6_MMIO0_FENCE
+#define DEV0_PF0_VF6_MMIO0_FENCE__WR_ENABLE__SHIFT                                                            0x0
+#define DEV0_PF0_VF6_MMIO0_FENCE__RD_ENABLE__SHIFT                                                            0x10
+#define DEV0_PF0_VF6_MMIO0_FENCE__WR_ENABLE_MASK                                                              0x0000FFFFL
+#define DEV0_PF0_VF6_MMIO0_FENCE__RD_ENABLE_MASK                                                              0xFFFF0000L
+//DEV0_PF0_VF7_MMIO0_FENCE
+#define DEV0_PF0_VF7_MMIO0_FENCE__WR_ENABLE__SHIFT                                                            0x0
+#define DEV0_PF0_VF7_MMIO0_FENCE__RD_ENABLE__SHIFT                                                            0x10
+#define DEV0_PF0_VF7_MMIO0_FENCE__WR_ENABLE_MASK                                                              0x0000FFFFL
+#define DEV0_PF0_VF7_MMIO0_FENCE__RD_ENABLE_MASK                                                              0xFFFF0000L
+//DEV0_PF0_VF_MMIO0_FENCE_RANGE0_START
+#define DEV0_PF0_VF_MMIO0_FENCE_RANGE0_START__ADDRESS__SHIFT                                                  0x0
+#define DEV0_PF0_VF_MMIO0_FENCE_RANGE0_START__ADDRESS_MASK                                                    0x3FFFFFFFL
+//DEV0_PF0_VF_MMIO0_FENCE_RANGE0_END
+#define DEV0_PF0_VF_MMIO0_FENCE_RANGE0_END__ADDRESS__SHIFT                                                    0x0
+#define DEV0_PF0_VF_MMIO0_FENCE_RANGE0_END__ADDRESS_MASK                                                      0x3FFFFFFFL
+//DEV0_PF0_VF_MMIO0_FENCE_RANGE1_START
+#define DEV0_PF0_VF_MMIO0_FENCE_RANGE1_START__ADDRESS__SHIFT                                                  0x0
+#define DEV0_PF0_VF_MMIO0_FENCE_RANGE1_START__ADDRESS_MASK                                                    0x3FFFFFFFL
+//DEV0_PF0_VF_MMIO0_FENCE_RANGE1_END
+#define DEV0_PF0_VF_MMIO0_FENCE_RANGE1_END__ADDRESS__SHIFT                                                    0x0
+#define DEV0_PF0_VF_MMIO0_FENCE_RANGE1_END__ADDRESS_MASK                                                      0x3FFFFFFFL
+//DEV0_PF0_VF_MMIO0_FENCE_RANGE2_START
+#define DEV0_PF0_VF_MMIO0_FENCE_RANGE2_START__ADDRESS__SHIFT                                                  0x0
+#define DEV0_PF0_VF_MMIO0_FENCE_RANGE2_START__ADDRESS_MASK                                                    0x3FFFFFFFL
+//DEV0_PF0_VF_MMIO0_FENCE_RANGE2_END
+#define DEV0_PF0_VF_MMIO0_FENCE_RANGE2_END__ADDRESS__SHIFT                                                    0x0
+#define DEV0_PF0_VF_MMIO0_FENCE_RANGE2_END__ADDRESS_MASK                                                      0x3FFFFFFFL
+//DEV0_PF0_VF_MMIO0_FENCE_RANGE3_START
+#define DEV0_PF0_VF_MMIO0_FENCE_RANGE3_START__ADDRESS__SHIFT                                                  0x0
+#define DEV0_PF0_VF_MMIO0_FENCE_RANGE3_START__ADDRESS_MASK                                                    0x3FFFFFFFL
+//DEV0_PF0_VF_MMIO0_FENCE_RANGE3_END
+#define DEV0_PF0_VF_MMIO0_FENCE_RANGE3_END__ADDRESS__SHIFT                                                    0x0
+#define DEV0_PF0_VF_MMIO0_FENCE_RANGE3_END__ADDRESS_MASK                                                      0x3FFFFFFFL
+//DEV0_PF0_VF_MMIO0_FENCE_RANGE4_START
+#define DEV0_PF0_VF_MMIO0_FENCE_RANGE4_START__ADDRESS__SHIFT                                                  0x0
+#define DEV0_PF0_VF_MMIO0_FENCE_RANGE4_START__ADDRESS_MASK                                                    0x3FFFFFFFL
+//DEV0_PF0_VF_MMIO0_FENCE_RANGE4_END
+#define DEV0_PF0_VF_MMIO0_FENCE_RANGE4_END__ADDRESS__SHIFT                                                    0x0
+#define DEV0_PF0_VF_MMIO0_FENCE_RANGE4_END__ADDRESS_MASK                                                      0x3FFFFFFFL
+//DEV0_PF0_VF_MMIO0_FENCE_RANGE5_START
+#define DEV0_PF0_VF_MMIO0_FENCE_RANGE5_START__ADDRESS__SHIFT                                                  0x0
+#define DEV0_PF0_VF_MMIO0_FENCE_RANGE5_START__ADDRESS_MASK                                                    0x3FFFFFFFL
+//DEV0_PF0_VF_MMIO0_FENCE_RANGE5_END
+#define DEV0_PF0_VF_MMIO0_FENCE_RANGE5_END__ADDRESS__SHIFT                                                    0x0
+#define DEV0_PF0_VF_MMIO0_FENCE_RANGE5_END__ADDRESS_MASK                                                      0x3FFFFFFFL
+//DEV0_PF0_VF_MMIO0_FENCE_RANGE6_START
+#define DEV0_PF0_VF_MMIO0_FENCE_RANGE6_START__ADDRESS__SHIFT                                                  0x0
+#define DEV0_PF0_VF_MMIO0_FENCE_RANGE6_START__ADDRESS_MASK                                                    0x3FFFFFFFL
+//DEV0_PF0_VF_MMIO0_FENCE_RANGE6_END
+#define DEV0_PF0_VF_MMIO0_FENCE_RANGE6_END__ADDRESS__SHIFT                                                    0x0
+#define DEV0_PF0_VF_MMIO0_FENCE_RANGE6_END__ADDRESS_MASK                                                      0x3FFFFFFFL
+//DEV0_PF0_VF_MMIO0_FENCE_RANGE7_START
+#define DEV0_PF0_VF_MMIO0_FENCE_RANGE7_START__ADDRESS__SHIFT                                                  0x0
+#define DEV0_PF0_VF_MMIO0_FENCE_RANGE7_START__ADDRESS_MASK                                                    0x3FFFFFFFL
+//DEV0_PF0_VF_MMIO0_FENCE_RANGE7_END
+#define DEV0_PF0_VF_MMIO0_FENCE_RANGE7_END__ADDRESS__SHIFT                                                    0x0
+#define DEV0_PF0_VF_MMIO0_FENCE_RANGE7_END__ADDRESS_MASK                                                      0x3FFFFFFFL
+//DEV0_PF1_VF0_MMIO0_FENCE
+#define DEV0_PF1_VF0_MMIO0_FENCE__WR_ENABLE__SHIFT                                                            0x0
+#define DEV0_PF1_VF0_MMIO0_FENCE__RD_ENABLE__SHIFT                                                            0x10
+#define DEV0_PF1_VF0_MMIO0_FENCE__WR_ENABLE_MASK                                                              0x0000FFFFL
+#define DEV0_PF1_VF0_MMIO0_FENCE__RD_ENABLE_MASK                                                              0xFFFF0000L
+//DEV0_PF1_VF_MMIO0_FENCE_RANGE0_START
+#define DEV0_PF1_VF_MMIO0_FENCE_RANGE0_START__ADDRESS__SHIFT                                                  0x0
+#define DEV0_PF1_VF_MMIO0_FENCE_RANGE0_START__ADDRESS_MASK                                                    0x3FFFFFFFL
+//DEV0_PF1_VF_MMIO0_FENCE_RANGE0_END
+#define DEV0_PF1_VF_MMIO0_FENCE_RANGE0_END__ADDRESS__SHIFT                                                    0x0
+#define DEV0_PF1_VF_MMIO0_FENCE_RANGE0_END__ADDRESS_MASK                                                      0x3FFFFFFFL
+//DEV0_PF1_VF_MMIO0_FENCE_RANGE1_START
+#define DEV0_PF1_VF_MMIO0_FENCE_RANGE1_START__ADDRESS__SHIFT                                                  0x0
+#define DEV0_PF1_VF_MMIO0_FENCE_RANGE1_START__ADDRESS_MASK                                                    0x3FFFFFFFL
+//DEV0_PF1_VF_MMIO0_FENCE_RANGE1_END
+#define DEV0_PF1_VF_MMIO0_FENCE_RANGE1_END__ADDRESS__SHIFT                                                    0x0
+#define DEV0_PF1_VF_MMIO0_FENCE_RANGE1_END__ADDRESS_MASK                                                      0x3FFFFFFFL
+//DEV0_PF1_VF_MMIO0_FENCE_RANGE2_START
+#define DEV0_PF1_VF_MMIO0_FENCE_RANGE2_START__ADDRESS__SHIFT                                                  0x0
+#define DEV0_PF1_VF_MMIO0_FENCE_RANGE2_START__ADDRESS_MASK                                                    0x3FFFFFFFL
+//DEV0_PF1_VF_MMIO0_FENCE_RANGE2_END
+#define DEV0_PF1_VF_MMIO0_FENCE_RANGE2_END__ADDRESS__SHIFT                                                    0x0
+#define DEV0_PF1_VF_MMIO0_FENCE_RANGE2_END__ADDRESS_MASK                                                      0x3FFFFFFFL
+//DEV0_PF1_VF_MMIO0_FENCE_RANGE3_START
+#define DEV0_PF1_VF_MMIO0_FENCE_RANGE3_START__ADDRESS__SHIFT                                                  0x0
+#define DEV0_PF1_VF_MMIO0_FENCE_RANGE3_START__ADDRESS_MASK                                                    0x3FFFFFFFL
+//DEV0_PF1_VF_MMIO0_FENCE_RANGE3_END
+#define DEV0_PF1_VF_MMIO0_FENCE_RANGE3_END__ADDRESS__SHIFT                                                    0x0
+#define DEV0_PF1_VF_MMIO0_FENCE_RANGE3_END__ADDRESS_MASK                                                      0x3FFFFFFFL
+//DEV0_PF0_PF_MMIO0_FENCE_WR
+#define DEV0_PF0_PF_MMIO0_FENCE_WR__ENABLE__SHIFT                                                             0x0
+#define DEV0_PF0_PF_MMIO0_FENCE_WR__ENABLE_MASK                                                               0xFFFFFFFFL
+//DEV0_PF0_PF_MMIO0_FENCE_RD
+#define DEV0_PF0_PF_MMIO0_FENCE_RD__ENABLE__SHIFT                                                             0x0
+#define DEV0_PF0_PF_MMIO0_FENCE_RD__ENABLE_MASK                                                               0xFFFFFFFFL
+//DEV0_PF0_PF_MMIO0_FENCE_RANGE0_START
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE0_START__ADDRESS__SHIFT                                                  0x0
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE0_START__ADDRESS_MASK                                                    0x3FFFFFFFL
+//DEV0_PF0_PF_MMIO0_FENCE_RANGE0_END
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE0_END__ADDRESS__SHIFT                                                    0x0
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE0_END__ADDRESS_MASK                                                      0x3FFFFFFFL
+//DEV0_PF0_PF_MMIO0_FENCE_RANGE1_START
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE1_START__ADDRESS__SHIFT                                                  0x0
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE1_START__ADDRESS_MASK                                                    0x3FFFFFFFL
+//DEV0_PF0_PF_MMIO0_FENCE_RANGE1_END
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE1_END__ADDRESS__SHIFT                                                    0x0
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE1_END__ADDRESS_MASK                                                      0x3FFFFFFFL
+//DEV0_PF0_PF_MMIO0_FENCE_RANGE2_START
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE2_START__ADDRESS__SHIFT                                                  0x0
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE2_START__ADDRESS_MASK                                                    0x3FFFFFFFL
+//DEV0_PF0_PF_MMIO0_FENCE_RANGE2_END
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE2_END__ADDRESS__SHIFT                                                    0x0
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE2_END__ADDRESS_MASK                                                      0x3FFFFFFFL
+//DEV0_PF0_PF_MMIO0_FENCE_RANGE3_START
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE3_START__ADDRESS__SHIFT                                                  0x0
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE3_START__ADDRESS_MASK                                                    0x3FFFFFFFL
+//DEV0_PF0_PF_MMIO0_FENCE_RANGE3_END
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE3_END__ADDRESS__SHIFT                                                    0x0
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE3_END__ADDRESS_MASK                                                      0x3FFFFFFFL
+//DEV0_PF0_PF_MMIO0_FENCE_RANGE4_START
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE4_START__ADDRESS__SHIFT                                                  0x0
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE4_START__ADDRESS_MASK                                                    0x3FFFFFFFL
+//DEV0_PF0_PF_MMIO0_FENCE_RANGE4_END
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE4_END__ADDRESS__SHIFT                                                    0x0
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE4_END__ADDRESS_MASK                                                      0x3FFFFFFFL
+//DEV0_PF0_PF_MMIO0_FENCE_RANGE5_START
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE5_START__ADDRESS__SHIFT                                                  0x0
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE5_START__ADDRESS_MASK                                                    0x3FFFFFFFL
+//DEV0_PF0_PF_MMIO0_FENCE_RANGE5_END
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE5_END__ADDRESS__SHIFT                                                    0x0
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE5_END__ADDRESS_MASK                                                      0x3FFFFFFFL
+//DEV0_PF0_PF_MMIO0_FENCE_RANGE6_START
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE6_START__ADDRESS__SHIFT                                                  0x0
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE6_START__ADDRESS_MASK                                                    0x3FFFFFFFL
+//DEV0_PF0_PF_MMIO0_FENCE_RANGE6_END
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE6_END__ADDRESS__SHIFT                                                    0x0
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE6_END__ADDRESS_MASK                                                      0x3FFFFFFFL
+//DEV0_PF0_PF_MMIO0_FENCE_RANGE7_START
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE7_START__ADDRESS__SHIFT                                                  0x0
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE7_START__ADDRESS_MASK                                                    0x3FFFFFFFL
+//DEV0_PF0_PF_MMIO0_FENCE_RANGE7_END
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE7_END__ADDRESS__SHIFT                                                    0x0
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE7_END__ADDRESS_MASK                                                      0x3FFFFFFFL
+//DEV0_PF0_PF_MMIO0_FENCE_RANGE8_START
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE8_START__ADDRESS__SHIFT                                                  0x0
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE8_START__ADDRESS_MASK                                                    0x3FFFFFFFL
+//DEV0_PF0_PF_MMIO0_FENCE_RANGE8_END
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE8_END__ADDRESS__SHIFT                                                    0x0
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE8_END__ADDRESS_MASK                                                      0x3FFFFFFFL
+//DEV0_PF0_PF_MMIO0_FENCE_RANGE9_START
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE9_START__ADDRESS__SHIFT                                                  0x0
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE9_START__ADDRESS_MASK                                                    0x3FFFFFFFL
+//DEV0_PF0_PF_MMIO0_FENCE_RANGE9_END
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE9_END__ADDRESS__SHIFT                                                    0x0
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE9_END__ADDRESS_MASK                                                      0x3FFFFFFFL
+//DEV0_PF0_PF_MMIO0_FENCE_RANGE10_START
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE10_START__ADDRESS__SHIFT                                                 0x0
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE10_START__ADDRESS_MASK                                                   0x3FFFFFFFL
+//DEV0_PF0_PF_MMIO0_FENCE_RANGE10_END
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE10_END__ADDRESS__SHIFT                                                   0x0
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE10_END__ADDRESS_MASK                                                     0x3FFFFFFFL
+//DEV0_PF0_PF_MMIO0_FENCE_RANGE11_START
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE11_START__ADDRESS__SHIFT                                                 0x0
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE11_START__ADDRESS_MASK                                                   0x3FFFFFFFL
+//DEV0_PF0_PF_MMIO0_FENCE_RANGE11_END
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE11_END__ADDRESS__SHIFT                                                   0x0
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE11_END__ADDRESS_MASK                                                     0x3FFFFFFFL
+//DEV0_PF0_PF_MMIO0_FENCE_RANGE12_START
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE12_START__ADDRESS__SHIFT                                                 0x0
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE12_START__ADDRESS_MASK                                                   0x3FFFFFFFL
+//DEV0_PF0_PF_MMIO0_FENCE_RANGE12_END
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE12_END__ADDRESS__SHIFT                                                   0x0
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE12_END__ADDRESS_MASK                                                     0x3FFFFFFFL
+//DEV0_PF0_PF_MMIO0_FENCE_RANGE13_START
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE13_START__ADDRESS__SHIFT                                                 0x0
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE13_START__ADDRESS_MASK                                                   0x3FFFFFFFL
+//DEV0_PF0_PF_MMIO0_FENCE_RANGE13_END
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE13_END__ADDRESS__SHIFT                                                   0x0
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE13_END__ADDRESS_MASK                                                     0x3FFFFFFFL
+//DEV0_PF0_PF_MMIO0_FENCE_RANGE14_START
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE14_START__ADDRESS__SHIFT                                                 0x0
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE14_START__ADDRESS_MASK                                                   0x3FFFFFFFL
+//DEV0_PF0_PF_MMIO0_FENCE_RANGE14_END
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE14_END__ADDRESS__SHIFT                                                   0x0
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE14_END__ADDRESS_MASK                                                     0x3FFFFFFFL
+//DEV0_PF0_PF_MMIO0_FENCE_RANGE15_START
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE15_START__ADDRESS__SHIFT                                                 0x0
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE15_START__ADDRESS_MASK                                                   0x3FFFFFFFL
+//DEV0_PF0_PF_MMIO0_FENCE_RANGE15_END
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE15_END__ADDRESS__SHIFT                                                   0x0
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE15_END__ADDRESS_MASK                                                     0x3FFFFFFFL
+//DEV0_PF0_PF_MMIO0_FENCE_RANGE16_START
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE16_START__ADDRESS__SHIFT                                                 0x0
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE16_START__ADDRESS_MASK                                                   0x3FFFFFFFL
+//DEV0_PF0_PF_MMIO0_FENCE_RANGE16_END
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE16_END__ADDRESS__SHIFT                                                   0x0
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE16_END__ADDRESS_MASK                                                     0x3FFFFFFFL
+//DEV0_PF0_PF_MMIO0_FENCE_RANGE17_START
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE17_START__ADDRESS__SHIFT                                                 0x0
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE17_START__ADDRESS_MASK                                                   0x3FFFFFFFL
+//DEV0_PF0_PF_MMIO0_FENCE_RANGE17_END
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE17_END__ADDRESS__SHIFT                                                   0x0
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE17_END__ADDRESS_MASK                                                     0x3FFFFFFFL
+//DEV0_PF0_PF_MMIO0_FENCE_RANGE18_START
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE18_START__ADDRESS__SHIFT                                                 0x0
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE18_START__ADDRESS_MASK                                                   0x3FFFFFFFL
+//DEV0_PF0_PF_MMIO0_FENCE_RANGE18_END
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE18_END__ADDRESS__SHIFT                                                   0x0
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE18_END__ADDRESS_MASK                                                     0x3FFFFFFFL
+//DEV0_PF0_PF_MMIO0_FENCE_RANGE19_START
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE19_START__ADDRESS__SHIFT                                                 0x0
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE19_START__ADDRESS_MASK                                                   0x3FFFFFFFL
+//DEV0_PF0_PF_MMIO0_FENCE_RANGE19_END
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE19_END__ADDRESS__SHIFT                                                   0x0
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE19_END__ADDRESS_MASK                                                     0x3FFFFFFFL
+//DEV0_PF0_PF_MMIO0_FENCE_RANGE20_START
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE20_START__ADDRESS__SHIFT                                                 0x0
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE20_START__ADDRESS_MASK                                                   0x3FFFFFFFL
+//DEV0_PF0_PF_MMIO0_FENCE_RANGE20_END
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE20_END__ADDRESS__SHIFT                                                   0x0
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE20_END__ADDRESS_MASK                                                     0x3FFFFFFFL
+//DEV0_PF0_PF_MMIO0_FENCE_RANGE21_START
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE21_START__ADDRESS__SHIFT                                                 0x0
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE21_START__ADDRESS_MASK                                                   0x3FFFFFFFL
+//DEV0_PF0_PF_MMIO0_FENCE_RANGE21_END
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE21_END__ADDRESS__SHIFT                                                   0x0
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE21_END__ADDRESS_MASK                                                     0x3FFFFFFFL
+//DEV0_PF0_PF_MMIO0_FENCE_RANGE22_START
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE22_START__ADDRESS__SHIFT                                                 0x0
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE22_START__ADDRESS_MASK                                                   0x3FFFFFFFL
+//DEV0_PF0_PF_MMIO0_FENCE_RANGE22_END
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE22_END__ADDRESS__SHIFT                                                   0x0
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE22_END__ADDRESS_MASK                                                     0x3FFFFFFFL
+//DEV0_PF0_PF_MMIO0_FENCE_RANGE23_START
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE23_START__ADDRESS__SHIFT                                                 0x0
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE23_START__ADDRESS_MASK                                                   0x3FFFFFFFL
+//DEV0_PF0_PF_MMIO0_FENCE_RANGE23_END
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE23_END__ADDRESS__SHIFT                                                   0x0
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE23_END__ADDRESS_MASK                                                     0x3FFFFFFFL
+//DEV0_PF0_PF_MMIO0_FENCE_RANGE24_START
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE24_START__ADDRESS__SHIFT                                                 0x0
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE24_START__ADDRESS_MASK                                                   0x3FFFFFFFL
+//DEV0_PF0_PF_MMIO0_FENCE_RANGE24_END
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE24_END__ADDRESS__SHIFT                                                   0x0
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE24_END__ADDRESS_MASK                                                     0x3FFFFFFFL
+//DEV0_PF0_PF_MMIO0_FENCE_RANGE25_START
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE25_START__ADDRESS__SHIFT                                                 0x0
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE25_START__ADDRESS_MASK                                                   0x3FFFFFFFL
+//DEV0_PF0_PF_MMIO0_FENCE_RANGE25_END
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE25_END__ADDRESS__SHIFT                                                   0x0
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE25_END__ADDRESS_MASK                                                     0x3FFFFFFFL
+//DEV0_PF0_PF_MMIO0_FENCE_RANGE26_START
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE26_START__ADDRESS__SHIFT                                                 0x0
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE26_START__ADDRESS_MASK                                                   0x3FFFFFFFL
+//DEV0_PF0_PF_MMIO0_FENCE_RANGE26_END
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE26_END__ADDRESS__SHIFT                                                   0x0
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE26_END__ADDRESS_MASK                                                     0x3FFFFFFFL
+//DEV0_PF0_PF_MMIO0_FENCE_RANGE27_START
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE27_START__ADDRESS__SHIFT                                                 0x0
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE27_START__ADDRESS_MASK                                                   0x3FFFFFFFL
+//DEV0_PF0_PF_MMIO0_FENCE_RANGE27_END
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE27_END__ADDRESS__SHIFT                                                   0x0
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE27_END__ADDRESS_MASK                                                     0x3FFFFFFFL
+//DEV0_PF0_PF_MMIO0_FENCE_RANGE28_START
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE28_START__ADDRESS__SHIFT                                                 0x0
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE28_START__ADDRESS_MASK                                                   0x3FFFFFFFL
+//DEV0_PF0_PF_MMIO0_FENCE_RANGE28_END
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE28_END__ADDRESS__SHIFT                                                   0x0
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE28_END__ADDRESS_MASK                                                     0x3FFFFFFFL
+//DEV0_PF0_PF_MMIO0_FENCE_RANGE29_START
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE29_START__ADDRESS__SHIFT                                                 0x0
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE29_START__ADDRESS_MASK                                                   0x3FFFFFFFL
+//DEV0_PF0_PF_MMIO0_FENCE_RANGE29_END
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE29_END__ADDRESS__SHIFT                                                   0x0
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE29_END__ADDRESS_MASK                                                     0x3FFFFFFFL
+//DEV0_PF0_PF_MMIO0_FENCE_RANGE30_START
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE30_START__ADDRESS__SHIFT                                                 0x0
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE30_START__ADDRESS_MASK                                                   0x3FFFFFFFL
+//DEV0_PF0_PF_MMIO0_FENCE_RANGE30_END
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE30_END__ADDRESS__SHIFT                                                   0x0
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE30_END__ADDRESS_MASK                                                     0x3FFFFFFFL
+//DEV0_PF0_PF_MMIO0_FENCE_RANGE31_START
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE31_START__ADDRESS__SHIFT                                                 0x0
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE31_START__ADDRESS_MASK                                                   0x3FFFFFFFL
+//DEV0_PF0_PF_MMIO0_FENCE_RANGE31_END
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE31_END__ADDRESS__SHIFT                                                   0x0
+#define DEV0_PF0_PF_MMIO0_FENCE_RANGE31_END__ADDRESS_MASK                                                     0x3FFFFFFFL
+//DEV0_PF1_PF_MMIO0_FENCE_WR
+#define DEV0_PF1_PF_MMIO0_FENCE_WR__ENABLE__SHIFT                                                             0x0
+#define DEV0_PF1_PF_MMIO0_FENCE_WR__ENABLE_MASK                                                               0xFFFFFFFFL
+//DEV0_PF1_PF_MMIO0_FENCE_RD
+#define DEV0_PF1_PF_MMIO0_FENCE_RD__ENABLE__SHIFT                                                             0x0
+#define DEV0_PF1_PF_MMIO0_FENCE_RD__ENABLE_MASK                                                               0xFFFFFFFFL
+//DEV0_PF1_PF_MMIO0_FENCE_RANGE0_START
+#define DEV0_PF1_PF_MMIO0_FENCE_RANGE0_START__ADDRESS__SHIFT                                                  0x0
+#define DEV0_PF1_PF_MMIO0_FENCE_RANGE0_START__ADDRESS_MASK                                                    0x3FFFFFFFL
+//DEV0_PF1_PF_MMIO0_FENCE_RANGE0_END
+#define DEV0_PF1_PF_MMIO0_FENCE_RANGE0_END__ADDRESS__SHIFT                                                    0x0
+#define DEV0_PF1_PF_MMIO0_FENCE_RANGE0_END__ADDRESS_MASK                                                      0x3FFFFFFFL
+//DEV0_PF1_PF_MMIO0_FENCE_RANGE1_START
+#define DEV0_PF1_PF_MMIO0_FENCE_RANGE1_START__ADDRESS__SHIFT                                                  0x0
+#define DEV0_PF1_PF_MMIO0_FENCE_RANGE1_START__ADDRESS_MASK                                                    0x3FFFFFFFL
+//DEV0_PF1_PF_MMIO0_FENCE_RANGE1_END
+#define DEV0_PF1_PF_MMIO0_FENCE_RANGE1_END__ADDRESS__SHIFT                                                    0x0
+#define DEV0_PF1_PF_MMIO0_FENCE_RANGE1_END__ADDRESS_MASK                                                      0x3FFFFFFFL
+//DEV0_PF1_PF_MMIO0_FENCE_RANGE2_START
+#define DEV0_PF1_PF_MMIO0_FENCE_RANGE2_START__ADDRESS__SHIFT                                                  0x0
+#define DEV0_PF1_PF_MMIO0_FENCE_RANGE2_START__ADDRESS_MASK                                                    0x3FFFFFFFL
+//DEV0_PF1_PF_MMIO0_FENCE_RANGE2_END
+#define DEV0_PF1_PF_MMIO0_FENCE_RANGE2_END__ADDRESS__SHIFT                                                    0x0
+#define DEV0_PF1_PF_MMIO0_FENCE_RANGE2_END__ADDRESS_MASK                                                      0x3FFFFFFFL
+//DEV0_PF1_PF_MMIO0_FENCE_RANGE3_START
+#define DEV0_PF1_PF_MMIO0_FENCE_RANGE3_START__ADDRESS__SHIFT                                                  0x0
+#define DEV0_PF1_PF_MMIO0_FENCE_RANGE3_START__ADDRESS_MASK                                                    0x3FFFFFFFL
+//DEV0_PF1_PF_MMIO0_FENCE_RANGE3_END
+#define DEV0_PF1_PF_MMIO0_FENCE_RANGE3_END__ADDRESS__SHIFT                                                    0x0
+#define DEV0_PF1_PF_MMIO0_FENCE_RANGE3_END__ADDRESS_MASK                                                      0x3FFFFFFFL
+//MISC_SCRATCH
+#define MISC_SCRATCH__MISC_SCRATCH0__SHIFT                                                                    0x0
+#define MISC_SCRATCH__MISC_SCRATCH0_MASK                                                                      0xFFFFFFFFL
+//INTR_LINE_POLARITY
+#define INTR_LINE_POLARITY__INTR_LINE_POLARITY_DEV0__SHIFT                                                    0x0
+#define INTR_LINE_POLARITY__INTR_LINE_POLARITY_DEV0_MASK                                                      0x000000FFL
+//INTR_LINE_ENABLE
+#define INTR_LINE_ENABLE__INTR_LINE_ENABLE_DEV0__SHIFT                                                        0x0
+#define INTR_LINE_ENABLE__INTR_LINE_ENABLE_DEV0_MASK                                                          0x000000FFL
+//OUTSTANDING_VC_ALLOC
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC0_ALLOC__SHIFT                                                0x0
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC1_ALLOC__SHIFT                                                0x2
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC2_ALLOC__SHIFT                                                0x4
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC3_ALLOC__SHIFT                                                0x6
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC4_ALLOC__SHIFT                                                0x8
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC5_ALLOC__SHIFT                                                0xa
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC6_ALLOC__SHIFT                                                0xc
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC7_ALLOC__SHIFT                                                0xe
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_THRD__SHIFT                                                     0x10
+#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC0_ALLOC__SHIFT                                                0x18
+#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC1_ALLOC__SHIFT                                                0x1a
+#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_THRD__SHIFT                                                     0x1c
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC0_ALLOC_MASK                                                  0x00000003L
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC1_ALLOC_MASK                                                  0x0000000CL
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC2_ALLOC_MASK                                                  0x00000030L
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC3_ALLOC_MASK                                                  0x000000C0L
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC4_ALLOC_MASK                                                  0x00000300L
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC5_ALLOC_MASK                                                  0x00000C00L
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC6_ALLOC_MASK                                                  0x00003000L
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_VC7_ALLOC_MASK                                                  0x0000C000L
+#define OUTSTANDING_VC_ALLOC__DMA_OUTSTANDING_THRD_MASK                                                       0x000F0000L
+#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC0_ALLOC_MASK                                                  0x03000000L
+#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_VC1_ALLOC_MASK                                                  0x0C000000L
+#define OUTSTANDING_VC_ALLOC__HST_OUTSTANDING_THRD_MASK                                                       0xF0000000L
+//BIFC_MISC_CTRL0
+#define BIFC_MISC_CTRL0__VWIRE_TARG_UNITID_CHECK_EN__SHIFT                                                    0x0
+#define BIFC_MISC_CTRL0__VWIRE_SRC_UNITID_CHECK_EN__SHIFT                                                     0x1
+#define BIFC_MISC_CTRL0__REG_ACTIVE_VLINK_L0_EN__SHIFT                                                        0x3
+#define BIFC_MISC_CTRL0__DMA_VC4_NON_DVM_STS__SHIFT                                                           0x4
+#define BIFC_MISC_CTRL0__DMA_CHAIN_BREAK_IN_RCMODE__SHIFT                                                     0x8
+#define BIFC_MISC_CTRL0__HST_ARB_CHAIN_LOCK_P__SHIFT                                                          0x9
+#define BIFC_MISC_CTRL0__GSI_SST_ARB_CHAIN_LOCK__SHIFT                                                        0xa
+#define BIFC_MISC_CTRL0__GSI_RD_SPLIT_STALL_FLUSH_EN__SHIFT                                                   0xb
+#define BIFC_MISC_CTRL0__GSI_RD_SPLIT_STALL_NPWR_DIS__SHIFT                                                   0xc
+#define BIFC_MISC_CTRL0__GSI_SET_PRECEEDINGWR_DIS__SHIFT                                                      0xd
+#define BIFC_MISC_CTRL0__HST_ARB_CHAIN_LOCK_NP__SHIFT                                                         0xe
+#define BIFC_MISC_CTRL0__HRP_CHAIN_DISABLE__SHIFT                                                             0xf
+#define BIFC_MISC_CTRL0__DMA_ATOMIC_LENGTH_CHK_DIS__SHIFT                                                     0x10
+#define BIFC_MISC_CTRL0__DMA_ATOMIC_FAILED_STS_SEL__SHIFT                                                     0x11
+#define BIFC_MISC_CTRL0__DMA_FORCE_VF_AS_PF_SRIOIVEN_LOW__SHIFT                                               0x12
+#define BIFC_MISC_CTRL0__DMA_ADDR_KEEP_PH__SHIFT                                                              0x13
+#define BIFC_MISC_CTRL0__RCC_GMI_TD_FORCE_ZERO__SHIFT                                                         0x14
+#define BIFC_MISC_CTRL0__HST_FLUSH_DEFER_EN__SHIFT                                                            0x15
+#define BIFC_MISC_CTRL0__HST_FLUSH_CLR_LOCK_EN__SHIFT                                                         0x16
+#define BIFC_MISC_CTRL0__STFETCH_BLOCK_IN_RST__SHIFT                                                          0x17
+#define BIFC_MISC_CTRL0__PCIE_CAPABILITY_PROT_DIS__SHIFT                                                      0x18
+#define BIFC_MISC_CTRL0__ATS_MSG_BLOCK_IN_RST__SHIFT                                                          0x19
+#define BIFC_MISC_CTRL0__DMA_2ND_REQ_DIS__SHIFT                                                               0x1a
+#define BIFC_MISC_CTRL0__PORT_DSTATE_BYPASS_MODE__SHIFT                                                       0x1b
+#define BIFC_MISC_CTRL0__PME_TURNOFF_MODE__SHIFT                                                              0x1c
+#define BIFC_MISC_CTRL0__DMA_ALL_RST_PROTECT_STS_SEL__SHIFT                                                   0x1d
+#define BIFC_MISC_CTRL0__HDP_P2P_DIRECT_ADD_ADJUST__SHIFT                                                     0x1e
+#define BIFC_MISC_CTRL0__PCIESWUS_SELECTION__SHIFT                                                            0x1f
+#define BIFC_MISC_CTRL0__VWIRE_TARG_UNITID_CHECK_EN_MASK                                                      0x00000001L
+#define BIFC_MISC_CTRL0__VWIRE_SRC_UNITID_CHECK_EN_MASK                                                       0x00000006L
+#define BIFC_MISC_CTRL0__REG_ACTIVE_VLINK_L0_EN_MASK                                                          0x00000008L
+#define BIFC_MISC_CTRL0__DMA_VC4_NON_DVM_STS_MASK                                                             0x000000F0L
+#define BIFC_MISC_CTRL0__DMA_CHAIN_BREAK_IN_RCMODE_MASK                                                       0x00000100L
+#define BIFC_MISC_CTRL0__HST_ARB_CHAIN_LOCK_P_MASK                                                            0x00000200L
+#define BIFC_MISC_CTRL0__GSI_SST_ARB_CHAIN_LOCK_MASK                                                          0x00000400L
+#define BIFC_MISC_CTRL0__GSI_RD_SPLIT_STALL_FLUSH_EN_MASK                                                     0x00000800L
+#define BIFC_MISC_CTRL0__GSI_RD_SPLIT_STALL_NPWR_DIS_MASK                                                     0x00001000L
+#define BIFC_MISC_CTRL0__GSI_SET_PRECEEDINGWR_DIS_MASK                                                        0x00002000L
+#define BIFC_MISC_CTRL0__HST_ARB_CHAIN_LOCK_NP_MASK                                                           0x00004000L
+#define BIFC_MISC_CTRL0__HRP_CHAIN_DISABLE_MASK                                                               0x00008000L
+#define BIFC_MISC_CTRL0__DMA_ATOMIC_LENGTH_CHK_DIS_MASK                                                       0x00010000L
+#define BIFC_MISC_CTRL0__DMA_ATOMIC_FAILED_STS_SEL_MASK                                                       0x00020000L
+#define BIFC_MISC_CTRL0__DMA_FORCE_VF_AS_PF_SRIOIVEN_LOW_MASK                                                 0x00040000L
+#define BIFC_MISC_CTRL0__DMA_ADDR_KEEP_PH_MASK                                                                0x00080000L
+#define BIFC_MISC_CTRL0__RCC_GMI_TD_FORCE_ZERO_MASK                                                           0x00100000L
+#define BIFC_MISC_CTRL0__HST_FLUSH_DEFER_EN_MASK                                                              0x00200000L
+#define BIFC_MISC_CTRL0__HST_FLUSH_CLR_LOCK_EN_MASK                                                           0x00400000L
+#define BIFC_MISC_CTRL0__STFETCH_BLOCK_IN_RST_MASK                                                            0x00800000L
+#define BIFC_MISC_CTRL0__PCIE_CAPABILITY_PROT_DIS_MASK                                                        0x01000000L
+#define BIFC_MISC_CTRL0__ATS_MSG_BLOCK_IN_RST_MASK                                                            0x02000000L
+#define BIFC_MISC_CTRL0__DMA_2ND_REQ_DIS_MASK                                                                 0x04000000L
+#define BIFC_MISC_CTRL0__PORT_DSTATE_BYPASS_MODE_MASK                                                         0x08000000L
+#define BIFC_MISC_CTRL0__PME_TURNOFF_MODE_MASK                                                                0x10000000L
+#define BIFC_MISC_CTRL0__DMA_ALL_RST_PROTECT_STS_SEL_MASK                                                     0x20000000L
+#define BIFC_MISC_CTRL0__HDP_P2P_DIRECT_ADD_ADJUST_MASK                                                       0x40000000L
+#define BIFC_MISC_CTRL0__PCIESWUS_SELECTION_MASK                                                              0x80000000L
+//BIFC_MISC_CTRL1
+#define BIFC_MISC_CTRL1__THT_HST_CPLD_POISON_REPORT__SHIFT                                                    0x0
+#define BIFC_MISC_CTRL1__DMA_REQ_POISON_REPORT__SHIFT                                                         0x1
+#define BIFC_MISC_CTRL1__DMA_REQ_ACSVIO_REPORT__SHIFT                                                         0x2
+#define BIFC_MISC_CTRL1__DMA_RSP_POISON_CPLD_REPORT__SHIFT                                                    0x3
+#define BIFC_MISC_CTRL1__GSI_SMN_WORST_ERR_STSTUS__SHIFT                                                      0x4
+#define BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE1_FOR_ERROR__SHIFT                                           0x5
+#define BIFC_MISC_CTRL1__GSI_RDWR_BALANCE_DIS__SHIFT                                                          0x6
+#define BIFC_MISC_CTRL1__GMI_ATOMIC_POISON_DROP__SHIFT                                                        0x7
+#define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_STS__SHIFT                                                      0x8
+#define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_DATASTS__SHIFT                                                  0xa
+#define BIFC_MISC_CTRL1__DROP_OTHER_HT_ADDR_REQ__SHIFT                                                        0xc
+#define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE__SHIFT                                                 0xd
+#define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE_VALUE__SHIFT                                           0xe
+#define BIFC_MISC_CTRL1__UPS_SDP_RDY_TIE1__SHIFT                                                              0xf
+#define BIFC_MISC_CTRL1__GMI_RCC_DN_BME_DROP_DIS__SHIFT                                                       0x10
+#define BIFC_MISC_CTRL1__GMI_RCC_EP_BME_DROP_DIS__SHIFT                                                       0x11
+#define BIFC_MISC_CTRL1__GMI_BIH_DN_BME_DROP_DIS__SHIFT                                                       0x12
+#define BIFC_MISC_CTRL1__GMI_BIH_EP_BME_DROP_DIS__SHIFT                                                       0x13
+#define BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE0_FOR_ERROR__SHIFT                                           0x14
+#define BIFC_MISC_CTRL1__DMAWRREQ_HSTWRRSP_ORDER_FORCE__SHIFT                                                 0x15
+#define BIFC_MISC_CTRL1__DMAWRREQ_HSTWRRSP_ORDER_FORCE_VALUE__SHIFT                                           0x16
+#define BIFC_MISC_CTRL1__GMI_ATOMIC_POISON_FOR_AERLOG__SHIFT                                                  0x17
+#define BIFC_MISC_CTRL1__GMI_RDSIZED_REQATTR_MASK__SHIFT                                                      0x18
+#define BIFC_MISC_CTRL1__GMI_RDSIZEDDW_REQATTR_MASK__SHIFT                                                    0x19
+#define BIFC_MISC_CTRL1__GMI_WRSIZED_REQATTR_MASK__SHIFT                                                      0x1a
+#define BIFC_MISC_CTRL1__GMI_WRSIZEDFL_REQATTR_MASK__SHIFT                                                    0x1b
+#define BIFC_MISC_CTRL1__GMI_FORCE_NOT_SEND_NON_BASEVC_RSPCREDIT__SHIFT                                       0x1c
+#define BIFC_MISC_CTRL1__GMI_CPLBUF_EN__SHIFT                                                                 0x1d
+#define BIFC_MISC_CTRL1__GMI_MSG_BLOCKLVL_SEL__SHIFT                                                          0x1e
+#define BIFC_MISC_CTRL1__THT_HST_CPLD_POISON_REPORT_MASK                                                      0x00000001L
+#define BIFC_MISC_CTRL1__DMA_REQ_POISON_REPORT_MASK                                                           0x00000002L
+#define BIFC_MISC_CTRL1__DMA_REQ_ACSVIO_REPORT_MASK                                                           0x00000004L
+#define BIFC_MISC_CTRL1__DMA_RSP_POISON_CPLD_REPORT_MASK                                                      0x00000008L
+#define BIFC_MISC_CTRL1__GSI_SMN_WORST_ERR_STSTUS_MASK                                                        0x00000010L
+#define BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE1_FOR_ERROR_MASK                                             0x00000020L
+#define BIFC_MISC_CTRL1__GSI_RDWR_BALANCE_DIS_MASK                                                            0x00000040L
+#define BIFC_MISC_CTRL1__GMI_ATOMIC_POISON_DROP_MASK                                                          0x00000080L
+#define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_STS_MASK                                                        0x00000300L
+#define BIFC_MISC_CTRL1__HST_UNSUPPORT_SDPCMD_DATASTS_MASK                                                    0x00000C00L
+#define BIFC_MISC_CTRL1__DROP_OTHER_HT_ADDR_REQ_MASK                                                          0x00001000L
+#define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE_MASK                                                   0x00002000L
+#define BIFC_MISC_CTRL1__DMAWRREQ_HSTRDRSP_ORDER_FORCE_VALUE_MASK                                             0x00004000L
+#define BIFC_MISC_CTRL1__UPS_SDP_RDY_TIE1_MASK                                                                0x00008000L
+#define BIFC_MISC_CTRL1__GMI_RCC_DN_BME_DROP_DIS_MASK                                                         0x00010000L
+#define BIFC_MISC_CTRL1__GMI_RCC_EP_BME_DROP_DIS_MASK                                                         0x00020000L
+#define BIFC_MISC_CTRL1__GMI_BIH_DN_BME_DROP_DIS_MASK                                                         0x00040000L
+#define BIFC_MISC_CTRL1__GMI_BIH_EP_BME_DROP_DIS_MASK                                                         0x00080000L
+#define BIFC_MISC_CTRL1__GSI_SDP_RDRSP_DATA_FORCE0_FOR_ERROR_MASK                                             0x00100000L
+#define BIFC_MISC_CTRL1__DMAWRREQ_HSTWRRSP_ORDER_FORCE_MASK                                                   0x00200000L
+#define BIFC_MISC_CTRL1__DMAWRREQ_HSTWRRSP_ORDER_FORCE_VALUE_MASK                                             0x00400000L
+#define BIFC_MISC_CTRL1__GMI_ATOMIC_POISON_FOR_AERLOG_MASK                                                    0x00800000L
+#define BIFC_MISC_CTRL1__GMI_RDSIZED_REQATTR_MASK_MASK                                                        0x01000000L
+#define BIFC_MISC_CTRL1__GMI_RDSIZEDDW_REQATTR_MASK_MASK                                                      0x02000000L
+#define BIFC_MISC_CTRL1__GMI_WRSIZED_REQATTR_MASK_MASK                                                        0x04000000L
+#define BIFC_MISC_CTRL1__GMI_WRSIZEDFL_REQATTR_MASK_MASK                                                      0x08000000L
+#define BIFC_MISC_CTRL1__GMI_FORCE_NOT_SEND_NON_BASEVC_RSPCREDIT_MASK                                         0x10000000L
+#define BIFC_MISC_CTRL1__GMI_CPLBUF_EN_MASK                                                                   0x20000000L
+#define BIFC_MISC_CTRL1__GMI_MSG_BLOCKLVL_SEL_MASK                                                            0xC0000000L
+//BIFC_BME_ERR_LOG_LB
+#define BIFC_BME_ERR_LOG_LB__DMA_ON_BME_LOW_DEV0_F0__SHIFT                                                    0x0
+#define BIFC_BME_ERR_LOG_LB__DMA_ON_BME_LOW_DEV0_F1__SHIFT                                                    0x1
+#define BIFC_BME_ERR_LOG_LB__CLEAR_DMA_ON_BME_LOW_DEV0_F0__SHIFT                                              0x10
+#define BIFC_BME_ERR_LOG_LB__CLEAR_DMA_ON_BME_LOW_DEV0_F1__SHIFT                                              0x11
+#define BIFC_BME_ERR_LOG_LB__DMA_ON_BME_LOW_DEV0_F0_MASK                                                      0x00000001L
+#define BIFC_BME_ERR_LOG_LB__DMA_ON_BME_LOW_DEV0_F1_MASK                                                      0x00000002L
+#define BIFC_BME_ERR_LOG_LB__CLEAR_DMA_ON_BME_LOW_DEV0_F0_MASK                                                0x00010000L
+#define BIFC_BME_ERR_LOG_LB__CLEAR_DMA_ON_BME_LOW_DEV0_F1_MASK                                                0x00020000L
+//BIFC_LC_TIMER_CTRL
+#define BIFC_LC_TIMER_CTRL__ASPM_IDLE_TIMER_SCALE__SHIFT                                                      0x0
+#define BIFC_LC_TIMER_CTRL__L1_EXIT_TIMER_SCALE__SHIFT                                                        0x10
+#define BIFC_LC_TIMER_CTRL__ASPM_IDLE_TIMER_SCALE_MASK                                                        0x0000FFFFL
+#define BIFC_LC_TIMER_CTRL__L1_EXIT_TIMER_SCALE_MASK                                                          0xFFFF0000L
+//BIFC_RCCBIH_BME_ERR_LOG0
+#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F0__SHIFT                                            0x0
+#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F1__SHIFT                                            0x1
+#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F0__SHIFT                                      0x10
+#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F1__SHIFT                                      0x11
+#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F0_MASK                                              0x00000001L
+#define BIFC_RCCBIH_BME_ERR_LOG0__RCCBIH_ON_BME_LOW_DEV0_F1_MASK                                              0x00000002L
+#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F0_MASK                                        0x00010000L
+#define BIFC_RCCBIH_BME_ERR_LOG0__CLEAR_RCCBIH_ON_BME_LOW_DEV0_F1_MASK                                        0x00020000L
+//BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F0__SHIFT                                    0x0
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F0__SHIFT                                   0x2
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_IDO_DEV0_F0__SHIFT                                      0x4
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F0__SHIFT                                     0x6
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F0__SHIFT                                    0x8
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F0__SHIFT                                    0xa
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F0__SHIFT                                   0xc
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_NONIDO_DEV0_F0__SHIFT                                   0xe
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F1__SHIFT                                    0x10
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F1__SHIFT                                   0x12
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_IDO_DEV0_F1__SHIFT                                      0x14
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F1__SHIFT                                     0x16
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F1__SHIFT                                    0x18
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F1__SHIFT                                    0x1a
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F1__SHIFT                                   0x1c
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_NONIDO_DEV0_F1__SHIFT                                   0x1e
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F0_MASK                                      0x00000003L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F0_MASK                                     0x0000000CL
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_IDO_DEV0_F0_MASK                                        0x00000030L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F0_MASK                                       0x000000C0L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F0_MASK                                      0x00000300L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F0_MASK                                      0x00000C00L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F0_MASK                                     0x00003000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_NONIDO_DEV0_F0_MASK                                     0x0000C000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_P_DEV0_F1_MASK                                      0x00030000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_IDO_OVERIDE_NP_DEV0_F1_MASK                                     0x000C0000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_IDO_DEV0_F1_MASK                                        0x00300000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_P_DEV0_F1_MASK                                       0x00C00000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_RO_OVERIDE_NP_DEV0_F1_MASK                                      0x03000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_P_DEV0_F1_MASK                                      0x0C000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__TX_SNR_OVERIDE_NP_DEV0_F1_MASK                                     0x30000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F0_F1__BLKLVL_FOR_NONIDO_DEV0_F1_MASK                                     0xC0000000L
+//BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F2__SHIFT                                    0x0
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F2__SHIFT                                   0x2
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_IDO_DEV0_F2__SHIFT                                      0x4
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F2__SHIFT                                     0x6
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F2__SHIFT                                    0x8
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F2__SHIFT                                    0xa
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F2__SHIFT                                   0xc
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_NONIDO_DEV0_F2__SHIFT                                   0xe
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F3__SHIFT                                    0x10
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F3__SHIFT                                   0x12
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_IDO_DEV0_F3__SHIFT                                      0x14
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F3__SHIFT                                     0x16
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F3__SHIFT                                    0x18
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F3__SHIFT                                    0x1a
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F3__SHIFT                                   0x1c
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_NONIDO_DEV0_F3__SHIFT                                   0x1e
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F2_MASK                                      0x00000003L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F2_MASK                                     0x0000000CL
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_IDO_DEV0_F2_MASK                                        0x00000030L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F2_MASK                                       0x000000C0L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F2_MASK                                      0x00000300L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F2_MASK                                      0x00000C00L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F2_MASK                                     0x00003000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_NONIDO_DEV0_F2_MASK                                     0x0000C000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_P_DEV0_F3_MASK                                      0x00030000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_IDO_OVERIDE_NP_DEV0_F3_MASK                                     0x000C0000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_IDO_DEV0_F3_MASK                                        0x00300000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_P_DEV0_F3_MASK                                       0x00C00000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_RO_OVERIDE_NP_DEV0_F3_MASK                                      0x03000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_P_DEV0_F3_MASK                                      0x0C000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__TX_SNR_OVERIDE_NP_DEV0_F3_MASK                                     0x30000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F2_F3__BLKLVL_FOR_NONIDO_DEV0_F3_MASK                                     0xC0000000L
+//BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F4__SHIFT                                    0x0
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F4__SHIFT                                   0x2
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_IDO_DEV0_F4__SHIFT                                      0x4
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F4__SHIFT                                     0x6
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F4__SHIFT                                    0x8
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F4__SHIFT                                    0xa
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F4__SHIFT                                   0xc
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_NONIDO_DEV0_F4__SHIFT                                   0xe
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F5__SHIFT                                    0x10
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F5__SHIFT                                   0x12
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_IDO_DEV0_F5__SHIFT                                      0x14
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F5__SHIFT                                     0x16
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F5__SHIFT                                    0x18
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F5__SHIFT                                    0x1a
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F5__SHIFT                                   0x1c
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_NONIDO_DEV0_F5__SHIFT                                   0x1e
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F4_MASK                                      0x00000003L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F4_MASK                                     0x0000000CL
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_IDO_DEV0_F4_MASK                                        0x00000030L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F4_MASK                                       0x000000C0L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F4_MASK                                      0x00000300L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F4_MASK                                      0x00000C00L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F4_MASK                                     0x00003000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_NONIDO_DEV0_F4_MASK                                     0x0000C000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_P_DEV0_F5_MASK                                      0x00030000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_IDO_OVERIDE_NP_DEV0_F5_MASK                                     0x000C0000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_IDO_DEV0_F5_MASK                                        0x00300000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_P_DEV0_F5_MASK                                       0x00C00000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_RO_OVERIDE_NP_DEV0_F5_MASK                                      0x03000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_P_DEV0_F5_MASK                                      0x0C000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__TX_SNR_OVERIDE_NP_DEV0_F5_MASK                                     0x30000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F4_F5__BLKLVL_FOR_NONIDO_DEV0_F5_MASK                                     0xC0000000L
+//BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F6__SHIFT                                    0x0
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F6__SHIFT                                   0x2
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_IDO_DEV0_F6__SHIFT                                      0x4
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F6__SHIFT                                     0x6
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F6__SHIFT                                    0x8
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F6__SHIFT                                    0xa
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F6__SHIFT                                   0xc
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_NONIDO_DEV0_F6__SHIFT                                   0xe
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F7__SHIFT                                    0x10
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F7__SHIFT                                   0x12
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_IDO_DEV0_F7__SHIFT                                      0x14
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F7__SHIFT                                     0x16
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F7__SHIFT                                    0x18
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F7__SHIFT                                    0x1a
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F7__SHIFT                                   0x1c
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_NONIDO_DEV0_F7__SHIFT                                   0x1e
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F6_MASK                                      0x00000003L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F6_MASK                                     0x0000000CL
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_IDO_DEV0_F6_MASK                                        0x00000030L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F6_MASK                                       0x000000C0L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F6_MASK                                      0x00000300L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F6_MASK                                      0x00000C00L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F6_MASK                                     0x00003000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_NONIDO_DEV0_F6_MASK                                     0x0000C000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_P_DEV0_F7_MASK                                      0x00030000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_IDO_OVERIDE_NP_DEV0_F7_MASK                                     0x000C0000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_IDO_DEV0_F7_MASK                                        0x00300000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_P_DEV0_F7_MASK                                       0x00C00000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_RO_OVERIDE_NP_DEV0_F7_MASK                                      0x03000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_P_DEV0_F7_MASK                                      0x0C000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__TX_SNR_OVERIDE_NP_DEV0_F7_MASK                                     0x30000000L
+#define BIFC_DMA_ATTR_OVERRIDE_DEV0_F6_F7__BLKLVL_FOR_NONIDO_DEV0_F7_MASK                                     0xC0000000L
+//BIFC_DMA_ATTR_CNTL2_DEV0
+#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F0__SHIFT                               0x0
+#define BIFC_DMA_ATTR_CNTL2_DEV0__NBIF_CDMA_ST_OVERRIDE_EN_DEV0_F0__SHIFT                                     0x1
+#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F1__SHIFT                               0x4
+#define BIFC_DMA_ATTR_CNTL2_DEV0__NBIF_CDMA_ST_OVERRIDE_EN_DEV0_F1__SHIFT                                     0x5
+#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F2__SHIFT                               0x8
+#define BIFC_DMA_ATTR_CNTL2_DEV0__NBIF_CDMA_ST_OVERRIDE_EN_DEV0_F2__SHIFT                                     0x9
+#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F3__SHIFT                               0xc
+#define BIFC_DMA_ATTR_CNTL2_DEV0__NBIF_CDMA_ST_OVERRIDE_EN_DEV0_F3__SHIFT                                     0xd
+#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F4__SHIFT                               0x10
+#define BIFC_DMA_ATTR_CNTL2_DEV0__NBIF_CDMA_ST_OVERRIDE_EN_DEV0_F4__SHIFT                                     0x11
+#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F5__SHIFT                               0x14
+#define BIFC_DMA_ATTR_CNTL2_DEV0__NBIF_CDMA_ST_OVERRIDE_EN_DEV0_F5__SHIFT                                     0x15
+#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F6__SHIFT                               0x18
+#define BIFC_DMA_ATTR_CNTL2_DEV0__NBIF_CDMA_ST_OVERRIDE_EN_DEV0_F6__SHIFT                                     0x19
+#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F7__SHIFT                               0x1c
+#define BIFC_DMA_ATTR_CNTL2_DEV0__NBIF_CDMA_ST_OVERRIDE_EN_DEV0_F7__SHIFT                                     0x1d
+#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F0_MASK                                 0x00000001L
+#define BIFC_DMA_ATTR_CNTL2_DEV0__NBIF_CDMA_ST_OVERRIDE_EN_DEV0_F0_MASK                                       0x00000002L
+#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F1_MASK                                 0x00000010L
+#define BIFC_DMA_ATTR_CNTL2_DEV0__NBIF_CDMA_ST_OVERRIDE_EN_DEV0_F1_MASK                                       0x00000020L
+#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F2_MASK                                 0x00000100L
+#define BIFC_DMA_ATTR_CNTL2_DEV0__NBIF_CDMA_ST_OVERRIDE_EN_DEV0_F2_MASK                                       0x00000200L
+#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F3_MASK                                 0x00001000L
+#define BIFC_DMA_ATTR_CNTL2_DEV0__NBIF_CDMA_ST_OVERRIDE_EN_DEV0_F3_MASK                                       0x00002000L
+#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F4_MASK                                 0x00010000L
+#define BIFC_DMA_ATTR_CNTL2_DEV0__NBIF_CDMA_ST_OVERRIDE_EN_DEV0_F4_MASK                                       0x00020000L
+#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F5_MASK                                 0x00100000L
+#define BIFC_DMA_ATTR_CNTL2_DEV0__NBIF_CDMA_ST_OVERRIDE_EN_DEV0_F5_MASK                                       0x00200000L
+#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F6_MASK                                 0x01000000L
+#define BIFC_DMA_ATTR_CNTL2_DEV0__NBIF_CDMA_ST_OVERRIDE_EN_DEV0_F6_MASK                                       0x02000000L
+#define BIFC_DMA_ATTR_CNTL2_DEV0__BLKLVL_BYPASS_PCIE_IDO_CONTROL_DEV0_F7_MASK                                 0x10000000L
+#define BIFC_DMA_ATTR_CNTL2_DEV0__NBIF_CDMA_ST_OVERRIDE_EN_DEV0_F7_MASK                                       0x20000000L
+//BIFC_MISC_CTRL2
+#define BIFC_MISC_CTRL2__DIH_INTR_STFETCH_BLOCK_IN_LINKDOWN__SHIFT                                            0x0
+#define BIFC_MISC_CTRL2__SLOW_GMI_UPS_RSP_CRED_REL_EN__SHIFT                                                  0x1
+#define BIFC_MISC_CTRL2__DMA_RSP_ECRC_REPORT__SHIFT                                                           0x2
+#define BIFC_MISC_CTRL2__SLFR_IGNORE_DATAERR_EN__SHIFT                                                        0x10
+#define BIFC_MISC_CTRL2__DATAERR_OVERRIDE_SLFR_BYTEEN_EN__SHIFT                                               0x11
+#define BIFC_MISC_CTRL2__PH_SUPPORT__SHIFT                                                                    0x12
+#define BIFC_MISC_CTRL2__GMI_FAIL_REQ_RTS_MASK__SHIFT                                                         0x16
+#define BIFC_MISC_CTRL2__NBIF_AERRPT_BACKPERSURE_EN__SHIFT                                                    0x17
+#define BIFC_MISC_CTRL2__DIH_INTR_STFETCH_BLOCK_IN_LINKDOWN_MASK                                              0x00000001L
+#define BIFC_MISC_CTRL2__SLOW_GMI_UPS_RSP_CRED_REL_EN_MASK                                                    0x00000002L
+#define BIFC_MISC_CTRL2__DMA_RSP_ECRC_REPORT_MASK                                                             0x00000004L
+#define BIFC_MISC_CTRL2__SLFR_IGNORE_DATAERR_EN_MASK                                                          0x00010000L
+#define BIFC_MISC_CTRL2__DATAERR_OVERRIDE_SLFR_BYTEEN_EN_MASK                                                 0x00020000L
+#define BIFC_MISC_CTRL2__PH_SUPPORT_MASK                                                                      0x003C0000L
+#define BIFC_MISC_CTRL2__GMI_FAIL_REQ_RTS_MASK_MASK                                                           0x00400000L
+#define BIFC_MISC_CTRL2__NBIF_AERRPT_BACKPERSURE_EN_MASK                                                      0x00800000L
+//BME_DUMMY_CNTL_0
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F0__SHIFT                                                     0x0
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F1__SHIFT                                                     0x2
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F2__SHIFT                                                     0x4
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F3__SHIFT                                                     0x6
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F4__SHIFT                                                     0x8
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F5__SHIFT                                                     0xa
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F6__SHIFT                                                     0xc
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F7__SHIFT                                                     0xe
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F0_MASK                                                       0x00000003L
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F1_MASK                                                       0x0000000CL
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F2_MASK                                                       0x00000030L
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F3_MASK                                                       0x000000C0L
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F4_MASK                                                       0x00000300L
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F5_MASK                                                       0x00000C00L
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F6_MASK                                                       0x00003000L
+#define BME_DUMMY_CNTL_0__BME_DUMMY_RSPSTS_DEV0_F7_MASK                                                       0x0000C000L
+//BIFC_THT_CNTL
+#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_RD_VC0__SHIFT                                                         0x0
+#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC0__SHIFT                                                         0x4
+#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC1__SHIFT                                                         0x8
+#define BIFC_THT_CNTL__UR_OVRD_FOR_ECRC_EN__SHIFT                                                             0x10
+#define BIFC_THT_CNTL__THT_NTB_VC0_APER0_ADSC_PUSH_DIS__SHIFT                                                 0x18
+#define BIFC_THT_CNTL__THT_NTB_VC0_OTHAPER_ADSC_PUSH_DIS__SHIFT                                               0x19
+#define BIFC_THT_CNTL__THT_NTB_VC1_APER0_ADSC_PUSH_DIS__SHIFT                                                 0x1a
+#define BIFC_THT_CNTL__THT_NTB_VC1_OTHAPER_ADSC_PUSH_DIS__SHIFT                                               0x1b
+#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_RD_VC0_MASK                                                           0x0000000FL
+#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC0_MASK                                                           0x000000F0L
+#define BIFC_THT_CNTL__CREDIT_ALLOC_THT_WR_VC1_MASK                                                           0x00000F00L
+#define BIFC_THT_CNTL__UR_OVRD_FOR_ECRC_EN_MASK                                                               0x00010000L
+#define BIFC_THT_CNTL__THT_NTB_VC0_APER0_ADSC_PUSH_DIS_MASK                                                   0x01000000L
+#define BIFC_THT_CNTL__THT_NTB_VC0_OTHAPER_ADSC_PUSH_DIS_MASK                                                 0x02000000L
+#define BIFC_THT_CNTL__THT_NTB_VC1_APER0_ADSC_PUSH_DIS_MASK                                                   0x04000000L
+#define BIFC_THT_CNTL__THT_NTB_VC1_OTHAPER_ADSC_PUSH_DIS_MASK                                                 0x08000000L
+//BIFC_HSTARB_CNTL
+#define BIFC_HSTARB_CNTL__SLVARB_MODE__SHIFT                                                                  0x0
+#define BIFC_HSTARB_CNTL__CFG_BLOCK_P_EN__SHIFT                                                               0x8
+#define BIFC_HSTARB_CNTL__SLVARB_MODE_MASK                                                                    0x00000003L
+#define BIFC_HSTARB_CNTL__CFG_BLOCK_P_EN_MASK                                                                 0x00000100L
+//BIFC_GSI_CNTL
+#define BIFC_GSI_CNTL__GSI_SDP_RSP_ARB_MODE__SHIFT                                                            0x0
+#define BIFC_GSI_CNTL__GSI_CPL_RSP_ARB_MODE__SHIFT                                                            0x2
+#define BIFC_GSI_CNTL__GSI_CPL_INTERLEAVING_EN__SHIFT                                                         0x6
+#define BIFC_GSI_CNTL__GSI_CPL_PCR_EP_CAUSE_UR_EN__SHIFT                                                      0x7
+#define BIFC_GSI_CNTL__GSI_CPL_SMN_P_EP_CAUSE_UR_EN__SHIFT                                                    0x8
+#define BIFC_GSI_CNTL__GSI_CPL_SMN_NP_EP_CAUSE_UR_EN__SHIFT                                                   0x9
+#define BIFC_GSI_CNTL__GSI_CPL_SST_EP_CAUSE_UR_EN__SHIFT                                                      0xa
+#define BIFC_GSI_CNTL__GSI_SDP_REQ_ARB_MODE__SHIFT                                                            0xb
+#define BIFC_GSI_CNTL__GSI_SMN_REQ_ARB_MODE__SHIFT                                                            0xd
+#define BIFC_GSI_CNTL__GSI_CPL_SST_ATOMIC_EP_CAUSE_UR_EN__SHIFT                                               0xf
+#define BIFC_GSI_CNTL__GSI_SMN_PARITY_CHK_BE_MSK__SHIFT                                                       0x10
+#define BIFC_GSI_CNTL__GSI_SMN_BURST_EN__SHIFT                                                                0x11
+#define BIFC_GSI_CNTL__GSI_SMN_256B_SPLIT_64B_EN__SHIFT                                                       0x12
+#define BIFC_GSI_CNTL__NBIF_UR_HPHIT_TRANS_DIS_EN__SHIFT                                                      0x16
+#define BIFC_GSI_CNTL__SMN_PP_PIPE_ENABLE__SHIFT                                                              0x1b
+#define BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_FBFLUSH__SHIFT                                                    0x1c
+#define BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_HDPFLUSH__SHIFT                                                   0x1d
+#define BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_HDPRD__SHIFT                                                      0x1e
+#define BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_ALL__SHIFT                                                        0x1f
+#define BIFC_GSI_CNTL__GSI_SDP_RSP_ARB_MODE_MASK                                                              0x00000003L
+#define BIFC_GSI_CNTL__GSI_CPL_RSP_ARB_MODE_MASK                                                              0x0000003CL
+#define BIFC_GSI_CNTL__GSI_CPL_INTERLEAVING_EN_MASK                                                           0x00000040L
+#define BIFC_GSI_CNTL__GSI_CPL_PCR_EP_CAUSE_UR_EN_MASK                                                        0x00000080L
+#define BIFC_GSI_CNTL__GSI_CPL_SMN_P_EP_CAUSE_UR_EN_MASK                                                      0x00000100L
+#define BIFC_GSI_CNTL__GSI_CPL_SMN_NP_EP_CAUSE_UR_EN_MASK                                                     0x00000200L
+#define BIFC_GSI_CNTL__GSI_CPL_SST_EP_CAUSE_UR_EN_MASK                                                        0x00000400L
+#define BIFC_GSI_CNTL__GSI_SDP_REQ_ARB_MODE_MASK                                                              0x00001800L
+#define BIFC_GSI_CNTL__GSI_SMN_REQ_ARB_MODE_MASK                                                              0x00006000L
+#define BIFC_GSI_CNTL__GSI_CPL_SST_ATOMIC_EP_CAUSE_UR_EN_MASK                                                 0x00008000L
+#define BIFC_GSI_CNTL__GSI_SMN_PARITY_CHK_BE_MSK_MASK                                                         0x00010000L
+#define BIFC_GSI_CNTL__GSI_SMN_BURST_EN_MASK                                                                  0x00020000L
+#define BIFC_GSI_CNTL__GSI_SMN_256B_SPLIT_64B_EN_MASK                                                         0x00040000L
+#define BIFC_GSI_CNTL__NBIF_UR_HPHIT_TRANS_DIS_EN_MASK                                                        0x00400000L
+#define BIFC_GSI_CNTL__SMN_PP_PIPE_ENABLE_MASK                                                                0x08000000L
+#define BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_FBFLUSH_MASK                                                      0x10000000L
+#define BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_HDPFLUSH_MASK                                                     0x20000000L
+#define BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_HDPRD_MASK                                                        0x40000000L
+#define BIFC_GSI_CNTL__HDP_FB_UPLIMIT_COUNT_ALL_MASK                                                          0x80000000L
+//BIFC_PCIEFUNC_CNTL
+#define BIFC_PCIEFUNC_CNTL__DMA_NON_PCIEFUNC_BUSDEVFUNC__SHIFT                                                0x0
+#define BIFC_PCIEFUNC_CNTL__MP1SYSHUBDATA_DRAM_IS_PCIEFUNC__SHIFT                                             0x10
+#define BIFC_PCIEFUNC_CNTL__DMA_NON_PCIEFUNC_BUSDEVFUNC_MASK                                                  0x0000FFFFL
+#define BIFC_PCIEFUNC_CNTL__MP1SYSHUBDATA_DRAM_IS_PCIEFUNC_MASK                                               0x00010000L
+//BIFC_PASID_CHECK_DIS
+#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F0__SHIFT                                                  0x0
+#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F1__SHIFT                                                  0x1
+#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F0_MASK                                                    0x00000001L
+#define BIFC_PASID_CHECK_DIS__PASID_CHECK_DIS_DEV0_F1_MASK                                                    0x00000002L
+//BIFC_SDP_CNTL_0
+#define BIFC_SDP_CNTL_0__HRP_SDP_DISCON_HYSTERESIS__SHIFT                                                     0x0
+#define BIFC_SDP_CNTL_0__GSI_SDP_DISCON_HYSTERESIS__SHIFT                                                     0x8
+#define BIFC_SDP_CNTL_0__GMI_DNS_SDP_DISCON_HYSTERESIS__SHIFT                                                 0x10
+#define BIFC_SDP_CNTL_0__GMI_UPS_SDP_DISCON_HYSTERESIS__SHIFT                                                 0x18
+#define BIFC_SDP_CNTL_0__HRP_SDP_DISCON_HYSTERESIS_MASK                                                       0x000000FFL
+#define BIFC_SDP_CNTL_0__GSI_SDP_DISCON_HYSTERESIS_MASK                                                       0x0000FF00L
+#define BIFC_SDP_CNTL_0__GMI_DNS_SDP_DISCON_HYSTERESIS_MASK                                                   0x00FF0000L
+#define BIFC_SDP_CNTL_0__GMI_UPS_SDP_DISCON_HYSTERESIS_MASK                                                   0xFF000000L
+//BIFC_SDP_CNTL_1
+#define BIFC_SDP_CNTL_1__HRP_SDP_DISCON_DIS__SHIFT                                                            0x0
+#define BIFC_SDP_CNTL_1__GSI_SDP_DISCON_DIS__SHIFT                                                            0x1
+#define BIFC_SDP_CNTL_1__GMI_DNS_SDP_DISCON_DIS__SHIFT                                                        0x2
+#define BIFC_SDP_CNTL_1__GMI_UPS_SDP_DISCON_DIS__SHIFT                                                        0x3
+#define BIFC_SDP_CNTL_1__HRP_SDP_DISCON_VLINK_NONL0_ONLY__SHIFT                                               0x4
+#define BIFC_SDP_CNTL_1__NP_KEEP_GOING_STALL_P__SHIFT                                                         0x5
+#define BIFC_SDP_CNTL_1__GMI_UPS_SDP_DISCON_VLINK_NONL0_ONLY__SHIFT                                           0x7
+#define BIFC_SDP_CNTL_1__ATOMIC_STALL_BY_RDWR_EN__SHIFT                                                       0x8
+#define BIFC_SDP_CNTL_1__POOL_CREDIT_ALLOC_OVERRIDE_DYNAMIC__SHIFT                                            0x9
+#define BIFC_SDP_CNTL_1__HRP_SDP_DISCON_DIS_MASK                                                              0x00000001L
+#define BIFC_SDP_CNTL_1__GSI_SDP_DISCON_DIS_MASK                                                              0x00000002L
+#define BIFC_SDP_CNTL_1__GMI_DNS_SDP_DISCON_DIS_MASK                                                          0x00000004L
+#define BIFC_SDP_CNTL_1__GMI_UPS_SDP_DISCON_DIS_MASK                                                          0x00000008L
+#define BIFC_SDP_CNTL_1__HRP_SDP_DISCON_VLINK_NONL0_ONLY_MASK                                                 0x00000010L
+#define BIFC_SDP_CNTL_1__NP_KEEP_GOING_STALL_P_MASK                                                           0x00000020L
+#define BIFC_SDP_CNTL_1__GMI_UPS_SDP_DISCON_VLINK_NONL0_ONLY_MASK                                             0x00000080L
+#define BIFC_SDP_CNTL_1__ATOMIC_STALL_BY_RDWR_EN_MASK                                                         0x00000100L
+#define BIFC_SDP_CNTL_1__POOL_CREDIT_ALLOC_OVERRIDE_DYNAMIC_MASK                                              0x00000200L
+//BIFC_PASID_STS
+#define BIFC_PASID_STS__PASID_STS__SHIFT                                                                      0x0
+#define BIFC_PASID_STS__PASID_STS_MASK                                                                        0x0000000FL
+//BIFC_ATHUB_ACT_CNTL
+#define BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_RSP_STS_TYPE__SHIFT                                                0x0
+#define BIFC_ATHUB_ACT_CNTL__ATHUB_SLFR_DATAERR_RSP_STS_TYPE__SHIFT                                           0x3
+#define BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_REQ_DROP_DIS__SHIFT                                                0x8
+#define BIFC_ATHUB_ACT_CNTL__GSI_ATHUB_ACT_FLUSH_TRIGGER__SHIFT                                               0x9
+#define BIFC_ATHUB_ACT_CNTL__GMI_ATHUB_ACT_FLUSH_TRIGGER__SHIFT                                               0xa
+#define BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_SST_PP_REQ_DROP_EN__SHIFT                                          0xb
+#define BIFC_ATHUB_ACT_CNTL__ERREVENT_MODE1RST_FLUSH_LOG_AER_EN__SHIFT                                        0xc
+#define BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_RSP_STS_TYPE_MASK                                                  0x00000007L
+#define BIFC_ATHUB_ACT_CNTL__ATHUB_SLFR_DATAERR_RSP_STS_TYPE_MASK                                             0x00000038L
+#define BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_REQ_DROP_DIS_MASK                                                  0x00000100L
+#define BIFC_ATHUB_ACT_CNTL__GSI_ATHUB_ACT_FLUSH_TRIGGER_MASK                                                 0x00000200L
+#define BIFC_ATHUB_ACT_CNTL__GMI_ATHUB_ACT_FLUSH_TRIGGER_MASK                                                 0x00000400L
+#define BIFC_ATHUB_ACT_CNTL__ATHUB_ACT_GSI_SST_PP_REQ_DROP_EN_MASK                                            0x00000800L
+#define BIFC_ATHUB_ACT_CNTL__ERREVENT_MODE1RST_FLUSH_LOG_AER_EN_MASK                                          0x00001000L
+//BIFC_PERF_CNTL_0
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_EN__SHIFT                                                          0x0
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_EN__SHIFT                                                          0x1
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_RESET__SHIFT                                                       0x8
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_RESET__SHIFT                                                       0x9
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_SEL__SHIFT                                                         0x10
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_SEL__SHIFT                                                         0x18
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_EN_MASK                                                            0x00000001L
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_EN_MASK                                                            0x00000002L
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_RESET_MASK                                                         0x00000100L
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_RESET_MASK                                                         0x00000200L
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_RD_SEL_MASK                                                           0x007F0000L
+#define BIFC_PERF_CNTL_0__PERF_CNT_MMIO_WR_SEL_MASK                                                           0x7F000000L
+//BIF_MISC_BIFC_PERF_CNTL_1
+#define BIF_MISC_BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_EN__SHIFT                                                  0x0
+#define BIF_MISC_BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_EN__SHIFT                                                  0x1
+#define BIF_MISC_BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_RESET__SHIFT                                               0x4
+#define BIF_MISC_BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_RESET__SHIFT                                               0x5
+#define BIF_MISC_BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_SEL__SHIFT                                                 0x8
+#define BIF_MISC_BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_SEL__SHIFT                                                 0x10
+#define BIF_MISC_BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_EN_MASK                                                    0x00000001L
+#define BIF_MISC_BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_EN_MASK                                                    0x00000002L
+#define BIF_MISC_BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_RESET_MASK                                                 0x00000010L
+#define BIF_MISC_BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_RESET_MASK                                                 0x00000020L
+#define BIF_MISC_BIFC_PERF_CNTL_1__PERF_CNT_DMA_RD_SEL_MASK                                                   0x0000FF00L
+#define BIF_MISC_BIFC_PERF_CNTL_1__PERF_CNT_DMA_WR_SEL_MASK                                                   0x03FF0000L
+//BIFC_PERF_CNT_MMIO_RD_L32BIT
+#define BIFC_PERF_CNT_MMIO_RD_L32BIT__PERF_CNT_MMIO_RD_VALUE_L32BIT__SHIFT                                    0x0
+#define BIFC_PERF_CNT_MMIO_RD_L32BIT__PERF_CNT_MMIO_RD_VALUE_L32BIT_MASK                                      0xFFFFFFFFL
+//BIFC_PERF_CNT_MMIO_WR_L32BIT
+#define BIFC_PERF_CNT_MMIO_WR_L32BIT__PERF_CNT_MMIO_WR_VALUE_L32BIT__SHIFT                                    0x0
+#define BIFC_PERF_CNT_MMIO_WR_L32BIT__PERF_CNT_MMIO_WR_VALUE_L32BIT_MASK                                      0xFFFFFFFFL
+//BIF_MISC_BIFC_PERF_CNT_DMA_RD_L32BIT
+#define BIF_MISC_BIFC_PERF_CNT_DMA_RD_L32BIT__PERF_CNT_DMA_RD_VALUE_L32BIT__SHIFT                             0x0
+#define BIF_MISC_BIFC_PERF_CNT_DMA_RD_L32BIT__PERF_CNT_DMA_RD_VALUE_L32BIT_MASK                               0xFFFFFFFFL
+//BIF_MISC_BIFC_PERF_CNT_DMA_WR_L32BIT
+#define BIF_MISC_BIFC_PERF_CNT_DMA_WR_L32BIT__PERF_CNT_DMA_WR_VALUE_L32BIT__SHIFT                             0x0
+#define BIF_MISC_BIFC_PERF_CNT_DMA_WR_L32BIT__PERF_CNT_DMA_WR_VALUE_L32BIT_MASK                               0xFFFFFFFFL
+//NBIF_REGIF_ERRSET_CTRL
+#define NBIF_REGIF_ERRSET_CTRL__DROP_NONPF_MMREGREQ_SETERR_DIS__SHIFT                                         0x0
+#define NBIF_REGIF_ERRSET_CTRL__DROP_NONPF_MMREGREQ_SETERR_DIS_MASK                                           0x00000001L
+//BIFC_SDP_CNTL_2
+#define BIFC_SDP_CNTL_2__SDP_SION_DISCON_HYSTERESIS__SHIFT                                                    0x0
+#define BIFC_SDP_CNTL_2__SDP_SION_DISCON_HYSTERESIS_H__SHIFT                                                  0x8
+#define BIFC_SDP_CNTL_2__HRP_SDP_DISCON_HYSTERESIS_H__SHIFT                                                   0x10
+#define BIFC_SDP_CNTL_2__GSI_SDP_DISCON_HYSTERESIS_H__SHIFT                                                   0x18
+#define BIFC_SDP_CNTL_2__SDP_SION_DISCON_HYSTERESIS_MASK                                                      0x000000FFL
+#define BIFC_SDP_CNTL_2__SDP_SION_DISCON_HYSTERESIS_H_MASK                                                    0x00000F00L
+#define BIFC_SDP_CNTL_2__HRP_SDP_DISCON_HYSTERESIS_H_MASK                                                     0x000F0000L
+#define BIFC_SDP_CNTL_2__GSI_SDP_DISCON_HYSTERESIS_H_MASK                                                     0x0F000000L
+//NBIF_PGMST_CTRL
+#define NBIF_PGMST_CTRL__NBIF_CFG_PG_HYSTERESIS__SHIFT                                                        0x0
+#define NBIF_PGMST_CTRL__NBIF_CFG_PG_EN__SHIFT                                                                0x8
+#define NBIF_PGMST_CTRL__NBIF_CFG_IDLENESS_COUNT_EN__SHIFT                                                    0xa
+#define NBIF_PGMST_CTRL__NBIF_CFG_FW_PG_EXIT_EN__SHIFT                                                        0xe
+#define NBIF_PGMST_CTRL__NBIF_CFG_PG_HYSTERESIS_MASK                                                          0x000000FFL
+#define NBIF_PGMST_CTRL__NBIF_CFG_PG_EN_MASK                                                                  0x00000100L
+#define NBIF_PGMST_CTRL__NBIF_CFG_IDLENESS_COUNT_EN_MASK                                                      0x00003C00L
+#define NBIF_PGMST_CTRL__NBIF_CFG_FW_PG_EXIT_EN_MASK                                                          0x0000C000L
+//NBIF_PGSLV_CTRL
+#define NBIF_PGSLV_CTRL__NBIF_CFG_IDLE_HYSTERESIS__SHIFT                                                      0x0
+#define NBIF_PGSLV_CTRL__NBIF_CFG_IDLE_HYSTERESIS_MASK                                                        0x0000001FL
+//NBIF_PG_MISC_CTRL
+#define NBIF_PG_MISC_CTRL__NBIF_CFG_SHUBCLK_0_IDLE_HYSTERESIS__SHIFT                                          0x0
+#define NBIF_PG_MISC_CTRL__NBIF_CFG_SHUBCLK_1_IDLE_HYSTERESIS__SHIFT                                          0x5
+#define NBIF_PG_MISC_CTRL__NBIF_PG_ENDP_D3_ONLY__SHIFT                                                        0xa
+#define NBIF_PG_MISC_CTRL__NBIF_PG_CLK_PERM1__SHIFT                                                           0xd
+#define NBIF_PG_MISC_CTRL__NBIF_PG_DS_ALLOW_DIS__SHIFT                                                        0xe
+#define NBIF_PG_MISC_CTRL__NBIF_PG_CLK_PERM2__SHIFT                                                           0x10
+#define NBIF_PG_MISC_CTRL__NBIF_CFG_REFCLK_CYCLE_FOR_200NS__SHIFT                                             0x18
+#define NBIF_PG_MISC_CTRL__NBIF_PG_PCIE_NBIF_LD_MASK__SHIFT                                                   0x1e
+#define NBIF_PG_MISC_CTRL__NBIF_CFG_PG_EXIT_OVERRIDE__SHIFT                                                   0x1f
+#define NBIF_PG_MISC_CTRL__NBIF_CFG_SHUBCLK_0_IDLE_HYSTERESIS_MASK                                            0x0000001FL
+#define NBIF_PG_MISC_CTRL__NBIF_CFG_SHUBCLK_1_IDLE_HYSTERESIS_MASK                                            0x000003E0L
+#define NBIF_PG_MISC_CTRL__NBIF_PG_ENDP_D3_ONLY_MASK                                                          0x00000400L
+#define NBIF_PG_MISC_CTRL__NBIF_PG_CLK_PERM1_MASK                                                             0x00002000L
+#define NBIF_PG_MISC_CTRL__NBIF_PG_DS_ALLOW_DIS_MASK                                                          0x00004000L
+#define NBIF_PG_MISC_CTRL__NBIF_PG_CLK_PERM2_MASK                                                             0x00010000L
+#define NBIF_PG_MISC_CTRL__NBIF_CFG_REFCLK_CYCLE_FOR_200NS_MASK                                               0x3F000000L
+#define NBIF_PG_MISC_CTRL__NBIF_PG_PCIE_NBIF_LD_MASK_MASK                                                     0x40000000L
+#define NBIF_PG_MISC_CTRL__NBIF_CFG_PG_EXIT_OVERRIDE_MASK                                                     0x80000000L
+//SMN_MST_EP_CNTL3
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF0__SHIFT                                                0x0
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF1__SHIFT                                                0x1
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF2__SHIFT                                                0x2
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF3__SHIFT                                                0x3
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF4__SHIFT                                                0x4
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF5__SHIFT                                                0x5
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF6__SHIFT                                                0x6
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF7__SHIFT                                                0x7
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF0_MASK                                                  0x00000001L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF1_MASK                                                  0x00000002L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF2_MASK                                                  0x00000004L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF3_MASK                                                  0x00000008L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF4_MASK                                                  0x00000010L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF5_MASK                                                  0x00000020L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF6_MASK                                                  0x00000040L
+#define SMN_MST_EP_CNTL3__SMN_ZERO_BE_WR_EN_EP_DEV0_PF7_MASK                                                  0x00000080L
+//SMN_MST_EP_CNTL4
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF0__SHIFT                                                0x0
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF1__SHIFT                                                0x1
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF2__SHIFT                                                0x2
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF3__SHIFT                                                0x3
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF4__SHIFT                                                0x4
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF5__SHIFT                                                0x5
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF6__SHIFT                                                0x6
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF7__SHIFT                                                0x7
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF0_MASK                                                  0x00000001L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF1_MASK                                                  0x00000002L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF2_MASK                                                  0x00000004L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF3_MASK                                                  0x00000008L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF4_MASK                                                  0x00000010L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF5_MASK                                                  0x00000020L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF6_MASK                                                  0x00000040L
+#define SMN_MST_EP_CNTL4__SMN_ZERO_BE_RD_EN_EP_DEV0_PF7_MASK                                                  0x00000080L
+//SMN_MST_CNTL1
+#define SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_UPS__SHIFT                                                    0x0
+#define SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_DNS_DEV0__SHIFT                                               0x10
+#define SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_UPS_MASK                                                      0x00000001L
+#define SMN_MST_CNTL1__SMN_ERRRSP_DATA_ALLF_DIS_DNS_DEV0_MASK                                                 0x00010000L
+//SMN_MST_EP_CNTL5
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF0__SHIFT                                         0x0
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF1__SHIFT                                         0x1
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF2__SHIFT                                         0x2
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF3__SHIFT                                         0x3
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF4__SHIFT                                         0x4
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF5__SHIFT                                         0x5
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF6__SHIFT                                         0x6
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF7__SHIFT                                         0x7
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF0_MASK                                           0x00000001L
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF1_MASK                                           0x00000002L
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF2_MASK                                           0x00000004L
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF3_MASK                                           0x00000008L
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF4_MASK                                           0x00000010L
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF5_MASK                                           0x00000020L
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF6_MASK                                           0x00000040L
+#define SMN_MST_EP_CNTL5__SMN_ERRRSP_DATA_ALLF_DIS_EP_DEV0_PF7_MASK                                           0x00000080L
+//BIF_SELFRING_BUFFER_VID
+#define BIF_SELFRING_BUFFER_VID__DOORBELL_MONITOR_CID__SHIFT                                                  0x0
+#define BIF_SELFRING_BUFFER_VID__RAS_CNTLR_INTR_CID__SHIFT                                                    0x8
+#define BIF_SELFRING_BUFFER_VID__RAS_ATHUB_ERR_EVENT_INTR_CID__SHIFT                                          0x10
+#define BIF_SELFRING_BUFFER_VID__DOORBELL_MONITOR_CID_MASK                                                    0x000000FFL
+#define BIF_SELFRING_BUFFER_VID__RAS_CNTLR_INTR_CID_MASK                                                      0x0000FF00L
+#define BIF_SELFRING_BUFFER_VID__RAS_ATHUB_ERR_EVENT_INTR_CID_MASK                                            0x00FF0000L
+//BIF_SELFRING_VECTOR_CNTL
+#define BIF_SELFRING_VECTOR_CNTL__MISC_DB_MNTR_INTR_DIS__SHIFT                                                0x0
+#define BIF_SELFRING_VECTOR_CNTL__DB_MNTR_TS_FROM__SHIFT                                                      0x1
+#define BIF_SELFRING_VECTOR_CNTL__MISC_DB_MNTR_INTR_DIS_MASK                                                  0x00000001L
+#define BIF_SELFRING_VECTOR_CNTL__DB_MNTR_TS_FROM_MASK                                                        0x00000002L
+//HDP_ERR_STATUS_EXT
+#define HDP_ERR_STATUS_EXT__HDP_ERR_STATUS_WR_EXT__SHIFT                                                      0x0
+#define HDP_ERR_STATUS_EXT__HDP_ERR_STATUS_RD_EXT__SHIFT                                                      0x1
+#define HDP_ERR_STATUS_EXT__HDP_ERR_STATUS_WR_EXT_MASK                                                        0x00000001L
+#define HDP_ERR_STATUS_EXT__HDP_ERR_STATUS_RD_EXT_MASK                                                        0x00000002L
+//NBIF_STRAP_WRITE_CTRL
+#define NBIF_STRAP_WRITE_CTRL__NBIF_STRAP_WRITE_ONCE_ENABLE__SHIFT                                            0x0
+#define NBIF_STRAP_WRITE_CTRL__NBIF_STRAP_WRITE_ONCE_ENABLE_MASK                                              0x00000001L
+//NBIF_INTX_DSTATE_MISC_CNTL
+#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_EP__SHIFT                                      0x0
+#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_DN__SHIFT                                      0x1
+#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_SWUS__SHIFT                                    0x2
+#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_IN_NOND0_EN_EP__SHIFT                                         0x3
+#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_IN_NOND0_EN_DN__SHIFT                                         0x4
+#define NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_EP__SHIFT                                                     0x5
+#define NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_DN__SHIFT                                                     0x6
+#define NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_SWUS__SHIFT                                                   0x7
+#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_EP_MASK                                        0x00000001L
+#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_DN_MASK                                        0x00000002L
+#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_DSTATE_CHK_DIS_SWUS_MASK                                      0x00000004L
+#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_IN_NOND0_EN_EP_MASK                                           0x00000008L
+#define NBIF_INTX_DSTATE_MISC_CNTL__DEASRT_INTX_IN_NOND0_EN_DN_MASK                                           0x00000010L
+#define NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_EP_MASK                                                       0x00000020L
+#define NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_DN_MASK                                                       0x00000040L
+#define NBIF_INTX_DSTATE_MISC_CNTL__PMI_INT_DIS_SWUS_MASK                                                     0x00000080L
+//NBIF_PENDING_MISC_CNTL
+#define NBIF_PENDING_MISC_CNTL__FLR_MST_PEND_CHK_DIS__SHIFT                                                   0x0
+#define NBIF_PENDING_MISC_CNTL__FLR_SLV_PEND_CHK_DIS__SHIFT                                                   0x1
+#define NBIF_PENDING_MISC_CNTL__FLR_MST_PEND_CHK_DIS_MASK                                                     0x00000001L
+#define NBIF_PENDING_MISC_CNTL__FLR_SLV_PEND_CHK_DIS_MASK                                                     0x00000002L
+//BIF_GMI_WRR_WEIGHT
+#define BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_LRG_COUNTER_MODE__SHIFT                                               0x1d
+#define BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_LRG_MODE__SHIFT                                                       0x1e
+#define BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_LRG_SIZE_MODE__SHIFT                                                  0x1f
+#define BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_LRG_COUNTER_MODE_MASK                                                 0x20000000L
+#define BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_LRG_MODE_MASK                                                         0x40000000L
+#define BIF_GMI_WRR_WEIGHT__GMI_REQ_WRR_LRG_SIZE_MODE_MASK                                                    0x80000000L
+//BIF_GMI_WRR_WEIGHT2
+#define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY0_WEIGHT__SHIFT                                                     0x0
+#define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY1_WEIGHT__SHIFT                                                     0x8
+#define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY2_WEIGHT__SHIFT                                                     0x10
+#define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY3_WEIGHT__SHIFT                                                     0x18
+#define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY0_WEIGHT_MASK                                                       0x000000FFL
+#define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY1_WEIGHT_MASK                                                       0x0000FF00L
+#define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY2_WEIGHT_MASK                                                       0x00FF0000L
+#define BIF_GMI_WRR_WEIGHT2__GMI_REQ_ENTRY3_WEIGHT_MASK                                                       0xFF000000L
+//BIF_GMI_WRR_WEIGHT3
+#define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY4_WEIGHT__SHIFT                                                     0x0
+#define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY5_WEIGHT__SHIFT                                                     0x8
+#define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY6_WEIGHT__SHIFT                                                     0x10
+#define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY7_WEIGHT__SHIFT                                                     0x18
+#define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY4_WEIGHT_MASK                                                       0x000000FFL
+#define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY5_WEIGHT_MASK                                                       0x0000FF00L
+#define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY6_WEIGHT_MASK                                                       0x00FF0000L
+#define BIF_GMI_WRR_WEIGHT3__GMI_REQ_ENTRY7_WEIGHT_MASK                                                       0xFF000000L
+//BIF_GMI_WRR_WEIGHT4
+#define BIF_GMI_WRR_WEIGHT4__GMI_REQ_ENTRY8_WEIGHT__SHIFT                                                     0x0
+#define BIF_GMI_WRR_WEIGHT4__GMI_REQ_ENTRY8_WEIGHT_MASK                                                       0x000000FFL
+//NBIF_PWRBRK_REQUEST
+#define NBIF_PWRBRK_REQUEST__NBIF_PWRBRK_REQUEST__SHIFT                                                       0x0
+#define NBIF_PWRBRK_REQUEST__NBIF_PWRBRK_REQUEST_MASK                                                         0x00000001L
+//BIF_ATOMIC_ERR_LOG_DEV0_F0
+#define BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_OPCODE_DEV0_F0__SHIFT                                           0x0
+#define BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_REQEN_LOW_DEV0_F0__SHIFT                                        0x1
+#define BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_LENGTH_DEV0_F0__SHIFT                                           0x2
+#define BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_NR_DEV0_F0__SHIFT                                               0x3
+#define BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_OPCODE_DEV0_F0__SHIFT                                     0x10
+#define BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F0__SHIFT                                  0x11
+#define BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_LENGTH_DEV0_F0__SHIFT                                     0x12
+#define BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_NR_DEV0_F0__SHIFT                                         0x13
+#define BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_OPCODE_DEV0_F0_MASK                                             0x00000001L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_REQEN_LOW_DEV0_F0_MASK                                          0x00000002L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_LENGTH_DEV0_F0_MASK                                             0x00000004L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F0__UR_ATOMIC_NR_DEV0_F0_MASK                                                 0x00000008L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_OPCODE_DEV0_F0_MASK                                       0x00010000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F0_MASK                                    0x00020000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_LENGTH_DEV0_F0_MASK                                       0x00040000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_NR_DEV0_F0_MASK                                           0x00080000L
+//BIF_ATOMIC_ERR_LOG_DEV0_F1
+#define BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_OPCODE_DEV0_F1__SHIFT                                           0x0
+#define BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_REQEN_LOW_DEV0_F1__SHIFT                                        0x1
+#define BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_LENGTH_DEV0_F1__SHIFT                                           0x2
+#define BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_NR_DEV0_F1__SHIFT                                               0x3
+#define BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_OPCODE_DEV0_F1__SHIFT                                     0x10
+#define BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F1__SHIFT                                  0x11
+#define BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_LENGTH_DEV0_F1__SHIFT                                     0x12
+#define BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_NR_DEV0_F1__SHIFT                                         0x13
+#define BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_OPCODE_DEV0_F1_MASK                                             0x00000001L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_REQEN_LOW_DEV0_F1_MASK                                          0x00000002L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_LENGTH_DEV0_F1_MASK                                             0x00000004L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F1__UR_ATOMIC_NR_DEV0_F1_MASK                                                 0x00000008L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_OPCODE_DEV0_F1_MASK                                       0x00010000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F1_MASK                                    0x00020000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_LENGTH_DEV0_F1_MASK                                       0x00040000L
+#define BIF_ATOMIC_ERR_LOG_DEV0_F1__CLEAR_UR_ATOMIC_NR_DEV0_F1_MASK                                           0x00080000L
+//BIF_DMA_MP4_ERR_LOG
+#define BIF_DMA_MP4_ERR_LOG__MP4SDP_VC4_NON_DVM_ERR__SHIFT                                                    0x0
+#define BIF_DMA_MP4_ERR_LOG__MP4SDP_ATOMIC_REQEN_LOW_ERR__SHIFT                                               0x1
+#define BIF_DMA_MP4_ERR_LOG__CLEAR_MP4SDP_VC4_NON_DVM_ERR__SHIFT                                              0x10
+#define BIF_DMA_MP4_ERR_LOG__CLEAR_MP4SDP_ATOMIC_REQEN_LOW_ERR__SHIFT                                         0x11
+#define BIF_DMA_MP4_ERR_LOG__MP4SDP_VC4_NON_DVM_ERR_MASK                                                      0x00000001L
+#define BIF_DMA_MP4_ERR_LOG__MP4SDP_ATOMIC_REQEN_LOW_ERR_MASK                                                 0x00000002L
+#define BIF_DMA_MP4_ERR_LOG__CLEAR_MP4SDP_VC4_NON_DVM_ERR_MASK                                                0x00010000L
+#define BIF_DMA_MP4_ERR_LOG__CLEAR_MP4SDP_ATOMIC_REQEN_LOW_ERR_MASK                                           0x00020000L
+//BIF_PASID_ERR_LOG
+#define BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F0__SHIFT                                                           0x0
+#define BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F1__SHIFT                                                           0x1
+#define BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F0_MASK                                                             0x00000001L
+#define BIF_PASID_ERR_LOG__PASID_ERR_DEV0_F1_MASK                                                             0x00000002L
+//BIF_PASID_ERR_CLR
+#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F0__SHIFT                                                       0x0
+#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F1__SHIFT                                                       0x1
+#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F0_MASK                                                         0x00000001L
+#define BIF_PASID_ERR_CLR__PASID_ERR_CLR_DEV0_F1_MASK                                                         0x00000002L
+//NBIF_VWIRE_CTRL
+#define NBIF_VWIRE_CTRL__NBIF_SMN_VWR_DIS__SHIFT                                                              0x0
+#define NBIF_VWIRE_CTRL__SMN_VWR_RESET_DELAY_CNT__SHIFT                                                       0x4
+#define NBIF_VWIRE_CTRL__SMN_VWR_POSTED__SHIFT                                                                0x8
+#define NBIF_VWIRE_CTRL__NBIF_SDP_UPS_VWR_DIS__SHIFT                                                          0x10
+#define NBIF_VWIRE_CTRL__SDP_VWR_RESET_DELAY_CNT__SHIFT                                                       0x14
+#define NBIF_VWIRE_CTRL__SDP_VWR_BLOCKLVL__SHIFT                                                              0x1a
+#define NBIF_VWIRE_CTRL__NBIF_SMN_VWR_DIS_MASK                                                                0x00000001L
+#define NBIF_VWIRE_CTRL__SMN_VWR_RESET_DELAY_CNT_MASK                                                         0x000000F0L
+#define NBIF_VWIRE_CTRL__SMN_VWR_POSTED_MASK                                                                  0x00000100L
+#define NBIF_VWIRE_CTRL__NBIF_SDP_UPS_VWR_DIS_MASK                                                            0x00010000L
+#define NBIF_VWIRE_CTRL__SDP_VWR_RESET_DELAY_CNT_MASK                                                         0x00F00000L
+#define NBIF_VWIRE_CTRL__SDP_VWR_BLOCKLVL_MASK                                                                0x0C000000L
+//NBIF_MGCG_CTRL_LCLK
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_EN_LCLK__SHIFT                                                         0x0
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_MODE_LCLK__SHIFT                                                       0x1
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_HYSTERESIS_LCLK__SHIFT                                                 0x2
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_HST_DIS_LCLK__SHIFT                                                    0xa
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_DMA_DIS_LCLK__SHIFT                                                    0xb
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_REG_DIS_LCLK__SHIFT                                                    0xc
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_AER_DIS_LCLK__SHIFT                                                    0xd
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_DBG_DIS_LCLK__SHIFT                                                    0xe
+#define NBIF_MGCG_CTRL_LCLK__NBIF_SRAM_FGCG_EN_LCLK__SHIFT                                                    0xf
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_EN_LCLK_MASK                                                           0x00000001L
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_MODE_LCLK_MASK                                                         0x00000002L
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_HYSTERESIS_LCLK_MASK                                                   0x000003FCL
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_HST_DIS_LCLK_MASK                                                      0x00000400L
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_DMA_DIS_LCLK_MASK                                                      0x00000800L
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_REG_DIS_LCLK_MASK                                                      0x00001000L
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_AER_DIS_LCLK_MASK                                                      0x00002000L
+#define NBIF_MGCG_CTRL_LCLK__NBIF_MGCG_DBG_DIS_LCLK_MASK                                                      0x00004000L
+#define NBIF_MGCG_CTRL_LCLK__NBIF_SRAM_FGCG_EN_LCLK_MASK                                                      0x00008000L
+//NBIF_DS_CTRL_LCLK
+#define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_EN__SHIFT                                                             0x0
+#define NBIF_DS_CTRL_LCLK__ATHUB_LCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT                                           0x1
+#define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_TIMER__SHIFT                                                          0x10
+#define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_EN_MASK                                                               0x00000001L
+#define NBIF_DS_CTRL_LCLK__ATHUB_LCLK_DEEPSLEEP_ALLOW_ENABLE_MASK                                             0x00000002L
+#define NBIF_DS_CTRL_LCLK__NBIF_LCLK_DS_TIMER_MASK                                                            0xFFFF0000L
+//SMN_MST_CNTL0
+#define SMN_MST_CNTL0__SMN_ARB_MODE__SHIFT                                                                    0x0
+#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_UPS__SHIFT                                                           0x8
+#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_UPS__SHIFT                                                           0x9
+#define SMN_MST_CNTL0__SMN_POST_MASK_EN_UPS__SHIFT                                                            0xa
+#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_UPS__SHIFT                                                      0xb
+#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_DNS_DEV0__SHIFT                                                      0x10
+#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_DNS_DEV0__SHIFT                                                      0x14
+#define SMN_MST_CNTL0__SMN_POST_MASK_EN_DNS_DEV0__SHIFT                                                       0x18
+#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_DNS_DEV0__SHIFT                                                 0x1c
+#define SMN_MST_CNTL0__SMN_ARB_MODE_MASK                                                                      0x00000003L
+#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_UPS_MASK                                                             0x00000100L
+#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_UPS_MASK                                                             0x00000200L
+#define SMN_MST_CNTL0__SMN_POST_MASK_EN_UPS_MASK                                                              0x00000400L
+#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_UPS_MASK                                                        0x00000800L
+#define SMN_MST_CNTL0__SMN_ZERO_BE_WR_EN_DNS_DEV0_MASK                                                        0x00010000L
+#define SMN_MST_CNTL0__SMN_ZERO_BE_RD_EN_DNS_DEV0_MASK                                                        0x00100000L
+#define SMN_MST_CNTL0__SMN_POST_MASK_EN_DNS_DEV0_MASK                                                         0x01000000L
+#define SMN_MST_CNTL0__MULTI_SMN_TRANS_ID_DIS_DNS_DEV0_MASK                                                   0x10000000L
+//SMN_MST_EP_CNTL1
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF0__SHIFT                                                 0x0
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF1__SHIFT                                                 0x1
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF2__SHIFT                                                 0x2
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF3__SHIFT                                                 0x3
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF4__SHIFT                                                 0x4
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF5__SHIFT                                                 0x5
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF6__SHIFT                                                 0x6
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF7__SHIFT                                                 0x7
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF0_MASK                                                   0x00000001L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF1_MASK                                                   0x00000002L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF2_MASK                                                   0x00000004L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF3_MASK                                                   0x00000008L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF4_MASK                                                   0x00000010L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF5_MASK                                                   0x00000020L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF6_MASK                                                   0x00000040L
+#define SMN_MST_EP_CNTL1__SMN_POST_MASK_EN_EP_DEV0_PF7_MASK                                                   0x00000080L
+//SMN_MST_EP_CNTL2
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF0__SHIFT                                           0x0
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF1__SHIFT                                           0x1
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF2__SHIFT                                           0x2
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF3__SHIFT                                           0x3
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF4__SHIFT                                           0x4
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF5__SHIFT                                           0x5
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF6__SHIFT                                           0x6
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF7__SHIFT                                           0x7
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF0_MASK                                             0x00000001L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF1_MASK                                             0x00000002L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF2_MASK                                             0x00000004L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF3_MASK                                             0x00000008L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF4_MASK                                             0x00000010L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF5_MASK                                             0x00000020L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF6_MASK                                             0x00000040L
+#define SMN_MST_EP_CNTL2__MULTI_SMN_TRANS_ID_DIS_EP_DEV0_PF7_MASK                                             0x00000080L
+//NBIF_SDP_VWR_VCHG_DIS_CTRL
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F0_DIS__SHIFT                                           0x0
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F1_DIS__SHIFT                                           0x1
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F2_DIS__SHIFT                                           0x2
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F3_DIS__SHIFT                                           0x3
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F4_DIS__SHIFT                                           0x4
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F5_DIS__SHIFT                                           0x5
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F6_DIS__SHIFT                                           0x6
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F7_DIS__SHIFT                                           0x7
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_SWDS_P0_DIS__SHIFT                                           0x18
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F0_DIS_MASK                                             0x00000001L
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F1_DIS_MASK                                             0x00000002L
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F2_DIS_MASK                                             0x00000004L
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F3_DIS_MASK                                             0x00000008L
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F4_DIS_MASK                                             0x00000010L
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F5_DIS_MASK                                             0x00000020L
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F6_DIS_MASK                                             0x00000040L
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_ENDP_F7_DIS_MASK                                             0x00000080L
+#define NBIF_SDP_VWR_VCHG_DIS_CTRL__SDP_VWR_VCHG_SWDS_P0_DIS_MASK                                             0x01000000L
+//NBIF_SDP_VWR_VCHG_RST_CTRL0
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_EN__SHIFT                                  0x0
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_EN__SHIFT                                  0x1
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_EN__SHIFT                                  0x2
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_EN__SHIFT                                  0x3
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_EN__SHIFT                                  0x4
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_EN__SHIFT                                  0x5
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_EN__SHIFT                                  0x6
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_EN__SHIFT                                  0x7
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_EN__SHIFT                                  0x18
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_EN_MASK                                    0x00000001L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_EN_MASK                                    0x00000002L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_EN_MASK                                    0x00000004L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_EN_MASK                                    0x00000008L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_EN_MASK                                    0x00000010L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_EN_MASK                                    0x00000020L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_EN_MASK                                    0x00000040L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_EN_MASK                                    0x00000080L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL0__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_EN_MASK                                    0x01000000L
+//NBIF_SDP_VWR_VCHG_RST_CTRL1
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_VAL__SHIFT                                 0x0
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_VAL__SHIFT                                 0x1
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_VAL__SHIFT                                 0x2
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_VAL__SHIFT                                 0x3
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_VAL__SHIFT                                 0x4
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_VAL__SHIFT                                 0x5
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_VAL__SHIFT                                 0x6
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_VAL__SHIFT                                 0x7
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_VAL__SHIFT                                 0x18
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F0_RST_OVRD_VAL_MASK                                   0x00000001L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F1_RST_OVRD_VAL_MASK                                   0x00000002L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F2_RST_OVRD_VAL_MASK                                   0x00000004L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F3_RST_OVRD_VAL_MASK                                   0x00000008L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F4_RST_OVRD_VAL_MASK                                   0x00000010L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F5_RST_OVRD_VAL_MASK                                   0x00000020L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F6_RST_OVRD_VAL_MASK                                   0x00000040L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_ENDP_F7_RST_OVRD_VAL_MASK                                   0x00000080L
+#define NBIF_SDP_VWR_VCHG_RST_CTRL1__SDP_VWR_VCHG_SWDS_P0_RST_OVRD_VAL_MASK                                   0x01000000L
+//NBIF_SDP_VWR_VCHG_TRIG
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F0_TRIG__SHIFT                                              0x0
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F1_TRIG__SHIFT                                              0x1
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F2_TRIG__SHIFT                                              0x2
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F3_TRIG__SHIFT                                              0x3
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F4_TRIG__SHIFT                                              0x4
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F5_TRIG__SHIFT                                              0x5
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F6_TRIG__SHIFT                                              0x6
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F7_TRIG__SHIFT                                              0x7
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_SWDS_P0_TRIG__SHIFT                                              0x18
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F0_TRIG_MASK                                                0x00000001L
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F1_TRIG_MASK                                                0x00000002L
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F2_TRIG_MASK                                                0x00000004L
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F3_TRIG_MASK                                                0x00000008L
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F4_TRIG_MASK                                                0x00000010L
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F5_TRIG_MASK                                                0x00000020L
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F6_TRIG_MASK                                                0x00000040L
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_ENDP_F7_TRIG_MASK                                                0x00000080L
+#define NBIF_SDP_VWR_VCHG_TRIG__SDP_VWR_VCHG_SWDS_P0_TRIG_MASK                                                0x01000000L
+//NBIO_LCLK_DEEPSLEEP_MASK
+#define NBIO_LCLK_DEEPSLEEP_MASK__LCLK_DS_MASK__SHIFT                                                         0x0
+#define NBIO_LCLK_DEEPSLEEP_MASK__LCLK_DS_MASK_MASK                                                           0xFFFFFFFFL
+//NBIF_DS_CTRL_USBCLK
+#define NBIF_DS_CTRL_USBCLK__NBIF_USBCLK_DS_EN__SHIFT                                                         0x0
+#define NBIF_DS_CTRL_USBCLK__USB_USBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT                                         0x1
+#define NBIF_DS_CTRL_USBCLK__NBIF_USBCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT                                        0x2
+#define NBIF_DS_CTRL_USBCLK__NBIF_USBCLK_DS_EN_MASK                                                           0x00000001L
+#define NBIF_DS_CTRL_USBCLK__USB_USBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK                                           0x00000002L
+#define NBIF_DS_CTRL_USBCLK__NBIF_USBCLK_DEEPSLEEP_ALLOW_ENABLE_MASK                                          0x00000004L
+//NBIF_SHUB_TODET_CLIENT_MISC3
+#define NBIF_SHUB_TODET_CLIENT_MISC3__NBIF_SHUB_TODET_SLVERR_EN3__SHIFT                                       0x0
+#define NBIF_SHUB_TODET_CLIENT_MISC3__NBIF_SHUB_TODET_SYNCFLOOD_EN3__SHIFT                                    0xa
+#define NBIF_SHUB_TODET_CLIENT_MISC3__NBIF_SHUB_TODET_SLVERR_EN3_MASK                                         0x000003FFL
+#define NBIF_SHUB_TODET_CLIENT_MISC3__NBIF_SHUB_TODET_SYNCFLOOD_EN3_MASK                                      0x000FFC00L
+//NBIF_SHUB_TODET_CTRL
+#define NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TODET_EN__SHIFT                                                       0x0
+#define NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TODET_AER_LOG_EN__SHIFT                                               0x1
+#define NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TODET_TIMER_UNIT__SHIFT                                               0x8
+#define NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TIMEOUT_COUNT__SHIFT                                                  0x10
+#define NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TODET_EN_MASK                                                         0x00000001L
+#define NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TODET_AER_LOG_EN_MASK                                                 0x00000002L
+#define NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TODET_TIMER_UNIT_MASK                                                 0x00000700L
+#define NBIF_SHUB_TODET_CTRL__NBIF_SHUB_TIMEOUT_COUNT_MASK                                                    0xFFFF0000L
+//NBIF_SHUB_TODET_CLIENT_CTRL
+#define NBIF_SHUB_TODET_CLIENT_CTRL__NBIF_SHUB_TODET_SLVERR_EN__SHIFT                                         0x0
+#define NBIF_SHUB_TODET_CLIENT_CTRL__NBIF_SHUB_TODET_SLVERR_EN_MASK                                           0xFFFFFFFFL
+//NBIF_SHUB_TODET_CLIENT_STATUS
+#define NBIF_SHUB_TODET_CLIENT_STATUS__NBIF_SHUB_TODET_CLIENT_STATUS__SHIFT                                   0x0
+#define NBIF_SHUB_TODET_CLIENT_STATUS__NBIF_SHUB_TODET_CLIENT_STATUS_MASK                                     0xFFFFFFFFL
+//NBIF_SHUB_TODET_SYNCFLOOD_CTRL
+#define NBIF_SHUB_TODET_SYNCFLOOD_CTRL__NBIF_SHUB_TODET_SYNCFLOOD_EN__SHIFT                                   0x0
+#define NBIF_SHUB_TODET_SYNCFLOOD_CTRL__NBIF_SHUB_TODET_SYNCFLOOD_EN_MASK                                     0xFFFFFFFFL
+//NBIF_SHUB_TODET_CLIENT_CTRL2
+#define NBIF_SHUB_TODET_CLIENT_CTRL2__NBIF_SHUB_TODET_SLVERR_EN2__SHIFT                                       0x0
+#define NBIF_SHUB_TODET_CLIENT_CTRL2__NBIF_SHUB_TODET_SLVERR_EN2_MASK                                         0xFFFFFFFFL
+//NBIF_SHUB_TODET_CLIENT_STATUS2
+#define NBIF_SHUB_TODET_CLIENT_STATUS2__NBIF_SHUB_TODET_CLIENT_STATUS2__SHIFT                                 0x0
+#define NBIF_SHUB_TODET_CLIENT_STATUS2__NBIF_SHUB_TODET_CLIENT_STATUS2_MASK                                   0xFFFFFFFFL
+//NBIF_SHUB_TODET_SYNCFLOOD_CTRL2
+#define NBIF_SHUB_TODET_SYNCFLOOD_CTRL2__NBIF_SHUB_TODET_SYNCFLOOD_EN2__SHIFT                                 0x0
+#define NBIF_SHUB_TODET_SYNCFLOOD_CTRL2__NBIF_SHUB_TODET_SYNCFLOOD_EN2_MASK                                   0xFFFFFFFFL
+//DMA_SDP_PORT_DEBUG
+#define DMA_SDP_PORT_DEBUG__DMA_SDP_PORT_REQ_CREDIT_RDY_FOR_VC__SHIFT                                         0x0
+#define DMA_SDP_PORT_DEBUG__DMA_SDP_PORT_DAT_CREDIT_RDY_FOR_VC__SHIFT                                         0x8
+#define DMA_SDP_PORT_DEBUG__DMA_SDP_PORT_RDRSP_CREDIT_VLD_FOR_VC__SHIFT                                       0x10
+#define DMA_SDP_PORT_DEBUG__DMA_SDP_PORT_WRRSP_CREDIT_VLD_FOR_VC__SHIFT                                       0x18
+#define DMA_SDP_PORT_DEBUG__DMA_SDP_PORT_REQ_CREDIT_RDY_FOR_VC_MASK                                           0x000000FFL
+#define DMA_SDP_PORT_DEBUG__DMA_SDP_PORT_DAT_CREDIT_RDY_FOR_VC_MASK                                           0x0000FF00L
+#define DMA_SDP_PORT_DEBUG__DMA_SDP_PORT_RDRSP_CREDIT_VLD_FOR_VC_MASK                                         0x00FF0000L
+#define DMA_SDP_PORT_DEBUG__DMA_SDP_PORT_WRRSP_CREDIT_VLD_FOR_VC_MASK                                         0xFF000000L
+//SDP_PORT_MONITOR_CONTROL
+#define SDP_PORT_MONITOR_CONTROL__DMA_SDP_PORT_MONITOR_EN__SHIFT                                              0x0
+#define SDP_PORT_MONITOR_CONTROL__HST_SDP_PORT_MONITOR_EN__SHIFT                                              0x1
+#define SDP_PORT_MONITOR_CONTROL__SDP_PORT_MONITOR_ADDRESS_EN__SHIFT                                          0x2
+#define SDP_PORT_MONITOR_CONTROL__SDP_PORT_MONITOR_UNITID_EN__SHIFT                                           0x3
+#define SDP_PORT_MONITOR_CONTROL__DMA_SDP_PORT_MONITOR_EN_MASK                                                0x00000001L
+#define SDP_PORT_MONITOR_CONTROL__HST_SDP_PORT_MONITOR_EN_MASK                                                0x00000002L
+#define SDP_PORT_MONITOR_CONTROL__SDP_PORT_MONITOR_ADDRESS_EN_MASK                                            0x00000004L
+#define SDP_PORT_MONITOR_CONTROL__SDP_PORT_MONITOR_UNITID_EN_MASK                                             0x00000008L
+//SDP_PORT_MONITOR_ADDRESS0
+#define SDP_PORT_MONITOR_ADDRESS0__SDP_PORT_MONITOR_ADDRESS0__SHIFT                                           0x0
+#define SDP_PORT_MONITOR_ADDRESS0__SDP_PORT_MONITOR_ADDRESS0_MASK                                             0xFFFFFFFFL
+//SDP_PORT_MONITOR_ADDRESS1
+#define SDP_PORT_MONITOR_ADDRESS1__SDP_PORT_MONITOR_ADDRESS1__SHIFT                                           0x0
+#define SDP_PORT_MONITOR_ADDRESS1__SDP_PORT_MONITOR_ADDRESS1_MASK                                             0xFFFFFFFFL
+//SDP_PORT_MONITOR_UNITID
+#define SDP_PORT_MONITOR_UNITID__SDP_PORT_MONITOR_UNITID__SHIFT                                               0x0
+#define SDP_PORT_MONITOR_UNITID__SDP_PORT_MONITOR_UNITID_MASK                                                 0x000007FFL
+//SDP_PORT_MONITOR_INFO0
+#define SDP_PORT_MONITOR_INFO0__SDP_PORT_MONITOR_INFO_ADDRESS0__SHIFT                                         0x0
+#define SDP_PORT_MONITOR_INFO0__SDP_PORT_MONITOR_INFO_ADDRESS0_MASK                                           0xFFFFFFFFL
+//SDP_PORT_MONITOR_INFO1
+#define SDP_PORT_MONITOR_INFO1__SDP_PORT_MONITOR_INFO_ADDRESS1__SHIFT                                         0x0
+#define SDP_PORT_MONITOR_INFO1__SDP_PORT_MONITOR_INFO_ADDRESS1_MASK                                           0xFFFFFFFFL
+//SDP_PORT_MONITOR_INFO2
+#define SDP_PORT_MONITOR_INFO2__SDP_PORT_MONITOR_INFO_BLOCKLEVEL__SHIFT                                       0x0
+#define SDP_PORT_MONITOR_INFO2__SDP_PORT_MONITOR_INFO_CHAIN__SHIFT                                            0x2
+#define SDP_PORT_MONITOR_INFO2__SDP_PORT_MONITOR_INFO_CMD__SHIFT                                              0x3
+#define SDP_PORT_MONITOR_INFO2__SDP_PORT_MONITOR_INFO_IO__SHIFT                                               0x9
+#define SDP_PORT_MONITOR_INFO2__SDP_PORT_MONITOR_INFO_PASSPW__SHIFT                                           0xa
+#define SDP_PORT_MONITOR_INFO2__SDP_PORT_MONITOR_INFO_RSPPASSPW__SHIFT                                        0xb
+#define SDP_PORT_MONITOR_INFO2__SDP_PORT_MONITOR_INFO_SECLEVEL__SHIFT                                         0xc
+#define SDP_PORT_MONITOR_INFO2__SDP_PORT_MONITOR_INFO_STREAMID__SHIFT                                         0x10
+#define SDP_PORT_MONITOR_INFO2__SDP_PORT_MONITOR_INFO_BLOCKLEVEL_MASK                                         0x00000003L
+#define SDP_PORT_MONITOR_INFO2__SDP_PORT_MONITOR_INFO_CHAIN_MASK                                              0x00000004L
+#define SDP_PORT_MONITOR_INFO2__SDP_PORT_MONITOR_INFO_CMD_MASK                                                0x000001F8L
+#define SDP_PORT_MONITOR_INFO2__SDP_PORT_MONITOR_INFO_IO_MASK                                                 0x00000200L
+#define SDP_PORT_MONITOR_INFO2__SDP_PORT_MONITOR_INFO_PASSPW_MASK                                             0x00000400L
+#define SDP_PORT_MONITOR_INFO2__SDP_PORT_MONITOR_INFO_RSPPASSPW_MASK                                          0x00000800L
+#define SDP_PORT_MONITOR_INFO2__SDP_PORT_MONITOR_INFO_SECLEVEL_MASK                                           0x0000F000L
+#define SDP_PORT_MONITOR_INFO2__SDP_PORT_MONITOR_INFO_STREAMID_MASK                                           0xFFFF0000L
+//SDP_PORT_MONITOR_INFO3
+#define SDP_PORT_MONITOR_INFO3__SDP_PORT_MONITOR_INFO_TAG__SHIFT                                              0x0
+#define SDP_PORT_MONITOR_INFO3__SDP_PORT_MONITOR_INFO_UNITID__SHIFT                                           0xc
+#define SDP_PORT_MONITOR_INFO3__SDP_PORT_MONITOR_INFO_VC__SHIFT                                               0x17
+#define SDP_PORT_MONITOR_INFO3__SDP_PORT_MONITOR_INFO_LEN__SHIFT                                              0x1a
+#define SDP_PORT_MONITOR_INFO3__SDP_PORT_MONITOR_INFO_TAG_MASK                                                0x00000FFFL
+#define SDP_PORT_MONITOR_INFO3__SDP_PORT_MONITOR_INFO_UNITID_MASK                                             0x007FF000L
+#define SDP_PORT_MONITOR_INFO3__SDP_PORT_MONITOR_INFO_VC_MASK                                                 0x03800000L
+#define SDP_PORT_MONITOR_INFO3__SDP_PORT_MONITOR_INFO_LEN_MASK                                                0xFC000000L
+//SDP_PORT_MONITOR_INFO4
+#define SDP_PORT_MONITOR_INFO4__SDP_PORT_MONITOR_INFO_ATTR__SHIFT                                             0x0
+#define SDP_PORT_MONITOR_INFO4__SDP_PORT_MONITOR_INFO_ATTR_MASK                                               0x000000FFL
+//BIFC_BME_ERR_LOG_HB
+//BIFC_GFX_INT_MONITOR_MASK
+#define BIFC_GFX_INT_MONITOR_MASK__GFX_INT_MONITOR_MSI_CTRL_MASK__SHIFT                                       0x0
+#define BIFC_GFX_INT_MONITOR_MASK__GFX_INT_MONITOR_MSI_ADDR_MASK__SHIFT                                       0x1
+#define BIFC_GFX_INT_MONITOR_MASK__GFX_INT_MONITOR_MSI_UPADDR_MASK__SHIFT                                     0x2
+#define BIFC_GFX_INT_MONITOR_MASK__GFX_INT_MONITOR_MSI_DATA_MASK__SHIFT                                       0x3
+#define BIFC_GFX_INT_MONITOR_MASK__GFX_INT_MONITOR_MSI_EDATA_MASK__SHIFT                                      0x4
+#define BIFC_GFX_INT_MONITOR_MASK__GFX_INT_MONITOR_MSIX_ADDR_MASK__SHIFT                                      0x5
+#define BIFC_GFX_INT_MONITOR_MASK__GFX_INT_MONITOR_MSIX_UPADDR_MASK__SHIFT                                    0x6
+#define BIFC_GFX_INT_MONITOR_MASK__GFX_INT_MONITOR_MSIX_DATA_MASK__SHIFT                                      0x7
+#define BIFC_GFX_INT_MONITOR_MASK__GFX_INT_MONITOR_VEC_MASK__SHIFT                                            0x8
+#define BIFC_GFX_INT_MONITOR_MASK__GFX_INT_MONITOR_PEND_MASK__SHIFT                                           0x9
+#define BIFC_GFX_INT_MONITOR_MASK__GFX_INT_MONITOR_MSIX_CTRL_MASK__SHIFT                                      0xa
+#define BIFC_GFX_INT_MONITOR_MASK__GFX_INT_MONITOR_MSI_CTRL_MASK_MASK                                         0x00000001L
+#define BIFC_GFX_INT_MONITOR_MASK__GFX_INT_MONITOR_MSI_ADDR_MASK_MASK                                         0x00000002L
+#define BIFC_GFX_INT_MONITOR_MASK__GFX_INT_MONITOR_MSI_UPADDR_MASK_MASK                                       0x00000004L
+#define BIFC_GFX_INT_MONITOR_MASK__GFX_INT_MONITOR_MSI_DATA_MASK_MASK                                         0x00000008L
+#define BIFC_GFX_INT_MONITOR_MASK__GFX_INT_MONITOR_MSI_EDATA_MASK_MASK                                        0x00000010L
+#define BIFC_GFX_INT_MONITOR_MASK__GFX_INT_MONITOR_MSIX_ADDR_MASK_MASK                                        0x00000020L
+#define BIFC_GFX_INT_MONITOR_MASK__GFX_INT_MONITOR_MSIX_UPADDR_MASK_MASK                                      0x00000040L
+#define BIFC_GFX_INT_MONITOR_MASK__GFX_INT_MONITOR_MSIX_DATA_MASK_MASK                                        0x00000080L
+#define BIFC_GFX_INT_MONITOR_MASK__GFX_INT_MONITOR_VEC_MASK_MASK                                              0x00000100L
+#define BIFC_GFX_INT_MONITOR_MASK__GFX_INT_MONITOR_PEND_MASK_MASK                                             0x00000200L
+#define BIFC_GFX_INT_MONITOR_MASK__GFX_INT_MONITOR_MSIX_CTRL_MASK_MASK                                        0x00000400L
+//BIFC_GFX_INT_MONITOR_STS
+#define BIFC_GFX_INT_MONITOR_STS__GFX_INT_MONITOR_MSI_CTRL_STS__SHIFT                                         0x0
+#define BIFC_GFX_INT_MONITOR_STS__GFX_INT_MONITOR_MSI_ADDR_STS__SHIFT                                         0x1
+#define BIFC_GFX_INT_MONITOR_STS__GFX_INT_MONITOR_MSI_UPADDR_STS__SHIFT                                       0x2
+#define BIFC_GFX_INT_MONITOR_STS__GFX_INT_MONITOR_MSI_DATA_STS__SHIFT                                         0x3
+#define BIFC_GFX_INT_MONITOR_STS__GFX_INT_MONITOR_MSI_EDATA_STS__SHIFT                                        0x4
+#define BIFC_GFX_INT_MONITOR_STS__GFX_INT_MONITOR_MSIX_ADDR_STS__SHIFT                                        0x5
+#define BIFC_GFX_INT_MONITOR_STS__GFX_INT_MONITOR_MSIX_UPADDR_STS__SHIFT                                      0x6
+#define BIFC_GFX_INT_MONITOR_STS__GFX_INT_MONITOR_MSIX_DATA_STS__SHIFT                                        0x7
+#define BIFC_GFX_INT_MONITOR_STS__GFX_INT_MONITOR_VEC_STS__SHIFT                                              0x8
+#define BIFC_GFX_INT_MONITOR_STS__GFX_INT_MONITOR_PEND_STS__SHIFT                                             0x9
+#define BIFC_GFX_INT_MONITOR_STS__GFX_INT_MONITOR_MSIX_CTRL_STS__SHIFT                                        0xa
+#define BIFC_GFX_INT_MONITOR_STS__GFX_INT_MONITOR_MSI_CTRL_STS_MASK                                           0x00000001L
+#define BIFC_GFX_INT_MONITOR_STS__GFX_INT_MONITOR_MSI_ADDR_STS_MASK                                           0x00000002L
+#define BIFC_GFX_INT_MONITOR_STS__GFX_INT_MONITOR_MSI_UPADDR_STS_MASK                                         0x00000004L
+#define BIFC_GFX_INT_MONITOR_STS__GFX_INT_MONITOR_MSI_DATA_STS_MASK                                           0x00000008L
+#define BIFC_GFX_INT_MONITOR_STS__GFX_INT_MONITOR_MSI_EDATA_STS_MASK                                          0x00000010L
+#define BIFC_GFX_INT_MONITOR_STS__GFX_INT_MONITOR_MSIX_ADDR_STS_MASK                                          0x00000020L
+#define BIFC_GFX_INT_MONITOR_STS__GFX_INT_MONITOR_MSIX_UPADDR_STS_MASK                                        0x00000040L
+#define BIFC_GFX_INT_MONITOR_STS__GFX_INT_MONITOR_MSIX_DATA_STS_MASK                                          0x00000080L
+#define BIFC_GFX_INT_MONITOR_STS__GFX_INT_MONITOR_VEC_STS_MASK                                                0x00000100L
+#define BIFC_GFX_INT_MONITOR_STS__GFX_INT_MONITOR_PEND_STS_MASK                                               0x00000200L
+#define BIFC_GFX_INT_MONITOR_STS__GFX_INT_MONITOR_MSIX_CTRL_STS_MASK                                          0x00000400L
+//BIFC_GFX_INT_MONITOR_CTRL
+#define BIFC_GFX_INT_MONITOR_CTRL__GFX_INT_MONITOR_VEC_SEL__SHIFT                                             0x0
+#define BIFC_GFX_INT_MONITOR_CTRL__GFX_INT_MONITOR_VEC_SEL_MASK                                               0x0000000FL
+//NBIF_FLUSH_CTRL
+#define NBIF_FLUSH_CTRL__GMI_FLUSH_OT_ENABLE__SHIFT                                                           0x0
+#define NBIF_FLUSH_CTRL__GSI_FLUSH_OT_ENABLE__SHIFT                                                           0x1
+#define NBIF_FLUSH_CTRL__FLUSH_ADD_BUBBLE_EN__SHIFT                                                           0x3
+#define NBIF_FLUSH_CTRL__FLUSH_ADD_BUBBLE_SEL__SHIFT                                                          0x4
+#define NBIF_FLUSH_CTRL__NBIF_GRP1_RW_OT_SWITCH__SHIFT                                                        0x6
+#define NBIF_FLUSH_CTRL__GMI_FLUSH_OT_ENABLE_MASK                                                             0x00000001L
+#define NBIF_FLUSH_CTRL__GSI_FLUSH_OT_ENABLE_MASK                                                             0x00000002L
+#define NBIF_FLUSH_CTRL__FLUSH_ADD_BUBBLE_EN_MASK                                                             0x00000008L
+#define NBIF_FLUSH_CTRL__FLUSH_ADD_BUBBLE_SEL_MASK                                                            0x00000030L
+#define NBIF_FLUSH_CTRL__NBIF_GRP1_RW_OT_SWITCH_MASK                                                          0x00000040L
+//NBIF_GUI_FLUSH_CNTL
+#define NBIF_GUI_FLUSH_CNTL__NBIF_GUI_FLUSH_REQ_MERGE__SHIFT                                                  0x0
+#define NBIF_GUI_FLUSH_CNTL__NBIF_GUI_FLUSH_REQ_MERGE_MASK                                                    0x00000001L
+//BIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC
+#define BIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC__VC0_ALLOC__SHIFT                                                   0x0
+#define BIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC__VC1_ALLOC__SHIFT                                                   0x4
+#define BIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC__VC0_ALLOC_MASK                                                     0x0000000FL
+#define BIFC_HRP_SDP_WRRSP_POOLCRED_ALLOC__VC1_ALLOC_MASK                                                     0x000000F0L
+//BIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC
+#define BIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC__VC0_ALLOC__SHIFT                                                   0x0
+#define BIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC__VC1_ALLOC__SHIFT                                                   0x4
+#define BIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC__VC0_ALLOC_MASK                                                     0x0000000FL
+#define BIFC_HRP_SDP_RDRSP_POOLCRED_ALLOC__VC1_ALLOC_MASK                                                     0x000000F0L
+//BIFC_GMI_SDP_REQ_POOLCRED_ALLOC
+#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC0_ALLOC__SHIFT                                                     0x0
+#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC1_ALLOC__SHIFT                                                     0x4
+#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC2_ALLOC__SHIFT                                                     0x8
+#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC3_ALLOC__SHIFT                                                     0xc
+#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC4_ALLOC__SHIFT                                                     0x10
+#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC5_ALLOC__SHIFT                                                     0x14
+#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC6_ALLOC__SHIFT                                                     0x18
+#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC7_ALLOC__SHIFT                                                     0x1c
+#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC0_ALLOC_MASK                                                       0x0000000FL
+#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC1_ALLOC_MASK                                                       0x000000F0L
+#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC2_ALLOC_MASK                                                       0x00000F00L
+#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC3_ALLOC_MASK                                                       0x0000F000L
+#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC4_ALLOC_MASK                                                       0x000F0000L
+#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC5_ALLOC_MASK                                                       0x00F00000L
+#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC6_ALLOC_MASK                                                       0x0F000000L
+#define BIFC_GMI_SDP_REQ_POOLCRED_ALLOC__VC7_ALLOC_MASK                                                       0xF0000000L
+//BIFC_GMI_SDP_DAT_POOLCRED_ALLOC
+#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC0_ALLOC__SHIFT                                                     0x0
+#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC1_ALLOC__SHIFT                                                     0x4
+#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC2_ALLOC__SHIFT                                                     0x8
+#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC3_ALLOC__SHIFT                                                     0xc
+#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC4_ALLOC__SHIFT                                                     0x10
+#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC5_ALLOC__SHIFT                                                     0x14
+#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC6_ALLOC__SHIFT                                                     0x18
+#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC7_ALLOC__SHIFT                                                     0x1c
+#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC0_ALLOC_MASK                                                       0x0000000FL
+#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC1_ALLOC_MASK                                                       0x000000F0L
+#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC2_ALLOC_MASK                                                       0x00000F00L
+#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC3_ALLOC_MASK                                                       0x0000F000L
+#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC4_ALLOC_MASK                                                       0x000F0000L
+#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC5_ALLOC_MASK                                                       0x00F00000L
+#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC6_ALLOC_MASK                                                       0x0F000000L
+#define BIFC_GMI_SDP_DAT_POOLCRED_ALLOC__VC7_ALLOC_MASK                                                       0xF0000000L
+//BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC
+#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC0_ALLOC__SHIFT                                                   0x0
+#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC1_ALLOC__SHIFT                                                   0x4
+#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC2_ALLOC__SHIFT                                                   0x8
+#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC3_ALLOC__SHIFT                                                   0xc
+#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC4_ALLOC__SHIFT                                                   0x10
+#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC5_ALLOC__SHIFT                                                   0x14
+#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC6_ALLOC__SHIFT                                                   0x18
+#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC7_ALLOC__SHIFT                                                   0x1c
+#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC0_ALLOC_MASK                                                     0x0000000FL
+#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC1_ALLOC_MASK                                                     0x000000F0L
+#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC2_ALLOC_MASK                                                     0x00000F00L
+#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC3_ALLOC_MASK                                                     0x0000F000L
+#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC4_ALLOC_MASK                                                     0x000F0000L
+#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC5_ALLOC_MASK                                                     0x00F00000L
+#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC6_ALLOC_MASK                                                     0x0F000000L
+#define BIFC_GMI_SST_RDRSP_POOLCRED_ALLOC__VC7_ALLOC_MASK                                                     0xF0000000L
+//BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC
+#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC0_ALLOC__SHIFT                                                   0x0
+#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC1_ALLOC__SHIFT                                                   0x4
+#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC2_ALLOC__SHIFT                                                   0x8
+#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC3_ALLOC__SHIFT                                                   0xc
+#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC4_ALLOC__SHIFT                                                   0x10
+#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC5_ALLOC__SHIFT                                                   0x14
+#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC6_ALLOC__SHIFT                                                   0x18
+#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC7_ALLOC__SHIFT                                                   0x1c
+#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC0_ALLOC_MASK                                                     0x0000000FL
+#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC1_ALLOC_MASK                                                     0x000000F0L
+#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC2_ALLOC_MASK                                                     0x00000F00L
+#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC3_ALLOC_MASK                                                     0x0000F000L
+#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC4_ALLOC_MASK                                                     0x000F0000L
+#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC5_ALLOC_MASK                                                     0x00F00000L
+#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC6_ALLOC_MASK                                                     0x0F000000L
+#define BIFC_GMI_SST_WRRSP_POOLCRED_ALLOC__VC7_ALLOC_MASK                                                     0xF0000000L
+//DISCON_HYSTERESIS_HEAD_CTRL
+#define DISCON_HYSTERESIS_HEAD_CTRL__GMI_DNS_SDP_DISCON_HYSTERESIS_H__SHIFT                                   0x0
+#define DISCON_HYSTERESIS_HEAD_CTRL__GMI_UPS_SDP_DISCON_HYSTERESIS_H__SHIFT                                   0x8
+#define DISCON_HYSTERESIS_HEAD_CTRL__GMI_DNS_SDP_DISCON_HYSTERESIS_H_MASK                                     0x0000000FL
+#define DISCON_HYSTERESIS_HEAD_CTRL__GMI_UPS_SDP_DISCON_HYSTERESIS_H_MASK                                     0x00000F00L
+//BIFC_GSI_SDP_REQ_POOLCRED_ALLOC
+#define BIFC_GSI_SDP_REQ_POOLCRED_ALLOC__VC0_ALLOC__SHIFT                                                     0x0
+#define BIFC_GSI_SDP_REQ_POOLCRED_ALLOC__VC1_ALLOC__SHIFT                                                     0x4
+#define BIFC_GSI_SDP_REQ_POOLCRED_ALLOC__VC2_ALLOC__SHIFT                                                     0x8
+#define BIFC_GSI_SDP_REQ_POOLCRED_ALLOC__VC3_ALLOC__SHIFT                                                     0xc
+#define BIFC_GSI_SDP_REQ_POOLCRED_ALLOC__VC4_ALLOC__SHIFT                                                     0x10
+#define BIFC_GSI_SDP_REQ_POOLCRED_ALLOC__VC5_ALLOC__SHIFT                                                     0x14
+#define BIFC_GSI_SDP_REQ_POOLCRED_ALLOC__VC6_ALLOC__SHIFT                                                     0x18
+#define BIFC_GSI_SDP_REQ_POOLCRED_ALLOC__VC7_ALLOC__SHIFT                                                     0x1c
+#define BIFC_GSI_SDP_REQ_POOLCRED_ALLOC__VC0_ALLOC_MASK                                                       0x0000000FL
+#define BIFC_GSI_SDP_REQ_POOLCRED_ALLOC__VC1_ALLOC_MASK                                                       0x000000F0L
+#define BIFC_GSI_SDP_REQ_POOLCRED_ALLOC__VC2_ALLOC_MASK                                                       0x00000F00L
+#define BIFC_GSI_SDP_REQ_POOLCRED_ALLOC__VC3_ALLOC_MASK                                                       0x0000F000L
+#define BIFC_GSI_SDP_REQ_POOLCRED_ALLOC__VC4_ALLOC_MASK                                                       0x000F0000L
+#define BIFC_GSI_SDP_REQ_POOLCRED_ALLOC__VC5_ALLOC_MASK                                                       0x00F00000L
+#define BIFC_GSI_SDP_REQ_POOLCRED_ALLOC__VC6_ALLOC_MASK                                                       0x0F000000L
+#define BIFC_GSI_SDP_REQ_POOLCRED_ALLOC__VC7_ALLOC_MASK                                                       0xF0000000L
+//BIFC_GSI_SDP_DAT_POOLCRED_ALLOC
+#define BIFC_GSI_SDP_DAT_POOLCRED_ALLOC__VC0_ALLOC__SHIFT                                                     0x0
+#define BIFC_GSI_SDP_DAT_POOLCRED_ALLOC__VC1_ALLOC__SHIFT                                                     0x4
+#define BIFC_GSI_SDP_DAT_POOLCRED_ALLOC__VC2_ALLOC__SHIFT                                                     0x8
+#define BIFC_GSI_SDP_DAT_POOLCRED_ALLOC__VC3_ALLOC__SHIFT                                                     0xc
+#define BIFC_GSI_SDP_DAT_POOLCRED_ALLOC__VC4_ALLOC__SHIFT                                                     0x10
+#define BIFC_GSI_SDP_DAT_POOLCRED_ALLOC__VC5_ALLOC__SHIFT                                                     0x14
+#define BIFC_GSI_SDP_DAT_POOLCRED_ALLOC__VC6_ALLOC__SHIFT                                                     0x18
+#define BIFC_GSI_SDP_DAT_POOLCRED_ALLOC__VC7_ALLOC__SHIFT                                                     0x1c
+#define BIFC_GSI_SDP_DAT_POOLCRED_ALLOC__VC0_ALLOC_MASK                                                       0x0000000FL
+#define BIFC_GSI_SDP_DAT_POOLCRED_ALLOC__VC1_ALLOC_MASK                                                       0x000000F0L
+#define BIFC_GSI_SDP_DAT_POOLCRED_ALLOC__VC2_ALLOC_MASK                                                       0x00000F00L
+#define BIFC_GSI_SDP_DAT_POOLCRED_ALLOC__VC3_ALLOC_MASK                                                       0x0000F000L
+#define BIFC_GSI_SDP_DAT_POOLCRED_ALLOC__VC4_ALLOC_MASK                                                       0x000F0000L
+#define BIFC_GSI_SDP_DAT_POOLCRED_ALLOC__VC5_ALLOC_MASK                                                       0x00F00000L
+#define BIFC_GSI_SDP_DAT_POOLCRED_ALLOC__VC6_ALLOC_MASK                                                       0x0F000000L
+#define BIFC_GSI_SDP_DAT_POOLCRED_ALLOC__VC7_ALLOC_MASK                                                       0xF0000000L
+//BIFC_MCA_SMN_CTRL0
+#define BIFC_MCA_SMN_CTRL0__MCA_SMN_POSTED__SHIFT                                                             0x0
+#define BIFC_MCA_SMN_CTRL0__MCA_SMN_POSTED_MASK                                                               0x00000001L
+//BIFC_MCTP_SMN_CTRL0
+#define BIFC_MCTP_SMN_CTRL0__MCTP_SMN_POSTED__SHIFT                                                           0x0
+#define BIFC_MCTP_SMN_CTRL0__MCTP_SMN_POSTED_MASK                                                             0x00000001L
+//NBIF_REGIF_DEBUG_COUNTER_CTRL
+//BIFC_EARLY_WAKEUP_CNTL
+#define BIFC_EARLY_WAKEUP_CNTL__NBIF_EARLY_WAKEUP_BY_CLIENT_ACTIVE__SHIFT                                     0x0
+#define BIFC_EARLY_WAKEUP_CNTL__NBIF_EARLY_WAKEUP_BY_CLIENT_DS_EXIT__SHIFT                                    0x1
+#define BIFC_EARLY_WAKEUP_CNTL__NBIF_EARLY_WAKEUP_ALLOW_AER_ACTIVE__SHIFT                                     0x2
+#define BIFC_EARLY_WAKEUP_CNTL__NBIF_EARLY_WAKEUP_BY_CLIENT_ACTIVE_MASK                                       0x00000001L
+#define BIFC_EARLY_WAKEUP_CNTL__NBIF_EARLY_WAKEUP_BY_CLIENT_DS_EXIT_MASK                                      0x00000002L
+#define BIFC_EARLY_WAKEUP_CNTL__NBIF_EARLY_WAKEUP_ALLOW_AER_ACTIVE_MASK                                       0x00000004L
+//BIFC_PERF_CNT_MMIO_RD_H16BIT
+#define BIFC_PERF_CNT_MMIO_RD_H16BIT__PERF_CNT_MMIO_RD_VALUE_H16BIT__SHIFT                                    0x0
+#define BIFC_PERF_CNT_MMIO_RD_H16BIT__PERF_CNT_MMIO_RD_VALUE_H16BIT_MASK                                      0x0000FFFFL
+//BIFC_PERF_CNT_MMIO_WR_H16BIT
+#define BIFC_PERF_CNT_MMIO_WR_H16BIT__PERF_CNT_MMIO_WR_VALUE_H16BIT__SHIFT                                    0x0
+#define BIFC_PERF_CNT_MMIO_WR_H16BIT__PERF_CNT_MMIO_WR_VALUE_H16BIT_MASK                                      0x0000FFFFL
+//BIF_MISC_BIFC_PERF_CNT_DMA_RD_H16BIT
+#define BIF_MISC_BIFC_PERF_CNT_DMA_RD_H16BIT__PERF_CNT_DMA_RD_VALUE_H16BIT__SHIFT                             0x0
+#define BIF_MISC_BIFC_PERF_CNT_DMA_RD_H16BIT__PERF_CNT_DMA_RD_VALUE_H16BIT_MASK                               0x0000FFFFL
+//BIF_MISC_BIFC_PERF_CNT_DMA_WR_H16BIT
+#define BIF_MISC_BIFC_PERF_CNT_DMA_WR_H16BIT__PERF_CNT_DMA_WR_VALUE_H16BIT__SHIFT                             0x0
+#define BIF_MISC_BIFC_PERF_CNT_DMA_WR_H16BIT__PERF_CNT_DMA_WR_VALUE_H16BIT_MASK                               0x0000FFFFL
+//BIF_MISC_NBIF_PERF_COM_COUNT_ENABLE
+#define BIF_MISC_NBIF_PERF_COM_COUNT_ENABLE__NBIF_COM_COUNT_ENABLE__SHIFT                                     0x0
+#define BIF_MISC_NBIF_PERF_COM_COUNT_ENABLE__START_COUNT_NOPULS__SHIFT                                        0x3
+#define BIF_MISC_NBIF_PERF_COM_COUNT_ENABLE__LEGACY_OUT_REALTIME_SEL__SHIFT                                   0x4
+#define BIF_MISC_NBIF_PERF_COM_COUNT_ENABLE__PERF_CNT_TRIG_MONI_SEL__SHIFT                                    0x5
+#define BIF_MISC_NBIF_PERF_COM_COUNT_ENABLE__NBIF_COM_COUNT_ENABLE_MASK                                       0x00000001L
+#define BIF_MISC_NBIF_PERF_COM_COUNT_ENABLE__START_COUNT_NOPULS_MASK                                          0x00000008L
+#define BIF_MISC_NBIF_PERF_COM_COUNT_ENABLE__LEGACY_OUT_REALTIME_SEL_MASK                                     0x00000010L
+#define BIF_MISC_NBIF_PERF_COM_COUNT_ENABLE__PERF_CNT_TRIG_MONI_SEL_MASK                                      0x00000060L
+//BIF_MISC_NBIF_SDP_PERF_CNT_FSM
+#define BIF_MISC_NBIF_SDP_PERF_CNT_FSM__SDP_GLOBAL_SHADOW_TGL_DELAY_COUNT__SHIFT                              0x0
+#define BIF_MISC_NBIF_SDP_PERF_CNT_FSM__SDP_GLOBAL_PERF_RESET_TGL_DELAY_COUNT__SHIFT                          0x4
+#define BIF_MISC_NBIF_SDP_PERF_CNT_FSM__SDP_GLOBAL_PERF_RESET_TGL_DELAY_EN__SHIFT                             0x8
+#define BIF_MISC_NBIF_SDP_PERF_CNT_FSM__SDP_PRE_FLD_GLOBAL_SHADOW_WR__SHIFT                                   0x9
+#define BIF_MISC_NBIF_SDP_PERF_CNT_FSM__SDP_PERF_CNT_DONE__SHIFT                                              0xa
+#define BIF_MISC_NBIF_SDP_PERF_CNT_FSM__SDP_PERF_CNT0_RESET__SHIFT                                            0xb
+#define BIF_MISC_NBIF_SDP_PERF_CNT_FSM__SDP_PERF_CNT1_RESET__SHIFT                                            0xc
+#define BIF_MISC_NBIF_SDP_PERF_CNT_FSM__SDP_PERF_CNT2_RESET__SHIFT                                            0xd
+#define BIF_MISC_NBIF_SDP_PERF_CNT_FSM__SDP_PERF_CNT3_RESET__SHIFT                                            0xe
+#define BIF_MISC_NBIF_SDP_PERF_CNT_FSM__SDP_PERF_REQ_UNIT_ID__SHIFT                                           0xf
+#define BIF_MISC_NBIF_SDP_PERF_CNT_FSM__SDP_GLOBAL_SHADOW_TGL_DELAY_COUNT_MASK                                0x0000000FL
+#define BIF_MISC_NBIF_SDP_PERF_CNT_FSM__SDP_GLOBAL_PERF_RESET_TGL_DELAY_COUNT_MASK                            0x000000F0L
+#define BIF_MISC_NBIF_SDP_PERF_CNT_FSM__SDP_GLOBAL_PERF_RESET_TGL_DELAY_EN_MASK                               0x00000100L
+#define BIF_MISC_NBIF_SDP_PERF_CNT_FSM__SDP_PRE_FLD_GLOBAL_SHADOW_WR_MASK                                     0x00000200L
+#define BIF_MISC_NBIF_SDP_PERF_CNT_FSM__SDP_PERF_CNT_DONE_MASK                                                0x00000400L
+#define BIF_MISC_NBIF_SDP_PERF_CNT_FSM__SDP_PERF_CNT0_RESET_MASK                                              0x00000800L
+#define BIF_MISC_NBIF_SDP_PERF_CNT_FSM__SDP_PERF_CNT1_RESET_MASK                                              0x00001000L
+#define BIF_MISC_NBIF_SDP_PERF_CNT_FSM__SDP_PERF_CNT2_RESET_MASK                                              0x00002000L
+#define BIF_MISC_NBIF_SDP_PERF_CNT_FSM__SDP_PERF_CNT3_RESET_MASK                                              0x00004000L
+#define BIF_MISC_NBIF_SDP_PERF_CNT_FSM__SDP_PERF_REQ_UNIT_ID_MASK                                             0x03FF8000L
+//BIF_MISC_NBIF_SDP_PERF_COUNTER
+#define BIF_MISC_NBIF_SDP_PERF_COUNTER__SDP_PERF_CNT_0_EN__SHIFT                                              0x0
+#define BIF_MISC_NBIF_SDP_PERF_COUNTER__SDP_PERF_CNT_1_EN__SHIFT                                              0x1
+#define BIF_MISC_NBIF_SDP_PERF_COUNTER__SDP_PERF_CNT_2_EN__SHIFT                                              0x2
+#define BIF_MISC_NBIF_SDP_PERF_COUNTER__SDP_PERF_CNT_3_EN__SHIFT                                              0x3
+#define BIF_MISC_NBIF_SDP_PERF_COUNTER__SDP_PERF_CNT_0_SEL__SHIFT                                             0x4
+#define BIF_MISC_NBIF_SDP_PERF_COUNTER__SDP_PERF_CNT_1_SEL__SHIFT                                             0xb
+#define BIF_MISC_NBIF_SDP_PERF_COUNTER__SDP_PERF_CNT_2_SEL__SHIFT                                             0x12
+#define BIF_MISC_NBIF_SDP_PERF_COUNTER__SDP_PERF_CNT_3_SEL__SHIFT                                             0x19
+#define BIF_MISC_NBIF_SDP_PERF_COUNTER__SDP_PERF_CNT_0_EN_MASK                                                0x00000001L
+#define BIF_MISC_NBIF_SDP_PERF_COUNTER__SDP_PERF_CNT_1_EN_MASK                                                0x00000002L
+#define BIF_MISC_NBIF_SDP_PERF_COUNTER__SDP_PERF_CNT_2_EN_MASK                                                0x00000004L
+#define BIF_MISC_NBIF_SDP_PERF_COUNTER__SDP_PERF_CNT_3_EN_MASK                                                0x00000008L
+#define BIF_MISC_NBIF_SDP_PERF_COUNTER__SDP_PERF_CNT_0_SEL_MASK                                               0x000007F0L
+#define BIF_MISC_NBIF_SDP_PERF_COUNTER__SDP_PERF_CNT_1_SEL_MASK                                               0x0003F800L
+#define BIF_MISC_NBIF_SDP_PERF_COUNTER__SDP_PERF_CNT_2_SEL_MASK                                               0x01FC0000L
+#define BIF_MISC_NBIF_SDP_PERF_COUNTER__SDP_PERF_CNT_3_SEL_MASK                                               0xFE000000L
+//BIF_MISC_NBIF_SDP_PERF_CNT_0_VALUE_L32BIT
+#define BIF_MISC_NBIF_SDP_PERF_CNT_0_VALUE_L32BIT__SDP_PERF_CNT_0_VALUE_L32BIT__SHIFT                         0x0
+#define BIF_MISC_NBIF_SDP_PERF_CNT_0_VALUE_L32BIT__SDP_PERF_CNT_0_VALUE_L32BIT_MASK                           0xFFFFFFFFL
+//BIF_MISC_NBIF_SDP_PERF_CNT_1_VALUE_L32BIT
+#define BIF_MISC_NBIF_SDP_PERF_CNT_1_VALUE_L32BIT__SDP_PERF_CNT_1_VALUE_L32BIT__SHIFT                         0x0
+#define BIF_MISC_NBIF_SDP_PERF_CNT_1_VALUE_L32BIT__SDP_PERF_CNT_1_VALUE_L32BIT_MASK                           0xFFFFFFFFL
+//BIF_MISC_NBIF_SDP_PERF_CNT_2_VALUE_L32BIT
+#define BIF_MISC_NBIF_SDP_PERF_CNT_2_VALUE_L32BIT__SDP_PERF_CNT_2_VALUE_L32BIT__SHIFT                         0x0
+#define BIF_MISC_NBIF_SDP_PERF_CNT_2_VALUE_L32BIT__SDP_PERF_CNT_2_VALUE_L32BIT_MASK                           0xFFFFFFFFL
+//BIF_MISC_NBIF_SDP_PERF_CNT_3_VALUE_L32BIT
+#define BIF_MISC_NBIF_SDP_PERF_CNT_3_VALUE_L32BIT__SDP_PERF_CNT_3_VALUE_L32BIT__SHIFT                         0x0
+#define BIF_MISC_NBIF_SDP_PERF_CNT_3_VALUE_L32BIT__SDP_PERF_CNT_3_VALUE_L32BIT_MASK                           0xFFFFFFFFL
+//BIF_MISC_NBIF_SDP_PERF_CNT_0_VALUE_H16BIT
+#define BIF_MISC_NBIF_SDP_PERF_CNT_0_VALUE_H16BIT__SDP_PERF_CNT_0_VALUE_H16BIT__SHIFT                         0x0
+#define BIF_MISC_NBIF_SDP_PERF_CNT_0_VALUE_H16BIT__SDP_PERF_CNT_0_VALUE_H16BIT_MASK                           0x0000FFFFL
+//BIF_MISC_NBIF_SDP_PERF_CNT_1_VALUE_H16BIT
+#define BIF_MISC_NBIF_SDP_PERF_CNT_1_VALUE_H16BIT__SDP_PERF_CNT_1_VALUE_H16BIT__SHIFT                         0x0
+#define BIF_MISC_NBIF_SDP_PERF_CNT_1_VALUE_H16BIT__SDP_PERF_CNT_1_VALUE_H16BIT_MASK                           0x0000FFFFL
+//BIF_MISC_NBIF_SDP_PERF_CNT_2_VALUE_H16BIT
+#define BIF_MISC_NBIF_SDP_PERF_CNT_2_VALUE_H16BIT__SDP_PERF_CNT_2_VALUE_H16BIT__SHIFT                         0x0
+#define BIF_MISC_NBIF_SDP_PERF_CNT_2_VALUE_H16BIT__SDP_PERF_CNT_2_VALUE_H16BIT_MASK                           0x0000FFFFL
+//BIF_MISC_NBIF_SDP_PERF_CNT_3_VALUE_H16BIT
+#define BIF_MISC_NBIF_SDP_PERF_CNT_3_VALUE_H16BIT__SDP_PERF_CNT_3_VALUE_H16BIT__SHIFT                         0x0
+#define BIF_MISC_NBIF_SDP_PERF_CNT_3_VALUE_H16BIT__SDP_PERF_CNT_3_VALUE_H16BIT_MASK                           0x0000FFFFL
+//BIF_MISC_NBIF_BX_PERF_CNT_FSM
+#define BIF_MISC_NBIF_BX_PERF_CNT_FSM__BX_GLOBAL_SHADOW_TGL_DELAY_COUNT__SHIFT                                0x0
+#define BIF_MISC_NBIF_BX_PERF_CNT_FSM__BX_GLOBAL_PERF_RESET_TGL_DELAY_COUNT__SHIFT                            0x4
+#define BIF_MISC_NBIF_BX_PERF_CNT_FSM__BX_GLOBAL_PERF_RESET_TGL_DELAY_EN__SHIFT                               0x8
+#define BIF_MISC_NBIF_BX_PERF_CNT_FSM__BX_PRE_FLD_GLOBAL_SHADOW_WR__SHIFT                                     0x9
+#define BIF_MISC_NBIF_BX_PERF_CNT_FSM__BX_PERF_CNT_DONE__SHIFT                                                0xa
+#define BIF_MISC_NBIF_BX_PERF_CNT_FSM__BX_GLOBAL_SHADOW_TGL_DELAY_COUNT_MASK                                  0x0000000FL
+#define BIF_MISC_NBIF_BX_PERF_CNT_FSM__BX_GLOBAL_PERF_RESET_TGL_DELAY_COUNT_MASK                              0x000000F0L
+#define BIF_MISC_NBIF_BX_PERF_CNT_FSM__BX_GLOBAL_PERF_RESET_TGL_DELAY_EN_MASK                                 0x00000100L
+#define BIF_MISC_NBIF_BX_PERF_CNT_FSM__BX_PRE_FLD_GLOBAL_SHADOW_WR_MASK                                       0x00000200L
+#define BIF_MISC_NBIF_BX_PERF_CNT_FSM__BX_PERF_CNT_DONE_MASK                                                  0x00000400L
+//NBIF_TDISP_ENTER_ERR_CNTL
+#define NBIF_TDISP_ENTER_ERR_CNTL__NBIF_TDISP_ENTER_ERR_BY_POISONEDTLP_EN__SHIFT                              0x0
+#define NBIF_TDISP_ENTER_ERR_CNTL__NBIF_TDISP_ENTER_ERR_BY_UR_EN__SHIFT                                       0x1
+#define NBIF_TDISP_ENTER_ERR_CNTL__NBIF_TDISP_ENTER_ERR_BY_CA_EN__SHIFT                                       0x2
+#define NBIF_TDISP_ENTER_ERR_CNTL__NBIF_TDISP_ENTER_ERR_BY_TO_EN__SHIFT                                       0x3
+#define NBIF_TDISP_ENTER_ERR_CNTL__NBIF_TDISP_ENTER_ERR_BY_POISONEDTLP_EN_MASK                                0x00000001L
+#define NBIF_TDISP_ENTER_ERR_CNTL__NBIF_TDISP_ENTER_ERR_BY_UR_EN_MASK                                         0x00000002L
+#define NBIF_TDISP_ENTER_ERR_CNTL__NBIF_TDISP_ENTER_ERR_BY_CA_EN_MASK                                         0x00000004L
+#define NBIF_TDISP_ENTER_ERR_CNTL__NBIF_TDISP_ENTER_ERR_BY_TO_EN_MASK                                         0x00000008L
+//BIF_UNITID_ERR_LOG
+#define BIF_UNITID_ERR_LOG__UR_UNITID_athub__SHIFT                                                            0x0
+#define BIF_UNITID_ERR_LOG__CLEAR_UR_UNITID_athub__SHIFT                                                      0x10
+#define BIF_UNITID_ERR_LOG__UR_UNITID_athub_MASK                                                              0x00000001L
+#define BIF_UNITID_ERR_LOG__CLEAR_UR_UNITID_athub_MASK                                                        0x00010000L
+//NBIF_COM_COUNT_VALUE
+#define NBIF_COM_COUNT_VALUE__NBIF_COM_COUNT_VALUE__SHIFT                                                     0x0
+#define NBIF_COM_COUNT_VALUE__NBIF_COM_COUNT_VALUE_MASK                                                       0xFFFFFFFFL
+//NBIF_ERREREVNT_SIDEBAND_RAS_V1_CTRL
+#define NBIF_ERREREVNT_SIDEBAND_RAS_V1_CTRL__NBIF_PORT0_RAS_V1_GEN_ERREVENT_EN__SHIFT                         0x0
+#define NBIF_ERREREVNT_SIDEBAND_RAS_V1_CTRL__NBIF_PORT1_RAS_V1_GEN_ERREVENT_EN__SHIFT                         0x1
+#define NBIF_ERREREVNT_SIDEBAND_RAS_V1_CTRL__NBIF_PORT2_RAS_V1_GEN_ERREVENT_EN__SHIFT                         0x2
+#define NBIF_ERREREVNT_SIDEBAND_RAS_V1_CTRL__NBIF_PORT3_RAS_V1_GEN_ERREVENT_EN__SHIFT                         0x3
+#define NBIF_ERREREVNT_SIDEBAND_RAS_V1_CTRL__NBIF_PORT4_RAS_V1_GEN_ERREVENT_EN__SHIFT                         0x4
+#define NBIF_ERREREVNT_SIDEBAND_RAS_V1_CTRL__NBIF_PORT5_RAS_V1_GEN_ERREVENT_EN__SHIFT                         0x5
+#define NBIF_ERREREVNT_SIDEBAND_RAS_V1_CTRL__NBIF_PORT6_RAS_V1_GEN_ERREVENT_EN__SHIFT                         0x6
+#define NBIF_ERREREVNT_SIDEBAND_RAS_V1_CTRL__NBIF_PORT7_RAS_V1_GEN_ERREVENT_EN__SHIFT                         0x7
+#define NBIF_ERREREVNT_SIDEBAND_RAS_V1_CTRL__NBIF_PORT0_RAS_V1_GEN_ERREVENT_EN_MASK                           0x00000001L
+#define NBIF_ERREREVNT_SIDEBAND_RAS_V1_CTRL__NBIF_PORT1_RAS_V1_GEN_ERREVENT_EN_MASK                           0x00000002L
+#define NBIF_ERREREVNT_SIDEBAND_RAS_V1_CTRL__NBIF_PORT2_RAS_V1_GEN_ERREVENT_EN_MASK                           0x00000004L
+#define NBIF_ERREREVNT_SIDEBAND_RAS_V1_CTRL__NBIF_PORT3_RAS_V1_GEN_ERREVENT_EN_MASK                           0x00000008L
+#define NBIF_ERREREVNT_SIDEBAND_RAS_V1_CTRL__NBIF_PORT4_RAS_V1_GEN_ERREVENT_EN_MASK                           0x00000010L
+#define NBIF_ERREREVNT_SIDEBAND_RAS_V1_CTRL__NBIF_PORT5_RAS_V1_GEN_ERREVENT_EN_MASK                           0x00000020L
+#define NBIF_ERREREVNT_SIDEBAND_RAS_V1_CTRL__NBIF_PORT6_RAS_V1_GEN_ERREVENT_EN_MASK                           0x00000040L
+#define NBIF_ERREREVNT_SIDEBAND_RAS_V1_CTRL__NBIF_PORT7_RAS_V1_GEN_ERREVENT_EN_MASK                           0x00000080L
+//NBIF_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL
+#define NBIF_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL__NBIF_PORT0_RECV_ERREVENT_GEN_ERREVENT_EN__SHIFT           0x0
+#define NBIF_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL__NBIF_PORT1_RECV_ERREVENT_GEN_ERREVENT_EN__SHIFT           0x1
+#define NBIF_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL__NBIF_PORT2_RECV_ERREVENT_GEN_ERREVENT_EN__SHIFT           0x2
+#define NBIF_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL__NBIF_PORT3_RECV_ERREVENT_GEN_ERREVENT_EN__SHIFT           0x3
+#define NBIF_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL__NBIF_PORT4_RECV_ERREVENT_GEN_ERREVENT_EN__SHIFT           0x4
+#define NBIF_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL__NBIF_PORT5_RECV_ERREVENT_GEN_ERREVENT_EN__SHIFT           0x5
+#define NBIF_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL__NBIF_PORT6_RECV_ERREVENT_GEN_ERREVENT_EN__SHIFT           0x6
+#define NBIF_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL__NBIF_PORT7_RECV_ERREVENT_GEN_ERREVENT_EN__SHIFT           0x7
+#define NBIF_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL__NBIF_PORT0_RECV_ERREVENT_GEN_ERREVENT_EN_MASK             0x00000001L
+#define NBIF_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL__NBIF_PORT1_RECV_ERREVENT_GEN_ERREVENT_EN_MASK             0x00000002L
+#define NBIF_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL__NBIF_PORT2_RECV_ERREVENT_GEN_ERREVENT_EN_MASK             0x00000004L
+#define NBIF_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL__NBIF_PORT3_RECV_ERREVENT_GEN_ERREVENT_EN_MASK             0x00000008L
+#define NBIF_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL__NBIF_PORT4_RECV_ERREVENT_GEN_ERREVENT_EN_MASK             0x00000010L
+#define NBIF_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL__NBIF_PORT5_RECV_ERREVENT_GEN_ERREVENT_EN_MASK             0x00000020L
+#define NBIF_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL__NBIF_PORT6_RECV_ERREVENT_GEN_ERREVENT_EN_MASK             0x00000040L
+#define NBIF_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL__NBIF_PORT7_RECV_ERREVENT_GEN_ERREVENT_EN_MASK             0x00000080L
+//BIF_AER_CNTL
+#define BIF_AER_CNTL__BIF_AER_VF_NUM__SHIFT                                                                   0x0
+#define BIF_AER_CNTL__BIF_AER_PF_NUM__SHIFT                                                                   0x8
+#define BIF_AER_CNTL__BIF_AER_ERR_PTR__SHIFT                                                                  0xb
+#define BIF_AER_CNTL__BIF_AER_HeaderStoreOffset__SHIFT                                                        0x10
+#define BIF_AER_CNTL__BIF_AER_ERR_MSG_TYPE__SHIFT                                                             0x18
+#define BIF_AER_CNTL__BIF_AER_DEVERR__SHIFT                                                                   0x1a
+#define BIF_AER_CNTL__BIF_AER_POSTED__SHIFT                                                                   0x1b
+#define BIF_AER_CNTL__BIF_AER_TOTAL_OF_PF__SHIFT                                                              0x1c
+#define BIF_AER_CNTL__BIF_AER_VF_HIT__SHIFT                                                                   0x1f
+#define BIF_AER_CNTL__BIF_AER_VF_NUM_MASK                                                                     0x000000FFL
+#define BIF_AER_CNTL__BIF_AER_PF_NUM_MASK                                                                     0x00000700L
+#define BIF_AER_CNTL__BIF_AER_ERR_PTR_MASK                                                                    0x0000F800L
+#define BIF_AER_CNTL__BIF_AER_HeaderStoreOffset_MASK                                                          0x00FF0000L
+#define BIF_AER_CNTL__BIF_AER_ERR_MSG_TYPE_MASK                                                               0x03000000L
+#define BIF_AER_CNTL__BIF_AER_DEVERR_MASK                                                                     0x04000000L
+#define BIF_AER_CNTL__BIF_AER_POSTED_MASK                                                                     0x08000000L
+#define BIF_AER_CNTL__BIF_AER_TOTAL_OF_PF_MASK                                                                0x70000000L
+#define BIF_AER_CNTL__BIF_AER_VF_HIT_MASK                                                                     0x80000000L
+//NBIF_IDE_INFO_CNTL
+#define NBIF_IDE_INFO_CNTL__NBIF_PRGR_MSG_IDE_INFO_FROM_DATA_EN__SHIFT                                        0x0
+#define NBIF_IDE_INFO_CNTL__NBIF_PRGR_MSG_IDE_INFO_FROM_DATA_EN_MASK                                          0x00000001L
+//BIFC_EXP_MISC_CTRL0
+#define BIFC_EXP_MISC_CTRL0__VC0_DMA_IOCFG_DIS__SHIFT                                                         0x0
+#define BIFC_EXP_MISC_CTRL0__VC1_DMA_IOCFG_DIS__SHIFT                                                         0x1
+#define BIFC_EXP_MISC_CTRL0__VC2_DMA_IOCFG_DIS__SHIFT                                                         0x2
+#define BIFC_EXP_MISC_CTRL0__VC3_DMA_IOCFG_DIS__SHIFT                                                         0x3
+#define BIFC_EXP_MISC_CTRL0__VC4_DMA_IOCFG_DIS__SHIFT                                                         0x4
+#define BIFC_EXP_MISC_CTRL0__VC5_DMA_IOCFG_DIS__SHIFT                                                         0x5
+#define BIFC_EXP_MISC_CTRL0__VC6_DMA_IOCFG_DIS__SHIFT                                                         0x6
+#define BIFC_EXP_MISC_CTRL0__VC7_DMA_IOCFG_DIS__SHIFT                                                         0x7
+#define BIFC_EXP_MISC_CTRL0__VC0_DMA_IOCFG_DIS_MASK                                                           0x00000001L
+#define BIFC_EXP_MISC_CTRL0__VC1_DMA_IOCFG_DIS_MASK                                                           0x00000002L
+#define BIFC_EXP_MISC_CTRL0__VC2_DMA_IOCFG_DIS_MASK                                                           0x00000004L
+#define BIFC_EXP_MISC_CTRL0__VC3_DMA_IOCFG_DIS_MASK                                                           0x00000008L
+#define BIFC_EXP_MISC_CTRL0__VC4_DMA_IOCFG_DIS_MASK                                                           0x00000010L
+#define BIFC_EXP_MISC_CTRL0__VC5_DMA_IOCFG_DIS_MASK                                                           0x00000020L
+#define BIFC_EXP_MISC_CTRL0__VC6_DMA_IOCFG_DIS_MASK                                                           0x00000040L
+#define BIFC_EXP_MISC_CTRL0__VC7_DMA_IOCFG_DIS_MASK                                                           0x00000080L
+//SECOND_HDP_MEM_FLUSH_CNTL_PF
+#define SECOND_HDP_MEM_FLUSH_CNTL_PF__ADDRESS__SHIFT                                                          0x2
+#define SECOND_HDP_MEM_FLUSH_CNTL_PF__ADDRESS_MASK                                                            0x0007FFFCL
+//SECOND_HDP_MEM_FLUSH_CNTL_VF0
+#define SECOND_HDP_MEM_FLUSH_CNTL_VF0__ADDRESS__SHIFT                                                         0x2
+#define SECOND_HDP_MEM_FLUSH_CNTL_VF0__ADDRESS_MASK                                                           0x0007FFFCL
+//SECOND_HDP_MEM_FLUSH_CNTL_VF1
+#define SECOND_HDP_MEM_FLUSH_CNTL_VF1__ADDRESS__SHIFT                                                         0x2
+#define SECOND_HDP_MEM_FLUSH_CNTL_VF1__ADDRESS_MASK                                                           0x0007FFFCL
+//SECOND_HDP_MEM_FLUSH_CNTL_VF2
+#define SECOND_HDP_MEM_FLUSH_CNTL_VF2__ADDRESS__SHIFT                                                         0x2
+#define SECOND_HDP_MEM_FLUSH_CNTL_VF2__ADDRESS_MASK                                                           0x0007FFFCL
+//SECOND_HDP_MEM_FLUSH_CNTL_VF3
+#define SECOND_HDP_MEM_FLUSH_CNTL_VF3__ADDRESS__SHIFT                                                         0x2
+#define SECOND_HDP_MEM_FLUSH_CNTL_VF3__ADDRESS_MASK                                                           0x0007FFFCL
+//SECOND_HDP_MEM_FLUSH_CNTL_VF4
+#define SECOND_HDP_MEM_FLUSH_CNTL_VF4__ADDRESS__SHIFT                                                         0x2
+#define SECOND_HDP_MEM_FLUSH_CNTL_VF4__ADDRESS_MASK                                                           0x0007FFFCL
+//SECOND_HDP_MEM_FLUSH_CNTL_VF5
+#define SECOND_HDP_MEM_FLUSH_CNTL_VF5__ADDRESS__SHIFT                                                         0x2
+#define SECOND_HDP_MEM_FLUSH_CNTL_VF5__ADDRESS_MASK                                                           0x0007FFFCL
+//SECOND_HDP_MEM_FLUSH_CNTL_VF6
+#define SECOND_HDP_MEM_FLUSH_CNTL_VF6__ADDRESS__SHIFT                                                         0x2
+#define SECOND_HDP_MEM_FLUSH_CNTL_VF6__ADDRESS_MASK                                                           0x0007FFFCL
+//SECOND_HDP_MEM_FLUSH_CNTL_VF7
+#define SECOND_HDP_MEM_FLUSH_CNTL_VF7__ADDRESS__SHIFT                                                         0x2
+#define SECOND_HDP_MEM_FLUSH_CNTL_VF7__ADDRESS_MASK                                                           0x0007FFFCL
+//SECOND_HDP_REG_FLUSH_CNTL_PF
+#define SECOND_HDP_REG_FLUSH_CNTL_PF__ADDRESS__SHIFT                                                          0x2
+#define SECOND_HDP_REG_FLUSH_CNTL_PF__ADDRESS_MASK                                                            0x0007FFFCL
+//SECOND_HDP_REG_FLUSH_CNTL_VF0
+#define SECOND_HDP_REG_FLUSH_CNTL_VF0__ADDRESS__SHIFT                                                         0x2
+#define SECOND_HDP_REG_FLUSH_CNTL_VF0__ADDRESS_MASK                                                           0x0007FFFCL
+//SECOND_HDP_REG_FLUSH_CNTL_VF1
+#define SECOND_HDP_REG_FLUSH_CNTL_VF1__ADDRESS__SHIFT                                                         0x2
+#define SECOND_HDP_REG_FLUSH_CNTL_VF1__ADDRESS_MASK                                                           0x0007FFFCL
+//SECOND_HDP_REG_FLUSH_CNTL_VF2
+#define SECOND_HDP_REG_FLUSH_CNTL_VF2__ADDRESS__SHIFT                                                         0x2
+#define SECOND_HDP_REG_FLUSH_CNTL_VF2__ADDRESS_MASK                                                           0x0007FFFCL
+//SECOND_HDP_REG_FLUSH_CNTL_VF3
+#define SECOND_HDP_REG_FLUSH_CNTL_VF3__ADDRESS__SHIFT                                                         0x2
+#define SECOND_HDP_REG_FLUSH_CNTL_VF3__ADDRESS_MASK                                                           0x0007FFFCL
+//SECOND_HDP_REG_FLUSH_CNTL_VF4
+#define SECOND_HDP_REG_FLUSH_CNTL_VF4__ADDRESS__SHIFT                                                         0x2
+#define SECOND_HDP_REG_FLUSH_CNTL_VF4__ADDRESS_MASK                                                           0x0007FFFCL
+//SECOND_HDP_REG_FLUSH_CNTL_VF5
+#define SECOND_HDP_REG_FLUSH_CNTL_VF5__ADDRESS__SHIFT                                                         0x2
+#define SECOND_HDP_REG_FLUSH_CNTL_VF5__ADDRESS_MASK                                                           0x0007FFFCL
+//SECOND_HDP_REG_FLUSH_CNTL_VF6
+#define SECOND_HDP_REG_FLUSH_CNTL_VF6__ADDRESS__SHIFT                                                         0x2
+#define SECOND_HDP_REG_FLUSH_CNTL_VF6__ADDRESS_MASK                                                           0x0007FFFCL
+//SECOND_HDP_REG_FLUSH_CNTL_VF7
+#define SECOND_HDP_REG_FLUSH_CNTL_VF7__ADDRESS__SHIFT                                                         0x2
+#define SECOND_HDP_REG_FLUSH_CNTL_VF7__ADDRESS_MASK                                                           0x0007FFFCL
+//GPU_HDP_FLUSH_GFX_FW
+#define GPU_HDP_FLUSH_GFX_FW__CLEAR_ALL_VF_FLUSH_DONE__SHIFT                                                  0x0
+#define GPU_HDP_FLUSH_GFX_FW__CLEAR_ALL_VF_FLUSH_DONE_MASK                                                    0x00000001L
+//NBIF_RRMT_CNTL
+#define NBIF_RRMT_CNTL__PARTITION_MODE__SHIFT                                                                 0x0
+#define NBIF_RRMT_CNTL__AID_DIE_ID__SHIFT                                                                     0x4
+#define NBIF_RRMT_CNTL__RRMT_ENABLE__SHIFT                                                                    0x8
+#define NBIF_RRMT_CNTL__RRMT_Invalid_Address_H__SHIFT                                                         0x10
+#define NBIF_RRMT_CNTL__PARTITION_MODE_MASK                                                                   0x00000007L
+#define NBIF_RRMT_CNTL__AID_DIE_ID_MASK                                                                       0x00000030L
+#define NBIF_RRMT_CNTL__RRMT_ENABLE_MASK                                                                      0x00000100L
+#define NBIF_RRMT_CNTL__RRMT_Invalid_Address_H_MASK                                                           0xFFFF0000L
+//RRMT_NBIF_MISC_REG1
+#define RRMT_NBIF_MISC_REG1__RRMT_Invalid_Address_L__SHIFT                                                    0x0
+#define RRMT_NBIF_MISC_REG1__RRMT_Invalid_Address_L_MASK                                                      0xFFFFFFFFL
+//RRMT_LUT_INDEX
+#define RRMT_LUT_INDEX__RRMT_LUT_INDEX__SHIFT                                                                 0x0
+#define RRMT_LUT_INDEX__RRMT_LUT_INDEX_MASK                                                                   0x000003FFL
+//RRMT_LUT_DATA
+#define RRMT_LUT_DATA__RRMT_LUT_DATA__SHIFT                                                                   0x0
+#define RRMT_LUT_DATA__RRMT_LUT_DATA_MASK                                                                     0xFFFFFFFFL
+
+
+// addressBlock: nbif0_nbif0_bif_misc_pfvf_dev0_epf0_bif_misc_pfvf_regblk
+//BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF0__SHIFT                               0x0
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF1__SHIFT                               0x1
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF2__SHIFT                               0x2
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF3__SHIFT                               0x3
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF4__SHIFT                               0x4
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF5__SHIFT                               0x5
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF6__SHIFT                               0x6
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF7__SHIFT                               0x7
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF8__SHIFT                               0x8
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF9__SHIFT                               0x9
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF10__SHIFT                              0xa
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF11__SHIFT                              0xb
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF12__SHIFT                              0xc
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF13__SHIFT                              0xd
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF14__SHIFT                              0xe
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF15__SHIFT                              0xf
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF16__SHIFT                              0x10
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF17__SHIFT                              0x11
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF18__SHIFT                              0x12
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF19__SHIFT                              0x13
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF20__SHIFT                              0x14
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF21__SHIFT                              0x15
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF22__SHIFT                              0x16
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF23__SHIFT                              0x17
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF24__SHIFT                              0x18
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF25__SHIFT                              0x19
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF26__SHIFT                              0x1a
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF27__SHIFT                              0x1b
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF28__SHIFT                              0x1c
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF29__SHIFT                              0x1d
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF30__SHIFT                              0x1e
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF31__SHIFT                              0x1f
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF0_MASK                                 0x00000001L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF1_MASK                                 0x00000002L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF2_MASK                                 0x00000004L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF3_MASK                                 0x00000008L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF4_MASK                                 0x00000010L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF5_MASK                                 0x00000020L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF6_MASK                                 0x00000040L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF7_MASK                                 0x00000080L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF8_MASK                                 0x00000100L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF9_MASK                                 0x00000200L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF10_MASK                                0x00000400L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF11_MASK                                0x00000800L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF12_MASK                                0x00001000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF13_MASK                                0x00002000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF14_MASK                                0x00004000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF15_MASK                                0x00008000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF16_MASK                                0x00010000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF17_MASK                                0x00020000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF18_MASK                                0x00040000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF19_MASK                                0x00080000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF20_MASK                                0x00100000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF21_MASK                                0x00200000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF22_MASK                                0x00400000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF23_MASK                                0x00800000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF24_MASK                                0x01000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF25_MASK                                0x02000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF26_MASK                                0x04000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF27_MASK                                0x08000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF28_MASK                                0x10000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF29_MASK                                0x20000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF30_MASK                                0x40000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF31_MASK                                0x80000000L
+//BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF32__SHIFT                              0x0
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF33__SHIFT                              0x1
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF34__SHIFT                              0x2
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF35__SHIFT                              0x3
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF36__SHIFT                              0x4
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF37__SHIFT                              0x5
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF38__SHIFT                              0x6
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF39__SHIFT                              0x7
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF40__SHIFT                              0x8
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF41__SHIFT                              0x9
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF42__SHIFT                              0xa
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF43__SHIFT                              0xb
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF44__SHIFT                              0xc
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF45__SHIFT                              0xd
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF46__SHIFT                              0xe
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF47__SHIFT                              0xf
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF48__SHIFT                              0x10
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF49__SHIFT                              0x11
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF50__SHIFT                              0x12
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF51__SHIFT                              0x13
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF52__SHIFT                              0x14
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF53__SHIFT                              0x15
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF54__SHIFT                              0x16
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF55__SHIFT                              0x17
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF56__SHIFT                              0x18
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF57__SHIFT                              0x19
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF58__SHIFT                              0x1a
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF59__SHIFT                              0x1b
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF60__SHIFT                              0x1c
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF61__SHIFT                              0x1d
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF62__SHIFT                              0x1e
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF63__SHIFT                              0x1f
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF32_MASK                                0x00000001L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF33_MASK                                0x00000002L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF34_MASK                                0x00000004L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF35_MASK                                0x00000008L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF36_MASK                                0x00000010L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF37_MASK                                0x00000020L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF38_MASK                                0x00000040L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF39_MASK                                0x00000080L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF40_MASK                                0x00000100L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF41_MASK                                0x00000200L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF42_MASK                                0x00000400L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF43_MASK                                0x00000800L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF44_MASK                                0x00001000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF45_MASK                                0x00002000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF46_MASK                                0x00004000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF47_MASK                                0x00008000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF48_MASK                                0x00010000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF49_MASK                                0x00020000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF50_MASK                                0x00040000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF51_MASK                                0x00080000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF52_MASK                                0x00100000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF53_MASK                                0x00200000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF54_MASK                                0x00400000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF55_MASK                                0x00800000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF56_MASK                                0x01000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF57_MASK                                0x02000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF58_MASK                                0x04000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF59_MASK                                0x08000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF60_MASK                                0x10000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF61_MASK                                0x20000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF62_MASK                                0x40000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF63_MASK                                0x80000000L
+//BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF64__SHIFT                              0x0
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF65__SHIFT                              0x1
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF66__SHIFT                              0x2
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF67__SHIFT                              0x3
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF68__SHIFT                              0x4
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF69__SHIFT                              0x5
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF70__SHIFT                              0x6
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF71__SHIFT                              0x7
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF72__SHIFT                              0x8
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF73__SHIFT                              0x9
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF74__SHIFT                              0xa
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF75__SHIFT                              0xb
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF76__SHIFT                              0xc
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF77__SHIFT                              0xd
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF78__SHIFT                              0xe
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF79__SHIFT                              0xf
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF80__SHIFT                              0x10
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF81__SHIFT                              0x11
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF82__SHIFT                              0x12
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF83__SHIFT                              0x13
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF84__SHIFT                              0x14
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF85__SHIFT                              0x15
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF86__SHIFT                              0x16
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF87__SHIFT                              0x17
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF88__SHIFT                              0x18
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF89__SHIFT                              0x19
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF90__SHIFT                              0x1a
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF91__SHIFT                              0x1b
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF92__SHIFT                              0x1c
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF93__SHIFT                              0x1d
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF94__SHIFT                              0x1e
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF95__SHIFT                              0x1f
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF64_MASK                                0x00000001L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF65_MASK                                0x00000002L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF66_MASK                                0x00000004L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF67_MASK                                0x00000008L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF68_MASK                                0x00000010L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF69_MASK                                0x00000020L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF70_MASK                                0x00000040L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF71_MASK                                0x00000080L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF72_MASK                                0x00000100L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF73_MASK                                0x00000200L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF74_MASK                                0x00000400L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF75_MASK                                0x00000800L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF76_MASK                                0x00001000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF77_MASK                                0x00002000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF78_MASK                                0x00004000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF79_MASK                                0x00008000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF80_MASK                                0x00010000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF81_MASK                                0x00020000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF82_MASK                                0x00040000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF83_MASK                                0x00080000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF84_MASK                                0x00100000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF85_MASK                                0x00200000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF86_MASK                                0x00400000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF87_MASK                                0x00800000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF88_MASK                                0x01000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF89_MASK                                0x02000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF90_MASK                                0x04000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF91_MASK                                0x08000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF92_MASK                                0x10000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF93_MASK                                0x20000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF94_MASK                                0x40000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF95_MASK                                0x80000000L
+//BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF96__SHIFT                              0x0
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF97__SHIFT                              0x1
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF98__SHIFT                              0x2
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF99__SHIFT                              0x3
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF100__SHIFT                             0x4
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF101__SHIFT                             0x5
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF102__SHIFT                             0x6
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF103__SHIFT                             0x7
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF104__SHIFT                             0x8
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF105__SHIFT                             0x9
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF106__SHIFT                             0xa
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF107__SHIFT                             0xb
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF108__SHIFT                             0xc
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF109__SHIFT                             0xd
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF110__SHIFT                             0xe
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF111__SHIFT                             0xf
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF112__SHIFT                             0x10
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF113__SHIFT                             0x11
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF114__SHIFT                             0x12
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF115__SHIFT                             0x13
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF116__SHIFT                             0x14
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF117__SHIFT                             0x15
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF118__SHIFT                             0x16
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF119__SHIFT                             0x17
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF120__SHIFT                             0x18
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF121__SHIFT                             0x19
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF122__SHIFT                             0x1a
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF123__SHIFT                             0x1b
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF124__SHIFT                             0x1c
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF125__SHIFT                             0x1d
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF126__SHIFT                             0x1e
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF127__SHIFT                             0x1f
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF96_MASK                                0x00000001L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF97_MASK                                0x00000002L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF98_MASK                                0x00000004L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF99_MASK                                0x00000008L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF100_MASK                               0x00000010L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF101_MASK                               0x00000020L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF102_MASK                               0x00000040L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF103_MASK                               0x00000080L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF104_MASK                               0x00000100L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF105_MASK                               0x00000200L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF106_MASK                               0x00000400L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF107_MASK                               0x00000800L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF108_MASK                               0x00001000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF109_MASK                               0x00002000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF110_MASK                               0x00004000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF111_MASK                               0x00008000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF112_MASK                               0x00010000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF113_MASK                               0x00020000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF114_MASK                               0x00040000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF115_MASK                               0x00080000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF116_MASK                               0x00100000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF117_MASK                               0x00200000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF118_MASK                               0x00400000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF119_MASK                               0x00800000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF120_MASK                               0x01000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF121_MASK                               0x02000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF122_MASK                               0x04000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF123_MASK                               0x08000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF124_MASK                               0x10000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF125_MASK                               0x20000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF126_MASK                               0x40000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF127_MASK                               0x80000000L
+//BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF0__SHIFT                         0x0
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF1__SHIFT                         0x1
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF2__SHIFT                         0x2
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF3__SHIFT                         0x3
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF4__SHIFT                         0x4
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF5__SHIFT                         0x5
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF6__SHIFT                         0x6
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF7__SHIFT                         0x7
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF8__SHIFT                         0x8
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF9__SHIFT                         0x9
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF10__SHIFT                        0xa
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF11__SHIFT                        0xb
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF12__SHIFT                        0xc
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF13__SHIFT                        0xd
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF14__SHIFT                        0xe
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF15__SHIFT                        0xf
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF16__SHIFT                        0x10
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF17__SHIFT                        0x11
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF18__SHIFT                        0x12
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF19__SHIFT                        0x13
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF20__SHIFT                        0x14
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF21__SHIFT                        0x15
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF22__SHIFT                        0x16
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF23__SHIFT                        0x17
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF24__SHIFT                        0x18
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF25__SHIFT                        0x19
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF26__SHIFT                        0x1a
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF27__SHIFT                        0x1b
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF28__SHIFT                        0x1c
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF29__SHIFT                        0x1d
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF30__SHIFT                        0x1e
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF31__SHIFT                        0x1f
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF0_MASK                           0x00000001L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF1_MASK                           0x00000002L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF2_MASK                           0x00000004L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF3_MASK                           0x00000008L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF4_MASK                           0x00000010L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF5_MASK                           0x00000020L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF6_MASK                           0x00000040L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF7_MASK                           0x00000080L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF8_MASK                           0x00000100L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF9_MASK                           0x00000200L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF10_MASK                          0x00000400L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF11_MASK                          0x00000800L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF12_MASK                          0x00001000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF13_MASK                          0x00002000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF14_MASK                          0x00004000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF15_MASK                          0x00008000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF16_MASK                          0x00010000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF17_MASK                          0x00020000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF18_MASK                          0x00040000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF19_MASK                          0x00080000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF20_MASK                          0x00100000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF21_MASK                          0x00200000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF22_MASK                          0x00400000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF23_MASK                          0x00800000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF24_MASK                          0x01000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF25_MASK                          0x02000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF26_MASK                          0x04000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF27_MASK                          0x08000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF28_MASK                          0x10000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF29_MASK                          0x20000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF30_MASK                          0x40000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF31_MASK                          0x80000000L
+//BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF32__SHIFT                        0x0
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF33__SHIFT                        0x1
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF34__SHIFT                        0x2
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF35__SHIFT                        0x3
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF36__SHIFT                        0x4
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF37__SHIFT                        0x5
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF38__SHIFT                        0x6
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF39__SHIFT                        0x7
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF40__SHIFT                        0x8
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF41__SHIFT                        0x9
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF42__SHIFT                        0xa
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF43__SHIFT                        0xb
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF44__SHIFT                        0xc
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF45__SHIFT                        0xd
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF46__SHIFT                        0xe
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF47__SHIFT                        0xf
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF48__SHIFT                        0x10
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF49__SHIFT                        0x11
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF50__SHIFT                        0x12
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF51__SHIFT                        0x13
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF52__SHIFT                        0x14
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF53__SHIFT                        0x15
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF54__SHIFT                        0x16
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF55__SHIFT                        0x17
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF56__SHIFT                        0x18
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF57__SHIFT                        0x19
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF58__SHIFT                        0x1a
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF59__SHIFT                        0x1b
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF60__SHIFT                        0x1c
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF61__SHIFT                        0x1d
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF62__SHIFT                        0x1e
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF63__SHIFT                        0x1f
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF32_MASK                          0x00000001L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF33_MASK                          0x00000002L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF34_MASK                          0x00000004L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF35_MASK                          0x00000008L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF36_MASK                          0x00000010L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF37_MASK                          0x00000020L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF38_MASK                          0x00000040L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF39_MASK                          0x00000080L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF40_MASK                          0x00000100L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF41_MASK                          0x00000200L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF42_MASK                          0x00000400L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF43_MASK                          0x00000800L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF44_MASK                          0x00001000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF45_MASK                          0x00002000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF46_MASK                          0x00004000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF47_MASK                          0x00008000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF48_MASK                          0x00010000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF49_MASK                          0x00020000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF50_MASK                          0x00040000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF51_MASK                          0x00080000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF52_MASK                          0x00100000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF53_MASK                          0x00200000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF54_MASK                          0x00400000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF55_MASK                          0x00800000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF56_MASK                          0x01000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF57_MASK                          0x02000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF58_MASK                          0x04000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF59_MASK                          0x08000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF60_MASK                          0x10000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF61_MASK                          0x20000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF62_MASK                          0x40000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF63_MASK                          0x80000000L
+//BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF64__SHIFT                        0x0
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF65__SHIFT                        0x1
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF66__SHIFT                        0x2
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF67__SHIFT                        0x3
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF68__SHIFT                        0x4
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF69__SHIFT                        0x5
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF70__SHIFT                        0x6
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF71__SHIFT                        0x7
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF72__SHIFT                        0x8
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF73__SHIFT                        0x9
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF74__SHIFT                        0xa
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF75__SHIFT                        0xb
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF76__SHIFT                        0xc
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF77__SHIFT                        0xd
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF78__SHIFT                        0xe
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF79__SHIFT                        0xf
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF80__SHIFT                        0x10
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF81__SHIFT                        0x11
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF82__SHIFT                        0x12
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF83__SHIFT                        0x13
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF84__SHIFT                        0x14
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF85__SHIFT                        0x15
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF86__SHIFT                        0x16
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF87__SHIFT                        0x17
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF88__SHIFT                        0x18
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF89__SHIFT                        0x19
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF90__SHIFT                        0x1a
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF91__SHIFT                        0x1b
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF92__SHIFT                        0x1c
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF93__SHIFT                        0x1d
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF94__SHIFT                        0x1e
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF95__SHIFT                        0x1f
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF64_MASK                          0x00000001L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF65_MASK                          0x00000002L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF66_MASK                          0x00000004L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF67_MASK                          0x00000008L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF68_MASK                          0x00000010L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF69_MASK                          0x00000020L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF70_MASK                          0x00000040L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF71_MASK                          0x00000080L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF72_MASK                          0x00000100L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF73_MASK                          0x00000200L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF74_MASK                          0x00000400L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF75_MASK                          0x00000800L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF76_MASK                          0x00001000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF77_MASK                          0x00002000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF78_MASK                          0x00004000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF79_MASK                          0x00008000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF80_MASK                          0x00010000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF81_MASK                          0x00020000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF82_MASK                          0x00040000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF83_MASK                          0x00080000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF84_MASK                          0x00100000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF85_MASK                          0x00200000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF86_MASK                          0x00400000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF87_MASK                          0x00800000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF88_MASK                          0x01000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF89_MASK                          0x02000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF90_MASK                          0x04000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF91_MASK                          0x08000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF92_MASK                          0x10000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF93_MASK                          0x20000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF94_MASK                          0x40000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF95_MASK                          0x80000000L
+//BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF96__SHIFT                        0x0
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF97__SHIFT                        0x1
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF98__SHIFT                        0x2
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF99__SHIFT                        0x3
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF100__SHIFT                       0x4
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF101__SHIFT                       0x5
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF102__SHIFT                       0x6
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF103__SHIFT                       0x7
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF104__SHIFT                       0x8
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF105__SHIFT                       0x9
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF106__SHIFT                       0xa
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF107__SHIFT                       0xb
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF108__SHIFT                       0xc
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF109__SHIFT                       0xd
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF110__SHIFT                       0xe
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF111__SHIFT                       0xf
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF112__SHIFT                       0x10
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF113__SHIFT                       0x11
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF114__SHIFT                       0x12
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF115__SHIFT                       0x13
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF116__SHIFT                       0x14
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF117__SHIFT                       0x15
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF118__SHIFT                       0x16
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF119__SHIFT                       0x17
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF120__SHIFT                       0x18
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF121__SHIFT                       0x19
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF122__SHIFT                       0x1a
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF123__SHIFT                       0x1b
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF124__SHIFT                       0x1c
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF125__SHIFT                       0x1d
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF126__SHIFT                       0x1e
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF127__SHIFT                       0x1f
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF96_MASK                          0x00000001L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF97_MASK                          0x00000002L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF98_MASK                          0x00000004L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF99_MASK                          0x00000008L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF100_MASK                         0x00000010L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF101_MASK                         0x00000020L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF102_MASK                         0x00000040L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF103_MASK                         0x00000080L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF104_MASK                         0x00000100L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF105_MASK                         0x00000200L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF106_MASK                         0x00000400L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF107_MASK                         0x00000800L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF108_MASK                         0x00001000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF109_MASK                         0x00002000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF110_MASK                         0x00004000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF111_MASK                         0x00008000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF112_MASK                         0x00010000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF113_MASK                         0x00020000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF114_MASK                         0x00040000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF115_MASK                         0x00080000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF116_MASK                         0x00100000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF117_MASK                         0x00200000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF118_MASK                         0x00400000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF119_MASK                         0x00800000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF120_MASK                         0x01000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF121_MASK                         0x02000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF122_MASK                         0x04000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF123_MASK                         0x08000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF124_MASK                         0x10000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF125_MASK                         0x20000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF126_MASK                         0x40000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF127_MASK                         0x80000000L
+//BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF0__SHIFT                   0x0
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF1__SHIFT                   0x1
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF2__SHIFT                   0x2
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF3__SHIFT                   0x3
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF4__SHIFT                   0x4
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF5__SHIFT                   0x5
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF6__SHIFT                   0x6
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF7__SHIFT                   0x7
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF8__SHIFT                   0x8
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF9__SHIFT                   0x9
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF10__SHIFT                  0xa
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF11__SHIFT                  0xb
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF12__SHIFT                  0xc
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF13__SHIFT                  0xd
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF14__SHIFT                  0xe
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF15__SHIFT                  0xf
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF16__SHIFT                  0x10
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF17__SHIFT                  0x11
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF18__SHIFT                  0x12
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF19__SHIFT                  0x13
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF20__SHIFT                  0x14
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF21__SHIFT                  0x15
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF22__SHIFT                  0x16
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF23__SHIFT                  0x17
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF24__SHIFT                  0x18
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF25__SHIFT                  0x19
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF26__SHIFT                  0x1a
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF27__SHIFT                  0x1b
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF28__SHIFT                  0x1c
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF29__SHIFT                  0x1d
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF30__SHIFT                  0x1e
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF31__SHIFT                  0x1f
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF0_MASK                     0x00000001L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF1_MASK                     0x00000002L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF2_MASK                     0x00000004L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF3_MASK                     0x00000008L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF4_MASK                     0x00000010L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF5_MASK                     0x00000020L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF6_MASK                     0x00000040L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF7_MASK                     0x00000080L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF8_MASK                     0x00000100L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF9_MASK                     0x00000200L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF10_MASK                    0x00000400L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF11_MASK                    0x00000800L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF12_MASK                    0x00001000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF13_MASK                    0x00002000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF14_MASK                    0x00004000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF15_MASK                    0x00008000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF16_MASK                    0x00010000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF17_MASK                    0x00020000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF18_MASK                    0x00040000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF19_MASK                    0x00080000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF20_MASK                    0x00100000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF21_MASK                    0x00200000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF22_MASK                    0x00400000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF23_MASK                    0x00800000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF24_MASK                    0x01000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF25_MASK                    0x02000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF26_MASK                    0x04000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF27_MASK                    0x08000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF28_MASK                    0x10000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF29_MASK                    0x20000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF30_MASK                    0x40000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF31_MASK                    0x80000000L
+//BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF32__SHIFT                  0x0
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF33__SHIFT                  0x1
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF34__SHIFT                  0x2
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF35__SHIFT                  0x3
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF36__SHIFT                  0x4
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF37__SHIFT                  0x5
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF38__SHIFT                  0x6
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF39__SHIFT                  0x7
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF40__SHIFT                  0x8
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF41__SHIFT                  0x9
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF42__SHIFT                  0xa
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF43__SHIFT                  0xb
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF44__SHIFT                  0xc
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF45__SHIFT                  0xd
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF46__SHIFT                  0xe
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF47__SHIFT                  0xf
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF48__SHIFT                  0x10
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF49__SHIFT                  0x11
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF50__SHIFT                  0x12
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF51__SHIFT                  0x13
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF52__SHIFT                  0x14
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF53__SHIFT                  0x15
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF54__SHIFT                  0x16
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF55__SHIFT                  0x17
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF56__SHIFT                  0x18
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF57__SHIFT                  0x19
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF58__SHIFT                  0x1a
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF59__SHIFT                  0x1b
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF60__SHIFT                  0x1c
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF61__SHIFT                  0x1d
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF62__SHIFT                  0x1e
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF63__SHIFT                  0x1f
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF32_MASK                    0x00000001L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF33_MASK                    0x00000002L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF34_MASK                    0x00000004L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF35_MASK                    0x00000008L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF36_MASK                    0x00000010L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF37_MASK                    0x00000020L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF38_MASK                    0x00000040L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF39_MASK                    0x00000080L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF40_MASK                    0x00000100L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF41_MASK                    0x00000200L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF42_MASK                    0x00000400L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF43_MASK                    0x00000800L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF44_MASK                    0x00001000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF45_MASK                    0x00002000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF46_MASK                    0x00004000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF47_MASK                    0x00008000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF48_MASK                    0x00010000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF49_MASK                    0x00020000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF50_MASK                    0x00040000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF51_MASK                    0x00080000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF52_MASK                    0x00100000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF53_MASK                    0x00200000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF54_MASK                    0x00400000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF55_MASK                    0x00800000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF56_MASK                    0x01000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF57_MASK                    0x02000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF58_MASK                    0x04000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF59_MASK                    0x08000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF60_MASK                    0x10000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF61_MASK                    0x20000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF62_MASK                    0x40000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF63_MASK                    0x80000000L
+//BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF64__SHIFT                  0x0
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF65__SHIFT                  0x1
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF66__SHIFT                  0x2
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF67__SHIFT                  0x3
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF68__SHIFT                  0x4
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF69__SHIFT                  0x5
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF70__SHIFT                  0x6
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF71__SHIFT                  0x7
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF72__SHIFT                  0x8
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF73__SHIFT                  0x9
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF74__SHIFT                  0xa
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF75__SHIFT                  0xb
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF76__SHIFT                  0xc
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF77__SHIFT                  0xd
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF78__SHIFT                  0xe
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF79__SHIFT                  0xf
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF80__SHIFT                  0x10
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF81__SHIFT                  0x11
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF82__SHIFT                  0x12
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF83__SHIFT                  0x13
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF84__SHIFT                  0x14
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF85__SHIFT                  0x15
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF86__SHIFT                  0x16
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF87__SHIFT                  0x17
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF88__SHIFT                  0x18
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF89__SHIFT                  0x19
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF90__SHIFT                  0x1a
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF91__SHIFT                  0x1b
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF92__SHIFT                  0x1c
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF93__SHIFT                  0x1d
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF94__SHIFT                  0x1e
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF95__SHIFT                  0x1f
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF64_MASK                    0x00000001L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF65_MASK                    0x00000002L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF66_MASK                    0x00000004L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF67_MASK                    0x00000008L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF68_MASK                    0x00000010L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF69_MASK                    0x00000020L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF70_MASK                    0x00000040L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF71_MASK                    0x00000080L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF72_MASK                    0x00000100L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF73_MASK                    0x00000200L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF74_MASK                    0x00000400L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF75_MASK                    0x00000800L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF76_MASK                    0x00001000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF77_MASK                    0x00002000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF78_MASK                    0x00004000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF79_MASK                    0x00008000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF80_MASK                    0x00010000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF81_MASK                    0x00020000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF82_MASK                    0x00040000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF83_MASK                    0x00080000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF84_MASK                    0x00100000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF85_MASK                    0x00200000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF86_MASK                    0x00400000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF87_MASK                    0x00800000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF88_MASK                    0x01000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF89_MASK                    0x02000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF90_MASK                    0x04000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF91_MASK                    0x08000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF92_MASK                    0x10000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF93_MASK                    0x20000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF94_MASK                    0x40000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF95_MASK                    0x80000000L
+//BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF96__SHIFT                  0x0
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF97__SHIFT                  0x1
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF98__SHIFT                  0x2
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF99__SHIFT                  0x3
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF100__SHIFT                 0x4
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF101__SHIFT                 0x5
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF102__SHIFT                 0x6
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF103__SHIFT                 0x7
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF104__SHIFT                 0x8
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF105__SHIFT                 0x9
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF106__SHIFT                 0xa
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF107__SHIFT                 0xb
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF108__SHIFT                 0xc
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF109__SHIFT                 0xd
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF110__SHIFT                 0xe
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF111__SHIFT                 0xf
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF112__SHIFT                 0x10
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF113__SHIFT                 0x11
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF114__SHIFT                 0x12
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF115__SHIFT                 0x13
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF116__SHIFT                 0x14
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF117__SHIFT                 0x15
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF118__SHIFT                 0x16
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF119__SHIFT                 0x17
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF120__SHIFT                 0x18
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF121__SHIFT                 0x19
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF122__SHIFT                 0x1a
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF123__SHIFT                 0x1b
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF124__SHIFT                 0x1c
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF125__SHIFT                 0x1d
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF126__SHIFT                 0x1e
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF127__SHIFT                 0x1f
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF96_MASK                    0x00000001L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF97_MASK                    0x00000002L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF98_MASK                    0x00000004L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF99_MASK                    0x00000008L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF100_MASK                   0x00000010L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF101_MASK                   0x00000020L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF102_MASK                   0x00000040L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF103_MASK                   0x00000080L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF104_MASK                   0x00000100L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF105_MASK                   0x00000200L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF106_MASK                   0x00000400L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF107_MASK                   0x00000800L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF108_MASK                   0x00001000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF109_MASK                   0x00002000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF110_MASK                   0x00004000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF111_MASK                   0x00008000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF112_MASK                   0x00010000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF113_MASK                   0x00020000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF114_MASK                   0x00040000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF115_MASK                   0x00080000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF116_MASK                   0x00100000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF117_MASK                   0x00200000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF118_MASK                   0x00400000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF119_MASK                   0x00800000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF120_MASK                   0x01000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF121_MASK                   0x02000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF122_MASK                   0x04000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF123_MASK                   0x08000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF124_MASK                   0x10000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF125_MASK                   0x20000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF126_MASK                   0x40000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF127_MASK                   0x80000000L
+//BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF0__SHIFT                         0x0
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF1__SHIFT                         0x1
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF2__SHIFT                         0x2
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF3__SHIFT                         0x3
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF4__SHIFT                         0x4
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF5__SHIFT                         0x5
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF6__SHIFT                         0x6
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF7__SHIFT                         0x7
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF8__SHIFT                         0x8
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF9__SHIFT                         0x9
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF10__SHIFT                        0xa
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF11__SHIFT                        0xb
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF12__SHIFT                        0xc
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF13__SHIFT                        0xd
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF14__SHIFT                        0xe
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF15__SHIFT                        0xf
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF16__SHIFT                        0x10
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF17__SHIFT                        0x11
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF18__SHIFT                        0x12
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF19__SHIFT                        0x13
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF20__SHIFT                        0x14
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF21__SHIFT                        0x15
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF22__SHIFT                        0x16
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF23__SHIFT                        0x17
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF24__SHIFT                        0x18
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF25__SHIFT                        0x19
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF26__SHIFT                        0x1a
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF27__SHIFT                        0x1b
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF28__SHIFT                        0x1c
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF29__SHIFT                        0x1d
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF30__SHIFT                        0x1e
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF31__SHIFT                        0x1f
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF0_MASK                           0x00000001L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF1_MASK                           0x00000002L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF2_MASK                           0x00000004L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF3_MASK                           0x00000008L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF4_MASK                           0x00000010L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF5_MASK                           0x00000020L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF6_MASK                           0x00000040L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF7_MASK                           0x00000080L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF8_MASK                           0x00000100L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF9_MASK                           0x00000200L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF10_MASK                          0x00000400L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF11_MASK                          0x00000800L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF12_MASK                          0x00001000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF13_MASK                          0x00002000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF14_MASK                          0x00004000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF15_MASK                          0x00008000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF16_MASK                          0x00010000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF17_MASK                          0x00020000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF18_MASK                          0x00040000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF19_MASK                          0x00080000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF20_MASK                          0x00100000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF21_MASK                          0x00200000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF22_MASK                          0x00400000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF23_MASK                          0x00800000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF24_MASK                          0x01000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF25_MASK                          0x02000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF26_MASK                          0x04000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF27_MASK                          0x08000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF28_MASK                          0x10000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF29_MASK                          0x20000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF30_MASK                          0x40000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF31_MASK                          0x80000000L
+//BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF32__SHIFT                        0x0
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF33__SHIFT                        0x1
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF34__SHIFT                        0x2
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF35__SHIFT                        0x3
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF36__SHIFT                        0x4
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF37__SHIFT                        0x5
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF38__SHIFT                        0x6
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF39__SHIFT                        0x7
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF40__SHIFT                        0x8
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF41__SHIFT                        0x9
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF42__SHIFT                        0xa
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF43__SHIFT                        0xb
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF44__SHIFT                        0xc
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF45__SHIFT                        0xd
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF46__SHIFT                        0xe
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF47__SHIFT                        0xf
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF48__SHIFT                        0x10
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF49__SHIFT                        0x11
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF50__SHIFT                        0x12
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF51__SHIFT                        0x13
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF52__SHIFT                        0x14
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF53__SHIFT                        0x15
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF54__SHIFT                        0x16
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF55__SHIFT                        0x17
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF56__SHIFT                        0x18
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF57__SHIFT                        0x19
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF58__SHIFT                        0x1a
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF59__SHIFT                        0x1b
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF60__SHIFT                        0x1c
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF61__SHIFT                        0x1d
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF62__SHIFT                        0x1e
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF63__SHIFT                        0x1f
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF32_MASK                          0x00000001L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF33_MASK                          0x00000002L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF34_MASK                          0x00000004L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF35_MASK                          0x00000008L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF36_MASK                          0x00000010L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF37_MASK                          0x00000020L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF38_MASK                          0x00000040L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF39_MASK                          0x00000080L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF40_MASK                          0x00000100L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF41_MASK                          0x00000200L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF42_MASK                          0x00000400L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF43_MASK                          0x00000800L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF44_MASK                          0x00001000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF45_MASK                          0x00002000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF46_MASK                          0x00004000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF47_MASK                          0x00008000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF48_MASK                          0x00010000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF49_MASK                          0x00020000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF50_MASK                          0x00040000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF51_MASK                          0x00080000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF52_MASK                          0x00100000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF53_MASK                          0x00200000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF54_MASK                          0x00400000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF55_MASK                          0x00800000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF56_MASK                          0x01000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF57_MASK                          0x02000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF58_MASK                          0x04000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF59_MASK                          0x08000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF60_MASK                          0x10000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF61_MASK                          0x20000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF62_MASK                          0x40000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF63_MASK                          0x80000000L
+//BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF64__SHIFT                        0x0
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF65__SHIFT                        0x1
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF66__SHIFT                        0x2
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF67__SHIFT                        0x3
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF68__SHIFT                        0x4
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF69__SHIFT                        0x5
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF70__SHIFT                        0x6
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF71__SHIFT                        0x7
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF72__SHIFT                        0x8
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF73__SHIFT                        0x9
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF74__SHIFT                        0xa
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF75__SHIFT                        0xb
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF76__SHIFT                        0xc
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF77__SHIFT                        0xd
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF78__SHIFT                        0xe
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF79__SHIFT                        0xf
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF80__SHIFT                        0x10
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF81__SHIFT                        0x11
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF82__SHIFT                        0x12
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF83__SHIFT                        0x13
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF84__SHIFT                        0x14
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF85__SHIFT                        0x15
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF86__SHIFT                        0x16
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF87__SHIFT                        0x17
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF88__SHIFT                        0x18
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF89__SHIFT                        0x19
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF90__SHIFT                        0x1a
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF91__SHIFT                        0x1b
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF92__SHIFT                        0x1c
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF93__SHIFT                        0x1d
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF94__SHIFT                        0x1e
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF95__SHIFT                        0x1f
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF64_MASK                          0x00000001L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF65_MASK                          0x00000002L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF66_MASK                          0x00000004L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF67_MASK                          0x00000008L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF68_MASK                          0x00000010L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF69_MASK                          0x00000020L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF70_MASK                          0x00000040L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF71_MASK                          0x00000080L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF72_MASK                          0x00000100L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF73_MASK                          0x00000200L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF74_MASK                          0x00000400L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF75_MASK                          0x00000800L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF76_MASK                          0x00001000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF77_MASK                          0x00002000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF78_MASK                          0x00004000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF79_MASK                          0x00008000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF80_MASK                          0x00010000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF81_MASK                          0x00020000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF82_MASK                          0x00040000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF83_MASK                          0x00080000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF84_MASK                          0x00100000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF85_MASK                          0x00200000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF86_MASK                          0x00400000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF87_MASK                          0x00800000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF88_MASK                          0x01000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF89_MASK                          0x02000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF90_MASK                          0x04000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF91_MASK                          0x08000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF92_MASK                          0x10000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF93_MASK                          0x20000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF94_MASK                          0x40000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF95_MASK                          0x80000000L
+//BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF96__SHIFT                        0x0
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF97__SHIFT                        0x1
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF98__SHIFT                        0x2
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF99__SHIFT                        0x3
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF100__SHIFT                       0x4
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF101__SHIFT                       0x5
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF102__SHIFT                       0x6
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF103__SHIFT                       0x7
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF104__SHIFT                       0x8
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF105__SHIFT                       0x9
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF106__SHIFT                       0xa
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF107__SHIFT                       0xb
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF108__SHIFT                       0xc
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF109__SHIFT                       0xd
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF110__SHIFT                       0xe
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF111__SHIFT                       0xf
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF112__SHIFT                       0x10
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF113__SHIFT                       0x11
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF114__SHIFT                       0x12
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF115__SHIFT                       0x13
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF116__SHIFT                       0x14
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF117__SHIFT                       0x15
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF118__SHIFT                       0x16
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF119__SHIFT                       0x17
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF120__SHIFT                       0x18
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF121__SHIFT                       0x19
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF122__SHIFT                       0x1a
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF123__SHIFT                       0x1b
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF124__SHIFT                       0x1c
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF125__SHIFT                       0x1d
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF126__SHIFT                       0x1e
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF127__SHIFT                       0x1f
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF96_MASK                          0x00000001L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF97_MASK                          0x00000002L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF98_MASK                          0x00000004L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF99_MASK                          0x00000008L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF100_MASK                         0x00000010L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF101_MASK                         0x00000020L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF102_MASK                         0x00000040L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF103_MASK                         0x00000080L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF104_MASK                         0x00000100L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF105_MASK                         0x00000200L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF106_MASK                         0x00000400L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF107_MASK                         0x00000800L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF108_MASK                         0x00001000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF109_MASK                         0x00002000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF110_MASK                         0x00004000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF111_MASK                         0x00008000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF112_MASK                         0x00010000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF113_MASK                         0x00020000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF114_MASK                         0x00040000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF115_MASK                         0x00080000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF116_MASK                         0x00100000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF117_MASK                         0x00200000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF118_MASK                         0x00400000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF119_MASK                         0x00800000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF120_MASK                         0x01000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF121_MASK                         0x02000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF122_MASK                         0x04000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF123_MASK                         0x08000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF124_MASK                         0x10000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF125_MASK                         0x20000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF126_MASK                         0x40000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF127_MASK                         0x80000000L
+//BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF0__SHIFT                                 0x0
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF1__SHIFT                                 0x1
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF2__SHIFT                                 0x2
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF3__SHIFT                                 0x3
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF4__SHIFT                                 0x4
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF5__SHIFT                                 0x5
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF6__SHIFT                                 0x6
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF7__SHIFT                                 0x7
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF8__SHIFT                                 0x8
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF9__SHIFT                                 0x9
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF10__SHIFT                                0xa
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF11__SHIFT                                0xb
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF12__SHIFT                                0xc
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF13__SHIFT                                0xd
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF14__SHIFT                                0xe
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF15__SHIFT                                0xf
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF16__SHIFT                                0x10
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF17__SHIFT                                0x11
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF18__SHIFT                                0x12
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF19__SHIFT                                0x13
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF20__SHIFT                                0x14
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF21__SHIFT                                0x15
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF22__SHIFT                                0x16
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF23__SHIFT                                0x17
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF24__SHIFT                                0x18
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF25__SHIFT                                0x19
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF26__SHIFT                                0x1a
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF27__SHIFT                                0x1b
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF28__SHIFT                                0x1c
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF29__SHIFT                                0x1d
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF30__SHIFT                                0x1e
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF31__SHIFT                                0x1f
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF0_MASK                                   0x00000001L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF1_MASK                                   0x00000002L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF2_MASK                                   0x00000004L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF3_MASK                                   0x00000008L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF4_MASK                                   0x00000010L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF5_MASK                                   0x00000020L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF6_MASK                                   0x00000040L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF7_MASK                                   0x00000080L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF8_MASK                                   0x00000100L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF9_MASK                                   0x00000200L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF10_MASK                                  0x00000400L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF11_MASK                                  0x00000800L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF12_MASK                                  0x00001000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF13_MASK                                  0x00002000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF14_MASK                                  0x00004000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF15_MASK                                  0x00008000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF16_MASK                                  0x00010000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF17_MASK                                  0x00020000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF18_MASK                                  0x00040000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF19_MASK                                  0x00080000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF20_MASK                                  0x00100000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF21_MASK                                  0x00200000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF22_MASK                                  0x00400000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF23_MASK                                  0x00800000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF24_MASK                                  0x01000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF25_MASK                                  0x02000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF26_MASK                                  0x04000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF27_MASK                                  0x08000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF28_MASK                                  0x10000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF29_MASK                                  0x20000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF30_MASK                                  0x40000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF31_MASK                                  0x80000000L
+//BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF32__SHIFT                                0x0
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF33__SHIFT                                0x1
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF34__SHIFT                                0x2
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF35__SHIFT                                0x3
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF36__SHIFT                                0x4
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF37__SHIFT                                0x5
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF38__SHIFT                                0x6
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF39__SHIFT                                0x7
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF40__SHIFT                                0x8
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF41__SHIFT                                0x9
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF42__SHIFT                                0xa
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF43__SHIFT                                0xb
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF44__SHIFT                                0xc
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF45__SHIFT                                0xd
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF46__SHIFT                                0xe
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF47__SHIFT                                0xf
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF48__SHIFT                                0x10
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF49__SHIFT                                0x11
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF50__SHIFT                                0x12
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF51__SHIFT                                0x13
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF52__SHIFT                                0x14
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF53__SHIFT                                0x15
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF54__SHIFT                                0x16
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF55__SHIFT                                0x17
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF56__SHIFT                                0x18
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF57__SHIFT                                0x19
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF58__SHIFT                                0x1a
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF59__SHIFT                                0x1b
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF60__SHIFT                                0x1c
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF61__SHIFT                                0x1d
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF62__SHIFT                                0x1e
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF63__SHIFT                                0x1f
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF32_MASK                                  0x00000001L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF33_MASK                                  0x00000002L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF34_MASK                                  0x00000004L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF35_MASK                                  0x00000008L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF36_MASK                                  0x00000010L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF37_MASK                                  0x00000020L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF38_MASK                                  0x00000040L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF39_MASK                                  0x00000080L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF40_MASK                                  0x00000100L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF41_MASK                                  0x00000200L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF42_MASK                                  0x00000400L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF43_MASK                                  0x00000800L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF44_MASK                                  0x00001000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF45_MASK                                  0x00002000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF46_MASK                                  0x00004000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF47_MASK                                  0x00008000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF48_MASK                                  0x00010000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF49_MASK                                  0x00020000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF50_MASK                                  0x00040000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF51_MASK                                  0x00080000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF52_MASK                                  0x00100000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF53_MASK                                  0x00200000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF54_MASK                                  0x00400000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF55_MASK                                  0x00800000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF56_MASK                                  0x01000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF57_MASK                                  0x02000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF58_MASK                                  0x04000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF59_MASK                                  0x08000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF60_MASK                                  0x10000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF61_MASK                                  0x20000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF62_MASK                                  0x40000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF63_MASK                                  0x80000000L
+//BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF64__SHIFT                                0x0
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF65__SHIFT                                0x1
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF66__SHIFT                                0x2
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF67__SHIFT                                0x3
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF68__SHIFT                                0x4
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF69__SHIFT                                0x5
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF70__SHIFT                                0x6
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF71__SHIFT                                0x7
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF72__SHIFT                                0x8
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF73__SHIFT                                0x9
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF74__SHIFT                                0xa
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF75__SHIFT                                0xb
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF76__SHIFT                                0xc
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF77__SHIFT                                0xd
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF78__SHIFT                                0xe
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF79__SHIFT                                0xf
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF80__SHIFT                                0x10
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF81__SHIFT                                0x11
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF82__SHIFT                                0x12
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF83__SHIFT                                0x13
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF84__SHIFT                                0x14
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF85__SHIFT                                0x15
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF86__SHIFT                                0x16
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF87__SHIFT                                0x17
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF88__SHIFT                                0x18
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF89__SHIFT                                0x19
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF90__SHIFT                                0x1a
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF91__SHIFT                                0x1b
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF92__SHIFT                                0x1c
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF93__SHIFT                                0x1d
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF94__SHIFT                                0x1e
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF95__SHIFT                                0x1f
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF64_MASK                                  0x00000001L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF65_MASK                                  0x00000002L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF66_MASK                                  0x00000004L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF67_MASK                                  0x00000008L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF68_MASK                                  0x00000010L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF69_MASK                                  0x00000020L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF70_MASK                                  0x00000040L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF71_MASK                                  0x00000080L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF72_MASK                                  0x00000100L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF73_MASK                                  0x00000200L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF74_MASK                                  0x00000400L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF75_MASK                                  0x00000800L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF76_MASK                                  0x00001000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF77_MASK                                  0x00002000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF78_MASK                                  0x00004000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF79_MASK                                  0x00008000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF80_MASK                                  0x00010000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF81_MASK                                  0x00020000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF82_MASK                                  0x00040000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF83_MASK                                  0x00080000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF84_MASK                                  0x00100000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF85_MASK                                  0x00200000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF86_MASK                                  0x00400000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF87_MASK                                  0x00800000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF88_MASK                                  0x01000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF89_MASK                                  0x02000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF90_MASK                                  0x04000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF91_MASK                                  0x08000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF92_MASK                                  0x10000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF93_MASK                                  0x20000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF94_MASK                                  0x40000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF95_MASK                                  0x80000000L
+//BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF96__SHIFT                                0x0
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF97__SHIFT                                0x1
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF98__SHIFT                                0x2
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF99__SHIFT                                0x3
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF100__SHIFT                               0x4
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF101__SHIFT                               0x5
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF102__SHIFT                               0x6
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF103__SHIFT                               0x7
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF104__SHIFT                               0x8
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF105__SHIFT                               0x9
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF106__SHIFT                               0xa
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF107__SHIFT                               0xb
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF108__SHIFT                               0xc
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF109__SHIFT                               0xd
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF110__SHIFT                               0xe
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF111__SHIFT                               0xf
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF112__SHIFT                               0x10
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF113__SHIFT                               0x11
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF114__SHIFT                               0x12
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF115__SHIFT                               0x13
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF116__SHIFT                               0x14
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF117__SHIFT                               0x15
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF118__SHIFT                               0x16
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF119__SHIFT                               0x17
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF120__SHIFT                               0x18
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF121__SHIFT                               0x19
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF122__SHIFT                               0x1a
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF123__SHIFT                               0x1b
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF124__SHIFT                               0x1c
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF125__SHIFT                               0x1d
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF126__SHIFT                               0x1e
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF127__SHIFT                               0x1f
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF96_MASK                                  0x00000001L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF97_MASK                                  0x00000002L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF98_MASK                                  0x00000004L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF99_MASK                                  0x00000008L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF100_MASK                                 0x00000010L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF101_MASK                                 0x00000020L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF102_MASK                                 0x00000040L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF103_MASK                                 0x00000080L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF104_MASK                                 0x00000100L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF105_MASK                                 0x00000200L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF106_MASK                                 0x00000400L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF107_MASK                                 0x00000800L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF108_MASK                                 0x00001000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF109_MASK                                 0x00002000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF110_MASK                                 0x00004000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF111_MASK                                 0x00008000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF112_MASK                                 0x00010000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF113_MASK                                 0x00020000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF114_MASK                                 0x00040000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF115_MASK                                 0x00080000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF116_MASK                                 0x00100000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF117_MASK                                 0x00200000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF118_MASK                                 0x00400000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF119_MASK                                 0x00800000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF120_MASK                                 0x01000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF121_MASK                                 0x02000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF122_MASK                                 0x04000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF123_MASK                                 0x08000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF124_MASK                                 0x10000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF125_MASK                                 0x20000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF126_MASK                                 0x40000000L
+#define BIF_MISC_PFVF_DEV0_EPF0_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF127_MASK                                 0x80000000L
+
+
+// addressBlock: nbif0_nbif0_bif_misc_pfvf_dev0_epf1_bif_misc_pfvf_regblk
+//BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF0__SHIFT                               0x0
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF1__SHIFT                               0x1
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF2__SHIFT                               0x2
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF3__SHIFT                               0x3
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF4__SHIFT                               0x4
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF5__SHIFT                               0x5
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF6__SHIFT                               0x6
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF7__SHIFT                               0x7
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF8__SHIFT                               0x8
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF9__SHIFT                               0x9
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF10__SHIFT                              0xa
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF11__SHIFT                              0xb
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF12__SHIFT                              0xc
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF13__SHIFT                              0xd
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF14__SHIFT                              0xe
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF15__SHIFT                              0xf
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF16__SHIFT                              0x10
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF17__SHIFT                              0x11
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF18__SHIFT                              0x12
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF19__SHIFT                              0x13
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF20__SHIFT                              0x14
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF21__SHIFT                              0x15
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF22__SHIFT                              0x16
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF23__SHIFT                              0x17
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF24__SHIFT                              0x18
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF25__SHIFT                              0x19
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF26__SHIFT                              0x1a
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF27__SHIFT                              0x1b
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF28__SHIFT                              0x1c
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF29__SHIFT                              0x1d
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF30__SHIFT                              0x1e
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF31__SHIFT                              0x1f
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF0_MASK                                 0x00000001L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF1_MASK                                 0x00000002L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF2_MASK                                 0x00000004L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF3_MASK                                 0x00000008L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF4_MASK                                 0x00000010L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF5_MASK                                 0x00000020L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF6_MASK                                 0x00000040L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF7_MASK                                 0x00000080L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF8_MASK                                 0x00000100L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF9_MASK                                 0x00000200L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF10_MASK                                0x00000400L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF11_MASK                                0x00000800L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF12_MASK                                0x00001000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF13_MASK                                0x00002000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF14_MASK                                0x00004000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF15_MASK                                0x00008000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF16_MASK                                0x00010000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF17_MASK                                0x00020000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF18_MASK                                0x00040000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF19_MASK                                0x00080000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF20_MASK                                0x00100000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF21_MASK                                0x00200000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF22_MASK                                0x00400000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF23_MASK                                0x00800000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF24_MASK                                0x01000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF25_MASK                                0x02000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF26_MASK                                0x04000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF27_MASK                                0x08000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF28_MASK                                0x10000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF29_MASK                                0x20000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF30_MASK                                0x40000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG0__DMA_ON_BME_LOW_VF31_MASK                                0x80000000L
+//BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF32__SHIFT                              0x0
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF33__SHIFT                              0x1
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF34__SHIFT                              0x2
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF35__SHIFT                              0x3
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF36__SHIFT                              0x4
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF37__SHIFT                              0x5
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF38__SHIFT                              0x6
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF39__SHIFT                              0x7
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF40__SHIFT                              0x8
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF41__SHIFT                              0x9
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF42__SHIFT                              0xa
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF43__SHIFT                              0xb
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF44__SHIFT                              0xc
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF45__SHIFT                              0xd
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF46__SHIFT                              0xe
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF47__SHIFT                              0xf
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF48__SHIFT                              0x10
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF49__SHIFT                              0x11
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF50__SHIFT                              0x12
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF51__SHIFT                              0x13
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF52__SHIFT                              0x14
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF53__SHIFT                              0x15
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF54__SHIFT                              0x16
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF55__SHIFT                              0x17
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF56__SHIFT                              0x18
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF57__SHIFT                              0x19
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF58__SHIFT                              0x1a
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF59__SHIFT                              0x1b
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF60__SHIFT                              0x1c
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF61__SHIFT                              0x1d
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF62__SHIFT                              0x1e
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF63__SHIFT                              0x1f
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF32_MASK                                0x00000001L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF33_MASK                                0x00000002L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF34_MASK                                0x00000004L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF35_MASK                                0x00000008L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF36_MASK                                0x00000010L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF37_MASK                                0x00000020L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF38_MASK                                0x00000040L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF39_MASK                                0x00000080L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF40_MASK                                0x00000100L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF41_MASK                                0x00000200L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF42_MASK                                0x00000400L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF43_MASK                                0x00000800L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF44_MASK                                0x00001000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF45_MASK                                0x00002000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF46_MASK                                0x00004000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF47_MASK                                0x00008000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF48_MASK                                0x00010000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF49_MASK                                0x00020000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF50_MASK                                0x00040000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF51_MASK                                0x00080000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF52_MASK                                0x00100000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF53_MASK                                0x00200000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF54_MASK                                0x00400000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF55_MASK                                0x00800000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF56_MASK                                0x01000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF57_MASK                                0x02000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF58_MASK                                0x04000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF59_MASK                                0x08000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF60_MASK                                0x10000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF61_MASK                                0x20000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF62_MASK                                0x40000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG1__DMA_ON_BME_LOW_VF63_MASK                                0x80000000L
+//BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF64__SHIFT                              0x0
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF65__SHIFT                              0x1
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF66__SHIFT                              0x2
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF67__SHIFT                              0x3
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF68__SHIFT                              0x4
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF69__SHIFT                              0x5
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF70__SHIFT                              0x6
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF71__SHIFT                              0x7
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF72__SHIFT                              0x8
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF73__SHIFT                              0x9
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF74__SHIFT                              0xa
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF75__SHIFT                              0xb
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF76__SHIFT                              0xc
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF77__SHIFT                              0xd
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF78__SHIFT                              0xe
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF79__SHIFT                              0xf
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF80__SHIFT                              0x10
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF81__SHIFT                              0x11
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF82__SHIFT                              0x12
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF83__SHIFT                              0x13
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF84__SHIFT                              0x14
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF85__SHIFT                              0x15
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF86__SHIFT                              0x16
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF87__SHIFT                              0x17
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF88__SHIFT                              0x18
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF89__SHIFT                              0x19
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF90__SHIFT                              0x1a
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF91__SHIFT                              0x1b
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF92__SHIFT                              0x1c
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF93__SHIFT                              0x1d
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF94__SHIFT                              0x1e
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF95__SHIFT                              0x1f
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF64_MASK                                0x00000001L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF65_MASK                                0x00000002L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF66_MASK                                0x00000004L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF67_MASK                                0x00000008L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF68_MASK                                0x00000010L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF69_MASK                                0x00000020L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF70_MASK                                0x00000040L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF71_MASK                                0x00000080L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF72_MASK                                0x00000100L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF73_MASK                                0x00000200L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF74_MASK                                0x00000400L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF75_MASK                                0x00000800L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF76_MASK                                0x00001000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF77_MASK                                0x00002000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF78_MASK                                0x00004000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF79_MASK                                0x00008000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF80_MASK                                0x00010000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF81_MASK                                0x00020000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF82_MASK                                0x00040000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF83_MASK                                0x00080000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF84_MASK                                0x00100000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF85_MASK                                0x00200000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF86_MASK                                0x00400000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF87_MASK                                0x00800000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF88_MASK                                0x01000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF89_MASK                                0x02000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF90_MASK                                0x04000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF91_MASK                                0x08000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF92_MASK                                0x10000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF93_MASK                                0x20000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF94_MASK                                0x40000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG2__DMA_ON_BME_LOW_VF95_MASK                                0x80000000L
+//BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF96__SHIFT                              0x0
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF97__SHIFT                              0x1
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF98__SHIFT                              0x2
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF99__SHIFT                              0x3
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF100__SHIFT                             0x4
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF101__SHIFT                             0x5
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF102__SHIFT                             0x6
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF103__SHIFT                             0x7
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF104__SHIFT                             0x8
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF105__SHIFT                             0x9
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF106__SHIFT                             0xa
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF107__SHIFT                             0xb
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF108__SHIFT                             0xc
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF109__SHIFT                             0xd
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF110__SHIFT                             0xe
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF111__SHIFT                             0xf
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF112__SHIFT                             0x10
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF113__SHIFT                             0x11
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF114__SHIFT                             0x12
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF115__SHIFT                             0x13
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF116__SHIFT                             0x14
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF117__SHIFT                             0x15
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF118__SHIFT                             0x16
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF119__SHIFT                             0x17
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF120__SHIFT                             0x18
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF121__SHIFT                             0x19
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF122__SHIFT                             0x1a
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF123__SHIFT                             0x1b
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF124__SHIFT                             0x1c
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF125__SHIFT                             0x1d
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF126__SHIFT                             0x1e
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF127__SHIFT                             0x1f
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF96_MASK                                0x00000001L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF97_MASK                                0x00000002L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF98_MASK                                0x00000004L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF99_MASK                                0x00000008L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF100_MASK                               0x00000010L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF101_MASK                               0x00000020L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF102_MASK                               0x00000040L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF103_MASK                               0x00000080L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF104_MASK                               0x00000100L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF105_MASK                               0x00000200L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF106_MASK                               0x00000400L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF107_MASK                               0x00000800L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF108_MASK                               0x00001000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF109_MASK                               0x00002000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF110_MASK                               0x00004000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF111_MASK                               0x00008000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF112_MASK                               0x00010000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF113_MASK                               0x00020000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF114_MASK                               0x00040000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF115_MASK                               0x00080000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF116_MASK                               0x00100000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF117_MASK                               0x00200000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF118_MASK                               0x00400000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF119_MASK                               0x00800000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF120_MASK                               0x01000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF121_MASK                               0x02000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF122_MASK                               0x04000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF123_MASK                               0x08000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF124_MASK                               0x10000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF125_MASK                               0x20000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF126_MASK                               0x40000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIFC_VF_BME_ERR_LOG3__DMA_ON_BME_LOW_VF127_MASK                               0x80000000L
+//BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF0__SHIFT                         0x0
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF1__SHIFT                         0x1
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF2__SHIFT                         0x2
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF3__SHIFT                         0x3
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF4__SHIFT                         0x4
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF5__SHIFT                         0x5
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF6__SHIFT                         0x6
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF7__SHIFT                         0x7
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF8__SHIFT                         0x8
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF9__SHIFT                         0x9
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF10__SHIFT                        0xa
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF11__SHIFT                        0xb
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF12__SHIFT                        0xc
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF13__SHIFT                        0xd
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF14__SHIFT                        0xe
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF15__SHIFT                        0xf
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF16__SHIFT                        0x10
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF17__SHIFT                        0x11
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF18__SHIFT                        0x12
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF19__SHIFT                        0x13
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF20__SHIFT                        0x14
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF21__SHIFT                        0x15
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF22__SHIFT                        0x16
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF23__SHIFT                        0x17
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF24__SHIFT                        0x18
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF25__SHIFT                        0x19
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF26__SHIFT                        0x1a
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF27__SHIFT                        0x1b
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF28__SHIFT                        0x1c
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF29__SHIFT                        0x1d
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF30__SHIFT                        0x1e
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF31__SHIFT                        0x1f
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF0_MASK                           0x00000001L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF1_MASK                           0x00000002L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF2_MASK                           0x00000004L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF3_MASK                           0x00000008L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF4_MASK                           0x00000010L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF5_MASK                           0x00000020L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF6_MASK                           0x00000040L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF7_MASK                           0x00000080L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF8_MASK                           0x00000100L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF9_MASK                           0x00000200L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF10_MASK                          0x00000400L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF11_MASK                          0x00000800L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF12_MASK                          0x00001000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF13_MASK                          0x00002000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF14_MASK                          0x00004000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF15_MASK                          0x00008000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF16_MASK                          0x00010000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF17_MASK                          0x00020000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF18_MASK                          0x00040000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF19_MASK                          0x00080000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF20_MASK                          0x00100000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF21_MASK                          0x00200000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF22_MASK                          0x00400000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF23_MASK                          0x00800000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF24_MASK                          0x01000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF25_MASK                          0x02000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF26_MASK                          0x04000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF27_MASK                          0x08000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF28_MASK                          0x10000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF29_MASK                          0x20000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF30_MASK                          0x40000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE0__UR_ATOMIC_OPCODE_VF31_MASK                          0x80000000L
+//BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF32__SHIFT                        0x0
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF33__SHIFT                        0x1
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF34__SHIFT                        0x2
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF35__SHIFT                        0x3
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF36__SHIFT                        0x4
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF37__SHIFT                        0x5
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF38__SHIFT                        0x6
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF39__SHIFT                        0x7
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF40__SHIFT                        0x8
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF41__SHIFT                        0x9
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF42__SHIFT                        0xa
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF43__SHIFT                        0xb
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF44__SHIFT                        0xc
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF45__SHIFT                        0xd
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF46__SHIFT                        0xe
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF47__SHIFT                        0xf
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF48__SHIFT                        0x10
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF49__SHIFT                        0x11
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF50__SHIFT                        0x12
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF51__SHIFT                        0x13
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF52__SHIFT                        0x14
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF53__SHIFT                        0x15
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF54__SHIFT                        0x16
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF55__SHIFT                        0x17
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF56__SHIFT                        0x18
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF57__SHIFT                        0x19
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF58__SHIFT                        0x1a
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF59__SHIFT                        0x1b
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF60__SHIFT                        0x1c
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF61__SHIFT                        0x1d
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF62__SHIFT                        0x1e
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF63__SHIFT                        0x1f
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF32_MASK                          0x00000001L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF33_MASK                          0x00000002L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF34_MASK                          0x00000004L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF35_MASK                          0x00000008L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF36_MASK                          0x00000010L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF37_MASK                          0x00000020L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF38_MASK                          0x00000040L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF39_MASK                          0x00000080L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF40_MASK                          0x00000100L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF41_MASK                          0x00000200L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF42_MASK                          0x00000400L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF43_MASK                          0x00000800L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF44_MASK                          0x00001000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF45_MASK                          0x00002000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF46_MASK                          0x00004000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF47_MASK                          0x00008000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF48_MASK                          0x00010000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF49_MASK                          0x00020000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF50_MASK                          0x00040000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF51_MASK                          0x00080000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF52_MASK                          0x00100000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF53_MASK                          0x00200000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF54_MASK                          0x00400000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF55_MASK                          0x00800000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF56_MASK                          0x01000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF57_MASK                          0x02000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF58_MASK                          0x04000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF59_MASK                          0x08000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF60_MASK                          0x10000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF61_MASK                          0x20000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF62_MASK                          0x40000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE1__UR_ATOMIC_OPCODE_VF63_MASK                          0x80000000L
+//BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF64__SHIFT                        0x0
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF65__SHIFT                        0x1
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF66__SHIFT                        0x2
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF67__SHIFT                        0x3
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF68__SHIFT                        0x4
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF69__SHIFT                        0x5
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF70__SHIFT                        0x6
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF71__SHIFT                        0x7
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF72__SHIFT                        0x8
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF73__SHIFT                        0x9
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF74__SHIFT                        0xa
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF75__SHIFT                        0xb
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF76__SHIFT                        0xc
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF77__SHIFT                        0xd
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF78__SHIFT                        0xe
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF79__SHIFT                        0xf
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF80__SHIFT                        0x10
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF81__SHIFT                        0x11
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF82__SHIFT                        0x12
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF83__SHIFT                        0x13
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF84__SHIFT                        0x14
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF85__SHIFT                        0x15
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF86__SHIFT                        0x16
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF87__SHIFT                        0x17
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF88__SHIFT                        0x18
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF89__SHIFT                        0x19
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF90__SHIFT                        0x1a
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF91__SHIFT                        0x1b
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF92__SHIFT                        0x1c
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF93__SHIFT                        0x1d
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF94__SHIFT                        0x1e
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF95__SHIFT                        0x1f
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF64_MASK                          0x00000001L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF65_MASK                          0x00000002L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF66_MASK                          0x00000004L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF67_MASK                          0x00000008L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF68_MASK                          0x00000010L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF69_MASK                          0x00000020L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF70_MASK                          0x00000040L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF71_MASK                          0x00000080L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF72_MASK                          0x00000100L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF73_MASK                          0x00000200L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF74_MASK                          0x00000400L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF75_MASK                          0x00000800L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF76_MASK                          0x00001000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF77_MASK                          0x00002000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF78_MASK                          0x00004000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF79_MASK                          0x00008000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF80_MASK                          0x00010000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF81_MASK                          0x00020000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF82_MASK                          0x00040000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF83_MASK                          0x00080000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF84_MASK                          0x00100000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF85_MASK                          0x00200000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF86_MASK                          0x00400000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF87_MASK                          0x00800000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF88_MASK                          0x01000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF89_MASK                          0x02000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF90_MASK                          0x04000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF91_MASK                          0x08000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF92_MASK                          0x10000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF93_MASK                          0x20000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF94_MASK                          0x40000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE2__UR_ATOMIC_OPCODE_VF95_MASK                          0x80000000L
+//BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF96__SHIFT                        0x0
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF97__SHIFT                        0x1
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF98__SHIFT                        0x2
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF99__SHIFT                        0x3
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF100__SHIFT                       0x4
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF101__SHIFT                       0x5
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF102__SHIFT                       0x6
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF103__SHIFT                       0x7
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF104__SHIFT                       0x8
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF105__SHIFT                       0x9
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF106__SHIFT                       0xa
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF107__SHIFT                       0xb
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF108__SHIFT                       0xc
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF109__SHIFT                       0xd
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF110__SHIFT                       0xe
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF111__SHIFT                       0xf
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF112__SHIFT                       0x10
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF113__SHIFT                       0x11
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF114__SHIFT                       0x12
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF115__SHIFT                       0x13
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF116__SHIFT                       0x14
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF117__SHIFT                       0x15
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF118__SHIFT                       0x16
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF119__SHIFT                       0x17
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF120__SHIFT                       0x18
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF121__SHIFT                       0x19
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF122__SHIFT                       0x1a
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF123__SHIFT                       0x1b
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF124__SHIFT                       0x1c
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF125__SHIFT                       0x1d
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF126__SHIFT                       0x1e
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF127__SHIFT                       0x1f
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF96_MASK                          0x00000001L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF97_MASK                          0x00000002L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF98_MASK                          0x00000004L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF99_MASK                          0x00000008L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF100_MASK                         0x00000010L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF101_MASK                         0x00000020L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF102_MASK                         0x00000040L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF103_MASK                         0x00000080L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF104_MASK                         0x00000100L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF105_MASK                         0x00000200L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF106_MASK                         0x00000400L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF107_MASK                         0x00000800L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF108_MASK                         0x00001000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF109_MASK                         0x00002000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF110_MASK                         0x00004000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF111_MASK                         0x00008000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF112_MASK                         0x00010000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF113_MASK                         0x00020000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF114_MASK                         0x00040000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF115_MASK                         0x00080000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF116_MASK                         0x00100000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF117_MASK                         0x00200000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF118_MASK                         0x00400000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF119_MASK                         0x00800000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF120_MASK                         0x01000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF121_MASK                         0x02000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF122_MASK                         0x04000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF123_MASK                         0x08000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF124_MASK                         0x10000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF125_MASK                         0x20000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF126_MASK                         0x40000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_OPCODE3__UR_ATOMIC_OPCODE_VF127_MASK                         0x80000000L
+//BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF0__SHIFT                   0x0
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF1__SHIFT                   0x1
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF2__SHIFT                   0x2
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF3__SHIFT                   0x3
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF4__SHIFT                   0x4
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF5__SHIFT                   0x5
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF6__SHIFT                   0x6
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF7__SHIFT                   0x7
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF8__SHIFT                   0x8
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF9__SHIFT                   0x9
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF10__SHIFT                  0xa
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF11__SHIFT                  0xb
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF12__SHIFT                  0xc
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF13__SHIFT                  0xd
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF14__SHIFT                  0xe
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF15__SHIFT                  0xf
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF16__SHIFT                  0x10
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF17__SHIFT                  0x11
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF18__SHIFT                  0x12
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF19__SHIFT                  0x13
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF20__SHIFT                  0x14
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF21__SHIFT                  0x15
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF22__SHIFT                  0x16
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF23__SHIFT                  0x17
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF24__SHIFT                  0x18
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF25__SHIFT                  0x19
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF26__SHIFT                  0x1a
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF27__SHIFT                  0x1b
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF28__SHIFT                  0x1c
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF29__SHIFT                  0x1d
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF30__SHIFT                  0x1e
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF31__SHIFT                  0x1f
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF0_MASK                     0x00000001L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF1_MASK                     0x00000002L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF2_MASK                     0x00000004L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF3_MASK                     0x00000008L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF4_MASK                     0x00000010L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF5_MASK                     0x00000020L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF6_MASK                     0x00000040L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF7_MASK                     0x00000080L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF8_MASK                     0x00000100L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF9_MASK                     0x00000200L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF10_MASK                    0x00000400L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF11_MASK                    0x00000800L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF12_MASK                    0x00001000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF13_MASK                    0x00002000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF14_MASK                    0x00004000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF15_MASK                    0x00008000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF16_MASK                    0x00010000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF17_MASK                    0x00020000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF18_MASK                    0x00040000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF19_MASK                    0x00080000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF20_MASK                    0x00100000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF21_MASK                    0x00200000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF22_MASK                    0x00400000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF23_MASK                    0x00800000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF24_MASK                    0x01000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF25_MASK                    0x02000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF26_MASK                    0x04000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF27_MASK                    0x08000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF28_MASK                    0x10000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF29_MASK                    0x20000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF30_MASK                    0x40000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW0__UR_ATOMIC_REQEN_LOW_VF31_MASK                    0x80000000L
+//BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF32__SHIFT                  0x0
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF33__SHIFT                  0x1
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF34__SHIFT                  0x2
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF35__SHIFT                  0x3
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF36__SHIFT                  0x4
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF37__SHIFT                  0x5
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF38__SHIFT                  0x6
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF39__SHIFT                  0x7
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF40__SHIFT                  0x8
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF41__SHIFT                  0x9
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF42__SHIFT                  0xa
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF43__SHIFT                  0xb
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF44__SHIFT                  0xc
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF45__SHIFT                  0xd
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF46__SHIFT                  0xe
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF47__SHIFT                  0xf
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF48__SHIFT                  0x10
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF49__SHIFT                  0x11
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF50__SHIFT                  0x12
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF51__SHIFT                  0x13
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF52__SHIFT                  0x14
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF53__SHIFT                  0x15
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF54__SHIFT                  0x16
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF55__SHIFT                  0x17
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF56__SHIFT                  0x18
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF57__SHIFT                  0x19
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF58__SHIFT                  0x1a
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF59__SHIFT                  0x1b
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF60__SHIFT                  0x1c
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF61__SHIFT                  0x1d
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF62__SHIFT                  0x1e
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF63__SHIFT                  0x1f
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF32_MASK                    0x00000001L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF33_MASK                    0x00000002L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF34_MASK                    0x00000004L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF35_MASK                    0x00000008L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF36_MASK                    0x00000010L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF37_MASK                    0x00000020L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF38_MASK                    0x00000040L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF39_MASK                    0x00000080L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF40_MASK                    0x00000100L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF41_MASK                    0x00000200L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF42_MASK                    0x00000400L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF43_MASK                    0x00000800L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF44_MASK                    0x00001000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF45_MASK                    0x00002000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF46_MASK                    0x00004000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF47_MASK                    0x00008000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF48_MASK                    0x00010000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF49_MASK                    0x00020000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF50_MASK                    0x00040000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF51_MASK                    0x00080000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF52_MASK                    0x00100000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF53_MASK                    0x00200000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF54_MASK                    0x00400000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF55_MASK                    0x00800000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF56_MASK                    0x01000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF57_MASK                    0x02000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF58_MASK                    0x04000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF59_MASK                    0x08000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF60_MASK                    0x10000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF61_MASK                    0x20000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF62_MASK                    0x40000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW1__UR_ATOMIC_REQEN_LOW_VF63_MASK                    0x80000000L
+//BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF64__SHIFT                  0x0
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF65__SHIFT                  0x1
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF66__SHIFT                  0x2
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF67__SHIFT                  0x3
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF68__SHIFT                  0x4
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF69__SHIFT                  0x5
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF70__SHIFT                  0x6
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF71__SHIFT                  0x7
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF72__SHIFT                  0x8
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF73__SHIFT                  0x9
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF74__SHIFT                  0xa
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF75__SHIFT                  0xb
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF76__SHIFT                  0xc
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF77__SHIFT                  0xd
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF78__SHIFT                  0xe
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF79__SHIFT                  0xf
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF80__SHIFT                  0x10
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF81__SHIFT                  0x11
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF82__SHIFT                  0x12
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF83__SHIFT                  0x13
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF84__SHIFT                  0x14
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF85__SHIFT                  0x15
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF86__SHIFT                  0x16
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF87__SHIFT                  0x17
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF88__SHIFT                  0x18
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF89__SHIFT                  0x19
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF90__SHIFT                  0x1a
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF91__SHIFT                  0x1b
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF92__SHIFT                  0x1c
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF93__SHIFT                  0x1d
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF94__SHIFT                  0x1e
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF95__SHIFT                  0x1f
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF64_MASK                    0x00000001L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF65_MASK                    0x00000002L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF66_MASK                    0x00000004L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF67_MASK                    0x00000008L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF68_MASK                    0x00000010L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF69_MASK                    0x00000020L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF70_MASK                    0x00000040L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF71_MASK                    0x00000080L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF72_MASK                    0x00000100L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF73_MASK                    0x00000200L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF74_MASK                    0x00000400L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF75_MASK                    0x00000800L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF76_MASK                    0x00001000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF77_MASK                    0x00002000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF78_MASK                    0x00004000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF79_MASK                    0x00008000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF80_MASK                    0x00010000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF81_MASK                    0x00020000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF82_MASK                    0x00040000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF83_MASK                    0x00080000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF84_MASK                    0x00100000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF85_MASK                    0x00200000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF86_MASK                    0x00400000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF87_MASK                    0x00800000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF88_MASK                    0x01000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF89_MASK                    0x02000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF90_MASK                    0x04000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF91_MASK                    0x08000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF92_MASK                    0x10000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF93_MASK                    0x20000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF94_MASK                    0x40000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW2__UR_ATOMIC_REQEN_LOW_VF95_MASK                    0x80000000L
+//BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF96__SHIFT                  0x0
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF97__SHIFT                  0x1
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF98__SHIFT                  0x2
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF99__SHIFT                  0x3
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF100__SHIFT                 0x4
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF101__SHIFT                 0x5
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF102__SHIFT                 0x6
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF103__SHIFT                 0x7
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF104__SHIFT                 0x8
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF105__SHIFT                 0x9
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF106__SHIFT                 0xa
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF107__SHIFT                 0xb
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF108__SHIFT                 0xc
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF109__SHIFT                 0xd
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF110__SHIFT                 0xe
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF111__SHIFT                 0xf
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF112__SHIFT                 0x10
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF113__SHIFT                 0x11
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF114__SHIFT                 0x12
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF115__SHIFT                 0x13
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF116__SHIFT                 0x14
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF117__SHIFT                 0x15
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF118__SHIFT                 0x16
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF119__SHIFT                 0x17
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF120__SHIFT                 0x18
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF121__SHIFT                 0x19
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF122__SHIFT                 0x1a
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF123__SHIFT                 0x1b
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF124__SHIFT                 0x1c
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF125__SHIFT                 0x1d
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF126__SHIFT                 0x1e
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF127__SHIFT                 0x1f
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF96_MASK                    0x00000001L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF97_MASK                    0x00000002L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF98_MASK                    0x00000004L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF99_MASK                    0x00000008L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF100_MASK                   0x00000010L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF101_MASK                   0x00000020L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF102_MASK                   0x00000040L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF103_MASK                   0x00000080L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF104_MASK                   0x00000100L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF105_MASK                   0x00000200L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF106_MASK                   0x00000400L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF107_MASK                   0x00000800L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF108_MASK                   0x00001000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF109_MASK                   0x00002000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF110_MASK                   0x00004000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF111_MASK                   0x00008000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF112_MASK                   0x00010000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF113_MASK                   0x00020000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF114_MASK                   0x00040000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF115_MASK                   0x00080000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF116_MASK                   0x00100000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF117_MASK                   0x00200000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF118_MASK                   0x00400000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF119_MASK                   0x00800000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF120_MASK                   0x01000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF121_MASK                   0x02000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF122_MASK                   0x04000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF123_MASK                   0x08000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF124_MASK                   0x10000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF125_MASK                   0x20000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF126_MASK                   0x40000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_REQEN_LOW3__UR_ATOMIC_REQEN_LOW_VF127_MASK                   0x80000000L
+//BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF0__SHIFT                         0x0
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF1__SHIFT                         0x1
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF2__SHIFT                         0x2
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF3__SHIFT                         0x3
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF4__SHIFT                         0x4
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF5__SHIFT                         0x5
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF6__SHIFT                         0x6
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF7__SHIFT                         0x7
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF8__SHIFT                         0x8
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF9__SHIFT                         0x9
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF10__SHIFT                        0xa
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF11__SHIFT                        0xb
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF12__SHIFT                        0xc
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF13__SHIFT                        0xd
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF14__SHIFT                        0xe
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF15__SHIFT                        0xf
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF16__SHIFT                        0x10
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF17__SHIFT                        0x11
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF18__SHIFT                        0x12
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF19__SHIFT                        0x13
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF20__SHIFT                        0x14
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF21__SHIFT                        0x15
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF22__SHIFT                        0x16
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF23__SHIFT                        0x17
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF24__SHIFT                        0x18
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF25__SHIFT                        0x19
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF26__SHIFT                        0x1a
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF27__SHIFT                        0x1b
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF28__SHIFT                        0x1c
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF29__SHIFT                        0x1d
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF30__SHIFT                        0x1e
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF31__SHIFT                        0x1f
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF0_MASK                           0x00000001L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF1_MASK                           0x00000002L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF2_MASK                           0x00000004L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF3_MASK                           0x00000008L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF4_MASK                           0x00000010L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF5_MASK                           0x00000020L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF6_MASK                           0x00000040L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF7_MASK                           0x00000080L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF8_MASK                           0x00000100L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF9_MASK                           0x00000200L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF10_MASK                          0x00000400L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF11_MASK                          0x00000800L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF12_MASK                          0x00001000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF13_MASK                          0x00002000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF14_MASK                          0x00004000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF15_MASK                          0x00008000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF16_MASK                          0x00010000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF17_MASK                          0x00020000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF18_MASK                          0x00040000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF19_MASK                          0x00080000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF20_MASK                          0x00100000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF21_MASK                          0x00200000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF22_MASK                          0x00400000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF23_MASK                          0x00800000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF24_MASK                          0x01000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF25_MASK                          0x02000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF26_MASK                          0x04000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF27_MASK                          0x08000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF28_MASK                          0x10000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF29_MASK                          0x20000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF30_MASK                          0x40000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH0__UR_ATOMIC_LENGTH_VF31_MASK                          0x80000000L
+//BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF32__SHIFT                        0x0
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF33__SHIFT                        0x1
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF34__SHIFT                        0x2
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF35__SHIFT                        0x3
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF36__SHIFT                        0x4
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF37__SHIFT                        0x5
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF38__SHIFT                        0x6
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF39__SHIFT                        0x7
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF40__SHIFT                        0x8
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF41__SHIFT                        0x9
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF42__SHIFT                        0xa
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF43__SHIFT                        0xb
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF44__SHIFT                        0xc
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF45__SHIFT                        0xd
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF46__SHIFT                        0xe
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF47__SHIFT                        0xf
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF48__SHIFT                        0x10
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF49__SHIFT                        0x11
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF50__SHIFT                        0x12
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF51__SHIFT                        0x13
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF52__SHIFT                        0x14
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF53__SHIFT                        0x15
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF54__SHIFT                        0x16
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF55__SHIFT                        0x17
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF56__SHIFT                        0x18
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF57__SHIFT                        0x19
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF58__SHIFT                        0x1a
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF59__SHIFT                        0x1b
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF60__SHIFT                        0x1c
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF61__SHIFT                        0x1d
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF62__SHIFT                        0x1e
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF63__SHIFT                        0x1f
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF32_MASK                          0x00000001L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF33_MASK                          0x00000002L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF34_MASK                          0x00000004L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF35_MASK                          0x00000008L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF36_MASK                          0x00000010L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF37_MASK                          0x00000020L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF38_MASK                          0x00000040L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF39_MASK                          0x00000080L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF40_MASK                          0x00000100L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF41_MASK                          0x00000200L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF42_MASK                          0x00000400L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF43_MASK                          0x00000800L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF44_MASK                          0x00001000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF45_MASK                          0x00002000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF46_MASK                          0x00004000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF47_MASK                          0x00008000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF48_MASK                          0x00010000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF49_MASK                          0x00020000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF50_MASK                          0x00040000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF51_MASK                          0x00080000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF52_MASK                          0x00100000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF53_MASK                          0x00200000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF54_MASK                          0x00400000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF55_MASK                          0x00800000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF56_MASK                          0x01000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF57_MASK                          0x02000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF58_MASK                          0x04000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF59_MASK                          0x08000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF60_MASK                          0x10000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF61_MASK                          0x20000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF62_MASK                          0x40000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH1__UR_ATOMIC_LENGTH_VF63_MASK                          0x80000000L
+//BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF64__SHIFT                        0x0
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF65__SHIFT                        0x1
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF66__SHIFT                        0x2
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF67__SHIFT                        0x3
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF68__SHIFT                        0x4
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF69__SHIFT                        0x5
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF70__SHIFT                        0x6
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF71__SHIFT                        0x7
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF72__SHIFT                        0x8
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF73__SHIFT                        0x9
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF74__SHIFT                        0xa
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF75__SHIFT                        0xb
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF76__SHIFT                        0xc
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF77__SHIFT                        0xd
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF78__SHIFT                        0xe
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF79__SHIFT                        0xf
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF80__SHIFT                        0x10
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF81__SHIFT                        0x11
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF82__SHIFT                        0x12
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF83__SHIFT                        0x13
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF84__SHIFT                        0x14
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF85__SHIFT                        0x15
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF86__SHIFT                        0x16
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF87__SHIFT                        0x17
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF88__SHIFT                        0x18
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF89__SHIFT                        0x19
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF90__SHIFT                        0x1a
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF91__SHIFT                        0x1b
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF92__SHIFT                        0x1c
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF93__SHIFT                        0x1d
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF94__SHIFT                        0x1e
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF95__SHIFT                        0x1f
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF64_MASK                          0x00000001L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF65_MASK                          0x00000002L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF66_MASK                          0x00000004L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF67_MASK                          0x00000008L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF68_MASK                          0x00000010L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF69_MASK                          0x00000020L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF70_MASK                          0x00000040L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF71_MASK                          0x00000080L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF72_MASK                          0x00000100L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF73_MASK                          0x00000200L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF74_MASK                          0x00000400L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF75_MASK                          0x00000800L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF76_MASK                          0x00001000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF77_MASK                          0x00002000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF78_MASK                          0x00004000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF79_MASK                          0x00008000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF80_MASK                          0x00010000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF81_MASK                          0x00020000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF82_MASK                          0x00040000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF83_MASK                          0x00080000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF84_MASK                          0x00100000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF85_MASK                          0x00200000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF86_MASK                          0x00400000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF87_MASK                          0x00800000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF88_MASK                          0x01000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF89_MASK                          0x02000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF90_MASK                          0x04000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF91_MASK                          0x08000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF92_MASK                          0x10000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF93_MASK                          0x20000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF94_MASK                          0x40000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH2__UR_ATOMIC_LENGTH_VF95_MASK                          0x80000000L
+//BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF96__SHIFT                        0x0
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF97__SHIFT                        0x1
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF98__SHIFT                        0x2
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF99__SHIFT                        0x3
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF100__SHIFT                       0x4
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF101__SHIFT                       0x5
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF102__SHIFT                       0x6
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF103__SHIFT                       0x7
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF104__SHIFT                       0x8
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF105__SHIFT                       0x9
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF106__SHIFT                       0xa
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF107__SHIFT                       0xb
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF108__SHIFT                       0xc
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF109__SHIFT                       0xd
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF110__SHIFT                       0xe
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF111__SHIFT                       0xf
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF112__SHIFT                       0x10
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF113__SHIFT                       0x11
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF114__SHIFT                       0x12
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF115__SHIFT                       0x13
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF116__SHIFT                       0x14
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF117__SHIFT                       0x15
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF118__SHIFT                       0x16
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF119__SHIFT                       0x17
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF120__SHIFT                       0x18
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF121__SHIFT                       0x19
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF122__SHIFT                       0x1a
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF123__SHIFT                       0x1b
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF124__SHIFT                       0x1c
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF125__SHIFT                       0x1d
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF126__SHIFT                       0x1e
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF127__SHIFT                       0x1f
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF96_MASK                          0x00000001L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF97_MASK                          0x00000002L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF98_MASK                          0x00000004L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF99_MASK                          0x00000008L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF100_MASK                         0x00000010L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF101_MASK                         0x00000020L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF102_MASK                         0x00000040L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF103_MASK                         0x00000080L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF104_MASK                         0x00000100L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF105_MASK                         0x00000200L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF106_MASK                         0x00000400L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF107_MASK                         0x00000800L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF108_MASK                         0x00001000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF109_MASK                         0x00002000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF110_MASK                         0x00004000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF111_MASK                         0x00008000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF112_MASK                         0x00010000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF113_MASK                         0x00020000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF114_MASK                         0x00040000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF115_MASK                         0x00080000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF116_MASK                         0x00100000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF117_MASK                         0x00200000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF118_MASK                         0x00400000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF119_MASK                         0x00800000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF120_MASK                         0x01000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF121_MASK                         0x02000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF122_MASK                         0x04000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF123_MASK                         0x08000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF124_MASK                         0x10000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF125_MASK                         0x20000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF126_MASK                         0x40000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_LENGTH3__UR_ATOMIC_LENGTH_VF127_MASK                         0x80000000L
+//BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF0__SHIFT                                 0x0
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF1__SHIFT                                 0x1
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF2__SHIFT                                 0x2
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF3__SHIFT                                 0x3
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF4__SHIFT                                 0x4
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF5__SHIFT                                 0x5
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF6__SHIFT                                 0x6
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF7__SHIFT                                 0x7
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF8__SHIFT                                 0x8
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF9__SHIFT                                 0x9
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF10__SHIFT                                0xa
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF11__SHIFT                                0xb
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF12__SHIFT                                0xc
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF13__SHIFT                                0xd
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF14__SHIFT                                0xe
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF15__SHIFT                                0xf
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF16__SHIFT                                0x10
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF17__SHIFT                                0x11
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF18__SHIFT                                0x12
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF19__SHIFT                                0x13
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF20__SHIFT                                0x14
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF21__SHIFT                                0x15
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF22__SHIFT                                0x16
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF23__SHIFT                                0x17
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF24__SHIFT                                0x18
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF25__SHIFT                                0x19
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF26__SHIFT                                0x1a
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF27__SHIFT                                0x1b
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF28__SHIFT                                0x1c
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF29__SHIFT                                0x1d
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF30__SHIFT                                0x1e
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF31__SHIFT                                0x1f
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF0_MASK                                   0x00000001L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF1_MASK                                   0x00000002L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF2_MASK                                   0x00000004L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF3_MASK                                   0x00000008L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF4_MASK                                   0x00000010L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF5_MASK                                   0x00000020L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF6_MASK                                   0x00000040L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF7_MASK                                   0x00000080L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF8_MASK                                   0x00000100L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF9_MASK                                   0x00000200L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF10_MASK                                  0x00000400L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF11_MASK                                  0x00000800L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF12_MASK                                  0x00001000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF13_MASK                                  0x00002000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF14_MASK                                  0x00004000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF15_MASK                                  0x00008000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF16_MASK                                  0x00010000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF17_MASK                                  0x00020000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF18_MASK                                  0x00040000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF19_MASK                                  0x00080000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF20_MASK                                  0x00100000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF21_MASK                                  0x00200000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF22_MASK                                  0x00400000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF23_MASK                                  0x00800000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF24_MASK                                  0x01000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF25_MASK                                  0x02000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF26_MASK                                  0x04000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF27_MASK                                  0x08000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF28_MASK                                  0x10000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF29_MASK                                  0x20000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF30_MASK                                  0x40000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR0__UR_ATOMIC_NR_VF31_MASK                                  0x80000000L
+//BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF32__SHIFT                                0x0
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF33__SHIFT                                0x1
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF34__SHIFT                                0x2
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF35__SHIFT                                0x3
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF36__SHIFT                                0x4
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF37__SHIFT                                0x5
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF38__SHIFT                                0x6
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF39__SHIFT                                0x7
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF40__SHIFT                                0x8
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF41__SHIFT                                0x9
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF42__SHIFT                                0xa
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF43__SHIFT                                0xb
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF44__SHIFT                                0xc
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF45__SHIFT                                0xd
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF46__SHIFT                                0xe
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF47__SHIFT                                0xf
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF48__SHIFT                                0x10
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF49__SHIFT                                0x11
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF50__SHIFT                                0x12
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF51__SHIFT                                0x13
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF52__SHIFT                                0x14
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF53__SHIFT                                0x15
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF54__SHIFT                                0x16
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF55__SHIFT                                0x17
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF56__SHIFT                                0x18
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF57__SHIFT                                0x19
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF58__SHIFT                                0x1a
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF59__SHIFT                                0x1b
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF60__SHIFT                                0x1c
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF61__SHIFT                                0x1d
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF62__SHIFT                                0x1e
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF63__SHIFT                                0x1f
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF32_MASK                                  0x00000001L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF33_MASK                                  0x00000002L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF34_MASK                                  0x00000004L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF35_MASK                                  0x00000008L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF36_MASK                                  0x00000010L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF37_MASK                                  0x00000020L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF38_MASK                                  0x00000040L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF39_MASK                                  0x00000080L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF40_MASK                                  0x00000100L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF41_MASK                                  0x00000200L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF42_MASK                                  0x00000400L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF43_MASK                                  0x00000800L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF44_MASK                                  0x00001000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF45_MASK                                  0x00002000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF46_MASK                                  0x00004000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF47_MASK                                  0x00008000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF48_MASK                                  0x00010000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF49_MASK                                  0x00020000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF50_MASK                                  0x00040000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF51_MASK                                  0x00080000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF52_MASK                                  0x00100000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF53_MASK                                  0x00200000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF54_MASK                                  0x00400000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF55_MASK                                  0x00800000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF56_MASK                                  0x01000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF57_MASK                                  0x02000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF58_MASK                                  0x04000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF59_MASK                                  0x08000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF60_MASK                                  0x10000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF61_MASK                                  0x20000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF62_MASK                                  0x40000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR1__UR_ATOMIC_NR_VF63_MASK                                  0x80000000L
+//BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF64__SHIFT                                0x0
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF65__SHIFT                                0x1
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF66__SHIFT                                0x2
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF67__SHIFT                                0x3
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF68__SHIFT                                0x4
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF69__SHIFT                                0x5
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF70__SHIFT                                0x6
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF71__SHIFT                                0x7
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF72__SHIFT                                0x8
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF73__SHIFT                                0x9
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF74__SHIFT                                0xa
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF75__SHIFT                                0xb
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF76__SHIFT                                0xc
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF77__SHIFT                                0xd
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF78__SHIFT                                0xe
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF79__SHIFT                                0xf
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF80__SHIFT                                0x10
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF81__SHIFT                                0x11
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF82__SHIFT                                0x12
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF83__SHIFT                                0x13
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF84__SHIFT                                0x14
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF85__SHIFT                                0x15
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF86__SHIFT                                0x16
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF87__SHIFT                                0x17
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF88__SHIFT                                0x18
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF89__SHIFT                                0x19
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF90__SHIFT                                0x1a
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF91__SHIFT                                0x1b
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF92__SHIFT                                0x1c
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF93__SHIFT                                0x1d
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF94__SHIFT                                0x1e
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF95__SHIFT                                0x1f
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF64_MASK                                  0x00000001L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF65_MASK                                  0x00000002L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF66_MASK                                  0x00000004L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF67_MASK                                  0x00000008L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF68_MASK                                  0x00000010L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF69_MASK                                  0x00000020L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF70_MASK                                  0x00000040L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF71_MASK                                  0x00000080L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF72_MASK                                  0x00000100L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF73_MASK                                  0x00000200L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF74_MASK                                  0x00000400L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF75_MASK                                  0x00000800L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF76_MASK                                  0x00001000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF77_MASK                                  0x00002000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF78_MASK                                  0x00004000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF79_MASK                                  0x00008000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF80_MASK                                  0x00010000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF81_MASK                                  0x00020000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF82_MASK                                  0x00040000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF83_MASK                                  0x00080000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF84_MASK                                  0x00100000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF85_MASK                                  0x00200000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF86_MASK                                  0x00400000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF87_MASK                                  0x00800000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF88_MASK                                  0x01000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF89_MASK                                  0x02000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF90_MASK                                  0x04000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF91_MASK                                  0x08000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF92_MASK                                  0x10000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF93_MASK                                  0x20000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF94_MASK                                  0x40000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR2__UR_ATOMIC_NR_VF95_MASK                                  0x80000000L
+//BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF96__SHIFT                                0x0
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF97__SHIFT                                0x1
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF98__SHIFT                                0x2
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF99__SHIFT                                0x3
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF100__SHIFT                               0x4
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF101__SHIFT                               0x5
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF102__SHIFT                               0x6
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF103__SHIFT                               0x7
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF104__SHIFT                               0x8
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF105__SHIFT                               0x9
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF106__SHIFT                               0xa
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF107__SHIFT                               0xb
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF108__SHIFT                               0xc
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF109__SHIFT                               0xd
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF110__SHIFT                               0xe
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF111__SHIFT                               0xf
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF112__SHIFT                               0x10
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF113__SHIFT                               0x11
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF114__SHIFT                               0x12
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF115__SHIFT                               0x13
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF116__SHIFT                               0x14
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF117__SHIFT                               0x15
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF118__SHIFT                               0x16
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF119__SHIFT                               0x17
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF120__SHIFT                               0x18
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF121__SHIFT                               0x19
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF122__SHIFT                               0x1a
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF123__SHIFT                               0x1b
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF124__SHIFT                               0x1c
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF125__SHIFT                               0x1d
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF126__SHIFT                               0x1e
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF127__SHIFT                               0x1f
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF96_MASK                                  0x00000001L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF97_MASK                                  0x00000002L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF98_MASK                                  0x00000004L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF99_MASK                                  0x00000008L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF100_MASK                                 0x00000010L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF101_MASK                                 0x00000020L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF102_MASK                                 0x00000040L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF103_MASK                                 0x00000080L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF104_MASK                                 0x00000100L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF105_MASK                                 0x00000200L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF106_MASK                                 0x00000400L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF107_MASK                                 0x00000800L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF108_MASK                                 0x00001000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF109_MASK                                 0x00002000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF110_MASK                                 0x00004000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF111_MASK                                 0x00008000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF112_MASK                                 0x00010000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF113_MASK                                 0x00020000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF114_MASK                                 0x00040000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF115_MASK                                 0x00080000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF116_MASK                                 0x00100000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF117_MASK                                 0x00200000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF118_MASK                                 0x00400000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF119_MASK                                 0x00800000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF120_MASK                                 0x01000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF121_MASK                                 0x02000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF122_MASK                                 0x04000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF123_MASK                                 0x08000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF124_MASK                                 0x10000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF125_MASK                                 0x20000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF126_MASK                                 0x40000000L
+#define BIF_MISC_PFVF_DEV0_EPF1_BIF_VF_UR_ATOMIC_NR3__UR_ATOMIC_NR_VF127_MASK                                 0x80000000L
+
+
+// addressBlock: nbif0_nbif0_bif_trap_bif_trap_regblk
+//NBIF_TRAP_NP_STATUS
+#define NBIF_TRAP_NP_STATUS__NBIF_TRAP_NP_TrapReqValid__SHIFT                                                 0x0
+#define NBIF_TRAP_NP_STATUS__NBIF_TRAP_NP_TrapNumber__SHIFT                                                   0x8
+#define NBIF_TRAP_NP_STATUS__NBIF_TRAP_NP_TrapS2Vld__SHIFT                                                    0xc
+#define NBIF_TRAP_NP_STATUS__NBIF_TRAP_NP_TrapS2Number__SHIFT                                                 0x10
+#define NBIF_TRAP_NP_STATUS__NBIF_TRAP_NP_TrapReqValid_MASK                                                   0x00000001L
+#define NBIF_TRAP_NP_STATUS__NBIF_TRAP_NP_TrapNumber_MASK                                                     0x00000F00L
+#define NBIF_TRAP_NP_STATUS__NBIF_TRAP_NP_TrapS2Vld_MASK                                                      0x00001000L
+#define NBIF_TRAP_NP_STATUS__NBIF_TRAP_NP_TrapS2Number_MASK                                                   0x01FF0000L
+//NBIF_TRAP_NP_REQUEST0
+#define NBIF_TRAP_NP_REQUEST0__NBIF_TRAP_NP_TrapReqAddrLo__SHIFT                                              0x2
+#define NBIF_TRAP_NP_REQUEST0__NBIF_TRAP_NP_TrapReqAddrLo_MASK                                                0xFFFFFFFCL
+//NBIF_TRAP_NP_REQUEST1
+#define NBIF_TRAP_NP_REQUEST1__NBIF_TRAP_NP_TrapReqAddrHi__SHIFT                                              0x0
+#define NBIF_TRAP_NP_REQUEST1__NBIF_TRAP_NP_TrapReqAddrHi_MASK                                                0xFFFFFFFFL
+//NBIF_TRAP_NP_REQUEST2
+#define NBIF_TRAP_NP_REQUEST2__NBIF_TRAP_NP_TrapReqCmd__SHIFT                                                 0x0
+#define NBIF_TRAP_NP_REQUEST2__NBIF_TRAP_NP_TrapReqAttr__SHIFT                                                0x8
+#define NBIF_TRAP_NP_REQUEST2__NBIF_TRAP_NP_TrapReqLen__SHIFT                                                 0x10
+#define NBIF_TRAP_NP_REQUEST2__NBIF_TRAP_NP_TrapReqCmd_MASK                                                   0x0000003FL
+#define NBIF_TRAP_NP_REQUEST2__NBIF_TRAP_NP_TrapReqAttr_MASK                                                  0x0000FF00L
+#define NBIF_TRAP_NP_REQUEST2__NBIF_TRAP_NP_TrapReqLen_MASK                                                   0x003F0000L
+//NBIF_TRAP_NP_REQUEST3
+#define NBIF_TRAP_NP_REQUEST3__NBIF_TRAP_NP_TrapReqVC__SHIFT                                                  0x0
+#define NBIF_TRAP_NP_REQUEST3__NBIF_TRAP_NP_TrapReqBlockLevel__SHIFT                                          0x4
+#define NBIF_TRAP_NP_REQUEST3__NBIF_TRAP_NP_TrapReqChain__SHIFT                                               0x6
+#define NBIF_TRAP_NP_REQUEST3__NBIF_TRAP_NP_TrapReqIO__SHIFT                                                  0x7
+#define NBIF_TRAP_NP_REQUEST3__NBIF_TRAP_NP_TrapReqPassPW__SHIFT                                              0x8
+#define NBIF_TRAP_NP_REQUEST3__NBIF_TRAP_NP_TrapReqRspPassPW__SHIFT                                           0x9
+#define NBIF_TRAP_NP_REQUEST3__NBIF_TRAP_NP_TrapReqUnitID__SHIFT                                              0x10
+#define NBIF_TRAP_NP_REQUEST3__NBIF_TRAP_NP_TrapReqVC_MASK                                                    0x00000007L
+#define NBIF_TRAP_NP_REQUEST3__NBIF_TRAP_NP_TrapReqBlockLevel_MASK                                            0x00000030L
+#define NBIF_TRAP_NP_REQUEST3__NBIF_TRAP_NP_TrapReqChain_MASK                                                 0x00000040L
+#define NBIF_TRAP_NP_REQUEST3__NBIF_TRAP_NP_TrapReqIO_MASK                                                    0x00000080L
+#define NBIF_TRAP_NP_REQUEST3__NBIF_TRAP_NP_TrapReqPassPW_MASK                                                0x00000100L
+#define NBIF_TRAP_NP_REQUEST3__NBIF_TRAP_NP_TrapReqRspPassPW_MASK                                             0x00000200L
+#define NBIF_TRAP_NP_REQUEST3__NBIF_TRAP_NP_TrapReqUnitID_MASK                                                0x07FF0000L
+//NBIF_TRAP_NP_REQUEST4
+#define NBIF_TRAP_NP_REQUEST4__NBIF_TRAP_NP_TrapReqSecLevel__SHIFT                                            0x0
+#define NBIF_TRAP_NP_REQUEST4__NBIF_TRAP_NP_TrapReqSecLevel_MASK                                              0x0000000FL
+//NBIF_TRAP_NP_REQUEST5
+#define NBIF_TRAP_NP_REQUEST5__NBIF_TRAP_NP_TrapReqDataVC__SHIFT                                              0x0
+#define NBIF_TRAP_NP_REQUEST5__NBIF_TRAP_NP_TrapReqDataErr__SHIFT                                             0x4
+#define NBIF_TRAP_NP_REQUEST5__NBIF_TRAP_NP_TrapReqDataVC_MASK                                                0x00000007L
+#define NBIF_TRAP_NP_REQUEST5__NBIF_TRAP_NP_TrapReqDataErr_MASK                                               0x000000F0L
+//NBIF_TRAP_NP_REQUEST6
+#define NBIF_TRAP_NP_REQUEST6__NBIF_TRAP_NP_TrapReqDataParity__SHIFT                                          0x0
+#define NBIF_TRAP_NP_REQUEST6__NBIF_TRAP_NP_TrapReqDataParity_MASK                                            0xFFFFFFFFL
+//NBIF_TRAP_NP_REQUEST_DATASTRB0
+#define NBIF_TRAP_NP_REQUEST_DATASTRB0__NBIF_TRAP_NP_TrapReqDataBytEn0__SHIFT                                 0x0
+#define NBIF_TRAP_NP_REQUEST_DATASTRB0__NBIF_TRAP_NP_TrapReqDataBytEn0_MASK                                   0xFFFFFFFFL
+//NBIF_TRAP_NP_REQUEST_DATASTRB1
+#define NBIF_TRAP_NP_REQUEST_DATASTRB1__NBIF_TRAP_NP_TrapReqDataBytEn1__SHIFT                                 0x0
+#define NBIF_TRAP_NP_REQUEST_DATASTRB1__NBIF_TRAP_NP_TrapReqDataBytEn1_MASK                                   0xFFFFFFFFL
+//NBIF_TRAP_NP_REQUEST_DATASTRB2
+#define NBIF_TRAP_NP_REQUEST_DATASTRB2__NBIF_TRAP_NP_TrapReqDataBytEn2__SHIFT                                 0x0
+#define NBIF_TRAP_NP_REQUEST_DATASTRB2__NBIF_TRAP_NP_TrapReqDataBytEn2_MASK                                   0xFFFFFFFFL
+//NBIF_TRAP_NP_REQUEST_DATASTRB3
+#define NBIF_TRAP_NP_REQUEST_DATASTRB3__NBIF_TRAP_NP_TrapReqDataBytEn3__SHIFT                                 0x0
+#define NBIF_TRAP_NP_REQUEST_DATASTRB3__NBIF_TRAP_NP_TrapReqDataBytEn3_MASK                                   0xFFFFFFFFL
+//NBIF_TRAP_NP_REQUEST_DATASTRB4
+#define NBIF_TRAP_NP_REQUEST_DATASTRB4__NBIF_TRAP_NP_TrapReqDataBytEn4__SHIFT                                 0x0
+#define NBIF_TRAP_NP_REQUEST_DATASTRB4__NBIF_TRAP_NP_TrapReqDataBytEn4_MASK                                   0xFFFFFFFFL
+//NBIF_TRAP_NP_REQUEST_DATASTRB5
+#define NBIF_TRAP_NP_REQUEST_DATASTRB5__NBIF_TRAP_NP_TrapReqDataBytEn5__SHIFT                                 0x0
+#define NBIF_TRAP_NP_REQUEST_DATASTRB5__NBIF_TRAP_NP_TrapReqDataBytEn5_MASK                                   0xFFFFFFFFL
+//NBIF_TRAP_NP_REQUEST_DATASTRB6
+#define NBIF_TRAP_NP_REQUEST_DATASTRB6__NBIF_TRAP_NP_TrapReqDataBytEn6__SHIFT                                 0x0
+#define NBIF_TRAP_NP_REQUEST_DATASTRB6__NBIF_TRAP_NP_TrapReqDataBytEn6_MASK                                   0xFFFFFFFFL
+//NBIF_TRAP_NP_REQUEST_DATASTRB7
+#define NBIF_TRAP_NP_REQUEST_DATASTRB7__NBIF_TRAP_NP_TrapReqDataBytEn7__SHIFT                                 0x0
+#define NBIF_TRAP_NP_REQUEST_DATASTRB7__NBIF_TRAP_NP_TrapReqDataBytEn7_MASK                                   0xFFFFFFFFL
+//NBIF_TRAP_NP_REQUEST_DATA0
+#define NBIF_TRAP_NP_REQUEST_DATA0__NBIF_TRAP_NP_TrapReqData0__SHIFT                                          0x0
+#define NBIF_TRAP_NP_REQUEST_DATA0__NBIF_TRAP_NP_TrapReqData0_MASK                                            0xFFFFFFFFL
+//NBIF_TRAP_NP_REQUEST_DATA1
+#define NBIF_TRAP_NP_REQUEST_DATA1__NBIF_TRAP_NP_TrapReqData1__SHIFT                                          0x0
+#define NBIF_TRAP_NP_REQUEST_DATA1__NBIF_TRAP_NP_TrapReqData1_MASK                                            0xFFFFFFFFL
+//NBIF_TRAP_NP_REQUEST_DATA2
+#define NBIF_TRAP_NP_REQUEST_DATA2__NBIF_TRAP_NP_TrapReqData2__SHIFT                                          0x0
+#define NBIF_TRAP_NP_REQUEST_DATA2__NBIF_TRAP_NP_TrapReqData2_MASK                                            0xFFFFFFFFL
+//NBIF_TRAP_NP_REQUEST_DATA3
+#define NBIF_TRAP_NP_REQUEST_DATA3__NBIF_TRAP_NP_TrapReqData3__SHIFT                                          0x0
+#define NBIF_TRAP_NP_REQUEST_DATA3__NBIF_TRAP_NP_TrapReqData3_MASK                                            0xFFFFFFFFL
+//NBIF_TRAP_NP_REQUEST_DATA4
+#define NBIF_TRAP_NP_REQUEST_DATA4__NBIF_TRAP_NP_TrapReqData4__SHIFT                                          0x0
+#define NBIF_TRAP_NP_REQUEST_DATA4__NBIF_TRAP_NP_TrapReqData4_MASK                                            0xFFFFFFFFL
+//NBIF_TRAP_NP_REQUEST_DATA5
+#define NBIF_TRAP_NP_REQUEST_DATA5__NBIF_TRAP_NP_TrapReqData5__SHIFT                                          0x0
+#define NBIF_TRAP_NP_REQUEST_DATA5__NBIF_TRAP_NP_TrapReqData5_MASK                                            0xFFFFFFFFL
+//NBIF_TRAP_NP_REQUEST_DATA6
+#define NBIF_TRAP_NP_REQUEST_DATA6__NBIF_TRAP_NP_TrapReqData6__SHIFT                                          0x0
+#define NBIF_TRAP_NP_REQUEST_DATA6__NBIF_TRAP_NP_TrapReqData6_MASK                                            0xFFFFFFFFL
+//NBIF_TRAP_NP_REQUEST_DATA7
+#define NBIF_TRAP_NP_REQUEST_DATA7__NBIF_TRAP_NP_TrapReqData7__SHIFT                                          0x0
+#define NBIF_TRAP_NP_REQUEST_DATA7__NBIF_TRAP_NP_TrapReqData7_MASK                                            0xFFFFFFFFL
+//NBIF_TRAP_NP_REQUEST_DATA8
+#define NBIF_TRAP_NP_REQUEST_DATA8__NBIF_TRAP_NP_TrapReqData8__SHIFT                                          0x0
+#define NBIF_TRAP_NP_REQUEST_DATA8__NBIF_TRAP_NP_TrapReqData8_MASK                                            0xFFFFFFFFL
+//NBIF_TRAP_NP_REQUEST_DATA9
+#define NBIF_TRAP_NP_REQUEST_DATA9__NBIF_TRAP_NP_TrapReqData9__SHIFT                                          0x0
+#define NBIF_TRAP_NP_REQUEST_DATA9__NBIF_TRAP_NP_TrapReqData9_MASK                                            0xFFFFFFFFL
+//NBIF_TRAP_NP_REQUEST_DATA10
+#define NBIF_TRAP_NP_REQUEST_DATA10__NBIF_TRAP_NP_TrapReqData10__SHIFT                                        0x0
+#define NBIF_TRAP_NP_REQUEST_DATA10__NBIF_TRAP_NP_TrapReqData10_MASK                                          0xFFFFFFFFL
+//NBIF_TRAP_NP_REQUEST_DATA11
+#define NBIF_TRAP_NP_REQUEST_DATA11__NBIF_TRAP_NP_TrapReqData11__SHIFT                                        0x0
+#define NBIF_TRAP_NP_REQUEST_DATA11__NBIF_TRAP_NP_TrapReqData11_MASK                                          0xFFFFFFFFL
+//NBIF_TRAP_NP_REQUEST_DATA12
+#define NBIF_TRAP_NP_REQUEST_DATA12__NBIF_TRAP_NP_TrapReqData12__SHIFT                                        0x0
+#define NBIF_TRAP_NP_REQUEST_DATA12__NBIF_TRAP_NP_TrapReqData12_MASK                                          0xFFFFFFFFL
+//NBIF_TRAP_NP_REQUEST_DATA13
+#define NBIF_TRAP_NP_REQUEST_DATA13__NBIF_TRAP_NP_TrapReqData13__SHIFT                                        0x0
+#define NBIF_TRAP_NP_REQUEST_DATA13__NBIF_TRAP_NP_TrapReqData13_MASK                                          0xFFFFFFFFL
+//NBIF_TRAP_NP_REQUEST_DATA14
+#define NBIF_TRAP_NP_REQUEST_DATA14__NBIF_TRAP_NP_TrapReqData14__SHIFT                                        0x0
+#define NBIF_TRAP_NP_REQUEST_DATA14__NBIF_TRAP_NP_TrapReqData14_MASK                                          0xFFFFFFFFL
+//NBIF_TRAP_NP_REQUEST_DATA15
+#define NBIF_TRAP_NP_REQUEST_DATA15__NBIF_TRAP_NP_TrapReqData15__SHIFT                                        0x0
+#define NBIF_TRAP_NP_REQUEST_DATA15__NBIF_TRAP_NP_TrapReqData15_MASK                                          0xFFFFFFFFL
+//NBIF_TRAP_NP_REQUEST_DATA16
+#define NBIF_TRAP_NP_REQUEST_DATA16__NBIF_TRAP_NP_TrapReqData16__SHIFT                                        0x0
+#define NBIF_TRAP_NP_REQUEST_DATA16__NBIF_TRAP_NP_TrapReqData16_MASK                                          0xFFFFFFFFL
+//NBIF_TRAP_NP_REQUEST_DATA17
+#define NBIF_TRAP_NP_REQUEST_DATA17__NBIF_TRAP_NP_TrapReqData17__SHIFT                                        0x0
+#define NBIF_TRAP_NP_REQUEST_DATA17__NBIF_TRAP_NP_TrapReqData17_MASK                                          0xFFFFFFFFL
+//NBIF_TRAP_NP_REQUEST_DATA18
+#define NBIF_TRAP_NP_REQUEST_DATA18__NBIF_TRAP_NP_TrapReqData18__SHIFT                                        0x0
+#define NBIF_TRAP_NP_REQUEST_DATA18__NBIF_TRAP_NP_TrapReqData18_MASK                                          0xFFFFFFFFL
+//NBIF_TRAP_NP_REQUEST_DATA19
+#define NBIF_TRAP_NP_REQUEST_DATA19__NBIF_TRAP_NP_TrapReqData19__SHIFT                                        0x0
+#define NBIF_TRAP_NP_REQUEST_DATA19__NBIF_TRAP_NP_TrapReqData19_MASK                                          0xFFFFFFFFL
+//NBIF_TRAP_NP_REQUEST_DATA20
+#define NBIF_TRAP_NP_REQUEST_DATA20__NBIF_TRAP_NP_TrapReqData20__SHIFT                                        0x0
+#define NBIF_TRAP_NP_REQUEST_DATA20__NBIF_TRAP_NP_TrapReqData20_MASK                                          0xFFFFFFFFL
+//NBIF_TRAP_NP_REQUEST_DATA21
+#define NBIF_TRAP_NP_REQUEST_DATA21__NBIF_TRAP_NP_TrapReqData21__SHIFT                                        0x0
+#define NBIF_TRAP_NP_REQUEST_DATA21__NBIF_TRAP_NP_TrapReqData21_MASK                                          0xFFFFFFFFL
+//NBIF_TRAP_NP_REQUEST_DATA22
+#define NBIF_TRAP_NP_REQUEST_DATA22__NBIF_TRAP_NP_TrapReqData22__SHIFT                                        0x0
+#define NBIF_TRAP_NP_REQUEST_DATA22__NBIF_TRAP_NP_TrapReqData22_MASK                                          0xFFFFFFFFL
+//NBIF_TRAP_NP_REQUEST_DATA23
+#define NBIF_TRAP_NP_REQUEST_DATA23__NBIF_TRAP_NP_TrapReqData23__SHIFT                                        0x0
+#define NBIF_TRAP_NP_REQUEST_DATA23__NBIF_TRAP_NP_TrapReqData23_MASK                                          0xFFFFFFFFL
+//NBIF_TRAP_NP_REQUEST_DATA24
+#define NBIF_TRAP_NP_REQUEST_DATA24__NBIF_TRAP_NP_TrapReqData24__SHIFT                                        0x0
+#define NBIF_TRAP_NP_REQUEST_DATA24__NBIF_TRAP_NP_TrapReqData24_MASK                                          0xFFFFFFFFL
+//NBIF_TRAP_NP_REQUEST_DATA25
+#define NBIF_TRAP_NP_REQUEST_DATA25__NBIF_TRAP_NP_TrapReqData25__SHIFT                                        0x0
+#define NBIF_TRAP_NP_REQUEST_DATA25__NBIF_TRAP_NP_TrapReqData25_MASK                                          0xFFFFFFFFL
+//NBIF_TRAP_NP_REQUEST_DATA26
+#define NBIF_TRAP_NP_REQUEST_DATA26__NBIF_TRAP_NP_TrapReqData26__SHIFT                                        0x0
+#define NBIF_TRAP_NP_REQUEST_DATA26__NBIF_TRAP_NP_TrapReqData26_MASK                                          0xFFFFFFFFL
+//NBIF_TRAP_NP_REQUEST_DATA27
+#define NBIF_TRAP_NP_REQUEST_DATA27__NBIF_TRAP_NP_TrapReqData27__SHIFT                                        0x0
+#define NBIF_TRAP_NP_REQUEST_DATA27__NBIF_TRAP_NP_TrapReqData27_MASK                                          0xFFFFFFFFL
+//NBIF_TRAP_NP_REQUEST_DATA28
+#define NBIF_TRAP_NP_REQUEST_DATA28__NBIF_TRAP_NP_TrapReqData28__SHIFT                                        0x0
+#define NBIF_TRAP_NP_REQUEST_DATA28__NBIF_TRAP_NP_TrapReqData28_MASK                                          0xFFFFFFFFL
+//NBIF_TRAP_NP_REQUEST_DATA29
+#define NBIF_TRAP_NP_REQUEST_DATA29__NBIF_TRAP_NP_TrapReqData29__SHIFT                                        0x0
+#define NBIF_TRAP_NP_REQUEST_DATA29__NBIF_TRAP_NP_TrapReqData29_MASK                                          0xFFFFFFFFL
+//NBIF_TRAP_NP_REQUEST_DATA30
+#define NBIF_TRAP_NP_REQUEST_DATA30__NBIF_TRAP_NP_TrapReqData30__SHIFT                                        0x0
+#define NBIF_TRAP_NP_REQUEST_DATA30__NBIF_TRAP_NP_TrapReqData30_MASK                                          0xFFFFFFFFL
+//NBIF_TRAP_NP_REQUEST_DATA31
+#define NBIF_TRAP_NP_REQUEST_DATA31__NBIF_TRAP_NP_TrapReqData31__SHIFT                                        0x0
+#define NBIF_TRAP_NP_REQUEST_DATA31__NBIF_TRAP_NP_TrapReqData31_MASK                                          0xFFFFFFFFL
+//NBIF_TRAP_NP_REQUEST_DATA32
+#define NBIF_TRAP_NP_REQUEST_DATA32__NBIF_TRAP_NP_TrapReqData32__SHIFT                                        0x0
+#define NBIF_TRAP_NP_REQUEST_DATA32__NBIF_TRAP_NP_TrapReqData32_MASK                                          0xFFFFFFFFL
+//NBIF_TRAP_NP_REQUEST_DATA33
+#define NBIF_TRAP_NP_REQUEST_DATA33__NBIF_TRAP_NP_TrapReqData33__SHIFT                                        0x0
+#define NBIF_TRAP_NP_REQUEST_DATA33__NBIF_TRAP_NP_TrapReqData33_MASK                                          0xFFFFFFFFL
+//NBIF_TRAP_NP_REQUEST_DATA34
+#define NBIF_TRAP_NP_REQUEST_DATA34__NBIF_TRAP_NP_TrapReqData34__SHIFT                                        0x0
+#define NBIF_TRAP_NP_REQUEST_DATA34__NBIF_TRAP_NP_TrapReqData34_MASK                                          0xFFFFFFFFL
+//NBIF_TRAP_NP_REQUEST_DATA35
+#define NBIF_TRAP_NP_REQUEST_DATA35__NBIF_TRAP_NP_TrapReqData35__SHIFT                                        0x0
+#define NBIF_TRAP_NP_REQUEST_DATA35__NBIF_TRAP_NP_TrapReqData35_MASK                                          0xFFFFFFFFL
+//NBIF_TRAP_NP_REQUEST_DATA36
+#define NBIF_TRAP_NP_REQUEST_DATA36__NBIF_TRAP_NP_TrapReqData36__SHIFT                                        0x0
+#define NBIF_TRAP_NP_REQUEST_DATA36__NBIF_TRAP_NP_TrapReqData36_MASK                                          0xFFFFFFFFL
+//NBIF_TRAP_NP_REQUEST_DATA37
+#define NBIF_TRAP_NP_REQUEST_DATA37__NBIF_TRAP_NP_TrapReqData37__SHIFT                                        0x0
+#define NBIF_TRAP_NP_REQUEST_DATA37__NBIF_TRAP_NP_TrapReqData37_MASK                                          0xFFFFFFFFL
+//NBIF_TRAP_NP_REQUEST_DATA38
+#define NBIF_TRAP_NP_REQUEST_DATA38__NBIF_TRAP_NP_TrapReqData38__SHIFT                                        0x0
+#define NBIF_TRAP_NP_REQUEST_DATA38__NBIF_TRAP_NP_TrapReqData38_MASK                                          0xFFFFFFFFL
+//NBIF_TRAP_NP_REQUEST_DATA39
+#define NBIF_TRAP_NP_REQUEST_DATA39__NBIF_TRAP_NP_TrapReqData39__SHIFT                                        0x0
+#define NBIF_TRAP_NP_REQUEST_DATA39__NBIF_TRAP_NP_TrapReqData39_MASK                                          0xFFFFFFFFL
+//NBIF_TRAP_NP_REQUEST_DATA40
+#define NBIF_TRAP_NP_REQUEST_DATA40__NBIF_TRAP_NP_TrapReqData40__SHIFT                                        0x0
+#define NBIF_TRAP_NP_REQUEST_DATA40__NBIF_TRAP_NP_TrapReqData40_MASK                                          0xFFFFFFFFL
+//NBIF_TRAP_NP_REQUEST_DATA41
+#define NBIF_TRAP_NP_REQUEST_DATA41__NBIF_TRAP_NP_TrapReqData41__SHIFT                                        0x0
+#define NBIF_TRAP_NP_REQUEST_DATA41__NBIF_TRAP_NP_TrapReqData41_MASK                                          0xFFFFFFFFL
+//NBIF_TRAP_NP_REQUEST_DATA42
+#define NBIF_TRAP_NP_REQUEST_DATA42__NBIF_TRAP_NP_TrapReqData42__SHIFT                                        0x0
+#define NBIF_TRAP_NP_REQUEST_DATA42__NBIF_TRAP_NP_TrapReqData42_MASK                                          0xFFFFFFFFL
+//NBIF_TRAP_NP_REQUEST_DATA43
+#define NBIF_TRAP_NP_REQUEST_DATA43__NBIF_TRAP_NP_TrapReqData43__SHIFT                                        0x0
+#define NBIF_TRAP_NP_REQUEST_DATA43__NBIF_TRAP_NP_TrapReqData43_MASK                                          0xFFFFFFFFL
+//NBIF_TRAP_NP_REQUEST_DATA44
+#define NBIF_TRAP_NP_REQUEST_DATA44__NBIF_TRAP_NP_TrapReqData44__SHIFT                                        0x0
+#define NBIF_TRAP_NP_REQUEST_DATA44__NBIF_TRAP_NP_TrapReqData44_MASK                                          0xFFFFFFFFL
+//NBIF_TRAP_NP_REQUEST_DATA45
+#define NBIF_TRAP_NP_REQUEST_DATA45__NBIF_TRAP_NP_TrapReqData45__SHIFT                                        0x0
+#define NBIF_TRAP_NP_REQUEST_DATA45__NBIF_TRAP_NP_TrapReqData45_MASK                                          0xFFFFFFFFL
+//NBIF_TRAP_NP_REQUEST_DATA46
+#define NBIF_TRAP_NP_REQUEST_DATA46__NBIF_TRAP_NP_TrapReqData46__SHIFT                                        0x0
+#define NBIF_TRAP_NP_REQUEST_DATA46__NBIF_TRAP_NP_TrapReqData46_MASK                                          0xFFFFFFFFL
+//NBIF_TRAP_NP_REQUEST_DATA47
+#define NBIF_TRAP_NP_REQUEST_DATA47__NBIF_TRAP_NP_TrapReqData47__SHIFT                                        0x0
+#define NBIF_TRAP_NP_REQUEST_DATA47__NBIF_TRAP_NP_TrapReqData47_MASK                                          0xFFFFFFFFL
+//NBIF_TRAP_NP_REQUEST_DATA48
+#define NBIF_TRAP_NP_REQUEST_DATA48__NBIF_TRAP_NP_TrapReqData48__SHIFT                                        0x0
+#define NBIF_TRAP_NP_REQUEST_DATA48__NBIF_TRAP_NP_TrapReqData48_MASK                                          0xFFFFFFFFL
+//NBIF_TRAP_NP_REQUEST_DATA49
+#define NBIF_TRAP_NP_REQUEST_DATA49__NBIF_TRAP_NP_TrapReqData49__SHIFT                                        0x0
+#define NBIF_TRAP_NP_REQUEST_DATA49__NBIF_TRAP_NP_TrapReqData49_MASK                                          0xFFFFFFFFL
+//NBIF_TRAP_NP_REQUEST_DATA50
+#define NBIF_TRAP_NP_REQUEST_DATA50__NBIF_TRAP_NP_TrapReqData50__SHIFT                                        0x0
+#define NBIF_TRAP_NP_REQUEST_DATA50__NBIF_TRAP_NP_TrapReqData50_MASK                                          0xFFFFFFFFL
+//NBIF_TRAP_NP_REQUEST_DATA51
+#define NBIF_TRAP_NP_REQUEST_DATA51__NBIF_TRAP_NP_TrapReqData51__SHIFT                                        0x0
+#define NBIF_TRAP_NP_REQUEST_DATA51__NBIF_TRAP_NP_TrapReqData51_MASK                                          0xFFFFFFFFL
+//NBIF_TRAP_NP_REQUEST_DATA52
+#define NBIF_TRAP_NP_REQUEST_DATA52__NBIF_TRAP_NP_TrapReqData52__SHIFT                                        0x0
+#define NBIF_TRAP_NP_REQUEST_DATA52__NBIF_TRAP_NP_TrapReqData52_MASK                                          0xFFFFFFFFL
+//NBIF_TRAP_NP_REQUEST_DATA53
+#define NBIF_TRAP_NP_REQUEST_DATA53__NBIF_TRAP_NP_TrapReqData53__SHIFT                                        0x0
+#define NBIF_TRAP_NP_REQUEST_DATA53__NBIF_TRAP_NP_TrapReqData53_MASK                                          0xFFFFFFFFL
+//NBIF_TRAP_NP_REQUEST_DATA54
+#define NBIF_TRAP_NP_REQUEST_DATA54__NBIF_TRAP_NP_TrapReqData54__SHIFT                                        0x0
+#define NBIF_TRAP_NP_REQUEST_DATA54__NBIF_TRAP_NP_TrapReqData54_MASK                                          0xFFFFFFFFL
+//NBIF_TRAP_NP_REQUEST_DATA55
+#define NBIF_TRAP_NP_REQUEST_DATA55__NBIF_TRAP_NP_TrapReqData55__SHIFT                                        0x0
+#define NBIF_TRAP_NP_REQUEST_DATA55__NBIF_TRAP_NP_TrapReqData55_MASK                                          0xFFFFFFFFL
+//NBIF_TRAP_NP_REQUEST_DATA56
+#define NBIF_TRAP_NP_REQUEST_DATA56__NBIF_TRAP_NP_TrapReqData56__SHIFT                                        0x0
+#define NBIF_TRAP_NP_REQUEST_DATA56__NBIF_TRAP_NP_TrapReqData56_MASK                                          0xFFFFFFFFL
+//NBIF_TRAP_NP_REQUEST_DATA57
+#define NBIF_TRAP_NP_REQUEST_DATA57__NBIF_TRAP_NP_TrapReqData57__SHIFT                                        0x0
+#define NBIF_TRAP_NP_REQUEST_DATA57__NBIF_TRAP_NP_TrapReqData57_MASK                                          0xFFFFFFFFL
+//NBIF_TRAP_NP_REQUEST_DATA58
+#define NBIF_TRAP_NP_REQUEST_DATA58__NBIF_TRAP_NP_TrapReqData58__SHIFT                                        0x0
+#define NBIF_TRAP_NP_REQUEST_DATA58__NBIF_TRAP_NP_TrapReqData58_MASK                                          0xFFFFFFFFL
+//NBIF_TRAP_NP_REQUEST_DATA59
+#define NBIF_TRAP_NP_REQUEST_DATA59__NBIF_TRAP_NP_TrapReqData59__SHIFT                                        0x0
+#define NBIF_TRAP_NP_REQUEST_DATA59__NBIF_TRAP_NP_TrapReqData59_MASK                                          0xFFFFFFFFL
+//NBIF_TRAP_NP_REQUEST_DATA60
+#define NBIF_TRAP_NP_REQUEST_DATA60__NBIF_TRAP_NP_TrapReqData60__SHIFT                                        0x0
+#define NBIF_TRAP_NP_REQUEST_DATA60__NBIF_TRAP_NP_TrapReqData60_MASK                                          0xFFFFFFFFL
+//NBIF_TRAP_NP_REQUEST_DATA61
+#define NBIF_TRAP_NP_REQUEST_DATA61__NBIF_TRAP_NP_TrapReqData61__SHIFT                                        0x0
+#define NBIF_TRAP_NP_REQUEST_DATA61__NBIF_TRAP_NP_TrapReqData61_MASK                                          0xFFFFFFFFL
+//NBIF_TRAP_NP_REQUEST_DATA62
+#define NBIF_TRAP_NP_REQUEST_DATA62__NBIF_TRAP_NP_TrapReqData62__SHIFT                                        0x0
+#define NBIF_TRAP_NP_REQUEST_DATA62__NBIF_TRAP_NP_TrapReqData62_MASK                                          0xFFFFFFFFL
+//NBIF_TRAP_NP_REQUEST_DATA63
+#define NBIF_TRAP_NP_REQUEST_DATA63__NBIF_TRAP_NP_TrapReqData63__SHIFT                                        0x0
+#define NBIF_TRAP_NP_REQUEST_DATA63__NBIF_TRAP_NP_TrapReqData63_MASK                                          0xFFFFFFFFL
+//NBIF_TRAP_NP_RESPONSE_CONTROL
+#define NBIF_TRAP_NP_RESPONSE_CONTROL__NBIF_TRAP_NP_TrapRspTrigger__SHIFT                                     0x0
+#define NBIF_TRAP_NP_RESPONSE_CONTROL__NBIF_TRAP_NP_TrapRspReqPassthru__SHIFT                                 0x1
+#define NBIF_TRAP_NP_RESPONSE_CONTROL__NBIF_TRAP_NP_TrapRspTrigger_MASK                                       0x00000001L
+#define NBIF_TRAP_NP_RESPONSE_CONTROL__NBIF_TRAP_NP_TrapRspReqPassthru_MASK                                   0x00000002L
+//NBIF_TRAP_NP_RESPONSE0
+#define NBIF_TRAP_NP_RESPONSE0__NBIF_TRAP_NP_TrapRspPassPW__SHIFT                                             0x0
+#define NBIF_TRAP_NP_RESPONSE0__NBIF_TRAP_NP_TrapRspStatus__SHIFT                                             0x4
+#define NBIF_TRAP_NP_RESPONSE0__NBIF_TRAP_NP_TrapRspDataStatus__SHIFT                                         0x10
+#define NBIF_TRAP_NP_RESPONSE0__NBIF_TRAP_NP_TrapRspPassPW_MASK                                               0x00000001L
+#define NBIF_TRAP_NP_RESPONSE0__NBIF_TRAP_NP_TrapRspStatus_MASK                                               0x000000F0L
+#define NBIF_TRAP_NP_RESPONSE0__NBIF_TRAP_NP_TrapRspDataStatus_MASK                                           0x00FF0000L
+//NBIF_TRAP_NP_RESPONSE1
+#define NBIF_TRAP_NP_RESPONSE1__NBIF_TRAP_NP_TrapRspCplid__SHIFT                                              0x0
+#define NBIF_TRAP_NP_RESPONSE1__NBIF_TRAP_NP_TrapRspSrcdata__SHIFT                                            0x10
+#define NBIF_TRAP_NP_RESPONSE1__NBIF_TRAP_NP_TrapRspCplid_MASK                                                0x0000FFFFL
+#define NBIF_TRAP_NP_RESPONSE1__NBIF_TRAP_NP_TrapRspSrcdata_MASK                                              0x003F0000L
+//NBIF_TRAP_NP_RESPONSE2
+#define NBIF_TRAP_NP_RESPONSE2__NBIF_TRAP_NP_TrapRspUser0__SHIFT                                              0x0
+#define NBIF_TRAP_NP_RESPONSE2__NBIF_TRAP_NP_TrapRspUser0_MASK                                                0xFFFFFFFFL
+//NBIF_TRAP_NP_RESPONSE3
+#define NBIF_TRAP_NP_RESPONSE3__NBIF_TRAP_NP_TrapRspUser1__SHIFT                                              0x0
+#define NBIF_TRAP_NP_RESPONSE3__NBIF_TRAP_NP_TrapRspUser1_MASK                                                0xFFFFFFFFL
+//NBIF_TRAP_NP_RESPONSE4
+#define NBIF_TRAP_NP_RESPONSE4__NBIF_TRAP_NP_TrapRspUser2__SHIFT                                              0x0
+#define NBIF_TRAP_NP_RESPONSE4__NBIF_TRAP_NP_TrapRspUser2_MASK                                                0xFFFFFFFFL
+//NBIF_TRAP_NP_RESPONSE5
+#define NBIF_TRAP_NP_RESPONSE5__NBIF_TRAP_NP_TrapRspUser3__SHIFT                                              0x0
+#define NBIF_TRAP_NP_RESPONSE5__NBIF_TRAP_NP_TrapRspUser3_MASK                                                0x00000007L
+//NBIF_TRAP_NP_RESPONSE_DATA0
+#define NBIF_TRAP_NP_RESPONSE_DATA0__NBIF_TRAP_NP_TrapRdRspData0__SHIFT                                       0x0
+#define NBIF_TRAP_NP_RESPONSE_DATA0__NBIF_TRAP_NP_TrapRdRspData0_MASK                                         0xFFFFFFFFL
+//NBIF_TRAP_NP_RESPONSE_DATA1
+#define NBIF_TRAP_NP_RESPONSE_DATA1__NBIF_TRAP_NP_TrapRdRspData1__SHIFT                                       0x0
+#define NBIF_TRAP_NP_RESPONSE_DATA1__NBIF_TRAP_NP_TrapRdRspData1_MASK                                         0xFFFFFFFFL
+//NBIF_TRAP_NP_RESPONSE_DATA2
+#define NBIF_TRAP_NP_RESPONSE_DATA2__NBIF_TRAP_NP_TrapRdRspData2__SHIFT                                       0x0
+#define NBIF_TRAP_NP_RESPONSE_DATA2__NBIF_TRAP_NP_TrapRdRspData2_MASK                                         0xFFFFFFFFL
+//NBIF_TRAP_NP_RESPONSE_DATA3
+#define NBIF_TRAP_NP_RESPONSE_DATA3__NBIF_TRAP_NP_TrapRdRspData3__SHIFT                                       0x0
+#define NBIF_TRAP_NP_RESPONSE_DATA3__NBIF_TRAP_NP_TrapRdRspData3_MASK                                         0xFFFFFFFFL
+//NBIF_TRAP_NP_RESPONSE_DATA4
+#define NBIF_TRAP_NP_RESPONSE_DATA4__NBIF_TRAP_NP_TrapRdRspData4__SHIFT                                       0x0
+#define NBIF_TRAP_NP_RESPONSE_DATA4__NBIF_TRAP_NP_TrapRdRspData4_MASK                                         0xFFFFFFFFL
+//NBIF_TRAP_NP_RESPONSE_DATA5
+#define NBIF_TRAP_NP_RESPONSE_DATA5__NBIF_TRAP_NP_TrapRdRspData5__SHIFT                                       0x0
+#define NBIF_TRAP_NP_RESPONSE_DATA5__NBIF_TRAP_NP_TrapRdRspData5_MASK                                         0xFFFFFFFFL
+//NBIF_TRAP_NP_RESPONSE_DATA6
+#define NBIF_TRAP_NP_RESPONSE_DATA6__NBIF_TRAP_NP_TrapRdRspData6__SHIFT                                       0x0
+#define NBIF_TRAP_NP_RESPONSE_DATA6__NBIF_TRAP_NP_TrapRdRspData6_MASK                                         0xFFFFFFFFL
+//NBIF_TRAP_NP_RESPONSE_DATA7
+#define NBIF_TRAP_NP_RESPONSE_DATA7__NBIF_TRAP_NP_TrapRdRspData7__SHIFT                                       0x0
+#define NBIF_TRAP_NP_RESPONSE_DATA7__NBIF_TRAP_NP_TrapRdRspData7_MASK                                         0xFFFFFFFFL
+//NBIF_TRAP_NP_RESPONSE_DATA8
+#define NBIF_TRAP_NP_RESPONSE_DATA8__NBIF_TRAP_NP_TrapRdRspData8__SHIFT                                       0x0
+#define NBIF_TRAP_NP_RESPONSE_DATA8__NBIF_TRAP_NP_TrapRdRspData8_MASK                                         0xFFFFFFFFL
+//NBIF_TRAP_NP_RESPONSE_DATA9
+#define NBIF_TRAP_NP_RESPONSE_DATA9__NBIF_TRAP_NP_TrapRdRspData9__SHIFT                                       0x0
+#define NBIF_TRAP_NP_RESPONSE_DATA9__NBIF_TRAP_NP_TrapRdRspData9_MASK                                         0xFFFFFFFFL
+//NBIF_TRAP_NP_RESPONSE_DATA10
+#define NBIF_TRAP_NP_RESPONSE_DATA10__NBIF_TRAP_NP_TrapRdRspData10__SHIFT                                     0x0
+#define NBIF_TRAP_NP_RESPONSE_DATA10__NBIF_TRAP_NP_TrapRdRspData10_MASK                                       0xFFFFFFFFL
+//NBIF_TRAP_NP_RESPONSE_DATA11
+#define NBIF_TRAP_NP_RESPONSE_DATA11__NBIF_TRAP_NP_TrapRdRspData11__SHIFT                                     0x0
+#define NBIF_TRAP_NP_RESPONSE_DATA11__NBIF_TRAP_NP_TrapRdRspData11_MASK                                       0xFFFFFFFFL
+//NBIF_TRAP_NP_RESPONSE_DATA12
+#define NBIF_TRAP_NP_RESPONSE_DATA12__NBIF_TRAP_NP_TrapRdRspData12__SHIFT                                     0x0
+#define NBIF_TRAP_NP_RESPONSE_DATA12__NBIF_TRAP_NP_TrapRdRspData12_MASK                                       0xFFFFFFFFL
+//NBIF_TRAP_NP_RESPONSE_DATA13
+#define NBIF_TRAP_NP_RESPONSE_DATA13__NBIF_TRAP_NP_TrapRdRspData13__SHIFT                                     0x0
+#define NBIF_TRAP_NP_RESPONSE_DATA13__NBIF_TRAP_NP_TrapRdRspData13_MASK                                       0xFFFFFFFFL
+//NBIF_TRAP_NP_RESPONSE_DATA14
+#define NBIF_TRAP_NP_RESPONSE_DATA14__NBIF_TRAP_NP_TrapRdRspData14__SHIFT                                     0x0
+#define NBIF_TRAP_NP_RESPONSE_DATA14__NBIF_TRAP_NP_TrapRdRspData14_MASK                                       0xFFFFFFFFL
+//NBIF_TRAP_NP_RESPONSE_DATA15
+#define NBIF_TRAP_NP_RESPONSE_DATA15__NBIF_TRAP_NP_TrapRdRspData15__SHIFT                                     0x0
+#define NBIF_TRAP_NP_RESPONSE_DATA15__NBIF_TRAP_NP_TrapRdRspData15_MASK                                       0xFFFFFFFFL
+//NBIF_TRAP_NP_RESPONSE_DATA16
+#define NBIF_TRAP_NP_RESPONSE_DATA16__NBIF_TRAP_NP_TrapRdRspData16__SHIFT                                     0x0
+#define NBIF_TRAP_NP_RESPONSE_DATA16__NBIF_TRAP_NP_TrapRdRspData16_MASK                                       0xFFFFFFFFL
+//NBIF_TRAP_NP_RESPONSE_DATA17
+#define NBIF_TRAP_NP_RESPONSE_DATA17__NBIF_TRAP_NP_TrapRdRspData17__SHIFT                                     0x0
+#define NBIF_TRAP_NP_RESPONSE_DATA17__NBIF_TRAP_NP_TrapRdRspData17_MASK                                       0xFFFFFFFFL
+//NBIF_TRAP_NP_RESPONSE_DATA18
+#define NBIF_TRAP_NP_RESPONSE_DATA18__NBIF_TRAP_NP_TrapRdRspData18__SHIFT                                     0x0
+#define NBIF_TRAP_NP_RESPONSE_DATA18__NBIF_TRAP_NP_TrapRdRspData18_MASK                                       0xFFFFFFFFL
+//NBIF_TRAP_NP_RESPONSE_DATA19
+#define NBIF_TRAP_NP_RESPONSE_DATA19__NBIF_TRAP_NP_TrapRdRspData19__SHIFT                                     0x0
+#define NBIF_TRAP_NP_RESPONSE_DATA19__NBIF_TRAP_NP_TrapRdRspData19_MASK                                       0xFFFFFFFFL
+//NBIF_TRAP_NP_RESPONSE_DATA20
+#define NBIF_TRAP_NP_RESPONSE_DATA20__NBIF_TRAP_NP_TrapRdRspData20__SHIFT                                     0x0
+#define NBIF_TRAP_NP_RESPONSE_DATA20__NBIF_TRAP_NP_TrapRdRspData20_MASK                                       0xFFFFFFFFL
+//NBIF_TRAP_NP_RESPONSE_DATA21
+#define NBIF_TRAP_NP_RESPONSE_DATA21__NBIF_TRAP_NP_TrapRdRspData21__SHIFT                                     0x0
+#define NBIF_TRAP_NP_RESPONSE_DATA21__NBIF_TRAP_NP_TrapRdRspData21_MASK                                       0xFFFFFFFFL
+//NBIF_TRAP_NP_RESPONSE_DATA22
+#define NBIF_TRAP_NP_RESPONSE_DATA22__NBIF_TRAP_NP_TrapRdRspData22__SHIFT                                     0x0
+#define NBIF_TRAP_NP_RESPONSE_DATA22__NBIF_TRAP_NP_TrapRdRspData22_MASK                                       0xFFFFFFFFL
+//NBIF_TRAP_NP_RESPONSE_DATA23
+#define NBIF_TRAP_NP_RESPONSE_DATA23__NBIF_TRAP_NP_TrapRdRspData23__SHIFT                                     0x0
+#define NBIF_TRAP_NP_RESPONSE_DATA23__NBIF_TRAP_NP_TrapRdRspData23_MASK                                       0xFFFFFFFFL
+//NBIF_TRAP_NP_RESPONSE_DATA24
+#define NBIF_TRAP_NP_RESPONSE_DATA24__NBIF_TRAP_NP_TrapRdRspData24__SHIFT                                     0x0
+#define NBIF_TRAP_NP_RESPONSE_DATA24__NBIF_TRAP_NP_TrapRdRspData24_MASK                                       0xFFFFFFFFL
+//NBIF_TRAP_NP_RESPONSE_DATA25
+#define NBIF_TRAP_NP_RESPONSE_DATA25__NBIF_TRAP_NP_TrapRdRspData25__SHIFT                                     0x0
+#define NBIF_TRAP_NP_RESPONSE_DATA25__NBIF_TRAP_NP_TrapRdRspData25_MASK                                       0xFFFFFFFFL
+//NBIF_TRAP_NP_RESPONSE_DATA26
+#define NBIF_TRAP_NP_RESPONSE_DATA26__NBIF_TRAP_NP_TrapRdRspData26__SHIFT                                     0x0
+#define NBIF_TRAP_NP_RESPONSE_DATA26__NBIF_TRAP_NP_TrapRdRspData26_MASK                                       0xFFFFFFFFL
+//NBIF_TRAP_NP_RESPONSE_DATA27
+#define NBIF_TRAP_NP_RESPONSE_DATA27__NBIF_TRAP_NP_TrapRdRspData27__SHIFT                                     0x0
+#define NBIF_TRAP_NP_RESPONSE_DATA27__NBIF_TRAP_NP_TrapRdRspData27_MASK                                       0xFFFFFFFFL
+//NBIF_TRAP_NP_RESPONSE_DATA28
+#define NBIF_TRAP_NP_RESPONSE_DATA28__NBIF_TRAP_NP_TrapRdRspData28__SHIFT                                     0x0
+#define NBIF_TRAP_NP_RESPONSE_DATA28__NBIF_TRAP_NP_TrapRdRspData28_MASK                                       0xFFFFFFFFL
+//NBIF_TRAP_NP_RESPONSE_DATA29
+#define NBIF_TRAP_NP_RESPONSE_DATA29__NBIF_TRAP_NP_TrapRdRspData29__SHIFT                                     0x0
+#define NBIF_TRAP_NP_RESPONSE_DATA29__NBIF_TRAP_NP_TrapRdRspData29_MASK                                       0xFFFFFFFFL
+//NBIF_TRAP_NP_RESPONSE_DATA30
+#define NBIF_TRAP_NP_RESPONSE_DATA30__NBIF_TRAP_NP_TrapRdRspData30__SHIFT                                     0x0
+#define NBIF_TRAP_NP_RESPONSE_DATA30__NBIF_TRAP_NP_TrapRdRspData30_MASK                                       0xFFFFFFFFL
+//NBIF_TRAP_NP_RESPONSE_DATA31
+#define NBIF_TRAP_NP_RESPONSE_DATA31__NBIF_TRAP_NP_TrapRdRspData31__SHIFT                                     0x0
+#define NBIF_TRAP_NP_RESPONSE_DATA31__NBIF_TRAP_NP_TrapRdRspData31_MASK                                       0xFFFFFFFFL
+//NBIF_TRAP_NP_RESPONSE_DATA32
+#define NBIF_TRAP_NP_RESPONSE_DATA32__NBIF_TRAP_NP_TrapRdRspData32__SHIFT                                     0x0
+#define NBIF_TRAP_NP_RESPONSE_DATA32__NBIF_TRAP_NP_TrapRdRspData32_MASK                                       0xFFFFFFFFL
+//NBIF_TRAP_NP_RESPONSE_DATA33
+#define NBIF_TRAP_NP_RESPONSE_DATA33__NBIF_TRAP_NP_TrapRdRspData33__SHIFT                                     0x0
+#define NBIF_TRAP_NP_RESPONSE_DATA33__NBIF_TRAP_NP_TrapRdRspData33_MASK                                       0xFFFFFFFFL
+//NBIF_TRAP_NP_RESPONSE_DATA34
+#define NBIF_TRAP_NP_RESPONSE_DATA34__NBIF_TRAP_NP_TrapRdRspData34__SHIFT                                     0x0
+#define NBIF_TRAP_NP_RESPONSE_DATA34__NBIF_TRAP_NP_TrapRdRspData34_MASK                                       0xFFFFFFFFL
+//NBIF_TRAP_NP_RESPONSE_DATA35
+#define NBIF_TRAP_NP_RESPONSE_DATA35__NBIF_TRAP_NP_TrapRdRspData35__SHIFT                                     0x0
+#define NBIF_TRAP_NP_RESPONSE_DATA35__NBIF_TRAP_NP_TrapRdRspData35_MASK                                       0xFFFFFFFFL
+//NBIF_TRAP_NP_RESPONSE_DATA36
+#define NBIF_TRAP_NP_RESPONSE_DATA36__NBIF_TRAP_NP_TrapRdRspData36__SHIFT                                     0x0
+#define NBIF_TRAP_NP_RESPONSE_DATA36__NBIF_TRAP_NP_TrapRdRspData36_MASK                                       0xFFFFFFFFL
+//NBIF_TRAP_NP_RESPONSE_DATA37
+#define NBIF_TRAP_NP_RESPONSE_DATA37__NBIF_TRAP_NP_TrapRdRspData37__SHIFT                                     0x0
+#define NBIF_TRAP_NP_RESPONSE_DATA37__NBIF_TRAP_NP_TrapRdRspData37_MASK                                       0xFFFFFFFFL
+//NBIF_TRAP_NP_RESPONSE_DATA38
+#define NBIF_TRAP_NP_RESPONSE_DATA38__NBIF_TRAP_NP_TrapRdRspData38__SHIFT                                     0x0
+#define NBIF_TRAP_NP_RESPONSE_DATA38__NBIF_TRAP_NP_TrapRdRspData38_MASK                                       0xFFFFFFFFL
+//NBIF_TRAP_NP_RESPONSE_DATA39
+#define NBIF_TRAP_NP_RESPONSE_DATA39__NBIF_TRAP_NP_TrapRdRspData39__SHIFT                                     0x0
+#define NBIF_TRAP_NP_RESPONSE_DATA39__NBIF_TRAP_NP_TrapRdRspData39_MASK                                       0xFFFFFFFFL
+//NBIF_TRAP_NP_RESPONSE_DATA40
+#define NBIF_TRAP_NP_RESPONSE_DATA40__NBIF_TRAP_NP_TrapRdRspData40__SHIFT                                     0x0
+#define NBIF_TRAP_NP_RESPONSE_DATA40__NBIF_TRAP_NP_TrapRdRspData40_MASK                                       0xFFFFFFFFL
+//NBIF_TRAP_NP_RESPONSE_DATA41
+#define NBIF_TRAP_NP_RESPONSE_DATA41__NBIF_TRAP_NP_TrapRdRspData41__SHIFT                                     0x0
+#define NBIF_TRAP_NP_RESPONSE_DATA41__NBIF_TRAP_NP_TrapRdRspData41_MASK                                       0xFFFFFFFFL
+//NBIF_TRAP_NP_RESPONSE_DATA42
+#define NBIF_TRAP_NP_RESPONSE_DATA42__NBIF_TRAP_NP_TrapRdRspData42__SHIFT                                     0x0
+#define NBIF_TRAP_NP_RESPONSE_DATA42__NBIF_TRAP_NP_TrapRdRspData42_MASK                                       0xFFFFFFFFL
+//NBIF_TRAP_NP_RESPONSE_DATA43
+#define NBIF_TRAP_NP_RESPONSE_DATA43__NBIF_TRAP_NP_TrapRdRspData43__SHIFT                                     0x0
+#define NBIF_TRAP_NP_RESPONSE_DATA43__NBIF_TRAP_NP_TrapRdRspData43_MASK                                       0xFFFFFFFFL
+//NBIF_TRAP_NP_RESPONSE_DATA44
+#define NBIF_TRAP_NP_RESPONSE_DATA44__NBIF_TRAP_NP_TrapRdRspData44__SHIFT                                     0x0
+#define NBIF_TRAP_NP_RESPONSE_DATA44__NBIF_TRAP_NP_TrapRdRspData44_MASK                                       0xFFFFFFFFL
+//NBIF_TRAP_NP_RESPONSE_DATA45
+#define NBIF_TRAP_NP_RESPONSE_DATA45__NBIF_TRAP_NP_TrapRdRspData45__SHIFT                                     0x0
+#define NBIF_TRAP_NP_RESPONSE_DATA45__NBIF_TRAP_NP_TrapRdRspData45_MASK                                       0xFFFFFFFFL
+//NBIF_TRAP_NP_RESPONSE_DATA46
+#define NBIF_TRAP_NP_RESPONSE_DATA46__NBIF_TRAP_NP_TrapRdRspData46__SHIFT                                     0x0
+#define NBIF_TRAP_NP_RESPONSE_DATA46__NBIF_TRAP_NP_TrapRdRspData46_MASK                                       0xFFFFFFFFL
+//NBIF_TRAP_NP_RESPONSE_DATA47
+#define NBIF_TRAP_NP_RESPONSE_DATA47__NBIF_TRAP_NP_TrapRdRspData47__SHIFT                                     0x0
+#define NBIF_TRAP_NP_RESPONSE_DATA47__NBIF_TRAP_NP_TrapRdRspData47_MASK                                       0xFFFFFFFFL
+//NBIF_TRAP_NP_RESPONSE_DATA48
+#define NBIF_TRAP_NP_RESPONSE_DATA48__NBIF_TRAP_NP_TrapRdRspData48__SHIFT                                     0x0
+#define NBIF_TRAP_NP_RESPONSE_DATA48__NBIF_TRAP_NP_TrapRdRspData48_MASK                                       0xFFFFFFFFL
+//NBIF_TRAP_NP_RESPONSE_DATA49
+#define NBIF_TRAP_NP_RESPONSE_DATA49__NBIF_TRAP_NP_TrapRdRspData49__SHIFT                                     0x0
+#define NBIF_TRAP_NP_RESPONSE_DATA49__NBIF_TRAP_NP_TrapRdRspData49_MASK                                       0xFFFFFFFFL
+//NBIF_TRAP_NP_RESPONSE_DATA50
+#define NBIF_TRAP_NP_RESPONSE_DATA50__NBIF_TRAP_NP_TrapRdRspData50__SHIFT                                     0x0
+#define NBIF_TRAP_NP_RESPONSE_DATA50__NBIF_TRAP_NP_TrapRdRspData50_MASK                                       0xFFFFFFFFL
+//NBIF_TRAP_NP_RESPONSE_DATA51
+#define NBIF_TRAP_NP_RESPONSE_DATA51__NBIF_TRAP_NP_TrapRdRspData51__SHIFT                                     0x0
+#define NBIF_TRAP_NP_RESPONSE_DATA51__NBIF_TRAP_NP_TrapRdRspData51_MASK                                       0xFFFFFFFFL
+//NBIF_TRAP_NP_RESPONSE_DATA52
+#define NBIF_TRAP_NP_RESPONSE_DATA52__NBIF_TRAP_NP_TrapRdRspData52__SHIFT                                     0x0
+#define NBIF_TRAP_NP_RESPONSE_DATA52__NBIF_TRAP_NP_TrapRdRspData52_MASK                                       0xFFFFFFFFL
+//NBIF_TRAP_NP_RESPONSE_DATA53
+#define NBIF_TRAP_NP_RESPONSE_DATA53__NBIF_TRAP_NP_TrapRdRspData53__SHIFT                                     0x0
+#define NBIF_TRAP_NP_RESPONSE_DATA53__NBIF_TRAP_NP_TrapRdRspData53_MASK                                       0xFFFFFFFFL
+//NBIF_TRAP_NP_RESPONSE_DATA54
+#define NBIF_TRAP_NP_RESPONSE_DATA54__NBIF_TRAP_NP_TrapRdRspData54__SHIFT                                     0x0
+#define NBIF_TRAP_NP_RESPONSE_DATA54__NBIF_TRAP_NP_TrapRdRspData54_MASK                                       0xFFFFFFFFL
+//NBIF_TRAP_NP_RESPONSE_DATA55
+#define NBIF_TRAP_NP_RESPONSE_DATA55__NBIF_TRAP_NP_TrapRdRspData55__SHIFT                                     0x0
+#define NBIF_TRAP_NP_RESPONSE_DATA55__NBIF_TRAP_NP_TrapRdRspData55_MASK                                       0xFFFFFFFFL
+//NBIF_TRAP_NP_RESPONSE_DATA56
+#define NBIF_TRAP_NP_RESPONSE_DATA56__NBIF_TRAP_NP_TrapRdRspData56__SHIFT                                     0x0
+#define NBIF_TRAP_NP_RESPONSE_DATA56__NBIF_TRAP_NP_TrapRdRspData56_MASK                                       0xFFFFFFFFL
+//NBIF_TRAP_NP_RESPONSE_DATA57
+#define NBIF_TRAP_NP_RESPONSE_DATA57__NBIF_TRAP_NP_TrapRdRspData57__SHIFT                                     0x0
+#define NBIF_TRAP_NP_RESPONSE_DATA57__NBIF_TRAP_NP_TrapRdRspData57_MASK                                       0xFFFFFFFFL
+//NBIF_TRAP_NP_RESPONSE_DATA58
+#define NBIF_TRAP_NP_RESPONSE_DATA58__NBIF_TRAP_NP_TrapRdRspData58__SHIFT                                     0x0
+#define NBIF_TRAP_NP_RESPONSE_DATA58__NBIF_TRAP_NP_TrapRdRspData58_MASK                                       0xFFFFFFFFL
+//NBIF_TRAP_NP_RESPONSE_DATA59
+#define NBIF_TRAP_NP_RESPONSE_DATA59__NBIF_TRAP_NP_TrapRdRspData59__SHIFT                                     0x0
+#define NBIF_TRAP_NP_RESPONSE_DATA59__NBIF_TRAP_NP_TrapRdRspData59_MASK                                       0xFFFFFFFFL
+//NBIF_TRAP_NP_RESPONSE_DATA60
+#define NBIF_TRAP_NP_RESPONSE_DATA60__NBIF_TRAP_NP_TrapRdRspData60__SHIFT                                     0x0
+#define NBIF_TRAP_NP_RESPONSE_DATA60__NBIF_TRAP_NP_TrapRdRspData60_MASK                                       0xFFFFFFFFL
+//NBIF_TRAP_NP_RESPONSE_DATA61
+#define NBIF_TRAP_NP_RESPONSE_DATA61__NBIF_TRAP_NP_TrapRdRspData61__SHIFT                                     0x0
+#define NBIF_TRAP_NP_RESPONSE_DATA61__NBIF_TRAP_NP_TrapRdRspData61_MASK                                       0xFFFFFFFFL
+//NBIF_TRAP_NP_RESPONSE_DATA62
+#define NBIF_TRAP_NP_RESPONSE_DATA62__NBIF_TRAP_NP_TrapRdRspData62__SHIFT                                     0x0
+#define NBIF_TRAP_NP_RESPONSE_DATA62__NBIF_TRAP_NP_TrapRdRspData62_MASK                                       0xFFFFFFFFL
+//NBIF_TRAP_NP_RESPONSE_DATA63
+#define NBIF_TRAP_NP_RESPONSE_DATA63__NBIF_TRAP_NP_TrapRdRspData63__SHIFT                                     0x0
+#define NBIF_TRAP_NP_RESPONSE_DATA63__NBIF_TRAP_NP_TrapRdRspData63_MASK                                       0xFFFFFFFFL
+//NBIF_TRAP_NP_0_CONTROL0
+#define NBIF_TRAP_NP_0_CONTROL0__NBIF_TRAP_NP_Trap0En__SHIFT                                                  0x0
+#define NBIF_TRAP_NP_0_CONTROL0__NBIF_TRAP_NP_Trap0SMUIntr__SHIFT                                             0x3
+#define NBIF_TRAP_NP_0_CONTROL0__NBIF_TRAP_NP_Trap0Stage2Ptr__SHIFT                                           0xe
+#define NBIF_TRAP_NP_0_CONTROL0__NBIF_TRAP_NP_Trap0CrossTrigger__SHIFT                                        0x18
+#define NBIF_TRAP_NP_0_CONTROL0__NBIF_TRAP_NP_Trap0Stage2En__SHIFT                                            0x1f
+#define NBIF_TRAP_NP_0_CONTROL0__NBIF_TRAP_NP_Trap0En_MASK                                                    0x00000001L
+#define NBIF_TRAP_NP_0_CONTROL0__NBIF_TRAP_NP_Trap0SMUIntr_MASK                                               0x00000008L
+#define NBIF_TRAP_NP_0_CONTROL0__NBIF_TRAP_NP_Trap0Stage2Ptr_MASK                                             0x00FFC000L
+#define NBIF_TRAP_NP_0_CONTROL0__NBIF_TRAP_NP_Trap0CrossTrigger_MASK                                          0x0F000000L
+#define NBIF_TRAP_NP_0_CONTROL0__NBIF_TRAP_NP_Trap0Stage2En_MASK                                              0x80000000L
+//NBIF_TRAP_NP_0_ADDRESS_LO
+#define NBIF_TRAP_NP_0_ADDRESS_LO__NBIF_TRAP_NP_Trap0AddrLo__SHIFT                                            0x2
+#define NBIF_TRAP_NP_0_ADDRESS_LO__NBIF_TRAP_NP_Trap0AddrLo_MASK                                              0xFFFFFFFCL
+//NBIF_TRAP_NP_0_ADDRESS_HI
+#define NBIF_TRAP_NP_0_ADDRESS_HI__NBIF_TRAP_NP_Trap0AddrHi__SHIFT                                            0x0
+#define NBIF_TRAP_NP_0_ADDRESS_HI__NBIF_TRAP_NP_Trap0AddrHi_MASK                                              0xFFFFFFFFL
+//NBIF_TRAP_NP_0_COMMAND
+#define NBIF_TRAP_NP_0_COMMAND__NBIF_TRAP_NP_Trap0Cmd0__SHIFT                                                 0x0
+#define NBIF_TRAP_NP_0_COMMAND__NBIF_TRAP_NP_Trap0Cmd1__SHIFT                                                 0x8
+#define NBIF_TRAP_NP_0_COMMAND__NBIF_TRAP_NP_Trap0Cmd0_MASK                                                   0x0000003FL
+#define NBIF_TRAP_NP_0_COMMAND__NBIF_TRAP_NP_Trap0Cmd1_MASK                                                   0x00003F00L
+//NBIF_TRAP_NP_0_ADDRESS_LO_MASK
+#define NBIF_TRAP_NP_0_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap0AddrLoMask__SHIFT                                   0x2
+#define NBIF_TRAP_NP_0_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap0AddrLoMask_MASK                                     0xFFFFFFFCL
+//NBIF_TRAP_NP_0_ADDRESS_HI_MASK
+#define NBIF_TRAP_NP_0_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap0AddrHiMask__SHIFT                                   0x0
+#define NBIF_TRAP_NP_0_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap0AddrHiMask_MASK                                     0xFFFFFFFFL
+//NBIF_TRAP_NP_0_COMMAND_MASK
+#define NBIF_TRAP_NP_0_COMMAND_MASK__NBIF_TRAP_NP_Trap0Cmd0Mask__SHIFT                                        0x0
+#define NBIF_TRAP_NP_0_COMMAND_MASK__NBIF_TRAP_NP_Trap0Cmd1Mask__SHIFT                                        0x8
+#define NBIF_TRAP_NP_0_COMMAND_MASK__NBIF_TRAP_NP_Trap0Cmd0Mask_MASK                                          0x0000003FL
+#define NBIF_TRAP_NP_0_COMMAND_MASK__NBIF_TRAP_NP_Trap0Cmd1Mask_MASK                                          0x00003F00L
+//NBIF_TRAP_NP_1_CONTROL0
+#define NBIF_TRAP_NP_1_CONTROL0__NBIF_TRAP_NP_Trap1En__SHIFT                                                  0x0
+#define NBIF_TRAP_NP_1_CONTROL0__NBIF_TRAP_NP_Trap1SMUIntr__SHIFT                                             0x3
+#define NBIF_TRAP_NP_1_CONTROL0__NBIF_TRAP_NP_Trap1Stage2Ptr__SHIFT                                           0xe
+#define NBIF_TRAP_NP_1_CONTROL0__NBIF_TRAP_NP_Trap1CrossTrigger__SHIFT                                        0x18
+#define NBIF_TRAP_NP_1_CONTROL0__NBIF_TRAP_NP_Trap1Stage2En__SHIFT                                            0x1f
+#define NBIF_TRAP_NP_1_CONTROL0__NBIF_TRAP_NP_Trap1En_MASK                                                    0x00000001L
+#define NBIF_TRAP_NP_1_CONTROL0__NBIF_TRAP_NP_Trap1SMUIntr_MASK                                               0x00000008L
+#define NBIF_TRAP_NP_1_CONTROL0__NBIF_TRAP_NP_Trap1Stage2Ptr_MASK                                             0x00FFC000L
+#define NBIF_TRAP_NP_1_CONTROL0__NBIF_TRAP_NP_Trap1CrossTrigger_MASK                                          0x0F000000L
+#define NBIF_TRAP_NP_1_CONTROL0__NBIF_TRAP_NP_Trap1Stage2En_MASK                                              0x80000000L
+//NBIF_TRAP_NP_1_ADDRESS_LO
+#define NBIF_TRAP_NP_1_ADDRESS_LO__NBIF_TRAP_NP_Trap1AddrLo__SHIFT                                            0x2
+#define NBIF_TRAP_NP_1_ADDRESS_LO__NBIF_TRAP_NP_Trap1AddrLo_MASK                                              0xFFFFFFFCL
+//NBIF_TRAP_NP_1_ADDRESS_HI
+#define NBIF_TRAP_NP_1_ADDRESS_HI__NBIF_TRAP_NP_Trap1AddrHi__SHIFT                                            0x0
+#define NBIF_TRAP_NP_1_ADDRESS_HI__NBIF_TRAP_NP_Trap1AddrHi_MASK                                              0xFFFFFFFFL
+//NBIF_TRAP_NP_1_COMMAND
+#define NBIF_TRAP_NP_1_COMMAND__NBIF_TRAP_NP_Trap1Cmd0__SHIFT                                                 0x0
+#define NBIF_TRAP_NP_1_COMMAND__NBIF_TRAP_NP_Trap1Cmd1__SHIFT                                                 0x8
+#define NBIF_TRAP_NP_1_COMMAND__NBIF_TRAP_NP_Trap1Cmd0_MASK                                                   0x0000003FL
+#define NBIF_TRAP_NP_1_COMMAND__NBIF_TRAP_NP_Trap1Cmd1_MASK                                                   0x00003F00L
+//NBIF_TRAP_NP_1_ADDRESS_LO_MASK
+#define NBIF_TRAP_NP_1_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap1AddrLoMask__SHIFT                                   0x2
+#define NBIF_TRAP_NP_1_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap1AddrLoMask_MASK                                     0xFFFFFFFCL
+//NBIF_TRAP_NP_1_ADDRESS_HI_MASK
+#define NBIF_TRAP_NP_1_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap1AddrHiMask__SHIFT                                   0x0
+#define NBIF_TRAP_NP_1_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap1AddrHiMask_MASK                                     0xFFFFFFFFL
+//NBIF_TRAP_NP_1_COMMAND_MASK
+#define NBIF_TRAP_NP_1_COMMAND_MASK__NBIF_TRAP_NP_Trap1Cmd0Mask__SHIFT                                        0x0
+#define NBIF_TRAP_NP_1_COMMAND_MASK__NBIF_TRAP_NP_Trap1Cmd1Mask__SHIFT                                        0x8
+#define NBIF_TRAP_NP_1_COMMAND_MASK__NBIF_TRAP_NP_Trap1Cmd0Mask_MASK                                          0x0000003FL
+#define NBIF_TRAP_NP_1_COMMAND_MASK__NBIF_TRAP_NP_Trap1Cmd1Mask_MASK                                          0x00003F00L
+//NBIF_TRAP_NP_2_CONTROL0
+#define NBIF_TRAP_NP_2_CONTROL0__NBIF_TRAP_NP_Trap2En__SHIFT                                                  0x0
+#define NBIF_TRAP_NP_2_CONTROL0__NBIF_TRAP_NP_Trap2SMUIntr__SHIFT                                             0x3
+#define NBIF_TRAP_NP_2_CONTROL0__NBIF_TRAP_NP_Trap2Stage2Ptr__SHIFT                                           0xe
+#define NBIF_TRAP_NP_2_CONTROL0__NBIF_TRAP_NP_Trap2CrossTrigger__SHIFT                                        0x18
+#define NBIF_TRAP_NP_2_CONTROL0__NBIF_TRAP_NP_Trap2Stage2En__SHIFT                                            0x1f
+#define NBIF_TRAP_NP_2_CONTROL0__NBIF_TRAP_NP_Trap2En_MASK                                                    0x00000001L
+#define NBIF_TRAP_NP_2_CONTROL0__NBIF_TRAP_NP_Trap2SMUIntr_MASK                                               0x00000008L
+#define NBIF_TRAP_NP_2_CONTROL0__NBIF_TRAP_NP_Trap2Stage2Ptr_MASK                                             0x00FFC000L
+#define NBIF_TRAP_NP_2_CONTROL0__NBIF_TRAP_NP_Trap2CrossTrigger_MASK                                          0x0F000000L
+#define NBIF_TRAP_NP_2_CONTROL0__NBIF_TRAP_NP_Trap2Stage2En_MASK                                              0x80000000L
+//NBIF_TRAP_NP_2_ADDRESS_LO
+#define NBIF_TRAP_NP_2_ADDRESS_LO__NBIF_TRAP_NP_Trap2AddrLo__SHIFT                                            0x2
+#define NBIF_TRAP_NP_2_ADDRESS_LO__NBIF_TRAP_NP_Trap2AddrLo_MASK                                              0xFFFFFFFCL
+//NBIF_TRAP_NP_2_ADDRESS_HI
+#define NBIF_TRAP_NP_2_ADDRESS_HI__NBIF_TRAP_NP_Trap2AddrHi__SHIFT                                            0x0
+#define NBIF_TRAP_NP_2_ADDRESS_HI__NBIF_TRAP_NP_Trap2AddrHi_MASK                                              0xFFFFFFFFL
+//NBIF_TRAP_NP_2_COMMAND
+#define NBIF_TRAP_NP_2_COMMAND__NBIF_TRAP_NP_Trap2Cmd0__SHIFT                                                 0x0
+#define NBIF_TRAP_NP_2_COMMAND__NBIF_TRAP_NP_Trap2Cmd1__SHIFT                                                 0x8
+#define NBIF_TRAP_NP_2_COMMAND__NBIF_TRAP_NP_Trap2Cmd0_MASK                                                   0x0000003FL
+#define NBIF_TRAP_NP_2_COMMAND__NBIF_TRAP_NP_Trap2Cmd1_MASK                                                   0x00003F00L
+//NBIF_TRAP_NP_2_ADDRESS_LO_MASK
+#define NBIF_TRAP_NP_2_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap2AddrLoMask__SHIFT                                   0x2
+#define NBIF_TRAP_NP_2_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap2AddrLoMask_MASK                                     0xFFFFFFFCL
+//NBIF_TRAP_NP_2_ADDRESS_HI_MASK
+#define NBIF_TRAP_NP_2_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap2AddrHiMask__SHIFT                                   0x0
+#define NBIF_TRAP_NP_2_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap2AddrHiMask_MASK                                     0xFFFFFFFFL
+//NBIF_TRAP_NP_2_COMMAND_MASK
+#define NBIF_TRAP_NP_2_COMMAND_MASK__NBIF_TRAP_NP_Trap2Cmd0Mask__SHIFT                                        0x0
+#define NBIF_TRAP_NP_2_COMMAND_MASK__NBIF_TRAP_NP_Trap2Cmd1Mask__SHIFT                                        0x8
+#define NBIF_TRAP_NP_2_COMMAND_MASK__NBIF_TRAP_NP_Trap2Cmd0Mask_MASK                                          0x0000003FL
+#define NBIF_TRAP_NP_2_COMMAND_MASK__NBIF_TRAP_NP_Trap2Cmd1Mask_MASK                                          0x00003F00L
+//NBIF_TRAP_NP_3_CONTROL0
+#define NBIF_TRAP_NP_3_CONTROL0__NBIF_TRAP_NP_Trap3En__SHIFT                                                  0x0
+#define NBIF_TRAP_NP_3_CONTROL0__NBIF_TRAP_NP_Trap3SMUIntr__SHIFT                                             0x3
+#define NBIF_TRAP_NP_3_CONTROL0__NBIF_TRAP_NP_Trap3Stage2Ptr__SHIFT                                           0xe
+#define NBIF_TRAP_NP_3_CONTROL0__NBIF_TRAP_NP_Trap3CrossTrigger__SHIFT                                        0x18
+#define NBIF_TRAP_NP_3_CONTROL0__NBIF_TRAP_NP_Trap3Stage2En__SHIFT                                            0x1f
+#define NBIF_TRAP_NP_3_CONTROL0__NBIF_TRAP_NP_Trap3En_MASK                                                    0x00000001L
+#define NBIF_TRAP_NP_3_CONTROL0__NBIF_TRAP_NP_Trap3SMUIntr_MASK                                               0x00000008L
+#define NBIF_TRAP_NP_3_CONTROL0__NBIF_TRAP_NP_Trap3Stage2Ptr_MASK                                             0x00FFC000L
+#define NBIF_TRAP_NP_3_CONTROL0__NBIF_TRAP_NP_Trap3CrossTrigger_MASK                                          0x0F000000L
+#define NBIF_TRAP_NP_3_CONTROL0__NBIF_TRAP_NP_Trap3Stage2En_MASK                                              0x80000000L
+//NBIF_TRAP_NP_3_ADDRESS_LO
+#define NBIF_TRAP_NP_3_ADDRESS_LO__NBIF_TRAP_NP_Trap3AddrLo__SHIFT                                            0x2
+#define NBIF_TRAP_NP_3_ADDRESS_LO__NBIF_TRAP_NP_Trap3AddrLo_MASK                                              0xFFFFFFFCL
+//NBIF_TRAP_NP_3_ADDRESS_HI
+#define NBIF_TRAP_NP_3_ADDRESS_HI__NBIF_TRAP_NP_Trap3AddrHi__SHIFT                                            0x0
+#define NBIF_TRAP_NP_3_ADDRESS_HI__NBIF_TRAP_NP_Trap3AddrHi_MASK                                              0xFFFFFFFFL
+//NBIF_TRAP_NP_3_COMMAND
+#define NBIF_TRAP_NP_3_COMMAND__NBIF_TRAP_NP_Trap3Cmd0__SHIFT                                                 0x0
+#define NBIF_TRAP_NP_3_COMMAND__NBIF_TRAP_NP_Trap3Cmd1__SHIFT                                                 0x8
+#define NBIF_TRAP_NP_3_COMMAND__NBIF_TRAP_NP_Trap3Cmd0_MASK                                                   0x0000003FL
+#define NBIF_TRAP_NP_3_COMMAND__NBIF_TRAP_NP_Trap3Cmd1_MASK                                                   0x00003F00L
+//NBIF_TRAP_NP_3_ADDRESS_LO_MASK
+#define NBIF_TRAP_NP_3_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap3AddrLoMask__SHIFT                                   0x2
+#define NBIF_TRAP_NP_3_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap3AddrLoMask_MASK                                     0xFFFFFFFCL
+//NBIF_TRAP_NP_3_ADDRESS_HI_MASK
+#define NBIF_TRAP_NP_3_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap3AddrHiMask__SHIFT                                   0x0
+#define NBIF_TRAP_NP_3_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap3AddrHiMask_MASK                                     0xFFFFFFFFL
+//NBIF_TRAP_NP_3_COMMAND_MASK
+#define NBIF_TRAP_NP_3_COMMAND_MASK__NBIF_TRAP_NP_Trap3Cmd0Mask__SHIFT                                        0x0
+#define NBIF_TRAP_NP_3_COMMAND_MASK__NBIF_TRAP_NP_Trap3Cmd1Mask__SHIFT                                        0x8
+#define NBIF_TRAP_NP_3_COMMAND_MASK__NBIF_TRAP_NP_Trap3Cmd0Mask_MASK                                          0x0000003FL
+#define NBIF_TRAP_NP_3_COMMAND_MASK__NBIF_TRAP_NP_Trap3Cmd1Mask_MASK                                          0x00003F00L
+//NBIF_TRAP_NP_4_CONTROL0
+#define NBIF_TRAP_NP_4_CONTROL0__NBIF_TRAP_NP_Trap4En__SHIFT                                                  0x0
+#define NBIF_TRAP_NP_4_CONTROL0__NBIF_TRAP_NP_Trap4SMUIntr__SHIFT                                             0x3
+#define NBIF_TRAP_NP_4_CONTROL0__NBIF_TRAP_NP_Trap4Stage2Ptr__SHIFT                                           0xe
+#define NBIF_TRAP_NP_4_CONTROL0__NBIF_TRAP_NP_Trap4CrossTrigger__SHIFT                                        0x18
+#define NBIF_TRAP_NP_4_CONTROL0__NBIF_TRAP_NP_Trap4Stage2En__SHIFT                                            0x1f
+#define NBIF_TRAP_NP_4_CONTROL0__NBIF_TRAP_NP_Trap4En_MASK                                                    0x00000001L
+#define NBIF_TRAP_NP_4_CONTROL0__NBIF_TRAP_NP_Trap4SMUIntr_MASK                                               0x00000008L
+#define NBIF_TRAP_NP_4_CONTROL0__NBIF_TRAP_NP_Trap4Stage2Ptr_MASK                                             0x00FFC000L
+#define NBIF_TRAP_NP_4_CONTROL0__NBIF_TRAP_NP_Trap4CrossTrigger_MASK                                          0x0F000000L
+#define NBIF_TRAP_NP_4_CONTROL0__NBIF_TRAP_NP_Trap4Stage2En_MASK                                              0x80000000L
+//NBIF_TRAP_NP_4_ADDRESS_LO
+#define NBIF_TRAP_NP_4_ADDRESS_LO__NBIF_TRAP_NP_Trap4AddrLo__SHIFT                                            0x2
+#define NBIF_TRAP_NP_4_ADDRESS_LO__NBIF_TRAP_NP_Trap4AddrLo_MASK                                              0xFFFFFFFCL
+//NBIF_TRAP_NP_4_ADDRESS_HI
+#define NBIF_TRAP_NP_4_ADDRESS_HI__NBIF_TRAP_NP_Trap4AddrHi__SHIFT                                            0x0
+#define NBIF_TRAP_NP_4_ADDRESS_HI__NBIF_TRAP_NP_Trap4AddrHi_MASK                                              0xFFFFFFFFL
+//NBIF_TRAP_NP_4_COMMAND
+#define NBIF_TRAP_NP_4_COMMAND__NBIF_TRAP_NP_Trap4Cmd0__SHIFT                                                 0x0
+#define NBIF_TRAP_NP_4_COMMAND__NBIF_TRAP_NP_Trap4Cmd1__SHIFT                                                 0x8
+#define NBIF_TRAP_NP_4_COMMAND__NBIF_TRAP_NP_Trap4Cmd0_MASK                                                   0x0000003FL
+#define NBIF_TRAP_NP_4_COMMAND__NBIF_TRAP_NP_Trap4Cmd1_MASK                                                   0x00003F00L
+//NBIF_TRAP_NP_4_ADDRESS_LO_MASK
+#define NBIF_TRAP_NP_4_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap4AddrLoMask__SHIFT                                   0x2
+#define NBIF_TRAP_NP_4_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap4AddrLoMask_MASK                                     0xFFFFFFFCL
+//NBIF_TRAP_NP_4_ADDRESS_HI_MASK
+#define NBIF_TRAP_NP_4_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap4AddrHiMask__SHIFT                                   0x0
+#define NBIF_TRAP_NP_4_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap4AddrHiMask_MASK                                     0xFFFFFFFFL
+//NBIF_TRAP_NP_4_COMMAND_MASK
+#define NBIF_TRAP_NP_4_COMMAND_MASK__NBIF_TRAP_NP_Trap4Cmd0Mask__SHIFT                                        0x0
+#define NBIF_TRAP_NP_4_COMMAND_MASK__NBIF_TRAP_NP_Trap4Cmd1Mask__SHIFT                                        0x8
+#define NBIF_TRAP_NP_4_COMMAND_MASK__NBIF_TRAP_NP_Trap4Cmd0Mask_MASK                                          0x0000003FL
+#define NBIF_TRAP_NP_4_COMMAND_MASK__NBIF_TRAP_NP_Trap4Cmd1Mask_MASK                                          0x00003F00L
+//NBIF_TRAP_NP_5_CONTROL0
+#define NBIF_TRAP_NP_5_CONTROL0__NBIF_TRAP_NP_Trap5En__SHIFT                                                  0x0
+#define NBIF_TRAP_NP_5_CONTROL0__NBIF_TRAP_NP_Trap5SMUIntr__SHIFT                                             0x3
+#define NBIF_TRAP_NP_5_CONTROL0__NBIF_TRAP_NP_Trap5Stage2Ptr__SHIFT                                           0xe
+#define NBIF_TRAP_NP_5_CONTROL0__NBIF_TRAP_NP_Trap5CrossTrigger__SHIFT                                        0x18
+#define NBIF_TRAP_NP_5_CONTROL0__NBIF_TRAP_NP_Trap5Stage2En__SHIFT                                            0x1f
+#define NBIF_TRAP_NP_5_CONTROL0__NBIF_TRAP_NP_Trap5En_MASK                                                    0x00000001L
+#define NBIF_TRAP_NP_5_CONTROL0__NBIF_TRAP_NP_Trap5SMUIntr_MASK                                               0x00000008L
+#define NBIF_TRAP_NP_5_CONTROL0__NBIF_TRAP_NP_Trap5Stage2Ptr_MASK                                             0x00FFC000L
+#define NBIF_TRAP_NP_5_CONTROL0__NBIF_TRAP_NP_Trap5CrossTrigger_MASK                                          0x0F000000L
+#define NBIF_TRAP_NP_5_CONTROL0__NBIF_TRAP_NP_Trap5Stage2En_MASK                                              0x80000000L
+//NBIF_TRAP_NP_5_ADDRESS_LO
+#define NBIF_TRAP_NP_5_ADDRESS_LO__NBIF_TRAP_NP_Trap5AddrLo__SHIFT                                            0x2
+#define NBIF_TRAP_NP_5_ADDRESS_LO__NBIF_TRAP_NP_Trap5AddrLo_MASK                                              0xFFFFFFFCL
+//NBIF_TRAP_NP_5_ADDRESS_HI
+#define NBIF_TRAP_NP_5_ADDRESS_HI__NBIF_TRAP_NP_Trap5AddrHi__SHIFT                                            0x0
+#define NBIF_TRAP_NP_5_ADDRESS_HI__NBIF_TRAP_NP_Trap5AddrHi_MASK                                              0xFFFFFFFFL
+//NBIF_TRAP_NP_5_COMMAND
+#define NBIF_TRAP_NP_5_COMMAND__NBIF_TRAP_NP_Trap5Cmd0__SHIFT                                                 0x0
+#define NBIF_TRAP_NP_5_COMMAND__NBIF_TRAP_NP_Trap5Cmd1__SHIFT                                                 0x8
+#define NBIF_TRAP_NP_5_COMMAND__NBIF_TRAP_NP_Trap5Cmd0_MASK                                                   0x0000003FL
+#define NBIF_TRAP_NP_5_COMMAND__NBIF_TRAP_NP_Trap5Cmd1_MASK                                                   0x00003F00L
+//NBIF_TRAP_NP_5_ADDRESS_LO_MASK
+#define NBIF_TRAP_NP_5_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap5AddrLoMask__SHIFT                                   0x2
+#define NBIF_TRAP_NP_5_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap5AddrLoMask_MASK                                     0xFFFFFFFCL
+//NBIF_TRAP_NP_5_ADDRESS_HI_MASK
+#define NBIF_TRAP_NP_5_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap5AddrHiMask__SHIFT                                   0x0
+#define NBIF_TRAP_NP_5_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap5AddrHiMask_MASK                                     0xFFFFFFFFL
+//NBIF_TRAP_NP_5_COMMAND_MASK
+#define NBIF_TRAP_NP_5_COMMAND_MASK__NBIF_TRAP_NP_Trap5Cmd0Mask__SHIFT                                        0x0
+#define NBIF_TRAP_NP_5_COMMAND_MASK__NBIF_TRAP_NP_Trap5Cmd1Mask__SHIFT                                        0x8
+#define NBIF_TRAP_NP_5_COMMAND_MASK__NBIF_TRAP_NP_Trap5Cmd0Mask_MASK                                          0x0000003FL
+#define NBIF_TRAP_NP_5_COMMAND_MASK__NBIF_TRAP_NP_Trap5Cmd1Mask_MASK                                          0x00003F00L
+//NBIF_TRAP_NP_6_CONTROL0
+#define NBIF_TRAP_NP_6_CONTROL0__NBIF_TRAP_NP_Trap6En__SHIFT                                                  0x0
+#define NBIF_TRAP_NP_6_CONTROL0__NBIF_TRAP_NP_Trap6SMUIntr__SHIFT                                             0x3
+#define NBIF_TRAP_NP_6_CONTROL0__NBIF_TRAP_NP_Trap6Stage2Ptr__SHIFT                                           0xe
+#define NBIF_TRAP_NP_6_CONTROL0__NBIF_TRAP_NP_Trap6CrossTrigger__SHIFT                                        0x18
+#define NBIF_TRAP_NP_6_CONTROL0__NBIF_TRAP_NP_Trap6Stage2En__SHIFT                                            0x1f
+#define NBIF_TRAP_NP_6_CONTROL0__NBIF_TRAP_NP_Trap6En_MASK                                                    0x00000001L
+#define NBIF_TRAP_NP_6_CONTROL0__NBIF_TRAP_NP_Trap6SMUIntr_MASK                                               0x00000008L
+#define NBIF_TRAP_NP_6_CONTROL0__NBIF_TRAP_NP_Trap6Stage2Ptr_MASK                                             0x00FFC000L
+#define NBIF_TRAP_NP_6_CONTROL0__NBIF_TRAP_NP_Trap6CrossTrigger_MASK                                          0x0F000000L
+#define NBIF_TRAP_NP_6_CONTROL0__NBIF_TRAP_NP_Trap6Stage2En_MASK                                              0x80000000L
+//NBIF_TRAP_NP_6_ADDRESS_LO
+#define NBIF_TRAP_NP_6_ADDRESS_LO__NBIF_TRAP_NP_Trap6AddrLo__SHIFT                                            0x2
+#define NBIF_TRAP_NP_6_ADDRESS_LO__NBIF_TRAP_NP_Trap6AddrLo_MASK                                              0xFFFFFFFCL
+//NBIF_TRAP_NP_6_ADDRESS_HI
+#define NBIF_TRAP_NP_6_ADDRESS_HI__NBIF_TRAP_NP_Trap6AddrHi__SHIFT                                            0x0
+#define NBIF_TRAP_NP_6_ADDRESS_HI__NBIF_TRAP_NP_Trap6AddrHi_MASK                                              0xFFFFFFFFL
+//NBIF_TRAP_NP_6_COMMAND
+#define NBIF_TRAP_NP_6_COMMAND__NBIF_TRAP_NP_Trap6Cmd0__SHIFT                                                 0x0
+#define NBIF_TRAP_NP_6_COMMAND__NBIF_TRAP_NP_Trap6Cmd1__SHIFT                                                 0x8
+#define NBIF_TRAP_NP_6_COMMAND__NBIF_TRAP_NP_Trap6Cmd0_MASK                                                   0x0000003FL
+#define NBIF_TRAP_NP_6_COMMAND__NBIF_TRAP_NP_Trap6Cmd1_MASK                                                   0x00003F00L
+//NBIF_TRAP_NP_6_ADDRESS_LO_MASK
+#define NBIF_TRAP_NP_6_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap6AddrLoMask__SHIFT                                   0x2
+#define NBIF_TRAP_NP_6_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap6AddrLoMask_MASK                                     0xFFFFFFFCL
+//NBIF_TRAP_NP_6_ADDRESS_HI_MASK
+#define NBIF_TRAP_NP_6_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap6AddrHiMask__SHIFT                                   0x0
+#define NBIF_TRAP_NP_6_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap6AddrHiMask_MASK                                     0xFFFFFFFFL
+//NBIF_TRAP_NP_6_COMMAND_MASK
+#define NBIF_TRAP_NP_6_COMMAND_MASK__NBIF_TRAP_NP_Trap6Cmd0Mask__SHIFT                                        0x0
+#define NBIF_TRAP_NP_6_COMMAND_MASK__NBIF_TRAP_NP_Trap6Cmd1Mask__SHIFT                                        0x8
+#define NBIF_TRAP_NP_6_COMMAND_MASK__NBIF_TRAP_NP_Trap6Cmd0Mask_MASK                                          0x0000003FL
+#define NBIF_TRAP_NP_6_COMMAND_MASK__NBIF_TRAP_NP_Trap6Cmd1Mask_MASK                                          0x00003F00L
+//NBIF_TRAP_NP_7_CONTROL0
+#define NBIF_TRAP_NP_7_CONTROL0__NBIF_TRAP_NP_Trap7En__SHIFT                                                  0x0
+#define NBIF_TRAP_NP_7_CONTROL0__NBIF_TRAP_NP_Trap7SMUIntr__SHIFT                                             0x3
+#define NBIF_TRAP_NP_7_CONTROL0__NBIF_TRAP_NP_Trap7Stage2Ptr__SHIFT                                           0xe
+#define NBIF_TRAP_NP_7_CONTROL0__NBIF_TRAP_NP_Trap7CrossTrigger__SHIFT                                        0x18
+#define NBIF_TRAP_NP_7_CONTROL0__NBIF_TRAP_NP_Trap7Stage2En__SHIFT                                            0x1f
+#define NBIF_TRAP_NP_7_CONTROL0__NBIF_TRAP_NP_Trap7En_MASK                                                    0x00000001L
+#define NBIF_TRAP_NP_7_CONTROL0__NBIF_TRAP_NP_Trap7SMUIntr_MASK                                               0x00000008L
+#define NBIF_TRAP_NP_7_CONTROL0__NBIF_TRAP_NP_Trap7Stage2Ptr_MASK                                             0x00FFC000L
+#define NBIF_TRAP_NP_7_CONTROL0__NBIF_TRAP_NP_Trap7CrossTrigger_MASK                                          0x0F000000L
+#define NBIF_TRAP_NP_7_CONTROL0__NBIF_TRAP_NP_Trap7Stage2En_MASK                                              0x80000000L
+//NBIF_TRAP_NP_7_ADDRESS_LO
+#define NBIF_TRAP_NP_7_ADDRESS_LO__NBIF_TRAP_NP_Trap7AddrLo__SHIFT                                            0x2
+#define NBIF_TRAP_NP_7_ADDRESS_LO__NBIF_TRAP_NP_Trap7AddrLo_MASK                                              0xFFFFFFFCL
+//NBIF_TRAP_NP_7_ADDRESS_HI
+#define NBIF_TRAP_NP_7_ADDRESS_HI__NBIF_TRAP_NP_Trap7AddrHi__SHIFT                                            0x0
+#define NBIF_TRAP_NP_7_ADDRESS_HI__NBIF_TRAP_NP_Trap7AddrHi_MASK                                              0xFFFFFFFFL
+//NBIF_TRAP_NP_7_COMMAND
+#define NBIF_TRAP_NP_7_COMMAND__NBIF_TRAP_NP_Trap7Cmd0__SHIFT                                                 0x0
+#define NBIF_TRAP_NP_7_COMMAND__NBIF_TRAP_NP_Trap7Cmd1__SHIFT                                                 0x8
+#define NBIF_TRAP_NP_7_COMMAND__NBIF_TRAP_NP_Trap7Cmd0_MASK                                                   0x0000003FL
+#define NBIF_TRAP_NP_7_COMMAND__NBIF_TRAP_NP_Trap7Cmd1_MASK                                                   0x00003F00L
+//NBIF_TRAP_NP_7_ADDRESS_LO_MASK
+#define NBIF_TRAP_NP_7_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap7AddrLoMask__SHIFT                                   0x2
+#define NBIF_TRAP_NP_7_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap7AddrLoMask_MASK                                     0xFFFFFFFCL
+//NBIF_TRAP_NP_7_ADDRESS_HI_MASK
+#define NBIF_TRAP_NP_7_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap7AddrHiMask__SHIFT                                   0x0
+#define NBIF_TRAP_NP_7_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap7AddrHiMask_MASK                                     0xFFFFFFFFL
+//NBIF_TRAP_NP_7_COMMAND_MASK
+#define NBIF_TRAP_NP_7_COMMAND_MASK__NBIF_TRAP_NP_Trap7Cmd0Mask__SHIFT                                        0x0
+#define NBIF_TRAP_NP_7_COMMAND_MASK__NBIF_TRAP_NP_Trap7Cmd1Mask__SHIFT                                        0x8
+#define NBIF_TRAP_NP_7_COMMAND_MASK__NBIF_TRAP_NP_Trap7Cmd0Mask_MASK                                          0x0000003FL
+#define NBIF_TRAP_NP_7_COMMAND_MASK__NBIF_TRAP_NP_Trap7Cmd1Mask_MASK                                          0x00003F00L
+//NBIF_TRAP_NP_8_CONTROL0
+#define NBIF_TRAP_NP_8_CONTROL0__NBIF_TRAP_NP_Trap8En__SHIFT                                                  0x0
+#define NBIF_TRAP_NP_8_CONTROL0__NBIF_TRAP_NP_Trap8SMUIntr__SHIFT                                             0x3
+#define NBIF_TRAP_NP_8_CONTROL0__NBIF_TRAP_NP_Trap8Stage2Ptr__SHIFT                                           0xe
+#define NBIF_TRAP_NP_8_CONTROL0__NBIF_TRAP_NP_Trap8CrossTrigger__SHIFT                                        0x18
+#define NBIF_TRAP_NP_8_CONTROL0__NBIF_TRAP_NP_Trap8Stage2En__SHIFT                                            0x1f
+#define NBIF_TRAP_NP_8_CONTROL0__NBIF_TRAP_NP_Trap8En_MASK                                                    0x00000001L
+#define NBIF_TRAP_NP_8_CONTROL0__NBIF_TRAP_NP_Trap8SMUIntr_MASK                                               0x00000008L
+#define NBIF_TRAP_NP_8_CONTROL0__NBIF_TRAP_NP_Trap8Stage2Ptr_MASK                                             0x00FFC000L
+#define NBIF_TRAP_NP_8_CONTROL0__NBIF_TRAP_NP_Trap8CrossTrigger_MASK                                          0x0F000000L
+#define NBIF_TRAP_NP_8_CONTROL0__NBIF_TRAP_NP_Trap8Stage2En_MASK                                              0x80000000L
+//NBIF_TRAP_NP_8_ADDRESS_LO
+#define NBIF_TRAP_NP_8_ADDRESS_LO__NBIF_TRAP_NP_Trap8AddrLo__SHIFT                                            0x2
+#define NBIF_TRAP_NP_8_ADDRESS_LO__NBIF_TRAP_NP_Trap8AddrLo_MASK                                              0xFFFFFFFCL
+//NBIF_TRAP_NP_8_ADDRESS_HI
+#define NBIF_TRAP_NP_8_ADDRESS_HI__NBIF_TRAP_NP_Trap8AddrHi__SHIFT                                            0x0
+#define NBIF_TRAP_NP_8_ADDRESS_HI__NBIF_TRAP_NP_Trap8AddrHi_MASK                                              0xFFFFFFFFL
+//NBIF_TRAP_NP_8_COMMAND
+#define NBIF_TRAP_NP_8_COMMAND__NBIF_TRAP_NP_Trap8Cmd0__SHIFT                                                 0x0
+#define NBIF_TRAP_NP_8_COMMAND__NBIF_TRAP_NP_Trap8Cmd1__SHIFT                                                 0x8
+#define NBIF_TRAP_NP_8_COMMAND__NBIF_TRAP_NP_Trap8Cmd0_MASK                                                   0x0000003FL
+#define NBIF_TRAP_NP_8_COMMAND__NBIF_TRAP_NP_Trap8Cmd1_MASK                                                   0x00003F00L
+//NBIF_TRAP_NP_8_ADDRESS_LO_MASK
+#define NBIF_TRAP_NP_8_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap8AddrLoMask__SHIFT                                   0x2
+#define NBIF_TRAP_NP_8_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap8AddrLoMask_MASK                                     0xFFFFFFFCL
+//NBIF_TRAP_NP_8_ADDRESS_HI_MASK
+#define NBIF_TRAP_NP_8_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap8AddrHiMask__SHIFT                                   0x0
+#define NBIF_TRAP_NP_8_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap8AddrHiMask_MASK                                     0xFFFFFFFFL
+//NBIF_TRAP_NP_8_COMMAND_MASK
+#define NBIF_TRAP_NP_8_COMMAND_MASK__NBIF_TRAP_NP_Trap8Cmd0Mask__SHIFT                                        0x0
+#define NBIF_TRAP_NP_8_COMMAND_MASK__NBIF_TRAP_NP_Trap8Cmd1Mask__SHIFT                                        0x8
+#define NBIF_TRAP_NP_8_COMMAND_MASK__NBIF_TRAP_NP_Trap8Cmd0Mask_MASK                                          0x0000003FL
+#define NBIF_TRAP_NP_8_COMMAND_MASK__NBIF_TRAP_NP_Trap8Cmd1Mask_MASK                                          0x00003F00L
+//NBIF_TRAP_NP_9_CONTROL0
+#define NBIF_TRAP_NP_9_CONTROL0__NBIF_TRAP_NP_Trap9En__SHIFT                                                  0x0
+#define NBIF_TRAP_NP_9_CONTROL0__NBIF_TRAP_NP_Trap9SMUIntr__SHIFT                                             0x3
+#define NBIF_TRAP_NP_9_CONTROL0__NBIF_TRAP_NP_Trap9Stage2Ptr__SHIFT                                           0xe
+#define NBIF_TRAP_NP_9_CONTROL0__NBIF_TRAP_NP_Trap9CrossTrigger__SHIFT                                        0x18
+#define NBIF_TRAP_NP_9_CONTROL0__NBIF_TRAP_NP_Trap9Stage2En__SHIFT                                            0x1f
+#define NBIF_TRAP_NP_9_CONTROL0__NBIF_TRAP_NP_Trap9En_MASK                                                    0x00000001L
+#define NBIF_TRAP_NP_9_CONTROL0__NBIF_TRAP_NP_Trap9SMUIntr_MASK                                               0x00000008L
+#define NBIF_TRAP_NP_9_CONTROL0__NBIF_TRAP_NP_Trap9Stage2Ptr_MASK                                             0x00FFC000L
+#define NBIF_TRAP_NP_9_CONTROL0__NBIF_TRAP_NP_Trap9CrossTrigger_MASK                                          0x0F000000L
+#define NBIF_TRAP_NP_9_CONTROL0__NBIF_TRAP_NP_Trap9Stage2En_MASK                                              0x80000000L
+//NBIF_TRAP_NP_9_ADDRESS_LO
+#define NBIF_TRAP_NP_9_ADDRESS_LO__NBIF_TRAP_NP_Trap9AddrLo__SHIFT                                            0x2
+#define NBIF_TRAP_NP_9_ADDRESS_LO__NBIF_TRAP_NP_Trap9AddrLo_MASK                                              0xFFFFFFFCL
+//NBIF_TRAP_NP_9_ADDRESS_HI
+#define NBIF_TRAP_NP_9_ADDRESS_HI__NBIF_TRAP_NP_Trap9AddrHi__SHIFT                                            0x0
+#define NBIF_TRAP_NP_9_ADDRESS_HI__NBIF_TRAP_NP_Trap9AddrHi_MASK                                              0xFFFFFFFFL
+//NBIF_TRAP_NP_9_COMMAND
+#define NBIF_TRAP_NP_9_COMMAND__NBIF_TRAP_NP_Trap9Cmd0__SHIFT                                                 0x0
+#define NBIF_TRAP_NP_9_COMMAND__NBIF_TRAP_NP_Trap9Cmd1__SHIFT                                                 0x8
+#define NBIF_TRAP_NP_9_COMMAND__NBIF_TRAP_NP_Trap9Cmd0_MASK                                                   0x0000003FL
+#define NBIF_TRAP_NP_9_COMMAND__NBIF_TRAP_NP_Trap9Cmd1_MASK                                                   0x00003F00L
+//NBIF_TRAP_NP_9_ADDRESS_LO_MASK
+#define NBIF_TRAP_NP_9_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap9AddrLoMask__SHIFT                                   0x2
+#define NBIF_TRAP_NP_9_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap9AddrLoMask_MASK                                     0xFFFFFFFCL
+//NBIF_TRAP_NP_9_ADDRESS_HI_MASK
+#define NBIF_TRAP_NP_9_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap9AddrHiMask__SHIFT                                   0x0
+#define NBIF_TRAP_NP_9_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap9AddrHiMask_MASK                                     0xFFFFFFFFL
+//NBIF_TRAP_NP_9_COMMAND_MASK
+#define NBIF_TRAP_NP_9_COMMAND_MASK__NBIF_TRAP_NP_Trap9Cmd0Mask__SHIFT                                        0x0
+#define NBIF_TRAP_NP_9_COMMAND_MASK__NBIF_TRAP_NP_Trap9Cmd1Mask__SHIFT                                        0x8
+#define NBIF_TRAP_NP_9_COMMAND_MASK__NBIF_TRAP_NP_Trap9Cmd0Mask_MASK                                          0x0000003FL
+#define NBIF_TRAP_NP_9_COMMAND_MASK__NBIF_TRAP_NP_Trap9Cmd1Mask_MASK                                          0x00003F00L
+//NBIF_TRAP_NP_10_CONTROL0
+#define NBIF_TRAP_NP_10_CONTROL0__NBIF_TRAP_NP_Trap10En__SHIFT                                                0x0
+#define NBIF_TRAP_NP_10_CONTROL0__NBIF_TRAP_NP_Trap10SMUIntr__SHIFT                                           0x3
+#define NBIF_TRAP_NP_10_CONTROL0__NBIF_TRAP_NP_Trap10Stage2Ptr__SHIFT                                         0xe
+#define NBIF_TRAP_NP_10_CONTROL0__NBIF_TRAP_NP_Trap10CrossTrigger__SHIFT                                      0x18
+#define NBIF_TRAP_NP_10_CONTROL0__NBIF_TRAP_NP_Trap10Stage2En__SHIFT                                          0x1f
+#define NBIF_TRAP_NP_10_CONTROL0__NBIF_TRAP_NP_Trap10En_MASK                                                  0x00000001L
+#define NBIF_TRAP_NP_10_CONTROL0__NBIF_TRAP_NP_Trap10SMUIntr_MASK                                             0x00000008L
+#define NBIF_TRAP_NP_10_CONTROL0__NBIF_TRAP_NP_Trap10Stage2Ptr_MASK                                           0x00FFC000L
+#define NBIF_TRAP_NP_10_CONTROL0__NBIF_TRAP_NP_Trap10CrossTrigger_MASK                                        0x0F000000L
+#define NBIF_TRAP_NP_10_CONTROL0__NBIF_TRAP_NP_Trap10Stage2En_MASK                                            0x80000000L
+//NBIF_TRAP_NP_10_ADDRESS_LO
+#define NBIF_TRAP_NP_10_ADDRESS_LO__NBIF_TRAP_NP_Trap10AddrLo__SHIFT                                          0x2
+#define NBIF_TRAP_NP_10_ADDRESS_LO__NBIF_TRAP_NP_Trap10AddrLo_MASK                                            0xFFFFFFFCL
+//NBIF_TRAP_NP_10_ADDRESS_HI
+#define NBIF_TRAP_NP_10_ADDRESS_HI__NBIF_TRAP_NP_Trap10AddrHi__SHIFT                                          0x0
+#define NBIF_TRAP_NP_10_ADDRESS_HI__NBIF_TRAP_NP_Trap10AddrHi_MASK                                            0xFFFFFFFFL
+//NBIF_TRAP_NP_10_COMMAND
+#define NBIF_TRAP_NP_10_COMMAND__NBIF_TRAP_NP_Trap10Cmd0__SHIFT                                               0x0
+#define NBIF_TRAP_NP_10_COMMAND__NBIF_TRAP_NP_Trap10Cmd1__SHIFT                                               0x8
+#define NBIF_TRAP_NP_10_COMMAND__NBIF_TRAP_NP_Trap10Cmd0_MASK                                                 0x0000003FL
+#define NBIF_TRAP_NP_10_COMMAND__NBIF_TRAP_NP_Trap10Cmd1_MASK                                                 0x00003F00L
+//NBIF_TRAP_NP_10_ADDRESS_LO_MASK
+#define NBIF_TRAP_NP_10_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap10AddrLoMask__SHIFT                                 0x2
+#define NBIF_TRAP_NP_10_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap10AddrLoMask_MASK                                   0xFFFFFFFCL
+//NBIF_TRAP_NP_10_ADDRESS_HI_MASK
+#define NBIF_TRAP_NP_10_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap10AddrHiMask__SHIFT                                 0x0
+#define NBIF_TRAP_NP_10_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap10AddrHiMask_MASK                                   0xFFFFFFFFL
+//NBIF_TRAP_NP_10_COMMAND_MASK
+#define NBIF_TRAP_NP_10_COMMAND_MASK__NBIF_TRAP_NP_Trap10Cmd0Mask__SHIFT                                      0x0
+#define NBIF_TRAP_NP_10_COMMAND_MASK__NBIF_TRAP_NP_Trap10Cmd1Mask__SHIFT                                      0x8
+#define NBIF_TRAP_NP_10_COMMAND_MASK__NBIF_TRAP_NP_Trap10Cmd0Mask_MASK                                        0x0000003FL
+#define NBIF_TRAP_NP_10_COMMAND_MASK__NBIF_TRAP_NP_Trap10Cmd1Mask_MASK                                        0x00003F00L
+//NBIF_TRAP_NP_11_CONTROL0
+#define NBIF_TRAP_NP_11_CONTROL0__NBIF_TRAP_NP_Trap11En__SHIFT                                                0x0
+#define NBIF_TRAP_NP_11_CONTROL0__NBIF_TRAP_NP_Trap11SMUIntr__SHIFT                                           0x3
+#define NBIF_TRAP_NP_11_CONTROL0__NBIF_TRAP_NP_Trap11Stage2Ptr__SHIFT                                         0xe
+#define NBIF_TRAP_NP_11_CONTROL0__NBIF_TRAP_NP_Trap11CrossTrigger__SHIFT                                      0x18
+#define NBIF_TRAP_NP_11_CONTROL0__NBIF_TRAP_NP_Trap11Stage2En__SHIFT                                          0x1f
+#define NBIF_TRAP_NP_11_CONTROL0__NBIF_TRAP_NP_Trap11En_MASK                                                  0x00000001L
+#define NBIF_TRAP_NP_11_CONTROL0__NBIF_TRAP_NP_Trap11SMUIntr_MASK                                             0x00000008L
+#define NBIF_TRAP_NP_11_CONTROL0__NBIF_TRAP_NP_Trap11Stage2Ptr_MASK                                           0x00FFC000L
+#define NBIF_TRAP_NP_11_CONTROL0__NBIF_TRAP_NP_Trap11CrossTrigger_MASK                                        0x0F000000L
+#define NBIF_TRAP_NP_11_CONTROL0__NBIF_TRAP_NP_Trap11Stage2En_MASK                                            0x80000000L
+//NBIF_TRAP_NP_11_ADDRESS_LO
+#define NBIF_TRAP_NP_11_ADDRESS_LO__NBIF_TRAP_NP_Trap11AddrLo__SHIFT                                          0x2
+#define NBIF_TRAP_NP_11_ADDRESS_LO__NBIF_TRAP_NP_Trap11AddrLo_MASK                                            0xFFFFFFFCL
+//NBIF_TRAP_NP_11_ADDRESS_HI
+#define NBIF_TRAP_NP_11_ADDRESS_HI__NBIF_TRAP_NP_Trap11AddrHi__SHIFT                                          0x0
+#define NBIF_TRAP_NP_11_ADDRESS_HI__NBIF_TRAP_NP_Trap11AddrHi_MASK                                            0xFFFFFFFFL
+//NBIF_TRAP_NP_11_COMMAND
+#define NBIF_TRAP_NP_11_COMMAND__NBIF_TRAP_NP_Trap11Cmd0__SHIFT                                               0x0
+#define NBIF_TRAP_NP_11_COMMAND__NBIF_TRAP_NP_Trap11Cmd1__SHIFT                                               0x8
+#define NBIF_TRAP_NP_11_COMMAND__NBIF_TRAP_NP_Trap11Cmd0_MASK                                                 0x0000003FL
+#define NBIF_TRAP_NP_11_COMMAND__NBIF_TRAP_NP_Trap11Cmd1_MASK                                                 0x00003F00L
+//NBIF_TRAP_NP_11_ADDRESS_LO_MASK
+#define NBIF_TRAP_NP_11_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap11AddrLoMask__SHIFT                                 0x2
+#define NBIF_TRAP_NP_11_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap11AddrLoMask_MASK                                   0xFFFFFFFCL
+//NBIF_TRAP_NP_11_ADDRESS_HI_MASK
+#define NBIF_TRAP_NP_11_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap11AddrHiMask__SHIFT                                 0x0
+#define NBIF_TRAP_NP_11_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap11AddrHiMask_MASK                                   0xFFFFFFFFL
+//NBIF_TRAP_NP_11_COMMAND_MASK
+#define NBIF_TRAP_NP_11_COMMAND_MASK__NBIF_TRAP_NP_Trap11Cmd0Mask__SHIFT                                      0x0
+#define NBIF_TRAP_NP_11_COMMAND_MASK__NBIF_TRAP_NP_Trap11Cmd1Mask__SHIFT                                      0x8
+#define NBIF_TRAP_NP_11_COMMAND_MASK__NBIF_TRAP_NP_Trap11Cmd0Mask_MASK                                        0x0000003FL
+#define NBIF_TRAP_NP_11_COMMAND_MASK__NBIF_TRAP_NP_Trap11Cmd1Mask_MASK                                        0x00003F00L
+//NBIF_TRAP_NP_12_CONTROL0
+#define NBIF_TRAP_NP_12_CONTROL0__NBIF_TRAP_NP_Trap12En__SHIFT                                                0x0
+#define NBIF_TRAP_NP_12_CONTROL0__NBIF_TRAP_NP_Trap12SMUIntr__SHIFT                                           0x3
+#define NBIF_TRAP_NP_12_CONTROL0__NBIF_TRAP_NP_Trap12Stage2Ptr__SHIFT                                         0xe
+#define NBIF_TRAP_NP_12_CONTROL0__NBIF_TRAP_NP_Trap12CrossTrigger__SHIFT                                      0x18
+#define NBIF_TRAP_NP_12_CONTROL0__NBIF_TRAP_NP_Trap12Stage2En__SHIFT                                          0x1f
+#define NBIF_TRAP_NP_12_CONTROL0__NBIF_TRAP_NP_Trap12En_MASK                                                  0x00000001L
+#define NBIF_TRAP_NP_12_CONTROL0__NBIF_TRAP_NP_Trap12SMUIntr_MASK                                             0x00000008L
+#define NBIF_TRAP_NP_12_CONTROL0__NBIF_TRAP_NP_Trap12Stage2Ptr_MASK                                           0x00FFC000L
+#define NBIF_TRAP_NP_12_CONTROL0__NBIF_TRAP_NP_Trap12CrossTrigger_MASK                                        0x0F000000L
+#define NBIF_TRAP_NP_12_CONTROL0__NBIF_TRAP_NP_Trap12Stage2En_MASK                                            0x80000000L
+//NBIF_TRAP_NP_12_ADDRESS_LO
+#define NBIF_TRAP_NP_12_ADDRESS_LO__NBIF_TRAP_NP_Trap12AddrLo__SHIFT                                          0x2
+#define NBIF_TRAP_NP_12_ADDRESS_LO__NBIF_TRAP_NP_Trap12AddrLo_MASK                                            0xFFFFFFFCL
+//NBIF_TRAP_NP_12_ADDRESS_HI
+#define NBIF_TRAP_NP_12_ADDRESS_HI__NBIF_TRAP_NP_Trap12AddrHi__SHIFT                                          0x0
+#define NBIF_TRAP_NP_12_ADDRESS_HI__NBIF_TRAP_NP_Trap12AddrHi_MASK                                            0xFFFFFFFFL
+//NBIF_TRAP_NP_12_COMMAND
+#define NBIF_TRAP_NP_12_COMMAND__NBIF_TRAP_NP_Trap12Cmd0__SHIFT                                               0x0
+#define NBIF_TRAP_NP_12_COMMAND__NBIF_TRAP_NP_Trap12Cmd1__SHIFT                                               0x8
+#define NBIF_TRAP_NP_12_COMMAND__NBIF_TRAP_NP_Trap12Cmd0_MASK                                                 0x0000003FL
+#define NBIF_TRAP_NP_12_COMMAND__NBIF_TRAP_NP_Trap12Cmd1_MASK                                                 0x00003F00L
+//NBIF_TRAP_NP_12_ADDRESS_LO_MASK
+#define NBIF_TRAP_NP_12_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap12AddrLoMask__SHIFT                                 0x2
+#define NBIF_TRAP_NP_12_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap12AddrLoMask_MASK                                   0xFFFFFFFCL
+//NBIF_TRAP_NP_12_ADDRESS_HI_MASK
+#define NBIF_TRAP_NP_12_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap12AddrHiMask__SHIFT                                 0x0
+#define NBIF_TRAP_NP_12_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap12AddrHiMask_MASK                                   0xFFFFFFFFL
+//NBIF_TRAP_NP_12_COMMAND_MASK
+#define NBIF_TRAP_NP_12_COMMAND_MASK__NBIF_TRAP_NP_Trap12Cmd0Mask__SHIFT                                      0x0
+#define NBIF_TRAP_NP_12_COMMAND_MASK__NBIF_TRAP_NP_Trap12Cmd1Mask__SHIFT                                      0x8
+#define NBIF_TRAP_NP_12_COMMAND_MASK__NBIF_TRAP_NP_Trap12Cmd0Mask_MASK                                        0x0000003FL
+#define NBIF_TRAP_NP_12_COMMAND_MASK__NBIF_TRAP_NP_Trap12Cmd1Mask_MASK                                        0x00003F00L
+//NBIF_TRAP_NP_13_CONTROL0
+#define NBIF_TRAP_NP_13_CONTROL0__NBIF_TRAP_NP_Trap13En__SHIFT                                                0x0
+#define NBIF_TRAP_NP_13_CONTROL0__NBIF_TRAP_NP_Trap13SMUIntr__SHIFT                                           0x3
+#define NBIF_TRAP_NP_13_CONTROL0__NBIF_TRAP_NP_Trap13Stage2Ptr__SHIFT                                         0xe
+#define NBIF_TRAP_NP_13_CONTROL0__NBIF_TRAP_NP_Trap13CrossTrigger__SHIFT                                      0x18
+#define NBIF_TRAP_NP_13_CONTROL0__NBIF_TRAP_NP_Trap13Stage2En__SHIFT                                          0x1f
+#define NBIF_TRAP_NP_13_CONTROL0__NBIF_TRAP_NP_Trap13En_MASK                                                  0x00000001L
+#define NBIF_TRAP_NP_13_CONTROL0__NBIF_TRAP_NP_Trap13SMUIntr_MASK                                             0x00000008L
+#define NBIF_TRAP_NP_13_CONTROL0__NBIF_TRAP_NP_Trap13Stage2Ptr_MASK                                           0x00FFC000L
+#define NBIF_TRAP_NP_13_CONTROL0__NBIF_TRAP_NP_Trap13CrossTrigger_MASK                                        0x0F000000L
+#define NBIF_TRAP_NP_13_CONTROL0__NBIF_TRAP_NP_Trap13Stage2En_MASK                                            0x80000000L
+//NBIF_TRAP_NP_13_ADDRESS_LO
+#define NBIF_TRAP_NP_13_ADDRESS_LO__NBIF_TRAP_NP_Trap13AddrLo__SHIFT                                          0x2
+#define NBIF_TRAP_NP_13_ADDRESS_LO__NBIF_TRAP_NP_Trap13AddrLo_MASK                                            0xFFFFFFFCL
+//NBIF_TRAP_NP_13_ADDRESS_HI
+#define NBIF_TRAP_NP_13_ADDRESS_HI__NBIF_TRAP_NP_Trap13AddrHi__SHIFT                                          0x0
+#define NBIF_TRAP_NP_13_ADDRESS_HI__NBIF_TRAP_NP_Trap13AddrHi_MASK                                            0xFFFFFFFFL
+//NBIF_TRAP_NP_13_COMMAND
+#define NBIF_TRAP_NP_13_COMMAND__NBIF_TRAP_NP_Trap13Cmd0__SHIFT                                               0x0
+#define NBIF_TRAP_NP_13_COMMAND__NBIF_TRAP_NP_Trap13Cmd1__SHIFT                                               0x8
+#define NBIF_TRAP_NP_13_COMMAND__NBIF_TRAP_NP_Trap13Cmd0_MASK                                                 0x0000003FL
+#define NBIF_TRAP_NP_13_COMMAND__NBIF_TRAP_NP_Trap13Cmd1_MASK                                                 0x00003F00L
+//NBIF_TRAP_NP_13_ADDRESS_LO_MASK
+#define NBIF_TRAP_NP_13_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap13AddrLoMask__SHIFT                                 0x2
+#define NBIF_TRAP_NP_13_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap13AddrLoMask_MASK                                   0xFFFFFFFCL
+//NBIF_TRAP_NP_13_ADDRESS_HI_MASK
+#define NBIF_TRAP_NP_13_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap13AddrHiMask__SHIFT                                 0x0
+#define NBIF_TRAP_NP_13_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap13AddrHiMask_MASK                                   0xFFFFFFFFL
+//NBIF_TRAP_NP_13_COMMAND_MASK
+#define NBIF_TRAP_NP_13_COMMAND_MASK__NBIF_TRAP_NP_Trap13Cmd0Mask__SHIFT                                      0x0
+#define NBIF_TRAP_NP_13_COMMAND_MASK__NBIF_TRAP_NP_Trap13Cmd1Mask__SHIFT                                      0x8
+#define NBIF_TRAP_NP_13_COMMAND_MASK__NBIF_TRAP_NP_Trap13Cmd0Mask_MASK                                        0x0000003FL
+#define NBIF_TRAP_NP_13_COMMAND_MASK__NBIF_TRAP_NP_Trap13Cmd1Mask_MASK                                        0x00003F00L
+//NBIF_TRAP_NP_14_CONTROL0
+#define NBIF_TRAP_NP_14_CONTROL0__NBIF_TRAP_NP_Trap14En__SHIFT                                                0x0
+#define NBIF_TRAP_NP_14_CONTROL0__NBIF_TRAP_NP_Trap14SMUIntr__SHIFT                                           0x3
+#define NBIF_TRAP_NP_14_CONTROL0__NBIF_TRAP_NP_Trap14Stage2Ptr__SHIFT                                         0xe
+#define NBIF_TRAP_NP_14_CONTROL0__NBIF_TRAP_NP_Trap14CrossTrigger__SHIFT                                      0x18
+#define NBIF_TRAP_NP_14_CONTROL0__NBIF_TRAP_NP_Trap14Stage2En__SHIFT                                          0x1f
+#define NBIF_TRAP_NP_14_CONTROL0__NBIF_TRAP_NP_Trap14En_MASK                                                  0x00000001L
+#define NBIF_TRAP_NP_14_CONTROL0__NBIF_TRAP_NP_Trap14SMUIntr_MASK                                             0x00000008L
+#define NBIF_TRAP_NP_14_CONTROL0__NBIF_TRAP_NP_Trap14Stage2Ptr_MASK                                           0x00FFC000L
+#define NBIF_TRAP_NP_14_CONTROL0__NBIF_TRAP_NP_Trap14CrossTrigger_MASK                                        0x0F000000L
+#define NBIF_TRAP_NP_14_CONTROL0__NBIF_TRAP_NP_Trap14Stage2En_MASK                                            0x80000000L
+//NBIF_TRAP_NP_14_ADDRESS_LO
+#define NBIF_TRAP_NP_14_ADDRESS_LO__NBIF_TRAP_NP_Trap14AddrLo__SHIFT                                          0x2
+#define NBIF_TRAP_NP_14_ADDRESS_LO__NBIF_TRAP_NP_Trap14AddrLo_MASK                                            0xFFFFFFFCL
+//NBIF_TRAP_NP_14_ADDRESS_HI
+#define NBIF_TRAP_NP_14_ADDRESS_HI__NBIF_TRAP_NP_Trap14AddrHi__SHIFT                                          0x0
+#define NBIF_TRAP_NP_14_ADDRESS_HI__NBIF_TRAP_NP_Trap14AddrHi_MASK                                            0xFFFFFFFFL
+//NBIF_TRAP_NP_14_COMMAND
+#define NBIF_TRAP_NP_14_COMMAND__NBIF_TRAP_NP_Trap14Cmd0__SHIFT                                               0x0
+#define NBIF_TRAP_NP_14_COMMAND__NBIF_TRAP_NP_Trap14Cmd1__SHIFT                                               0x8
+#define NBIF_TRAP_NP_14_COMMAND__NBIF_TRAP_NP_Trap14Cmd0_MASK                                                 0x0000003FL
+#define NBIF_TRAP_NP_14_COMMAND__NBIF_TRAP_NP_Trap14Cmd1_MASK                                                 0x00003F00L
+//NBIF_TRAP_NP_14_ADDRESS_LO_MASK
+#define NBIF_TRAP_NP_14_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap14AddrLoMask__SHIFT                                 0x2
+#define NBIF_TRAP_NP_14_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap14AddrLoMask_MASK                                   0xFFFFFFFCL
+//NBIF_TRAP_NP_14_ADDRESS_HI_MASK
+#define NBIF_TRAP_NP_14_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap14AddrHiMask__SHIFT                                 0x0
+#define NBIF_TRAP_NP_14_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap14AddrHiMask_MASK                                   0xFFFFFFFFL
+//NBIF_TRAP_NP_14_COMMAND_MASK
+#define NBIF_TRAP_NP_14_COMMAND_MASK__NBIF_TRAP_NP_Trap14Cmd0Mask__SHIFT                                      0x0
+#define NBIF_TRAP_NP_14_COMMAND_MASK__NBIF_TRAP_NP_Trap14Cmd1Mask__SHIFT                                      0x8
+#define NBIF_TRAP_NP_14_COMMAND_MASK__NBIF_TRAP_NP_Trap14Cmd0Mask_MASK                                        0x0000003FL
+#define NBIF_TRAP_NP_14_COMMAND_MASK__NBIF_TRAP_NP_Trap14Cmd1Mask_MASK                                        0x00003F00L
+//NBIF_TRAP_NP_15_CONTROL0
+#define NBIF_TRAP_NP_15_CONTROL0__NBIF_TRAP_NP_Trap15En__SHIFT                                                0x0
+#define NBIF_TRAP_NP_15_CONTROL0__NBIF_TRAP_NP_Trap15SMUIntr__SHIFT                                           0x3
+#define NBIF_TRAP_NP_15_CONTROL0__NBIF_TRAP_NP_Trap15Stage2Ptr__SHIFT                                         0xe
+#define NBIF_TRAP_NP_15_CONTROL0__NBIF_TRAP_NP_Trap15CrossTrigger__SHIFT                                      0x18
+#define NBIF_TRAP_NP_15_CONTROL0__NBIF_TRAP_NP_Trap15Stage2En__SHIFT                                          0x1f
+#define NBIF_TRAP_NP_15_CONTROL0__NBIF_TRAP_NP_Trap15En_MASK                                                  0x00000001L
+#define NBIF_TRAP_NP_15_CONTROL0__NBIF_TRAP_NP_Trap15SMUIntr_MASK                                             0x00000008L
+#define NBIF_TRAP_NP_15_CONTROL0__NBIF_TRAP_NP_Trap15Stage2Ptr_MASK                                           0x00FFC000L
+#define NBIF_TRAP_NP_15_CONTROL0__NBIF_TRAP_NP_Trap15CrossTrigger_MASK                                        0x0F000000L
+#define NBIF_TRAP_NP_15_CONTROL0__NBIF_TRAP_NP_Trap15Stage2En_MASK                                            0x80000000L
+//NBIF_TRAP_NP_15_ADDRESS_LO
+#define NBIF_TRAP_NP_15_ADDRESS_LO__NBIF_TRAP_NP_Trap15AddrLo__SHIFT                                          0x2
+#define NBIF_TRAP_NP_15_ADDRESS_LO__NBIF_TRAP_NP_Trap15AddrLo_MASK                                            0xFFFFFFFCL
+//NBIF_TRAP_NP_15_ADDRESS_HI
+#define NBIF_TRAP_NP_15_ADDRESS_HI__NBIF_TRAP_NP_Trap15AddrHi__SHIFT                                          0x0
+#define NBIF_TRAP_NP_15_ADDRESS_HI__NBIF_TRAP_NP_Trap15AddrHi_MASK                                            0xFFFFFFFFL
+//NBIF_TRAP_NP_15_COMMAND
+#define NBIF_TRAP_NP_15_COMMAND__NBIF_TRAP_NP_Trap15Cmd0__SHIFT                                               0x0
+#define NBIF_TRAP_NP_15_COMMAND__NBIF_TRAP_NP_Trap15Cmd1__SHIFT                                               0x8
+#define NBIF_TRAP_NP_15_COMMAND__NBIF_TRAP_NP_Trap15Cmd0_MASK                                                 0x0000003FL
+#define NBIF_TRAP_NP_15_COMMAND__NBIF_TRAP_NP_Trap15Cmd1_MASK                                                 0x00003F00L
+//NBIF_TRAP_NP_15_ADDRESS_LO_MASK
+#define NBIF_TRAP_NP_15_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap15AddrLoMask__SHIFT                                 0x2
+#define NBIF_TRAP_NP_15_ADDRESS_LO_MASK__NBIF_TRAP_NP_Trap15AddrLoMask_MASK                                   0xFFFFFFFCL
+//NBIF_TRAP_NP_15_ADDRESS_HI_MASK
+#define NBIF_TRAP_NP_15_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap15AddrHiMask__SHIFT                                 0x0
+#define NBIF_TRAP_NP_15_ADDRESS_HI_MASK__NBIF_TRAP_NP_Trap15AddrHiMask_MASK                                   0xFFFFFFFFL
+//NBIF_TRAP_NP_15_COMMAND_MASK
+#define NBIF_TRAP_NP_15_COMMAND_MASK__NBIF_TRAP_NP_Trap15Cmd0Mask__SHIFT                                      0x0
+#define NBIF_TRAP_NP_15_COMMAND_MASK__NBIF_TRAP_NP_Trap15Cmd1Mask__SHIFT                                      0x8
+#define NBIF_TRAP_NP_15_COMMAND_MASK__NBIF_TRAP_NP_Trap15Cmd0Mask_MASK                                        0x0000003FL
+#define NBIF_TRAP_NP_15_COMMAND_MASK__NBIF_TRAP_NP_Trap15Cmd1Mask_MASK                                        0x00003F00L
+//NBIF_TRAP_NP_S2_CONTROL0
+#define NBIF_TRAP_NP_S2_CONTROL0__NBIF_TRAP_NP_S2_TrapEn__SHIFT                                               0x0
+#define NBIF_TRAP_NP_S2_CONTROL0__NBIF_TRAP_NP_S2_TrapSMUIntr__SHIFT                                          0x3
+#define NBIF_TRAP_NP_S2_CONTROL0__NBIF_TRAP_NP_S2_TrapStage2Offset__SHIFT                                     0x4
+#define NBIF_TRAP_NP_S2_CONTROL0__NBIF_TRAP_NP_S2_TrapStage2Ptr__SHIFT                                        0xe
+#define NBIF_TRAP_NP_S2_CONTROL0__NBIF_TRAP_NP_S2_TrapCrossTrigger__SHIFT                                     0x18
+#define NBIF_TRAP_NP_S2_CONTROL0__NBIF_TRAP_NP_S2_TrapStage2En__SHIFT                                         0x1f
+#define NBIF_TRAP_NP_S2_CONTROL0__NBIF_TRAP_NP_S2_TrapEn_MASK                                                 0x00000001L
+#define NBIF_TRAP_NP_S2_CONTROL0__NBIF_TRAP_NP_S2_TrapSMUIntr_MASK                                            0x00000008L
+#define NBIF_TRAP_NP_S2_CONTROL0__NBIF_TRAP_NP_S2_TrapStage2Offset_MASK                                       0x00003FF0L
+#define NBIF_TRAP_NP_S2_CONTROL0__NBIF_TRAP_NP_S2_TrapStage2Ptr_MASK                                          0x00FFC000L
+#define NBIF_TRAP_NP_S2_CONTROL0__NBIF_TRAP_NP_S2_TrapCrossTrigger_MASK                                       0x0F000000L
+#define NBIF_TRAP_NP_S2_CONTROL0__NBIF_TRAP_NP_S2_TrapStage2En_MASK                                           0x80000000L
+//NBIF_TRAP_NP_S2_ADDRESS_LO
+#define NBIF_TRAP_NP_S2_ADDRESS_LO__NBIF_TRAP_NP_S2_TrapAddrLo__SHIFT                                         0x2
+#define NBIF_TRAP_NP_S2_ADDRESS_LO__NBIF_TRAP_NP_S2_TrapAddrLo_MASK                                           0xFFFFFFFCL
+//NBIF_TRAP_NP_S2_ADDRESS_HI
+#define NBIF_TRAP_NP_S2_ADDRESS_HI__NBIF_TRAP_NP_S2_TrapAddrHi__SHIFT                                         0x0
+#define NBIF_TRAP_NP_S2_ADDRESS_HI__NBIF_TRAP_NP_S2_TrapAddrHi_MASK                                           0xFFFFFFFFL
+//NBIF_TRAP_NP_S2_COMMAND
+#define NBIF_TRAP_NP_S2_COMMAND__NBIF_TRAP_NP_S2_TrapCmd0__SHIFT                                              0x0
+#define NBIF_TRAP_NP_S2_COMMAND__NBIF_TRAP_NP_S2_TrapCmd1__SHIFT                                              0x8
+#define NBIF_TRAP_NP_S2_COMMAND__NBIF_TRAP_NP_S2_TrapCmd0_MASK                                                0x0000003FL
+#define NBIF_TRAP_NP_S2_COMMAND__NBIF_TRAP_NP_S2_TrapCmd1_MASK                                                0x00003F00L
+//NBIF_TRAP_NP_S2_ADDRESS_LO_MASK
+#define NBIF_TRAP_NP_S2_ADDRESS_LO_MASK__NBIF_TRAP_NP_S2_TrapAddrLoMask__SHIFT                                0x2
+#define NBIF_TRAP_NP_S2_ADDRESS_LO_MASK__NBIF_TRAP_NP_S2_TrapAddrLoMask_MASK                                  0xFFFFFFFCL
+//NBIF_TRAP_NP_S2_ADDRESS_HI_MASK
+#define NBIF_TRAP_NP_S2_ADDRESS_HI_MASK__NBIF_TRAP_NP_S2_TrapAddrHiMask__SHIFT                                0x0
+#define NBIF_TRAP_NP_S2_ADDRESS_HI_MASK__NBIF_TRAP_NP_S2_TrapAddrHiMask_MASK                                  0xFFFFFFFFL
+//NBIF_TRAP_NP_S2_COMMAND_MASK
+#define NBIF_TRAP_NP_S2_COMMAND_MASK__NBIF_TRAP_NP_S2_TrapCmd0Mask__SHIFT                                     0x0
+#define NBIF_TRAP_NP_S2_COMMAND_MASK__NBIF_TRAP_NP_S2_TrapCmd1Mask__SHIFT                                     0x8
+#define NBIF_TRAP_NP_S2_COMMAND_MASK__NBIF_TRAP_NP_S2_TrapCmd0Mask_MASK                                       0x0000003FL
+#define NBIF_TRAP_NP_S2_COMMAND_MASK__NBIF_TRAP_NP_S2_TrapCmd1Mask_MASK                                       0x00003F00L
+
+
+// addressBlock: nbif0_nbif0_bif_ras_bif_ras_regblk
+//BIFL_RAS_CENTRAL_CNTL
+#define BIFL_RAS_CENTRAL_CNTL__BIFL_RAS_CONTL_ERREVENT_HST_STALL_DIS__SHIFT                                   0x1b
+#define BIFL_RAS_CENTRAL_CNTL__BIFL_RAS_CONTL_ERREVENT_STALL_DIS__SHIFT                                       0x1c
+#define BIFL_RAS_CENTRAL_CNTL__BIFL_RAS_CONTL_ERREVENT_DIS__SHIFT                                             0x1d
+#define BIFL_RAS_CENTRAL_CNTL__BIFL_RAS_CONTL_INTR_DIS__SHIFT                                                 0x1e
+#define BIFL_RAS_CENTRAL_CNTL__BIFL_LINKDIS_TRIG_EGRESS_STALL_DIS__SHIFT                                      0x1f
+#define BIFL_RAS_CENTRAL_CNTL__BIFL_RAS_CONTL_ERREVENT_HST_STALL_DIS_MASK                                     0x08000000L
+#define BIFL_RAS_CENTRAL_CNTL__BIFL_RAS_CONTL_ERREVENT_STALL_DIS_MASK                                         0x10000000L
+#define BIFL_RAS_CENTRAL_CNTL__BIFL_RAS_CONTL_ERREVENT_DIS_MASK                                               0x20000000L
+#define BIFL_RAS_CENTRAL_CNTL__BIFL_RAS_CONTL_INTR_DIS_MASK                                                   0x40000000L
+#define BIFL_RAS_CENTRAL_CNTL__BIFL_LINKDIS_TRIG_EGRESS_STALL_DIS_MASK                                        0x80000000L
+//BIFL_RAS_CENTRAL_STATUS
+#define BIFL_RAS_CENTRAL_STATUS__BIFL_L2C_EgStall_det__SHIFT                                                  0x0
+#define BIFL_RAS_CENTRAL_STATUS__BIFL_L2C_ErrEvent_det__SHIFT                                                 0x1
+#define BIFL_RAS_CENTRAL_STATUS__BIFL_C2L_EgStall_det__SHIFT                                                  0x2
+#define BIFL_RAS_CENTRAL_STATUS__BIFL_C2L_ErrEvent_det__SHIFT                                                 0x3
+#define BIFL_RAS_CENTRAL_STATUS__BIFL_RasContller_ErrEvent_Recv__SHIFT                                        0x1d
+#define BIFL_RAS_CENTRAL_STATUS__BIFL_RasContller_Intr_Recv__SHIFT                                            0x1e
+#define BIFL_RAS_CENTRAL_STATUS__BIFL_LinkDis_Recv__SHIFT                                                     0x1f
+#define BIFL_RAS_CENTRAL_STATUS__BIFL_L2C_EgStall_det_MASK                                                    0x00000001L
+#define BIFL_RAS_CENTRAL_STATUS__BIFL_L2C_ErrEvent_det_MASK                                                   0x00000002L
+#define BIFL_RAS_CENTRAL_STATUS__BIFL_C2L_EgStall_det_MASK                                                    0x00000004L
+#define BIFL_RAS_CENTRAL_STATUS__BIFL_C2L_ErrEvent_det_MASK                                                   0x00000008L
+#define BIFL_RAS_CENTRAL_STATUS__BIFL_RasContller_ErrEvent_Recv_MASK                                          0x20000000L
+#define BIFL_RAS_CENTRAL_STATUS__BIFL_RasContller_Intr_Recv_MASK                                              0x40000000L
+#define BIFL_RAS_CENTRAL_STATUS__BIFL_LinkDis_Recv_MASK                                                       0x80000000L
+//BIFL_RAS_LEAF0_CTRL
+#define BIFL_RAS_LEAF0_CTRL__ERR_EVENT_DET_EN__SHIFT                                                          0x0
+#define BIFL_RAS_LEAF0_CTRL__POISON_ERREVENT_EN__SHIFT                                                        0x1
+#define BIFL_RAS_LEAF0_CTRL__POISON_STALL_EN__SHIFT                                                           0x2
+#define BIFL_RAS_LEAF0_CTRL__PARITY_ERREVENT_EN__SHIFT                                                        0x3
+#define BIFL_RAS_LEAF0_CTRL__PARITY_STALL_EN__SHIFT                                                           0x4
+#define BIFL_RAS_LEAF0_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT                                                   0x5
+#define BIFL_RAS_LEAF0_CTRL__RCVERREVENT_STALL_EN__SHIFT                                                      0x6
+#define BIFL_RAS_LEAF0_CTRL__ERR_EVENT_GEN_EN__SHIFT                                                          0x8
+#define BIFL_RAS_LEAF0_CTRL__EGRESS_STALL_GEN_EN__SHIFT                                                       0x9
+#define BIFL_RAS_LEAF0_CTRL__ERR_EVENT_PROP_EN__SHIFT                                                         0xa
+#define BIFL_RAS_LEAF0_CTRL__EGRESS_STALL_PROP_EN__SHIFT                                                      0xb
+#define BIFL_RAS_LEAF0_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT                                                     0x10
+#define BIFL_RAS_LEAF0_CTRL__PARITY_ERREVENT_LOG_MCA__SHIFT                                                   0x11
+#define BIFL_RAS_LEAF0_CTRL__POISON_ERREVENT_LOG_MCA__SHIFT                                                   0x12
+#define BIFL_RAS_LEAF0_CTRL__TIMEOUT_ERREVENT_LOG_MCA__SHIFT                                                  0x13
+#define BIFL_RAS_LEAF0_CTRL__RCVERREVENT_ERREVENT_LOG_MCA__SHIFT                                              0x14
+#define BIFL_RAS_LEAF0_CTRL__UCP_EN__SHIFT                                                                    0x15
+#define BIFL_RAS_LEAF0_CTRL__POISON_PROPAGATION_LOG_MCA__SHIFT                                                0x16
+#define BIFL_RAS_LEAF0_CTRL__ERR_EVENT_PARITY_CHECK_EN__SHIFT                                                 0x17
+#define BIFL_RAS_LEAF0_CTRL__ERR_EVENT_DET_EN_MASK                                                            0x00000001L
+#define BIFL_RAS_LEAF0_CTRL__POISON_ERREVENT_EN_MASK                                                          0x00000002L
+#define BIFL_RAS_LEAF0_CTRL__POISON_STALL_EN_MASK                                                             0x00000004L
+#define BIFL_RAS_LEAF0_CTRL__PARITY_ERREVENT_EN_MASK                                                          0x00000008L
+#define BIFL_RAS_LEAF0_CTRL__PARITY_STALL_EN_MASK                                                             0x00000010L
+#define BIFL_RAS_LEAF0_CTRL__RCVERREVENT_ERREVENT_EN_MASK                                                     0x00000020L
+#define BIFL_RAS_LEAF0_CTRL__RCVERREVENT_STALL_EN_MASK                                                        0x00000040L
+#define BIFL_RAS_LEAF0_CTRL__ERR_EVENT_GEN_EN_MASK                                                            0x00000100L
+#define BIFL_RAS_LEAF0_CTRL__EGRESS_STALL_GEN_EN_MASK                                                         0x00000200L
+#define BIFL_RAS_LEAF0_CTRL__ERR_EVENT_PROP_EN_MASK                                                           0x00000400L
+#define BIFL_RAS_LEAF0_CTRL__EGRESS_STALL_PROP_EN_MASK                                                        0x00000800L
+#define BIFL_RAS_LEAF0_CTRL__ERR_EVENT_RAS_INTR_EN_MASK                                                       0x00010000L
+#define BIFL_RAS_LEAF0_CTRL__PARITY_ERREVENT_LOG_MCA_MASK                                                     0x00020000L
+#define BIFL_RAS_LEAF0_CTRL__POISON_ERREVENT_LOG_MCA_MASK                                                     0x00040000L
+#define BIFL_RAS_LEAF0_CTRL__TIMEOUT_ERREVENT_LOG_MCA_MASK                                                    0x00080000L
+#define BIFL_RAS_LEAF0_CTRL__RCVERREVENT_ERREVENT_LOG_MCA_MASK                                                0x00100000L
+#define BIFL_RAS_LEAF0_CTRL__UCP_EN_MASK                                                                      0x00200000L
+#define BIFL_RAS_LEAF0_CTRL__POISON_PROPAGATION_LOG_MCA_MASK                                                  0x00400000L
+#define BIFL_RAS_LEAF0_CTRL__ERR_EVENT_PARITY_CHECK_EN_MASK                                                   0x00800000L
+//BIFL_RAS_LEAF1_CTRL
+#define BIFL_RAS_LEAF1_CTRL__ERR_EVENT_DET_EN__SHIFT                                                          0x0
+#define BIFL_RAS_LEAF1_CTRL__POISON_ERREVENT_EN__SHIFT                                                        0x1
+#define BIFL_RAS_LEAF1_CTRL__POISON_STALL_EN__SHIFT                                                           0x2
+#define BIFL_RAS_LEAF1_CTRL__PARITY_ERREVENT_EN__SHIFT                                                        0x3
+#define BIFL_RAS_LEAF1_CTRL__PARITY_STALL_EN__SHIFT                                                           0x4
+#define BIFL_RAS_LEAF1_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT                                                   0x5
+#define BIFL_RAS_LEAF1_CTRL__RCVERREVENT_STALL_EN__SHIFT                                                      0x6
+#define BIFL_RAS_LEAF1_CTRL__ERR_EVENT_GEN_EN__SHIFT                                                          0x8
+#define BIFL_RAS_LEAF1_CTRL__EGRESS_STALL_GEN_EN__SHIFT                                                       0x9
+#define BIFL_RAS_LEAF1_CTRL__ERR_EVENT_PROP_EN__SHIFT                                                         0xa
+#define BIFL_RAS_LEAF1_CTRL__EGRESS_STALL_PROP_EN__SHIFT                                                      0xb
+#define BIFL_RAS_LEAF1_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT                                                     0x10
+#define BIFL_RAS_LEAF1_CTRL__PARITY_ERREVENT_LOG_MCA__SHIFT                                                   0x11
+#define BIFL_RAS_LEAF1_CTRL__POISON_ERREVENT_LOG_MCA__SHIFT                                                   0x12
+#define BIFL_RAS_LEAF1_CTRL__TIMEOUT_ERREVENT_LOG_MCA__SHIFT                                                  0x13
+#define BIFL_RAS_LEAF1_CTRL__RCVERREVENT_ERREVENT_LOG_MCA__SHIFT                                              0x14
+#define BIFL_RAS_LEAF1_CTRL__UCP_EN__SHIFT                                                                    0x15
+#define BIFL_RAS_LEAF1_CTRL__POISON_PROPAGATION_LOG_MCA__SHIFT                                                0x16
+#define BIFL_RAS_LEAF1_CTRL__ERR_EVENT_PARITY_CHECK_EN__SHIFT                                                 0x17
+#define BIFL_RAS_LEAF1_CTRL__ERR_EVENT_DET_EN_MASK                                                            0x00000001L
+#define BIFL_RAS_LEAF1_CTRL__POISON_ERREVENT_EN_MASK                                                          0x00000002L
+#define BIFL_RAS_LEAF1_CTRL__POISON_STALL_EN_MASK                                                             0x00000004L
+#define BIFL_RAS_LEAF1_CTRL__PARITY_ERREVENT_EN_MASK                                                          0x00000008L
+#define BIFL_RAS_LEAF1_CTRL__PARITY_STALL_EN_MASK                                                             0x00000010L
+#define BIFL_RAS_LEAF1_CTRL__RCVERREVENT_ERREVENT_EN_MASK                                                     0x00000020L
+#define BIFL_RAS_LEAF1_CTRL__RCVERREVENT_STALL_EN_MASK                                                        0x00000040L
+#define BIFL_RAS_LEAF1_CTRL__ERR_EVENT_GEN_EN_MASK                                                            0x00000100L
+#define BIFL_RAS_LEAF1_CTRL__EGRESS_STALL_GEN_EN_MASK                                                         0x00000200L
+#define BIFL_RAS_LEAF1_CTRL__ERR_EVENT_PROP_EN_MASK                                                           0x00000400L
+#define BIFL_RAS_LEAF1_CTRL__EGRESS_STALL_PROP_EN_MASK                                                        0x00000800L
+#define BIFL_RAS_LEAF1_CTRL__ERR_EVENT_RAS_INTR_EN_MASK                                                       0x00010000L
+#define BIFL_RAS_LEAF1_CTRL__PARITY_ERREVENT_LOG_MCA_MASK                                                     0x00020000L
+#define BIFL_RAS_LEAF1_CTRL__POISON_ERREVENT_LOG_MCA_MASK                                                     0x00040000L
+#define BIFL_RAS_LEAF1_CTRL__TIMEOUT_ERREVENT_LOG_MCA_MASK                                                    0x00080000L
+#define BIFL_RAS_LEAF1_CTRL__RCVERREVENT_ERREVENT_LOG_MCA_MASK                                                0x00100000L
+#define BIFL_RAS_LEAF1_CTRL__UCP_EN_MASK                                                                      0x00200000L
+#define BIFL_RAS_LEAF1_CTRL__POISON_PROPAGATION_LOG_MCA_MASK                                                  0x00400000L
+#define BIFL_RAS_LEAF1_CTRL__ERR_EVENT_PARITY_CHECK_EN_MASK                                                   0x00800000L
+//BIFL_RAS_LEAF2_CTRL
+#define BIFL_RAS_LEAF2_CTRL__ERR_EVENT_DET_EN__SHIFT                                                          0x0
+#define BIFL_RAS_LEAF2_CTRL__POISON_ERREVENT_EN__SHIFT                                                        0x1
+#define BIFL_RAS_LEAF2_CTRL__POISON_STALL_EN__SHIFT                                                           0x2
+#define BIFL_RAS_LEAF2_CTRL__PARITY_ERREVENT_EN__SHIFT                                                        0x3
+#define BIFL_RAS_LEAF2_CTRL__PARITY_STALL_EN__SHIFT                                                           0x4
+#define BIFL_RAS_LEAF2_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT                                                   0x5
+#define BIFL_RAS_LEAF2_CTRL__RCVERREVENT_STALL_EN__SHIFT                                                      0x6
+#define BIFL_RAS_LEAF2_CTRL__ERR_EVENT_GEN_EN__SHIFT                                                          0x8
+#define BIFL_RAS_LEAF2_CTRL__EGRESS_STALL_GEN_EN__SHIFT                                                       0x9
+#define BIFL_RAS_LEAF2_CTRL__ERR_EVENT_PROP_EN__SHIFT                                                         0xa
+#define BIFL_RAS_LEAF2_CTRL__EGRESS_STALL_PROP_EN__SHIFT                                                      0xb
+#define BIFL_RAS_LEAF2_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT                                                     0x10
+#define BIFL_RAS_LEAF2_CTRL__PARITY_ERREVENT_LOG_MCA__SHIFT                                                   0x11
+#define BIFL_RAS_LEAF2_CTRL__POISON_ERREVENT_LOG_MCA__SHIFT                                                   0x12
+#define BIFL_RAS_LEAF2_CTRL__TIMEOUT_ERREVENT_LOG_MCA__SHIFT                                                  0x13
+#define BIFL_RAS_LEAF2_CTRL__RCVERREVENT_ERREVENT_LOG_MCA__SHIFT                                              0x14
+#define BIFL_RAS_LEAF2_CTRL__UCP_EN__SHIFT                                                                    0x15
+#define BIFL_RAS_LEAF2_CTRL__POISON_PROPAGATION_LOG_MCA__SHIFT                                                0x16
+#define BIFL_RAS_LEAF2_CTRL__ERR_EVENT_PARITY_CHECK_EN__SHIFT                                                 0x17
+#define BIFL_RAS_LEAF2_CTRL__ERR_EVENT_DET_EN_MASK                                                            0x00000001L
+#define BIFL_RAS_LEAF2_CTRL__POISON_ERREVENT_EN_MASK                                                          0x00000002L
+#define BIFL_RAS_LEAF2_CTRL__POISON_STALL_EN_MASK                                                             0x00000004L
+#define BIFL_RAS_LEAF2_CTRL__PARITY_ERREVENT_EN_MASK                                                          0x00000008L
+#define BIFL_RAS_LEAF2_CTRL__PARITY_STALL_EN_MASK                                                             0x00000010L
+#define BIFL_RAS_LEAF2_CTRL__RCVERREVENT_ERREVENT_EN_MASK                                                     0x00000020L
+#define BIFL_RAS_LEAF2_CTRL__RCVERREVENT_STALL_EN_MASK                                                        0x00000040L
+#define BIFL_RAS_LEAF2_CTRL__ERR_EVENT_GEN_EN_MASK                                                            0x00000100L
+#define BIFL_RAS_LEAF2_CTRL__EGRESS_STALL_GEN_EN_MASK                                                         0x00000200L
+#define BIFL_RAS_LEAF2_CTRL__ERR_EVENT_PROP_EN_MASK                                                           0x00000400L
+#define BIFL_RAS_LEAF2_CTRL__EGRESS_STALL_PROP_EN_MASK                                                        0x00000800L
+#define BIFL_RAS_LEAF2_CTRL__ERR_EVENT_RAS_INTR_EN_MASK                                                       0x00010000L
+#define BIFL_RAS_LEAF2_CTRL__PARITY_ERREVENT_LOG_MCA_MASK                                                     0x00020000L
+#define BIFL_RAS_LEAF2_CTRL__POISON_ERREVENT_LOG_MCA_MASK                                                     0x00040000L
+#define BIFL_RAS_LEAF2_CTRL__TIMEOUT_ERREVENT_LOG_MCA_MASK                                                    0x00080000L
+#define BIFL_RAS_LEAF2_CTRL__RCVERREVENT_ERREVENT_LOG_MCA_MASK                                                0x00100000L
+#define BIFL_RAS_LEAF2_CTRL__UCP_EN_MASK                                                                      0x00200000L
+#define BIFL_RAS_LEAF2_CTRL__POISON_PROPAGATION_LOG_MCA_MASK                                                  0x00400000L
+#define BIFL_RAS_LEAF2_CTRL__ERR_EVENT_PARITY_CHECK_EN_MASK                                                   0x00800000L
+//BIFL_RAS_LEAF3_CTRL
+#define BIFL_RAS_LEAF3_CTRL__ERR_EVENT_DET_EN__SHIFT                                                          0x0
+#define BIFL_RAS_LEAF3_CTRL__POISON_ERREVENT_EN__SHIFT                                                        0x1
+#define BIFL_RAS_LEAF3_CTRL__POISON_STALL_EN__SHIFT                                                           0x2
+#define BIFL_RAS_LEAF3_CTRL__PARITY_ERREVENT_EN__SHIFT                                                        0x3
+#define BIFL_RAS_LEAF3_CTRL__PARITY_STALL_EN__SHIFT                                                           0x4
+#define BIFL_RAS_LEAF3_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT                                                   0x5
+#define BIFL_RAS_LEAF3_CTRL__RCVERREVENT_STALL_EN__SHIFT                                                      0x6
+#define BIFL_RAS_LEAF3_CTRL__ERR_EVENT_GEN_EN__SHIFT                                                          0x8
+#define BIFL_RAS_LEAF3_CTRL__EGRESS_STALL_GEN_EN__SHIFT                                                       0x9
+#define BIFL_RAS_LEAF3_CTRL__ERR_EVENT_PROP_EN__SHIFT                                                         0xa
+#define BIFL_RAS_LEAF3_CTRL__EGRESS_STALL_PROP_EN__SHIFT                                                      0xb
+#define BIFL_RAS_LEAF3_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT                                                     0x10
+#define BIFL_RAS_LEAF3_CTRL__PARITY_ERREVENT_LOG_MCA__SHIFT                                                   0x11
+#define BIFL_RAS_LEAF3_CTRL__POISON_ERREVENT_LOG_MCA__SHIFT                                                   0x12
+#define BIFL_RAS_LEAF3_CTRL__TIMEOUT_ERREVENT_LOG_MCA__SHIFT                                                  0x13
+#define BIFL_RAS_LEAF3_CTRL__RCVERREVENT_ERREVENT_LOG_MCA__SHIFT                                              0x14
+#define BIFL_RAS_LEAF3_CTRL__UCP_EN__SHIFT                                                                    0x15
+#define BIFL_RAS_LEAF3_CTRL__POISON_PROPAGATION_LOG_MCA__SHIFT                                                0x16
+#define BIFL_RAS_LEAF3_CTRL__ERR_EVENT_PARITY_CHECK_EN__SHIFT                                                 0x17
+#define BIFL_RAS_LEAF3_CTRL__ERR_EVENT_DET_EN_MASK                                                            0x00000001L
+#define BIFL_RAS_LEAF3_CTRL__POISON_ERREVENT_EN_MASK                                                          0x00000002L
+#define BIFL_RAS_LEAF3_CTRL__POISON_STALL_EN_MASK                                                             0x00000004L
+#define BIFL_RAS_LEAF3_CTRL__PARITY_ERREVENT_EN_MASK                                                          0x00000008L
+#define BIFL_RAS_LEAF3_CTRL__PARITY_STALL_EN_MASK                                                             0x00000010L
+#define BIFL_RAS_LEAF3_CTRL__RCVERREVENT_ERREVENT_EN_MASK                                                     0x00000020L
+#define BIFL_RAS_LEAF3_CTRL__RCVERREVENT_STALL_EN_MASK                                                        0x00000040L
+#define BIFL_RAS_LEAF3_CTRL__ERR_EVENT_GEN_EN_MASK                                                            0x00000100L
+#define BIFL_RAS_LEAF3_CTRL__EGRESS_STALL_GEN_EN_MASK                                                         0x00000200L
+#define BIFL_RAS_LEAF3_CTRL__ERR_EVENT_PROP_EN_MASK                                                           0x00000400L
+#define BIFL_RAS_LEAF3_CTRL__EGRESS_STALL_PROP_EN_MASK                                                        0x00000800L
+#define BIFL_RAS_LEAF3_CTRL__ERR_EVENT_RAS_INTR_EN_MASK                                                       0x00010000L
+#define BIFL_RAS_LEAF3_CTRL__PARITY_ERREVENT_LOG_MCA_MASK                                                     0x00020000L
+#define BIFL_RAS_LEAF3_CTRL__POISON_ERREVENT_LOG_MCA_MASK                                                     0x00040000L
+#define BIFL_RAS_LEAF3_CTRL__TIMEOUT_ERREVENT_LOG_MCA_MASK                                                    0x00080000L
+#define BIFL_RAS_LEAF3_CTRL__RCVERREVENT_ERREVENT_LOG_MCA_MASK                                                0x00100000L
+#define BIFL_RAS_LEAF3_CTRL__UCP_EN_MASK                                                                      0x00200000L
+#define BIFL_RAS_LEAF3_CTRL__POISON_PROPAGATION_LOG_MCA_MASK                                                  0x00400000L
+#define BIFL_RAS_LEAF3_CTRL__ERR_EVENT_PARITY_CHECK_EN_MASK                                                   0x00800000L
+//BIFL_RAS_LEAF4_CTRL
+#define BIFL_RAS_LEAF4_CTRL__ERR_EVENT_DET_EN__SHIFT                                                          0x0
+#define BIFL_RAS_LEAF4_CTRL__POISON_ERREVENT_EN__SHIFT                                                        0x1
+#define BIFL_RAS_LEAF4_CTRL__POISON_STALL_EN__SHIFT                                                           0x2
+#define BIFL_RAS_LEAF4_CTRL__PARITY_ERREVENT_EN__SHIFT                                                        0x3
+#define BIFL_RAS_LEAF4_CTRL__PARITY_STALL_EN__SHIFT                                                           0x4
+#define BIFL_RAS_LEAF4_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT                                                   0x5
+#define BIFL_RAS_LEAF4_CTRL__RCVERREVENT_STALL_EN__SHIFT                                                      0x6
+#define BIFL_RAS_LEAF4_CTRL__ERR_EVENT_GEN_EN__SHIFT                                                          0x8
+#define BIFL_RAS_LEAF4_CTRL__EGRESS_STALL_GEN_EN__SHIFT                                                       0x9
+#define BIFL_RAS_LEAF4_CTRL__ERR_EVENT_PROP_EN__SHIFT                                                         0xa
+#define BIFL_RAS_LEAF4_CTRL__EGRESS_STALL_PROP_EN__SHIFT                                                      0xb
+#define BIFL_RAS_LEAF4_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT                                                     0x10
+#define BIFL_RAS_LEAF4_CTRL__PARITY_ERREVENT_LOG_MCA__SHIFT                                                   0x11
+#define BIFL_RAS_LEAF4_CTRL__POISON_ERREVENT_LOG_MCA__SHIFT                                                   0x12
+#define BIFL_RAS_LEAF4_CTRL__TIMEOUT_ERREVENT_LOG_MCA__SHIFT                                                  0x13
+#define BIFL_RAS_LEAF4_CTRL__RCVERREVENT_ERREVENT_LOG_MCA__SHIFT                                              0x14
+#define BIFL_RAS_LEAF4_CTRL__UCP_EN__SHIFT                                                                    0x15
+#define BIFL_RAS_LEAF4_CTRL__POISON_PROPAGATION_LOG_MCA__SHIFT                                                0x16
+#define BIFL_RAS_LEAF4_CTRL__ERR_EVENT_PARITY_CHECK_EN__SHIFT                                                 0x17
+#define BIFL_RAS_LEAF4_CTRL__ERR_EVENT_DET_EN_MASK                                                            0x00000001L
+#define BIFL_RAS_LEAF4_CTRL__POISON_ERREVENT_EN_MASK                                                          0x00000002L
+#define BIFL_RAS_LEAF4_CTRL__POISON_STALL_EN_MASK                                                             0x00000004L
+#define BIFL_RAS_LEAF4_CTRL__PARITY_ERREVENT_EN_MASK                                                          0x00000008L
+#define BIFL_RAS_LEAF4_CTRL__PARITY_STALL_EN_MASK                                                             0x00000010L
+#define BIFL_RAS_LEAF4_CTRL__RCVERREVENT_ERREVENT_EN_MASK                                                     0x00000020L
+#define BIFL_RAS_LEAF4_CTRL__RCVERREVENT_STALL_EN_MASK                                                        0x00000040L
+#define BIFL_RAS_LEAF4_CTRL__ERR_EVENT_GEN_EN_MASK                                                            0x00000100L
+#define BIFL_RAS_LEAF4_CTRL__EGRESS_STALL_GEN_EN_MASK                                                         0x00000200L
+#define BIFL_RAS_LEAF4_CTRL__ERR_EVENT_PROP_EN_MASK                                                           0x00000400L
+#define BIFL_RAS_LEAF4_CTRL__EGRESS_STALL_PROP_EN_MASK                                                        0x00000800L
+#define BIFL_RAS_LEAF4_CTRL__ERR_EVENT_RAS_INTR_EN_MASK                                                       0x00010000L
+#define BIFL_RAS_LEAF4_CTRL__PARITY_ERREVENT_LOG_MCA_MASK                                                     0x00020000L
+#define BIFL_RAS_LEAF4_CTRL__POISON_ERREVENT_LOG_MCA_MASK                                                     0x00040000L
+#define BIFL_RAS_LEAF4_CTRL__TIMEOUT_ERREVENT_LOG_MCA_MASK                                                    0x00080000L
+#define BIFL_RAS_LEAF4_CTRL__RCVERREVENT_ERREVENT_LOG_MCA_MASK                                                0x00100000L
+#define BIFL_RAS_LEAF4_CTRL__UCP_EN_MASK                                                                      0x00200000L
+#define BIFL_RAS_LEAF4_CTRL__POISON_PROPAGATION_LOG_MCA_MASK                                                  0x00400000L
+#define BIFL_RAS_LEAF4_CTRL__ERR_EVENT_PARITY_CHECK_EN_MASK                                                   0x00800000L
+//BIFL_RAS_LEAF5_CTRL
+#define BIFL_RAS_LEAF5_CTRL__ERR_EVENT_DET_EN__SHIFT                                                          0x0
+#define BIFL_RAS_LEAF5_CTRL__POISON_ERREVENT_EN__SHIFT                                                        0x1
+#define BIFL_RAS_LEAF5_CTRL__POISON_STALL_EN__SHIFT                                                           0x2
+#define BIFL_RAS_LEAF5_CTRL__PARITY_ERREVENT_EN__SHIFT                                                        0x3
+#define BIFL_RAS_LEAF5_CTRL__PARITY_STALL_EN__SHIFT                                                           0x4
+#define BIFL_RAS_LEAF5_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT                                                   0x5
+#define BIFL_RAS_LEAF5_CTRL__RCVERREVENT_STALL_EN__SHIFT                                                      0x6
+#define BIFL_RAS_LEAF5_CTRL__ERR_EVENT_GEN_EN__SHIFT                                                          0x8
+#define BIFL_RAS_LEAF5_CTRL__EGRESS_STALL_GEN_EN__SHIFT                                                       0x9
+#define BIFL_RAS_LEAF5_CTRL__ERR_EVENT_PROP_EN__SHIFT                                                         0xa
+#define BIFL_RAS_LEAF5_CTRL__EGRESS_STALL_PROP_EN__SHIFT                                                      0xb
+#define BIFL_RAS_LEAF5_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT                                                     0x10
+#define BIFL_RAS_LEAF5_CTRL__PARITY_ERREVENT_LOG_MCA__SHIFT                                                   0x11
+#define BIFL_RAS_LEAF5_CTRL__POISON_ERREVENT_LOG_MCA__SHIFT                                                   0x12
+#define BIFL_RAS_LEAF5_CTRL__TIMEOUT_ERREVENT_LOG_MCA__SHIFT                                                  0x13
+#define BIFL_RAS_LEAF5_CTRL__RCVERREVENT_ERREVENT_LOG_MCA__SHIFT                                              0x14
+#define BIFL_RAS_LEAF5_CTRL__UCP_EN__SHIFT                                                                    0x15
+#define BIFL_RAS_LEAF5_CTRL__POISON_PROPAGATION_LOG_MCA__SHIFT                                                0x16
+#define BIFL_RAS_LEAF5_CTRL__ERR_EVENT_PARITY_CHECK_EN__SHIFT                                                 0x17
+#define BIFL_RAS_LEAF5_CTRL__ERR_EVENT_DET_EN_MASK                                                            0x00000001L
+#define BIFL_RAS_LEAF5_CTRL__POISON_ERREVENT_EN_MASK                                                          0x00000002L
+#define BIFL_RAS_LEAF5_CTRL__POISON_STALL_EN_MASK                                                             0x00000004L
+#define BIFL_RAS_LEAF5_CTRL__PARITY_ERREVENT_EN_MASK                                                          0x00000008L
+#define BIFL_RAS_LEAF5_CTRL__PARITY_STALL_EN_MASK                                                             0x00000010L
+#define BIFL_RAS_LEAF5_CTRL__RCVERREVENT_ERREVENT_EN_MASK                                                     0x00000020L
+#define BIFL_RAS_LEAF5_CTRL__RCVERREVENT_STALL_EN_MASK                                                        0x00000040L
+#define BIFL_RAS_LEAF5_CTRL__ERR_EVENT_GEN_EN_MASK                                                            0x00000100L
+#define BIFL_RAS_LEAF5_CTRL__EGRESS_STALL_GEN_EN_MASK                                                         0x00000200L
+#define BIFL_RAS_LEAF5_CTRL__ERR_EVENT_PROP_EN_MASK                                                           0x00000400L
+#define BIFL_RAS_LEAF5_CTRL__EGRESS_STALL_PROP_EN_MASK                                                        0x00000800L
+#define BIFL_RAS_LEAF5_CTRL__ERR_EVENT_RAS_INTR_EN_MASK                                                       0x00010000L
+#define BIFL_RAS_LEAF5_CTRL__PARITY_ERREVENT_LOG_MCA_MASK                                                     0x00020000L
+#define BIFL_RAS_LEAF5_CTRL__POISON_ERREVENT_LOG_MCA_MASK                                                     0x00040000L
+#define BIFL_RAS_LEAF5_CTRL__TIMEOUT_ERREVENT_LOG_MCA_MASK                                                    0x00080000L
+#define BIFL_RAS_LEAF5_CTRL__RCVERREVENT_ERREVENT_LOG_MCA_MASK                                                0x00100000L
+#define BIFL_RAS_LEAF5_CTRL__UCP_EN_MASK                                                                      0x00200000L
+#define BIFL_RAS_LEAF5_CTRL__POISON_PROPAGATION_LOG_MCA_MASK                                                  0x00400000L
+#define BIFL_RAS_LEAF5_CTRL__ERR_EVENT_PARITY_CHECK_EN_MASK                                                   0x00800000L
+//BIFL_RAS_LEAF6_CTRL
+#define BIFL_RAS_LEAF6_CTRL__ERR_EVENT_DET_EN__SHIFT                                                          0x0
+#define BIFL_RAS_LEAF6_CTRL__POISON_ERREVENT_EN__SHIFT                                                        0x1
+#define BIFL_RAS_LEAF6_CTRL__POISON_STALL_EN__SHIFT                                                           0x2
+#define BIFL_RAS_LEAF6_CTRL__PARITY_ERREVENT_EN__SHIFT                                                        0x3
+#define BIFL_RAS_LEAF6_CTRL__PARITY_STALL_EN__SHIFT                                                           0x4
+#define BIFL_RAS_LEAF6_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT                                                   0x5
+#define BIFL_RAS_LEAF6_CTRL__RCVERREVENT_STALL_EN__SHIFT                                                      0x6
+#define BIFL_RAS_LEAF6_CTRL__ERR_EVENT_GEN_EN__SHIFT                                                          0x8
+#define BIFL_RAS_LEAF6_CTRL__EGRESS_STALL_GEN_EN__SHIFT                                                       0x9
+#define BIFL_RAS_LEAF6_CTRL__ERR_EVENT_PROP_EN__SHIFT                                                         0xa
+#define BIFL_RAS_LEAF6_CTRL__EGRESS_STALL_PROP_EN__SHIFT                                                      0xb
+#define BIFL_RAS_LEAF6_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT                                                     0x10
+#define BIFL_RAS_LEAF6_CTRL__PARITY_ERREVENT_LOG_MCA__SHIFT                                                   0x11
+#define BIFL_RAS_LEAF6_CTRL__POISON_ERREVENT_LOG_MCA__SHIFT                                                   0x12
+#define BIFL_RAS_LEAF6_CTRL__TIMEOUT_ERREVENT_LOG_MCA__SHIFT                                                  0x13
+#define BIFL_RAS_LEAF6_CTRL__RCVERREVENT_ERREVENT_LOG_MCA__SHIFT                                              0x14
+#define BIFL_RAS_LEAF6_CTRL__UCP_EN__SHIFT                                                                    0x15
+#define BIFL_RAS_LEAF6_CTRL__POISON_PROPAGATION_LOG_MCA__SHIFT                                                0x16
+#define BIFL_RAS_LEAF6_CTRL__ERR_EVENT_PARITY_CHECK_EN__SHIFT                                                 0x17
+#define BIFL_RAS_LEAF6_CTRL__ERR_EVENT_DET_EN_MASK                                                            0x00000001L
+#define BIFL_RAS_LEAF6_CTRL__POISON_ERREVENT_EN_MASK                                                          0x00000002L
+#define BIFL_RAS_LEAF6_CTRL__POISON_STALL_EN_MASK                                                             0x00000004L
+#define BIFL_RAS_LEAF6_CTRL__PARITY_ERREVENT_EN_MASK                                                          0x00000008L
+#define BIFL_RAS_LEAF6_CTRL__PARITY_STALL_EN_MASK                                                             0x00000010L
+#define BIFL_RAS_LEAF6_CTRL__RCVERREVENT_ERREVENT_EN_MASK                                                     0x00000020L
+#define BIFL_RAS_LEAF6_CTRL__RCVERREVENT_STALL_EN_MASK                                                        0x00000040L
+#define BIFL_RAS_LEAF6_CTRL__ERR_EVENT_GEN_EN_MASK                                                            0x00000100L
+#define BIFL_RAS_LEAF6_CTRL__EGRESS_STALL_GEN_EN_MASK                                                         0x00000200L
+#define BIFL_RAS_LEAF6_CTRL__ERR_EVENT_PROP_EN_MASK                                                           0x00000400L
+#define BIFL_RAS_LEAF6_CTRL__EGRESS_STALL_PROP_EN_MASK                                                        0x00000800L
+#define BIFL_RAS_LEAF6_CTRL__ERR_EVENT_RAS_INTR_EN_MASK                                                       0x00010000L
+#define BIFL_RAS_LEAF6_CTRL__PARITY_ERREVENT_LOG_MCA_MASK                                                     0x00020000L
+#define BIFL_RAS_LEAF6_CTRL__POISON_ERREVENT_LOG_MCA_MASK                                                     0x00040000L
+#define BIFL_RAS_LEAF6_CTRL__TIMEOUT_ERREVENT_LOG_MCA_MASK                                                    0x00080000L
+#define BIFL_RAS_LEAF6_CTRL__RCVERREVENT_ERREVENT_LOG_MCA_MASK                                                0x00100000L
+#define BIFL_RAS_LEAF6_CTRL__UCP_EN_MASK                                                                      0x00200000L
+#define BIFL_RAS_LEAF6_CTRL__POISON_PROPAGATION_LOG_MCA_MASK                                                  0x00400000L
+#define BIFL_RAS_LEAF6_CTRL__ERR_EVENT_PARITY_CHECK_EN_MASK                                                   0x00800000L
+//BIFL_RAS_LEAF7_CTRL
+#define BIFL_RAS_LEAF7_CTRL__ERR_EVENT_DET_EN__SHIFT                                                          0x0
+#define BIFL_RAS_LEAF7_CTRL__POISON_ERREVENT_EN__SHIFT                                                        0x1
+#define BIFL_RAS_LEAF7_CTRL__POISON_STALL_EN__SHIFT                                                           0x2
+#define BIFL_RAS_LEAF7_CTRL__PARITY_ERREVENT_EN__SHIFT                                                        0x3
+#define BIFL_RAS_LEAF7_CTRL__PARITY_STALL_EN__SHIFT                                                           0x4
+#define BIFL_RAS_LEAF7_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT                                                   0x5
+#define BIFL_RAS_LEAF7_CTRL__RCVERREVENT_STALL_EN__SHIFT                                                      0x6
+#define BIFL_RAS_LEAF7_CTRL__ERR_EVENT_GEN_EN__SHIFT                                                          0x8
+#define BIFL_RAS_LEAF7_CTRL__EGRESS_STALL_GEN_EN__SHIFT                                                       0x9
+#define BIFL_RAS_LEAF7_CTRL__ERR_EVENT_PROP_EN__SHIFT                                                         0xa
+#define BIFL_RAS_LEAF7_CTRL__EGRESS_STALL_PROP_EN__SHIFT                                                      0xb
+#define BIFL_RAS_LEAF7_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT                                                     0x10
+#define BIFL_RAS_LEAF7_CTRL__PARITY_ERREVENT_LOG_MCA__SHIFT                                                   0x11
+#define BIFL_RAS_LEAF7_CTRL__POISON_ERREVENT_LOG_MCA__SHIFT                                                   0x12
+#define BIFL_RAS_LEAF7_CTRL__TIMEOUT_ERREVENT_LOG_MCA__SHIFT                                                  0x13
+#define BIFL_RAS_LEAF7_CTRL__RCVERREVENT_ERREVENT_LOG_MCA__SHIFT                                              0x14
+#define BIFL_RAS_LEAF7_CTRL__UCP_EN__SHIFT                                                                    0x15
+#define BIFL_RAS_LEAF7_CTRL__POISON_PROPAGATION_LOG_MCA__SHIFT                                                0x16
+#define BIFL_RAS_LEAF7_CTRL__ERR_EVENT_PARITY_CHECK_EN__SHIFT                                                 0x17
+#define BIFL_RAS_LEAF7_CTRL__ERR_EVENT_DET_EN_MASK                                                            0x00000001L
+#define BIFL_RAS_LEAF7_CTRL__POISON_ERREVENT_EN_MASK                                                          0x00000002L
+#define BIFL_RAS_LEAF7_CTRL__POISON_STALL_EN_MASK                                                             0x00000004L
+#define BIFL_RAS_LEAF7_CTRL__PARITY_ERREVENT_EN_MASK                                                          0x00000008L
+#define BIFL_RAS_LEAF7_CTRL__PARITY_STALL_EN_MASK                                                             0x00000010L
+#define BIFL_RAS_LEAF7_CTRL__RCVERREVENT_ERREVENT_EN_MASK                                                     0x00000020L
+#define BIFL_RAS_LEAF7_CTRL__RCVERREVENT_STALL_EN_MASK                                                        0x00000040L
+#define BIFL_RAS_LEAF7_CTRL__ERR_EVENT_GEN_EN_MASK                                                            0x00000100L
+#define BIFL_RAS_LEAF7_CTRL__EGRESS_STALL_GEN_EN_MASK                                                         0x00000200L
+#define BIFL_RAS_LEAF7_CTRL__ERR_EVENT_PROP_EN_MASK                                                           0x00000400L
+#define BIFL_RAS_LEAF7_CTRL__EGRESS_STALL_PROP_EN_MASK                                                        0x00000800L
+#define BIFL_RAS_LEAF7_CTRL__ERR_EVENT_RAS_INTR_EN_MASK                                                       0x00010000L
+#define BIFL_RAS_LEAF7_CTRL__PARITY_ERREVENT_LOG_MCA_MASK                                                     0x00020000L
+#define BIFL_RAS_LEAF7_CTRL__POISON_ERREVENT_LOG_MCA_MASK                                                     0x00040000L
+#define BIFL_RAS_LEAF7_CTRL__TIMEOUT_ERREVENT_LOG_MCA_MASK                                                    0x00080000L
+#define BIFL_RAS_LEAF7_CTRL__RCVERREVENT_ERREVENT_LOG_MCA_MASK                                                0x00100000L
+#define BIFL_RAS_LEAF7_CTRL__UCP_EN_MASK                                                                      0x00200000L
+#define BIFL_RAS_LEAF7_CTRL__POISON_PROPAGATION_LOG_MCA_MASK                                                  0x00400000L
+#define BIFL_RAS_LEAF7_CTRL__ERR_EVENT_PARITY_CHECK_EN_MASK                                                   0x00800000L
+//BIFL_RAS_LEAF8_CTRL
+#define BIFL_RAS_LEAF8_CTRL__ERR_EVENT_DET_EN__SHIFT                                                          0x0
+#define BIFL_RAS_LEAF8_CTRL__POISON_ERREVENT_EN__SHIFT                                                        0x1
+#define BIFL_RAS_LEAF8_CTRL__POISON_STALL_EN__SHIFT                                                           0x2
+#define BIFL_RAS_LEAF8_CTRL__PARITY_ERREVENT_EN__SHIFT                                                        0x3
+#define BIFL_RAS_LEAF8_CTRL__PARITY_STALL_EN__SHIFT                                                           0x4
+#define BIFL_RAS_LEAF8_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT                                                   0x5
+#define BIFL_RAS_LEAF8_CTRL__RCVERREVENT_STALL_EN__SHIFT                                                      0x6
+#define BIFL_RAS_LEAF8_CTRL__ERR_EVENT_GEN_EN__SHIFT                                                          0x8
+#define BIFL_RAS_LEAF8_CTRL__EGRESS_STALL_GEN_EN__SHIFT                                                       0x9
+#define BIFL_RAS_LEAF8_CTRL__ERR_EVENT_PROP_EN__SHIFT                                                         0xa
+#define BIFL_RAS_LEAF8_CTRL__EGRESS_STALL_PROP_EN__SHIFT                                                      0xb
+#define BIFL_RAS_LEAF8_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT                                                     0x10
+#define BIFL_RAS_LEAF8_CTRL__PARITY_ERREVENT_LOG_MCA__SHIFT                                                   0x11
+#define BIFL_RAS_LEAF8_CTRL__POISON_ERREVENT_LOG_MCA__SHIFT                                                   0x12
+#define BIFL_RAS_LEAF8_CTRL__TIMEOUT_ERREVENT_LOG_MCA__SHIFT                                                  0x13
+#define BIFL_RAS_LEAF8_CTRL__RCVERREVENT_ERREVENT_LOG_MCA__SHIFT                                              0x14
+#define BIFL_RAS_LEAF8_CTRL__UCP_EN__SHIFT                                                                    0x15
+#define BIFL_RAS_LEAF8_CTRL__POISON_PROPAGATION_LOG_MCA__SHIFT                                                0x16
+#define BIFL_RAS_LEAF8_CTRL__ERR_EVENT_PARITY_CHECK_EN__SHIFT                                                 0x17
+#define BIFL_RAS_LEAF8_CTRL__ERR_EVENT_DET_EN_MASK                                                            0x00000001L
+#define BIFL_RAS_LEAF8_CTRL__POISON_ERREVENT_EN_MASK                                                          0x00000002L
+#define BIFL_RAS_LEAF8_CTRL__POISON_STALL_EN_MASK                                                             0x00000004L
+#define BIFL_RAS_LEAF8_CTRL__PARITY_ERREVENT_EN_MASK                                                          0x00000008L
+#define BIFL_RAS_LEAF8_CTRL__PARITY_STALL_EN_MASK                                                             0x00000010L
+#define BIFL_RAS_LEAF8_CTRL__RCVERREVENT_ERREVENT_EN_MASK                                                     0x00000020L
+#define BIFL_RAS_LEAF8_CTRL__RCVERREVENT_STALL_EN_MASK                                                        0x00000040L
+#define BIFL_RAS_LEAF8_CTRL__ERR_EVENT_GEN_EN_MASK                                                            0x00000100L
+#define BIFL_RAS_LEAF8_CTRL__EGRESS_STALL_GEN_EN_MASK                                                         0x00000200L
+#define BIFL_RAS_LEAF8_CTRL__ERR_EVENT_PROP_EN_MASK                                                           0x00000400L
+#define BIFL_RAS_LEAF8_CTRL__EGRESS_STALL_PROP_EN_MASK                                                        0x00000800L
+#define BIFL_RAS_LEAF8_CTRL__ERR_EVENT_RAS_INTR_EN_MASK                                                       0x00010000L
+#define BIFL_RAS_LEAF8_CTRL__PARITY_ERREVENT_LOG_MCA_MASK                                                     0x00020000L
+#define BIFL_RAS_LEAF8_CTRL__POISON_ERREVENT_LOG_MCA_MASK                                                     0x00040000L
+#define BIFL_RAS_LEAF8_CTRL__TIMEOUT_ERREVENT_LOG_MCA_MASK                                                    0x00080000L
+#define BIFL_RAS_LEAF8_CTRL__RCVERREVENT_ERREVENT_LOG_MCA_MASK                                                0x00100000L
+#define BIFL_RAS_LEAF8_CTRL__UCP_EN_MASK                                                                      0x00200000L
+#define BIFL_RAS_LEAF8_CTRL__POISON_PROPAGATION_LOG_MCA_MASK                                                  0x00400000L
+#define BIFL_RAS_LEAF8_CTRL__ERR_EVENT_PARITY_CHECK_EN_MASK                                                   0x00800000L
+//BIFL_RAS_LEAF9_CTRL
+#define BIFL_RAS_LEAF9_CTRL__ERR_EVENT_DET_EN__SHIFT                                                          0x0
+#define BIFL_RAS_LEAF9_CTRL__POISON_ERREVENT_EN__SHIFT                                                        0x1
+#define BIFL_RAS_LEAF9_CTRL__POISON_STALL_EN__SHIFT                                                           0x2
+#define BIFL_RAS_LEAF9_CTRL__PARITY_ERREVENT_EN__SHIFT                                                        0x3
+#define BIFL_RAS_LEAF9_CTRL__PARITY_STALL_EN__SHIFT                                                           0x4
+#define BIFL_RAS_LEAF9_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT                                                   0x5
+#define BIFL_RAS_LEAF9_CTRL__RCVERREVENT_STALL_EN__SHIFT                                                      0x6
+#define BIFL_RAS_LEAF9_CTRL__ERR_EVENT_GEN_EN__SHIFT                                                          0x8
+#define BIFL_RAS_LEAF9_CTRL__EGRESS_STALL_GEN_EN__SHIFT                                                       0x9
+#define BIFL_RAS_LEAF9_CTRL__ERR_EVENT_PROP_EN__SHIFT                                                         0xa
+#define BIFL_RAS_LEAF9_CTRL__EGRESS_STALL_PROP_EN__SHIFT                                                      0xb
+#define BIFL_RAS_LEAF9_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT                                                     0x10
+#define BIFL_RAS_LEAF9_CTRL__PARITY_ERREVENT_LOG_MCA__SHIFT                                                   0x11
+#define BIFL_RAS_LEAF9_CTRL__POISON_ERREVENT_LOG_MCA__SHIFT                                                   0x12
+#define BIFL_RAS_LEAF9_CTRL__TIMEOUT_ERREVENT_LOG_MCA__SHIFT                                                  0x13
+#define BIFL_RAS_LEAF9_CTRL__RCVERREVENT_ERREVENT_LOG_MCA__SHIFT                                              0x14
+#define BIFL_RAS_LEAF9_CTRL__UCP_EN__SHIFT                                                                    0x15
+#define BIFL_RAS_LEAF9_CTRL__POISON_PROPAGATION_LOG_MCA__SHIFT                                                0x16
+#define BIFL_RAS_LEAF9_CTRL__ERR_EVENT_PARITY_CHECK_EN__SHIFT                                                 0x17
+#define BIFL_RAS_LEAF9_CTRL__ERR_EVENT_DET_EN_MASK                                                            0x00000001L
+#define BIFL_RAS_LEAF9_CTRL__POISON_ERREVENT_EN_MASK                                                          0x00000002L
+#define BIFL_RAS_LEAF9_CTRL__POISON_STALL_EN_MASK                                                             0x00000004L
+#define BIFL_RAS_LEAF9_CTRL__PARITY_ERREVENT_EN_MASK                                                          0x00000008L
+#define BIFL_RAS_LEAF9_CTRL__PARITY_STALL_EN_MASK                                                             0x00000010L
+#define BIFL_RAS_LEAF9_CTRL__RCVERREVENT_ERREVENT_EN_MASK                                                     0x00000020L
+#define BIFL_RAS_LEAF9_CTRL__RCVERREVENT_STALL_EN_MASK                                                        0x00000040L
+#define BIFL_RAS_LEAF9_CTRL__ERR_EVENT_GEN_EN_MASK                                                            0x00000100L
+#define BIFL_RAS_LEAF9_CTRL__EGRESS_STALL_GEN_EN_MASK                                                         0x00000200L
+#define BIFL_RAS_LEAF9_CTRL__ERR_EVENT_PROP_EN_MASK                                                           0x00000400L
+#define BIFL_RAS_LEAF9_CTRL__EGRESS_STALL_PROP_EN_MASK                                                        0x00000800L
+#define BIFL_RAS_LEAF9_CTRL__ERR_EVENT_RAS_INTR_EN_MASK                                                       0x00010000L
+#define BIFL_RAS_LEAF9_CTRL__PARITY_ERREVENT_LOG_MCA_MASK                                                     0x00020000L
+#define BIFL_RAS_LEAF9_CTRL__POISON_ERREVENT_LOG_MCA_MASK                                                     0x00040000L
+#define BIFL_RAS_LEAF9_CTRL__TIMEOUT_ERREVENT_LOG_MCA_MASK                                                    0x00080000L
+#define BIFL_RAS_LEAF9_CTRL__RCVERREVENT_ERREVENT_LOG_MCA_MASK                                                0x00100000L
+#define BIFL_RAS_LEAF9_CTRL__UCP_EN_MASK                                                                      0x00200000L
+#define BIFL_RAS_LEAF9_CTRL__POISON_PROPAGATION_LOG_MCA_MASK                                                  0x00400000L
+#define BIFL_RAS_LEAF9_CTRL__ERR_EVENT_PARITY_CHECK_EN_MASK                                                   0x00800000L
+//BIFL_RAS_LEAF10_CTRL
+#define BIFL_RAS_LEAF10_CTRL__ERR_EVENT_DET_EN__SHIFT                                                         0x0
+#define BIFL_RAS_LEAF10_CTRL__POISON_ERREVENT_EN__SHIFT                                                       0x1
+#define BIFL_RAS_LEAF10_CTRL__POISON_STALL_EN__SHIFT                                                          0x2
+#define BIFL_RAS_LEAF10_CTRL__PARITY_ERREVENT_EN__SHIFT                                                       0x3
+#define BIFL_RAS_LEAF10_CTRL__PARITY_STALL_EN__SHIFT                                                          0x4
+#define BIFL_RAS_LEAF10_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT                                                  0x5
+#define BIFL_RAS_LEAF10_CTRL__RCVERREVENT_STALL_EN__SHIFT                                                     0x6
+#define BIFL_RAS_LEAF10_CTRL__ERR_EVENT_GEN_EN__SHIFT                                                         0x8
+#define BIFL_RAS_LEAF10_CTRL__EGRESS_STALL_GEN_EN__SHIFT                                                      0x9
+#define BIFL_RAS_LEAF10_CTRL__ERR_EVENT_PROP_EN__SHIFT                                                        0xa
+#define BIFL_RAS_LEAF10_CTRL__EGRESS_STALL_PROP_EN__SHIFT                                                     0xb
+#define BIFL_RAS_LEAF10_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT                                                    0x10
+#define BIFL_RAS_LEAF10_CTRL__PARITY_ERREVENT_LOG_MCA__SHIFT                                                  0x11
+#define BIFL_RAS_LEAF10_CTRL__POISON_ERREVENT_LOG_MCA__SHIFT                                                  0x12
+#define BIFL_RAS_LEAF10_CTRL__TIMEOUT_ERREVENT_LOG_MCA__SHIFT                                                 0x13
+#define BIFL_RAS_LEAF10_CTRL__RCVERREVENT_ERREVENT_LOG_MCA__SHIFT                                             0x14
+#define BIFL_RAS_LEAF10_CTRL__UCP_EN__SHIFT                                                                   0x15
+#define BIFL_RAS_LEAF10_CTRL__POISON_PROPAGATION_LOG_MCA__SHIFT                                               0x16
+#define BIFL_RAS_LEAF10_CTRL__ERR_EVENT_PARITY_CHECK_EN__SHIFT                                                0x17
+#define BIFL_RAS_LEAF10_CTRL__ERR_EVENT_DET_EN_MASK                                                           0x00000001L
+#define BIFL_RAS_LEAF10_CTRL__POISON_ERREVENT_EN_MASK                                                         0x00000002L
+#define BIFL_RAS_LEAF10_CTRL__POISON_STALL_EN_MASK                                                            0x00000004L
+#define BIFL_RAS_LEAF10_CTRL__PARITY_ERREVENT_EN_MASK                                                         0x00000008L
+#define BIFL_RAS_LEAF10_CTRL__PARITY_STALL_EN_MASK                                                            0x00000010L
+#define BIFL_RAS_LEAF10_CTRL__RCVERREVENT_ERREVENT_EN_MASK                                                    0x00000020L
+#define BIFL_RAS_LEAF10_CTRL__RCVERREVENT_STALL_EN_MASK                                                       0x00000040L
+#define BIFL_RAS_LEAF10_CTRL__ERR_EVENT_GEN_EN_MASK                                                           0x00000100L
+#define BIFL_RAS_LEAF10_CTRL__EGRESS_STALL_GEN_EN_MASK                                                        0x00000200L
+#define BIFL_RAS_LEAF10_CTRL__ERR_EVENT_PROP_EN_MASK                                                          0x00000400L
+#define BIFL_RAS_LEAF10_CTRL__EGRESS_STALL_PROP_EN_MASK                                                       0x00000800L
+#define BIFL_RAS_LEAF10_CTRL__ERR_EVENT_RAS_INTR_EN_MASK                                                      0x00010000L
+#define BIFL_RAS_LEAF10_CTRL__PARITY_ERREVENT_LOG_MCA_MASK                                                    0x00020000L
+#define BIFL_RAS_LEAF10_CTRL__POISON_ERREVENT_LOG_MCA_MASK                                                    0x00040000L
+#define BIFL_RAS_LEAF10_CTRL__TIMEOUT_ERREVENT_LOG_MCA_MASK                                                   0x00080000L
+#define BIFL_RAS_LEAF10_CTRL__RCVERREVENT_ERREVENT_LOG_MCA_MASK                                               0x00100000L
+#define BIFL_RAS_LEAF10_CTRL__UCP_EN_MASK                                                                     0x00200000L
+#define BIFL_RAS_LEAF10_CTRL__POISON_PROPAGATION_LOG_MCA_MASK                                                 0x00400000L
+#define BIFL_RAS_LEAF10_CTRL__ERR_EVENT_PARITY_CHECK_EN_MASK                                                  0x00800000L
+//BIFL_RAS_LEAF11_CTRL
+#define BIFL_RAS_LEAF11_CTRL__ERR_EVENT_DET_EN__SHIFT                                                         0x0
+#define BIFL_RAS_LEAF11_CTRL__POISON_ERREVENT_EN__SHIFT                                                       0x1
+#define BIFL_RAS_LEAF11_CTRL__POISON_STALL_EN__SHIFT                                                          0x2
+#define BIFL_RAS_LEAF11_CTRL__PARITY_ERREVENT_EN__SHIFT                                                       0x3
+#define BIFL_RAS_LEAF11_CTRL__PARITY_STALL_EN__SHIFT                                                          0x4
+#define BIFL_RAS_LEAF11_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT                                                  0x5
+#define BIFL_RAS_LEAF11_CTRL__RCVERREVENT_STALL_EN__SHIFT                                                     0x6
+#define BIFL_RAS_LEAF11_CTRL__ERR_EVENT_GEN_EN__SHIFT                                                         0x8
+#define BIFL_RAS_LEAF11_CTRL__EGRESS_STALL_GEN_EN__SHIFT                                                      0x9
+#define BIFL_RAS_LEAF11_CTRL__ERR_EVENT_PROP_EN__SHIFT                                                        0xa
+#define BIFL_RAS_LEAF11_CTRL__EGRESS_STALL_PROP_EN__SHIFT                                                     0xb
+#define BIFL_RAS_LEAF11_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT                                                    0x10
+#define BIFL_RAS_LEAF11_CTRL__PARITY_ERREVENT_LOG_MCA__SHIFT                                                  0x11
+#define BIFL_RAS_LEAF11_CTRL__POISON_ERREVENT_LOG_MCA__SHIFT                                                  0x12
+#define BIFL_RAS_LEAF11_CTRL__TIMEOUT_ERREVENT_LOG_MCA__SHIFT                                                 0x13
+#define BIFL_RAS_LEAF11_CTRL__RCVERREVENT_ERREVENT_LOG_MCA__SHIFT                                             0x14
+#define BIFL_RAS_LEAF11_CTRL__UCP_EN__SHIFT                                                                   0x15
+#define BIFL_RAS_LEAF11_CTRL__POISON_PROPAGATION_LOG_MCA__SHIFT                                               0x16
+#define BIFL_RAS_LEAF11_CTRL__ERR_EVENT_PARITY_CHECK_EN__SHIFT                                                0x17
+#define BIFL_RAS_LEAF11_CTRL__ERR_EVENT_DET_EN_MASK                                                           0x00000001L
+#define BIFL_RAS_LEAF11_CTRL__POISON_ERREVENT_EN_MASK                                                         0x00000002L
+#define BIFL_RAS_LEAF11_CTRL__POISON_STALL_EN_MASK                                                            0x00000004L
+#define BIFL_RAS_LEAF11_CTRL__PARITY_ERREVENT_EN_MASK                                                         0x00000008L
+#define BIFL_RAS_LEAF11_CTRL__PARITY_STALL_EN_MASK                                                            0x00000010L
+#define BIFL_RAS_LEAF11_CTRL__RCVERREVENT_ERREVENT_EN_MASK                                                    0x00000020L
+#define BIFL_RAS_LEAF11_CTRL__RCVERREVENT_STALL_EN_MASK                                                       0x00000040L
+#define BIFL_RAS_LEAF11_CTRL__ERR_EVENT_GEN_EN_MASK                                                           0x00000100L
+#define BIFL_RAS_LEAF11_CTRL__EGRESS_STALL_GEN_EN_MASK                                                        0x00000200L
+#define BIFL_RAS_LEAF11_CTRL__ERR_EVENT_PROP_EN_MASK                                                          0x00000400L
+#define BIFL_RAS_LEAF11_CTRL__EGRESS_STALL_PROP_EN_MASK                                                       0x00000800L
+#define BIFL_RAS_LEAF11_CTRL__ERR_EVENT_RAS_INTR_EN_MASK                                                      0x00010000L
+#define BIFL_RAS_LEAF11_CTRL__PARITY_ERREVENT_LOG_MCA_MASK                                                    0x00020000L
+#define BIFL_RAS_LEAF11_CTRL__POISON_ERREVENT_LOG_MCA_MASK                                                    0x00040000L
+#define BIFL_RAS_LEAF11_CTRL__TIMEOUT_ERREVENT_LOG_MCA_MASK                                                   0x00080000L
+#define BIFL_RAS_LEAF11_CTRL__RCVERREVENT_ERREVENT_LOG_MCA_MASK                                               0x00100000L
+#define BIFL_RAS_LEAF11_CTRL__UCP_EN_MASK                                                                     0x00200000L
+#define BIFL_RAS_LEAF11_CTRL__POISON_PROPAGATION_LOG_MCA_MASK                                                 0x00400000L
+#define BIFL_RAS_LEAF11_CTRL__ERR_EVENT_PARITY_CHECK_EN_MASK                                                  0x00800000L
+//BIFL_RAS_LEAF12_CTRL
+#define BIFL_RAS_LEAF12_CTRL__ERR_EVENT_DET_EN__SHIFT                                                         0x0
+#define BIFL_RAS_LEAF12_CTRL__POISON_ERREVENT_EN__SHIFT                                                       0x1
+#define BIFL_RAS_LEAF12_CTRL__POISON_STALL_EN__SHIFT                                                          0x2
+#define BIFL_RAS_LEAF12_CTRL__PARITY_ERREVENT_EN__SHIFT                                                       0x3
+#define BIFL_RAS_LEAF12_CTRL__PARITY_STALL_EN__SHIFT                                                          0x4
+#define BIFL_RAS_LEAF12_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT                                                  0x5
+#define BIFL_RAS_LEAF12_CTRL__RCVERREVENT_STALL_EN__SHIFT                                                     0x6
+#define BIFL_RAS_LEAF12_CTRL__ERR_EVENT_GEN_EN__SHIFT                                                         0x8
+#define BIFL_RAS_LEAF12_CTRL__EGRESS_STALL_GEN_EN__SHIFT                                                      0x9
+#define BIFL_RAS_LEAF12_CTRL__ERR_EVENT_PROP_EN__SHIFT                                                        0xa
+#define BIFL_RAS_LEAF12_CTRL__EGRESS_STALL_PROP_EN__SHIFT                                                     0xb
+#define BIFL_RAS_LEAF12_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT                                                    0x10
+#define BIFL_RAS_LEAF12_CTRL__PARITY_ERREVENT_LOG_MCA__SHIFT                                                  0x11
+#define BIFL_RAS_LEAF12_CTRL__POISON_ERREVENT_LOG_MCA__SHIFT                                                  0x12
+#define BIFL_RAS_LEAF12_CTRL__TIMEOUT_ERREVENT_LOG_MCA__SHIFT                                                 0x13
+#define BIFL_RAS_LEAF12_CTRL__RCVERREVENT_ERREVENT_LOG_MCA__SHIFT                                             0x14
+#define BIFL_RAS_LEAF12_CTRL__UCP_EN__SHIFT                                                                   0x15
+#define BIFL_RAS_LEAF12_CTRL__POISON_PROPAGATION_LOG_MCA__SHIFT                                               0x16
+#define BIFL_RAS_LEAF12_CTRL__ERR_EVENT_PARITY_CHECK_EN__SHIFT                                                0x17
+#define BIFL_RAS_LEAF12_CTRL__ERR_EVENT_DET_EN_MASK                                                           0x00000001L
+#define BIFL_RAS_LEAF12_CTRL__POISON_ERREVENT_EN_MASK                                                         0x00000002L
+#define BIFL_RAS_LEAF12_CTRL__POISON_STALL_EN_MASK                                                            0x00000004L
+#define BIFL_RAS_LEAF12_CTRL__PARITY_ERREVENT_EN_MASK                                                         0x00000008L
+#define BIFL_RAS_LEAF12_CTRL__PARITY_STALL_EN_MASK                                                            0x00000010L
+#define BIFL_RAS_LEAF12_CTRL__RCVERREVENT_ERREVENT_EN_MASK                                                    0x00000020L
+#define BIFL_RAS_LEAF12_CTRL__RCVERREVENT_STALL_EN_MASK                                                       0x00000040L
+#define BIFL_RAS_LEAF12_CTRL__ERR_EVENT_GEN_EN_MASK                                                           0x00000100L
+#define BIFL_RAS_LEAF12_CTRL__EGRESS_STALL_GEN_EN_MASK                                                        0x00000200L
+#define BIFL_RAS_LEAF12_CTRL__ERR_EVENT_PROP_EN_MASK                                                          0x00000400L
+#define BIFL_RAS_LEAF12_CTRL__EGRESS_STALL_PROP_EN_MASK                                                       0x00000800L
+#define BIFL_RAS_LEAF12_CTRL__ERR_EVENT_RAS_INTR_EN_MASK                                                      0x00010000L
+#define BIFL_RAS_LEAF12_CTRL__PARITY_ERREVENT_LOG_MCA_MASK                                                    0x00020000L
+#define BIFL_RAS_LEAF12_CTRL__POISON_ERREVENT_LOG_MCA_MASK                                                    0x00040000L
+#define BIFL_RAS_LEAF12_CTRL__TIMEOUT_ERREVENT_LOG_MCA_MASK                                                   0x00080000L
+#define BIFL_RAS_LEAF12_CTRL__RCVERREVENT_ERREVENT_LOG_MCA_MASK                                               0x00100000L
+#define BIFL_RAS_LEAF12_CTRL__UCP_EN_MASK                                                                     0x00200000L
+#define BIFL_RAS_LEAF12_CTRL__POISON_PROPAGATION_LOG_MCA_MASK                                                 0x00400000L
+#define BIFL_RAS_LEAF12_CTRL__ERR_EVENT_PARITY_CHECK_EN_MASK                                                  0x00800000L
+//BIFL_RAS_LEAF13_CTRL
+#define BIFL_RAS_LEAF13_CTRL__ERR_EVENT_DET_EN__SHIFT                                                         0x0
+#define BIFL_RAS_LEAF13_CTRL__POISON_ERREVENT_EN__SHIFT                                                       0x1
+#define BIFL_RAS_LEAF13_CTRL__POISON_STALL_EN__SHIFT                                                          0x2
+#define BIFL_RAS_LEAF13_CTRL__PARITY_ERREVENT_EN__SHIFT                                                       0x3
+#define BIFL_RAS_LEAF13_CTRL__PARITY_STALL_EN__SHIFT                                                          0x4
+#define BIFL_RAS_LEAF13_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT                                                  0x5
+#define BIFL_RAS_LEAF13_CTRL__RCVERREVENT_STALL_EN__SHIFT                                                     0x6
+#define BIFL_RAS_LEAF13_CTRL__ERR_EVENT_GEN_EN__SHIFT                                                         0x8
+#define BIFL_RAS_LEAF13_CTRL__EGRESS_STALL_GEN_EN__SHIFT                                                      0x9
+#define BIFL_RAS_LEAF13_CTRL__ERR_EVENT_PROP_EN__SHIFT                                                        0xa
+#define BIFL_RAS_LEAF13_CTRL__EGRESS_STALL_PROP_EN__SHIFT                                                     0xb
+#define BIFL_RAS_LEAF13_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT                                                    0x10
+#define BIFL_RAS_LEAF13_CTRL__PARITY_ERREVENT_LOG_MCA__SHIFT                                                  0x11
+#define BIFL_RAS_LEAF13_CTRL__POISON_ERREVENT_LOG_MCA__SHIFT                                                  0x12
+#define BIFL_RAS_LEAF13_CTRL__TIMEOUT_ERREVENT_LOG_MCA__SHIFT                                                 0x13
+#define BIFL_RAS_LEAF13_CTRL__RCVERREVENT_ERREVENT_LOG_MCA__SHIFT                                             0x14
+#define BIFL_RAS_LEAF13_CTRL__UCP_EN__SHIFT                                                                   0x15
+#define BIFL_RAS_LEAF13_CTRL__POISON_PROPAGATION_LOG_MCA__SHIFT                                               0x16
+#define BIFL_RAS_LEAF13_CTRL__ERR_EVENT_PARITY_CHECK_EN__SHIFT                                                0x17
+#define BIFL_RAS_LEAF13_CTRL__ERR_EVENT_DET_EN_MASK                                                           0x00000001L
+#define BIFL_RAS_LEAF13_CTRL__POISON_ERREVENT_EN_MASK                                                         0x00000002L
+#define BIFL_RAS_LEAF13_CTRL__POISON_STALL_EN_MASK                                                            0x00000004L
+#define BIFL_RAS_LEAF13_CTRL__PARITY_ERREVENT_EN_MASK                                                         0x00000008L
+#define BIFL_RAS_LEAF13_CTRL__PARITY_STALL_EN_MASK                                                            0x00000010L
+#define BIFL_RAS_LEAF13_CTRL__RCVERREVENT_ERREVENT_EN_MASK                                                    0x00000020L
+#define BIFL_RAS_LEAF13_CTRL__RCVERREVENT_STALL_EN_MASK                                                       0x00000040L
+#define BIFL_RAS_LEAF13_CTRL__ERR_EVENT_GEN_EN_MASK                                                           0x00000100L
+#define BIFL_RAS_LEAF13_CTRL__EGRESS_STALL_GEN_EN_MASK                                                        0x00000200L
+#define BIFL_RAS_LEAF13_CTRL__ERR_EVENT_PROP_EN_MASK                                                          0x00000400L
+#define BIFL_RAS_LEAF13_CTRL__EGRESS_STALL_PROP_EN_MASK                                                       0x00000800L
+#define BIFL_RAS_LEAF13_CTRL__ERR_EVENT_RAS_INTR_EN_MASK                                                      0x00010000L
+#define BIFL_RAS_LEAF13_CTRL__PARITY_ERREVENT_LOG_MCA_MASK                                                    0x00020000L
+#define BIFL_RAS_LEAF13_CTRL__POISON_ERREVENT_LOG_MCA_MASK                                                    0x00040000L
+#define BIFL_RAS_LEAF13_CTRL__TIMEOUT_ERREVENT_LOG_MCA_MASK                                                   0x00080000L
+#define BIFL_RAS_LEAF13_CTRL__RCVERREVENT_ERREVENT_LOG_MCA_MASK                                               0x00100000L
+#define BIFL_RAS_LEAF13_CTRL__UCP_EN_MASK                                                                     0x00200000L
+#define BIFL_RAS_LEAF13_CTRL__POISON_PROPAGATION_LOG_MCA_MASK                                                 0x00400000L
+#define BIFL_RAS_LEAF13_CTRL__ERR_EVENT_PARITY_CHECK_EN_MASK                                                  0x00800000L
+//BIFL_RAS_LEAF14_CTRL
+#define BIFL_RAS_LEAF14_CTRL__ERR_EVENT_DET_EN__SHIFT                                                         0x0
+#define BIFL_RAS_LEAF14_CTRL__POISON_ERREVENT_EN__SHIFT                                                       0x1
+#define BIFL_RAS_LEAF14_CTRL__POISON_STALL_EN__SHIFT                                                          0x2
+#define BIFL_RAS_LEAF14_CTRL__PARITY_ERREVENT_EN__SHIFT                                                       0x3
+#define BIFL_RAS_LEAF14_CTRL__PARITY_STALL_EN__SHIFT                                                          0x4
+#define BIFL_RAS_LEAF14_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT                                                  0x5
+#define BIFL_RAS_LEAF14_CTRL__RCVERREVENT_STALL_EN__SHIFT                                                     0x6
+#define BIFL_RAS_LEAF14_CTRL__ERR_EVENT_GEN_EN__SHIFT                                                         0x8
+#define BIFL_RAS_LEAF14_CTRL__EGRESS_STALL_GEN_EN__SHIFT                                                      0x9
+#define BIFL_RAS_LEAF14_CTRL__ERR_EVENT_PROP_EN__SHIFT                                                        0xa
+#define BIFL_RAS_LEAF14_CTRL__EGRESS_STALL_PROP_EN__SHIFT                                                     0xb
+#define BIFL_RAS_LEAF14_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT                                                    0x10
+#define BIFL_RAS_LEAF14_CTRL__PARITY_ERREVENT_LOG_MCA__SHIFT                                                  0x11
+#define BIFL_RAS_LEAF14_CTRL__POISON_ERREVENT_LOG_MCA__SHIFT                                                  0x12
+#define BIFL_RAS_LEAF14_CTRL__TIMEOUT_ERREVENT_LOG_MCA__SHIFT                                                 0x13
+#define BIFL_RAS_LEAF14_CTRL__RCVERREVENT_ERREVENT_LOG_MCA__SHIFT                                             0x14
+#define BIFL_RAS_LEAF14_CTRL__UCP_EN__SHIFT                                                                   0x15
+#define BIFL_RAS_LEAF14_CTRL__POISON_PROPAGATION_LOG_MCA__SHIFT                                               0x16
+#define BIFL_RAS_LEAF14_CTRL__ERR_EVENT_PARITY_CHECK_EN__SHIFT                                                0x17
+#define BIFL_RAS_LEAF14_CTRL__ERR_EVENT_DET_EN_MASK                                                           0x00000001L
+#define BIFL_RAS_LEAF14_CTRL__POISON_ERREVENT_EN_MASK                                                         0x00000002L
+#define BIFL_RAS_LEAF14_CTRL__POISON_STALL_EN_MASK                                                            0x00000004L
+#define BIFL_RAS_LEAF14_CTRL__PARITY_ERREVENT_EN_MASK                                                         0x00000008L
+#define BIFL_RAS_LEAF14_CTRL__PARITY_STALL_EN_MASK                                                            0x00000010L
+#define BIFL_RAS_LEAF14_CTRL__RCVERREVENT_ERREVENT_EN_MASK                                                    0x00000020L
+#define BIFL_RAS_LEAF14_CTRL__RCVERREVENT_STALL_EN_MASK                                                       0x00000040L
+#define BIFL_RAS_LEAF14_CTRL__ERR_EVENT_GEN_EN_MASK                                                           0x00000100L
+#define BIFL_RAS_LEAF14_CTRL__EGRESS_STALL_GEN_EN_MASK                                                        0x00000200L
+#define BIFL_RAS_LEAF14_CTRL__ERR_EVENT_PROP_EN_MASK                                                          0x00000400L
+#define BIFL_RAS_LEAF14_CTRL__EGRESS_STALL_PROP_EN_MASK                                                       0x00000800L
+#define BIFL_RAS_LEAF14_CTRL__ERR_EVENT_RAS_INTR_EN_MASK                                                      0x00010000L
+#define BIFL_RAS_LEAF14_CTRL__PARITY_ERREVENT_LOG_MCA_MASK                                                    0x00020000L
+#define BIFL_RAS_LEAF14_CTRL__POISON_ERREVENT_LOG_MCA_MASK                                                    0x00040000L
+#define BIFL_RAS_LEAF14_CTRL__TIMEOUT_ERREVENT_LOG_MCA_MASK                                                   0x00080000L
+#define BIFL_RAS_LEAF14_CTRL__RCVERREVENT_ERREVENT_LOG_MCA_MASK                                               0x00100000L
+#define BIFL_RAS_LEAF14_CTRL__UCP_EN_MASK                                                                     0x00200000L
+#define BIFL_RAS_LEAF14_CTRL__POISON_PROPAGATION_LOG_MCA_MASK                                                 0x00400000L
+#define BIFL_RAS_LEAF14_CTRL__ERR_EVENT_PARITY_CHECK_EN_MASK                                                  0x00800000L
+//BIFL_RAS_LEAF15_CTRL
+#define BIFL_RAS_LEAF15_CTRL__ERR_EVENT_DET_EN__SHIFT                                                         0x0
+#define BIFL_RAS_LEAF15_CTRL__POISON_ERREVENT_EN__SHIFT                                                       0x1
+#define BIFL_RAS_LEAF15_CTRL__POISON_STALL_EN__SHIFT                                                          0x2
+#define BIFL_RAS_LEAF15_CTRL__PARITY_ERREVENT_EN__SHIFT                                                       0x3
+#define BIFL_RAS_LEAF15_CTRL__PARITY_STALL_EN__SHIFT                                                          0x4
+#define BIFL_RAS_LEAF15_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT                                                  0x5
+#define BIFL_RAS_LEAF15_CTRL__RCVERREVENT_STALL_EN__SHIFT                                                     0x6
+#define BIFL_RAS_LEAF15_CTRL__ERR_EVENT_GEN_EN__SHIFT                                                         0x8
+#define BIFL_RAS_LEAF15_CTRL__EGRESS_STALL_GEN_EN__SHIFT                                                      0x9
+#define BIFL_RAS_LEAF15_CTRL__ERR_EVENT_PROP_EN__SHIFT                                                        0xa
+#define BIFL_RAS_LEAF15_CTRL__EGRESS_STALL_PROP_EN__SHIFT                                                     0xb
+#define BIFL_RAS_LEAF15_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT                                                    0x10
+#define BIFL_RAS_LEAF15_CTRL__PARITY_ERREVENT_LOG_MCA__SHIFT                                                  0x11
+#define BIFL_RAS_LEAF15_CTRL__POISON_ERREVENT_LOG_MCA__SHIFT                                                  0x12
+#define BIFL_RAS_LEAF15_CTRL__TIMEOUT_ERREVENT_LOG_MCA__SHIFT                                                 0x13
+#define BIFL_RAS_LEAF15_CTRL__RCVERREVENT_ERREVENT_LOG_MCA__SHIFT                                             0x14
+#define BIFL_RAS_LEAF15_CTRL__UCP_EN__SHIFT                                                                   0x15
+#define BIFL_RAS_LEAF15_CTRL__POISON_PROPAGATION_LOG_MCA__SHIFT                                               0x16
+#define BIFL_RAS_LEAF15_CTRL__ERR_EVENT_PARITY_CHECK_EN__SHIFT                                                0x17
+#define BIFL_RAS_LEAF15_CTRL__ERR_EVENT_DET_EN_MASK                                                           0x00000001L
+#define BIFL_RAS_LEAF15_CTRL__POISON_ERREVENT_EN_MASK                                                         0x00000002L
+#define BIFL_RAS_LEAF15_CTRL__POISON_STALL_EN_MASK                                                            0x00000004L
+#define BIFL_RAS_LEAF15_CTRL__PARITY_ERREVENT_EN_MASK                                                         0x00000008L
+#define BIFL_RAS_LEAF15_CTRL__PARITY_STALL_EN_MASK                                                            0x00000010L
+#define BIFL_RAS_LEAF15_CTRL__RCVERREVENT_ERREVENT_EN_MASK                                                    0x00000020L
+#define BIFL_RAS_LEAF15_CTRL__RCVERREVENT_STALL_EN_MASK                                                       0x00000040L
+#define BIFL_RAS_LEAF15_CTRL__ERR_EVENT_GEN_EN_MASK                                                           0x00000100L
+#define BIFL_RAS_LEAF15_CTRL__EGRESS_STALL_GEN_EN_MASK                                                        0x00000200L
+#define BIFL_RAS_LEAF15_CTRL__ERR_EVENT_PROP_EN_MASK                                                          0x00000400L
+#define BIFL_RAS_LEAF15_CTRL__EGRESS_STALL_PROP_EN_MASK                                                       0x00000800L
+#define BIFL_RAS_LEAF15_CTRL__ERR_EVENT_RAS_INTR_EN_MASK                                                      0x00010000L
+#define BIFL_RAS_LEAF15_CTRL__PARITY_ERREVENT_LOG_MCA_MASK                                                    0x00020000L
+#define BIFL_RAS_LEAF15_CTRL__POISON_ERREVENT_LOG_MCA_MASK                                                    0x00040000L
+#define BIFL_RAS_LEAF15_CTRL__TIMEOUT_ERREVENT_LOG_MCA_MASK                                                   0x00080000L
+#define BIFL_RAS_LEAF15_CTRL__RCVERREVENT_ERREVENT_LOG_MCA_MASK                                               0x00100000L
+#define BIFL_RAS_LEAF15_CTRL__UCP_EN_MASK                                                                     0x00200000L
+#define BIFL_RAS_LEAF15_CTRL__POISON_PROPAGATION_LOG_MCA_MASK                                                 0x00400000L
+#define BIFL_RAS_LEAF15_CTRL__ERR_EVENT_PARITY_CHECK_EN_MASK                                                  0x00800000L
+//BIFL_RAS_LEAF16_CTRL
+#define BIFL_RAS_LEAF16_CTRL__ERR_EVENT_DET_EN__SHIFT                                                         0x0
+#define BIFL_RAS_LEAF16_CTRL__POISON_ERREVENT_EN__SHIFT                                                       0x1
+#define BIFL_RAS_LEAF16_CTRL__POISON_STALL_EN__SHIFT                                                          0x2
+#define BIFL_RAS_LEAF16_CTRL__PARITY_ERREVENT_EN__SHIFT                                                       0x3
+#define BIFL_RAS_LEAF16_CTRL__PARITY_STALL_EN__SHIFT                                                          0x4
+#define BIFL_RAS_LEAF16_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT                                                  0x5
+#define BIFL_RAS_LEAF16_CTRL__RCVERREVENT_STALL_EN__SHIFT                                                     0x6
+#define BIFL_RAS_LEAF16_CTRL__ERR_EVENT_GEN_EN__SHIFT                                                         0x8
+#define BIFL_RAS_LEAF16_CTRL__EGRESS_STALL_GEN_EN__SHIFT                                                      0x9
+#define BIFL_RAS_LEAF16_CTRL__ERR_EVENT_PROP_EN__SHIFT                                                        0xa
+#define BIFL_RAS_LEAF16_CTRL__EGRESS_STALL_PROP_EN__SHIFT                                                     0xb
+#define BIFL_RAS_LEAF16_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT                                                    0x10
+#define BIFL_RAS_LEAF16_CTRL__PARITY_ERREVENT_LOG_MCA__SHIFT                                                  0x11
+#define BIFL_RAS_LEAF16_CTRL__POISON_ERREVENT_LOG_MCA__SHIFT                                                  0x12
+#define BIFL_RAS_LEAF16_CTRL__TIMEOUT_ERREVENT_LOG_MCA__SHIFT                                                 0x13
+#define BIFL_RAS_LEAF16_CTRL__RCVERREVENT_ERREVENT_LOG_MCA__SHIFT                                             0x14
+#define BIFL_RAS_LEAF16_CTRL__UCP_EN__SHIFT                                                                   0x15
+#define BIFL_RAS_LEAF16_CTRL__POISON_PROPAGATION_LOG_MCA__SHIFT                                               0x16
+#define BIFL_RAS_LEAF16_CTRL__ERR_EVENT_PARITY_CHECK_EN__SHIFT                                                0x17
+#define BIFL_RAS_LEAF16_CTRL__ERR_EVENT_DET_EN_MASK                                                           0x00000001L
+#define BIFL_RAS_LEAF16_CTRL__POISON_ERREVENT_EN_MASK                                                         0x00000002L
+#define BIFL_RAS_LEAF16_CTRL__POISON_STALL_EN_MASK                                                            0x00000004L
+#define BIFL_RAS_LEAF16_CTRL__PARITY_ERREVENT_EN_MASK                                                         0x00000008L
+#define BIFL_RAS_LEAF16_CTRL__PARITY_STALL_EN_MASK                                                            0x00000010L
+#define BIFL_RAS_LEAF16_CTRL__RCVERREVENT_ERREVENT_EN_MASK                                                    0x00000020L
+#define BIFL_RAS_LEAF16_CTRL__RCVERREVENT_STALL_EN_MASK                                                       0x00000040L
+#define BIFL_RAS_LEAF16_CTRL__ERR_EVENT_GEN_EN_MASK                                                           0x00000100L
+#define BIFL_RAS_LEAF16_CTRL__EGRESS_STALL_GEN_EN_MASK                                                        0x00000200L
+#define BIFL_RAS_LEAF16_CTRL__ERR_EVENT_PROP_EN_MASK                                                          0x00000400L
+#define BIFL_RAS_LEAF16_CTRL__EGRESS_STALL_PROP_EN_MASK                                                       0x00000800L
+#define BIFL_RAS_LEAF16_CTRL__ERR_EVENT_RAS_INTR_EN_MASK                                                      0x00010000L
+#define BIFL_RAS_LEAF16_CTRL__PARITY_ERREVENT_LOG_MCA_MASK                                                    0x00020000L
+#define BIFL_RAS_LEAF16_CTRL__POISON_ERREVENT_LOG_MCA_MASK                                                    0x00040000L
+#define BIFL_RAS_LEAF16_CTRL__TIMEOUT_ERREVENT_LOG_MCA_MASK                                                   0x00080000L
+#define BIFL_RAS_LEAF16_CTRL__RCVERREVENT_ERREVENT_LOG_MCA_MASK                                               0x00100000L
+#define BIFL_RAS_LEAF16_CTRL__UCP_EN_MASK                                                                     0x00200000L
+#define BIFL_RAS_LEAF16_CTRL__POISON_PROPAGATION_LOG_MCA_MASK                                                 0x00400000L
+#define BIFL_RAS_LEAF16_CTRL__ERR_EVENT_PARITY_CHECK_EN_MASK                                                  0x00800000L
+//BIFL_RAS_LEAF17_CTRL
+#define BIFL_RAS_LEAF17_CTRL__ERR_EVENT_DET_EN__SHIFT                                                         0x0
+#define BIFL_RAS_LEAF17_CTRL__POISON_ERREVENT_EN__SHIFT                                                       0x1
+#define BIFL_RAS_LEAF17_CTRL__POISON_STALL_EN__SHIFT                                                          0x2
+#define BIFL_RAS_LEAF17_CTRL__PARITY_ERREVENT_EN__SHIFT                                                       0x3
+#define BIFL_RAS_LEAF17_CTRL__PARITY_STALL_EN__SHIFT                                                          0x4
+#define BIFL_RAS_LEAF17_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT                                                  0x5
+#define BIFL_RAS_LEAF17_CTRL__RCVERREVENT_STALL_EN__SHIFT                                                     0x6
+#define BIFL_RAS_LEAF17_CTRL__ERR_EVENT_GEN_EN__SHIFT                                                         0x8
+#define BIFL_RAS_LEAF17_CTRL__EGRESS_STALL_GEN_EN__SHIFT                                                      0x9
+#define BIFL_RAS_LEAF17_CTRL__ERR_EVENT_PROP_EN__SHIFT                                                        0xa
+#define BIFL_RAS_LEAF17_CTRL__EGRESS_STALL_PROP_EN__SHIFT                                                     0xb
+#define BIFL_RAS_LEAF17_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT                                                    0x10
+#define BIFL_RAS_LEAF17_CTRL__PARITY_ERREVENT_LOG_MCA__SHIFT                                                  0x11
+#define BIFL_RAS_LEAF17_CTRL__POISON_ERREVENT_LOG_MCA__SHIFT                                                  0x12
+#define BIFL_RAS_LEAF17_CTRL__TIMEOUT_ERREVENT_LOG_MCA__SHIFT                                                 0x13
+#define BIFL_RAS_LEAF17_CTRL__RCVERREVENT_ERREVENT_LOG_MCA__SHIFT                                             0x14
+#define BIFL_RAS_LEAF17_CTRL__UCP_EN__SHIFT                                                                   0x15
+#define BIFL_RAS_LEAF17_CTRL__POISON_PROPAGATION_LOG_MCA__SHIFT                                               0x16
+#define BIFL_RAS_LEAF17_CTRL__ERR_EVENT_PARITY_CHECK_EN__SHIFT                                                0x17
+#define BIFL_RAS_LEAF17_CTRL__ERR_EVENT_DET_EN_MASK                                                           0x00000001L
+#define BIFL_RAS_LEAF17_CTRL__POISON_ERREVENT_EN_MASK                                                         0x00000002L
+#define BIFL_RAS_LEAF17_CTRL__POISON_STALL_EN_MASK                                                            0x00000004L
+#define BIFL_RAS_LEAF17_CTRL__PARITY_ERREVENT_EN_MASK                                                         0x00000008L
+#define BIFL_RAS_LEAF17_CTRL__PARITY_STALL_EN_MASK                                                            0x00000010L
+#define BIFL_RAS_LEAF17_CTRL__RCVERREVENT_ERREVENT_EN_MASK                                                    0x00000020L
+#define BIFL_RAS_LEAF17_CTRL__RCVERREVENT_STALL_EN_MASK                                                       0x00000040L
+#define BIFL_RAS_LEAF17_CTRL__ERR_EVENT_GEN_EN_MASK                                                           0x00000100L
+#define BIFL_RAS_LEAF17_CTRL__EGRESS_STALL_GEN_EN_MASK                                                        0x00000200L
+#define BIFL_RAS_LEAF17_CTRL__ERR_EVENT_PROP_EN_MASK                                                          0x00000400L
+#define BIFL_RAS_LEAF17_CTRL__EGRESS_STALL_PROP_EN_MASK                                                       0x00000800L
+#define BIFL_RAS_LEAF17_CTRL__ERR_EVENT_RAS_INTR_EN_MASK                                                      0x00010000L
+#define BIFL_RAS_LEAF17_CTRL__PARITY_ERREVENT_LOG_MCA_MASK                                                    0x00020000L
+#define BIFL_RAS_LEAF17_CTRL__POISON_ERREVENT_LOG_MCA_MASK                                                    0x00040000L
+#define BIFL_RAS_LEAF17_CTRL__TIMEOUT_ERREVENT_LOG_MCA_MASK                                                   0x00080000L
+#define BIFL_RAS_LEAF17_CTRL__RCVERREVENT_ERREVENT_LOG_MCA_MASK                                               0x00100000L
+#define BIFL_RAS_LEAF17_CTRL__UCP_EN_MASK                                                                     0x00200000L
+#define BIFL_RAS_LEAF17_CTRL__POISON_PROPAGATION_LOG_MCA_MASK                                                 0x00400000L
+#define BIFL_RAS_LEAF17_CTRL__ERR_EVENT_PARITY_CHECK_EN_MASK                                                  0x00800000L
+//BIFL_RAS_LEAF18_CTRL
+#define BIFL_RAS_LEAF18_CTRL__ERR_EVENT_DET_EN__SHIFT                                                         0x0
+#define BIFL_RAS_LEAF18_CTRL__POISON_ERREVENT_EN__SHIFT                                                       0x1
+#define BIFL_RAS_LEAF18_CTRL__POISON_STALL_EN__SHIFT                                                          0x2
+#define BIFL_RAS_LEAF18_CTRL__PARITY_ERREVENT_EN__SHIFT                                                       0x3
+#define BIFL_RAS_LEAF18_CTRL__PARITY_STALL_EN__SHIFT                                                          0x4
+#define BIFL_RAS_LEAF18_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT                                                  0x5
+#define BIFL_RAS_LEAF18_CTRL__RCVERREVENT_STALL_EN__SHIFT                                                     0x6
+#define BIFL_RAS_LEAF18_CTRL__ERR_EVENT_GEN_EN__SHIFT                                                         0x8
+#define BIFL_RAS_LEAF18_CTRL__EGRESS_STALL_GEN_EN__SHIFT                                                      0x9
+#define BIFL_RAS_LEAF18_CTRL__ERR_EVENT_PROP_EN__SHIFT                                                        0xa
+#define BIFL_RAS_LEAF18_CTRL__EGRESS_STALL_PROP_EN__SHIFT                                                     0xb
+#define BIFL_RAS_LEAF18_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT                                                    0x10
+#define BIFL_RAS_LEAF18_CTRL__PARITY_ERREVENT_LOG_MCA__SHIFT                                                  0x11
+#define BIFL_RAS_LEAF18_CTRL__POISON_ERREVENT_LOG_MCA__SHIFT                                                  0x12
+#define BIFL_RAS_LEAF18_CTRL__TIMEOUT_ERREVENT_LOG_MCA__SHIFT                                                 0x13
+#define BIFL_RAS_LEAF18_CTRL__RCVERREVENT_ERREVENT_LOG_MCA__SHIFT                                             0x14
+#define BIFL_RAS_LEAF18_CTRL__UCP_EN__SHIFT                                                                   0x15
+#define BIFL_RAS_LEAF18_CTRL__POISON_PROPAGATION_LOG_MCA__SHIFT                                               0x16
+#define BIFL_RAS_LEAF18_CTRL__ERR_EVENT_PARITY_CHECK_EN__SHIFT                                                0x17
+#define BIFL_RAS_LEAF18_CTRL__ERR_EVENT_DET_EN_MASK                                                           0x00000001L
+#define BIFL_RAS_LEAF18_CTRL__POISON_ERREVENT_EN_MASK                                                         0x00000002L
+#define BIFL_RAS_LEAF18_CTRL__POISON_STALL_EN_MASK                                                            0x00000004L
+#define BIFL_RAS_LEAF18_CTRL__PARITY_ERREVENT_EN_MASK                                                         0x00000008L
+#define BIFL_RAS_LEAF18_CTRL__PARITY_STALL_EN_MASK                                                            0x00000010L
+#define BIFL_RAS_LEAF18_CTRL__RCVERREVENT_ERREVENT_EN_MASK                                                    0x00000020L
+#define BIFL_RAS_LEAF18_CTRL__RCVERREVENT_STALL_EN_MASK                                                       0x00000040L
+#define BIFL_RAS_LEAF18_CTRL__ERR_EVENT_GEN_EN_MASK                                                           0x00000100L
+#define BIFL_RAS_LEAF18_CTRL__EGRESS_STALL_GEN_EN_MASK                                                        0x00000200L
+#define BIFL_RAS_LEAF18_CTRL__ERR_EVENT_PROP_EN_MASK                                                          0x00000400L
+#define BIFL_RAS_LEAF18_CTRL__EGRESS_STALL_PROP_EN_MASK                                                       0x00000800L
+#define BIFL_RAS_LEAF18_CTRL__ERR_EVENT_RAS_INTR_EN_MASK                                                      0x00010000L
+#define BIFL_RAS_LEAF18_CTRL__PARITY_ERREVENT_LOG_MCA_MASK                                                    0x00020000L
+#define BIFL_RAS_LEAF18_CTRL__POISON_ERREVENT_LOG_MCA_MASK                                                    0x00040000L
+#define BIFL_RAS_LEAF18_CTRL__TIMEOUT_ERREVENT_LOG_MCA_MASK                                                   0x00080000L
+#define BIFL_RAS_LEAF18_CTRL__RCVERREVENT_ERREVENT_LOG_MCA_MASK                                               0x00100000L
+#define BIFL_RAS_LEAF18_CTRL__UCP_EN_MASK                                                                     0x00200000L
+#define BIFL_RAS_LEAF18_CTRL__POISON_PROPAGATION_LOG_MCA_MASK                                                 0x00400000L
+#define BIFL_RAS_LEAF18_CTRL__ERR_EVENT_PARITY_CHECK_EN_MASK                                                  0x00800000L
+//BIFL_RAS_LEAF19_CTRL
+#define BIFL_RAS_LEAF19_CTRL__ERR_EVENT_DET_EN__SHIFT                                                         0x0
+#define BIFL_RAS_LEAF19_CTRL__POISON_ERREVENT_EN__SHIFT                                                       0x1
+#define BIFL_RAS_LEAF19_CTRL__POISON_STALL_EN__SHIFT                                                          0x2
+#define BIFL_RAS_LEAF19_CTRL__PARITY_ERREVENT_EN__SHIFT                                                       0x3
+#define BIFL_RAS_LEAF19_CTRL__PARITY_STALL_EN__SHIFT                                                          0x4
+#define BIFL_RAS_LEAF19_CTRL__RCVERREVENT_ERREVENT_EN__SHIFT                                                  0x5
+#define BIFL_RAS_LEAF19_CTRL__RCVERREVENT_STALL_EN__SHIFT                                                     0x6
+#define BIFL_RAS_LEAF19_CTRL__ERR_EVENT_GEN_EN__SHIFT                                                         0x8
+#define BIFL_RAS_LEAF19_CTRL__EGRESS_STALL_GEN_EN__SHIFT                                                      0x9
+#define BIFL_RAS_LEAF19_CTRL__ERR_EVENT_PROP_EN__SHIFT                                                        0xa
+#define BIFL_RAS_LEAF19_CTRL__EGRESS_STALL_PROP_EN__SHIFT                                                     0xb
+#define BIFL_RAS_LEAF19_CTRL__ERR_EVENT_RAS_INTR_EN__SHIFT                                                    0x10
+#define BIFL_RAS_LEAF19_CTRL__PARITY_ERREVENT_LOG_MCA__SHIFT                                                  0x11
+#define BIFL_RAS_LEAF19_CTRL__POISON_ERREVENT_LOG_MCA__SHIFT                                                  0x12
+#define BIFL_RAS_LEAF19_CTRL__TIMEOUT_ERREVENT_LOG_MCA__SHIFT                                                 0x13
+#define BIFL_RAS_LEAF19_CTRL__RCVERREVENT_ERREVENT_LOG_MCA__SHIFT                                             0x14
+#define BIFL_RAS_LEAF19_CTRL__UCP_EN__SHIFT                                                                   0x15
+#define BIFL_RAS_LEAF19_CTRL__POISON_PROPAGATION_LOG_MCA__SHIFT                                               0x16
+#define BIFL_RAS_LEAF19_CTRL__ERR_EVENT_PARITY_CHECK_EN__SHIFT                                                0x17
+#define BIFL_RAS_LEAF19_CTRL__ERR_EVENT_DET_EN_MASK                                                           0x00000001L
+#define BIFL_RAS_LEAF19_CTRL__POISON_ERREVENT_EN_MASK                                                         0x00000002L
+#define BIFL_RAS_LEAF19_CTRL__POISON_STALL_EN_MASK                                                            0x00000004L
+#define BIFL_RAS_LEAF19_CTRL__PARITY_ERREVENT_EN_MASK                                                         0x00000008L
+#define BIFL_RAS_LEAF19_CTRL__PARITY_STALL_EN_MASK                                                            0x00000010L
+#define BIFL_RAS_LEAF19_CTRL__RCVERREVENT_ERREVENT_EN_MASK                                                    0x00000020L
+#define BIFL_RAS_LEAF19_CTRL__RCVERREVENT_STALL_EN_MASK                                                       0x00000040L
+#define BIFL_RAS_LEAF19_CTRL__ERR_EVENT_GEN_EN_MASK                                                           0x00000100L
+#define BIFL_RAS_LEAF19_CTRL__EGRESS_STALL_GEN_EN_MASK                                                        0x00000200L
+#define BIFL_RAS_LEAF19_CTRL__ERR_EVENT_PROP_EN_MASK                                                          0x00000400L
+#define BIFL_RAS_LEAF19_CTRL__EGRESS_STALL_PROP_EN_MASK                                                       0x00000800L
+#define BIFL_RAS_LEAF19_CTRL__ERR_EVENT_RAS_INTR_EN_MASK                                                      0x00010000L
+#define BIFL_RAS_LEAF19_CTRL__PARITY_ERREVENT_LOG_MCA_MASK                                                    0x00020000L
+#define BIFL_RAS_LEAF19_CTRL__POISON_ERREVENT_LOG_MCA_MASK                                                    0x00040000L
+#define BIFL_RAS_LEAF19_CTRL__TIMEOUT_ERREVENT_LOG_MCA_MASK                                                   0x00080000L
+#define BIFL_RAS_LEAF19_CTRL__RCVERREVENT_ERREVENT_LOG_MCA_MASK                                               0x00100000L
+#define BIFL_RAS_LEAF19_CTRL__UCP_EN_MASK                                                                     0x00200000L
+#define BIFL_RAS_LEAF19_CTRL__POISON_PROPAGATION_LOG_MCA_MASK                                                 0x00400000L
+#define BIFL_RAS_LEAF19_CTRL__ERR_EVENT_PARITY_CHECK_EN_MASK                                                  0x00800000L
+//BIFL_RAS_LEAF2_MISC_CTRL
+#define BIFL_RAS_LEAF2_MISC_CTRL__BIFL_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_HSTRSP_SHUB_DROP_EN__SHIFT           0x0
+#define BIFL_RAS_LEAF2_MISC_CTRL__BIFL_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_HSTRSP_CDC_DROP_EN__SHIFT            0x1
+#define BIFL_RAS_LEAF2_MISC_CTRL__BIFL_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_IHINTR_PORT_MASK_DIS__SHIFT          0x8
+#define BIFL_RAS_LEAF2_MISC_CTRL__BIFL_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_IHINTR_TRANS_MASK_DIS__SHIFT         0x9
+#define BIFL_RAS_LEAF2_MISC_CTRL__BIFL_RAS_LEAF2_MISC_CTRL_ERR_EVENT_ATHUB_RAS_ACTION_DIS_DMA_REQ__SHIFT      0xb
+#define BIFL_RAS_LEAF2_MISC_CTRL__BIFL_RAS_LEAF2_MISC_CTRL_ERR_EVENT_ATHUB_RAS_ACTION_EN_DMA_REQ_CHAIN_CHK__SHIFT  0xc
+#define BIFL_RAS_LEAF2_MISC_CTRL__BIFL_RAS_LEAF2_MISC_CTRL_ERR_EVENT_ATHUB_RAS_ACTION_DIS_DMA_RSP__SHIFT      0xd
+#define BIFL_RAS_LEAF2_MISC_CTRL__BIFL_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_ATHUB_DUMMYCHAIN_REQ_UNITID_EN__SHIFT  0x10
+#define BIFL_RAS_LEAF2_MISC_CTRL__BIFL_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_ATHUB_DUMMYCHAIN_REQ_TAG_CONST_EN__SHIFT  0x11
+#define BIFL_RAS_LEAF2_MISC_CTRL__BIFL_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_HSTRSP_SHUB_DROP_EN_MASK             0x00000001L
+#define BIFL_RAS_LEAF2_MISC_CTRL__BIFL_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_HSTRSP_CDC_DROP_EN_MASK              0x00000002L
+#define BIFL_RAS_LEAF2_MISC_CTRL__BIFL_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_IHINTR_PORT_MASK_DIS_MASK            0x00000100L
+#define BIFL_RAS_LEAF2_MISC_CTRL__BIFL_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_IHINTR_TRANS_MASK_DIS_MASK           0x00000200L
+#define BIFL_RAS_LEAF2_MISC_CTRL__BIFL_RAS_LEAF2_MISC_CTRL_ERR_EVENT_ATHUB_RAS_ACTION_DIS_DMA_REQ_MASK        0x00000800L
+#define BIFL_RAS_LEAF2_MISC_CTRL__BIFL_RAS_LEAF2_MISC_CTRL_ERR_EVENT_ATHUB_RAS_ACTION_EN_DMA_REQ_CHAIN_CHK_MASK  0x00001000L
+#define BIFL_RAS_LEAF2_MISC_CTRL__BIFL_RAS_LEAF2_MISC_CTRL_ERR_EVENT_ATHUB_RAS_ACTION_DIS_DMA_RSP_MASK        0x00002000L
+#define BIFL_RAS_LEAF2_MISC_CTRL__BIFL_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_ATHUB_DUMMYCHAIN_REQ_UNITID_EN_MASK  0x00010000L
+#define BIFL_RAS_LEAF2_MISC_CTRL__BIFL_RAS_LEAF2_MISC_CTRL_ERR_EVENT_RAS_ATHUB_DUMMYCHAIN_REQ_TAG_CONST_EN_MASK  0x00020000L
+//BIFL_RAS_LEAF2_MISC_CTRL2
+#define BIFL_RAS_LEAF2_MISC_CTRL2__BIFL_RAS_LEAF2_MISC_CTRL2_ERR_EVENT_RAS_ATHUB_DUMMYCHAIN_REQ_UNITID__SHIFT  0x0
+#define BIFL_RAS_LEAF2_MISC_CTRL2__BIFL_RAS_LEAF2_MISC_CTRL2_ERR_EVENT_RAS_ATHUB_DUMMYCHAIN_REQ_TAG__SHIFT    0xb
+#define BIFL_RAS_LEAF2_MISC_CTRL2__BIFL_RAS_LEAF2_MISC_CTRL2_ERR_EVENT_RAS_ATHUB_DUMMYCHAIN_REQ_TAG_OFFSET__SHIFT  0x15
+#define BIFL_RAS_LEAF2_MISC_CTRL2__BIFL_RAS_LEAF2_MISC_CTRL2_ERR_EVENT_RAS_ATHUB_DUMMYCHAIN_REQ_UNITID_MASK   0x000007FFL
+#define BIFL_RAS_LEAF2_MISC_CTRL2__BIFL_RAS_LEAF2_MISC_CTRL2_ERR_EVENT_RAS_ATHUB_DUMMYCHAIN_REQ_TAG_MASK      0x001FF800L
+#define BIFL_RAS_LEAF2_MISC_CTRL2__BIFL_RAS_LEAF2_MISC_CTRL2_ERR_EVENT_RAS_ATHUB_DUMMYCHAIN_REQ_TAG_OFFSET_MASK  0x7FE00000L
+//BIFL_RAS_LEAF_NTB_CTRL
+#define BIFL_RAS_LEAF_NTB_CTRL__RCVERREVENT_ERREVENT_LOG_MCA__SHIFT                                           0x0
+#define BIFL_RAS_LEAF_NTB_CTRL__RCVERREVENT_ERREVENT_LOG_MCA_MASK                                             0x00000001L
+//BIFL_RAS_LEAF0_STATUS
+#define BIFL_RAS_LEAF0_STATUS__ERR_EVENT_RECV__SHIFT                                                          0x0
+#define BIFL_RAS_LEAF0_STATUS__POISON_ERR_DET__SHIFT                                                          0x1
+#define BIFL_RAS_LEAF0_STATUS__PARITY_ERR_DET__SHIFT                                                          0x2
+#define BIFL_RAS_LEAF0_STATUS__ERR_EVENT_GENN_STAT__SHIFT                                                     0x8
+#define BIFL_RAS_LEAF0_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT                                                0x9
+#define BIFL_RAS_LEAF0_STATUS__ERR_EVENT_PROP_STAT__SHIFT                                                     0xa
+#define BIFL_RAS_LEAF0_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT                                                0xb
+#define BIFL_RAS_LEAF0_STATUS__ERR_EVENT_RECV_MASK                                                            0x00000001L
+#define BIFL_RAS_LEAF0_STATUS__POISON_ERR_DET_MASK                                                            0x00000002L
+#define BIFL_RAS_LEAF0_STATUS__PARITY_ERR_DET_MASK                                                            0x00000004L
+#define BIFL_RAS_LEAF0_STATUS__ERR_EVENT_GENN_STAT_MASK                                                       0x00000100L
+#define BIFL_RAS_LEAF0_STATUS__EGRESS_STALLED_GENN_STAT_MASK                                                  0x00000200L
+#define BIFL_RAS_LEAF0_STATUS__ERR_EVENT_PROP_STAT_MASK                                                       0x00000400L
+#define BIFL_RAS_LEAF0_STATUS__EGRESS_STALLED_PROP_STAT_MASK                                                  0x00000800L
+//BIFL_RAS_LEAF1_STATUS
+#define BIFL_RAS_LEAF1_STATUS__ERR_EVENT_RECV__SHIFT                                                          0x0
+#define BIFL_RAS_LEAF1_STATUS__POISON_ERR_DET__SHIFT                                                          0x1
+#define BIFL_RAS_LEAF1_STATUS__PARITY_ERR_DET__SHIFT                                                          0x2
+#define BIFL_RAS_LEAF1_STATUS__ERR_EVENT_GENN_STAT__SHIFT                                                     0x8
+#define BIFL_RAS_LEAF1_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT                                                0x9
+#define BIFL_RAS_LEAF1_STATUS__ERR_EVENT_PROP_STAT__SHIFT                                                     0xa
+#define BIFL_RAS_LEAF1_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT                                                0xb
+#define BIFL_RAS_LEAF1_STATUS__ERR_EVENT_RECV_MASK                                                            0x00000001L
+#define BIFL_RAS_LEAF1_STATUS__POISON_ERR_DET_MASK                                                            0x00000002L
+#define BIFL_RAS_LEAF1_STATUS__PARITY_ERR_DET_MASK                                                            0x00000004L
+#define BIFL_RAS_LEAF1_STATUS__ERR_EVENT_GENN_STAT_MASK                                                       0x00000100L
+#define BIFL_RAS_LEAF1_STATUS__EGRESS_STALLED_GENN_STAT_MASK                                                  0x00000200L
+#define BIFL_RAS_LEAF1_STATUS__ERR_EVENT_PROP_STAT_MASK                                                       0x00000400L
+#define BIFL_RAS_LEAF1_STATUS__EGRESS_STALLED_PROP_STAT_MASK                                                  0x00000800L
+//BIFL_RAS_LEAF2_STATUS
+#define BIFL_RAS_LEAF2_STATUS__ERR_EVENT_RECV__SHIFT                                                          0x0
+#define BIFL_RAS_LEAF2_STATUS__POISON_ERR_DET__SHIFT                                                          0x1
+#define BIFL_RAS_LEAF2_STATUS__PARITY_ERR_DET__SHIFT                                                          0x2
+#define BIFL_RAS_LEAF2_STATUS__ERR_EVENT_GENN_STAT__SHIFT                                                     0x8
+#define BIFL_RAS_LEAF2_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT                                                0x9
+#define BIFL_RAS_LEAF2_STATUS__ERR_EVENT_PROP_STAT__SHIFT                                                     0xa
+#define BIFL_RAS_LEAF2_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT                                                0xb
+#define BIFL_RAS_LEAF2_STATUS__ERR_EVENT_RECV_MASK                                                            0x00000001L
+#define BIFL_RAS_LEAF2_STATUS__POISON_ERR_DET_MASK                                                            0x00000002L
+#define BIFL_RAS_LEAF2_STATUS__PARITY_ERR_DET_MASK                                                            0x00000004L
+#define BIFL_RAS_LEAF2_STATUS__ERR_EVENT_GENN_STAT_MASK                                                       0x00000100L
+#define BIFL_RAS_LEAF2_STATUS__EGRESS_STALLED_GENN_STAT_MASK                                                  0x00000200L
+#define BIFL_RAS_LEAF2_STATUS__ERR_EVENT_PROP_STAT_MASK                                                       0x00000400L
+#define BIFL_RAS_LEAF2_STATUS__EGRESS_STALLED_PROP_STAT_MASK                                                  0x00000800L
+//BIFL_RAS_LEAF3_STATUS
+#define BIFL_RAS_LEAF3_STATUS__ERR_EVENT_RECV__SHIFT                                                          0x0
+#define BIFL_RAS_LEAF3_STATUS__POISON_ERR_DET__SHIFT                                                          0x1
+#define BIFL_RAS_LEAF3_STATUS__PARITY_ERR_DET__SHIFT                                                          0x2
+#define BIFL_RAS_LEAF3_STATUS__ERR_EVENT_GENN_STAT__SHIFT                                                     0x8
+#define BIFL_RAS_LEAF3_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT                                                0x9
+#define BIFL_RAS_LEAF3_STATUS__ERR_EVENT_PROP_STAT__SHIFT                                                     0xa
+#define BIFL_RAS_LEAF3_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT                                                0xb
+#define BIFL_RAS_LEAF3_STATUS__ERR_EVENT_RECV_MASK                                                            0x00000001L
+#define BIFL_RAS_LEAF3_STATUS__POISON_ERR_DET_MASK                                                            0x00000002L
+#define BIFL_RAS_LEAF3_STATUS__PARITY_ERR_DET_MASK                                                            0x00000004L
+#define BIFL_RAS_LEAF3_STATUS__ERR_EVENT_GENN_STAT_MASK                                                       0x00000100L
+#define BIFL_RAS_LEAF3_STATUS__EGRESS_STALLED_GENN_STAT_MASK                                                  0x00000200L
+#define BIFL_RAS_LEAF3_STATUS__ERR_EVENT_PROP_STAT_MASK                                                       0x00000400L
+#define BIFL_RAS_LEAF3_STATUS__EGRESS_STALLED_PROP_STAT_MASK                                                  0x00000800L
+//BIFL_RAS_LEAF4_STATUS
+#define BIFL_RAS_LEAF4_STATUS__ERR_EVENT_RECV__SHIFT                                                          0x0
+#define BIFL_RAS_LEAF4_STATUS__POISON_ERR_DET__SHIFT                                                          0x1
+#define BIFL_RAS_LEAF4_STATUS__PARITY_ERR_DET__SHIFT                                                          0x2
+#define BIFL_RAS_LEAF4_STATUS__ERR_EVENT_GENN_STAT__SHIFT                                                     0x8
+#define BIFL_RAS_LEAF4_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT                                                0x9
+#define BIFL_RAS_LEAF4_STATUS__ERR_EVENT_PROP_STAT__SHIFT                                                     0xa
+#define BIFL_RAS_LEAF4_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT                                                0xb
+#define BIFL_RAS_LEAF4_STATUS__ERR_EVENT_RECV_MASK                                                            0x00000001L
+#define BIFL_RAS_LEAF4_STATUS__POISON_ERR_DET_MASK                                                            0x00000002L
+#define BIFL_RAS_LEAF4_STATUS__PARITY_ERR_DET_MASK                                                            0x00000004L
+#define BIFL_RAS_LEAF4_STATUS__ERR_EVENT_GENN_STAT_MASK                                                       0x00000100L
+#define BIFL_RAS_LEAF4_STATUS__EGRESS_STALLED_GENN_STAT_MASK                                                  0x00000200L
+#define BIFL_RAS_LEAF4_STATUS__ERR_EVENT_PROP_STAT_MASK                                                       0x00000400L
+#define BIFL_RAS_LEAF4_STATUS__EGRESS_STALLED_PROP_STAT_MASK                                                  0x00000800L
+//BIFL_RAS_LEAF5_STATUS
+#define BIFL_RAS_LEAF5_STATUS__ERR_EVENT_RECV__SHIFT                                                          0x0
+#define BIFL_RAS_LEAF5_STATUS__POISON_ERR_DET__SHIFT                                                          0x1
+#define BIFL_RAS_LEAF5_STATUS__PARITY_ERR_DET__SHIFT                                                          0x2
+#define BIFL_RAS_LEAF5_STATUS__ERR_EVENT_GENN_STAT__SHIFT                                                     0x8
+#define BIFL_RAS_LEAF5_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT                                                0x9
+#define BIFL_RAS_LEAF5_STATUS__ERR_EVENT_PROP_STAT__SHIFT                                                     0xa
+#define BIFL_RAS_LEAF5_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT                                                0xb
+#define BIFL_RAS_LEAF5_STATUS__ERR_EVENT_RECV_MASK                                                            0x00000001L
+#define BIFL_RAS_LEAF5_STATUS__POISON_ERR_DET_MASK                                                            0x00000002L
+#define BIFL_RAS_LEAF5_STATUS__PARITY_ERR_DET_MASK                                                            0x00000004L
+#define BIFL_RAS_LEAF5_STATUS__ERR_EVENT_GENN_STAT_MASK                                                       0x00000100L
+#define BIFL_RAS_LEAF5_STATUS__EGRESS_STALLED_GENN_STAT_MASK                                                  0x00000200L
+#define BIFL_RAS_LEAF5_STATUS__ERR_EVENT_PROP_STAT_MASK                                                       0x00000400L
+#define BIFL_RAS_LEAF5_STATUS__EGRESS_STALLED_PROP_STAT_MASK                                                  0x00000800L
+//BIFL_RAS_LEAF6_STATUS
+#define BIFL_RAS_LEAF6_STATUS__ERR_EVENT_RECV__SHIFT                                                          0x0
+#define BIFL_RAS_LEAF6_STATUS__POISON_ERR_DET__SHIFT                                                          0x1
+#define BIFL_RAS_LEAF6_STATUS__PARITY_ERR_DET__SHIFT                                                          0x2
+#define BIFL_RAS_LEAF6_STATUS__ERR_EVENT_GENN_STAT__SHIFT                                                     0x8
+#define BIFL_RAS_LEAF6_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT                                                0x9
+#define BIFL_RAS_LEAF6_STATUS__ERR_EVENT_PROP_STAT__SHIFT                                                     0xa
+#define BIFL_RAS_LEAF6_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT                                                0xb
+#define BIFL_RAS_LEAF6_STATUS__ERR_EVENT_RECV_MASK                                                            0x00000001L
+#define BIFL_RAS_LEAF6_STATUS__POISON_ERR_DET_MASK                                                            0x00000002L
+#define BIFL_RAS_LEAF6_STATUS__PARITY_ERR_DET_MASK                                                            0x00000004L
+#define BIFL_RAS_LEAF6_STATUS__ERR_EVENT_GENN_STAT_MASK                                                       0x00000100L
+#define BIFL_RAS_LEAF6_STATUS__EGRESS_STALLED_GENN_STAT_MASK                                                  0x00000200L
+#define BIFL_RAS_LEAF6_STATUS__ERR_EVENT_PROP_STAT_MASK                                                       0x00000400L
+#define BIFL_RAS_LEAF6_STATUS__EGRESS_STALLED_PROP_STAT_MASK                                                  0x00000800L
+//BIFL_RAS_LEAF7_STATUS
+#define BIFL_RAS_LEAF7_STATUS__ERR_EVENT_RECV__SHIFT                                                          0x0
+#define BIFL_RAS_LEAF7_STATUS__POISON_ERR_DET__SHIFT                                                          0x1
+#define BIFL_RAS_LEAF7_STATUS__PARITY_ERR_DET__SHIFT                                                          0x2
+#define BIFL_RAS_LEAF7_STATUS__ERR_EVENT_GENN_STAT__SHIFT                                                     0x8
+#define BIFL_RAS_LEAF7_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT                                                0x9
+#define BIFL_RAS_LEAF7_STATUS__ERR_EVENT_PROP_STAT__SHIFT                                                     0xa
+#define BIFL_RAS_LEAF7_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT                                                0xb
+#define BIFL_RAS_LEAF7_STATUS__ERR_EVENT_RECV_MASK                                                            0x00000001L
+#define BIFL_RAS_LEAF7_STATUS__POISON_ERR_DET_MASK                                                            0x00000002L
+#define BIFL_RAS_LEAF7_STATUS__PARITY_ERR_DET_MASK                                                            0x00000004L
+#define BIFL_RAS_LEAF7_STATUS__ERR_EVENT_GENN_STAT_MASK                                                       0x00000100L
+#define BIFL_RAS_LEAF7_STATUS__EGRESS_STALLED_GENN_STAT_MASK                                                  0x00000200L
+#define BIFL_RAS_LEAF7_STATUS__ERR_EVENT_PROP_STAT_MASK                                                       0x00000400L
+#define BIFL_RAS_LEAF7_STATUS__EGRESS_STALLED_PROP_STAT_MASK                                                  0x00000800L
+//BIFL_RAS_LEAF8_STATUS
+#define BIFL_RAS_LEAF8_STATUS__ERR_EVENT_RECV__SHIFT                                                          0x0
+#define BIFL_RAS_LEAF8_STATUS__POISON_ERR_DET__SHIFT                                                          0x1
+#define BIFL_RAS_LEAF8_STATUS__PARITY_ERR_DET__SHIFT                                                          0x2
+#define BIFL_RAS_LEAF8_STATUS__ERR_EVENT_GENN_STAT__SHIFT                                                     0x8
+#define BIFL_RAS_LEAF8_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT                                                0x9
+#define BIFL_RAS_LEAF8_STATUS__ERR_EVENT_PROP_STAT__SHIFT                                                     0xa
+#define BIFL_RAS_LEAF8_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT                                                0xb
+#define BIFL_RAS_LEAF8_STATUS__ERR_EVENT_RECV_MASK                                                            0x00000001L
+#define BIFL_RAS_LEAF8_STATUS__POISON_ERR_DET_MASK                                                            0x00000002L
+#define BIFL_RAS_LEAF8_STATUS__PARITY_ERR_DET_MASK                                                            0x00000004L
+#define BIFL_RAS_LEAF8_STATUS__ERR_EVENT_GENN_STAT_MASK                                                       0x00000100L
+#define BIFL_RAS_LEAF8_STATUS__EGRESS_STALLED_GENN_STAT_MASK                                                  0x00000200L
+#define BIFL_RAS_LEAF8_STATUS__ERR_EVENT_PROP_STAT_MASK                                                       0x00000400L
+#define BIFL_RAS_LEAF8_STATUS__EGRESS_STALLED_PROP_STAT_MASK                                                  0x00000800L
+//BIFL_RAS_LEAF9_STATUS
+#define BIFL_RAS_LEAF9_STATUS__ERR_EVENT_RECV__SHIFT                                                          0x0
+#define BIFL_RAS_LEAF9_STATUS__POISON_ERR_DET__SHIFT                                                          0x1
+#define BIFL_RAS_LEAF9_STATUS__PARITY_ERR_DET__SHIFT                                                          0x2
+#define BIFL_RAS_LEAF9_STATUS__ERR_EVENT_GENN_STAT__SHIFT                                                     0x8
+#define BIFL_RAS_LEAF9_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT                                                0x9
+#define BIFL_RAS_LEAF9_STATUS__ERR_EVENT_PROP_STAT__SHIFT                                                     0xa
+#define BIFL_RAS_LEAF9_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT                                                0xb
+#define BIFL_RAS_LEAF9_STATUS__ERR_EVENT_RECV_MASK                                                            0x00000001L
+#define BIFL_RAS_LEAF9_STATUS__POISON_ERR_DET_MASK                                                            0x00000002L
+#define BIFL_RAS_LEAF9_STATUS__PARITY_ERR_DET_MASK                                                            0x00000004L
+#define BIFL_RAS_LEAF9_STATUS__ERR_EVENT_GENN_STAT_MASK                                                       0x00000100L
+#define BIFL_RAS_LEAF9_STATUS__EGRESS_STALLED_GENN_STAT_MASK                                                  0x00000200L
+#define BIFL_RAS_LEAF9_STATUS__ERR_EVENT_PROP_STAT_MASK                                                       0x00000400L
+#define BIFL_RAS_LEAF9_STATUS__EGRESS_STALLED_PROP_STAT_MASK                                                  0x00000800L
+//BIFL_RAS_LEAF10_STATUS
+#define BIFL_RAS_LEAF10_STATUS__ERR_EVENT_RECV__SHIFT                                                         0x0
+#define BIFL_RAS_LEAF10_STATUS__POISON_ERR_DET__SHIFT                                                         0x1
+#define BIFL_RAS_LEAF10_STATUS__PARITY_ERR_DET__SHIFT                                                         0x2
+#define BIFL_RAS_LEAF10_STATUS__ERR_EVENT_GENN_STAT__SHIFT                                                    0x8
+#define BIFL_RAS_LEAF10_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT                                               0x9
+#define BIFL_RAS_LEAF10_STATUS__ERR_EVENT_PROP_STAT__SHIFT                                                    0xa
+#define BIFL_RAS_LEAF10_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT                                               0xb
+#define BIFL_RAS_LEAF10_STATUS__ERR_EVENT_RECV_MASK                                                           0x00000001L
+#define BIFL_RAS_LEAF10_STATUS__POISON_ERR_DET_MASK                                                           0x00000002L
+#define BIFL_RAS_LEAF10_STATUS__PARITY_ERR_DET_MASK                                                           0x00000004L
+#define BIFL_RAS_LEAF10_STATUS__ERR_EVENT_GENN_STAT_MASK                                                      0x00000100L
+#define BIFL_RAS_LEAF10_STATUS__EGRESS_STALLED_GENN_STAT_MASK                                                 0x00000200L
+#define BIFL_RAS_LEAF10_STATUS__ERR_EVENT_PROP_STAT_MASK                                                      0x00000400L
+#define BIFL_RAS_LEAF10_STATUS__EGRESS_STALLED_PROP_STAT_MASK                                                 0x00000800L
+//BIFL_RAS_LEAF11_STATUS
+#define BIFL_RAS_LEAF11_STATUS__ERR_EVENT_RECV__SHIFT                                                         0x0
+#define BIFL_RAS_LEAF11_STATUS__POISON_ERR_DET__SHIFT                                                         0x1
+#define BIFL_RAS_LEAF11_STATUS__PARITY_ERR_DET__SHIFT                                                         0x2
+#define BIFL_RAS_LEAF11_STATUS__ERR_EVENT_GENN_STAT__SHIFT                                                    0x8
+#define BIFL_RAS_LEAF11_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT                                               0x9
+#define BIFL_RAS_LEAF11_STATUS__ERR_EVENT_PROP_STAT__SHIFT                                                    0xa
+#define BIFL_RAS_LEAF11_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT                                               0xb
+#define BIFL_RAS_LEAF11_STATUS__ERR_EVENT_RECV_MASK                                                           0x00000001L
+#define BIFL_RAS_LEAF11_STATUS__POISON_ERR_DET_MASK                                                           0x00000002L
+#define BIFL_RAS_LEAF11_STATUS__PARITY_ERR_DET_MASK                                                           0x00000004L
+#define BIFL_RAS_LEAF11_STATUS__ERR_EVENT_GENN_STAT_MASK                                                      0x00000100L
+#define BIFL_RAS_LEAF11_STATUS__EGRESS_STALLED_GENN_STAT_MASK                                                 0x00000200L
+#define BIFL_RAS_LEAF11_STATUS__ERR_EVENT_PROP_STAT_MASK                                                      0x00000400L
+#define BIFL_RAS_LEAF11_STATUS__EGRESS_STALLED_PROP_STAT_MASK                                                 0x00000800L
+//BIFL_RAS_LEAF12_STATUS
+#define BIFL_RAS_LEAF12_STATUS__ERR_EVENT_RECV__SHIFT                                                         0x0
+#define BIFL_RAS_LEAF12_STATUS__POISON_ERR_DET__SHIFT                                                         0x1
+#define BIFL_RAS_LEAF12_STATUS__PARITY_ERR_DET__SHIFT                                                         0x2
+#define BIFL_RAS_LEAF12_STATUS__ERR_EVENT_GENN_STAT__SHIFT                                                    0x8
+#define BIFL_RAS_LEAF12_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT                                               0x9
+#define BIFL_RAS_LEAF12_STATUS__ERR_EVENT_PROP_STAT__SHIFT                                                    0xa
+#define BIFL_RAS_LEAF12_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT                                               0xb
+#define BIFL_RAS_LEAF12_STATUS__ERR_EVENT_RECV_MASK                                                           0x00000001L
+#define BIFL_RAS_LEAF12_STATUS__POISON_ERR_DET_MASK                                                           0x00000002L
+#define BIFL_RAS_LEAF12_STATUS__PARITY_ERR_DET_MASK                                                           0x00000004L
+#define BIFL_RAS_LEAF12_STATUS__ERR_EVENT_GENN_STAT_MASK                                                      0x00000100L
+#define BIFL_RAS_LEAF12_STATUS__EGRESS_STALLED_GENN_STAT_MASK                                                 0x00000200L
+#define BIFL_RAS_LEAF12_STATUS__ERR_EVENT_PROP_STAT_MASK                                                      0x00000400L
+#define BIFL_RAS_LEAF12_STATUS__EGRESS_STALLED_PROP_STAT_MASK                                                 0x00000800L
+//BIFL_RAS_LEAF13_STATUS
+#define BIFL_RAS_LEAF13_STATUS__ERR_EVENT_RECV__SHIFT                                                         0x0
+#define BIFL_RAS_LEAF13_STATUS__POISON_ERR_DET__SHIFT                                                         0x1
+#define BIFL_RAS_LEAF13_STATUS__PARITY_ERR_DET__SHIFT                                                         0x2
+#define BIFL_RAS_LEAF13_STATUS__ERR_EVENT_GENN_STAT__SHIFT                                                    0x8
+#define BIFL_RAS_LEAF13_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT                                               0x9
+#define BIFL_RAS_LEAF13_STATUS__ERR_EVENT_PROP_STAT__SHIFT                                                    0xa
+#define BIFL_RAS_LEAF13_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT                                               0xb
+#define BIFL_RAS_LEAF13_STATUS__ERR_EVENT_RECV_MASK                                                           0x00000001L
+#define BIFL_RAS_LEAF13_STATUS__POISON_ERR_DET_MASK                                                           0x00000002L
+#define BIFL_RAS_LEAF13_STATUS__PARITY_ERR_DET_MASK                                                           0x00000004L
+#define BIFL_RAS_LEAF13_STATUS__ERR_EVENT_GENN_STAT_MASK                                                      0x00000100L
+#define BIFL_RAS_LEAF13_STATUS__EGRESS_STALLED_GENN_STAT_MASK                                                 0x00000200L
+#define BIFL_RAS_LEAF13_STATUS__ERR_EVENT_PROP_STAT_MASK                                                      0x00000400L
+#define BIFL_RAS_LEAF13_STATUS__EGRESS_STALLED_PROP_STAT_MASK                                                 0x00000800L
+//BIFL_RAS_LEAF14_STATUS
+#define BIFL_RAS_LEAF14_STATUS__ERR_EVENT_RECV__SHIFT                                                         0x0
+#define BIFL_RAS_LEAF14_STATUS__POISON_ERR_DET__SHIFT                                                         0x1
+#define BIFL_RAS_LEAF14_STATUS__PARITY_ERR_DET__SHIFT                                                         0x2
+#define BIFL_RAS_LEAF14_STATUS__ERR_EVENT_GENN_STAT__SHIFT                                                    0x8
+#define BIFL_RAS_LEAF14_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT                                               0x9
+#define BIFL_RAS_LEAF14_STATUS__ERR_EVENT_PROP_STAT__SHIFT                                                    0xa
+#define BIFL_RAS_LEAF14_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT                                               0xb
+#define BIFL_RAS_LEAF14_STATUS__ERR_EVENT_RECV_MASK                                                           0x00000001L
+#define BIFL_RAS_LEAF14_STATUS__POISON_ERR_DET_MASK                                                           0x00000002L
+#define BIFL_RAS_LEAF14_STATUS__PARITY_ERR_DET_MASK                                                           0x00000004L
+#define BIFL_RAS_LEAF14_STATUS__ERR_EVENT_GENN_STAT_MASK                                                      0x00000100L
+#define BIFL_RAS_LEAF14_STATUS__EGRESS_STALLED_GENN_STAT_MASK                                                 0x00000200L
+#define BIFL_RAS_LEAF14_STATUS__ERR_EVENT_PROP_STAT_MASK                                                      0x00000400L
+#define BIFL_RAS_LEAF14_STATUS__EGRESS_STALLED_PROP_STAT_MASK                                                 0x00000800L
+//BIFL_RAS_LEAF15_STATUS
+#define BIFL_RAS_LEAF15_STATUS__ERR_EVENT_RECV__SHIFT                                                         0x0
+#define BIFL_RAS_LEAF15_STATUS__POISON_ERR_DET__SHIFT                                                         0x1
+#define BIFL_RAS_LEAF15_STATUS__PARITY_ERR_DET__SHIFT                                                         0x2
+#define BIFL_RAS_LEAF15_STATUS__ERR_EVENT_GENN_STAT__SHIFT                                                    0x8
+#define BIFL_RAS_LEAF15_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT                                               0x9
+#define BIFL_RAS_LEAF15_STATUS__ERR_EVENT_PROP_STAT__SHIFT                                                    0xa
+#define BIFL_RAS_LEAF15_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT                                               0xb
+#define BIFL_RAS_LEAF15_STATUS__ERR_EVENT_RECV_MASK                                                           0x00000001L
+#define BIFL_RAS_LEAF15_STATUS__POISON_ERR_DET_MASK                                                           0x00000002L
+#define BIFL_RAS_LEAF15_STATUS__PARITY_ERR_DET_MASK                                                           0x00000004L
+#define BIFL_RAS_LEAF15_STATUS__ERR_EVENT_GENN_STAT_MASK                                                      0x00000100L
+#define BIFL_RAS_LEAF15_STATUS__EGRESS_STALLED_GENN_STAT_MASK                                                 0x00000200L
+#define BIFL_RAS_LEAF15_STATUS__ERR_EVENT_PROP_STAT_MASK                                                      0x00000400L
+#define BIFL_RAS_LEAF15_STATUS__EGRESS_STALLED_PROP_STAT_MASK                                                 0x00000800L
+//BIFL_RAS_LEAF16_STATUS
+#define BIFL_RAS_LEAF16_STATUS__ERR_EVENT_RECV__SHIFT                                                         0x0
+#define BIFL_RAS_LEAF16_STATUS__POISON_ERR_DET__SHIFT                                                         0x1
+#define BIFL_RAS_LEAF16_STATUS__PARITY_ERR_DET__SHIFT                                                         0x2
+#define BIFL_RAS_LEAF16_STATUS__ERR_EVENT_GENN_STAT__SHIFT                                                    0x8
+#define BIFL_RAS_LEAF16_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT                                               0x9
+#define BIFL_RAS_LEAF16_STATUS__ERR_EVENT_PROP_STAT__SHIFT                                                    0xa
+#define BIFL_RAS_LEAF16_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT                                               0xb
+#define BIFL_RAS_LEAF16_STATUS__ERR_EVENT_RECV_MASK                                                           0x00000001L
+#define BIFL_RAS_LEAF16_STATUS__POISON_ERR_DET_MASK                                                           0x00000002L
+#define BIFL_RAS_LEAF16_STATUS__PARITY_ERR_DET_MASK                                                           0x00000004L
+#define BIFL_RAS_LEAF16_STATUS__ERR_EVENT_GENN_STAT_MASK                                                      0x00000100L
+#define BIFL_RAS_LEAF16_STATUS__EGRESS_STALLED_GENN_STAT_MASK                                                 0x00000200L
+#define BIFL_RAS_LEAF16_STATUS__ERR_EVENT_PROP_STAT_MASK                                                      0x00000400L
+#define BIFL_RAS_LEAF16_STATUS__EGRESS_STALLED_PROP_STAT_MASK                                                 0x00000800L
+//BIFL_RAS_LEAF17_STATUS
+#define BIFL_RAS_LEAF17_STATUS__ERR_EVENT_RECV__SHIFT                                                         0x0
+#define BIFL_RAS_LEAF17_STATUS__POISON_ERR_DET__SHIFT                                                         0x1
+#define BIFL_RAS_LEAF17_STATUS__PARITY_ERR_DET__SHIFT                                                         0x2
+#define BIFL_RAS_LEAF17_STATUS__ERR_EVENT_GENN_STAT__SHIFT                                                    0x8
+#define BIFL_RAS_LEAF17_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT                                               0x9
+#define BIFL_RAS_LEAF17_STATUS__ERR_EVENT_PROP_STAT__SHIFT                                                    0xa
+#define BIFL_RAS_LEAF17_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT                                               0xb
+#define BIFL_RAS_LEAF17_STATUS__ERR_EVENT_RECV_MASK                                                           0x00000001L
+#define BIFL_RAS_LEAF17_STATUS__POISON_ERR_DET_MASK                                                           0x00000002L
+#define BIFL_RAS_LEAF17_STATUS__PARITY_ERR_DET_MASK                                                           0x00000004L
+#define BIFL_RAS_LEAF17_STATUS__ERR_EVENT_GENN_STAT_MASK                                                      0x00000100L
+#define BIFL_RAS_LEAF17_STATUS__EGRESS_STALLED_GENN_STAT_MASK                                                 0x00000200L
+#define BIFL_RAS_LEAF17_STATUS__ERR_EVENT_PROP_STAT_MASK                                                      0x00000400L
+#define BIFL_RAS_LEAF17_STATUS__EGRESS_STALLED_PROP_STAT_MASK                                                 0x00000800L
+//BIFL_RAS_LEAF18_STATUS
+#define BIFL_RAS_LEAF18_STATUS__ERR_EVENT_RECV__SHIFT                                                         0x0
+#define BIFL_RAS_LEAF18_STATUS__POISON_ERR_DET__SHIFT                                                         0x1
+#define BIFL_RAS_LEAF18_STATUS__PARITY_ERR_DET__SHIFT                                                         0x2
+#define BIFL_RAS_LEAF18_STATUS__ERR_EVENT_GENN_STAT__SHIFT                                                    0x8
+#define BIFL_RAS_LEAF18_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT                                               0x9
+#define BIFL_RAS_LEAF18_STATUS__ERR_EVENT_PROP_STAT__SHIFT                                                    0xa
+#define BIFL_RAS_LEAF18_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT                                               0xb
+#define BIFL_RAS_LEAF18_STATUS__ERR_EVENT_RECV_MASK                                                           0x00000001L
+#define BIFL_RAS_LEAF18_STATUS__POISON_ERR_DET_MASK                                                           0x00000002L
+#define BIFL_RAS_LEAF18_STATUS__PARITY_ERR_DET_MASK                                                           0x00000004L
+#define BIFL_RAS_LEAF18_STATUS__ERR_EVENT_GENN_STAT_MASK                                                      0x00000100L
+#define BIFL_RAS_LEAF18_STATUS__EGRESS_STALLED_GENN_STAT_MASK                                                 0x00000200L
+#define BIFL_RAS_LEAF18_STATUS__ERR_EVENT_PROP_STAT_MASK                                                      0x00000400L
+#define BIFL_RAS_LEAF18_STATUS__EGRESS_STALLED_PROP_STAT_MASK                                                 0x00000800L
+//BIFL_RAS_LEAF19_STATUS
+#define BIFL_RAS_LEAF19_STATUS__ERR_EVENT_RECV__SHIFT                                                         0x0
+#define BIFL_RAS_LEAF19_STATUS__POISON_ERR_DET__SHIFT                                                         0x1
+#define BIFL_RAS_LEAF19_STATUS__PARITY_ERR_DET__SHIFT                                                         0x2
+#define BIFL_RAS_LEAF19_STATUS__ERR_EVENT_GENN_STAT__SHIFT                                                    0x8
+#define BIFL_RAS_LEAF19_STATUS__EGRESS_STALLED_GENN_STAT__SHIFT                                               0x9
+#define BIFL_RAS_LEAF19_STATUS__ERR_EVENT_PROP_STAT__SHIFT                                                    0xa
+#define BIFL_RAS_LEAF19_STATUS__EGRESS_STALLED_PROP_STAT__SHIFT                                               0xb
+#define BIFL_RAS_LEAF19_STATUS__ERR_EVENT_RECV_MASK                                                           0x00000001L
+#define BIFL_RAS_LEAF19_STATUS__POISON_ERR_DET_MASK                                                           0x00000002L
+#define BIFL_RAS_LEAF19_STATUS__PARITY_ERR_DET_MASK                                                           0x00000004L
+#define BIFL_RAS_LEAF19_STATUS__ERR_EVENT_GENN_STAT_MASK                                                      0x00000100L
+#define BIFL_RAS_LEAF19_STATUS__EGRESS_STALLED_GENN_STAT_MASK                                                 0x00000200L
+#define BIFL_RAS_LEAF19_STATUS__ERR_EVENT_PROP_STAT_MASK                                                      0x00000400L
+#define BIFL_RAS_LEAF19_STATUS__EGRESS_STALLED_PROP_STAT_MASK                                                 0x00000800L
+//BIFL_DFV_POISON_INJ_IOHUB_ORIG_SDP
+#define BIFL_DFV_POISON_INJ_IOHUB_ORIG_SDP__IOHUB_ORIG_INGRESS_RDRSPDATA_POISON_INJ__SHIFT                    0x0
+#define BIFL_DFV_POISON_INJ_IOHUB_ORIG_SDP__IOHUB_ORIG_INGRESS_RDRSPDATA_PARITY_INJ__SHIFT                    0x4
+#define BIFL_DFV_POISON_INJ_IOHUB_ORIG_SDP__IOHUB_ORIG_EGRESS_ORIGDATA_POISON_INJ__SHIFT                      0x8
+#define BIFL_DFV_POISON_INJ_IOHUB_ORIG_SDP__IOHUB_ORIG_EGRESS_ORIGDATA_PARITY_INJ__SHIFT                      0xc
+#define BIFL_DFV_POISON_INJ_IOHUB_ORIG_SDP__IOHUB_ORIG_INGRESS_RDRSPDATA_POISON_INJ_MASK                      0x0000000FL
+#define BIFL_DFV_POISON_INJ_IOHUB_ORIG_SDP__IOHUB_ORIG_INGRESS_RDRSPDATA_PARITY_INJ_MASK                      0x000000F0L
+#define BIFL_DFV_POISON_INJ_IOHUB_ORIG_SDP__IOHUB_ORIG_EGRESS_ORIGDATA_POISON_INJ_MASK                        0x00000F00L
+#define BIFL_DFV_POISON_INJ_IOHUB_ORIG_SDP__IOHUB_ORIG_EGRESS_ORIGDATA_PARITY_INJ_MASK                        0x0000F000L
+//BIFL_DFV_POISON_INJ_IOHUB_CMPL_SDP
+#define BIFL_DFV_POISON_INJ_IOHUB_CMPL_SDP__IOHUB_CMPL_INGRESS_ORIGDATA_POISON_INJ__SHIFT                     0x0
+#define BIFL_DFV_POISON_INJ_IOHUB_CMPL_SDP__IOHUB_CMPL_INGRESS_ORIGDATA_PARITY_INJ__SHIFT                     0x4
+#define BIFL_DFV_POISON_INJ_IOHUB_CMPL_SDP__IOHUB_CMPL_EGRESS_RDRSPDATA_POISON_INJ__SHIFT                     0x8
+#define BIFL_DFV_POISON_INJ_IOHUB_CMPL_SDP__IOHUB_CMPL_EGRESS_RDRSPDATA_PARITY_INJ__SHIFT                     0xc
+#define BIFL_DFV_POISON_INJ_IOHUB_CMPL_SDP__IOHUB_CMPL_INGRESS_ORIGDATA_POISON_INJ_MASK                       0x0000000FL
+#define BIFL_DFV_POISON_INJ_IOHUB_CMPL_SDP__IOHUB_CMPL_INGRESS_ORIGDATA_PARITY_INJ_MASK                       0x000000F0L
+#define BIFL_DFV_POISON_INJ_IOHUB_CMPL_SDP__IOHUB_CMPL_EGRESS_RDRSPDATA_POISON_INJ_MASK                       0x00000F00L
+#define BIFL_DFV_POISON_INJ_IOHUB_CMPL_SDP__IOHUB_CMPL_EGRESS_RDRSPDATA_PARITY_INJ_MASK                       0x0000F000L
+//BIFL_DFV_POISON_INJ_ATHUB_CMPL_SDP
+#define BIFL_DFV_POISON_INJ_ATHUB_CMPL_SDP__ATHUB_CMPL_INGRESS_ORIGDATA_POISON_INJ__SHIFT                     0x0
+#define BIFL_DFV_POISON_INJ_ATHUB_CMPL_SDP__ATHUB_CMPL_INGRESS_ORIGDATA_PARITY_INJ__SHIFT                     0x4
+#define BIFL_DFV_POISON_INJ_ATHUB_CMPL_SDP__ATHUB_CMPL_EGRESS_RDRSPDATA_POISON_INJ__SHIFT                     0x8
+#define BIFL_DFV_POISON_INJ_ATHUB_CMPL_SDP__ATHUB_CMPL_EGRESS_RDRSPDATA_PARITY_INJ__SHIFT                     0xc
+#define BIFL_DFV_POISON_INJ_ATHUB_CMPL_SDP__ATHUB_CMPL_INGRESS_ORIGDATA_POISON_INJ_MASK                       0x0000000FL
+#define BIFL_DFV_POISON_INJ_ATHUB_CMPL_SDP__ATHUB_CMPL_INGRESS_ORIGDATA_PARITY_INJ_MASK                       0x000000F0L
+#define BIFL_DFV_POISON_INJ_ATHUB_CMPL_SDP__ATHUB_CMPL_EGRESS_RDRSPDATA_POISON_INJ_MASK                       0x00000F00L
+#define BIFL_DFV_POISON_INJ_ATHUB_CMPL_SDP__ATHUB_CMPL_EGRESS_RDRSPDATA_PARITY_INJ_MASK                       0x0000F000L
+//BIFL_DFV_POISON_INJ_ATHUB_ORIG_SDP
+#define BIFL_DFV_POISON_INJ_ATHUB_ORIG_SDP__ATHUB_ORIG_EGRESS_ORIGDATA_POISON_INJ__SHIFT                      0x8
+#define BIFL_DFV_POISON_INJ_ATHUB_ORIG_SDP__ATHUB_ORIG_EGRESS_ORIGDATA_PARITY_INJ__SHIFT                      0xc
+#define BIFL_DFV_POISON_INJ_ATHUB_ORIG_SDP__ATHUB_ORIG_EGRESS_ORIGDATA_POISON_INJ_MASK                        0x00000F00L
+#define BIFL_DFV_POISON_INJ_ATHUB_ORIG_SDP__ATHUB_ORIG_EGRESS_ORIGDATA_PARITY_INJ_MASK                        0x0000F000L
+//BIFL_DFV_POISON_INJ_CNT_IOHUB_ORIG_SDP
+#define BIFL_DFV_POISON_INJ_CNT_IOHUB_ORIG_SDP__IOHUB_ORIG_INGRESS_RDRSPDATA_POISON_INJ_CNT__SHIFT            0x0
+#define BIFL_DFV_POISON_INJ_CNT_IOHUB_ORIG_SDP__IOHUB_ORIG_INGRESS_RDRSPDATA_PARITY_INJ_CNT__SHIFT            0x4
+#define BIFL_DFV_POISON_INJ_CNT_IOHUB_ORIG_SDP__IOHUB_ORIG_EGRESS_ORIGDATA_POISON_INJ_CNT__SHIFT              0x8
+#define BIFL_DFV_POISON_INJ_CNT_IOHUB_ORIG_SDP__IOHUB_ORIG_EGRESS_ORIGDATA_PARITY_INJ_CNT__SHIFT              0xc
+#define BIFL_DFV_POISON_INJ_CNT_IOHUB_ORIG_SDP__IOHUB_ORIG_INGRESS_RDRSPDATA_POISON_INJ_CNT_MASK              0x0000000FL
+#define BIFL_DFV_POISON_INJ_CNT_IOHUB_ORIG_SDP__IOHUB_ORIG_INGRESS_RDRSPDATA_PARITY_INJ_CNT_MASK              0x000000F0L
+#define BIFL_DFV_POISON_INJ_CNT_IOHUB_ORIG_SDP__IOHUB_ORIG_EGRESS_ORIGDATA_POISON_INJ_CNT_MASK                0x00000F00L
+#define BIFL_DFV_POISON_INJ_CNT_IOHUB_ORIG_SDP__IOHUB_ORIG_EGRESS_ORIGDATA_PARITY_INJ_CNT_MASK                0x0000F000L
+//BIFL_DFV_POISON_INJ_CNT_IOHUB_CMPL_SDP
+#define BIFL_DFV_POISON_INJ_CNT_IOHUB_CMPL_SDP__IOHUB_CMPL_INGRESS_ORIGDATA_POISON_INJ_CNT__SHIFT             0x0
+#define BIFL_DFV_POISON_INJ_CNT_IOHUB_CMPL_SDP__IOHUB_CMPL_INGRESS_ORIGDATA_PARITY_INJ_CNT__SHIFT             0x4
+#define BIFL_DFV_POISON_INJ_CNT_IOHUB_CMPL_SDP__IOHUB_CMPL_EGRESS_RDRSPDATA_POISON_INJ_CNT__SHIFT             0x8
+#define BIFL_DFV_POISON_INJ_CNT_IOHUB_CMPL_SDP__IOHUB_CMPL_EGRESS_RDRSPDATA_PARITY_INJ_CNT__SHIFT             0xc
+#define BIFL_DFV_POISON_INJ_CNT_IOHUB_CMPL_SDP__IOHUB_CMPL_INGRESS_ORIGDATA_POISON_INJ_CNT_MASK               0x0000000FL
+#define BIFL_DFV_POISON_INJ_CNT_IOHUB_CMPL_SDP__IOHUB_CMPL_INGRESS_ORIGDATA_PARITY_INJ_CNT_MASK               0x000000F0L
+#define BIFL_DFV_POISON_INJ_CNT_IOHUB_CMPL_SDP__IOHUB_CMPL_EGRESS_RDRSPDATA_POISON_INJ_CNT_MASK               0x00000F00L
+#define BIFL_DFV_POISON_INJ_CNT_IOHUB_CMPL_SDP__IOHUB_CMPL_EGRESS_RDRSPDATA_PARITY_INJ_CNT_MASK               0x0000F000L
+//BIFL_DFV_POISON_INJ_CNT_ATHUB_CMPL_SDP
+#define BIFL_DFV_POISON_INJ_CNT_ATHUB_CMPL_SDP__ATHUB_CMPL_INGRESS_ORIGDATA_POISON_INJ_CNT__SHIFT             0x0
+#define BIFL_DFV_POISON_INJ_CNT_ATHUB_CMPL_SDP__ATHUB_CMPL_INGRESS_ORIGDATA_PARITY_INJ_CNT__SHIFT             0x4
+#define BIFL_DFV_POISON_INJ_CNT_ATHUB_CMPL_SDP__ATHUB_CMPL_EGRESS_RDRSPDATA_POISON_INJ_CNT__SHIFT             0x8
+#define BIFL_DFV_POISON_INJ_CNT_ATHUB_CMPL_SDP__ATHUB_CMPL_EGRESS_RDRSPDATA_PARITY_INJ_CNT__SHIFT             0xc
+#define BIFL_DFV_POISON_INJ_CNT_ATHUB_CMPL_SDP__ATHUB_CMPL_INGRESS_ORIGDATA_POISON_INJ_CNT_MASK               0x0000000FL
+#define BIFL_DFV_POISON_INJ_CNT_ATHUB_CMPL_SDP__ATHUB_CMPL_INGRESS_ORIGDATA_PARITY_INJ_CNT_MASK               0x000000F0L
+#define BIFL_DFV_POISON_INJ_CNT_ATHUB_CMPL_SDP__ATHUB_CMPL_EGRESS_RDRSPDATA_POISON_INJ_CNT_MASK               0x00000F00L
+#define BIFL_DFV_POISON_INJ_CNT_ATHUB_CMPL_SDP__ATHUB_CMPL_EGRESS_RDRSPDATA_PARITY_INJ_CNT_MASK               0x0000F000L
+//BIFL_DFV_POISON_INJ_CNT_ATHUB_ORIG_SDP
+#define BIFL_DFV_POISON_INJ_CNT_ATHUB_ORIG_SDP__ATHUB_ORIG_EGRESS_ORIGDATA_POISON_INJ_CNT__SHIFT              0x8
+#define BIFL_DFV_POISON_INJ_CNT_ATHUB_ORIG_SDP__ATHUB_ORIG_EGRESS_ORIGDATA_PARITY_INJ_CNT__SHIFT              0xc
+#define BIFL_DFV_POISON_INJ_CNT_ATHUB_ORIG_SDP__ATHUB_ORIG_EGRESS_ORIGDATA_POISON_INJ_CNT_MASK                0x00000F00L
+#define BIFL_DFV_POISON_INJ_CNT_ATHUB_ORIG_SDP__ATHUB_ORIG_EGRESS_ORIGDATA_PARITY_INJ_CNT_MASK                0x0000F000L
+//BIFL_DFV_POISON_INJ_LOG_IOHUB_ORIG_SDP
+#define BIFL_DFV_POISON_INJ_LOG_IOHUB_ORIG_SDP__IOHUB_ORIG_INGRESS_RDRSPDATA_POISON_INJ_LOG__SHIFT            0x0
+#define BIFL_DFV_POISON_INJ_LOG_IOHUB_ORIG_SDP__IOHUB_ORIG_INGRESS_RDRSPDATA_PARITY_INJ_LOG__SHIFT            0x4
+#define BIFL_DFV_POISON_INJ_LOG_IOHUB_ORIG_SDP__IOHUB_ORIG_INGRESS_RDRSPDATA_POISON_INJ_LOG_MASK              0x0000000FL
+#define BIFL_DFV_POISON_INJ_LOG_IOHUB_ORIG_SDP__IOHUB_ORIG_INGRESS_RDRSPDATA_PARITY_INJ_LOG_MASK              0x000000F0L
+//BIFL_DFV_POISON_INJ_LOG_IOHUB_CMPL_SDP
+#define BIFL_DFV_POISON_INJ_LOG_IOHUB_CMPL_SDP__IOHUB_CMPL_INGRESS_ORIGDATA_POISON_INJ_LOG__SHIFT             0x0
+#define BIFL_DFV_POISON_INJ_LOG_IOHUB_CMPL_SDP__IOHUB_CMPL_INGRESS_ORIGDATA_PARITY_INJ_LOG__SHIFT             0x4
+#define BIFL_DFV_POISON_INJ_LOG_IOHUB_CMPL_SDP__IOHUB_CMPL_INGRESS_ORIGDATA_POISON_INJ_LOG_MASK               0x0000000FL
+#define BIFL_DFV_POISON_INJ_LOG_IOHUB_CMPL_SDP__IOHUB_CMPL_INGRESS_ORIGDATA_PARITY_INJ_LOG_MASK               0x000000F0L
+//BIFL_DFV_POISON_INJ_LOG_ATHUB_CMPL_SDP
+#define BIFL_DFV_POISON_INJ_LOG_ATHUB_CMPL_SDP__ATHUB_CMPL_INGRESS_ORIGDATA_POISON_INJ_LOG__SHIFT             0x0
+#define BIFL_DFV_POISON_INJ_LOG_ATHUB_CMPL_SDP__ATHUB_CMPL_INGRESS_ORIGDATA_PARITY_INJ_LOG__SHIFT             0x4
+#define BIFL_DFV_POISON_INJ_LOG_ATHUB_CMPL_SDP__ATHUB_CMPL_INGRESS_ORIGDATA_POISON_INJ_LOG_MASK               0x0000000FL
+#define BIFL_DFV_POISON_INJ_LOG_ATHUB_CMPL_SDP__ATHUB_CMPL_INGRESS_ORIGDATA_PARITY_INJ_LOG_MASK               0x000000F0L
+//BIFL_DFV_POISON_INJ_LOG_ATHUB_ORIG_SDP
+//BIFL_IOHUB_RAS_IH_CNTL
+#define BIFL_IOHUB_RAS_IH_CNTL__BIFL_RAS_IH_INTR_EN__SHIFT                                                    0x0
+#define BIFL_IOHUB_RAS_IH_CNTL__BIFL_RAS_IH_INTR_EN_MASK                                                      0x00000001L
+//BIFL_RAS_VWR_FROM_IOHUB
+#define BIFL_RAS_VWR_FROM_IOHUB__BIFL_RAS_IH_INTR_TRIG__SHIFT                                                 0x0
+#define BIFL_RAS_VWR_FROM_IOHUB__BIFL_RAS_IH_INTR_TRIG_MASK                                                   0x00000001L
+
+
+// addressBlock: nbif0_nbif0_rcc_dwn_dev0_BIFDEC1
+//RCC_DWN_DEV0_2_DN_PCIE_RESERVED
+#define RCC_DWN_DEV0_2_DN_PCIE_RESERVED__PCIE_RESERVED__SHIFT                                                 0x0
+#define RCC_DWN_DEV0_2_DN_PCIE_RESERVED__PCIE_RESERVED_MASK                                                   0xFFFFFFFFL
+//RCC_DWN_DEV0_2_DN_PCIE_SCRATCH
+#define RCC_DWN_DEV0_2_DN_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT                                                   0x0
+#define RCC_DWN_DEV0_2_DN_PCIE_SCRATCH__PCIE_SCRATCH_MASK                                                     0xFFFFFFFFL
+//RCC_DWN_DEV0_2_DN_PCIE_CNTL
+#define RCC_DWN_DEV0_2_DN_PCIE_CNTL__HWINIT_WR_LOCK__SHIFT                                                    0x0
+#define RCC_DWN_DEV0_2_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN__SHIFT                                              0x7
+#define RCC_DWN_DEV0_2_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT                                              0x1e
+#define RCC_DWN_DEV0_2_DN_PCIE_CNTL__HWINIT_WR_LOCK_MASK                                                      0x00000001L
+#define RCC_DWN_DEV0_2_DN_PCIE_CNTL__UR_ERR_REPORT_DIS_DN_MASK                                                0x00000080L
+#define RCC_DWN_DEV0_2_DN_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK                                                0x40000000L
+//RCC_DWN_DEV0_2_DN_PCIE_CONFIG_CNTL
+#define RCC_DWN_DEV0_2_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE__SHIFT                                0x19
+#define RCC_DWN_DEV0_2_DN_PCIE_CONFIG_CNTL__CI_EXTENDED_TAG_EN_OVERRIDE_MASK                                  0x06000000L
+//RCC_DWN_DEV0_2_DN_PCIE_RX_CNTL2
+#define RCC_DWN_DEV0_2_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE__SHIFT                                               0x1c
+#define RCC_DWN_DEV0_2_DN_PCIE_RX_CNTL2__FLR_EXTEND_MODE_MASK                                                 0x70000000L
+//RCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL
+#define RCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT                                             0x7
+#define RCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN__SHIFT                                   0x8
+#define RCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK                                               0x00000080L
+#define RCC_DWN_DEV0_2_DN_PCIE_BUS_CNTL__AER_CPL_TIMEOUT_RO_DIS_SWDN_MASK                                     0x00000100L
+//RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL
+#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT                                      0x0
+#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT                                 0x1
+#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT                                 0x2
+#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT                                 0x3
+#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT                                 0x4
+#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN6_HIDDEN_REG__SHIFT                                 0x5
+#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK                                        0x00000001L
+#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK                                   0x00000002L
+#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK                                   0x00000004L
+#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK                                   0x00000008L
+#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK                                   0x00000010L
+#define RCC_DWN_DEV0_2_DN_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN6_HIDDEN_REG_MASK                                   0x00000020L
+//RCC_DWN_DEV0_2_DN_PCIE_STRAP_F0
+#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_F0__STRAP_F0_EN__SHIFT                                                   0x0
+#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN__SHIFT                                                0x11
+#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP__SHIFT                                        0x15
+#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_F0__STRAP_F0_EN_MASK                                                     0x00000001L
+#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_F0__STRAP_F0_MC_EN_MASK                                                  0x00020000L
+#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_F0__STRAP_F0_MSI_MULTI_CAP_MASK                                          0x00E00000L
+//RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC
+#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN__SHIFT                                             0x18
+#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT                                          0x1d
+#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC__STRAP_CLK_PM_EN_MASK                                               0x01000000L
+#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK                                            0x20000000L
+//RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC2
+#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN__SHIFT                                    0x2
+#define RCC_DWN_DEV0_2_DN_PCIE_STRAP_MISC2__STRAP_MSTCPL_TIMEOUT_EN_MASK                                      0x00000004L
+
+
+// addressBlock: nbif0_nbif0_rcc_dwnp_dev0_BIFDEC1
+//RCC_DWNP_DEV0_2_PCIE_ERR_CNTL
+#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT                                               0x0
+#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT                                             0x8
+#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT                                    0xb
+#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT                                        0x11
+#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR__SHIFT                                               0x12
+#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR__SHIFT                                           0x13
+#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR__SHIFT                                              0x14
+#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK                                                 0x00000001L
+#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK                                               0x00000700L
+#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK                                      0x00000800L
+#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK                                          0x00020000L
+#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__ERR_CORR_RCVD_CLR_MASK                                                 0x00040000L
+#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__NONFATAL_ERR_RCVD_CLR_MASK                                             0x00080000L
+#define RCC_DWNP_DEV0_2_PCIE_ERR_CNTL__FATAL_ERR_RCVD_CLR_MASK                                                0x00100000L
+//RCC_DWNP_DEV0_2_PCIE_RX_CNTL
+#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT                                        0x8
+#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN__SHIFT                                              0x9
+#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT                                          0x14
+#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN__SHIFT                                     0x15
+#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS__SHIFT                                           0x1b
+#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK                                          0x00000100L
+#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_DN_MASK                                                0x00000200L
+#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK                                            0x00100000L
+#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_DN_MASK                                       0x00200000L
+#define RCC_DWNP_DEV0_2_PCIE_RX_CNTL__RX_RCB_FLR_TIMEOUT_DIS_MASK                                             0x08000000L
+//RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL
+#define RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT                                           0x0
+#define RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT                                           0x1
+#define RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT                                           0x2
+#define RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP__SHIFT                                           0x3
+#define RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN6_EN_STRAP__SHIFT                                           0x4
+#define RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK                                             0x00000001L
+#define RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK                                             0x00000002L
+#define RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK                                             0x00000004L
+#define RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP_MASK                                             0x00000008L
+#define RCC_DWNP_DEV0_2_PCIE_LC_SPEED_CNTL__LC_GEN6_EN_STRAP_MASK                                             0x00000010L
+//RCC_DWNP_DEV0_2_PCIE_LC_CNTL2
+#define RCC_DWNP_DEV0_2_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS__SHIFT                               0x0
+#define RCC_DWNP_DEV0_2_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS__SHIFT                                     0x1b
+#define RCC_DWNP_DEV0_2_PCIE_LC_CNTL2__DL_STATE_CHANGED_NOTIFICATION_DIS_MASK                                 0x00000001L
+#define RCC_DWNP_DEV0_2_PCIE_LC_CNTL2__LC_LINK_BW_NOTIFICATION_DIS_MASK                                       0x08000000L
+//RCC_DWNP_DEV0_2_PCIEP_STRAP_MISC
+#define RCC_DWNP_DEV0_2_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN__SHIFT                                          0xa
+#define RCC_DWNP_DEV0_2_PCIEP_STRAP_MISC__STRAP_MULTI_FUNC_EN_MASK                                            0x00000400L
+//RCC_DWNP_DEV0_2_LTR_MSG_INFO_FROM_EP
+#define RCC_DWNP_DEV0_2_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP__SHIFT                                     0x0
+#define RCC_DWNP_DEV0_2_LTR_MSG_INFO_FROM_EP__LTR_MSG_INFO_FROM_EP_MASK                                       0xFFFFFFFFL
+
+
+// addressBlock: nbif0_nbif0_rcc_ep_dev0_BIFDEC1
+//RCC_EP_DEV0_2_EP_PCIE_SCRATCH
+#define RCC_EP_DEV0_2_EP_PCIE_SCRATCH__PCIE_SCRATCH__SHIFT                                                    0x0
+#define RCC_EP_DEV0_2_EP_PCIE_SCRATCH__PCIE_SCRATCH_MASK                                                      0xFFFFFFFFL
+//RCC_EP_DEV0_2_EP_PCIE_CNTL
+#define RCC_EP_DEV0_2_EP_PCIE_CNTL__UR_ERR_REPORT_DIS__SHIFT                                                  0x7
+#define RCC_EP_DEV0_2_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS__SHIFT                                            0x8
+#define RCC_EP_DEV0_2_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR__SHIFT                                               0x1e
+#define RCC_EP_DEV0_2_EP_PCIE_CNTL__UR_ERR_REPORT_DIS_MASK                                                    0x00000080L
+#define RCC_EP_DEV0_2_EP_PCIE_CNTL__PCIE_MALFORM_ATOMIC_OPS_MASK                                              0x00000100L
+#define RCC_EP_DEV0_2_EP_PCIE_CNTL__RX_IGNORE_LTR_MSG_UR_MASK                                                 0x40000000L
+//RCC_EP_DEV0_2_EP_PCIE_INT_CNTL
+#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN__SHIFT                                                0x0
+#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN__SHIFT                                           0x1
+#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN__SHIFT                                               0x2
+#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN__SHIFT                                            0x3
+#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN__SHIFT                                                0x4
+#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN__SHIFT                                         0x6
+#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__CORR_ERR_INT_EN_MASK                                                  0x00000001L
+#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__NON_FATAL_ERR_INT_EN_MASK                                             0x00000002L
+#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__FATAL_ERR_INT_EN_MASK                                                 0x00000004L
+#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__USR_DETECTED_INT_EN_MASK                                              0x00000008L
+#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__MISC_ERR_INT_EN_MASK                                                  0x00000010L
+#define RCC_EP_DEV0_2_EP_PCIE_INT_CNTL__POWER_STATE_CHG_INT_EN_MASK                                           0x00000040L
+//RCC_EP_DEV0_2_EP_PCIE_INT_STATUS
+#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS__SHIFT                                          0x0
+#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS__SHIFT                                     0x1
+#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS__SHIFT                                         0x2
+#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS__SHIFT                                      0x3
+#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS__SHIFT                                          0x4
+#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS__SHIFT                                   0x6
+#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0__SHIFT                                0x7
+#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__CORR_ERR_INT_STATUS_MASK                                            0x00000001L
+#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__NON_FATAL_ERR_INT_STATUS_MASK                                       0x00000002L
+#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__FATAL_ERR_INT_STATUS_MASK                                           0x00000004L
+#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__USR_DETECTED_INT_STATUS_MASK                                        0x00000008L
+#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__MISC_ERR_INT_STATUS_MASK                                            0x00000010L
+#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_MASK                                     0x00000040L
+#define RCC_EP_DEV0_2_EP_PCIE_INT_STATUS__POWER_STATE_CHG_INT_STATUS_F0_MASK                                  0x00000080L
+//RCC_EP_DEV0_2_EP_PCIE_RX_CNTL2
+#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR__SHIFT                                   0x0
+#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL2__RX_IGNORE_EP_INVALIDPASID_UR_MASK                                     0x00000001L
+//RCC_EP_DEV0_2_EP_PCIE_BUS_CNTL
+#define RCC_EP_DEV0_2_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS__SHIFT                                              0x7
+#define RCC_EP_DEV0_2_EP_PCIE_BUS_CNTL__IMMEDIATE_PMI_DIS_MASK                                                0x00000080L
+//RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL
+#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG__SHIFT                                       0x0
+#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG__SHIFT                                  0x1
+#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG__SHIFT                                  0x2
+#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG__SHIFT                                  0x3
+#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG__SHIFT                                  0x4
+#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN6_HIDDEN_REG__SHIFT                                  0x5
+#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_HIDDEN_REG_MASK                                         0x00000001L
+#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN2_HIDDEN_REG_MASK                                    0x00000002L
+#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN3_HIDDEN_REG_MASK                                    0x00000004L
+#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN4_HIDDEN_REG_MASK                                    0x00000008L
+#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN5_HIDDEN_REG_MASK                                    0x00000010L
+#define RCC_EP_DEV0_2_EP_PCIE_CFG_CNTL__CFG_EN_DEC_TO_GEN6_HIDDEN_REG_MASK                                    0x00000020L
+//RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE__SHIFT                                      0x0
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE__SHIFT                                       0x3
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT__SHIFT                                      0x6
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE__SHIFT                                     0x7
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE__SHIFT                                      0xa
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT__SHIFT                                     0xd
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0__SHIFT                               0xe
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN__SHIFT                                 0xf
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1__SHIFT                                            0x10
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN__SHIFT                                   0x11
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_SHORT_VALUE_MASK                                        0x00000007L
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_LONG_VALUE_MASK                                         0x00000038L
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_S_REQUIREMENT_MASK                                        0x00000040L
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_SHORT_VALUE_MASK                                       0x00000380L
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_LONG_VALUE_MASK                                        0x00001C00L
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_NS_REQUIREMENT_MASK                                       0x00002000L
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_MSG_DIS_IN_PM_NON_D0_MASK                                 0x00004000L
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_PRIV_RST_LTR_IN_DL_DOWN_MASK                                   0x00008000L
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__TX_CHK_FC_FOR_L1_MASK                                              0x00010000L
+#define RCC_EP_DEV0_2_EP_PCIE_TX_LTR_CNTL__LTR_DSTATE_USING_WDATA_EN_MASK                                     0x00020000L
+//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0
+#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1
+#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2
+#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3
+#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4
+#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5
+#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6
+#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7
+#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_1_PCIE_F1_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_2_EP_PCIE_STRAP_MISC
+#define RCC_EP_DEV0_2_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN__SHIFT                                           0x1d
+#define RCC_EP_DEV0_2_EP_PCIE_STRAP_MISC__STRAP_MST_ADR64_EN_MASK                                             0x20000000L
+//RCC_EP_DEV0_2_EP_PCIE_STRAP_MISC2
+#define RCC_EP_DEV0_2_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED__SHIFT                                         0x4
+#define RCC_EP_DEV0_2_EP_PCIE_STRAP_MISC2__STRAP_TPH_SUPPORTED_MASK                                           0x00000010L
+//RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP
+#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT__SHIFT                                               0x8
+#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE__SHIFT                                              0xc
+#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0__SHIFT                                              0x10
+#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1__SHIFT                                              0x18
+#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_UNIT_MASK                                                 0x00000300L
+#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__PWR_ALLOC_SCALE_MASK                                                0x00003000L
+#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_0_MASK                                                0x00FF0000L
+#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CAP__TRANS_LAT_VAL_1_MASK                                                0xFF000000L
+//RCC_EP_DEV0_2_EP_PCIE_F0_DPA_LATENCY_INDICATOR
+#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS__SHIFT                       0x0
+#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_LATENCY_INDICATOR__TRANS_LAT_INDICATOR_BITS_MASK                         0xFFL
+//RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL
+#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS__SHIFT                                             0x0
+#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE__SHIFT                                         0x8
+#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL__SUBSTATE_STATUS_MASK                                               0x001FL
+#define RCC_EP_DEV0_2_EP_PCIE_F0_DPA_CNTL__DPA_COMPLIANCE_MODE_MASK                                           0x0100L
+//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0
+#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_0__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1
+#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_1__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2
+#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_2__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3
+#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_3__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4
+#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_4__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5
+#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_5__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6
+#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_6__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7
+#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC__SHIFT                             0x0
+#define RCC_EP_DEV0_2_PCIE_F0_DPA_SUBSTATE_PWR_ALLOC_7__SUBSTATE_PWR_ALLOC_MASK                               0xFFL
+//RCC_EP_DEV0_2_EP_PCIE_PME_CONTROL
+#define RCC_EP_DEV0_2_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER__SHIFT                                           0x0
+#define RCC_EP_DEV0_2_EP_PCIE_PME_CONTROL__PME_SERVICE_TIMER_MASK                                             0x1FL
+//RCC_EP_DEV0_2_EP_PCIEP_RESERVED
+#define RCC_EP_DEV0_2_EP_PCIEP_RESERVED__PCIEP_RESERVED__SHIFT                                                0x0
+#define RCC_EP_DEV0_2_EP_PCIEP_RESERVED__PCIEP_RESERVED_MASK                                                  0xFFFFFFFFL
+//RCC_EP_DEV0_2_EP_PCIE_TX_CNTL
+#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE__SHIFT                                                 0xa
+#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE__SHIFT                                                  0xc
+#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS__SHIFT                                                   0x18
+#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS__SHIFT                                                   0x19
+#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS__SHIFT                                                   0x1a
+#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_SNR_OVERRIDE_MASK                                                   0x00000C00L
+#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_RO_OVERRIDE_MASK                                                    0x00003000L
+#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F0_TPH_DIS_MASK                                                     0x01000000L
+#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F1_TPH_DIS_MASK                                                     0x02000000L
+#define RCC_EP_DEV0_2_EP_PCIE_TX_CNTL__TX_F2_TPH_DIS_MASK                                                     0x04000000L
+//RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID
+#define RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION__SHIFT                                0x0
+#define RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE__SHIFT                                  0x3
+#define RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS__SHIFT                                     0x8
+#define RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_FUNCTION_MASK                                  0x00000007L
+#define RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_DEVICE_MASK                                    0x000000F8L
+#define RCC_EP_DEV0_2_EP_PCIE_TX_REQUESTER_ID__TX_REQUESTER_ID_BUS_MASK                                       0x0000FF00L
+//RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS__SHIFT                                              0x0
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT__SHIFT                                            0x8
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY__SHIFT                                       0x11
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL__SHIFT                               0x12
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED__SHIFT                                   0x18
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED__SHIFT                                   0x19
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED__SHIFT                                   0x1a
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED__SHIFT                                   0x1b
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED__SHIFT                                   0x1c
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED__SHIFT                                   0x1d
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED__SHIFT                                   0x1e
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED__SHIFT                                   0x1f
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__ERR_REPORTING_DIS_MASK                                                0x00000001L
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_TIMEOUT_MASK                                              0x00000700L
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__SEND_ERR_MSG_IMMEDIATELY_MASK                                         0x00020000L
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__STRAP_POISONED_ADVISORY_NONFATAL_MASK                                 0x00040000L
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F0_TIMER_EXPIRED_MASK                                     0x01000000L
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F1_TIMER_EXPIRED_MASK                                     0x02000000L
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F2_TIMER_EXPIRED_MASK                                     0x04000000L
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F3_TIMER_EXPIRED_MASK                                     0x08000000L
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F4_TIMER_EXPIRED_MASK                                     0x10000000L
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F5_TIMER_EXPIRED_MASK                                     0x20000000L
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F6_TIMER_EXPIRED_MASK                                     0x40000000L
+#define RCC_EP_DEV0_2_EP_PCIE_ERR_CNTL__AER_HDR_LOG_F7_TIMER_EXPIRED_MASK                                     0x80000000L
+//RCC_EP_DEV0_2_EP_PCIE_RX_CNTL
+#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR__SHIFT                                       0x8
+#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR__SHIFT                                                0x9
+#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS__SHIFT                                         0x14
+#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR__SHIFT                                       0x15
+#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR__SHIFT                                         0x16
+#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR__SHIFT                                      0x18
+#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR__SHIFT                                          0x19
+#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_TPH_DIS__SHIFT                                                      0x1a
+#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_MAX_PAYLOAD_ERR_MASK                                         0x00000100L
+#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_TC_ERR_MASK                                                  0x00000200L
+#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_PCIE_CPL_TIMEOUT_DIS_MASK                                           0x00100000L
+#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_SHORTPREFIX_ERR_MASK                                         0x00200000L
+#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_MAXPREFIX_ERR_MASK                                           0x00400000L
+#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_INVALIDPASID_ERR_MASK                                        0x01000000L
+#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_IGNORE_NOT_PASID_UR_MASK                                            0x02000000L
+#define RCC_EP_DEV0_2_EP_PCIE_RX_CNTL__RX_TPH_DIS_MASK                                                        0x04000000L
+//RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL
+#define RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP__SHIFT                                          0x0
+#define RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP__SHIFT                                          0x1
+#define RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP__SHIFT                                          0x2
+#define RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP__SHIFT                                          0x3
+#define RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN6_EN_STRAP__SHIFT                                          0x4
+#define RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN2_EN_STRAP_MASK                                            0x00000001L
+#define RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN3_EN_STRAP_MASK                                            0x00000002L
+#define RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN4_EN_STRAP_MASK                                            0x00000004L
+#define RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN5_EN_STRAP_MASK                                            0x00000008L
+#define RCC_EP_DEV0_2_EP_PCIE_LC_SPEED_CNTL__LC_GEN6_EN_STRAP_MASK                                            0x00000010L
+//RCC_EP_DEV0_2_EP_PCIE_DEVICE_CNTL3
+#define RCC_EP_DEV0_2_EP_PCIE_DEVICE_CNTL3__SHADOW_F0_DEVICE_CNTL3_14BIT_TAG_REQUESTER_ENABLE__SHIFT          0x2
+#define RCC_EP_DEV0_2_EP_PCIE_DEVICE_CNTL3__SHADOW_F0_DEVICE_CNTL3_14BIT_TAG_REQUESTER_ENABLE_MASK            0x00000004L
+
+
+// addressBlock: nbif0_nbif0_rcc_dev0_BIFDEC1
+//RCC_DEV0_1_RCC_ERR_INT_CNTL
+#define RCC_DEV0_1_RCC_ERR_INT_CNTL__INVALID_REG_ACCESS_IN_SRIOV_INT_EN__SHIFT                                0x0
+#define RCC_DEV0_1_RCC_ERR_INT_CNTL__INVALID_REG_ACCESS_IN_SRIOV_INT_EN_MASK                                  0x00000001L
+//RCC_DEV0_1_RCC_BACO_CNTL_MISC
+#define RCC_DEV0_1_RCC_BACO_CNTL_MISC__BIF_ROM_REQ_DIS__SHIFT                                                 0x0
+#define RCC_DEV0_1_RCC_BACO_CNTL_MISC__BIF_AZ_REQ_DIS__SHIFT                                                  0x1
+#define RCC_DEV0_1_RCC_BACO_CNTL_MISC__BIF_ROM_REQ_DIS_MASK                                                   0x00000001L
+#define RCC_DEV0_1_RCC_BACO_CNTL_MISC__BIF_AZ_REQ_DIS_MASK                                                    0x00000002L
+//RCC_DEV0_1_RCC_RESET_EN
+#define RCC_DEV0_1_RCC_RESET_EN__DB_APER_RESET_EN__SHIFT                                                      0xf
+#define RCC_DEV0_1_RCC_RESET_EN__DB_APER_RESET_EN_MASK                                                        0x00008000L
+//RCC_DEV0_2_RCC_VDM_SUPPORT
+#define RCC_DEV0_2_RCC_VDM_SUPPORT__MCTP_SUPPORT__SHIFT                                                       0x0
+#define RCC_DEV0_2_RCC_VDM_SUPPORT__AMPTP_SUPPORT__SHIFT                                                      0x1
+#define RCC_DEV0_2_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT__SHIFT                                                  0x2
+#define RCC_DEV0_2_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE__SHIFT                                        0x3
+#define RCC_DEV0_2_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE__SHIFT                                    0x4
+#define RCC_DEV0_2_RCC_VDM_SUPPORT__MCTP_SUPPORT_MASK                                                         0x00000001L
+#define RCC_DEV0_2_RCC_VDM_SUPPORT__AMPTP_SUPPORT_MASK                                                        0x00000002L
+#define RCC_DEV0_2_RCC_VDM_SUPPORT__OTHER_VDM_SUPPORT_MASK                                                    0x00000004L
+#define RCC_DEV0_2_RCC_VDM_SUPPORT__ROUTE_TO_RC_CHECK_IN_RCMODE_MASK                                          0x00000008L
+#define RCC_DEV0_2_RCC_VDM_SUPPORT__ROUTE_BROADCAST_CHECK_IN_RCMODE_MASK                                      0x00000010L
+//RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED__SHIFT                                 0x0
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING__SHIFT                              0x1
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE__SHIFT                                0x2
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER__SHIFT                                 0x3
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD__SHIFT                           0x4
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS__SHIFT                                  0x5
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET__SHIFT                                 0xb
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS__SHIFT                                 0x12
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET__SHIFT                                0x19
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_VOLTAGE_SUPPORTED_MASK                                   0x00000001L
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_LEFTRIGHT_TIMING_MASK                                0x00000002L
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_UPDOWN_VOLTAGE_MASK                                  0x00000004L
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_IND_ERROR_SAMPLER_MASK                                   0x00000008L
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_SAMPLE_REPORTING_METHOD_MASK                             0x00000010L
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_TIMING_STEPS_MASK                                    0x000007E0L
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_TIMING_OFFSET_MASK                                   0x0003F800L
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_NUM_VOLTAGE_STEPS_MASK                                   0x01FC0000L
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL0__MARGINING_MAX_VOLTAGE_OFFSET_MASK                                  0xFE000000L
+//RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE__SHIFT                             0x0
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING__SHIFT                              0x6
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES__SHIFT                                         0xc
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT__SHIFT                                      0x11
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_VOLTAGE_MASK                               0x0000003FL
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLING_RATE_TIMING_MASK                                0x00000FC0L
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_MAX_LANES_MASK                                           0x0001F000L
+#define RCC_DEV0_2_RCC_MARGIN_PARAM_CNTL1__MARGINING_SAMPLE_COUNT_MASK                                        0x00FE0000L
+//RCC_DEV0_1_RCC_GPUIOV_REGION
+#define RCC_DEV0_1_RCC_GPUIOV_REGION__LFB_REGION__SHIFT                                                       0x0
+#define RCC_DEV0_1_RCC_GPUIOV_REGION__MAX_REGION__SHIFT                                                       0x4
+#define RCC_DEV0_1_RCC_GPUIOV_REGION__LFB_REGION_MASK                                                         0x0000000FL
+#define RCC_DEV0_1_RCC_GPUIOV_REGION__MAX_REGION_MASK                                                         0x000000F0L
+//RCC_DEV0_1_RCC_GPU_HOSTVM_EN
+#define RCC_DEV0_1_RCC_GPU_HOSTVM_EN__GPU_HOSTVM_EN__SHIFT                                                    0x0
+#define RCC_DEV0_1_RCC_GPU_HOSTVM_EN__GPU_HOSTVM_EN_MASK                                                      0x00000001L
+//RCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL
+#define RCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL__RCC_CONSOLE_IOV_MODE_ENABLE__SHIFT                              0x0
+#define RCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL__MULTIOS_IH_SUPPORT_EN__SHIFT                                    0x1
+#define RCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL__RCC_CONSOLE_IOV_MODE_ENABLE_MASK                                0x00000001L
+#define RCC_DEV0_1_RCC_CONSOLE_IOV_MODE_CNTL__MULTIOS_IH_SUPPORT_EN_MASK                                      0x00000002L
+//RCC_DEV0_1_RCC_CONSOLE_IOV_FIRST_VF_OFFSET
+#define RCC_DEV0_1_RCC_CONSOLE_IOV_FIRST_VF_OFFSET__CONSOLE_IOV_FIRST_VF_OFFSET__SHIFT                        0x0
+#define RCC_DEV0_1_RCC_CONSOLE_IOV_FIRST_VF_OFFSET__CONSOLE_IOV_FIRST_VF_OFFSET_MASK                          0xFFFFL
+//RCC_DEV0_1_RCC_CONSOLE_IOV_VF_STRIDE
+#define RCC_DEV0_1_RCC_CONSOLE_IOV_VF_STRIDE__CONSOLE_IOV_VF_STRIDE__SHIFT                                    0x0
+#define RCC_DEV0_1_RCC_CONSOLE_IOV_VF_STRIDE__CONSOLE_IOV_VF_STRIDE_MASK                                      0xFFFFL
+//RCC_DEV0_1_RCC_PEER_REG_RANGE0
+#define RCC_DEV0_1_RCC_PEER_REG_RANGE0__START_ADDR__SHIFT                                                     0x0
+#define RCC_DEV0_1_RCC_PEER_REG_RANGE0__END_ADDR__SHIFT                                                       0x10
+#define RCC_DEV0_1_RCC_PEER_REG_RANGE0__START_ADDR_MASK                                                       0x0000FFFFL
+#define RCC_DEV0_1_RCC_PEER_REG_RANGE0__END_ADDR_MASK                                                         0xFFFF0000L
+//RCC_DEV0_1_RCC_PEER_REG_RANGE1
+#define RCC_DEV0_1_RCC_PEER_REG_RANGE1__START_ADDR__SHIFT                                                     0x0
+#define RCC_DEV0_1_RCC_PEER_REG_RANGE1__END_ADDR__SHIFT                                                       0x10
+#define RCC_DEV0_1_RCC_PEER_REG_RANGE1__START_ADDR_MASK                                                       0x0000FFFFL
+#define RCC_DEV0_1_RCC_PEER_REG_RANGE1__END_ADDR_MASK                                                         0xFFFF0000L
+//RCC_DEV0_2_RCC_BUS_CNTL
+#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_IO_DIS__SHIFT                                                            0x2
+#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_MEM_DIS__SHIFT                                                           0x3
+#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_BM_DIS__SHIFT                                                            0x4
+#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_IO_DIS_DN__SHIFT                                                         0x5
+#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_MEM_DIS_DN__SHIFT                                                        0x6
+#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_IO_DIS_UP__SHIFT                                                         0x7
+#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_MEM_DIS_UP__SHIFT                                                        0x8
+#define RCC_DEV0_2_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT__SHIFT                                                 0xc
+#define RCC_DEV0_2_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC__SHIFT                                           0xd
+#define RCC_DEV0_2_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR__SHIFT                                          0x10
+#define RCC_DEV0_2_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR__SHIFT                                          0x11
+#define RCC_DEV0_2_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR__SHIFT                                          0x12
+#define RCC_DEV0_2_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR__SHIFT                                          0x13
+#define RCC_DEV0_2_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR__SHIFT                                          0x14
+#define RCC_DEV0_2_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR__SHIFT                                          0x15
+#define RCC_DEV0_2_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE__SHIFT                                                 0x18
+#define RCC_DEV0_2_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE__SHIFT                                                 0x19
+#define RCC_DEV0_2_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE__SHIFT                                            0x1c
+#define RCC_DEV0_2_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE__SHIFT                                            0x1d
+#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_IO_DIS_MASK                                                              0x00000004L
+#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_MEM_DIS_MASK                                                             0x00000008L
+#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_BM_DIS_MASK                                                              0x00000010L
+#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_IO_DIS_DN_MASK                                                           0x00000020L
+#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_MEM_DIS_DN_MASK                                                          0x00000040L
+#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_IO_DIS_UP_MASK                                                           0x00000080L
+#define RCC_DEV0_2_RCC_BUS_CNTL__PMI_MEM_DIS_UP_MASK                                                          0x00000100L
+#define RCC_DEV0_2_RCC_BUS_CNTL__ROOT_ERR_LOG_ON_EVENT_MASK                                                   0x00001000L
+#define RCC_DEV0_2_RCC_BUS_CNTL__HOST_CPL_POISONED_LOG_IN_RC_MASK                                             0x00002000L
+#define RCC_DEV0_2_RCC_BUS_CNTL__DN_SEC_SIG_CPLCA_WITH_EP_ERR_MASK                                            0x00010000L
+#define RCC_DEV0_2_RCC_BUS_CNTL__DN_SEC_RCV_CPLCA_WITH_EP_ERR_MASK                                            0x00020000L
+#define RCC_DEV0_2_RCC_BUS_CNTL__DN_SEC_RCV_CPLUR_WITH_EP_ERR_MASK                                            0x00040000L
+#define RCC_DEV0_2_RCC_BUS_CNTL__DN_PRI_SIG_CPLCA_WITH_EP_ERR_MASK                                            0x00080000L
+#define RCC_DEV0_2_RCC_BUS_CNTL__DN_PRI_RCV_CPLCA_WITH_EP_ERR_MASK                                            0x00100000L
+#define RCC_DEV0_2_RCC_BUS_CNTL__DN_PRI_RCV_CPLUR_WITH_EP_ERR_MASK                                            0x00200000L
+#define RCC_DEV0_2_RCC_BUS_CNTL__MAX_PAYLOAD_SIZE_MODE_MASK                                                   0x01000000L
+#define RCC_DEV0_2_RCC_BUS_CNTL__PRIV_MAX_PAYLOAD_SIZE_MASK                                                   0x0E000000L
+#define RCC_DEV0_2_RCC_BUS_CNTL__MAX_READ_REQUEST_SIZE_MODE_MASK                                              0x10000000L
+#define RCC_DEV0_2_RCC_BUS_CNTL__PRIV_MAX_READ_REQUEST_SIZE_MASK                                              0xE0000000L
+//RCC_DEV0_1_RCC_CONFIG_CNTL
+#define RCC_DEV0_1_RCC_CONFIG_CNTL__CFG_VGA_RAM_EN__SHIFT                                                     0x0
+#define RCC_DEV0_1_RCC_CONFIG_CNTL__GENMO_MONO_ADDRESS_B__SHIFT                                               0x2
+#define RCC_DEV0_1_RCC_CONFIG_CNTL__GRPH_ADRSEL__SHIFT                                                        0x3
+#define RCC_DEV0_1_RCC_CONFIG_CNTL__CFG_VGA_RAM_EN_MASK                                                       0x00000001L
+#define RCC_DEV0_1_RCC_CONFIG_CNTL__GENMO_MONO_ADDRESS_B_MASK                                                 0x00000004L
+#define RCC_DEV0_1_RCC_CONFIG_CNTL__GRPH_ADRSEL_MASK                                                          0x00000018L
+//RCC_DEV0_1_RCC_CONFIG_F0_BASE
+#define RCC_DEV0_1_RCC_CONFIG_F0_BASE__F0_BASE__SHIFT                                                         0x0
+#define RCC_DEV0_1_RCC_CONFIG_F0_BASE__F0_BASE_MASK                                                           0xFFFFFFFFL
+//RCC_DEV0_1_RCC_CONFIG_APER_SIZE
+#define RCC_DEV0_1_RCC_CONFIG_APER_SIZE__APER_SIZE__SHIFT                                                     0x0
+#define RCC_DEV0_1_RCC_CONFIG_APER_SIZE__APER_SIZE_MASK                                                       0xFFFFFFFFL
+//RCC_DEV0_1_RCC_CONFIG_REG_APER_SIZE
+#define RCC_DEV0_1_RCC_CONFIG_REG_APER_SIZE__REG_APER_SIZE__SHIFT                                             0x0
+#define RCC_DEV0_1_RCC_CONFIG_REG_APER_SIZE__REG_APER_SIZE_MASK                                               0x07FFFFFFL
+//RCC_DEV0_1_RCC_XDMA_LO
+#define RCC_DEV0_1_RCC_XDMA_LO__BIF_XDMA_LOWER_BOUND__SHIFT                                                   0x0
+#define RCC_DEV0_1_RCC_XDMA_LO__BIF_XDMA_APER_EN__SHIFT                                                       0x1f
+#define RCC_DEV0_1_RCC_XDMA_LO__BIF_XDMA_LOWER_BOUND_MASK                                                     0x7FFFFFFFL
+#define RCC_DEV0_1_RCC_XDMA_LO__BIF_XDMA_APER_EN_MASK                                                         0x80000000L
+//RCC_DEV0_1_RCC_XDMA_HI
+#define RCC_DEV0_1_RCC_XDMA_HI__BIF_XDMA_UPPER_BOUND__SHIFT                                                   0x0
+#define RCC_DEV0_1_RCC_XDMA_HI__BIF_XDMA_UPPER_BOUND_MASK                                                     0x7FFFFFFFL
+//RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS__SHIFT                                   0x7
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN__SHIFT                                 0x8
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR__SHIFT                                    0x9
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR__SHIFT                                    0xa
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR__SHIFT                                 0xb
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR__SHIFT                                  0xc
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR__SHIFT                                      0xd
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS__SHIFT                      0xe
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS__SHIFT                         0xf
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS__SHIFT                                 0x10
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS__SHIFT                           0x11
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN__SHIFT                               0x12
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS__SHIFT                     0x13
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__INIT_PFFLR_CRS_RET_DIS_MASK                                     0x00000080L
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__ATC_PRG_RESP_PASID_UR_EN_MASK                                   0x00000100L
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMRD_UR_MASK                                      0x00000200L
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_TRANSMWR_UR_MASK                                      0x00000400L
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_ATSTRANSREQ_UR_MASK                                   0x00000800L
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_PAGEREQMSG_UR_MASK                                    0x00001000L
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__RX_IGNORE_INVCPL_UR_MASK                                        0x00002000L
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__CLR_MSI_X_PENDING_WHEN_DISABLED_DIS_MASK                        0x00004000L
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__CHECK_BME_ON_PENDING_PKT_GEN_DIS_MASK                           0x00008000L
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__PSN_CHECK_ON_PAYLOAD_DIS_MASK                                   0x00010000L
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__CLR_MSI_PENDING_ON_MULTIEN_DIS_MASK                             0x00020000L
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__SET_DEVICE_ERR_FOR_ECRC_EN_MASK                                 0x00040000L
+#define RCC_DEV0_2_RCC_FEATURES_CONTROL_MISC__HOST_POISON_FLAG_CHECK_FOR_CHAIN_DIS_MASK                       0x00080000L
+//RCC_DEV0_1_RCC_BUSNUM_CNTL1
+#define RCC_DEV0_1_RCC_BUSNUM_CNTL1__ID_MASK__SHIFT                                                           0x0
+#define RCC_DEV0_1_RCC_BUSNUM_CNTL1__ID_MASK_MASK                                                             0x000000FFL
+//RCC_DEV0_1_RCC_BUSNUM_LIST0
+#define RCC_DEV0_1_RCC_BUSNUM_LIST0__ID0__SHIFT                                                               0x0
+#define RCC_DEV0_1_RCC_BUSNUM_LIST0__ID1__SHIFT                                                               0x8
+#define RCC_DEV0_1_RCC_BUSNUM_LIST0__ID2__SHIFT                                                               0x10
+#define RCC_DEV0_1_RCC_BUSNUM_LIST0__ID3__SHIFT                                                               0x18
+#define RCC_DEV0_1_RCC_BUSNUM_LIST0__ID0_MASK                                                                 0x000000FFL
+#define RCC_DEV0_1_RCC_BUSNUM_LIST0__ID1_MASK                                                                 0x0000FF00L
+#define RCC_DEV0_1_RCC_BUSNUM_LIST0__ID2_MASK                                                                 0x00FF0000L
+#define RCC_DEV0_1_RCC_BUSNUM_LIST0__ID3_MASK                                                                 0xFF000000L
+//RCC_DEV0_1_RCC_BUSNUM_LIST1
+#define RCC_DEV0_1_RCC_BUSNUM_LIST1__ID4__SHIFT                                                               0x0
+#define RCC_DEV0_1_RCC_BUSNUM_LIST1__ID5__SHIFT                                                               0x8
+#define RCC_DEV0_1_RCC_BUSNUM_LIST1__ID6__SHIFT                                                               0x10
+#define RCC_DEV0_1_RCC_BUSNUM_LIST1__ID7__SHIFT                                                               0x18
+#define RCC_DEV0_1_RCC_BUSNUM_LIST1__ID4_MASK                                                                 0x000000FFL
+#define RCC_DEV0_1_RCC_BUSNUM_LIST1__ID5_MASK                                                                 0x0000FF00L
+#define RCC_DEV0_1_RCC_BUSNUM_LIST1__ID6_MASK                                                                 0x00FF0000L
+#define RCC_DEV0_1_RCC_BUSNUM_LIST1__ID7_MASK                                                                 0xFF000000L
+//RCC_DEV0_1_RCC_BUSNUM_CNTL2
+#define RCC_DEV0_1_RCC_BUSNUM_CNTL2__AUTOUPDATE_SEL__SHIFT                                                    0x0
+#define RCC_DEV0_1_RCC_BUSNUM_CNTL2__AUTOUPDATE_EN__SHIFT                                                     0x8
+#define RCC_DEV0_1_RCC_BUSNUM_CNTL2__HDPREG_CNTL__SHIFT                                                       0x10
+#define RCC_DEV0_1_RCC_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH__SHIFT                                           0x11
+#define RCC_DEV0_1_RCC_BUSNUM_CNTL2__AUTOUPDATE_SEL_MASK                                                      0x000000FFL
+#define RCC_DEV0_1_RCC_BUSNUM_CNTL2__AUTOUPDATE_EN_MASK                                                       0x00000100L
+#define RCC_DEV0_1_RCC_BUSNUM_CNTL2__HDPREG_CNTL_MASK                                                         0x00010000L
+#define RCC_DEV0_1_RCC_BUSNUM_CNTL2__ERROR_MULTIPLE_ID_MATCH_MASK                                             0x00020000L
+//RCC_DEV0_1_RCC_CAPTURE_HOST_BUSNUM
+#define RCC_DEV0_1_RCC_CAPTURE_HOST_BUSNUM__CHECK_EN__SHIFT                                                   0x0
+#define RCC_DEV0_1_RCC_CAPTURE_HOST_BUSNUM__CHECK_EN_MASK                                                     0x00000001L
+//RCC_DEV0_1_RCC_HOST_BUSNUM
+#define RCC_DEV0_1_RCC_HOST_BUSNUM__HOST_ID__SHIFT                                                            0x0
+#define RCC_DEV0_1_RCC_HOST_BUSNUM__HOST_ID_MASK                                                              0x0000FFFFL
+//RCC_DEV0_1_RCC_PEER0_FB_OFFSET_HI
+#define RCC_DEV0_1_RCC_PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI__SHIFT                                          0x0
+#define RCC_DEV0_1_RCC_PEER0_FB_OFFSET_HI__PEER0_FB_OFFSET_HI_MASK                                            0x000FFFFFL
+//RCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO
+#define RCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO__SHIFT                                          0x0
+#define RCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_EN__SHIFT                                                 0x1f
+#define RCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_OFFSET_LO_MASK                                            0x000FFFFFL
+#define RCC_DEV0_1_RCC_PEER0_FB_OFFSET_LO__PEER0_FB_EN_MASK                                                   0x80000000L
+//RCC_DEV0_1_RCC_PEER1_FB_OFFSET_HI
+#define RCC_DEV0_1_RCC_PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI__SHIFT                                          0x0
+#define RCC_DEV0_1_RCC_PEER1_FB_OFFSET_HI__PEER1_FB_OFFSET_HI_MASK                                            0x000FFFFFL
+//RCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO
+#define RCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO__SHIFT                                          0x0
+#define RCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_EN__SHIFT                                                 0x1f
+#define RCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_OFFSET_LO_MASK                                            0x000FFFFFL
+#define RCC_DEV0_1_RCC_PEER1_FB_OFFSET_LO__PEER1_FB_EN_MASK                                                   0x80000000L
+//RCC_DEV0_1_RCC_PEER2_FB_OFFSET_HI
+#define RCC_DEV0_1_RCC_PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI__SHIFT                                          0x0
+#define RCC_DEV0_1_RCC_PEER2_FB_OFFSET_HI__PEER2_FB_OFFSET_HI_MASK                                            0x000FFFFFL
+//RCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO
+#define RCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO__SHIFT                                          0x0
+#define RCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_EN__SHIFT                                                 0x1f
+#define RCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_OFFSET_LO_MASK                                            0x000FFFFFL
+#define RCC_DEV0_1_RCC_PEER2_FB_OFFSET_LO__PEER2_FB_EN_MASK                                                   0x80000000L
+//RCC_DEV0_1_RCC_PEER3_FB_OFFSET_HI
+#define RCC_DEV0_1_RCC_PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI__SHIFT                                          0x0
+#define RCC_DEV0_1_RCC_PEER3_FB_OFFSET_HI__PEER3_FB_OFFSET_HI_MASK                                            0x000FFFFFL
+//RCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO
+#define RCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO__SHIFT                                          0x0
+#define RCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_EN__SHIFT                                                 0x1f
+#define RCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_OFFSET_LO_MASK                                            0x000FFFFFL
+#define RCC_DEV0_1_RCC_PEER3_FB_OFFSET_LO__PEER3_FB_EN_MASK                                                   0x80000000L
+//RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0
+#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID0__SHIFT                                                   0x0
+#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID1__SHIFT                                                   0x8
+#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID2__SHIFT                                                   0x10
+#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID3__SHIFT                                                   0x18
+#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID0_MASK                                                     0x000000FFL
+#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID1_MASK                                                     0x0000FF00L
+#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID2_MASK                                                     0x00FF0000L
+#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST0__DEVFUNC_ID3_MASK                                                     0xFF000000L
+//RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1
+#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID4__SHIFT                                                   0x0
+#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID5__SHIFT                                                   0x8
+#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID6__SHIFT                                                   0x10
+#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID7__SHIFT                                                   0x18
+#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID4_MASK                                                     0x000000FFL
+#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID5_MASK                                                     0x0000FF00L
+#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID6_MASK                                                     0x00FF0000L
+#define RCC_DEV0_1_RCC_DEVFUNCNUM_LIST1__DEVFUNC_ID7_MASK                                                     0xFF000000L
+//RCC_DEV0_2_RCC_DEV0_LINK_CNTL
+#define RCC_DEV0_2_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT__SHIFT                                                  0x0
+#define RCC_DEV0_2_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY__SHIFT                                                 0x8
+#define RCC_DEV0_2_RCC_DEV0_LINK_CNTL__SWUS_SRB_RST_TLS_DIS__SHIFT                                            0x10
+#define RCC_DEV0_2_RCC_DEV0_LINK_CNTL__SWUS_LDN_RST_TLS_DIS__SHIFT                                            0x11
+#define RCC_DEV0_2_RCC_DEV0_LINK_CNTL__LINK_DOWN_EXIT_MASK                                                    0x00000001L
+#define RCC_DEV0_2_RCC_DEV0_LINK_CNTL__LINK_DOWN_ENTRY_MASK                                                   0x00000100L
+#define RCC_DEV0_2_RCC_DEV0_LINK_CNTL__SWUS_SRB_RST_TLS_DIS_MASK                                              0x00010000L
+#define RCC_DEV0_2_RCC_DEV0_LINK_CNTL__SWUS_LDN_RST_TLS_DIS_MASK                                              0x00020000L
+//RCC_DEV0_2_RCC_CMN_LINK_CNTL
+#define RCC_DEV0_2_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS__SHIFT                                             0x0
+#define RCC_DEV0_2_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS__SHIFT                                              0x1
+#define RCC_DEV0_2_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS__SHIFT                                             0x2
+#define RCC_DEV0_2_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN__SHIFT                                          0x3
+#define RCC_DEV0_2_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER__SHIFT                                             0x10
+#define RCC_DEV0_2_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L0S_DIS_MASK                                               0x00000001L
+#define RCC_DEV0_2_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_L1_DIS_MASK                                                0x00000002L
+#define RCC_DEV0_2_RCC_CMN_LINK_CNTL__BLOCK_PME_ON_LDN_DIS_MASK                                               0x00000004L
+#define RCC_DEV0_2_RCC_CMN_LINK_CNTL__PM_L1_IDLE_CHECK_DMA_EN_MASK                                            0x00000008L
+#define RCC_DEV0_2_RCC_CMN_LINK_CNTL__VLINK_IN_L1LTR_TIMER_MASK                                               0xFFFF0000L
+//RCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE
+#define RCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS__SHIFT                                            0x0
+#define RCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV__SHIFT                                            0x8
+#define RCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE__EP_REQID_SEG__SHIFT                                            0x10
+#define RCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE__EP_REQID_BUS_MASK                                              0x000000FFL
+#define RCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE__EP_REQID_DEV_MASK                                              0x00001F00L
+#define RCC_DEV0_2_RCC_EP_REQUESTERID_RESTORE__EP_REQID_SEG_MASK                                              0x00FF0000L
+//RCC_DEV0_2_RCC_LTR_LSWITCH_CNTL
+#define RCC_DEV0_2_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE__SHIFT                                         0x0
+#define RCC_DEV0_2_RCC_LTR_LSWITCH_CNTL__LSWITCH_LATENCY_VALUE_MASK                                           0x000003FFL
+//RCC_DEV0_2_RCC_MH_ARB_CNTL
+#define RCC_DEV0_2_RCC_MH_ARB_CNTL__MH_ARB_MODE__SHIFT                                                        0x0
+#define RCC_DEV0_2_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY__SHIFT                                                0x1
+#define RCC_DEV0_2_RCC_MH_ARB_CNTL__MH_ARB_MODE_MASK                                                          0x00000001L
+#define RCC_DEV0_2_RCC_MH_ARB_CNTL__MH_ARB_FIX_PRIORITY_MASK                                                  0x0000FFFEL
+
+
+// addressBlock: nbif0_nbif0_bif_bx_SYSDEC
+//BIF_BX1_SYSHUB_INDEX_OVLP
+#define BIF_BX1_SYSHUB_INDEX_OVLP__SYSHUB_OFFSET__SHIFT                                                       0x0
+#define BIF_BX1_SYSHUB_INDEX_OVLP__SYSHUB_OFFSET_MASK                                                         0x003FFFFFL
+//BIF_BX1_SYSHUB_DATA_OVLP
+#define BIF_BX1_SYSHUB_DATA_OVLP__SYSHUB_DATA__SHIFT                                                          0x0
+#define BIF_BX1_SYSHUB_DATA_OVLP__SYSHUB_DATA_MASK                                                            0xFFFFFFFFL
+//BIF_BX1_SYSHUB_INDEX_HI_OVLP
+#define BIF_BX1_SYSHUB_INDEX_HI_OVLP__SYSHUB_OFFSET_HI__SHIFT                                                 0x0
+#define BIF_BX1_SYSHUB_INDEX_HI_OVLP__SYSHUB_OFFSET_HI_MASK                                                   0x0000FFFFL
+//BIF_BX1_PCIE_INDEX
+#define BIF_BX1_PCIE_INDEX__PCIE_INDEX__SHIFT                                                                 0x0
+#define BIF_BX1_PCIE_INDEX__PCIE_INDEX_MASK                                                                   0xFFFFFFFFL
+//BIF_BX1_PCIE_DATA
+#define BIF_BX1_PCIE_DATA__PCIE_DATA__SHIFT                                                                   0x0
+#define BIF_BX1_PCIE_DATA__PCIE_DATA_MASK                                                                     0xFFFFFFFFL
+//BIF_BX1_PCIE_INDEX2
+#define BIF_BX1_PCIE_INDEX2__PCIE_INDEX2__SHIFT                                                               0x0
+#define BIF_BX1_PCIE_INDEX2__PCIE_INDEX2_MASK                                                                 0xFFFFFFFFL
+//BIF_BX1_PCIE_DATA2
+#define BIF_BX1_PCIE_DATA2__PCIE_DATA2__SHIFT                                                                 0x0
+#define BIF_BX1_PCIE_DATA2__PCIE_DATA2_MASK                                                                   0xFFFFFFFFL
+//BIF_BX1_PCIE_INDEX_HI
+#define BIF_BX1_PCIE_INDEX_HI__PCIE_INDEX_HI__SHIFT                                                           0x0
+#define BIF_BX1_PCIE_INDEX_HI__PCIE_INDEX_HI_MASK                                                             0x0000FFFFL
+//BIF_BX1_PCIE_INDEX2_HI
+#define BIF_BX1_PCIE_INDEX2_HI__PCIE_INDEX2_HI__SHIFT                                                         0x0
+#define BIF_BX1_PCIE_INDEX2_HI__PCIE_INDEX2_HI_MASK                                                           0x0000FFFFL
+//BIF_BX1_SBIOS_SCRATCH_0
+#define BIF_BX1_SBIOS_SCRATCH_0__SBIOS_SCRATCH_0__SHIFT                                                       0x0
+#define BIF_BX1_SBIOS_SCRATCH_0__SBIOS_SCRATCH_0_MASK                                                         0xFFFFFFFFL
+//BIF_BX1_SBIOS_SCRATCH_1
+#define BIF_BX1_SBIOS_SCRATCH_1__SBIOS_SCRATCH_1__SHIFT                                                       0x0
+#define BIF_BX1_SBIOS_SCRATCH_1__SBIOS_SCRATCH_1_MASK                                                         0xFFFFFFFFL
+//BIF_BX1_SBIOS_SCRATCH_2
+#define BIF_BX1_SBIOS_SCRATCH_2__SBIOS_SCRATCH_2__SHIFT                                                       0x0
+#define BIF_BX1_SBIOS_SCRATCH_2__SBIOS_SCRATCH_2_MASK                                                         0xFFFFFFFFL
+//BIF_BX1_SBIOS_SCRATCH_3
+#define BIF_BX1_SBIOS_SCRATCH_3__SBIOS_SCRATCH_3__SHIFT                                                       0x0
+#define BIF_BX1_SBIOS_SCRATCH_3__SBIOS_SCRATCH_3_MASK                                                         0xFFFFFFFFL
+//BIF_BX1_BIOS_SCRATCH_0
+#define BIF_BX1_BIOS_SCRATCH_0__BIOS_SCRATCH_0__SHIFT                                                         0x0
+#define BIF_BX1_BIOS_SCRATCH_0__BIOS_SCRATCH_0_MASK                                                           0xFFFFFFFFL
+//BIF_BX1_BIOS_SCRATCH_1
+#define BIF_BX1_BIOS_SCRATCH_1__BIOS_SCRATCH_1__SHIFT                                                         0x0
+#define BIF_BX1_BIOS_SCRATCH_1__BIOS_SCRATCH_1_MASK                                                           0xFFFFFFFFL
+//BIF_BX1_BIOS_SCRATCH_2
+#define BIF_BX1_BIOS_SCRATCH_2__BIOS_SCRATCH_2__SHIFT                                                         0x0
+#define BIF_BX1_BIOS_SCRATCH_2__BIOS_SCRATCH_2_MASK                                                           0xFFFFFFFFL
+//BIF_BX1_BIOS_SCRATCH_3
+#define BIF_BX1_BIOS_SCRATCH_3__BIOS_SCRATCH_3__SHIFT                                                         0x0
+#define BIF_BX1_BIOS_SCRATCH_3__BIOS_SCRATCH_3_MASK                                                           0xFFFFFFFFL
+//BIF_BX1_BIOS_SCRATCH_4
+#define BIF_BX1_BIOS_SCRATCH_4__BIOS_SCRATCH_4__SHIFT                                                         0x0
+#define BIF_BX1_BIOS_SCRATCH_4__BIOS_SCRATCH_4_MASK                                                           0xFFFFFFFFL
+//BIF_BX1_BIOS_SCRATCH_5
+#define BIF_BX1_BIOS_SCRATCH_5__BIOS_SCRATCH_5__SHIFT                                                         0x0
+#define BIF_BX1_BIOS_SCRATCH_5__BIOS_SCRATCH_5_MASK                                                           0xFFFFFFFFL
+//BIF_BX1_BIOS_SCRATCH_6
+#define BIF_BX1_BIOS_SCRATCH_6__BIOS_SCRATCH_6__SHIFT                                                         0x0
+#define BIF_BX1_BIOS_SCRATCH_6__BIOS_SCRATCH_6_MASK                                                           0xFFFFFFFFL
+//BIF_BX1_BIOS_SCRATCH_7
+#define BIF_BX1_BIOS_SCRATCH_7__BIOS_SCRATCH_7__SHIFT                                                         0x0
+#define BIF_BX1_BIOS_SCRATCH_7__BIOS_SCRATCH_7_MASK                                                           0xFFFFFFFFL
+//BIF_BX1_BIOS_SCRATCH_8
+#define BIF_BX1_BIOS_SCRATCH_8__BIOS_SCRATCH_8__SHIFT                                                         0x0
+#define BIF_BX1_BIOS_SCRATCH_8__BIOS_SCRATCH_8_MASK                                                           0xFFFFFFFFL
+//BIF_BX1_BIOS_SCRATCH_9
+#define BIF_BX1_BIOS_SCRATCH_9__BIOS_SCRATCH_9__SHIFT                                                         0x0
+#define BIF_BX1_BIOS_SCRATCH_9__BIOS_SCRATCH_9_MASK                                                           0xFFFFFFFFL
+//BIF_BX1_BIOS_SCRATCH_10
+#define BIF_BX1_BIOS_SCRATCH_10__BIOS_SCRATCH_10__SHIFT                                                       0x0
+#define BIF_BX1_BIOS_SCRATCH_10__BIOS_SCRATCH_10_MASK                                                         0xFFFFFFFFL
+//BIF_BX1_BIOS_SCRATCH_11
+#define BIF_BX1_BIOS_SCRATCH_11__BIOS_SCRATCH_11__SHIFT                                                       0x0
+#define BIF_BX1_BIOS_SCRATCH_11__BIOS_SCRATCH_11_MASK                                                         0xFFFFFFFFL
+//BIF_BX1_BIOS_SCRATCH_12
+#define BIF_BX1_BIOS_SCRATCH_12__BIOS_SCRATCH_12__SHIFT                                                       0x0
+#define BIF_BX1_BIOS_SCRATCH_12__BIOS_SCRATCH_12_MASK                                                         0xFFFFFFFFL
+//BIF_BX1_BIOS_SCRATCH_13
+#define BIF_BX1_BIOS_SCRATCH_13__BIOS_SCRATCH_13__SHIFT                                                       0x0
+#define BIF_BX1_BIOS_SCRATCH_13__BIOS_SCRATCH_13_MASK                                                         0xFFFFFFFFL
+//BIF_BX1_BIOS_SCRATCH_14
+#define BIF_BX1_BIOS_SCRATCH_14__BIOS_SCRATCH_14__SHIFT                                                       0x0
+#define BIF_BX1_BIOS_SCRATCH_14__BIOS_SCRATCH_14_MASK                                                         0xFFFFFFFFL
+//BIF_BX1_BIOS_SCRATCH_15
+#define BIF_BX1_BIOS_SCRATCH_15__BIOS_SCRATCH_15__SHIFT                                                       0x0
+#define BIF_BX1_BIOS_SCRATCH_15__BIOS_SCRATCH_15_MASK                                                         0xFFFFFFFFL
+//BIF_BX1_BIF_RLC_INTR_CNTL
+//BIF_BX1_BIF_VCE_INTR_CNTL
+//BIF_BX1_BIF_UVD_INTR_CNTL
+//BIF_BX1_BIF_Engine_INTR_CNTL
+#define BIF_BX1_BIF_Engine_INTR_CNTL__Engine_CMD_COMPLETE__SHIFT                                              0x0
+#define BIF_BX1_BIF_Engine_INTR_CNTL__Engine_HANG_SELF_RECOVERED__SHIFT                                       0x1
+#define BIF_BX1_BIF_Engine_INTR_CNTL__Engine_HANG_NEED_FLR__SHIFT                                             0x2
+#define BIF_BX1_BIF_Engine_INTR_CNTL__Engine_VM_BUSY_TRANSITION__SHIFT                                        0x3
+#define BIF_BX1_BIF_Engine_INTR_CNTL__Engine_INST_SEL__SHIFT                                                  0x1b
+#define BIF_BX1_BIF_Engine_INTR_CNTL__Engine_CMD_COMPLETE_MASK                                                0x00000001L
+#define BIF_BX1_BIF_Engine_INTR_CNTL__Engine_HANG_SELF_RECOVERED_MASK                                         0x00000002L
+#define BIF_BX1_BIF_Engine_INTR_CNTL__Engine_HANG_NEED_FLR_MASK                                               0x00000004L
+#define BIF_BX1_BIF_Engine_INTR_CNTL__Engine_VM_BUSY_TRANSITION_MASK                                          0x00000008L
+#define BIF_BX1_BIF_Engine_INTR_CNTL__Engine_INST_SEL_MASK                                                    0xF8000000L
+//BIF_BX1_GFX_MMIOREG_CAM_ADDR0
+#define BIF_BX1_GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0__SHIFT                                                       0x0
+#define BIF_BX1_GFX_MMIOREG_CAM_ADDR0__CAM_ADDR0_MASK                                                         0x000FFFFFL
+//BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR0
+#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0__SHIFT                                           0x0
+#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR0__CAM_REMAP_ADDR0_MASK                                             0x000FFFFFL
+//BIF_BX1_GFX_MMIOREG_CAM_ADDR1
+#define BIF_BX1_GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1__SHIFT                                                       0x0
+#define BIF_BX1_GFX_MMIOREG_CAM_ADDR1__CAM_ADDR1_MASK                                                         0x000FFFFFL
+//BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR1
+#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1__SHIFT                                           0x0
+#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR1__CAM_REMAP_ADDR1_MASK                                             0x000FFFFFL
+//BIF_BX1_GFX_MMIOREG_CAM_ADDR2
+#define BIF_BX1_GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2__SHIFT                                                       0x0
+#define BIF_BX1_GFX_MMIOREG_CAM_ADDR2__CAM_ADDR2_MASK                                                         0x000FFFFFL
+//BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR2
+#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2__SHIFT                                           0x0
+#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR2__CAM_REMAP_ADDR2_MASK                                             0x000FFFFFL
+//BIF_BX1_GFX_MMIOREG_CAM_ADDR3
+#define BIF_BX1_GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3__SHIFT                                                       0x0
+#define BIF_BX1_GFX_MMIOREG_CAM_ADDR3__CAM_ADDR3_MASK                                                         0x000FFFFFL
+//BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR3
+#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3__SHIFT                                           0x0
+#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR3__CAM_REMAP_ADDR3_MASK                                             0x000FFFFFL
+//BIF_BX1_GFX_MMIOREG_CAM_ADDR4
+#define BIF_BX1_GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4__SHIFT                                                       0x0
+#define BIF_BX1_GFX_MMIOREG_CAM_ADDR4__CAM_ADDR4_MASK                                                         0x000FFFFFL
+//BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR4
+#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4__SHIFT                                           0x0
+#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR4__CAM_REMAP_ADDR4_MASK                                             0x000FFFFFL
+//BIF_BX1_GFX_MMIOREG_CAM_ADDR5
+#define BIF_BX1_GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5__SHIFT                                                       0x0
+#define BIF_BX1_GFX_MMIOREG_CAM_ADDR5__CAM_ADDR5_MASK                                                         0x000FFFFFL
+//BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR5
+#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5__SHIFT                                           0x0
+#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR5__CAM_REMAP_ADDR5_MASK                                             0x000FFFFFL
+//BIF_BX1_GFX_MMIOREG_CAM_ADDR6
+#define BIF_BX1_GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6__SHIFT                                                       0x0
+#define BIF_BX1_GFX_MMIOREG_CAM_ADDR6__CAM_ADDR6_MASK                                                         0x000FFFFFL
+//BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR6
+#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6__SHIFT                                           0x0
+#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR6__CAM_REMAP_ADDR6_MASK                                             0x000FFFFFL
+//BIF_BX1_GFX_MMIOREG_CAM_ADDR7
+#define BIF_BX1_GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7__SHIFT                                                       0x0
+#define BIF_BX1_GFX_MMIOREG_CAM_ADDR7__CAM_ADDR7_MASK                                                         0x000FFFFFL
+//BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR7
+#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7__SHIFT                                           0x0
+#define BIF_BX1_GFX_MMIOREG_CAM_REMAP_ADDR7__CAM_REMAP_ADDR7_MASK                                             0x000FFFFFL
+//BIF_BX1_GFX_MMIOREG_CAM_CNTL
+#define BIF_BX1_GFX_MMIOREG_CAM_CNTL__CAM_ENABLE__SHIFT                                                       0x0
+#define BIF_BX1_GFX_MMIOREG_CAM_CNTL__CAM_ENABLE_MASK                                                         0x000000FFL
+//BIF_BX1_GFX_MMIOREG_CAM_ZERO_CPL
+#define BIF_BX1_GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL__SHIFT                                                 0x0
+#define BIF_BX1_GFX_MMIOREG_CAM_ZERO_CPL__CAM_ZERO_CPL_MASK                                                   0xFFFFFFFFL
+//BIF_BX1_GFX_MMIOREG_CAM_ONE_CPL
+#define BIF_BX1_GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL__SHIFT                                                   0x0
+#define BIF_BX1_GFX_MMIOREG_CAM_ONE_CPL__CAM_ONE_CPL_MASK                                                     0xFFFFFFFFL
+//BIF_BX1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL
+#define BIF_BX1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL__SHIFT                                 0x0
+#define BIF_BX1_GFX_MMIOREG_CAM_PROGRAMMABLE_CPL__CAM_PROGRAMMABLE_CPL_MASK                                   0xFFFFFFFFL
+//BIF_BX1_DRIVER_SCRATCH_0
+#define BIF_BX1_DRIVER_SCRATCH_0__DRIVER_SCRATCH_0__SHIFT                                                     0x0
+#define BIF_BX1_DRIVER_SCRATCH_0__DRIVER_SCRATCH_0_MASK                                                       0xFFFFFFFFL
+//BIF_BX1_DRIVER_SCRATCH_1
+#define BIF_BX1_DRIVER_SCRATCH_1__DRIVER_SCRATCH_1__SHIFT                                                     0x0
+#define BIF_BX1_DRIVER_SCRATCH_1__DRIVER_SCRATCH_1_MASK                                                       0xFFFFFFFFL
+//BIF_BX1_DRIVER_SCRATCH_2
+#define BIF_BX1_DRIVER_SCRATCH_2__DRIVER_SCRATCH_2__SHIFT                                                     0x0
+#define BIF_BX1_DRIVER_SCRATCH_2__DRIVER_SCRATCH_2_MASK                                                       0xFFFFFFFFL
+//BIF_BX1_DRIVER_SCRATCH_3
+#define BIF_BX1_DRIVER_SCRATCH_3__DRIVER_SCRATCH_3__SHIFT                                                     0x0
+#define BIF_BX1_DRIVER_SCRATCH_3__DRIVER_SCRATCH_3_MASK                                                       0xFFFFFFFFL
+//BIF_BX1_DRIVER_SCRATCH_4
+#define BIF_BX1_DRIVER_SCRATCH_4__DRIVER_SCRATCH_4__SHIFT                                                     0x0
+#define BIF_BX1_DRIVER_SCRATCH_4__DRIVER_SCRATCH_4_MASK                                                       0xFFFFFFFFL
+//BIF_BX1_DRIVER_SCRATCH_5
+#define BIF_BX1_DRIVER_SCRATCH_5__DRIVER_SCRATCH_5__SHIFT                                                     0x0
+#define BIF_BX1_DRIVER_SCRATCH_5__DRIVER_SCRATCH_5_MASK                                                       0xFFFFFFFFL
+//BIF_BX1_DRIVER_SCRATCH_6
+#define BIF_BX1_DRIVER_SCRATCH_6__DRIVER_SCRATCH_6__SHIFT                                                     0x0
+#define BIF_BX1_DRIVER_SCRATCH_6__DRIVER_SCRATCH_6_MASK                                                       0xFFFFFFFFL
+//BIF_BX1_DRIVER_SCRATCH_7
+#define BIF_BX1_DRIVER_SCRATCH_7__DRIVER_SCRATCH_7__SHIFT                                                     0x0
+#define BIF_BX1_DRIVER_SCRATCH_7__DRIVER_SCRATCH_7_MASK                                                       0xFFFFFFFFL
+//BIF_BX1_DRIVER_SCRATCH_8
+#define BIF_BX1_DRIVER_SCRATCH_8__DRIVER_SCRATCH_8__SHIFT                                                     0x0
+#define BIF_BX1_DRIVER_SCRATCH_8__DRIVER_SCRATCH_8_MASK                                                       0xFFFFFFFFL
+//BIF_BX1_DRIVER_SCRATCH_9
+#define BIF_BX1_DRIVER_SCRATCH_9__DRIVER_SCRATCH_9__SHIFT                                                     0x0
+#define BIF_BX1_DRIVER_SCRATCH_9__DRIVER_SCRATCH_9_MASK                                                       0xFFFFFFFFL
+//BIF_BX1_DRIVER_SCRATCH_10
+#define BIF_BX1_DRIVER_SCRATCH_10__DRIVER_SCRATCH_10__SHIFT                                                   0x0
+#define BIF_BX1_DRIVER_SCRATCH_10__DRIVER_SCRATCH_10_MASK                                                     0xFFFFFFFFL
+//BIF_BX1_DRIVER_SCRATCH_11
+#define BIF_BX1_DRIVER_SCRATCH_11__DRIVER_SCRATCH_11__SHIFT                                                   0x0
+#define BIF_BX1_DRIVER_SCRATCH_11__DRIVER_SCRATCH_11_MASK                                                     0xFFFFFFFFL
+//BIF_BX1_DRIVER_SCRATCH_12
+#define BIF_BX1_DRIVER_SCRATCH_12__DRIVER_SCRATCH_12__SHIFT                                                   0x0
+#define BIF_BX1_DRIVER_SCRATCH_12__DRIVER_SCRATCH_12_MASK                                                     0xFFFFFFFFL
+//BIF_BX1_DRIVER_SCRATCH_13
+#define BIF_BX1_DRIVER_SCRATCH_13__DRIVER_SCRATCH_13__SHIFT                                                   0x0
+#define BIF_BX1_DRIVER_SCRATCH_13__DRIVER_SCRATCH_13_MASK                                                     0xFFFFFFFFL
+//BIF_BX1_DRIVER_SCRATCH_14
+#define BIF_BX1_DRIVER_SCRATCH_14__DRIVER_SCRATCH_14__SHIFT                                                   0x0
+#define BIF_BX1_DRIVER_SCRATCH_14__DRIVER_SCRATCH_14_MASK                                                     0xFFFFFFFFL
+//BIF_BX1_DRIVER_SCRATCH_15
+#define BIF_BX1_DRIVER_SCRATCH_15__DRIVER_SCRATCH_15__SHIFT                                                   0x0
+#define BIF_BX1_DRIVER_SCRATCH_15__DRIVER_SCRATCH_15_MASK                                                     0xFFFFFFFFL
+//BIF_BX1_FW_SCRATCH_0
+#define BIF_BX1_FW_SCRATCH_0__FW_SCRATCH_0__SHIFT                                                             0x0
+#define BIF_BX1_FW_SCRATCH_0__FW_SCRATCH_0_MASK                                                               0xFFFFFFFFL
+//BIF_BX1_FW_SCRATCH_1
+#define BIF_BX1_FW_SCRATCH_1__FW_SCRATCH_1__SHIFT                                                             0x0
+#define BIF_BX1_FW_SCRATCH_1__FW_SCRATCH_1_MASK                                                               0xFFFFFFFFL
+//BIF_BX1_FW_SCRATCH_2
+#define BIF_BX1_FW_SCRATCH_2__FW_SCRATCH_2__SHIFT                                                             0x0
+#define BIF_BX1_FW_SCRATCH_2__FW_SCRATCH_2_MASK                                                               0xFFFFFFFFL
+//BIF_BX1_FW_SCRATCH_3
+#define BIF_BX1_FW_SCRATCH_3__FW_SCRATCH_3__SHIFT                                                             0x0
+#define BIF_BX1_FW_SCRATCH_3__FW_SCRATCH_3_MASK                                                               0xFFFFFFFFL
+//BIF_BX1_FW_SCRATCH_4
+#define BIF_BX1_FW_SCRATCH_4__FW_SCRATCH_4__SHIFT                                                             0x0
+#define BIF_BX1_FW_SCRATCH_4__FW_SCRATCH_4_MASK                                                               0xFFFFFFFFL
+//BIF_BX1_FW_SCRATCH_5
+#define BIF_BX1_FW_SCRATCH_5__FW_SCRATCH_5__SHIFT                                                             0x0
+#define BIF_BX1_FW_SCRATCH_5__FW_SCRATCH_5_MASK                                                               0xFFFFFFFFL
+//BIF_BX1_FW_SCRATCH_6
+#define BIF_BX1_FW_SCRATCH_6__FW_SCRATCH_6__SHIFT                                                             0x0
+#define BIF_BX1_FW_SCRATCH_6__FW_SCRATCH_6_MASK                                                               0xFFFFFFFFL
+//BIF_BX1_FW_SCRATCH_7
+#define BIF_BX1_FW_SCRATCH_7__FW_SCRATCH_7__SHIFT                                                             0x0
+#define BIF_BX1_FW_SCRATCH_7__FW_SCRATCH_7_MASK                                                               0xFFFFFFFFL
+//BIF_BX1_FW_SCRATCH_8
+#define BIF_BX1_FW_SCRATCH_8__FW_SCRATCH_8__SHIFT                                                             0x0
+#define BIF_BX1_FW_SCRATCH_8__FW_SCRATCH_8_MASK                                                               0xFFFFFFFFL
+//BIF_BX1_FW_SCRATCH_9
+#define BIF_BX1_FW_SCRATCH_9__FW_SCRATCH_9__SHIFT                                                             0x0
+#define BIF_BX1_FW_SCRATCH_9__FW_SCRATCH_9_MASK                                                               0xFFFFFFFFL
+//BIF_BX1_FW_SCRATCH_10
+#define BIF_BX1_FW_SCRATCH_10__FW_SCRATCH_10__SHIFT                                                           0x0
+#define BIF_BX1_FW_SCRATCH_10__FW_SCRATCH_10_MASK                                                             0xFFFFFFFFL
+//BIF_BX1_FW_SCRATCH_11
+#define BIF_BX1_FW_SCRATCH_11__FW_SCRATCH_11__SHIFT                                                           0x0
+#define BIF_BX1_FW_SCRATCH_11__FW_SCRATCH_11_MASK                                                             0xFFFFFFFFL
+//BIF_BX1_FW_SCRATCH_12
+#define BIF_BX1_FW_SCRATCH_12__FW_SCRATCH_12__SHIFT                                                           0x0
+#define BIF_BX1_FW_SCRATCH_12__FW_SCRATCH_12_MASK                                                             0xFFFFFFFFL
+//BIF_BX1_FW_SCRATCH_13
+#define BIF_BX1_FW_SCRATCH_13__FW_SCRATCH_13__SHIFT                                                           0x0
+#define BIF_BX1_FW_SCRATCH_13__FW_SCRATCH_13_MASK                                                             0xFFFFFFFFL
+//BIF_BX1_FW_SCRATCH_14
+#define BIF_BX1_FW_SCRATCH_14__FW_SCRATCH_14__SHIFT                                                           0x0
+#define BIF_BX1_FW_SCRATCH_14__FW_SCRATCH_14_MASK                                                             0xFFFFFFFFL
+//BIF_BX1_FW_SCRATCH_15
+#define BIF_BX1_FW_SCRATCH_15__FW_SCRATCH_15__SHIFT                                                           0x0
+#define BIF_BX1_FW_SCRATCH_15__FW_SCRATCH_15_MASK                                                             0xFFFFFFFFL
+//BIF_BX1_SBIOS_SCRATCH_4
+#define BIF_BX1_SBIOS_SCRATCH_4__SBIOS_SCRATCH_4__SHIFT                                                       0x0
+#define BIF_BX1_SBIOS_SCRATCH_4__SBIOS_SCRATCH_4_MASK                                                         0xFFFFFFFFL
+//BIF_BX1_SBIOS_SCRATCH_5
+#define BIF_BX1_SBIOS_SCRATCH_5__SBIOS_SCRATCH_5__SHIFT                                                       0x0
+#define BIF_BX1_SBIOS_SCRATCH_5__SBIOS_SCRATCH_5_MASK                                                         0xFFFFFFFFL
+//BIF_BX1_SBIOS_SCRATCH_6
+#define BIF_BX1_SBIOS_SCRATCH_6__SBIOS_SCRATCH_6__SHIFT                                                       0x0
+#define BIF_BX1_SBIOS_SCRATCH_6__SBIOS_SCRATCH_6_MASK                                                         0xFFFFFFFFL
+//BIF_BX1_SBIOS_SCRATCH_7
+#define BIF_BX1_SBIOS_SCRATCH_7__SBIOS_SCRATCH_7__SHIFT                                                       0x0
+#define BIF_BX1_SBIOS_SCRATCH_7__SBIOS_SCRATCH_7_MASK                                                         0xFFFFFFFFL
+//BIF_BX1_SBIOS_SCRATCH_8
+#define BIF_BX1_SBIOS_SCRATCH_8__SBIOS_SCRATCH_8__SHIFT                                                       0x0
+#define BIF_BX1_SBIOS_SCRATCH_8__SBIOS_SCRATCH_8_MASK                                                         0xFFFFFFFFL
+//BIF_BX1_SBIOS_SCRATCH_9
+#define BIF_BX1_SBIOS_SCRATCH_9__SBIOS_SCRATCH_9__SHIFT                                                       0x0
+#define BIF_BX1_SBIOS_SCRATCH_9__SBIOS_SCRATCH_9_MASK                                                         0xFFFFFFFFL
+//BIF_BX1_SBIOS_SCRATCH_10
+#define BIF_BX1_SBIOS_SCRATCH_10__SBIOS_SCRATCH_10__SHIFT                                                     0x0
+#define BIF_BX1_SBIOS_SCRATCH_10__SBIOS_SCRATCH_10_MASK                                                       0xFFFFFFFFL
+//BIF_BX1_SBIOS_SCRATCH_11
+#define BIF_BX1_SBIOS_SCRATCH_11__SBIOS_SCRATCH_11__SHIFT                                                     0x0
+#define BIF_BX1_SBIOS_SCRATCH_11__SBIOS_SCRATCH_11_MASK                                                       0xFFFFFFFFL
+//BIF_BX1_SBIOS_SCRATCH_12
+#define BIF_BX1_SBIOS_SCRATCH_12__SBIOS_SCRATCH_12__SHIFT                                                     0x0
+#define BIF_BX1_SBIOS_SCRATCH_12__SBIOS_SCRATCH_12_MASK                                                       0xFFFFFFFFL
+//BIF_BX1_SBIOS_SCRATCH_13
+#define BIF_BX1_SBIOS_SCRATCH_13__SBIOS_SCRATCH_13__SHIFT                                                     0x0
+#define BIF_BX1_SBIOS_SCRATCH_13__SBIOS_SCRATCH_13_MASK                                                       0xFFFFFFFFL
+//BIF_BX1_SBIOS_SCRATCH_14
+#define BIF_BX1_SBIOS_SCRATCH_14__SBIOS_SCRATCH_14__SHIFT                                                     0x0
+#define BIF_BX1_SBIOS_SCRATCH_14__SBIOS_SCRATCH_14_MASK                                                       0xFFFFFFFFL
+//BIF_BX1_SBIOS_SCRATCH_15
+#define BIF_BX1_SBIOS_SCRATCH_15__SBIOS_SCRATCH_15__SHIFT                                                     0x0
+#define BIF_BX1_SBIOS_SCRATCH_15__SBIOS_SCRATCH_15_MASK                                                       0xFFFFFFFFL
+
+
+// addressBlock: nbif0_nbif0_bif_bx_pf_SYSPFVFDEC
+//BIF_BX_PF1_MM_INDEX
+#define BIF_BX_PF1_MM_INDEX__MM_OFFSET__SHIFT                                                                 0x0
+#define BIF_BX_PF1_MM_INDEX__MM_APER__SHIFT                                                                   0x1f
+#define BIF_BX_PF1_MM_INDEX__MM_OFFSET_MASK                                                                   0x7FFFFFFFL
+#define BIF_BX_PF1_MM_INDEX__MM_APER_MASK                                                                     0x80000000L
+//BIF_BX_PF1_MM_DATA
+#define BIF_BX_PF1_MM_DATA__MM_DATA__SHIFT                                                                    0x0
+#define BIF_BX_PF1_MM_DATA__MM_DATA_MASK                                                                      0xFFFFFFFFL
+//BIF_BX_PF1_MM_INDEX_HI
+#define BIF_BX_PF1_MM_INDEX_HI__MM_OFFSET_HI__SHIFT                                                           0x0
+#define BIF_BX_PF1_MM_INDEX_HI__MM_OFFSET_HI_MASK                                                             0xFFFFFFFFL
+
+
+// addressBlock: nbif0_nbif0_bif_bx_BIFDEC1
+//BIF_BX1_CC_BIF_BX_STRAP0
+#define BIF_BX1_CC_BIF_BX_STRAP0__STRAP_RESERVED__SHIFT                                                       0x19
+#define BIF_BX1_CC_BIF_BX_STRAP0__STRAP_RESERVED_MASK                                                         0xFE000000L
+//BIF_BX1_CC_BIF_BX_PINSTRAP0
+//BIF_BX1_BIF_MM_INDACCESS_CNTL
+#define BIF_BX1_BIF_MM_INDACCESS_CNTL__WRITE_DIS__SHIFT                                                       0x0
+#define BIF_BX1_BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS__SHIFT                                                0x1
+#define BIF_BX1_BIF_MM_INDACCESS_CNTL__WRITE_DIS_MASK                                                         0x00000001L
+#define BIF_BX1_BIF_MM_INDACCESS_CNTL__MM_INDACCESS_DIS_MASK                                                  0x00000002L
+//BIF_BX1_BUS_CNTL
+#define BIF_BX1_BUS_CNTL__VGA_REG_COHERENCY_DIS__SHIFT                                                        0x6
+#define BIF_BX1_BUS_CNTL__VGA_MEM_COHERENCY_DIS__SHIFT                                                        0x7
+#define BIF_BX1_BUS_CNTL__SET_AZ_TC__SHIFT                                                                    0xa
+#define BIF_BX1_BUS_CNTL__SET_MC_TC__SHIFT                                                                    0xd
+#define BIF_BX1_BUS_CNTL__ZERO_BE_WR_EN__SHIFT                                                                0x10
+#define BIF_BX1_BUS_CNTL__ZERO_BE_RD_EN__SHIFT                                                                0x11
+#define BIF_BX1_BUS_CNTL__RD_STALL_IO_WR__SHIFT                                                               0x12
+#define BIF_BX1_BUS_CNTL__HDP_FB_FLUSH_STALL_DOORBELL_DIS__SHIFT                                              0x18
+#define BIF_BX1_BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS__SHIFT                                          0x19
+#define BIF_BX1_BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS__SHIFT                                         0x1a
+#define BIF_BX1_BUS_CNTL__MMDAT_RD_HDP_TRIGGER_HDP_FB_FLUSH_DIS__SHIFT                                        0x1b
+#define BIF_BX1_BUS_CNTL__HDP_FB_FLUSH_STALL_MMDAT_RD_HDP_DIS__SHIFT                                          0x1c
+#define BIF_BX1_BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN__SHIFT                                                     0x1d
+#define BIF_BX1_BUS_CNTL__VGAFB_ZERO_BE_WR_EN__SHIFT                                                          0x1e
+#define BIF_BX1_BUS_CNTL__VGAFB_ZERO_BE_RD_EN__SHIFT                                                          0x1f
+#define BIF_BX1_BUS_CNTL__VGA_REG_COHERENCY_DIS_MASK                                                          0x00000040L
+#define BIF_BX1_BUS_CNTL__VGA_MEM_COHERENCY_DIS_MASK                                                          0x00000080L
+#define BIF_BX1_BUS_CNTL__SET_AZ_TC_MASK                                                                      0x00001C00L
+#define BIF_BX1_BUS_CNTL__SET_MC_TC_MASK                                                                      0x0000E000L
+#define BIF_BX1_BUS_CNTL__ZERO_BE_WR_EN_MASK                                                                  0x00010000L
+#define BIF_BX1_BUS_CNTL__ZERO_BE_RD_EN_MASK                                                                  0x00020000L
+#define BIF_BX1_BUS_CNTL__RD_STALL_IO_WR_MASK                                                                 0x00040000L
+#define BIF_BX1_BUS_CNTL__HDP_FB_FLUSH_STALL_DOORBELL_DIS_MASK                                                0x01000000L
+#define BIF_BX1_BUS_CNTL__PRECEEDINGWR_STALL_VGA_FB_FLUSH_DIS_MASK                                            0x02000000L
+#define BIF_BX1_BUS_CNTL__PRECEEDINGWR_STALL_VGA_REG_FLUSH_DIS_MASK                                           0x04000000L
+#define BIF_BX1_BUS_CNTL__MMDAT_RD_HDP_TRIGGER_HDP_FB_FLUSH_DIS_MASK                                          0x08000000L
+#define BIF_BX1_BUS_CNTL__HDP_FB_FLUSH_STALL_MMDAT_RD_HDP_DIS_MASK                                            0x10000000L
+#define BIF_BX1_BUS_CNTL__HDP_REG_FLUSH_VF_MASK_EN_MASK                                                       0x20000000L
+#define BIF_BX1_BUS_CNTL__VGAFB_ZERO_BE_WR_EN_MASK                                                            0x40000000L
+#define BIF_BX1_BUS_CNTL__VGAFB_ZERO_BE_RD_EN_MASK                                                            0x80000000L
+//BIF_BX1_BIF_SCRATCH0
+#define BIF_BX1_BIF_SCRATCH0__BIF_SCRATCH0__SHIFT                                                             0x0
+#define BIF_BX1_BIF_SCRATCH0__BIF_SCRATCH0_MASK                                                               0xFFFFFFFFL
+//BIF_BX1_BIF_SCRATCH1
+#define BIF_BX1_BIF_SCRATCH1__BIF_SCRATCH1__SHIFT                                                             0x0
+#define BIF_BX1_BIF_SCRATCH1__BIF_SCRATCH1_MASK                                                               0xFFFFFFFFL
+//BIF_BX1_BX_RESET_EN
+#define BIF_BX1_BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN__SHIFT                                                  0x10
+#define BIF_BX1_BX_RESET_EN__RESET_ON_VFENABLE_LOW_EN_MASK                                                    0x00010000L
+//BIF_BX1_MM_CFGREGS_CNTL
+#define BIF_BX1_MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL__SHIFT                                                       0x0
+#define BIF_BX1_MM_CFGREGS_CNTL__MM_CFG_DEV_SEL__SHIFT                                                        0x6
+#define BIF_BX1_MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN__SHIFT                                                       0x1f
+#define BIF_BX1_MM_CFGREGS_CNTL__MM_CFG_FUNC_SEL_MASK                                                         0x00000007L
+#define BIF_BX1_MM_CFGREGS_CNTL__MM_CFG_DEV_SEL_MASK                                                          0x000000C0L
+#define BIF_BX1_MM_CFGREGS_CNTL__MM_WR_TO_CFG_EN_MASK                                                         0x80000000L
+//BIF_BX1_BX_RESET_CNTL
+#define BIF_BX1_BX_RESET_CNTL__LINK_TRAIN_EN__SHIFT                                                           0x0
+#define BIF_BX1_BX_RESET_CNTL__LINK_TRAIN_EN_MASK                                                             0x00000001L
+//BIF_BX1_INTERRUPT_CNTL
+#define BIF_BX1_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE__SHIFT                                                   0x0
+#define BIF_BX1_INTERRUPT_CNTL__IH_DUMMY_RD_EN__SHIFT                                                         0x1
+#define BIF_BX1_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN__SHIFT                                                     0x3
+#define BIF_BX1_INTERRUPT_CNTL__IH_INTR_DLY_CNTR__SHIFT                                                       0x4
+#define BIF_BX1_INTERRUPT_CNTL__GEN_IH_INT_EN__SHIFT                                                          0x8
+#define BIF_BX1_INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN__SHIFT                                                 0xf
+#define BIF_BX1_INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN__SHIFT                                               0x10
+#define BIF_BX1_INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS__SHIFT                                   0x11
+#define BIF_BX1_INTERRUPT_CNTL__BIF_RB_REQ_RELAX_ORDER_EN__SHIFT                                              0x12
+#define BIF_BX1_INTERRUPT_CNTL__IH_DUMMY_RD_OVERRIDE_MASK                                                     0x00000001L
+#define BIF_BX1_INTERRUPT_CNTL__IH_DUMMY_RD_EN_MASK                                                           0x00000002L
+#define BIF_BX1_INTERRUPT_CNTL__IH_REQ_NONSNOOP_EN_MASK                                                       0x00000008L
+#define BIF_BX1_INTERRUPT_CNTL__IH_INTR_DLY_CNTR_MASK                                                         0x000000F0L
+#define BIF_BX1_INTERRUPT_CNTL__GEN_IH_INT_EN_MASK                                                            0x00000100L
+#define BIF_BX1_INTERRUPT_CNTL__BIF_RB_REQ_NONSNOOP_EN_MASK                                                   0x00008000L
+#define BIF_BX1_INTERRUPT_CNTL__DUMMYRD_BYPASS_IN_MSI_EN_MASK                                                 0x00010000L
+#define BIF_BX1_INTERRUPT_CNTL__ALWAYS_SEND_INTPKT_AFTER_DUMMYRD_DIS_MASK                                     0x00020000L
+#define BIF_BX1_INTERRUPT_CNTL__BIF_RB_REQ_RELAX_ORDER_EN_MASK                                                0x00040000L
+//BIF_BX1_INTERRUPT_CNTL2
+#define BIF_BX1_INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR__SHIFT                                                      0x0
+#define BIF_BX1_INTERRUPT_CNTL2__IH_DUMMY_RD_ADDR_MASK                                                        0xFFFFFFFFL
+//BIF_BX1_CLKREQB_PAD_CNTL
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_A__SHIFT                                                        0x0
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL__SHIFT                                                      0x1
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE__SHIFT                                                     0x2
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE__SHIFT                                                    0x3
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0__SHIFT                                                      0x5
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1__SHIFT                                                      0x6
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2__SHIFT                                                      0x7
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3__SHIFT                                                      0x8
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN__SHIFT                                                    0x9
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE__SHIFT                                                     0xa
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN__SHIFT                                                   0xb
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN__SHIFT                                                  0xc
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_Y__SHIFT                                                        0xd
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_A_MASK                                                          0x00000001L
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SEL_MASK                                                        0x00000002L
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_MODE_MASK                                                       0x00000004L
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SPARE_MASK                                                      0x00000018L
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN0_MASK                                                        0x00000020L
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN1_MASK                                                        0x00000040L
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN2_MASK                                                        0x00000080L
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SN3_MASK                                                        0x00000100L
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SLEWN_MASK                                                      0x00000200L
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_WAKE_MASK                                                       0x00000400L
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_SCHMEN_MASK                                                     0x00000800L
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_EN_MASK                                                    0x00001000L
+#define BIF_BX1_CLKREQB_PAD_CNTL__CLKREQB_PAD_Y_MASK                                                          0x00002000L
+//BIF_BX1_BIF_FEATURES_CONTROL_MISC
+#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS__SHIFT                                          0x0
+#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS__SHIFT                                          0x1
+#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS__SHIFT                                          0x2
+#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS__SHIFT                                          0x3
+#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_RB_MSI_VEC_NOT_ENABLED_MODE__SHIFT                             0xb
+#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN__SHIFT                                      0xc
+#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS__SHIFT                                          0xd
+#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__ATOMIC_ONLY_WRITE_DIS__SHIFT                                       0xe
+#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN__SHIFT                                           0xf
+#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__HDP_NP_OSTD_LIMIT__SHIFT                                           0x10
+#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR__SHIFT                   0x19
+#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__MST_BIF_REQ_EP_DIS_MASK                                            0x00000001L
+#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__SLV_BIF_CPL_EP_DIS_MASK                                            0x00000002L
+#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_SLV_REQ_EP_DIS_MASK                                            0x00000004L
+#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_MST_CPL_EP_DIS_MASK                                            0x00000008L
+#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_RB_MSI_VEC_NOT_ENABLED_MODE_MASK                               0x00000800L
+#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BIF_RB_SET_OVERFLOW_EN_MASK                                        0x00001000L
+#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__ATOMIC_ERR_INT_DIS_MASK                                            0x00002000L
+#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__ATOMIC_ONLY_WRITE_DIS_MASK                                         0x00004000L
+#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__BME_HDL_NONVIR_EN_MASK                                             0x00008000L
+#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__HDP_NP_OSTD_LIMIT_MASK                                             0x01FF0000L
+#define BIF_BX1_BIF_FEATURES_CONTROL_MISC__DOORBELL_SELFRING_GPA_APER_CHK_48BIT_ADDR_MASK                     0x02000000L
+//BIF_BX1_HDP_ATOMIC_CONTROL_MISC
+#define BIF_BX1_HDP_ATOMIC_CONTROL_MISC__HDP_NP_ATOMIC_OSTD_LIMIT__SHIFT                                      0x0
+#define BIF_BX1_HDP_ATOMIC_CONTROL_MISC__HDP_NP_ATOMIC_OSTD_LIMIT_MASK                                        0x000000FFL
+//BIF_BX1_BIF_DOORBELL_CNTL
+#define BIF_BX1_BIF_DOORBELL_CNTL__SELF_RING_DIS__SHIFT                                                       0x0
+#define BIF_BX1_BIF_DOORBELL_CNTL__TRANS_CHECK_DIS__SHIFT                                                     0x1
+#define BIF_BX1_BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN__SHIFT                                                    0x2
+#define BIF_BX1_BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS__SHIFT                                         0x3
+#define BIF_BX1_BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN__SHIFT                                                 0x4
+#define BIF_BX1_BIF_DOORBELL_CNTL__SELF_RING_DIS_LOCAL__SHIFT                                                 0x5
+#define BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS__SHIFT                                                  0x18
+#define BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0__SHIFT                                               0x19
+#define BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1__SHIFT                                               0x1a
+#define BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2__SHIFT                                               0x1b
+#define BIF_BX1_BIF_DOORBELL_CNTL__SELF_RING_DIS_MASK                                                         0x00000001L
+#define BIF_BX1_BIF_DOORBELL_CNTL__TRANS_CHECK_DIS_MASK                                                       0x00000002L
+#define BIF_BX1_BIF_DOORBELL_CNTL__UNTRANS_LBACK_EN_MASK                                                      0x00000004L
+#define BIF_BX1_BIF_DOORBELL_CNTL__NON_CONSECUTIVE_BE_ZERO_DIS_MASK                                           0x00000008L
+#define BIF_BX1_BIF_DOORBELL_CNTL__DOORBELL_MONITOR_EN_MASK                                                   0x00000010L
+#define BIF_BX1_BIF_DOORBELL_CNTL__SELF_RING_DIS_LOCAL_MASK                                                   0x00000020L
+#define BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_DIS_MASK                                                    0x01000000L
+#define BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_0_MASK                                                 0x02000000L
+#define BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_1_MASK                                                 0x04000000L
+#define BIF_BX1_BIF_DOORBELL_CNTL__DB_MNTR_INTGEN_MODE_2_MASK                                                 0x08000000L
+//BIF_BX1_BIF_DOORBELL_INT_CNTL
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS__SHIFT                                       0x0
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_STATUS__SHIFT                                      0x1
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS__SHIFT                            0x2
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR__SHIFT                                        0x10
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_CLEAR__SHIFT                                       0x11
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR__SHIFT                             0x12
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_ERR_EVENT_INTERRUPT_ENABLE__SHIFT                            0x17
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_DISABLE__SHIFT                                      0x18
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_DISABLE__SHIFT                                     0x19
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_DISABLE__SHIFT                           0x1a
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__SET_DB_INTR_STATUS_WHEN_RB_ENABLE__SHIFT                               0x1c
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__SET_IOH_RAS_INTR_STATUS_WHEN_RB_ENABLE__SHIFT                          0x1d
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__SET_ATH_RAS_INTR_STATUS_WHEN_RB_ENABLE__SHIFT                          0x1e
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__TIMEOUT_ERR_EVENT_INTERRUPT_ENABLE__SHIFT                              0x1f
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_STATUS_MASK                                         0x00000001L
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_STATUS_MASK                                        0x00000002L
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_STATUS_MASK                              0x00000004L
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_CLEAR_MASK                                          0x00010000L
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_CLEAR_MASK                                         0x00020000L
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_CLEAR_MASK                               0x00040000L
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_ERR_EVENT_INTERRUPT_ENABLE_MASK                              0x00800000L
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__DOORBELL_INTERRUPT_DISABLE_MASK                                        0x01000000L
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_CNTLR_INTERRUPT_DISABLE_MASK                                       0x02000000L
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__RAS_ATHUB_ERR_EVENT_INTERRUPT_DISABLE_MASK                             0x04000000L
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__SET_DB_INTR_STATUS_WHEN_RB_ENABLE_MASK                                 0x10000000L
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__SET_IOH_RAS_INTR_STATUS_WHEN_RB_ENABLE_MASK                            0x20000000L
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__SET_ATH_RAS_INTR_STATUS_WHEN_RB_ENABLE_MASK                            0x40000000L
+#define BIF_BX1_BIF_DOORBELL_INT_CNTL__TIMEOUT_ERR_EVENT_INTERRUPT_ENABLE_MASK                                0x80000000L
+//BIF_BX1_BIF_FB_EN
+#define BIF_BX1_BIF_FB_EN__FB_READ_EN__SHIFT                                                                  0x0
+#define BIF_BX1_BIF_FB_EN__FB_WRITE_EN__SHIFT                                                                 0x1
+#define BIF_BX1_BIF_FB_EN__FB_READ_EN_MASK                                                                    0x00000001L
+#define BIF_BX1_BIF_FB_EN__FB_WRITE_EN_MASK                                                                   0x00000002L
+//BIF_BX1_BIF_INTR_CNTL
+#define BIF_BX1_BIF_INTR_CNTL__RAS_INTR_VEC_SEL__SHIFT                                                        0x0
+#define BIF_BX1_BIF_INTR_CNTL__RAS_INTR_VEC_SEL_MASK                                                          0x00000001L
+//BIF_BX1_BIF_MST_TRANS_PENDING_VF
+#define BIF_BX1_BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING__SHIFT                                        0x0
+#define BIF_BX1_BIF_MST_TRANS_PENDING_VF__BIF_MST_TRANS_PENDING_MASK                                          0x7FFFFFFFL
+//BIF_BX1_BIF_SLV_TRANS_PENDING_VF
+#define BIF_BX1_BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING__SHIFT                                        0x0
+#define BIF_BX1_BIF_SLV_TRANS_PENDING_VF__BIF_SLV_TRANS_PENDING_MASK                                          0x7FFFFFFFL
+//BIF_BX1_BACO_CNTL
+#define BIF_BX1_BACO_CNTL__BACO_EN__SHIFT                                                                     0x0
+#define BIF_BX1_BACO_CNTL__BACO_DUMMY_EN__SHIFT                                                               0x2
+#define BIF_BX1_BACO_CNTL__BACO_POWER_OFF__SHIFT                                                              0x3
+#define BIF_BX1_BACO_CNTL__BACO_DSTATE_BYPASS__SHIFT                                                          0x5
+#define BIF_BX1_BACO_CNTL__BACO_RST_INTR_MASK__SHIFT                                                          0x6
+#define BIF_BX1_BACO_CNTL__BACO_MODE__SHIFT                                                                   0x8
+#define BIF_BX1_BACO_CNTL__RCU_BIF_CONFIG_DONE__SHIFT                                                         0x9
+#define BIF_BX1_BACO_CNTL__PWRGOOD_VDDSOC__SHIFT                                                              0x10
+#define BIF_BX1_BACO_CNTL__BACO_AUTO_EXIT__SHIFT                                                              0x1f
+#define BIF_BX1_BACO_CNTL__BACO_EN_MASK                                                                       0x00000001L
+#define BIF_BX1_BACO_CNTL__BACO_DUMMY_EN_MASK                                                                 0x00000004L
+#define BIF_BX1_BACO_CNTL__BACO_POWER_OFF_MASK                                                                0x00000008L
+#define BIF_BX1_BACO_CNTL__BACO_DSTATE_BYPASS_MASK                                                            0x00000020L
+#define BIF_BX1_BACO_CNTL__BACO_RST_INTR_MASK_MASK                                                            0x00000040L
+#define BIF_BX1_BACO_CNTL__BACO_MODE_MASK                                                                     0x00000100L
+#define BIF_BX1_BACO_CNTL__RCU_BIF_CONFIG_DONE_MASK                                                           0x00000200L
+#define BIF_BX1_BACO_CNTL__PWRGOOD_VDDSOC_MASK                                                                0x00010000L
+#define BIF_BX1_BACO_CNTL__BACO_AUTO_EXIT_MASK                                                                0x80000000L
+//BIF_BX1_BIF_BACO_EXIT_TIME0
+#define BIF_BX1_BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER__SHIFT                                          0x0
+#define BIF_BX1_BIF_BACO_EXIT_TIME0__BACO_EXIT_PXEN_CLR_TIMER_MASK                                            0x000FFFFFL
+//BIF_BX1_BIF_BACO_EXIT_TIMER1
+#define BIF_BX1_BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER__SHIFT                                         0x0
+#define BIF_BX1_BIF_BACO_EXIT_TIMER1__BACO_HW_AUTO_FLUSH_EN__SHIFT                                            0x18
+#define BIF_BX1_BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS__SHIFT                                                 0x1a
+#define BIF_BX1_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH__SHIFT                                           0x1b
+#define BIF_BX1_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW__SHIFT                                            0x1c
+#define BIF_BX1_BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL__SHIFT                                                    0x1d
+#define BIF_BX1_BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS__SHIFT                                     0x1f
+#define BIF_BX1_BIF_BACO_EXIT_TIMER1__BACO_EXIT_SIDEBAND_TIMER_MASK                                           0x000FFFFFL
+#define BIF_BX1_BIF_BACO_EXIT_TIMER1__BACO_HW_AUTO_FLUSH_EN_MASK                                              0x01000000L
+#define BIF_BX1_BIF_BACO_EXIT_TIMER1__BACO_HW_EXIT_DIS_MASK                                                   0x04000000L
+#define BIF_BX1_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_HIGH_MASK                                             0x08000000L
+#define BIF_BX1_BIF_BACO_EXIT_TIMER1__PX_EN_OE_IN_PX_EN_LOW_MASK                                              0x10000000L
+#define BIF_BX1_BIF_BACO_EXIT_TIMER1__BACO_MODE_SEL_MASK                                                      0x60000000L
+#define BIF_BX1_BIF_BACO_EXIT_TIMER1__AUTO_BACO_EXIT_CLR_BY_HW_DIS_MASK                                       0x80000000L
+//BIF_BX1_BIF_BACO_EXIT_TIMER2
+#define BIF_BX1_BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER__SHIFT                                         0x0
+#define BIF_BX1_BIF_BACO_EXIT_TIMER2__BACO_EXIT_LCLK_BAK_TIMER_MASK                                           0x000FFFFFL
+//BIF_BX1_BIF_BACO_EXIT_TIMER3
+#define BIF_BX1_BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER__SHIFT                                     0x0
+#define BIF_BX1_BIF_BACO_EXIT_TIMER3__BACO_EXIT_DUMMY_EN_CLR_TIMER_MASK                                       0x000FFFFFL
+//BIF_BX1_BIF_BACO_EXIT_TIMER4
+#define BIF_BX1_BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER__SHIFT                                      0x0
+#define BIF_BX1_BIF_BACO_EXIT_TIMER4__BACO_EXIT_BACO_EN_CLR_TIMER_MASK                                        0x000FFFFFL
+//BIF_BX1_MEM_TYPE_CNTL
+#define BIF_BX1_MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3__SHIFT                                                        0x0
+#define BIF_BX1_MEM_TYPE_CNTL__BF_MEM_PHY_G5_G3_MASK                                                          0x00000001L
+//BIF_BX1_NBIF_GFX_ADDR_LUT_CNTL
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_CNTL__LUT_ENABLE__SHIFT                                                     0x0
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_CNTL__MSI_ADDR_MODE__SHIFT                                                  0x1
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_CNTL__LUT_BC_MODE__SHIFT                                                    0x8
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_CNTL__LUT_ENABLE_MASK                                                       0x00000001L
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_CNTL__MSI_ADDR_MODE_MASK                                                    0x00000002L
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_CNTL__LUT_BC_MODE_MASK                                                      0x00000100L
+//BIF_BX1_NBIF_GFX_ADDR_LUT_0
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_0__ADDR__SHIFT                                                              0x0
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_0__ADDR_MASK                                                                0x00FFFFFFL
+//BIF_BX1_NBIF_GFX_ADDR_LUT_1
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_1__ADDR__SHIFT                                                              0x0
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_1__ADDR_MASK                                                                0x00FFFFFFL
+//BIF_BX1_NBIF_GFX_ADDR_LUT_2
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_2__ADDR__SHIFT                                                              0x0
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_2__ADDR_MASK                                                                0x00FFFFFFL
+//BIF_BX1_NBIF_GFX_ADDR_LUT_3
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_3__ADDR__SHIFT                                                              0x0
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_3__ADDR_MASK                                                                0x00FFFFFFL
+//BIF_BX1_NBIF_GFX_ADDR_LUT_4
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_4__ADDR__SHIFT                                                              0x0
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_4__ADDR_MASK                                                                0x00FFFFFFL
+//BIF_BX1_NBIF_GFX_ADDR_LUT_5
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_5__ADDR__SHIFT                                                              0x0
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_5__ADDR_MASK                                                                0x00FFFFFFL
+//BIF_BX1_NBIF_GFX_ADDR_LUT_6
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_6__ADDR__SHIFT                                                              0x0
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_6__ADDR_MASK                                                                0x00FFFFFFL
+//BIF_BX1_NBIF_GFX_ADDR_LUT_7
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_7__ADDR__SHIFT                                                              0x0
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_7__ADDR_MASK                                                                0x00FFFFFFL
+//BIF_BX1_NBIF_GFX_ADDR_LUT_8
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_8__ADDR__SHIFT                                                              0x0
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_8__ADDR_MASK                                                                0x00FFFFFFL
+//BIF_BX1_NBIF_GFX_ADDR_LUT_9
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_9__ADDR__SHIFT                                                              0x0
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_9__ADDR_MASK                                                                0x00FFFFFFL
+//BIF_BX1_NBIF_GFX_ADDR_LUT_10
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_10__ADDR__SHIFT                                                             0x0
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_10__ADDR_MASK                                                               0x00FFFFFFL
+//BIF_BX1_NBIF_GFX_ADDR_LUT_11
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_11__ADDR__SHIFT                                                             0x0
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_11__ADDR_MASK                                                               0x00FFFFFFL
+//BIF_BX1_NBIF_GFX_ADDR_LUT_12
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_12__ADDR__SHIFT                                                             0x0
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_12__ADDR_MASK                                                               0x00FFFFFFL
+//BIF_BX1_NBIF_GFX_ADDR_LUT_13
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_13__ADDR__SHIFT                                                             0x0
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_13__ADDR_MASK                                                               0x00FFFFFFL
+//BIF_BX1_NBIF_GFX_ADDR_LUT_14
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_14__ADDR__SHIFT                                                             0x0
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_14__ADDR_MASK                                                               0x00FFFFFFL
+//BIF_BX1_NBIF_GFX_ADDR_LUT_15
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_15__ADDR__SHIFT                                                             0x0
+#define BIF_BX1_NBIF_GFX_ADDR_LUT_15__ADDR_MASK                                                               0x00FFFFFFL
+//BIF_BX1_VF_REGWR_EN
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF0__SHIFT                                                           0x0
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF1__SHIFT                                                           0x1
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF2__SHIFT                                                           0x2
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF3__SHIFT                                                           0x3
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF4__SHIFT                                                           0x4
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF5__SHIFT                                                           0x5
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF6__SHIFT                                                           0x6
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF7__SHIFT                                                           0x7
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF8__SHIFT                                                           0x8
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF9__SHIFT                                                           0x9
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF10__SHIFT                                                          0xa
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF11__SHIFT                                                          0xb
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF12__SHIFT                                                          0xc
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF13__SHIFT                                                          0xd
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF14__SHIFT                                                          0xe
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF15__SHIFT                                                          0xf
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF16__SHIFT                                                          0x10
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF17__SHIFT                                                          0x11
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF18__SHIFT                                                          0x12
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF19__SHIFT                                                          0x13
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF20__SHIFT                                                          0x14
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF21__SHIFT                                                          0x15
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF22__SHIFT                                                          0x16
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF23__SHIFT                                                          0x17
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF24__SHIFT                                                          0x18
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF25__SHIFT                                                          0x19
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF26__SHIFT                                                          0x1a
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF27__SHIFT                                                          0x1b
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF28__SHIFT                                                          0x1c
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF29__SHIFT                                                          0x1d
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF30__SHIFT                                                          0x1e
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF0_MASK                                                             0x00000001L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF1_MASK                                                             0x00000002L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF2_MASK                                                             0x00000004L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF3_MASK                                                             0x00000008L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF4_MASK                                                             0x00000010L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF5_MASK                                                             0x00000020L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF6_MASK                                                             0x00000040L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF7_MASK                                                             0x00000080L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF8_MASK                                                             0x00000100L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF9_MASK                                                             0x00000200L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF10_MASK                                                            0x00000400L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF11_MASK                                                            0x00000800L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF12_MASK                                                            0x00001000L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF13_MASK                                                            0x00002000L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF14_MASK                                                            0x00004000L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF15_MASK                                                            0x00008000L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF16_MASK                                                            0x00010000L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF17_MASK                                                            0x00020000L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF18_MASK                                                            0x00040000L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF19_MASK                                                            0x00080000L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF20_MASK                                                            0x00100000L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF21_MASK                                                            0x00200000L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF22_MASK                                                            0x00400000L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF23_MASK                                                            0x00800000L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF24_MASK                                                            0x01000000L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF25_MASK                                                            0x02000000L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF26_MASK                                                            0x04000000L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF27_MASK                                                            0x08000000L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF28_MASK                                                            0x10000000L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF29_MASK                                                            0x20000000L
+#define BIF_BX1_VF_REGWR_EN__VF_REGWR_EN_VF30_MASK                                                            0x40000000L
+//BIF_BX1_VF_DOORBELL_EN
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF0__SHIFT                                                     0x0
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF1__SHIFT                                                     0x1
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF2__SHIFT                                                     0x2
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF3__SHIFT                                                     0x3
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF4__SHIFT                                                     0x4
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF5__SHIFT                                                     0x5
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF6__SHIFT                                                     0x6
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF7__SHIFT                                                     0x7
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF8__SHIFT                                                     0x8
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF9__SHIFT                                                     0x9
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF10__SHIFT                                                    0xa
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF11__SHIFT                                                    0xb
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF12__SHIFT                                                    0xc
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF13__SHIFT                                                    0xd
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF14__SHIFT                                                    0xe
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF15__SHIFT                                                    0xf
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF16__SHIFT                                                    0x10
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF17__SHIFT                                                    0x11
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF18__SHIFT                                                    0x12
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF19__SHIFT                                                    0x13
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF20__SHIFT                                                    0x14
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF21__SHIFT                                                    0x15
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF22__SHIFT                                                    0x16
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF23__SHIFT                                                    0x17
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF24__SHIFT                                                    0x18
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF25__SHIFT                                                    0x19
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF26__SHIFT                                                    0x1a
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF27__SHIFT                                                    0x1b
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF28__SHIFT                                                    0x1c
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF29__SHIFT                                                    0x1d
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF30__SHIFT                                                    0x1e
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_RD_LOG_DIS__SHIFT                                                 0x1f
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF0_MASK                                                       0x00000001L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF1_MASK                                                       0x00000002L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF2_MASK                                                       0x00000004L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF3_MASK                                                       0x00000008L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF4_MASK                                                       0x00000010L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF5_MASK                                                       0x00000020L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF6_MASK                                                       0x00000040L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF7_MASK                                                       0x00000080L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF8_MASK                                                       0x00000100L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF9_MASK                                                       0x00000200L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF10_MASK                                                      0x00000400L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF11_MASK                                                      0x00000800L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF12_MASK                                                      0x00001000L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF13_MASK                                                      0x00002000L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF14_MASK                                                      0x00004000L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF15_MASK                                                      0x00008000L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF16_MASK                                                      0x00010000L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF17_MASK                                                      0x00020000L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF18_MASK                                                      0x00040000L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF19_MASK                                                      0x00080000L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF20_MASK                                                      0x00100000L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF21_MASK                                                      0x00200000L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF22_MASK                                                      0x00400000L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF23_MASK                                                      0x00800000L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF24_MASK                                                      0x01000000L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF25_MASK                                                      0x02000000L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF26_MASK                                                      0x04000000L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF27_MASK                                                      0x08000000L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF28_MASK                                                      0x10000000L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF29_MASK                                                      0x20000000L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_EN_VF30_MASK                                                      0x40000000L
+#define BIF_BX1_VF_DOORBELL_EN__VF_DOORBELL_RD_LOG_DIS_MASK                                                   0x80000000L
+//BIF_BX1_VF_FB_EN
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF0__SHIFT                                                                 0x0
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF1__SHIFT                                                                 0x1
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF2__SHIFT                                                                 0x2
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF3__SHIFT                                                                 0x3
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF4__SHIFT                                                                 0x4
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF5__SHIFT                                                                 0x5
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF6__SHIFT                                                                 0x6
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF7__SHIFT                                                                 0x7
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF8__SHIFT                                                                 0x8
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF9__SHIFT                                                                 0x9
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF10__SHIFT                                                                0xa
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF11__SHIFT                                                                0xb
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF12__SHIFT                                                                0xc
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF13__SHIFT                                                                0xd
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF14__SHIFT                                                                0xe
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF15__SHIFT                                                                0xf
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF16__SHIFT                                                                0x10
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF17__SHIFT                                                                0x11
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF18__SHIFT                                                                0x12
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF19__SHIFT                                                                0x13
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF20__SHIFT                                                                0x14
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF21__SHIFT                                                                0x15
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF22__SHIFT                                                                0x16
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF23__SHIFT                                                                0x17
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF24__SHIFT                                                                0x18
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF25__SHIFT                                                                0x19
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF26__SHIFT                                                                0x1a
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF27__SHIFT                                                                0x1b
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF28__SHIFT                                                                0x1c
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF29__SHIFT                                                                0x1d
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF30__SHIFT                                                                0x1e
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF0_MASK                                                                   0x00000001L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF1_MASK                                                                   0x00000002L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF2_MASK                                                                   0x00000004L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF3_MASK                                                                   0x00000008L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF4_MASK                                                                   0x00000010L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF5_MASK                                                                   0x00000020L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF6_MASK                                                                   0x00000040L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF7_MASK                                                                   0x00000080L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF8_MASK                                                                   0x00000100L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF9_MASK                                                                   0x00000200L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF10_MASK                                                                  0x00000400L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF11_MASK                                                                  0x00000800L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF12_MASK                                                                  0x00001000L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF13_MASK                                                                  0x00002000L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF14_MASK                                                                  0x00004000L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF15_MASK                                                                  0x00008000L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF16_MASK                                                                  0x00010000L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF17_MASK                                                                  0x00020000L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF18_MASK                                                                  0x00040000L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF19_MASK                                                                  0x00080000L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF20_MASK                                                                  0x00100000L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF21_MASK                                                                  0x00200000L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF22_MASK                                                                  0x00400000L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF23_MASK                                                                  0x00800000L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF24_MASK                                                                  0x01000000L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF25_MASK                                                                  0x02000000L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF26_MASK                                                                  0x04000000L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF27_MASK                                                                  0x08000000L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF28_MASK                                                                  0x10000000L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF29_MASK                                                                  0x20000000L
+#define BIF_BX1_VF_FB_EN__VF_FB_EN_VF30_MASK                                                                  0x40000000L
+//BIF_BX1_VF_REGWR_STATUS
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF0__SHIFT                                                   0x0
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF1__SHIFT                                                   0x1
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF2__SHIFT                                                   0x2
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF3__SHIFT                                                   0x3
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF4__SHIFT                                                   0x4
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF5__SHIFT                                                   0x5
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF6__SHIFT                                                   0x6
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF7__SHIFT                                                   0x7
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF8__SHIFT                                                   0x8
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF9__SHIFT                                                   0x9
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF10__SHIFT                                                  0xa
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF11__SHIFT                                                  0xb
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF12__SHIFT                                                  0xc
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF13__SHIFT                                                  0xd
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF14__SHIFT                                                  0xe
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF15__SHIFT                                                  0xf
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF16__SHIFT                                                  0x10
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF17__SHIFT                                                  0x11
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF18__SHIFT                                                  0x12
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF19__SHIFT                                                  0x13
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF20__SHIFT                                                  0x14
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF21__SHIFT                                                  0x15
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF22__SHIFT                                                  0x16
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF23__SHIFT                                                  0x17
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF24__SHIFT                                                  0x18
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF25__SHIFT                                                  0x19
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF26__SHIFT                                                  0x1a
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF27__SHIFT                                                  0x1b
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF28__SHIFT                                                  0x1c
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF29__SHIFT                                                  0x1d
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF30__SHIFT                                                  0x1e
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF0_MASK                                                     0x00000001L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF1_MASK                                                     0x00000002L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF2_MASK                                                     0x00000004L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF3_MASK                                                     0x00000008L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF4_MASK                                                     0x00000010L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF5_MASK                                                     0x00000020L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF6_MASK                                                     0x00000040L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF7_MASK                                                     0x00000080L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF8_MASK                                                     0x00000100L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF9_MASK                                                     0x00000200L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF10_MASK                                                    0x00000400L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF11_MASK                                                    0x00000800L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF12_MASK                                                    0x00001000L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF13_MASK                                                    0x00002000L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF14_MASK                                                    0x00004000L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF15_MASK                                                    0x00008000L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF16_MASK                                                    0x00010000L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF17_MASK                                                    0x00020000L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF18_MASK                                                    0x00040000L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF19_MASK                                                    0x00080000L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF20_MASK                                                    0x00100000L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF21_MASK                                                    0x00200000L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF22_MASK                                                    0x00400000L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF23_MASK                                                    0x00800000L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF24_MASK                                                    0x01000000L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF25_MASK                                                    0x02000000L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF26_MASK                                                    0x04000000L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF27_MASK                                                    0x08000000L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF28_MASK                                                    0x10000000L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF29_MASK                                                    0x20000000L
+#define BIF_BX1_VF_REGWR_STATUS__VF_REGWR_STATUS_VF30_MASK                                                    0x40000000L
+//BIF_BX1_VF_DOORBELL_STATUS
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF0__SHIFT                                             0x0
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF1__SHIFT                                             0x1
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF2__SHIFT                                             0x2
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF3__SHIFT                                             0x3
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF4__SHIFT                                             0x4
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF5__SHIFT                                             0x5
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF6__SHIFT                                             0x6
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF7__SHIFT                                             0x7
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF8__SHIFT                                             0x8
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF9__SHIFT                                             0x9
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF10__SHIFT                                            0xa
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF11__SHIFT                                            0xb
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF12__SHIFT                                            0xc
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF13__SHIFT                                            0xd
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF14__SHIFT                                            0xe
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF15__SHIFT                                            0xf
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF16__SHIFT                                            0x10
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF17__SHIFT                                            0x11
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF18__SHIFT                                            0x12
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF19__SHIFT                                            0x13
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF20__SHIFT                                            0x14
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF21__SHIFT                                            0x15
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF22__SHIFT                                            0x16
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF23__SHIFT                                            0x17
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF24__SHIFT                                            0x18
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF25__SHIFT                                            0x19
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF26__SHIFT                                            0x1a
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF27__SHIFT                                            0x1b
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF28__SHIFT                                            0x1c
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF29__SHIFT                                            0x1d
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF30__SHIFT                                            0x1e
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF0_MASK                                               0x00000001L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF1_MASK                                               0x00000002L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF2_MASK                                               0x00000004L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF3_MASK                                               0x00000008L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF4_MASK                                               0x00000010L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF5_MASK                                               0x00000020L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF6_MASK                                               0x00000040L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF7_MASK                                               0x00000080L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF8_MASK                                               0x00000100L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF9_MASK                                               0x00000200L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF10_MASK                                              0x00000400L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF11_MASK                                              0x00000800L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF12_MASK                                              0x00001000L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF13_MASK                                              0x00002000L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF14_MASK                                              0x00004000L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF15_MASK                                              0x00008000L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF16_MASK                                              0x00010000L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF17_MASK                                              0x00020000L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF18_MASK                                              0x00040000L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF19_MASK                                              0x00080000L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF20_MASK                                              0x00100000L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF21_MASK                                              0x00200000L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF22_MASK                                              0x00400000L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF23_MASK                                              0x00800000L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF24_MASK                                              0x01000000L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF25_MASK                                              0x02000000L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF26_MASK                                              0x04000000L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF27_MASK                                              0x08000000L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF28_MASK                                              0x10000000L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF29_MASK                                              0x20000000L
+#define BIF_BX1_VF_DOORBELL_STATUS__VF_DOORBELL_STATUS_VF30_MASK                                              0x40000000L
+//BIF_BX1_VF_FB_STATUS
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF0__SHIFT                                                         0x0
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF1__SHIFT                                                         0x1
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF2__SHIFT                                                         0x2
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF3__SHIFT                                                         0x3
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF4__SHIFT                                                         0x4
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF5__SHIFT                                                         0x5
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF6__SHIFT                                                         0x6
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF7__SHIFT                                                         0x7
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF8__SHIFT                                                         0x8
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF9__SHIFT                                                         0x9
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF10__SHIFT                                                        0xa
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF11__SHIFT                                                        0xb
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF12__SHIFT                                                        0xc
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF13__SHIFT                                                        0xd
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF14__SHIFT                                                        0xe
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF15__SHIFT                                                        0xf
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF16__SHIFT                                                        0x10
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF17__SHIFT                                                        0x11
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF18__SHIFT                                                        0x12
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF19__SHIFT                                                        0x13
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF20__SHIFT                                                        0x14
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF21__SHIFT                                                        0x15
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF22__SHIFT                                                        0x16
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF23__SHIFT                                                        0x17
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF24__SHIFT                                                        0x18
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF25__SHIFT                                                        0x19
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF26__SHIFT                                                        0x1a
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF27__SHIFT                                                        0x1b
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF28__SHIFT                                                        0x1c
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF29__SHIFT                                                        0x1d
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF30__SHIFT                                                        0x1e
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF0_MASK                                                           0x00000001L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF1_MASK                                                           0x00000002L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF2_MASK                                                           0x00000004L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF3_MASK                                                           0x00000008L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF4_MASK                                                           0x00000010L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF5_MASK                                                           0x00000020L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF6_MASK                                                           0x00000040L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF7_MASK                                                           0x00000080L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF8_MASK                                                           0x00000100L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF9_MASK                                                           0x00000200L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF10_MASK                                                          0x00000400L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF11_MASK                                                          0x00000800L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF12_MASK                                                          0x00001000L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF13_MASK                                                          0x00002000L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF14_MASK                                                          0x00004000L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF15_MASK                                                          0x00008000L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF16_MASK                                                          0x00010000L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF17_MASK                                                          0x00020000L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF18_MASK                                                          0x00040000L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF19_MASK                                                          0x00080000L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF20_MASK                                                          0x00100000L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF21_MASK                                                          0x00200000L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF22_MASK                                                          0x00400000L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF23_MASK                                                          0x00800000L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF24_MASK                                                          0x01000000L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF25_MASK                                                          0x02000000L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF26_MASK                                                          0x04000000L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF27_MASK                                                          0x08000000L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF28_MASK                                                          0x10000000L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF29_MASK                                                          0x20000000L
+#define BIF_BX1_VF_FB_STATUS__VF_FB_STATUS_VF30_MASK                                                          0x40000000L
+//BIF_BX1_REMAP_HDP_MEM_FLUSH_CNTL
+#define BIF_BX1_REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS__SHIFT                                                      0x2
+#define BIF_BX1_REMAP_HDP_MEM_FLUSH_CNTL__ADDRESS_MASK                                                        0x0007FFFCL
+//BIF_BX1_REMAP_HDP_REG_FLUSH_CNTL
+#define BIF_BX1_REMAP_HDP_REG_FLUSH_CNTL__ADDRESS__SHIFT                                                      0x2
+#define BIF_BX1_REMAP_HDP_REG_FLUSH_CNTL__ADDRESS_MASK                                                        0x0007FFFCL
+//BIF_BX1_BIF_RB_CNTL
+#define BIF_BX1_BIF_RB_CNTL__RB_ENABLE__SHIFT                                                                 0x0
+#define BIF_BX1_BIF_RB_CNTL__RB_SIZE__SHIFT                                                                   0x1
+#define BIF_BX1_BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE__SHIFT                                                     0x8
+#define BIF_BX1_BIF_RB_CNTL__WPTR_WRITEBACK_TIMER__SHIFT                                                      0x9
+#define BIF_BX1_BIF_RB_CNTL__BIF_RB_TRAN__SHIFT                                                               0x11
+#define BIF_BX1_BIF_RB_CNTL__DIS_PROTECT_WHEN_RB_FULL__SHIFT                                                  0x19
+#define BIF_BX1_BIF_RB_CNTL__RB_INTR_FIX_PRIORITY__SHIFT                                                      0x1a
+#define BIF_BX1_BIF_RB_CNTL__RB_INTR_ARB_MODE__SHIFT                                                          0x1d
+#define BIF_BX1_BIF_RB_CNTL__RB_RST_BY_FLR_DISABLE__SHIFT                                                     0x1e
+#define BIF_BX1_BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR__SHIFT                                                       0x1f
+#define BIF_BX1_BIF_RB_CNTL__RB_ENABLE_MASK                                                                   0x00000001L
+#define BIF_BX1_BIF_RB_CNTL__RB_SIZE_MASK                                                                     0x0000003EL
+#define BIF_BX1_BIF_RB_CNTL__WPTR_WRITEBACK_ENABLE_MASK                                                       0x00000100L
+#define BIF_BX1_BIF_RB_CNTL__WPTR_WRITEBACK_TIMER_MASK                                                        0x00003E00L
+#define BIF_BX1_BIF_RB_CNTL__BIF_RB_TRAN_MASK                                                                 0x00020000L
+#define BIF_BX1_BIF_RB_CNTL__DIS_PROTECT_WHEN_RB_FULL_MASK                                                    0x02000000L
+#define BIF_BX1_BIF_RB_CNTL__RB_INTR_FIX_PRIORITY_MASK                                                        0x1C000000L
+#define BIF_BX1_BIF_RB_CNTL__RB_INTR_ARB_MODE_MASK                                                            0x20000000L
+#define BIF_BX1_BIF_RB_CNTL__RB_RST_BY_FLR_DISABLE_MASK                                                       0x40000000L
+#define BIF_BX1_BIF_RB_CNTL__WPTR_OVERFLOW_CLEAR_MASK                                                         0x80000000L
+//BIF_BX1_BIF_RB_BASE
+#define BIF_BX1_BIF_RB_BASE__ADDR__SHIFT                                                                      0x0
+#define BIF_BX1_BIF_RB_BASE__ADDR_MASK                                                                        0xFFFFFFFFL
+//BIF_BX1_BIF_RB_RPTR
+#define BIF_BX1_BIF_RB_RPTR__OFFSET__SHIFT                                                                    0x2
+#define BIF_BX1_BIF_RB_RPTR__OFFSET_MASK                                                                      0x0003FFFCL
+//BIF_BX1_BIF_RB_WPTR
+#define BIF_BX1_BIF_RB_WPTR__BIF_RB_OVERFLOW__SHIFT                                                           0x0
+#define BIF_BX1_BIF_RB_WPTR__OFFSET__SHIFT                                                                    0x2
+#define BIF_BX1_BIF_RB_WPTR__BIF_RB_OVERFLOW_MASK                                                             0x00000001L
+#define BIF_BX1_BIF_RB_WPTR__OFFSET_MASK                                                                      0x0003FFFCL
+//BIF_BX1_BIF_RB_WPTR_ADDR_HI
+#define BIF_BX1_BIF_RB_WPTR_ADDR_HI__ADDR__SHIFT                                                              0x0
+#define BIF_BX1_BIF_RB_WPTR_ADDR_HI__ADDR_MASK                                                                0x000000FFL
+//BIF_BX1_BIF_RB_WPTR_ADDR_LO
+#define BIF_BX1_BIF_RB_WPTR_ADDR_LO__ADDR__SHIFT                                                              0x2
+#define BIF_BX1_BIF_RB_WPTR_ADDR_LO__ADDR_MASK                                                                0xFFFFFFFCL
+//BIF_BX1_MAILBOX_INDEX
+#define BIF_BX1_MAILBOX_INDEX__MAILBOX_INDEX__SHIFT                                                           0x0
+#define BIF_BX1_MAILBOX_INDEX__MAILBOX_INDEX_MASK                                                             0x0000001FL
+//BIF_BX1_BACO_AZ_ENHANCE_CTRL
+#define BIF_BX1_BACO_AZ_ENHANCE_CTRL__GCTL_OFFSET__SHIFT                                                      0x2
+#define BIF_BX1_BACO_AZ_ENHANCE_CTRL__AZ_CRST_WRITTEN_ONE__SHIFT                                              0x10
+#define BIF_BX1_BACO_AZ_ENHANCE_CTRL__AZ_CRST_WRITTEN_ZERO__SHIFT                                             0x11
+#define BIF_BX1_BACO_AZ_ENHANCE_CTRL__AZ_MMIO_RDRSPDATA_FORCE_ZERO__SHIFT                                     0x1f
+#define BIF_BX1_BACO_AZ_ENHANCE_CTRL__GCTL_OFFSET_MASK                                                        0x00003FFCL
+#define BIF_BX1_BACO_AZ_ENHANCE_CTRL__AZ_CRST_WRITTEN_ONE_MASK                                                0x00010000L
+#define BIF_BX1_BACO_AZ_ENHANCE_CTRL__AZ_CRST_WRITTEN_ZERO_MASK                                               0x00020000L
+#define BIF_BX1_BACO_AZ_ENHANCE_CTRL__AZ_MMIO_RDRSPDATA_FORCE_ZERO_MASK                                       0x80000000L
+//BIF_BX1_BIF_MP1_INTR_CTRL
+#define BIF_BX1_BIF_MP1_INTR_CTRL__BACO_EXIT_DONE__SHIFT                                                      0x0
+#define BIF_BX1_BIF_MP1_INTR_CTRL__BACO_EXIT_DONE_MASK                                                        0x00000001L
+//BIF_BX1_BIF_PERSTB_PAD_CNTL
+#define BIF_BX1_BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL__SHIFT                                                   0x0
+#define BIF_BX1_BIF_PERSTB_PAD_CNTL__PERSTB_PAD_CNTL_MASK                                                     0x0000FFFFL
+//BIF_BX1_BIF_PX_EN_PAD_CNTL
+#define BIF_BX1_BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL__SHIFT                                                     0x0
+#define BIF_BX1_BIF_PX_EN_PAD_CNTL__PX_EN_PAD_CNTL_MASK                                                       0x00000FFFL
+//BIF_BX1_BIF_REFPADKIN_PAD_CNTL
+#define BIF_BX1_BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL__SHIFT                                             0x0
+#define BIF_BX1_BIF_REFPADKIN_PAD_CNTL__REFPADKIN_PAD_CNTL_MASK                                               0x000000FFL
+//BIF_BX1_BIF_CLKREQB_PAD_CNTL
+#define BIF_BX1_BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL__SHIFT                                                 0x0
+#define BIF_BX1_BIF_CLKREQB_PAD_CNTL__CLKREQB_PAD_CNTL_MASK                                                   0x7FFFFFFFL
+//BIF_BX1_BIF_PWRBRK_PAD_CNTL
+#define BIF_BX1_BIF_PWRBRK_PAD_CNTL__PWRBRK_PAD_CNTL__SHIFT                                                   0x0
+#define BIF_BX1_BIF_PWRBRK_PAD_CNTL__PWRBRK_PAD_CNTL_MASK                                                     0x000000FFL
+//BIF_BX1_BIF_GPUIOV_SCH_CFG_SIZE
+#define BIF_BX1_BIF_GPUIOV_SCH_CFG_SIZE__GPUIOV_SCH_CFG_SIZE__SHIFT                                           0x0
+#define BIF_BX1_BIF_GPUIOV_SCH_CFG_SIZE__GPUIOV_SCH_CFG_SIZE_MASK                                             0x0000000FL
+
+
+// addressBlock: nbif0_nbif0_bif_bx_pf_BIFPFVFDEC1
+//BIF_BX_PF1_BIF_BME_STATUS
+#define BIF_BX_PF1_BIF_BME_STATUS__DMA_ON_BME_LOW__SHIFT                                                      0x0
+#define BIF_BX_PF1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW__SHIFT                                                0x10
+#define BIF_BX_PF1_BIF_BME_STATUS__DMA_ON_BME_LOW_MASK                                                        0x00000001L
+#define BIF_BX_PF1_BIF_BME_STATUS__CLEAR_DMA_ON_BME_LOW_MASK                                                  0x00010000L
+//BIF_BX_PF1_BIF_ATOMIC_ERR_LOG
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE__SHIFT                                                0x0
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW__SHIFT                                             0x1
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH__SHIFT                                                0x2
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR__SHIFT                                                    0x3
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE__SHIFT                                          0x10
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW__SHIFT                                       0x11
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH__SHIFT                                          0x12
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR__SHIFT                                              0x13
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_OPCODE_MASK                                                  0x00000001L
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_REQEN_LOW_MASK                                               0x00000002L
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_LENGTH_MASK                                                  0x00000004L
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__UR_ATOMIC_NR_MASK                                                      0x00000008L
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_OPCODE_MASK                                            0x00010000L
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_REQEN_LOW_MASK                                         0x00020000L
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_LENGTH_MASK                                            0x00040000L
+#define BIF_BX_PF1_BIF_ATOMIC_ERR_LOG__CLEAR_UR_ATOMIC_NR_MASK                                                0x00080000L
+//BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH
+#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH__SHIFT          0x0
+#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_HIGH__DOORBELL_SELFRING_GPA_APER_BASE_HIGH_MASK            0xFFFFFFFFL
+//BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW
+#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW__SHIFT            0x0
+#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_BASE_LOW__DOORBELL_SELFRING_GPA_APER_BASE_LOW_MASK              0xFFFFFFFFL
+//BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL
+#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN__SHIFT                      0x0
+#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE__SHIFT                    0x1
+#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE__SHIFT                    0x8
+#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_EN_MASK                        0x00000001L
+#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_MODE_MASK                      0x00000002L
+#define BIF_BX_PF1_DOORBELL_SELFRING_GPA_APER_CNTL__DOORBELL_SELFRING_GPA_APER_SIZE_MASK                      0x000FFF00L
+//BIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL
+#define BIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR__SHIFT                                    0x0
+#define BIF_BX_PF1_HDP_REG_COHERENCY_FLUSH_CNTL__HDP_REG_FLUSH_ADDR_MASK                                      0x00000001L
+//BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL
+#define BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR__SHIFT                                    0x0
+#define BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_CNTL__HDP_MEM_FLUSH_ADDR_MASK                                      0x00000001L
+//BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL
+#define BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR__SHIFT                          0x0
+#define BIF_BX_PF1_HDP_MEM_COHERENCY_FLUSH_ONLY_CNTL__HDP_MEM_FLUSH_ONLY_ADDR_MASK                            0x00000001L
+//BIF_BX_PF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL
+#define BIF_BX_PF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR__SHIFT                0x0
+#define BIF_BX_PF1_HDP_MEM_COHERENCY_INVALIDATE_ONLY_CNTL__HDP_MEM_INVALIDATE_ONLY_ADDR_MASK                  0x00000001L
+//BIF_BX_PF1_GPU_HDP_FLUSH_REQ
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP0__SHIFT                                                              0x0
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP1__SHIFT                                                              0x1
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP2__SHIFT                                                              0x2
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP3__SHIFT                                                              0x3
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP4__SHIFT                                                              0x4
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP5__SHIFT                                                              0x5
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP6__SHIFT                                                              0x6
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP7__SHIFT                                                              0x7
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP8__SHIFT                                                              0x8
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP9__SHIFT                                                              0x9
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__SDMA0__SHIFT                                                            0xa
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__SDMA1__SHIFT                                                            0xb
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG0__SHIFT                                                        0xc
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG1__SHIFT                                                        0xd
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG2__SHIFT                                                        0xe
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG3__SHIFT                                                        0xf
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG4__SHIFT                                                        0x10
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG5__SHIFT                                                        0x11
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG6__SHIFT                                                        0x12
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG7__SHIFT                                                        0x13
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG8__SHIFT                                                        0x14
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG9__SHIFT                                                        0x15
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG10__SHIFT                                                       0x16
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG11__SHIFT                                                       0x17
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG12__SHIFT                                                       0x18
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG13__SHIFT                                                       0x19
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG14__SHIFT                                                       0x1a
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG15__SHIFT                                                       0x1b
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG16__SHIFT                                                       0x1c
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG17__SHIFT                                                       0x1d
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG18__SHIFT                                                       0x1e
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG19__SHIFT                                                       0x1f
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP0_MASK                                                                0x00000001L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP1_MASK                                                                0x00000002L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP2_MASK                                                                0x00000004L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP3_MASK                                                                0x00000008L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP4_MASK                                                                0x00000010L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP5_MASK                                                                0x00000020L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP6_MASK                                                                0x00000040L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP7_MASK                                                                0x00000080L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP8_MASK                                                                0x00000100L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__CP9_MASK                                                                0x00000200L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__SDMA0_MASK                                                              0x00000400L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__SDMA1_MASK                                                              0x00000800L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG0_MASK                                                          0x00001000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG1_MASK                                                          0x00002000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG2_MASK                                                          0x00004000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG3_MASK                                                          0x00008000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG4_MASK                                                          0x00010000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG5_MASK                                                          0x00020000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG6_MASK                                                          0x00040000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG7_MASK                                                          0x00080000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG8_MASK                                                          0x00100000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG9_MASK                                                          0x00200000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG10_MASK                                                         0x00400000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG11_MASK                                                         0x00800000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG12_MASK                                                         0x01000000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG13_MASK                                                         0x02000000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG14_MASK                                                         0x04000000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG15_MASK                                                         0x08000000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG16_MASK                                                         0x10000000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG17_MASK                                                         0x20000000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG18_MASK                                                         0x40000000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_REQ__RSVD_ENG19_MASK                                                         0x80000000L
+//BIF_BX_PF1_GPU_HDP_FLUSH_DONE
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP0__SHIFT                                                             0x0
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP1__SHIFT                                                             0x1
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP2__SHIFT                                                             0x2
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP3__SHIFT                                                             0x3
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP4__SHIFT                                                             0x4
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP5__SHIFT                                                             0x5
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP6__SHIFT                                                             0x6
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP7__SHIFT                                                             0x7
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP8__SHIFT                                                             0x8
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP9__SHIFT                                                             0x9
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__SDMA0__SHIFT                                                           0xa
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__SDMA1__SHIFT                                                           0xb
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG0__SHIFT                                                       0xc
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG1__SHIFT                                                       0xd
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG2__SHIFT                                                       0xe
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG3__SHIFT                                                       0xf
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG4__SHIFT                                                       0x10
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG5__SHIFT                                                       0x11
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG6__SHIFT                                                       0x12
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG7__SHIFT                                                       0x13
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG8__SHIFT                                                       0x14
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG9__SHIFT                                                       0x15
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG10__SHIFT                                                      0x16
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG11__SHIFT                                                      0x17
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG12__SHIFT                                                      0x18
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG13__SHIFT                                                      0x19
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG14__SHIFT                                                      0x1a
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG15__SHIFT                                                      0x1b
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG16__SHIFT                                                      0x1c
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG17__SHIFT                                                      0x1d
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG18__SHIFT                                                      0x1e
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG19__SHIFT                                                      0x1f
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP0_MASK                                                               0x00000001L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP1_MASK                                                               0x00000002L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP2_MASK                                                               0x00000004L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP3_MASK                                                               0x00000008L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP4_MASK                                                               0x00000010L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP5_MASK                                                               0x00000020L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP6_MASK                                                               0x00000040L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP7_MASK                                                               0x00000080L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP8_MASK                                                               0x00000100L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__CP9_MASK                                                               0x00000200L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__SDMA0_MASK                                                             0x00000400L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__SDMA1_MASK                                                             0x00000800L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG0_MASK                                                         0x00001000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG1_MASK                                                         0x00002000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG2_MASK                                                         0x00004000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG3_MASK                                                         0x00008000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG4_MASK                                                         0x00010000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG5_MASK                                                         0x00020000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG6_MASK                                                         0x00040000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG7_MASK                                                         0x00080000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG8_MASK                                                         0x00100000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG9_MASK                                                         0x00200000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG10_MASK                                                        0x00400000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG11_MASK                                                        0x00800000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG12_MASK                                                        0x01000000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG13_MASK                                                        0x02000000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG14_MASK                                                        0x04000000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG15_MASK                                                        0x08000000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG16_MASK                                                        0x10000000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG17_MASK                                                        0x20000000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG18_MASK                                                        0x40000000L
+#define BIF_BX_PF1_GPU_HDP_FLUSH_DONE__RSVD_ENG19_MASK                                                        0x80000000L
+//BIF_BX_PF1_BIF_TRANS_PENDING
+#define BIF_BX_PF1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING__SHIFT                                            0x0
+#define BIF_BX_PF1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING__SHIFT                                            0x1
+#define BIF_BX_PF1_BIF_TRANS_PENDING__BIF_MST_TRANS_PENDING_MASK                                              0x00000001L
+#define BIF_BX_PF1_BIF_TRANS_PENDING__BIF_SLV_TRANS_PENDING_MASK                                              0x00000002L
+//BIF_BX_PF1_NBIF_GFX_ADDR_LUT_BYPASS
+#define BIF_BX_PF1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS__SHIFT                                                0x0
+#define BIF_BX_PF1_NBIF_GFX_ADDR_LUT_BYPASS__LUT_BYPASS_MASK                                                  0x00000001L
+//BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0
+#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA__SHIFT                                                 0x0
+#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW0__MSGBUF_DATA_MASK                                                   0xFFFFFFFFL
+//BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1
+#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA__SHIFT                                                 0x0
+#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW1__MSGBUF_DATA_MASK                                                   0xFFFFFFFFL
+//BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2
+#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA__SHIFT                                                 0x0
+#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW2__MSGBUF_DATA_MASK                                                   0xFFFFFFFFL
+//BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3
+#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA__SHIFT                                                 0x0
+#define BIF_BX_PF1_MAILBOX_MSGBUF_TRN_DW3__MSGBUF_DATA_MASK                                                   0xFFFFFFFFL
+//BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0
+#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA__SHIFT                                                 0x0
+#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW0__MSGBUF_DATA_MASK                                                   0xFFFFFFFFL
+//BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1
+#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA__SHIFT                                                 0x0
+#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW1__MSGBUF_DATA_MASK                                                   0xFFFFFFFFL
+//BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2
+#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA__SHIFT                                                 0x0
+#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW2__MSGBUF_DATA_MASK                                                   0xFFFFFFFFL
+//BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3
+#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA__SHIFT                                                 0x0
+#define BIF_BX_PF1_MAILBOX_MSGBUF_RCV_DW3__MSGBUF_DATA_MASK                                                   0xFFFFFFFFL
+//BIF_BX_PF1_MAILBOX_CONTROL
+#define BIF_BX_PF1_MAILBOX_CONTROL__TRN_MSG_VALID__SHIFT                                                      0x0
+#define BIF_BX_PF1_MAILBOX_CONTROL__TRN_MSG_ACK__SHIFT                                                        0x1
+#define BIF_BX_PF1_MAILBOX_CONTROL__RCV_MSG_VALID__SHIFT                                                      0x8
+#define BIF_BX_PF1_MAILBOX_CONTROL__RCV_MSG_ACK__SHIFT                                                        0x9
+#define BIF_BX_PF1_MAILBOX_CONTROL__TRN_MSG_VALID_MASK                                                        0x00000001L
+#define BIF_BX_PF1_MAILBOX_CONTROL__TRN_MSG_ACK_MASK                                                          0x00000002L
+#define BIF_BX_PF1_MAILBOX_CONTROL__RCV_MSG_VALID_MASK                                                        0x00000100L
+#define BIF_BX_PF1_MAILBOX_CONTROL__RCV_MSG_ACK_MASK                                                          0x00000200L
+//BIF_BX_PF1_MAILBOX_INT_CNTL
+#define BIF_BX_PF1_MAILBOX_INT_CNTL__VALID_INT_EN__SHIFT                                                      0x0
+#define BIF_BX_PF1_MAILBOX_INT_CNTL__ACK_INT_EN__SHIFT                                                        0x1
+#define BIF_BX_PF1_MAILBOX_INT_CNTL__VALID_INT_EN_MASK                                                        0x00000001L
+#define BIF_BX_PF1_MAILBOX_INT_CNTL__ACK_INT_EN_MASK                                                          0x00000002L
+//BIF_BX_PF1_BIF_VMHV_MAILBOX
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN__SHIFT                                      0x0
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN__SHIFT                                    0x1
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA__SHIFT                                         0x8
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID__SHIFT                                        0xf
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA__SHIFT                                         0x10
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID__SHIFT                                        0x17
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK__SHIFT                                          0x18
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK__SHIFT                                          0x19
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_ACK_INTR_EN_MASK                                        0x00000001L
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_VALID_INTR_EN_MASK                                      0x00000002L
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_DATA_MASK                                           0x00000F00L
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_VALID_MASK                                          0x00008000L
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_DATA_MASK                                           0x000F0000L
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_VALID_MASK                                          0x00800000L
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_TRN_MSG_ACK_MASK                                            0x01000000L
+#define BIF_BX_PF1_BIF_VMHV_MAILBOX__VMHV_MAILBOX_RCV_MSG_ACK_MASK                                            0x02000000L
+//BIF_BX_PF1_PARTITION_COMPUTE_CAP
+#define BIF_BX_PF1_PARTITION_COMPUTE_CAP__SPX_SUPPORT__SHIFT                                                  0x0
+#define BIF_BX_PF1_PARTITION_COMPUTE_CAP__DPX_SUPPORT__SHIFT                                                  0x1
+#define BIF_BX_PF1_PARTITION_COMPUTE_CAP__TPX_SUPPORT__SHIFT                                                  0x2
+#define BIF_BX_PF1_PARTITION_COMPUTE_CAP__QPX_SUPPORT__SHIFT                                                  0x3
+#define BIF_BX_PF1_PARTITION_COMPUTE_CAP__CPX_SUPPORT__SHIFT                                                  0x4
+#define BIF_BX_PF1_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY__SHIFT                                             0xa
+#define BIF_BX_PF1_PARTITION_COMPUTE_CAP__SPX_SUPPORT_MASK                                                    0x00000001L
+#define BIF_BX_PF1_PARTITION_COMPUTE_CAP__DPX_SUPPORT_MASK                                                    0x00000002L
+#define BIF_BX_PF1_PARTITION_COMPUTE_CAP__TPX_SUPPORT_MASK                                                    0x00000004L
+#define BIF_BX_PF1_PARTITION_COMPUTE_CAP__QPX_SUPPORT_MASK                                                    0x00000008L
+#define BIF_BX_PF1_PARTITION_COMPUTE_CAP__CPX_SUPPORT_MASK                                                    0x00000010L
+#define BIF_BX_PF1_PARTITION_COMPUTE_CAP__CPX_AVAILABILITY_MASK                                               0x0003FC00L
+//BIF_BX_PF1_PARTITION_MEM_CAP
+#define BIF_BX_PF1_PARTITION_MEM_CAP__NPS1_SUPPORT__SHIFT                                                     0x0
+#define BIF_BX_PF1_PARTITION_MEM_CAP__NPS2_SUPPORT__SHIFT                                                     0x1
+#define BIF_BX_PF1_PARTITION_MEM_CAP__NPS3_SUPPORT__SHIFT                                                     0x2
+#define BIF_BX_PF1_PARTITION_MEM_CAP__NPS4_SUPPORT__SHIFT                                                     0x3
+#define BIF_BX_PF1_PARTITION_MEM_CAP__NPS6_SUPPORT__SHIFT                                                     0x5
+#define BIF_BX_PF1_PARTITION_MEM_CAP__NPS8_SUPPORT__SHIFT                                                     0x7
+#define BIF_BX_PF1_PARTITION_MEM_CAP__NPS1_SUPPORT_MASK                                                       0x00000001L
+#define BIF_BX_PF1_PARTITION_MEM_CAP__NPS2_SUPPORT_MASK                                                       0x00000002L
+#define BIF_BX_PF1_PARTITION_MEM_CAP__NPS3_SUPPORT_MASK                                                       0x00000004L
+#define BIF_BX_PF1_PARTITION_MEM_CAP__NPS4_SUPPORT_MASK                                                       0x00000008L
+#define BIF_BX_PF1_PARTITION_MEM_CAP__NPS6_SUPPORT_MASK                                                       0x00000020L
+#define BIF_BX_PF1_PARTITION_MEM_CAP__NPS8_SUPPORT_MASK                                                       0x00000080L
+//BIF_BX_PF1_PARTITION_COMPUTE_STATUS
+#define BIF_BX_PF1_PARTITION_COMPUTE_STATUS__PARTITION_MODE__SHIFT                                            0x4
+#define BIF_BX_PF1_PARTITION_COMPUTE_STATUS__PARTITION_MODE_MASK                                              0x000000F0L
+//BIF_BX_PF1_PARTITION_MEM_STATUS
+#define BIF_BX_PF1_PARTITION_MEM_STATUS__CHANGE_STATUS__SHIFT                                                 0x0
+#define BIF_BX_PF1_PARTITION_MEM_STATUS__NPS_MODE__SHIFT                                                      0x4
+#define BIF_BX_PF1_PARTITION_MEM_STATUS__CHANGE_STATUS_MASK                                                   0x0000000FL
+#define BIF_BX_PF1_PARTITION_MEM_STATUS__NPS_MODE_MASK                                                        0x00000FF0L
+
+
+// addressBlock: nbif0_nbif0_rcc_strap_BIFDEC1:1
+//RCC_STRAP2_RCC_BIF_STRAP0
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_GEN4_DIS__SHIFT                                                      0x0
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_EXPANSION_ROM_VALIDATION_SUPPORT__SHIFT                              0x1
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_PX_CAPABLE__SHIFT                                                    0x7
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3__SHIFT                                                 0x8
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN__SHIFT                                  0x9
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR__SHIFT                                         0xa
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN__SHIFT                                     0xb
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR__SHIFT                                              0xc
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR__SHIFT                                             0xd
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_AUD_PIN__SHIFT                                                       0x12
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN__SHIFT                                               0x14
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIF_GFX_IOBAR_DIS_AND_REGBAR_64BIT_EN__SHIFT                         0x15
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_GPUIOV_EN__SHIFT                                                     0x16
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_OVERRIDE__SHIFT                                          0x17
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_GEN3_DIS__SHIFT                                                      0x18
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4__SHIFT                                                 0x19
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_QUICKSIM_START__SHIFT                                                0x1a
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING__SHIFT                                     0x1b
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_IGNORE_LOCAL_PREFIX_UR_SWUS__SHIFT                                   0x1c
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN__SHIFT                                      0x1d
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE__SHIFT                                                   0x1e
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN__SHIFT                                            0x1f
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_GEN4_DIS_MASK                                                        0x00000001L
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_EXPANSION_ROM_VALIDATION_SUPPORT_MASK                                0x00000002L
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK                                                      0x00000080L
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN3_MASK                                                   0x00000100L
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_MSI_FIRST_BE_FULL_PAYLOAD_EN_MASK                                    0x00000200L
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_NBIF_IGNORE_ERR_INFLR_MASK                                           0x00000400L
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_PME_SUPPORT_COMPLIANCE_EN_MASK                                       0x00000800L
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_EP_ERR_MASK                                                0x00001000L
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_RX_IGNORE_MSG_ERR_MASK                                               0x00002000L
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_AUD_PIN_MASK                                                         0x000C0000L
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_PIN_MASK                                                 0x00100000L
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIF_GFX_IOBAR_DIS_AND_REGBAR_64BIT_EN_MASK                           0x00200000L
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_GPUIOV_EN_MASK                                                       0x00400000L
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIOS_ROM_EN_OVERRIDE_MASK                                            0x00800000L
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_GEN3_DIS_MASK                                                        0x01000000L
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIF_KILL_GEN4_MASK                                                   0x02000000L
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_QUICKSIM_START_MASK                                                  0x04000000L
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_NO_RO_ENABLED_P2P_PASSING_MASK                                       0x08000000L
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_IGNORE_LOCAL_PREFIX_UR_SWUS_MASK                                     0x10000000L
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_CFG0_RD_VF_BUSNUM_CHK_EN_MASK                                        0x20000000L
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_BIGAPU_MODE_MASK                                                     0x40000000L
+#define RCC_STRAP2_RCC_BIF_STRAP0__STRAP_LINK_DOWN_RESET_EN_MASK                                              0x80000000L
+//RCC_STRAP2_RCC_BIF_STRAP1
+#define RCC_STRAP2_RCC_BIF_STRAP1__FUSESTRAP_VALID__SHIFT                                                     0x0
+#define RCC_STRAP2_RCC_BIF_STRAP1__ROMSTRAP_VALID__SHIFT                                                      0x1
+#define RCC_STRAP2_RCC_BIF_STRAP1__WRITE_DISABLE__SHIFT                                                       0x2
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN__SHIFT                                      0x3
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_FLIT_MODE_SUPPORT__SHIFT                                             0x4
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS__SHIFT                                     0x5
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE__SHIFT                                       0x6
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_MARGINING_READY__SHIFT                                               0x7
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN__SHIFT                                                  0x8
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN__SHIFT                                                 0x9
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE__SHIFT                                                  0xa
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE__SHIFT                                        0xc
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_HWREV_LSB2__SHIFT                                                    0xd
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWREV_LSB2__SHIFT                                                    0xf
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY__SHIFT                                             0x11
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS__SHIFT                                             0x12
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_DLF_EN__SHIFT                                                        0x13
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_PHY_16GT_EN__SHIFT                                                   0x14
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_MARGIN_EN__SHIFT                                                     0x15
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN__SHIFT                                             0x16
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN__SHIFT                                     0x17
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE__SHIFT                                             0x1a
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_GSI_SMN_POSTWR_MULTI_EN__SHIFT                                       0x1b
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_DLF_EN_EP__SHIFT                                                     0x1d
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_AP_EN__SHIFT                                                         0x1e
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_AP_EN_DN__SHIFT                                                      0x1f
+#define RCC_STRAP2_RCC_BIF_STRAP1__FUSESTRAP_VALID_MASK                                                       0x00000001L
+#define RCC_STRAP2_RCC_BIF_STRAP1__ROMSTRAP_VALID_MASK                                                        0x00000002L
+#define RCC_STRAP2_RCC_BIF_STRAP1__WRITE_DISABLE_MASK                                                         0x00000004L
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_ECRC_INTERMEDIATE_CHK_EN_MASK                                        0x00000008L
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_FLIT_MODE_SUPPORT_MASK                                               0x00000010L
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_IGNORE_E2E_PREFIX_UR_SWUS_MASK                                       0x00000020L
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_MARGINING_USES_SOFTWARE_MASK                                         0x00000040L
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_MARGINING_READY_MASK                                                 0x00000080L
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_APER_EN_MASK                                                    0x00000100L
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_64BAR_EN_MASK                                                   0x00000200L
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_AP_SIZE_MASK                                                    0x00000C00L
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWUS_APER_PREFETCHABLE_MASK                                          0x00001000L
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_HWREV_LSB2_MASK                                                      0x00006000L
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_SWREV_LSB2_MASK                                                      0x00018000L
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_LINK_RST_CFG_ONLY_MASK                                               0x00020000L
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_BIF_IOV_LKRST_DIS_MASK                                               0x00040000L
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_DLF_EN_MASK                                                          0x00080000L
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_PHY_16GT_EN_MASK                                                     0x00100000L
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_MARGIN_EN_MASK                                                       0x00200000L
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_BIF_PSN_UR_RPT_EN_MASK                                               0x00400000L
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_BIF_SLOT_POWER_SUPPORT_EN_MASK                                       0x00800000L
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_GFX_FUNC_LTR_MODE_MASK                                               0x04000000L
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_GSI_SMN_POSTWR_MULTI_EN_MASK                                         0x18000000L
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_DLF_EN_EP_MASK                                                       0x20000000L
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_AP_EN_MASK                                                           0x40000000L
+#define RCC_STRAP2_RCC_BIF_STRAP1__STRAP_AP_EN_DN_MASK                                                        0x80000000L
+//RCC_STRAP2_RCC_BIF_STRAP10
+//RCC_STRAP2_RCC_BIF_STRAP11
+//RCC_STRAP2_RCC_BIF_STRAP12
+//RCC_STRAP2_RCC_BIF_STRAP13
+#define RCC_STRAP2_RCC_BIF_STRAP13__STRAP_PCIE_SMN_APER__SHIFT                                                0x0
+#define RCC_STRAP2_RCC_BIF_STRAP13__STRAP_PCIE_SMN_APER_MASK                                                  0x00000FFFL
+//RCC_STRAP2_RCC_BIF_STRAP2
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE__SHIFT                                     0x0
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SWUS_SPT__SHIFT                                                      0x1
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SWDS_SPT__SHIFT                                                      0x2
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS__SHIFT                                            0x3
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS__SHIFT                                            0x4
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA__SHIFT                                        0x5
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA__SHIFT                                      0x6
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS__SHIFT                                 0x8
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS__SHIFT                                        0x9
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN__SHIFT                                   0xa
+#define RCC_STRAP2_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2__SHIFT                                                 0xd
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS__SHIFT                                             0xe
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN__SHIFT                                 0xf
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE__SHIFT                                         0x10
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS__SHIFT                                        0x18
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_ARI_EN_UP__SHIFT                                                     0x19
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_VLINK_PMETO_LDN_EXIT_BY_LNKRST_DIS__SHIFT                            0x1f
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_PCIESWUS_INDEX_APER_RANGE_MASK                                       0x00000001L
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SWUS_SPT_MASK                                                        0x00000002L
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SWDS_SPT_MASK                                                        0x00000004L
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SUC_IND_ACCESS_DIS_MASK                                              0x00000008L
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SUM_IND_ACCESS_DIS_MASK                                              0x00000010L
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_ENDP_LINKDOWN_DROP_DMA_MASK                                          0x00000020L
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_SWITCH_LINKDOWN_DROP_DMA_MASK                                        0x00000040L
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_GMI_DNS_SDP_CLKREQ_TOGGLE_DIS_MASK                                   0x00000100L
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_ACS_MSKSEV_EP_HIDE_DIS_MASK                                          0x00000200L
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_CFG_PG_FW_INTERLOCK_EXIT_EN_MASK                                     0x00000C00L
+#define RCC_STRAP2_RCC_BIF_STRAP2__RESERVED_BIF_STRAP2_MASK                                                   0x00002000L
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_LTR_IN_ASPML1_DIS_MASK                                               0x00004000L
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_GFXAZ_POWERSTATE_INTERLOCK_EN_MASK                                   0x00008000L
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_CYCLE_MASK                                           0x00FF0000L
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_PWRBRK_DEGLITCH_BYPASS_MASK                                          0x01000000L
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_ARI_EN_UP_MASK                                                       0x02000000L
+#define RCC_STRAP2_RCC_BIF_STRAP2__STRAP_VLINK_PMETO_LDN_EXIT_BY_LNKRST_DIS_MASK                              0x80000000L
+//RCC_STRAP2_RCC_BIF_STRAP3
+#define RCC_STRAP2_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER__SHIFT                                         0x0
+#define RCC_STRAP2_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER__SHIFT                                       0x10
+#define RCC_STRAP2_RCC_BIF_STRAP3__STRAP_VLINK_ASPM_IDLE_TIMER_MASK                                           0x0000FFFFL
+#define RCC_STRAP2_RCC_BIF_STRAP3__STRAP_VLINK_PM_L1_ENTRY_TIMER_MASK                                         0xFFFF0000L
+//RCC_STRAP2_RCC_BIF_STRAP4
+#define RCC_STRAP2_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER__SHIFT                                          0x0
+#define RCC_STRAP2_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER__SHIFT                                           0x10
+#define RCC_STRAP2_RCC_BIF_STRAP4__STRAP_VLINK_L0S_EXIT_TIMER_MASK                                            0x0000FFFFL
+#define RCC_STRAP2_RCC_BIF_STRAP4__STRAP_VLINK_L1_EXIT_TIMER_MASK                                             0xFFFF0000L
+//RCC_STRAP2_RCC_BIF_STRAP5
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER__SHIFT                                         0x0
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN__SHIFT                                      0x10
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN__SHIFT                                   0x11
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS__SHIFT                                    0x12
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS__SHIFT                                        0x13
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS__SHIFT                                    0x14
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_REG_PROTECTION_DIS__SHIFT                                            0x15
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE__SHIFT                                         0x16
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE__SHIFT                          0x18
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                0x19
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                 0x1b
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER__SHIFT                                           0x1c
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_BIF_GFX_REG_APER_REMAPPING_EN__SHIFT                                 0x1f
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ENTRY_TIMER_MASK                                           0x0000FFFFL
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_LDN_EN_MASK                                        0x00010000L
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_LDN_ON_SWUS_SECRST_EN_MASK                                     0x00020000L
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_VLINK_ENTER_COMPLIANCE_DIS_MASK                                      0x00040000L
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_IGNORE_PSN_ON_VDM1_DIS_MASK                                          0x00080000L
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_SMN_ERR_STATUS_MASK_EN_UPS_MASK                                      0x00100000L
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_REG_PROTECTION_DIS_MASK                                              0x00200000L
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_SMN_ERRRSP_DATA_FORCE_MASK                                           0x00C00000L
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_INTERMEDIATERSP_DATA_ALLF_DATA_FORCE_MASK                            0x01000000L
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_SUPPORTED_MASK                                  0x06000000L
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_EMER_POWER_REDUCTION_INIT_REQ_MASK                                   0x08000000L
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_PWRBRK_STATUS_TIMER_MASK                                             0x70000000L
+#define RCC_STRAP2_RCC_BIF_STRAP5__STRAP_BIF_GFX_REG_APER_REMAPPING_EN_MASK                                   0x80000000L
+//RCC_STRAP2_RCC_BIF_STRAP6
+#define RCC_STRAP2_RCC_BIF_STRAP6__STRAP_GEN5_DIS__SHIFT                                                      0x0
+#define RCC_STRAP2_RCC_BIF_STRAP6__STRAP_BIF_KILL_GEN5__SHIFT                                                 0x1
+#define RCC_STRAP2_RCC_BIF_STRAP6__STRAP_PHY_32GT_EN__SHIFT                                                   0x2
+#define RCC_STRAP2_RCC_BIF_STRAP6__STRAP_DOE_VERSION_SEL__SHIFT                                               0x3
+#define RCC_STRAP2_RCC_BIF_STRAP6__STRAP_PRODUCTION_MODE__SHIFT                                               0x5
+#define RCC_STRAP2_RCC_BIF_STRAP6__STRAP_MEM_AP_SIZE_PIN__SHIFT                                               0xa
+#define RCC_STRAP2_RCC_BIF_STRAP6__RESERVED_BIF_STRAP6__SHIFT                                                 0xf
+#define RCC_STRAP2_RCC_BIF_STRAP6__STRAP_GEN5_DIS_MASK                                                        0x00000001L
+#define RCC_STRAP2_RCC_BIF_STRAP6__STRAP_BIF_KILL_GEN5_MASK                                                   0x00000002L
+#define RCC_STRAP2_RCC_BIF_STRAP6__STRAP_PHY_32GT_EN_MASK                                                     0x00000004L
+#define RCC_STRAP2_RCC_BIF_STRAP6__STRAP_DOE_VERSION_SEL_MASK                                                 0x00000008L
+#define RCC_STRAP2_RCC_BIF_STRAP6__STRAP_PRODUCTION_MODE_MASK                                                 0x00000020L
+#define RCC_STRAP2_RCC_BIF_STRAP6__STRAP_MEM_AP_SIZE_PIN_MASK                                                 0x00007C00L
+#define RCC_STRAP2_RCC_BIF_STRAP6__RESERVED_BIF_STRAP6_MASK                                                   0xFFFF8000L
+//RCC_STRAP2_RCC_BIF_STRAP7
+#define RCC_STRAP2_RCC_BIF_STRAP7__STRAP_GEN6_DIS__SHIFT                                                      0x19
+#define RCC_STRAP2_RCC_BIF_STRAP7__STRAP_BIF_KILL_GEN6__SHIFT                                                 0x1a
+#define RCC_STRAP2_RCC_BIF_STRAP7__STRAP_GEN6_DIS_MASK                                                        0x02000000L
+#define RCC_STRAP2_RCC_BIF_STRAP7__STRAP_BIF_KILL_GEN6_MASK                                                   0x04000000L
+//RCC_STRAP2_RCC_BIF_STRAP8
+//RCC_STRAP2_RCC_BIF_STRAP9
+//RCC_STRAP2_RCC_DEV0_PORT_STRAP0
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0__SHIFT                                       0x0
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0__SHIFT                                          0x10
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0__SHIFT                                          0x11
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0__SHIFT                                          0x12
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0__SHIFT                                0x13
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_NEGO_GLOBAL_EN_DEV0__SHIFT                                     0x14
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0__SHIFT                                   0x15
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0__SHIFT                            0x18
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0__SHIFT                             0x19
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0__SHIFT                             0x1c
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0__SHIFT                                      0x1f
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_DEVICE_ID_DN_DEV0_MASK                                         0x0000FFFFL
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_ARI_EN_DN_DEV0_MASK                                            0x00010000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_ACS_EN_DN_DEV0_MASK                                            0x00020000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_AER_EN_DN_DEV0_MASK                                            0x00040000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_CPL_ABORT_ERR_EN_DN_DEV0_MASK                                  0x00080000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_NEGO_GLOBAL_EN_DEV0_MASK                                       0x00100000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_INTERRUPT_PIN_DN_DEV0_MASK                                     0x00E00000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_IGNORE_E2E_PREFIX_UR_DN_DEV0_MASK                              0x01000000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_MAX_PAYLOAD_SUPPORT_DN_DEV0_MASK                               0x0E000000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_MAX_LINK_WIDTH_SUPPORT_DEV0_MASK                               0x70000000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP0__STRAP_EPF0_DUMMY_EN_DEV0_MASK                                        0x80000000L
+//RCC_STRAP2_RCC_DEV0_PORT_STRAP1
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0__SHIFT                                       0x0
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0__SHIFT                                   0x10
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_ID_DN_DEV0_MASK                                         0x0000FFFFL
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP1__STRAP_SUBSYS_VEN_ID_DN_DEV0_MASK                                     0xFFFF0000L
+//RCC_STRAP2_RCC_DEV0_PORT_STRAP10
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DEV0__SHIFT                              0x0
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DN_DEV0__SHIFT                           0x1
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE1_SUPPORTED_DEV0__SHIFT                  0x2
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE2_SUPPORTED_DEV0__SHIFT                  0x3
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODEING_ON_DEV0__SHIFT                         0x4
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODE_REQUEST_DEV0__SHIFT                       0x5
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_MODIFIED_TS_INFOR1_DEV0__SHIFT                                0x6
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_GEN6_COMPLIANCE_DEV0__SHIFT                                   0x14
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_MAX_E2E_TLP_PREFIXES_DEV0__SHIFT                              0x18
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_MAX_E2E_TLP_PREFIXES_DN_DEV0__SHIFT                           0x1a
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DEV0_MASK                                0x00000001L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_NO_EQ_NEED_SUPPORTED_DN_DEV0_MASK                             0x00000002L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE1_SUPPORTED_DEV0_MASK                    0x00000004L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_MODIFID_TS_USAGE_MODE2_SUPPORTED_DEV0_MASK                    0x00000008L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODEING_ON_DEV0_MASK                           0x00000010L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_TRANSMITTER_PRECODE_REQUEST_DEV0_MASK                         0x00000020L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_MODIFIED_TS_INFOR1_DEV0_MASK                                  0x0007FFC0L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_GEN6_COMPLIANCE_DEV0_MASK                                     0x00100000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_MAX_E2E_TLP_PREFIXES_DEV0_MASK                                0x03000000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP10__STRAP_MAX_E2E_TLP_PREFIXES_DN_DEV0_MASK                             0x0C000000L
+//RCC_STRAP2_RCC_DEV0_PORT_STRAP11
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_MODIFIED_TS_VENDOR_ID_DEV0__SHIFT                             0x0
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_RTR_RESET_TIME_DN_DEV0__SHIFT                                 0x10
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_RTR_VALID_DN_DEV0__SHIFT                                      0x1c
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_RTR_EN_DN_DEV0__SHIFT                                         0x1d
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_SDPVW_REG_UPDATE_EN_DEV0__SHIFT                               0x1e
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_VF_14BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT                  0x1f
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_MODIFIED_TS_VENDOR_ID_DEV0_MASK                               0x0000FFFFL
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_RTR_RESET_TIME_DN_DEV0_MASK                                   0x0FFF0000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_RTR_VALID_DN_DEV0_MASK                                        0x10000000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_RTR_EN_DN_DEV0_MASK                                           0x20000000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_SDPVW_REG_UPDATE_EN_DEV0_MASK                                 0x40000000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP11__STRAP_VF_14BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK                    0x80000000L
+//RCC_STRAP2_RCC_DEV0_PORT_STRAP12
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP12__STRAP_MODIFIED_TS_INFOR2_DEV0__SHIFT                                0x0
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP12__STRAP_14BIT_TAG_COMPLETER_SUPPORTED_DEV0__SHIFT                     0x18
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP12__STRAP_14BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT                     0x19
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP12__STRAP_RECEIVER_L0P_SUPPORTED_DEV0__SHIFT                            0x1a
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP12__STRAP_PORT_L0P_EXIT_LATENCY_DEV0__SHIFT                             0x1b
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP12__STRAP_MODIFIED_TS_INFOR2_DEV0_MASK                                  0x00FFFFFFL
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP12__STRAP_14BIT_TAG_COMPLETER_SUPPORTED_DEV0_MASK                       0x01000000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP12__STRAP_14BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK                       0x02000000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP12__STRAP_RECEIVER_L0P_SUPPORTED_DEV0_MASK                              0x04000000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP12__STRAP_PORT_L0P_EXIT_LATENCY_DEV0_MASK                               0x38000000L
+//RCC_STRAP2_RCC_DEV0_PORT_STRAP13
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_COUNT_DEV0__SHIFT                          0x0
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_SELECTIVE_ENABLE_SUPPORTED_DEV0__SHIFT     0x8
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_DETAILS_DEV0__SHIFT                        0x9
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP13__STRAP_RTR_D3HOTD0_TIME_DN_DEV0__SHIFT                               0x14
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_COUNT_DEV0_MASK                            0x000000FFL
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_SELECTIVE_ENABLE_SUPPORTED_DEV0_MASK       0x00000100L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP13__STRAP_ALTERNATE_PROTOCOL_DETAILS_DEV0_MASK                          0x000FFE00L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP13__STRAP_RTR_D3HOTD0_TIME_DN_DEV0_MASK                                 0xFFF00000L
+//RCC_STRAP2_RCC_DEV0_PORT_STRAP14
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_CTO_LOGGING_SUPPORT_DEV0__SHIFT                               0x0
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_ACS_ENH_CAPABILITY_DN_DEV0__SHIFT                             0x1
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_COMMAND_COMPLETED_DEV0__SHIFT                                 0x2
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_ERR_COR_SUBCLASS_CAPABLE_DEV0__SHIFT                          0x3
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_DOE_EN_UP_DEV0__SHIFT                                         0x4
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_RX_MPS_FIXED_DEV0__SHIFT                                      0x5
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_RX_MPS_FIXED_DN_DEV0__SHIFT                                   0x6
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_IDE_EN_DEV0__SHIFT                                            0x7
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_RETIMER_L0P_EXIT_LATENCY_DEV0__SHIFT                          0x9
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_DEVICE3_EN_DN_DEV0__SHIFT                                     0xc
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_IDE_EN_DN_DEV0__SHIFT                                         0xd
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_CTO_LOGGING_SUPPORT_DEV0_MASK                                 0x00000001L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_ACS_ENH_CAPABILITY_DN_DEV0_MASK                               0x00000002L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_COMMAND_COMPLETED_DEV0_MASK                                   0x00000004L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_ERR_COR_SUBCLASS_CAPABLE_DEV0_MASK                            0x00000008L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_DOE_EN_UP_DEV0_MASK                                           0x00000010L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_RX_MPS_FIXED_DEV0_MASK                                        0x00000020L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_RX_MPS_FIXED_DN_DEV0_MASK                                     0x00000040L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_IDE_EN_DEV0_MASK                                              0x00000080L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_RETIMER_L0P_EXIT_LATENCY_DEV0_MASK                            0x00000E00L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_DEVICE3_EN_DN_DEV0_MASK                                       0x00001000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP14__STRAP_IDE_EN_DN_DEV0_MASK                                           0x00002000L
+//RCC_STRAP2_RCC_DEV0_PORT_STRAP15
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP15__STRAP_DSN_CODE_L_DN_DEV0__SHIFT                                     0x0
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP15__STRAP_DSN_CODE_L_DN_DEV0_MASK                                       0xFFFFFFFFL
+//RCC_STRAP2_RCC_DEV0_PORT_STRAP16
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP16__STRAP_DSN_CODE_H_DN_DEV0__SHIFT                                     0x0
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP16__STRAP_DSN_CODE_H_DN_DEV0_MASK                                       0xFFFFFFFFL
+//RCC_STRAP2_RCC_DEV0_PORT_STRAP17
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP17__STRAP_LINK_IDE_STREAM_SUPPORTED_DEV0__SHIFT                         0x0
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP17__STRAP_SELECTIVE_IDE_STREAM_SUPPORTED_DEV0__SHIFT                    0x1
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP17__STRAP_FLOW_THROUGH_IDE_STREAM_SUPPORTED_DEV0__SHIFT                 0x2
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP17__STRAP_PARTIAL_HDR_ENCRYPTION_SUPPORTED_DEV0__SHIFT                  0x3
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP17__STRAP_AGGREGATION_SUPPORTED_DEV0__SHIFT                             0x4
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP17__STRAP_PCRC_SUPPORTED_DEV0__SHIFT                                    0x5
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP17__STRAP_IDE_KM_PROTOCOL_SUPPORTED_DEV0__SHIFT                         0x6
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP17__STRAP_SELECTIVE_IDE_FOR_CFG_REQ_SUPPORTED_DEV0__SHIFT               0x7
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP17__STRAP_NUM_OF_TCS_SUPPORTED_FOR_LINK_IDE_DEV0__SHIFT                 0xd
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP17__STRAP_NUM_OF_SELECTIVE_IDE_STREAMS_SUPPORTED_DEV0__SHIFT            0x10
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP17__STRAP_TEE_LIMITED_SUPPORTED_DEV0__SHIFT                             0x18
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP17__STRAP_XT_SUPPORTED_DEV0__SHIFT                                      0x19
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP17__STRAP_LINK_IDE_STREAM_SUPPORTED_DEV0_MASK                           0x00000001L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP17__STRAP_SELECTIVE_IDE_STREAM_SUPPORTED_DEV0_MASK                      0x00000002L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP17__STRAP_FLOW_THROUGH_IDE_STREAM_SUPPORTED_DEV0_MASK                   0x00000004L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP17__STRAP_PARTIAL_HDR_ENCRYPTION_SUPPORTED_DEV0_MASK                    0x00000008L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP17__STRAP_AGGREGATION_SUPPORTED_DEV0_MASK                               0x00000010L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP17__STRAP_PCRC_SUPPORTED_DEV0_MASK                                      0x00000020L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP17__STRAP_IDE_KM_PROTOCOL_SUPPORTED_DEV0_MASK                           0x00000040L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP17__STRAP_SELECTIVE_IDE_FOR_CFG_REQ_SUPPORTED_DEV0_MASK                 0x00000080L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP17__STRAP_NUM_OF_TCS_SUPPORTED_FOR_LINK_IDE_DEV0_MASK                   0x0000E000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP17__STRAP_NUM_OF_SELECTIVE_IDE_STREAMS_SUPPORTED_DEV0_MASK              0x00FF0000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP17__STRAP_TEE_LIMITED_SUPPORTED_DEV0_MASK                               0x01000000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP17__STRAP_XT_SUPPORTED_DEV0_MASK                                        0x02000000L
+//RCC_STRAP2_RCC_DEV0_PORT_STRAP18
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP18__STRAP_NUM_ADDR_ASSOCIATION_REG_BLKS_DEV0__SHIFT                     0x0
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP18__STRAP_NUM_ADDR_ASSOCIATION_REG_BLKS_DEV0_MASK                       0x0000000FL
+//RCC_STRAP2_RCC_DEV0_PORT_STRAP2
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0__SHIFT                                 0x0
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0__SHIFT                                          0x1
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0__SHIFT                                      0x2
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0__SHIFT                                          0x3
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0__SHIFT                                      0x4
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0__SHIFT                                        0x5
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0__SHIFT                             0x7
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0__SHIFT                                0x8
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0__SHIFT                                    0x9
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0__SHIFT                              0xc
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0__SHIFT                      0xd
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0__SHIFT                                    0xe
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0__SHIFT                                            0xf
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0__SHIFT                                    0x10
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0__SHIFT                                    0x11
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0__SHIFT                             0x14
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0__SHIFT                                   0x17
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0__SHIFT                              0x1a
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0__SHIFT                                    0x1d
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_DE_EMPHASIS_SEL_DN_DEV0_MASK                                   0x00000001L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_DSN_EN_DN_DEV0_MASK                                            0x00000002L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_E2E_PREFIX_EN_DEV0_MASK                                        0x00000004L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_ECN1P1_EN_DEV0_MASK                                            0x00000008L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_CHECK_EN_DEV0_MASK                                        0x00000010L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_ECRC_GEN_EN_DEV0_MASK                                          0x00000020L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_FMT_SUPPORTED_DEV0_MASK                               0x00000080L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_EXTENDED_TAG_ECN_EN_DEV0_MASK                                  0x00000100L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_EXT_VC_COUNT_DN_DEV0_MASK                                      0x00000E00L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_FIRST_RCVD_ERR_LOG_DN_DEV0_MASK                                0x00001000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_POISONED_ADVISORY_NONFATAL_DN_DEV0_MASK                        0x00002000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_COMPLIANCE_DEV0_MASK                                      0x00004000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN2_EN_DEV0_MASK                                              0x00008000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN3_COMPLIANCE_DEV0_MASK                                      0x00010000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_GEN4_COMPLIANCE_DEV0_MASK                                      0x00020000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L0S_ACCEPTABLE_LATENCY_DEV0_MASK                               0x00700000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L0S_EXIT_LATENCY_DEV0_MASK                                     0x03800000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L1_ACCEPTABLE_LATENCY_DEV0_MASK                                0x1C000000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP2__STRAP_L1_EXIT_LATENCY_DEV0_MASK                                      0xE0000000L
+//RCC_STRAP2_RCC_DEV0_PORT_STRAP3
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0__SHIFT                     0x0
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0__SHIFT                                             0x1
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0__SHIFT                                          0x2
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0__SHIFT                                0x3
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0__SHIFT                                          0x6
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0__SHIFT                                  0x7
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0__SHIFT                                   0x8
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0__SHIFT                                     0x9
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT  0xb
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0__SHIFT  0xe
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0__SHIFT  0x12
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0__SHIFT  0x15
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0__SHIFT                                         0x19
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0__SHIFT                                      0x1b
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0__SHIFT                                       0x1d
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0__SHIFT                                         0x1f
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_LINK_BW_NOTIFICATION_CAP_DN_EN_DEV0_MASK                       0x00000001L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DEV0_MASK                                               0x00000002L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_LTR_EN_DN_DEV0_MASK                                            0x00000004L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_MAX_PAYLOAD_SUPPORT_DEV0_MASK                                  0x00000038L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_MSI_EN_DN_DEV0_MASK                                            0x00000040L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_MSTCPL_TIMEOUT_EN_DEV0_MASK                                    0x00000080L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_NO_SOFT_RESET_DN_DEV0_MASK                                     0x00000100L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_OBFF_SUPPORTED_DEV0_MASK                                       0x00000600L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK  0x00003800L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_DOWNSTREAM_PORT_TX_PRESET_DEV0_MASK  0x0003C000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_RX_PRESET_HINT_DEV0_MASK  0x001C0000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PCIE_LANE_EQUALIZATION_CNTL_UPSTREAM_PORT_TX_PRESET_DEV0_MASK  0x01E00000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DEV0_MASK                                           0x06000000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PM_SUPPORT_DN_DEV0_MASK                                        0x18000000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_ATOMIC_EN_DN_DEV0_MASK                                         0x20000000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP3__STRAP_PMC_DSI_DN_DEV0_MASK                                           0x80000000L
+//RCC_STRAP2_RCC_DEV0_PORT_STRAP4
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0__SHIFT                              0x0
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0__SHIFT                              0x8
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0__SHIFT                              0x10
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0__SHIFT                              0x18
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_0_DEV0_MASK                                0x000000FFL
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_1_DEV0_MASK                                0x0000FF00L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_2_DEV0_MASK                                0x00FF0000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP4__STRAP_PWR_BUDGET_DATA_8T0_3_DEV0_MASK                                0xFF000000L
+//RCC_STRAP2_RCC_DEV0_PORT_STRAP5
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0__SHIFT                              0x0
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0__SHIFT                              0x8
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0__SHIFT                        0x10
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0__SHIFT                                 0x11
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0__SHIFT                                  0x12
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0__SHIFT                                           0x13
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0__SHIFT                                           0x14
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0__SHIFT                                        0x15
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0__SHIFT                                0x16
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0__SHIFT                           0x17
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0__SHIFT                        0x18
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0__SHIFT                        0x19
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0__SHIFT                     0x1a
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0__SHIFT                         0x1b
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0__SHIFT                          0x1c
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0__SHIFT                       0x1d
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV0__SHIFT                                         0x1e
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0__SHIFT                                            0x1f
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_4_DEV0_MASK                                0x000000FFL
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_DATA_8T0_5_DEV0_MASK                                0x0000FF00L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_PWR_BUDGET_SYSTEM_ALLOCATED_DEV0_MASK                          0x00010000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_64BIT_EN_DN_DEV0_MASK                                   0x00020000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ATOMIC_ROUTING_EN_DEV0_MASK                                    0x00040000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_VC_EN_DN_DEV0_MASK                                             0x00080000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DEV0_MASK                                             0x00100000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_TwoVC_EN_DN_DEV0_MASK                                          0x00200000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_LOCAL_DLF_SUPPORTED_DEV0_MASK                                  0x00400000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_SOURCE_VALIDATION_DN_DEV0_MASK                             0x00800000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_TRANSLATION_BLOCKING_DN_DEV0_MASK                          0x01000000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_REQUEST_REDIRECT_DN_DEV0_MASK                          0x02000000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_COMPLETION_REDIRECT_DN_DEV0_MASK                       0x04000000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_UPSTREAM_FORWARDING_DN_DEV0_MASK                           0x08000000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_P2P_EGRESS_CONTROL_DN_DEV0_MASK                            0x10000000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_ACS_DIRECT_TRANSLATED_P2P_DN_DEV0_MASK                         0x20000000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_MSI_MAP_EN_DEV0_MASK                                           0x40000000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP5__STRAP_SSID_EN_DEV0_MASK                                              0x80000000L
+//RCC_STRAP2_RCC_DEV0_PORT_STRAP6
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0__SHIFT                                         0x0
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0__SHIFT                         0x1
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV0__SHIFT                                    0x2
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0__SHIFT                          0x3
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0__SHIFT                          0x4
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0__SHIFT                      0x5
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT                      0x6
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0__SHIFT                   0x7
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0__SHIFT     0x8
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0__SHIFT     0xc
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0__SHIFT                              0x10
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV0__SHIFT                            0x12
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV0__SHIFT                     0x13
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_GEN5_COMPLIANCE_DEV0__SHIFT                                    0x14
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_TARGET_LINK_SPEED_DEV0__SHIFT                                  0x15
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0__SHIFT     0x18
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0__SHIFT     0x1c
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_CFG_CRS_EN_DEV0_MASK                                           0x00000001L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_SMN_ERR_STATUS_MASK_EN_DNS_DEV0_MASK                           0x00000002L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_INTERNAL_ERR_EN_DEV0_MASK                                      0x00000004L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_RTM1_PRESENCE_DET_SUPPORT_DEV0_MASK                            0x00000008L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_RTM2_PRESENCE_DET_SUPPORT_DEV0_MASK                            0x00000010L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_COMPLETER_SUPPORTED_DEV0_MASK                        0x00000020L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK                        0x00000040L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_VF_10BIT_TAG_REQUESTER_SUPPORTED_DEV0_MASK                     0x00000080L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0_MASK       0x00000F00L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_16GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0_MASK       0x0000F000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_TPH_CPLR_SUPPORTED_DN_DEV0_MASK                                0x00030000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_MSI_EXT_MSG_DATA_CAP_DN_DEV0_MASK                              0x00040000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_NO_COMMAND_COMPLETED_SUPPORTED_DEV0_MASK                       0x00080000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_GEN5_COMPLIANCE_DEV0_MASK                                      0x00100000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_TARGET_LINK_SPEED_DEV0_MASK                                    0x00E00000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_DSP_TX_PRESET_DEV0_MASK       0x0F000000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP6__STRAP_PCIE_32GT_LANE_EQUALIZATION_CNTL_USP_TX_PRESET_DEV0_MASK       0xF0000000L
+//RCC_STRAP2_RCC_DEV0_PORT_STRAP7
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0__SHIFT                                        0x0
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0__SHIFT                                    0x8
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0__SHIFT                                    0xc
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0__SHIFT                                          0x10
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0__SHIFT                                          0x18
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0__SHIFT                                          0x1d
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_PORT_NUMBER_DEV0_MASK                                          0x000000FFL
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_MAJOR_REV_ID_DN_DEV0_MASK                                      0x00000F00L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_MINOR_REV_ID_DN_DEV0_MASK                                      0x0000F000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_RP_BUSNUM_DEV0_MASK                                            0x00FF0000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_DN_DEVNUM_DEV0_MASK                                            0x1F000000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP7__STRAP_DN_FUNCID_DEV0_MASK                                            0xE0000000L
+//RCC_STRAP2_RCC_DEV0_PORT_STRAP8
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0__SHIFT                              0x0
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0__SHIFT                              0x8
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0__SHIFT                              0x10
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0__SHIFT                              0x18
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_6_DEV0_MASK                                0x000000FFL
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_7_DEV0_MASK                                0x0000FF00L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_8_DEV0_MASK                                0x00FF0000L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP8__STRAP_PWR_BUDGET_DATA_8T0_9_DEV0_MASK                                0xFF000000L
+//RCC_STRAP2_RCC_DEV0_PORT_STRAP9
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0__SHIFT                              0x0
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0__SHIFT                              0x8
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV0__SHIFT                                       0x10
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_a_DEV0_MASK                                0x000000FFL
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP9__STRAP_PWR_BUDGET_DATA_8T0_b_DEV0_MASK                                0x0000FF00L
+#define RCC_STRAP2_RCC_DEV0_PORT_STRAP9__STRAP_VENDOR_ID_DN_DEV0_MASK                                         0xFFFF0000L
+//RCC_STRAP2_RCC_DEV0_EPF0_STRAP0
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT                                       0x0
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT                                    0x10
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0__SHIFT                                    0x14
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0__SHIFT                                      0x18
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0__SHIFT                                         0x1c
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0__SHIFT                           0x1d
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0__SHIFT                                      0x1e
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0__SHIFT                                      0x1f
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0_MASK                                         0x0000FFFFL
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0_MASK                                      0x000F0000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_MINOR_REV_ID_DEV0_F0_MASK                                      0x00F00000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_ATI_REV_ID_DEV0_F0_MASK                                        0x0F000000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_FUNC_EN_DEV0_F0_MASK                                           0x10000000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F0_MASK                             0x20000000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_D1_SUPPORT_DEV0_F0_MASK                                        0x40000000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP0__STRAP_D2_SUPPORT_DEV0_F0_MASK                                        0x80000000L
+//RCC_STRAP2_RCC_DEV0_EPF0_STRAP1
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0__SHIFT                              0x0
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0__SHIFT                       0x10
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F0_MASK                                0x0000FFFFL
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F0_MASK                         0xFFFF0000L
+//RCC_STRAP2_RCC_DEV0_EPF0_STRAP13
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0__SHIFT                                 0x0
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0__SHIFT                                 0x8
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0__SHIFT                                0x10
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_SRIOV_TOTAL_VFS_DEV0_F0__SHIFT                                0x18
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F0_MASK                                   0x000000FFL
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F0_MASK                                   0x0000FF00L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F0_MASK                                  0x00FF0000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP13__STRAP_SRIOV_TOTAL_VFS_DEV0_F0_MASK                                  0xFF000000L
+//RCC_STRAP2_RCC_DEV0_EPF0_STRAP14
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP14__STRAP_VENDOR_ID_DEV0_F0__SHIFT                                      0x0
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP14__STRAP_VENDOR_ID_DEV0_F0_MASK                                        0x0000FFFFL
+//RCC_STRAP2_RCC_DEV0_EPF0_STRAP15
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F0__SHIFT                                 0x0
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F0__SHIFT                                  0xc
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_VALID_DEV0_F0__SHIFT                                      0x18
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_INVALIDATE_QUEUE_DEPTH_DEV0_F0__SHIFT                     0x19
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_PAGE_ALIGNED_REQUEST_DEV0_F0__SHIFT                       0x1e
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F0_MASK                                   0x00000FFFL
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F0_MASK                                    0x00FFF000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_RTR_VALID_DEV0_F0_MASK                                        0x01000000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_INVALIDATE_QUEUE_DEPTH_DEV0_F0_MASK                       0x3E000000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP15__STRAP_ATS_PAGE_ALIGNED_REQUEST_DEV0_F0_MASK                         0x40000000L
+//RCC_STRAP2_RCC_DEV0_EPF0_STRAP16
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F0__SHIFT                                   0x0
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F0__SHIFT                               0xc
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F0_MASK                                     0x00000FFFL
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F0_MASK                                 0x00FFF000L
+//RCC_STRAP2_RCC_DEV0_EPF0_STRAP17
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F0__SHIFT                              0x0
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_VALID_DEV0_F0__SHIFT                                   0xc
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F0__SHIFT                                0xd
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F0_MASK                                0x00000FFFL
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_VALID_DEV0_F0_MASK                                     0x00001000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F0_MASK                                  0x01FFE000L
+//RCC_STRAP2_RCC_DEV0_EPF0_STRAP18
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F0__SHIFT                            0x0
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP18__STRAP_SRIOV_FUNC_DEP_LINK_DEV0_F0__SHIFT                            0xc
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F0_MASK                              0x00000FFFL
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP18__STRAP_SRIOV_FUNC_DEP_LINK_DEV0_F0_MASK                              0x000FF000L
+//RCC_STRAP2_RCC_DEV0_EPF0_STRAP19
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP19__STRAP_SRIOV_FIRST_VF_OFFSET_DEV0_F0__SHIFT                          0x0
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP19__STRAP_SRIOV_VF_STRIDE_DEV0_F0__SHIFT                                0x10
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP19__STRAP_SRIOV_FIRST_VF_OFFSET_DEV0_F0_MASK                            0x0000FFFFL
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP19__STRAP_SRIOV_VF_STRIDE_DEV0_F0_MASK                                  0xFFFF0000L
+//RCC_STRAP2_RCC_DEV0_EPF0_STRAP2
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0__SHIFT                                        0x0
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_RELAXED_ORDERING_SUPPORTED_DEV0_F0__SHIFT                      0x1
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_CAP_HIERARCHY_PRESERVED_DEV0_F0__SHIFT                     0x2
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_DEVICE3_EN_DEV0_F0__SHIFT                                      0x3
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_TEE_EXCLUSIVE_ATTR_SUPPORTED_DEV0_F0__SHIFT                    0x4
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0__SHIFT                                       0x6
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0__SHIFT                                   0x7
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0__SHIFT                                   0x8
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0__SHIFT                                 0x9
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0__SHIFT                          0xe
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0__SHIFT                                          0xf
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0__SHIFT                                          0x10
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0__SHIFT                                          0x11
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0__SHIFT                                          0x12
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0__SHIFT                                0x14
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0__SHIFT                                          0x15
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0__SHIFT                                          0x16
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0__SHIFT                                           0x17
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0__SHIFT                                   0x18
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0__SHIFT                                     0x1b
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0__SHIFT                                        0x1c
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0__SHIFT                  0x1d
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0__SHIFT               0x1e
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0__SHIFT                       0x1f
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_SRIOV_EN_DEV0_F0_MASK                                          0x00000001L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_RELAXED_ORDERING_SUPPORTED_DEV0_F0_MASK                        0x00000002L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_CAP_HIERARCHY_PRESERVED_DEV0_F0_MASK                       0x00000004L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_DEVICE3_EN_DEV0_F0_MASK                                        0x00000008L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_TEE_EXCLUSIVE_ATTR_SUPPORTED_DEV0_F0_MASK                      0x00000010L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_64BAR_DIS_DEV0_F0_MASK                                         0x00000040L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F0_MASK                                     0x00000080L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F0_MASK                                     0x00000100L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F0_MASK                                   0x00003E00L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F0_MASK                            0x00004000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_ARI_EN_DEV0_F0_MASK                                            0x00008000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_AER_EN_DEV0_F0_MASK                                            0x00010000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_ACS_EN_DEV0_F0_MASK                                            0x00020000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_ATS_EN_DEV0_F0_MASK                                            0x00040000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F0_MASK                                  0x00100000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_DPA_EN_DEV0_F0_MASK                                            0x00200000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_DSN_EN_DEV0_F0_MASK                                            0x00400000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_VC_EN_DEV0_F0_MASK                                             0x00800000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F0_MASK                                     0x07000000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F0_MASK                                       0x08000000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EN_DEV0_F0_MASK                                          0x10000000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F0_MASK                    0x20000000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F0_MASK                 0x40000000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F0_MASK                         0x80000000L
+//RCC_STRAP2_RCC_DEV0_EPF0_STRAP22
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP22__STRAP_GPUIOV_VSEC_LENGTH_DEV0_F0__SHIFT                             0x0
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP22__STRAP_MEM_AP_SIZE_DEV0_F0__SHIFT                                    0xc
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP22__STRAP_VF_MEM_AP_SIZE_DEV0_F0__SHIFT                                 0x11
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP22__STRAP_PF_RESIZABLE_BAR_DEFAULT_SIZE_DEV0_F0__SHIFT                  0x16
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP22__STRAP_VF_RESIZABLE_BAR_DEFAULT_SIZE_DEV0_F0__SHIFT                  0x1b
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP22__STRAP_GPUIOV_VSEC_LENGTH_DEV0_F0_MASK                               0x00000FFFL
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP22__STRAP_MEM_AP_SIZE_DEV0_F0_MASK                                      0x0001F000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP22__STRAP_VF_MEM_AP_SIZE_DEV0_F0_MASK                                   0x003E0000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP22__STRAP_PF_RESIZABLE_BAR_DEFAULT_SIZE_DEV0_F0_MASK                    0x07C00000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP22__STRAP_VF_RESIZABLE_BAR_DEFAULT_SIZE_DEV0_F0_MASK                    0xF8000000L
+//RCC_STRAP2_RCC_DEV0_EPF0_STRAP23
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP23__STRAP_DSN_CODE_L_DEV0_F0__SHIFT                                     0x0
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP23__STRAP_DSN_CODE_L_DEV0_F0_MASK                                       0xFFFFFFFFL
+//RCC_STRAP2_RCC_DEV0_EPF0_STRAP24
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP24__STRAP_DSN_CODE_H_DEV0_F0__SHIFT                                     0x0
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP24__STRAP_DSN_CODE_H_DEV0_F0_MASK                                       0xFFFFFFFFL
+//RCC_STRAP2_RCC_DEV0_EPF0_STRAP3
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0__SHIFT                                       0x0
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0__SHIFT                      0x10
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0__SHIFT                                          0x11
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0__SHIFT                                          0x12
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0__SHIFT                              0x13
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0__SHIFT                                         0x14
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0__SHIFT                                  0x15
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0__SHIFT                                         0x18
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_TRANSLATED_REQ_WITH_PASID_SUPPORTED_DEV0_F0__SHIFT             0x19
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0__SHIFT                        0x1a
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0__SHIFT                       0x1b
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0__SHIFT                                0x1c
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV0_F0__SHIFT                                       0x1d
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F0__SHIFT                               0x1e
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_RTR_EN_DEV0_F0__SHIFT                                          0x1f
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_SUBSYS_ID_DEV0_F0_MASK                                         0x0000FFFFL
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F0_MASK                        0x00010000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_PWR_EN_DEV0_F0_MASK                                            0x00020000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_EN_DEV0_F0_MASK                                            0x00040000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F0_MASK                                0x00080000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_EN_DEV0_F0_MASK                                           0x00100000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_MSIX_TABLE_BIR_DEV0_F0_MASK                                    0x00E00000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_PMC_DSI_DEV0_F0_MASK                                           0x01000000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_TRANSLATED_REQ_WITH_PASID_SUPPORTED_DEV0_F0_MASK               0x02000000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F0_MASK                          0x04000000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F0_MASK                         0x08000000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F0_MASK                                  0x10000000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_CLK_PM_EN_DEV0_F0_MASK                                         0x20000000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F0_MASK                                 0x40000000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP3__STRAP_RTR_EN_DEV0_F0_MASK                                            0x80000000L
+//RCC_STRAP2_RCC_DEV0_EPF0_STRAP4
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0__SHIFT                                 0x0
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_DOE_EN_DEV0_F0__SHIFT                                          0x12
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0__SHIFT                                 0x14
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0__SHIFT                                       0x15
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0__SHIFT                                          0x16
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0__SHIFT                                     0x17
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0__SHIFT                                   0x1c
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F0__SHIFT                                  0x1f
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_RESERVED_STRAP4_DEV0_F0_MASK                                   0x000003FFL
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_DOE_EN_DEV0_F0_MASK                                            0x00040000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F0_MASK                                   0x00100000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_ATOMIC_EN_DEV0_F0_MASK                                         0x00200000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_FLR_EN_DEV0_F0_MASK                                            0x00400000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_PME_SUPPORT_DEV0_F0_MASK                                       0x0F800000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F0_MASK                                     0x70000000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F0_MASK                                    0x80000000L
+//RCC_STRAP2_RCC_DEV0_EPF0_STRAP5
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0__SHIFT                                   0x0
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP5__STRAP_AUX_CURRENT_DEV0_F0__SHIFT                                     0x1b
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F0__SHIFT                            0x1e
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F0_MASK                                     0x0000FFFFL
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP5__STRAP_AUX_CURRENT_DEV0_F0_MASK                                       0x38000000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F0_MASK                              0x40000000L
+//RCC_STRAP2_RCC_DEV0_EPF0_STRAP8
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0__SHIFT                              0x0
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0__SHIFT                                0x3
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0__SHIFT                                     0x4
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0__SHIFT                                      0x7
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0__SHIFT                                   0x8
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0__SHIFT                                     0xd
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0__SHIFT                           0x10
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0__SHIFT                                  0x17
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0__SHIFT                                0x1b
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0__SHIFT                           0x1e
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_APER_SIZE_DEV0_F0_MASK                                0x00000007L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_DOORBELL_BAR_DIS_DEV0_F0_MASK                                  0x00000008L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_ROM_AP_SIZE_DEV0_F0_MASK                                       0x00000070L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_IO_BAR_DIS_DEV0_F0_MASK                                        0x00000080L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_LFB_ERRMSG_EN_DEV0_F0_MASK                                     0x00000100L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_REG_AP_SIZE_DEV0_F0_MASK                                       0x0000E000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_DOORBELL_APER_SIZE_DEV0_F0_MASK                             0x00070000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_REG_AP_SIZE_DEV0_F0_MASK                                    0x03800000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F0_MASK                                  0x38000000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F0_MASK                             0xC0000000L
+//RCC_STRAP2_RCC_DEV0_EPF0_STRAP9
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0__SHIFT                           0x0
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0__SHIFT                               0x12
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0__SHIFT                        0x13
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0__SHIFT                                 0x14
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_FB_ALWAYS_ON_DEV0_F0__SHIFT                                    0x15
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_FB_CPL_TYPE_SEL_DEV0_F0__SHIFT                                 0x16
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_GPUIOV_VSEC_REV_DEV0_F0__SHIFT                                 0x18
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_TEE_IO_SUPPORT_DEV0_F0__SHIFT                                  0x1c
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F0_MASK                             0x0000FFFFL
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_BAR_COMPLIANCE_EN_DEV0_F0_MASK                                 0x00040000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_NBIF_ROM_BAR_DIS_CHICKEN_DEV0_F0_MASK                          0x00080000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_VF_REG_PROT_DIS_DEV0_F0_MASK                                   0x00100000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_FB_ALWAYS_ON_DEV0_F0_MASK                                      0x00200000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_FB_CPL_TYPE_SEL_DEV0_F0_MASK                                   0x00C00000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_GPUIOV_VSEC_REV_DEV0_F0_MASK                                   0x0F000000L
+#define RCC_STRAP2_RCC_DEV0_EPF0_STRAP9__STRAP_TEE_IO_SUPPORT_DEV0_F0_MASK                                    0x10000000L
+//RCC_STRAP2_RCC_DEV0_EPF1_STRAP0
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1__SHIFT                                       0x0
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1__SHIFT                                    0x10
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1__SHIFT                                    0x14
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1__SHIFT                                         0x1c
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1__SHIFT                           0x1d
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1__SHIFT                                      0x1e
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1__SHIFT                                      0x1f
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_DEVICE_ID_DEV0_F1_MASK                                         0x0000FFFFL
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F1_MASK                                      0x000F0000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_MINOR_REV_ID_DEV0_F1_MASK                                      0x00F00000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_FUNC_EN_DEV0_F1_MASK                                           0x10000000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_LEGACY_DEVICE_TYPE_EN_DEV0_F1_MASK                             0x20000000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_D1_SUPPORT_DEV0_F1_MASK                                        0x40000000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP0__STRAP_D2_SUPPORT_DEV0_F1_MASK                                        0x80000000L
+//RCC_STRAP2_RCC_DEV0_EPF1_STRAP1
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F1__SHIFT                              0x0
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F1__SHIFT                       0x10
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP1__STRAP_SRIOV_VF_DEVICE_ID_DEV0_F1_MASK                                0x0000FFFFL
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP1__STRAP_SRIOV_SUPPORTED_PAGE_SIZE_DEV0_F1_MASK                         0xFFFF0000L
+//RCC_STRAP2_RCC_DEV0_EPF1_STRAP10
+//RCC_STRAP2_RCC_DEV0_EPF1_STRAP11
+//RCC_STRAP2_RCC_DEV0_EPF1_STRAP12
+//RCC_STRAP2_RCC_DEV0_EPF1_STRAP13
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F1__SHIFT                                 0x0
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F1__SHIFT                                 0x8
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F1__SHIFT                                0x10
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP13__STRAP_SRIOV_TOTAL_VFS_DEV0_F1__SHIFT                                0x18
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_PIF_DEV0_F1_MASK                                   0x000000FFL
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_SUB_DEV0_F1_MASK                                   0x0000FF00L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP13__STRAP_CLASS_CODE_BASE_DEV0_F1_MASK                                  0x00FF0000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP13__STRAP_SRIOV_TOTAL_VFS_DEV0_F1_MASK                                  0xFF000000L
+//RCC_STRAP2_RCC_DEV0_EPF1_STRAP14
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP14__STRAP_VENDOR_ID_DEV0_F1__SHIFT                                      0x0
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP14__STRAP_VENDOR_ID_DEV0_F1_MASK                                        0x0000FFFFL
+//RCC_STRAP2_RCC_DEV0_EPF1_STRAP15
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F1__SHIFT                                 0x0
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F1__SHIFT                                  0xc
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP15__STRAP_RTR_VALID_DEV0_F1__SHIFT                                      0x18
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP15__STRAP_RTR_RESET_TIME_DEV0_F1_MASK                                   0x00000FFFL
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP15__STRAP_RTR_DLUP_TIME_DEV0_F1_MASK                                    0x00FFF000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP15__STRAP_RTR_VALID_DEV0_F1_MASK                                        0x01000000L
+//RCC_STRAP2_RCC_DEV0_EPF1_STRAP16
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F1__SHIFT                                   0x0
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F1__SHIFT                               0xc
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP16__STRAP_RTR_FLR_TIME_DEV0_F1_MASK                                     0x00000FFFL
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP16__STRAP_RTR_D3HOTD0_TIME_DEV0_F1_MASK                                 0x00FFF000L
+//RCC_STRAP2_RCC_DEV0_EPF1_STRAP17
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F1__SHIFT                              0x0
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP17__STRAP_RTR_VF_VALID_DEV0_F1__SHIFT                                   0xc
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F1__SHIFT                                0xd
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP17__STRAP_RTR_VF_RESET_TIME_DEV0_F1_MASK                                0x00000FFFL
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP17__STRAP_RTR_VF_VALID_DEV0_F1_MASK                                     0x00001000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP17__STRAP_RTR_VF_FLR_TIME_DEV0_F1_MASK                                  0x01FFE000L
+//RCC_STRAP2_RCC_DEV0_EPF1_STRAP18
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F1__SHIFT                            0x0
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP18__STRAP_SRIOV_FUNC_DEP_LINK_DEV0_F1__SHIFT                            0xc
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP18__STRAP_RTR_VF_D3HOTD0_TIME_DEV0_F1_MASK                              0x00000FFFL
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP18__STRAP_SRIOV_FUNC_DEP_LINK_DEV0_F1_MASK                              0x000FF000L
+//RCC_STRAP2_RCC_DEV0_EPF1_STRAP19
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP19__STRAP_SRIOV_FIRST_VF_OFFSET_DEV0_F1__SHIFT                          0x0
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP19__STRAP_SRIOV_VF_STRIDE_DEV0_F1__SHIFT                                0x10
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP19__STRAP_SRIOV_FIRST_VF_OFFSET_DEV0_F1_MASK                            0x0000FFFFL
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP19__STRAP_SRIOV_VF_STRIDE_DEV0_F1_MASK                                  0xFFFF0000L
+//RCC_STRAP2_RCC_DEV0_EPF1_STRAP2
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_SRIOV_EN_DEV0_F1__SHIFT                                        0x0
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_ARI_CAP_HIERARCHY_PRESERVED_DEV0_F1__SHIFT                     0x2
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_DEVICE3_EN_DEV0_F1__SHIFT                                      0x3
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_TEE_EXCLUSIVE_ATTR_SUPPORTED_DEV0_F1__SHIFT                    0x4
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1__SHIFT                                   0x7
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1__SHIFT                                   0x8
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1__SHIFT                                 0x9
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1__SHIFT                          0xe
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1__SHIFT                                          0x10
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1__SHIFT                                          0x11
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1__SHIFT                                0x14
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1__SHIFT                                          0x15
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1__SHIFT                                   0x18
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F1__SHIFT                                     0x1b
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1__SHIFT                                        0x1c
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1__SHIFT                  0x1d
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1__SHIFT               0x1e
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1__SHIFT                       0x1f
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_SRIOV_EN_DEV0_F1_MASK                                          0x00000001L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_ARI_CAP_HIERARCHY_PRESERVED_DEV0_F1_MASK                       0x00000004L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_DEVICE3_EN_DEV0_F1_MASK                                        0x00000008L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_TEE_EXCLUSIVE_ATTR_SUPPORTED_DEV0_F1_MASK                      0x00000010L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_NO_SOFT_RESET_DEV0_F1_MASK                                     0x00000080L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_RESIZE_BAR_EN_DEV0_F1_MASK                                     0x00000100L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_MAX_PASID_WIDTH_DEV0_F1_MASK                                   0x00003E00L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_PERVECTOR_MASK_CAP_DEV0_F1_MASK                            0x00004000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_AER_EN_DEV0_F1_MASK                                            0x00010000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_ACS_EN_DEV0_F1_MASK                                            0x00020000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_CPL_ABORT_ERR_EN_DEV0_F1_MASK                                  0x00100000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_DPA_EN_DEV0_F1_MASK                                            0x00200000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_MSI_MULTI_CAP_DEV0_F1_MASK                                     0x07000000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PAGE_REQ_EN_DEV0_F1_MASK                                       0x08000000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EN_DEV0_F1_MASK                                          0x10000000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_EXE_PERMISSION_SUPPORTED_DEV0_F1_MASK                    0x20000000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_GLOBAL_INVALIDATE_SUPPORTED_DEV0_F1_MASK                 0x40000000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP2__STRAP_PASID_PRIV_MODE_SUPPORTED_DEV0_F1_MASK                         0x80000000L
+//RCC_STRAP2_RCC_DEV0_EPF1_STRAP20
+//RCC_STRAP2_RCC_DEV0_EPF1_STRAP21
+//RCC_STRAP2_RCC_DEV0_EPF1_STRAP23
+//RCC_STRAP2_RCC_DEV0_EPF1_STRAP24
+//RCC_STRAP2_RCC_DEV0_EPF1_STRAP3
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1__SHIFT                                       0x0
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1__SHIFT                      0x10
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1__SHIFT                                          0x11
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1__SHIFT                                          0x12
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1__SHIFT                              0x13
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1__SHIFT                                         0x14
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1__SHIFT                                         0x18
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_TRANSLATED_REQ_WITH_PASID_SUPPORTED_DEV0_F1__SHIFT             0x19
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1__SHIFT                        0x1a
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1__SHIFT                       0x1b
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F1__SHIFT                                0x1c
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV0_F1__SHIFT                                       0x1d
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F1__SHIFT                               0x1e
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_RTR_EN_DEV0_F1__SHIFT                                          0x1f
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_SUBSYS_ID_DEV0_F1_MASK                                         0x0000FFFFL
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_POISONED_ADVISORY_NONFATAL_DEV0_F1_MASK                        0x00010000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_PWR_EN_DEV0_F1_MASK                                            0x00020000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_EN_DEV0_F1_MASK                                            0x00040000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_MSI_CLR_PENDING_EN_DEV0_F1_MASK                                0x00080000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_MSIX_EN_DEV0_F1_MASK                                           0x00100000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_PMC_DSI_DEV0_F1_MASK                                           0x01000000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_TRANSLATED_REQ_WITH_PASID_SUPPORTED_DEV0_F1_MASK               0x02000000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_ALL_MSI_EVENT_SUPPORT_EN_DEV0_F1_MASK                          0x04000000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_SMN_ERR_STATUS_MASK_EN_EP_DEV0_F1_MASK                         0x08000000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_VF_RESIZE_BAR_EN_DEV0_F1_MASK                                  0x10000000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_CLK_PM_EN_DEV0_F1_MASK                                         0x20000000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_TRUE_PM_STATUS_EN_DEV0_F1_MASK                                 0x40000000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP3__STRAP_RTR_EN_DEV0_F1_MASK                                            0x80000000L
+//RCC_STRAP2_RCC_DEV0_EPF1_STRAP4
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1__SHIFT                                 0x14
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1__SHIFT                                       0x15
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1__SHIFT                                          0x16
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1__SHIFT                                     0x17
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1__SHIFT                                   0x1c
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1__SHIFT                                  0x1f
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_64BIT_EN_DEV0_F1_MASK                                   0x00100000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_ATOMIC_EN_DEV0_F1_MASK                                         0x00200000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_FLR_EN_DEV0_F1_MASK                                            0x00400000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_PME_SUPPORT_DEV0_F1_MASK                                       0x0F800000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_INTERRUPT_PIN_DEV0_F1_MASK                                     0x70000000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP4__STRAP_AUXPWR_SUPPORT_DEV0_F1_MASK                                    0x80000000L
+//RCC_STRAP2_RCC_DEV0_EPF1_STRAP5
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1__SHIFT                                   0x0
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP5__STRAP_AUX_CURRENT_DEV0_F1__SHIFT                                     0x1b
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F1__SHIFT                            0x1e
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP5__STRAP_SUBSYS_VEN_ID_DEV0_F1_MASK                                     0x0000FFFFL
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP5__STRAP_AUX_CURRENT_DEV0_F1_MASK                                       0x38000000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP5__STRAP_MSI_EXT_MSG_DATA_CAP_DEV0_F1_MASK                              0x40000000L
+//RCC_STRAP2_RCC_DEV0_EPF1_STRAP6
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1__SHIFT                                        0x0
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F1__SHIFT                           0x1
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1__SHIFT                                  0x2
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_EN_DEV0_F1__SHIFT                                        0x8
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F1__SHIFT                           0x9
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_64BAR_EN_DEV0_F1__SHIFT                                  0xa
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_EN_DEV0_F1__SHIFT                                        0x10
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F1__SHIFT                           0x11
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_64BAR_EN_DEV0_F1__SHIFT                                  0x12
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER3_EN_DEV0_F1__SHIFT                                        0x18
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV0_F1__SHIFT                           0x19
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER4_EN_DEV0_F1__SHIFT                                        0x1a
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER4_PREFETCHABLE_EN_DEV0_F1__SHIFT                           0x1b
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_EN_DEV0_F1_MASK                                          0x00000001L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_PREFETCHABLE_EN_DEV0_F1_MASK                             0x00000002L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER0_64BAR_EN_DEV0_F1_MASK                                    0x00000004L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_EN_DEV0_F1_MASK                                          0x00000100L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_PREFETCHABLE_EN_DEV0_F1_MASK                             0x00000200L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER1_64BAR_EN_DEV0_F1_MASK                                    0x00000400L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_EN_DEV0_F1_MASK                                          0x00010000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_PREFETCHABLE_EN_DEV0_F1_MASK                             0x00020000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER2_64BAR_EN_DEV0_F1_MASK                                    0x00040000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER3_EN_DEV0_F1_MASK                                          0x01000000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER3_PREFETCHABLE_EN_DEV0_F1_MASK                             0x02000000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER4_EN_DEV0_F1_MASK                                          0x04000000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP6__STRAP_APER4_PREFETCHABLE_EN_DEV0_F1_MASK                             0x08000000L
+//RCC_STRAP2_RCC_DEV0_EPF1_STRAP7
+//RCC_STRAP2_RCC_DEV0_EPF1_STRAP8
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F1__SHIFT                                0x1b
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F1__SHIFT                           0x1e
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP8__STRAP_VF_MSI_MULTI_CAP_DEV0_F1_MASK                                  0x38000000L
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP8__STRAP_SRIOV_VF_MAPPING_MODE_DEV0_F1_MASK                             0xC0000000L
+//RCC_STRAP2_RCC_DEV0_EPF1_STRAP9
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F1__SHIFT                           0x0
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP9__STRAP_TEE_IO_SUPPORT_DEV0_F1__SHIFT                                  0x1c
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP9__STRAP_OUTSTAND_PAGE_REQ_CAP_DEV0_F1_MASK                             0x0000FFFFL
+#define RCC_STRAP2_RCC_DEV0_EPF1_STRAP9__STRAP_TEE_IO_SUPPORT_DEV0_F1_MASK                                    0x10000000L
+
+
+// addressBlock: nbif0_hpdma0_hpdma_private_hpdma_private_regblk
+//NBIF_SDP_PERF_COUNTER_2
+#define NBIF_SDP_PERF_COUNTER_2__SDP_PERF_CNT_0_SEL__SHIFT                                                    0x0
+#define NBIF_SDP_PERF_COUNTER_2__SDP_PERF_CNT_1_SEL__SHIFT                                                    0x8
+#define NBIF_SDP_PERF_COUNTER_2__SDP_PERF_CNT_2_SEL__SHIFT                                                    0x10
+#define NBIF_SDP_PERF_COUNTER_2__SDP_PERF_CNT_3_SEL__SHIFT                                                    0x18
+#define NBIF_SDP_PERF_COUNTER_2__SDP_PERF_CNT_0_SEL_MASK                                                      0x000000FFL
+#define NBIF_SDP_PERF_COUNTER_2__SDP_PERF_CNT_1_SEL_MASK                                                      0x0000FF00L
+#define NBIF_SDP_PERF_COUNTER_2__SDP_PERF_CNT_2_SEL_MASK                                                      0x00FF0000L
+#define NBIF_SDP_PERF_COUNTER_2__SDP_PERF_CNT_3_SEL_MASK                                                      0xFF000000L
+//NBIF_SHUB_TODET_CLIENT_STATUS3
+#define NBIF_SHUB_TODET_CLIENT_STATUS3__NBIF_SHUB_TODET_CLIENT_STATUS3__SHIFT                                 0x0
+#define NBIF_SHUB_TODET_CLIENT_STATUS3__NBIF_SHUB_TODET_CLIENT_STATUS3_MASK                                   0x000003FFL
+//BIF_AER_ERR_LOG_DEV0_F0
+#define BIF_AER_ERR_LOG_DEV0_F0__UR_ATOMIC_OPCODE_DEV0_F0__SHIFT                                              0x0
+#define BIF_AER_ERR_LOG_DEV0_F0__UR_ATOMIC_REQEN_LOW_DEV0_F0__SHIFT                                           0x1
+#define BIF_AER_ERR_LOG_DEV0_F0__UR_ATOMIC_LENGTH_DEV0_F0__SHIFT                                              0x2
+#define BIF_AER_ERR_LOG_DEV0_F0__UR_ATOMIC_NR_DEV0_F0__SHIFT                                                  0x3
+#define BIF_AER_ERR_LOG_DEV0_F0__DMA_ON_BME_LOW_DEV0_F0__SHIFT                                                0x4
+#define BIF_AER_ERR_LOG_DEV0_F0__PASID_ERR_DEV0_F0__SHIFT                                                     0x5
+#define BIF_AER_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_OPCODE_DEV0_F0__SHIFT                                        0x10
+#define BIF_AER_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F0__SHIFT                                     0x11
+#define BIF_AER_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_LENGTH_DEV0_F0__SHIFT                                        0x12
+#define BIF_AER_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_NR_DEV0_F0__SHIFT                                            0x13
+#define BIF_AER_ERR_LOG_DEV0_F0__CLEAR_DMA_ON_BME_LOW_DEV0_F0__SHIFT                                          0x14
+#define BIF_AER_ERR_LOG_DEV0_F0__PASID_ERR_CLR_DEV0_F0__SHIFT                                                 0x15
+#define BIF_AER_ERR_LOG_DEV0_F0__UR_ATOMIC_OPCODE_DEV0_F0_MASK                                                0x00000001L
+#define BIF_AER_ERR_LOG_DEV0_F0__UR_ATOMIC_REQEN_LOW_DEV0_F0_MASK                                             0x00000002L
+#define BIF_AER_ERR_LOG_DEV0_F0__UR_ATOMIC_LENGTH_DEV0_F0_MASK                                                0x00000004L
+#define BIF_AER_ERR_LOG_DEV0_F0__UR_ATOMIC_NR_DEV0_F0_MASK                                                    0x00000008L
+#define BIF_AER_ERR_LOG_DEV0_F0__DMA_ON_BME_LOW_DEV0_F0_MASK                                                  0x00000010L
+#define BIF_AER_ERR_LOG_DEV0_F0__PASID_ERR_DEV0_F0_MASK                                                       0x00000020L
+#define BIF_AER_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_OPCODE_DEV0_F0_MASK                                          0x00010000L
+#define BIF_AER_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F0_MASK                                       0x00020000L
+#define BIF_AER_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_LENGTH_DEV0_F0_MASK                                          0x00040000L
+#define BIF_AER_ERR_LOG_DEV0_F0__CLEAR_UR_ATOMIC_NR_DEV0_F0_MASK                                              0x00080000L
+#define BIF_AER_ERR_LOG_DEV0_F0__CLEAR_DMA_ON_BME_LOW_DEV0_F0_MASK                                            0x00100000L
+#define BIF_AER_ERR_LOG_DEV0_F0__PASID_ERR_CLR_DEV0_F0_MASK                                                   0x00200000L
+//BIF_AER_ERR_LOG_DEV0_F0_vf0
+#define BIF_AER_ERR_LOG_DEV0_F0_vf0__UR_ATOMIC_OPCODE_DEV0_F0_vf0__SHIFT                                      0x0
+#define BIF_AER_ERR_LOG_DEV0_F0_vf0__UR_ATOMIC_REQEN_LOW_DEV0_F0_vf0__SHIFT                                   0x1
+#define BIF_AER_ERR_LOG_DEV0_F0_vf0__UR_ATOMIC_LENGTH_DEV0_F0_vf0__SHIFT                                      0x2
+#define BIF_AER_ERR_LOG_DEV0_F0_vf0__UR_ATOMIC_NR_DEV0_F0_vf0__SHIFT                                          0x3
+#define BIF_AER_ERR_LOG_DEV0_F0_vf0__DMA_ON_BME_LOW_DEV0_F0_vf0__SHIFT                                        0x4
+#define BIF_AER_ERR_LOG_DEV0_F0_vf0__CLEAR_UR_ATOMIC_OPCODE_DEV0_F0_vf0__SHIFT                                0x10
+#define BIF_AER_ERR_LOG_DEV0_F0_vf0__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F0_vf0__SHIFT                             0x11
+#define BIF_AER_ERR_LOG_DEV0_F0_vf0__CLEAR_UR_ATOMIC_LENGTH_DEV0_F0_vf0__SHIFT                                0x12
+#define BIF_AER_ERR_LOG_DEV0_F0_vf0__CLEAR_UR_ATOMIC_NR_DEV0_F0_vf0__SHIFT                                    0x13
+#define BIF_AER_ERR_LOG_DEV0_F0_vf0__CLEAR_DMA_ON_BME_LOW_DEV0_F0_vf0__SHIFT                                  0x14
+#define BIF_AER_ERR_LOG_DEV0_F0_vf0__UR_ATOMIC_OPCODE_DEV0_F0_vf0_MASK                                        0x00000001L
+#define BIF_AER_ERR_LOG_DEV0_F0_vf0__UR_ATOMIC_REQEN_LOW_DEV0_F0_vf0_MASK                                     0x00000002L
+#define BIF_AER_ERR_LOG_DEV0_F0_vf0__UR_ATOMIC_LENGTH_DEV0_F0_vf0_MASK                                        0x00000004L
+#define BIF_AER_ERR_LOG_DEV0_F0_vf0__UR_ATOMIC_NR_DEV0_F0_vf0_MASK                                            0x00000008L
+#define BIF_AER_ERR_LOG_DEV0_F0_vf0__DMA_ON_BME_LOW_DEV0_F0_vf0_MASK                                          0x00000010L
+#define BIF_AER_ERR_LOG_DEV0_F0_vf0__CLEAR_UR_ATOMIC_OPCODE_DEV0_F0_vf0_MASK                                  0x00010000L
+#define BIF_AER_ERR_LOG_DEV0_F0_vf0__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F0_vf0_MASK                               0x00020000L
+#define BIF_AER_ERR_LOG_DEV0_F0_vf0__CLEAR_UR_ATOMIC_LENGTH_DEV0_F0_vf0_MASK                                  0x00040000L
+#define BIF_AER_ERR_LOG_DEV0_F0_vf0__CLEAR_UR_ATOMIC_NR_DEV0_F0_vf0_MASK                                      0x00080000L
+#define BIF_AER_ERR_LOG_DEV0_F0_vf0__CLEAR_DMA_ON_BME_LOW_DEV0_F0_vf0_MASK                                    0x00100000L
+//BIF_AER_ERR_LOG_DEV0_F0_vf1
+#define BIF_AER_ERR_LOG_DEV0_F0_vf1__UR_ATOMIC_OPCODE_DEV0_F0_vf1__SHIFT                                      0x0
+#define BIF_AER_ERR_LOG_DEV0_F0_vf1__UR_ATOMIC_REQEN_LOW_DEV0_F0_vf1__SHIFT                                   0x1
+#define BIF_AER_ERR_LOG_DEV0_F0_vf1__UR_ATOMIC_LENGTH_DEV0_F0_vf1__SHIFT                                      0x2
+#define BIF_AER_ERR_LOG_DEV0_F0_vf1__UR_ATOMIC_NR_DEV0_F0_vf1__SHIFT                                          0x3
+#define BIF_AER_ERR_LOG_DEV0_F0_vf1__DMA_ON_BME_LOW_DEV0_F0_vf1__SHIFT                                        0x4
+#define BIF_AER_ERR_LOG_DEV0_F0_vf1__CLEAR_UR_ATOMIC_OPCODE_DEV0_F0_vf1__SHIFT                                0x10
+#define BIF_AER_ERR_LOG_DEV0_F0_vf1__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F0_vf1__SHIFT                             0x11
+#define BIF_AER_ERR_LOG_DEV0_F0_vf1__CLEAR_UR_ATOMIC_LENGTH_DEV0_F0_vf1__SHIFT                                0x12
+#define BIF_AER_ERR_LOG_DEV0_F0_vf1__CLEAR_UR_ATOMIC_NR_DEV0_F0_vf1__SHIFT                                    0x13
+#define BIF_AER_ERR_LOG_DEV0_F0_vf1__CLEAR_DMA_ON_BME_LOW_DEV0_F0_vf1__SHIFT                                  0x14
+#define BIF_AER_ERR_LOG_DEV0_F0_vf1__UR_ATOMIC_OPCODE_DEV0_F0_vf1_MASK                                        0x00000001L
+#define BIF_AER_ERR_LOG_DEV0_F0_vf1__UR_ATOMIC_REQEN_LOW_DEV0_F0_vf1_MASK                                     0x00000002L
+#define BIF_AER_ERR_LOG_DEV0_F0_vf1__UR_ATOMIC_LENGTH_DEV0_F0_vf1_MASK                                        0x00000004L
+#define BIF_AER_ERR_LOG_DEV0_F0_vf1__UR_ATOMIC_NR_DEV0_F0_vf1_MASK                                            0x00000008L
+#define BIF_AER_ERR_LOG_DEV0_F0_vf1__DMA_ON_BME_LOW_DEV0_F0_vf1_MASK                                          0x00000010L
+#define BIF_AER_ERR_LOG_DEV0_F0_vf1__CLEAR_UR_ATOMIC_OPCODE_DEV0_F0_vf1_MASK                                  0x00010000L
+#define BIF_AER_ERR_LOG_DEV0_F0_vf1__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F0_vf1_MASK                               0x00020000L
+#define BIF_AER_ERR_LOG_DEV0_F0_vf1__CLEAR_UR_ATOMIC_LENGTH_DEV0_F0_vf1_MASK                                  0x00040000L
+#define BIF_AER_ERR_LOG_DEV0_F0_vf1__CLEAR_UR_ATOMIC_NR_DEV0_F0_vf1_MASK                                      0x00080000L
+#define BIF_AER_ERR_LOG_DEV0_F0_vf1__CLEAR_DMA_ON_BME_LOW_DEV0_F0_vf1_MASK                                    0x00100000L
+//BIF_AER_ERR_LOG_DEV0_F0_vf2
+#define BIF_AER_ERR_LOG_DEV0_F0_vf2__UR_ATOMIC_OPCODE_DEV0_F0_vf2__SHIFT                                      0x0
+#define BIF_AER_ERR_LOG_DEV0_F0_vf2__UR_ATOMIC_REQEN_LOW_DEV0_F0_vf2__SHIFT                                   0x1
+#define BIF_AER_ERR_LOG_DEV0_F0_vf2__UR_ATOMIC_LENGTH_DEV0_F0_vf2__SHIFT                                      0x2
+#define BIF_AER_ERR_LOG_DEV0_F0_vf2__UR_ATOMIC_NR_DEV0_F0_vf2__SHIFT                                          0x3
+#define BIF_AER_ERR_LOG_DEV0_F0_vf2__DMA_ON_BME_LOW_DEV0_F0_vf2__SHIFT                                        0x4
+#define BIF_AER_ERR_LOG_DEV0_F0_vf2__CLEAR_UR_ATOMIC_OPCODE_DEV0_F0_vf2__SHIFT                                0x10
+#define BIF_AER_ERR_LOG_DEV0_F0_vf2__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F0_vf2__SHIFT                             0x11
+#define BIF_AER_ERR_LOG_DEV0_F0_vf2__CLEAR_UR_ATOMIC_LENGTH_DEV0_F0_vf2__SHIFT                                0x12
+#define BIF_AER_ERR_LOG_DEV0_F0_vf2__CLEAR_UR_ATOMIC_NR_DEV0_F0_vf2__SHIFT                                    0x13
+#define BIF_AER_ERR_LOG_DEV0_F0_vf2__CLEAR_DMA_ON_BME_LOW_DEV0_F0_vf2__SHIFT                                  0x14
+#define BIF_AER_ERR_LOG_DEV0_F0_vf2__UR_ATOMIC_OPCODE_DEV0_F0_vf2_MASK                                        0x00000001L
+#define BIF_AER_ERR_LOG_DEV0_F0_vf2__UR_ATOMIC_REQEN_LOW_DEV0_F0_vf2_MASK                                     0x00000002L
+#define BIF_AER_ERR_LOG_DEV0_F0_vf2__UR_ATOMIC_LENGTH_DEV0_F0_vf2_MASK                                        0x00000004L
+#define BIF_AER_ERR_LOG_DEV0_F0_vf2__UR_ATOMIC_NR_DEV0_F0_vf2_MASK                                            0x00000008L
+#define BIF_AER_ERR_LOG_DEV0_F0_vf2__DMA_ON_BME_LOW_DEV0_F0_vf2_MASK                                          0x00000010L
+#define BIF_AER_ERR_LOG_DEV0_F0_vf2__CLEAR_UR_ATOMIC_OPCODE_DEV0_F0_vf2_MASK                                  0x00010000L
+#define BIF_AER_ERR_LOG_DEV0_F0_vf2__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F0_vf2_MASK                               0x00020000L
+#define BIF_AER_ERR_LOG_DEV0_F0_vf2__CLEAR_UR_ATOMIC_LENGTH_DEV0_F0_vf2_MASK                                  0x00040000L
+#define BIF_AER_ERR_LOG_DEV0_F0_vf2__CLEAR_UR_ATOMIC_NR_DEV0_F0_vf2_MASK                                      0x00080000L
+#define BIF_AER_ERR_LOG_DEV0_F0_vf2__CLEAR_DMA_ON_BME_LOW_DEV0_F0_vf2_MASK                                    0x00100000L
+//BIF_AER_ERR_LOG_DEV0_F0_vf3
+#define BIF_AER_ERR_LOG_DEV0_F0_vf3__UR_ATOMIC_OPCODE_DEV0_F0_vf3__SHIFT                                      0x0
+#define BIF_AER_ERR_LOG_DEV0_F0_vf3__UR_ATOMIC_REQEN_LOW_DEV0_F0_vf3__SHIFT                                   0x1
+#define BIF_AER_ERR_LOG_DEV0_F0_vf3__UR_ATOMIC_LENGTH_DEV0_F0_vf3__SHIFT                                      0x2
+#define BIF_AER_ERR_LOG_DEV0_F0_vf3__UR_ATOMIC_NR_DEV0_F0_vf3__SHIFT                                          0x3
+#define BIF_AER_ERR_LOG_DEV0_F0_vf3__DMA_ON_BME_LOW_DEV0_F0_vf3__SHIFT                                        0x4
+#define BIF_AER_ERR_LOG_DEV0_F0_vf3__CLEAR_UR_ATOMIC_OPCODE_DEV0_F0_vf3__SHIFT                                0x10
+#define BIF_AER_ERR_LOG_DEV0_F0_vf3__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F0_vf3__SHIFT                             0x11
+#define BIF_AER_ERR_LOG_DEV0_F0_vf3__CLEAR_UR_ATOMIC_LENGTH_DEV0_F0_vf3__SHIFT                                0x12
+#define BIF_AER_ERR_LOG_DEV0_F0_vf3__CLEAR_UR_ATOMIC_NR_DEV0_F0_vf3__SHIFT                                    0x13
+#define BIF_AER_ERR_LOG_DEV0_F0_vf3__CLEAR_DMA_ON_BME_LOW_DEV0_F0_vf3__SHIFT                                  0x14
+#define BIF_AER_ERR_LOG_DEV0_F0_vf3__UR_ATOMIC_OPCODE_DEV0_F0_vf3_MASK                                        0x00000001L
+#define BIF_AER_ERR_LOG_DEV0_F0_vf3__UR_ATOMIC_REQEN_LOW_DEV0_F0_vf3_MASK                                     0x00000002L
+#define BIF_AER_ERR_LOG_DEV0_F0_vf3__UR_ATOMIC_LENGTH_DEV0_F0_vf3_MASK                                        0x00000004L
+#define BIF_AER_ERR_LOG_DEV0_F0_vf3__UR_ATOMIC_NR_DEV0_F0_vf3_MASK                                            0x00000008L
+#define BIF_AER_ERR_LOG_DEV0_F0_vf3__DMA_ON_BME_LOW_DEV0_F0_vf3_MASK                                          0x00000010L
+#define BIF_AER_ERR_LOG_DEV0_F0_vf3__CLEAR_UR_ATOMIC_OPCODE_DEV0_F0_vf3_MASK                                  0x00010000L
+#define BIF_AER_ERR_LOG_DEV0_F0_vf3__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F0_vf3_MASK                               0x00020000L
+#define BIF_AER_ERR_LOG_DEV0_F0_vf3__CLEAR_UR_ATOMIC_LENGTH_DEV0_F0_vf3_MASK                                  0x00040000L
+#define BIF_AER_ERR_LOG_DEV0_F0_vf3__CLEAR_UR_ATOMIC_NR_DEV0_F0_vf3_MASK                                      0x00080000L
+#define BIF_AER_ERR_LOG_DEV0_F0_vf3__CLEAR_DMA_ON_BME_LOW_DEV0_F0_vf3_MASK                                    0x00100000L
+//BIF_AER_ERR_LOG_DEV0_F0_vf4
+#define BIF_AER_ERR_LOG_DEV0_F0_vf4__UR_ATOMIC_OPCODE_DEV0_F0_vf4__SHIFT                                      0x0
+#define BIF_AER_ERR_LOG_DEV0_F0_vf4__UR_ATOMIC_REQEN_LOW_DEV0_F0_vf4__SHIFT                                   0x1
+#define BIF_AER_ERR_LOG_DEV0_F0_vf4__UR_ATOMIC_LENGTH_DEV0_F0_vf4__SHIFT                                      0x2
+#define BIF_AER_ERR_LOG_DEV0_F0_vf4__UR_ATOMIC_NR_DEV0_F0_vf4__SHIFT                                          0x3
+#define BIF_AER_ERR_LOG_DEV0_F0_vf4__DMA_ON_BME_LOW_DEV0_F0_vf4__SHIFT                                        0x4
+#define BIF_AER_ERR_LOG_DEV0_F0_vf4__CLEAR_UR_ATOMIC_OPCODE_DEV0_F0_vf4__SHIFT                                0x10
+#define BIF_AER_ERR_LOG_DEV0_F0_vf4__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F0_vf4__SHIFT                             0x11
+#define BIF_AER_ERR_LOG_DEV0_F0_vf4__CLEAR_UR_ATOMIC_LENGTH_DEV0_F0_vf4__SHIFT                                0x12
+#define BIF_AER_ERR_LOG_DEV0_F0_vf4__CLEAR_UR_ATOMIC_NR_DEV0_F0_vf4__SHIFT                                    0x13
+#define BIF_AER_ERR_LOG_DEV0_F0_vf4__CLEAR_DMA_ON_BME_LOW_DEV0_F0_vf4__SHIFT                                  0x14
+#define BIF_AER_ERR_LOG_DEV0_F0_vf4__UR_ATOMIC_OPCODE_DEV0_F0_vf4_MASK                                        0x00000001L
+#define BIF_AER_ERR_LOG_DEV0_F0_vf4__UR_ATOMIC_REQEN_LOW_DEV0_F0_vf4_MASK                                     0x00000002L
+#define BIF_AER_ERR_LOG_DEV0_F0_vf4__UR_ATOMIC_LENGTH_DEV0_F0_vf4_MASK                                        0x00000004L
+#define BIF_AER_ERR_LOG_DEV0_F0_vf4__UR_ATOMIC_NR_DEV0_F0_vf4_MASK                                            0x00000008L
+#define BIF_AER_ERR_LOG_DEV0_F0_vf4__DMA_ON_BME_LOW_DEV0_F0_vf4_MASK                                          0x00000010L
+#define BIF_AER_ERR_LOG_DEV0_F0_vf4__CLEAR_UR_ATOMIC_OPCODE_DEV0_F0_vf4_MASK                                  0x00010000L
+#define BIF_AER_ERR_LOG_DEV0_F0_vf4__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F0_vf4_MASK                               0x00020000L
+#define BIF_AER_ERR_LOG_DEV0_F0_vf4__CLEAR_UR_ATOMIC_LENGTH_DEV0_F0_vf4_MASK                                  0x00040000L
+#define BIF_AER_ERR_LOG_DEV0_F0_vf4__CLEAR_UR_ATOMIC_NR_DEV0_F0_vf4_MASK                                      0x00080000L
+#define BIF_AER_ERR_LOG_DEV0_F0_vf4__CLEAR_DMA_ON_BME_LOW_DEV0_F0_vf4_MASK                                    0x00100000L
+//BIF_AER_ERR_LOG_DEV0_F0_vf5
+#define BIF_AER_ERR_LOG_DEV0_F0_vf5__UR_ATOMIC_OPCODE_DEV0_F0_vf5__SHIFT                                      0x0
+#define BIF_AER_ERR_LOG_DEV0_F0_vf5__UR_ATOMIC_REQEN_LOW_DEV0_F0_vf5__SHIFT                                   0x1
+#define BIF_AER_ERR_LOG_DEV0_F0_vf5__UR_ATOMIC_LENGTH_DEV0_F0_vf5__SHIFT                                      0x2
+#define BIF_AER_ERR_LOG_DEV0_F0_vf5__UR_ATOMIC_NR_DEV0_F0_vf5__SHIFT                                          0x3
+#define BIF_AER_ERR_LOG_DEV0_F0_vf5__DMA_ON_BME_LOW_DEV0_F0_vf5__SHIFT                                        0x4
+#define BIF_AER_ERR_LOG_DEV0_F0_vf5__CLEAR_UR_ATOMIC_OPCODE_DEV0_F0_vf5__SHIFT                                0x10
+#define BIF_AER_ERR_LOG_DEV0_F0_vf5__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F0_vf5__SHIFT                             0x11
+#define BIF_AER_ERR_LOG_DEV0_F0_vf5__CLEAR_UR_ATOMIC_LENGTH_DEV0_F0_vf5__SHIFT                                0x12
+#define BIF_AER_ERR_LOG_DEV0_F0_vf5__CLEAR_UR_ATOMIC_NR_DEV0_F0_vf5__SHIFT                                    0x13
+#define BIF_AER_ERR_LOG_DEV0_F0_vf5__CLEAR_DMA_ON_BME_LOW_DEV0_F0_vf5__SHIFT                                  0x14
+#define BIF_AER_ERR_LOG_DEV0_F0_vf5__UR_ATOMIC_OPCODE_DEV0_F0_vf5_MASK                                        0x00000001L
+#define BIF_AER_ERR_LOG_DEV0_F0_vf5__UR_ATOMIC_REQEN_LOW_DEV0_F0_vf5_MASK                                     0x00000002L
+#define BIF_AER_ERR_LOG_DEV0_F0_vf5__UR_ATOMIC_LENGTH_DEV0_F0_vf5_MASK                                        0x00000004L
+#define BIF_AER_ERR_LOG_DEV0_F0_vf5__UR_ATOMIC_NR_DEV0_F0_vf5_MASK                                            0x00000008L
+#define BIF_AER_ERR_LOG_DEV0_F0_vf5__DMA_ON_BME_LOW_DEV0_F0_vf5_MASK                                          0x00000010L
+#define BIF_AER_ERR_LOG_DEV0_F0_vf5__CLEAR_UR_ATOMIC_OPCODE_DEV0_F0_vf5_MASK                                  0x00010000L
+#define BIF_AER_ERR_LOG_DEV0_F0_vf5__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F0_vf5_MASK                               0x00020000L
+#define BIF_AER_ERR_LOG_DEV0_F0_vf5__CLEAR_UR_ATOMIC_LENGTH_DEV0_F0_vf5_MASK                                  0x00040000L
+#define BIF_AER_ERR_LOG_DEV0_F0_vf5__CLEAR_UR_ATOMIC_NR_DEV0_F0_vf5_MASK                                      0x00080000L
+#define BIF_AER_ERR_LOG_DEV0_F0_vf5__CLEAR_DMA_ON_BME_LOW_DEV0_F0_vf5_MASK                                    0x00100000L
+//BIF_AER_ERR_LOG_DEV0_F0_vf6
+#define BIF_AER_ERR_LOG_DEV0_F0_vf6__UR_ATOMIC_OPCODE_DEV0_F0_vf6__SHIFT                                      0x0
+#define BIF_AER_ERR_LOG_DEV0_F0_vf6__UR_ATOMIC_REQEN_LOW_DEV0_F0_vf6__SHIFT                                   0x1
+#define BIF_AER_ERR_LOG_DEV0_F0_vf6__UR_ATOMIC_LENGTH_DEV0_F0_vf6__SHIFT                                      0x2
+#define BIF_AER_ERR_LOG_DEV0_F0_vf6__UR_ATOMIC_NR_DEV0_F0_vf6__SHIFT                                          0x3
+#define BIF_AER_ERR_LOG_DEV0_F0_vf6__DMA_ON_BME_LOW_DEV0_F0_vf6__SHIFT                                        0x4
+#define BIF_AER_ERR_LOG_DEV0_F0_vf6__CLEAR_UR_ATOMIC_OPCODE_DEV0_F0_vf6__SHIFT                                0x10
+#define BIF_AER_ERR_LOG_DEV0_F0_vf6__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F0_vf6__SHIFT                             0x11
+#define BIF_AER_ERR_LOG_DEV0_F0_vf6__CLEAR_UR_ATOMIC_LENGTH_DEV0_F0_vf6__SHIFT                                0x12
+#define BIF_AER_ERR_LOG_DEV0_F0_vf6__CLEAR_UR_ATOMIC_NR_DEV0_F0_vf6__SHIFT                                    0x13
+#define BIF_AER_ERR_LOG_DEV0_F0_vf6__CLEAR_DMA_ON_BME_LOW_DEV0_F0_vf6__SHIFT                                  0x14
+#define BIF_AER_ERR_LOG_DEV0_F0_vf6__UR_ATOMIC_OPCODE_DEV0_F0_vf6_MASK                                        0x00000001L
+#define BIF_AER_ERR_LOG_DEV0_F0_vf6__UR_ATOMIC_REQEN_LOW_DEV0_F0_vf6_MASK                                     0x00000002L
+#define BIF_AER_ERR_LOG_DEV0_F0_vf6__UR_ATOMIC_LENGTH_DEV0_F0_vf6_MASK                                        0x00000004L
+#define BIF_AER_ERR_LOG_DEV0_F0_vf6__UR_ATOMIC_NR_DEV0_F0_vf6_MASK                                            0x00000008L
+#define BIF_AER_ERR_LOG_DEV0_F0_vf6__DMA_ON_BME_LOW_DEV0_F0_vf6_MASK                                          0x00000010L
+#define BIF_AER_ERR_LOG_DEV0_F0_vf6__CLEAR_UR_ATOMIC_OPCODE_DEV0_F0_vf6_MASK                                  0x00010000L
+#define BIF_AER_ERR_LOG_DEV0_F0_vf6__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F0_vf6_MASK                               0x00020000L
+#define BIF_AER_ERR_LOG_DEV0_F0_vf6__CLEAR_UR_ATOMIC_LENGTH_DEV0_F0_vf6_MASK                                  0x00040000L
+#define BIF_AER_ERR_LOG_DEV0_F0_vf6__CLEAR_UR_ATOMIC_NR_DEV0_F0_vf6_MASK                                      0x00080000L
+#define BIF_AER_ERR_LOG_DEV0_F0_vf6__CLEAR_DMA_ON_BME_LOW_DEV0_F0_vf6_MASK                                    0x00100000L
+//BIF_AER_ERR_LOG_DEV0_F0_vf7
+#define BIF_AER_ERR_LOG_DEV0_F0_vf7__UR_ATOMIC_OPCODE_DEV0_F0_vf7__SHIFT                                      0x0
+#define BIF_AER_ERR_LOG_DEV0_F0_vf7__UR_ATOMIC_REQEN_LOW_DEV0_F0_vf7__SHIFT                                   0x1
+#define BIF_AER_ERR_LOG_DEV0_F0_vf7__UR_ATOMIC_LENGTH_DEV0_F0_vf7__SHIFT                                      0x2
+#define BIF_AER_ERR_LOG_DEV0_F0_vf7__UR_ATOMIC_NR_DEV0_F0_vf7__SHIFT                                          0x3
+#define BIF_AER_ERR_LOG_DEV0_F0_vf7__DMA_ON_BME_LOW_DEV0_F0_vf7__SHIFT                                        0x4
+#define BIF_AER_ERR_LOG_DEV0_F0_vf7__CLEAR_UR_ATOMIC_OPCODE_DEV0_F0_vf7__SHIFT                                0x10
+#define BIF_AER_ERR_LOG_DEV0_F0_vf7__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F0_vf7__SHIFT                             0x11
+#define BIF_AER_ERR_LOG_DEV0_F0_vf7__CLEAR_UR_ATOMIC_LENGTH_DEV0_F0_vf7__SHIFT                                0x12
+#define BIF_AER_ERR_LOG_DEV0_F0_vf7__CLEAR_UR_ATOMIC_NR_DEV0_F0_vf7__SHIFT                                    0x13
+#define BIF_AER_ERR_LOG_DEV0_F0_vf7__CLEAR_DMA_ON_BME_LOW_DEV0_F0_vf7__SHIFT                                  0x14
+#define BIF_AER_ERR_LOG_DEV0_F0_vf7__UR_ATOMIC_OPCODE_DEV0_F0_vf7_MASK                                        0x00000001L
+#define BIF_AER_ERR_LOG_DEV0_F0_vf7__UR_ATOMIC_REQEN_LOW_DEV0_F0_vf7_MASK                                     0x00000002L
+#define BIF_AER_ERR_LOG_DEV0_F0_vf7__UR_ATOMIC_LENGTH_DEV0_F0_vf7_MASK                                        0x00000004L
+#define BIF_AER_ERR_LOG_DEV0_F0_vf7__UR_ATOMIC_NR_DEV0_F0_vf7_MASK                                            0x00000008L
+#define BIF_AER_ERR_LOG_DEV0_F0_vf7__DMA_ON_BME_LOW_DEV0_F0_vf7_MASK                                          0x00000010L
+#define BIF_AER_ERR_LOG_DEV0_F0_vf7__CLEAR_UR_ATOMIC_OPCODE_DEV0_F0_vf7_MASK                                  0x00010000L
+#define BIF_AER_ERR_LOG_DEV0_F0_vf7__CLEAR_UR_ATOMIC_REQEN_LOW_DEV0_F0_vf7_MASK                               0x00020000L
+#define BIF_AER_ERR_LOG_DEV0_F0_vf7__CLEAR_UR_ATOMIC_LENGTH_DEV0_F0_vf7_MASK                                  0x00040000L
+#define BIF_AER_ERR_LOG_DEV0_F0_vf7__CLEAR_UR_ATOMIC_NR_DEV0_F0_vf7_MASK                                      0x00080000L
+#define BIF_AER_ERR_LOG_DEV0_F0_vf7__CLEAR_DMA_ON_BME_LOW_DEV0_F0_vf7_MASK                                    0x00100000L
+
+
+// addressBlock: nbif0_hphost0_hphost_private_hphost_private_regblk
+//NBIF_AON_SVA_DISABLE_SAD
+#define NBIF_AON_SVA_DISABLE_SAD__NBIF_AON_SVA_DISABLE__SHIFT                                                 0x0
+#define NBIF_AON_SVA_DISABLE_SAD__NBIF_AON_SVA_DISABLE_MASK                                                   0x00000001L
+
+
+// addressBlock: nbif0_nbif0_gdc_dma_sion_SIONDEC
+//GDC_DMA_SION_CL0_RdRsp_BurstTarget_REG0
+#define GDC_DMA_SION_CL0_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT                                0x0
+#define GDC_DMA_SION_CL0_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0_MASK                                  0xFFFFFFFFL
+//GDC_DMA_SION_CL0_RdRsp_BurstTarget_REG1
+#define GDC_DMA_SION_CL0_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT                               0x0
+#define GDC_DMA_SION_CL0_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32_MASK                                 0xFFFFFFFFL
+//GDC_DMA_SION_CL0_RdRsp_TimeSlot_REG0
+#define GDC_DMA_SION_CL0_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT                                      0x0
+#define GDC_DMA_SION_CL0_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0_MASK                                        0xFFFFFFFFL
+//GDC_DMA_SION_CL0_RdRsp_TimeSlot_REG1
+#define GDC_DMA_SION_CL0_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT                                     0x0
+#define GDC_DMA_SION_CL0_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32_MASK                                       0xFFFFFFFFL
+//GDC_DMA_SION_CL0_WrRsp_BurstTarget_REG0
+#define GDC_DMA_SION_CL0_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT                                0x0
+#define GDC_DMA_SION_CL0_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0_MASK                                  0xFFFFFFFFL
+//GDC_DMA_SION_CL0_WrRsp_BurstTarget_REG1
+#define GDC_DMA_SION_CL0_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT                               0x0
+#define GDC_DMA_SION_CL0_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32_MASK                                 0xFFFFFFFFL
+//GDC_DMA_SION_CL0_WrRsp_TimeSlot_REG0
+#define GDC_DMA_SION_CL0_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT                                      0x0
+#define GDC_DMA_SION_CL0_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0_MASK                                        0xFFFFFFFFL
+//GDC_DMA_SION_CL0_WrRsp_TimeSlot_REG1
+#define GDC_DMA_SION_CL0_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT                                     0x0
+#define GDC_DMA_SION_CL0_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32_MASK                                       0xFFFFFFFFL
+//GDC_DMA_SION_CL0_Req_BurstTarget_REG0
+#define GDC_DMA_SION_CL0_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT                                    0x0
+#define GDC_DMA_SION_CL0_Req_BurstTarget_REG0__Req_BurstTarget_31_0_MASK                                      0xFFFFFFFFL
+//GDC_DMA_SION_CL0_Req_BurstTarget_REG1
+#define GDC_DMA_SION_CL0_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT                                   0x0
+#define GDC_DMA_SION_CL0_Req_BurstTarget_REG1__Req_BurstTarget_63_32_MASK                                     0xFFFFFFFFL
+//GDC_DMA_SION_CL0_Req_TimeSlot_REG0
+#define GDC_DMA_SION_CL0_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT                                          0x0
+#define GDC_DMA_SION_CL0_Req_TimeSlot_REG0__Req_TimeSlot_31_0_MASK                                            0xFFFFFFFFL
+//GDC_DMA_SION_CL0_Req_TimeSlot_REG1
+#define GDC_DMA_SION_CL0_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT                                         0x0
+#define GDC_DMA_SION_CL0_Req_TimeSlot_REG1__Req_TimeSlot_63_32_MASK                                           0xFFFFFFFFL
+//GDC_DMA_SION_CL0_ReqPoolCredit_Alloc_REG0
+#define GDC_DMA_SION_CL0_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT                            0x0
+#define GDC_DMA_SION_CL0_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0_MASK                              0xFFFFFFFFL
+//GDC_DMA_SION_CL0_ReqPoolCredit_Alloc_REG1
+#define GDC_DMA_SION_CL0_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT                           0x0
+#define GDC_DMA_SION_CL0_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32_MASK                             0xFFFFFFFFL
+//GDC_DMA_SION_CL0_DataPoolCredit_Alloc_REG0
+#define GDC_DMA_SION_CL0_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT                          0x0
+#define GDC_DMA_SION_CL0_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0_MASK                            0xFFFFFFFFL
+//GDC_DMA_SION_CL0_DataPoolCredit_Alloc_REG1
+#define GDC_DMA_SION_CL0_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT                         0x0
+#define GDC_DMA_SION_CL0_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32_MASK                           0xFFFFFFFFL
+//GDC_DMA_SION_CL0_RdRspPoolCredit_Alloc_REG0
+#define GDC_DMA_SION_CL0_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT                        0x0
+#define GDC_DMA_SION_CL0_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0_MASK                          0xFFFFFFFFL
+//GDC_DMA_SION_CL0_RdRspPoolCredit_Alloc_REG1
+#define GDC_DMA_SION_CL0_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT                       0x0
+#define GDC_DMA_SION_CL0_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32_MASK                         0xFFFFFFFFL
+//GDC_DMA_SION_CL0_WrRspPoolCredit_Alloc_REG0
+#define GDC_DMA_SION_CL0_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT                        0x0
+#define GDC_DMA_SION_CL0_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0_MASK                          0xFFFFFFFFL
+//GDC_DMA_SION_CL0_WrRspPoolCredit_Alloc_REG1
+#define GDC_DMA_SION_CL0_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT                       0x0
+#define GDC_DMA_SION_CL0_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32_MASK                         0xFFFFFFFFL
+//GDC_DMA_SION_CL1_RdRsp_BurstTarget_REG0
+#define GDC_DMA_SION_CL1_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT                                0x0
+#define GDC_DMA_SION_CL1_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0_MASK                                  0xFFFFFFFFL
+//GDC_DMA_SION_CL1_RdRsp_BurstTarget_REG1
+#define GDC_DMA_SION_CL1_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT                               0x0
+#define GDC_DMA_SION_CL1_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32_MASK                                 0xFFFFFFFFL
+//GDC_DMA_SION_CL1_RdRsp_TimeSlot_REG0
+#define GDC_DMA_SION_CL1_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT                                      0x0
+#define GDC_DMA_SION_CL1_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0_MASK                                        0xFFFFFFFFL
+//GDC_DMA_SION_CL1_RdRsp_TimeSlot_REG1
+#define GDC_DMA_SION_CL1_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT                                     0x0
+#define GDC_DMA_SION_CL1_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32_MASK                                       0xFFFFFFFFL
+//GDC_DMA_SION_CL1_WrRsp_BurstTarget_REG0
+#define GDC_DMA_SION_CL1_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT                                0x0
+#define GDC_DMA_SION_CL1_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0_MASK                                  0xFFFFFFFFL
+//GDC_DMA_SION_CL1_WrRsp_BurstTarget_REG1
+#define GDC_DMA_SION_CL1_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT                               0x0
+#define GDC_DMA_SION_CL1_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32_MASK                                 0xFFFFFFFFL
+//GDC_DMA_SION_CL1_WrRsp_TimeSlot_REG0
+#define GDC_DMA_SION_CL1_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT                                      0x0
+#define GDC_DMA_SION_CL1_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0_MASK                                        0xFFFFFFFFL
+//GDC_DMA_SION_CL1_WrRsp_TimeSlot_REG1
+#define GDC_DMA_SION_CL1_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT                                     0x0
+#define GDC_DMA_SION_CL1_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32_MASK                                       0xFFFFFFFFL
+//GDC_DMA_SION_CL1_Req_BurstTarget_REG0
+#define GDC_DMA_SION_CL1_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT                                    0x0
+#define GDC_DMA_SION_CL1_Req_BurstTarget_REG0__Req_BurstTarget_31_0_MASK                                      0xFFFFFFFFL
+//GDC_DMA_SION_CL1_Req_BurstTarget_REG1
+#define GDC_DMA_SION_CL1_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT                                   0x0
+#define GDC_DMA_SION_CL1_Req_BurstTarget_REG1__Req_BurstTarget_63_32_MASK                                     0xFFFFFFFFL
+//GDC_DMA_SION_CL1_Req_TimeSlot_REG0
+#define GDC_DMA_SION_CL1_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT                                          0x0
+#define GDC_DMA_SION_CL1_Req_TimeSlot_REG0__Req_TimeSlot_31_0_MASK                                            0xFFFFFFFFL
+//GDC_DMA_SION_CL1_Req_TimeSlot_REG1
+#define GDC_DMA_SION_CL1_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT                                         0x0
+#define GDC_DMA_SION_CL1_Req_TimeSlot_REG1__Req_TimeSlot_63_32_MASK                                           0xFFFFFFFFL
+//GDC_DMA_SION_CL1_ReqPoolCredit_Alloc_REG0
+#define GDC_DMA_SION_CL1_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT                            0x0
+#define GDC_DMA_SION_CL1_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0_MASK                              0xFFFFFFFFL
+//GDC_DMA_SION_CL1_ReqPoolCredit_Alloc_REG1
+#define GDC_DMA_SION_CL1_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT                           0x0
+#define GDC_DMA_SION_CL1_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32_MASK                             0xFFFFFFFFL
+//GDC_DMA_SION_CL1_DataPoolCredit_Alloc_REG0
+#define GDC_DMA_SION_CL1_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT                          0x0
+#define GDC_DMA_SION_CL1_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0_MASK                            0xFFFFFFFFL
+//GDC_DMA_SION_CL1_DataPoolCredit_Alloc_REG1
+#define GDC_DMA_SION_CL1_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT                         0x0
+#define GDC_DMA_SION_CL1_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32_MASK                           0xFFFFFFFFL
+//GDC_DMA_SION_CL1_RdRspPoolCredit_Alloc_REG0
+#define GDC_DMA_SION_CL1_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT                        0x0
+#define GDC_DMA_SION_CL1_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0_MASK                          0xFFFFFFFFL
+//GDC_DMA_SION_CL1_RdRspPoolCredit_Alloc_REG1
+#define GDC_DMA_SION_CL1_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT                       0x0
+#define GDC_DMA_SION_CL1_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32_MASK                         0xFFFFFFFFL
+//GDC_DMA_SION_CL1_WrRspPoolCredit_Alloc_REG0
+#define GDC_DMA_SION_CL1_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT                        0x0
+#define GDC_DMA_SION_CL1_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0_MASK                          0xFFFFFFFFL
+//GDC_DMA_SION_CL1_WrRspPoolCredit_Alloc_REG1
+#define GDC_DMA_SION_CL1_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT                       0x0
+#define GDC_DMA_SION_CL1_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32_MASK                         0xFFFFFFFFL
+//GDC_DMA_SION_CL2_RdRsp_BurstTarget_REG0
+#define GDC_DMA_SION_CL2_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT                                0x0
+#define GDC_DMA_SION_CL2_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0_MASK                                  0xFFFFFFFFL
+//GDC_DMA_SION_CL2_RdRsp_BurstTarget_REG1
+#define GDC_DMA_SION_CL2_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT                               0x0
+#define GDC_DMA_SION_CL2_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32_MASK                                 0xFFFFFFFFL
+//GDC_DMA_SION_CL2_RdRsp_TimeSlot_REG0
+#define GDC_DMA_SION_CL2_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT                                      0x0
+#define GDC_DMA_SION_CL2_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0_MASK                                        0xFFFFFFFFL
+//GDC_DMA_SION_CL2_RdRsp_TimeSlot_REG1
+#define GDC_DMA_SION_CL2_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT                                     0x0
+#define GDC_DMA_SION_CL2_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32_MASK                                       0xFFFFFFFFL
+//GDC_DMA_SION_CL2_WrRsp_BurstTarget_REG0
+#define GDC_DMA_SION_CL2_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT                                0x0
+#define GDC_DMA_SION_CL2_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0_MASK                                  0xFFFFFFFFL
+//GDC_DMA_SION_CL2_WrRsp_BurstTarget_REG1
+#define GDC_DMA_SION_CL2_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT                               0x0
+#define GDC_DMA_SION_CL2_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32_MASK                                 0xFFFFFFFFL
+//GDC_DMA_SION_CL2_WrRsp_TimeSlot_REG0
+#define GDC_DMA_SION_CL2_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT                                      0x0
+#define GDC_DMA_SION_CL2_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0_MASK                                        0xFFFFFFFFL
+//GDC_DMA_SION_CL2_WrRsp_TimeSlot_REG1
+#define GDC_DMA_SION_CL2_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT                                     0x0
+#define GDC_DMA_SION_CL2_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32_MASK                                       0xFFFFFFFFL
+//GDC_DMA_SION_CL2_Req_BurstTarget_REG0
+#define GDC_DMA_SION_CL2_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT                                    0x0
+#define GDC_DMA_SION_CL2_Req_BurstTarget_REG0__Req_BurstTarget_31_0_MASK                                      0xFFFFFFFFL
+//GDC_DMA_SION_CL2_Req_BurstTarget_REG1
+#define GDC_DMA_SION_CL2_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT                                   0x0
+#define GDC_DMA_SION_CL2_Req_BurstTarget_REG1__Req_BurstTarget_63_32_MASK                                     0xFFFFFFFFL
+//GDC_DMA_SION_CL2_Req_TimeSlot_REG0
+#define GDC_DMA_SION_CL2_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT                                          0x0
+#define GDC_DMA_SION_CL2_Req_TimeSlot_REG0__Req_TimeSlot_31_0_MASK                                            0xFFFFFFFFL
+//GDC_DMA_SION_CL2_Req_TimeSlot_REG1
+#define GDC_DMA_SION_CL2_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT                                         0x0
+#define GDC_DMA_SION_CL2_Req_TimeSlot_REG1__Req_TimeSlot_63_32_MASK                                           0xFFFFFFFFL
+//GDC_DMA_SION_CL2_ReqPoolCredit_Alloc_REG0
+#define GDC_DMA_SION_CL2_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT                            0x0
+#define GDC_DMA_SION_CL2_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0_MASK                              0xFFFFFFFFL
+//GDC_DMA_SION_CL2_ReqPoolCredit_Alloc_REG1
+#define GDC_DMA_SION_CL2_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT                           0x0
+#define GDC_DMA_SION_CL2_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32_MASK                             0xFFFFFFFFL
+//GDC_DMA_SION_CL2_DataPoolCredit_Alloc_REG0
+#define GDC_DMA_SION_CL2_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT                          0x0
+#define GDC_DMA_SION_CL2_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0_MASK                            0xFFFFFFFFL
+//GDC_DMA_SION_CL2_DataPoolCredit_Alloc_REG1
+#define GDC_DMA_SION_CL2_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT                         0x0
+#define GDC_DMA_SION_CL2_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32_MASK                           0xFFFFFFFFL
+//GDC_DMA_SION_CL2_RdRspPoolCredit_Alloc_REG0
+#define GDC_DMA_SION_CL2_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT                        0x0
+#define GDC_DMA_SION_CL2_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0_MASK                          0xFFFFFFFFL
+//GDC_DMA_SION_CL2_RdRspPoolCredit_Alloc_REG1
+#define GDC_DMA_SION_CL2_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT                       0x0
+#define GDC_DMA_SION_CL2_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32_MASK                         0xFFFFFFFFL
+//GDC_DMA_SION_CL2_WrRspPoolCredit_Alloc_REG0
+#define GDC_DMA_SION_CL2_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT                        0x0
+#define GDC_DMA_SION_CL2_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0_MASK                          0xFFFFFFFFL
+//GDC_DMA_SION_CL2_WrRspPoolCredit_Alloc_REG1
+#define GDC_DMA_SION_CL2_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT                       0x0
+#define GDC_DMA_SION_CL2_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32_MASK                         0xFFFFFFFFL
+//GDC_DMA_SION_CNTL_REG0
+#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK0__SHIFT                    0x0
+#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK1__SHIFT                    0x1
+#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK2__SHIFT                    0x2
+#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK3__SHIFT                    0x3
+#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK4__SHIFT                    0x4
+#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK5__SHIFT                    0x5
+#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK6__SHIFT                    0x6
+#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK7__SHIFT                    0x7
+#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK8__SHIFT                    0x8
+#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK9__SHIFT                    0x9
+#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK0__SHIFT                    0xa
+#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK1__SHIFT                    0xb
+#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK2__SHIFT                    0xc
+#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK3__SHIFT                    0xd
+#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK4__SHIFT                    0xe
+#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK5__SHIFT                    0xf
+#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK6__SHIFT                    0x10
+#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK7__SHIFT                    0x11
+#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK8__SHIFT                    0x12
+#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK9__SHIFT                    0x13
+#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK0_MASK                      0x00000001L
+#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK1_MASK                      0x00000002L
+#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK2_MASK                      0x00000004L
+#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK3_MASK                      0x00000008L
+#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK4_MASK                      0x00000010L
+#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK5_MASK                      0x00000020L
+#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK6_MASK                      0x00000040L
+#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK7_MASK                      0x00000080L
+#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK8_MASK                      0x00000100L
+#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK9_MASK                      0x00000200L
+#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK0_MASK                      0x00000400L
+#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK1_MASK                      0x00000800L
+#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK2_MASK                      0x00001000L
+#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK3_MASK                      0x00002000L
+#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK4_MASK                      0x00004000L
+#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK5_MASK                      0x00008000L
+#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK6_MASK                      0x00010000L
+#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK7_MASK                      0x00020000L
+#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK8_MASK                      0x00040000L
+#define GDC_DMA_SION_CNTL_REG0__GDC_DMA_SION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK9_MASK                      0x00080000L
+//GDC_DMA_SION_CNTL_REG1
+#define GDC_DMA_SION_CNTL_REG1__GDC_DMA_SION_LIVELOCK_WATCHDOG_THRESHOLD__SHIFT                               0x0
+#define GDC_DMA_SION_CNTL_REG1__GDC_DMA_SION_CG_OFF_HYSTERESIS__SHIFT                                         0x8
+#define GDC_DMA_SION_CNTL_REG1__GDC_DMA_SION_LIVELOCK_WATCHDOG_THRESHOLD_MASK                                 0x000000FFL
+#define GDC_DMA_SION_CNTL_REG1__GDC_DMA_SION_CG_OFF_HYSTERESIS_MASK                                           0x0000FF00L
+
+
+// addressBlock: nbif0_nbif0_gdc_hst_sion_SIONDEC
+//GDC_HST_SION_CL0_RdRsp_BurstTarget_REG0
+#define GDC_HST_SION_CL0_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT                                0x0
+#define GDC_HST_SION_CL0_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0_MASK                                  0xFFFFFFFFL
+//GDC_HST_SION_CL0_RdRsp_BurstTarget_REG1
+#define GDC_HST_SION_CL0_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT                               0x0
+#define GDC_HST_SION_CL0_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32_MASK                                 0xFFFFFFFFL
+//GDC_HST_SION_CL0_RdRsp_TimeSlot_REG0
+#define GDC_HST_SION_CL0_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT                                      0x0
+#define GDC_HST_SION_CL0_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0_MASK                                        0xFFFFFFFFL
+//GDC_HST_SION_CL0_RdRsp_TimeSlot_REG1
+#define GDC_HST_SION_CL0_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT                                     0x0
+#define GDC_HST_SION_CL0_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32_MASK                                       0xFFFFFFFFL
+//GDC_HST_SION_CL0_WrRsp_BurstTarget_REG0
+#define GDC_HST_SION_CL0_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT                                0x0
+#define GDC_HST_SION_CL0_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0_MASK                                  0xFFFFFFFFL
+//GDC_HST_SION_CL0_WrRsp_BurstTarget_REG1
+#define GDC_HST_SION_CL0_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT                               0x0
+#define GDC_HST_SION_CL0_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32_MASK                                 0xFFFFFFFFL
+//GDC_HST_SION_CL0_WrRsp_TimeSlot_REG0
+#define GDC_HST_SION_CL0_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT                                      0x0
+#define GDC_HST_SION_CL0_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0_MASK                                        0xFFFFFFFFL
+//GDC_HST_SION_CL0_WrRsp_TimeSlot_REG1
+#define GDC_HST_SION_CL0_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT                                     0x0
+#define GDC_HST_SION_CL0_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32_MASK                                       0xFFFFFFFFL
+//GDC_HST_SION_CL0_Req_BurstTarget_REG0
+#define GDC_HST_SION_CL0_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT                                    0x0
+#define GDC_HST_SION_CL0_Req_BurstTarget_REG0__Req_BurstTarget_31_0_MASK                                      0xFFFFFFFFL
+//GDC_HST_SION_CL0_Req_BurstTarget_REG1
+#define GDC_HST_SION_CL0_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT                                   0x0
+#define GDC_HST_SION_CL0_Req_BurstTarget_REG1__Req_BurstTarget_63_32_MASK                                     0xFFFFFFFFL
+//GDC_HST_SION_CL0_Req_TimeSlot_REG0
+#define GDC_HST_SION_CL0_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT                                          0x0
+#define GDC_HST_SION_CL0_Req_TimeSlot_REG0__Req_TimeSlot_31_0_MASK                                            0xFFFFFFFFL
+//GDC_HST_SION_CL0_Req_TimeSlot_REG1
+#define GDC_HST_SION_CL0_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT                                         0x0
+#define GDC_HST_SION_CL0_Req_TimeSlot_REG1__Req_TimeSlot_63_32_MASK                                           0xFFFFFFFFL
+//GDC_HST_SION_CL0_ReqPoolCredit_Alloc_REG0
+#define GDC_HST_SION_CL0_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT                            0x0
+#define GDC_HST_SION_CL0_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0_MASK                              0xFFFFFFFFL
+//GDC_HST_SION_CL0_ReqPoolCredit_Alloc_REG1
+#define GDC_HST_SION_CL0_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT                           0x0
+#define GDC_HST_SION_CL0_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32_MASK                             0xFFFFFFFFL
+//GDC_HST_SION_CL0_DataPoolCredit_Alloc_REG0
+#define GDC_HST_SION_CL0_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT                          0x0
+#define GDC_HST_SION_CL0_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0_MASK                            0xFFFFFFFFL
+//GDC_HST_SION_CL0_DataPoolCredit_Alloc_REG1
+#define GDC_HST_SION_CL0_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT                         0x0
+#define GDC_HST_SION_CL0_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32_MASK                           0xFFFFFFFFL
+//GDC_HST_SION_CL0_RdRspPoolCredit_Alloc_REG0
+#define GDC_HST_SION_CL0_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT                        0x0
+#define GDC_HST_SION_CL0_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0_MASK                          0xFFFFFFFFL
+//GDC_HST_SION_CL0_RdRspPoolCredit_Alloc_REG1
+#define GDC_HST_SION_CL0_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT                       0x0
+#define GDC_HST_SION_CL0_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32_MASK                         0xFFFFFFFFL
+//GDC_HST_SION_CL0_WrRspPoolCredit_Alloc_REG0
+#define GDC_HST_SION_CL0_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT                        0x0
+#define GDC_HST_SION_CL0_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0_MASK                          0xFFFFFFFFL
+//GDC_HST_SION_CL0_WrRspPoolCredit_Alloc_REG1
+#define GDC_HST_SION_CL0_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT                       0x0
+#define GDC_HST_SION_CL0_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32_MASK                         0xFFFFFFFFL
+//GDC_HST_SION_CL1_RdRsp_BurstTarget_REG0
+#define GDC_HST_SION_CL1_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0__SHIFT                                0x0
+#define GDC_HST_SION_CL1_RdRsp_BurstTarget_REG0__RdRsp_BurstTarget_31_0_MASK                                  0xFFFFFFFFL
+//GDC_HST_SION_CL1_RdRsp_BurstTarget_REG1
+#define GDC_HST_SION_CL1_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32__SHIFT                               0x0
+#define GDC_HST_SION_CL1_RdRsp_BurstTarget_REG1__RdRsp_BurstTarget_63_32_MASK                                 0xFFFFFFFFL
+//GDC_HST_SION_CL1_RdRsp_TimeSlot_REG0
+#define GDC_HST_SION_CL1_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0__SHIFT                                      0x0
+#define GDC_HST_SION_CL1_RdRsp_TimeSlot_REG0__RdRsp_TimeSlot_31_0_MASK                                        0xFFFFFFFFL
+//GDC_HST_SION_CL1_RdRsp_TimeSlot_REG1
+#define GDC_HST_SION_CL1_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32__SHIFT                                     0x0
+#define GDC_HST_SION_CL1_RdRsp_TimeSlot_REG1__RdRsp_TimeSlot_63_32_MASK                                       0xFFFFFFFFL
+//GDC_HST_SION_CL1_WrRsp_BurstTarget_REG0
+#define GDC_HST_SION_CL1_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0__SHIFT                                0x0
+#define GDC_HST_SION_CL1_WrRsp_BurstTarget_REG0__WrRsp_BurstTarget_31_0_MASK                                  0xFFFFFFFFL
+//GDC_HST_SION_CL1_WrRsp_BurstTarget_REG1
+#define GDC_HST_SION_CL1_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32__SHIFT                               0x0
+#define GDC_HST_SION_CL1_WrRsp_BurstTarget_REG1__WrRsp_BurstTarget_63_32_MASK                                 0xFFFFFFFFL
+//GDC_HST_SION_CL1_WrRsp_TimeSlot_REG0
+#define GDC_HST_SION_CL1_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0__SHIFT                                      0x0
+#define GDC_HST_SION_CL1_WrRsp_TimeSlot_REG0__WrRsp_TimeSlot_31_0_MASK                                        0xFFFFFFFFL
+//GDC_HST_SION_CL1_WrRsp_TimeSlot_REG1
+#define GDC_HST_SION_CL1_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32__SHIFT                                     0x0
+#define GDC_HST_SION_CL1_WrRsp_TimeSlot_REG1__WrRsp_TimeSlot_63_32_MASK                                       0xFFFFFFFFL
+//GDC_HST_SION_CL1_Req_BurstTarget_REG0
+#define GDC_HST_SION_CL1_Req_BurstTarget_REG0__Req_BurstTarget_31_0__SHIFT                                    0x0
+#define GDC_HST_SION_CL1_Req_BurstTarget_REG0__Req_BurstTarget_31_0_MASK                                      0xFFFFFFFFL
+//GDC_HST_SION_CL1_Req_BurstTarget_REG1
+#define GDC_HST_SION_CL1_Req_BurstTarget_REG1__Req_BurstTarget_63_32__SHIFT                                   0x0
+#define GDC_HST_SION_CL1_Req_BurstTarget_REG1__Req_BurstTarget_63_32_MASK                                     0xFFFFFFFFL
+//GDC_HST_SION_CL1_Req_TimeSlot_REG0
+#define GDC_HST_SION_CL1_Req_TimeSlot_REG0__Req_TimeSlot_31_0__SHIFT                                          0x0
+#define GDC_HST_SION_CL1_Req_TimeSlot_REG0__Req_TimeSlot_31_0_MASK                                            0xFFFFFFFFL
+//GDC_HST_SION_CL1_Req_TimeSlot_REG1
+#define GDC_HST_SION_CL1_Req_TimeSlot_REG1__Req_TimeSlot_63_32__SHIFT                                         0x0
+#define GDC_HST_SION_CL1_Req_TimeSlot_REG1__Req_TimeSlot_63_32_MASK                                           0xFFFFFFFFL
+//GDC_HST_SION_CL1_ReqPoolCredit_Alloc_REG0
+#define GDC_HST_SION_CL1_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0__SHIFT                            0x0
+#define GDC_HST_SION_CL1_ReqPoolCredit_Alloc_REG0__ReqPoolCredit_Alloc_31_0_MASK                              0xFFFFFFFFL
+//GDC_HST_SION_CL1_ReqPoolCredit_Alloc_REG1
+#define GDC_HST_SION_CL1_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32__SHIFT                           0x0
+#define GDC_HST_SION_CL1_ReqPoolCredit_Alloc_REG1__ReqPoolCredit_Alloc_63_32_MASK                             0xFFFFFFFFL
+//GDC_HST_SION_CL1_DataPoolCredit_Alloc_REG0
+#define GDC_HST_SION_CL1_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0__SHIFT                          0x0
+#define GDC_HST_SION_CL1_DataPoolCredit_Alloc_REG0__DataPoolCredit_Alloc_31_0_MASK                            0xFFFFFFFFL
+//GDC_HST_SION_CL1_DataPoolCredit_Alloc_REG1
+#define GDC_HST_SION_CL1_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32__SHIFT                         0x0
+#define GDC_HST_SION_CL1_DataPoolCredit_Alloc_REG1__DataPoolCredit_Alloc_63_32_MASK                           0xFFFFFFFFL
+//GDC_HST_SION_CL1_RdRspPoolCredit_Alloc_REG0
+#define GDC_HST_SION_CL1_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0__SHIFT                        0x0
+#define GDC_HST_SION_CL1_RdRspPoolCredit_Alloc_REG0__RdRspPoolCredit_Alloc_31_0_MASK                          0xFFFFFFFFL
+//GDC_HST_SION_CL1_RdRspPoolCredit_Alloc_REG1
+#define GDC_HST_SION_CL1_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32__SHIFT                       0x0
+#define GDC_HST_SION_CL1_RdRspPoolCredit_Alloc_REG1__RdRspPoolCredit_Alloc_63_32_MASK                         0xFFFFFFFFL
+//GDC_HST_SION_CL1_WrRspPoolCredit_Alloc_REG0
+#define GDC_HST_SION_CL1_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0__SHIFT                        0x0
+#define GDC_HST_SION_CL1_WrRspPoolCredit_Alloc_REG0__WrRspPoolCredit_Alloc_31_0_MASK                          0xFFFFFFFFL
+//GDC_HST_SION_CL1_WrRspPoolCredit_Alloc_REG1
+#define GDC_HST_SION_CL1_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32__SHIFT                       0x0
+#define GDC_HST_SION_CL1_WrRspPoolCredit_Alloc_REG1__WrRspPoolCredit_Alloc_63_32_MASK                         0xFFFFFFFFL
+//GDC_HST_SION_CNTL_REG0
+#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK0__SHIFT                     0x0
+#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK1__SHIFT                     0x1
+#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK2__SHIFT                     0x2
+#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK3__SHIFT                     0x3
+#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK4__SHIFT                     0x4
+#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK5__SHIFT                     0x5
+#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK6__SHIFT                     0x6
+#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK7__SHIFT                     0x7
+#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK8__SHIFT                     0x8
+#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK9__SHIFT                     0x9
+#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK0__SHIFT                     0xa
+#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK1__SHIFT                     0xb
+#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK2__SHIFT                     0xc
+#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK3__SHIFT                     0xd
+#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK4__SHIFT                     0xe
+#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK5__SHIFT                     0xf
+#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK6__SHIFT                     0x10
+#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK7__SHIFT                     0x11
+#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK8__SHIFT                     0x12
+#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK9__SHIFT                     0x13
+#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK0_MASK                       0x00000001L
+#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK1_MASK                       0x00000002L
+#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK2_MASK                       0x00000004L
+#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK3_MASK                       0x00000008L
+#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK4_MASK                       0x00000010L
+#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK5_MASK                       0x00000020L
+#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK6_MASK                       0x00000040L
+#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK7_MASK                       0x00000080L
+#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK8_MASK                       0x00000100L
+#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_0_SOFT_OVERRIDE_CLK9_MASK                       0x00000200L
+#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK0_MASK                       0x00000400L
+#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK1_MASK                       0x00000800L
+#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK2_MASK                       0x00001000L
+#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK3_MASK                       0x00002000L
+#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK4_MASK                       0x00004000L
+#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK5_MASK                       0x00008000L
+#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK6_MASK                       0x00010000L
+#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK7_MASK                       0x00020000L
+#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK8_MASK                       0x00040000L
+#define GDC_HST_SION_CNTL_REG0__GDC_HSTSION_GLUE_CG_LCLK_CTRL_1_SOFT_OVERRIDE_CLK9_MASK                       0x00080000L
+//GDC_HST_SION_CNTL_REG1
+#define GDC_HST_SION_CNTL_REG1__GDC_HSTSION_LIVELOCK_WATCHDOG_THRESHOLD__SHIFT                                0x0
+#define GDC_HST_SION_CNTL_REG1__GDC_HSTSION_CG_OFF_HYSTERESIS__SHIFT                                          0x8
+#define GDC_HST_SION_CNTL_REG1__GDC_HSTSION_LIVE_ACTIVE__SHIFT                                                0x10
+#define GDC_HST_SION_CNTL_REG1__GDC_HSTSION_LIVELOCK_WATCHDOG_THRESHOLD_MASK                                  0x000000FFL
+#define GDC_HST_SION_CNTL_REG1__GDC_HSTSION_CG_OFF_HYSTERESIS_MASK                                            0x0000FF00L
+#define GDC_HST_SION_CNTL_REG1__GDC_HSTSION_LIVE_ACTIVE_MASK                                                  0xFFFF0000L
+
+
+// addressBlock: nbif0_nbif0_gdc_GDCDEC
+//GDC1_NGDC_SDP_PORT_CTRL
+#define GDC1_NGDC_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS__SHIFT                                                 0x0
+#define GDC1_NGDC_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS_H__SHIFT                                               0x10
+#define GDC1_NGDC_SDP_PORT_CTRL__SDP_DISCON_DIS__SHIFT                                                        0x1f
+#define GDC1_NGDC_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS_MASK                                                   0x000000FFL
+#define GDC1_NGDC_SDP_PORT_CTRL__SDP_DISCON_HYSTERESIS_H_MASK                                                 0x000F0000L
+#define GDC1_NGDC_SDP_PORT_CTRL__SDP_DISCON_DIS_MASK                                                          0x80000000L
+//GDC1_SHUB_REGS_IF_CTL
+#define GDC1_SHUB_REGS_IF_CTL__SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS__SHIFT                                0x0
+#define GDC1_SHUB_REGS_IF_CTL__SHUB_REGS_VF_PROTECTION_DIS__SHIFT                                             0x1
+#define GDC1_SHUB_REGS_IF_CTL__SHUB_REGS_DROP_NONPF_MMREGREQ_SETERR_DIS_MASK                                  0x00000001L
+#define GDC1_SHUB_REGS_IF_CTL__SHUB_REGS_VF_PROTECTION_DIS_MASK                                               0x00000002L
+//GDC1_NGDC_MGCG_CTRL
+#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_EN__SHIFT                                                              0x0
+#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_MODE__SHIFT                                                            0x1
+#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_HYSTERESIS__SHIFT                                                      0x2
+#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_HST_DIS__SHIFT                                                         0xa
+#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_DMA_DIS__SHIFT                                                         0xb
+#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_REG_DIS__SHIFT                                                         0xc
+#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_AER_DIS__SHIFT                                                         0xd
+#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_DBG_DIS__SHIFT                                                         0xe
+#define GDC1_NGDC_MGCG_CTRL__NGDC_SRAM_FGCG_EN__SHIFT                                                         0xf
+#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_EN_MASK                                                                0x00000001L
+#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_MODE_MASK                                                              0x00000002L
+#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_HYSTERESIS_MASK                                                        0x000003FCL
+#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_HST_DIS_MASK                                                           0x00000400L
+#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_DMA_DIS_MASK                                                           0x00000800L
+#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_REG_DIS_MASK                                                           0x00001000L
+#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_AER_DIS_MASK                                                           0x00002000L
+#define GDC1_NGDC_MGCG_CTRL__NGDC_MGCG_DBG_DIS_MASK                                                           0x00004000L
+#define GDC1_NGDC_MGCG_CTRL__NGDC_SRAM_FGCG_EN_MASK                                                           0x00008000L
+//GDC1_S2A_MISC_CNTL
+#define GDC1_S2A_MISC_CNTL__AXI_HST_CPL_EP_DIS__SHIFT                                                         0x3
+#define GDC1_S2A_MISC_CNTL__ATM_ARB_MODE__SHIFT                                                               0x8
+#define GDC1_S2A_MISC_CNTL__RB_ARB_MODE__SHIFT                                                                0xa
+#define GDC1_S2A_MISC_CNTL__HSTR_ARB_MODE__SHIFT                                                              0xc
+#define GDC1_S2A_MISC_CNTL__HDP_PERF_ENH_DIS__SHIFT                                                           0xf
+#define GDC1_S2A_MISC_CNTL__WRSP_ARB_MODE__SHIFT                                                              0x10
+#define GDC1_S2A_MISC_CNTL__AXI_HST_CPL_EP_DIS_MASK                                                           0x00000008L
+#define GDC1_S2A_MISC_CNTL__ATM_ARB_MODE_MASK                                                                 0x00000300L
+#define GDC1_S2A_MISC_CNTL__RB_ARB_MODE_MASK                                                                  0x00000C00L
+#define GDC1_S2A_MISC_CNTL__HSTR_ARB_MODE_MASK                                                                0x00003000L
+#define GDC1_S2A_MISC_CNTL__HDP_PERF_ENH_DIS_MASK                                                             0x00008000L
+#define GDC1_S2A_MISC_CNTL__WRSP_ARB_MODE_MASK                                                                0x000F0000L
+//GDC1_NGDC_MCA_SMN_CTRL0
+#define GDC1_NGDC_MCA_SMN_CTRL0__MCA_SMN_POSTED__SHIFT                                                        0x0
+#define GDC1_NGDC_MCA_SMN_CTRL0__MCA_SMN_POSTED_MASK                                                          0x00000001L
+//GDC1_NGDC_EARLY_WAKEUP_CTRL
+#define GDC1_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_BY_CLIENT_ACTIVE__SHIFT                                0x0
+#define GDC1_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_BY_CLIENT_DS_EXIT__SHIFT                               0x1
+#define GDC1_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_ALLOW_AER_ACTIVE__SHIFT                                0x2
+#define GDC1_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_BY_CLIENT_ACTIVE_MASK                                  0x00000001L
+#define GDC1_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_BY_CLIENT_DS_EXIT_MASK                                 0x00000002L
+#define GDC1_NGDC_EARLY_WAKEUP_CTRL__NGDC_EARLY_WAKEUP_ALLOW_AER_ACTIVE_MASK                                  0x00000004L
+//GDC1_GDC_GDCCLK_S2A_ERR_RSP_CNTL
+#define GDC1_GDC_GDCCLK_S2A_ERR_RSP_CNTL__GDC_GDCCLK_S2A_RDRSP_BYPASS__SHIFT                                  0x0
+#define GDC1_GDC_GDCCLK_S2A_ERR_RSP_CNTL__GDC_GDCCLK_S2A_RDRSP_ACCUM_SEL__SHIFT                               0x1
+#define GDC1_GDC_GDCCLK_S2A_ERR_RSP_CNTL__GDC_GDCCLK_S2A_RDRSP_FORCE_EN__SHIFT                                0x2
+#define GDC1_GDC_GDCCLK_S2A_ERR_RSP_CNTL__GDC_GDCCLK_S2A_RDRSP_FORCE_DATA__SHIFT                              0x3
+#define GDC1_GDC_GDCCLK_S2A_ERR_RSP_CNTL__GDC_GDCCLK_S2A_RDRSP_STATUS_ACCUM_EN__SHIFT                         0x4
+#define GDC1_GDC_GDCCLK_S2A_ERR_RSP_CNTL__GDC_GDCCLK_S2A_RDRSP_DATASTATUS_ACCUM_EN__SHIFT                     0x5
+#define GDC1_GDC_GDCCLK_S2A_ERR_RSP_CNTL__GDC_GDCCLK_S2A_RDRSP_BYPASS_MASK                                    0x00000001L
+#define GDC1_GDC_GDCCLK_S2A_ERR_RSP_CNTL__GDC_GDCCLK_S2A_RDRSP_ACCUM_SEL_MASK                                 0x00000002L
+#define GDC1_GDC_GDCCLK_S2A_ERR_RSP_CNTL__GDC_GDCCLK_S2A_RDRSP_FORCE_EN_MASK                                  0x00000004L
+#define GDC1_GDC_GDCCLK_S2A_ERR_RSP_CNTL__GDC_GDCCLK_S2A_RDRSP_FORCE_DATA_MASK                                0x00000008L
+#define GDC1_GDC_GDCCLK_S2A_ERR_RSP_CNTL__GDC_GDCCLK_S2A_RDRSP_STATUS_ACCUM_EN_MASK                           0x00000010L
+#define GDC1_GDC_GDCCLK_S2A_ERR_RSP_CNTL__GDC_GDCCLK_S2A_RDRSP_DATASTATUS_ACCUM_EN_MASK                       0x00000020L
+//GDC1_GDC_DMA_SION_PCTRL
+#define GDC1_GDC_DMA_SION_PCTRL__BIF_SDP_DISCON_DIS__SHIFT                                                    0x0
+#define GDC1_GDC_DMA_SION_PCTRL__SYSHUB_SDP_DISCON_DIS__SHIFT                                                 0x3
+#define GDC1_GDC_DMA_SION_PCTRL__INT_SDP_DISCON_DIS__SHIFT                                                    0x6
+#define GDC1_GDC_DMA_SION_PCTRL__BIF_SDP_DISCON_DIS_MASK                                                      0x00000001L
+#define GDC1_GDC_DMA_SION_PCTRL__SYSHUB_SDP_DISCON_DIS_MASK                                                   0x00000008L
+#define GDC1_GDC_DMA_SION_PCTRL__INT_SDP_DISCON_DIS_MASK                                                      0x00000040L
+//GDC1_NGDC_MP4SDP_CNTL
+#define GDC1_NGDC_MP4SDP_CNTL__MP4SDP_BLKLVL_VC0_OVERRIDE_EN__SHIFT                                           0x0
+#define GDC1_NGDC_MP4SDP_CNTL__MP4SDP_BLKLVL_VC0_OVERRIDE_VAL__SHIFT                                          0x1
+#define GDC1_NGDC_MP4SDP_CNTL__MP4SDP_BLKLVL_VC1_OVERRIDE_EN__SHIFT                                           0x4
+#define GDC1_NGDC_MP4SDP_CNTL__MP4SDP_BLKLVL_VC1_OVERRIDE_VAL__SHIFT                                          0x5
+#define GDC1_NGDC_MP4SDP_CNTL__MP4SDP_BLKLVL_VC4_OVERRIDE_EN__SHIFT                                           0x8
+#define GDC1_NGDC_MP4SDP_CNTL__MP4SDP_BLKLVL_VC4_OVERRIDE_VAL__SHIFT                                          0x9
+#define GDC1_NGDC_MP4SDP_CNTL__MP4SDP_BLKLVL_VC0_OVERRIDE_EN_MASK                                             0x00000001L
+#define GDC1_NGDC_MP4SDP_CNTL__MP4SDP_BLKLVL_VC0_OVERRIDE_VAL_MASK                                            0x00000006L
+#define GDC1_NGDC_MP4SDP_CNTL__MP4SDP_BLKLVL_VC1_OVERRIDE_EN_MASK                                             0x00000010L
+#define GDC1_NGDC_MP4SDP_CNTL__MP4SDP_BLKLVL_VC1_OVERRIDE_VAL_MASK                                            0x00000060L
+#define GDC1_NGDC_MP4SDP_CNTL__MP4SDP_BLKLVL_VC4_OVERRIDE_EN_MASK                                             0x00000100L
+#define GDC1_NGDC_MP4SDP_CNTL__MP4SDP_BLKLVL_VC4_OVERRIDE_VAL_MASK                                            0x00000600L
+//GDC1_DOORBELL_VCN_TARGET_VF0
+#define GDC1_DOORBELL_VCN_TARGET_VF0__DOORBELL_VCN0_TARGET_VF0__SHIFT                                         0x0
+#define GDC1_DOORBELL_VCN_TARGET_VF0__DOORBELL_VCN1_TARGET_VF0__SHIFT                                         0x4
+#define GDC1_DOORBELL_VCN_TARGET_VF0__DOORBELL_VCN2_TARGET_VF0__SHIFT                                         0x8
+#define GDC1_DOORBELL_VCN_TARGET_VF0__DOORBELL_VCN3_TARGET_VF0__SHIFT                                         0xc
+#define GDC1_DOORBELL_VCN_TARGET_VF0__DOORBELL_VCN0_TARGET_VF0_MASK                                           0x000FL
+#define GDC1_DOORBELL_VCN_TARGET_VF0__DOORBELL_VCN1_TARGET_VF0_MASK                                           0x00F0L
+#define GDC1_DOORBELL_VCN_TARGET_VF0__DOORBELL_VCN2_TARGET_VF0_MASK                                           0x0F00L
+#define GDC1_DOORBELL_VCN_TARGET_VF0__DOORBELL_VCN3_TARGET_VF0_MASK                                           0xF000L
+//GDC1_DOORBELL_VCN_TARGET_VF1
+#define GDC1_DOORBELL_VCN_TARGET_VF1__DOORBELL_VCN0_TARGET_VF1__SHIFT                                         0x0
+#define GDC1_DOORBELL_VCN_TARGET_VF1__DOORBELL_VCN1_TARGET_VF1__SHIFT                                         0x4
+#define GDC1_DOORBELL_VCN_TARGET_VF1__DOORBELL_VCN2_TARGET_VF1__SHIFT                                         0x8
+#define GDC1_DOORBELL_VCN_TARGET_VF1__DOORBELL_VCN3_TARGET_VF1__SHIFT                                         0xc
+#define GDC1_DOORBELL_VCN_TARGET_VF1__DOORBELL_VCN0_TARGET_VF1_MASK                                           0x000FL
+#define GDC1_DOORBELL_VCN_TARGET_VF1__DOORBELL_VCN1_TARGET_VF1_MASK                                           0x00F0L
+#define GDC1_DOORBELL_VCN_TARGET_VF1__DOORBELL_VCN2_TARGET_VF1_MASK                                           0x0F00L
+#define GDC1_DOORBELL_VCN_TARGET_VF1__DOORBELL_VCN3_TARGET_VF1_MASK                                           0xF000L
+//GDC1_DOORBELL_VCN_TARGET_VF2
+#define GDC1_DOORBELL_VCN_TARGET_VF2__DOORBELL_VCN0_TARGET_VF2__SHIFT                                         0x0
+#define GDC1_DOORBELL_VCN_TARGET_VF2__DOORBELL_VCN1_TARGET_VF2__SHIFT                                         0x4
+#define GDC1_DOORBELL_VCN_TARGET_VF2__DOORBELL_VCN2_TARGET_VF2__SHIFT                                         0x8
+#define GDC1_DOORBELL_VCN_TARGET_VF2__DOORBELL_VCN3_TARGET_VF2__SHIFT                                         0xc
+#define GDC1_DOORBELL_VCN_TARGET_VF2__DOORBELL_VCN0_TARGET_VF2_MASK                                           0x000FL
+#define GDC1_DOORBELL_VCN_TARGET_VF2__DOORBELL_VCN1_TARGET_VF2_MASK                                           0x00F0L
+#define GDC1_DOORBELL_VCN_TARGET_VF2__DOORBELL_VCN2_TARGET_VF2_MASK                                           0x0F00L
+#define GDC1_DOORBELL_VCN_TARGET_VF2__DOORBELL_VCN3_TARGET_VF2_MASK                                           0xF000L
+//GDC1_DOORBELL_VCN_TARGET_VF3
+#define GDC1_DOORBELL_VCN_TARGET_VF3__DOORBELL_VCN0_TARGET_VF3__SHIFT                                         0x0
+#define GDC1_DOORBELL_VCN_TARGET_VF3__DOORBELL_VCN1_TARGET_VF3__SHIFT                                         0x4
+#define GDC1_DOORBELL_VCN_TARGET_VF3__DOORBELL_VCN2_TARGET_VF3__SHIFT                                         0x8
+#define GDC1_DOORBELL_VCN_TARGET_VF3__DOORBELL_VCN3_TARGET_VF3__SHIFT                                         0xc
+#define GDC1_DOORBELL_VCN_TARGET_VF3__DOORBELL_VCN0_TARGET_VF3_MASK                                           0x000FL
+#define GDC1_DOORBELL_VCN_TARGET_VF3__DOORBELL_VCN1_TARGET_VF3_MASK                                           0x00F0L
+#define GDC1_DOORBELL_VCN_TARGET_VF3__DOORBELL_VCN2_TARGET_VF3_MASK                                           0x0F00L
+#define GDC1_DOORBELL_VCN_TARGET_VF3__DOORBELL_VCN3_TARGET_VF3_MASK                                           0xF000L
+//GDC1_DOORBELL_VCN_TARGET_VF4
+#define GDC1_DOORBELL_VCN_TARGET_VF4__DOORBELL_VCN0_TARGET_VF4__SHIFT                                         0x0
+#define GDC1_DOORBELL_VCN_TARGET_VF4__DOORBELL_VCN1_TARGET_VF4__SHIFT                                         0x4
+#define GDC1_DOORBELL_VCN_TARGET_VF4__DOORBELL_VCN2_TARGET_VF4__SHIFT                                         0x8
+#define GDC1_DOORBELL_VCN_TARGET_VF4__DOORBELL_VCN3_TARGET_VF4__SHIFT                                         0xc
+#define GDC1_DOORBELL_VCN_TARGET_VF4__DOORBELL_VCN0_TARGET_VF4_MASK                                           0x000FL
+#define GDC1_DOORBELL_VCN_TARGET_VF4__DOORBELL_VCN1_TARGET_VF4_MASK                                           0x00F0L
+#define GDC1_DOORBELL_VCN_TARGET_VF4__DOORBELL_VCN2_TARGET_VF4_MASK                                           0x0F00L
+#define GDC1_DOORBELL_VCN_TARGET_VF4__DOORBELL_VCN3_TARGET_VF4_MASK                                           0xF000L
+//GDC1_DOORBELL_VCN_TARGET_VF5
+#define GDC1_DOORBELL_VCN_TARGET_VF5__DOORBELL_VCN0_TARGET_VF5__SHIFT                                         0x0
+#define GDC1_DOORBELL_VCN_TARGET_VF5__DOORBELL_VCN1_TARGET_VF5__SHIFT                                         0x4
+#define GDC1_DOORBELL_VCN_TARGET_VF5__DOORBELL_VCN2_TARGET_VF5__SHIFT                                         0x8
+#define GDC1_DOORBELL_VCN_TARGET_VF5__DOORBELL_VCN3_TARGET_VF5__SHIFT                                         0xc
+#define GDC1_DOORBELL_VCN_TARGET_VF5__DOORBELL_VCN0_TARGET_VF5_MASK                                           0x000FL
+#define GDC1_DOORBELL_VCN_TARGET_VF5__DOORBELL_VCN1_TARGET_VF5_MASK                                           0x00F0L
+#define GDC1_DOORBELL_VCN_TARGET_VF5__DOORBELL_VCN2_TARGET_VF5_MASK                                           0x0F00L
+#define GDC1_DOORBELL_VCN_TARGET_VF5__DOORBELL_VCN3_TARGET_VF5_MASK                                           0xF000L
+//GDC1_DOORBELL_VCN_TARGET_VF6
+#define GDC1_DOORBELL_VCN_TARGET_VF6__DOORBELL_VCN0_TARGET_VF6__SHIFT                                         0x0
+#define GDC1_DOORBELL_VCN_TARGET_VF6__DOORBELL_VCN1_TARGET_VF6__SHIFT                                         0x4
+#define GDC1_DOORBELL_VCN_TARGET_VF6__DOORBELL_VCN2_TARGET_VF6__SHIFT                                         0x8
+#define GDC1_DOORBELL_VCN_TARGET_VF6__DOORBELL_VCN3_TARGET_VF6__SHIFT                                         0xc
+#define GDC1_DOORBELL_VCN_TARGET_VF6__DOORBELL_VCN0_TARGET_VF6_MASK                                           0x000FL
+#define GDC1_DOORBELL_VCN_TARGET_VF6__DOORBELL_VCN1_TARGET_VF6_MASK                                           0x00F0L
+#define GDC1_DOORBELL_VCN_TARGET_VF6__DOORBELL_VCN2_TARGET_VF6_MASK                                           0x0F00L
+#define GDC1_DOORBELL_VCN_TARGET_VF6__DOORBELL_VCN3_TARGET_VF6_MASK                                           0xF000L
+//GDC1_DOORBELL_VCN_TARGET_VF7
+#define GDC1_DOORBELL_VCN_TARGET_VF7__DOORBELL_VCN0_TARGET_VF7__SHIFT                                         0x0
+#define GDC1_DOORBELL_VCN_TARGET_VF7__DOORBELL_VCN1_TARGET_VF7__SHIFT                                         0x4
+#define GDC1_DOORBELL_VCN_TARGET_VF7__DOORBELL_VCN2_TARGET_VF7__SHIFT                                         0x8
+#define GDC1_DOORBELL_VCN_TARGET_VF7__DOORBELL_VCN3_TARGET_VF7__SHIFT                                         0xc
+#define GDC1_DOORBELL_VCN_TARGET_VF7__DOORBELL_VCN0_TARGET_VF7_MASK                                           0x000FL
+#define GDC1_DOORBELL_VCN_TARGET_VF7__DOORBELL_VCN1_TARGET_VF7_MASK                                           0x00F0L
+#define GDC1_DOORBELL_VCN_TARGET_VF7__DOORBELL_VCN2_TARGET_VF7_MASK                                           0x0F00L
+#define GDC1_DOORBELL_VCN_TARGET_VF7__DOORBELL_VCN3_TARGET_VF7_MASK                                           0xF000L
+//GDC1_DOORBELL_ACCESS_EN_PF
+#define GDC1_DOORBELL_ACCESS_EN_PF__DOORBELL_ACCESS_EN_PF__SHIFT                                              0x0
+#define GDC1_DOORBELL_ACCESS_EN_PF__DOORBELL_ACCESS_EN_PF_MASK                                                0x00FFL
+//GDC1_DOORBELL_ACCESS_EN_VF0
+#define GDC1_DOORBELL_ACCESS_EN_VF0__DOORBELL_ACCESS_EN_VF0__SHIFT                                            0x0
+#define GDC1_DOORBELL_ACCESS_EN_VF0__XCD_ACCESS_EN_VF0__SHIFT                                                 0x8
+#define GDC1_DOORBELL_ACCESS_EN_VF0__DOORBELL_ACCESS_EN_VF0_MASK                                              0x00FFL
+#define GDC1_DOORBELL_ACCESS_EN_VF0__XCD_ACCESS_EN_VF0_MASK                                                   0xFF00L
+//GDC1_DOORBELL_ACCESS_EN_VF1
+#define GDC1_DOORBELL_ACCESS_EN_VF1__DOORBELL_ACCESS_EN_VF1__SHIFT                                            0x0
+#define GDC1_DOORBELL_ACCESS_EN_VF1__XCD_ACCESS_EN_VF1__SHIFT                                                 0x8
+#define GDC1_DOORBELL_ACCESS_EN_VF1__DOORBELL_ACCESS_EN_VF1_MASK                                              0x00FFL
+#define GDC1_DOORBELL_ACCESS_EN_VF1__XCD_ACCESS_EN_VF1_MASK                                                   0xFF00L
+//GDC1_DOORBELL_ACCESS_EN_VF2
+#define GDC1_DOORBELL_ACCESS_EN_VF2__DOORBELL_ACCESS_EN_VF2__SHIFT                                            0x0
+#define GDC1_DOORBELL_ACCESS_EN_VF2__XCD_ACCESS_EN_VF2__SHIFT                                                 0x8
+#define GDC1_DOORBELL_ACCESS_EN_VF2__DOORBELL_ACCESS_EN_VF2_MASK                                              0x00FFL
+#define GDC1_DOORBELL_ACCESS_EN_VF2__XCD_ACCESS_EN_VF2_MASK                                                   0xFF00L
+//GDC1_DOORBELL_ACCESS_EN_VF3
+#define GDC1_DOORBELL_ACCESS_EN_VF3__DOORBELL_ACCESS_EN_VF3__SHIFT                                            0x0
+#define GDC1_DOORBELL_ACCESS_EN_VF3__XCD_ACCESS_EN_VF3__SHIFT                                                 0x8
+#define GDC1_DOORBELL_ACCESS_EN_VF3__DOORBELL_ACCESS_EN_VF3_MASK                                              0x00FFL
+#define GDC1_DOORBELL_ACCESS_EN_VF3__XCD_ACCESS_EN_VF3_MASK                                                   0xFF00L
+//GDC1_DOORBELL_ACCESS_EN_VF4
+#define GDC1_DOORBELL_ACCESS_EN_VF4__DOORBELL_ACCESS_EN_VF4__SHIFT                                            0x0
+#define GDC1_DOORBELL_ACCESS_EN_VF4__XCD_ACCESS_EN_VF4__SHIFT                                                 0x8
+#define GDC1_DOORBELL_ACCESS_EN_VF4__DOORBELL_ACCESS_EN_VF4_MASK                                              0x00FFL
+#define GDC1_DOORBELL_ACCESS_EN_VF4__XCD_ACCESS_EN_VF4_MASK                                                   0xFF00L
+//GDC1_DOORBELL_ACCESS_EN_VF5
+#define GDC1_DOORBELL_ACCESS_EN_VF5__DOORBELL_ACCESS_EN_VF5__SHIFT                                            0x0
+#define GDC1_DOORBELL_ACCESS_EN_VF5__XCD_ACCESS_EN_VF5__SHIFT                                                 0x8
+#define GDC1_DOORBELL_ACCESS_EN_VF5__DOORBELL_ACCESS_EN_VF5_MASK                                              0x00FFL
+#define GDC1_DOORBELL_ACCESS_EN_VF5__XCD_ACCESS_EN_VF5_MASK                                                   0xFF00L
+//GDC1_DOORBELL_ACCESS_EN_VF6
+#define GDC1_DOORBELL_ACCESS_EN_VF6__DOORBELL_ACCESS_EN_VF6__SHIFT                                            0x0
+#define GDC1_DOORBELL_ACCESS_EN_VF6__XCD_ACCESS_EN_VF6__SHIFT                                                 0x8
+#define GDC1_DOORBELL_ACCESS_EN_VF6__DOORBELL_ACCESS_EN_VF6_MASK                                              0x00FFL
+#define GDC1_DOORBELL_ACCESS_EN_VF6__XCD_ACCESS_EN_VF6_MASK                                                   0xFF00L
+//GDC1_DOORBELL_ACCESS_EN_VF7
+#define GDC1_DOORBELL_ACCESS_EN_VF7__DOORBELL_ACCESS_EN_VF7__SHIFT                                            0x0
+#define GDC1_DOORBELL_ACCESS_EN_VF7__XCD_ACCESS_EN_VF7__SHIFT                                                 0x8
+#define GDC1_DOORBELL_ACCESS_EN_VF7__DOORBELL_ACCESS_EN_VF7_MASK                                              0x00FFL
+#define GDC1_DOORBELL_ACCESS_EN_VF7__XCD_ACCESS_EN_VF7_MASK                                                   0xFF00L
+//GDC1_NGDC_CNDI_BUS_PORT_CTRL
+#define GDC1_NGDC_CNDI_BUS_PORT_CTRL__CNDI_ORIG_DISCON_HYSTERESIS__SHIFT                                      0x0
+#define GDC1_NGDC_CNDI_BUS_PORT_CTRL__CNDI_ORIG_DISCON_DIS_SOCCLK__SHIFT                                      0xc
+#define GDC1_NGDC_CNDI_BUS_PORT_CTRL__CNDI_CMPL_DISCON_HYSTERESIS__SHIFT                                      0xd
+#define GDC1_NGDC_CNDI_BUS_PORT_CTRL__CNDI_CMPL_DISCON_DIS_SOCCLK__SHIFT                                      0x19
+#define GDC1_NGDC_CNDI_BUS_PORT_CTRL__CNDI_ORIG_PORT_IDLE__SHIFT                                              0x1a
+#define GDC1_NGDC_CNDI_BUS_PORT_CTRL__SHUB_CNDI_VDCI_CKEN_MASK__SHIFT                                         0x1b
+#define GDC1_NGDC_CNDI_BUS_PORT_CTRL__CNDI_ORIG_DISCON_HYSTERESIS_MASK                                        0x00000FFFL
+#define GDC1_NGDC_CNDI_BUS_PORT_CTRL__CNDI_ORIG_DISCON_DIS_SOCCLK_MASK                                        0x00001000L
+#define GDC1_NGDC_CNDI_BUS_PORT_CTRL__CNDI_CMPL_DISCON_HYSTERESIS_MASK                                        0x01FFE000L
+#define GDC1_NGDC_CNDI_BUS_PORT_CTRL__CNDI_CMPL_DISCON_DIS_SOCCLK_MASK                                        0x02000000L
+#define GDC1_NGDC_CNDI_BUS_PORT_CTRL__CNDI_ORIG_PORT_IDLE_MASK                                                0x04000000L
+#define GDC1_NGDC_CNDI_BUS_PORT_CTRL__SHUB_CNDI_VDCI_CKEN_MASK_MASK                                           0x08000000L
+//GDC1_NGDC_CNDI_BUS_POOL_CRED_CTRL
+#define GDC1_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_CMPL_WRRSP_POOLCRED_ALLOC_VC0_ALLOC__SHIFT                    0x0
+#define GDC1_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_CMPL_WRRSP_POOLCRED_ALLOC_VC1_ALLOC__SHIFT                    0x4
+#define GDC1_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_CMPL_RDRSP_POOLCRED_ALLOC_VC0_ALLOC__SHIFT                    0x8
+#define GDC1_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_CMPL_RDRSP_POOLCRED_ALLOC_VC1_ALLOC__SHIFT                    0xc
+#define GDC1_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_ORIG_REQ_POOL_CREDIT_ALLOC_OVERRIDE_DYNAMIC__SHIFT            0x10
+#define GDC1_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_ORIG_ORIGDATA_POOL_CREDIT_ALLOC_OVERRIDE_DYNAMIC__SHIFT       0x11
+#define GDC1_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_CMPL_WRRSP_POOL_CREDIT_ALLOC_OVERRIDE_DYNAMIC__SHIFT          0x12
+#define GDC1_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_CMPL_RDRSP_POOL_CREDIT_ALLOC_OVERRIDE_DYNAMIC__SHIFT          0x13
+#define GDC1_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_CMPL_WRRSP_POOLCRED_ALLOC_VC0_ALLOC_MASK                      0x0000000FL
+#define GDC1_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_CMPL_WRRSP_POOLCRED_ALLOC_VC1_ALLOC_MASK                      0x000000F0L
+#define GDC1_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_CMPL_RDRSP_POOLCRED_ALLOC_VC0_ALLOC_MASK                      0x00000F00L
+#define GDC1_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_CMPL_RDRSP_POOLCRED_ALLOC_VC1_ALLOC_MASK                      0x0000F000L
+#define GDC1_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_ORIG_REQ_POOL_CREDIT_ALLOC_OVERRIDE_DYNAMIC_MASK              0x00010000L
+#define GDC1_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_ORIG_ORIGDATA_POOL_CREDIT_ALLOC_OVERRIDE_DYNAMIC_MASK         0x00020000L
+#define GDC1_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_CMPL_WRRSP_POOL_CREDIT_ALLOC_OVERRIDE_DYNAMIC_MASK            0x00040000L
+#define GDC1_NGDC_CNDI_BUS_POOL_CRED_CTRL__CNDI_CMPL_RDRSP_POOL_CREDIT_ALLOC_OVERRIDE_DYNAMIC_MASK            0x00080000L
+
+
+// addressBlock: nbif0_nbif0_gdc_ras_gdc_ras_regblk
+//GDCSOC_ERR_RSP_CNTL
+#define GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_BYPASS__SHIFT                                                       0x0
+#define GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_ACCUM_SEL__SHIFT                                                    0x1
+#define GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_FORCE_EN__SHIFT                                                     0x2
+#define GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_FORCE_DATA__SHIFT                                                   0x3
+#define GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_STATUS_ACCUM_EN__SHIFT                                              0x4
+#define GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_DATASTATUS_ACCUM_EN__SHIFT                                          0x5
+#define GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_BYPASS_MASK                                                         0x00000001L
+#define GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_ACCUM_SEL_MASK                                                      0x00000002L
+#define GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_FORCE_EN_MASK                                                       0x00000004L
+#define GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_FORCE_DATA_MASK                                                     0x00000008L
+#define GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_STATUS_ACCUM_EN_MASK                                                0x00000010L
+#define GDCSOC_ERR_RSP_CNTL__GDCSOC_RDRSP_DATASTATUS_ACCUM_EN_MASK                                            0x00000020L
+//GDCSOC_RAS_CENTRAL_STATUS
+#define GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_L2C_EgStall_det__SHIFT                                              0x0
+#define GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_L2C_ErrEvent_det__SHIFT                                             0x1
+#define GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_C2L_EgStall_det__SHIFT                                              0x2
+#define GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_C2L_ErrEvent_det__SHIFT                                             0x3
+#define GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_L2C_EgStall_det_MASK                                                0x00000001L
+#define GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_L2C_ErrEvent_det_MASK                                               0x00000002L
+#define GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_C2L_EgStall_det_MASK                                                0x00000004L
+#define GDCSOC_RAS_CENTRAL_STATUS__GDCSOC_C2L_ErrEvent_det_MASK                                               0x00000008L
+//GDCSOC_RAS_LEAF0_CTRL
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_ERR_EVENT_DET_EN__SHIFT                                  0x0
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_POISON_ERREVENT_EN__SHIFT                                0x1
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_POISON_STALL_EN__SHIFT                                   0x2
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_PARITY_ERREVENT_EN__SHIFT                                0x3
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_PARITY_STALL_EN__SHIFT                                   0x4
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT                           0x5
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_RCVERREVENT_STALL_EN__SHIFT                              0x6
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_ERR_EVENT_GEN_EN__SHIFT                                  0x8
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_EGRESS_STALL_GEN_EN__SHIFT                               0x9
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_ERR_EVENT_PROP_EN__SHIFT                                 0xa
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_EGRESS_STALL_PROP_EN__SHIFT                              0xb
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_PARITY_ERREVENT_LOG_MCA__SHIFT                           0x11
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_POISON_ERREVENT_LOG_MCA__SHIFT                           0x12
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_TIMEOUT_ERREVENT_LOG_MCA__SHIFT                          0x13
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_RCVERREVENT_ERREVENT_LOG_MCA__SHIFT                      0x14
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_UCP_EN__SHIFT                                            0x15
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_POISON_PROPAGATION_LOG_MCA__SHIFT                        0x16
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_ERR_EVENT_PARITY_CHECK_EN__SHIFT                         0x17
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_ERR_EVENT_DET_EN_MASK                                    0x00000001L
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_POISON_ERREVENT_EN_MASK                                  0x00000002L
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_POISON_STALL_EN_MASK                                     0x00000004L
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_PARITY_ERREVENT_EN_MASK                                  0x00000008L
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_PARITY_STALL_EN_MASK                                     0x00000010L
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_RCVERREVENT_ERREVENT_EN_MASK                             0x00000020L
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_RCVERREVENT_STALL_EN_MASK                                0x00000040L
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_ERR_EVENT_GEN_EN_MASK                                    0x00000100L
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_EGRESS_STALL_GEN_EN_MASK                                 0x00000200L
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_ERR_EVENT_PROP_EN_MASK                                   0x00000400L
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_EGRESS_STALL_PROP_EN_MASK                                0x00000800L
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_PARITY_ERREVENT_LOG_MCA_MASK                             0x00020000L
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_POISON_ERREVENT_LOG_MCA_MASK                             0x00040000L
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_TIMEOUT_ERREVENT_LOG_MCA_MASK                            0x00080000L
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_RCVERREVENT_ERREVENT_LOG_MCA_MASK                        0x00100000L
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_UCP_EN_MASK                                              0x00200000L
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_POISON_PROPAGATION_LOG_MCA_MASK                          0x00400000L
+#define GDCSOC_RAS_LEAF0_CTRL__GDCSOC_RAS_LEAF0_CTRL_ERR_EVENT_PARITY_CHECK_EN_MASK                           0x00800000L
+//GDCSOC_RAS_LEAF1_CTRL
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_ERR_EVENT_DET_EN__SHIFT                                  0x0
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_POISON_ERREVENT_EN__SHIFT                                0x1
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_POISON_STALL_EN__SHIFT                                   0x2
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_PARITY_ERREVENT_EN__SHIFT                                0x3
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_PARITY_STALL_EN__SHIFT                                   0x4
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT                           0x5
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_RCVERREVENT_STALL_EN__SHIFT                              0x6
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_ERR_EVENT_GEN_EN__SHIFT                                  0x8
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_EGRESS_STALL_GEN_EN__SHIFT                               0x9
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_ERR_EVENT_PROP_EN__SHIFT                                 0xa
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_EGRESS_STALL_PROP_EN__SHIFT                              0xb
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_PARITY_ERREVENT_LOG_MCA__SHIFT                           0x11
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_POISON_ERREVENT_LOG_MCA__SHIFT                           0x12
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_TIMEOUT_ERREVENT_LOG_MCA__SHIFT                          0x13
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_RCVERREVENT_ERREVENT_LOG_MCA__SHIFT                      0x14
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_UCP_EN__SHIFT                                            0x15
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_POISON_PROPAGATION_LOG_MCA__SHIFT                        0x16
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_ERR_EVENT_PARITY_CHECK_EN__SHIFT                         0x17
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_ERR_EVENT_DET_EN_MASK                                    0x00000001L
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_POISON_ERREVENT_EN_MASK                                  0x00000002L
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_POISON_STALL_EN_MASK                                     0x00000004L
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_PARITY_ERREVENT_EN_MASK                                  0x00000008L
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_PARITY_STALL_EN_MASK                                     0x00000010L
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_RCVERREVENT_ERREVENT_EN_MASK                             0x00000020L
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_RCVERREVENT_STALL_EN_MASK                                0x00000040L
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_ERR_EVENT_GEN_EN_MASK                                    0x00000100L
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_EGRESS_STALL_GEN_EN_MASK                                 0x00000200L
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_ERR_EVENT_PROP_EN_MASK                                   0x00000400L
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_EGRESS_STALL_PROP_EN_MASK                                0x00000800L
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_PARITY_ERREVENT_LOG_MCA_MASK                             0x00020000L
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_POISON_ERREVENT_LOG_MCA_MASK                             0x00040000L
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_TIMEOUT_ERREVENT_LOG_MCA_MASK                            0x00080000L
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_RCVERREVENT_ERREVENT_LOG_MCA_MASK                        0x00100000L
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_UCP_EN_MASK                                              0x00200000L
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_POISON_PROPAGATION_LOG_MCA_MASK                          0x00400000L
+#define GDCSOC_RAS_LEAF1_CTRL__GDCSOC_RAS_LEAF1_CTRL_ERR_EVENT_PARITY_CHECK_EN_MASK                           0x00800000L
+//GDCSOC_RAS_LEAF2_CTRL
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_DET_EN__SHIFT                                  0x0
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_POISON_ERREVENT_EN__SHIFT                                0x1
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_POISON_STALL_EN__SHIFT                                   0x2
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_PARITY_ERREVENT_EN__SHIFT                                0x3
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_PARITY_STALL_EN__SHIFT                                   0x4
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT                           0x5
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_RCVERREVENT_STALL_EN__SHIFT                              0x6
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_GEN_EN__SHIFT                                  0x8
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_EGRESS_STALL_GEN_EN__SHIFT                               0x9
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_PROP_EN__SHIFT                                 0xa
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_EGRESS_STALL_PROP_EN__SHIFT                              0xb
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_RAS_INTR_EN__SHIFT                             0x10
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_PARITY_ERREVENT_LOG_MCA__SHIFT                           0x11
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_POISON_ERREVENT_LOG_MCA__SHIFT                           0x12
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_TIMEOUT_ERREVENT_LOG_MCA__SHIFT                          0x13
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_RCVERREVENT_ERREVENT_LOG_MCA__SHIFT                      0x14
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_UCP_EN__SHIFT                                            0x15
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_POISON_PROPAGATION_LOG_MCA__SHIFT                        0x16
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_PARITY_CHECK_EN__SHIFT                         0x17
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_DET_EN_MASK                                    0x00000001L
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_POISON_ERREVENT_EN_MASK                                  0x00000002L
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_POISON_STALL_EN_MASK                                     0x00000004L
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_PARITY_ERREVENT_EN_MASK                                  0x00000008L
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_PARITY_STALL_EN_MASK                                     0x00000010L
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_RCVERREVENT_ERREVENT_EN_MASK                             0x00000020L
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_RCVERREVENT_STALL_EN_MASK                                0x00000040L
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_GEN_EN_MASK                                    0x00000100L
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_EGRESS_STALL_GEN_EN_MASK                                 0x00000200L
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_PROP_EN_MASK                                   0x00000400L
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_EGRESS_STALL_PROP_EN_MASK                                0x00000800L
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_RAS_INTR_EN_MASK                               0x00010000L
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_PARITY_ERREVENT_LOG_MCA_MASK                             0x00020000L
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_POISON_ERREVENT_LOG_MCA_MASK                             0x00040000L
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_TIMEOUT_ERREVENT_LOG_MCA_MASK                            0x00080000L
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_RCVERREVENT_ERREVENT_LOG_MCA_MASK                        0x00100000L
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_UCP_EN_MASK                                              0x00200000L
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_POISON_PROPAGATION_LOG_MCA_MASK                          0x00400000L
+#define GDCSOC_RAS_LEAF2_CTRL__GDCSOC_RAS_LEAF2_CTRL_ERR_EVENT_PARITY_CHECK_EN_MASK                           0x00800000L
+//GDCSOC_RAS_LEAF3_CTRL
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_ERR_EVENT_DET_EN__SHIFT                                  0x0
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_POISON_ERREVENT_EN__SHIFT                                0x1
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_POISON_STALL_EN__SHIFT                                   0x2
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_PARITY_ERREVENT_EN__SHIFT                                0x3
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_PARITY_STALL_EN__SHIFT                                   0x4
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT                           0x5
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_RCVERREVENT_STALL_EN__SHIFT                              0x6
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_ERR_EVENT_GEN_EN__SHIFT                                  0x8
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_EGRESS_STALL_GEN_EN__SHIFT                               0x9
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_ERR_EVENT_PROP_EN__SHIFT                                 0xa
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_EGRESS_STALL_PROP_EN__SHIFT                              0xb
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_PARITY_ERREVENT_LOG_MCA__SHIFT                           0x11
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_POISON_ERREVENT_LOG_MCA__SHIFT                           0x12
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_TIMEOUT_ERREVENT_LOG_MCA__SHIFT                          0x13
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_RCVERREVENT_ERREVENT_LOG_MCA__SHIFT                      0x14
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_UCP_EN__SHIFT                                            0x15
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_POISON_PROPAGATION_LOG_MCA__SHIFT                        0x16
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_ERR_EVENT_PARITY_CHECK_EN__SHIFT                         0x17
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_ERR_EVENT_DET_EN_MASK                                    0x00000001L
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_POISON_ERREVENT_EN_MASK                                  0x00000002L
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_POISON_STALL_EN_MASK                                     0x00000004L
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_PARITY_ERREVENT_EN_MASK                                  0x00000008L
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_PARITY_STALL_EN_MASK                                     0x00000010L
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_RCVERREVENT_ERREVENT_EN_MASK                             0x00000020L
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_RCVERREVENT_STALL_EN_MASK                                0x00000040L
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_ERR_EVENT_GEN_EN_MASK                                    0x00000100L
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_EGRESS_STALL_GEN_EN_MASK                                 0x00000200L
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_ERR_EVENT_PROP_EN_MASK                                   0x00000400L
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_EGRESS_STALL_PROP_EN_MASK                                0x00000800L
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_PARITY_ERREVENT_LOG_MCA_MASK                             0x00020000L
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_POISON_ERREVENT_LOG_MCA_MASK                             0x00040000L
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_TIMEOUT_ERREVENT_LOG_MCA_MASK                            0x00080000L
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_RCVERREVENT_ERREVENT_LOG_MCA_MASK                        0x00100000L
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_UCP_EN_MASK                                              0x00200000L
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_POISON_PROPAGATION_LOG_MCA_MASK                          0x00400000L
+#define GDCSOC_RAS_LEAF3_CTRL__GDCSOC_RAS_LEAF3_CTRL_ERR_EVENT_PARITY_CHECK_EN_MASK                           0x00800000L
+//GDCSOC_RAS_LEAF4_CTRL
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_ERR_EVENT_DET_EN__SHIFT                                  0x0
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_POISON_ERREVENT_EN__SHIFT                                0x1
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_POISON_STALL_EN__SHIFT                                   0x2
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_PARITY_ERREVENT_EN__SHIFT                                0x3
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_PARITY_STALL_EN__SHIFT                                   0x4
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT                           0x5
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_RCVERREVENT_STALL_EN__SHIFT                              0x6
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_ERR_EVENT_GEN_EN__SHIFT                                  0x8
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_EGRESS_STALL_GEN_EN__SHIFT                               0x9
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_ERR_EVENT_PROP_EN__SHIFT                                 0xa
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_EGRESS_STALL_PROP_EN__SHIFT                              0xb
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_PARITY_ERREVENT_LOG_MCA__SHIFT                           0x11
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_POISON_ERREVENT_LOG_MCA__SHIFT                           0x12
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_TIMEOUT_ERREVENT_LOG_MCA__SHIFT                          0x13
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_RCVERREVENT_ERREVENT_LOG_MCA__SHIFT                      0x14
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_UCP_EN__SHIFT                                            0x15
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_POISON_PROPAGATION_LOG_MCA__SHIFT                        0x16
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_ERR_EVENT_PARITY_CHECK_EN__SHIFT                         0x17
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_ERR_EVENT_DET_EN_MASK                                    0x00000001L
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_POISON_ERREVENT_EN_MASK                                  0x00000002L
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_POISON_STALL_EN_MASK                                     0x00000004L
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_PARITY_ERREVENT_EN_MASK                                  0x00000008L
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_PARITY_STALL_EN_MASK                                     0x00000010L
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_RCVERREVENT_ERREVENT_EN_MASK                             0x00000020L
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_RCVERREVENT_STALL_EN_MASK                                0x00000040L
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_ERR_EVENT_GEN_EN_MASK                                    0x00000100L
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_EGRESS_STALL_GEN_EN_MASK                                 0x00000200L
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_ERR_EVENT_PROP_EN_MASK                                   0x00000400L
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_EGRESS_STALL_PROP_EN_MASK                                0x00000800L
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_PARITY_ERREVENT_LOG_MCA_MASK                             0x00020000L
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_POISON_ERREVENT_LOG_MCA_MASK                             0x00040000L
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_TIMEOUT_ERREVENT_LOG_MCA_MASK                            0x00080000L
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_RCVERREVENT_ERREVENT_LOG_MCA_MASK                        0x00100000L
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_UCP_EN_MASK                                              0x00200000L
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_POISON_PROPAGATION_LOG_MCA_MASK                          0x00400000L
+#define GDCSOC_RAS_LEAF4_CTRL__GDCSOC_RAS_LEAF4_CTRL_ERR_EVENT_PARITY_CHECK_EN_MASK                           0x00800000L
+//GDCSOC_RAS_LEAF5_CTRL
+#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_ERR_EVENT_DET_EN__SHIFT                                  0x0
+#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_POISON_ERREVENT_EN__SHIFT                                0x1
+#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_POISON_STALL_EN__SHIFT                                   0x2
+#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_PARITY_ERREVENT_EN__SHIFT                                0x3
+#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_PARITY_STALL_EN__SHIFT                                   0x4
+#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT                           0x5
+#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_RCVERREVENT_STALL_EN__SHIFT                              0x6
+#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_ERR_EVENT_GEN_EN__SHIFT                                  0x8
+#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_EGRESS_STALL_GEN_EN__SHIFT                               0x9
+#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_ERR_EVENT_PROP_EN__SHIFT                                 0xa
+#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_EGRESS_STALL_PROP_EN__SHIFT                              0xb
+#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_PARITY_ERREVENT_LOG_MCA__SHIFT                           0x11
+#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_POISON_ERREVENT_LOG_MCA__SHIFT                           0x12
+#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_TIMEOUT_ERREVENT_LOG_MCA__SHIFT                          0x13
+#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_RCVERREVENT_ERREVENT_LOG_MCA__SHIFT                      0x14
+#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_UCP_EN__SHIFT                                            0x15
+#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_POISON_PROPAGATION_LOG_MCA__SHIFT                        0x16
+#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_ERR_EVENT_PARITY_CHECK_EN__SHIFT                         0x17
+#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_ERR_EVENT_DET_EN_MASK                                    0x00000001L
+#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_POISON_ERREVENT_EN_MASK                                  0x00000002L
+#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_POISON_STALL_EN_MASK                                     0x00000004L
+#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_PARITY_ERREVENT_EN_MASK                                  0x00000008L
+#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_PARITY_STALL_EN_MASK                                     0x00000010L
+#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_RCVERREVENT_ERREVENT_EN_MASK                             0x00000020L
+#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_RCVERREVENT_STALL_EN_MASK                                0x00000040L
+#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_ERR_EVENT_GEN_EN_MASK                                    0x00000100L
+#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_EGRESS_STALL_GEN_EN_MASK                                 0x00000200L
+#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_ERR_EVENT_PROP_EN_MASK                                   0x00000400L
+#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_EGRESS_STALL_PROP_EN_MASK                                0x00000800L
+#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_PARITY_ERREVENT_LOG_MCA_MASK                             0x00020000L
+#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_POISON_ERREVENT_LOG_MCA_MASK                             0x00040000L
+#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_TIMEOUT_ERREVENT_LOG_MCA_MASK                            0x00080000L
+#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_RCVERREVENT_ERREVENT_LOG_MCA_MASK                        0x00100000L
+#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_UCP_EN_MASK                                              0x00200000L
+#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_POISON_PROPAGATION_LOG_MCA_MASK                          0x00400000L
+#define GDCSOC_RAS_LEAF5_CTRL__GDCSOC_RAS_LEAF5_CTRL_ERR_EVENT_PARITY_CHECK_EN_MASK                           0x00800000L
+//GDCSOC_RAS_LEAF6_CTRL
+#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_ERR_EVENT_DET_EN__SHIFT                                  0x0
+#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_POISON_ERREVENT_EN__SHIFT                                0x1
+#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_POISON_STALL_EN__SHIFT                                   0x2
+#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_PARITY_ERREVENT_EN__SHIFT                                0x3
+#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_PARITY_STALL_EN__SHIFT                                   0x4
+#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT                           0x5
+#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_RCVERREVENT_STALL_EN__SHIFT                              0x6
+#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_ERR_EVENT_GEN_EN__SHIFT                                  0x8
+#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_EGRESS_STALL_GEN_EN__SHIFT                               0x9
+#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_ERR_EVENT_PROP_EN__SHIFT                                 0xa
+#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_EGRESS_STALL_PROP_EN__SHIFT                              0xb
+#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_PARITY_ERREVENT_LOG_MCA__SHIFT                           0x11
+#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_POISON_ERREVENT_LOG_MCA__SHIFT                           0x12
+#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_TIMEOUT_ERREVENT_LOG_MCA__SHIFT                          0x13
+#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_RCVERREVENT_ERREVENT_LOG_MCA__SHIFT                      0x14
+#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_UCP_EN__SHIFT                                            0x15
+#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_POISON_PROPAGATION_LOG_MCA__SHIFT                        0x16
+#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_ERR_EVENT_PARITY_CHECK_EN__SHIFT                         0x17
+#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_ERR_EVENT_DET_EN_MASK                                    0x00000001L
+#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_POISON_ERREVENT_EN_MASK                                  0x00000002L
+#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_POISON_STALL_EN_MASK                                     0x00000004L
+#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_PARITY_ERREVENT_EN_MASK                                  0x00000008L
+#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_PARITY_STALL_EN_MASK                                     0x00000010L
+#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_RCVERREVENT_ERREVENT_EN_MASK                             0x00000020L
+#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_RCVERREVENT_STALL_EN_MASK                                0x00000040L
+#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_ERR_EVENT_GEN_EN_MASK                                    0x00000100L
+#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_EGRESS_STALL_GEN_EN_MASK                                 0x00000200L
+#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_ERR_EVENT_PROP_EN_MASK                                   0x00000400L
+#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_EGRESS_STALL_PROP_EN_MASK                                0x00000800L
+#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_PARITY_ERREVENT_LOG_MCA_MASK                             0x00020000L
+#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_POISON_ERREVENT_LOG_MCA_MASK                             0x00040000L
+#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_TIMEOUT_ERREVENT_LOG_MCA_MASK                            0x00080000L
+#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_RCVERREVENT_ERREVENT_LOG_MCA_MASK                        0x00100000L
+#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_UCP_EN_MASK                                              0x00200000L
+#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_POISON_PROPAGATION_LOG_MCA_MASK                          0x00400000L
+#define GDCSOC_RAS_LEAF6_CTRL__GDCSOC_RAS_LEAF6_CTRL_ERR_EVENT_PARITY_CHECK_EN_MASK                           0x00800000L
+//GDCSOC_RAS_LEAF7_CTRL
+#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_ERR_EVENT_DET_EN__SHIFT                                  0x0
+#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_POISON_ERREVENT_EN__SHIFT                                0x1
+#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_POISON_STALL_EN__SHIFT                                   0x2
+#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_PARITY_ERREVENT_EN__SHIFT                                0x3
+#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_PARITY_STALL_EN__SHIFT                                   0x4
+#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT                           0x5
+#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_RCVERREVENT_STALL_EN__SHIFT                              0x6
+#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_ERR_EVENT_GEN_EN__SHIFT                                  0x8
+#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_EGRESS_STALL_GEN_EN__SHIFT                               0x9
+#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_ERR_EVENT_PROP_EN__SHIFT                                 0xa
+#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_EGRESS_STALL_PROP_EN__SHIFT                              0xb
+#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_PARITY_ERREVENT_LOG_MCA__SHIFT                           0x11
+#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_POISON_ERREVENT_LOG_MCA__SHIFT                           0x12
+#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_TIMEOUT_ERREVENT_LOG_MCA__SHIFT                          0x13
+#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_RCVERREVENT_ERREVENT_LOG_MCA__SHIFT                      0x14
+#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_UCP_EN__SHIFT                                            0x15
+#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_POISON_PROPAGATION_LOG_MCA__SHIFT                        0x16
+#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_ERR_EVENT_PARITY_CHECK_EN__SHIFT                         0x17
+#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_ERR_EVENT_DET_EN_MASK                                    0x00000001L
+#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_POISON_ERREVENT_EN_MASK                                  0x00000002L
+#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_POISON_STALL_EN_MASK                                     0x00000004L
+#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_PARITY_ERREVENT_EN_MASK                                  0x00000008L
+#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_PARITY_STALL_EN_MASK                                     0x00000010L
+#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_RCVERREVENT_ERREVENT_EN_MASK                             0x00000020L
+#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_RCVERREVENT_STALL_EN_MASK                                0x00000040L
+#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_ERR_EVENT_GEN_EN_MASK                                    0x00000100L
+#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_EGRESS_STALL_GEN_EN_MASK                                 0x00000200L
+#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_ERR_EVENT_PROP_EN_MASK                                   0x00000400L
+#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_EGRESS_STALL_PROP_EN_MASK                                0x00000800L
+#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_PARITY_ERREVENT_LOG_MCA_MASK                             0x00020000L
+#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_POISON_ERREVENT_LOG_MCA_MASK                             0x00040000L
+#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_TIMEOUT_ERREVENT_LOG_MCA_MASK                            0x00080000L
+#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_RCVERREVENT_ERREVENT_LOG_MCA_MASK                        0x00100000L
+#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_UCP_EN_MASK                                              0x00200000L
+#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_POISON_PROPAGATION_LOG_MCA_MASK                          0x00400000L
+#define GDCSOC_RAS_LEAF7_CTRL__GDCSOC_RAS_LEAF7_CTRL_ERR_EVENT_PARITY_CHECK_EN_MASK                           0x00800000L
+//GDCSOC_RAS_LEAF8_CTRL
+#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_ERR_EVENT_DET_EN__SHIFT                                  0x0
+#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_POISON_ERREVENT_EN__SHIFT                                0x1
+#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_POISON_STALL_EN__SHIFT                                   0x2
+#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_PARITY_ERREVENT_EN__SHIFT                                0x3
+#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_PARITY_STALL_EN__SHIFT                                   0x4
+#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT                           0x5
+#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_RCVERREVENT_STALL_EN__SHIFT                              0x6
+#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_ERR_EVENT_GEN_EN__SHIFT                                  0x8
+#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_EGRESS_STALL_GEN_EN__SHIFT                               0x9
+#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_ERR_EVENT_PROP_EN__SHIFT                                 0xa
+#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_EGRESS_STALL_PROP_EN__SHIFT                              0xb
+#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_PARITY_ERREVENT_LOG_MCA__SHIFT                           0x11
+#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_POISON_ERREVENT_LOG_MCA__SHIFT                           0x12
+#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_TIMEOUT_ERREVENT_LOG_MCA__SHIFT                          0x13
+#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_RCVERREVENT_ERREVENT_LOG_MCA__SHIFT                      0x14
+#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_UCP_EN__SHIFT                                            0x15
+#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_POISON_PROPAGATION_LOG_MCA__SHIFT                        0x16
+#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_ERR_EVENT_PARITY_CHECK_EN__SHIFT                         0x17
+#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_ERR_EVENT_DET_EN_MASK                                    0x00000001L
+#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_POISON_ERREVENT_EN_MASK                                  0x00000002L
+#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_POISON_STALL_EN_MASK                                     0x00000004L
+#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_PARITY_ERREVENT_EN_MASK                                  0x00000008L
+#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_PARITY_STALL_EN_MASK                                     0x00000010L
+#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_RCVERREVENT_ERREVENT_EN_MASK                             0x00000020L
+#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_RCVERREVENT_STALL_EN_MASK                                0x00000040L
+#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_ERR_EVENT_GEN_EN_MASK                                    0x00000100L
+#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_EGRESS_STALL_GEN_EN_MASK                                 0x00000200L
+#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_ERR_EVENT_PROP_EN_MASK                                   0x00000400L
+#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_EGRESS_STALL_PROP_EN_MASK                                0x00000800L
+#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_PARITY_ERREVENT_LOG_MCA_MASK                             0x00020000L
+#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_POISON_ERREVENT_LOG_MCA_MASK                             0x00040000L
+#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_TIMEOUT_ERREVENT_LOG_MCA_MASK                            0x00080000L
+#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_RCVERREVENT_ERREVENT_LOG_MCA_MASK                        0x00100000L
+#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_UCP_EN_MASK                                              0x00200000L
+#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_POISON_PROPAGATION_LOG_MCA_MASK                          0x00400000L
+#define GDCSOC_RAS_LEAF8_CTRL__GDCSOC_RAS_LEAF8_CTRL_ERR_EVENT_PARITY_CHECK_EN_MASK                           0x00800000L
+//GDCSOC_RAS_LEAF9_CTRL
+#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_ERR_EVENT_DET_EN__SHIFT                                  0x0
+#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_POISON_ERREVENT_EN__SHIFT                                0x1
+#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_POISON_STALL_EN__SHIFT                                   0x2
+#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_PARITY_ERREVENT_EN__SHIFT                                0x3
+#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_PARITY_STALL_EN__SHIFT                                   0x4
+#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT                           0x5
+#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_RCVERREVENT_STALL_EN__SHIFT                              0x6
+#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_ERR_EVENT_GEN_EN__SHIFT                                  0x8
+#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_EGRESS_STALL_GEN_EN__SHIFT                               0x9
+#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_ERR_EVENT_PROP_EN__SHIFT                                 0xa
+#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_EGRESS_STALL_PROP_EN__SHIFT                              0xb
+#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_PARITY_ERREVENT_LOG_MCA__SHIFT                           0x11
+#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_POISON_ERREVENT_LOG_MCA__SHIFT                           0x12
+#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_TIMEOUT_ERREVENT_LOG_MCA__SHIFT                          0x13
+#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_RCVERREVENT_ERREVENT_LOG_MCA__SHIFT                      0x14
+#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_UCP_EN__SHIFT                                            0x15
+#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_POISON_PROPAGATION_LOG_MCA__SHIFT                        0x16
+#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_ERR_EVENT_PARITY_CHECK_EN__SHIFT                         0x17
+#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_ERR_EVENT_DET_EN_MASK                                    0x00000001L
+#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_POISON_ERREVENT_EN_MASK                                  0x00000002L
+#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_POISON_STALL_EN_MASK                                     0x00000004L
+#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_PARITY_ERREVENT_EN_MASK                                  0x00000008L
+#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_PARITY_STALL_EN_MASK                                     0x00000010L
+#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_RCVERREVENT_ERREVENT_EN_MASK                             0x00000020L
+#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_RCVERREVENT_STALL_EN_MASK                                0x00000040L
+#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_ERR_EVENT_GEN_EN_MASK                                    0x00000100L
+#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_EGRESS_STALL_GEN_EN_MASK                                 0x00000200L
+#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_ERR_EVENT_PROP_EN_MASK                                   0x00000400L
+#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_EGRESS_STALL_PROP_EN_MASK                                0x00000800L
+#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_PARITY_ERREVENT_LOG_MCA_MASK                             0x00020000L
+#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_POISON_ERREVENT_LOG_MCA_MASK                             0x00040000L
+#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_TIMEOUT_ERREVENT_LOG_MCA_MASK                            0x00080000L
+#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_RCVERREVENT_ERREVENT_LOG_MCA_MASK                        0x00100000L
+#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_UCP_EN_MASK                                              0x00200000L
+#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_POISON_PROPAGATION_LOG_MCA_MASK                          0x00400000L
+#define GDCSOC_RAS_LEAF9_CTRL__GDCSOC_RAS_LEAF9_CTRL_ERR_EVENT_PARITY_CHECK_EN_MASK                           0x00800000L
+//GDCSOC_RAS_LEAF10_CTRL
+#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_ERR_EVENT_DET_EN__SHIFT                                0x0
+#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_POISON_ERREVENT_EN__SHIFT                              0x1
+#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_POISON_STALL_EN__SHIFT                                 0x2
+#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_PARITY_ERREVENT_EN__SHIFT                              0x3
+#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_PARITY_STALL_EN__SHIFT                                 0x4
+#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT                         0x5
+#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_RCVERREVENT_STALL_EN__SHIFT                            0x6
+#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_ERR_EVENT_GEN_EN__SHIFT                                0x8
+#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_EGRESS_STALL_GEN_EN__SHIFT                             0x9
+#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_ERR_EVENT_PROP_EN__SHIFT                               0xa
+#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_EGRESS_STALL_PROP_EN__SHIFT                            0xb
+#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_PARITY_ERREVENT_LOG_MCA__SHIFT                         0x11
+#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_POISON_ERREVENT_LOG_MCA__SHIFT                         0x12
+#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_TIMEOUT_ERREVENT_LOG_MCA__SHIFT                        0x13
+#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_RCVERREVENT_ERREVENT_LOG_MCA__SHIFT                    0x14
+#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_UCP_EN__SHIFT                                          0x15
+#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_POISON_PROPAGATION_LOG_MCA__SHIFT                      0x16
+#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_ERR_EVENT_PARITY_CHECK_EN__SHIFT                       0x17
+#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_ERR_EVENT_DET_EN_MASK                                  0x00000001L
+#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_POISON_ERREVENT_EN_MASK                                0x00000002L
+#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_POISON_STALL_EN_MASK                                   0x00000004L
+#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_PARITY_ERREVENT_EN_MASK                                0x00000008L
+#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_PARITY_STALL_EN_MASK                                   0x00000010L
+#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_RCVERREVENT_ERREVENT_EN_MASK                           0x00000020L
+#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_RCVERREVENT_STALL_EN_MASK                              0x00000040L
+#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_ERR_EVENT_GEN_EN_MASK                                  0x00000100L
+#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_EGRESS_STALL_GEN_EN_MASK                               0x00000200L
+#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_ERR_EVENT_PROP_EN_MASK                                 0x00000400L
+#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_EGRESS_STALL_PROP_EN_MASK                              0x00000800L
+#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_PARITY_ERREVENT_LOG_MCA_MASK                           0x00020000L
+#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_POISON_ERREVENT_LOG_MCA_MASK                           0x00040000L
+#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_TIMEOUT_ERREVENT_LOG_MCA_MASK                          0x00080000L
+#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_RCVERREVENT_ERREVENT_LOG_MCA_MASK                      0x00100000L
+#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_UCP_EN_MASK                                            0x00200000L
+#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_POISON_PROPAGATION_LOG_MCA_MASK                        0x00400000L
+#define GDCSOC_RAS_LEAF10_CTRL__GDCSOC_RAS_LEAF10_CTRL_ERR_EVENT_PARITY_CHECK_EN_MASK                         0x00800000L
+//GDCSOC_RAS_LEAF11_CTRL
+#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_ERR_EVENT_DET_EN__SHIFT                                0x0
+#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_POISON_ERREVENT_EN__SHIFT                              0x1
+#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_POISON_STALL_EN__SHIFT                                 0x2
+#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_PARITY_ERREVENT_EN__SHIFT                              0x3
+#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_PARITY_STALL_EN__SHIFT                                 0x4
+#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT                         0x5
+#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_RCVERREVENT_STALL_EN__SHIFT                            0x6
+#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_ERR_EVENT_GEN_EN__SHIFT                                0x8
+#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_EGRESS_STALL_GEN_EN__SHIFT                             0x9
+#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_ERR_EVENT_PROP_EN__SHIFT                               0xa
+#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_EGRESS_STALL_PROP_EN__SHIFT                            0xb
+#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_PARITY_ERREVENT_LOG_MCA__SHIFT                         0x11
+#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_POISON_ERREVENT_LOG_MCA__SHIFT                         0x12
+#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_TIMEOUT_ERREVENT_LOG_MCA__SHIFT                        0x13
+#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_RCVERREVENT_ERREVENT_LOG_MCA__SHIFT                    0x14
+#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_UCP_EN__SHIFT                                          0x15
+#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_POISON_PROPAGATION_LOG_MCA__SHIFT                      0x16
+#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_ERR_EVENT_PARITY_CHECK_EN__SHIFT                       0x17
+#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_ERR_EVENT_DET_EN_MASK                                  0x00000001L
+#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_POISON_ERREVENT_EN_MASK                                0x00000002L
+#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_POISON_STALL_EN_MASK                                   0x00000004L
+#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_PARITY_ERREVENT_EN_MASK                                0x00000008L
+#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_PARITY_STALL_EN_MASK                                   0x00000010L
+#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_RCVERREVENT_ERREVENT_EN_MASK                           0x00000020L
+#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_RCVERREVENT_STALL_EN_MASK                              0x00000040L
+#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_ERR_EVENT_GEN_EN_MASK                                  0x00000100L
+#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_EGRESS_STALL_GEN_EN_MASK                               0x00000200L
+#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_ERR_EVENT_PROP_EN_MASK                                 0x00000400L
+#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_EGRESS_STALL_PROP_EN_MASK                              0x00000800L
+#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_PARITY_ERREVENT_LOG_MCA_MASK                           0x00020000L
+#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_POISON_ERREVENT_LOG_MCA_MASK                           0x00040000L
+#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_TIMEOUT_ERREVENT_LOG_MCA_MASK                          0x00080000L
+#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_RCVERREVENT_ERREVENT_LOG_MCA_MASK                      0x00100000L
+#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_UCP_EN_MASK                                            0x00200000L
+#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_POISON_PROPAGATION_LOG_MCA_MASK                        0x00400000L
+#define GDCSOC_RAS_LEAF11_CTRL__GDCSOC_RAS_LEAF11_CTRL_ERR_EVENT_PARITY_CHECK_EN_MASK                         0x00800000L
+//GDCSOC_RAS_LEAF12_CTRL
+#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_ERR_EVENT_DET_EN__SHIFT                                0x0
+#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_POISON_ERREVENT_EN__SHIFT                              0x1
+#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_POISON_STALL_EN__SHIFT                                 0x2
+#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_PARITY_ERREVENT_EN__SHIFT                              0x3
+#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_PARITY_STALL_EN__SHIFT                                 0x4
+#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT                         0x5
+#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_RCVERREVENT_STALL_EN__SHIFT                            0x6
+#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_ERR_EVENT_GEN_EN__SHIFT                                0x8
+#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_EGRESS_STALL_GEN_EN__SHIFT                             0x9
+#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_ERR_EVENT_PROP_EN__SHIFT                               0xa
+#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_EGRESS_STALL_PROP_EN__SHIFT                            0xb
+#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_PARITY_ERREVENT_LOG_MCA__SHIFT                         0x11
+#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_POISON_ERREVENT_LOG_MCA__SHIFT                         0x12
+#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_TIMEOUT_ERREVENT_LOG_MCA__SHIFT                        0x13
+#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_RCVERREVENT_ERREVENT_LOG_MCA__SHIFT                    0x14
+#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_UCP_EN__SHIFT                                          0x15
+#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_POISON_PROPAGATION_LOG_MCA__SHIFT                      0x16
+#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_ERR_EVENT_PARITY_CHECK_EN__SHIFT                       0x17
+#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_ERR_EVENT_DET_EN_MASK                                  0x00000001L
+#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_POISON_ERREVENT_EN_MASK                                0x00000002L
+#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_POISON_STALL_EN_MASK                                   0x00000004L
+#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_PARITY_ERREVENT_EN_MASK                                0x00000008L
+#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_PARITY_STALL_EN_MASK                                   0x00000010L
+#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_RCVERREVENT_ERREVENT_EN_MASK                           0x00000020L
+#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_RCVERREVENT_STALL_EN_MASK                              0x00000040L
+#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_ERR_EVENT_GEN_EN_MASK                                  0x00000100L
+#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_EGRESS_STALL_GEN_EN_MASK                               0x00000200L
+#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_ERR_EVENT_PROP_EN_MASK                                 0x00000400L
+#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_EGRESS_STALL_PROP_EN_MASK                              0x00000800L
+#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_PARITY_ERREVENT_LOG_MCA_MASK                           0x00020000L
+#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_POISON_ERREVENT_LOG_MCA_MASK                           0x00040000L
+#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_TIMEOUT_ERREVENT_LOG_MCA_MASK                          0x00080000L
+#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_RCVERREVENT_ERREVENT_LOG_MCA_MASK                      0x00100000L
+#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_UCP_EN_MASK                                            0x00200000L
+#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_POISON_PROPAGATION_LOG_MCA_MASK                        0x00400000L
+#define GDCSOC_RAS_LEAF12_CTRL__GDCSOC_RAS_LEAF12_CTRL_ERR_EVENT_PARITY_CHECK_EN_MASK                         0x00800000L
+//GDCSOC_RAS_LEAF13_CTRL
+#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_ERR_EVENT_DET_EN__SHIFT                                0x0
+#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_POISON_ERREVENT_EN__SHIFT                              0x1
+#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_POISON_STALL_EN__SHIFT                                 0x2
+#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_PARITY_ERREVENT_EN__SHIFT                              0x3
+#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_PARITY_STALL_EN__SHIFT                                 0x4
+#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_RCVERREVENT_ERREVENT_EN__SHIFT                         0x5
+#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_RCVERREVENT_STALL_EN__SHIFT                            0x6
+#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_ERR_EVENT_GEN_EN__SHIFT                                0x8
+#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_EGRESS_STALL_GEN_EN__SHIFT                             0x9
+#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_ERR_EVENT_PROP_EN__SHIFT                               0xa
+#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_EGRESS_STALL_PROP_EN__SHIFT                            0xb
+#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_PARITY_ERREVENT_LOG_MCA__SHIFT                         0x11
+#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_POISON_ERREVENT_LOG_MCA__SHIFT                         0x12
+#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_TIMEOUT_ERREVENT_LOG_MCA__SHIFT                        0x13
+#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_RCVERREVENT_ERREVENT_LOG_MCA__SHIFT                    0x14
+#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_UCP_EN__SHIFT                                          0x15
+#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_POISON_PROPAGATION_LOG_MCA__SHIFT                      0x16
+#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_ERR_EVENT_PARITY_CHECK_EN__SHIFT                       0x17
+#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_ERR_EVENT_DET_EN_MASK                                  0x00000001L
+#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_POISON_ERREVENT_EN_MASK                                0x00000002L
+#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_POISON_STALL_EN_MASK                                   0x00000004L
+#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_PARITY_ERREVENT_EN_MASK                                0x00000008L
+#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_PARITY_STALL_EN_MASK                                   0x00000010L
+#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_RCVERREVENT_ERREVENT_EN_MASK                           0x00000020L
+#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_RCVERREVENT_STALL_EN_MASK                              0x00000040L
+#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_ERR_EVENT_GEN_EN_MASK                                  0x00000100L
+#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_EGRESS_STALL_GEN_EN_MASK                               0x00000200L
+#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_ERR_EVENT_PROP_EN_MASK                                 0x00000400L
+#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_EGRESS_STALL_PROP_EN_MASK                              0x00000800L
+#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_PARITY_ERREVENT_LOG_MCA_MASK                           0x00020000L
+#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_POISON_ERREVENT_LOG_MCA_MASK                           0x00040000L
+#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_TIMEOUT_ERREVENT_LOG_MCA_MASK                          0x00080000L
+#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_RCVERREVENT_ERREVENT_LOG_MCA_MASK                      0x00100000L
+#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_UCP_EN_MASK                                            0x00200000L
+#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_POISON_PROPAGATION_LOG_MCA_MASK                        0x00400000L
+#define GDCSOC_RAS_LEAF13_CTRL__GDCSOC_RAS_LEAF13_CTRL_ERR_EVENT_PARITY_CHECK_EN_MASK                         0x00800000L
+//GDCSOC_RAS_LEAF0_STATUS
+#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_ERR_EVENT_RECV__SHIFT                                0x0
+#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_POISON_ERR_DET__SHIFT                                0x1
+#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_PARITY_ERR_DET__SHIFT                                0x2
+#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_ERR_EVENT_GENN_STAT__SHIFT                           0x8
+#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT                      0x9
+#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_ERR_EVENT_PROP_STAT__SHIFT                           0xa
+#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT                      0xb
+#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_ERR_EVENT_RECV_MASK                                  0x00000001L
+#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_POISON_ERR_DET_MASK                                  0x00000002L
+#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_PARITY_ERR_DET_MASK                                  0x00000004L
+#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_ERR_EVENT_GENN_STAT_MASK                             0x00000100L
+#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_EGRESS_STALLED_GENN_STAT_MASK                        0x00000200L
+#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_ERR_EVENT_PROP_STAT_MASK                             0x00000400L
+#define GDCSOC_RAS_LEAF0_STATUS__GDCSOC_RAS_LEAF0_STATUS_EGRESS_STALLED_PROP_STAT_MASK                        0x00000800L
+//GDCSOC_RAS_LEAF1_STATUS
+#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_ERR_EVENT_RECV__SHIFT                                0x0
+#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_POISON_ERR_DET__SHIFT                                0x1
+#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_PARITY_ERR_DET__SHIFT                                0x2
+#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_ERR_EVENT_GENN_STAT__SHIFT                           0x8
+#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT                      0x9
+#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_ERR_EVENT_PROP_STAT__SHIFT                           0xa
+#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT                      0xb
+#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_ERR_EVENT_RECV_MASK                                  0x00000001L
+#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_POISON_ERR_DET_MASK                                  0x00000002L
+#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_PARITY_ERR_DET_MASK                                  0x00000004L
+#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_ERR_EVENT_GENN_STAT_MASK                             0x00000100L
+#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_EGRESS_STALLED_GENN_STAT_MASK                        0x00000200L
+#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_ERR_EVENT_PROP_STAT_MASK                             0x00000400L
+#define GDCSOC_RAS_LEAF1_STATUS__GDCSOC_RAS_LEAF1_STATUS_EGRESS_STALLED_PROP_STAT_MASK                        0x00000800L
+//GDCSOC_RAS_LEAF2_STATUS
+#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_ERR_EVENT_RECV__SHIFT                                0x0
+#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_POISON_ERR_DET__SHIFT                                0x1
+#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_PARITY_ERR_DET__SHIFT                                0x2
+#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_ERR_EVENT_GENN_STAT__SHIFT                           0x8
+#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT                      0x9
+#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_ERR_EVENT_PROP_STAT__SHIFT                           0xa
+#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT                      0xb
+#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_ERR_EVENT_RECV_MASK                                  0x00000001L
+#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_POISON_ERR_DET_MASK                                  0x00000002L
+#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_PARITY_ERR_DET_MASK                                  0x00000004L
+#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_ERR_EVENT_GENN_STAT_MASK                             0x00000100L
+#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_EGRESS_STALLED_GENN_STAT_MASK                        0x00000200L
+#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_ERR_EVENT_PROP_STAT_MASK                             0x00000400L
+#define GDCSOC_RAS_LEAF2_STATUS__GDCSOC_RAS_LEAF2_STATUS_EGRESS_STALLED_PROP_STAT_MASK                        0x00000800L
+//GDCSOC_RAS_LEAF3_STATUS
+#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_ERR_EVENT_RECV__SHIFT                                0x0
+#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_POISON_ERR_DET__SHIFT                                0x1
+#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_PARITY_ERR_DET__SHIFT                                0x2
+#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_ERR_EVENT_GENN_STAT__SHIFT                           0x8
+#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT                      0x9
+#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_ERR_EVENT_PROP_STAT__SHIFT                           0xa
+#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT                      0xb
+#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_ERR_EVENT_RECV_MASK                                  0x00000001L
+#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_POISON_ERR_DET_MASK                                  0x00000002L
+#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_PARITY_ERR_DET_MASK                                  0x00000004L
+#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_ERR_EVENT_GENN_STAT_MASK                             0x00000100L
+#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_EGRESS_STALLED_GENN_STAT_MASK                        0x00000200L
+#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_ERR_EVENT_PROP_STAT_MASK                             0x00000400L
+#define GDCSOC_RAS_LEAF3_STATUS__GDCSOC_RAS_LEAF3_STATUS_EGRESS_STALLED_PROP_STAT_MASK                        0x00000800L
+//GDCSOC_RAS_LEAF4_STATUS
+#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_ERR_EVENT_RECV__SHIFT                                0x0
+#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_POISON_ERR_DET__SHIFT                                0x1
+#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_PARITY_ERR_DET__SHIFT                                0x2
+#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_ERR_EVENT_GENN_STAT__SHIFT                           0x8
+#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT                      0x9
+#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_ERR_EVENT_PROP_STAT__SHIFT                           0xa
+#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT                      0xb
+#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_ERR_EVENT_RECV_MASK                                  0x00000001L
+#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_POISON_ERR_DET_MASK                                  0x00000002L
+#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_PARITY_ERR_DET_MASK                                  0x00000004L
+#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_ERR_EVENT_GENN_STAT_MASK                             0x00000100L
+#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_EGRESS_STALLED_GENN_STAT_MASK                        0x00000200L
+#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_ERR_EVENT_PROP_STAT_MASK                             0x00000400L
+#define GDCSOC_RAS_LEAF4_STATUS__GDCSOC_RAS_LEAF4_STATUS_EGRESS_STALLED_PROP_STAT_MASK                        0x00000800L
+//GDCSOC_RAS_LEAF5_STATUS
+#define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_ERR_EVENT_RECV__SHIFT                                0x0
+#define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_POISON_ERR_DET__SHIFT                                0x1
+#define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_PARITY_ERR_DET__SHIFT                                0x2
+#define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_ERR_EVENT_GENN_STAT__SHIFT                           0x8
+#define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT                      0x9
+#define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_ERR_EVENT_PROP_STAT__SHIFT                           0xa
+#define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT                      0xb
+#define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_ERR_EVENT_RECV_MASK                                  0x00000001L
+#define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_POISON_ERR_DET_MASK                                  0x00000002L
+#define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_PARITY_ERR_DET_MASK                                  0x00000004L
+#define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_ERR_EVENT_GENN_STAT_MASK                             0x00000100L
+#define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_EGRESS_STALLED_GENN_STAT_MASK                        0x00000200L
+#define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_ERR_EVENT_PROP_STAT_MASK                             0x00000400L
+#define GDCSOC_RAS_LEAF5_STATUS__GDCSOC_RAS_LEAF5_STATUS_EGRESS_STALLED_PROP_STAT_MASK                        0x00000800L
+//GDCSOC_RAS_LEAF6_STATUS
+#define GDCSOC_RAS_LEAF6_STATUS__GDCSOC_RAS_LEAF6_STATUS_ERR_EVENT_RECV__SHIFT                                0x0
+#define GDCSOC_RAS_LEAF6_STATUS__GDCSOC_RAS_LEAF6_STATUS_POISON_ERR_DET__SHIFT                                0x1
+#define GDCSOC_RAS_LEAF6_STATUS__GDCSOC_RAS_LEAF6_STATUS_PARITY_ERR_DET__SHIFT                                0x2
+#define GDCSOC_RAS_LEAF6_STATUS__GDCSOC_RAS_LEAF6_STATUS_ERR_EVENT_GENN_STAT__SHIFT                           0x8
+#define GDCSOC_RAS_LEAF6_STATUS__GDCSOC_RAS_LEAF6_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT                      0x9
+#define GDCSOC_RAS_LEAF6_STATUS__GDCSOC_RAS_LEAF6_STATUS_ERR_EVENT_PROP_STAT__SHIFT                           0xa
+#define GDCSOC_RAS_LEAF6_STATUS__GDCSOC_RAS_LEAF6_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT                      0xb
+#define GDCSOC_RAS_LEAF6_STATUS__GDCSOC_RAS_LEAF6_STATUS_ERR_EVENT_RECV_MASK                                  0x00000001L
+#define GDCSOC_RAS_LEAF6_STATUS__GDCSOC_RAS_LEAF6_STATUS_POISON_ERR_DET_MASK                                  0x00000002L
+#define GDCSOC_RAS_LEAF6_STATUS__GDCSOC_RAS_LEAF6_STATUS_PARITY_ERR_DET_MASK                                  0x00000004L
+#define GDCSOC_RAS_LEAF6_STATUS__GDCSOC_RAS_LEAF6_STATUS_ERR_EVENT_GENN_STAT_MASK                             0x00000100L
+#define GDCSOC_RAS_LEAF6_STATUS__GDCSOC_RAS_LEAF6_STATUS_EGRESS_STALLED_GENN_STAT_MASK                        0x00000200L
+#define GDCSOC_RAS_LEAF6_STATUS__GDCSOC_RAS_LEAF6_STATUS_ERR_EVENT_PROP_STAT_MASK                             0x00000400L
+#define GDCSOC_RAS_LEAF6_STATUS__GDCSOC_RAS_LEAF6_STATUS_EGRESS_STALLED_PROP_STAT_MASK                        0x00000800L
+//GDCSOC_RAS_LEAF7_STATUS
+#define GDCSOC_RAS_LEAF7_STATUS__GDCSOC_RAS_LEAF7_STATUS_ERR_EVENT_RECV__SHIFT                                0x0
+#define GDCSOC_RAS_LEAF7_STATUS__GDCSOC_RAS_LEAF7_STATUS_POISON_ERR_DET__SHIFT                                0x1
+#define GDCSOC_RAS_LEAF7_STATUS__GDCSOC_RAS_LEAF7_STATUS_PARITY_ERR_DET__SHIFT                                0x2
+#define GDCSOC_RAS_LEAF7_STATUS__GDCSOC_RAS_LEAF7_STATUS_ERR_EVENT_GENN_STAT__SHIFT                           0x8
+#define GDCSOC_RAS_LEAF7_STATUS__GDCSOC_RAS_LEAF7_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT                      0x9
+#define GDCSOC_RAS_LEAF7_STATUS__GDCSOC_RAS_LEAF7_STATUS_ERR_EVENT_PROP_STAT__SHIFT                           0xa
+#define GDCSOC_RAS_LEAF7_STATUS__GDCSOC_RAS_LEAF7_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT                      0xb
+#define GDCSOC_RAS_LEAF7_STATUS__GDCSOC_RAS_LEAF7_STATUS_ERR_EVENT_RECV_MASK                                  0x00000001L
+#define GDCSOC_RAS_LEAF7_STATUS__GDCSOC_RAS_LEAF7_STATUS_POISON_ERR_DET_MASK                                  0x00000002L
+#define GDCSOC_RAS_LEAF7_STATUS__GDCSOC_RAS_LEAF7_STATUS_PARITY_ERR_DET_MASK                                  0x00000004L
+#define GDCSOC_RAS_LEAF7_STATUS__GDCSOC_RAS_LEAF7_STATUS_ERR_EVENT_GENN_STAT_MASK                             0x00000100L
+#define GDCSOC_RAS_LEAF7_STATUS__GDCSOC_RAS_LEAF7_STATUS_EGRESS_STALLED_GENN_STAT_MASK                        0x00000200L
+#define GDCSOC_RAS_LEAF7_STATUS__GDCSOC_RAS_LEAF7_STATUS_ERR_EVENT_PROP_STAT_MASK                             0x00000400L
+#define GDCSOC_RAS_LEAF7_STATUS__GDCSOC_RAS_LEAF7_STATUS_EGRESS_STALLED_PROP_STAT_MASK                        0x00000800L
+//GDCSOC_RAS_LEAF8_STATUS
+#define GDCSOC_RAS_LEAF8_STATUS__GDCSOC_RAS_LEAF8_STATUS_ERR_EVENT_RECV__SHIFT                                0x0
+#define GDCSOC_RAS_LEAF8_STATUS__GDCSOC_RAS_LEAF8_STATUS_POISON_ERR_DET__SHIFT                                0x1
+#define GDCSOC_RAS_LEAF8_STATUS__GDCSOC_RAS_LEAF8_STATUS_PARITY_ERR_DET__SHIFT                                0x2
+#define GDCSOC_RAS_LEAF8_STATUS__GDCSOC_RAS_LEAF8_STATUS_ERR_EVENT_GENN_STAT__SHIFT                           0x8
+#define GDCSOC_RAS_LEAF8_STATUS__GDCSOC_RAS_LEAF8_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT                      0x9
+#define GDCSOC_RAS_LEAF8_STATUS__GDCSOC_RAS_LEAF8_STATUS_ERR_EVENT_PROP_STAT__SHIFT                           0xa
+#define GDCSOC_RAS_LEAF8_STATUS__GDCSOC_RAS_LEAF8_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT                      0xb
+#define GDCSOC_RAS_LEAF8_STATUS__GDCSOC_RAS_LEAF8_STATUS_ERR_EVENT_RECV_MASK                                  0x00000001L
+#define GDCSOC_RAS_LEAF8_STATUS__GDCSOC_RAS_LEAF8_STATUS_POISON_ERR_DET_MASK                                  0x00000002L
+#define GDCSOC_RAS_LEAF8_STATUS__GDCSOC_RAS_LEAF8_STATUS_PARITY_ERR_DET_MASK                                  0x00000004L
+#define GDCSOC_RAS_LEAF8_STATUS__GDCSOC_RAS_LEAF8_STATUS_ERR_EVENT_GENN_STAT_MASK                             0x00000100L
+#define GDCSOC_RAS_LEAF8_STATUS__GDCSOC_RAS_LEAF8_STATUS_EGRESS_STALLED_GENN_STAT_MASK                        0x00000200L
+#define GDCSOC_RAS_LEAF8_STATUS__GDCSOC_RAS_LEAF8_STATUS_ERR_EVENT_PROP_STAT_MASK                             0x00000400L
+#define GDCSOC_RAS_LEAF8_STATUS__GDCSOC_RAS_LEAF8_STATUS_EGRESS_STALLED_PROP_STAT_MASK                        0x00000800L
+//GDCSOC_RAS_LEAF9_STATUS
+#define GDCSOC_RAS_LEAF9_STATUS__GDCSOC_RAS_LEAF9_STATUS_ERR_EVENT_RECV__SHIFT                                0x0
+#define GDCSOC_RAS_LEAF9_STATUS__GDCSOC_RAS_LEAF9_STATUS_POISON_ERR_DET__SHIFT                                0x1
+#define GDCSOC_RAS_LEAF9_STATUS__GDCSOC_RAS_LEAF9_STATUS_PARITY_ERR_DET__SHIFT                                0x2
+#define GDCSOC_RAS_LEAF9_STATUS__GDCSOC_RAS_LEAF9_STATUS_ERR_EVENT_GENN_STAT__SHIFT                           0x8
+#define GDCSOC_RAS_LEAF9_STATUS__GDCSOC_RAS_LEAF9_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT                      0x9
+#define GDCSOC_RAS_LEAF9_STATUS__GDCSOC_RAS_LEAF9_STATUS_ERR_EVENT_PROP_STAT__SHIFT                           0xa
+#define GDCSOC_RAS_LEAF9_STATUS__GDCSOC_RAS_LEAF9_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT                      0xb
+#define GDCSOC_RAS_LEAF9_STATUS__GDCSOC_RAS_LEAF9_STATUS_ERR_EVENT_RECV_MASK                                  0x00000001L
+#define GDCSOC_RAS_LEAF9_STATUS__GDCSOC_RAS_LEAF9_STATUS_POISON_ERR_DET_MASK                                  0x00000002L
+#define GDCSOC_RAS_LEAF9_STATUS__GDCSOC_RAS_LEAF9_STATUS_PARITY_ERR_DET_MASK                                  0x00000004L
+#define GDCSOC_RAS_LEAF9_STATUS__GDCSOC_RAS_LEAF9_STATUS_ERR_EVENT_GENN_STAT_MASK                             0x00000100L
+#define GDCSOC_RAS_LEAF9_STATUS__GDCSOC_RAS_LEAF9_STATUS_EGRESS_STALLED_GENN_STAT_MASK                        0x00000200L
+#define GDCSOC_RAS_LEAF9_STATUS__GDCSOC_RAS_LEAF9_STATUS_ERR_EVENT_PROP_STAT_MASK                             0x00000400L
+#define GDCSOC_RAS_LEAF9_STATUS__GDCSOC_RAS_LEAF9_STATUS_EGRESS_STALLED_PROP_STAT_MASK                        0x00000800L
+//GDCSOC_RAS_LEAF10_STATUS
+#define GDCSOC_RAS_LEAF10_STATUS__GDCSOC_RAS_LEAF10_STATUS_ERR_EVENT_RECV__SHIFT                              0x0
+#define GDCSOC_RAS_LEAF10_STATUS__GDCSOC_RAS_LEAF10_STATUS_POISON_ERR_DET__SHIFT                              0x1
+#define GDCSOC_RAS_LEAF10_STATUS__GDCSOC_RAS_LEAF10_STATUS_PARITY_ERR_DET__SHIFT                              0x2
+#define GDCSOC_RAS_LEAF10_STATUS__GDCSOC_RAS_LEAF10_STATUS_ERR_EVENT_GENN_STAT__SHIFT                         0x8
+#define GDCSOC_RAS_LEAF10_STATUS__GDCSOC_RAS_LEAF10_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT                    0x9
+#define GDCSOC_RAS_LEAF10_STATUS__GDCSOC_RAS_LEAF10_STATUS_ERR_EVENT_PROP_STAT__SHIFT                         0xa
+#define GDCSOC_RAS_LEAF10_STATUS__GDCSOC_RAS_LEAF10_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT                    0xb
+#define GDCSOC_RAS_LEAF10_STATUS__GDCSOC_RAS_LEAF10_STATUS_ERR_EVENT_RECV_MASK                                0x00000001L
+#define GDCSOC_RAS_LEAF10_STATUS__GDCSOC_RAS_LEAF10_STATUS_POISON_ERR_DET_MASK                                0x00000002L
+#define GDCSOC_RAS_LEAF10_STATUS__GDCSOC_RAS_LEAF10_STATUS_PARITY_ERR_DET_MASK                                0x00000004L
+#define GDCSOC_RAS_LEAF10_STATUS__GDCSOC_RAS_LEAF10_STATUS_ERR_EVENT_GENN_STAT_MASK                           0x00000100L
+#define GDCSOC_RAS_LEAF10_STATUS__GDCSOC_RAS_LEAF10_STATUS_EGRESS_STALLED_GENN_STAT_MASK                      0x00000200L
+#define GDCSOC_RAS_LEAF10_STATUS__GDCSOC_RAS_LEAF10_STATUS_ERR_EVENT_PROP_STAT_MASK                           0x00000400L
+#define GDCSOC_RAS_LEAF10_STATUS__GDCSOC_RAS_LEAF10_STATUS_EGRESS_STALLED_PROP_STAT_MASK                      0x00000800L
+//GDCSOC_RAS_LEAF11_STATUS
+#define GDCSOC_RAS_LEAF11_STATUS__GDCSOC_RAS_LEAF11_STATUS_ERR_EVENT_RECV__SHIFT                              0x0
+#define GDCSOC_RAS_LEAF11_STATUS__GDCSOC_RAS_LEAF11_STATUS_POISON_ERR_DET__SHIFT                              0x1
+#define GDCSOC_RAS_LEAF11_STATUS__GDCSOC_RAS_LEAF11_STATUS_PARITY_ERR_DET__SHIFT                              0x2
+#define GDCSOC_RAS_LEAF11_STATUS__GDCSOC_RAS_LEAF11_STATUS_ERR_EVENT_GENN_STAT__SHIFT                         0x8
+#define GDCSOC_RAS_LEAF11_STATUS__GDCSOC_RAS_LEAF11_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT                    0x9
+#define GDCSOC_RAS_LEAF11_STATUS__GDCSOC_RAS_LEAF11_STATUS_ERR_EVENT_PROP_STAT__SHIFT                         0xa
+#define GDCSOC_RAS_LEAF11_STATUS__GDCSOC_RAS_LEAF11_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT                    0xb
+#define GDCSOC_RAS_LEAF11_STATUS__GDCSOC_RAS_LEAF11_STATUS_ERR_EVENT_RECV_MASK                                0x00000001L
+#define GDCSOC_RAS_LEAF11_STATUS__GDCSOC_RAS_LEAF11_STATUS_POISON_ERR_DET_MASK                                0x00000002L
+#define GDCSOC_RAS_LEAF11_STATUS__GDCSOC_RAS_LEAF11_STATUS_PARITY_ERR_DET_MASK                                0x00000004L
+#define GDCSOC_RAS_LEAF11_STATUS__GDCSOC_RAS_LEAF11_STATUS_ERR_EVENT_GENN_STAT_MASK                           0x00000100L
+#define GDCSOC_RAS_LEAF11_STATUS__GDCSOC_RAS_LEAF11_STATUS_EGRESS_STALLED_GENN_STAT_MASK                      0x00000200L
+#define GDCSOC_RAS_LEAF11_STATUS__GDCSOC_RAS_LEAF11_STATUS_ERR_EVENT_PROP_STAT_MASK                           0x00000400L
+#define GDCSOC_RAS_LEAF11_STATUS__GDCSOC_RAS_LEAF11_STATUS_EGRESS_STALLED_PROP_STAT_MASK                      0x00000800L
+//GDCSOC_RAS_LEAF12_STATUS
+#define GDCSOC_RAS_LEAF12_STATUS__GDCSOC_RAS_LEAF12_STATUS_ERR_EVENT_RECV__SHIFT                              0x0
+#define GDCSOC_RAS_LEAF12_STATUS__GDCSOC_RAS_LEAF12_STATUS_POISON_ERR_DET__SHIFT                              0x1
+#define GDCSOC_RAS_LEAF12_STATUS__GDCSOC_RAS_LEAF12_STATUS_PARITY_ERR_DET__SHIFT                              0x2
+#define GDCSOC_RAS_LEAF12_STATUS__GDCSOC_RAS_LEAF12_STATUS_ERR_EVENT_GENN_STAT__SHIFT                         0x8
+#define GDCSOC_RAS_LEAF12_STATUS__GDCSOC_RAS_LEAF12_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT                    0x9
+#define GDCSOC_RAS_LEAF12_STATUS__GDCSOC_RAS_LEAF12_STATUS_ERR_EVENT_PROP_STAT__SHIFT                         0xa
+#define GDCSOC_RAS_LEAF12_STATUS__GDCSOC_RAS_LEAF12_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT                    0xb
+#define GDCSOC_RAS_LEAF12_STATUS__GDCSOC_RAS_LEAF12_STATUS_ERR_EVENT_RECV_MASK                                0x00000001L
+#define GDCSOC_RAS_LEAF12_STATUS__GDCSOC_RAS_LEAF12_STATUS_POISON_ERR_DET_MASK                                0x00000002L
+#define GDCSOC_RAS_LEAF12_STATUS__GDCSOC_RAS_LEAF12_STATUS_PARITY_ERR_DET_MASK                                0x00000004L
+#define GDCSOC_RAS_LEAF12_STATUS__GDCSOC_RAS_LEAF12_STATUS_ERR_EVENT_GENN_STAT_MASK                           0x00000100L
+#define GDCSOC_RAS_LEAF12_STATUS__GDCSOC_RAS_LEAF12_STATUS_EGRESS_STALLED_GENN_STAT_MASK                      0x00000200L
+#define GDCSOC_RAS_LEAF12_STATUS__GDCSOC_RAS_LEAF12_STATUS_ERR_EVENT_PROP_STAT_MASK                           0x00000400L
+#define GDCSOC_RAS_LEAF12_STATUS__GDCSOC_RAS_LEAF12_STATUS_EGRESS_STALLED_PROP_STAT_MASK                      0x00000800L
+//GDCSOC_RAS_LEAF13_STATUS
+#define GDCSOC_RAS_LEAF13_STATUS__GDCSOC_RAS_LEAF13_STATUS_ERR_EVENT_RECV__SHIFT                              0x0
+#define GDCSOC_RAS_LEAF13_STATUS__GDCSOC_RAS_LEAF13_STATUS_POISON_ERR_DET__SHIFT                              0x1
+#define GDCSOC_RAS_LEAF13_STATUS__GDCSOC_RAS_LEAF13_STATUS_PARITY_ERR_DET__SHIFT                              0x2
+#define GDCSOC_RAS_LEAF13_STATUS__GDCSOC_RAS_LEAF13_STATUS_ERR_EVENT_GENN_STAT__SHIFT                         0x8
+#define GDCSOC_RAS_LEAF13_STATUS__GDCSOC_RAS_LEAF13_STATUS_EGRESS_STALLED_GENN_STAT__SHIFT                    0x9
+#define GDCSOC_RAS_LEAF13_STATUS__GDCSOC_RAS_LEAF13_STATUS_ERR_EVENT_PROP_STAT__SHIFT                         0xa
+#define GDCSOC_RAS_LEAF13_STATUS__GDCSOC_RAS_LEAF13_STATUS_EGRESS_STALLED_PROP_STAT__SHIFT                    0xb
+#define GDCSOC_RAS_LEAF13_STATUS__GDCSOC_RAS_LEAF13_STATUS_ERR_EVENT_RECV_MASK                                0x00000001L
+#define GDCSOC_RAS_LEAF13_STATUS__GDCSOC_RAS_LEAF13_STATUS_POISON_ERR_DET_MASK                                0x00000002L
+#define GDCSOC_RAS_LEAF13_STATUS__GDCSOC_RAS_LEAF13_STATUS_PARITY_ERR_DET_MASK                                0x00000004L
+#define GDCSOC_RAS_LEAF13_STATUS__GDCSOC_RAS_LEAF13_STATUS_ERR_EVENT_GENN_STAT_MASK                           0x00000100L
+#define GDCSOC_RAS_LEAF13_STATUS__GDCSOC_RAS_LEAF13_STATUS_EGRESS_STALLED_GENN_STAT_MASK                      0x00000200L
+#define GDCSOC_RAS_LEAF13_STATUS__GDCSOC_RAS_LEAF13_STATUS_ERR_EVENT_PROP_STAT_MASK                           0x00000400L
+#define GDCSOC_RAS_LEAF13_STATUS__GDCSOC_RAS_LEAF13_STATUS_EGRESS_STALLED_PROP_STAT_MASK                      0x00000800L
+
+
+// addressBlock: nbif0_nbif0_gdc_sec_GDCSEC_DEC
+//GDC_SEC_MCA_SMN_CTRL0
+#define GDC_SEC_MCA_SMN_CTRL0__MCA_INT_REQ_ADDR__SHIFT                                                        0x0
+#define GDC_SEC_MCA_SMN_CTRL0__MCA_INT_REQ_APER_ID__SHIFT                                                     0x14
+#define GDC_SEC_MCA_SMN_CTRL0__MCA_INT_REQ_ADDR_MASK                                                          0x000FFFFFL
+#define GDC_SEC_MCA_SMN_CTRL0__MCA_INT_REQ_APER_ID_MASK                                                       0xFFF00000L
+//GDC_SEC_MCA_SMN_CTRL1
+#define GDC_SEC_MCA_SMN_CTRL1__MCA_INT_REQ_MCM_ADDR__SHIFT                                                    0x0
+#define GDC_SEC_MCA_SMN_CTRL1__MCA_SMN_SEC_FLAG__SHIFT                                                        0x10
+#define GDC_SEC_MCA_SMN_CTRL1__MCA_INT_REQ_MCM_ADDR_MASK                                                      0x0000FFFFL
+#define GDC_SEC_MCA_SMN_CTRL1__MCA_SMN_SEC_FLAG_MASK                                                          0x000F0000L
+//XCD_DOORBELL_FENCE
+#define XCD_DOORBELL_FENCE__XCD_DOORBELL_FENCE_ONCE_TRIGGER_DIS__SHIFT                                        0x0
+#define XCD_DOORBELL_FENCE__XCD_DOORBELL_FENCE_INTR_ENABLE__SHIFT                                             0x1
+#define XCD_DOORBELL_FENCE__RMOTE_SDMA_SENT__SHIFT                                                            0x8
+#define XCD_DOORBELL_FENCE__SDMA_0_SENT__SHIFT                                                                0x9
+#define XCD_DOORBELL_FENCE__SDMA_1_SENT__SHIFT                                                                0xa
+#define XCD_DOORBELL_FENCE__SDMA_2_SENT__SHIFT                                                                0xb
+#define XCD_DOORBELL_FENCE__SDMA_3_SENT__SHIFT                                                                0xc
+#define XCD_DOORBELL_FENCE__SDMA_4_SENT__SHIFT                                                                0xd
+#define XCD_DOORBELL_FENCE__SDMA_5_SENT__SHIFT                                                                0xe
+#define XCD_DOORBELL_FENCE__SDMA_6_SENT__SHIFT                                                                0xf
+#define XCD_DOORBELL_FENCE__SDMA_7_SENT__SHIFT                                                                0x10
+#define XCD_DOORBELL_FENCE__RMOTE_CP_SENT__SHIFT                                                              0x11
+#define XCD_DOORBELL_FENCE__CP_0_SENT__SHIFT                                                                  0x12
+#define XCD_DOORBELL_FENCE__CP_1_SENT__SHIFT                                                                  0x13
+#define XCD_DOORBELL_FENCE__CP_2_SENT__SHIFT                                                                  0x14
+#define XCD_DOORBELL_FENCE__CP_3_SENT__SHIFT                                                                  0x15
+#define XCD_DOORBELL_FENCE__CP_4_SENT__SHIFT                                                                  0x16
+#define XCD_DOORBELL_FENCE__CP_5_SENT__SHIFT                                                                  0x17
+#define XCD_DOORBELL_FENCE__CP_6_SENT__SHIFT                                                                  0x18
+#define XCD_DOORBELL_FENCE__CP_7_SENT__SHIFT                                                                  0x19
+#define XCD_DOORBELL_FENCE__REMOTE_CLIENT_SENT__SHIFT                                                         0x1a
+#define XCD_DOORBELL_FENCE__REMOTE_CLIENT_CLR_PENDING__SHIFT                                                  0x1b
+#define XCD_DOORBELL_FENCE__SHUB_SLV_MODE__SHIFT                                                              0x1c
+#define XCD_DOORBELL_FENCE__XCD_DOORBELL_FENCE_ONCE_TRIGGER_DIS_MASK                                          0x00000001L
+#define XCD_DOORBELL_FENCE__XCD_DOORBELL_FENCE_INTR_ENABLE_MASK                                               0x00000002L
+#define XCD_DOORBELL_FENCE__RMOTE_SDMA_SENT_MASK                                                              0x00000100L
+#define XCD_DOORBELL_FENCE__SDMA_0_SENT_MASK                                                                  0x00000200L
+#define XCD_DOORBELL_FENCE__SDMA_1_SENT_MASK                                                                  0x00000400L
+#define XCD_DOORBELL_FENCE__SDMA_2_SENT_MASK                                                                  0x00000800L
+#define XCD_DOORBELL_FENCE__SDMA_3_SENT_MASK                                                                  0x00001000L
+#define XCD_DOORBELL_FENCE__SDMA_4_SENT_MASK                                                                  0x00002000L
+#define XCD_DOORBELL_FENCE__SDMA_5_SENT_MASK                                                                  0x00004000L
+#define XCD_DOORBELL_FENCE__SDMA_6_SENT_MASK                                                                  0x00008000L
+#define XCD_DOORBELL_FENCE__SDMA_7_SENT_MASK                                                                  0x00010000L
+#define XCD_DOORBELL_FENCE__RMOTE_CP_SENT_MASK                                                                0x00020000L
+#define XCD_DOORBELL_FENCE__CP_0_SENT_MASK                                                                    0x00040000L
+#define XCD_DOORBELL_FENCE__CP_1_SENT_MASK                                                                    0x00080000L
+#define XCD_DOORBELL_FENCE__CP_2_SENT_MASK                                                                    0x00100000L
+#define XCD_DOORBELL_FENCE__CP_3_SENT_MASK                                                                    0x00200000L
+#define XCD_DOORBELL_FENCE__CP_4_SENT_MASK                                                                    0x00400000L
+#define XCD_DOORBELL_FENCE__CP_5_SENT_MASK                                                                    0x00800000L
+#define XCD_DOORBELL_FENCE__CP_6_SENT_MASK                                                                    0x01000000L
+#define XCD_DOORBELL_FENCE__CP_7_SENT_MASK                                                                    0x02000000L
+#define XCD_DOORBELL_FENCE__REMOTE_CLIENT_SENT_MASK                                                           0x04000000L
+#define XCD_DOORBELL_FENCE__REMOTE_CLIENT_CLR_PENDING_MASK                                                    0x08000000L
+#define XCD_DOORBELL_FENCE__SHUB_SLV_MODE_MASK                                                                0x10000000L
+//SHUB_PWRBRK_DEGLITCH
+#define SHUB_PWRBRK_DEGLITCH__SHUB_PWRBRK_DEGLITCH_CYCLE__SHIFT                                               0x0
+#define SHUB_PWRBRK_DEGLITCH__SHUB_PWRBRK_DEGLITCH_BYPASS__SHIFT                                              0x8
+#define SHUB_PWRBRK_DEGLITCH__SHUB_PWRBRK_DEGLITCH_CYCLE_MASK                                                 0x000000FFL
+#define SHUB_PWRBRK_DEGLITCH__SHUB_PWRBRK_DEGLITCH_BYPASS_MASK                                                0x00000100L
+//SHUB_DIE_CTRL
+#define SHUB_DIE_CTRL__SHUB_MST_DIE__SHIFT                                                                    0x0
+#define SHUB_DIE_CTRL__SHUB_MST_DIE_MASK                                                                      0x00000001L
+//GDC_A2S_ROUTING_TABLE_SECLVL_TRUST_LEVEL
+#define GDC_A2S_ROUTING_TABLE_SECLVL_TRUST_LEVEL__GDC_A2S_ROUTING_TABLE_SECLVL_TRUST_LEVEL__SHIFT             0x0
+#define GDC_A2S_ROUTING_TABLE_SECLVL_TRUST_LEVEL__GDC_A2S_ROUTING_TABLE_SECLVL_TRUST_LEVEL_MASK               0x00000007L
+//XCD_DOORBELL_FENCE_1
+#define XCD_DOORBELL_FENCE_1__XCD_0_DOORBELL_FENCE__SHIFT                                                     0x0
+#define XCD_DOORBELL_FENCE_1__XCD_1_DOORBELL_FENCE__SHIFT                                                     0x1
+#define XCD_DOORBELL_FENCE_1__XCD_2_DOORBELL_FENCE__SHIFT                                                     0x2
+#define XCD_DOORBELL_FENCE_1__XCD_3_DOORBELL_FENCE__SHIFT                                                     0x3
+#define XCD_DOORBELL_FENCE_1__XCD_4_DOORBELL_FENCE__SHIFT                                                     0x4
+#define XCD_DOORBELL_FENCE_1__XCD_5_DOORBELL_FENCE__SHIFT                                                     0x5
+#define XCD_DOORBELL_FENCE_1__XCD_6_DOORBELL_FENCE__SHIFT                                                     0x6
+#define XCD_DOORBELL_FENCE_1__XCD_7_DOORBELL_FENCE__SHIFT                                                     0x7
+#define XCD_DOORBELL_FENCE_1__XCD_0_DOORBELL_DISABLE__SHIFT                                                   0x8
+#define XCD_DOORBELL_FENCE_1__XCD_1_DOORBELL_DISABLE__SHIFT                                                   0x9
+#define XCD_DOORBELL_FENCE_1__XCD_2_DOORBELL_DISABLE__SHIFT                                                   0xa
+#define XCD_DOORBELL_FENCE_1__XCD_3_DOORBELL_DISABLE__SHIFT                                                   0xb
+#define XCD_DOORBELL_FENCE_1__XCD_4_DOORBELL_DISABLE__SHIFT                                                   0xc
+#define XCD_DOORBELL_FENCE_1__XCD_5_DOORBELL_DISABLE__SHIFT                                                   0xd
+#define XCD_DOORBELL_FENCE_1__XCD_6_DOORBELL_DISABLE__SHIFT                                                   0xe
+#define XCD_DOORBELL_FENCE_1__XCD_7_DOORBELL_DISABLE__SHIFT                                                   0xf
+#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_CP_0_REG__SHIFT                                       0x10
+#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_CP_1_REG__SHIFT                                       0x11
+#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_CP_2_REG__SHIFT                                       0x12
+#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_CP_3_REG__SHIFT                                       0x13
+#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_CP_4_REG__SHIFT                                       0x14
+#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_CP_5_REG__SHIFT                                       0x15
+#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_CP_6_REG__SHIFT                                       0x16
+#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_CP_7_REG__SHIFT                                       0x17
+#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_SDMA_0_REG__SHIFT                                     0x18
+#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_SDMA_1_REG__SHIFT                                     0x19
+#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_SDMA_2_REG__SHIFT                                     0x1a
+#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_SDMA_3_REG__SHIFT                                     0x1b
+#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_SDMA_4_REG__SHIFT                                     0x1c
+#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_SDMA_5_REG__SHIFT                                     0x1d
+#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_SDMA_6_REG__SHIFT                                     0x1e
+#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_SDMA_7_REG__SHIFT                                     0x1f
+#define XCD_DOORBELL_FENCE_1__XCD_0_DOORBELL_FENCE_MASK                                                       0x00000001L
+#define XCD_DOORBELL_FENCE_1__XCD_1_DOORBELL_FENCE_MASK                                                       0x00000002L
+#define XCD_DOORBELL_FENCE_1__XCD_2_DOORBELL_FENCE_MASK                                                       0x00000004L
+#define XCD_DOORBELL_FENCE_1__XCD_3_DOORBELL_FENCE_MASK                                                       0x00000008L
+#define XCD_DOORBELL_FENCE_1__XCD_4_DOORBELL_FENCE_MASK                                                       0x00000010L
+#define XCD_DOORBELL_FENCE_1__XCD_5_DOORBELL_FENCE_MASK                                                       0x00000020L
+#define XCD_DOORBELL_FENCE_1__XCD_6_DOORBELL_FENCE_MASK                                                       0x00000040L
+#define XCD_DOORBELL_FENCE_1__XCD_7_DOORBELL_FENCE_MASK                                                       0x00000080L
+#define XCD_DOORBELL_FENCE_1__XCD_0_DOORBELL_DISABLE_MASK                                                     0x00000100L
+#define XCD_DOORBELL_FENCE_1__XCD_1_DOORBELL_DISABLE_MASK                                                     0x00000200L
+#define XCD_DOORBELL_FENCE_1__XCD_2_DOORBELL_DISABLE_MASK                                                     0x00000400L
+#define XCD_DOORBELL_FENCE_1__XCD_3_DOORBELL_DISABLE_MASK                                                     0x00000800L
+#define XCD_DOORBELL_FENCE_1__XCD_4_DOORBELL_DISABLE_MASK                                                     0x00001000L
+#define XCD_DOORBELL_FENCE_1__XCD_5_DOORBELL_DISABLE_MASK                                                     0x00002000L
+#define XCD_DOORBELL_FENCE_1__XCD_6_DOORBELL_DISABLE_MASK                                                     0x00004000L
+#define XCD_DOORBELL_FENCE_1__XCD_7_DOORBELL_DISABLE_MASK                                                     0x00008000L
+#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_CP_0_REG_MASK                                         0x00010000L
+#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_CP_1_REG_MASK                                         0x00020000L
+#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_CP_2_REG_MASK                                         0x00040000L
+#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_CP_3_REG_MASK                                         0x00080000L
+#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_CP_4_REG_MASK                                         0x00100000L
+#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_CP_5_REG_MASK                                         0x00200000L
+#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_CP_6_REG_MASK                                         0x00400000L
+#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_CP_7_REG_MASK                                         0x00800000L
+#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_SDMA_0_REG_MASK                                       0x01000000L
+#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_SDMA_1_REG_MASK                                       0x02000000L
+#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_SDMA_2_REG_MASK                                       0x04000000L
+#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_SDMA_3_REG_MASK                                       0x08000000L
+#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_SDMA_4_REG_MASK                                       0x10000000L
+#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_SDMA_5_REG_MASK                                       0x20000000L
+#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_SDMA_6_REG_MASK                                       0x40000000L
+#define XCD_DOORBELL_FENCE_1__REMOTE_CLIENT_CLR_PENDING_SDMA_7_REG_MASK                                       0x80000000L
+//NGDC_CNDI_DOORBELL_REQUSER_0
+#define NGDC_CNDI_DOORBELL_REQUSER_0__NGDC_CNDI_IH_ReqUser__SHIFT                                             0x0
+#define NGDC_CNDI_DOORBELL_REQUSER_0__NGDC_CNDI_IH_ReqUser_MASK                                               0x0000003FL
+//NGDC_CNDI_DOORBELL_REQUSER_1
+#define NGDC_CNDI_DOORBELL_REQUSER_1__NGDC_CNDI_VCN0_ReqUser__SHIFT                                           0x0
+#define NGDC_CNDI_DOORBELL_REQUSER_1__NGDC_CNDI_VCN1_ReqUser__SHIFT                                           0x8
+#define NGDC_CNDI_DOORBELL_REQUSER_1__NGDC_CNDI_VCN2_ReqUser__SHIFT                                           0x10
+#define NGDC_CNDI_DOORBELL_REQUSER_1__NGDC_CNDI_VCN3_ReqUser__SHIFT                                           0x18
+#define NGDC_CNDI_DOORBELL_REQUSER_1__NGDC_CNDI_VCN0_ReqUser_MASK                                             0x0000003FL
+#define NGDC_CNDI_DOORBELL_REQUSER_1__NGDC_CNDI_VCN1_ReqUser_MASK                                             0x00003F00L
+#define NGDC_CNDI_DOORBELL_REQUSER_1__NGDC_CNDI_VCN2_ReqUser_MASK                                             0x003F0000L
+#define NGDC_CNDI_DOORBELL_REQUSER_1__NGDC_CNDI_VCN3_ReqUser_MASK                                             0x3F000000L
+//NGDC_CNDI_DOORBELL_REQUSER_2
+#define NGDC_CNDI_DOORBELL_REQUSER_2__NGDC_CNDI_XCD0_SDMA_ReqUser__SHIFT                                      0x0
+#define NGDC_CNDI_DOORBELL_REQUSER_2__NGDC_CNDI_XCD1_SDMA_ReqUser__SHIFT                                      0x8
+#define NGDC_CNDI_DOORBELL_REQUSER_2__NGDC_CNDI_XCD2_SDMA_ReqUser__SHIFT                                      0x10
+#define NGDC_CNDI_DOORBELL_REQUSER_2__NGDC_CNDI_XCD3_SDMA_ReqUser__SHIFT                                      0x18
+#define NGDC_CNDI_DOORBELL_REQUSER_2__NGDC_CNDI_XCD0_SDMA_ReqUser_MASK                                        0x0000003FL
+#define NGDC_CNDI_DOORBELL_REQUSER_2__NGDC_CNDI_XCD1_SDMA_ReqUser_MASK                                        0x00003F00L
+#define NGDC_CNDI_DOORBELL_REQUSER_2__NGDC_CNDI_XCD2_SDMA_ReqUser_MASK                                        0x003F0000L
+#define NGDC_CNDI_DOORBELL_REQUSER_2__NGDC_CNDI_XCD3_SDMA_ReqUser_MASK                                        0x3F000000L
+//NGDC_CNDI_DOORBELL_REQUSER_3
+#define NGDC_CNDI_DOORBELL_REQUSER_3__NGDC_CNDI_XCD4_SDMA_ReqUser__SHIFT                                      0x0
+#define NGDC_CNDI_DOORBELL_REQUSER_3__NGDC_CNDI_XCD5_SDMA_ReqUser__SHIFT                                      0x8
+#define NGDC_CNDI_DOORBELL_REQUSER_3__NGDC_CNDI_XCD6_SDMA_ReqUser__SHIFT                                      0x10
+#define NGDC_CNDI_DOORBELL_REQUSER_3__NGDC_CNDI_XCD7_SDMA_ReqUser__SHIFT                                      0x18
+#define NGDC_CNDI_DOORBELL_REQUSER_3__NGDC_CNDI_XCD4_SDMA_ReqUser_MASK                                        0x0000003FL
+#define NGDC_CNDI_DOORBELL_REQUSER_3__NGDC_CNDI_XCD5_SDMA_ReqUser_MASK                                        0x00003F00L
+#define NGDC_CNDI_DOORBELL_REQUSER_3__NGDC_CNDI_XCD6_SDMA_ReqUser_MASK                                        0x003F0000L
+#define NGDC_CNDI_DOORBELL_REQUSER_3__NGDC_CNDI_XCD7_SDMA_ReqUser_MASK                                        0x3F000000L
+//NGDC_CNDI_DOORBELL_REQUSER_4
+#define NGDC_CNDI_DOORBELL_REQUSER_4__NGDC_CNDI_XCD0_CP_ReqUser__SHIFT                                        0x0
+#define NGDC_CNDI_DOORBELL_REQUSER_4__NGDC_CNDI_XCD1_CP_ReqUser__SHIFT                                        0x8
+#define NGDC_CNDI_DOORBELL_REQUSER_4__NGDC_CNDI_XCD2_CP_ReqUser__SHIFT                                        0x10
+#define NGDC_CNDI_DOORBELL_REQUSER_4__NGDC_CNDI_XCD3_CP_ReqUser__SHIFT                                        0x18
+#define NGDC_CNDI_DOORBELL_REQUSER_4__NGDC_CNDI_XCD0_CP_ReqUser_MASK                                          0x0000003FL
+#define NGDC_CNDI_DOORBELL_REQUSER_4__NGDC_CNDI_XCD1_CP_ReqUser_MASK                                          0x00003F00L
+#define NGDC_CNDI_DOORBELL_REQUSER_4__NGDC_CNDI_XCD2_CP_ReqUser_MASK                                          0x003F0000L
+#define NGDC_CNDI_DOORBELL_REQUSER_4__NGDC_CNDI_XCD3_CP_ReqUser_MASK                                          0x3F000000L
+//NGDC_CNDI_DOORBELL_REQUSER_5
+#define NGDC_CNDI_DOORBELL_REQUSER_5__NGDC_CNDI_XCD4_CP_ReqUser__SHIFT                                        0x0
+#define NGDC_CNDI_DOORBELL_REQUSER_5__NGDC_CNDI_XCD5_CP_ReqUser__SHIFT                                        0x8
+#define NGDC_CNDI_DOORBELL_REQUSER_5__NGDC_CNDI_XCD6_CP_ReqUser__SHIFT                                        0x10
+#define NGDC_CNDI_DOORBELL_REQUSER_5__NGDC_CNDI_XCD7_CP_ReqUser__SHIFT                                        0x18
+#define NGDC_CNDI_DOORBELL_REQUSER_5__NGDC_CNDI_XCD4_CP_ReqUser_MASK                                          0x0000003FL
+#define NGDC_CNDI_DOORBELL_REQUSER_5__NGDC_CNDI_XCD5_CP_ReqUser_MASK                                          0x00003F00L
+#define NGDC_CNDI_DOORBELL_REQUSER_5__NGDC_CNDI_XCD6_CP_ReqUser_MASK                                          0x003F0000L
+#define NGDC_CNDI_DOORBELL_REQUSER_5__NGDC_CNDI_XCD7_CP_ReqUser_MASK                                          0x3F000000L
+//NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_0
+#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_0__NGDC_CNDI_IH_REQADDR_32_33BIT__SHIFT                           0x0
+#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_0__NGDC_CNDI_VCN0_REQADDR_32_33BIT__SHIFT                         0x2
+#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_0__NGDC_CNDI_VCN1_REQADDR_32_33BIT__SHIFT                         0x4
+#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_0__NGDC_CNDI_VCN2_REQADDR_32_33BIT__SHIFT                         0x6
+#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_0__NGDC_CNDI_VCN3_REQADDR_32_33BIT__SHIFT                         0x8
+#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_0__NGDC_CNDI_XCD0_SDMA_REQADDR_32_33BIT__SHIFT                    0xa
+#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_0__NGDC_CNDI_XCD1_SDMA_REQADDR_32_33BIT__SHIFT                    0xc
+#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_0__NGDC_CNDI_XCD2_SDMA_REQADDR_32_33BIT__SHIFT                    0xe
+#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_0__NGDC_CNDI_XCD3_SDMA_REQADDR_32_33BIT__SHIFT                    0x10
+#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_0__NGDC_CNDI_XCD4_SDMA_REQADDR_32_33BIT__SHIFT                    0x12
+#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_0__NGDC_CNDI_XCD5_SDMA_REQADDR_32_33BIT__SHIFT                    0x14
+#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_0__NGDC_CNDI_XCD6_SDMA_REQADDR_32_33BIT__SHIFT                    0x16
+#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_0__NGDC_CNDI_XCD7_SDMA_REQADDR_32_33BIT__SHIFT                    0x18
+#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_0__NGDC_CNDI_IH_REQADDR_32_33BIT_MASK                             0x00000003L
+#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_0__NGDC_CNDI_VCN0_REQADDR_32_33BIT_MASK                           0x0000000CL
+#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_0__NGDC_CNDI_VCN1_REQADDR_32_33BIT_MASK                           0x00000030L
+#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_0__NGDC_CNDI_VCN2_REQADDR_32_33BIT_MASK                           0x000000C0L
+#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_0__NGDC_CNDI_VCN3_REQADDR_32_33BIT_MASK                           0x00000300L
+#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_0__NGDC_CNDI_XCD0_SDMA_REQADDR_32_33BIT_MASK                      0x00000C00L
+#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_0__NGDC_CNDI_XCD1_SDMA_REQADDR_32_33BIT_MASK                      0x00003000L
+#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_0__NGDC_CNDI_XCD2_SDMA_REQADDR_32_33BIT_MASK                      0x0000C000L
+#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_0__NGDC_CNDI_XCD3_SDMA_REQADDR_32_33BIT_MASK                      0x00030000L
+#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_0__NGDC_CNDI_XCD4_SDMA_REQADDR_32_33BIT_MASK                      0x000C0000L
+#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_0__NGDC_CNDI_XCD5_SDMA_REQADDR_32_33BIT_MASK                      0x00300000L
+#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_0__NGDC_CNDI_XCD6_SDMA_REQADDR_32_33BIT_MASK                      0x00C00000L
+#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_0__NGDC_CNDI_XCD7_SDMA_REQADDR_32_33BIT_MASK                      0x03000000L
+//NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_1
+#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_1__NGDC_CNDI_XCD0_CP_REQADDR_32_33BIT__SHIFT                      0x0
+#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_1__NGDC_CNDI_XCD1_CP_REQADDR_32_33BIT__SHIFT                      0x2
+#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_1__NGDC_CNDI_XCD2_CP_REQADDR_32_33BIT__SHIFT                      0x4
+#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_1__NGDC_CNDI_XCD3_CP_REQADDR_32_33BIT__SHIFT                      0x6
+#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_1__NGDC_CNDI_XCD4_CP_REQADDR_32_33BIT__SHIFT                      0x8
+#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_1__NGDC_CNDI_XCD5_CP_REQADDR_32_33BIT__SHIFT                      0xa
+#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_1__NGDC_CNDI_XCD6_CP_REQADDR_32_33BIT__SHIFT                      0xc
+#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_1__NGDC_CNDI_XCD7_CP_REQADDR_32_33BIT__SHIFT                      0xe
+#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_1__NGDC_CNDI_XCD0_CP_REQADDR_32_33BIT_MASK                        0x00000003L
+#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_1__NGDC_CNDI_XCD1_CP_REQADDR_32_33BIT_MASK                        0x0000000CL
+#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_1__NGDC_CNDI_XCD2_CP_REQADDR_32_33BIT_MASK                        0x00000030L
+#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_1__NGDC_CNDI_XCD3_CP_REQADDR_32_33BIT_MASK                        0x000000C0L
+#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_1__NGDC_CNDI_XCD4_CP_REQADDR_32_33BIT_MASK                        0x00000300L
+#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_1__NGDC_CNDI_XCD5_CP_REQADDR_32_33BIT_MASK                        0x00000C00L
+#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_1__NGDC_CNDI_XCD6_CP_REQADDR_32_33BIT_MASK                        0x00003000L
+#define NGDC_CNDI_DOORBELL_REQADDR_32_33BIT_1__NGDC_CNDI_XCD7_CP_REQADDR_32_33BIT_MASK                        0x0000C000L
+
+
+// addressBlock: nbif0_nbif0_gdc_rst_GDCRST_DEC
+//SHUB_PF_FLR_RST
+#define SHUB_PF_FLR_RST__DEV0_PF0_FLR_RST__SHIFT                                                              0x0
+#define SHUB_PF_FLR_RST__DEV0_PF1_FLR_RST__SHIFT                                                              0x1
+#define SHUB_PF_FLR_RST__DEV0_PF0_FLR_RST_MASK                                                                0x00000001L
+#define SHUB_PF_FLR_RST__DEV0_PF1_FLR_RST_MASK                                                                0x00000002L
+//SHUB_GFX_DRV_VPU_RST
+#define SHUB_GFX_DRV_VPU_RST__GFX_DRV_MODE1_RST__SHIFT                                                        0x0
+#define SHUB_GFX_DRV_VPU_RST__GFX_DRV_MODE1_RST_MASK                                                          0x00000001L
+//SHUB_LINK_RESET
+#define SHUB_LINK_RESET__LINK_P0_RESET__SHIFT                                                                 0x0
+#define SHUB_LINK_RESET__LINK_P1_RESET__SHIFT                                                                 0x1
+#define SHUB_LINK_RESET__LINK_P2_RESET__SHIFT                                                                 0x2
+#define SHUB_LINK_RESET__LINK_P3_RESET__SHIFT                                                                 0x3
+#define SHUB_LINK_RESET__LINK_P0_RESET_MASK                                                                   0x00000001L
+#define SHUB_LINK_RESET__LINK_P1_RESET_MASK                                                                   0x00000002L
+#define SHUB_LINK_RESET__LINK_P2_RESET_MASK                                                                   0x00000004L
+#define SHUB_LINK_RESET__LINK_P3_RESET_MASK                                                                   0x00000008L
+//SHUB_HST_NIC400_SW_CTRL_RESET
+#define SHUB_HST_NIC400_SW_CTRL_RESET__HST_NIC400_SW_CTRL_RESET__SHIFT                                        0x0
+#define SHUB_HST_NIC400_SW_CTRL_RESET__HST_NIC400_SW_CTRL_RESET_MASK                                          0x00000001L
+//SHUB_DEV0_PF0_VF_FLR_RST
+#define SHUB_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF0_FLR_RST__SHIFT                                                 0x0
+#define SHUB_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF1_FLR_RST__SHIFT                                                 0x1
+#define SHUB_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF2_FLR_RST__SHIFT                                                 0x2
+#define SHUB_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF3_FLR_RST__SHIFT                                                 0x3
+#define SHUB_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF4_FLR_RST__SHIFT                                                 0x4
+#define SHUB_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF5_FLR_RST__SHIFT                                                 0x5
+#define SHUB_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF6_FLR_RST__SHIFT                                                 0x6
+#define SHUB_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF7_FLR_RST__SHIFT                                                 0x7
+#define SHUB_DEV0_PF0_VF_FLR_RST__DEV0_PF0_SOFTPF_FLR_RST__SHIFT                                              0x1f
+#define SHUB_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF0_FLR_RST_MASK                                                   0x00000001L
+#define SHUB_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF1_FLR_RST_MASK                                                   0x00000002L
+#define SHUB_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF2_FLR_RST_MASK                                                   0x00000004L
+#define SHUB_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF3_FLR_RST_MASK                                                   0x00000008L
+#define SHUB_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF4_FLR_RST_MASK                                                   0x00000010L
+#define SHUB_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF5_FLR_RST_MASK                                                   0x00000020L
+#define SHUB_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF6_FLR_RST_MASK                                                   0x00000040L
+#define SHUB_DEV0_PF0_VF_FLR_RST__DEV0_PF0_VF7_FLR_RST_MASK                                                   0x00000080L
+#define SHUB_DEV0_PF0_VF_FLR_RST__DEV0_PF0_SOFTPF_FLR_RST_MASK                                                0x80000000L
+//SHUB_DEV0_PF1_VF_FLR_RST
+#define SHUB_DEV0_PF1_VF_FLR_RST__DEV0_PF1_VF0_FLR_RST__SHIFT                                                 0x0
+#define SHUB_DEV0_PF1_VF_FLR_RST__DEV0_PF1_VF0_FLR_RST_MASK                                                   0x00000001L
+//SHUB_HARD_RST_CTRL
+#define SHUB_HARD_RST_CTRL__COR_RESET_EN__SHIFT                                                               0x0
+#define SHUB_HARD_RST_CTRL__REG_RESET_EN__SHIFT                                                               0x1
+#define SHUB_HARD_RST_CTRL__STY_RESET_EN__SHIFT                                                               0x2
+#define SHUB_HARD_RST_CTRL__NIC400_RESET_EN__SHIFT                                                            0x3
+#define SHUB_HARD_RST_CTRL__SDP_PORT_RESET_EN__SHIFT                                                          0x4
+#define SHUB_HARD_RST_CTRL__SION_AON_RESET_EN__SHIFT                                                          0x5
+#define SHUB_HARD_RST_CTRL__COR_RESET_EN_MASK                                                                 0x00000001L
+#define SHUB_HARD_RST_CTRL__REG_RESET_EN_MASK                                                                 0x00000002L
+#define SHUB_HARD_RST_CTRL__STY_RESET_EN_MASK                                                                 0x00000004L
+#define SHUB_HARD_RST_CTRL__NIC400_RESET_EN_MASK                                                              0x00000008L
+#define SHUB_HARD_RST_CTRL__SDP_PORT_RESET_EN_MASK                                                            0x00000010L
+#define SHUB_HARD_RST_CTRL__SION_AON_RESET_EN_MASK                                                            0x00000020L
+//SHUB_SOFT_RST_CTRL
+#define SHUB_SOFT_RST_CTRL__COR_RESET_EN__SHIFT                                                               0x0
+#define SHUB_SOFT_RST_CTRL__REG_RESET_EN__SHIFT                                                               0x1
+#define SHUB_SOFT_RST_CTRL__STY_RESET_EN__SHIFT                                                               0x2
+#define SHUB_SOFT_RST_CTRL__NIC400_RESET_EN__SHIFT                                                            0x3
+#define SHUB_SOFT_RST_CTRL__SDP_PORT_RESET_EN__SHIFT                                                          0x4
+#define SHUB_SOFT_RST_CTRL__SION_AON_RESET_EN__SHIFT                                                          0x5
+#define SHUB_SOFT_RST_CTRL__COR_RESET_EN_MASK                                                                 0x00000001L
+#define SHUB_SOFT_RST_CTRL__REG_RESET_EN_MASK                                                                 0x00000002L
+#define SHUB_SOFT_RST_CTRL__STY_RESET_EN_MASK                                                                 0x00000004L
+#define SHUB_SOFT_RST_CTRL__NIC400_RESET_EN_MASK                                                              0x00000008L
+#define SHUB_SOFT_RST_CTRL__SDP_PORT_RESET_EN_MASK                                                            0x00000010L
+#define SHUB_SOFT_RST_CTRL__SION_AON_RESET_EN_MASK                                                            0x00000020L
+//SHUB_SDP_PORT_RST
+#define SHUB_SDP_PORT_RST__A2S_SDP_PORT_RST__SHIFT                                                            0x0
+#define SHUB_SDP_PORT_RST__NBIFSION_BIF_SDP_PORT_RST__SHIFT                                                   0x1
+#define SHUB_SDP_PORT_RST__ATHUB_HST_SDP_PORT_RST__SHIFT                                                      0x2
+#define SHUB_SDP_PORT_RST__ATHUB_DMA_SDP_PORT_RST__SHIFT                                                      0x3
+#define SHUB_SDP_PORT_RST__ATDMA_NBIFSOIN_SDP_PORT_RST__SHIFT                                                 0x4
+#define SHUB_SDP_PORT_RST__INT_NBIFSION_SDP_PORT_RST__SHIFT                                                   0x5
+#define SHUB_SDP_PORT_RST__MP4_SDP_SDP_PORT_RST__SHIFT                                                        0x6
+#define SHUB_SDP_PORT_RST__GDC_HST_SDP_PORT_RST__SHIFT                                                        0x7
+#define SHUB_SDP_PORT_RST__NTB_HST_SDP_PORT_RST__SHIFT                                                        0x8
+#define SHUB_SDP_PORT_RST__NTB_DMA_SDP_PORT_RST__SHIFT                                                        0x9
+#define SHUB_SDP_PORT_RST__DACCFE_NBIF_DMA_SDP_PORT_RST__SHIFT                                                0xa
+#define SHUB_SDP_PORT_RST__DACCBE_NBIF_DMA_SDP_PORT_RST__SHIFT                                                0xb
+#define SHUB_SDP_PORT_RST__DACCFE_HST_SDP_PORT_RST__SHIFT                                                     0xc
+#define SHUB_SDP_PORT_RST__SHUB_CNDI_HST_SDP_PORT_RST__SHIFT                                                  0xd
+#define SHUB_SDP_PORT_RST__HST_ATHUB_HST_SION_SDP_PORT_RST__SHIFT                                             0xe
+#define SHUB_SDP_PORT_RST__SION_AON_RST__SHIFT                                                                0x18
+#define SHUB_SDP_PORT_RST__A2S_SDP_PORT_RST_MASK                                                              0x00000001L
+#define SHUB_SDP_PORT_RST__NBIFSION_BIF_SDP_PORT_RST_MASK                                                     0x00000002L
+#define SHUB_SDP_PORT_RST__ATHUB_HST_SDP_PORT_RST_MASK                                                        0x00000004L
+#define SHUB_SDP_PORT_RST__ATHUB_DMA_SDP_PORT_RST_MASK                                                        0x00000008L
+#define SHUB_SDP_PORT_RST__ATDMA_NBIFSOIN_SDP_PORT_RST_MASK                                                   0x00000010L
+#define SHUB_SDP_PORT_RST__INT_NBIFSION_SDP_PORT_RST_MASK                                                     0x00000020L
+#define SHUB_SDP_PORT_RST__MP4_SDP_SDP_PORT_RST_MASK                                                          0x00000040L
+#define SHUB_SDP_PORT_RST__GDC_HST_SDP_PORT_RST_MASK                                                          0x00000080L
+#define SHUB_SDP_PORT_RST__NTB_HST_SDP_PORT_RST_MASK                                                          0x00000100L
+#define SHUB_SDP_PORT_RST__NTB_DMA_SDP_PORT_RST_MASK                                                          0x00000200L
+#define SHUB_SDP_PORT_RST__DACCFE_NBIF_DMA_SDP_PORT_RST_MASK                                                  0x00000400L
+#define SHUB_SDP_PORT_RST__DACCBE_NBIF_DMA_SDP_PORT_RST_MASK                                                  0x00000800L
+#define SHUB_SDP_PORT_RST__DACCFE_HST_SDP_PORT_RST_MASK                                                       0x00001000L
+#define SHUB_SDP_PORT_RST__SHUB_CNDI_HST_SDP_PORT_RST_MASK                                                    0x00002000L
+#define SHUB_SDP_PORT_RST__HST_ATHUB_HST_SION_SDP_PORT_RST_MASK                                               0x00004000L
+#define SHUB_SDP_PORT_RST__SION_AON_RST_MASK                                                                  0x01000000L
+//SHUB_RST_MISC_TRL
+
+
+// addressBlock: nbif0_nbif0_gdc_s2a_GDCS2A_DEC
+//GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_ENABLE__SHIFT                                  0x0
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_AWID__SHIFT                                    0x1
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_FENCE_ENABLE__SHIFT                            0x6
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_RANGE_OFFSET__SHIFT                            0x7
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_RANGE_SIZE__SHIFT                              0x11
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_64BIT_SUPPORT_DIS__SHIFT                       0x19
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_NEED_DEDUCT_RANGE_OFFSET__SHIFT                0x1a
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_DROP_EN__SHIFT                                 0x1b
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_AWADDR_31_28_VALUE__SHIFT                      0x1c
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_ENABLE_MASK                                    0x00000001L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_AWID_MASK                                      0x0000003EL
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_FENCE_ENABLE_MASK                              0x00000040L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_RANGE_OFFSET_MASK                              0x0001FF80L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_RANGE_SIZE_MASK                                0x01FE0000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_64BIT_SUPPORT_DIS_MASK                         0x02000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_NEED_DEDUCT_RANGE_OFFSET_MASK                  0x04000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_DROP_EN_MASK                                   0x08000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL__S2A_DOORBELL_PORT0_AWADDR_31_28_VALUE_MASK                        0xF0000000L
+//GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL1
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL1__S2A_DOORBELL_PORT0_TARGET_PORT_TYPE__SHIFT                       0x0
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL1__S2A_DOORBELL_PORT0_TARGET_DIEID__SHIFT                           0x2
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL1__S2A_DOORBELL_PORT0_TARGET_PORT_ID__SHIFT                         0x4
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL1__S2A_DOORBELL_PORT0_OVERRIDE_POISON_DATA__SHIFT                   0x6
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL1__S2A_DOORBELL_PORT0_4K_PAGE_DECODE_DISABLE__SHIFT                 0x7
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL1__S2A_DOORBELL_PORT0_TARGET_PORT_TYPE_MASK                         0x00000003L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL1__S2A_DOORBELL_PORT0_TARGET_DIEID_MASK                             0x0000000CL
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL1__S2A_DOORBELL_PORT0_TARGET_PORT_ID_MASK                           0x00000030L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL1__S2A_DOORBELL_PORT0_OVERRIDE_POISON_DATA_MASK                     0x00000040L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_0_CTRL1__S2A_DOORBELL_PORT0_4K_PAGE_DECODE_DISABLE_MASK                   0x00000080L
+//GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_ENABLE__SHIFT                                  0x0
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_AWID__SHIFT                                    0x1
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_FENCE_ENABLE__SHIFT                            0x6
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_RANGE_OFFSET__SHIFT                            0x7
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_RANGE_SIZE__SHIFT                              0x11
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_64BIT_SUPPORT_DIS__SHIFT                       0x19
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_NEED_DEDUCT_RANGE_OFFSET__SHIFT                0x1a
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_DROP_EN__SHIFT                                 0x1b
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE__SHIFT                      0x1c
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_ENABLE_MASK                                    0x00000001L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_AWID_MASK                                      0x0000003EL
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_FENCE_ENABLE_MASK                              0x00000040L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_RANGE_OFFSET_MASK                              0x0001FF80L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_RANGE_SIZE_MASK                                0x01FE0000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_64BIT_SUPPORT_DIS_MASK                         0x02000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_NEED_DEDUCT_RANGE_OFFSET_MASK                  0x04000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_DROP_EN_MASK                                   0x08000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL__S2A_DOORBELL_PORT1_AWADDR_31_28_VALUE_MASK                        0xF0000000L
+//GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL1
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL1__S2A_DOORBELL_PORT1_TARGET_PORT_TYPE__SHIFT                       0x0
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL1__S2A_DOORBELL_PORT1_TARGET_DIEID__SHIFT                           0x2
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL1__S2A_DOORBELL_PORT1_TARGET_PORT_ID__SHIFT                         0x4
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL1__S2A_DOORBELL_PORT1_OVERRIDE_POISON_DATA__SHIFT                   0x6
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL1__S2A_DOORBELL_PORT1_4K_PAGE_DECODE_DISABLE__SHIFT                 0x7
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL1__S2A_DOORBELL_PORT1_TARGET_PORT_TYPE_MASK                         0x00000003L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL1__S2A_DOORBELL_PORT1_TARGET_DIEID_MASK                             0x0000000CL
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL1__S2A_DOORBELL_PORT1_TARGET_PORT_ID_MASK                           0x00000030L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL1__S2A_DOORBELL_PORT1_OVERRIDE_POISON_DATA_MASK                     0x00000040L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_1_CTRL1__S2A_DOORBELL_PORT1_4K_PAGE_DECODE_DISABLE_MASK                   0x00000080L
+//GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_ENABLE__SHIFT                                  0x0
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_AWID__SHIFT                                    0x1
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_FENCE_ENABLE__SHIFT                            0x6
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_RANGE_OFFSET__SHIFT                            0x7
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_RANGE_SIZE__SHIFT                              0x11
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_64BIT_SUPPORT_DIS__SHIFT                       0x19
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_NEED_DEDUCT_RANGE_OFFSET__SHIFT                0x1a
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_DROP_EN__SHIFT                                 0x1b
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_AWADDR_31_28_VALUE__SHIFT                      0x1c
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_ENABLE_MASK                                    0x00000001L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_AWID_MASK                                      0x0000003EL
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_FENCE_ENABLE_MASK                              0x00000040L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_RANGE_OFFSET_MASK                              0x0001FF80L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_RANGE_SIZE_MASK                                0x01FE0000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_64BIT_SUPPORT_DIS_MASK                         0x02000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_NEED_DEDUCT_RANGE_OFFSET_MASK                  0x04000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_DROP_EN_MASK                                   0x08000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL__S2A_DOORBELL_PORT2_AWADDR_31_28_VALUE_MASK                        0xF0000000L
+//GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL1
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL1__S2A_DOORBELL_PORT2_TARGET_PORT_TYPE__SHIFT                       0x0
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL1__S2A_DOORBELL_PORT2_TARGET_DIEID__SHIFT                           0x2
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL1__S2A_DOORBELL_PORT2_TARGET_PORT_ID__SHIFT                         0x4
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL1__S2A_DOORBELL_PORT2_OVERRIDE_POISON_DATA__SHIFT                   0x6
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL1__S2A_DOORBELL_PORT2_4K_PAGE_DECODE_DISABLE__SHIFT                 0x7
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL1__S2A_DOORBELL_PORT2_TARGET_PORT_TYPE_MASK                         0x00000003L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL1__S2A_DOORBELL_PORT2_TARGET_DIEID_MASK                             0x0000000CL
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL1__S2A_DOORBELL_PORT2_TARGET_PORT_ID_MASK                           0x00000030L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL1__S2A_DOORBELL_PORT2_OVERRIDE_POISON_DATA_MASK                     0x00000040L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_2_CTRL1__S2A_DOORBELL_PORT2_4K_PAGE_DECODE_DISABLE_MASK                   0x00000080L
+//GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_ENABLE__SHIFT                                  0x0
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_AWID__SHIFT                                    0x1
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_FENCE_ENABLE__SHIFT                            0x6
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_RANGE_OFFSET__SHIFT                            0x7
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_RANGE_SIZE__SHIFT                              0x11
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_64BIT_SUPPORT_DIS__SHIFT                       0x19
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_NEED_DEDUCT_RANGE_OFFSET__SHIFT                0x1a
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_DROP_EN__SHIFT                                 0x1b
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_AWADDR_31_28_VALUE__SHIFT                      0x1c
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_ENABLE_MASK                                    0x00000001L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_AWID_MASK                                      0x0000003EL
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_FENCE_ENABLE_MASK                              0x00000040L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_RANGE_OFFSET_MASK                              0x0001FF80L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_RANGE_SIZE_MASK                                0x01FE0000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_64BIT_SUPPORT_DIS_MASK                         0x02000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_NEED_DEDUCT_RANGE_OFFSET_MASK                  0x04000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_DROP_EN_MASK                                   0x08000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL__S2A_DOORBELL_PORT3_AWADDR_31_28_VALUE_MASK                        0xF0000000L
+//GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL1
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL1__S2A_DOORBELL_PORT3_TARGET_PORT_TYPE__SHIFT                       0x0
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL1__S2A_DOORBELL_PORT3_TARGET_DIEID__SHIFT                           0x2
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL1__S2A_DOORBELL_PORT3_TARGET_PORT_ID__SHIFT                         0x4
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL1__S2A_DOORBELL_PORT3_OVERRIDE_POISON_DATA__SHIFT                   0x6
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL1__S2A_DOORBELL_PORT3_4K_PAGE_DECODE_DISABLE__SHIFT                 0x7
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL1__S2A_DOORBELL_PORT3_TARGET_PORT_TYPE_MASK                         0x00000003L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL1__S2A_DOORBELL_PORT3_TARGET_DIEID_MASK                             0x0000000CL
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL1__S2A_DOORBELL_PORT3_TARGET_PORT_ID_MASK                           0x00000030L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL1__S2A_DOORBELL_PORT3_OVERRIDE_POISON_DATA_MASK                     0x00000040L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_3_CTRL1__S2A_DOORBELL_PORT3_4K_PAGE_DECODE_DISABLE_MASK                   0x00000080L
+//GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_ENABLE__SHIFT                                  0x0
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_AWID__SHIFT                                    0x1
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_FENCE_ENABLE__SHIFT                            0x6
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_RANGE_OFFSET__SHIFT                            0x7
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_RANGE_SIZE__SHIFT                              0x11
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_64BIT_SUPPORT_DIS__SHIFT                       0x19
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_NEED_DEDUCT_RANGE_OFFSET__SHIFT                0x1a
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_DROP_EN__SHIFT                                 0x1b
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_AWADDR_31_28_VALUE__SHIFT                      0x1c
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_ENABLE_MASK                                    0x00000001L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_AWID_MASK                                      0x0000003EL
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_FENCE_ENABLE_MASK                              0x00000040L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_RANGE_OFFSET_MASK                              0x0001FF80L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_RANGE_SIZE_MASK                                0x01FE0000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_64BIT_SUPPORT_DIS_MASK                         0x02000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_NEED_DEDUCT_RANGE_OFFSET_MASK                  0x04000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_DROP_EN_MASK                                   0x08000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL__S2A_DOORBELL_PORT4_AWADDR_31_28_VALUE_MASK                        0xF0000000L
+//GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL1
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL1__S2A_DOORBELL_PORT4_TARGET_PORT_TYPE__SHIFT                       0x0
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL1__S2A_DOORBELL_PORT4_TARGET_DIEID__SHIFT                           0x2
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL1__S2A_DOORBELL_PORT4_TARGET_PORT_ID__SHIFT                         0x4
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL1__S2A_DOORBELL_PORT4_OVERRIDE_POISON_DATA__SHIFT                   0x6
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL1__S2A_DOORBELL_PORT4_4K_PAGE_DECODE_DISABLE__SHIFT                 0x7
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL1__S2A_DOORBELL_PORT4_TARGET_PORT_TYPE_MASK                         0x00000003L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL1__S2A_DOORBELL_PORT4_TARGET_DIEID_MASK                             0x0000000CL
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL1__S2A_DOORBELL_PORT4_TARGET_PORT_ID_MASK                           0x00000030L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL1__S2A_DOORBELL_PORT4_OVERRIDE_POISON_DATA_MASK                     0x00000040L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_4_CTRL1__S2A_DOORBELL_PORT4_4K_PAGE_DECODE_DISABLE_MASK                   0x00000080L
+//GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_ENABLE__SHIFT                                  0x0
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_AWID__SHIFT                                    0x1
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_FENCE_ENABLE__SHIFT                            0x6
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_RANGE_OFFSET__SHIFT                            0x7
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_RANGE_SIZE__SHIFT                              0x11
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_64BIT_SUPPORT_DIS__SHIFT                       0x19
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_NEED_DEDUCT_RANGE_OFFSET__SHIFT                0x1a
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_DROP_EN__SHIFT                                 0x1b
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_AWADDR_31_28_VALUE__SHIFT                      0x1c
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_ENABLE_MASK                                    0x00000001L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_AWID_MASK                                      0x0000003EL
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_FENCE_ENABLE_MASK                              0x00000040L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_RANGE_OFFSET_MASK                              0x0001FF80L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_RANGE_SIZE_MASK                                0x01FE0000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_64BIT_SUPPORT_DIS_MASK                         0x02000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_NEED_DEDUCT_RANGE_OFFSET_MASK                  0x04000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_DROP_EN_MASK                                   0x08000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL__S2A_DOORBELL_PORT5_AWADDR_31_28_VALUE_MASK                        0xF0000000L
+//GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL1
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL1__S2A_DOORBELL_PORT5_TARGET_PORT_TYPE__SHIFT                       0x0
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL1__S2A_DOORBELL_PORT5_TARGET_DIEID__SHIFT                           0x2
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL1__S2A_DOORBELL_PORT5_TARGET_PORT_ID__SHIFT                         0x4
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL1__S2A_DOORBELL_PORT5_OVERRIDE_POISON_DATA__SHIFT                   0x6
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL1__S2A_DOORBELL_PORT5_4K_PAGE_DECODE_DISABLE__SHIFT                 0x7
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL1__S2A_DOORBELL_PORT5_TARGET_PORT_TYPE_MASK                         0x00000003L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL1__S2A_DOORBELL_PORT5_TARGET_DIEID_MASK                             0x0000000CL
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL1__S2A_DOORBELL_PORT5_TARGET_PORT_ID_MASK                           0x00000030L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL1__S2A_DOORBELL_PORT5_OVERRIDE_POISON_DATA_MASK                     0x00000040L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_5_CTRL1__S2A_DOORBELL_PORT5_4K_PAGE_DECODE_DISABLE_MASK                   0x00000080L
+//GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_ENABLE__SHIFT                                  0x0
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_AWID__SHIFT                                    0x1
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_FENCE_ENABLE__SHIFT                            0x6
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_RANGE_OFFSET__SHIFT                            0x7
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_RANGE_SIZE__SHIFT                              0x11
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_64BIT_SUPPORT_DIS__SHIFT                       0x19
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_NEED_DEDUCT_RANGE_OFFSET__SHIFT                0x1a
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_DROP_EN__SHIFT                                 0x1b
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_AWADDR_31_28_VALUE__SHIFT                      0x1c
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_ENABLE_MASK                                    0x00000001L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_AWID_MASK                                      0x0000003EL
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_FENCE_ENABLE_MASK                              0x00000040L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_RANGE_OFFSET_MASK                              0x0001FF80L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_RANGE_SIZE_MASK                                0x01FE0000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_64BIT_SUPPORT_DIS_MASK                         0x02000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_NEED_DEDUCT_RANGE_OFFSET_MASK                  0x04000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_DROP_EN_MASK                                   0x08000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL__S2A_DOORBELL_PORT6_AWADDR_31_28_VALUE_MASK                        0xF0000000L
+//GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL1
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL1__S2A_DOORBELL_PORT6_TARGET_PORT_TYPE__SHIFT                       0x0
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL1__S2A_DOORBELL_PORT6_TARGET_DIEID__SHIFT                           0x2
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL1__S2A_DOORBELL_PORT6_TARGET_PORT_ID__SHIFT                         0x4
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL1__S2A_DOORBELL_PORT6_OVERRIDE_POISON_DATA__SHIFT                   0x6
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL1__S2A_DOORBELL_PORT6_4K_PAGE_DECODE_DISABLE__SHIFT                 0x7
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL1__S2A_DOORBELL_PORT6_TARGET_PORT_TYPE_MASK                         0x00000003L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL1__S2A_DOORBELL_PORT6_TARGET_DIEID_MASK                             0x0000000CL
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL1__S2A_DOORBELL_PORT6_TARGET_PORT_ID_MASK                           0x00000030L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL1__S2A_DOORBELL_PORT6_OVERRIDE_POISON_DATA_MASK                     0x00000040L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_6_CTRL1__S2A_DOORBELL_PORT6_4K_PAGE_DECODE_DISABLE_MASK                   0x00000080L
+//GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_ENABLE__SHIFT                                  0x0
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_AWID__SHIFT                                    0x1
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_FENCE_ENABLE__SHIFT                            0x6
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_RANGE_OFFSET__SHIFT                            0x7
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_RANGE_SIZE__SHIFT                              0x11
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_64BIT_SUPPORT_DIS__SHIFT                       0x19
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_NEED_DEDUCT_RANGE_OFFSET__SHIFT                0x1a
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_DROP_EN__SHIFT                                 0x1b
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_AWADDR_31_28_VALUE__SHIFT                      0x1c
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_ENABLE_MASK                                    0x00000001L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_AWID_MASK                                      0x0000003EL
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_FENCE_ENABLE_MASK                              0x00000040L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_RANGE_OFFSET_MASK                              0x0001FF80L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_RANGE_SIZE_MASK                                0x01FE0000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_64BIT_SUPPORT_DIS_MASK                         0x02000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_NEED_DEDUCT_RANGE_OFFSET_MASK                  0x04000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_DROP_EN_MASK                                   0x08000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL__S2A_DOORBELL_PORT7_AWADDR_31_28_VALUE_MASK                        0xF0000000L
+//GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL1
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL1__S2A_DOORBELL_PORT7_TARGET_PORT_TYPE__SHIFT                       0x0
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL1__S2A_DOORBELL_PORT7_TARGET_DIEID__SHIFT                           0x2
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL1__S2A_DOORBELL_PORT7_TARGET_PORT_ID__SHIFT                         0x4
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL1__S2A_DOORBELL_PORT7_OVERRIDE_POISON_DATA__SHIFT                   0x6
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL1__S2A_DOORBELL_PORT7_4K_PAGE_DECODE_DISABLE__SHIFT                 0x7
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL1__S2A_DOORBELL_PORT7_TARGET_PORT_TYPE_MASK                         0x00000003L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL1__S2A_DOORBELL_PORT7_TARGET_DIEID_MASK                             0x0000000CL
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL1__S2A_DOORBELL_PORT7_TARGET_PORT_ID_MASK                           0x00000030L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL1__S2A_DOORBELL_PORT7_OVERRIDE_POISON_DATA_MASK                     0x00000040L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_7_CTRL1__S2A_DOORBELL_PORT7_4K_PAGE_DECODE_DISABLE_MASK                   0x00000080L
+//GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_ENABLE__SHIFT                                  0x0
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_AWID__SHIFT                                    0x1
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_FENCE_ENABLE__SHIFT                            0x6
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_RANGE_OFFSET__SHIFT                            0x7
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_RANGE_SIZE__SHIFT                              0x11
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_64BIT_SUPPORT_DIS__SHIFT                       0x19
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_NEED_DEDUCT_RANGE_OFFSET__SHIFT                0x1a
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_DROP_EN__SHIFT                                 0x1b
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_AWADDR_31_28_VALUE__SHIFT                      0x1c
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_ENABLE_MASK                                    0x00000001L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_AWID_MASK                                      0x0000003EL
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_FENCE_ENABLE_MASK                              0x00000040L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_RANGE_OFFSET_MASK                              0x0001FF80L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_RANGE_SIZE_MASK                                0x01FE0000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_64BIT_SUPPORT_DIS_MASK                         0x02000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_NEED_DEDUCT_RANGE_OFFSET_MASK                  0x04000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_DROP_EN_MASK                                   0x08000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL__S2A_DOORBELL_PORT8_AWADDR_31_28_VALUE_MASK                        0xF0000000L
+//GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL1
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL1__S2A_DOORBELL_PORT8_TARGET_PORT_TYPE__SHIFT                       0x0
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL1__S2A_DOORBELL_PORT8_TARGET_DIEID__SHIFT                           0x2
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL1__S2A_DOORBELL_PORT8_TARGET_PORT_ID__SHIFT                         0x4
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL1__S2A_DOORBELL_PORT8_OVERRIDE_POISON_DATA__SHIFT                   0x6
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL1__S2A_DOORBELL_PORT8_4K_PAGE_DECODE_DISABLE__SHIFT                 0x7
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL1__S2A_DOORBELL_PORT8_TARGET_PORT_TYPE_MASK                         0x00000003L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL1__S2A_DOORBELL_PORT8_TARGET_DIEID_MASK                             0x0000000CL
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL1__S2A_DOORBELL_PORT8_TARGET_PORT_ID_MASK                           0x00000030L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL1__S2A_DOORBELL_PORT8_OVERRIDE_POISON_DATA_MASK                     0x00000040L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_8_CTRL1__S2A_DOORBELL_PORT8_4K_PAGE_DECODE_DISABLE_MASK                   0x00000080L
+//GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_ENABLE__SHIFT                                  0x0
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_AWID__SHIFT                                    0x1
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_FENCE_ENABLE__SHIFT                            0x6
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_RANGE_OFFSET__SHIFT                            0x7
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_RANGE_SIZE__SHIFT                              0x11
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_64BIT_SUPPORT_DIS__SHIFT                       0x19
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_NEED_DEDUCT_RANGE_OFFSET__SHIFT                0x1a
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_DROP_EN__SHIFT                                 0x1b
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_AWADDR_31_28_VALUE__SHIFT                      0x1c
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_ENABLE_MASK                                    0x00000001L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_AWID_MASK                                      0x0000003EL
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_FENCE_ENABLE_MASK                              0x00000040L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_RANGE_OFFSET_MASK                              0x0001FF80L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_RANGE_SIZE_MASK                                0x01FE0000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_64BIT_SUPPORT_DIS_MASK                         0x02000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_NEED_DEDUCT_RANGE_OFFSET_MASK                  0x04000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_DROP_EN_MASK                                   0x08000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL__S2A_DOORBELL_PORT9_AWADDR_31_28_VALUE_MASK                        0xF0000000L
+//GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL1
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL1__S2A_DOORBELL_PORT9_TARGET_PORT_TYPE__SHIFT                       0x0
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL1__S2A_DOORBELL_PORT9_TARGET_DIEID__SHIFT                           0x2
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL1__S2A_DOORBELL_PORT9_TARGET_PORT_ID__SHIFT                         0x4
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL1__S2A_DOORBELL_PORT9_OVERRIDE_POISON_DATA__SHIFT                   0x6
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL1__S2A_DOORBELL_PORT9_4K_PAGE_DECODE_DISABLE__SHIFT                 0x7
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL1__S2A_DOORBELL_PORT9_TARGET_PORT_TYPE_MASK                         0x00000003L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL1__S2A_DOORBELL_PORT9_TARGET_DIEID_MASK                             0x0000000CL
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL1__S2A_DOORBELL_PORT9_TARGET_PORT_ID_MASK                           0x00000030L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL1__S2A_DOORBELL_PORT9_OVERRIDE_POISON_DATA_MASK                     0x00000040L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_9_CTRL1__S2A_DOORBELL_PORT9_4K_PAGE_DECODE_DISABLE_MASK                   0x00000080L
+//GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_ENABLE__SHIFT                                0x0
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_AWID__SHIFT                                  0x1
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_FENCE_ENABLE__SHIFT                          0x6
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_RANGE_OFFSET__SHIFT                          0x7
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_RANGE_SIZE__SHIFT                            0x11
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_64BIT_SUPPORT_DIS__SHIFT                     0x19
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_NEED_DEDUCT_RANGE_OFFSET__SHIFT              0x1a
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_DROP_EN__SHIFT                               0x1b
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_AWADDR_31_28_VALUE__SHIFT                    0x1c
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_ENABLE_MASK                                  0x00000001L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_AWID_MASK                                    0x0000003EL
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_FENCE_ENABLE_MASK                            0x00000040L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_RANGE_OFFSET_MASK                            0x0001FF80L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_RANGE_SIZE_MASK                              0x01FE0000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_64BIT_SUPPORT_DIS_MASK                       0x02000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_NEED_DEDUCT_RANGE_OFFSET_MASK                0x04000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_DROP_EN_MASK                                 0x08000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL__S2A_DOORBELL_PORT10_AWADDR_31_28_VALUE_MASK                      0xF0000000L
+//GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL1
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL1__S2A_DOORBELL_PORT10_TARGET_PORT_TYPE__SHIFT                     0x0
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL1__S2A_DOORBELL_PORT10_TARGET_DIEID__SHIFT                         0x2
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL1__S2A_DOORBELL_PORT10_TARGET_PORT_ID__SHIFT                       0x4
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL1__S2A_DOORBELL_PORT10_OVERRIDE_POISON_DATA__SHIFT                 0x6
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL1__S2A_DOORBELL_PORT10_4K_PAGE_DECODE_DISABLE__SHIFT               0x7
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL1__S2A_DOORBELL_PORT10_TARGET_PORT_TYPE_MASK                       0x00000003L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL1__S2A_DOORBELL_PORT10_TARGET_DIEID_MASK                           0x0000000CL
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL1__S2A_DOORBELL_PORT10_TARGET_PORT_ID_MASK                         0x00000030L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL1__S2A_DOORBELL_PORT10_OVERRIDE_POISON_DATA_MASK                   0x00000040L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_10_CTRL1__S2A_DOORBELL_PORT10_4K_PAGE_DECODE_DISABLE_MASK                 0x00000080L
+//GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_ENABLE__SHIFT                                0x0
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_AWID__SHIFT                                  0x1
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_FENCE_ENABLE__SHIFT                          0x6
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_RANGE_OFFSET__SHIFT                          0x7
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_RANGE_SIZE__SHIFT                            0x11
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_64BIT_SUPPORT_DIS__SHIFT                     0x19
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_NEED_DEDUCT_RANGE_OFFSET__SHIFT              0x1a
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_DROP_EN__SHIFT                               0x1b
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_AWADDR_31_28_VALUE__SHIFT                    0x1c
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_ENABLE_MASK                                  0x00000001L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_AWID_MASK                                    0x0000003EL
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_FENCE_ENABLE_MASK                            0x00000040L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_RANGE_OFFSET_MASK                            0x0001FF80L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_RANGE_SIZE_MASK                              0x01FE0000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_64BIT_SUPPORT_DIS_MASK                       0x02000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_NEED_DEDUCT_RANGE_OFFSET_MASK                0x04000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_DROP_EN_MASK                                 0x08000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL__S2A_DOORBELL_PORT11_AWADDR_31_28_VALUE_MASK                      0xF0000000L
+//GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL1
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL1__S2A_DOORBELL_PORT11_TARGET_PORT_TYPE__SHIFT                     0x0
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL1__S2A_DOORBELL_PORT11_TARGET_DIEID__SHIFT                         0x2
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL1__S2A_DOORBELL_PORT11_TARGET_PORT_ID__SHIFT                       0x4
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL1__S2A_DOORBELL_PORT11_OVERRIDE_POISON_DATA__SHIFT                 0x6
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL1__S2A_DOORBELL_PORT11_4K_PAGE_DECODE_DISABLE__SHIFT               0x7
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL1__S2A_DOORBELL_PORT11_TARGET_PORT_TYPE_MASK                       0x00000003L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL1__S2A_DOORBELL_PORT11_TARGET_DIEID_MASK                           0x0000000CL
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL1__S2A_DOORBELL_PORT11_TARGET_PORT_ID_MASK                         0x00000030L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL1__S2A_DOORBELL_PORT11_OVERRIDE_POISON_DATA_MASK                   0x00000040L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_11_CTRL1__S2A_DOORBELL_PORT11_4K_PAGE_DECODE_DISABLE_MASK                 0x00000080L
+//GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_ENABLE__SHIFT                                0x0
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_AWID__SHIFT                                  0x1
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_FENCE_ENABLE__SHIFT                          0x6
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_RANGE_OFFSET__SHIFT                          0x7
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_RANGE_SIZE__SHIFT                            0x11
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_64BIT_SUPPORT_DIS__SHIFT                     0x19
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_NEED_DEDUCT_RANGE_OFFSET__SHIFT              0x1a
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_DROP_EN__SHIFT                               0x1b
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_AWADDR_31_28_VALUE__SHIFT                    0x1c
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_ENABLE_MASK                                  0x00000001L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_AWID_MASK                                    0x0000003EL
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_FENCE_ENABLE_MASK                            0x00000040L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_RANGE_OFFSET_MASK                            0x0001FF80L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_RANGE_SIZE_MASK                              0x01FE0000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_64BIT_SUPPORT_DIS_MASK                       0x02000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_NEED_DEDUCT_RANGE_OFFSET_MASK                0x04000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_DROP_EN_MASK                                 0x08000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL__S2A_DOORBELL_PORT12_AWADDR_31_28_VALUE_MASK                      0xF0000000L
+//GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL1
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL1__S2A_DOORBELL_PORT12_TARGET_PORT_TYPE__SHIFT                     0x0
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL1__S2A_DOORBELL_PORT12_TARGET_DIEID__SHIFT                         0x2
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL1__S2A_DOORBELL_PORT12_TARGET_PORT_ID__SHIFT                       0x4
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL1__S2A_DOORBELL_PORT12_OVERRIDE_POISON_DATA__SHIFT                 0x6
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL1__S2A_DOORBELL_PORT12_4K_PAGE_DECODE_DISABLE__SHIFT               0x7
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL1__S2A_DOORBELL_PORT12_TARGET_PORT_TYPE_MASK                       0x00000003L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL1__S2A_DOORBELL_PORT12_TARGET_DIEID_MASK                           0x0000000CL
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL1__S2A_DOORBELL_PORT12_TARGET_PORT_ID_MASK                         0x00000030L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL1__S2A_DOORBELL_PORT12_OVERRIDE_POISON_DATA_MASK                   0x00000040L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_12_CTRL1__S2A_DOORBELL_PORT12_4K_PAGE_DECODE_DISABLE_MASK                 0x00000080L
+//GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_ENABLE__SHIFT                                0x0
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_AWID__SHIFT                                  0x1
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_FENCE_ENABLE__SHIFT                          0x6
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_RANGE_OFFSET__SHIFT                          0x7
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_RANGE_SIZE__SHIFT                            0x11
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_64BIT_SUPPORT_DIS__SHIFT                     0x19
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_NEED_DEDUCT_RANGE_OFFSET__SHIFT              0x1a
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_DROP_EN__SHIFT                               0x1b
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_AWADDR_31_28_VALUE__SHIFT                    0x1c
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_ENABLE_MASK                                  0x00000001L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_AWID_MASK                                    0x0000003EL
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_FENCE_ENABLE_MASK                            0x00000040L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_RANGE_OFFSET_MASK                            0x0001FF80L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_RANGE_SIZE_MASK                              0x01FE0000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_64BIT_SUPPORT_DIS_MASK                       0x02000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_NEED_DEDUCT_RANGE_OFFSET_MASK                0x04000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_DROP_EN_MASK                                 0x08000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL__S2A_DOORBELL_PORT13_AWADDR_31_28_VALUE_MASK                      0xF0000000L
+//GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL1
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL1__S2A_DOORBELL_PORT13_TARGET_PORT_TYPE__SHIFT                     0x0
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL1__S2A_DOORBELL_PORT13_TARGET_DIEID__SHIFT                         0x2
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL1__S2A_DOORBELL_PORT13_TARGET_PORT_ID__SHIFT                       0x4
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL1__S2A_DOORBELL_PORT13_OVERRIDE_POISON_DATA__SHIFT                 0x6
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL1__S2A_DOORBELL_PORT13_4K_PAGE_DECODE_DISABLE__SHIFT               0x7
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL1__S2A_DOORBELL_PORT13_TARGET_PORT_TYPE_MASK                       0x00000003L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL1__S2A_DOORBELL_PORT13_TARGET_DIEID_MASK                           0x0000000CL
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL1__S2A_DOORBELL_PORT13_TARGET_PORT_ID_MASK                         0x00000030L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL1__S2A_DOORBELL_PORT13_OVERRIDE_POISON_DATA_MASK                   0x00000040L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_13_CTRL1__S2A_DOORBELL_PORT13_4K_PAGE_DECODE_DISABLE_MASK                 0x00000080L
+//GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_ENABLE__SHIFT                                0x0
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_AWID__SHIFT                                  0x1
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_FENCE_ENABLE__SHIFT                          0x6
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_RANGE_OFFSET__SHIFT                          0x7
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_RANGE_SIZE__SHIFT                            0x11
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_64BIT_SUPPORT_DIS__SHIFT                     0x19
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_NEED_DEDUCT_RANGE_OFFSET__SHIFT              0x1a
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_DROP_EN__SHIFT                               0x1b
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_AWADDR_31_28_VALUE__SHIFT                    0x1c
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_ENABLE_MASK                                  0x00000001L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_AWID_MASK                                    0x0000003EL
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_FENCE_ENABLE_MASK                            0x00000040L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_RANGE_OFFSET_MASK                            0x0001FF80L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_RANGE_SIZE_MASK                              0x01FE0000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_64BIT_SUPPORT_DIS_MASK                       0x02000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_NEED_DEDUCT_RANGE_OFFSET_MASK                0x04000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_DROP_EN_MASK                                 0x08000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL__S2A_DOORBELL_PORT14_AWADDR_31_28_VALUE_MASK                      0xF0000000L
+//GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL1
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL1__S2A_DOORBELL_PORT14_TARGET_PORT_TYPE__SHIFT                     0x0
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL1__S2A_DOORBELL_PORT14_TARGET_DIEID__SHIFT                         0x2
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL1__S2A_DOORBELL_PORT14_TARGET_PORT_ID__SHIFT                       0x4
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL1__S2A_DOORBELL_PORT14_OVERRIDE_POISON_DATA__SHIFT                 0x6
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL1__S2A_DOORBELL_PORT14_4K_PAGE_DECODE_DISABLE__SHIFT               0x7
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL1__S2A_DOORBELL_PORT14_TARGET_PORT_TYPE_MASK                       0x00000003L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL1__S2A_DOORBELL_PORT14_TARGET_DIEID_MASK                           0x0000000CL
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL1__S2A_DOORBELL_PORT14_TARGET_PORT_ID_MASK                         0x00000030L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL1__S2A_DOORBELL_PORT14_OVERRIDE_POISON_DATA_MASK                   0x00000040L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_14_CTRL1__S2A_DOORBELL_PORT14_4K_PAGE_DECODE_DISABLE_MASK                 0x00000080L
+//GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_ENABLE__SHIFT                                0x0
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_AWID__SHIFT                                  0x1
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_FENCE_ENABLE__SHIFT                          0x6
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_RANGE_OFFSET__SHIFT                          0x7
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_RANGE_SIZE__SHIFT                            0x11
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_64BIT_SUPPORT_DIS__SHIFT                     0x19
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_NEED_DEDUCT_RANGE_OFFSET__SHIFT              0x1a
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_DROP_EN__SHIFT                               0x1b
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_AWADDR_31_28_VALUE__SHIFT                    0x1c
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_ENABLE_MASK                                  0x00000001L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_AWID_MASK                                    0x0000003EL
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_FENCE_ENABLE_MASK                            0x00000040L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_RANGE_OFFSET_MASK                            0x0001FF80L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_RANGE_SIZE_MASK                              0x01FE0000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_64BIT_SUPPORT_DIS_MASK                       0x02000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_NEED_DEDUCT_RANGE_OFFSET_MASK                0x04000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_DROP_EN_MASK                                 0x08000000L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL__S2A_DOORBELL_PORT15_AWADDR_31_28_VALUE_MASK                      0xF0000000L
+//GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL1
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL1__S2A_DOORBELL_PORT15_TARGET_PORT_TYPE__SHIFT                     0x0
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL1__S2A_DOORBELL_PORT15_TARGET_DIEID__SHIFT                         0x2
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL1__S2A_DOORBELL_PORT15_TARGET_PORT_ID__SHIFT                       0x4
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL1__S2A_DOORBELL_PORT15_OVERRIDE_POISON_DATA__SHIFT                 0x6
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL1__S2A_DOORBELL_PORT15_4K_PAGE_DECODE_DISABLE__SHIFT               0x7
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL1__S2A_DOORBELL_PORT15_TARGET_PORT_TYPE_MASK                       0x00000003L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL1__S2A_DOORBELL_PORT15_TARGET_DIEID_MASK                           0x0000000CL
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL1__S2A_DOORBELL_PORT15_TARGET_PORT_ID_MASK                         0x00000030L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL1__S2A_DOORBELL_PORT15_OVERRIDE_POISON_DATA_MASK                   0x00000040L
+#define GDC_S2A1_S2A_DOORBELL_ENTRY_15_CTRL1__S2A_DOORBELL_PORT15_4K_PAGE_DECODE_DISABLE_MASK                 0x00000080L
+//GDC_S2A1_S2A_DOORBELL_COMMON_CTRL_REG
+#define GDC_S2A1_S2A_DOORBELL_COMMON_CTRL_REG__S2A_DOORBELL_FENCE_ONCE_TRIGGER_DIS__SHIFT                     0x0
+#define GDC_S2A1_S2A_DOORBELL_COMMON_CTRL_REG__S2A_DOORBE_FENCE_INTR_ENABLE__SHIFT                            0x1
+#define GDC_S2A1_S2A_DOORBELL_COMMON_CTRL_REG__S2A_DOORBELL_FENCE_ONCE_TRIGGER_DIS_MASK                       0x00000001L
+#define GDC_S2A1_S2A_DOORBELL_COMMON_CTRL_REG__S2A_DOORBE_FENCE_INTR_ENABLE_MASK                              0x00000002L
+//GDC_S2A1_NBIF_GFX_DOORBELL_STATUS
+#define GDC_S2A1_NBIF_GFX_DOORBELL_STATUS__NBIF_GFX_DOORBELL_SENT__SHIFT                                      0x0
+#define GDC_S2A1_NBIF_GFX_DOORBELL_STATUS__S2A_DOORBELL_ALL_CLR_EN__SHIFT                                     0x10
+#define GDC_S2A1_NBIF_GFX_DOORBELL_STATUS__S2A_DOORBELL_ALL_CLR_ST__SHIFT                                     0x18
+#define GDC_S2A1_NBIF_GFX_DOORBELL_STATUS__NBIF_GFX_DOORBELL_SENT_MASK                                        0x0000FFFFL
+#define GDC_S2A1_NBIF_GFX_DOORBELL_STATUS__S2A_DOORBELL_ALL_CLR_EN_MASK                                       0x00010000L
+#define GDC_S2A1_NBIF_GFX_DOORBELL_STATUS__S2A_DOORBELL_ALL_CLR_ST_MASK                                       0x01000000L
+
+
+// addressBlock: nbif0_nbif0_gdc_misc_GDCMISC_DEC
+//GDC_DMA_SION_CRED_RST
+#define GDC_DMA_SION_CRED_RST__GDC_DMA_SION_BIF_CRED_RST__SHIFT                                               0x0
+#define GDC_DMA_SION_CRED_RST__GDC_DMA_SION_BIF_SDP_TX_DS_MSK__SHIFT                                          0x1
+#define GDC_DMA_SION_CRED_RST__GDC_DMA_SION_BIF_SDP_RX_DS_MSK__SHIFT                                          0x2
+#define GDC_DMA_SION_CRED_RST__GDC_DMA_SION_SYSHUB_CRED_RST__SHIFT                                            0x4
+#define GDC_DMA_SION_CRED_RST__GDC_DMA_SION_SYSHUB_SDP_TX_DS_MSK__SHIFT                                       0x5
+#define GDC_DMA_SION_CRED_RST__GDC_DMA_SION_SYSHUB_SDP_RX_DS_MSK__SHIFT                                       0x6
+#define GDC_DMA_SION_CRED_RST__GDC_DMA_SION_INT_CRED_RST__SHIFT                                               0x8
+#define GDC_DMA_SION_CRED_RST__GDC_DMA_SION_INT_SDP_TX_DS_MSK__SHIFT                                          0x9
+#define GDC_DMA_SION_CRED_RST__GDC_DMA_SION_INT_SDP_RX_DS_MSK__SHIFT                                          0xa
+#define GDC_DMA_SION_CRED_RST__GDC_DMA_SION_BIF_CRED_RST_MASK                                                 0x00000001L
+#define GDC_DMA_SION_CRED_RST__GDC_DMA_SION_BIF_SDP_TX_DS_MSK_MASK                                            0x00000002L
+#define GDC_DMA_SION_CRED_RST__GDC_DMA_SION_BIF_SDP_RX_DS_MSK_MASK                                            0x00000004L
+#define GDC_DMA_SION_CRED_RST__GDC_DMA_SION_SYSHUB_CRED_RST_MASK                                              0x00000010L
+#define GDC_DMA_SION_CRED_RST__GDC_DMA_SION_SYSHUB_SDP_TX_DS_MSK_MASK                                         0x00000020L
+#define GDC_DMA_SION_CRED_RST__GDC_DMA_SION_SYSHUB_SDP_RX_DS_MSK_MASK                                         0x00000040L
+#define GDC_DMA_SION_CRED_RST__GDC_DMA_SION_INT_CRED_RST_MASK                                                 0x00000100L
+#define GDC_DMA_SION_CRED_RST__GDC_DMA_SION_INT_SDP_TX_DS_MSK_MASK                                            0x00000200L
+#define GDC_DMA_SION_CRED_RST__GDC_DMA_SION_INT_SDP_RX_DS_MSK_MASK                                            0x00000400L
+//GDC_HST_SION_PER_SDP_PORT_RST
+#define GDC_HST_SION_PER_SDP_PORT_RST__GDC_HST_SION_GSI_CRED_RST__SHIFT                                       0x0
+#define GDC_HST_SION_PER_SDP_PORT_RST__NBIF_GSI_SDP_PORT_RST__SHIFT                                           0x1
+#define GDC_HST_SION_PER_SDP_PORT_RST__NBIF_GSI_SDP_DISCON_DIS__SHIFT                                         0x2
+#define GDC_HST_SION_PER_SDP_PORT_RST__GDC_HST_SION_GSI_SDP_TX_DS_MSK__SHIFT                                  0x3
+#define GDC_HST_SION_PER_SDP_PORT_RST__GDC_HST_SION_GSI_SDP_RX_DS_MSK__SHIFT                                  0x4
+#define GDC_HST_SION_PER_SDP_PORT_RST__GDC_HST_SION_HSTHB_DB0_CRED_RST__SHIFT                                 0x5
+#define GDC_HST_SION_PER_SDP_PORT_RST__NBIF_HSTHB_DB0_SDP_PORT_RST__SHIFT                                     0x6
+#define GDC_HST_SION_PER_SDP_PORT_RST__NBIF_HSTHB_DB0_SDP_DISCON_DIS__SHIFT                                   0x7
+#define GDC_HST_SION_PER_SDP_PORT_RST__GDC_HST_SION_HSTHB_DB0_SDP_TX_DS_MSK__SHIFT                            0x8
+#define GDC_HST_SION_PER_SDP_PORT_RST__GDC_HST_SION_HSTHB_DB0_SDP_RX_DS_MSK__SHIFT                            0x9
+#define GDC_HST_SION_PER_SDP_PORT_RST__GDC_HST_SION_GSI_CRED_RST_MASK                                         0x00000001L
+#define GDC_HST_SION_PER_SDP_PORT_RST__NBIF_GSI_SDP_PORT_RST_MASK                                             0x00000002L
+#define GDC_HST_SION_PER_SDP_PORT_RST__NBIF_GSI_SDP_DISCON_DIS_MASK                                           0x00000004L
+#define GDC_HST_SION_PER_SDP_PORT_RST__GDC_HST_SION_GSI_SDP_TX_DS_MSK_MASK                                    0x00000008L
+#define GDC_HST_SION_PER_SDP_PORT_RST__GDC_HST_SION_GSI_SDP_RX_DS_MSK_MASK                                    0x00000010L
+#define GDC_HST_SION_PER_SDP_PORT_RST__GDC_HST_SION_HSTHB_DB0_CRED_RST_MASK                                   0x00000020L
+#define GDC_HST_SION_PER_SDP_PORT_RST__NBIF_HSTHB_DB0_SDP_PORT_RST_MASK                                       0x00000040L
+#define GDC_HST_SION_PER_SDP_PORT_RST__NBIF_HSTHB_DB0_SDP_DISCON_DIS_MASK                                     0x00000080L
+#define GDC_HST_SION_PER_SDP_PORT_RST__GDC_HST_SION_HSTHB_DB0_SDP_TX_DS_MSK_MASK                              0x00000100L
+#define GDC_HST_SION_PER_SDP_PORT_RST__GDC_HST_SION_HSTHB_DB0_SDP_RX_DS_MSK_MASK                              0x00000200L
+//GDC_HST_SION_PER_SDP_CNTL_REG1
+//GDC_HST_AXI_STALL_FOR_FLUSH
+#define GDC_HST_AXI_STALL_FOR_FLUSH__SHUB_HST_AXI_STALL_FOR_FLUSH_GFX__SHIFT                                  0x0
+#define GDC_HST_AXI_STALL_FOR_FLUSH__SHUB_HST_AXI_STALL_FOR_FLUSH_GFX_MASK                                    0x00000001L
+//SYSHUB_SDP_DEBUG_COUNTER_CTRL
+#define SYSHUB_SDP_DEBUG_COUNTER_CTRL__SHUB_SDP_DEBUG_COUNTER_EN__SHIFT                                       0x0
+#define SYSHUB_SDP_DEBUG_COUNTER_CTRL__SHUB_SDP_DEBUG_COUNTER_EN_MASK                                         0x00000001L
+//NBIF_PWRBRK_IN_PAD_CNTL
+#define NBIF_PWRBRK_IN_PAD_CNTL__PWRBRK_IN_PAD_CNTL_BIT0__SHIFT                                               0x0
+#define NBIF_PWRBRK_IN_PAD_CNTL__PWRBRK_IN_PAD_CNTL__SHIFT                                                    0x1
+#define NBIF_PWRBRK_IN_PAD_CNTL__PWRBRK_IN_PAD_CNTL_BIT0_MASK                                                 0x00000001L
+#define NBIF_PWRBRK_IN_PAD_CNTL__PWRBRK_IN_PAD_CNTL_MASK                                                      0x000000FEL
+//NBIF_PWRBRK_OUT_PAD_CNTL
+#define NBIF_PWRBRK_OUT_PAD_CNTL__PWRBRK_OUT_PAD_CNTL_BIT0__SHIFT                                             0x0
+#define NBIF_PWRBRK_OUT_PAD_CNTL__PWRBRK_OUT_PAD_CNTL__SHIFT                                                  0x1
+#define NBIF_PWRBRK_OUT_PAD_CNTL__PWRBRK_OUT_PAD_CNTL_BIT0_MASK                                               0x00000001L
+#define NBIF_PWRBRK_OUT_PAD_CNTL__PWRBRK_OUT_PAD_CNTL_MASK                                                    0x000000FEL
+//SHUB_OOB_CRUSH_DUMP_CTRL
+#define SHUB_OOB_CRUSH_DUMP_CTRL__REGS_SHUB_OOB_TRIGGER__SHIFT                                                0x0
+#define SHUB_OOB_CRUSH_DUMP_CTRL__REGS_SHUB_OOB_TRIGGER_MASK                                                  0x00000001L
+//SHUB_MP_ERREVENT_MASK_CTRL
+#define SHUB_MP_ERREVENT_MASK_CTRL__SHUB_MP_ERREVENT_MASK_EN__SHIFT                                           0x0
+#define SHUB_MP_ERREVENT_MASK_CTRL__MCA_FATAL_OUT_PROP_EN__SHIFT                                              0x1
+#define SHUB_MP_ERREVENT_MASK_CTRL__SHUB_MP_ERREVENT_MASK_EN_MASK                                             0x00000001L
+#define SHUB_MP_ERREVENT_MASK_CTRL__MCA_FATAL_OUT_PROP_EN_MASK                                                0x00000002L
+//SHUB_ERREREVNT_SIDEBAND_RAS_V1_CTRL
+#define SHUB_ERREREVNT_SIDEBAND_RAS_V1_CTRL__SHUB_PORT0_RAS_V1_GEN_ERREVENT_EN__SHIFT                         0x0
+#define SHUB_ERREREVNT_SIDEBAND_RAS_V1_CTRL__SHUB_PORT1_RAS_V1_GEN_ERREVENT_EN__SHIFT                         0x1
+#define SHUB_ERREREVNT_SIDEBAND_RAS_V1_CTRL__SHUB_PORT2_RAS_V1_GEN_ERREVENT_EN__SHIFT                         0x2
+#define SHUB_ERREREVNT_SIDEBAND_RAS_V1_CTRL__SHUB_PORT3_RAS_V1_GEN_ERREVENT_EN__SHIFT                         0x3
+#define SHUB_ERREREVNT_SIDEBAND_RAS_V1_CTRL__SHUB_PORT4_RAS_V1_GEN_ERREVENT_EN__SHIFT                         0x4
+#define SHUB_ERREREVNT_SIDEBAND_RAS_V1_CTRL__SHUB_PORT0_RAS_V1_GEN_ERREVENT_EN_MASK                           0x00000001L
+#define SHUB_ERREREVNT_SIDEBAND_RAS_V1_CTRL__SHUB_PORT1_RAS_V1_GEN_ERREVENT_EN_MASK                           0x00000002L
+#define SHUB_ERREREVNT_SIDEBAND_RAS_V1_CTRL__SHUB_PORT2_RAS_V1_GEN_ERREVENT_EN_MASK                           0x00000004L
+#define SHUB_ERREREVNT_SIDEBAND_RAS_V1_CTRL__SHUB_PORT3_RAS_V1_GEN_ERREVENT_EN_MASK                           0x00000008L
+#define SHUB_ERREREVNT_SIDEBAND_RAS_V1_CTRL__SHUB_PORT4_RAS_V1_GEN_ERREVENT_EN_MASK                           0x00000010L
+//SHUB_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL
+#define SHUB_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL__SHUB_PORT0_RECV_ERREVENT_GEN_ERREVENT_EN__SHIFT           0x0
+#define SHUB_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL__SHUB_PORT1_RECV_ERREVENT_GEN_ERREVENT_EN__SHIFT           0x1
+#define SHUB_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL__SHUB_PORT2_RECV_ERREVENT_GEN_ERREVENT_EN__SHIFT           0x2
+#define SHUB_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL__SHUB_PORT3_RECV_ERREVENT_GEN_ERREVENT_EN__SHIFT           0x3
+#define SHUB_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL__SHUB_PORT4_RECV_ERREVENT_GEN_ERREVENT_EN__SHIFT           0x4
+#define SHUB_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL__SHUB_PORT0_RECV_ERREVENT_GEN_ERREVENT_EN_MASK             0x00000001L
+#define SHUB_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL__SHUB_PORT1_RECV_ERREVENT_GEN_ERREVENT_EN_MASK             0x00000002L
+#define SHUB_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL__SHUB_PORT2_RECV_ERREVENT_GEN_ERREVENT_EN_MASK             0x00000004L
+#define SHUB_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL__SHUB_PORT3_RECV_ERREVENT_GEN_ERREVENT_EN_MASK             0x00000008L
+#define SHUB_ERREREVNT_SIDEBAND_RECV_ERREVENT_CTRL__SHUB_PORT4_RECV_ERREVENT_GEN_ERREVENT_EN_MASK             0x00000010L
+
+
+// addressBlock: nbif0_nbif0_gdc_sec_misc_GDCSEC_MISC_DEC
+//GDCSOC_SEC_DFV_POISON_INJ_DMACK0V3_AXI
+#define GDCSOC_SEC_DFV_POISON_INJ_DMACK0V3_AXI__DMACK0V3_EGRESS_RDATA_POISON_INJ__SHIFT                       0x8
+#define GDCSOC_SEC_DFV_POISON_INJ_DMACK0V3_AXI__DMACK0V3_EGRESS_RDATA_POISON_INJ_MASK                         0x00000F00L
+//GDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0V3_AXI
+#define GDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0V3_AXI__DMACK0V3_EGRESS_RDATA_POISON_INJ_CNT__SHIFT               0x8
+#define GDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0V3_AXI__DMACK0V3_EGRESS_RDATA_POISON_INJ_CNT_MASK                 0x00000F00L
+//GDCSOC_SEC_DFV_POISON_INJ_LOG_DMACK0V3_AXI
+//GDCSOC_SEC_DFV_POISON_INJ_DMACK0B_AXI
+#define GDCSOC_SEC_DFV_POISON_INJ_DMACK0B_AXI__DMACK0B_EGRESS_RDATA_POISON_INJ__SHIFT                         0x8
+#define GDCSOC_SEC_DFV_POISON_INJ_DMACK0B_AXI__DMACK0B_EGRESS_RDATA_POISON_INJ_MASK                           0x00000F00L
+//GDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0B_AXI
+#define GDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0B_AXI__DMACK0B_EGRESS_RDATA_POISON_INJ_CNT__SHIFT                 0x8
+#define GDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0B_AXI__DMACK0B_EGRESS_RDATA_POISON_INJ_CNT_MASK                   0x00000F00L
+//GDCSOC_SEC_DFV_POISON_INJ_LOG_DMACK0B_AXI
+//GDCSOC_SEC_DFV_POISON_INJ_DMACK0V4_AXI
+#define GDCSOC_SEC_DFV_POISON_INJ_DMACK0V4_AXI__DMACK0V4_EGRESS_RDATA_POISON_INJ__SHIFT                       0x8
+#define GDCSOC_SEC_DFV_POISON_INJ_DMACK0V4_AXI__DMACK0V4_EGRESS_RDATA_POISON_INJ_MASK                         0x00000F00L
+//GDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0V4_AXI
+#define GDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0V4_AXI__DMACK0V4_EGRESS_RDATA_POISON_INJ_CNT__SHIFT               0x8
+#define GDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0V4_AXI__DMACK0V4_EGRESS_RDATA_POISON_INJ_CNT_MASK                 0x00000F00L
+//GDCSOC_SEC_DFV_POISON_INJ_LOG_DMACK0V4_AXI
+//GDCSOC_SEC_DFV_POISON_INJ_DMACK0V4B_AXI
+#define GDCSOC_SEC_DFV_POISON_INJ_DMACK0V4B_AXI__DMACK0V4B_EGRESS_RDATA_POISON_INJ__SHIFT                     0x8
+#define GDCSOC_SEC_DFV_POISON_INJ_DMACK0V4B_AXI__DMACK0V4B_EGRESS_RDATA_POISON_INJ_MASK                       0x00000F00L
+//GDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0V4B_AXI
+#define GDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0V4B_AXI__DMACK0V4B_EGRESS_RDATA_POISON_INJ_CNT__SHIFT             0x8
+#define GDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0V4B_AXI__DMACK0V4B_EGRESS_RDATA_POISON_INJ_CNT_MASK               0x00000F00L
+//GDCSOC_SEC_DFV_POISON_INJ_LOG_DMACK0V4B_AXI
+//GDCSOC_SEC_DFV_POISON_INJ_DMACK0V7_AXI
+#define GDCSOC_SEC_DFV_POISON_INJ_DMACK0V7_AXI__DMACK0V7_EGRESS_RDATA_POISON_INJ__SHIFT                       0x8
+#define GDCSOC_SEC_DFV_POISON_INJ_DMACK0V7_AXI__DMACK0V7_EGRESS_RDATA_POISON_INJ_MASK                         0x00000F00L
+//GDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0V7_AXI
+#define GDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0V7_AXI__DMACK0V7_EGRESS_RDATA_POISON_INJ_CNT__SHIFT               0x8
+#define GDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0V7_AXI__DMACK0V7_EGRESS_RDATA_POISON_INJ_CNT_MASK                 0x00000F00L
+//GDCSOC_SEC_DFV_POISON_INJ_LOG_DMACK0V7_AXI
+//GDCSOC_SEC_DFV_POISON_INJ_SHUB_CNDI_ORIG_SDP
+#define GDCSOC_SEC_DFV_POISON_INJ_SHUB_CNDI_ORIG_SDP__SHUB_CNDI_ORIG_EGRESS_ORIGDATA_POISON_INJ__SHIFT        0x8
+#define GDCSOC_SEC_DFV_POISON_INJ_SHUB_CNDI_ORIG_SDP__SHUB_CNDI_ORIG_EGRESS_ORIGDATA_PARITY_INJ__SHIFT        0xc
+#define GDCSOC_SEC_DFV_POISON_INJ_SHUB_CNDI_ORIG_SDP__SHUB_CNDI_ORIG_EGRESS_ORIGDATA_POISON_INJ_MASK          0x00000F00L
+#define GDCSOC_SEC_DFV_POISON_INJ_SHUB_CNDI_ORIG_SDP__SHUB_CNDI_ORIG_EGRESS_ORIGDATA_PARITY_INJ_MASK          0x0000F000L
+//GDCSOC_SEC_DFV_POISON_INJ_CNT_SHUB_CNDI_ORIG_SDP
+#define GDCSOC_SEC_DFV_POISON_INJ_CNT_SHUB_CNDI_ORIG_SDP__SHUB_CNDI_ORIG_EGRESS_ORIGDATA_POISON_INJ_CNT__SHIFT  0x8
+#define GDCSOC_SEC_DFV_POISON_INJ_CNT_SHUB_CNDI_ORIG_SDP__SHUB_CNDI_ORIG_EGRESS_ORIGDATA_PARITY_INJ_CNT__SHIFT  0xc
+#define GDCSOC_SEC_DFV_POISON_INJ_CNT_SHUB_CNDI_ORIG_SDP__SHUB_CNDI_ORIG_EGRESS_ORIGDATA_POISON_INJ_CNT_MASK  0x00000F00L
+#define GDCSOC_SEC_DFV_POISON_INJ_CNT_SHUB_CNDI_ORIG_SDP__SHUB_CNDI_ORIG_EGRESS_ORIGDATA_PARITY_INJ_CNT_MASK  0x0000F000L
+//GDCSOC_SEC_DFV_POISON_INJ_LOG_SHUB_CNDI_ORIG_SDP
+//GDCSOC_SEC_DFV_POISON_INJ_DMACK0B1_AXI
+#define GDCSOC_SEC_DFV_POISON_INJ_DMACK0B1_AXI__DMACK0B1_EGRESS_RDATA_POISON_INJ__SHIFT                       0x8
+#define GDCSOC_SEC_DFV_POISON_INJ_DMACK0B1_AXI__DMACK0B1_EGRESS_RDATA_POISON_INJ_MASK                         0x00000F00L
+//GDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0B1_AXI
+#define GDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0B1_AXI__DMACK0B1_EGRESS_RDATA_POISON_INJ_CNT__SHIFT               0x8
+#define GDCSOC_SEC_DFV_POISON_INJ_CNT_DMACK0B1_AXI__DMACK0B1_EGRESS_RDATA_POISON_INJ_CNT_MASK                 0x00000F00L
+//GDCSOC_SEC_DFV_POISON_INJ_LOG_DMACK0B1_AXI
+//GDCSOC_SEC_RAS_POISON_DBUG_CTRL
+#define GDCSOC_SEC_RAS_POISON_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF0_CTRL_POISON_DBUG_EN__SHIFT                      0x0
+#define GDCSOC_SEC_RAS_POISON_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF1_CTRL_POISON_DBUG_EN__SHIFT                      0x1
+#define GDCSOC_SEC_RAS_POISON_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF2_CTRL_POISON_DBUG_EN__SHIFT                      0x2
+#define GDCSOC_SEC_RAS_POISON_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF3_CTRL_POISON_DBUG_EN__SHIFT                      0x3
+#define GDCSOC_SEC_RAS_POISON_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF4_CTRL_POISON_DBUG_EN__SHIFT                      0x4
+#define GDCSOC_SEC_RAS_POISON_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF5_CTRL_POISON_DBUG_EN__SHIFT                      0x5
+#define GDCSOC_SEC_RAS_POISON_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF6_CTRL_POISON_DBUG_EN__SHIFT                      0x6
+#define GDCSOC_SEC_RAS_POISON_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF7_CTRL_POISON_DBUG_EN__SHIFT                      0x7
+#define GDCSOC_SEC_RAS_POISON_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF8_CTRL_POISON_DBUG_EN__SHIFT                      0x8
+#define GDCSOC_SEC_RAS_POISON_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF9_CTRL_POISON_DBUG_EN__SHIFT                      0x9
+#define GDCSOC_SEC_RAS_POISON_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF10_CTRL_POISON_DBUG_EN__SHIFT                     0xa
+#define GDCSOC_SEC_RAS_POISON_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF11_CTRL_POISON_DBUG_EN__SHIFT                     0xb
+#define GDCSOC_SEC_RAS_POISON_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF12_CTRL_POISON_DBUG_EN__SHIFT                     0xc
+#define GDCSOC_SEC_RAS_POISON_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF13_CTRL_POISON_DBUG_EN__SHIFT                     0xd
+#define GDCSOC_SEC_RAS_POISON_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF0_CTRL_POISON_DBUG_EN_MASK                        0x00000001L
+#define GDCSOC_SEC_RAS_POISON_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF1_CTRL_POISON_DBUG_EN_MASK                        0x00000002L
+#define GDCSOC_SEC_RAS_POISON_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF2_CTRL_POISON_DBUG_EN_MASK                        0x00000004L
+#define GDCSOC_SEC_RAS_POISON_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF3_CTRL_POISON_DBUG_EN_MASK                        0x00000008L
+#define GDCSOC_SEC_RAS_POISON_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF4_CTRL_POISON_DBUG_EN_MASK                        0x00000010L
+#define GDCSOC_SEC_RAS_POISON_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF5_CTRL_POISON_DBUG_EN_MASK                        0x00000020L
+#define GDCSOC_SEC_RAS_POISON_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF6_CTRL_POISON_DBUG_EN_MASK                        0x00000040L
+#define GDCSOC_SEC_RAS_POISON_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF7_CTRL_POISON_DBUG_EN_MASK                        0x00000080L
+#define GDCSOC_SEC_RAS_POISON_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF8_CTRL_POISON_DBUG_EN_MASK                        0x00000100L
+#define GDCSOC_SEC_RAS_POISON_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF9_CTRL_POISON_DBUG_EN_MASK                        0x00000200L
+#define GDCSOC_SEC_RAS_POISON_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF10_CTRL_POISON_DBUG_EN_MASK                       0x00000400L
+#define GDCSOC_SEC_RAS_POISON_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF11_CTRL_POISON_DBUG_EN_MASK                       0x00000800L
+#define GDCSOC_SEC_RAS_POISON_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF12_CTRL_POISON_DBUG_EN_MASK                       0x00001000L
+#define GDCSOC_SEC_RAS_POISON_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF13_CTRL_POISON_DBUG_EN_MASK                       0x00002000L
+//GDCSOC_SEC_RAS_PARITY_DBUG_CTRL
+#define GDCSOC_SEC_RAS_PARITY_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF0_CTRL_PARITY_DBUG_EN__SHIFT                      0x0
+#define GDCSOC_SEC_RAS_PARITY_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF1_CTRL_PARITY_DBUG_EN__SHIFT                      0x1
+#define GDCSOC_SEC_RAS_PARITY_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF2_CTRL_PARITY_DBUG_EN__SHIFT                      0x2
+#define GDCSOC_SEC_RAS_PARITY_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF3_CTRL_PARITY_DBUG_EN__SHIFT                      0x3
+#define GDCSOC_SEC_RAS_PARITY_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF4_CTRL_PARITY_DBUG_EN__SHIFT                      0x4
+#define GDCSOC_SEC_RAS_PARITY_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF5_CTRL_PARITY_DBUG_EN__SHIFT                      0x5
+#define GDCSOC_SEC_RAS_PARITY_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF6_CTRL_PARITY_DBUG_EN__SHIFT                      0x6
+#define GDCSOC_SEC_RAS_PARITY_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF7_CTRL_PARITY_DBUG_EN__SHIFT                      0x7
+#define GDCSOC_SEC_RAS_PARITY_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF8_CTRL_PARITY_DBUG_EN__SHIFT                      0x8
+#define GDCSOC_SEC_RAS_PARITY_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF9_CTRL_PARITY_DBUG_EN__SHIFT                      0x9
+#define GDCSOC_SEC_RAS_PARITY_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF10_CTRL_PARITY_DBUG_EN__SHIFT                     0xa
+#define GDCSOC_SEC_RAS_PARITY_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF11_CTRL_PARITY_DBUG_EN__SHIFT                     0xb
+#define GDCSOC_SEC_RAS_PARITY_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF12_CTRL_PARITY_DBUG_EN__SHIFT                     0xc
+#define GDCSOC_SEC_RAS_PARITY_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF13_CTRL_PARITY_DBUG_EN__SHIFT                     0xd
+#define GDCSOC_SEC_RAS_PARITY_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF0_CTRL_PARITY_DBUG_EN_MASK                        0x00000001L
+#define GDCSOC_SEC_RAS_PARITY_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF1_CTRL_PARITY_DBUG_EN_MASK                        0x00000002L
+#define GDCSOC_SEC_RAS_PARITY_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF2_CTRL_PARITY_DBUG_EN_MASK                        0x00000004L
+#define GDCSOC_SEC_RAS_PARITY_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF3_CTRL_PARITY_DBUG_EN_MASK                        0x00000008L
+#define GDCSOC_SEC_RAS_PARITY_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF4_CTRL_PARITY_DBUG_EN_MASK                        0x00000010L
+#define GDCSOC_SEC_RAS_PARITY_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF5_CTRL_PARITY_DBUG_EN_MASK                        0x00000020L
+#define GDCSOC_SEC_RAS_PARITY_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF6_CTRL_PARITY_DBUG_EN_MASK                        0x00000040L
+#define GDCSOC_SEC_RAS_PARITY_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF7_CTRL_PARITY_DBUG_EN_MASK                        0x00000080L
+#define GDCSOC_SEC_RAS_PARITY_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF8_CTRL_PARITY_DBUG_EN_MASK                        0x00000100L
+#define GDCSOC_SEC_RAS_PARITY_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF9_CTRL_PARITY_DBUG_EN_MASK                        0x00000200L
+#define GDCSOC_SEC_RAS_PARITY_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF10_CTRL_PARITY_DBUG_EN_MASK                       0x00000400L
+#define GDCSOC_SEC_RAS_PARITY_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF11_CTRL_PARITY_DBUG_EN_MASK                       0x00000800L
+#define GDCSOC_SEC_RAS_PARITY_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF12_CTRL_PARITY_DBUG_EN_MASK                       0x00001000L
+#define GDCSOC_SEC_RAS_PARITY_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF13_CTRL_PARITY_DBUG_EN_MASK                       0x00002000L
+//GDCSOC_SEC_RAS_RCVERREVENT_DBUG_CTRL
+#define GDCSOC_SEC_RAS_RCVERREVENT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF0_CTRL_RCVERREVENT_DBUG_EN__SHIFT            0x0
+#define GDCSOC_SEC_RAS_RCVERREVENT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF1_CTRL_RCVERREVENT_DBUG_EN__SHIFT            0x1
+#define GDCSOC_SEC_RAS_RCVERREVENT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF2_CTRL_RCVERREVENT_DBUG_EN__SHIFT            0x2
+#define GDCSOC_SEC_RAS_RCVERREVENT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF3_CTRL_RCVERREVENT_DBUG_EN__SHIFT            0x3
+#define GDCSOC_SEC_RAS_RCVERREVENT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF4_CTRL_RCVERREVENT_DBUG_EN__SHIFT            0x4
+#define GDCSOC_SEC_RAS_RCVERREVENT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF5_CTRL_RCVERREVENT_DBUG_EN__SHIFT            0x5
+#define GDCSOC_SEC_RAS_RCVERREVENT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF6_CTRL_RCVERREVENT_DBUG_EN__SHIFT            0x6
+#define GDCSOC_SEC_RAS_RCVERREVENT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF7_CTRL_RCVERREVENT_DBUG_EN__SHIFT            0x7
+#define GDCSOC_SEC_RAS_RCVERREVENT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF8_CTRL_RCVERREVENT_DBUG_EN__SHIFT            0x8
+#define GDCSOC_SEC_RAS_RCVERREVENT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF9_CTRL_RCVERREVENT_DBUG_EN__SHIFT            0x9
+#define GDCSOC_SEC_RAS_RCVERREVENT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF10_CTRL_RCVERREVENT_DBUG_EN__SHIFT           0xa
+#define GDCSOC_SEC_RAS_RCVERREVENT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF11_CTRL_RCVERREVENT_DBUG_EN__SHIFT           0xb
+#define GDCSOC_SEC_RAS_RCVERREVENT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF12_CTRL_RCVERREVENT_DBUG_EN__SHIFT           0xc
+#define GDCSOC_SEC_RAS_RCVERREVENT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF13_CTRL_RCVERREVENT_DBUG_EN__SHIFT           0xd
+#define GDCSOC_SEC_RAS_RCVERREVENT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF0_CTRL_RCVERREVENT_DBUG_EN_MASK              0x00000001L
+#define GDCSOC_SEC_RAS_RCVERREVENT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF1_CTRL_RCVERREVENT_DBUG_EN_MASK              0x00000002L
+#define GDCSOC_SEC_RAS_RCVERREVENT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF2_CTRL_RCVERREVENT_DBUG_EN_MASK              0x00000004L
+#define GDCSOC_SEC_RAS_RCVERREVENT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF3_CTRL_RCVERREVENT_DBUG_EN_MASK              0x00000008L
+#define GDCSOC_SEC_RAS_RCVERREVENT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF4_CTRL_RCVERREVENT_DBUG_EN_MASK              0x00000010L
+#define GDCSOC_SEC_RAS_RCVERREVENT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF5_CTRL_RCVERREVENT_DBUG_EN_MASK              0x00000020L
+#define GDCSOC_SEC_RAS_RCVERREVENT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF6_CTRL_RCVERREVENT_DBUG_EN_MASK              0x00000040L
+#define GDCSOC_SEC_RAS_RCVERREVENT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF7_CTRL_RCVERREVENT_DBUG_EN_MASK              0x00000080L
+#define GDCSOC_SEC_RAS_RCVERREVENT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF8_CTRL_RCVERREVENT_DBUG_EN_MASK              0x00000100L
+#define GDCSOC_SEC_RAS_RCVERREVENT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF9_CTRL_RCVERREVENT_DBUG_EN_MASK              0x00000200L
+#define GDCSOC_SEC_RAS_RCVERREVENT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF10_CTRL_RCVERREVENT_DBUG_EN_MASK             0x00000400L
+#define GDCSOC_SEC_RAS_RCVERREVENT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF11_CTRL_RCVERREVENT_DBUG_EN_MASK             0x00000800L
+#define GDCSOC_SEC_RAS_RCVERREVENT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF12_CTRL_RCVERREVENT_DBUG_EN_MASK             0x00001000L
+#define GDCSOC_SEC_RAS_RCVERREVENT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF13_CTRL_RCVERREVENT_DBUG_EN_MASK             0x00002000L
+//GDCSOC_SEC_RAS_TIMEOUT_DBUG_CTRL
+#define GDCSOC_SEC_RAS_TIMEOUT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF0_CTRL_TIMEOUT_DBUG_EN__SHIFT                    0x0
+#define GDCSOC_SEC_RAS_TIMEOUT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF1_CTRL_TIMEOUT_DBUG_EN__SHIFT                    0x1
+#define GDCSOC_SEC_RAS_TIMEOUT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF2_CTRL_TIMEOUT_DBUG_EN__SHIFT                    0x2
+#define GDCSOC_SEC_RAS_TIMEOUT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF3_CTRL_TIMEOUT_DBUG_EN__SHIFT                    0x3
+#define GDCSOC_SEC_RAS_TIMEOUT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF4_CTRL_TIMEOUT_DBUG_EN__SHIFT                    0x4
+#define GDCSOC_SEC_RAS_TIMEOUT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF5_CTRL_TIMEOUT_DBUG_EN__SHIFT                    0x5
+#define GDCSOC_SEC_RAS_TIMEOUT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF6_CTRL_TIMEOUT_DBUG_EN__SHIFT                    0x6
+#define GDCSOC_SEC_RAS_TIMEOUT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF7_CTRL_TIMEOUT_DBUG_EN__SHIFT                    0x7
+#define GDCSOC_SEC_RAS_TIMEOUT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF8_CTRL_TIMEOUT_DBUG_EN__SHIFT                    0x8
+#define GDCSOC_SEC_RAS_TIMEOUT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF9_CTRL_TIMEOUT_DBUG_EN__SHIFT                    0x9
+#define GDCSOC_SEC_RAS_TIMEOUT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF10_CTRL_TIMEOUT_DBUG_EN__SHIFT                   0xa
+#define GDCSOC_SEC_RAS_TIMEOUT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF11_CTRL_TIMEOUT_DBUG_EN__SHIFT                   0xb
+#define GDCSOC_SEC_RAS_TIMEOUT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF12_CTRL_TIMEOUT_DBUG_EN__SHIFT                   0xc
+#define GDCSOC_SEC_RAS_TIMEOUT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF13_CTRL_TIMEOUT_DBUG_EN__SHIFT                   0xd
+#define GDCSOC_SEC_RAS_TIMEOUT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF0_CTRL_TIMEOUT_DBUG_EN_MASK                      0x00000001L
+#define GDCSOC_SEC_RAS_TIMEOUT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF1_CTRL_TIMEOUT_DBUG_EN_MASK                      0x00000002L
+#define GDCSOC_SEC_RAS_TIMEOUT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF2_CTRL_TIMEOUT_DBUG_EN_MASK                      0x00000004L
+#define GDCSOC_SEC_RAS_TIMEOUT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF3_CTRL_TIMEOUT_DBUG_EN_MASK                      0x00000008L
+#define GDCSOC_SEC_RAS_TIMEOUT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF4_CTRL_TIMEOUT_DBUG_EN_MASK                      0x00000010L
+#define GDCSOC_SEC_RAS_TIMEOUT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF5_CTRL_TIMEOUT_DBUG_EN_MASK                      0x00000020L
+#define GDCSOC_SEC_RAS_TIMEOUT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF6_CTRL_TIMEOUT_DBUG_EN_MASK                      0x00000040L
+#define GDCSOC_SEC_RAS_TIMEOUT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF7_CTRL_TIMEOUT_DBUG_EN_MASK                      0x00000080L
+#define GDCSOC_SEC_RAS_TIMEOUT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF8_CTRL_TIMEOUT_DBUG_EN_MASK                      0x00000100L
+#define GDCSOC_SEC_RAS_TIMEOUT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF9_CTRL_TIMEOUT_DBUG_EN_MASK                      0x00000200L
+#define GDCSOC_SEC_RAS_TIMEOUT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF10_CTRL_TIMEOUT_DBUG_EN_MASK                     0x00000400L
+#define GDCSOC_SEC_RAS_TIMEOUT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF11_CTRL_TIMEOUT_DBUG_EN_MASK                     0x00000800L
+#define GDCSOC_SEC_RAS_TIMEOUT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF12_CTRL_TIMEOUT_DBUG_EN_MASK                     0x00001000L
+#define GDCSOC_SEC_RAS_TIMEOUT_DBUG_CTRL__GDCSOC_SEC_RAS_LEAF13_CTRL_TIMEOUT_DBUG_EN_MASK                     0x00002000L
+//GDCSOC_SEC_RAS_POISON_DATA_DROP_CTRL
+#define GDCSOC_SEC_RAS_POISON_DATA_DROP_CTRL__GDCSOC_SEC_RAS_LEAF0_POISON_DATA_DROP_EN__SHIFT                 0x0
+#define GDCSOC_SEC_RAS_POISON_DATA_DROP_CTRL__GDCSOC_SEC_RAS_LEAF1_POISON_DATA_DROP_EN__SHIFT                 0x1
+#define GDCSOC_SEC_RAS_POISON_DATA_DROP_CTRL__GDCSOC_SEC_RAS_LEAF2_POISON_DATA_DROP_EN__SHIFT                 0x2
+#define GDCSOC_SEC_RAS_POISON_DATA_DROP_CTRL__GDCSOC_SEC_RAS_LEAF3_POISON_DATA_DROP_EN__SHIFT                 0x3
+#define GDCSOC_SEC_RAS_POISON_DATA_DROP_CTRL__GDCSOC_SEC_RAS_LEAF4_POISON_DATA_DROP_EN__SHIFT                 0x4
+#define GDCSOC_SEC_RAS_POISON_DATA_DROP_CTRL__GDCSOC_SEC_RAS_LEAF5_POISON_DATA_DROP_EN__SHIFT                 0x5
+#define GDCSOC_SEC_RAS_POISON_DATA_DROP_CTRL__GDCSOC_SEC_RAS_LEAF6_POISON_DATA_DROP_EN__SHIFT                 0x6
+#define GDCSOC_SEC_RAS_POISON_DATA_DROP_CTRL__GDCSOC_SEC_RAS_LEAF7_POISON_DATA_DROP_EN__SHIFT                 0x7
+#define GDCSOC_SEC_RAS_POISON_DATA_DROP_CTRL__GDCSOC_SEC_RAS_LEAF8_POISON_DATA_DROP_EN__SHIFT                 0x8
+#define GDCSOC_SEC_RAS_POISON_DATA_DROP_CTRL__GDCSOC_SEC_RAS_LEAF9_POISON_DATA_DROP_EN__SHIFT                 0x9
+#define GDCSOC_SEC_RAS_POISON_DATA_DROP_CTRL__GDCSOC_SEC_RAS_LEAF10_POISON_DATA_DROP_EN__SHIFT                0xa
+#define GDCSOC_SEC_RAS_POISON_DATA_DROP_CTRL__GDCSOC_SEC_RAS_LEAF11_POISON_DATA_DROP_EN__SHIFT                0xb
+#define GDCSOC_SEC_RAS_POISON_DATA_DROP_CTRL__GDCSOC_SEC_RAS_LEAF12_POISON_DATA_DROP_EN__SHIFT                0xc
+#define GDCSOC_SEC_RAS_POISON_DATA_DROP_CTRL__GDCSOC_SEC_RAS_LEAF13_POISON_DATA_DROP_EN__SHIFT                0xd
+#define GDCSOC_SEC_RAS_POISON_DATA_DROP_CTRL__GDCSOC_SEC_RAS_LEAF0_POISON_DATA_DROP_EN_MASK                   0x00000001L
+#define GDCSOC_SEC_RAS_POISON_DATA_DROP_CTRL__GDCSOC_SEC_RAS_LEAF1_POISON_DATA_DROP_EN_MASK                   0x00000002L
+#define GDCSOC_SEC_RAS_POISON_DATA_DROP_CTRL__GDCSOC_SEC_RAS_LEAF2_POISON_DATA_DROP_EN_MASK                   0x00000004L
+#define GDCSOC_SEC_RAS_POISON_DATA_DROP_CTRL__GDCSOC_SEC_RAS_LEAF3_POISON_DATA_DROP_EN_MASK                   0x00000008L
+#define GDCSOC_SEC_RAS_POISON_DATA_DROP_CTRL__GDCSOC_SEC_RAS_LEAF4_POISON_DATA_DROP_EN_MASK                   0x00000010L
+#define GDCSOC_SEC_RAS_POISON_DATA_DROP_CTRL__GDCSOC_SEC_RAS_LEAF5_POISON_DATA_DROP_EN_MASK                   0x00000020L
+#define GDCSOC_SEC_RAS_POISON_DATA_DROP_CTRL__GDCSOC_SEC_RAS_LEAF6_POISON_DATA_DROP_EN_MASK                   0x00000040L
+#define GDCSOC_SEC_RAS_POISON_DATA_DROP_CTRL__GDCSOC_SEC_RAS_LEAF7_POISON_DATA_DROP_EN_MASK                   0x00000080L
+#define GDCSOC_SEC_RAS_POISON_DATA_DROP_CTRL__GDCSOC_SEC_RAS_LEAF8_POISON_DATA_DROP_EN_MASK                   0x00000100L
+#define GDCSOC_SEC_RAS_POISON_DATA_DROP_CTRL__GDCSOC_SEC_RAS_LEAF9_POISON_DATA_DROP_EN_MASK                   0x00000200L
+#define GDCSOC_SEC_RAS_POISON_DATA_DROP_CTRL__GDCSOC_SEC_RAS_LEAF10_POISON_DATA_DROP_EN_MASK                  0x00000400L
+#define GDCSOC_SEC_RAS_POISON_DATA_DROP_CTRL__GDCSOC_SEC_RAS_LEAF11_POISON_DATA_DROP_EN_MASK                  0x00000800L
+#define GDCSOC_SEC_RAS_POISON_DATA_DROP_CTRL__GDCSOC_SEC_RAS_LEAF12_POISON_DATA_DROP_EN_MASK                  0x00001000L
+#define GDCSOC_SEC_RAS_POISON_DATA_DROP_CTRL__GDCSOC_SEC_RAS_LEAF13_POISON_DATA_DROP_EN_MASK                  0x00002000L
+//GDCSOC_SEC_RAS_RESPONSE_DROP_CTRL
+#define GDCSOC_SEC_RAS_RESPONSE_DROP_CTRL__GDCSOC_SEC_RAS_LEAF0_RESPONSE_DROP_EN__SHIFT                       0x0
+#define GDCSOC_SEC_RAS_RESPONSE_DROP_CTRL__GDCSOC_SEC_RAS_LEAF1_RESPONSE_DROP_EN__SHIFT                       0x1
+#define GDCSOC_SEC_RAS_RESPONSE_DROP_CTRL__GDCSOC_SEC_RAS_LEAF2_RESPONSE_DROP_EN__SHIFT                       0x2
+#define GDCSOC_SEC_RAS_RESPONSE_DROP_CTRL__GDCSOC_SEC_RAS_LEAF3_RESPONSE_DROP_EN__SHIFT                       0x3
+#define GDCSOC_SEC_RAS_RESPONSE_DROP_CTRL__GDCSOC_SEC_RAS_LEAF4_RESPONSE_DROP_EN__SHIFT                       0x4
+#define GDCSOC_SEC_RAS_RESPONSE_DROP_CTRL__GDCSOC_SEC_RAS_LEAF5_RESPONSE_DROP_EN__SHIFT                       0x5
+#define GDCSOC_SEC_RAS_RESPONSE_DROP_CTRL__GDCSOC_SEC_RAS_LEAF6_RESPONSE_DROP_EN__SHIFT                       0x6
+#define GDCSOC_SEC_RAS_RESPONSE_DROP_CTRL__GDCSOC_SEC_RAS_LEAF7_RESPONSE_DROP_EN__SHIFT                       0x7
+#define GDCSOC_SEC_RAS_RESPONSE_DROP_CTRL__GDCSOC_SEC_RAS_LEAF8_RESPONSE_DROP_EN__SHIFT                       0x8
+#define GDCSOC_SEC_RAS_RESPONSE_DROP_CTRL__GDCSOC_SEC_RAS_LEAF9_RESPONSE_DROP_EN__SHIFT                       0x9
+#define GDCSOC_SEC_RAS_RESPONSE_DROP_CTRL__GDCSOC_SEC_RAS_LEAF10_RESPONSE_DROP_EN__SHIFT                      0xa
+#define GDCSOC_SEC_RAS_RESPONSE_DROP_CTRL__GDCSOC_SEC_RAS_LEAF11_RESPONSE_DROP_EN__SHIFT                      0xb
+#define GDCSOC_SEC_RAS_RESPONSE_DROP_CTRL__GDCSOC_SEC_RAS_LEAF12_RESPONSE_DROP_EN__SHIFT                      0xc
+#define GDCSOC_SEC_RAS_RESPONSE_DROP_CTRL__GDCSOC_SEC_RAS_LEAF13_RESPONSE_DROP_EN__SHIFT                      0xd
+#define GDCSOC_SEC_RAS_RESPONSE_DROP_CTRL__GDCSOC_SEC_RAS_LEAF0_RESPONSE_DROP_EN_MASK                         0x00000001L
+#define GDCSOC_SEC_RAS_RESPONSE_DROP_CTRL__GDCSOC_SEC_RAS_LEAF1_RESPONSE_DROP_EN_MASK                         0x00000002L
+#define GDCSOC_SEC_RAS_RESPONSE_DROP_CTRL__GDCSOC_SEC_RAS_LEAF2_RESPONSE_DROP_EN_MASK                         0x00000004L
+#define GDCSOC_SEC_RAS_RESPONSE_DROP_CTRL__GDCSOC_SEC_RAS_LEAF3_RESPONSE_DROP_EN_MASK                         0x00000008L
+#define GDCSOC_SEC_RAS_RESPONSE_DROP_CTRL__GDCSOC_SEC_RAS_LEAF4_RESPONSE_DROP_EN_MASK                         0x00000010L
+#define GDCSOC_SEC_RAS_RESPONSE_DROP_CTRL__GDCSOC_SEC_RAS_LEAF5_RESPONSE_DROP_EN_MASK                         0x00000020L
+#define GDCSOC_SEC_RAS_RESPONSE_DROP_CTRL__GDCSOC_SEC_RAS_LEAF6_RESPONSE_DROP_EN_MASK                         0x00000040L
+#define GDCSOC_SEC_RAS_RESPONSE_DROP_CTRL__GDCSOC_SEC_RAS_LEAF7_RESPONSE_DROP_EN_MASK                         0x00000080L
+#define GDCSOC_SEC_RAS_RESPONSE_DROP_CTRL__GDCSOC_SEC_RAS_LEAF8_RESPONSE_DROP_EN_MASK                         0x00000100L
+#define GDCSOC_SEC_RAS_RESPONSE_DROP_CTRL__GDCSOC_SEC_RAS_LEAF9_RESPONSE_DROP_EN_MASK                         0x00000200L
+#define GDCSOC_SEC_RAS_RESPONSE_DROP_CTRL__GDCSOC_SEC_RAS_LEAF10_RESPONSE_DROP_EN_MASK                        0x00000400L
+#define GDCSOC_SEC_RAS_RESPONSE_DROP_CTRL__GDCSOC_SEC_RAS_LEAF11_RESPONSE_DROP_EN_MASK                        0x00000800L
+#define GDCSOC_SEC_RAS_RESPONSE_DROP_CTRL__GDCSOC_SEC_RAS_LEAF12_RESPONSE_DROP_EN_MASK                        0x00001000L
+#define GDCSOC_SEC_RAS_RESPONSE_DROP_CTRL__GDCSOC_SEC_RAS_LEAF13_RESPONSE_DROP_EN_MASK                        0x00002000L
+//GDCSOC_SEC_RAS_LEAF0_RRESP_POISON_CTRL
+#define GDCSOC_SEC_RAS_LEAF0_RRESP_POISON_CTRL__GDCSOC_SEC_RAS_LEAF0_RRESP_POISON_EN__SHIFT                   0x0
+#define GDCSOC_SEC_RAS_LEAF0_RRESP_POISON_CTRL__GDCSOC_SEC_RAS_LEAF0_RRESP_POISON_EN_MASK                     0x000000FFL
+//GDCSOC_SEC_RAS_LEAF0_RUSER_POISON_CTRL
+#define GDCSOC_SEC_RAS_LEAF0_RUSER_POISON_CTRL__GDCSOC_SEC_RAS_LEAF0_RUSER_POISON_EN__SHIFT                   0x0
+#define GDCSOC_SEC_RAS_LEAF0_RUSER_POISON_CTRL__GDCSOC_SEC_RAS_LEAF0_RUSER_POISON_EN_MASK                     0x000000FFL
+//GDCSOC_SEC_RAS_LEAF1_RRESP_POISON_CTRL
+#define GDCSOC_SEC_RAS_LEAF1_RRESP_POISON_CTRL__GDCSOC_SEC_RAS_LEAF1_RRESP_POISON_EN__SHIFT                   0x0
+#define GDCSOC_SEC_RAS_LEAF1_RRESP_POISON_CTRL__GDCSOC_SEC_RAS_LEAF1_RRESP_POISON_EN_MASK                     0x000000FFL
+//GDCSOC_SEC_RAS_LEAF1_RUSER_POISON_CTRL
+#define GDCSOC_SEC_RAS_LEAF1_RUSER_POISON_CTRL__GDCSOC_SEC_RAS_LEAF1_RUSER_POISON_EN__SHIFT                   0x0
+#define GDCSOC_SEC_RAS_LEAF1_RUSER_POISON_CTRL__GDCSOC_SEC_RAS_LEAF1_RUSER_POISON_EN_MASK                     0x000000FFL
+//GDCSOC_SEC_RAS_LEAF2_RRESP_POISON_CTRL
+#define GDCSOC_SEC_RAS_LEAF2_RRESP_POISON_CTRL__GDCSOC_SEC_RAS_LEAF2_RRESP_POISON_EN__SHIFT                   0x0
+#define GDCSOC_SEC_RAS_LEAF2_RRESP_POISON_CTRL__GDCSOC_SEC_RAS_LEAF2_RRESP_POISON_EN_MASK                     0x000000FFL
+//GDCSOC_SEC_RAS_LEAF2_RUSER_POISON_CTRL
+#define GDCSOC_SEC_RAS_LEAF2_RUSER_POISON_CTRL__GDCSOC_SEC_RAS_LEAF2_RUSER_POISON_EN__SHIFT                   0x0
+#define GDCSOC_SEC_RAS_LEAF2_RUSER_POISON_CTRL__GDCSOC_SEC_RAS_LEAF2_RUSER_POISON_EN_MASK                     0x000000FFL
+//GDCSOC_SEC_RAS_LEAF3_RRESP_POISON_CTRL
+#define GDCSOC_SEC_RAS_LEAF3_RRESP_POISON_CTRL__GDCSOC_SEC_RAS_LEAF3_RRESP_POISON_EN__SHIFT                   0x0
+#define GDCSOC_SEC_RAS_LEAF3_RRESP_POISON_CTRL__GDCSOC_SEC_RAS_LEAF3_RRESP_POISON_EN_MASK                     0x000000FFL
+//GDCSOC_SEC_RAS_LEAF3_RUSER_POISON_CTRL
+#define GDCSOC_SEC_RAS_LEAF3_RUSER_POISON_CTRL__GDCSOC_SEC_RAS_LEAF3_RUSER_POISON_EN__SHIFT                   0x0
+#define GDCSOC_SEC_RAS_LEAF3_RUSER_POISON_CTRL__GDCSOC_SEC_RAS_LEAF3_RUSER_POISON_EN_MASK                     0x000000FFL
+//GDCSOC_SEC_RAS_LEAF4_RRESP_POISON_CTRL
+#define GDCSOC_SEC_RAS_LEAF4_RRESP_POISON_CTRL__GDCSOC_SEC_RAS_LEAF4_RRESP_POISON_EN__SHIFT                   0x0
+#define GDCSOC_SEC_RAS_LEAF4_RRESP_POISON_CTRL__GDCSOC_SEC_RAS_LEAF4_RRESP_POISON_EN_MASK                     0x000000FFL
+//GDCSOC_SEC_RAS_LEAF4_RUSER_POISON_CTRL
+#define GDCSOC_SEC_RAS_LEAF4_RUSER_POISON_CTRL__GDCSOC_SEC_RAS_LEAF4_RUSER_POISON_EN__SHIFT                   0x0
+#define GDCSOC_SEC_RAS_LEAF4_RUSER_POISON_CTRL__GDCSOC_SEC_RAS_LEAF4_RUSER_POISON_EN_MASK                     0x000000FFL
+//GDCSOC_SEC_RAS_LEAF5_RRESP_POISON_CTRL
+#define GDCSOC_SEC_RAS_LEAF5_RRESP_POISON_CTRL__GDCSOC_SEC_RAS_LEAF5_RRESP_POISON_EN__SHIFT                   0x0
+#define GDCSOC_SEC_RAS_LEAF5_RRESP_POISON_CTRL__GDCSOC_SEC_RAS_LEAF5_RRESP_POISON_EN_MASK                     0x000000FFL
+//GDCSOC_SEC_RAS_LEAF5_RUSER_POISON_CTRL
+#define GDCSOC_SEC_RAS_LEAF5_RUSER_POISON_CTRL__GDCSOC_SEC_RAS_LEAF5_RUSER_POISON_EN__SHIFT                   0x0
+#define GDCSOC_SEC_RAS_LEAF5_RUSER_POISON_CTRL__GDCSOC_SEC_RAS_LEAF5_RUSER_POISON_EN_MASK                     0x000000FFL
+//GDCSOC_SEC_RAS_LEAF6_RRESP_POISON_CTRL
+#define GDCSOC_SEC_RAS_LEAF6_RRESP_POISON_CTRL__GDCSOC_SEC_RAS_LEAF6_RRESP_POISON_EN__SHIFT                   0x0
+#define GDCSOC_SEC_RAS_LEAF6_RRESP_POISON_CTRL__GDCSOC_SEC_RAS_LEAF6_RRESP_POISON_EN_MASK                     0x000000FFL
+//GDCSOC_SEC_RAS_LEAF6_RUSER_POISON_CTRL
+#define GDCSOC_SEC_RAS_LEAF6_RUSER_POISON_CTRL__GDCSOC_SEC_RAS_LEAF6_RUSER_POISON_EN__SHIFT                   0x0
+#define GDCSOC_SEC_RAS_LEAF6_RUSER_POISON_CTRL__GDCSOC_SEC_RAS_LEAF6_RUSER_POISON_EN_MASK                     0x000000FFL
+//GDCSOC_SEC_RAS_LEAF7_RRESP_POISON_CTRL
+#define GDCSOC_SEC_RAS_LEAF7_RRESP_POISON_CTRL__GDCSOC_SEC_RAS_LEAF7_RRESP_POISON_EN__SHIFT                   0x0
+#define GDCSOC_SEC_RAS_LEAF7_RRESP_POISON_CTRL__GDCSOC_SEC_RAS_LEAF7_RRESP_POISON_EN_MASK                     0x000000FFL
+//GDCSOC_SEC_RAS_LEAF7_RUSER_POISON_CTRL
+#define GDCSOC_SEC_RAS_LEAF7_RUSER_POISON_CTRL__GDCSOC_SEC_RAS_LEAF7_RUSER_POISON_EN__SHIFT                   0x0
+#define GDCSOC_SEC_RAS_LEAF7_RUSER_POISON_CTRL__GDCSOC_SEC_RAS_LEAF7_RUSER_POISON_EN_MASK                     0x000000FFL
+//GDCSOC_SEC_RAS_LEAF8_RRESP_POISON_CTRL
+#define GDCSOC_SEC_RAS_LEAF8_RRESP_POISON_CTRL__GDCSOC_SEC_RAS_LEAF8_RRESP_POISON_EN__SHIFT                   0x0
+#define GDCSOC_SEC_RAS_LEAF8_RRESP_POISON_CTRL__GDCSOC_SEC_RAS_LEAF8_RRESP_POISON_EN_MASK                     0x000000FFL
+//GDCSOC_SEC_RAS_LEAF8_RUSER_POISON_CTRL
+#define GDCSOC_SEC_RAS_LEAF8_RUSER_POISON_CTRL__GDCSOC_SEC_RAS_LEAF8_RUSER_POISON_EN__SHIFT                   0x0
+#define GDCSOC_SEC_RAS_LEAF8_RUSER_POISON_CTRL__GDCSOC_SEC_RAS_LEAF8_RUSER_POISON_EN_MASK                     0x000000FFL
+//GDCSOC_SEC_RAS_LEAF9_RRESP_POISON_CTRL
+#define GDCSOC_SEC_RAS_LEAF9_RRESP_POISON_CTRL__GDCSOC_SEC_RAS_LEAF9_RRESP_POISON_EN__SHIFT                   0x0
+#define GDCSOC_SEC_RAS_LEAF9_RRESP_POISON_CTRL__GDCSOC_SEC_RAS_LEAF9_RRESP_POISON_EN_MASK                     0x000000FFL
+//GDCSOC_SEC_RAS_LEAF9_RUSER_POISON_CTRL
+#define GDCSOC_SEC_RAS_LEAF9_RUSER_POISON_CTRL__GDCSOC_SEC_RAS_LEAF9_RUSER_POISON_EN__SHIFT                   0x0
+#define GDCSOC_SEC_RAS_LEAF9_RUSER_POISON_CTRL__GDCSOC_SEC_RAS_LEAF9_RUSER_POISON_EN_MASK                     0x000000FFL
+//GDCSOC_SEC_RAS_LEAF10_RRESP_POISON_CTRL
+#define GDCSOC_SEC_RAS_LEAF10_RRESP_POISON_CTRL__GDCSOC_SEC_RAS_LEAF10_RRESP_POISON_EN__SHIFT                 0x0
+#define GDCSOC_SEC_RAS_LEAF10_RRESP_POISON_CTRL__GDCSOC_SEC_RAS_LEAF10_RRESP_POISON_EN_MASK                   0x000000FFL
+//GDCSOC_SEC_RAS_LEAF10_RUSER_POISON_CTRL
+#define GDCSOC_SEC_RAS_LEAF10_RUSER_POISON_CTRL__GDCSOC_SEC_RAS_LEAF10_RUSER_POISON_EN__SHIFT                 0x0
+#define GDCSOC_SEC_RAS_LEAF10_RUSER_POISON_CTRL__GDCSOC_SEC_RAS_LEAF10_RUSER_POISON_EN_MASK                   0x000000FFL
+//GDCSOC_SEC_RAS_LEAF11_RRESP_POISON_CTRL
+#define GDCSOC_SEC_RAS_LEAF11_RRESP_POISON_CTRL__GDCSOC_SEC_RAS_LEAF11_RRESP_POISON_EN__SHIFT                 0x0
+#define GDCSOC_SEC_RAS_LEAF11_RRESP_POISON_CTRL__GDCSOC_SEC_RAS_LEAF11_RRESP_POISON_EN_MASK                   0x000000FFL
+//GDCSOC_SEC_RAS_LEAF11_RUSER_POISON_CTRL
+#define GDCSOC_SEC_RAS_LEAF11_RUSER_POISON_CTRL__GDCSOC_SEC_RAS_LEAF11_RUSER_POISON_EN__SHIFT                 0x0
+#define GDCSOC_SEC_RAS_LEAF11_RUSER_POISON_CTRL__GDCSOC_SEC_RAS_LEAF11_RUSER_POISON_EN_MASK                   0x000000FFL
+//GDCSOC_SEC_RAS_LEAF12_RRESP_POISON_CTRL
+#define GDCSOC_SEC_RAS_LEAF12_RRESP_POISON_CTRL__GDCSOC_SEC_RAS_LEAF12_RRESP_POISON_EN__SHIFT                 0x0
+#define GDCSOC_SEC_RAS_LEAF12_RRESP_POISON_CTRL__GDCSOC_SEC_RAS_LEAF12_RRESP_POISON_EN_MASK                   0x000000FFL
+//GDCSOC_SEC_RAS_LEAF12_RUSER_POISON_CTRL
+#define GDCSOC_SEC_RAS_LEAF12_RUSER_POISON_CTRL__GDCSOC_SEC_RAS_LEAF12_RUSER_POISON_EN__SHIFT                 0x0
+#define GDCSOC_SEC_RAS_LEAF12_RUSER_POISON_CTRL__GDCSOC_SEC_RAS_LEAF12_RUSER_POISON_EN_MASK                   0x000000FFL
+//GDCSOC_SEC_RAS_LEAF13_RRESP_POISON_CTRL
+#define GDCSOC_SEC_RAS_LEAF13_RRESP_POISON_CTRL__GDCSOC_SEC_RAS_LEAF13_RRESP_POISON_EN__SHIFT                 0x0
+#define GDCSOC_SEC_RAS_LEAF13_RRESP_POISON_CTRL__GDCSOC_SEC_RAS_LEAF13_RRESP_POISON_EN_MASK                   0x000000FFL
+//GDCSOC_SEC_RAS_LEAF13_RUSER_POISON_CTRL
+#define GDCSOC_SEC_RAS_LEAF13_RUSER_POISON_CTRL__GDCSOC_SEC_RAS_LEAF13_RUSER_POISON_EN__SHIFT                 0x0
+#define GDCSOC_SEC_RAS_LEAF13_RUSER_POISON_CTRL__GDCSOC_SEC_RAS_LEAF13_RUSER_POISON_EN_MASK                   0x000000FFL
+
+
+// addressBlock: nbif0_nbif0_gdc_a2s_GDCA2S_DEC
+//A2S_CNTL_SW0
+#define A2S_CNTL_SW0__STATIC_VC_ENABLE__SHIFT                                                                 0x0
+#define A2S_CNTL_SW0__STATIC_VC_VALUE__SHIFT                                                                  0x1
+#define A2S_CNTL_SW0__SDP_WR_CHAIN_DIS__SHIFT                                                                 0x9
+#define A2S_CNTL_SW0__WR_TAG_FOR_CHAIN_ENABLE__SHIFT                                                          0xa
+#define A2S_CNTL_SW0__WR_TAG_FOR_NONCHAIN_ENABLE__SHIFT                                                       0xb
+#define A2S_CNTL_SW0__SDP_DYNAMIC_VC_WR_CHAIN_DIS__SHIFT                                                      0xc
+#define A2S_CNTL_SW0__WRR_RD_WEIGHT__SHIFT                                                                    0x10
+#define A2S_CNTL_SW0__WRR_WR_WEIGHT__SHIFT                                                                    0x18
+#define A2S_CNTL_SW0__STATIC_VC_ENABLE_MASK                                                                   0x00000001L
+#define A2S_CNTL_SW0__STATIC_VC_VALUE_MASK                                                                    0x0000000EL
+#define A2S_CNTL_SW0__SDP_WR_CHAIN_DIS_MASK                                                                   0x00000200L
+#define A2S_CNTL_SW0__WR_TAG_FOR_CHAIN_ENABLE_MASK                                                            0x00000400L
+#define A2S_CNTL_SW0__WR_TAG_FOR_NONCHAIN_ENABLE_MASK                                                         0x00000800L
+#define A2S_CNTL_SW0__SDP_DYNAMIC_VC_WR_CHAIN_DIS_MASK                                                        0x00001000L
+#define A2S_CNTL_SW0__WRR_RD_WEIGHT_MASK                                                                      0x00FF0000L
+#define A2S_CNTL_SW0__WRR_WR_WEIGHT_MASK                                                                      0xFF000000L
+//A2S_CNTL_SW1
+#define A2S_CNTL_SW1__STATIC_VC_ENABLE__SHIFT                                                                 0x0
+#define A2S_CNTL_SW1__STATIC_VC_VALUE__SHIFT                                                                  0x1
+#define A2S_CNTL_SW1__SDP_WR_CHAIN_DIS__SHIFT                                                                 0x9
+#define A2S_CNTL_SW1__WR_TAG_FOR_CHAIN_ENABLE__SHIFT                                                          0xa
+#define A2S_CNTL_SW1__WR_TAG_FOR_NONCHAIN_ENABLE__SHIFT                                                       0xb
+#define A2S_CNTL_SW1__SDP_DYNAMIC_VC_WR_CHAIN_DIS__SHIFT                                                      0xc
+#define A2S_CNTL_SW1__WRR_RD_WEIGHT__SHIFT                                                                    0x10
+#define A2S_CNTL_SW1__WRR_WR_WEIGHT__SHIFT                                                                    0x18
+#define A2S_CNTL_SW1__STATIC_VC_ENABLE_MASK                                                                   0x00000001L
+#define A2S_CNTL_SW1__STATIC_VC_VALUE_MASK                                                                    0x0000000EL
+#define A2S_CNTL_SW1__SDP_WR_CHAIN_DIS_MASK                                                                   0x00000200L
+#define A2S_CNTL_SW1__WR_TAG_FOR_CHAIN_ENABLE_MASK                                                            0x00000400L
+#define A2S_CNTL_SW1__WR_TAG_FOR_NONCHAIN_ENABLE_MASK                                                         0x00000800L
+#define A2S_CNTL_SW1__SDP_DYNAMIC_VC_WR_CHAIN_DIS_MASK                                                        0x00001000L
+#define A2S_CNTL_SW1__WRR_RD_WEIGHT_MASK                                                                      0x00FF0000L
+#define A2S_CNTL_SW1__WRR_WR_WEIGHT_MASK                                                                      0xFF000000L
+//A2S_CNTL_SW2
+#define A2S_CNTL_SW2__STATIC_VC_ENABLE__SHIFT                                                                 0x0
+#define A2S_CNTL_SW2__STATIC_VC_VALUE__SHIFT                                                                  0x1
+#define A2S_CNTL_SW2__SDP_WR_CHAIN_DIS__SHIFT                                                                 0x9
+#define A2S_CNTL_SW2__WR_TAG_FOR_CHAIN_ENABLE__SHIFT                                                          0xa
+#define A2S_CNTL_SW2__WR_TAG_FOR_NONCHAIN_ENABLE__SHIFT                                                       0xb
+#define A2S_CNTL_SW2__SDP_DYNAMIC_VC_WR_CHAIN_DIS__SHIFT                                                      0xc
+#define A2S_CNTL_SW2__WRR_RD_WEIGHT__SHIFT                                                                    0x10
+#define A2S_CNTL_SW2__WRR_WR_WEIGHT__SHIFT                                                                    0x18
+#define A2S_CNTL_SW2__STATIC_VC_ENABLE_MASK                                                                   0x00000001L
+#define A2S_CNTL_SW2__STATIC_VC_VALUE_MASK                                                                    0x0000000EL
+#define A2S_CNTL_SW2__SDP_WR_CHAIN_DIS_MASK                                                                   0x00000200L
+#define A2S_CNTL_SW2__WR_TAG_FOR_CHAIN_ENABLE_MASK                                                            0x00000400L
+#define A2S_CNTL_SW2__WR_TAG_FOR_NONCHAIN_ENABLE_MASK                                                         0x00000800L
+#define A2S_CNTL_SW2__SDP_DYNAMIC_VC_WR_CHAIN_DIS_MASK                                                        0x00001000L
+#define A2S_CNTL_SW2__WRR_RD_WEIGHT_MASK                                                                      0x00FF0000L
+#define A2S_CNTL_SW2__WRR_WR_WEIGHT_MASK                                                                      0xFF000000L
+//A2S_CNTL_SW3
+#define A2S_CNTL_SW3__STATIC_VC_ENABLE__SHIFT                                                                 0x0
+#define A2S_CNTL_SW3__STATIC_VC_VALUE__SHIFT                                                                  0x1
+#define A2S_CNTL_SW3__SDP_WR_CHAIN_DIS__SHIFT                                                                 0x9
+#define A2S_CNTL_SW3__WR_TAG_FOR_CHAIN_ENABLE__SHIFT                                                          0xa
+#define A2S_CNTL_SW3__WR_TAG_FOR_NONCHAIN_ENABLE__SHIFT                                                       0xb
+#define A2S_CNTL_SW3__SDP_DYNAMIC_VC_WR_CHAIN_DIS__SHIFT                                                      0xc
+#define A2S_CNTL_SW3__WRR_RD_WEIGHT__SHIFT                                                                    0x10
+#define A2S_CNTL_SW3__WRR_WR_WEIGHT__SHIFT                                                                    0x18
+#define A2S_CNTL_SW3__STATIC_VC_ENABLE_MASK                                                                   0x00000001L
+#define A2S_CNTL_SW3__STATIC_VC_VALUE_MASK                                                                    0x0000000EL
+#define A2S_CNTL_SW3__SDP_WR_CHAIN_DIS_MASK                                                                   0x00000200L
+#define A2S_CNTL_SW3__WR_TAG_FOR_CHAIN_ENABLE_MASK                                                            0x00000400L
+#define A2S_CNTL_SW3__WR_TAG_FOR_NONCHAIN_ENABLE_MASK                                                         0x00000800L
+#define A2S_CNTL_SW3__SDP_DYNAMIC_VC_WR_CHAIN_DIS_MASK                                                        0x00001000L
+#define A2S_CNTL_SW3__WRR_RD_WEIGHT_MASK                                                                      0x00FF0000L
+#define A2S_CNTL_SW3__WRR_WR_WEIGHT_MASK                                                                      0xFF000000L
+//A2S_CNTL_SW4
+#define A2S_CNTL_SW4__STATIC_VC_ENABLE__SHIFT                                                                 0x0
+#define A2S_CNTL_SW4__STATIC_VC_VALUE__SHIFT                                                                  0x1
+#define A2S_CNTL_SW4__SDP_WR_CHAIN_DIS__SHIFT                                                                 0x9
+#define A2S_CNTL_SW4__WR_TAG_FOR_CHAIN_ENABLE__SHIFT                                                          0xa
+#define A2S_CNTL_SW4__WR_TAG_FOR_NONCHAIN_ENABLE__SHIFT                                                       0xb
+#define A2S_CNTL_SW4__SDP_DYNAMIC_VC_WR_CHAIN_DIS__SHIFT                                                      0xc
+#define A2S_CNTL_SW4__WRR_RD_WEIGHT__SHIFT                                                                    0x10
+#define A2S_CNTL_SW4__WRR_WR_WEIGHT__SHIFT                                                                    0x18
+#define A2S_CNTL_SW4__STATIC_VC_ENABLE_MASK                                                                   0x00000001L
+#define A2S_CNTL_SW4__STATIC_VC_VALUE_MASK                                                                    0x0000000EL
+#define A2S_CNTL_SW4__SDP_WR_CHAIN_DIS_MASK                                                                   0x00000200L
+#define A2S_CNTL_SW4__WR_TAG_FOR_CHAIN_ENABLE_MASK                                                            0x00000400L
+#define A2S_CNTL_SW4__WR_TAG_FOR_NONCHAIN_ENABLE_MASK                                                         0x00000800L
+#define A2S_CNTL_SW4__SDP_DYNAMIC_VC_WR_CHAIN_DIS_MASK                                                        0x00001000L
+#define A2S_CNTL_SW4__WRR_RD_WEIGHT_MASK                                                                      0x00FF0000L
+#define A2S_CNTL_SW4__WRR_WR_WEIGHT_MASK                                                                      0xFF000000L
+//A2S_CNTL_SW5
+#define A2S_CNTL_SW5__STATIC_VC_ENABLE__SHIFT                                                                 0x0
+#define A2S_CNTL_SW5__STATIC_VC_VALUE__SHIFT                                                                  0x1
+#define A2S_CNTL_SW5__SDP_WR_CHAIN_DIS__SHIFT                                                                 0x9
+#define A2S_CNTL_SW5__WR_TAG_FOR_CHAIN_ENABLE__SHIFT                                                          0xa
+#define A2S_CNTL_SW5__WR_TAG_FOR_NONCHAIN_ENABLE__SHIFT                                                       0xb
+#define A2S_CNTL_SW5__SDP_DYNAMIC_VC_WR_CHAIN_DIS__SHIFT                                                      0xc
+#define A2S_CNTL_SW5__WRR_RD_WEIGHT__SHIFT                                                                    0x10
+#define A2S_CNTL_SW5__WRR_WR_WEIGHT__SHIFT                                                                    0x18
+#define A2S_CNTL_SW5__STATIC_VC_ENABLE_MASK                                                                   0x00000001L
+#define A2S_CNTL_SW5__STATIC_VC_VALUE_MASK                                                                    0x0000000EL
+#define A2S_CNTL_SW5__SDP_WR_CHAIN_DIS_MASK                                                                   0x00000200L
+#define A2S_CNTL_SW5__WR_TAG_FOR_CHAIN_ENABLE_MASK                                                            0x00000400L
+#define A2S_CNTL_SW5__WR_TAG_FOR_NONCHAIN_ENABLE_MASK                                                         0x00000800L
+#define A2S_CNTL_SW5__SDP_DYNAMIC_VC_WR_CHAIN_DIS_MASK                                                        0x00001000L
+#define A2S_CNTL_SW5__WRR_RD_WEIGHT_MASK                                                                      0x00FF0000L
+#define A2S_CNTL_SW5__WRR_WR_WEIGHT_MASK                                                                      0xFF000000L
+//A2S_CNTL_2_SW0
+#define A2S_CNTL_2_SW0__SDP_LARGE_WR_CHAIN_DIS__SHIFT                                                         0x0
+#define A2S_CNTL_2_SW0__SDP_LARGE_WR_CHAIN_DIS_MASK                                                           0x00000001L
+//A2S_CNTL_2_SW1
+#define A2S_CNTL_2_SW1__SDP_LARGE_WR_CHAIN_DIS__SHIFT                                                         0x0
+#define A2S_CNTL_2_SW1__SDP_LARGE_WR_CHAIN_DIS_MASK                                                           0x00000001L
+//A2S_CNTL_2_SW2
+#define A2S_CNTL_2_SW2__SDP_LARGE_WR_CHAIN_DIS__SHIFT                                                         0x0
+#define A2S_CNTL_2_SW2__SDP_LARGE_WR_CHAIN_DIS_MASK                                                           0x00000001L
+//A2S_CNTL_2_SW3
+#define A2S_CNTL_2_SW3__SDP_LARGE_WR_CHAIN_DIS__SHIFT                                                         0x0
+#define A2S_CNTL_2_SW3__SDP_LARGE_WR_CHAIN_DIS_MASK                                                           0x00000001L
+//A2S_CNTL_2_SW4
+#define A2S_CNTL_2_SW4__SDP_LARGE_WR_CHAIN_DIS__SHIFT                                                         0x0
+#define A2S_CNTL_2_SW4__SDP_LARGE_WR_CHAIN_DIS_MASK                                                           0x00000001L
+//A2S_CNTL_2_SW5
+#define A2S_CNTL_2_SW5__SDP_LARGE_WR_CHAIN_DIS__SHIFT                                                         0x0
+#define A2S_CNTL_2_SW5__SDP_LARGE_WR_CHAIN_DIS_MASK                                                           0x00000001L
+//A2S_WRSIZEFULL_SUPPORT_DISABLE
+#define A2S_WRSIZEFULL_SUPPORT_DISABLE__SHUB_A2S_WRSIZEFULL_SUPPORT_DISABLE__SHIFT                            0x0
+#define A2S_WRSIZEFULL_SUPPORT_DISABLE__SHUB_A2S_WRSIZEFULL_SUPPORT_DISABLE_MASK                              0x00000001L
+//ROUTING_TABLE_CNTL
+#define ROUTING_TABLE_CNTL__TABLE_INDEX__SHIFT                                                                0x0
+#define ROUTING_TABLE_CNTL__TABLE_INDEX_MASK                                                                  0x0000FFFFL
+//ROUTING_TABLE_DATA0
+#define ROUTING_TABLE_DATA0__TABLE_DATA0__SHIFT                                                               0x0
+#define ROUTING_TABLE_DATA0__TABLE_DATA0_MASK                                                                 0xFFFFFFFFL
+//A2S_ARB_CONTROL_FOR_VC0
+#define A2S_ARB_CONTROL_FOR_VC0__VC_RD_WEIGHT__SHIFT                                                          0x0
+#define A2S_ARB_CONTROL_FOR_VC0__VC_WR_WEIGHT__SHIFT                                                          0x8
+#define A2S_ARB_CONTROL_FOR_VC0__VC_RW_WEIGHT__SHIFT                                                          0x10
+#define A2S_ARB_CONTROL_FOR_VC0__VC_LRG_MODE_RW__SHIFT                                                        0x18
+#define A2S_ARB_CONTROL_FOR_VC0__VC_LRG_SIZE_MODE_RW__SHIFT                                                   0x19
+#define A2S_ARB_CONTROL_FOR_VC0__VC_LRG_COUNTER_MODE_RW__SHIFT                                                0x1a
+#define A2S_ARB_CONTROL_FOR_VC0__VC_RD_WEIGHT_MASK                                                            0x000000FFL
+#define A2S_ARB_CONTROL_FOR_VC0__VC_WR_WEIGHT_MASK                                                            0x0000FF00L
+#define A2S_ARB_CONTROL_FOR_VC0__VC_RW_WEIGHT_MASK                                                            0x00FF0000L
+#define A2S_ARB_CONTROL_FOR_VC0__VC_LRG_MODE_RW_MASK                                                          0x01000000L
+#define A2S_ARB_CONTROL_FOR_VC0__VC_LRG_SIZE_MODE_RW_MASK                                                     0x02000000L
+#define A2S_ARB_CONTROL_FOR_VC0__VC_LRG_COUNTER_MODE_RW_MASK                                                  0x04000000L
+//A2S_ARB_CONTROL_FOR_VC1
+#define A2S_ARB_CONTROL_FOR_VC1__VC_RD_WEIGHT__SHIFT                                                          0x0
+#define A2S_ARB_CONTROL_FOR_VC1__VC_WR_WEIGHT__SHIFT                                                          0x8
+#define A2S_ARB_CONTROL_FOR_VC1__VC_RW_WEIGHT__SHIFT                                                          0x10
+#define A2S_ARB_CONTROL_FOR_VC1__VC_LRG_MODE_RW__SHIFT                                                        0x18
+#define A2S_ARB_CONTROL_FOR_VC1__VC_LRG_SIZE_MODE_RW__SHIFT                                                   0x19
+#define A2S_ARB_CONTROL_FOR_VC1__VC_LRG_COUNTER_MODE_RW__SHIFT                                                0x1a
+#define A2S_ARB_CONTROL_FOR_VC1__VC_RD_WEIGHT_MASK                                                            0x000000FFL
+#define A2S_ARB_CONTROL_FOR_VC1__VC_WR_WEIGHT_MASK                                                            0x0000FF00L
+#define A2S_ARB_CONTROL_FOR_VC1__VC_RW_WEIGHT_MASK                                                            0x00FF0000L
+#define A2S_ARB_CONTROL_FOR_VC1__VC_LRG_MODE_RW_MASK                                                          0x01000000L
+#define A2S_ARB_CONTROL_FOR_VC1__VC_LRG_SIZE_MODE_RW_MASK                                                     0x02000000L
+#define A2S_ARB_CONTROL_FOR_VC1__VC_LRG_COUNTER_MODE_RW_MASK                                                  0x04000000L
+//A2S_ARB_CONTROL_FOR_VC2
+#define A2S_ARB_CONTROL_FOR_VC2__VC_RD_WEIGHT__SHIFT                                                          0x0
+#define A2S_ARB_CONTROL_FOR_VC2__VC_WR_WEIGHT__SHIFT                                                          0x8
+#define A2S_ARB_CONTROL_FOR_VC2__VC_RW_WEIGHT__SHIFT                                                          0x10
+#define A2S_ARB_CONTROL_FOR_VC2__VC_LRG_MODE_RW__SHIFT                                                        0x18
+#define A2S_ARB_CONTROL_FOR_VC2__VC_LRG_SIZE_MODE_RW__SHIFT                                                   0x19
+#define A2S_ARB_CONTROL_FOR_VC2__VC_LRG_COUNTER_MODE_RW__SHIFT                                                0x1a
+#define A2S_ARB_CONTROL_FOR_VC2__VC_RD_WEIGHT_MASK                                                            0x000000FFL
+#define A2S_ARB_CONTROL_FOR_VC2__VC_WR_WEIGHT_MASK                                                            0x0000FF00L
+#define A2S_ARB_CONTROL_FOR_VC2__VC_RW_WEIGHT_MASK                                                            0x00FF0000L
+#define A2S_ARB_CONTROL_FOR_VC2__VC_LRG_MODE_RW_MASK                                                          0x01000000L
+#define A2S_ARB_CONTROL_FOR_VC2__VC_LRG_SIZE_MODE_RW_MASK                                                     0x02000000L
+#define A2S_ARB_CONTROL_FOR_VC2__VC_LRG_COUNTER_MODE_RW_MASK                                                  0x04000000L
+//A2S_ARB_CONTROL_FOR_VC3
+#define A2S_ARB_CONTROL_FOR_VC3__VC_RD_WEIGHT__SHIFT                                                          0x0
+#define A2S_ARB_CONTROL_FOR_VC3__VC_WR_WEIGHT__SHIFT                                                          0x8
+#define A2S_ARB_CONTROL_FOR_VC3__VC_RW_WEIGHT__SHIFT                                                          0x10
+#define A2S_ARB_CONTROL_FOR_VC3__VC_LRG_MODE_RW__SHIFT                                                        0x18
+#define A2S_ARB_CONTROL_FOR_VC3__VC_LRG_SIZE_MODE_RW__SHIFT                                                   0x19
+#define A2S_ARB_CONTROL_FOR_VC3__VC_LRG_COUNTER_MODE_RW__SHIFT                                                0x1a
+#define A2S_ARB_CONTROL_FOR_VC3__VC_RD_WEIGHT_MASK                                                            0x000000FFL
+#define A2S_ARB_CONTROL_FOR_VC3__VC_WR_WEIGHT_MASK                                                            0x0000FF00L
+#define A2S_ARB_CONTROL_FOR_VC3__VC_RW_WEIGHT_MASK                                                            0x00FF0000L
+#define A2S_ARB_CONTROL_FOR_VC3__VC_LRG_MODE_RW_MASK                                                          0x01000000L
+#define A2S_ARB_CONTROL_FOR_VC3__VC_LRG_SIZE_MODE_RW_MASK                                                     0x02000000L
+#define A2S_ARB_CONTROL_FOR_VC3__VC_LRG_COUNTER_MODE_RW_MASK                                                  0x04000000L
+//A2S_ARB_CONTROL_FOR_VC4
+#define A2S_ARB_CONTROL_FOR_VC4__VC_RD_WEIGHT__SHIFT                                                          0x0
+#define A2S_ARB_CONTROL_FOR_VC4__VC_WR_WEIGHT__SHIFT                                                          0x8
+#define A2S_ARB_CONTROL_FOR_VC4__VC_RW_WEIGHT__SHIFT                                                          0x10
+#define A2S_ARB_CONTROL_FOR_VC4__VC_LRG_MODE_RW__SHIFT                                                        0x18
+#define A2S_ARB_CONTROL_FOR_VC4__VC_LRG_SIZE_MODE_RW__SHIFT                                                   0x19
+#define A2S_ARB_CONTROL_FOR_VC4__VC_LRG_COUNTER_MODE_RW__SHIFT                                                0x1a
+#define A2S_ARB_CONTROL_FOR_VC4__VC_RD_WEIGHT_MASK                                                            0x000000FFL
+#define A2S_ARB_CONTROL_FOR_VC4__VC_WR_WEIGHT_MASK                                                            0x0000FF00L
+#define A2S_ARB_CONTROL_FOR_VC4__VC_RW_WEIGHT_MASK                                                            0x00FF0000L
+#define A2S_ARB_CONTROL_FOR_VC4__VC_LRG_MODE_RW_MASK                                                          0x01000000L
+#define A2S_ARB_CONTROL_FOR_VC4__VC_LRG_SIZE_MODE_RW_MASK                                                     0x02000000L
+#define A2S_ARB_CONTROL_FOR_VC4__VC_LRG_COUNTER_MODE_RW_MASK                                                  0x04000000L
+//A2S_ARB_CONTROL_FOR_VC5
+#define A2S_ARB_CONTROL_FOR_VC5__VC_RD_WEIGHT__SHIFT                                                          0x0
+#define A2S_ARB_CONTROL_FOR_VC5__VC_WR_WEIGHT__SHIFT                                                          0x8
+#define A2S_ARB_CONTROL_FOR_VC5__VC_RW_WEIGHT__SHIFT                                                          0x10
+#define A2S_ARB_CONTROL_FOR_VC5__VC_LRG_MODE_RW__SHIFT                                                        0x18
+#define A2S_ARB_CONTROL_FOR_VC5__VC_LRG_SIZE_MODE_RW__SHIFT                                                   0x19
+#define A2S_ARB_CONTROL_FOR_VC5__VC_LRG_COUNTER_MODE_RW__SHIFT                                                0x1a
+#define A2S_ARB_CONTROL_FOR_VC5__VC_RD_WEIGHT_MASK                                                            0x000000FFL
+#define A2S_ARB_CONTROL_FOR_VC5__VC_WR_WEIGHT_MASK                                                            0x0000FF00L
+#define A2S_ARB_CONTROL_FOR_VC5__VC_RW_WEIGHT_MASK                                                            0x00FF0000L
+#define A2S_ARB_CONTROL_FOR_VC5__VC_LRG_MODE_RW_MASK                                                          0x01000000L
+#define A2S_ARB_CONTROL_FOR_VC5__VC_LRG_SIZE_MODE_RW_MASK                                                     0x02000000L
+#define A2S_ARB_CONTROL_FOR_VC5__VC_LRG_COUNTER_MODE_RW_MASK                                                  0x04000000L
+//A2S_ARB_CONTROL_FOR_VC6
+#define A2S_ARB_CONTROL_FOR_VC6__VC_RD_WEIGHT__SHIFT                                                          0x0
+#define A2S_ARB_CONTROL_FOR_VC6__VC_WR_WEIGHT__SHIFT                                                          0x8
+#define A2S_ARB_CONTROL_FOR_VC6__VC_RW_WEIGHT__SHIFT                                                          0x10
+#define A2S_ARB_CONTROL_FOR_VC6__VC_LRG_MODE_RW__SHIFT                                                        0x18
+#define A2S_ARB_CONTROL_FOR_VC6__VC_LRG_SIZE_MODE_RW__SHIFT                                                   0x19
+#define A2S_ARB_CONTROL_FOR_VC6__VC_LRG_COUNTER_MODE_RW__SHIFT                                                0x1a
+#define A2S_ARB_CONTROL_FOR_VC6__VC_RD_WEIGHT_MASK                                                            0x000000FFL
+#define A2S_ARB_CONTROL_FOR_VC6__VC_WR_WEIGHT_MASK                                                            0x0000FF00L
+#define A2S_ARB_CONTROL_FOR_VC6__VC_RW_WEIGHT_MASK                                                            0x00FF0000L
+#define A2S_ARB_CONTROL_FOR_VC6__VC_LRG_MODE_RW_MASK                                                          0x01000000L
+#define A2S_ARB_CONTROL_FOR_VC6__VC_LRG_SIZE_MODE_RW_MASK                                                     0x02000000L
+#define A2S_ARB_CONTROL_FOR_VC6__VC_LRG_COUNTER_MODE_RW_MASK                                                  0x04000000L
+//A2S_ARB_CONTROL_FOR_VC7
+#define A2S_ARB_CONTROL_FOR_VC7__VC_RD_WEIGHT__SHIFT                                                          0x0
+#define A2S_ARB_CONTROL_FOR_VC7__VC_WR_WEIGHT__SHIFT                                                          0x8
+#define A2S_ARB_CONTROL_FOR_VC7__VC_RW_WEIGHT__SHIFT                                                          0x10
+#define A2S_ARB_CONTROL_FOR_VC7__VC_LRG_MODE_RW__SHIFT                                                        0x18
+#define A2S_ARB_CONTROL_FOR_VC7__VC_LRG_SIZE_MODE_RW__SHIFT                                                   0x19
+#define A2S_ARB_CONTROL_FOR_VC7__VC_LRG_COUNTER_MODE_RW__SHIFT                                                0x1a
+#define A2S_ARB_CONTROL_FOR_VC7__VC_RD_WEIGHT_MASK                                                            0x000000FFL
+#define A2S_ARB_CONTROL_FOR_VC7__VC_WR_WEIGHT_MASK                                                            0x0000FF00L
+#define A2S_ARB_CONTROL_FOR_VC7__VC_RW_WEIGHT_MASK                                                            0x00FF0000L
+#define A2S_ARB_CONTROL_FOR_VC7__VC_LRG_MODE_RW_MASK                                                          0x01000000L
+#define A2S_ARB_CONTROL_FOR_VC7__VC_LRG_SIZE_MODE_RW_MASK                                                     0x02000000L
+#define A2S_ARB_CONTROL_FOR_VC7__VC_LRG_COUNTER_MODE_RW_MASK                                                  0x04000000L
+//A2S_RW_ARB_CNTL
+#define A2S_RW_ARB_CNTL__A2S_WRR_WEIGHT_RD__SHIFT                                                             0x0
+#define A2S_RW_ARB_CNTL__A2S_WRR_WEIGHT_WR__SHIFT                                                             0x8
+#define A2S_RW_ARB_CNTL__A2S_LRG_MODE_RW__SHIFT                                                               0x10
+#define A2S_RW_ARB_CNTL__A2S_LRG_SIZE_MODE_RW__SHIFT                                                          0x11
+#define A2S_RW_ARB_CNTL__A2S_LRG_COUNTER_MODE_RW__SHIFT                                                       0x12
+#define A2S_RW_ARB_CNTL__A2S_WRR_WEIGHT_RD_MASK                                                               0x000000FFL
+#define A2S_RW_ARB_CNTL__A2S_WRR_WEIGHT_WR_MASK                                                               0x0000FF00L
+#define A2S_RW_ARB_CNTL__A2S_LRG_MODE_RW_MASK                                                                 0x00010000L
+#define A2S_RW_ARB_CNTL__A2S_LRG_SIZE_MODE_RW_MASK                                                            0x00020000L
+#define A2S_RW_ARB_CNTL__A2S_LRG_COUNTER_MODE_RW_MASK                                                         0x00040000L
+//A2S_REQ_RSP_TAG_CNTL
+#define A2S_REQ_RSP_TAG_CNTL__RD_WRR_LRG_MODE__SHIFT                                                          0x0
+#define A2S_REQ_RSP_TAG_CNTL__RD_WRR_LRG_SIZE_MODE__SHIFT                                                     0x1
+#define A2S_REQ_RSP_TAG_CNTL__RD_WRR_LRG_COUNTER_MODE__SHIFT                                                  0x2
+#define A2S_REQ_RSP_TAG_CNTL__RD_A2S_RSP_ARBMODE__SHIFT                                                       0x3
+#define A2S_REQ_RSP_TAG_CNTL__WR_WRR_LRG_MODE__SHIFT                                                          0x10
+#define A2S_REQ_RSP_TAG_CNTL__WR_WRR_LRG_SIZE_MODE__SHIFT                                                     0x11
+#define A2S_REQ_RSP_TAG_CNTL__WR_WRR_LRG_COUNTER_MODE__SHIFT                                                  0x12
+#define A2S_REQ_RSP_TAG_CNTL__WR_A2S_RSP_ARBMODE__SHIFT                                                       0x13
+#define A2S_REQ_RSP_TAG_CNTL__RD_WRR_LRG_MODE_MASK                                                            0x00000001L
+#define A2S_REQ_RSP_TAG_CNTL__RD_WRR_LRG_SIZE_MODE_MASK                                                       0x00000002L
+#define A2S_REQ_RSP_TAG_CNTL__RD_WRR_LRG_COUNTER_MODE_MASK                                                    0x00000004L
+#define A2S_REQ_RSP_TAG_CNTL__RD_A2S_RSP_ARBMODE_MASK                                                         0x00000008L
+#define A2S_REQ_RSP_TAG_CNTL__WR_WRR_LRG_MODE_MASK                                                            0x00010000L
+#define A2S_REQ_RSP_TAG_CNTL__WR_WRR_LRG_SIZE_MODE_MASK                                                       0x00020000L
+#define A2S_REQ_RSP_TAG_CNTL__WR_WRR_LRG_COUNTER_MODE_MASK                                                    0x00040000L
+#define A2S_REQ_RSP_TAG_CNTL__WR_A2S_RSP_ARBMODE_MASK                                                         0x00080000L
+//A2S_MISC_CNTL
+#define A2S_MISC_CNTL__BLKLVL_FOR_MSG__SHIFT                                                                  0x0
+#define A2S_MISC_CNTL__WRRSP_ACCUM_SEL__SHIFT                                                                 0x6
+#define A2S_MISC_CNTL__BLKLVL_FOR_MSG_MASK                                                                    0x00000003L
+#define A2S_MISC_CNTL__WRRSP_ACCUM_SEL_MASK                                                                   0x00000040L
+//A2S_TAG_ALLOC_0
+#define A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC0_WR__SHIFT                                                          0x0
+#define A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC0_RD__SHIFT                                                          0x8
+#define A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC1_WR__SHIFT                                                          0x10
+#define A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC0_WR_MASK                                                            0x000000FFL
+#define A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC0_RD_MASK                                                            0x0000FF00L
+#define A2S_TAG_ALLOC_0__TAG_ALLOC_FOR_VC1_WR_MASK                                                            0x00FF0000L
+//A2S_TAG_ALLOC_1
+#define A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC3_WR__SHIFT                                                          0x0
+#define A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC7_WR__SHIFT                                                          0x10
+#define A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC7_RD__SHIFT                                                          0x18
+#define A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC3_WR_MASK                                                            0x000000FFL
+#define A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC7_WR_MASK                                                            0x00FF0000L
+#define A2S_TAG_ALLOC_1__TAG_ALLOC_FOR_VC7_RD_MASK                                                            0xFF000000L
+//A2S_TAG_ALLOC_2
+#define A2S_TAG_ALLOC_2__TAG_ALLOC_FOR_VC5_WR__SHIFT                                                          0x0
+#define A2S_TAG_ALLOC_2__TAG_ALLOC_FOR_VC5_RD__SHIFT                                                          0x8
+#define A2S_TAG_ALLOC_2__TAG_ALLOC_FOR_VC6_WR__SHIFT                                                          0x10
+#define A2S_TAG_ALLOC_2__TAG_ALLOC_FOR_VC6_RD__SHIFT                                                          0x18
+#define A2S_TAG_ALLOC_2__TAG_ALLOC_FOR_VC5_WR_MASK                                                            0x000000FFL
+#define A2S_TAG_ALLOC_2__TAG_ALLOC_FOR_VC5_RD_MASK                                                            0x0000FF00L
+#define A2S_TAG_ALLOC_2__TAG_ALLOC_FOR_VC6_WR_MASK                                                            0x00FF0000L
+#define A2S_TAG_ALLOC_2__TAG_ALLOC_FOR_VC6_RD_MASK                                                            0xFF000000L
+//A2S_TAG_ALLOC_3
+#define A2S_TAG_ALLOC_3__TAG_ALLOC_FOR_VC4_WR__SHIFT                                                          0x0
+#define A2S_TAG_ALLOC_3__TAG_ALLOC_FOR_VC4_RD__SHIFT                                                          0x8
+#define A2S_TAG_ALLOC_3__TAG_ALLOC_FOR_VC2_WR__SHIFT                                                          0x10
+#define A2S_TAG_ALLOC_3__TAG_ALLOC_FOR_VC2_RD__SHIFT                                                          0x18
+#define A2S_TAG_ALLOC_3__TAG_ALLOC_FOR_VC4_WR_MASK                                                            0x000000FFL
+#define A2S_TAG_ALLOC_3__TAG_ALLOC_FOR_VC4_RD_MASK                                                            0x0000FF00L
+#define A2S_TAG_ALLOC_3__TAG_ALLOC_FOR_VC2_WR_MASK                                                            0x00FF0000L
+#define A2S_TAG_ALLOC_3__TAG_ALLOC_FOR_VC2_RD_MASK                                                            0xFF000000L
+//SHUB_A2S_TAG_ALLOC_FOR_CHAIN_0
+#define SHUB_A2S_TAG_ALLOC_FOR_CHAIN_0__TAG_ALLOC_FOR_VC0_CHAIN__SHIFT                                        0x0
+#define SHUB_A2S_TAG_ALLOC_FOR_CHAIN_0__TAG_ALLOC_FOR_VC1_CHAIN__SHIFT                                        0x8
+#define SHUB_A2S_TAG_ALLOC_FOR_CHAIN_0__TAG_ALLOC_FOR_VC2_CHAIN__SHIFT                                        0x10
+#define SHUB_A2S_TAG_ALLOC_FOR_CHAIN_0__TAG_ALLOC_FOR_VC3_CHAIN__SHIFT                                        0x18
+#define SHUB_A2S_TAG_ALLOC_FOR_CHAIN_0__TAG_ALLOC_FOR_VC0_CHAIN_MASK                                          0x000000FFL
+#define SHUB_A2S_TAG_ALLOC_FOR_CHAIN_0__TAG_ALLOC_FOR_VC1_CHAIN_MASK                                          0x0000FF00L
+#define SHUB_A2S_TAG_ALLOC_FOR_CHAIN_0__TAG_ALLOC_FOR_VC2_CHAIN_MASK                                          0x00FF0000L
+#define SHUB_A2S_TAG_ALLOC_FOR_CHAIN_0__TAG_ALLOC_FOR_VC3_CHAIN_MASK                                          0xFF000000L
+//SHUB_A2S_TAG_ALLOC_FOR_CHAIN_1
+#define SHUB_A2S_TAG_ALLOC_FOR_CHAIN_1__TAG_ALLOC_FOR_VC4_CHAIN__SHIFT                                        0x0
+#define SHUB_A2S_TAG_ALLOC_FOR_CHAIN_1__TAG_ALLOC_FOR_VC5_CHAIN__SHIFT                                        0x8
+#define SHUB_A2S_TAG_ALLOC_FOR_CHAIN_1__TAG_ALLOC_FOR_VC6_CHAIN__SHIFT                                        0x10
+#define SHUB_A2S_TAG_ALLOC_FOR_CHAIN_1__TAG_ALLOC_FOR_VC7_CHAIN__SHIFT                                        0x18
+#define SHUB_A2S_TAG_ALLOC_FOR_CHAIN_1__TAG_ALLOC_FOR_VC4_CHAIN_MASK                                          0x000000FFL
+#define SHUB_A2S_TAG_ALLOC_FOR_CHAIN_1__TAG_ALLOC_FOR_VC5_CHAIN_MASK                                          0x0000FF00L
+#define SHUB_A2S_TAG_ALLOC_FOR_CHAIN_1__TAG_ALLOC_FOR_VC6_CHAIN_MASK                                          0x00FF0000L
+#define SHUB_A2S_TAG_ALLOC_FOR_CHAIN_1__TAG_ALLOC_FOR_VC7_CHAIN_MASK                                          0xFF000000L
+//GDC_SDP_PORT_CTRL
+#define GDC_SDP_PORT_CTRL__POOL_CREDIT_ALLOC_OVERRIDE_DYNAMIC__SHIFT                                          0x0
+#define GDC_SDP_PORT_CTRL__POOL_CREDIT_ALLOC_OVERRIDE_DYNAMIC_MASK                                            0x00000001L
+//GDC_A2S_SDP_REQ_POOLCRED_ALLOC
+#define GDC_A2S_SDP_REQ_POOLCRED_ALLOC__VC0_ALLOC__SHIFT                                                      0x0
+#define GDC_A2S_SDP_REQ_POOLCRED_ALLOC__VC1_ALLOC__SHIFT                                                      0x4
+#define GDC_A2S_SDP_REQ_POOLCRED_ALLOC__VC2_ALLOC__SHIFT                                                      0x8
+#define GDC_A2S_SDP_REQ_POOLCRED_ALLOC__VC3_ALLOC__SHIFT                                                      0xc
+#define GDC_A2S_SDP_REQ_POOLCRED_ALLOC__VC4_ALLOC__SHIFT                                                      0x10
+#define GDC_A2S_SDP_REQ_POOLCRED_ALLOC__VC5_ALLOC__SHIFT                                                      0x14
+#define GDC_A2S_SDP_REQ_POOLCRED_ALLOC__VC6_ALLOC__SHIFT                                                      0x18
+#define GDC_A2S_SDP_REQ_POOLCRED_ALLOC__VC7_ALLOC__SHIFT                                                      0x1c
+#define GDC_A2S_SDP_REQ_POOLCRED_ALLOC__VC0_ALLOC_MASK                                                        0x0000000FL
+#define GDC_A2S_SDP_REQ_POOLCRED_ALLOC__VC1_ALLOC_MASK                                                        0x000000F0L
+#define GDC_A2S_SDP_REQ_POOLCRED_ALLOC__VC2_ALLOC_MASK                                                        0x00000F00L
+#define GDC_A2S_SDP_REQ_POOLCRED_ALLOC__VC3_ALLOC_MASK                                                        0x0000F000L
+#define GDC_A2S_SDP_REQ_POOLCRED_ALLOC__VC4_ALLOC_MASK                                                        0x000F0000L
+#define GDC_A2S_SDP_REQ_POOLCRED_ALLOC__VC5_ALLOC_MASK                                                        0x00F00000L
+#define GDC_A2S_SDP_REQ_POOLCRED_ALLOC__VC6_ALLOC_MASK                                                        0x0F000000L
+#define GDC_A2S_SDP_REQ_POOLCRED_ALLOC__VC7_ALLOC_MASK                                                        0xF0000000L
+//GDC_A2S_SDP_DAT_POOLCRED_ALLOC
+#define GDC_A2S_SDP_DAT_POOLCRED_ALLOC__VC0_ALLOC__SHIFT                                                      0x0
+#define GDC_A2S_SDP_DAT_POOLCRED_ALLOC__VC1_ALLOC__SHIFT                                                      0x4
+#define GDC_A2S_SDP_DAT_POOLCRED_ALLOC__VC2_ALLOC__SHIFT                                                      0x8
+#define GDC_A2S_SDP_DAT_POOLCRED_ALLOC__VC3_ALLOC__SHIFT                                                      0xc
+#define GDC_A2S_SDP_DAT_POOLCRED_ALLOC__VC4_ALLOC__SHIFT                                                      0x10
+#define GDC_A2S_SDP_DAT_POOLCRED_ALLOC__VC5_ALLOC__SHIFT                                                      0x14
+#define GDC_A2S_SDP_DAT_POOLCRED_ALLOC__VC6_ALLOC__SHIFT                                                      0x18
+#define GDC_A2S_SDP_DAT_POOLCRED_ALLOC__VC7_ALLOC__SHIFT                                                      0x1c
+#define GDC_A2S_SDP_DAT_POOLCRED_ALLOC__VC0_ALLOC_MASK                                                        0x0000000FL
+#define GDC_A2S_SDP_DAT_POOLCRED_ALLOC__VC1_ALLOC_MASK                                                        0x000000F0L
+#define GDC_A2S_SDP_DAT_POOLCRED_ALLOC__VC2_ALLOC_MASK                                                        0x00000F00L
+#define GDC_A2S_SDP_DAT_POOLCRED_ALLOC__VC3_ALLOC_MASK                                                        0x0000F000L
+#define GDC_A2S_SDP_DAT_POOLCRED_ALLOC__VC4_ALLOC_MASK                                                        0x000F0000L
+#define GDC_A2S_SDP_DAT_POOLCRED_ALLOC__VC5_ALLOC_MASK                                                        0x00F00000L
+#define GDC_A2S_SDP_DAT_POOLCRED_ALLOC__VC6_ALLOC_MASK                                                        0x0F000000L
+#define GDC_A2S_SDP_DAT_POOLCRED_ALLOC__VC7_ALLOC_MASK                                                        0xF0000000L
+//SHUB_PERF_COMMON_COUNTER
+#define SHUB_PERF_COMMON_COUNTER__SHUB_COM_COUNT_ENBALE__SHIFT                                                0x0
+#define SHUB_PERF_COMMON_COUNTER__SHUB_COM_COUNT_ENBALE_MASK                                                  0x00000001L
+//SHUB_A2S_PERF_CNT_FSM
+#define SHUB_A2S_PERF_CNT_FSM__A2S_GLOBAL_SHADOW_TGL_DELAY_COUNT__SHIFT                                       0x0
+#define SHUB_A2S_PERF_CNT_FSM__A2S_GLOBAL_PERF_RESET_TGL_DELAY_COUNT__SHIFT                                   0x4
+#define SHUB_A2S_PERF_CNT_FSM__A2S_GLOBAL_PERF_RESET_TGL_DELAY_EN__SHIFT                                      0x8
+#define SHUB_A2S_PERF_CNT_FSM__A2S_PRE_FLD_GLOBAL_SHADOW_WR__SHIFT                                            0x9
+#define SHUB_A2S_PERF_CNT_FSM__A2S_PERF_CNT_DONE__SHIFT                                                       0xa
+#define SHUB_A2S_PERF_CNT_FSM__A2S_GLOBAL_SHADOW_TGL_DELAY_COUNT_MASK                                         0x0000000FL
+#define SHUB_A2S_PERF_CNT_FSM__A2S_GLOBAL_PERF_RESET_TGL_DELAY_COUNT_MASK                                     0x000000F0L
+#define SHUB_A2S_PERF_CNT_FSM__A2S_GLOBAL_PERF_RESET_TGL_DELAY_EN_MASK                                        0x00000100L
+#define SHUB_A2S_PERF_CNT_FSM__A2S_PRE_FLD_GLOBAL_SHADOW_WR_MASK                                              0x00000200L
+#define SHUB_A2S_PERF_CNT_FSM__A2S_PERF_CNT_DONE_MASK                                                         0x00000400L
+//SHUB_A2S_PERF_CNT_RSP_UNITID
+#define SHUB_A2S_PERF_CNT_RSP_UNITID__MONITOR_WRRSP_UNITID__SHIFT                                             0x0
+#define SHUB_A2S_PERF_CNT_RSP_UNITID__MONITOR_WRRSP_UNITID_EN__SHIFT                                          0xf
+#define SHUB_A2S_PERF_CNT_RSP_UNITID__MONITOR_RDRSP_UNITID__SHIFT                                             0x10
+#define SHUB_A2S_PERF_CNT_RSP_UNITID__MONITOR_RDRSP_UNITID_EN__SHIFT                                          0x1f
+#define SHUB_A2S_PERF_CNT_RSP_UNITID__MONITOR_WRRSP_UNITID_MASK                                               0x000007FFL
+#define SHUB_A2S_PERF_CNT_RSP_UNITID__MONITOR_WRRSP_UNITID_EN_MASK                                            0x00008000L
+#define SHUB_A2S_PERF_CNT_RSP_UNITID__MONITOR_RDRSP_UNITID_MASK                                               0x07FF0000L
+#define SHUB_A2S_PERF_CNT_RSP_UNITID__MONITOR_RDRSP_UNITID_EN_MASK                                            0x80000000L
+//SHUB_A2S_PERF_CNT_0_CTRL
+#define SHUB_A2S_PERF_CNT_0_CTRL__A2S_PERF_CNT_0_SEL__SHIFT                                                   0x0
+#define SHUB_A2S_PERF_CNT_0_CTRL__A2S_PERF_CNT_0_EN__SHIFT                                                    0x1f
+#define SHUB_A2S_PERF_CNT_0_CTRL__A2S_PERF_CNT_0_SEL_MASK                                                     0x7FFFFFFFL
+#define SHUB_A2S_PERF_CNT_0_CTRL__A2S_PERF_CNT_0_EN_MASK                                                      0x80000000L
+//SHUB_A2S_PERF_CNT_1_CTRL
+#define SHUB_A2S_PERF_CNT_1_CTRL__A2S_PERF_CNT_1_SEL__SHIFT                                                   0x0
+#define SHUB_A2S_PERF_CNT_1_CTRL__A2S_PERF_CNT_1_EN__SHIFT                                                    0x1f
+#define SHUB_A2S_PERF_CNT_1_CTRL__A2S_PERF_CNT_1_SEL_MASK                                                     0x7FFFFFFFL
+#define SHUB_A2S_PERF_CNT_1_CTRL__A2S_PERF_CNT_1_EN_MASK                                                      0x80000000L
+//SHUB_A2S_PERF_CNT_2_CTRL
+#define SHUB_A2S_PERF_CNT_2_CTRL__A2S_PERF_CNT_2_SEL__SHIFT                                                   0x0
+#define SHUB_A2S_PERF_CNT_2_CTRL__A2S_PERF_CNT_2_EN__SHIFT                                                    0x1f
+#define SHUB_A2S_PERF_CNT_2_CTRL__A2S_PERF_CNT_2_SEL_MASK                                                     0x7FFFFFFFL
+#define SHUB_A2S_PERF_CNT_2_CTRL__A2S_PERF_CNT_2_EN_MASK                                                      0x80000000L
+//SHUB_A2S_PERF_CNT_3_CTRL
+#define SHUB_A2S_PERF_CNT_3_CTRL__A2S_PERF_CNT_3_SEL__SHIFT                                                   0x0
+#define SHUB_A2S_PERF_CNT_3_CTRL__A2S_PERF_CNT_3_EN__SHIFT                                                    0x1f
+#define SHUB_A2S_PERF_CNT_3_CTRL__A2S_PERF_CNT_3_SEL_MASK                                                     0x7FFFFFFFL
+#define SHUB_A2S_PERF_CNT_3_CTRL__A2S_PERF_CNT_3_EN_MASK                                                      0x80000000L
+//SHUB_A2S_PERF_CNT_0_VALUE_L32BIT
+#define SHUB_A2S_PERF_CNT_0_VALUE_L32BIT__A2S_PERF_CNT_0_VALUE_L32BIT__SHIFT                                  0x0
+#define SHUB_A2S_PERF_CNT_0_VALUE_L32BIT__A2S_PERF_CNT_0_VALUE_L32BIT_MASK                                    0xFFFFFFFFL
+//SHUB_A2S_PERF_CNT_0_VALUE_H16BIT
+#define SHUB_A2S_PERF_CNT_0_VALUE_H16BIT__A2S_PERF_CNT_0_VALUE_H16BIT__SHIFT                                  0x0
+#define SHUB_A2S_PERF_CNT_0_VALUE_H16BIT__A2S_PERF_CNT_0_VALUE_H16BIT_MASK                                    0xFFFFL
+//SHUB_A2S_PERF_CNT_1_VALUE_L32BIT
+#define SHUB_A2S_PERF_CNT_1_VALUE_L32BIT__A2S_PERF_CNT_1_VALUE_L32BIT__SHIFT                                  0x0
+#define SHUB_A2S_PERF_CNT_1_VALUE_L32BIT__A2S_PERF_CNT_1_VALUE_L32BIT_MASK                                    0xFFFFFFFFL
+//SHUB_A2S_PERF_CNT_1_VALUE_H16BIT
+#define SHUB_A2S_PERF_CNT_1_VALUE_H16BIT__A2S_PERF_CNT_1_VALUE_H16BIT__SHIFT                                  0x0
+#define SHUB_A2S_PERF_CNT_1_VALUE_H16BIT__A2S_PERF_CNT_1_VALUE_H16BIT_MASK                                    0xFFFFL
+//SHUB_A2S_PERF_CNT_2_VALUE_L32BIT
+#define SHUB_A2S_PERF_CNT_2_VALUE_L32BIT__A2S_PERF_CNT_2_VALUE_L32BIT__SHIFT                                  0x0
+#define SHUB_A2S_PERF_CNT_2_VALUE_L32BIT__A2S_PERF_CNT_2_VALUE_L32BIT_MASK                                    0xFFFFFFFFL
+//SHUB_A2S_PERF_CNT_2_VALUE_H16BIT
+#define SHUB_A2S_PERF_CNT_2_VALUE_H16BIT__A2S_PERF_CNT_2_VALUE_H16BIT__SHIFT                                  0x0
+#define SHUB_A2S_PERF_CNT_2_VALUE_H16BIT__A2S_PERF_CNT_2_VALUE_H16BIT_MASK                                    0xFFFFL
+//SHUB_A2S_PERF_CNT_3_VALUE_L32BIT
+#define SHUB_A2S_PERF_CNT_3_VALUE_L32BIT__A2S_PERF_CNT_3_VALUE_L32BIT__SHIFT                                  0x0
+#define SHUB_A2S_PERF_CNT_3_VALUE_L32BIT__A2S_PERF_CNT_3_VALUE_L32BIT_MASK                                    0xFFFFFFFFL
+//SHUB_A2S_PERF_CNT_3_VALUE_H16BIT
+#define SHUB_A2S_PERF_CNT_3_VALUE_H16BIT__A2S_PERF_CNT_3_VALUE_H16BIT__SHIFT                                  0x0
+#define SHUB_A2S_PERF_CNT_3_VALUE_H16BIT__A2S_PERF_CNT_3_VALUE_H16BIT_MASK                                    0xFFFFL
+//SHUB_TO_ALL_PERF_COUNTER
+#define SHUB_TO_ALL_PERF_COUNTER__START_COUNT_NOPULS__SHIFT                                                   0x0
+#define SHUB_TO_ALL_PERF_COUNTER__LEGACY_OUT_REALTIME_SEL__SHIFT                                              0x1
+#define SHUB_TO_ALL_PERF_COUNTER__PERF_CNT_TRIG_MONI_SEL__SHIFT                                               0x2
+#define SHUB_TO_ALL_PERF_COUNTER__START_COUNT_NOPULS_MASK                                                     0x00000001L
+#define SHUB_TO_ALL_PERF_COUNTER__LEGACY_OUT_REALTIME_SEL_MASK                                                0x00000002L
+#define SHUB_TO_ALL_PERF_COUNTER__PERF_CNT_TRIG_MONI_SEL_MASK                                                 0x0000000CL
+//GDC_PERF_COUNTER_RESET
+#define GDC_PERF_COUNTER_RESET__GDC_PERF_CNT0_RESET__SHIFT                                                    0x0
+#define GDC_PERF_COUNTER_RESET__GDC_PERF_CNT1_RESET__SHIFT                                                    0x1
+#define GDC_PERF_COUNTER_RESET__GDC_PERF_CNT2_RESET__SHIFT                                                    0x2
+#define GDC_PERF_COUNTER_RESET__GDC_PERF_CNT3_RESET__SHIFT                                                    0x3
+#define GDC_PERF_COUNTER_RESET__GDC_PERF_CNT0_RESET_MASK                                                      0x00000001L
+#define GDC_PERF_COUNTER_RESET__GDC_PERF_CNT1_RESET_MASK                                                      0x00000002L
+#define GDC_PERF_COUNTER_RESET__GDC_PERF_CNT2_RESET_MASK                                                      0x00000004L
+#define GDC_PERF_COUNTER_RESET__GDC_PERF_CNT3_RESET_MASK                                                      0x00000008L
+//SHUB_COM_COUNT_VALUE
+#define SHUB_COM_COUNT_VALUE__SHUB_COM_COUNT_VALUE__SHIFT                                                     0x0
+#define SHUB_COM_COUNT_VALUE__SHUB_COM_COUNT_VALUE_MASK                                                       0xFFFFFFFFL
+//A2S_QUEUE_FIFO_ARB_CNTL
+#define A2S_QUEUE_FIFO_ARB_CNTL__WR_QUEUE_FIFO_POP_ARB_PRIORITY__SHIFT                                        0x0
+#define A2S_QUEUE_FIFO_ARB_CNTL__RD_QUEUE_FIFO_POP_ARB_PRIORITY__SHIFT                                        0xa
+#define A2S_QUEUE_FIFO_ARB_CNTL__WR_QUEUE_FIFO_POP_ARB_MODE__SHIFT                                            0x14
+#define A2S_QUEUE_FIFO_ARB_CNTL__RD_QUEUE_FIFO_POP_ARB_MODE__SHIFT                                            0x15
+#define A2S_QUEUE_FIFO_ARB_CNTL__WR_QUEUE_FIFO_POP_ARB_PRIORITY_MASK                                          0x000003FFL
+#define A2S_QUEUE_FIFO_ARB_CNTL__RD_QUEUE_FIFO_POP_ARB_PRIORITY_MASK                                          0x000FFC00L
+#define A2S_QUEUE_FIFO_ARB_CNTL__WR_QUEUE_FIFO_POP_ARB_MODE_MASK                                              0x00100000L
+#define A2S_QUEUE_FIFO_ARB_CNTL__RD_QUEUE_FIFO_POP_ARB_MODE_MASK                                              0x00200000L
+//WR_A2S_RSP_WRR_CNTL
+#define WR_A2S_RSP_WRR_CNTL__WR_A2S_WRR_SIZE_QUEUE0__SHIFT                                                    0x0
+#define WR_A2S_RSP_WRR_CNTL__WR_A2S_WRR_SIZE_QUEUE1__SHIFT                                                    0x4
+#define WR_A2S_RSP_WRR_CNTL__WR_A2S_WRR_SIZE_QUEUE2__SHIFT                                                    0x8
+#define WR_A2S_RSP_WRR_CNTL__WR_A2S_WRR_SIZE_QUEUE3__SHIFT                                                    0xc
+#define WR_A2S_RSP_WRR_CNTL__WR_A2S_WRR_SIZE_QUEUE4__SHIFT                                                    0x10
+#define WR_A2S_RSP_WRR_CNTL__WR_A2S_WRR_SIZE_QUEUE5__SHIFT                                                    0x14
+#define WR_A2S_RSP_WRR_CNTL__WR_A2S_WRR_SIZE_QUEUE6__SHIFT                                                    0x18
+#define WR_A2S_RSP_WRR_CNTL__WR_A2S_WRR_SIZE_QUEUE7__SHIFT                                                    0x1c
+#define WR_A2S_RSP_WRR_CNTL__WR_A2S_WRR_SIZE_QUEUE0_MASK                                                      0x0000000FL
+#define WR_A2S_RSP_WRR_CNTL__WR_A2S_WRR_SIZE_QUEUE1_MASK                                                      0x000000F0L
+#define WR_A2S_RSP_WRR_CNTL__WR_A2S_WRR_SIZE_QUEUE2_MASK                                                      0x00000F00L
+#define WR_A2S_RSP_WRR_CNTL__WR_A2S_WRR_SIZE_QUEUE3_MASK                                                      0x0000F000L
+#define WR_A2S_RSP_WRR_CNTL__WR_A2S_WRR_SIZE_QUEUE4_MASK                                                      0x000F0000L
+#define WR_A2S_RSP_WRR_CNTL__WR_A2S_WRR_SIZE_QUEUE5_MASK                                                      0x00F00000L
+#define WR_A2S_RSP_WRR_CNTL__WR_A2S_WRR_SIZE_QUEUE6_MASK                                                      0x0F000000L
+#define WR_A2S_RSP_WRR_CNTL__WR_A2S_WRR_SIZE_QUEUE7_MASK                                                      0xF0000000L
+//RD_A2S_RSP_WRR_CNTL
+#define RD_A2S_RSP_WRR_CNTL__RD_A2S_WRR_SIZE_QUEUE0__SHIFT                                                    0x0
+#define RD_A2S_RSP_WRR_CNTL__RD_A2S_WRR_SIZE_QUEUE1__SHIFT                                                    0x4
+#define RD_A2S_RSP_WRR_CNTL__RD_A2S_WRR_SIZE_QUEUE2__SHIFT                                                    0x8
+#define RD_A2S_RSP_WRR_CNTL__RD_A2S_WRR_SIZE_QUEUE3__SHIFT                                                    0xc
+#define RD_A2S_RSP_WRR_CNTL__RD_A2S_WRR_SIZE_QUEUE4__SHIFT                                                    0x10
+#define RD_A2S_RSP_WRR_CNTL__RD_A2S_WRR_SIZE_QUEUE5__SHIFT                                                    0x14
+#define RD_A2S_RSP_WRR_CNTL__RD_A2S_WRR_SIZE_QUEUE6__SHIFT                                                    0x18
+#define RD_A2S_RSP_WRR_CNTL__RD_A2S_WRR_SIZE_QUEUE7__SHIFT                                                    0x1c
+#define RD_A2S_RSP_WRR_CNTL__RD_A2S_WRR_SIZE_QUEUE0_MASK                                                      0x0000000FL
+#define RD_A2S_RSP_WRR_CNTL__RD_A2S_WRR_SIZE_QUEUE1_MASK                                                      0x000000F0L
+#define RD_A2S_RSP_WRR_CNTL__RD_A2S_WRR_SIZE_QUEUE2_MASK                                                      0x00000F00L
+#define RD_A2S_RSP_WRR_CNTL__RD_A2S_WRR_SIZE_QUEUE3_MASK                                                      0x0000F000L
+#define RD_A2S_RSP_WRR_CNTL__RD_A2S_WRR_SIZE_QUEUE4_MASK                                                      0x000F0000L
+#define RD_A2S_RSP_WRR_CNTL__RD_A2S_WRR_SIZE_QUEUE5_MASK                                                      0x00F00000L
+#define RD_A2S_RSP_WRR_CNTL__RD_A2S_WRR_SIZE_QUEUE6_MASK                                                      0x0F000000L
+#define RD_A2S_RSP_WRR_CNTL__RD_A2S_WRR_SIZE_QUEUE7_MASK                                                      0xF0000000L
+
+
+// addressBlock: nbif0_nbif0_syshub_mmreg_syshubdirect
+//SYSHUB_DS_CTRL_SOCCLK
+#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT                                   0x0
+#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT                                   0x1
+#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT                                   0x2
+#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT                                   0x3
+#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT                                   0x4
+#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT                                   0x5
+#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT                                   0x6
+#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT                                   0x7
+#define SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DEEPSLEEP_ALLOW_ENABLE__SHIFT                                    0x1c
+#define SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DS_EN__SHIFT                                                     0x1f
+#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL0_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK                                     0x00000001L
+#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL1_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK                                     0x00000002L
+#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL2_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK                                     0x00000004L
+#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL3_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK                                     0x00000008L
+#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL4_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK                                     0x00000010L
+#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL5_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK                                     0x00000020L
+#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL6_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK                                     0x00000040L
+#define SYSHUB_DS_CTRL_SOCCLK__DMA_CL7_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK                                     0x00000080L
+#define SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DEEPSLEEP_ALLOW_ENABLE_MASK                                      0x10000000L
+#define SYSHUB_DS_CTRL_SOCCLK__SYSHUB_SOCCLK_DS_EN_MASK                                                       0x80000000L
+//SYSHUB_DS_CTRL2_SOCCLK
+#define SYSHUB_DS_CTRL2_SOCCLK__SYSHUB_SOCCLK_DS_TIMER__SHIFT                                                 0x0
+#define SYSHUB_DS_CTRL2_SOCCLK__SYSHUB_SOCCLK_DS_TIMER_MASK                                                   0x0000FFFFL
+//SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK
+#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_bypass_en__SHIFT                 0x10
+#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_bypass_en__SHIFT                 0x11
+#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_bypass_en__SHIFT                 0x12
+#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW3_bypass_en__SHIFT                 0x13
+#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW4_bypass_en__SHIFT                 0x14
+#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW5_bypass_en__SHIFT                 0x15
+#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_DYNAMIC_BYPASS_EN_socclk__SHIFT                      0x1f
+#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_bypass_en_MASK                   0x00010000L
+#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_bypass_en_MASK                   0x00020000L
+#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_bypass_en_MASK                   0x00040000L
+#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW3_bypass_en_MASK                   0x00080000L
+#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW4_bypass_en_MASK                   0x00100000L
+#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW5_bypass_en_MASK                   0x00200000L
+#define SYSHUB_BGEN_ENHANCEMENT_BYPASS_EN_SOCCLK__SYSHUB_DYNAMIC_BYPASS_EN_socclk_MASK                        0x80000000L
+//SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK
+#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_imm_en__SHIFT                       0x10
+#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_imm_en__SHIFT                       0x11
+#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_imm_en__SHIFT                       0x12
+#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW3_imm_en__SHIFT                       0x13
+#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW4_imm_en__SHIFT                       0x14
+#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW5_imm_en__SHIFT                       0x15
+#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW0_imm_en_MASK                         0x00010000L
+#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW1_imm_en_MASK                         0x00020000L
+#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW2_imm_en_MASK                         0x00040000L
+#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW3_imm_en_MASK                         0x00080000L
+#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW4_imm_en_MASK                         0x00100000L
+#define SYSHUB_BGEN_ENHANCEMENT_IMM_EN_SOCCLK__SYSHUB_bgen_socclk_DMA_SW5_imm_en_MASK                         0x00200000L
+//SYSHUB_MGCG_CTRL_SOCCLK
+#define SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_EN_SOCCLK__SHIFT                                                 0x0
+#define SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_MODE_SOCCLK__SHIFT                                               0x1
+#define SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_HYSTERESIS_SOCCLK__SHIFT                                         0x2
+#define SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_HST_DIS_SOCCLK__SHIFT                                            0xa
+#define SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_DMA_DIS_SOCCLK__SHIFT                                            0xb
+#define SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_REG_DIS_SOCCLK__SHIFT                                            0xc
+#define SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_AER_DIS_SOCCLK__SHIFT                                            0xd
+#define SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_DBG_DIS_SOCCLK__SHIFT                                            0xe
+#define SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_EN_SOCCLK_MASK                                                   0x00000001L
+#define SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_MODE_SOCCLK_MASK                                                 0x00000002L
+#define SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_HYSTERESIS_SOCCLK_MASK                                           0x000003FCL
+#define SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_HST_DIS_SOCCLK_MASK                                              0x00000400L
+#define SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_DMA_DIS_SOCCLK_MASK                                              0x00000800L
+#define SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_REG_DIS_SOCCLK_MASK                                              0x00001000L
+#define SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_AER_DIS_SOCCLK_MASK                                              0x00002000L
+#define SYSHUB_MGCG_CTRL_SOCCLK__SYSHUB_MGCG_DBG_DIS_SOCCLK_MASK                                              0x00004000L
+//SYSHUB_SCRATCH_SOCCLK
+#define SYSHUB_SCRATCH_SOCCLK__SCRATCH_SOCCLK__SHIFT                                                          0x0
+#define SYSHUB_SCRATCH_SOCCLK__SCRATCH_SOCCLK_MASK                                                            0xFFFFFFFFL
+//SYSHUB_HANG_CNTL_SOCCLK
+//SYSHUB_SELECT_SOCCLK
+#define SYSHUB_SELECT_SOCCLK__SELECT_USB0__SHIFT                                                              0x0
+#define SYSHUB_SELECT_SOCCLK__SELECT_USB0_MASK                                                                0x00000001L
+//SYSHUB_DS_AW_READY_SOCCLK
+#define SYSHUB_DS_AW_READY_SOCCLK__DMA_CL0_SOCCLK_AW_READY_DIS_ENABLE__SHIFT                                  0x0
+#define SYSHUB_DS_AW_READY_SOCCLK__DMA_CL1_SOCCLK_AW_READY_DIS_ENABLE__SHIFT                                  0x1
+#define SYSHUB_DS_AW_READY_SOCCLK__DMA_CL2_SOCCLK_AW_READY_DIS_ENABLE__SHIFT                                  0x2
+#define SYSHUB_DS_AW_READY_SOCCLK__DMA_CL3_SOCCLK_AW_READY_DIS_ENABLE__SHIFT                                  0x3
+#define SYSHUB_DS_AW_READY_SOCCLK__DMA_CL4_SOCCLK_AW_READY_DIS_ENABLE__SHIFT                                  0x4
+#define SYSHUB_DS_AW_READY_SOCCLK__DMA_CL5_SOCCLK_AW_READY_DIS_ENABLE__SHIFT                                  0x5
+#define SYSHUB_DS_AW_READY_SOCCLK__DMA_CL6_SOCCLK_AW_READY_DIS_ENABLE__SHIFT                                  0x6
+#define SYSHUB_DS_AW_READY_SOCCLK__DMA_CL7_SOCCLK_AW_READY_DIS_ENABLE__SHIFT                                  0x7
+#define SYSHUB_DS_AW_READY_SOCCLK__DMA_CL0_SOCCLK_AW_READY_DIS_ENABLE_MASK                                    0x00000001L
+#define SYSHUB_DS_AW_READY_SOCCLK__DMA_CL1_SOCCLK_AW_READY_DIS_ENABLE_MASK                                    0x00000002L
+#define SYSHUB_DS_AW_READY_SOCCLK__DMA_CL2_SOCCLK_AW_READY_DIS_ENABLE_MASK                                    0x00000004L
+#define SYSHUB_DS_AW_READY_SOCCLK__DMA_CL3_SOCCLK_AW_READY_DIS_ENABLE_MASK                                    0x00000008L
+#define SYSHUB_DS_AW_READY_SOCCLK__DMA_CL4_SOCCLK_AW_READY_DIS_ENABLE_MASK                                    0x00000010L
+#define SYSHUB_DS_AW_READY_SOCCLK__DMA_CL5_SOCCLK_AW_READY_DIS_ENABLE_MASK                                    0x00000020L
+#define SYSHUB_DS_AW_READY_SOCCLK__DMA_CL6_SOCCLK_AW_READY_DIS_ENABLE_MASK                                    0x00000040L
+#define SYSHUB_DS_AW_READY_SOCCLK__DMA_CL7_SOCCLK_AW_READY_DIS_ENABLE_MASK                                    0x00000080L
+//SYSHUB_DS_AR_READY_SOCCLK
+#define SYSHUB_DS_AR_READY_SOCCLK__DMA_CL0_SOCCLK_AR_READY_DIS_ENABLE__SHIFT                                  0x0
+#define SYSHUB_DS_AR_READY_SOCCLK__DMA_CL1_SOCCLK_AR_READY_DIS_ENABLE__SHIFT                                  0x1
+#define SYSHUB_DS_AR_READY_SOCCLK__DMA_CL2_SOCCLK_AR_READY_DIS_ENABLE__SHIFT                                  0x2
+#define SYSHUB_DS_AR_READY_SOCCLK__DMA_CL3_SOCCLK_AR_READY_DIS_ENABLE__SHIFT                                  0x3
+#define SYSHUB_DS_AR_READY_SOCCLK__DMA_CL4_SOCCLK_AR_READY_DIS_ENABLE__SHIFT                                  0x4
+#define SYSHUB_DS_AR_READY_SOCCLK__DMA_CL5_SOCCLK_AR_READY_DIS_ENABLE__SHIFT                                  0x5
+#define SYSHUB_DS_AR_READY_SOCCLK__DMA_CL6_SOCCLK_AR_READY_DIS_ENABLE__SHIFT                                  0x6
+#define SYSHUB_DS_AR_READY_SOCCLK__DMA_CL7_SOCCLK_AR_READY_DIS_ENABLE__SHIFT                                  0x7
+#define SYSHUB_DS_AR_READY_SOCCLK__DMA_CL0_SOCCLK_AR_READY_DIS_ENABLE_MASK                                    0x00000001L
+#define SYSHUB_DS_AR_READY_SOCCLK__DMA_CL1_SOCCLK_AR_READY_DIS_ENABLE_MASK                                    0x00000002L
+#define SYSHUB_DS_AR_READY_SOCCLK__DMA_CL2_SOCCLK_AR_READY_DIS_ENABLE_MASK                                    0x00000004L
+#define SYSHUB_DS_AR_READY_SOCCLK__DMA_CL3_SOCCLK_AR_READY_DIS_ENABLE_MASK                                    0x00000008L
+#define SYSHUB_DS_AR_READY_SOCCLK__DMA_CL4_SOCCLK_AR_READY_DIS_ENABLE_MASK                                    0x00000010L
+#define SYSHUB_DS_AR_READY_SOCCLK__DMA_CL5_SOCCLK_AR_READY_DIS_ENABLE_MASK                                    0x00000020L
+#define SYSHUB_DS_AR_READY_SOCCLK__DMA_CL6_SOCCLK_AR_READY_DIS_ENABLE_MASK                                    0x00000040L
+#define SYSHUB_DS_AR_READY_SOCCLK__DMA_CL7_SOCCLK_AR_READY_DIS_ENABLE_MASK                                    0x00000080L
+//SYSHUB_DS_W_READY_SOCCLK
+#define SYSHUB_DS_W_READY_SOCCLK__DMA_CL0_SOCCLK_W_READY_DIS_ENABLE__SHIFT                                    0x0
+#define SYSHUB_DS_W_READY_SOCCLK__DMA_CL1_SOCCLK_W_READY_DIS_ENABLE__SHIFT                                    0x1
+#define SYSHUB_DS_W_READY_SOCCLK__DMA_CL2_SOCCLK_W_READY_DIS_ENABLE__SHIFT                                    0x2
+#define SYSHUB_DS_W_READY_SOCCLK__DMA_CL3_SOCCLK_W_READY_DIS_ENABLE__SHIFT                                    0x3
+#define SYSHUB_DS_W_READY_SOCCLK__DMA_CL4_SOCCLK_W_READY_DIS_ENABLE__SHIFT                                    0x4
+#define SYSHUB_DS_W_READY_SOCCLK__DMA_CL5_SOCCLK_W_READY_DIS_ENABLE__SHIFT                                    0x5
+#define SYSHUB_DS_W_READY_SOCCLK__DMA_CL6_SOCCLK_W_READY_DIS_ENABLE__SHIFT                                    0x6
+#define SYSHUB_DS_W_READY_SOCCLK__DMA_CL7_SOCCLK_W_READY_DIS_ENABLE__SHIFT                                    0x7
+#define SYSHUB_DS_W_READY_SOCCLK__DMA_CL0_SOCCLK_W_READY_DIS_ENABLE_MASK                                      0x00000001L
+#define SYSHUB_DS_W_READY_SOCCLK__DMA_CL1_SOCCLK_W_READY_DIS_ENABLE_MASK                                      0x00000002L
+#define SYSHUB_DS_W_READY_SOCCLK__DMA_CL2_SOCCLK_W_READY_DIS_ENABLE_MASK                                      0x00000004L
+#define SYSHUB_DS_W_READY_SOCCLK__DMA_CL3_SOCCLK_W_READY_DIS_ENABLE_MASK                                      0x00000008L
+#define SYSHUB_DS_W_READY_SOCCLK__DMA_CL4_SOCCLK_W_READY_DIS_ENABLE_MASK                                      0x00000010L
+#define SYSHUB_DS_W_READY_SOCCLK__DMA_CL5_SOCCLK_W_READY_DIS_ENABLE_MASK                                      0x00000020L
+#define SYSHUB_DS_W_READY_SOCCLK__DMA_CL6_SOCCLK_W_READY_DIS_ENABLE_MASK                                      0x00000040L
+#define SYSHUB_DS_W_READY_SOCCLK__DMA_CL7_SOCCLK_W_READY_DIS_ENABLE_MASK                                      0x00000080L
+//SYSHUB_DS_R_READY_SOCCLK
+#define SYSHUB_DS_R_READY_SOCCLK__DMA_CL0_SOCCLK_R_READY_DIS_ENABLE__SHIFT                                    0x0
+#define SYSHUB_DS_R_READY_SOCCLK__DMA_CL1_SOCCLK_R_READY_DIS_ENABLE__SHIFT                                    0x1
+#define SYSHUB_DS_R_READY_SOCCLK__DMA_CL2_SOCCLK_R_READY_DIS_ENABLE__SHIFT                                    0x2
+#define SYSHUB_DS_R_READY_SOCCLK__DMA_CL3_SOCCLK_R_READY_DIS_ENABLE__SHIFT                                    0x3
+#define SYSHUB_DS_R_READY_SOCCLK__DMA_CL4_SOCCLK_R_READY_DIS_ENABLE__SHIFT                                    0x4
+#define SYSHUB_DS_R_READY_SOCCLK__DMA_CL5_SOCCLK_R_READY_DIS_ENABLE__SHIFT                                    0x5
+#define SYSHUB_DS_R_READY_SOCCLK__DMA_CL6_SOCCLK_R_READY_DIS_ENABLE__SHIFT                                    0x6
+#define SYSHUB_DS_R_READY_SOCCLK__DMA_CL7_SOCCLK_R_READY_DIS_ENABLE__SHIFT                                    0x7
+#define SYSHUB_DS_R_READY_SOCCLK__DMA_CL0_SOCCLK_R_READY_DIS_ENABLE_MASK                                      0x00000001L
+#define SYSHUB_DS_R_READY_SOCCLK__DMA_CL1_SOCCLK_R_READY_DIS_ENABLE_MASK                                      0x00000002L
+#define SYSHUB_DS_R_READY_SOCCLK__DMA_CL2_SOCCLK_R_READY_DIS_ENABLE_MASK                                      0x00000004L
+#define SYSHUB_DS_R_READY_SOCCLK__DMA_CL3_SOCCLK_R_READY_DIS_ENABLE_MASK                                      0x00000008L
+#define SYSHUB_DS_R_READY_SOCCLK__DMA_CL4_SOCCLK_R_READY_DIS_ENABLE_MASK                                      0x00000010L
+#define SYSHUB_DS_R_READY_SOCCLK__DMA_CL5_SOCCLK_R_READY_DIS_ENABLE_MASK                                      0x00000020L
+#define SYSHUB_DS_R_READY_SOCCLK__DMA_CL6_SOCCLK_R_READY_DIS_ENABLE_MASK                                      0x00000040L
+#define SYSHUB_DS_R_READY_SOCCLK__DMA_CL7_SOCCLK_R_READY_DIS_ENABLE_MASK                                      0x00000080L
+//SYSHUB_DS_B_READY_SOCCLK
+#define SYSHUB_DS_B_READY_SOCCLK__DMA_CL0_SOCCLK_B_READY_DIS_ENABLE__SHIFT                                    0x0
+#define SYSHUB_DS_B_READY_SOCCLK__DMA_CL1_SOCCLK_B_READY_DIS_ENABLE__SHIFT                                    0x1
+#define SYSHUB_DS_B_READY_SOCCLK__DMA_CL2_SOCCLK_B_READY_DIS_ENABLE__SHIFT                                    0x2
+#define SYSHUB_DS_B_READY_SOCCLK__DMA_CL3_SOCCLK_B_READY_DIS_ENABLE__SHIFT                                    0x3
+#define SYSHUB_DS_B_READY_SOCCLK__DMA_CL4_SOCCLK_B_READY_DIS_ENABLE__SHIFT                                    0x4
+#define SYSHUB_DS_B_READY_SOCCLK__DMA_CL5_SOCCLK_B_READY_DIS_ENABLE__SHIFT                                    0x5
+#define SYSHUB_DS_B_READY_SOCCLK__DMA_CL6_SOCCLK_B_READY_DIS_ENABLE__SHIFT                                    0x6
+#define SYSHUB_DS_B_READY_SOCCLK__DMA_CL7_SOCCLK_B_READY_DIS_ENABLE__SHIFT                                    0x7
+#define SYSHUB_DS_B_READY_SOCCLK__DMA_CL0_SOCCLK_B_READY_DIS_ENABLE_MASK                                      0x00000001L
+#define SYSHUB_DS_B_READY_SOCCLK__DMA_CL1_SOCCLK_B_READY_DIS_ENABLE_MASK                                      0x00000002L
+#define SYSHUB_DS_B_READY_SOCCLK__DMA_CL2_SOCCLK_B_READY_DIS_ENABLE_MASK                                      0x00000004L
+#define SYSHUB_DS_B_READY_SOCCLK__DMA_CL3_SOCCLK_B_READY_DIS_ENABLE_MASK                                      0x00000008L
+#define SYSHUB_DS_B_READY_SOCCLK__DMA_CL4_SOCCLK_B_READY_DIS_ENABLE_MASK                                      0x00000010L
+#define SYSHUB_DS_B_READY_SOCCLK__DMA_CL5_SOCCLK_B_READY_DIS_ENABLE_MASK                                      0x00000020L
+#define SYSHUB_DS_B_READY_SOCCLK__DMA_CL6_SOCCLK_B_READY_DIS_ENABLE_MASK                                      0x00000040L
+#define SYSHUB_DS_B_READY_SOCCLK__DMA_CL7_SOCCLK_B_READY_DIS_ENABLE_MASK                                      0x00000080L
+//SYSHUB_AXI_DEBUG_COUNTER_CNTL_SOCCLK
+#define SYSHUB_AXI_DEBUG_COUNTER_CNTL_SOCCLK__HST_SOCCLK_AXI_DEBUG_COUNTER_EN__SHIFT                          0x0
+#define SYSHUB_AXI_DEBUG_COUNTER_CNTL_SOCCLK__DMA_SOCCLK_AXI_DEBUG_COUNTER_EN__SHIFT                          0x1
+#define SYSHUB_AXI_DEBUG_COUNTER_CNTL_SOCCLK__HST_SOCCLK_AXI_DEBUG_COUNTER_EN_MASK                            0x00000001L
+#define SYSHUB_AXI_DEBUG_COUNTER_CNTL_SOCCLK__DMA_SOCCLK_AXI_DEBUG_COUNTER_EN_MASK                            0x00000002L
+//DMA_CLK0_SW0_SYSHUB_QOS_CNTL
+#define DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT                                                    0x0
+#define DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT                                                    0x1
+#define DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT                                                    0x5
+#define DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_CNTL_MODE_MASK                                                      0x00000001L
+#define DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MAX_VALUE_MASK                                                      0x0000001EL
+#define DMA_CLK0_SW0_SYSHUB_QOS_CNTL__QOS_MIN_VALUE_MASK                                                      0x000001E0L
+//DMA_CLK0_SW1_SYSHUB_QOS_CNTL
+#define DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE__SHIFT                                                    0x0
+#define DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE__SHIFT                                                    0x1
+#define DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE__SHIFT                                                    0x5
+#define DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_CNTL_MODE_MASK                                                      0x00000001L
+#define DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MAX_VALUE_MASK                                                      0x0000001EL
+#define DMA_CLK0_SW1_SYSHUB_QOS_CNTL__QOS_MIN_VALUE_MASK                                                      0x000001E0L
+//DMA_CLK0_SW0_CL0_CNTL
+#define DMA_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT                                                      0x0
+#define DMA_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT                                                    0x1
+#define DMA_CLK0_SW0_CL0_CNTL__DEBUG_RS_RESET_EN__SHIFT                                                       0x2
+#define DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT                                                  0x8
+#define DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT                                               0x9
+#define DMA_CLK0_SW0_CL0_CNTL__READ_WRR_WEIGHT__SHIFT                                                         0x10
+#define DMA_CLK0_SW0_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT                                                        0x18
+#define DMA_CLK0_SW0_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK                                                        0x00000001L
+#define DMA_CLK0_SW0_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK                                                      0x00000002L
+#define DMA_CLK0_SW0_CL0_CNTL__DEBUG_RS_RESET_EN_MASK                                                         0x00000004L
+#define DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_EN_MASK                                                    0x00000100L
+#define DMA_CLK0_SW0_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK                                                 0x00001E00L
+#define DMA_CLK0_SW0_CL0_CNTL__READ_WRR_WEIGHT_MASK                                                           0x00FF0000L
+#define DMA_CLK0_SW0_CL0_CNTL__WRITE_WRR_WEIGHT_MASK                                                          0xFF000000L
+//DMA_CLK0_SW0_CL1_CNTL
+#define DMA_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT                                                      0x0
+#define DMA_CLK0_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT                                                    0x1
+#define DMA_CLK0_SW0_CL1_CNTL__DEBUG_RS_RESET_EN__SHIFT                                                       0x2
+#define DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT                                                  0x8
+#define DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT                                               0x9
+#define DMA_CLK0_SW0_CL1_CNTL__READ_WRR_WEIGHT__SHIFT                                                         0x10
+#define DMA_CLK0_SW0_CL1_CNTL__WRITE_WRR_WEIGHT__SHIFT                                                        0x18
+#define DMA_CLK0_SW0_CL1_CNTL__FLR_ON_RS_RESET_EN_MASK                                                        0x00000001L
+#define DMA_CLK0_SW0_CL1_CNTL__LKRST_ON_RS_RESET_EN_MASK                                                      0x00000002L
+#define DMA_CLK0_SW0_CL1_CNTL__DEBUG_RS_RESET_EN_MASK                                                         0x00000004L
+#define DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_EN_MASK                                                    0x00000100L
+#define DMA_CLK0_SW0_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK                                                 0x00001E00L
+#define DMA_CLK0_SW0_CL1_CNTL__READ_WRR_WEIGHT_MASK                                                           0x00FF0000L
+#define DMA_CLK0_SW0_CL1_CNTL__WRITE_WRR_WEIGHT_MASK                                                          0xFF000000L
+//DMA_CLK0_SW1_CL0_CNTL
+#define DMA_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT                                                      0x0
+#define DMA_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT                                                    0x1
+#define DMA_CLK0_SW1_CL0_CNTL__DEBUG_RS_RESET_EN__SHIFT                                                       0x2
+#define DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT                                                  0x8
+#define DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT                                               0x9
+#define DMA_CLK0_SW1_CL0_CNTL__READ_WRR_WEIGHT__SHIFT                                                         0x10
+#define DMA_CLK0_SW1_CL0_CNTL__WRITE_WRR_WEIGHT__SHIFT                                                        0x18
+#define DMA_CLK0_SW1_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK                                                        0x00000001L
+#define DMA_CLK0_SW1_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK                                                      0x00000002L
+#define DMA_CLK0_SW1_CL0_CNTL__DEBUG_RS_RESET_EN_MASK                                                         0x00000004L
+#define DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_EN_MASK                                                    0x00000100L
+#define DMA_CLK0_SW1_CL0_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK                                                 0x00001E00L
+#define DMA_CLK0_SW1_CL0_CNTL__READ_WRR_WEIGHT_MASK                                                           0x00FF0000L
+#define DMA_CLK0_SW1_CL0_CNTL__WRITE_WRR_WEIGHT_MASK                                                          0xFF000000L
+//DMA_CLK0_SW1_CL1_CNTL
+#define DMA_CLK0_SW1_CL1_CNTL__FLR_ON_RS_RESET_EN__SHIFT                                                      0x0
+#define DMA_CLK0_SW1_CL1_CNTL__LKRST_ON_RS_RESET_EN__SHIFT                                                    0x1
+#define DMA_CLK0_SW1_CL1_CNTL__DEBUG_RS_RESET_EN__SHIFT                                                       0x2
+#define DMA_CLK0_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_EN__SHIFT                                                  0x8
+#define DMA_CLK0_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE__SHIFT                                               0x9
+#define DMA_CLK0_SW1_CL1_CNTL__READ_WRR_WEIGHT__SHIFT                                                         0x10
+#define DMA_CLK0_SW1_CL1_CNTL__WRITE_WRR_WEIGHT__SHIFT                                                        0x18
+#define DMA_CLK0_SW1_CL1_CNTL__FLR_ON_RS_RESET_EN_MASK                                                        0x00000001L
+#define DMA_CLK0_SW1_CL1_CNTL__LKRST_ON_RS_RESET_EN_MASK                                                      0x00000002L
+#define DMA_CLK0_SW1_CL1_CNTL__DEBUG_RS_RESET_EN_MASK                                                         0x00000004L
+#define DMA_CLK0_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_EN_MASK                                                    0x00000100L
+#define DMA_CLK0_SW1_CL1_CNTL__QOS_STATIC_OVERRIDE_VALUE_MASK                                                 0x00001E00L
+#define DMA_CLK0_SW1_CL1_CNTL__READ_WRR_WEIGHT_MASK                                                           0x00FF0000L
+#define DMA_CLK0_SW1_CL1_CNTL__WRITE_WRR_WEIGHT_MASK                                                          0xFF000000L
+//DMA_CLK0_SW2_CL0_CNTL
+#define DMA_CLK0_SW2_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT                                                      0x0
+#define DMA_CLK0_SW2_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT                                                    0x1
+#define DMA_CLK0_SW2_CL0_CNTL__DEBUG_RS_RESET_EN__SHIFT                                                       0x2
+#define DMA_CLK0_SW2_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK                                                        0x00000001L
+#define DMA_CLK0_SW2_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK                                                      0x00000002L
+#define DMA_CLK0_SW2_CL0_CNTL__DEBUG_RS_RESET_EN_MASK                                                         0x00000004L
+//DMA_CLK0_SW3_CL0_CNTL
+#define DMA_CLK0_SW3_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT                                                      0x0
+#define DMA_CLK0_SW3_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT                                                    0x1
+#define DMA_CLK0_SW3_CL0_CNTL__DEBUG_RS_RESET_EN__SHIFT                                                       0x2
+#define DMA_CLK0_SW3_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK                                                        0x00000001L
+#define DMA_CLK0_SW3_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK                                                      0x00000002L
+#define DMA_CLK0_SW3_CL0_CNTL__DEBUG_RS_RESET_EN_MASK                                                         0x00000004L
+//DMA_CLK0_SW4_CL0_CNTL
+#define DMA_CLK0_SW4_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT                                                      0x0
+#define DMA_CLK0_SW4_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT                                                    0x1
+#define DMA_CLK0_SW4_CL0_CNTL__DEBUG_RS_RESET_EN__SHIFT                                                       0x2
+#define DMA_CLK0_SW4_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK                                                        0x00000001L
+#define DMA_CLK0_SW4_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK                                                      0x00000002L
+#define DMA_CLK0_SW4_CL0_CNTL__DEBUG_RS_RESET_EN_MASK                                                         0x00000004L
+//DMA_CLK0_SW5_CL0_CNTL
+#define DMA_CLK0_SW5_CL0_CNTL__FLR_ON_RS_RESET_EN__SHIFT                                                      0x0
+#define DMA_CLK0_SW5_CL0_CNTL__LKRST_ON_RS_RESET_EN__SHIFT                                                    0x1
+#define DMA_CLK0_SW5_CL0_CNTL__DEBUG_RS_RESET_EN__SHIFT                                                       0x2
+#define DMA_CLK0_SW5_CL0_CNTL__FLR_ON_RS_RESET_EN_MASK                                                        0x00000001L
+#define DMA_CLK0_SW5_CL0_CNTL__LKRST_ON_RS_RESET_EN_MASK                                                      0x00000002L
+#define DMA_CLK0_SW5_CL0_CNTL__DEBUG_RS_RESET_EN_MASK                                                         0x00000004L
+//NIC400_0_AMIB_0_FN_MOD_BM_ISS
+#define NIC400_0_AMIB_0_FN_MOD_BM_ISS__read_iss_override__SHIFT                                               0x0
+#define NIC400_0_AMIB_0_FN_MOD_BM_ISS__write_iss_override__SHIFT                                              0x1
+#define NIC400_0_AMIB_0_FN_MOD_BM_ISS__read_iss_override_MASK                                                 0x00000001L
+#define NIC400_0_AMIB_0_FN_MOD_BM_ISS__write_iss_override_MASK                                                0x00000002L
+//NIC400_0_AMIB_0_FN_MOD
+#define NIC400_0_AMIB_0_FN_MOD__read_iss_override__SHIFT                                                      0x0
+#define NIC400_0_AMIB_0_FN_MOD__write_iss_override__SHIFT                                                     0x1
+#define NIC400_0_AMIB_0_FN_MOD__read_iss_override_MASK                                                        0x00000001L
+#define NIC400_0_AMIB_0_FN_MOD__write_iss_override_MASK                                                       0x00000002L
+//NIC400_0_ASIB_0_FN_MOD
+#define NIC400_0_ASIB_0_FN_MOD__read_iss_override__SHIFT                                                      0x0
+#define NIC400_0_ASIB_0_FN_MOD__write_iss_override__SHIFT                                                     0x1
+#define NIC400_0_ASIB_0_FN_MOD__read_iss_override_MASK                                                        0x00000001L
+#define NIC400_0_ASIB_0_FN_MOD__write_iss_override_MASK                                                       0x00000002L
+//NIC400_0_ASIB_0_QOS_CNTL
+#define NIC400_0_ASIB_0_QOS_CNTL__en_aw_rate__SHIFT                                                           0x0
+#define NIC400_0_ASIB_0_QOS_CNTL__en_ar_rate__SHIFT                                                           0x1
+#define NIC400_0_ASIB_0_QOS_CNTL__en_awar_rate__SHIFT                                                         0x2
+#define NIC400_0_ASIB_0_QOS_CNTL__en_aw_fc__SHIFT                                                             0x3
+#define NIC400_0_ASIB_0_QOS_CNTL__en_ar_fc__SHIFT                                                             0x4
+#define NIC400_0_ASIB_0_QOS_CNTL__en_aw_ot__SHIFT                                                             0x5
+#define NIC400_0_ASIB_0_QOS_CNTL__en_ar_ot__SHIFT                                                             0x6
+#define NIC400_0_ASIB_0_QOS_CNTL__en_awar_ot__SHIFT                                                           0x7
+#define NIC400_0_ASIB_0_QOS_CNTL__mode_aw_fc__SHIFT                                                           0x10
+#define NIC400_0_ASIB_0_QOS_CNTL__mode_ar_fc__SHIFT                                                           0x14
+#define NIC400_0_ASIB_0_QOS_CNTL__en_aw_rate_MASK                                                             0x00000001L
+#define NIC400_0_ASIB_0_QOS_CNTL__en_ar_rate_MASK                                                             0x00000002L
+#define NIC400_0_ASIB_0_QOS_CNTL__en_awar_rate_MASK                                                           0x00000004L
+#define NIC400_0_ASIB_0_QOS_CNTL__en_aw_fc_MASK                                                               0x00000008L
+#define NIC400_0_ASIB_0_QOS_CNTL__en_ar_fc_MASK                                                               0x00000010L
+#define NIC400_0_ASIB_0_QOS_CNTL__en_aw_ot_MASK                                                               0x00000020L
+#define NIC400_0_ASIB_0_QOS_CNTL__en_ar_ot_MASK                                                               0x00000040L
+#define NIC400_0_ASIB_0_QOS_CNTL__en_awar_ot_MASK                                                             0x00000080L
+#define NIC400_0_ASIB_0_QOS_CNTL__mode_aw_fc_MASK                                                             0x00010000L
+#define NIC400_0_ASIB_0_QOS_CNTL__mode_ar_fc_MASK                                                             0x00100000L
+//NIC400_0_ASIB_0_MAX_OT
+#define NIC400_0_ASIB_0_MAX_OT__aw_max_otf__SHIFT                                                             0x0
+#define NIC400_0_ASIB_0_MAX_OT__aw_max_oti__SHIFT                                                             0x8
+#define NIC400_0_ASIB_0_MAX_OT__ar_max_otf__SHIFT                                                             0x10
+#define NIC400_0_ASIB_0_MAX_OT__ar_max_oti__SHIFT                                                             0x18
+#define NIC400_0_ASIB_0_MAX_OT__aw_max_otf_MASK                                                               0x000000FFL
+#define NIC400_0_ASIB_0_MAX_OT__aw_max_oti_MASK                                                               0x00003F00L
+#define NIC400_0_ASIB_0_MAX_OT__ar_max_otf_MASK                                                               0x00FF0000L
+#define NIC400_0_ASIB_0_MAX_OT__ar_max_oti_MASK                                                               0x3F000000L
+//NIC400_0_ASIB_0_MAX_COMB_OT
+#define NIC400_0_ASIB_0_MAX_COMB_OT__awar_max_otf__SHIFT                                                      0x0
+#define NIC400_0_ASIB_0_MAX_COMB_OT__awar_max_oti__SHIFT                                                      0x8
+#define NIC400_0_ASIB_0_MAX_COMB_OT__awar_max_otf_MASK                                                        0x000000FFL
+#define NIC400_0_ASIB_0_MAX_COMB_OT__awar_max_oti_MASK                                                        0x00007F00L
+//NIC400_0_ASIB_0_AW_P
+#define NIC400_0_ASIB_0_AW_P__aw_p__SHIFT                                                                     0x18
+#define NIC400_0_ASIB_0_AW_P__aw_p_MASK                                                                       0xFF000000L
+//NIC400_0_ASIB_0_AW_B
+#define NIC400_0_ASIB_0_AW_B__aw_b__SHIFT                                                                     0x0
+#define NIC400_0_ASIB_0_AW_B__aw_b_MASK                                                                       0x0000FFFFL
+//NIC400_0_ASIB_0_AW_R
+#define NIC400_0_ASIB_0_AW_R__aw_r__SHIFT                                                                     0x14
+#define NIC400_0_ASIB_0_AW_R__aw_r_MASK                                                                       0xFFF00000L
+//NIC400_0_ASIB_0_AR_P
+#define NIC400_0_ASIB_0_AR_P__ar_p__SHIFT                                                                     0x18
+#define NIC400_0_ASIB_0_AR_P__ar_p_MASK                                                                       0xFF000000L
+//NIC400_0_ASIB_0_AR_B
+#define NIC400_0_ASIB_0_AR_B__ar_b__SHIFT                                                                     0x0
+#define NIC400_0_ASIB_0_AR_B__ar_b_MASK                                                                       0x0000FFFFL
+//NIC400_0_ASIB_0_AR_R
+#define NIC400_0_ASIB_0_AR_R__ar_r__SHIFT                                                                     0x14
+#define NIC400_0_ASIB_0_AR_R__ar_r_MASK                                                                       0xFFF00000L
+//NIC400_0_ASIB_0_TARGET_FC
+#define NIC400_0_ASIB_0_TARGET_FC__aw_tgt_latency__SHIFT                                                      0x0
+#define NIC400_0_ASIB_0_TARGET_FC__ar_tgt_latency__SHIFT                                                      0x10
+#define NIC400_0_ASIB_0_TARGET_FC__aw_tgt_latency_MASK                                                        0x00000FFFL
+#define NIC400_0_ASIB_0_TARGET_FC__ar_tgt_latency_MASK                                                        0x0FFF0000L
+//NIC400_0_ASIB_0_KI_FC
+#define NIC400_0_ASIB_0_KI_FC__aw_tgt_latency__SHIFT                                                          0x0
+#define NIC400_0_ASIB_0_KI_FC__ar_tgt_latency__SHIFT                                                          0x8
+#define NIC400_0_ASIB_0_KI_FC__aw_tgt_latency_MASK                                                            0x00000007L
+#define NIC400_0_ASIB_0_KI_FC__ar_tgt_latency_MASK                                                            0x00000700L
+//NIC400_0_ASIB_0_QOS_RANGE
+#define NIC400_0_ASIB_0_QOS_RANGE__aw_min_qos__SHIFT                                                          0x0
+#define NIC400_0_ASIB_0_QOS_RANGE__aw_max_qos__SHIFT                                                          0x8
+#define NIC400_0_ASIB_0_QOS_RANGE__ar_min_qos__SHIFT                                                          0x10
+#define NIC400_0_ASIB_0_QOS_RANGE__ar_max_qos__SHIFT                                                          0x18
+#define NIC400_0_ASIB_0_QOS_RANGE__aw_min_qos_MASK                                                            0x0000000FL
+#define NIC400_0_ASIB_0_QOS_RANGE__aw_max_qos_MASK                                                            0x00000F00L
+#define NIC400_0_ASIB_0_QOS_RANGE__ar_min_qos_MASK                                                            0x000F0000L
+#define NIC400_0_ASIB_0_QOS_RANGE__ar_max_qos_MASK                                                            0x0F000000L
+//NIC400_0_ASIB_1_FN_MOD
+#define NIC400_0_ASIB_1_FN_MOD__read_iss_override__SHIFT                                                      0x0
+#define NIC400_0_ASIB_1_FN_MOD__write_iss_override__SHIFT                                                     0x1
+#define NIC400_0_ASIB_1_FN_MOD__read_iss_override_MASK                                                        0x00000001L
+#define NIC400_0_ASIB_1_FN_MOD__write_iss_override_MASK                                                       0x00000002L
+//NIC400_0_ASIB_1_QOS_CNTL
+#define NIC400_0_ASIB_1_QOS_CNTL__en_aw_rate__SHIFT                                                           0x0
+#define NIC400_0_ASIB_1_QOS_CNTL__en_ar_rate__SHIFT                                                           0x1
+#define NIC400_0_ASIB_1_QOS_CNTL__en_awar_rate__SHIFT                                                         0x2
+#define NIC400_0_ASIB_1_QOS_CNTL__en_aw_fc__SHIFT                                                             0x3
+#define NIC400_0_ASIB_1_QOS_CNTL__en_ar_fc__SHIFT                                                             0x4
+#define NIC400_0_ASIB_1_QOS_CNTL__en_aw_ot__SHIFT                                                             0x5
+#define NIC400_0_ASIB_1_QOS_CNTL__en_ar_ot__SHIFT                                                             0x6
+#define NIC400_0_ASIB_1_QOS_CNTL__en_awar_ot__SHIFT                                                           0x7
+#define NIC400_0_ASIB_1_QOS_CNTL__mode_aw_fc__SHIFT                                                           0x10
+#define NIC400_0_ASIB_1_QOS_CNTL__mode_ar_fc__SHIFT                                                           0x14
+#define NIC400_0_ASIB_1_QOS_CNTL__en_aw_rate_MASK                                                             0x00000001L
+#define NIC400_0_ASIB_1_QOS_CNTL__en_ar_rate_MASK                                                             0x00000002L
+#define NIC400_0_ASIB_1_QOS_CNTL__en_awar_rate_MASK                                                           0x00000004L
+#define NIC400_0_ASIB_1_QOS_CNTL__en_aw_fc_MASK                                                               0x00000008L
+#define NIC400_0_ASIB_1_QOS_CNTL__en_ar_fc_MASK                                                               0x00000010L
+#define NIC400_0_ASIB_1_QOS_CNTL__en_aw_ot_MASK                                                               0x00000020L
+#define NIC400_0_ASIB_1_QOS_CNTL__en_ar_ot_MASK                                                               0x00000040L
+#define NIC400_0_ASIB_1_QOS_CNTL__en_awar_ot_MASK                                                             0x00000080L
+#define NIC400_0_ASIB_1_QOS_CNTL__mode_aw_fc_MASK                                                             0x00010000L
+#define NIC400_0_ASIB_1_QOS_CNTL__mode_ar_fc_MASK                                                             0x00100000L
+//NIC400_0_ASIB_1_MAX_OT
+#define NIC400_0_ASIB_1_MAX_OT__aw_max_otf__SHIFT                                                             0x0
+#define NIC400_0_ASIB_1_MAX_OT__aw_max_oti__SHIFT                                                             0x8
+#define NIC400_0_ASIB_1_MAX_OT__ar_max_otf__SHIFT                                                             0x10
+#define NIC400_0_ASIB_1_MAX_OT__ar_max_oti__SHIFT                                                             0x18
+#define NIC400_0_ASIB_1_MAX_OT__aw_max_otf_MASK                                                               0x000000FFL
+#define NIC400_0_ASIB_1_MAX_OT__aw_max_oti_MASK                                                               0x00003F00L
+#define NIC400_0_ASIB_1_MAX_OT__ar_max_otf_MASK                                                               0x00FF0000L
+#define NIC400_0_ASIB_1_MAX_OT__ar_max_oti_MASK                                                               0x3F000000L
+//NIC400_0_ASIB_1_MAX_COMB_OT
+#define NIC400_0_ASIB_1_MAX_COMB_OT__awar_max_otf__SHIFT                                                      0x0
+#define NIC400_0_ASIB_1_MAX_COMB_OT__awar_max_oti__SHIFT                                                      0x8
+#define NIC400_0_ASIB_1_MAX_COMB_OT__awar_max_otf_MASK                                                        0x000000FFL
+#define NIC400_0_ASIB_1_MAX_COMB_OT__awar_max_oti_MASK                                                        0x00007F00L
+//NIC400_0_ASIB_1_AW_P
+#define NIC400_0_ASIB_1_AW_P__aw_p__SHIFT                                                                     0x18
+#define NIC400_0_ASIB_1_AW_P__aw_p_MASK                                                                       0xFF000000L
+//NIC400_0_ASIB_1_AW_B
+#define NIC400_0_ASIB_1_AW_B__aw_b__SHIFT                                                                     0x0
+#define NIC400_0_ASIB_1_AW_B__aw_b_MASK                                                                       0x0000FFFFL
+//NIC400_0_ASIB_1_AW_R
+#define NIC400_0_ASIB_1_AW_R__aw_r__SHIFT                                                                     0x14
+#define NIC400_0_ASIB_1_AW_R__aw_r_MASK                                                                       0xFFF00000L
+//NIC400_0_ASIB_1_AR_P
+#define NIC400_0_ASIB_1_AR_P__ar_p__SHIFT                                                                     0x18
+#define NIC400_0_ASIB_1_AR_P__ar_p_MASK                                                                       0xFF000000L
+//NIC400_0_ASIB_1_AR_B
+#define NIC400_0_ASIB_1_AR_B__ar_b__SHIFT                                                                     0x0
+#define NIC400_0_ASIB_1_AR_B__ar_b_MASK                                                                       0x0000FFFFL
+//NIC400_0_ASIB_1_AR_R
+#define NIC400_0_ASIB_1_AR_R__ar_r__SHIFT                                                                     0x14
+#define NIC400_0_ASIB_1_AR_R__ar_r_MASK                                                                       0xFFF00000L
+//NIC400_0_ASIB_1_TARGET_FC
+#define NIC400_0_ASIB_1_TARGET_FC__aw_tgt_latency__SHIFT                                                      0x0
+#define NIC400_0_ASIB_1_TARGET_FC__ar_tgt_latency__SHIFT                                                      0x10
+#define NIC400_0_ASIB_1_TARGET_FC__aw_tgt_latency_MASK                                                        0x00000FFFL
+#define NIC400_0_ASIB_1_TARGET_FC__ar_tgt_latency_MASK                                                        0x0FFF0000L
+//NIC400_0_ASIB_1_KI_FC
+#define NIC400_0_ASIB_1_KI_FC__aw_tgt_latency__SHIFT                                                          0x0
+#define NIC400_0_ASIB_1_KI_FC__ar_tgt_latency__SHIFT                                                          0x8
+#define NIC400_0_ASIB_1_KI_FC__aw_tgt_latency_MASK                                                            0x00000007L
+#define NIC400_0_ASIB_1_KI_FC__ar_tgt_latency_MASK                                                            0x00000700L
+//NIC400_0_ASIB_1_QOS_RANGE
+#define NIC400_0_ASIB_1_QOS_RANGE__aw_min_qos__SHIFT                                                          0x0
+#define NIC400_0_ASIB_1_QOS_RANGE__aw_max_qos__SHIFT                                                          0x8
+#define NIC400_0_ASIB_1_QOS_RANGE__ar_min_qos__SHIFT                                                          0x10
+#define NIC400_0_ASIB_1_QOS_RANGE__ar_max_qos__SHIFT                                                          0x18
+#define NIC400_0_ASIB_1_QOS_RANGE__aw_min_qos_MASK                                                            0x0000000FL
+#define NIC400_0_ASIB_1_QOS_RANGE__aw_max_qos_MASK                                                            0x00000F00L
+#define NIC400_0_ASIB_1_QOS_RANGE__ar_min_qos_MASK                                                            0x000F0000L
+#define NIC400_0_ASIB_1_QOS_RANGE__ar_max_qos_MASK                                                            0x0F000000L
+//NIC400_0_IB_0_FN_MOD
+#define NIC400_0_IB_0_FN_MOD__read_iss_override__SHIFT                                                        0x0
+#define NIC400_0_IB_0_FN_MOD__write_iss_override__SHIFT                                                       0x1
+#define NIC400_0_IB_0_FN_MOD__read_iss_override_MASK                                                          0x00000001L
+#define NIC400_0_IB_0_FN_MOD__write_iss_override_MASK                                                         0x00000002L
+//NIC400_1_AMIB_0_FN_MOD_BM_ISS
+#define NIC400_1_AMIB_0_FN_MOD_BM_ISS__read_iss_override__SHIFT                                               0x0
+#define NIC400_1_AMIB_0_FN_MOD_BM_ISS__write_iss_override__SHIFT                                              0x1
+#define NIC400_1_AMIB_0_FN_MOD_BM_ISS__read_iss_override_MASK                                                 0x00000001L
+#define NIC400_1_AMIB_0_FN_MOD_BM_ISS__write_iss_override_MASK                                                0x00000002L
+//NIC400_1_AMIB_0_FN_MOD
+#define NIC400_1_AMIB_0_FN_MOD__read_iss_override__SHIFT                                                      0x0
+#define NIC400_1_AMIB_0_FN_MOD__write_iss_override__SHIFT                                                     0x1
+#define NIC400_1_AMIB_0_FN_MOD__read_iss_override_MASK                                                        0x00000001L
+#define NIC400_1_AMIB_0_FN_MOD__write_iss_override_MASK                                                       0x00000002L
+//NIC400_1_ASIB_0_FN_MOD
+#define NIC400_1_ASIB_0_FN_MOD__read_iss_override__SHIFT                                                      0x0
+#define NIC400_1_ASIB_0_FN_MOD__write_iss_override__SHIFT                                                     0x1
+#define NIC400_1_ASIB_0_FN_MOD__read_iss_override_MASK                                                        0x00000001L
+#define NIC400_1_ASIB_0_FN_MOD__write_iss_override_MASK                                                       0x00000002L
+//NIC400_1_ASIB_0_QOS_CNTL
+#define NIC400_1_ASIB_0_QOS_CNTL__en_aw_rate__SHIFT                                                           0x0
+#define NIC400_1_ASIB_0_QOS_CNTL__en_ar_rate__SHIFT                                                           0x1
+#define NIC400_1_ASIB_0_QOS_CNTL__en_awar_rate__SHIFT                                                         0x2
+#define NIC400_1_ASIB_0_QOS_CNTL__en_aw_fc__SHIFT                                                             0x3
+#define NIC400_1_ASIB_0_QOS_CNTL__en_ar_fc__SHIFT                                                             0x4
+#define NIC400_1_ASIB_0_QOS_CNTL__en_aw_ot__SHIFT                                                             0x5
+#define NIC400_1_ASIB_0_QOS_CNTL__en_ar_ot__SHIFT                                                             0x6
+#define NIC400_1_ASIB_0_QOS_CNTL__en_awar_ot__SHIFT                                                           0x7
+#define NIC400_1_ASIB_0_QOS_CNTL__mode_aw_fc__SHIFT                                                           0x10
+#define NIC400_1_ASIB_0_QOS_CNTL__mode_ar_fc__SHIFT                                                           0x14
+#define NIC400_1_ASIB_0_QOS_CNTL__en_aw_rate_MASK                                                             0x00000001L
+#define NIC400_1_ASIB_0_QOS_CNTL__en_ar_rate_MASK                                                             0x00000002L
+#define NIC400_1_ASIB_0_QOS_CNTL__en_awar_rate_MASK                                                           0x00000004L
+#define NIC400_1_ASIB_0_QOS_CNTL__en_aw_fc_MASK                                                               0x00000008L
+#define NIC400_1_ASIB_0_QOS_CNTL__en_ar_fc_MASK                                                               0x00000010L
+#define NIC400_1_ASIB_0_QOS_CNTL__en_aw_ot_MASK                                                               0x00000020L
+#define NIC400_1_ASIB_0_QOS_CNTL__en_ar_ot_MASK                                                               0x00000040L
+#define NIC400_1_ASIB_0_QOS_CNTL__en_awar_ot_MASK                                                             0x00000080L
+#define NIC400_1_ASIB_0_QOS_CNTL__mode_aw_fc_MASK                                                             0x00010000L
+#define NIC400_1_ASIB_0_QOS_CNTL__mode_ar_fc_MASK                                                             0x00100000L
+//NIC400_1_ASIB_0_MAX_OT
+#define NIC400_1_ASIB_0_MAX_OT__aw_max_otf__SHIFT                                                             0x0
+#define NIC400_1_ASIB_0_MAX_OT__aw_max_oti__SHIFT                                                             0x8
+#define NIC400_1_ASIB_0_MAX_OT__ar_max_otf__SHIFT                                                             0x10
+#define NIC400_1_ASIB_0_MAX_OT__ar_max_oti__SHIFT                                                             0x18
+#define NIC400_1_ASIB_0_MAX_OT__aw_max_otf_MASK                                                               0x000000FFL
+#define NIC400_1_ASIB_0_MAX_OT__aw_max_oti_MASK                                                               0x00003F00L
+#define NIC400_1_ASIB_0_MAX_OT__ar_max_otf_MASK                                                               0x00FF0000L
+#define NIC400_1_ASIB_0_MAX_OT__ar_max_oti_MASK                                                               0x3F000000L
+//NIC400_1_ASIB_0_MAX_COMB_OT
+#define NIC400_1_ASIB_0_MAX_COMB_OT__awar_max_otf__SHIFT                                                      0x0
+#define NIC400_1_ASIB_0_MAX_COMB_OT__awar_max_oti__SHIFT                                                      0x8
+#define NIC400_1_ASIB_0_MAX_COMB_OT__awar_max_otf_MASK                                                        0x000000FFL
+#define NIC400_1_ASIB_0_MAX_COMB_OT__awar_max_oti_MASK                                                        0x00007F00L
+//NIC400_1_ASIB_0_AW_P
+#define NIC400_1_ASIB_0_AW_P__aw_p__SHIFT                                                                     0x18
+#define NIC400_1_ASIB_0_AW_P__aw_p_MASK                                                                       0xFF000000L
+//NIC400_1_ASIB_0_AW_B
+#define NIC400_1_ASIB_0_AW_B__aw_b__SHIFT                                                                     0x0
+#define NIC400_1_ASIB_0_AW_B__aw_b_MASK                                                                       0x0000FFFFL
+//NIC400_1_ASIB_0_AW_R
+#define NIC400_1_ASIB_0_AW_R__aw_r__SHIFT                                                                     0x14
+#define NIC400_1_ASIB_0_AW_R__aw_r_MASK                                                                       0xFFF00000L
+//NIC400_1_ASIB_0_AR_P
+#define NIC400_1_ASIB_0_AR_P__ar_p__SHIFT                                                                     0x18
+#define NIC400_1_ASIB_0_AR_P__ar_p_MASK                                                                       0xFF000000L
+//NIC400_1_ASIB_0_AR_B
+#define NIC400_1_ASIB_0_AR_B__ar_b__SHIFT                                                                     0x0
+#define NIC400_1_ASIB_0_AR_B__ar_b_MASK                                                                       0x0000FFFFL
+//NIC400_1_ASIB_0_AR_R
+#define NIC400_1_ASIB_0_AR_R__ar_r__SHIFT                                                                     0x14
+#define NIC400_1_ASIB_0_AR_R__ar_r_MASK                                                                       0xFFF00000L
+//NIC400_1_ASIB_0_TARGET_FC
+#define NIC400_1_ASIB_0_TARGET_FC__aw_tgt_latency__SHIFT                                                      0x0
+#define NIC400_1_ASIB_0_TARGET_FC__ar_tgt_latency__SHIFT                                                      0x10
+#define NIC400_1_ASIB_0_TARGET_FC__aw_tgt_latency_MASK                                                        0x00000FFFL
+#define NIC400_1_ASIB_0_TARGET_FC__ar_tgt_latency_MASK                                                        0x0FFF0000L
+//NIC400_1_ASIB_0_KI_FC
+#define NIC400_1_ASIB_0_KI_FC__aw_tgt_latency__SHIFT                                                          0x0
+#define NIC400_1_ASIB_0_KI_FC__ar_tgt_latency__SHIFT                                                          0x8
+#define NIC400_1_ASIB_0_KI_FC__aw_tgt_latency_MASK                                                            0x00000007L
+#define NIC400_1_ASIB_0_KI_FC__ar_tgt_latency_MASK                                                            0x00000700L
+//NIC400_1_ASIB_0_QOS_RANGE
+#define NIC400_1_ASIB_0_QOS_RANGE__aw_min_qos__SHIFT                                                          0x0
+#define NIC400_1_ASIB_0_QOS_RANGE__aw_max_qos__SHIFT                                                          0x8
+#define NIC400_1_ASIB_0_QOS_RANGE__ar_min_qos__SHIFT                                                          0x10
+#define NIC400_1_ASIB_0_QOS_RANGE__ar_max_qos__SHIFT                                                          0x18
+#define NIC400_1_ASIB_0_QOS_RANGE__aw_min_qos_MASK                                                            0x0000000FL
+#define NIC400_1_ASIB_0_QOS_RANGE__aw_max_qos_MASK                                                            0x00000F00L
+#define NIC400_1_ASIB_0_QOS_RANGE__ar_min_qos_MASK                                                            0x000F0000L
+#define NIC400_1_ASIB_0_QOS_RANGE__ar_max_qos_MASK                                                            0x0F000000L
+//NIC400_1_ASIB_1_FN_MOD
+#define NIC400_1_ASIB_1_FN_MOD__read_iss_override__SHIFT                                                      0x0
+#define NIC400_1_ASIB_1_FN_MOD__write_iss_override__SHIFT                                                     0x1
+#define NIC400_1_ASIB_1_FN_MOD__read_iss_override_MASK                                                        0x00000001L
+#define NIC400_1_ASIB_1_FN_MOD__write_iss_override_MASK                                                       0x00000002L
+//NIC400_1_ASIB_1_QOS_CNTL
+#define NIC400_1_ASIB_1_QOS_CNTL__en_aw_rate__SHIFT                                                           0x0
+#define NIC400_1_ASIB_1_QOS_CNTL__en_ar_rate__SHIFT                                                           0x1
+#define NIC400_1_ASIB_1_QOS_CNTL__en_awar_rate__SHIFT                                                         0x2
+#define NIC400_1_ASIB_1_QOS_CNTL__en_aw_fc__SHIFT                                                             0x3
+#define NIC400_1_ASIB_1_QOS_CNTL__en_ar_fc__SHIFT                                                             0x4
+#define NIC400_1_ASIB_1_QOS_CNTL__en_aw_ot__SHIFT                                                             0x5
+#define NIC400_1_ASIB_1_QOS_CNTL__en_ar_ot__SHIFT                                                             0x6
+#define NIC400_1_ASIB_1_QOS_CNTL__en_awar_ot__SHIFT                                                           0x7
+#define NIC400_1_ASIB_1_QOS_CNTL__mode_aw_fc__SHIFT                                                           0x10
+#define NIC400_1_ASIB_1_QOS_CNTL__mode_ar_fc__SHIFT                                                           0x14
+#define NIC400_1_ASIB_1_QOS_CNTL__en_aw_rate_MASK                                                             0x00000001L
+#define NIC400_1_ASIB_1_QOS_CNTL__en_ar_rate_MASK                                                             0x00000002L
+#define NIC400_1_ASIB_1_QOS_CNTL__en_awar_rate_MASK                                                           0x00000004L
+#define NIC400_1_ASIB_1_QOS_CNTL__en_aw_fc_MASK                                                               0x00000008L
+#define NIC400_1_ASIB_1_QOS_CNTL__en_ar_fc_MASK                                                               0x00000010L
+#define NIC400_1_ASIB_1_QOS_CNTL__en_aw_ot_MASK                                                               0x00000020L
+#define NIC400_1_ASIB_1_QOS_CNTL__en_ar_ot_MASK                                                               0x00000040L
+#define NIC400_1_ASIB_1_QOS_CNTL__en_awar_ot_MASK                                                             0x00000080L
+#define NIC400_1_ASIB_1_QOS_CNTL__mode_aw_fc_MASK                                                             0x00010000L
+#define NIC400_1_ASIB_1_QOS_CNTL__mode_ar_fc_MASK                                                             0x00100000L
+//NIC400_1_ASIB_1_MAX_OT
+#define NIC400_1_ASIB_1_MAX_OT__aw_max_otf__SHIFT                                                             0x0
+#define NIC400_1_ASIB_1_MAX_OT__aw_max_oti__SHIFT                                                             0x8
+#define NIC400_1_ASIB_1_MAX_OT__ar_max_otf__SHIFT                                                             0x10
+#define NIC400_1_ASIB_1_MAX_OT__ar_max_oti__SHIFT                                                             0x18
+#define NIC400_1_ASIB_1_MAX_OT__aw_max_otf_MASK                                                               0x000000FFL
+#define NIC400_1_ASIB_1_MAX_OT__aw_max_oti_MASK                                                               0x00003F00L
+#define NIC400_1_ASIB_1_MAX_OT__ar_max_otf_MASK                                                               0x00FF0000L
+#define NIC400_1_ASIB_1_MAX_OT__ar_max_oti_MASK                                                               0x3F000000L
+//NIC400_1_ASIB_1_MAX_COMB_OT
+#define NIC400_1_ASIB_1_MAX_COMB_OT__awar_max_otf__SHIFT                                                      0x0
+#define NIC400_1_ASIB_1_MAX_COMB_OT__awar_max_oti__SHIFT                                                      0x8
+#define NIC400_1_ASIB_1_MAX_COMB_OT__awar_max_otf_MASK                                                        0x000000FFL
+#define NIC400_1_ASIB_1_MAX_COMB_OT__awar_max_oti_MASK                                                        0x00007F00L
+//NIC400_1_ASIB_1_AW_P
+#define NIC400_1_ASIB_1_AW_P__aw_p__SHIFT                                                                     0x18
+#define NIC400_1_ASIB_1_AW_P__aw_p_MASK                                                                       0xFF000000L
+//NIC400_1_ASIB_1_AW_B
+#define NIC400_1_ASIB_1_AW_B__aw_b__SHIFT                                                                     0x0
+#define NIC400_1_ASIB_1_AW_B__aw_b_MASK                                                                       0x0000FFFFL
+//NIC400_1_ASIB_1_AW_R
+#define NIC400_1_ASIB_1_AW_R__aw_r__SHIFT                                                                     0x14
+#define NIC400_1_ASIB_1_AW_R__aw_r_MASK                                                                       0xFFF00000L
+//NIC400_1_ASIB_1_AR_P
+#define NIC400_1_ASIB_1_AR_P__ar_p__SHIFT                                                                     0x18
+#define NIC400_1_ASIB_1_AR_P__ar_p_MASK                                                                       0xFF000000L
+//NIC400_1_ASIB_1_AR_B
+#define NIC400_1_ASIB_1_AR_B__ar_b__SHIFT                                                                     0x0
+#define NIC400_1_ASIB_1_AR_B__ar_b_MASK                                                                       0x0000FFFFL
+//NIC400_1_ASIB_1_AR_R
+#define NIC400_1_ASIB_1_AR_R__ar_r__SHIFT                                                                     0x14
+#define NIC400_1_ASIB_1_AR_R__ar_r_MASK                                                                       0xFFF00000L
+//NIC400_1_ASIB_1_TARGET_FC
+#define NIC400_1_ASIB_1_TARGET_FC__aw_tgt_latency__SHIFT                                                      0x0
+#define NIC400_1_ASIB_1_TARGET_FC__ar_tgt_latency__SHIFT                                                      0x10
+#define NIC400_1_ASIB_1_TARGET_FC__aw_tgt_latency_MASK                                                        0x00000FFFL
+#define NIC400_1_ASIB_1_TARGET_FC__ar_tgt_latency_MASK                                                        0x0FFF0000L
+//NIC400_1_ASIB_1_KI_FC
+#define NIC400_1_ASIB_1_KI_FC__aw_tgt_latency__SHIFT                                                          0x0
+#define NIC400_1_ASIB_1_KI_FC__ar_tgt_latency__SHIFT                                                          0x8
+#define NIC400_1_ASIB_1_KI_FC__aw_tgt_latency_MASK                                                            0x00000007L
+#define NIC400_1_ASIB_1_KI_FC__ar_tgt_latency_MASK                                                            0x00000700L
+//NIC400_1_ASIB_1_QOS_RANGE
+#define NIC400_1_ASIB_1_QOS_RANGE__aw_min_qos__SHIFT                                                          0x0
+#define NIC400_1_ASIB_1_QOS_RANGE__aw_max_qos__SHIFT                                                          0x8
+#define NIC400_1_ASIB_1_QOS_RANGE__ar_min_qos__SHIFT                                                          0x10
+#define NIC400_1_ASIB_1_QOS_RANGE__ar_max_qos__SHIFT                                                          0x18
+#define NIC400_1_ASIB_1_QOS_RANGE__aw_min_qos_MASK                                                            0x0000000FL
+#define NIC400_1_ASIB_1_QOS_RANGE__aw_max_qos_MASK                                                            0x00000F00L
+#define NIC400_1_ASIB_1_QOS_RANGE__ar_min_qos_MASK                                                            0x000F0000L
+#define NIC400_1_ASIB_1_QOS_RANGE__ar_max_qos_MASK                                                            0x0F000000L
+//NIC400_1_IB_0_FN_MOD
+#define NIC400_1_IB_0_FN_MOD__read_iss_override__SHIFT                                                        0x0
+#define NIC400_1_IB_0_FN_MOD__write_iss_override__SHIFT                                                       0x1
+#define NIC400_1_IB_0_FN_MOD__read_iss_override_MASK                                                          0x00000001L
+#define NIC400_1_IB_0_FN_MOD__write_iss_override_MASK                                                         0x00000002L
+
+
+// addressBlock: nbif0_nbif0_syshub_mmreg_syshubdec
+//SYSHUB_INDEX
+#define SYSHUB_INDEX__INDEX__SHIFT                                                                            0x0
+#define SYSHUB_INDEX__INDEX_MASK                                                                              0xFFFFFFFFL
+//SYSHUB_DATA
+#define SYSHUB_DATA__DATA__SHIFT                                                                              0x0
+#define SYSHUB_DATA__DATA_MASK                                                                                0xFFFFFFFFL
+
+
+// addressBlock: nbif0_nbif0_bif_cfg_dev0_rc_bifcfgdecp
+//BIF_CFG_DEV0_RC_VENDOR_ID
+#define BIF_CFG_DEV0_RC_VENDOR_ID__VENDOR_ID__SHIFT                                                           0x0
+#define BIF_CFG_DEV0_RC_VENDOR_ID__VENDOR_ID_MASK                                                             0xFFFFL
+//BIF_CFG_DEV0_RC_DEVICE_ID
+#define BIF_CFG_DEV0_RC_DEVICE_ID__DEVICE_ID__SHIFT                                                           0x0
+#define BIF_CFG_DEV0_RC_DEVICE_ID__DEVICE_ID_MASK                                                             0xFFFFL
+//BIF_CFG_DEV0_RC_COMMAND
+#define BIF_CFG_DEV0_RC_COMMAND__IOEN_DN__SHIFT                                                               0x0
+#define BIF_CFG_DEV0_RC_COMMAND__MEMEN_DN__SHIFT                                                              0x1
+#define BIF_CFG_DEV0_RC_COMMAND__BUS_MASTER_EN__SHIFT                                                         0x2
+#define BIF_CFG_DEV0_RC_COMMAND__SPECIAL_CYCLE_EN__SHIFT                                                      0x3
+#define BIF_CFG_DEV0_RC_COMMAND__MEM_WRITE_INVALIDATE_EN__SHIFT                                               0x4
+#define BIF_CFG_DEV0_RC_COMMAND__PAL_SNOOP_EN__SHIFT                                                          0x5
+#define BIF_CFG_DEV0_RC_COMMAND__PARITY_ERROR_RESPONSE__SHIFT                                                 0x6
+#define BIF_CFG_DEV0_RC_COMMAND__AD_STEPPING__SHIFT                                                           0x7
+#define BIF_CFG_DEV0_RC_COMMAND__SERR_EN__SHIFT                                                               0x8
+#define BIF_CFG_DEV0_RC_COMMAND__FAST_B2B_EN__SHIFT                                                           0x9
+#define BIF_CFG_DEV0_RC_COMMAND__INT_DIS__SHIFT                                                               0xa
+#define BIF_CFG_DEV0_RC_COMMAND__IOEN_DN_MASK                                                                 0x0001L
+#define BIF_CFG_DEV0_RC_COMMAND__MEMEN_DN_MASK                                                                0x0002L
+#define BIF_CFG_DEV0_RC_COMMAND__BUS_MASTER_EN_MASK                                                           0x0004L
+#define BIF_CFG_DEV0_RC_COMMAND__SPECIAL_CYCLE_EN_MASK                                                        0x0008L
+#define BIF_CFG_DEV0_RC_COMMAND__MEM_WRITE_INVALIDATE_EN_MASK                                                 0x0010L
+#define BIF_CFG_DEV0_RC_COMMAND__PAL_SNOOP_EN_MASK                                                            0x0020L
+#define BIF_CFG_DEV0_RC_COMMAND__PARITY_ERROR_RESPONSE_MASK                                                   0x0040L
+#define BIF_CFG_DEV0_RC_COMMAND__AD_STEPPING_MASK                                                             0x0080L
+#define BIF_CFG_DEV0_RC_COMMAND__SERR_EN_MASK                                                                 0x0100L
+#define BIF_CFG_DEV0_RC_COMMAND__FAST_B2B_EN_MASK                                                             0x0200L
+#define BIF_CFG_DEV0_RC_COMMAND__INT_DIS_MASK                                                                 0x0400L
+//BIF_CFG_DEV0_RC_STATUS
+#define BIF_CFG_DEV0_RC_STATUS__IMMEDIATE_READINESS__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_RC_STATUS__INT_STATUS__SHIFT                                                             0x3
+#define BIF_CFG_DEV0_RC_STATUS__CAP_LIST__SHIFT                                                               0x4
+#define BIF_CFG_DEV0_RC_STATUS__PCI_66_CAP__SHIFT                                                             0x5
+#define BIF_CFG_DEV0_RC_STATUS__FAST_BACK_CAPABLE__SHIFT                                                      0x7
+#define BIF_CFG_DEV0_RC_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                               0x8
+#define BIF_CFG_DEV0_RC_STATUS__DEVSEL_TIMING__SHIFT                                                          0x9
+#define BIF_CFG_DEV0_RC_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                    0xb
+#define BIF_CFG_DEV0_RC_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                                  0xc
+#define BIF_CFG_DEV0_RC_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                                  0xd
+#define BIF_CFG_DEV0_RC_STATUS__SIGNALED_SYSTEM_ERROR__SHIFT                                                  0xe
+#define BIF_CFG_DEV0_RC_STATUS__PARITY_ERROR_DETECTED__SHIFT                                                  0xf
+#define BIF_CFG_DEV0_RC_STATUS__IMMEDIATE_READINESS_MASK                                                      0x0001L
+#define BIF_CFG_DEV0_RC_STATUS__INT_STATUS_MASK                                                               0x0008L
+#define BIF_CFG_DEV0_RC_STATUS__CAP_LIST_MASK                                                                 0x0010L
+#define BIF_CFG_DEV0_RC_STATUS__PCI_66_CAP_MASK                                                               0x0020L
+#define BIF_CFG_DEV0_RC_STATUS__FAST_BACK_CAPABLE_MASK                                                        0x0080L
+#define BIF_CFG_DEV0_RC_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                                 0x0100L
+#define BIF_CFG_DEV0_RC_STATUS__DEVSEL_TIMING_MASK                                                            0x0600L
+#define BIF_CFG_DEV0_RC_STATUS__SIGNAL_TARGET_ABORT_MASK                                                      0x0800L
+#define BIF_CFG_DEV0_RC_STATUS__RECEIVED_TARGET_ABORT_MASK                                                    0x1000L
+#define BIF_CFG_DEV0_RC_STATUS__RECEIVED_MASTER_ABORT_MASK                                                    0x2000L
+#define BIF_CFG_DEV0_RC_STATUS__SIGNALED_SYSTEM_ERROR_MASK                                                    0x4000L
+#define BIF_CFG_DEV0_RC_STATUS__PARITY_ERROR_DETECTED_MASK                                                    0x8000L
+//BIF_CFG_DEV0_RC_REVISION_ID
+#define BIF_CFG_DEV0_RC_REVISION_ID__MINOR_REV_ID__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_RC_REVISION_ID__MAJOR_REV_ID__SHIFT                                                      0x4
+#define BIF_CFG_DEV0_RC_REVISION_ID__MINOR_REV_ID_MASK                                                        0x0FL
+#define BIF_CFG_DEV0_RC_REVISION_ID__MAJOR_REV_ID_MASK                                                        0xF0L
+//BIF_CFG_DEV0_RC_PROG_INTERFACE
+#define BIF_CFG_DEV0_RC_PROG_INTERFACE__PROG_INTERFACE__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_RC_PROG_INTERFACE__PROG_INTERFACE_MASK                                                   0xFFL
+//BIF_CFG_DEV0_RC_SUB_CLASS
+#define BIF_CFG_DEV0_RC_SUB_CLASS__SUB_CLASS__SHIFT                                                           0x0
+#define BIF_CFG_DEV0_RC_SUB_CLASS__SUB_CLASS_MASK                                                             0xFFL
+//BIF_CFG_DEV0_RC_BASE_CLASS
+#define BIF_CFG_DEV0_RC_BASE_CLASS__BASE_CLASS__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_RC_BASE_CLASS__BASE_CLASS_MASK                                                           0xFFL
+//BIF_CFG_DEV0_RC_CACHE_LINE
+#define BIF_CFG_DEV0_RC_CACHE_LINE__CACHE_LINE_SIZE__SHIFT                                                    0x0
+#define BIF_CFG_DEV0_RC_CACHE_LINE__CACHE_LINE_SIZE_MASK                                                      0xFFL
+//BIF_CFG_DEV0_RC_LATENCY
+#define BIF_CFG_DEV0_RC_LATENCY__LATENCY_TIMER__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_RC_LATENCY__LATENCY_TIMER_MASK                                                           0xFFL
+//BIF_CFG_DEV0_RC_HEADER
+#define BIF_CFG_DEV0_RC_HEADER__HEADER_TYPE__SHIFT                                                            0x0
+#define BIF_CFG_DEV0_RC_HEADER__DEVICE_TYPE__SHIFT                                                            0x7
+#define BIF_CFG_DEV0_RC_HEADER__HEADER_TYPE_MASK                                                              0x7FL
+#define BIF_CFG_DEV0_RC_HEADER__DEVICE_TYPE_MASK                                                              0x80L
+//BIF_CFG_DEV0_RC_BIST
+#define BIF_CFG_DEV0_RC_BIST__BIST_COMP__SHIFT                                                                0x0
+#define BIF_CFG_DEV0_RC_BIST__BIST_STRT__SHIFT                                                                0x6
+#define BIF_CFG_DEV0_RC_BIST__BIST_CAP__SHIFT                                                                 0x7
+#define BIF_CFG_DEV0_RC_BIST__BIST_COMP_MASK                                                                  0x0FL
+#define BIF_CFG_DEV0_RC_BIST__BIST_STRT_MASK                                                                  0x40L
+#define BIF_CFG_DEV0_RC_BIST__BIST_CAP_MASK                                                                   0x80L
+//BIF_CFG_DEV0_RC_BASE_ADDR_1
+#define BIF_CFG_DEV0_RC_BASE_ADDR_1__BASE_ADDR__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_RC_BASE_ADDR_1__BASE_ADDR_MASK                                                           0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_BASE_ADDR_2
+#define BIF_CFG_DEV0_RC_BASE_ADDR_2__BASE_ADDR__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_RC_BASE_ADDR_2__BASE_ADDR_MASK                                                           0xFFFFFFFFL
+//SUB_BUS_NUMBER_LATENCY
+#define SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS__SHIFT                                                            0x0
+#define SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS__SHIFT                                                          0x8
+#define SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM__SHIFT                                                            0x10
+#define SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER__SHIFT                                                0x18
+#define SUB_BUS_NUMBER_LATENCY__PRIMARY_BUS_MASK                                                              0x000000FFL
+#define SUB_BUS_NUMBER_LATENCY__SECONDARY_BUS_MASK                                                            0x0000FF00L
+#define SUB_BUS_NUMBER_LATENCY__SUB_BUS_NUM_MASK                                                              0x00FF0000L
+#define SUB_BUS_NUMBER_LATENCY__SECONDARY_LATENCY_TIMER_MASK                                                  0xFF000000L
+//IO_BASE_LIMIT
+#define IO_BASE_LIMIT__IO_BASE_TYPE__SHIFT                                                                    0x0
+#define IO_BASE_LIMIT__IO_BASE__SHIFT                                                                         0x4
+#define IO_BASE_LIMIT__IO_LIMIT_TYPE__SHIFT                                                                   0x8
+#define IO_BASE_LIMIT__IO_LIMIT__SHIFT                                                                        0xc
+#define IO_BASE_LIMIT__IO_BASE_TYPE_MASK                                                                      0x000FL
+#define IO_BASE_LIMIT__IO_BASE_MASK                                                                           0x00F0L
+#define IO_BASE_LIMIT__IO_LIMIT_TYPE_MASK                                                                     0x0F00L
+#define IO_BASE_LIMIT__IO_LIMIT_MASK                                                                          0xF000L
+//SECONDARY_STATUS
+#define SECONDARY_STATUS__PCI_66_CAP__SHIFT                                                                   0x5
+#define SECONDARY_STATUS__FAST_BACK_CAPABLE__SHIFT                                                            0x7
+#define SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR__SHIFT                                                     0x8
+#define SECONDARY_STATUS__DEVSEL_TIMING__SHIFT                                                                0x9
+#define SECONDARY_STATUS__SIGNAL_TARGET_ABORT__SHIFT                                                          0xb
+#define SECONDARY_STATUS__RECEIVED_TARGET_ABORT__SHIFT                                                        0xc
+#define SECONDARY_STATUS__RECEIVED_MASTER_ABORT__SHIFT                                                        0xd
+#define SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR__SHIFT                                                        0xe
+#define SECONDARY_STATUS__PARITY_ERROR_DETECTED__SHIFT                                                        0xf
+#define SECONDARY_STATUS__PCI_66_CAP_MASK                                                                     0x0020L
+#define SECONDARY_STATUS__FAST_BACK_CAPABLE_MASK                                                              0x0080L
+#define SECONDARY_STATUS__MASTER_DATA_PARITY_ERROR_MASK                                                       0x0100L
+#define SECONDARY_STATUS__DEVSEL_TIMING_MASK                                                                  0x0600L
+#define SECONDARY_STATUS__SIGNAL_TARGET_ABORT_MASK                                                            0x0800L
+#define SECONDARY_STATUS__RECEIVED_TARGET_ABORT_MASK                                                          0x1000L
+#define SECONDARY_STATUS__RECEIVED_MASTER_ABORT_MASK                                                          0x2000L
+#define SECONDARY_STATUS__RECEIVED_SYSTEM_ERROR_MASK                                                          0x4000L
+#define SECONDARY_STATUS__PARITY_ERROR_DETECTED_MASK                                                          0x8000L
+//MEM_BASE_LIMIT
+#define MEM_BASE_LIMIT__MEM_BASE_TYPE__SHIFT                                                                  0x0
+#define MEM_BASE_LIMIT__MEM_BASE_31_20__SHIFT                                                                 0x4
+#define MEM_BASE_LIMIT__MEM_LIMIT_TYPE__SHIFT                                                                 0x10
+#define MEM_BASE_LIMIT__MEM_LIMIT_31_20__SHIFT                                                                0x14
+#define MEM_BASE_LIMIT__MEM_BASE_TYPE_MASK                                                                    0x0000000FL
+#define MEM_BASE_LIMIT__MEM_BASE_31_20_MASK                                                                   0x0000FFF0L
+#define MEM_BASE_LIMIT__MEM_LIMIT_TYPE_MASK                                                                   0x000F0000L
+#define MEM_BASE_LIMIT__MEM_LIMIT_31_20_MASK                                                                  0xFFF00000L
+//PREF_BASE_LIMIT
+#define PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE__SHIFT                                                            0x0
+#define PREF_BASE_LIMIT__PREF_MEM_BASE_31_20__SHIFT                                                           0x4
+#define PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE__SHIFT                                                           0x10
+#define PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20__SHIFT                                                          0x14
+#define PREF_BASE_LIMIT__PREF_MEM_BASE_TYPE_MASK                                                              0x0000000FL
+#define PREF_BASE_LIMIT__PREF_MEM_BASE_31_20_MASK                                                             0x0000FFF0L
+#define PREF_BASE_LIMIT__PREF_MEM_LIMIT_TYPE_MASK                                                             0x000F0000L
+#define PREF_BASE_LIMIT__PREF_MEM_LIMIT_31_20_MASK                                                            0xFFF00000L
+//PREF_BASE_UPPER
+#define PREF_BASE_UPPER__PREF_BASE_UPPER__SHIFT                                                               0x0
+#define PREF_BASE_UPPER__PREF_BASE_UPPER_MASK                                                                 0xFFFFFFFFL
+//PREF_LIMIT_UPPER
+#define PREF_LIMIT_UPPER__PREF_LIMIT_UPPER__SHIFT                                                             0x0
+#define PREF_LIMIT_UPPER__PREF_LIMIT_UPPER_MASK                                                               0xFFFFFFFFL
+//IO_BASE_LIMIT_HI
+#define IO_BASE_LIMIT_HI__IO_BASE_31_16__SHIFT                                                                0x0
+#define IO_BASE_LIMIT_HI__IO_LIMIT_31_16__SHIFT                                                               0x10
+#define IO_BASE_LIMIT_HI__IO_BASE_31_16_MASK                                                                  0x0000FFFFL
+#define IO_BASE_LIMIT_HI__IO_LIMIT_31_16_MASK                                                                 0xFFFF0000L
+//BIF_CFG_DEV0_RC_CAP_PTR
+#define BIF_CFG_DEV0_RC_CAP_PTR__CAP_PTR__SHIFT                                                               0x0
+#define BIF_CFG_DEV0_RC_CAP_PTR__CAP_PTR_MASK                                                                 0xFFL
+//BIF_CFG_DEV0_RC_ROM_BASE_ADDR
+#define BIF_CFG_DEV0_RC_ROM_BASE_ADDR__ROM_ENABLE__SHIFT                                                      0x0
+#define BIF_CFG_DEV0_RC_ROM_BASE_ADDR__ROM_VALIDATION_STATUS__SHIFT                                           0x1
+#define BIF_CFG_DEV0_RC_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS__SHIFT                                          0x4
+#define BIF_CFG_DEV0_RC_ROM_BASE_ADDR__BASE_ADDR__SHIFT                                                       0xb
+#define BIF_CFG_DEV0_RC_ROM_BASE_ADDR__ROM_ENABLE_MASK                                                        0x00000001L
+#define BIF_CFG_DEV0_RC_ROM_BASE_ADDR__ROM_VALIDATION_STATUS_MASK                                             0x0000000EL
+#define BIF_CFG_DEV0_RC_ROM_BASE_ADDR__ROM_VALIDATION_DETAILS_MASK                                            0x000000F0L
+#define BIF_CFG_DEV0_RC_ROM_BASE_ADDR__BASE_ADDR_MASK                                                         0xFFFFF800L
+//BIF_CFG_DEV0_RC_INTERRUPT_LINE
+#define BIF_CFG_DEV0_RC_INTERRUPT_LINE__INTERRUPT_LINE__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_RC_INTERRUPT_LINE__INTERRUPT_LINE_MASK                                                   0xFFL
+//BIF_CFG_DEV0_RC_INTERRUPT_PIN
+#define BIF_CFG_DEV0_RC_INTERRUPT_PIN__INTERRUPT_PIN__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_RC_INTERRUPT_PIN__INTERRUPT_PIN_MASK                                                     0xFFL
+//IRQ_BRIDGE_CNTL
+#define IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN__SHIFT                                                            0x0
+#define IRQ_BRIDGE_CNTL__SERR_EN__SHIFT                                                                       0x1
+#define IRQ_BRIDGE_CNTL__ISA_EN__SHIFT                                                                        0x2
+#define IRQ_BRIDGE_CNTL__VGA_EN__SHIFT                                                                        0x3
+#define IRQ_BRIDGE_CNTL__VGA_DEC__SHIFT                                                                       0x4
+#define IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE__SHIFT                                                             0x5
+#define IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET__SHIFT                                                           0x6
+#define IRQ_BRIDGE_CNTL__FAST_B2B_EN__SHIFT                                                                   0x7
+#define IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER__SHIFT                                                         0x8
+#define IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER__SHIFT                                                       0x9
+#define IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS__SHIFT                                                          0xa
+#define IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE__SHIFT                                                     0xb
+#define IRQ_BRIDGE_CNTL__PARITY_RESPONSE_EN_MASK                                                              0x0001L
+#define IRQ_BRIDGE_CNTL__SERR_EN_MASK                                                                         0x0002L
+#define IRQ_BRIDGE_CNTL__ISA_EN_MASK                                                                          0x0004L
+#define IRQ_BRIDGE_CNTL__VGA_EN_MASK                                                                          0x0008L
+#define IRQ_BRIDGE_CNTL__VGA_DEC_MASK                                                                         0x0010L
+#define IRQ_BRIDGE_CNTL__MASTER_ABORT_MODE_MASK                                                               0x0020L
+#define IRQ_BRIDGE_CNTL__SECONDARY_BUS_RESET_MASK                                                             0x0040L
+#define IRQ_BRIDGE_CNTL__FAST_B2B_EN_MASK                                                                     0x0080L
+#define IRQ_BRIDGE_CNTL__PRIMARY_DISCARD_TIMER_MASK                                                           0x0100L
+#define IRQ_BRIDGE_CNTL__SECONDARY_DISCARD_TIMER_MASK                                                         0x0200L
+#define IRQ_BRIDGE_CNTL__DISCARD_TIMER_STATUS_MASK                                                            0x0400L
+#define IRQ_BRIDGE_CNTL__DISCARD_TIMER_SERR_ENABLE_MASK                                                       0x0800L
+//EXT_BRIDGE_CNTL
+#define EXT_BRIDGE_CNTL__IO_PORT_80_EN__SHIFT                                                                 0x0
+#define EXT_BRIDGE_CNTL__IO_PORT_80_EN_MASK                                                                   0x01L
+//BIF_CFG_DEV0_RC_PMI_CAP_LIST
+#define BIF_CFG_DEV0_RC_PMI_CAP_LIST__CAP_ID__SHIFT                                                           0x0
+#define BIF_CFG_DEV0_RC_PMI_CAP_LIST__NEXT_PTR__SHIFT                                                         0x8
+#define BIF_CFG_DEV0_RC_PMI_CAP_LIST__CAP_ID_MASK                                                             0x00FFL
+#define BIF_CFG_DEV0_RC_PMI_CAP_LIST__NEXT_PTR_MASK                                                           0xFF00L
+//BIF_CFG_DEV0_RC_PMI_CAP
+#define BIF_CFG_DEV0_RC_PMI_CAP__VERSION__SHIFT                                                               0x0
+#define BIF_CFG_DEV0_RC_PMI_CAP__PME_CLOCK__SHIFT                                                             0x3
+#define BIF_CFG_DEV0_RC_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0__SHIFT                                   0x4
+#define BIF_CFG_DEV0_RC_PMI_CAP__DEV_SPECIFIC_INIT__SHIFT                                                     0x5
+#define BIF_CFG_DEV0_RC_PMI_CAP__AUX_CURRENT__SHIFT                                                           0x6
+#define BIF_CFG_DEV0_RC_PMI_CAP__D1_SUPPORT__SHIFT                                                            0x9
+#define BIF_CFG_DEV0_RC_PMI_CAP__D2_SUPPORT__SHIFT                                                            0xa
+#define BIF_CFG_DEV0_RC_PMI_CAP__PME_SUPPORT__SHIFT                                                           0xb
+#define BIF_CFG_DEV0_RC_PMI_CAP__VERSION_MASK                                                                 0x0007L
+#define BIF_CFG_DEV0_RC_PMI_CAP__PME_CLOCK_MASK                                                               0x0008L
+#define BIF_CFG_DEV0_RC_PMI_CAP__IMMEDIATE_READINESS_ON_RETURN_TO_D0_MASK                                     0x0010L
+#define BIF_CFG_DEV0_RC_PMI_CAP__DEV_SPECIFIC_INIT_MASK                                                       0x0020L
+#define BIF_CFG_DEV0_RC_PMI_CAP__AUX_CURRENT_MASK                                                             0x01C0L
+#define BIF_CFG_DEV0_RC_PMI_CAP__D1_SUPPORT_MASK                                                              0x0200L
+#define BIF_CFG_DEV0_RC_PMI_CAP__D2_SUPPORT_MASK                                                              0x0400L
+#define BIF_CFG_DEV0_RC_PMI_CAP__PME_SUPPORT_MASK                                                             0xF800L
+//BIF_CFG_DEV0_RC_PMI_STATUS_CNTL
+#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__POWER_STATE__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__NO_SOFT_RESET__SHIFT                                                 0x3
+#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__PME_EN__SHIFT                                                        0x8
+#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__DATA_SELECT__SHIFT                                                   0x9
+#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__DATA_SCALE__SHIFT                                                    0xd
+#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__PME_STATUS__SHIFT                                                    0xf
+#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__B2_B3_SUPPORT__SHIFT                                                 0x16
+#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__BUS_PWR_EN__SHIFT                                                    0x17
+#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__PMI_DATA__SHIFT                                                      0x18
+#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__POWER_STATE_MASK                                                     0x00000003L
+#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__NO_SOFT_RESET_MASK                                                   0x00000008L
+#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__PME_EN_MASK                                                          0x00000100L
+#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__DATA_SELECT_MASK                                                     0x00001E00L
+#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__DATA_SCALE_MASK                                                      0x00006000L
+#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__PME_STATUS_MASK                                                      0x00008000L
+#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__B2_B3_SUPPORT_MASK                                                   0x00400000L
+#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__BUS_PWR_EN_MASK                                                      0x00800000L
+#define BIF_CFG_DEV0_RC_PMI_STATUS_CNTL__PMI_DATA_MASK                                                        0xFF000000L
+//BIF_CFG_DEV0_RC_PCIE_CAP_LIST
+#define BIF_CFG_DEV0_RC_PCIE_CAP_LIST__CAP_ID__SHIFT                                                          0x0
+#define BIF_CFG_DEV0_RC_PCIE_CAP_LIST__NEXT_PTR__SHIFT                                                        0x8
+#define BIF_CFG_DEV0_RC_PCIE_CAP_LIST__CAP_ID_MASK                                                            0x00FFL
+#define BIF_CFG_DEV0_RC_PCIE_CAP_LIST__NEXT_PTR_MASK                                                          0xFF00L
+//BIF_CFG_DEV0_RC_PCIE_CAP
+#define BIF_CFG_DEV0_RC_PCIE_CAP__VERSION__SHIFT                                                              0x0
+#define BIF_CFG_DEV0_RC_PCIE_CAP__DEVICE_TYPE__SHIFT                                                          0x4
+#define BIF_CFG_DEV0_RC_PCIE_CAP__SLOT_IMPLEMENTED__SHIFT                                                     0x8
+#define BIF_CFG_DEV0_RC_PCIE_CAP__INT_MESSAGE_NUM__SHIFT                                                      0x9
+#define BIF_CFG_DEV0_RC_PCIE_CAP__FLIT_MODE_SUPPORT__SHIFT                                                    0xf
+#define BIF_CFG_DEV0_RC_PCIE_CAP__VERSION_MASK                                                                0x000FL
+#define BIF_CFG_DEV0_RC_PCIE_CAP__DEVICE_TYPE_MASK                                                            0x00F0L
+#define BIF_CFG_DEV0_RC_PCIE_CAP__SLOT_IMPLEMENTED_MASK                                                       0x0100L
+#define BIF_CFG_DEV0_RC_PCIE_CAP__INT_MESSAGE_NUM_MASK                                                        0x3E00L
+#define BIF_CFG_DEV0_RC_PCIE_CAP__FLIT_MODE_SUPPORT_MASK                                                      0x8000L
+//BIF_CFG_DEV0_RC_DEVICE_CAP
+#define BIF_CFG_DEV0_RC_DEVICE_CAP__MAX_PAYLOAD_SUPPORT__SHIFT                                                0x0
+#define BIF_CFG_DEV0_RC_DEVICE_CAP__PHANTOM_FUNC__SHIFT                                                       0x3
+#define BIF_CFG_DEV0_RC_DEVICE_CAP__EXTENDED_TAG__SHIFT                                                       0x5
+#define BIF_CFG_DEV0_RC_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY__SHIFT                                             0x6
+#define BIF_CFG_DEV0_RC_DEVICE_CAP__L1_ACCEPTABLE_LATENCY__SHIFT                                              0x9
+#define BIF_CFG_DEV0_RC_DEVICE_CAP__ROLE_BASED_ERR_REPORTING__SHIFT                                           0xf
+#define BIF_CFG_DEV0_RC_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE__SHIFT                                           0x10
+#define BIF_CFG_DEV0_RC_DEVICE_CAP__RX_MPS_FIXED__SHIFT                                                       0x11
+#define BIF_CFG_DEV0_RC_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT__SHIFT                                          0x12
+#define BIF_CFG_DEV0_RC_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE__SHIFT                                          0x1a
+#define BIF_CFG_DEV0_RC_DEVICE_CAP__FLR_CAPABLE__SHIFT                                                        0x1c
+#define BIF_CFG_DEV0_RC_DEVICE_CAP__MIXED_MPS_SUPPORTED__SHIFT                                                0x1d
+#define BIF_CFG_DEV0_RC_DEVICE_CAP__MAX_PAYLOAD_SUPPORT_MASK                                                  0x00000007L
+#define BIF_CFG_DEV0_RC_DEVICE_CAP__PHANTOM_FUNC_MASK                                                         0x00000018L
+#define BIF_CFG_DEV0_RC_DEVICE_CAP__EXTENDED_TAG_MASK                                                         0x00000020L
+#define BIF_CFG_DEV0_RC_DEVICE_CAP__L0S_ACCEPTABLE_LATENCY_MASK                                               0x000001C0L
+#define BIF_CFG_DEV0_RC_DEVICE_CAP__L1_ACCEPTABLE_LATENCY_MASK                                                0x00000E00L
+#define BIF_CFG_DEV0_RC_DEVICE_CAP__ROLE_BASED_ERR_REPORTING_MASK                                             0x00008000L
+#define BIF_CFG_DEV0_RC_DEVICE_CAP__ERR_COR_SUBCLASS_CAPABLE_MASK                                             0x00010000L
+#define BIF_CFG_DEV0_RC_DEVICE_CAP__RX_MPS_FIXED_MASK                                                         0x00020000L
+#define BIF_CFG_DEV0_RC_DEVICE_CAP__CAPTURED_SLOT_POWER_LIMIT_MASK                                            0x03FC0000L
+#define BIF_CFG_DEV0_RC_DEVICE_CAP__CAPTURED_SLOT_POWER_SCALE_MASK                                            0x0C000000L
+#define BIF_CFG_DEV0_RC_DEVICE_CAP__FLR_CAPABLE_MASK                                                          0x10000000L
+#define BIF_CFG_DEV0_RC_DEVICE_CAP__MIXED_MPS_SUPPORTED_MASK                                                  0x20000000L
+//BIF_CFG_DEV0_RC_DEVICE_CNTL
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL__CORR_ERR_EN__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL__NON_FATAL_ERR_EN__SHIFT                                                  0x1
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL__FATAL_ERR_EN__SHIFT                                                      0x2
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL__USR_REPORT_EN__SHIFT                                                     0x3
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL__RELAXED_ORD_EN__SHIFT                                                    0x4
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL__MAX_PAYLOAD_SIZE__SHIFT                                                  0x5
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL__EXTENDED_TAG_EN__SHIFT                                                   0x8
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL__PHANTOM_FUNC_EN__SHIFT                                                   0x9
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL__AUX_POWER_PM_EN__SHIFT                                                   0xa
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL__NO_SNOOP_EN__SHIFT                                                       0xb
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL__MAX_READ_REQUEST_SIZE__SHIFT                                             0xc
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN__SHIFT                                               0xf
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL__CORR_ERR_EN_MASK                                                         0x0001L
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL__NON_FATAL_ERR_EN_MASK                                                    0x0002L
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL__FATAL_ERR_EN_MASK                                                        0x0004L
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL__USR_REPORT_EN_MASK                                                       0x0008L
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL__RELAXED_ORD_EN_MASK                                                      0x0010L
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL__MAX_PAYLOAD_SIZE_MASK                                                    0x00E0L
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL__EXTENDED_TAG_EN_MASK                                                     0x0100L
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL__PHANTOM_FUNC_EN_MASK                                                     0x0200L
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL__AUX_POWER_PM_EN_MASK                                                     0x0400L
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL__NO_SNOOP_EN_MASK                                                         0x0800L
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL__MAX_READ_REQUEST_SIZE_MASK                                               0x7000L
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL__BRIDGE_CFG_RETRY_EN_MASK                                                 0x8000L
+//BIF_CFG_DEV0_RC_DEVICE_STATUS
+#define BIF_CFG_DEV0_RC_DEVICE_STATUS__CORR_ERR__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_RC_DEVICE_STATUS__NON_FATAL_ERR__SHIFT                                                   0x1
+#define BIF_CFG_DEV0_RC_DEVICE_STATUS__FATAL_ERR__SHIFT                                                       0x2
+#define BIF_CFG_DEV0_RC_DEVICE_STATUS__USR_DETECTED__SHIFT                                                    0x3
+#define BIF_CFG_DEV0_RC_DEVICE_STATUS__AUX_PWR__SHIFT                                                         0x4
+#define BIF_CFG_DEV0_RC_DEVICE_STATUS__TRANSACTIONS_PEND__SHIFT                                               0x5
+#define BIF_CFG_DEV0_RC_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED__SHIFT                                   0x6
+#define BIF_CFG_DEV0_RC_DEVICE_STATUS__CORR_ERR_MASK                                                          0x0001L
+#define BIF_CFG_DEV0_RC_DEVICE_STATUS__NON_FATAL_ERR_MASK                                                     0x0002L
+#define BIF_CFG_DEV0_RC_DEVICE_STATUS__FATAL_ERR_MASK                                                         0x0004L
+#define BIF_CFG_DEV0_RC_DEVICE_STATUS__USR_DETECTED_MASK                                                      0x0008L
+#define BIF_CFG_DEV0_RC_DEVICE_STATUS__AUX_PWR_MASK                                                           0x0010L
+#define BIF_CFG_DEV0_RC_DEVICE_STATUS__TRANSACTIONS_PEND_MASK                                                 0x0020L
+#define BIF_CFG_DEV0_RC_DEVICE_STATUS__EMER_POWER_REDUCTION_DETECTED_MASK                                     0x0040L
+//BIF_CFG_DEV0_RC_LINK_CAP
+#define BIF_CFG_DEV0_RC_LINK_CAP__LINK_SPEED__SHIFT                                                           0x0
+#define BIF_CFG_DEV0_RC_LINK_CAP__LINK_WIDTH__SHIFT                                                           0x4
+#define BIF_CFG_DEV0_RC_LINK_CAP__PM_SUPPORT__SHIFT                                                           0xa
+#define BIF_CFG_DEV0_RC_LINK_CAP__L0S_EXIT_LATENCY__SHIFT                                                     0xc
+#define BIF_CFG_DEV0_RC_LINK_CAP__L1_EXIT_LATENCY__SHIFT                                                      0xf
+#define BIF_CFG_DEV0_RC_LINK_CAP__CLOCK_POWER_MANAGEMENT__SHIFT                                               0x12
+#define BIF_CFG_DEV0_RC_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING__SHIFT                                          0x13
+#define BIF_CFG_DEV0_RC_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE__SHIFT                                          0x14
+#define BIF_CFG_DEV0_RC_LINK_CAP__LINK_BW_NOTIFICATION_CAP__SHIFT                                             0x15
+#define BIF_CFG_DEV0_RC_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE__SHIFT                                          0x16
+#define BIF_CFG_DEV0_RC_LINK_CAP__PORT_NUMBER__SHIFT                                                          0x18
+#define BIF_CFG_DEV0_RC_LINK_CAP__LINK_SPEED_MASK                                                             0x0000000FL
+#define BIF_CFG_DEV0_RC_LINK_CAP__LINK_WIDTH_MASK                                                             0x000003F0L
+#define BIF_CFG_DEV0_RC_LINK_CAP__PM_SUPPORT_MASK                                                             0x00000C00L
+#define BIF_CFG_DEV0_RC_LINK_CAP__L0S_EXIT_LATENCY_MASK                                                       0x00007000L
+#define BIF_CFG_DEV0_RC_LINK_CAP__L1_EXIT_LATENCY_MASK                                                        0x00038000L
+#define BIF_CFG_DEV0_RC_LINK_CAP__CLOCK_POWER_MANAGEMENT_MASK                                                 0x00040000L
+#define BIF_CFG_DEV0_RC_LINK_CAP__SURPRISE_DOWN_ERR_REPORTING_MASK                                            0x00080000L
+#define BIF_CFG_DEV0_RC_LINK_CAP__DL_ACTIVE_REPORTING_CAPABLE_MASK                                            0x00100000L
+#define BIF_CFG_DEV0_RC_LINK_CAP__LINK_BW_NOTIFICATION_CAP_MASK                                               0x00200000L
+#define BIF_CFG_DEV0_RC_LINK_CAP__ASPM_OPTIONALITY_COMPLIANCE_MASK                                            0x00400000L
+#define BIF_CFG_DEV0_RC_LINK_CAP__PORT_NUMBER_MASK                                                            0xFF000000L
+//BIF_CFG_DEV0_RC_LINK_CNTL
+#define BIF_CFG_DEV0_RC_LINK_CNTL__PM_CONTROL__SHIFT                                                          0x0
+#define BIF_CFG_DEV0_RC_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B__SHIFT                                        0x2
+#define BIF_CFG_DEV0_RC_LINK_CNTL__READ_CPL_BOUNDARY__SHIFT                                                   0x3
+#define BIF_CFG_DEV0_RC_LINK_CNTL__LINK_DIS__SHIFT                                                            0x4
+#define BIF_CFG_DEV0_RC_LINK_CNTL__RETRAIN_LINK__SHIFT                                                        0x5
+#define BIF_CFG_DEV0_RC_LINK_CNTL__COMMON_CLOCK_CFG__SHIFT                                                    0x6
+#define BIF_CFG_DEV0_RC_LINK_CNTL__EXTENDED_SYNC__SHIFT                                                       0x7
+#define BIF_CFG_DEV0_RC_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN__SHIFT                                           0x8
+#define BIF_CFG_DEV0_RC_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE__SHIFT                                         0x9
+#define BIF_CFG_DEV0_RC_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN__SHIFT                                           0xa
+#define BIF_CFG_DEV0_RC_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN__SHIFT                                           0xb
+#define BIF_CFG_DEV0_RC_LINK_CNTL__DRS_SIGNALING_CONTROL__SHIFT                                               0xe
+#define BIF_CFG_DEV0_RC_LINK_CNTL__PM_CONTROL_MASK                                                            0x0003L
+#define BIF_CFG_DEV0_RC_LINK_CNTL__PTM_PROP_DELAY_ADAPT_INTER_B_MASK                                          0x0004L
+#define BIF_CFG_DEV0_RC_LINK_CNTL__READ_CPL_BOUNDARY_MASK                                                     0x0008L
+#define BIF_CFG_DEV0_RC_LINK_CNTL__LINK_DIS_MASK                                                              0x0010L
+#define BIF_CFG_DEV0_RC_LINK_CNTL__RETRAIN_LINK_MASK                                                          0x0020L
+#define BIF_CFG_DEV0_RC_LINK_CNTL__COMMON_CLOCK_CFG_MASK                                                      0x0040L
+#define BIF_CFG_DEV0_RC_LINK_CNTL__EXTENDED_SYNC_MASK                                                         0x0080L
+#define BIF_CFG_DEV0_RC_LINK_CNTL__CLOCK_POWER_MANAGEMENT_EN_MASK                                             0x0100L
+#define BIF_CFG_DEV0_RC_LINK_CNTL__HW_AUTONOMOUS_WIDTH_DISABLE_MASK                                           0x0200L
+#define BIF_CFG_DEV0_RC_LINK_CNTL__LINK_BW_MANAGEMENT_INT_EN_MASK                                             0x0400L
+#define BIF_CFG_DEV0_RC_LINK_CNTL__LINK_AUTONOMOUS_BW_INT_EN_MASK                                             0x0800L
+#define BIF_CFG_DEV0_RC_LINK_CNTL__DRS_SIGNALING_CONTROL_MASK                                                 0xC000L
+//BIF_CFG_DEV0_RC_LINK_STATUS
+#define BIF_CFG_DEV0_RC_LINK_STATUS__CURRENT_LINK_SPEED__SHIFT                                                0x0
+#define BIF_CFG_DEV0_RC_LINK_STATUS__NEGOTIATED_LINK_WIDTH__SHIFT                                             0x4
+#define BIF_CFG_DEV0_RC_LINK_STATUS__LINK_TRAINING__SHIFT                                                     0xb
+#define BIF_CFG_DEV0_RC_LINK_STATUS__SLOT_CLOCK_CFG__SHIFT                                                    0xc
+#define BIF_CFG_DEV0_RC_LINK_STATUS__DL_ACTIVE__SHIFT                                                         0xd
+#define BIF_CFG_DEV0_RC_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS__SHIFT                                         0xe
+#define BIF_CFG_DEV0_RC_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS__SHIFT                                         0xf
+#define BIF_CFG_DEV0_RC_LINK_STATUS__CURRENT_LINK_SPEED_MASK                                                  0x000FL
+#define BIF_CFG_DEV0_RC_LINK_STATUS__NEGOTIATED_LINK_WIDTH_MASK                                               0x03F0L
+#define BIF_CFG_DEV0_RC_LINK_STATUS__LINK_TRAINING_MASK                                                       0x0800L
+#define BIF_CFG_DEV0_RC_LINK_STATUS__SLOT_CLOCK_CFG_MASK                                                      0x1000L
+#define BIF_CFG_DEV0_RC_LINK_STATUS__DL_ACTIVE_MASK                                                           0x2000L
+#define BIF_CFG_DEV0_RC_LINK_STATUS__LINK_BW_MANAGEMENT_STATUS_MASK                                           0x4000L
+#define BIF_CFG_DEV0_RC_LINK_STATUS__LINK_AUTONOMOUS_BW_STATUS_MASK                                           0x8000L
+//SLOT_CAP
+#define SLOT_CAP__ATTN_BUTTON_PRESENT__SHIFT                                                                  0x0
+#define SLOT_CAP__PWR_CONTROLLER_PRESENT__SHIFT                                                               0x1
+#define SLOT_CAP__MRL_SENSOR_PRESENT__SHIFT                                                                   0x2
+#define SLOT_CAP__ATTN_INDICATOR_PRESENT__SHIFT                                                               0x3
+#define SLOT_CAP__PWR_INDICATOR_PRESENT__SHIFT                                                                0x4
+#define SLOT_CAP__HOTPLUG_SURPRISE__SHIFT                                                                     0x5
+#define SLOT_CAP__HOTPLUG_CAPABLE__SHIFT                                                                      0x6
+#define SLOT_CAP__SLOT_PWR_LIMIT_VALUE__SHIFT                                                                 0x7
+#define SLOT_CAP__SLOT_PWR_LIMIT_SCALE__SHIFT                                                                 0xf
+#define SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT__SHIFT                                                        0x11
+#define SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED__SHIFT                                                       0x12
+#define SLOT_CAP__PHYSICAL_SLOT_NUM__SHIFT                                                                    0x13
+#define SLOT_CAP__ATTN_BUTTON_PRESENT_MASK                                                                    0x00000001L
+#define SLOT_CAP__PWR_CONTROLLER_PRESENT_MASK                                                                 0x00000002L
+#define SLOT_CAP__MRL_SENSOR_PRESENT_MASK                                                                     0x00000004L
+#define SLOT_CAP__ATTN_INDICATOR_PRESENT_MASK                                                                 0x00000008L
+#define SLOT_CAP__PWR_INDICATOR_PRESENT_MASK                                                                  0x00000010L
+#define SLOT_CAP__HOTPLUG_SURPRISE_MASK                                                                       0x00000020L
+#define SLOT_CAP__HOTPLUG_CAPABLE_MASK                                                                        0x00000040L
+#define SLOT_CAP__SLOT_PWR_LIMIT_VALUE_MASK                                                                   0x00007F80L
+#define SLOT_CAP__SLOT_PWR_LIMIT_SCALE_MASK                                                                   0x00018000L
+#define SLOT_CAP__ELECTROMECH_INTERLOCK_PRESENT_MASK                                                          0x00020000L
+#define SLOT_CAP__NO_COMMAND_COMPLETED_SUPPORTED_MASK                                                         0x00040000L
+#define SLOT_CAP__PHYSICAL_SLOT_NUM_MASK                                                                      0xFFF80000L
+//SLOT_CNTL
+#define SLOT_CNTL__ATTN_BUTTON_PRESSED_EN__SHIFT                                                              0x0
+#define SLOT_CNTL__PWR_FAULT_DETECTED_EN__SHIFT                                                               0x1
+#define SLOT_CNTL__MRL_SENSOR_CHANGED_EN__SHIFT                                                               0x2
+#define SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN__SHIFT                                                          0x3
+#define SLOT_CNTL__COMMAND_COMPLETED_INTR_EN__SHIFT                                                           0x4
+#define SLOT_CNTL__HOTPLUG_INTR_EN__SHIFT                                                                     0x5
+#define SLOT_CNTL__ATTN_INDICATOR_CNTL__SHIFT                                                                 0x6
+#define SLOT_CNTL__PWR_INDICATOR_CNTL__SHIFT                                                                  0x8
+#define SLOT_CNTL__PWR_CONTROLLER_CNTL__SHIFT                                                                 0xa
+#define SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL__SHIFT                                                          0xb
+#define SLOT_CNTL__DL_STATE_CHANGED_EN__SHIFT                                                                 0xc
+#define SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE__SHIFT                                                         0xd
+#define SLOT_CNTL__INBAND_PD_DISABLE__SHIFT                                                                   0xe
+#define SLOT_CNTL__ATTN_BUTTON_PRESSED_EN_MASK                                                                0x0001L
+#define SLOT_CNTL__PWR_FAULT_DETECTED_EN_MASK                                                                 0x0002L
+#define SLOT_CNTL__MRL_SENSOR_CHANGED_EN_MASK                                                                 0x0004L
+#define SLOT_CNTL__PRESENCE_DETECT_CHANGED_EN_MASK                                                            0x0008L
+#define SLOT_CNTL__COMMAND_COMPLETED_INTR_EN_MASK                                                             0x0010L
+#define SLOT_CNTL__HOTPLUG_INTR_EN_MASK                                                                       0x0020L
+#define SLOT_CNTL__ATTN_INDICATOR_CNTL_MASK                                                                   0x00C0L
+#define SLOT_CNTL__PWR_INDICATOR_CNTL_MASK                                                                    0x0300L
+#define SLOT_CNTL__PWR_CONTROLLER_CNTL_MASK                                                                   0x0400L
+#define SLOT_CNTL__ELECTROMECH_INTERLOCK_CNTL_MASK                                                            0x0800L
+#define SLOT_CNTL__DL_STATE_CHANGED_EN_MASK                                                                   0x1000L
+#define SLOT_CNTL__AUTO_SLOT_PWR_LIMIT_DISABLE_MASK                                                           0x2000L
+#define SLOT_CNTL__INBAND_PD_DISABLE_MASK                                                                     0x4000L
+//SLOT_STATUS
+#define SLOT_STATUS__ATTN_BUTTON_PRESSED__SHIFT                                                               0x0
+#define SLOT_STATUS__PWR_FAULT_DETECTED__SHIFT                                                                0x1
+#define SLOT_STATUS__MRL_SENSOR_CHANGED__SHIFT                                                                0x2
+#define SLOT_STATUS__PRESENCE_DETECT_CHANGED__SHIFT                                                           0x3
+#define SLOT_STATUS__COMMAND_COMPLETED__SHIFT                                                                 0x4
+#define SLOT_STATUS__MRL_SENSOR_STATE__SHIFT                                                                  0x5
+#define SLOT_STATUS__PRESENCE_DETECT_STATE__SHIFT                                                             0x6
+#define SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS__SHIFT                                                      0x7
+#define SLOT_STATUS__DL_STATE_CHANGED__SHIFT                                                                  0x8
+#define SLOT_STATUS__ATTN_BUTTON_PRESSED_MASK                                                                 0x0001L
+#define SLOT_STATUS__PWR_FAULT_DETECTED_MASK                                                                  0x0002L
+#define SLOT_STATUS__MRL_SENSOR_CHANGED_MASK                                                                  0x0004L
+#define SLOT_STATUS__PRESENCE_DETECT_CHANGED_MASK                                                             0x0008L
+#define SLOT_STATUS__COMMAND_COMPLETED_MASK                                                                   0x0010L
+#define SLOT_STATUS__MRL_SENSOR_STATE_MASK                                                                    0x0020L
+#define SLOT_STATUS__PRESENCE_DETECT_STATE_MASK                                                               0x0040L
+#define SLOT_STATUS__ELECTROMECH_INTERLOCK_STATUS_MASK                                                        0x0080L
+#define SLOT_STATUS__DL_STATE_CHANGED_MASK                                                                    0x0100L
+//ROOT_CNTL
+#define ROOT_CNTL__SERR_ON_CORR_ERR_EN__SHIFT                                                                 0x0
+#define ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN__SHIFT                                                             0x1
+#define ROOT_CNTL__SERR_ON_FATAL_ERR_EN__SHIFT                                                                0x2
+#define ROOT_CNTL__PM_INTERRUPT_EN__SHIFT                                                                     0x3
+#define ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN__SHIFT                                                          0x4
+#define ROOT_CNTL__SERR_ON_CORR_ERR_EN_MASK                                                                   0x0001L
+#define ROOT_CNTL__SERR_ON_NONFATAL_ERR_EN_MASK                                                               0x0002L
+#define ROOT_CNTL__SERR_ON_FATAL_ERR_EN_MASK                                                                  0x0004L
+#define ROOT_CNTL__PM_INTERRUPT_EN_MASK                                                                       0x0008L
+#define ROOT_CNTL__CRS_SOFTWARE_VISIBILITY_EN_MASK                                                            0x0010L
+//ROOT_CAP
+#define ROOT_CAP__CRS_SOFTWARE_VISIBILITY__SHIFT                                                              0x0
+#define ROOT_CAP__CRS_SOFTWARE_VISIBILITY_MASK                                                                0x0001L
+//ROOT_STATUS
+#define ROOT_STATUS__PME_REQUESTOR_ID__SHIFT                                                                  0x0
+#define ROOT_STATUS__PME_STATUS__SHIFT                                                                        0x10
+#define ROOT_STATUS__PME_PENDING__SHIFT                                                                       0x11
+#define ROOT_STATUS__PME_REQUESTOR_ID_MASK                                                                    0x0000FFFFL
+#define ROOT_STATUS__PME_STATUS_MASK                                                                          0x00010000L
+#define ROOT_STATUS__PME_PENDING_MASK                                                                         0x00020000L
+//BIF_CFG_DEV0_RC_DEVICE_CAP2
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED__SHIFT                                       0x0
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED__SHIFT                                         0x4
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED__SHIFT                                          0x5
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED__SHIFT                                        0x6
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED__SHIFT                                        0x7
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED__SHIFT                                        0x8
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED__SHIFT                                            0x9
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING__SHIFT                                         0xa
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__LTR_SUPPORTED__SHIFT                                                     0xb
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__TPH_CPLR_SUPPORTED__SHIFT                                                0xc
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__LN_SYSTEM_CLS__SHIFT                                                     0xe
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED__SHIFT                                   0x10
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED__SHIFT                                   0x11
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__OBFF_SUPPORTED__SHIFT                                                    0x12
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED__SHIFT                                      0x14
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED__SHIFT                                      0x15
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES__SHIFT                                          0x16
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED__SHIFT                                    0x18
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ__SHIFT                                     0x1a
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__FRS_SUPPORTED__SHIFT                                                     0x1f
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__CPL_TIMEOUT_RANGE_SUPPORTED_MASK                                         0x0000000FL
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__CPL_TIMEOUT_DIS_SUPPORTED_MASK                                           0x00000010L
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__ARI_FORWARDING_SUPPORTED_MASK                                            0x00000020L
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__ATOMICOP_ROUTING_SUPPORTED_MASK                                          0x00000040L
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__ATOMICOP_32CMPLT_SUPPORTED_MASK                                          0x00000080L
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__ATOMICOP_64CMPLT_SUPPORTED_MASK                                          0x00000100L
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__CAS128_CMPLT_SUPPORTED_MASK                                              0x00000200L
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__NO_RO_ENABLED_P2P_PASSING_MASK                                           0x00000400L
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__LTR_SUPPORTED_MASK                                                       0x00000800L
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__TPH_CPLR_SUPPORTED_MASK                                                  0x00003000L
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__LN_SYSTEM_CLS_MASK                                                       0x0000C000L
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__TEN_BIT_TAG_COMPLETER_SUPPORTED_MASK                                     0x00010000L
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__TEN_BIT_TAG_REQUESTER_SUPPORTED_MASK                                     0x00020000L
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__OBFF_SUPPORTED_MASK                                                      0x000C0000L
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__EXTENDED_FMT_FIELD_SUPPORTED_MASK                                        0x00100000L
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__END_END_TLP_PREFIX_SUPPORTED_MASK                                        0x00200000L
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__MAX_END_END_TLP_PREFIXES_MASK                                            0x00C00000L
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__EMER_POWER_REDUCTION_SUPPORTED_MASK                                      0x03000000L
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__EMER_POWER_REDUCTION_INIT_REQ_MASK                                       0x04000000L
+#define BIF_CFG_DEV0_RC_DEVICE_CAP2__FRS_SUPPORTED_MASK                                                       0x80000000L
+//BIF_CFG_DEV0_RC_DEVICE_CNTL2
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__CPL_TIMEOUT_VALUE__SHIFT                                                0x0
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__CPL_TIMEOUT_DIS__SHIFT                                                  0x4
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__ARI_FORWARDING_EN__SHIFT                                                0x5
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__ATOMICOP_REQUEST_EN__SHIFT                                              0x6
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING__SHIFT                                         0x7
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__IDO_REQUEST_ENABLE__SHIFT                                               0x8
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__IDO_COMPLETION_ENABLE__SHIFT                                            0x9
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__LTR_EN__SHIFT                                                           0xa
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST__SHIFT                                     0xb
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE__SHIFT                                     0xc
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__OBFF_EN__SHIFT                                                          0xd
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING__SHIFT                                      0xf
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__CPL_TIMEOUT_VALUE_MASK                                                  0x000FL
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__CPL_TIMEOUT_DIS_MASK                                                    0x0010L
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__ARI_FORWARDING_EN_MASK                                                  0x0020L
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__ATOMICOP_REQUEST_EN_MASK                                                0x0040L
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__ATOMICOP_EGRESS_BLOCKING_MASK                                           0x0080L
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__IDO_REQUEST_ENABLE_MASK                                                 0x0100L
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__IDO_COMPLETION_ENABLE_MASK                                              0x0200L
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__LTR_EN_MASK                                                             0x0400L
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__EMER_POWER_REDUCTION_REQUEST_MASK                                       0x0800L
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__TEN_BIT_TAG_REQUESTER_ENABLE_MASK                                       0x1000L
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__OBFF_EN_MASK                                                            0x6000L
+#define BIF_CFG_DEV0_RC_DEVICE_CNTL2__END_END_TLP_PREFIX_BLOCKING_MASK                                        0x8000L
+//BIF_CFG_DEV0_RC_DEVICE_STATUS2
+#define BIF_CFG_DEV0_RC_DEVICE_STATUS2__RESERVED__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_RC_DEVICE_STATUS2__RESERVED_MASK                                                         0xFFFFL
+//BIF_CFG_DEV0_RC_LINK_CAP2
+#define BIF_CFG_DEV0_RC_LINK_CAP2__SUPPORTED_LINK_SPEED__SHIFT                                                0x1
+#define BIF_CFG_DEV0_RC_LINK_CAP2__CROSSLINK_SUPPORTED__SHIFT                                                 0x8
+#define BIF_CFG_DEV0_RC_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT__SHIFT                                            0x9
+#define BIF_CFG_DEV0_RC_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT__SHIFT                                            0x10
+#define BIF_CFG_DEV0_RC_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT__SHIFT                                           0x17
+#define BIF_CFG_DEV0_RC_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT__SHIFT                                           0x18
+#define BIF_CFG_DEV0_RC_LINK_CAP2__DRS_SUPPORTED__SHIFT                                                       0x1f
+#define BIF_CFG_DEV0_RC_LINK_CAP2__SUPPORTED_LINK_SPEED_MASK                                                  0x000000FEL
+#define BIF_CFG_DEV0_RC_LINK_CAP2__CROSSLINK_SUPPORTED_MASK                                                   0x00000100L
+#define BIF_CFG_DEV0_RC_LINK_CAP2__LOWER_SKP_OS_GEN_SUPPORT_MASK                                              0x0000FE00L
+#define BIF_CFG_DEV0_RC_LINK_CAP2__LOWER_SKP_OS_RCV_SUPPORT_MASK                                              0x007F0000L
+#define BIF_CFG_DEV0_RC_LINK_CAP2__RTM1_PRESENCE_DET_SUPPORT_MASK                                             0x00800000L
+#define BIF_CFG_DEV0_RC_LINK_CAP2__RTM2_PRESENCE_DET_SUPPORT_MASK                                             0x01000000L
+#define BIF_CFG_DEV0_RC_LINK_CAP2__DRS_SUPPORTED_MASK                                                         0x80000000L
+//BIF_CFG_DEV0_RC_LINK_CNTL2
+#define BIF_CFG_DEV0_RC_LINK_CNTL2__TARGET_LINK_SPEED__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_RC_LINK_CNTL2__ENTER_COMPLIANCE__SHIFT                                                   0x4
+#define BIF_CFG_DEV0_RC_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE__SHIFT                                        0x5
+#define BIF_CFG_DEV0_RC_LINK_CNTL2__SELECTABLE_DEEMPHASIS__SHIFT                                              0x6
+#define BIF_CFG_DEV0_RC_LINK_CNTL2__XMIT_MARGIN__SHIFT                                                        0x7
+#define BIF_CFG_DEV0_RC_LINK_CNTL2__ENTER_MOD_COMPLIANCE__SHIFT                                               0xa
+#define BIF_CFG_DEV0_RC_LINK_CNTL2__COMPLIANCE_SOS__SHIFT                                                     0xb
+#define BIF_CFG_DEV0_RC_LINK_CNTL2__COMPLIANCE_DEEMPHASIS__SHIFT                                              0xc
+#define BIF_CFG_DEV0_RC_LINK_CNTL2__TARGET_LINK_SPEED_MASK                                                    0x000FL
+#define BIF_CFG_DEV0_RC_LINK_CNTL2__ENTER_COMPLIANCE_MASK                                                     0x0010L
+#define BIF_CFG_DEV0_RC_LINK_CNTL2__HW_AUTONOMOUS_SPEED_DISABLE_MASK                                          0x0020L
+#define BIF_CFG_DEV0_RC_LINK_CNTL2__SELECTABLE_DEEMPHASIS_MASK                                                0x0040L
+#define BIF_CFG_DEV0_RC_LINK_CNTL2__XMIT_MARGIN_MASK                                                          0x0380L
+#define BIF_CFG_DEV0_RC_LINK_CNTL2__ENTER_MOD_COMPLIANCE_MASK                                                 0x0400L
+#define BIF_CFG_DEV0_RC_LINK_CNTL2__COMPLIANCE_SOS_MASK                                                       0x0800L
+#define BIF_CFG_DEV0_RC_LINK_CNTL2__COMPLIANCE_DEEMPHASIS_MASK                                                0xF000L
+//BIF_CFG_DEV0_RC_LINK_STATUS2
+#define BIF_CFG_DEV0_RC_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL__SHIFT                                             0x0
+#define BIF_CFG_DEV0_RC_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT__SHIFT                                        0x1
+#define BIF_CFG_DEV0_RC_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT__SHIFT                                  0x2
+#define BIF_CFG_DEV0_RC_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT__SHIFT                                  0x3
+#define BIF_CFG_DEV0_RC_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT__SHIFT                                  0x4
+#define BIF_CFG_DEV0_RC_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT__SHIFT                                    0x5
+#define BIF_CFG_DEV0_RC_LINK_STATUS2__RTM1_PRESENCE_DET__SHIFT                                                0x6
+#define BIF_CFG_DEV0_RC_LINK_STATUS2__RTM2_PRESENCE_DET__SHIFT                                                0x7
+#define BIF_CFG_DEV0_RC_LINK_STATUS2__CROSSLINK_RESOLUTION__SHIFT                                             0x8
+#define BIF_CFG_DEV0_RC_LINK_STATUS2__FLIT_MODE_STATUS__SHIFT                                                 0xa
+#define BIF_CFG_DEV0_RC_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE__SHIFT                                    0xc
+#define BIF_CFG_DEV0_RC_LINK_STATUS2__DRS_MESSAGE_RECEIVED__SHIFT                                             0xf
+#define BIF_CFG_DEV0_RC_LINK_STATUS2__CUR_DEEMPHASIS_LEVEL_MASK                                               0x0001L
+#define BIF_CFG_DEV0_RC_LINK_STATUS2__EQUALIZATION_COMPLETE_8GT_MASK                                          0x0002L
+#define BIF_CFG_DEV0_RC_LINK_STATUS2__EQUALIZATION_PHASE1_SUCCESS_8GT_MASK                                    0x0004L
+#define BIF_CFG_DEV0_RC_LINK_STATUS2__EQUALIZATION_PHASE2_SUCCESS_8GT_MASK                                    0x0008L
+#define BIF_CFG_DEV0_RC_LINK_STATUS2__EQUALIZATION_PHASE3_SUCCESS_8GT_MASK                                    0x0010L
+#define BIF_CFG_DEV0_RC_LINK_STATUS2__LINK_EQUALIZATION_REQUEST_8GT_MASK                                      0x0020L
+#define BIF_CFG_DEV0_RC_LINK_STATUS2__RTM1_PRESENCE_DET_MASK                                                  0x0040L
+#define BIF_CFG_DEV0_RC_LINK_STATUS2__RTM2_PRESENCE_DET_MASK                                                  0x0080L
+#define BIF_CFG_DEV0_RC_LINK_STATUS2__CROSSLINK_RESOLUTION_MASK                                               0x0300L
+#define BIF_CFG_DEV0_RC_LINK_STATUS2__FLIT_MODE_STATUS_MASK                                                   0x0400L
+#define BIF_CFG_DEV0_RC_LINK_STATUS2__DOWNSTREAM_COMPONENT_PRESENCE_MASK                                      0x7000L
+#define BIF_CFG_DEV0_RC_LINK_STATUS2__DRS_MESSAGE_RECEIVED_MASK                                               0x8000L
+//SLOT_CAP2
+#define SLOT_CAP2__INBAND_PD_DISABLE_SUPPORTED__SHIFT                                                         0x0
+#define SLOT_CAP2__INBAND_PD_DISABLE_SUPPORTED_MASK                                                           0x00000001L
+//SLOT_CNTL2
+#define SLOT_CNTL2__RESERVED__SHIFT                                                                           0x0
+#define SLOT_CNTL2__RESERVED_MASK                                                                             0xFFFFL
+//SLOT_STATUS2
+#define SLOT_STATUS2__RESERVED__SHIFT                                                                         0x0
+#define SLOT_STATUS2__RESERVED_MASK                                                                           0xFFFFL
+//BIF_CFG_DEV0_RC_MSI_CAP_LIST
+#define BIF_CFG_DEV0_RC_MSI_CAP_LIST__CAP_ID__SHIFT                                                           0x0
+#define BIF_CFG_DEV0_RC_MSI_CAP_LIST__NEXT_PTR__SHIFT                                                         0x8
+#define BIF_CFG_DEV0_RC_MSI_CAP_LIST__CAP_ID_MASK                                                             0x00FFL
+#define BIF_CFG_DEV0_RC_MSI_CAP_LIST__NEXT_PTR_MASK                                                           0xFF00L
+//BIF_CFG_DEV0_RC_MSI_MSG_CNTL
+#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_EN__SHIFT                                                           0x0
+#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_MULTI_CAP__SHIFT                                                    0x1
+#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_MULTI_EN__SHIFT                                                     0x4
+#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_64BIT__SHIFT                                                        0x7
+#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP__SHIFT                                        0x8
+#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP__SHIFT                                             0x9
+#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN__SHIFT                                              0xa
+#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_EN_MASK                                                             0x0001L
+#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_MULTI_CAP_MASK                                                      0x000EL
+#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_MULTI_EN_MASK                                                       0x0070L
+#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_64BIT_MASK                                                          0x0080L
+#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_PERVECTOR_MASKING_CAP_MASK                                          0x0100L
+#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_CAP_MASK                                               0x0200L
+#define BIF_CFG_DEV0_RC_MSI_MSG_CNTL__MSI_EXT_MSG_DATA_EN_MASK                                                0x0400L
+//BIF_CFG_DEV0_RC_MSI_MSG_ADDR_LO
+#define BIF_CFG_DEV0_RC_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO__SHIFT                                               0x2
+#define BIF_CFG_DEV0_RC_MSI_MSG_ADDR_LO__MSI_MSG_ADDR_LO_MASK                                                 0xFFFFFFFCL
+//BIF_CFG_DEV0_RC_MSI_MSG_ADDR_HI
+#define BIF_CFG_DEV0_RC_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI__SHIFT                                               0x0
+#define BIF_CFG_DEV0_RC_MSI_MSG_ADDR_HI__MSI_MSG_ADDR_HI_MASK                                                 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_MSI_MSG_DATA
+#define BIF_CFG_DEV0_RC_MSI_MSG_DATA__MSI_DATA__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_RC_MSI_MSG_DATA__MSI_DATA_MASK                                                           0xFFFFL
+//BIF_CFG_DEV0_RC_MSI_EXT_MSG_DATA
+#define BIF_CFG_DEV0_RC_MSI_EXT_MSG_DATA__MSI_EXT_DATA__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_RC_MSI_EXT_MSG_DATA__MSI_EXT_DATA_MASK                                                   0xFFFFL
+//BIF_CFG_DEV0_RC_MSI_MSG_DATA_64
+#define BIF_CFG_DEV0_RC_MSI_MSG_DATA_64__MSI_DATA_64__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_RC_MSI_MSG_DATA_64__MSI_DATA_64_MASK                                                     0xFFFFL
+//BIF_CFG_DEV0_RC_MSI_EXT_MSG_DATA_64
+#define BIF_CFG_DEV0_RC_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64__SHIFT                                           0x0
+#define BIF_CFG_DEV0_RC_MSI_EXT_MSG_DATA_64__MSI_EXT_DATA_64_MASK                                             0xFFFFL
+//SSID_CAP_LIST
+#define SSID_CAP_LIST__CAP_ID__SHIFT                                                                          0x0
+#define SSID_CAP_LIST__NEXT_PTR__SHIFT                                                                        0x8
+#define SSID_CAP_LIST__CAP_ID_MASK                                                                            0x00FFL
+#define SSID_CAP_LIST__NEXT_PTR_MASK                                                                          0xFF00L
+//SSID_CAP
+#define SSID_CAP__SUBSYSTEM_VENDOR_ID__SHIFT                                                                  0x0
+#define SSID_CAP__SUBSYSTEM_ID__SHIFT                                                                         0x10
+#define SSID_CAP__SUBSYSTEM_VENDOR_ID_MASK                                                                    0x0000FFFFL
+#define SSID_CAP__SUBSYSTEM_ID_MASK                                                                           0xFFFF0000L
+//BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID__SHIFT                                      0x0
+#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER__SHIFT                                     0x10
+#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                    0x14
+#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_ID_MASK                                        0x0000FFFFL
+#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__CAP_VER_MASK                                       0x000F0000L
+#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_ENH_CAP_LIST__NEXT_PTR_MASK                                      0xFFF00000L
+//BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_HDR
+#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV__SHIFT                                             0x10
+#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH__SHIFT                                          0x14
+#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_ID_MASK                                                0x0000FFFFL
+#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_REV_MASK                                               0x000F0000L
+#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC_HDR__VSEC_LENGTH_MASK                                            0xFFF00000L
+//BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC1
+#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC1__SCRATCH__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC1__SCRATCH_MASK                                                   0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC2
+#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC2__SCRATCH__SHIFT                                                 0x0
+#define BIF_CFG_DEV0_RC_PCIE_VENDOR_SPECIFIC2__SCRATCH_MASK                                                   0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_PCIE_SECONDARY_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_RC_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
+#define BIF_CFG_DEV0_RC_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
+#define BIF_CFG_DEV0_RC_PCIE_SECONDARY_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV0_RC_PCIE_SECONDARY_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
+#define BIF_CFG_DEV0_RC_PCIE_SECONDARY_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
+//BIF_CFG_DEV0_RC_PCIE_LINK_CNTL3
+#define BIF_CFG_DEV0_RC_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION__SHIFT                                          0x0
+#define BIF_CFG_DEV0_RC_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN__SHIFT                                  0x1
+#define BIF_CFG_DEV0_RC_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN__SHIFT                                       0x9
+#define BIF_CFG_DEV0_RC_PCIE_LINK_CNTL3__PERFORM_EQUALIZATION_MASK                                            0x00000001L
+#define BIF_CFG_DEV0_RC_PCIE_LINK_CNTL3__LINK_EQUALIZATION_REQ_INT_EN_MASK                                    0x00000002L
+#define BIF_CFG_DEV0_RC_PCIE_LINK_CNTL3__ENABLE_LOWER_SKP_OS_GEN_MASK                                         0x0000FE00L
+//BIF_CFG_DEV0_RC_PCIE_LANE_ERROR_STATUS
+#define BIF_CFG_DEV0_RC_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS__SHIFT                                 0x0
+#define BIF_CFG_DEV0_RC_PCIE_LANE_ERROR_STATUS__LANE_ERROR_STATUS_BITS_MASK                                   0x0000FFFFL
+//BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0x4
+#define BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                     0x8
+#define BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT                0xc
+#define BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                     0x000FL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x0070L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                       0x0F00L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_0_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                  0x7000L
+//BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0x4
+#define BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                     0x8
+#define BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT                0xc
+#define BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                     0x000FL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x0070L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                       0x0F00L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_1_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                  0x7000L
+//BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0x4
+#define BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                     0x8
+#define BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT                0xc
+#define BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                     0x000FL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x0070L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                       0x0F00L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_2_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                  0x7000L
+//BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0x4
+#define BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                     0x8
+#define BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT                0xc
+#define BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                     0x000FL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x0070L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                       0x0F00L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_3_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                  0x7000L
+//BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0x4
+#define BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                     0x8
+#define BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT                0xc
+#define BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                     0x000FL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x0070L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                       0x0F00L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_4_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                  0x7000L
+//BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0x4
+#define BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                     0x8
+#define BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT                0xc
+#define BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                     0x000FL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x0070L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                       0x0F00L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_5_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                  0x7000L
+//BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0x4
+#define BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                     0x8
+#define BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT                0xc
+#define BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                     0x000FL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x0070L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                       0x0F00L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_6_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                  0x7000L
+//BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0x4
+#define BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                     0x8
+#define BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT                0xc
+#define BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                     0x000FL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x0070L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                       0x0F00L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_7_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                  0x7000L
+//BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0x4
+#define BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                     0x8
+#define BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT                0xc
+#define BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                     0x000FL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x0070L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                       0x0F00L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_8_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                  0x7000L
+//BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                   0x0
+#define BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT              0x4
+#define BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                     0x8
+#define BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT                0xc
+#define BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                     0x000FL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                0x0070L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                       0x0F00L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_9_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                  0x7000L
+//BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
+#define BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
+#define BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
+#define BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
+#define BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_10_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
+//BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
+#define BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
+#define BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
+#define BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
+#define BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_11_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
+//BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
+#define BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
+#define BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
+#define BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
+#define BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_12_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
+//BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
+#define BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
+#define BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
+#define BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
+#define BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_13_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
+//BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
+#define BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
+#define BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
+#define BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
+#define BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_14_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
+//BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET__SHIFT                  0x0
+#define BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT             0x4
+#define BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET__SHIFT                    0x8
+#define BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT__SHIFT               0xc
+#define BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_TX_PRESET_MASK                    0x000FL
+#define BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL__DOWNSTREAM_PORT_8GT_RX_PRESET_HINT_MASK               0x0070L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_TX_PRESET_MASK                      0x0F00L
+#define BIF_CFG_DEV0_RC_PCIE_LANE_15_EQUALIZATION_CNTL__UPSTREAM_PORT_8GT_RX_PRESET_HINT_MASK                 0x7000L
+//BIF_CFG_DEV0_RC_PCIE_PHY_16GT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID__SHIFT                                             0x0
+#define BIF_CFG_DEV0_RC_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER__SHIFT                                            0x10
+#define BIF_CFG_DEV0_RC_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                           0x14
+#define BIF_CFG_DEV0_RC_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_ID_MASK                                               0x0000FFFFL
+#define BIF_CFG_DEV0_RC_PCIE_PHY_16GT_ENH_CAP_LIST__CAP_VER_MASK                                              0x000F0000L
+#define BIF_CFG_DEV0_RC_PCIE_PHY_16GT_ENH_CAP_LIST__NEXT_PTR_MASK                                             0xFFF00000L
+//BIF_CFG_DEV0_RC_LINK_CAP_16GT
+#define BIF_CFG_DEV0_RC_LINK_CAP_16GT__RESERVED__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_RC_LINK_CAP_16GT__RESERVED_MASK                                                          0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_LINK_CNTL_16GT
+#define BIF_CFG_DEV0_RC_LINK_CNTL_16GT__RESERVED__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_RC_LINK_CNTL_16GT__RESERVED_MASK                                                         0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_LINK_STATUS_16GT
+#define BIF_CFG_DEV0_RC_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT__SHIFT                                   0x0
+#define BIF_CFG_DEV0_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT__SHIFT                             0x1
+#define BIF_CFG_DEV0_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT__SHIFT                             0x2
+#define BIF_CFG_DEV0_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT__SHIFT                             0x3
+#define BIF_CFG_DEV0_RC_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT__SHIFT                               0x4
+#define BIF_CFG_DEV0_RC_LINK_STATUS_16GT__EQUALIZATION_COMPLETE_16GT_MASK                                     0x00000001L
+#define BIF_CFG_DEV0_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE1_SUCCESS_16GT_MASK                               0x00000002L
+#define BIF_CFG_DEV0_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE2_SUCCESS_16GT_MASK                               0x00000004L
+#define BIF_CFG_DEV0_RC_LINK_STATUS_16GT__EQUALIZATION_PHASE3_SUCCESS_16GT_MASK                               0x00000008L
+#define BIF_CFG_DEV0_RC_LINK_STATUS_16GT__LINK_EQUALIZATION_REQUEST_16GT_MASK                                 0x00000010L
+//BIF_CFG_DEV0_RC_LOCAL_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_RC_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS__SHIFT           0x0
+#define BIF_CFG_DEV0_RC_LOCAL_PARITY_MISMATCH_STATUS_16GT__LOCAL_PARITY_MISMATCH_STATUS_BITS_MASK             0x0000FFFFL
+//BIF_CFG_DEV0_RC_RTM1_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_RC_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS__SHIFT             0x0
+#define BIF_CFG_DEV0_RC_RTM1_PARITY_MISMATCH_STATUS_16GT__RTM1_PARITY_MISMATCH_STATUS_BITS_MASK               0x0000FFFFL
+//BIF_CFG_DEV0_RC_RTM2_PARITY_MISMATCH_STATUS_16GT
+#define BIF_CFG_DEV0_RC_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS__SHIFT             0x0
+#define BIF_CFG_DEV0_RC_RTM2_PARITY_MISMATCH_STATUS_16GT__RTM2_PARITY_MISMATCH_STATUS_BITS_MASK               0x0000FFFFL
+//BIF_CFG_DEV0_RC_LANE_0_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET__SHIFT                       0x0
+#define BIF_CFG_DEV0_RC_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET__SHIFT                       0x4
+#define BIF_CFG_DEV0_RC_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_DSP_16GT_TX_PRESET_MASK                         0x0FL
+#define BIF_CFG_DEV0_RC_LANE_0_EQUALIZATION_CNTL_16GT__LANE_0_USP_16GT_TX_PRESET_MASK                         0xF0L
+//BIF_CFG_DEV0_RC_LANE_1_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET__SHIFT                       0x0
+#define BIF_CFG_DEV0_RC_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET__SHIFT                       0x4
+#define BIF_CFG_DEV0_RC_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_DSP_16GT_TX_PRESET_MASK                         0x0FL
+#define BIF_CFG_DEV0_RC_LANE_1_EQUALIZATION_CNTL_16GT__LANE_1_USP_16GT_TX_PRESET_MASK                         0xF0L
+//BIF_CFG_DEV0_RC_LANE_2_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET__SHIFT                       0x0
+#define BIF_CFG_DEV0_RC_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET__SHIFT                       0x4
+#define BIF_CFG_DEV0_RC_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_DSP_16GT_TX_PRESET_MASK                         0x0FL
+#define BIF_CFG_DEV0_RC_LANE_2_EQUALIZATION_CNTL_16GT__LANE_2_USP_16GT_TX_PRESET_MASK                         0xF0L
+//BIF_CFG_DEV0_RC_LANE_3_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET__SHIFT                       0x0
+#define BIF_CFG_DEV0_RC_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET__SHIFT                       0x4
+#define BIF_CFG_DEV0_RC_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_DSP_16GT_TX_PRESET_MASK                         0x0FL
+#define BIF_CFG_DEV0_RC_LANE_3_EQUALIZATION_CNTL_16GT__LANE_3_USP_16GT_TX_PRESET_MASK                         0xF0L
+//BIF_CFG_DEV0_RC_LANE_4_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET__SHIFT                       0x0
+#define BIF_CFG_DEV0_RC_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET__SHIFT                       0x4
+#define BIF_CFG_DEV0_RC_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_DSP_16GT_TX_PRESET_MASK                         0x0FL
+#define BIF_CFG_DEV0_RC_LANE_4_EQUALIZATION_CNTL_16GT__LANE_4_USP_16GT_TX_PRESET_MASK                         0xF0L
+//BIF_CFG_DEV0_RC_LANE_5_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET__SHIFT                       0x0
+#define BIF_CFG_DEV0_RC_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET__SHIFT                       0x4
+#define BIF_CFG_DEV0_RC_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_DSP_16GT_TX_PRESET_MASK                         0x0FL
+#define BIF_CFG_DEV0_RC_LANE_5_EQUALIZATION_CNTL_16GT__LANE_5_USP_16GT_TX_PRESET_MASK                         0xF0L
+//BIF_CFG_DEV0_RC_LANE_6_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET__SHIFT                       0x0
+#define BIF_CFG_DEV0_RC_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET__SHIFT                       0x4
+#define BIF_CFG_DEV0_RC_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_DSP_16GT_TX_PRESET_MASK                         0x0FL
+#define BIF_CFG_DEV0_RC_LANE_6_EQUALIZATION_CNTL_16GT__LANE_6_USP_16GT_TX_PRESET_MASK                         0xF0L
+//BIF_CFG_DEV0_RC_LANE_7_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET__SHIFT                       0x0
+#define BIF_CFG_DEV0_RC_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET__SHIFT                       0x4
+#define BIF_CFG_DEV0_RC_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_DSP_16GT_TX_PRESET_MASK                         0x0FL
+#define BIF_CFG_DEV0_RC_LANE_7_EQUALIZATION_CNTL_16GT__LANE_7_USP_16GT_TX_PRESET_MASK                         0xF0L
+//BIF_CFG_DEV0_RC_LANE_8_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET__SHIFT                       0x0
+#define BIF_CFG_DEV0_RC_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET__SHIFT                       0x4
+#define BIF_CFG_DEV0_RC_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_DSP_16GT_TX_PRESET_MASK                         0x0FL
+#define BIF_CFG_DEV0_RC_LANE_8_EQUALIZATION_CNTL_16GT__LANE_8_USP_16GT_TX_PRESET_MASK                         0xF0L
+//BIF_CFG_DEV0_RC_LANE_9_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET__SHIFT                       0x0
+#define BIF_CFG_DEV0_RC_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET__SHIFT                       0x4
+#define BIF_CFG_DEV0_RC_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_DSP_16GT_TX_PRESET_MASK                         0x0FL
+#define BIF_CFG_DEV0_RC_LANE_9_EQUALIZATION_CNTL_16GT__LANE_9_USP_16GT_TX_PRESET_MASK                         0xF0L
+//BIF_CFG_DEV0_RC_LANE_10_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET__SHIFT                     0x0
+#define BIF_CFG_DEV0_RC_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET__SHIFT                     0x4
+#define BIF_CFG_DEV0_RC_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_DSP_16GT_TX_PRESET_MASK                       0x0FL
+#define BIF_CFG_DEV0_RC_LANE_10_EQUALIZATION_CNTL_16GT__LANE_10_USP_16GT_TX_PRESET_MASK                       0xF0L
+//BIF_CFG_DEV0_RC_LANE_11_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET__SHIFT                     0x0
+#define BIF_CFG_DEV0_RC_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET__SHIFT                     0x4
+#define BIF_CFG_DEV0_RC_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_DSP_16GT_TX_PRESET_MASK                       0x0FL
+#define BIF_CFG_DEV0_RC_LANE_11_EQUALIZATION_CNTL_16GT__LANE_11_USP_16GT_TX_PRESET_MASK                       0xF0L
+//BIF_CFG_DEV0_RC_LANE_12_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET__SHIFT                     0x0
+#define BIF_CFG_DEV0_RC_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET__SHIFT                     0x4
+#define BIF_CFG_DEV0_RC_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_DSP_16GT_TX_PRESET_MASK                       0x0FL
+#define BIF_CFG_DEV0_RC_LANE_12_EQUALIZATION_CNTL_16GT__LANE_12_USP_16GT_TX_PRESET_MASK                       0xF0L
+//BIF_CFG_DEV0_RC_LANE_13_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET__SHIFT                     0x0
+#define BIF_CFG_DEV0_RC_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET__SHIFT                     0x4
+#define BIF_CFG_DEV0_RC_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_DSP_16GT_TX_PRESET_MASK                       0x0FL
+#define BIF_CFG_DEV0_RC_LANE_13_EQUALIZATION_CNTL_16GT__LANE_13_USP_16GT_TX_PRESET_MASK                       0xF0L
+//BIF_CFG_DEV0_RC_LANE_14_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET__SHIFT                     0x0
+#define BIF_CFG_DEV0_RC_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET__SHIFT                     0x4
+#define BIF_CFG_DEV0_RC_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_DSP_16GT_TX_PRESET_MASK                       0x0FL
+#define BIF_CFG_DEV0_RC_LANE_14_EQUALIZATION_CNTL_16GT__LANE_14_USP_16GT_TX_PRESET_MASK                       0xF0L
+//BIF_CFG_DEV0_RC_LANE_15_EQUALIZATION_CNTL_16GT
+#define BIF_CFG_DEV0_RC_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET__SHIFT                     0x0
+#define BIF_CFG_DEV0_RC_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET__SHIFT                     0x4
+#define BIF_CFG_DEV0_RC_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_DSP_16GT_TX_PRESET_MASK                       0x0FL
+#define BIF_CFG_DEV0_RC_LANE_15_EQUALIZATION_CNTL_16GT__LANE_15_USP_16GT_TX_PRESET_MASK                       0xF0L
+//BIF_CFG_DEV0_RC_PCIE_PHY_32GT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_ID__SHIFT                                             0x0
+#define BIF_CFG_DEV0_RC_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_VER__SHIFT                                            0x10
+#define BIF_CFG_DEV0_RC_PCIE_PHY_32GT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                           0x14
+#define BIF_CFG_DEV0_RC_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_ID_MASK                                               0x0000FFFFL
+#define BIF_CFG_DEV0_RC_PCIE_PHY_32GT_ENH_CAP_LIST__CAP_VER_MASK                                              0x000F0000L
+#define BIF_CFG_DEV0_RC_PCIE_PHY_32GT_ENH_CAP_LIST__NEXT_PTR_MASK                                             0xFFF00000L
+//BIF_CFG_DEV0_RC_LINK_CAP_32GT
+#define BIF_CFG_DEV0_RC_LINK_CAP_32GT__EQ_BYPASS_TO_HIGHEST_RATE_SUPPORTED__SHIFT                             0x0
+#define BIF_CFG_DEV0_RC_LINK_CAP_32GT__NO_EQ_NEEDED_SUPPORTED__SHIFT                                          0x1
+#define BIF_CFG_DEV0_RC_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE0_SUPPORTED__SHIFT                               0x8
+#define BIF_CFG_DEV0_RC_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE1_SUPPORTED__SHIFT                               0x9
+#define BIF_CFG_DEV0_RC_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE2_SUPPORTED__SHIFT                               0xa
+#define BIF_CFG_DEV0_RC_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES__SHIFT                                0xb
+#define BIF_CFG_DEV0_RC_LINK_CAP_32GT__EQ_BYPASS_TO_HIGHEST_RATE_SUPPORTED_MASK                               0x00000001L
+#define BIF_CFG_DEV0_RC_LINK_CAP_32GT__NO_EQ_NEEDED_SUPPORTED_MASK                                            0x00000002L
+#define BIF_CFG_DEV0_RC_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE0_SUPPORTED_MASK                                 0x00000100L
+#define BIF_CFG_DEV0_RC_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE1_SUPPORTED_MASK                                 0x00000200L
+#define BIF_CFG_DEV0_RC_LINK_CAP_32GT__MODIFIED_TS_USAGE_MODE2_SUPPORTED_MASK                                 0x00000400L
+#define BIF_CFG_DEV0_RC_LINK_CAP_32GT__MODIFIED_TS_RESERVED_USAGE_MODES_MASK                                  0x0000F800L
+//BIF_CFG_DEV0_RC_LINK_CNTL_32GT
+#define BIF_CFG_DEV0_RC_LINK_CNTL_32GT__EQ_BYPASS_TO_HIGHEST_RATE_DIS__SHIFT                                  0x0
+#define BIF_CFG_DEV0_RC_LINK_CNTL_32GT__NO_EQ_NEEDED_DIS__SHIFT                                               0x1
+#define BIF_CFG_DEV0_RC_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SEL__SHIFT                                     0x8
+#define BIF_CFG_DEV0_RC_LINK_CNTL_32GT__EQ_BYPASS_TO_HIGHEST_RATE_DIS_MASK                                    0x00000001L
+#define BIF_CFG_DEV0_RC_LINK_CNTL_32GT__NO_EQ_NEEDED_DIS_MASK                                                 0x00000002L
+#define BIF_CFG_DEV0_RC_LINK_CNTL_32GT__MODIFIED_TS_USAGE_MODE_SEL_MASK                                       0x00000700L
+//BIF_CFG_DEV0_RC_LINK_STATUS_32GT
+#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT__SHIFT                                   0x0
+#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT__SHIFT                             0x1
+#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT__SHIFT                             0x2
+#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT__SHIFT                             0x3
+#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT__SHIFT                               0x4
+#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED__SHIFT                                         0x5
+#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOR_CNTL__SHIFT                         0x6
+#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON__SHIFT                                     0x8
+#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST__SHIFT                                  0x9
+#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__NO_EQ_NEEDED_RECEIVED__SHIFT                                        0xa
+#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__EQUALIZATION_COMPLETE_32GT_MASK                                     0x00000001L
+#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__EQUALIZATION_PHASE1_SUCCESS_32GT_MASK                               0x00000002L
+#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__EQUALIZATION_PHASE2_SUCCESS_32GT_MASK                               0x00000004L
+#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__EQUALIZATION_PHASE3_SUCCESS_32GT_MASK                               0x00000008L
+#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__LINK_EQUALIZATION_REQUEST_32GT_MASK                                 0x00000010L
+#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__MODIFIED_TS_RECEIVED_MASK                                           0x00000020L
+#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__RECEIVED_ENHANCED_LINK_BEHAVIOR_CNTL_MASK                           0x000000C0L
+#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__TRANSMITTER_PRECODING_ON_MASK                                       0x00000100L
+#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__TRANSMITTER_PRECODE_REQUEST_MASK                                    0x00000200L
+#define BIF_CFG_DEV0_RC_LINK_STATUS_32GT__NO_EQ_NEEDED_RECEIVED_MASK                                          0x00000400L
+//BIF_CFG_DEV0_RC_RECEIVED_MODIFIED_TS_DATA1
+#define BIF_CFG_DEV0_RC_RECEIVED_MODIFIED_TS_DATA1__USAGE_MODE__SHIFT                                         0x0
+#define BIF_CFG_DEV0_RC_RECEIVED_MODIFIED_TS_DATA1__INFOR1__SHIFT                                             0x3
+#define BIF_CFG_DEV0_RC_RECEIVED_MODIFIED_TS_DATA1__VENDORID__SHIFT                                           0x10
+#define BIF_CFG_DEV0_RC_RECEIVED_MODIFIED_TS_DATA1__USAGE_MODE_MASK                                           0x00000007L
+#define BIF_CFG_DEV0_RC_RECEIVED_MODIFIED_TS_DATA1__INFOR1_MASK                                               0x0000FFF8L
+#define BIF_CFG_DEV0_RC_RECEIVED_MODIFIED_TS_DATA1__VENDORID_MASK                                             0xFFFF0000L
+//BIF_CFG_DEV0_RC_RECEIVED_MODIFIED_TS_DATA2
+#define BIF_CFG_DEV0_RC_RECEIVED_MODIFIED_TS_DATA2__INFOR2__SHIFT                                             0x0
+#define BIF_CFG_DEV0_RC_RECEIVED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS__SHIFT              0x18
+#define BIF_CFG_DEV0_RC_RECEIVED_MODIFIED_TS_DATA2__INFOR2_MASK                                               0x00FFFFFFL
+#define BIF_CFG_DEV0_RC_RECEIVED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS_MASK                0x03000000L
+//BIF_CFG_DEV0_RC_TRANSMITTED_MODIFIED_TS_DATA1
+#define BIF_CFG_DEV0_RC_TRANSMITTED_MODIFIED_TS_DATA1__USAGE_MODE__SHIFT                                      0x0
+#define BIF_CFG_DEV0_RC_TRANSMITTED_MODIFIED_TS_DATA1__INFOR1__SHIFT                                          0x3
+#define BIF_CFG_DEV0_RC_TRANSMITTED_MODIFIED_TS_DATA1__VENDORID__SHIFT                                        0x10
+#define BIF_CFG_DEV0_RC_TRANSMITTED_MODIFIED_TS_DATA1__USAGE_MODE_MASK                                        0x00000007L
+#define BIF_CFG_DEV0_RC_TRANSMITTED_MODIFIED_TS_DATA1__INFOR1_MASK                                            0x0000FFF8L
+#define BIF_CFG_DEV0_RC_TRANSMITTED_MODIFIED_TS_DATA1__VENDORID_MASK                                          0xFFFF0000L
+//BIF_CFG_DEV0_RC_TRANSMITTED_MODIFIED_TS_DATA2
+#define BIF_CFG_DEV0_RC_TRANSMITTED_MODIFIED_TS_DATA2__INFOR2__SHIFT                                          0x0
+#define BIF_CFG_DEV0_RC_TRANSMITTED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS__SHIFT           0x18
+#define BIF_CFG_DEV0_RC_TRANSMITTED_MODIFIED_TS_DATA2__INFOR2_MASK                                            0x00FFFFFFL
+#define BIF_CFG_DEV0_RC_TRANSMITTED_MODIFIED_TS_DATA2__ALTERNATE_PROTOCOL_NEGOTIATION_STATUS_MASK             0x03000000L
+//BIF_CFG_DEV0_RC_LANE_0_EQUALIZATION_CNTL_32GT
+#define BIF_CFG_DEV0_RC_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_DSP_32GT_TX_PRESET__SHIFT                       0x0
+#define BIF_CFG_DEV0_RC_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_USP_32GT_TX_PRESET__SHIFT                       0x4
+#define BIF_CFG_DEV0_RC_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_DSP_32GT_TX_PRESET_MASK                         0x0FL
+#define BIF_CFG_DEV0_RC_LANE_0_EQUALIZATION_CNTL_32GT__LANE_0_USP_32GT_TX_PRESET_MASK                         0xF0L
+//BIF_CFG_DEV0_RC_LANE_1_EQUALIZATION_CNTL_32GT
+#define BIF_CFG_DEV0_RC_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_DSP_32GT_TX_PRESET__SHIFT                       0x0
+#define BIF_CFG_DEV0_RC_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_USP_32GT_TX_PRESET__SHIFT                       0x4
+#define BIF_CFG_DEV0_RC_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_DSP_32GT_TX_PRESET_MASK                         0x0FL
+#define BIF_CFG_DEV0_RC_LANE_1_EQUALIZATION_CNTL_32GT__LANE_1_USP_32GT_TX_PRESET_MASK                         0xF0L
+//BIF_CFG_DEV0_RC_LANE_2_EQUALIZATION_CNTL_32GT
+#define BIF_CFG_DEV0_RC_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_DSP_32GT_TX_PRESET__SHIFT                       0x0
+#define BIF_CFG_DEV0_RC_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_USP_32GT_TX_PRESET__SHIFT                       0x4
+#define BIF_CFG_DEV0_RC_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_DSP_32GT_TX_PRESET_MASK                         0x0FL
+#define BIF_CFG_DEV0_RC_LANE_2_EQUALIZATION_CNTL_32GT__LANE_2_USP_32GT_TX_PRESET_MASK                         0xF0L
+//BIF_CFG_DEV0_RC_LANE_3_EQUALIZATION_CNTL_32GT
+#define BIF_CFG_DEV0_RC_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_DSP_32GT_TX_PRESET__SHIFT                       0x0
+#define BIF_CFG_DEV0_RC_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_USP_32GT_TX_PRESET__SHIFT                       0x4
+#define BIF_CFG_DEV0_RC_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_DSP_32GT_TX_PRESET_MASK                         0x0FL
+#define BIF_CFG_DEV0_RC_LANE_3_EQUALIZATION_CNTL_32GT__LANE_3_USP_32GT_TX_PRESET_MASK                         0xF0L
+//BIF_CFG_DEV0_RC_LANE_4_EQUALIZATION_CNTL_32GT
+#define BIF_CFG_DEV0_RC_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_DSP_32GT_TX_PRESET__SHIFT                       0x0
+#define BIF_CFG_DEV0_RC_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_USP_32GT_TX_PRESET__SHIFT                       0x4
+#define BIF_CFG_DEV0_RC_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_DSP_32GT_TX_PRESET_MASK                         0x0FL
+#define BIF_CFG_DEV0_RC_LANE_4_EQUALIZATION_CNTL_32GT__LANE_4_USP_32GT_TX_PRESET_MASK                         0xF0L
+//BIF_CFG_DEV0_RC_LANE_5_EQUALIZATION_CNTL_32GT
+#define BIF_CFG_DEV0_RC_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_DSP_32GT_TX_PRESET__SHIFT                       0x0
+#define BIF_CFG_DEV0_RC_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_USP_32GT_TX_PRESET__SHIFT                       0x4
+#define BIF_CFG_DEV0_RC_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_DSP_32GT_TX_PRESET_MASK                         0x0FL
+#define BIF_CFG_DEV0_RC_LANE_5_EQUALIZATION_CNTL_32GT__LANE_5_USP_32GT_TX_PRESET_MASK                         0xF0L
+//BIF_CFG_DEV0_RC_LANE_6_EQUALIZATION_CNTL_32GT
+#define BIF_CFG_DEV0_RC_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_DSP_32GT_TX_PRESET__SHIFT                       0x0
+#define BIF_CFG_DEV0_RC_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_USP_32GT_TX_PRESET__SHIFT                       0x4
+#define BIF_CFG_DEV0_RC_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_DSP_32GT_TX_PRESET_MASK                         0x0FL
+#define BIF_CFG_DEV0_RC_LANE_6_EQUALIZATION_CNTL_32GT__LANE_6_USP_32GT_TX_PRESET_MASK                         0xF0L
+//BIF_CFG_DEV0_RC_LANE_7_EQUALIZATION_CNTL_32GT
+#define BIF_CFG_DEV0_RC_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_DSP_32GT_TX_PRESET__SHIFT                       0x0
+#define BIF_CFG_DEV0_RC_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_USP_32GT_TX_PRESET__SHIFT                       0x4
+#define BIF_CFG_DEV0_RC_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_DSP_32GT_TX_PRESET_MASK                         0x0FL
+#define BIF_CFG_DEV0_RC_LANE_7_EQUALIZATION_CNTL_32GT__LANE_7_USP_32GT_TX_PRESET_MASK                         0xF0L
+//BIF_CFG_DEV0_RC_LANE_8_EQUALIZATION_CNTL_32GT
+#define BIF_CFG_DEV0_RC_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_DSP_32GT_TX_PRESET__SHIFT                       0x0
+#define BIF_CFG_DEV0_RC_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_USP_32GT_TX_PRESET__SHIFT                       0x4
+#define BIF_CFG_DEV0_RC_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_DSP_32GT_TX_PRESET_MASK                         0x0FL
+#define BIF_CFG_DEV0_RC_LANE_8_EQUALIZATION_CNTL_32GT__LANE_8_USP_32GT_TX_PRESET_MASK                         0xF0L
+//BIF_CFG_DEV0_RC_LANE_9_EQUALIZATION_CNTL_32GT
+#define BIF_CFG_DEV0_RC_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_DSP_32GT_TX_PRESET__SHIFT                       0x0
+#define BIF_CFG_DEV0_RC_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_USP_32GT_TX_PRESET__SHIFT                       0x4
+#define BIF_CFG_DEV0_RC_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_DSP_32GT_TX_PRESET_MASK                         0x0FL
+#define BIF_CFG_DEV0_RC_LANE_9_EQUALIZATION_CNTL_32GT__LANE_9_USP_32GT_TX_PRESET_MASK                         0xF0L
+//BIF_CFG_DEV0_RC_LANE_10_EQUALIZATION_CNTL_32GT
+#define BIF_CFG_DEV0_RC_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_DSP_32GT_TX_PRESET__SHIFT                     0x0
+#define BIF_CFG_DEV0_RC_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_USP_32GT_TX_PRESET__SHIFT                     0x4
+#define BIF_CFG_DEV0_RC_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_DSP_32GT_TX_PRESET_MASK                       0x0FL
+#define BIF_CFG_DEV0_RC_LANE_10_EQUALIZATION_CNTL_32GT__LANE_10_USP_32GT_TX_PRESET_MASK                       0xF0L
+//BIF_CFG_DEV0_RC_LANE_11_EQUALIZATION_CNTL_32GT
+#define BIF_CFG_DEV0_RC_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_DSP_32GT_TX_PRESET__SHIFT                     0x0
+#define BIF_CFG_DEV0_RC_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_USP_32GT_TX_PRESET__SHIFT                     0x4
+#define BIF_CFG_DEV0_RC_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_DSP_32GT_TX_PRESET_MASK                       0x0FL
+#define BIF_CFG_DEV0_RC_LANE_11_EQUALIZATION_CNTL_32GT__LANE_11_USP_32GT_TX_PRESET_MASK                       0xF0L
+//BIF_CFG_DEV0_RC_LANE_12_EQUALIZATION_CNTL_32GT
+#define BIF_CFG_DEV0_RC_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_DSP_32GT_TX_PRESET__SHIFT                     0x0
+#define BIF_CFG_DEV0_RC_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_USP_32GT_TX_PRESET__SHIFT                     0x4
+#define BIF_CFG_DEV0_RC_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_DSP_32GT_TX_PRESET_MASK                       0x0FL
+#define BIF_CFG_DEV0_RC_LANE_12_EQUALIZATION_CNTL_32GT__LANE_12_USP_32GT_TX_PRESET_MASK                       0xF0L
+//BIF_CFG_DEV0_RC_LANE_13_EQUALIZATION_CNTL_32GT
+#define BIF_CFG_DEV0_RC_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_DSP_32GT_TX_PRESET__SHIFT                     0x0
+#define BIF_CFG_DEV0_RC_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_USP_32GT_TX_PRESET__SHIFT                     0x4
+#define BIF_CFG_DEV0_RC_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_DSP_32GT_TX_PRESET_MASK                       0x0FL
+#define BIF_CFG_DEV0_RC_LANE_13_EQUALIZATION_CNTL_32GT__LANE_13_USP_32GT_TX_PRESET_MASK                       0xF0L
+//BIF_CFG_DEV0_RC_LANE_14_EQUALIZATION_CNTL_32GT
+#define BIF_CFG_DEV0_RC_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_DSP_32GT_TX_PRESET__SHIFT                     0x0
+#define BIF_CFG_DEV0_RC_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_USP_32GT_TX_PRESET__SHIFT                     0x4
+#define BIF_CFG_DEV0_RC_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_DSP_32GT_TX_PRESET_MASK                       0x0FL
+#define BIF_CFG_DEV0_RC_LANE_14_EQUALIZATION_CNTL_32GT__LANE_14_USP_32GT_TX_PRESET_MASK                       0xF0L
+//BIF_CFG_DEV0_RC_LANE_15_EQUALIZATION_CNTL_32GT
+#define BIF_CFG_DEV0_RC_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_DSP_32GT_TX_PRESET__SHIFT                     0x0
+#define BIF_CFG_DEV0_RC_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_USP_32GT_TX_PRESET__SHIFT                     0x4
+#define BIF_CFG_DEV0_RC_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_DSP_32GT_TX_PRESET_MASK                       0x0FL
+#define BIF_CFG_DEV0_RC_LANE_15_EQUALIZATION_CNTL_32GT__LANE_15_USP_32GT_TX_PRESET_MASK                       0xF0L
+//BIF_CFG_DEV0_RC_PCIE_AP_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC_PCIE_AP_ENH_CAP_LIST__CAP_ID__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_RC_PCIE_AP_ENH_CAP_LIST__CAP_VER__SHIFT                                                  0x10
+#define BIF_CFG_DEV0_RC_PCIE_AP_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                 0x14
+#define BIF_CFG_DEV0_RC_PCIE_AP_ENH_CAP_LIST__CAP_ID_MASK                                                     0x0000FFFFL
+#define BIF_CFG_DEV0_RC_PCIE_AP_ENH_CAP_LIST__CAP_VER_MASK                                                    0x000F0000L
+#define BIF_CFG_DEV0_RC_PCIE_AP_ENH_CAP_LIST__NEXT_PTR_MASK                                                   0xFFF00000L
+//BIF_CFG_DEV0_RC_AP_CAP
+#define BIF_CFG_DEV0_RC_AP_CAP__COUNT__SHIFT                                                                  0x0
+#define BIF_CFG_DEV0_RC_AP_CAP__SEL_EN_SUPPORTED__SHIFT                                                       0x8
+#define BIF_CFG_DEV0_RC_AP_CAP__COUNT_MASK                                                                    0x000000FFL
+#define BIF_CFG_DEV0_RC_AP_CAP__SEL_EN_SUPPORTED_MASK                                                         0x00000100L
+//BIF_CFG_DEV0_RC_AP_CNTL
+#define BIF_CFG_DEV0_RC_AP_CNTL__INX_SEL__SHIFT                                                               0x0
+#define BIF_CFG_DEV0_RC_AP_CNTL__NEGO_GLOBAL_EN__SHIFT                                                        0x8
+#define BIF_CFG_DEV0_RC_AP_CNTL__INX_SEL_MASK                                                                 0x000000FFL
+#define BIF_CFG_DEV0_RC_AP_CNTL__NEGO_GLOBAL_EN_MASK                                                          0x00000100L
+//BIF_CFG_DEV0_RC_AP_DATA1
+#define BIF_CFG_DEV0_RC_AP_DATA1__USAGE_INFOR__SHIFT                                                          0x0
+#define BIF_CFG_DEV0_RC_AP_DATA1__DETAILS__SHIFT                                                              0x5
+#define BIF_CFG_DEV0_RC_AP_DATA1__VENDORID__SHIFT                                                             0x10
+#define BIF_CFG_DEV0_RC_AP_DATA1__USAGE_INFOR_MASK                                                            0x00000007L
+#define BIF_CFG_DEV0_RC_AP_DATA1__DETAILS_MASK                                                                0x0000FFE0L
+#define BIF_CFG_DEV0_RC_AP_DATA1__VENDORID_MASK                                                               0xFFFF0000L
+//BIF_CFG_DEV0_RC_AP_DATA2
+#define BIF_CFG_DEV0_RC_AP_DATA2__MODIFIED_TS_INFOR2__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_RC_AP_DATA2__MODIFIED_TS_INFOR2_MASK                                                     0x00FFFFFFL
+//BIF_CFG_DEV0_RC_AP_SEL_EN_MASK
+#define BIF_CFG_DEV0_RC_AP_SEL_EN_MASK__PCIE__SHIFT                                                           0x0
+#define BIF_CFG_DEV0_RC_AP_SEL_EN_MASK__OTHERS__SHIFT                                                         0x1
+#define BIF_CFG_DEV0_RC_AP_SEL_EN_MASK__PCIE_MASK                                                             0x00000001L
+#define BIF_CFG_DEV0_RC_AP_SEL_EN_MASK__OTHERS_MASK                                                           0xFFFFFFFEL
+//BIF_CFG_DEV0_RC_PCIE_MARGINING_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID__SHIFT                                            0x0
+#define BIF_CFG_DEV0_RC_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER__SHIFT                                           0x10
+#define BIF_CFG_DEV0_RC_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR__SHIFT                                          0x14
+#define BIF_CFG_DEV0_RC_PCIE_MARGINING_ENH_CAP_LIST__CAP_ID_MASK                                              0x0000FFFFL
+#define BIF_CFG_DEV0_RC_PCIE_MARGINING_ENH_CAP_LIST__CAP_VER_MASK                                             0x000F0000L
+#define BIF_CFG_DEV0_RC_PCIE_MARGINING_ENH_CAP_LIST__NEXT_PTR_MASK                                            0xFFF00000L
+//BIF_CFG_DEV0_RC_MARGINING_PORT_CAP
+#define BIF_CFG_DEV0_RC_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE__SHIFT                                    0x0
+#define BIF_CFG_DEV0_RC_MARGINING_PORT_CAP__MARGINING_USES_SOFTWARE_MASK                                      0x0001L
+//BIF_CFG_DEV0_RC_MARGINING_PORT_STATUS
+#define BIF_CFG_DEV0_RC_MARGINING_PORT_STATUS__MARGINING_READY__SHIFT                                         0x0
+#define BIF_CFG_DEV0_RC_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY__SHIFT                                0x1
+#define BIF_CFG_DEV0_RC_MARGINING_PORT_STATUS__MARGINING_READY_MASK                                           0x0001L
+#define BIF_CFG_DEV0_RC_MARGINING_PORT_STATUS__MARGINING_SOFTWARE_READY_MASK                                  0x0002L
+//BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER__SHIFT                             0x0
+#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE__SHIFT                                 0x3
+#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL__SHIFT                                 0x6
+#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD__SHIFT                              0x8
+#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_RECEIVER_NUMBER_MASK                               0x0007L
+#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_TYPE_MASK                                   0x0038L
+#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_USAGE_MODEL_MASK                                   0x0040L
+#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_CNTL__LANE_0_MARGIN_PAYLOAD_MASK                                0xFF00L
+//BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS__SHIFT                    0x0
+#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS__SHIFT                        0x3
+#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS__SHIFT                        0x6
+#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS__SHIFT                     0x8
+#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_RECEIVER_NUMBER_STATUS_MASK                      0x0007L
+#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_TYPE_STATUS_MASK                          0x0038L
+#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_USAGE_MODEL_STATUS_MASK                          0x0040L
+#define BIF_CFG_DEV0_RC_LANE_0_MARGINING_LANE_STATUS__LANE_0_MARGIN_PAYLOAD_STATUS_MASK                       0xFF00L
+//BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER__SHIFT                             0x0
+#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE__SHIFT                                 0x3
+#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL__SHIFT                                 0x6
+#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD__SHIFT                              0x8
+#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_RECEIVER_NUMBER_MASK                               0x0007L
+#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_TYPE_MASK                                   0x0038L
+#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_USAGE_MODEL_MASK                                   0x0040L
+#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_CNTL__LANE_1_MARGIN_PAYLOAD_MASK                                0xFF00L
+//BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS__SHIFT                    0x0
+#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS__SHIFT                        0x3
+#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS__SHIFT                        0x6
+#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS__SHIFT                     0x8
+#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_RECEIVER_NUMBER_STATUS_MASK                      0x0007L
+#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_TYPE_STATUS_MASK                          0x0038L
+#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_USAGE_MODEL_STATUS_MASK                          0x0040L
+#define BIF_CFG_DEV0_RC_LANE_1_MARGINING_LANE_STATUS__LANE_1_MARGIN_PAYLOAD_STATUS_MASK                       0xFF00L
+//BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER__SHIFT                             0x0
+#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE__SHIFT                                 0x3
+#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL__SHIFT                                 0x6
+#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD__SHIFT                              0x8
+#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_RECEIVER_NUMBER_MASK                               0x0007L
+#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_TYPE_MASK                                   0x0038L
+#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_USAGE_MODEL_MASK                                   0x0040L
+#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_CNTL__LANE_2_MARGIN_PAYLOAD_MASK                                0xFF00L
+//BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS__SHIFT                    0x0
+#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS__SHIFT                        0x3
+#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS__SHIFT                        0x6
+#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS__SHIFT                     0x8
+#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_RECEIVER_NUMBER_STATUS_MASK                      0x0007L
+#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_TYPE_STATUS_MASK                          0x0038L
+#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_USAGE_MODEL_STATUS_MASK                          0x0040L
+#define BIF_CFG_DEV0_RC_LANE_2_MARGINING_LANE_STATUS__LANE_2_MARGIN_PAYLOAD_STATUS_MASK                       0xFF00L
+//BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER__SHIFT                             0x0
+#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE__SHIFT                                 0x3
+#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL__SHIFT                                 0x6
+#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD__SHIFT                              0x8
+#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_RECEIVER_NUMBER_MASK                               0x0007L
+#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_TYPE_MASK                                   0x0038L
+#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_USAGE_MODEL_MASK                                   0x0040L
+#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_CNTL__LANE_3_MARGIN_PAYLOAD_MASK                                0xFF00L
+//BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS__SHIFT                    0x0
+#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS__SHIFT                        0x3
+#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS__SHIFT                        0x6
+#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS__SHIFT                     0x8
+#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_RECEIVER_NUMBER_STATUS_MASK                      0x0007L
+#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_TYPE_STATUS_MASK                          0x0038L
+#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_USAGE_MODEL_STATUS_MASK                          0x0040L
+#define BIF_CFG_DEV0_RC_LANE_3_MARGINING_LANE_STATUS__LANE_3_MARGIN_PAYLOAD_STATUS_MASK                       0xFF00L
+//BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER__SHIFT                             0x0
+#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE__SHIFT                                 0x3
+#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL__SHIFT                                 0x6
+#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD__SHIFT                              0x8
+#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_RECEIVER_NUMBER_MASK                               0x0007L
+#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_TYPE_MASK                                   0x0038L
+#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_USAGE_MODEL_MASK                                   0x0040L
+#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_CNTL__LANE_4_MARGIN_PAYLOAD_MASK                                0xFF00L
+//BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS__SHIFT                    0x0
+#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS__SHIFT                        0x3
+#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS__SHIFT                        0x6
+#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS__SHIFT                     0x8
+#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_RECEIVER_NUMBER_STATUS_MASK                      0x0007L
+#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_TYPE_STATUS_MASK                          0x0038L
+#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_USAGE_MODEL_STATUS_MASK                          0x0040L
+#define BIF_CFG_DEV0_RC_LANE_4_MARGINING_LANE_STATUS__LANE_4_MARGIN_PAYLOAD_STATUS_MASK                       0xFF00L
+//BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER__SHIFT                             0x0
+#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE__SHIFT                                 0x3
+#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL__SHIFT                                 0x6
+#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD__SHIFT                              0x8
+#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_RECEIVER_NUMBER_MASK                               0x0007L
+#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_TYPE_MASK                                   0x0038L
+#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_USAGE_MODEL_MASK                                   0x0040L
+#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_CNTL__LANE_5_MARGIN_PAYLOAD_MASK                                0xFF00L
+//BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS__SHIFT                    0x0
+#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS__SHIFT                        0x3
+#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS__SHIFT                        0x6
+#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS__SHIFT                     0x8
+#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_RECEIVER_NUMBER_STATUS_MASK                      0x0007L
+#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_TYPE_STATUS_MASK                          0x0038L
+#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_USAGE_MODEL_STATUS_MASK                          0x0040L
+#define BIF_CFG_DEV0_RC_LANE_5_MARGINING_LANE_STATUS__LANE_5_MARGIN_PAYLOAD_STATUS_MASK                       0xFF00L
+//BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER__SHIFT                             0x0
+#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE__SHIFT                                 0x3
+#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL__SHIFT                                 0x6
+#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD__SHIFT                              0x8
+#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_RECEIVER_NUMBER_MASK                               0x0007L
+#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_TYPE_MASK                                   0x0038L
+#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_USAGE_MODEL_MASK                                   0x0040L
+#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_CNTL__LANE_6_MARGIN_PAYLOAD_MASK                                0xFF00L
+//BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS__SHIFT                    0x0
+#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS__SHIFT                        0x3
+#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS__SHIFT                        0x6
+#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS__SHIFT                     0x8
+#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_RECEIVER_NUMBER_STATUS_MASK                      0x0007L
+#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_TYPE_STATUS_MASK                          0x0038L
+#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_USAGE_MODEL_STATUS_MASK                          0x0040L
+#define BIF_CFG_DEV0_RC_LANE_6_MARGINING_LANE_STATUS__LANE_6_MARGIN_PAYLOAD_STATUS_MASK                       0xFF00L
+//BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER__SHIFT                             0x0
+#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE__SHIFT                                 0x3
+#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL__SHIFT                                 0x6
+#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD__SHIFT                              0x8
+#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_RECEIVER_NUMBER_MASK                               0x0007L
+#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_TYPE_MASK                                   0x0038L
+#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_USAGE_MODEL_MASK                                   0x0040L
+#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_CNTL__LANE_7_MARGIN_PAYLOAD_MASK                                0xFF00L
+//BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS__SHIFT                    0x0
+#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS__SHIFT                        0x3
+#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS__SHIFT                        0x6
+#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS__SHIFT                     0x8
+#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_RECEIVER_NUMBER_STATUS_MASK                      0x0007L
+#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_TYPE_STATUS_MASK                          0x0038L
+#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_USAGE_MODEL_STATUS_MASK                          0x0040L
+#define BIF_CFG_DEV0_RC_LANE_7_MARGINING_LANE_STATUS__LANE_7_MARGIN_PAYLOAD_STATUS_MASK                       0xFF00L
+//BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER__SHIFT                             0x0
+#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE__SHIFT                                 0x3
+#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL__SHIFT                                 0x6
+#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD__SHIFT                              0x8
+#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_RECEIVER_NUMBER_MASK                               0x0007L
+#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_TYPE_MASK                                   0x0038L
+#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_USAGE_MODEL_MASK                                   0x0040L
+#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_CNTL__LANE_8_MARGIN_PAYLOAD_MASK                                0xFF00L
+//BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS__SHIFT                    0x0
+#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS__SHIFT                        0x3
+#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS__SHIFT                        0x6
+#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS__SHIFT                     0x8
+#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_RECEIVER_NUMBER_STATUS_MASK                      0x0007L
+#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_TYPE_STATUS_MASK                          0x0038L
+#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_USAGE_MODEL_STATUS_MASK                          0x0040L
+#define BIF_CFG_DEV0_RC_LANE_8_MARGINING_LANE_STATUS__LANE_8_MARGIN_PAYLOAD_STATUS_MASK                       0xFF00L
+//BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER__SHIFT                             0x0
+#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE__SHIFT                                 0x3
+#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL__SHIFT                                 0x6
+#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD__SHIFT                              0x8
+#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_RECEIVER_NUMBER_MASK                               0x0007L
+#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_TYPE_MASK                                   0x0038L
+#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_USAGE_MODEL_MASK                                   0x0040L
+#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_CNTL__LANE_9_MARGIN_PAYLOAD_MASK                                0xFF00L
+//BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS__SHIFT                    0x0
+#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS__SHIFT                        0x3
+#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS__SHIFT                        0x6
+#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS__SHIFT                     0x8
+#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_RECEIVER_NUMBER_STATUS_MASK                      0x0007L
+#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_TYPE_STATUS_MASK                          0x0038L
+#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_USAGE_MODEL_STATUS_MASK                          0x0040L
+#define BIF_CFG_DEV0_RC_LANE_9_MARGINING_LANE_STATUS__LANE_9_MARGIN_PAYLOAD_STATUS_MASK                       0xFF00L
+//BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER__SHIFT                           0x0
+#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE__SHIFT                               0x3
+#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL__SHIFT                               0x6
+#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD__SHIFT                            0x8
+#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_RECEIVER_NUMBER_MASK                             0x0007L
+#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_TYPE_MASK                                 0x0038L
+#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_USAGE_MODEL_MASK                                 0x0040L
+#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_CNTL__LANE_10_MARGIN_PAYLOAD_MASK                              0xFF00L
+//BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
+#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS__SHIFT                      0x3
+#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS__SHIFT                      0x6
+#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
+#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
+#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_TYPE_STATUS_MASK                        0x0038L
+#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_USAGE_MODEL_STATUS_MASK                        0x0040L
+#define BIF_CFG_DEV0_RC_LANE_10_MARGINING_LANE_STATUS__LANE_10_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
+//BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER__SHIFT                           0x0
+#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE__SHIFT                               0x3
+#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL__SHIFT                               0x6
+#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD__SHIFT                            0x8
+#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_RECEIVER_NUMBER_MASK                             0x0007L
+#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_TYPE_MASK                                 0x0038L
+#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_USAGE_MODEL_MASK                                 0x0040L
+#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_CNTL__LANE_11_MARGIN_PAYLOAD_MASK                              0xFF00L
+//BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
+#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS__SHIFT                      0x3
+#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS__SHIFT                      0x6
+#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
+#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
+#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_TYPE_STATUS_MASK                        0x0038L
+#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_USAGE_MODEL_STATUS_MASK                        0x0040L
+#define BIF_CFG_DEV0_RC_LANE_11_MARGINING_LANE_STATUS__LANE_11_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
+//BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER__SHIFT                           0x0
+#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE__SHIFT                               0x3
+#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL__SHIFT                               0x6
+#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD__SHIFT                            0x8
+#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_RECEIVER_NUMBER_MASK                             0x0007L
+#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_TYPE_MASK                                 0x0038L
+#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_USAGE_MODEL_MASK                                 0x0040L
+#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_CNTL__LANE_12_MARGIN_PAYLOAD_MASK                              0xFF00L
+//BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
+#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS__SHIFT                      0x3
+#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS__SHIFT                      0x6
+#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
+#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
+#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_TYPE_STATUS_MASK                        0x0038L
+#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_USAGE_MODEL_STATUS_MASK                        0x0040L
+#define BIF_CFG_DEV0_RC_LANE_12_MARGINING_LANE_STATUS__LANE_12_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
+//BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER__SHIFT                           0x0
+#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE__SHIFT                               0x3
+#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL__SHIFT                               0x6
+#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD__SHIFT                            0x8
+#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_RECEIVER_NUMBER_MASK                             0x0007L
+#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_TYPE_MASK                                 0x0038L
+#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_USAGE_MODEL_MASK                                 0x0040L
+#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_CNTL__LANE_13_MARGIN_PAYLOAD_MASK                              0xFF00L
+//BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
+#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS__SHIFT                      0x3
+#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS__SHIFT                      0x6
+#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
+#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
+#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_TYPE_STATUS_MASK                        0x0038L
+#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_USAGE_MODEL_STATUS_MASK                        0x0040L
+#define BIF_CFG_DEV0_RC_LANE_13_MARGINING_LANE_STATUS__LANE_13_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
+//BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER__SHIFT                           0x0
+#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE__SHIFT                               0x3
+#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL__SHIFT                               0x6
+#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD__SHIFT                            0x8
+#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_RECEIVER_NUMBER_MASK                             0x0007L
+#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_TYPE_MASK                                 0x0038L
+#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_USAGE_MODEL_MASK                                 0x0040L
+#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_CNTL__LANE_14_MARGIN_PAYLOAD_MASK                              0xFF00L
+//BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
+#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS__SHIFT                      0x3
+#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS__SHIFT                      0x6
+#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
+#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
+#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_TYPE_STATUS_MASK                        0x0038L
+#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_USAGE_MODEL_STATUS_MASK                        0x0040L
+#define BIF_CFG_DEV0_RC_LANE_14_MARGINING_LANE_STATUS__LANE_14_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
+//BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL
+#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER__SHIFT                           0x0
+#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE__SHIFT                               0x3
+#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL__SHIFT                               0x6
+#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD__SHIFT                            0x8
+#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_RECEIVER_NUMBER_MASK                             0x0007L
+#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_TYPE_MASK                                 0x0038L
+#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_USAGE_MODEL_MASK                                 0x0040L
+#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_CNTL__LANE_15_MARGIN_PAYLOAD_MASK                              0xFF00L
+//BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS
+#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS__SHIFT                  0x0
+#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS__SHIFT                      0x3
+#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS__SHIFT                      0x6
+#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS__SHIFT                   0x8
+#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_RECEIVER_NUMBER_STATUS_MASK                    0x0007L
+#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_TYPE_STATUS_MASK                        0x0038L
+#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_USAGE_MODEL_STATUS_MASK                        0x0040L
+#define BIF_CFG_DEV0_RC_LANE_15_MARGINING_LANE_STATUS__LANE_15_MARGIN_PAYLOAD_STATUS_MASK                     0xFF00L
+//BIF_CFG_DEV0_RC_PCIE_NULL1_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC_PCIE_NULL1_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
+#define BIF_CFG_DEV0_RC_PCIE_NULL1_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
+#define BIF_CFG_DEV0_RC_PCIE_NULL1_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
+#define BIF_CFG_DEV0_RC_PCIE_NULL1_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
+#define BIF_CFG_DEV0_RC_PCIE_NULL1_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
+#define BIF_CFG_DEV0_RC_PCIE_NULL1_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
+//BIF_CFG_DEV0_RC_PCIE_VC_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC_PCIE_VC_ENH_CAP_LIST__CAP_ID__SHIFT                                                   0x0
+#define BIF_CFG_DEV0_RC_PCIE_VC_ENH_CAP_LIST__CAP_VER__SHIFT                                                  0x10
+#define BIF_CFG_DEV0_RC_PCIE_VC_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                 0x14
+#define BIF_CFG_DEV0_RC_PCIE_VC_ENH_CAP_LIST__CAP_ID_MASK                                                     0x0000FFFFL
+#define BIF_CFG_DEV0_RC_PCIE_VC_ENH_CAP_LIST__CAP_VER_MASK                                                    0x000F0000L
+#define BIF_CFG_DEV0_RC_PCIE_VC_ENH_CAP_LIST__NEXT_PTR_MASK                                                   0xFFF00000L
+//BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1
+#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT__SHIFT                                            0x0
+#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT__SHIFT                               0x4
+#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1__REF_CLK__SHIFT                                                 0x8
+#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE__SHIFT                               0xa
+#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1__EXT_VC_COUNT_MASK                                              0x00000007L
+#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1__LOW_PRIORITY_EXT_VC_COUNT_MASK                                 0x00000070L
+#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1__REF_CLK_MASK                                                   0x00000300L
+#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG1__PORT_ARB_TABLE_ENTRY_SIZE_MASK                                 0x00000C00L
+//BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG2
+#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP__SHIFT                                              0x0
+#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET__SHIFT                                     0x18
+#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG2__VC_ARB_CAP_MASK                                                0x000000FFL
+#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CAP_REG2__VC_ARB_TABLE_OFFSET_MASK                                       0xFF000000L
+//BIF_CFG_DEV0_RC_PCIE_PORT_VC_CNTL
+#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE__SHIFT                                           0x0
+#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CNTL__VC_ARB_SELECT__SHIFT                                               0x1
+#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CNTL__LOAD_VC_ARB_TABLE_MASK                                             0x0001L
+#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_CNTL__VC_ARB_SELECT_MASK                                                 0x000EL
+//BIF_CFG_DEV0_RC_PCIE_PORT_VC_STATUS
+#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS__SHIFT                                       0x0
+#define BIF_CFG_DEV0_RC_PCIE_PORT_VC_STATUS__VC_ARB_TABLE_STATUS_MASK                                         0x0001L
+//BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP
+#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                            0x0
+#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                      0xf
+#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                          0x10
+#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                                   0x18
+#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP__PORT_ARB_CAP_MASK                                              0x000000FFL
+#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                        0x00008000L
+#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                            0x007F0000L
+#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                     0xFF000000L
+//BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL
+#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                          0x0
+#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                        0x1
+#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                    0x10
+#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                        0x11
+#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__VC_ID__SHIFT                                                  0x18
+#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE__SHIFT                                              0x1f
+#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                            0x00000001L
+#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                          0x000000FEL
+#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                      0x00010000L
+#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                          0x000E0000L
+#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__VC_ID_MASK                                                    0x07000000L
+#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_CNTL__VC_ENABLE_MASK                                                0x80000000L
+//BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_STATUS
+#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                                0x0
+#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                               0x1
+#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                                  0x0001L
+#define BIF_CFG_DEV0_RC_PCIE_VC0_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                                 0x0002L
+//BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP
+#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP__SHIFT                                            0x0
+#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS__SHIFT                                      0xf
+#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS__SHIFT                                          0x10
+#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET__SHIFT                                   0x18
+#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP__PORT_ARB_CAP_MASK                                              0x000000FFL
+#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP__REJECT_SNOOP_TRANS_MASK                                        0x00008000L
+#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP__MAX_TIME_SLOTS_MASK                                            0x003F0000L
+#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CAP__PORT_ARB_TABLE_OFFSET_MASK                                     0xFF000000L
+//BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL
+#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0__SHIFT                                          0x0
+#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7__SHIFT                                        0x1
+#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE__SHIFT                                    0x10
+#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT__SHIFT                                        0x11
+#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__VC_ID__SHIFT                                                  0x18
+#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE__SHIFT                                              0x1f
+#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC0_MASK                                            0x00000001L
+#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__TC_VC_MAP_TC1_7_MASK                                          0x000000FEL
+#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__LOAD_PORT_ARB_TABLE_MASK                                      0x00010000L
+#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__PORT_ARB_SELECT_MASK                                          0x000E0000L
+#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__VC_ID_MASK                                                    0x07000000L
+#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_CNTL__VC_ENABLE_MASK                                                0x80000000L
+//BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_STATUS
+#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS__SHIFT                                0x0
+#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING__SHIFT                               0x1
+#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_STATUS__PORT_ARB_TABLE_STATUS_MASK                                  0x0001L
+#define BIF_CFG_DEV0_RC_PCIE_VC1_RESOURCE_STATUS__VC_NEGOTIATION_PENDING_MASK                                 0x0002L
+//BIF_CFG_DEV0_RC_PCIE_DLF_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC_PCIE_DLF_ENH_CAP_LIST__CAP_ID__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_RC_PCIE_DLF_ENH_CAP_LIST__CAP_VER__SHIFT                                                 0x10
+#define BIF_CFG_DEV0_RC_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                0x14
+#define BIF_CFG_DEV0_RC_PCIE_DLF_ENH_CAP_LIST__CAP_ID_MASK                                                    0x0000FFFFL
+#define BIF_CFG_DEV0_RC_PCIE_DLF_ENH_CAP_LIST__CAP_VER_MASK                                                   0x000F0000L
+#define BIF_CFG_DEV0_RC_PCIE_DLF_ENH_CAP_LIST__NEXT_PTR_MASK                                                  0xFFF00000L
+//BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_CAP
+#define BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED__SHIFT                                     0x0
+#define BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE__SHIFT                                     0x1f
+#define BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_CAP__LOCAL_DLF_SUPPORTED_MASK                                       0x007FFFFFL
+#define BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_CAP__DLF_EXCHANGE_ENABLE_MASK                                       0x80000000L
+//BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_STATUS
+#define BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED__SHIFT                                 0x0
+#define BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID__SHIFT                           0x1f
+#define BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_MASK                                   0x007FFFFFL
+#define BIF_CFG_DEV0_RC_DATA_LINK_FEATURE_STATUS__REMOTE_DLF_SUPPORTED_VALID_MASK                             0x80000000L
+//BIF_CFG_DEV0_RC_PCIE_NULL2_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC_PCIE_NULL2_ENH_CAP_LIST__CAP_ID__SHIFT                                                0x0
+#define BIF_CFG_DEV0_RC_PCIE_NULL2_ENH_CAP_LIST__CAP_VER__SHIFT                                               0x10
+#define BIF_CFG_DEV0_RC_PCIE_NULL2_ENH_CAP_LIST__NEXT_PTR__SHIFT                                              0x14
+#define BIF_CFG_DEV0_RC_PCIE_NULL2_ENH_CAP_LIST__CAP_ID_MASK                                                  0x0000FFFFL
+#define BIF_CFG_DEV0_RC_PCIE_NULL2_ENH_CAP_LIST__CAP_VER_MASK                                                 0x000F0000L
+#define BIF_CFG_DEV0_RC_PCIE_NULL2_ENH_CAP_LIST__NEXT_PTR_MASK                                                0xFFF00000L
+//BIF_CFG_DEV0_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID__SHIFT                                          0x0
+#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER__SHIFT                                         0x10
+#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR__SHIFT                                        0x14
+#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_ID_MASK                                            0x0000FFFFL
+#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__CAP_VER_MASK                                           0x000F0000L
+#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_RPT_ENH_CAP_LIST__NEXT_PTR_MASK                                          0xFFF00000L
+//BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS__SHIFT                                         0x4
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS__SHIFT                                      0x5
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS__SHIFT                                         0xc
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS__SHIFT                                          0xd
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS__SHIFT                                     0xe
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS__SHIFT                                   0xf
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS__SHIFT                                       0x10
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS__SHIFT                                        0x11
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS__SHIFT                                         0x12
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS__SHIFT                                        0x13
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS__SHIFT                                  0x14
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS__SHIFT                                   0x15
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS__SHIFT                                  0x16
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS__SHIFT                                  0x17
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS__SHIFT                         0x18
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS__SHIFT                          0x19
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS__SHIFT                     0x1a
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__DMWR_REQUEST_EGRESS_BLOCKED_STATUS__SHIFT                     0x1b
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__IDE_CHECK_FAILED_STATUS__SHIFT                                0x1c
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__MISROUTED_IDE_TLP_STATUS__SHIFT                               0x1d
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__PCRC_CHECK_FAILED_STATUS__SHIFT                               0x1e
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__DLP_ERR_STATUS_MASK                                           0x00000010L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__SURPDN_ERR_STATUS_MASK                                        0x00000020L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__PSN_ERR_STATUS_MASK                                           0x00001000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__FC_ERR_STATUS_MASK                                            0x00002000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__CPL_TIMEOUT_STATUS_MASK                                       0x00004000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__CPL_ABORT_ERR_STATUS_MASK                                     0x00008000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__UNEXP_CPL_STATUS_MASK                                         0x00010000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__RCV_OVFL_STATUS_MASK                                          0x00020000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__MAL_TLP_STATUS_MASK                                           0x00040000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__ECRC_ERR_STATUS_MASK                                          0x00080000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__UNSUPP_REQ_ERR_STATUS_MASK                                    0x00100000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__ACS_VIOLATION_STATUS_MASK                                     0x00200000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__UNCORR_INT_ERR_STATUS_MASK                                    0x00400000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__MC_BLOCKED_TLP_STATUS_MASK                                    0x00800000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__ATOMICOP_EGRESS_BLOCKED_STATUS_MASK                           0x01000000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__TLP_PREFIX_BLOCKED_ERR_STATUS_MASK                            0x02000000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__POISONED_TLP_EGRESS_BLOCKED_STATUS_MASK                       0x04000000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__DMWR_REQUEST_EGRESS_BLOCKED_STATUS_MASK                       0x08000000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__IDE_CHECK_FAILED_STATUS_MASK                                  0x10000000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__MISROUTED_IDE_TLP_STATUS_MASK                                 0x20000000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_STATUS__PCRC_CHECK_FAILED_STATUS_MASK                                 0x40000000L
+//BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK__SHIFT                                             0x4
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK__SHIFT                                          0x5
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK__SHIFT                                             0xc
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK__SHIFT                                              0xd
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK__SHIFT                                         0xe
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK__SHIFT                                       0xf
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK__SHIFT                                           0x10
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK__SHIFT                                            0x11
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK__SHIFT                                             0x12
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK__SHIFT                                            0x13
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK__SHIFT                                      0x14
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK__SHIFT                                       0x15
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK__SHIFT                                      0x16
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK__SHIFT                                      0x17
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK__SHIFT                             0x18
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK__SHIFT                              0x19
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK__SHIFT                         0x1a
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__DMWR_REQUEST_EGRESS_BLOCKED_MASK__SHIFT                         0x1b
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__IDE_CHECK_FAILED_MASK__SHIFT                                    0x1c
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__MISROUTED_IDE_TLP_MASK__SHIFT                                   0x1d
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__PCRC_CHECK_FAILED_MASK__SHIFT                                   0x1e
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__DLP_ERR_MASK_MASK                                               0x00000010L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__SURPDN_ERR_MASK_MASK                                            0x00000020L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__PSN_ERR_MASK_MASK                                               0x00001000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__FC_ERR_MASK_MASK                                                0x00002000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__CPL_TIMEOUT_MASK_MASK                                           0x00004000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__CPL_ABORT_ERR_MASK_MASK                                         0x00008000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__UNEXP_CPL_MASK_MASK                                             0x00010000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__RCV_OVFL_MASK_MASK                                              0x00020000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__MAL_TLP_MASK_MASK                                               0x00040000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__ECRC_ERR_MASK_MASK                                              0x00080000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__UNSUPP_REQ_ERR_MASK_MASK                                        0x00100000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__ACS_VIOLATION_MASK_MASK                                         0x00200000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__UNCORR_INT_ERR_MASK_MASK                                        0x00400000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__MC_BLOCKED_TLP_MASK_MASK                                        0x00800000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__ATOMICOP_EGRESS_BLOCKED_MASK_MASK                               0x01000000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__TLP_PREFIX_BLOCKED_ERR_MASK_MASK                                0x02000000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__POISONED_TLP_EGRESS_BLOCKED_MASK_MASK                           0x04000000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__DMWR_REQUEST_EGRESS_BLOCKED_MASK_MASK                           0x08000000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__IDE_CHECK_FAILED_MASK_MASK                                      0x10000000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__MISROUTED_IDE_TLP_MASK_MASK                                     0x20000000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_MASK__PCRC_CHECK_FAILED_MASK_MASK                                     0x40000000L
+//BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY__SHIFT                                     0x4
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY__SHIFT                                  0x5
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY__SHIFT                                     0xc
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY__SHIFT                                      0xd
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY__SHIFT                                 0xe
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY__SHIFT                               0xf
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY__SHIFT                                   0x10
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY__SHIFT                                    0x11
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY__SHIFT                                     0x12
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY__SHIFT                                    0x13
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY__SHIFT                              0x14
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY__SHIFT                               0x15
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY__SHIFT                              0x16
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY__SHIFT                              0x17
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY__SHIFT                     0x18
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY__SHIFT                      0x19
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY__SHIFT                 0x1a
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__DMWR_REQUEST_EGRESS_BLOCKED_SEVERITY__SHIFT                 0x1b
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__IDE_CHECK_FAILED_SEVERITY__SHIFT                            0x1c
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__MISROUTED_IDE_TLP_SEVERITY__SHIFT                           0x1d
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__PCRC_CHECK_FAILED_SEVERITY__SHIFT                           0x1e
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__DLP_ERR_SEVERITY_MASK                                       0x00000010L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__SURPDN_ERR_SEVERITY_MASK                                    0x00000020L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__PSN_ERR_SEVERITY_MASK                                       0x00001000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__FC_ERR_SEVERITY_MASK                                        0x00002000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__CPL_TIMEOUT_SEVERITY_MASK                                   0x00004000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__CPL_ABORT_ERR_SEVERITY_MASK                                 0x00008000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__UNEXP_CPL_SEVERITY_MASK                                     0x00010000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__RCV_OVFL_SEVERITY_MASK                                      0x00020000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__MAL_TLP_SEVERITY_MASK                                       0x00040000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__ECRC_ERR_SEVERITY_MASK                                      0x00080000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__UNSUPP_REQ_ERR_SEVERITY_MASK                                0x00100000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__ACS_VIOLATION_SEVERITY_MASK                                 0x00200000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__UNCORR_INT_ERR_SEVERITY_MASK                                0x00400000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__MC_BLOCKED_TLP_SEVERITY_MASK                                0x00800000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__ATOMICOP_EGRESS_BLOCKED_SEVERITY_MASK                       0x01000000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__TLP_PREFIX_BLOCKED_ERR_SEVERITY_MASK                        0x02000000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__POISONED_TLP_EGRESS_BLOCKED_SEVERITY_MASK                   0x04000000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__DMWR_REQUEST_EGRESS_BLOCKED_SEVERITY_MASK                   0x08000000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__IDE_CHECK_FAILED_SEVERITY_MASK                              0x10000000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__MISROUTED_IDE_TLP_SEVERITY_MASK                             0x20000000L
+#define BIF_CFG_DEV0_RC_PCIE_UNCORR_ERR_SEVERITY__PCRC_CHECK_FAILED_SEVERITY_MASK                             0x40000000L
+//BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS__SHIFT                                           0x0
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS__SHIFT                                           0x6
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS__SHIFT                                          0x7
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS__SHIFT                               0x8
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS__SHIFT                              0xc
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS__SHIFT                             0xd
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS__SHIFT                                      0xe
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS__SHIFT                                      0xf
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__RCV_ERR_STATUS_MASK                                             0x00000001L
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__BAD_TLP_STATUS_MASK                                             0x00000040L
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__BAD_DLLP_STATUS_MASK                                            0x00000080L
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__REPLAY_NUM_ROLLOVER_STATUS_MASK                                 0x00000100L
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__REPLAY_TIMER_TIMEOUT_STATUS_MASK                                0x00001000L
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__ADVISORY_NONFATAL_ERR_STATUS_MASK                               0x00002000L
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__CORR_INT_ERR_STATUS_MASK                                        0x00004000L
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_STATUS__HDR_LOG_OVFL_STATUS_MASK                                        0x00008000L
+//BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__RCV_ERR_MASK__SHIFT                                               0x0
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__BAD_TLP_MASK__SHIFT                                               0x6
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK__SHIFT                                              0x7
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK__SHIFT                                   0x8
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK__SHIFT                                  0xc
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK__SHIFT                                 0xd
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK__SHIFT                                          0xe
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK__SHIFT                                          0xf
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__RCV_ERR_MASK_MASK                                                 0x00000001L
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__BAD_TLP_MASK_MASK                                                 0x00000040L
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__BAD_DLLP_MASK_MASK                                                0x00000080L
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__REPLAY_NUM_ROLLOVER_MASK_MASK                                     0x00000100L
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__REPLAY_TIMER_TIMEOUT_MASK_MASK                                    0x00001000L
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__ADVISORY_NONFATAL_ERR_MASK_MASK                                   0x00002000L
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__CORR_INT_ERR_MASK_MASK                                            0x00004000L
+#define BIF_CFG_DEV0_RC_PCIE_CORR_ERR_MASK__HDR_LOG_OVFL_MASK_MASK                                            0x00008000L
+//BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL
+#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR__SHIFT                                           0x0
+#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP__SHIFT                                            0x5
+#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN__SHIFT                                             0x6
+#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP__SHIFT                                          0x7
+#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN__SHIFT                                           0x8
+#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP__SHIFT                                      0x9
+#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN__SHIFT                                       0xa
+#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT__SHIFT                                  0xb
+#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE__SHIFT                          0xc
+#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__HEADER_LOG_SIZE__SHIFT                                         0xd
+#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_WAS_FLIT_MODE__SHIFT                                0x12
+#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_SIZE__SHIFT                                         0x13
+#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__FIRST_ERR_PTR_MASK                                             0x0000001FL
+#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_CAP_MASK                                              0x00000020L
+#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_GEN_EN_MASK                                               0x00000040L
+#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_CAP_MASK                                            0x00000080L
+#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__ECRC_CHECK_EN_MASK                                             0x00000100L
+#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_CAP_MASK                                        0x00000200L
+#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__MULTI_HDR_RECD_EN_MASK                                         0x00000400L
+#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__TLP_PREFIX_LOG_PRESENT_MASK                                    0x00000800L
+#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__COMPLETION_TIMEOUT_LOG_CAPABLE_MASK                            0x00001000L
+#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__HEADER_LOG_SIZE_MASK                                           0x0003E000L
+#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_WAS_FLIT_MODE_MASK                                  0x00040000L
+#define BIF_CFG_DEV0_RC_PCIE_ADV_ERR_CAP_CNTL__LOGGED_TLP_SIZE_MASK                                           0x00F80000L
+//BIF_CFG_DEV0_RC_PCIE_HDR_LOG0
+#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG0__TLP_HDR__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG0__TLP_HDR_MASK                                                           0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_PCIE_HDR_LOG1
+#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG1__TLP_HDR__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG1__TLP_HDR_MASK                                                           0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_PCIE_HDR_LOG2
+#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG2__TLP_HDR__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG2__TLP_HDR_MASK                                                           0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_PCIE_HDR_LOG3
+#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG3__TLP_HDR__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG3__TLP_HDR_MASK                                                           0xFFFFFFFFL
+//PCIE_ROOT_ERR_CMD
+#define PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN__SHIFT                                                             0x0
+#define PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN__SHIFT                                                         0x1
+#define PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN__SHIFT                                                            0x2
+#define PCIE_ROOT_ERR_CMD__CORR_ERR_REP_EN_MASK                                                               0x00000001L
+#define PCIE_ROOT_ERR_CMD__NONFATAL_ERR_REP_EN_MASK                                                           0x00000002L
+#define PCIE_ROOT_ERR_CMD__FATAL_ERR_REP_EN_MASK                                                              0x00000004L
+//PCIE_ROOT_ERR_STATUS
+#define PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD__SHIFT                                                            0x0
+#define PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD__SHIFT                                                       0x1
+#define PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD__SHIFT                                                  0x2
+#define PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD__SHIFT                                             0x3
+#define PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL__SHIFT                                                0x4
+#define PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD__SHIFT                                                  0x5
+#define PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD__SHIFT                                                     0x6
+#define PCIE_ROOT_ERR_STATUS__ERR_COR_SUBCLASS__SHIFT                                                         0x7
+#define PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM__SHIFT                                                      0x1b
+#define PCIE_ROOT_ERR_STATUS__ERR_CORR_RCVD_MASK                                                              0x00000001L
+#define PCIE_ROOT_ERR_STATUS__MULT_ERR_CORR_RCVD_MASK                                                         0x00000002L
+#define PCIE_ROOT_ERR_STATUS__ERR_FATAL_NONFATAL_RCVD_MASK                                                    0x00000004L
+#define PCIE_ROOT_ERR_STATUS__MULT_ERR_FATAL_NONFATAL_RCVD_MASK                                               0x00000008L
+#define PCIE_ROOT_ERR_STATUS__FIRST_UNCORRECTABLE_FATAL_MASK                                                  0x00000010L
+#define PCIE_ROOT_ERR_STATUS__NONFATAL_ERROR_MSG_RCVD_MASK                                                    0x00000020L
+#define PCIE_ROOT_ERR_STATUS__FATAL_ERROR_MSG_RCVD_MASK                                                       0x00000040L
+#define PCIE_ROOT_ERR_STATUS__ERR_COR_SUBCLASS_MASK                                                           0x00000180L
+#define PCIE_ROOT_ERR_STATUS__ADV_ERR_INT_MSG_NUM_MASK                                                        0xF8000000L
+//PCIE_ERR_SRC_ID
+#define PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID__SHIFT                                                               0x0
+#define PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID__SHIFT                                                     0x10
+#define PCIE_ERR_SRC_ID__ERR_CORR_SRC_ID_MASK                                                                 0x0000FFFFL
+#define PCIE_ERR_SRC_ID__ERR_FATAL_NONFATAL_SRC_ID_MASK                                                       0xFFFF0000L
+//BIF_CFG_DEV0_RC_PCIE_HDR_LOG4
+#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG4__TLP_HDR__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG4__TLP_HDR_MASK                                                           0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG0
+#define BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX__SHIFT                                               0x0
+#define BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG0__TLP_PREFIX_MASK                                                 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_PCIE_HDR_LOG5
+#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG5__TLP_HDR__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG5__TLP_HDR_MASK                                                           0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG1
+#define BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX__SHIFT                                               0x0
+#define BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG1__TLP_PREFIX_MASK                                                 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_PCIE_HDR_LOG6
+#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG6__TLP_HDR__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG6__TLP_HDR_MASK                                                           0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG2
+#define BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX__SHIFT                                               0x0
+#define BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG2__TLP_PREFIX_MASK                                                 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_PCIE_HDR_LOG7
+#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG7__TLP_HDR__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG7__TLP_HDR_MASK                                                           0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG3
+#define BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX__SHIFT                                               0x0
+#define BIF_CFG_DEV0_RC_PCIE_TLP_PREFIX_LOG3__TLP_PREFIX_MASK                                                 0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_PCIE_HDR_LOG8
+#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG8__TLP_HDR__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG8__TLP_HDR_MASK                                                           0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_PCIE_HDR_LOG9
+#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG9__TLP_HDR__SHIFT                                                         0x0
+#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG9__TLP_HDR_MASK                                                           0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_PCIE_HDR_LOG10
+#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG10__TLP_HDR__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG10__TLP_HDR_MASK                                                          0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_PCIE_HDR_LOG11
+#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG11__TLP_HDR__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG11__TLP_HDR_MASK                                                          0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_PCIE_HDR_LOG12
+#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG12__TLP_HDR__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG12__TLP_HDR_MASK                                                          0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_PCIE_HDR_LOG13
+#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG13__TLP_HDR__SHIFT                                                        0x0
+#define BIF_CFG_DEV0_RC_PCIE_HDR_LOG13__TLP_HDR_MASK                                                          0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID__SHIFT                                       0x0
+#define BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER__SHIFT                                      0x10
+#define BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR__SHIFT                                     0x14
+#define BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_ID_MASK                                         0x0000FFFFL
+#define BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__CAP_VER_MASK                                        0x000F0000L
+#define BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_ENH_CAP_LIST__NEXT_PTR_MASK                                       0xFFF00000L
+//BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_DW1
+#define BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO__SHIFT                                      0x0
+#define BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_DW1__SERIAL_NUMBER_LO_MASK                                        0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_DW2
+#define BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI__SHIFT                                      0x0
+#define BIF_CFG_DEV0_RC_PCIE_DEV_SERIAL_NUM_DW2__SERIAL_NUMBER_HI_MASK                                        0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_PCIE_ACS_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC_PCIE_ACS_ENH_CAP_LIST__CAP_ID__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_RC_PCIE_ACS_ENH_CAP_LIST__CAP_VER__SHIFT                                                 0x10
+#define BIF_CFG_DEV0_RC_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                0x14
+#define BIF_CFG_DEV0_RC_PCIE_ACS_ENH_CAP_LIST__CAP_ID_MASK                                                    0x0000FFFFL
+#define BIF_CFG_DEV0_RC_PCIE_ACS_ENH_CAP_LIST__CAP_VER_MASK                                                   0x000F0000L
+#define BIF_CFG_DEV0_RC_PCIE_ACS_ENH_CAP_LIST__NEXT_PTR_MASK                                                  0xFFF00000L
+//BIF_CFG_DEV0_RC_PCIE_ACS_CAP
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__SOURCE_VALIDATION__SHIFT                                                0x0
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__TRANSLATION_BLOCKING__SHIFT                                             0x1
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT__SHIFT                                             0x2
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT__SHIFT                                          0x3
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__UPSTREAM_FORWARDING__SHIFT                                              0x4
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__P2P_EGRESS_CONTROL__SHIFT                                               0x5
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P__SHIFT                                            0x6
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__ENHANCED_CAPABILITY__SHIFT                                              0x7
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE__SHIFT                                       0x8
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__SOURCE_VALIDATION_MASK                                                  0x0001L
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__TRANSLATION_BLOCKING_MASK                                               0x0002L
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__P2P_REQUEST_REDIRECT_MASK                                               0x0004L
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__P2P_COMPLETION_REDIRECT_MASK                                            0x0008L
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__UPSTREAM_FORWARDING_MASK                                                0x0010L
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__P2P_EGRESS_CONTROL_MASK                                                 0x0020L
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__DIRECT_TRANSLATED_P2P_MASK                                              0x0040L
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__ENHANCED_CAPABILITY_MASK                                                0x0080L
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CAP__EGRESS_CONTROL_VECTOR_SIZE_MASK                                         0xFF00L
+//BIF_CFG_DEV0_RC_PCIE_ACS_CNTL
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN__SHIFT                                            0x0
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN__SHIFT                                         0x1
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN__SHIFT                                         0x2
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN__SHIFT                                      0x3
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN__SHIFT                                          0x4
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN__SHIFT                                           0x5
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN__SHIFT                                        0x6
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN__SHIFT                                          0x7
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL__SHIFT                                   0x8
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL__SHIFT                                   0xa
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL__SHIFT                                 0xc
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__SOURCE_VALIDATION_EN_MASK                                              0x0001L
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__TRANSLATION_BLOCKING_EN_MASK                                           0x0002L
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__P2P_REQUEST_REDIRECT_EN_MASK                                           0x0004L
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__P2P_COMPLETION_REDIRECT_EN_MASK                                        0x0008L
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__UPSTREAM_FORWARDING_EN_MASK                                            0x0010L
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__P2P_EGRESS_CONTROL_EN_MASK                                             0x0020L
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__DIRECT_TRANSLATED_P2P_EN_MASK                                          0x0040L
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__IO_REQUEST_BLOCKING_EN_MASK                                            0x0080L
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__DSP_MEMORY_TARGET_ACCESS_CNTL_MASK                                     0x0300L
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__USP_MEMORY_TARGET_ACCESS_CNTL_MASK                                     0x0C00L
+#define BIF_CFG_DEV0_RC_PCIE_ACS_CNTL__UNCLAIMED_REQUEST_REDIRECT_CNTL_MASK                                   0x1000L
+//BIF_CFG_DEV0_RC_PCIE_RTR_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC_PCIE_RTR_ENH_CAP_LIST__CAP_ID__SHIFT                                                  0x0
+#define BIF_CFG_DEV0_RC_PCIE_RTR_ENH_CAP_LIST__CAP_VER__SHIFT                                                 0x10
+#define BIF_CFG_DEV0_RC_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                0x14
+#define BIF_CFG_DEV0_RC_PCIE_RTR_ENH_CAP_LIST__CAP_ID_MASK                                                    0x0000FFFFL
+#define BIF_CFG_DEV0_RC_PCIE_RTR_ENH_CAP_LIST__CAP_VER_MASK                                                   0x000F0000L
+#define BIF_CFG_DEV0_RC_PCIE_RTR_ENH_CAP_LIST__NEXT_PTR_MASK                                                  0xFFF00000L
+//BIF_CFG_DEV0_RC_RTR_DATA1
+#define BIF_CFG_DEV0_RC_RTR_DATA1__RESET_TIME__SHIFT                                                          0x0
+#define BIF_CFG_DEV0_RC_RTR_DATA1__DLUP_TIME__SHIFT                                                           0xc
+#define BIF_CFG_DEV0_RC_RTR_DATA1__RTR_VALID__SHIFT                                                           0x1f
+#define BIF_CFG_DEV0_RC_RTR_DATA1__RESET_TIME_MASK                                                            0x00000FFFL
+#define BIF_CFG_DEV0_RC_RTR_DATA1__DLUP_TIME_MASK                                                             0x00FFF000L
+#define BIF_CFG_DEV0_RC_RTR_DATA1__RTR_VALID_MASK                                                             0x80000000L
+//BIF_CFG_DEV0_RC_RTR_DATA2
+#define BIF_CFG_DEV0_RC_RTR_DATA2__FLR_TIME__SHIFT                                                            0x0
+#define BIF_CFG_DEV0_RC_RTR_DATA2__D3HOTD0_TIME__SHIFT                                                        0xc
+#define BIF_CFG_DEV0_RC_RTR_DATA2__FLR_TIME_MASK                                                              0x00000FFFL
+#define BIF_CFG_DEV0_RC_RTR_DATA2__D3HOTD0_TIME_MASK                                                          0x00FFF000L
+//BIF_CFG_DEV0_RC_IDE_ENH_CAP_LIST
+#define BIF_CFG_DEV0_RC_IDE_ENH_CAP_LIST__CAP_ID__SHIFT                                                       0x0
+#define BIF_CFG_DEV0_RC_IDE_ENH_CAP_LIST__CAP_VER__SHIFT                                                      0x10
+#define BIF_CFG_DEV0_RC_IDE_ENH_CAP_LIST__NEXT_PTR__SHIFT                                                     0x14
+#define BIF_CFG_DEV0_RC_IDE_ENH_CAP_LIST__CAP_ID_MASK                                                         0x0000FFFFL
+#define BIF_CFG_DEV0_RC_IDE_ENH_CAP_LIST__CAP_VER_MASK                                                        0x000F0000L
+#define BIF_CFG_DEV0_RC_IDE_ENH_CAP_LIST__NEXT_PTR_MASK                                                       0xFFF00000L
+//BIF_CFG_DEV0_RC_IDE_CAP
+#define BIF_CFG_DEV0_RC_IDE_CAP__IDE_CAP_LINK_IDE_STREAM_SUPPORTED__SHIFT                                     0x0
+#define BIF_CFG_DEV0_RC_IDE_CAP__IDE_CAP_SELECTIVE_IDE_STREAM_SUPPORTED__SHIFT                                0x1
+#define BIF_CFG_DEV0_RC_IDE_CAP__IDE_CAP_FLOW_THROUGH_IDE_STREAM_SUPPORTED__SHIFT                             0x2
+#define BIF_CFG_DEV0_RC_IDE_CAP__IDE_CAP_PARTIAL_HDR_ENCRYPTION_SUPPORTED__SHIFT                              0x3
+#define BIF_CFG_DEV0_RC_IDE_CAP__IDE_CAP_AGGREGATION_SUPPORTED__SHIFT                                         0x4
+#define BIF_CFG_DEV0_RC_IDE_CAP__IDE_CAP_PCRC_SUPPORTED__SHIFT                                                0x5
+#define BIF_CFG_DEV0_RC_IDE_CAP__IDE_CAP_IDE_KM_PROTOCOL_SUPPORTED__SHIFT                                     0x6
+#define BIF_CFG_DEV0_RC_IDE_CAP__IDE_CAP_SELECTIVE_IDE_FOR_CFG_REQ_SUPPORTED__SHIFT                           0x7
+#define BIF_CFG_DEV0_RC_IDE_CAP__IDE_CAP_SUPPORTED_ALGORITHMS__SHIFT                                          0x8
+#define BIF_CFG_DEV0_RC_IDE_CAP__IDE_CAP_NUM_OF_TCS_SUPPORTED_FOR_LINK_IDE__SHIFT                             0xd
+#define BIF_CFG_DEV0_RC_IDE_CAP__IDE_CAP_NUM_OF_SELECTIVE_IDE_STREAMS_SUPPORTED__SHIFT                        0x10
+#define BIF_CFG_DEV0_RC_IDE_CAP__IDE_CAP_TEE_LIMITED_SUPPORTED__SHIFT                                         0x18
+#define BIF_CFG_DEV0_RC_IDE_CAP__IDE_CAP_XT_SUPPORTED__SHIFT                                                  0x19
+#define BIF_CFG_DEV0_RC_IDE_CAP__IDE_CAP_LINK_IDE_STREAM_SUPPORTED_MASK                                       0x00000001L
+#define BIF_CFG_DEV0_RC_IDE_CAP__IDE_CAP_SELECTIVE_IDE_STREAM_SUPPORTED_MASK                                  0x00000002L
+#define BIF_CFG_DEV0_RC_IDE_CAP__IDE_CAP_FLOW_THROUGH_IDE_STREAM_SUPPORTED_MASK                               0x00000004L
+#define BIF_CFG_DEV0_RC_IDE_CAP__IDE_CAP_PARTIAL_HDR_ENCRYPTION_SUPPORTED_MASK                                0x00000008L
+#define BIF_CFG_DEV0_RC_IDE_CAP__IDE_CAP_AGGREGATION_SUPPORTED_MASK                                           0x00000010L
+#define BIF_CFG_DEV0_RC_IDE_CAP__IDE_CAP_PCRC_SUPPORTED_MASK                                                  0x00000020L
+#define BIF_CFG_DEV0_RC_IDE_CAP__IDE_CAP_IDE_KM_PROTOCOL_SUPPORTED_MASK                                       0x00000040L
+#define BIF_CFG_DEV0_RC_IDE_CAP__IDE_CAP_SELECTIVE_IDE_FOR_CFG_REQ_SUPPORTED_MASK                             0x00000080L
+#define BIF_CFG_DEV0_RC_IDE_CAP__IDE_CAP_SUPPORTED_ALGORITHMS_MASK                                            0x00001F00L
+#define BIF_CFG_DEV0_RC_IDE_CAP__IDE_CAP_NUM_OF_TCS_SUPPORTED_FOR_LINK_IDE_MASK                               0x0000E000L
+#define BIF_CFG_DEV0_RC_IDE_CAP__IDE_CAP_NUM_OF_SELECTIVE_IDE_STREAMS_SUPPORTED_MASK                          0x00FF0000L
+#define BIF_CFG_DEV0_RC_IDE_CAP__IDE_CAP_TEE_LIMITED_SUPPORTED_MASK                                           0x01000000L
+#define BIF_CFG_DEV0_RC_IDE_CAP__IDE_CAP_XT_SUPPORTED_MASK                                                    0x02000000L
+//BIF_CFG_DEV0_RC_IDE_CNTL
+#define BIF_CFG_DEV0_RC_IDE_CNTL__IDE_CNTL_FLOW_THROUGH_IDE_STREAM_ENABLED__SHIFT                             0x2
+#define BIF_CFG_DEV0_RC_IDE_CNTL__IDE_CNTL_FLOW_THROUGH_IDE_STREAM_ENABLED_MASK                               0x00000004L
+//BIF_CFG_DEV0_RC_LINK_IDE_STREAM_0_CNTL
+#define BIF_CFG_DEV0_RC_LINK_IDE_STREAM_0_CNTL__LINK_IDE_STREAM_ENABLE__SHIFT                                 0x0
+#define BIF_CFG_DEV0_RC_LINK_IDE_STREAM_0_CNTL__XT_ENABLE__SHIFT                                              0x1
+#define BIF_CFG_DEV0_RC_LINK_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT                                0x2
+#define BIF_CFG_DEV0_RC_LINK_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_PR__SHIFT                                 0x4
+#define BIF_CFG_DEV0_RC_LINK_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT                                0x6
+#define BIF_CFG_DEV0_RC_LINK_IDE_STREAM_0_CNTL__PCRC_ENABLE__SHIFT                                            0x8
+#define BIF_CFG_DEV0_RC_LINK_IDE_STREAM_0_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT                               0xa
+#define BIF_CFG_DEV0_RC_LINK_IDE_STREAM_0_CNTL__SELECTED_ALGORITHM__SHIFT                                     0xe
+#define BIF_CFG_DEV0_RC_LINK_IDE_STREAM_0_CNTL__TC__SHIFT                                                     0x13
+#define BIF_CFG_DEV0_RC_LINK_IDE_STREAM_0_CNTL__STREAM_ID__SHIFT                                              0x18
+#define BIF_CFG_DEV0_RC_LINK_IDE_STREAM_0_CNTL__LINK_IDE_STREAM_ENABLE_MASK                                   0x00000001L
+#define BIF_CFG_DEV0_RC_LINK_IDE_STREAM_0_CNTL__XT_ENABLE_MASK                                                0x00000002L
+#define BIF_CFG_DEV0_RC_LINK_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_NPR_MASK                                  0x0000000CL
+#define BIF_CFG_DEV0_RC_LINK_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_PR_MASK                                   0x00000030L
+#define BIF_CFG_DEV0_RC_LINK_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_CPL_MASK                                  0x000000C0L
+#define BIF_CFG_DEV0_RC_LINK_IDE_STREAM_0_CNTL__PCRC_ENABLE_MASK                                              0x00000100L
+#define BIF_CFG_DEV0_RC_LINK_IDE_STREAM_0_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK                                 0x00003C00L
+#define BIF_CFG_DEV0_RC_LINK_IDE_STREAM_0_CNTL__SELECTED_ALGORITHM_MASK                                       0x0007C000L
+#define BIF_CFG_DEV0_RC_LINK_IDE_STREAM_0_CNTL__TC_MASK                                                       0x00380000L
+#define BIF_CFG_DEV0_RC_LINK_IDE_STREAM_0_CNTL__STREAM_ID_MASK                                                0xFF000000L
+//BIF_CFG_DEV0_RC_LINK_IDE_STREAM_0_STATUS
+#define BIF_CFG_DEV0_RC_LINK_IDE_STREAM_0_STATUS__LINK_IDE_STREAM_STATE__SHIFT                                0x0
+#define BIF_CFG_DEV0_RC_LINK_IDE_STREAM_0_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT                                0x1f
+#define BIF_CFG_DEV0_RC_LINK_IDE_STREAM_0_STATUS__LINK_IDE_STREAM_STATE_MASK                                  0x0000000FL
+#define BIF_CFG_DEV0_RC_LINK_IDE_STREAM_0_STATUS__RECEIVED_IDE_FAIL_MSG_MASK                                  0x80000000L
+//BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CAP
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT                      0x0
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK                        0x0000000FL
+//BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CNTL
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT                       0x0
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CNTL__XT_ENABLE__SHIFT                                         0x1
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT                           0x2
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_PR__SHIFT                            0x4
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT                           0x6
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CNTL__PCRC_ENABLE__SHIFT                                       0x8
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT                      0x9
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT                          0xa
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CNTL__SELECTED_ALGORITHM__SHIFT                                0xe
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CNTL__TC__SHIFT                                                0x13
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CNTL__DEFAULT_STREAM__SHIFT                                    0x16
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CNTL__TEE_LIMITED_STREAM__SHIFT                                0x17
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CNTL__STREAM_ID__SHIFT                                         0x18
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK                         0x00000001L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CNTL__XT_ENABLE_MASK                                           0x00000002L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_NPR_MASK                             0x0000000CL
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_PR_MASK                              0x00000030L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CNTL__TX_AGGREGATION_MODE_CPL_MASK                             0x000000C0L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CNTL__PCRC_ENABLE_MASK                                         0x00000100L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK                        0x00000200L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK                            0x00003C00L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CNTL__SELECTED_ALGORITHM_MASK                                  0x0007C000L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CNTL__TC_MASK                                                  0x00380000L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CNTL__DEFAULT_STREAM_MASK                                      0x00400000L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CNTL__TEE_LIMITED_STREAM_MASK                                  0x00800000L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_CNTL__STREAM_ID_MASK                                           0xFF000000L
+//BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_STATUS
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT                      0x0
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT                           0x1f
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK                        0x0000000FL
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_0_STATUS__RECEIVED_IDE_FAIL_MSG_MASK                             0x80000000L
+//BIF_CFG_DEV0_RC_IDE_0_RID_ASSOCIATION_REG1
+#define BIF_CFG_DEV0_RC_IDE_0_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT                                          0x8
+#define BIF_CFG_DEV0_RC_IDE_0_RID_ASSOCIATION_REG1__RID_LIMIT_MASK                                            0x00FFFF00L
+//BIF_CFG_DEV0_RC_IDE_0_RID_ASSOCIATION_REG2
+#define BIF_CFG_DEV0_RC_IDE_0_RID_ASSOCIATION_REG2__VALID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_RC_IDE_0_RID_ASSOCIATION_REG2__RID_BASE__SHIFT                                           0x8
+#define BIF_CFG_DEV0_RC_IDE_0_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT                                       0x18
+#define BIF_CFG_DEV0_RC_IDE_0_RID_ASSOCIATION_REG2__VALID_MASK                                                0x00000001L
+#define BIF_CFG_DEV0_RC_IDE_0_RID_ASSOCIATION_REG2__RID_BASE_MASK                                             0x00FFFF00L
+#define BIF_CFG_DEV0_RC_IDE_0_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK                                         0xFF000000L
+//BIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_0_REG1
+#define BIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT                                           0x0
+#define BIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT                                  0x8
+#define BIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT                                 0x14
+#define BIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_0_REG1__VALID_MASK                                             0x00000001L
+#define BIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK                                    0x000FFF00L
+#define BIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK                                   0xFFF00000L
+//BIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_0_REG2
+#define BIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT                                 0x0
+#define BIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK                                   0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_0_REG3
+#define BIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT                                  0x0
+#define BIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK                                    0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_1_REG1
+#define BIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT                                           0x0
+#define BIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT                                  0x8
+#define BIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT                                 0x14
+#define BIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_1_REG1__VALID_MASK                                             0x00000001L
+#define BIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK                                    0x000FFF00L
+#define BIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK                                   0xFFF00000L
+//BIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_1_REG2
+#define BIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT                                 0x0
+#define BIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK                                   0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_1_REG3
+#define BIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT                                  0x0
+#define BIF_CFG_DEV0_RC_IDE_0_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK                                    0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CAP
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT                      0x0
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK                        0x0000000FL
+//BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CNTL
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT                       0x0
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CNTL__XT_ENABLE__SHIFT                                         0x1
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT                           0x2
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CNTL__TX_AGGREGATION_MODE_PR__SHIFT                            0x4
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT                           0x6
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CNTL__PCRC_ENABLE__SHIFT                                       0x8
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT                      0x9
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT                          0xa
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CNTL__SELECTED_ALGORITHM__SHIFT                                0xe
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CNTL__TC__SHIFT                                                0x13
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CNTL__DEFAULT_STREAM__SHIFT                                    0x16
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CNTL__TEE_LIMITED_STREAM__SHIFT                                0x17
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CNTL__STREAM_ID__SHIFT                                         0x18
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK                         0x00000001L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CNTL__XT_ENABLE_MASK                                           0x00000002L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CNTL__TX_AGGREGATION_MODE_NPR_MASK                             0x0000000CL
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CNTL__TX_AGGREGATION_MODE_PR_MASK                              0x00000030L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CNTL__TX_AGGREGATION_MODE_CPL_MASK                             0x000000C0L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CNTL__PCRC_ENABLE_MASK                                         0x00000100L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK                        0x00000200L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK                            0x00003C00L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CNTL__SELECTED_ALGORITHM_MASK                                  0x0007C000L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CNTL__TC_MASK                                                  0x00380000L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CNTL__DEFAULT_STREAM_MASK                                      0x00400000L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CNTL__TEE_LIMITED_STREAM_MASK                                  0x00800000L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_CNTL__STREAM_ID_MASK                                           0xFF000000L
+//BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_STATUS
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT                      0x0
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT                           0x1f
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK                        0x0000000FL
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_1_STATUS__RECEIVED_IDE_FAIL_MSG_MASK                             0x80000000L
+//BIF_CFG_DEV0_RC_IDE_1_RID_ASSOCIATION_REG1
+#define BIF_CFG_DEV0_RC_IDE_1_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT                                          0x8
+#define BIF_CFG_DEV0_RC_IDE_1_RID_ASSOCIATION_REG1__RID_LIMIT_MASK                                            0x00FFFF00L
+//BIF_CFG_DEV0_RC_IDE_1_RID_ASSOCIATION_REG2
+#define BIF_CFG_DEV0_RC_IDE_1_RID_ASSOCIATION_REG2__VALID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_RC_IDE_1_RID_ASSOCIATION_REG2__RID_BASE__SHIFT                                           0x8
+#define BIF_CFG_DEV0_RC_IDE_1_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT                                       0x18
+#define BIF_CFG_DEV0_RC_IDE_1_RID_ASSOCIATION_REG2__VALID_MASK                                                0x00000001L
+#define BIF_CFG_DEV0_RC_IDE_1_RID_ASSOCIATION_REG2__RID_BASE_MASK                                             0x00FFFF00L
+#define BIF_CFG_DEV0_RC_IDE_1_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK                                         0xFF000000L
+//BIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_0_REG1
+#define BIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT                                           0x0
+#define BIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT                                  0x8
+#define BIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT                                 0x14
+#define BIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_0_REG1__VALID_MASK                                             0x00000001L
+#define BIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK                                    0x000FFF00L
+#define BIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK                                   0xFFF00000L
+//BIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_0_REG2
+#define BIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT                                 0x0
+#define BIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK                                   0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_0_REG3
+#define BIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT                                  0x0
+#define BIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK                                    0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_1_REG1
+#define BIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT                                           0x0
+#define BIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT                                  0x8
+#define BIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT                                 0x14
+#define BIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_1_REG1__VALID_MASK                                             0x00000001L
+#define BIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK                                    0x000FFF00L
+#define BIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK                                   0xFFF00000L
+//BIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_1_REG2
+#define BIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT                                 0x0
+#define BIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK                                   0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_1_REG3
+#define BIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT                                  0x0
+#define BIF_CFG_DEV0_RC_IDE_1_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK                                    0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CAP
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT                      0x0
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK                        0x0000000FL
+//BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CNTL
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT                       0x0
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CNTL__XT_ENABLE__SHIFT                                         0x1
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT                           0x2
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CNTL__TX_AGGREGATION_MODE_PR__SHIFT                            0x4
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT                           0x6
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CNTL__PCRC_ENABLE__SHIFT                                       0x8
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT                      0x9
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT                          0xa
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CNTL__SELECTED_ALGORITHM__SHIFT                                0xe
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CNTL__TC__SHIFT                                                0x13
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CNTL__DEFAULT_STREAM__SHIFT                                    0x16
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CNTL__TEE_LIMITED_STREAM__SHIFT                                0x17
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CNTL__STREAM_ID__SHIFT                                         0x18
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK                         0x00000001L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CNTL__XT_ENABLE_MASK                                           0x00000002L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CNTL__TX_AGGREGATION_MODE_NPR_MASK                             0x0000000CL
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CNTL__TX_AGGREGATION_MODE_PR_MASK                              0x00000030L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CNTL__TX_AGGREGATION_MODE_CPL_MASK                             0x000000C0L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CNTL__PCRC_ENABLE_MASK                                         0x00000100L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK                        0x00000200L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK                            0x00003C00L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CNTL__SELECTED_ALGORITHM_MASK                                  0x0007C000L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CNTL__TC_MASK                                                  0x00380000L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CNTL__DEFAULT_STREAM_MASK                                      0x00400000L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CNTL__TEE_LIMITED_STREAM_MASK                                  0x00800000L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_CNTL__STREAM_ID_MASK                                           0xFF000000L
+//BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_STATUS
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT                      0x0
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT                           0x1f
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK                        0x0000000FL
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_2_STATUS__RECEIVED_IDE_FAIL_MSG_MASK                             0x80000000L
+//BIF_CFG_DEV0_RC_IDE_2_RID_ASSOCIATION_REG1
+#define BIF_CFG_DEV0_RC_IDE_2_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT                                          0x8
+#define BIF_CFG_DEV0_RC_IDE_2_RID_ASSOCIATION_REG1__RID_LIMIT_MASK                                            0x00FFFF00L
+//BIF_CFG_DEV0_RC_IDE_2_RID_ASSOCIATION_REG2
+#define BIF_CFG_DEV0_RC_IDE_2_RID_ASSOCIATION_REG2__VALID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_RC_IDE_2_RID_ASSOCIATION_REG2__RID_BASE__SHIFT                                           0x8
+#define BIF_CFG_DEV0_RC_IDE_2_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT                                       0x18
+#define BIF_CFG_DEV0_RC_IDE_2_RID_ASSOCIATION_REG2__VALID_MASK                                                0x00000001L
+#define BIF_CFG_DEV0_RC_IDE_2_RID_ASSOCIATION_REG2__RID_BASE_MASK                                             0x00FFFF00L
+#define BIF_CFG_DEV0_RC_IDE_2_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK                                         0xFF000000L
+//BIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_0_REG1
+#define BIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT                                           0x0
+#define BIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT                                  0x8
+#define BIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT                                 0x14
+#define BIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_0_REG1__VALID_MASK                                             0x00000001L
+#define BIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK                                    0x000FFF00L
+#define BIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK                                   0xFFF00000L
+//BIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_0_REG2
+#define BIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT                                 0x0
+#define BIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK                                   0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_0_REG3
+#define BIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT                                  0x0
+#define BIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK                                    0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_1_REG1
+#define BIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT                                           0x0
+#define BIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT                                  0x8
+#define BIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT                                 0x14
+#define BIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_1_REG1__VALID_MASK                                             0x00000001L
+#define BIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK                                    0x000FFF00L
+#define BIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK                                   0xFFF00000L
+//BIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_1_REG2
+#define BIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT                                 0x0
+#define BIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK                                   0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_1_REG3
+#define BIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT                                  0x0
+#define BIF_CFG_DEV0_RC_IDE_2_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK                                    0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CAP
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT                      0x0
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK                        0x0000000FL
+//BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CNTL
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT                       0x0
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CNTL__XT_ENABLE__SHIFT                                         0x1
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT                           0x2
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CNTL__TX_AGGREGATION_MODE_PR__SHIFT                            0x4
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT                           0x6
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CNTL__PCRC_ENABLE__SHIFT                                       0x8
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT                      0x9
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT                          0xa
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CNTL__SELECTED_ALGORITHM__SHIFT                                0xe
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CNTL__TC__SHIFT                                                0x13
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CNTL__DEFAULT_STREAM__SHIFT                                    0x16
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CNTL__TEE_LIMITED_STREAM__SHIFT                                0x17
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CNTL__STREAM_ID__SHIFT                                         0x18
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK                         0x00000001L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CNTL__XT_ENABLE_MASK                                           0x00000002L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CNTL__TX_AGGREGATION_MODE_NPR_MASK                             0x0000000CL
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CNTL__TX_AGGREGATION_MODE_PR_MASK                              0x00000030L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CNTL__TX_AGGREGATION_MODE_CPL_MASK                             0x000000C0L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CNTL__PCRC_ENABLE_MASK                                         0x00000100L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK                        0x00000200L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK                            0x00003C00L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CNTL__SELECTED_ALGORITHM_MASK                                  0x0007C000L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CNTL__TC_MASK                                                  0x00380000L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CNTL__DEFAULT_STREAM_MASK                                      0x00400000L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CNTL__TEE_LIMITED_STREAM_MASK                                  0x00800000L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_CNTL__STREAM_ID_MASK                                           0xFF000000L
+//BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_STATUS
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT                      0x0
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT                           0x1f
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK                        0x0000000FL
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_3_STATUS__RECEIVED_IDE_FAIL_MSG_MASK                             0x80000000L
+//BIF_CFG_DEV0_RC_IDE_3_RID_ASSOCIATION_REG1
+#define BIF_CFG_DEV0_RC_IDE_3_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT                                          0x8
+#define BIF_CFG_DEV0_RC_IDE_3_RID_ASSOCIATION_REG1__RID_LIMIT_MASK                                            0x00FFFF00L
+//BIF_CFG_DEV0_RC_IDE_3_RID_ASSOCIATION_REG2
+#define BIF_CFG_DEV0_RC_IDE_3_RID_ASSOCIATION_REG2__VALID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_RC_IDE_3_RID_ASSOCIATION_REG2__RID_BASE__SHIFT                                           0x8
+#define BIF_CFG_DEV0_RC_IDE_3_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT                                       0x18
+#define BIF_CFG_DEV0_RC_IDE_3_RID_ASSOCIATION_REG2__VALID_MASK                                                0x00000001L
+#define BIF_CFG_DEV0_RC_IDE_3_RID_ASSOCIATION_REG2__RID_BASE_MASK                                             0x00FFFF00L
+#define BIF_CFG_DEV0_RC_IDE_3_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK                                         0xFF000000L
+//BIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_0_REG1
+#define BIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT                                           0x0
+#define BIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT                                  0x8
+#define BIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT                                 0x14
+#define BIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_0_REG1__VALID_MASK                                             0x00000001L
+#define BIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK                                    0x000FFF00L
+#define BIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK                                   0xFFF00000L
+//BIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_0_REG2
+#define BIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT                                 0x0
+#define BIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK                                   0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_0_REG3
+#define BIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT                                  0x0
+#define BIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK                                    0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_1_REG1
+#define BIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT                                           0x0
+#define BIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT                                  0x8
+#define BIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT                                 0x14
+#define BIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_1_REG1__VALID_MASK                                             0x00000001L
+#define BIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK                                    0x000FFF00L
+#define BIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK                                   0xFFF00000L
+//BIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_1_REG2
+#define BIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT                                 0x0
+#define BIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK                                   0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_1_REG3
+#define BIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT                                  0x0
+#define BIF_CFG_DEV0_RC_IDE_3_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK                                    0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CAP
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT                      0x0
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK                        0x0000000FL
+//BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CNTL
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT                       0x0
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CNTL__XT_ENABLE__SHIFT                                         0x1
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT                           0x2
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CNTL__TX_AGGREGATION_MODE_PR__SHIFT                            0x4
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT                           0x6
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CNTL__PCRC_ENABLE__SHIFT                                       0x8
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT                      0x9
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT                          0xa
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CNTL__SELECTED_ALGORITHM__SHIFT                                0xe
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CNTL__TC__SHIFT                                                0x13
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CNTL__DEFAULT_STREAM__SHIFT                                    0x16
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CNTL__TEE_LIMITED_STREAM__SHIFT                                0x17
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CNTL__STREAM_ID__SHIFT                                         0x18
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK                         0x00000001L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CNTL__XT_ENABLE_MASK                                           0x00000002L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CNTL__TX_AGGREGATION_MODE_NPR_MASK                             0x0000000CL
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CNTL__TX_AGGREGATION_MODE_PR_MASK                              0x00000030L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CNTL__TX_AGGREGATION_MODE_CPL_MASK                             0x000000C0L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CNTL__PCRC_ENABLE_MASK                                         0x00000100L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK                        0x00000200L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK                            0x00003C00L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CNTL__SELECTED_ALGORITHM_MASK                                  0x0007C000L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CNTL__TC_MASK                                                  0x00380000L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CNTL__DEFAULT_STREAM_MASK                                      0x00400000L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CNTL__TEE_LIMITED_STREAM_MASK                                  0x00800000L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_CNTL__STREAM_ID_MASK                                           0xFF000000L
+//BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_STATUS
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT                      0x0
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT                           0x1f
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK                        0x0000000FL
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_4_STATUS__RECEIVED_IDE_FAIL_MSG_MASK                             0x80000000L
+//BIF_CFG_DEV0_RC_IDE_4_RID_ASSOCIATION_REG1
+#define BIF_CFG_DEV0_RC_IDE_4_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT                                          0x8
+#define BIF_CFG_DEV0_RC_IDE_4_RID_ASSOCIATION_REG1__RID_LIMIT_MASK                                            0x00FFFF00L
+//BIF_CFG_DEV0_RC_IDE_4_RID_ASSOCIATION_REG2
+#define BIF_CFG_DEV0_RC_IDE_4_RID_ASSOCIATION_REG2__VALID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_RC_IDE_4_RID_ASSOCIATION_REG2__RID_BASE__SHIFT                                           0x8
+#define BIF_CFG_DEV0_RC_IDE_4_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT                                       0x18
+#define BIF_CFG_DEV0_RC_IDE_4_RID_ASSOCIATION_REG2__VALID_MASK                                                0x00000001L
+#define BIF_CFG_DEV0_RC_IDE_4_RID_ASSOCIATION_REG2__RID_BASE_MASK                                             0x00FFFF00L
+#define BIF_CFG_DEV0_RC_IDE_4_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK                                         0xFF000000L
+//BIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_0_REG1
+#define BIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT                                           0x0
+#define BIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT                                  0x8
+#define BIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT                                 0x14
+#define BIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_0_REG1__VALID_MASK                                             0x00000001L
+#define BIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK                                    0x000FFF00L
+#define BIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK                                   0xFFF00000L
+//BIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_0_REG2
+#define BIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT                                 0x0
+#define BIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK                                   0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_0_REG3
+#define BIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT                                  0x0
+#define BIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK                                    0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_1_REG1
+#define BIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT                                           0x0
+#define BIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT                                  0x8
+#define BIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT                                 0x14
+#define BIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_1_REG1__VALID_MASK                                             0x00000001L
+#define BIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK                                    0x000FFF00L
+#define BIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK                                   0xFFF00000L
+//BIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_1_REG2
+#define BIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT                                 0x0
+#define BIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK                                   0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_1_REG3
+#define BIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT                                  0x0
+#define BIF_CFG_DEV0_RC_IDE_4_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK                                    0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CAP
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT                      0x0
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK                        0x0000000FL
+//BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CNTL
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT                       0x0
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CNTL__XT_ENABLE__SHIFT                                         0x1
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT                           0x2
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CNTL__TX_AGGREGATION_MODE_PR__SHIFT                            0x4
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT                           0x6
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CNTL__PCRC_ENABLE__SHIFT                                       0x8
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT                      0x9
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT                          0xa
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CNTL__SELECTED_ALGORITHM__SHIFT                                0xe
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CNTL__TC__SHIFT                                                0x13
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CNTL__DEFAULT_STREAM__SHIFT                                    0x16
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CNTL__TEE_LIMITED_STREAM__SHIFT                                0x17
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CNTL__STREAM_ID__SHIFT                                         0x18
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK                         0x00000001L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CNTL__XT_ENABLE_MASK                                           0x00000002L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CNTL__TX_AGGREGATION_MODE_NPR_MASK                             0x0000000CL
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CNTL__TX_AGGREGATION_MODE_PR_MASK                              0x00000030L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CNTL__TX_AGGREGATION_MODE_CPL_MASK                             0x000000C0L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CNTL__PCRC_ENABLE_MASK                                         0x00000100L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK                        0x00000200L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK                            0x00003C00L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CNTL__SELECTED_ALGORITHM_MASK                                  0x0007C000L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CNTL__TC_MASK                                                  0x00380000L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CNTL__DEFAULT_STREAM_MASK                                      0x00400000L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CNTL__TEE_LIMITED_STREAM_MASK                                  0x00800000L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_CNTL__STREAM_ID_MASK                                           0xFF000000L
+//BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_STATUS
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT                      0x0
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT                           0x1f
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK                        0x0000000FL
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_5_STATUS__RECEIVED_IDE_FAIL_MSG_MASK                             0x80000000L
+//BIF_CFG_DEV0_RC_IDE_5_RID_ASSOCIATION_REG1
+#define BIF_CFG_DEV0_RC_IDE_5_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT                                          0x8
+#define BIF_CFG_DEV0_RC_IDE_5_RID_ASSOCIATION_REG1__RID_LIMIT_MASK                                            0x00FFFF00L
+//BIF_CFG_DEV0_RC_IDE_5_RID_ASSOCIATION_REG2
+#define BIF_CFG_DEV0_RC_IDE_5_RID_ASSOCIATION_REG2__VALID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_RC_IDE_5_RID_ASSOCIATION_REG2__RID_BASE__SHIFT                                           0x8
+#define BIF_CFG_DEV0_RC_IDE_5_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT                                       0x18
+#define BIF_CFG_DEV0_RC_IDE_5_RID_ASSOCIATION_REG2__VALID_MASK                                                0x00000001L
+#define BIF_CFG_DEV0_RC_IDE_5_RID_ASSOCIATION_REG2__RID_BASE_MASK                                             0x00FFFF00L
+#define BIF_CFG_DEV0_RC_IDE_5_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK                                         0xFF000000L
+//BIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_0_REG1
+#define BIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT                                           0x0
+#define BIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT                                  0x8
+#define BIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT                                 0x14
+#define BIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_0_REG1__VALID_MASK                                             0x00000001L
+#define BIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK                                    0x000FFF00L
+#define BIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK                                   0xFFF00000L
+//BIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_0_REG2
+#define BIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT                                 0x0
+#define BIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK                                   0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_0_REG3
+#define BIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT                                  0x0
+#define BIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK                                    0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_1_REG1
+#define BIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT                                           0x0
+#define BIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT                                  0x8
+#define BIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT                                 0x14
+#define BIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_1_REG1__VALID_MASK                                             0x00000001L
+#define BIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK                                    0x000FFF00L
+#define BIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK                                   0xFFF00000L
+//BIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_1_REG2
+#define BIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT                                 0x0
+#define BIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK                                   0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_1_REG3
+#define BIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT                                  0x0
+#define BIF_CFG_DEV0_RC_IDE_5_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK                                    0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CAP
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT                      0x0
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK                        0x0000000FL
+//BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CNTL
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT                       0x0
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CNTL__XT_ENABLE__SHIFT                                         0x1
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT                           0x2
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CNTL__TX_AGGREGATION_MODE_PR__SHIFT                            0x4
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT                           0x6
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CNTL__PCRC_ENABLE__SHIFT                                       0x8
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT                      0x9
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT                          0xa
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CNTL__SELECTED_ALGORITHM__SHIFT                                0xe
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CNTL__TC__SHIFT                                                0x13
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CNTL__DEFAULT_STREAM__SHIFT                                    0x16
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CNTL__TEE_LIMITED_STREAM__SHIFT                                0x17
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CNTL__STREAM_ID__SHIFT                                         0x18
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK                         0x00000001L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CNTL__XT_ENABLE_MASK                                           0x00000002L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CNTL__TX_AGGREGATION_MODE_NPR_MASK                             0x0000000CL
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CNTL__TX_AGGREGATION_MODE_PR_MASK                              0x00000030L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CNTL__TX_AGGREGATION_MODE_CPL_MASK                             0x000000C0L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CNTL__PCRC_ENABLE_MASK                                         0x00000100L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK                        0x00000200L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK                            0x00003C00L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CNTL__SELECTED_ALGORITHM_MASK                                  0x0007C000L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CNTL__TC_MASK                                                  0x00380000L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CNTL__DEFAULT_STREAM_MASK                                      0x00400000L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CNTL__TEE_LIMITED_STREAM_MASK                                  0x00800000L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_CNTL__STREAM_ID_MASK                                           0xFF000000L
+//BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_STATUS
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT                      0x0
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT                           0x1f
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK                        0x0000000FL
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_6_STATUS__RECEIVED_IDE_FAIL_MSG_MASK                             0x80000000L
+//BIF_CFG_DEV0_RC_IDE_6_RID_ASSOCIATION_REG1
+#define BIF_CFG_DEV0_RC_IDE_6_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT                                          0x8
+#define BIF_CFG_DEV0_RC_IDE_6_RID_ASSOCIATION_REG1__RID_LIMIT_MASK                                            0x00FFFF00L
+//BIF_CFG_DEV0_RC_IDE_6_RID_ASSOCIATION_REG2
+#define BIF_CFG_DEV0_RC_IDE_6_RID_ASSOCIATION_REG2__VALID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_RC_IDE_6_RID_ASSOCIATION_REG2__RID_BASE__SHIFT                                           0x8
+#define BIF_CFG_DEV0_RC_IDE_6_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT                                       0x18
+#define BIF_CFG_DEV0_RC_IDE_6_RID_ASSOCIATION_REG2__VALID_MASK                                                0x00000001L
+#define BIF_CFG_DEV0_RC_IDE_6_RID_ASSOCIATION_REG2__RID_BASE_MASK                                             0x00FFFF00L
+#define BIF_CFG_DEV0_RC_IDE_6_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK                                         0xFF000000L
+//BIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_0_REG1
+#define BIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT                                           0x0
+#define BIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT                                  0x8
+#define BIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT                                 0x14
+#define BIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_0_REG1__VALID_MASK                                             0x00000001L
+#define BIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK                                    0x000FFF00L
+#define BIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK                                   0xFFF00000L
+//BIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_0_REG2
+#define BIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT                                 0x0
+#define BIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK                                   0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_0_REG3
+#define BIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT                                  0x0
+#define BIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK                                    0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_1_REG1
+#define BIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT                                           0x0
+#define BIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT                                  0x8
+#define BIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT                                 0x14
+#define BIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_1_REG1__VALID_MASK                                             0x00000001L
+#define BIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK                                    0x000FFF00L
+#define BIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK                                   0xFFF00000L
+//BIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_1_REG2
+#define BIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT                                 0x0
+#define BIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK                                   0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_1_REG3
+#define BIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT                                  0x0
+#define BIF_CFG_DEV0_RC_IDE_6_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK                                    0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CAP
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT                      0x0
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK                        0x0000000FL
+//BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CNTL
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT                       0x0
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CNTL__XT_ENABLE__SHIFT                                         0x1
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT                           0x2
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CNTL__TX_AGGREGATION_MODE_PR__SHIFT                            0x4
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT                           0x6
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CNTL__PCRC_ENABLE__SHIFT                                       0x8
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT                      0x9
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT                          0xa
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CNTL__SELECTED_ALGORITHM__SHIFT                                0xe
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CNTL__TC__SHIFT                                                0x13
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CNTL__DEFAULT_STREAM__SHIFT                                    0x16
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CNTL__TEE_LIMITED_STREAM__SHIFT                                0x17
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CNTL__STREAM_ID__SHIFT                                         0x18
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK                         0x00000001L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CNTL__XT_ENABLE_MASK                                           0x00000002L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CNTL__TX_AGGREGATION_MODE_NPR_MASK                             0x0000000CL
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CNTL__TX_AGGREGATION_MODE_PR_MASK                              0x00000030L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CNTL__TX_AGGREGATION_MODE_CPL_MASK                             0x000000C0L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CNTL__PCRC_ENABLE_MASK                                         0x00000100L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK                        0x00000200L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK                            0x00003C00L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CNTL__SELECTED_ALGORITHM_MASK                                  0x0007C000L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CNTL__TC_MASK                                                  0x00380000L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CNTL__DEFAULT_STREAM_MASK                                      0x00400000L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CNTL__TEE_LIMITED_STREAM_MASK                                  0x00800000L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_CNTL__STREAM_ID_MASK                                           0xFF000000L
+//BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_STATUS
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT                      0x0
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT                           0x1f
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK                        0x0000000FL
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_7_STATUS__RECEIVED_IDE_FAIL_MSG_MASK                             0x80000000L
+//BIF_CFG_DEV0_RC_IDE_7_RID_ASSOCIATION_REG1
+#define BIF_CFG_DEV0_RC_IDE_7_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT                                          0x8
+#define BIF_CFG_DEV0_RC_IDE_7_RID_ASSOCIATION_REG1__RID_LIMIT_MASK                                            0x00FFFF00L
+//BIF_CFG_DEV0_RC_IDE_7_RID_ASSOCIATION_REG2
+#define BIF_CFG_DEV0_RC_IDE_7_RID_ASSOCIATION_REG2__VALID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_RC_IDE_7_RID_ASSOCIATION_REG2__RID_BASE__SHIFT                                           0x8
+#define BIF_CFG_DEV0_RC_IDE_7_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT                                       0x18
+#define BIF_CFG_DEV0_RC_IDE_7_RID_ASSOCIATION_REG2__VALID_MASK                                                0x00000001L
+#define BIF_CFG_DEV0_RC_IDE_7_RID_ASSOCIATION_REG2__RID_BASE_MASK                                             0x00FFFF00L
+#define BIF_CFG_DEV0_RC_IDE_7_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK                                         0xFF000000L
+//BIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_0_REG1
+#define BIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT                                           0x0
+#define BIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT                                  0x8
+#define BIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT                                 0x14
+#define BIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_0_REG1__VALID_MASK                                             0x00000001L
+#define BIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK                                    0x000FFF00L
+#define BIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK                                   0xFFF00000L
+//BIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_0_REG2
+#define BIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT                                 0x0
+#define BIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK                                   0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_0_REG3
+#define BIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT                                  0x0
+#define BIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK                                    0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_1_REG1
+#define BIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT                                           0x0
+#define BIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT                                  0x8
+#define BIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT                                 0x14
+#define BIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_1_REG1__VALID_MASK                                             0x00000001L
+#define BIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK                                    0x000FFF00L
+#define BIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK                                   0xFFF00000L
+//BIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_1_REG2
+#define BIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT                                 0x0
+#define BIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK                                   0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_1_REG3
+#define BIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT                                  0x0
+#define BIF_CFG_DEV0_RC_IDE_7_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK                                    0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CAP
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS__SHIFT                      0x0
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CAP__NUM_ADDR_ASSOCIATION_REG_BLKS_MASK                        0x0000000FL
+//BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CNTL
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CNTL__SELECTIVE_IDE_STREAM_ENABLE__SHIFT                       0x0
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CNTL__XT_ENABLE__SHIFT                                         0x1
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CNTL__TX_AGGREGATION_MODE_NPR__SHIFT                           0x2
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CNTL__TX_AGGREGATION_MODE_PR__SHIFT                            0x4
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CNTL__TX_AGGREGATION_MODE_CPL__SHIFT                           0x6
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CNTL__PCRC_ENABLE__SHIFT                                       0x8
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN__SHIFT                      0x9
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CNTL__PARTIAL_HDR_ENCRYPT_MODE__SHIFT                          0xa
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CNTL__SELECTED_ALGORITHM__SHIFT                                0xe
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CNTL__TC__SHIFT                                                0x13
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CNTL__DEFAULT_STREAM__SHIFT                                    0x16
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CNTL__TEE_LIMITED_STREAM__SHIFT                                0x17
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CNTL__STREAM_ID__SHIFT                                         0x18
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CNTL__SELECTIVE_IDE_STREAM_ENABLE_MASK                         0x00000001L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CNTL__XT_ENABLE_MASK                                           0x00000002L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CNTL__TX_AGGREGATION_MODE_NPR_MASK                             0x0000000CL
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CNTL__TX_AGGREGATION_MODE_PR_MASK                              0x00000030L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CNTL__TX_AGGREGATION_MODE_CPL_MASK                             0x000000C0L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CNTL__PCRC_ENABLE_MASK                                         0x00000100L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CNTL__SELECTIVE_IDE_FOR_CFG_REQ_EN_MASK                        0x00000200L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CNTL__PARTIAL_HDR_ENCRYPT_MODE_MASK                            0x00003C00L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CNTL__SELECTED_ALGORITHM_MASK                                  0x0007C000L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CNTL__TC_MASK                                                  0x00380000L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CNTL__DEFAULT_STREAM_MASK                                      0x00400000L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CNTL__TEE_LIMITED_STREAM_MASK                                  0x00800000L
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_CNTL__STREAM_ID_MASK                                           0xFF000000L
+//BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_STATUS
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_STATUS__SELECTIVE_IDE_STREAM_STATE__SHIFT                      0x0
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_STATUS__RECEIVED_IDE_FAIL_MSG__SHIFT                           0x1f
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_STATUS__SELECTIVE_IDE_STREAM_STATE_MASK                        0x0000000FL
+#define BIF_CFG_DEV0_RC_SELECTIVE_IDE_STREAM_8_STATUS__RECEIVED_IDE_FAIL_MSG_MASK                             0x80000000L
+//BIF_CFG_DEV0_RC_IDE_8_RID_ASSOCIATION_REG1
+#define BIF_CFG_DEV0_RC_IDE_8_RID_ASSOCIATION_REG1__RID_LIMIT__SHIFT                                          0x8
+#define BIF_CFG_DEV0_RC_IDE_8_RID_ASSOCIATION_REG1__RID_LIMIT_MASK                                            0x00FFFF00L
+//BIF_CFG_DEV0_RC_IDE_8_RID_ASSOCIATION_REG2
+#define BIF_CFG_DEV0_RC_IDE_8_RID_ASSOCIATION_REG2__VALID__SHIFT                                              0x0
+#define BIF_CFG_DEV0_RC_IDE_8_RID_ASSOCIATION_REG2__RID_BASE__SHIFT                                           0x8
+#define BIF_CFG_DEV0_RC_IDE_8_RID_ASSOCIATION_REG2__SEGMENT_BASE__SHIFT                                       0x18
+#define BIF_CFG_DEV0_RC_IDE_8_RID_ASSOCIATION_REG2__VALID_MASK                                                0x00000001L
+#define BIF_CFG_DEV0_RC_IDE_8_RID_ASSOCIATION_REG2__RID_BASE_MASK                                             0x00FFFF00L
+#define BIF_CFG_DEV0_RC_IDE_8_RID_ASSOCIATION_REG2__SEGMENT_BASE_MASK                                         0xFF000000L
+//BIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_0_REG1
+#define BIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_0_REG1__VALID__SHIFT                                           0x0
+#define BIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER__SHIFT                                  0x8
+#define BIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER__SHIFT                                 0x14
+#define BIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_0_REG1__VALID_MASK                                             0x00000001L
+#define BIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_0_REG1__MEM_BASE_LOWER_MASK                                    0x000FFF00L
+#define BIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_0_REG1__MEM_LIMIT_LOWER_MASK                                   0xFFF00000L
+//BIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_0_REG2
+#define BIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER__SHIFT                                 0x0
+#define BIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_0_REG2__MEM_LIMIT_UPPER_MASK                                   0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_0_REG3
+#define BIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER__SHIFT                                  0x0
+#define BIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_0_REG3__MEM_BASE_UPPER_MASK                                    0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_1_REG1
+#define BIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_1_REG1__VALID__SHIFT                                           0x0
+#define BIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER__SHIFT                                  0x8
+#define BIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER__SHIFT                                 0x14
+#define BIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_1_REG1__VALID_MASK                                             0x00000001L
+#define BIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_1_REG1__MEM_BASE_LOWER_MASK                                    0x000FFF00L
+#define BIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_1_REG1__MEM_LIMIT_LOWER_MASK                                   0xFFF00000L
+//BIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_1_REG2
+#define BIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER__SHIFT                                 0x0
+#define BIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_1_REG2__MEM_LIMIT_UPPER_MASK                                   0xFFFFFFFFL
+//BIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_1_REG3
+#define BIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER__SHIFT                                  0x0
+#define BIF_CFG_DEV0_RC_IDE_8_ADDR_ASSOCIATION_1_REG3__MEM_BASE_UPPER_MASK                                    0xFFFFFFFFL
+
+
+#endif
diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index 736304e73ca4..024bfdb7c157 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
@@ -2505,12 +2505,12 @@ static ssize_t amdgpu_set_pm_policy_attr(struct device *dev,
 		.dev_attr = __ATTR(_name, 0644, amdgpu_get_pm_policy_attr, \
 				   amdgpu_set_pm_policy_attr),             \
 		.id = PP_PM_POLICY_##_id,                                  \
-	};
+	}
 
 #define AMDGPU_PM_POLICY_ATTR_VAR(_name) pm_policy_attr_##_name.dev_attr.attr
 
-AMDGPU_PM_POLICY_ATTR(soc_pstate, SOC_PSTATE)
-AMDGPU_PM_POLICY_ATTR(xgmi_plpd, XGMI_PLPD)
+AMDGPU_PM_POLICY_ATTR(soc_pstate, SOC_PSTATE);
+AMDGPU_PM_POLICY_ATTR(xgmi_plpd, XGMI_PLPD);
 
 static struct attribute *pm_policy_attrs[] = {
 	&AMDGPU_PM_POLICY_ATTR_VAR(soc_pstate),
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
index 7f386ff0c872..9d8b1227388f 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/aldebaran_ppt.c
@@ -425,6 +425,7 @@ static int aldebaran_set_default_dpm_table(struct smu_context *smu)
 		dpm_table->dpm_levels[0].enabled = true;
 		dpm_table->dpm_levels[1].value = pptable->GfxclkFmax;
 		dpm_table->dpm_levels[1].enabled = true;
+		dpm_table->flags |= SMU_DPM_TABLE_FINE_GRAINED;
 	} else {
 		dpm_table->count = 1;
 		dpm_table->dpm_levels[0].value = smu->smu_table.boot_values.gfxclk / 100;
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
index cd0a23f432ff..36716541e505 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_6_ppt.c
@@ -783,6 +783,10 @@ int smu_v13_0_6_get_metrics_table(struct smu_context *smu, void *metrics_table,
 		if (ret)
 			return ret;
 
+		if (!memchr_inv(smu_table->metrics_table, 0xff,
+				min(16, table_size)))
+			return -EHWPOISON;
+
 		smu_table->metrics_time = jiffies;
 	}
 
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c
index db85186f2d66..977590377021 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.c
@@ -63,6 +63,8 @@
 	for ((stack_idx) = 0; (umc_mask); \
 	     (umc_mask) >>= 4, (stack_idx)++) \
 
+#define NUM_JPEG_RINGS_FW	10
+
 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c))
 
 #define SMU_15_0_8_FEA_MAP(smu_feature, smu_15_0_8_feature)                    \
@@ -171,6 +173,13 @@ static const struct cmn2asic_mapping smu_v15_0_8_table_map[SMU_TABLE_COUNT] = {
 	TAB_MAP(I2C_COMMANDS),
 };
 
+static const uint8_t smu_v15_0_8_throttler_map[] = {
+	[THROTTLER_PROCHOT_BIT] = (SMU_THROTTLER_PROCHOT_GFX_BIT),
+	[THROTTLER_THERMAL_SOCKET_BIT] = (SMU_THROTTLER_TEMP_GPU_BIT),
+	[THROTTLER_THERMAL_VR_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT),
+	[THROTTLER_THERMAL_HBM_BIT] = (SMU_THROTTLER_TEMP_MEM_BIT),
+};
+
 static size_t smu_v15_0_8_get_system_metrics_size(void)
 {
 	return sizeof(SystemMetricsTable_t);
@@ -1062,38 +1071,30 @@ static int smu_v15_0_8_set_driver_pptable(struct smu_context *smu)
 		smu_table->tables[SMU_TABLE_SMU_METRICS].version =
 			table_version;
 
-		pptable->MaxSocketPowerLimit =
-			SMUQ10_ROUND(static_metrics->MaxSocketPowerLimit);
-		pptable->MaxGfxclkFrequency =
-			SMUQ10_ROUND(static_metrics->MaxGfxclkFrequency);
-		pptable->MinGfxclkFrequency =
-			SMUQ10_ROUND(static_metrics->MinGfxclkFrequency);
-		pptable->MaxFclkFrequency =
-			SMUQ10_ROUND(static_metrics->MaxFclkFrequency);
-		pptable->MinFclkFrequency =
-			SMUQ10_ROUND(static_metrics->MinFclkFrequency);
-		pptable->MaxGl2clkFrequency =
-			SMUQ10_ROUND(static_metrics->MaxGl2clkFrequency);
-		pptable->MinGl2clkFrequency =
-			SMUQ10_ROUND(static_metrics->MinGl2clkFrequency);
+		pptable->MaxSocketPowerLimit = static_metrics->MaxSocketPowerLimit;
+		pptable->MaxGfxclkFrequency = static_metrics->MaxGfxclkFrequency;
+		pptable->MinGfxclkFrequency = static_metrics->MinGfxclkFrequency;
+		pptable->MaxFclkFrequency = static_metrics->MaxFclkFrequency;
+		pptable->MinFclkFrequency = static_metrics->MinFclkFrequency;
+		pptable->MaxGl2clkFrequency = static_metrics->MaxGl2clkFrequency;
+		pptable->MinGl2clkFrequency = static_metrics->MinGl2clkFrequency;
 
 		for (i = 0; i < ARRAY_SIZE(static_metrics->UclkFrequencyTable); ++i)
-			pptable->UclkFrequencyTable[i] =
-				SMUQ10_ROUND(static_metrics->UclkFrequencyTable[i]);
-
-		pptable->SocclkFrequency = SMUQ10_ROUND(static_metrics->SocclkFrequency);
-		pptable->LclkFrequency = SMUQ10_ROUND(static_metrics->LclkFrequency);
-		pptable->VclkFrequency = SMUQ10_ROUND(static_metrics->VclkFrequency);
-		pptable->DclkFrequency = SMUQ10_ROUND(static_metrics->DclkFrequency);
-
-		pptable->CTFLimitMID = SMUQ10_ROUND(static_metrics->CTFLimit_MID);
-		pptable->CTFLimitAID = SMUQ10_ROUND(static_metrics->CTFLimit_AID);
-		pptable->CTFLimitXCD = SMUQ10_ROUND(static_metrics->CTFLimit_XCD);
-		pptable->CTFLimitHBM = SMUQ10_ROUND(static_metrics->CTFLimit_HBM);
-		pptable->ThermalLimitMID = SMUQ10_ROUND(static_metrics->ThermalLimit_MID);
-		pptable->ThermalLimitAID = SMUQ10_ROUND(static_metrics->ThermalLimit_AID);
-		pptable->ThermalLimitXCD = SMUQ10_ROUND(static_metrics->ThermalLimit_XCD);
-		pptable->ThermalLimitHBM = SMUQ10_ROUND(static_metrics->ThermalLimit_HBM);
+			pptable->UclkFrequencyTable[i] = static_metrics->UclkFrequencyTable[i];
+
+		pptable->SocclkFrequency = static_metrics->SocclkFrequency;
+		pptable->LclkFrequency = static_metrics->LclkFrequency;
+		pptable->VclkFrequency = static_metrics->VclkFrequency;
+		pptable->DclkFrequency = static_metrics->DclkFrequency;
+
+		pptable->CTFLimitMID = static_metrics->CTFLimit_MID;
+		pptable->CTFLimitAID = static_metrics->CTFLimit_AID;
+		pptable->CTFLimitXCD = static_metrics->CTFLimit_XCD;
+		pptable->CTFLimitHBM = static_metrics->CTFLimit_HBM;
+		pptable->ThermalLimitMID = static_metrics->ThermalLimit_MID;
+		pptable->ThermalLimitAID = static_metrics->ThermalLimit_AID;
+		pptable->ThermalLimitXCD = static_metrics->ThermalLimit_XCD;
+		pptable->ThermalLimitHBM = static_metrics->ThermalLimit_HBM;
 
 		/* use MID0 serial number by default */
 		pptable->PublicSerialNumberMID =
@@ -1601,6 +1602,81 @@ static ssize_t smu_v15_0_8_get_temp_metrics(struct smu_context *smu,
 	}
 }
 
+static ssize_t smu_v15_0_8_get_xcp_metrics(struct smu_context *smu, int xcp_id,
+					   void *table)
+{
+	struct smu_table_context *smu_table = &smu->smu_table;
+	const u8 num_jpeg_rings = NUM_JPEG_RINGS_FW;
+	struct smu_v15_0_8_partition_metrics *xcp_metrics;
+	MetricsTable_t *metrics;
+	struct amdgpu_device *adev = smu->adev;
+	int ret, inst, i, j, k, idx;
+	struct amdgpu_xcp *xcp;
+	u32 inst_mask;
+
+	if (!table)
+		return sizeof(*xcp_metrics);
+
+	for_each_xcp(adev->xcp_mgr, xcp, i) {
+		if (xcp->id == xcp_id)
+			break;
+	}
+	if (i == adev->xcp_mgr->num_xcps)
+		return -EINVAL;
+
+	xcp_metrics = (struct smu_v15_0_8_partition_metrics *)table;
+	smu_v15_0_8_partition_metrics_init(xcp_metrics, 1, 1);
+
+	ret = smu_v15_0_8_get_metrics_table_internal(smu, 1, NULL);
+	if (ret)
+		return ret;
+
+	metrics = (MetricsTable_t *)smu_table->metrics_table;
+
+	amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_VCN, &inst_mask);
+	idx = 0;
+	for_each_inst(k, inst_mask) {
+		/* Both JPEG and VCN has same instances */
+		inst = GET_INST(VCN, k);
+		for (j = 0; j < num_jpeg_rings; ++j) {
+			xcp_metrics->jpeg_busy[(idx * num_jpeg_rings) + j] =
+				SMUQ10_ROUND(metrics->JpegBusy[(inst * num_jpeg_rings) + j]);
+		}
+		xcp_metrics->vcn_busy[idx] =
+			SMUQ10_ROUND(metrics->VcnBusy[inst]);
+
+		xcp_metrics->current_vclk[idx] = SMUQ10_ROUND(metrics->VclkFrequency[inst]);
+		xcp_metrics->current_dclk[idx] = SMUQ10_ROUND(metrics->DclkFrequency[inst]);
+
+		idx++;
+	}
+
+	amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_GFX, &inst_mask);
+	idx = 0;
+	for_each_inst(k, inst_mask) {
+		inst = GET_INST(GC, k);
+		xcp_metrics->current_gfxclk[idx] =
+			SMUQ10_ROUND(metrics->GfxclkFrequency[inst]);
+
+		xcp_metrics->gfx_busy_inst[idx] = SMUQ10_ROUND(metrics->GfxBusy[inst]);
+		xcp_metrics->gfx_busy_acc[idx] = SMUQ10_ROUND(metrics->GfxBusyAcc[inst]);
+		xcp_metrics->gfx_below_host_limit_ppt_acc[idx] =
+			SMUQ10_ROUND(metrics->GfxclkBelowHostLimitPptAcc[inst]);
+		xcp_metrics->gfx_below_host_limit_thm_acc[idx] =
+			SMUQ10_ROUND(metrics->GfxclkBelowHostLimitThmAcc[inst]);
+		xcp_metrics->gfx_low_utilization_acc[idx] =
+			SMUQ10_ROUND(metrics->GfxclkLowUtilizationAcc[inst]);
+		xcp_metrics->gfx_below_host_limit_total_acc[idx] =
+			SMUQ10_ROUND(metrics->GfxclkBelowHostLimitTotalAcc[inst]);
+		idx++;
+	}
+
+	xcp_metrics->accumulation_counter = metrics->AccumulationCounter;
+	xcp_metrics->firmware_timestamp = metrics->Timestamp;
+
+	return sizeof(*xcp_metrics);
+}
+
 static ssize_t smu_v15_0_8_get_gpu_metrics(struct smu_context *smu, void **table)
 {
 	struct smu_table_context *smu_table = &smu->smu_table;
@@ -1627,17 +1703,23 @@ static ssize_t smu_v15_0_8_get_gpu_metrics(struct smu_context *smu, void **table
 	if (adev->umc.active_mask) {
 		u64 mask = adev->umc.active_mask;
 		int out_idx = 0;
+		u16 max_hbm_temp = 0;
 		int stack_idx;
 
-		if (unlikely(hweight64(mask)/4 > SMU_15_0_8_MAX_HBM_STACKS))
+		if (unlikely(hweight64(mask) / 4 > SMU_15_0_8_MAX_HBM_STACKS)) {
 			dev_warn(adev->dev, "Invalid umc mask %lld\n", mask);
-		else  {
+		} else  {
 			for_each_hbm_stack(stack_idx, mask) {
+				u16 temp;
+
 				if (!hbm_stack_mask_valid(mask))
 					continue;
-				gpu_metrics->temperature_hbm[out_idx++] =
-					SMUQ10_ROUND(metrics->HbmTemperature[stack_idx]);
+				temp = SMUQ10_ROUND(metrics->HbmTemperature[stack_idx]);
+				gpu_metrics->temperature_hbm[out_idx++] = temp;
+				if (temp > max_hbm_temp)
+					max_hbm_temp = temp;
 			}
+			gpu_metrics->temperature_mem = max_hbm_temp;
 		}
 	}
 
@@ -2199,6 +2281,71 @@ static int smu_v15_0_8_get_ppt_limit(struct smu_context *smu,
 	return -EOPNOTSUPP;
 }
 
+static uint32_t smu_v15_0_8_get_throttler_status(struct smu_context *smu)
+{
+	struct smu_power_context *smu_power = &smu->smu_power;
+	struct smu_15_0_power_context *power_context = smu_power->power_context;
+	uint32_t throttler_status = 0;
+
+	throttler_status = atomic_read(&power_context->throttle_status);
+	dev_dbg(smu->adev->dev, "SMU Throttler status: %u", throttler_status);
+
+	return throttler_status;
+}
+
+static const char *const throttling_logging_label[] = {
+	[THROTTLER_PROCHOT_BIT] = "Prochot",
+	[THROTTLER_THERMAL_SOCKET_BIT] = "SOC",
+	[THROTTLER_THERMAL_VR_BIT] = "VR",
+	[THROTTLER_THERMAL_HBM_BIT] = "HBM"
+};
+
+static void smu_v15_0_8_log_thermal_throttling_event(struct smu_context *smu)
+{
+	int throttler_idx, throttling_events = 0, buf_idx = 0;
+	struct amdgpu_device *adev = smu->adev;
+	uint32_t throttler_status;
+	char log_buf[256];
+
+	throttler_status = smu_v15_0_8_get_throttler_status(smu);
+	if (!throttler_status)
+		return;
+
+	memset(log_buf, 0, sizeof(log_buf));
+	for (throttler_idx = 0;
+	     throttler_idx < ARRAY_SIZE(throttling_logging_label);
+	     throttler_idx++) {
+		if (throttler_status & (1U << throttler_idx)) {
+			throttling_events++;
+			buf_idx += snprintf(
+				log_buf + buf_idx, sizeof(log_buf) - buf_idx,
+				"%s%s", throttling_events > 1 ? " and " : "",
+				throttling_logging_label[throttler_idx]);
+			if (buf_idx >= sizeof(log_buf)) {
+				dev_err(adev->dev, "buffer overflow!\n");
+				log_buf[sizeof(log_buf) - 1] = '\0';
+				break;
+			}
+		}
+	}
+
+	dev_warn(adev->dev,
+		 "WARN: GPU is throttled, expect performance decrease. %s.\n",
+		 log_buf);
+	kgd2kfd_smi_event_throttle(
+		smu->adev->kfd.dev,
+		smu_cmn_get_indep_throttler_status(throttler_status,
+						   smu_v15_0_8_throttler_map));
+}
+
+static int smu_v15_0_8_enable_thermal_alert(struct smu_context *smu)
+{
+	if (!smu->irq_source.num_types)
+		return 0;
+
+	return amdgpu_irq_get(smu->adev, &smu->irq_source, 0);
+}
+
 static const struct pptable_funcs smu_v15_0_8_ppt_funcs = {
 	.init_allowed_features = smu_v15_0_8_init_allowed_features,
 	.set_default_dpm_table = smu_v15_0_8_set_default_dpm_table,
@@ -2216,10 +2363,14 @@ static const struct pptable_funcs smu_v15_0_8_ppt_funcs = {
 	.get_enabled_mask = smu_v15_0_8_get_enabled_mask,
 	.feature_is_enabled = smu_cmn_feature_is_enabled,
 	.register_irq_handler = smu_v15_0_8_register_irq_handler,
+	.enable_thermal_alert = smu_v15_0_8_enable_thermal_alert,
+	.disable_thermal_alert = smu_v15_0_disable_thermal_alert,
+	.log_thermal_throttling_event = smu_v15_0_8_log_thermal_throttling_event,
 	.setup_pptable = smu_v15_0_8_setup_pptable,
 	.get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
 	.wait_for_event = smu_v15_0_wait_for_event,
 	.get_pm_metrics = smu_v15_0_8_get_pm_metrics,
+	.get_xcp_metrics = smu_v15_0_8_get_xcp_metrics,
 	.mode2_reset = smu_v15_0_8_mode2_reset,
 	.get_dpm_ultimate_freq = smu_v15_0_8_get_dpm_ultimate_freq,
 	.get_gpu_metrics = smu_v15_0_8_get_gpu_metrics,
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.h b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.h
index 398ce4482174..4dfc40aaffcb 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu15/smu_v15_0_8_ppt.h
@@ -309,5 +309,39 @@ DECLARE_SMU_METRICS_CLASS(smu_v15_0_8_gpuboard_temp_metrics,
 
 DECLARE_SMU_METRICS_CLASS(smu_v15_0_8_baseboard_temp_metrics,
 			  SMU_15_0_8_BASEBOARD_TEMP_METRICS_FIELDS);
+#define SMU_15_0_8_PARTITION_METRICS_FIELDS(SMU_SCALAR, SMU_ARRAY)             \
+	SMU_ARRAY(SMU_MATTR(CURRENT_GFXCLK), SMU_MUNIT(CLOCK_1),               \
+		  SMU_MTYPE(U16), current_gfxclk, SMU_15_0_8_MAX_XCC);         \
+	SMU_ARRAY(SMU_MATTR(CURRENT_VCLK0), SMU_MUNIT(CLOCK_1),                \
+		  SMU_MTYPE(U16), current_vclk, SMU_15_0_8_MAX_VCN);          \
+	SMU_ARRAY(SMU_MATTR(CURRENT_DCLK0), SMU_MUNIT(CLOCK_1),                \
+		  SMU_MTYPE(U16), current_dclk, SMU_15_0_8_MAX_VCN);          \
+	SMU_ARRAY(SMU_MATTR(GFX_BUSY_INST), SMU_MUNIT(PERCENT),                \
+		  SMU_MTYPE(U8), gfx_busy_inst, SMU_15_0_8_MAX_XCC);          \
+	SMU_ARRAY(SMU_MATTR(JPEG_BUSY), SMU_MUNIT(PERCENT), SMU_MTYPE(U8),    \
+		  jpeg_busy, SMU_15_0_8_MAX_JPEG);                             \
+	SMU_ARRAY(SMU_MATTR(VCN_BUSY), SMU_MUNIT(PERCENT), SMU_MTYPE(U8),     \
+		  vcn_busy, SMU_15_0_8_MAX_VCN);                               \
+	SMU_ARRAY(SMU_MATTR(GFX_BUSY_ACC), SMU_MUNIT(NONE), SMU_MTYPE(U64),    \
+		  gfx_busy_acc, SMU_15_0_8_MAX_XCC);                           \
+	SMU_ARRAY(SMU_MATTR(GFX_BELOW_HOST_LIMIT_PPT_ACC), SMU_MUNIT(NONE),    \
+		  SMU_MTYPE(U64), gfx_below_host_limit_ppt_acc,                \
+		  SMU_15_0_8_MAX_XCC);                                         \
+	SMU_ARRAY(SMU_MATTR(GFX_BELOW_HOST_LIMIT_THM_ACC), SMU_MUNIT(NONE),    \
+		  SMU_MTYPE(U64), gfx_below_host_limit_thm_acc,                \
+		  SMU_15_0_8_MAX_XCC);                                         \
+	SMU_ARRAY(SMU_MATTR(GFX_LOW_UTILIZATION_ACC), SMU_MUNIT(NONE),         \
+		  SMU_MTYPE(U64), gfx_low_utilization_acc,                     \
+		  SMU_15_0_8_MAX_XCC);                                         \
+	SMU_ARRAY(SMU_MATTR(GFX_BELOW_HOST_LIMIT_TOTAL_ACC), SMU_MUNIT(NONE),  \
+		  SMU_MTYPE(U64), gfx_below_host_limit_total_acc,              \
+		  SMU_15_0_8_MAX_XCC);					       \
+	SMU_SCALAR(SMU_MATTR(ACCUMULATION_COUNTER), SMU_MUNIT(NONE),           \
+		   SMU_MTYPE(U64), accumulation_counter);                      \
+	SMU_SCALAR(SMU_MATTR(FIRMWARE_TIMESTAMP), SMU_MUNIT(TIME_2),           \
+		   SMU_MTYPE(U64), firmware_timestamp);
+
+DECLARE_SMU_METRICS_CLASS(smu_v15_0_8_partition_metrics,
+			  SMU_15_0_8_PARTITION_METRICS_FIELDS);
 #endif
 #endif
diff --git a/drivers/gpu/drm/drm_gpusvm.c b/drivers/gpu/drm/drm_gpusvm.c
index 4b928fda5b12..7993e85c0566 100644
--- a/drivers/gpu/drm/drm_gpusvm.c
+++ b/drivers/gpu/drm/drm_gpusvm.c
@@ -1065,6 +1065,11 @@ drm_gpusvm_range_find_or_insert(struct drm_gpusvm *gpusvm,
 		goto err_notifier_remove;
 	}
 
+	if (vas->vm_flags & (VM_IO | VM_PFNMAP)) {
+		err = -EIO;
+		goto err_notifier_remove;
+	}
+
 	range = drm_gpusvm_range_find(notifier, fault_addr, fault_addr + 1);
 	if (range)
 		goto out_mmunlock;
diff --git a/drivers/gpu/drm/drm_ras.c b/drivers/gpu/drm/drm_ras.c
index b2fa5ab86d87..d6eab29a1394 100644
--- a/drivers/gpu/drm/drm_ras.c
+++ b/drivers/gpu/drm/drm_ras.c
@@ -26,7 +26,7 @@
  * efficient lookup by ID. Nodes can be registered or unregistered
  * dynamically at runtime.
  *
- * A Generic Netlink family `drm_ras` exposes two main operations to
+ * A Generic Netlink family `drm_ras` exposes the below operations to
  * userspace:
  *
  * 1. LIST_NODES: Dump all currently registered RAS nodes.
@@ -37,6 +37,10 @@
  *    Returns all counters of a node if only Node ID is provided or specific
  *    error counters.
  *
+ * 3. CLEAR_ERROR_COUNTER: Clear error counter of a given node.
+ *    Userspace must provide Node ID, Error ID.
+ *    Clears specific error counter of a node if supported.
+ *
  * Node registration:
  *
  * - drm_ras_node_register(): Registers a new node and assigns
@@ -66,6 +70,8 @@
  *   operation, fetching all counters from a specific node.
  * - drm_ras_nl_get_error_counter_doit(): Implements the GET_ERROR_COUNTER doit
  *   operation, fetching a counter value from a specific node.
+ * - drm_ras_nl_clear_error_counter_doit(): Implements the CLEAR_ERROR_COUNTER doit
+ *   operation, clearing a counter value from a specific node.
  */
 
 static DEFINE_XARRAY_ALLOC(drm_ras_xa);
@@ -314,6 +320,41 @@ int drm_ras_nl_get_error_counter_doit(struct sk_buff *skb,
 	return doit_reply_value(info, node_id, error_id);
 }
 
+/**
+ * drm_ras_nl_clear_error_counter_doit() - Clear an error counter of a node
+ * @skb: Netlink message buffer
+ * @info: Generic Netlink info containing attributes of the request
+ *
+ * Extracts the node ID and error ID from the netlink attributes and
+ * clears the current value.
+ *
+ * Return: 0 on success, or negative errno on failure.
+ */
+int drm_ras_nl_clear_error_counter_doit(struct sk_buff *skb,
+					struct genl_info *info)
+{
+	struct drm_ras_node *node;
+	u32 node_id, error_id;
+
+	if (!info->attrs ||
+	    GENL_REQ_ATTR_CHECK(info, DRM_RAS_A_ERROR_COUNTER_ATTRS_NODE_ID) ||
+	    GENL_REQ_ATTR_CHECK(info, DRM_RAS_A_ERROR_COUNTER_ATTRS_ERROR_ID))
+		return -EINVAL;
+
+	node_id = nla_get_u32(info->attrs[DRM_RAS_A_ERROR_COUNTER_ATTRS_NODE_ID]);
+	error_id = nla_get_u32(info->attrs[DRM_RAS_A_ERROR_COUNTER_ATTRS_ERROR_ID]);
+
+	node = xa_load(&drm_ras_xa, node_id);
+	if (!node || !node->clear_error_counter)
+		return -ENOENT;
+
+	if (error_id < node->error_counter_range.first ||
+	    error_id > node->error_counter_range.last)
+		return -EINVAL;
+
+	return node->clear_error_counter(node, error_id);
+}
+
 /**
  * drm_ras_node_register() - Register a new RAS node
  * @node: Node structure to register
diff --git a/drivers/gpu/drm/drm_ras_nl.c b/drivers/gpu/drm/drm_ras_nl.c
index 16803d0c4a44..dea1c1b2494e 100644
--- a/drivers/gpu/drm/drm_ras_nl.c
+++ b/drivers/gpu/drm/drm_ras_nl.c
@@ -22,6 +22,12 @@ static const struct nla_policy drm_ras_get_error_counter_dump_nl_policy[DRM_RAS_
 	[DRM_RAS_A_ERROR_COUNTER_ATTRS_NODE_ID] = { .type = NLA_U32, },
 };
 
+/* DRM_RAS_CMD_CLEAR_ERROR_COUNTER - do */
+static const struct nla_policy drm_ras_clear_error_counter_nl_policy[DRM_RAS_A_ERROR_COUNTER_ATTRS_ERROR_ID + 1] = {
+	[DRM_RAS_A_ERROR_COUNTER_ATTRS_NODE_ID] = { .type = NLA_U32, },
+	[DRM_RAS_A_ERROR_COUNTER_ATTRS_ERROR_ID] = { .type = NLA_U32, },
+};
+
 /* Ops table for drm_ras */
 static const struct genl_split_ops drm_ras_nl_ops[] = {
 	{
@@ -43,6 +49,13 @@ static const struct genl_split_ops drm_ras_nl_ops[] = {
 		.maxattr	= DRM_RAS_A_ERROR_COUNTER_ATTRS_NODE_ID,
 		.flags		= GENL_ADMIN_PERM | GENL_CMD_CAP_DUMP,
 	},
+	{
+		.cmd		= DRM_RAS_CMD_CLEAR_ERROR_COUNTER,
+		.doit		= drm_ras_nl_clear_error_counter_doit,
+		.policy		= drm_ras_clear_error_counter_nl_policy,
+		.maxattr	= DRM_RAS_A_ERROR_COUNTER_ATTRS_ERROR_ID,
+		.flags		= GENL_ADMIN_PERM | GENL_CMD_CAP_DO,
+	},
 };
 
 struct genl_family drm_ras_nl_family __ro_after_init = {
diff --git a/drivers/gpu/drm/drm_ras_nl.h b/drivers/gpu/drm/drm_ras_nl.h
index 06ccd9342773..a398643572a5 100644
--- a/drivers/gpu/drm/drm_ras_nl.h
+++ b/drivers/gpu/drm/drm_ras_nl.h
@@ -18,6 +18,8 @@ int drm_ras_nl_get_error_counter_doit(struct sk_buff *skb,
 				      struct genl_info *info);
 int drm_ras_nl_get_error_counter_dumpit(struct sk_buff *skb,
 					struct netlink_callback *cb);
+int drm_ras_nl_clear_error_counter_doit(struct sk_buff *skb,
+					struct genl_info *info);
 
 extern struct genl_family drm_ras_nl_family;
 
diff --git a/drivers/gpu/drm/hyperv/Kconfig b/drivers/gpu/drm/hyperv/Kconfig
index 86234f6a73f2..e48e35fb7f8b 100644
--- a/drivers/gpu/drm/hyperv/Kconfig
+++ b/drivers/gpu/drm/hyperv/Kconfig
@@ -8,7 +8,6 @@ config DRM_HYPERV
 	help
 	 This is a KMS driver for Hyper-V synthetic video device. Choose this
 	 option if you would like to enable drm driver for Hyper-V virtual
-	 machine. Unselect Hyper-V framebuffer driver (CONFIG_FB_HYPERV) so
-	 that DRM driver is used by default.
+	 machine.
 
 	 If M is selected the module will be called hyperv_drm.
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index a47736613f6e..e3b044ee3e16 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -28,6 +28,7 @@
 #include <drm/drm_fixed.h>
 #include <drm/drm_print.h>
 #include <drm/intel/intel_pcode_regs.h>
+#include <drm/intel/step.h>
 
 #include "hsw_ips.h"
 #include "intel_atomic.h"
@@ -46,7 +47,6 @@
 #include "intel_pci_config.h"
 #include "intel_plane.h"
 #include "intel_psr.h"
-#include "intel_step.h"
 #include "intel_vdsc.h"
 #include "skl_watermark.h"
 #include "skl_watermark_regs.h"
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index ebefa889bc8c..178074316a2c 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -33,6 +33,7 @@
 #include <drm/display/drm_scdc_helper.h>
 #include <drm/drm_print.h>
 #include <drm/drm_privacy_screen_consumer.h>
+#include <drm/intel/step.h>
 
 #include "icl_dsi.h"
 #include "intel_alpm.h"
@@ -81,7 +82,6 @@
 #include "intel_psr.h"
 #include "intel_quirks.h"
 #include "intel_snps_phy.h"
-#include "intel_step.h"
 #include "intel_tc.h"
 #include "intel_vdsc.h"
 #include "intel_vdsc_regs.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display_device.c b/drivers/gpu/drm/i915/display/intel_display_device.c
index be55ef8ea617..7260990038dd 100644
--- a/drivers/gpu/drm/i915/display/intel_display_device.c
+++ b/drivers/gpu/drm/i915/display/intel_display_device.c
@@ -9,6 +9,7 @@
 #include <drm/drm_drv.h>
 #include <drm/drm_print.h>
 #include <drm/intel/pciids.h>
+#include <drm/intel/step.h>
 
 #include "intel_cx0_phy_regs.h"
 #include "intel_de.h"
@@ -21,7 +22,6 @@
 #include "intel_display_types.h"
 #include "intel_display_wa.h"
 #include "intel_fbc.h"
-#include "intel_step.h"
 
 __diag_push();
 __diag_ignore_all("-Woverride-init", "Allow field initialization overrides for display info");
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index ec96b141c74c..1a2de99ad78f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -8,6 +8,7 @@
 
 #include <drm/drm_print.h>
 #include <drm/intel/intel_pcode_regs.h>
+#include <drm/intel/step.h>
 
 #include "intel_backlight_regs.h"
 #include "intel_cdclk.h"
@@ -30,7 +31,6 @@
 #include "intel_pmdemand.h"
 #include "intel_pps_regs.h"
 #include "intel_snps_phy.h"
-#include "intel_step.h"
 #include "skl_watermark.h"
 #include "skl_watermark_regs.h"
 #include "vlv_sideband.h"
diff --git a/drivers/gpu/drm/i915/display/intel_display_wa.c b/drivers/gpu/drm/i915/display/intel_display_wa.c
index 081a4092cd13..7d3d63a59882 100644
--- a/drivers/gpu/drm/i915/display/intel_display_wa.c
+++ b/drivers/gpu/drm/i915/display/intel_display_wa.c
@@ -4,12 +4,12 @@
  */
 
 #include <drm/drm_print.h>
+#include <drm/intel/step.h>
 
 #include "intel_de.h"
 #include "intel_display_core.h"
 #include "intel_display_regs.h"
 #include "intel_display_wa.h"
-#include "intel_step.h"
 
 static void gen11_display_wa_apply(struct intel_display *display)
 {
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 887b6de14e46..96c5bcf7e21e 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -32,6 +32,7 @@
 #include <drm/drm_fixed.h>
 #include <drm/drm_print.h>
 #include <drm/drm_probe_helper.h>
+#include <drm/intel/step.h>
 
 #include "intel_atomic.h"
 #include "intel_audio.h"
@@ -56,7 +57,6 @@
 #include "intel_link_bw.h"
 #include "intel_pfit.h"
 #include "intel_psr.h"
-#include "intel_step.h"
 #include "intel_vdsc.h"
 #include "intel_vrr.h"
 #include "skl_scaler.h"
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index f5d4f7146fbc..e97b38f5d98e 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -25,6 +25,7 @@
 #include <linux/string_helpers.h>
 
 #include <drm/drm_print.h>
+#include <drm/intel/step.h>
 
 #include "bxt_dpio_phy_regs.h"
 #include "intel_cx0_phy.h"
@@ -41,7 +42,6 @@
 #include "intel_lt_phy.h"
 #include "intel_mg_phy_regs.h"
 #include "intel_pch_refclk.h"
-#include "intel_step.h"
 #include "intel_tc.h"
 
 /**
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index ea0ce00c8474..55cb3ceb3523 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -44,6 +44,7 @@
 #include <drm/drm_blend.h>
 #include <drm/drm_fourcc.h>
 #include <drm/drm_print.h>
+#include <drm/intel/step.h>
 
 #include "i9xx_plane_regs.h"
 #include "intel_de.h"
@@ -58,7 +59,6 @@
 #include "intel_fbc_regs.h"
 #include "intel_frontbuffer.h"
 #include "intel_parent.h"
-#include "intel_step.h"
 
 #define for_each_fbc_id(__display, __fbc_id) \
 	for ((__fbc_id) = INTEL_FBC_A; (__fbc_id) < I915_MAX_FBCS; (__fbc_id)++) \
diff --git a/drivers/gpu/drm/i915/display/intel_flipq.c b/drivers/gpu/drm/i915/display/intel_flipq.c
index 253dc2e96d2d..333d28faf4ca 100644
--- a/drivers/gpu/drm/i915/display/intel_flipq.c
+++ b/drivers/gpu/drm/i915/display/intel_flipq.c
@@ -6,6 +6,7 @@
 #include <linux/pci.h>
 
 #include <drm/drm_print.h>
+#include <drm/intel/step.h>
 
 #include "intel_crtc.h"
 #include "intel_de.h"
@@ -17,7 +18,6 @@
 #include "intel_dmc_regs.h"
 #include "intel_dsb.h"
 #include "intel_flipq.h"
-#include "intel_step.h"
 #include "intel_vblank.h"
 #include "intel_vrr.h"
 
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
index 892eab4b6f92..9b4ff3b80b05 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -18,6 +18,7 @@
 #include <drm/drm_print.h>
 #include <drm/intel/i915_component.h>
 #include <drm/intel/intel_pcode_regs.h>
+#include <drm/intel/step.h>
 
 #include "intel_connector.h"
 #include "intel_de.h"
@@ -33,7 +34,6 @@
 #include "intel_hdcp_regs.h"
 #include "intel_hdcp_shim.h"
 #include "intel_parent.h"
-#include "intel_step.h"
 
 #define USE_HDCP_GSC(__display)		(DISPLAY_VER(__display) >= 14)
 
diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.c b/drivers/gpu/drm/i915/display/intel_pmdemand.c
index 244806a26da3..7819b724795b 100644
--- a/drivers/gpu/drm/i915/display/intel_pmdemand.c
+++ b/drivers/gpu/drm/i915/display/intel_pmdemand.c
@@ -6,6 +6,7 @@
 #include <linux/bitops.h>
 
 #include <drm/drm_print.h>
+#include <drm/intel/step.h>
 
 #include "intel_atomic.h"
 #include "intel_bw.h"
@@ -17,7 +18,6 @@
 #include "intel_display_utils.h"
 #include "intel_display_wa.h"
 #include "intel_pmdemand.h"
-#include "intel_step.h"
 #include "skl_watermark.h"
 
 struct pmdemand_params {
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 53c10ae76ab5..6978c81ed48b 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -28,6 +28,7 @@
 #include <drm/drm_debugfs.h>
 #include <drm/drm_print.h>
 #include <drm/drm_vblank.h>
+#include <drm/intel/step.h>
 
 #include "intel_alpm.h"
 #include "intel_atomic.h"
@@ -51,7 +52,6 @@
 #include "intel_psr_regs.h"
 #include "intel_quirks.h"
 #include "intel_snps_phy.h"
-#include "intel_step.h"
 #include "intel_vblank.h"
 #include "intel_vdsc.h"
 #include "intel_vrr.h"
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index 11ba42c67e3e..7a9d494334b5 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -8,6 +8,7 @@
 #include <drm/drm_damage_helper.h>
 #include <drm/drm_fourcc.h>
 #include <drm/drm_print.h>
+#include <drm/intel/step.h>
 
 #include "intel_bo.h"
 #include "intel_color.h"
@@ -25,7 +26,6 @@
 #include "intel_plane.h"
 #include "intel_psr.h"
 #include "intel_psr_regs.h"
-#include "intel_step.h"
 #include "skl_scaler.h"
 #include "skl_universal_plane.h"
 #include "skl_universal_plane_regs.h"
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index 51a3e0fc2f56..a13635443833 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -9063,7 +9063,7 @@ static u32 dce8_available_bandwidth(struct dce8_wm_params *wm)
 	u32 data_return_bandwidth = dce8_data_return_bandwidth(wm);
 	u32 dmif_req_bandwidth = dce8_dmif_request_bandwidth(wm);
 
-	return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
+	return min3(dram_bandwidth, data_return_bandwidth, dmif_req_bandwidth);
 }
 
 /**
diff --git a/drivers/gpu/drm/radeon/radeon_gem.c b/drivers/gpu/drm/radeon/radeon_gem.c
index 20fc87409f2e..8ce180e22d1d 100644
--- a/drivers/gpu/drm/radeon/radeon_gem.c
+++ b/drivers/gpu/drm/radeon/radeon_gem.c
@@ -28,6 +28,7 @@
 
 #include <linux/debugfs.h>
 #include <linux/iosys-map.h>
+#include <linux/overflow.h>
 #include <linux/pci.h>
 
 #include <drm/drm_device.h>
@@ -812,6 +813,7 @@ int radeon_align_pitch(struct radeon_device *rdev, int width, int cpp, bool tile
 	int aligned = width;
 	int align_large = (ASIC_IS_AVIVO(rdev)) || tiled;
 	int pitch_mask = 0;
+	int pitch;
 
 	switch (cpp) {
 	case 1:
@@ -826,9 +828,12 @@ int radeon_align_pitch(struct radeon_device *rdev, int width, int cpp, bool tile
 		break;
 	}
 
-	aligned += pitch_mask;
+	if (check_add_overflow(aligned, pitch_mask, &aligned))
+		return 0;
 	aligned &= ~pitch_mask;
-	return aligned * cpp;
+	if (check_mul_overflow(aligned, cpp, &pitch))
+		return 0;
+	return pitch;
 }
 
 int radeon_mode_dumb_create(struct drm_file *file_priv,
@@ -842,8 +847,12 @@ int radeon_mode_dumb_create(struct drm_file *file_priv,
 
 	args->pitch = radeon_align_pitch(rdev, args->width,
 					 DIV_ROUND_UP(args->bpp, 8), 0);
+	if (!args->pitch)
+		return -EINVAL;
 	args->size = (u64)args->pitch * args->height;
 	args->size = ALIGN(args->size, PAGE_SIZE);
+	if (!args->size)
+		return -EINVAL;
 
 	r = radeon_gem_object_create(rdev, args->size, 0,
 				     RADEON_GEM_DOMAIN_VRAM, 0,
diff --git a/drivers/gpu/drm/radeon/radeon_ring.c b/drivers/gpu/drm/radeon/radeon_ring.c
index 581ae20c46e4..a5dff072c1ac 100644
--- a/drivers/gpu/drm/radeon/radeon_ring.c
+++ b/drivers/gpu/drm/radeon/radeon_ring.c
@@ -356,8 +356,10 @@ int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring,
 
 	/* restore the saved ring content */
 	r = radeon_ring_lock(rdev, ring, size);
-	if (r)
+	if (r) {
+		kvfree(data);
 		return r;
+	}
 
 	for (i = 0; i < size; ++i) {
 		radeon_ring_write(ring, data[i]);
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index 26197aceb001..4681ff28630a 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -2150,7 +2150,7 @@ static u32 dce6_available_bandwidth(struct dce6_wm_params *wm)
 	u32 data_return_bandwidth = dce6_data_return_bandwidth(wm);
 	u32 dmif_req_bandwidth = dce6_dmif_request_bandwidth(wm);
 
-	return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
+	return min3(dram_bandwidth, data_return_bandwidth, dmif_req_bandwidth);
 }
 
 static u32 dce6_average_bandwidth(struct dce6_wm_params *wm)
diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index 49de1c22a469..8e31b14239ec 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -88,6 +88,7 @@ xe-y += xe_bb.o \
 	xe_irq.o \
 	xe_late_bind_fw.o \
 	xe_lrc.o \
+	xe_mem_pool.o \
 	xe_migrate.o \
 	xe_mmio.o \
 	xe_mmio_gem.o \
@@ -123,6 +124,8 @@ xe-y += xe_bb.o \
 	xe_step.o \
 	xe_survivability_mode.o \
 	xe_sync.o \
+	xe_sysctrl.o \
+	xe_sysctrl_mailbox.o \
 	xe_tile.o \
 	xe_tile_sysfs.o \
 	xe_tlb_inval.o \
diff --git a/drivers/gpu/drm/xe/abi/guc_klvs_abi.h b/drivers/gpu/drm/xe/abi/guc_klvs_abi.h
index e33bd622ab44..644f5a4226d7 100644
--- a/drivers/gpu/drm/xe/abi/guc_klvs_abi.h
+++ b/drivers/gpu/drm/xe/abi/guc_klvs_abi.h
@@ -192,6 +192,13 @@ enum  {
  * `GuC KLV`_ keys available for use with PF2GUC_UPDATE_VGT_POLICY.
  *
  * _`GUC_KLV_VGT_POLICY_SCHED_IF_IDLE` : 0x8001
+ *      [From 70.12.0]
+ *      This config allows to update scheduling priority of PF and all VFs at once.
+ *      Setting this policy to 0 updates all VFs scheduling priorities to LOW, and
+ *      setting this policy to 1 updates all VFs scheduling priorities to NORMAL.
+ *      Those changes will take effect on the next VF-Switch event.
+ *
+ *      [Before 70.12.0]
  *      This config sets whether strict scheduling is enabled whereby any VF
  *      that doesn’t have work to submit is still allocated a fixed execution
  *      time-slice to ensure active VFs execution is always consistent even
@@ -496,6 +503,7 @@ enum xe_guc_klv_ids {
 	GUC_WA_KLV_WAKE_POWER_DOMAINS_FOR_OUTBOUND_MMIO					= 0x900a,
 	GUC_WA_KLV_RESET_BB_STACK_PTR_ON_VF_SWITCH					= 0x900b,
 	GUC_WA_KLV_RESTORE_UNSAVED_MEDIA_CONTROL_REG					= 0x900c,
+	GUC_WA_KLV_CLR_CS_INDIRECT_RING_STATE_IF_IDLE_AT_CTX_REG			= 0x900e,
 };
 
 #endif
diff --git a/drivers/gpu/drm/xe/abi/xe_sysctrl_abi.h b/drivers/gpu/drm/xe/abi/xe_sysctrl_abi.h
new file mode 100644
index 000000000000..4cbde267ac44
--- /dev/null
+++ b/drivers/gpu/drm/xe/abi/xe_sysctrl_abi.h
@@ -0,0 +1,65 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#ifndef _XE_SYSCTRL_ABI_H_
+#define _XE_SYSCTRL_ABI_H_
+
+#include <linux/types.h>
+
+/**
+ * DOC: System Controller ABI
+ *
+ * This header defines the Application Binary Interface (ABI) used by
+ * drm/xe to communicate with System Controller firmware on Intel Xe3p
+ * discrete GPU platforms.
+ *
+ * System Controller (sysctrl) is a firmware-managed entity on Intel
+ * dGPUs responsible for certain low-level platform management
+ * functions.
+ *
+ * Communication protocol:
+ *
+ * Communication uses a mailbox interface with messages composed of:
+ *
+ * - Application message header (struct xe_sysctrl_app_msg_hdr)
+ *   containing group_id, command, and version
+ * - Variable-length, command-specific payload
+ *
+ * Message header format:
+ *
+ * The 32-bit application message header is packed as:
+ *
+ * - Bits [7:0]   : Group ID identifying command group
+ * - Bits [15:8]  : Command identifier within group
+ * - Bits [23:16] : Command version for interface compatibility
+ * - Bits [31:24] : Reserved, must be zero
+ *
+ * This header defines firmware ABI message formats and constants shared
+ * between driver and System Controller firmware.
+ */
+
+/**
+ * struct xe_sysctrl_app_msg_hdr - Application layer message header
+ * @data: 32-bit header data
+ *
+ * Header structure for application-level messages.
+ */
+struct xe_sysctrl_app_msg_hdr {
+	u32 data;
+} __packed;
+
+#define SYSCTRL_HDR_GROUP_ID_MASK	GENMASK(7, 0)
+#define SYSCTRL_HDR_COMMAND_MASK	GENMASK(14, 8)
+#define SYSCTRL_HDR_COMMAND_MAX		0x7f
+#define SYSCTRL_HDR_IS_RESPONSE		BIT(15)
+#define SYSCTRL_HDR_RESERVED_MASK	GENMASK(23, 16)
+#define SYSCTRL_HDR_RESULT_MASK		GENMASK(31, 24)
+
+#define APP_HDR_GROUP_ID_MASK		GENMASK(7, 0)
+#define APP_HDR_COMMAND_MASK		GENMASK(15, 8)
+#define APP_HDR_VERSION_MASK		GENMASK(23, 16)
+#define APP_HDR_RESERVED_MASK		GENMASK(31, 24)
+
+#endif
diff --git a/drivers/gpu/drm/xe/compat-i915-headers/intel_step.h b/drivers/gpu/drm/xe/compat-i915-headers/intel_step.h
deleted file mode 100644
index 0eabe2866f5f..000000000000
--- a/drivers/gpu/drm/xe/compat-i915-headers/intel_step.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/* SPDX-License-Identifier: MIT */
-/*
- * Copyright © 2023 Intel Corporation
- */
-
-#ifndef __INTEL_STEP_H__
-#define __INTEL_STEP_H__
-
-#include "xe_step_types.h"
-
-#define intel_step xe_step
-
-#endif /* __INTEL_STEP_H__ */
diff --git a/drivers/gpu/drm/xe/display/xe_fb_pin.c b/drivers/gpu/drm/xe/display/xe_fb_pin.c
index e45a1e7a4670..d670a3cf1b84 100644
--- a/drivers/gpu/drm/xe/display/xe_fb_pin.c
+++ b/drivers/gpu/drm/xe/display/xe_fb_pin.c
@@ -14,6 +14,7 @@
 #include "xe_device.h"
 #include "xe_display_vma.h"
 #include "xe_ggtt.h"
+#include "xe_pat.h"
 #include "xe_pm.h"
 #include "xe_vram_types.h"
 
@@ -24,7 +25,7 @@ write_dpt_rotated(struct xe_bo *bo, struct iosys_map *map, u32 *dpt_ofs, u32 bo_
 	struct xe_device *xe = xe_bo_device(bo);
 	struct xe_ggtt *ggtt = xe_device_get_root_tile(xe)->mem.ggtt;
 	u32 column, row;
-	u64 pte = xe_ggtt_encode_pte_flags(ggtt, bo, xe->pat.idx[XE_CACHE_NONE]);
+	u64 pte = xe_ggtt_encode_pte_flags(ggtt, bo, xe_cache_pat_idx(xe, XE_CACHE_NONE));
 
 	/* TODO: Maybe rewrite so we can traverse the bo addresses sequentially,
 	 * by writing dpt/ggtt in a different order?
@@ -64,7 +65,7 @@ write_dpt_remapped_linear(struct xe_bo *bo, struct iosys_map *map,
 	struct xe_device *xe = xe_bo_device(bo);
 	struct xe_ggtt *ggtt = xe_device_get_root_tile(xe)->mem.ggtt;
 	const u64 pte = xe_ggtt_encode_pte_flags(ggtt, bo,
-						 xe->pat.idx[XE_CACHE_NONE]);
+						 xe_cache_pat_idx(xe, XE_CACHE_NONE));
 	unsigned int offset = plane->offset * XE_PAGE_SIZE;
 	unsigned int size = plane->size;
 
@@ -87,7 +88,7 @@ write_dpt_remapped_tiled(struct xe_bo *bo, struct iosys_map *map,
 	struct xe_device *xe = xe_bo_device(bo);
 	struct xe_ggtt *ggtt = xe_device_get_root_tile(xe)->mem.ggtt;
 	const u64 pte = xe_ggtt_encode_pte_flags(ggtt, bo,
-						 xe->pat.idx[XE_CACHE_NONE]);
+						 xe_cache_pat_idx(xe, XE_CACHE_NONE));
 	unsigned int offset, column, row;
 
 	for (row = 0; row < plane->height; row++) {
@@ -190,7 +191,7 @@ static int __xe_pin_fb_vma_dpt(const struct intel_framebuffer *fb,
 		return PTR_ERR(dpt);
 
 	if (view->type == I915_GTT_VIEW_NORMAL) {
-		u64 pte = xe_ggtt_encode_pte_flags(ggtt, bo, xe->pat.idx[XE_CACHE_NONE]);
+		u64 pte = xe_ggtt_encode_pte_flags(ggtt, bo, xe_cache_pat_idx(xe, XE_CACHE_NONE));
 		u32 x;
 
 		for (x = 0; x < size / XE_PAGE_SIZE; x++) {
@@ -306,7 +307,7 @@ static int __xe_pin_fb_vma_ggtt(const struct intel_framebuffer *fb,
 		/* display uses tiles instead of bytes here, so convert it back.. */
 		size = intel_rotation_info_size(&view->rotated) * XE_PAGE_SIZE;
 
-	pte = xe_ggtt_encode_pte_flags(ggtt, bo, xe->pat.idx[XE_CACHE_NONE]);
+	pte = xe_ggtt_encode_pte_flags(ggtt, bo, xe_cache_pat_idx(xe, XE_CACHE_NONE));
 	vma->node = xe_ggtt_insert_node_transform(ggtt, bo, pte,
 						  ALIGN(size, align), align,
 						  view->type == I915_GTT_VIEW_NORMAL ?
diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
index 4ebaa0888a43..16c87ce3f614 100644
--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
@@ -528,6 +528,7 @@
 
 #define ROW_CHICKEN3				XE_REG_MCR(0xe49c, XE_REG_OPTION_MASKED)
 #define   XE2_EUPEND_CHK_FLUSH_DIS		REG_BIT(14)
+#define   DIS_EU_GRF_POISON_TO_LSC		REG_BIT(13)
 #define   DIS_FIX_EOT1_FLUSH			REG_BIT(9)
 
 #define TDL_TSL_CHICKEN				XE_REG_MCR(0xe4c4, XE_REG_OPTION_MASKED)
@@ -535,6 +536,9 @@
 #define   SLM_WMTP_RESTORE			REG_BIT(11)
 #define   RES_CHK_SPR_DIS			REG_BIT(6)
 
+#define TDL_TSL_CHICKEN2			XE_REG_MCR(0xe4cc, XE_REG_OPTION_MASKED)
+#define   TILEY_LOCALID				REG_BIT(2)
+
 #define ROW_CHICKEN				XE_REG_MCR(0xe4f0, XE_REG_OPTION_MASKED)
 #define   UGM_BACKUP_MODE			REG_BIT(13)
 #define   MDQ_ARBITRATION_MODE			REG_BIT(12)
@@ -560,6 +564,7 @@
 #define   DIS_ATOMIC_CHAINING_TYPED_WRITES	REG_BIT(3)
 
 #define TDL_CHICKEN				XE_REG_MCR(0xe5f4, XE_REG_OPTION_MASKED)
+#define   BIT_APQ_OPT_DIS			REG_BIT(14)
 #define   QID_WAIT_FOR_THREAD_NOT_RUN_DISABLE	REG_BIT(12)
 #define   EUSTALL_PERF_SAMPLING_DISABLE		REG_BIT(5)
 
@@ -583,7 +588,7 @@
 #define   DISABLE_128B_EVICTION_COMMAND_UDW	REG_BIT(36 - 32)
 #define   LSCFE_SAME_ADDRESS_ATOMICS_COALESCING_DISABLE	REG_BIT(35 - 32)
 
-#define ROW_CHICKEN5				XE_REG_MCR(0xe7f0)
+#define ROW_CHICKEN5				XE_REG_MCR(0xe7f0, XE_REG_OPTION_MASKED)
 #define   CPSS_AWARE_DIS			REG_BIT(3)
 
 #define SARB_CHICKEN1				XE_REG_MCR(0xe90c)
diff --git a/drivers/gpu/drm/xe/regs/xe_pcode_regs.h b/drivers/gpu/drm/xe/regs/xe_pcode_regs.h
index 4b3c46eb858f..c63b409d7a82 100644
--- a/drivers/gpu/drm/xe/regs/xe_pcode_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_pcode_regs.h
@@ -27,4 +27,7 @@
 #define   TEMP_SIGN_MASK			REG_BIT(31)
 #define BMG_PACKAGE_TEMPERATURE			XE_REG(0x138434)
 
+#define CRI_PACKAGE_ENERGY_STATUS		XE_REG(0x138120)
+#define CRI_PLATFORM_ENERGY_STATUS		XE_REG(0x138458)
+
 #endif /* _XE_PCODE_REGS_H_ */
diff --git a/drivers/gpu/drm/xe/regs/xe_sysctrl_regs.h b/drivers/gpu/drm/xe/regs/xe_sysctrl_regs.h
new file mode 100644
index 000000000000..59f3f3ec59a6
--- /dev/null
+++ b/drivers/gpu/drm/xe/regs/xe_sysctrl_regs.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#ifndef _XE_SYSCTRL_REGS_H_
+#define _XE_SYSCTRL_REGS_H_
+
+#include "xe_regs.h"
+
+#define SYSCTRL_BASE_OFFSET			0xdb000
+#define SYSCTRL_BASE				(SOC_BASE + SYSCTRL_BASE_OFFSET)
+#define SYSCTRL_MAILBOX_INDEX			0x03
+#define SYSCTRL_BAR_LENGTH			0x1000
+
+#define SYSCTRL_MB_CTRL				XE_REG(0x10)
+#define   SYSCTRL_MB_CTRL_RUN_BUSY		REG_BIT(31)
+#define   SYSCTRL_MB_CTRL_IRQ			REG_BIT(30)
+#define   SYSCTRL_MB_CTRL_RUN_BUSY_OUT		REG_BIT(29)
+#define   SYSCTRL_MB_CTRL_PARAM3_MASK		REG_GENMASK(28, 24)
+#define   SYSCTRL_MB_CTRL_PARAM2_MASK		REG_GENMASK(23, 16)
+#define   SYSCTRL_MB_CTRL_PARAM1_MASK		REG_GENMASK(15, 8)
+#define   SYSCTRL_MB_CTRL_COMMAND_MASK		REG_GENMASK(7, 0)
+#define   SYSCTRL_MB_CTRL_CMD			REG_FIELD_PREP(SYSCTRL_MB_CTRL_COMMAND_MASK, 5)
+
+#define SYSCTRL_MB_DATA0			XE_REG(0x14)
+#define SYSCTRL_MB_DATA1			XE_REG(0x18)
+#define SYSCTRL_MB_DATA2			XE_REG(0x1c)
+#define SYSCTRL_MB_DATA3			XE_REG(0x20)
+
+#define SYSCTRL_FRAME_PHASE			REG_BIT(24)
+#define SYSCTRL_FRAME_CURRENT_MASK		REG_GENMASK(21, 16)
+#define SYSCTRL_FRAME_TOTAL_MASK		REG_GENMASK(13, 8)
+#define SYSCTRL_FRAME_COMMAND_MASK		REG_GENMASK(7, 0)
+
+#endif
diff --git a/drivers/gpu/drm/xe/tests/xe_gt_sriov_pf_config_kunit.c b/drivers/gpu/drm/xe/tests/xe_gt_sriov_pf_config_kunit.c
index efa8963ec248..e6eaa94d4d30 100644
--- a/drivers/gpu/drm/xe/tests/xe_gt_sriov_pf_config_kunit.c
+++ b/drivers/gpu/drm/xe/tests/xe_gt_sriov_pf_config_kunit.c
@@ -13,11 +13,28 @@
 #define TEST_MAX_VFS	63
 #define TEST_VRAM	0x7a800000ull	/* random size that works on 32-bit */
 
+static bool xe_device_is_admin_only_stub_enable(const struct xe_device *xe)
+{
+	return true;
+}
+
+static bool xe_device_is_admin_only_stub_disable(const struct xe_device *xe)
+{
+	return false;
+}
+
 static void pf_set_admin_mode(struct xe_device *xe, bool enable)
 {
-	/* should match logic of xe_sriov_pf_admin_only() */
-	xe->sriov.pf.admin_only = enable;
+	typeof(xe_device_is_admin_only) *stub = enable ?
+		xe_device_is_admin_only_stub_enable :
+		xe_device_is_admin_only_stub_disable;
+
+	kunit_activate_static_stub(kunit_get_current_test(),
+				   xe_device_is_admin_only,
+				   *stub);
+
 	KUNIT_EXPECT_EQ(kunit_get_current_test(), enable, xe_sriov_pf_admin_only(xe));
+	KUNIT_EXPECT_EQ(kunit_get_current_test(), enable, xe_device_is_admin_only(xe));
 }
 
 static void pf_set_usable_vram(struct xe_device *xe, u64 usable)
diff --git a/drivers/gpu/drm/xe/tests/xe_migrate.c b/drivers/gpu/drm/xe/tests/xe_migrate.c
index 34e2f0f4631f..50a97705e0ac 100644
--- a/drivers/gpu/drm/xe/tests/xe_migrate.c
+++ b/drivers/gpu/drm/xe/tests/xe_migrate.c
@@ -9,6 +9,7 @@
 #include "tests/xe_kunit_helpers.h"
 #include "tests/xe_pci_test.h"
 
+#include "xe_pat.h"
 #include "xe_pci.h"
 #include "xe_pm.h"
 
@@ -246,7 +247,7 @@ static void xe_migrate_sanity_test(struct xe_migrate *m, struct kunit *test,
 	/* First part of the test, are we updating our pagetable bo with a new entry? */
 	xe_map_wr(xe, &bo->vmap, XE_PAGE_SIZE * (NUM_KERNEL_PDE - 1), u64,
 		  0xdeaddeadbeefbeef);
-	expected = m->q->vm->pt_ops->pte_encode_bo(pt, 0, xe->pat.idx[XE_CACHE_WB], 0);
+	expected = m->q->vm->pt_ops->pte_encode_bo(pt, 0, xe_cache_pat_idx(xe, XE_CACHE_WB), 0);
 	if (m->q->vm->flags & XE_VM_FLAG_64K)
 		expected |= XE_PTE_PS64;
 	if (xe_bo_is_vram(pt))
diff --git a/drivers/gpu/drm/xe/tests/xe_pci.c b/drivers/gpu/drm/xe/tests/xe_pci.c
index f3179b31f13e..860409c579f8 100644
--- a/drivers/gpu/drm/xe/tests/xe_pci.c
+++ b/drivers/gpu/drm/xe/tests/xe_pci.c
@@ -131,12 +131,12 @@ static const char *subplatform_prefix(enum xe_subplatform s)
 	return s == XE_SUBPLATFORM_NONE ? "" : " ";
 }
 
-static const char *step_prefix(enum xe_step step)
+static const char *step_prefix(enum intel_step step)
 {
 	return step == STEP_NONE ? "" : " ";
 }
 
-static const char *step_name(enum xe_step step)
+static const char *step_name(enum intel_step step)
 {
 	return step == STEP_NONE ? "" : xe_step_name(step);
 }
diff --git a/drivers/gpu/drm/xe/xe_bo.c b/drivers/gpu/drm/xe/xe_bo.c
index a7c2dc7f224c..5ce60d161e09 100644
--- a/drivers/gpu/drm/xe/xe_bo.c
+++ b/drivers/gpu/drm/xe/xe_bo.c
@@ -173,19 +173,6 @@ mem_type_to_migrate(struct xe_device *xe, u32 mem_type)
 	return tile->migrate;
 }
 
-static struct xe_vram_region *res_to_mem_region(struct ttm_resource *res)
-{
-	struct xe_device *xe = ttm_to_xe_device(res->bo->bdev);
-	struct ttm_resource_manager *mgr;
-	struct xe_ttm_vram_mgr *vram_mgr;
-
-	xe_assert(xe, resource_is_vram(res));
-	mgr = ttm_manager_type(&xe->ttm, res->mem_type);
-	vram_mgr = to_xe_ttm_vram_mgr(mgr);
-
-	return container_of(vram_mgr, struct xe_vram_region, ttm);
-}
-
 static void try_add_system(struct xe_device *xe, struct xe_bo *bo,
 			   u32 bo_flags, u32 *c)
 {
@@ -635,7 +622,7 @@ static int xe_ttm_io_mem_reserve(struct ttm_device *bdev,
 		return 0;
 	case XE_PL_VRAM0:
 	case XE_PL_VRAM1: {
-		struct xe_vram_region *vram = res_to_mem_region(mem);
+		struct xe_vram_region *vram = xe_map_resource_to_region(mem);
 
 		if (!xe_ttm_resource_visible(mem))
 			return -EINVAL;
@@ -1642,7 +1629,7 @@ static unsigned long xe_ttm_io_mem_pfn(struct ttm_buffer_object *ttm_bo,
 	if (ttm_bo->resource->mem_type == XE_PL_STOLEN)
 		return xe_ttm_stolen_io_offset(bo, page_offset << PAGE_SHIFT) >> PAGE_SHIFT;
 
-	vram = res_to_mem_region(ttm_bo->resource);
+	vram = xe_map_resource_to_region(ttm_bo->resource);
 	xe_res_first(ttm_bo->resource, (u64)page_offset << PAGE_SHIFT, 0, &cursor);
 	return (vram->io_start + cursor.start) >> PAGE_SHIFT;
 }
@@ -1782,7 +1769,7 @@ static int xe_ttm_access_memory(struct ttm_buffer_object *ttm_bo,
 		goto out;
 	}
 
-	vram = res_to_mem_region(ttm_bo->resource);
+	vram = xe_map_resource_to_region(ttm_bo->resource);
 	xe_res_first(ttm_bo->resource, offset & PAGE_MASK,
 		     xe_bo_size(bo) - (offset & PAGE_MASK), &cursor);
 
@@ -2322,8 +2309,10 @@ struct xe_bo *xe_bo_init_locked(struct xe_device *xe, struct xe_bo *bo,
 	}
 
 	/* XE_BO_FLAG_GGTTx requires XE_BO_FLAG_GGTT also be set */
-	if ((flags & XE_BO_FLAG_GGTT_ALL) && !(flags & XE_BO_FLAG_GGTT))
+	if ((flags & XE_BO_FLAG_GGTT_ALL) && !(flags & XE_BO_FLAG_GGTT)) {
+		xe_bo_free(bo);
 		return ERR_PTR(-EINVAL);
+	}
 
 	if (flags & (XE_BO_FLAG_VRAM_MASK | XE_BO_FLAG_STOLEN) &&
 	    !(flags & XE_BO_FLAG_IGNORE_MIN_PAGE_SIZE) &&
@@ -2342,8 +2331,10 @@ struct xe_bo *xe_bo_init_locked(struct xe_device *xe, struct xe_bo *bo,
 		alignment = SZ_4K >> PAGE_SHIFT;
 	}
 
-	if (type == ttm_bo_type_device && aligned_size != size)
+	if (type == ttm_bo_type_device && aligned_size != size) {
+		xe_bo_free(bo);
 		return ERR_PTR(-EINVAL);
+	}
 
 	if (!bo) {
 		bo = xe_bo_alloc();
@@ -2923,7 +2914,7 @@ uint64_t vram_region_gpu_offset(struct ttm_resource *res)
 	case XE_PL_SYSTEM:
 		return 0;
 	default:
-		return res_to_mem_region(res)->dpa_base;
+		return xe_map_resource_to_region(res)->dpa_base;
 	}
 	return 0;
 }
diff --git a/drivers/gpu/drm/xe/xe_bo_types.h b/drivers/gpu/drm/xe/xe_bo_types.h
index ff8317bfc1ae..9c199badd9b2 100644
--- a/drivers/gpu/drm/xe/xe_bo_types.h
+++ b/drivers/gpu/drm/xe/xe_bo_types.h
@@ -18,6 +18,7 @@
 #include "xe_ggtt_types.h"
 
 struct xe_device;
+struct xe_mem_pool_node;
 struct xe_vm;
 
 #define XE_BO_MAX_PLACEMENTS	3
@@ -66,7 +67,7 @@ struct xe_bo {
 	/** @attr: User controlled attributes for bo */
 	struct {
 		/**
-		 * @atomic_access: type of atomic access bo needs
+		 * @attr.atomic_access: type of atomic access bo needs
 		 * protected by bo dma-resv lock
 		 */
 		u32 atomic_access;
@@ -88,7 +89,7 @@ struct xe_bo {
 	bool ccs_cleared;
 
 	/** @bb_ccs: BB instructions of CCS read/write. Valid only for VF */
-	struct xe_bb *bb_ccs[XE_SRIOV_VF_CCS_CTX_COUNT];
+	struct xe_mem_pool_node *bb_ccs[XE_SRIOV_VF_CCS_CTX_COUNT];
 
 	/**
 	 * @cpu_caching: CPU caching mode. Currently only used for userspace
diff --git a/drivers/gpu/drm/xe/xe_debugfs.c b/drivers/gpu/drm/xe/xe_debugfs.c
index ad2d8f179eb6..22b471303984 100644
--- a/drivers/gpu/drm/xe/xe_debugfs.c
+++ b/drivers/gpu/drm/xe/xe_debugfs.c
@@ -15,9 +15,11 @@
 #include "xe_bo.h"
 #include "xe_device.h"
 #include "xe_force_wake.h"
+#include "xe_gt.h"
 #include "xe_gt_debugfs.h"
 #include "xe_gt_printk.h"
 #include "xe_guc_ads.h"
+#include "xe_hw_engine.h"
 #include "xe_mmio.h"
 #include "xe_pm.h"
 #include "xe_psmi.h"
@@ -61,6 +63,37 @@ static struct xe_device *node_to_xe(struct drm_info_node *node)
 	return to_xe_device(node->minor->dev);
 }
 
+static void print_engine_class_mask(struct drm_printer *p, u16 mask)
+{
+	if (!mask) {
+		drm_printf(p, " none\n");
+		return;
+	}
+
+	for (enum xe_engine_class ec = 0; ec < XE_ENGINE_CLASS_MAX; ec++) {
+		if (mask & BIT(ec))
+			drm_printf(p, " %s", xe_hw_engine_class_to_str(ec));
+	}
+	drm_printf(p, "\n");
+}
+
+static void print_engine_mask(struct drm_printer *p, struct xe_gt *gt, u64 mask)
+{
+	struct xe_hw_engine *hwe;
+	enum xe_hw_engine_id id;
+
+	if (!mask) {
+		drm_printf(p, " none\n");
+		return;
+	}
+
+	for_each_hw_engine(hwe, gt, id) {
+		if (mask & BIT_ULL(id))
+			drm_printf(p, " %s", hwe->name);
+	}
+	drm_printf(p, "\n");
+}
+
 static int info(struct seq_file *m, void *data)
 {
 	struct xe_device *xe = node_to_xe(m->private);
@@ -88,13 +121,15 @@ static int info(struct seq_file *m, void *data)
 	drm_printf(&p, "has_flat_ccs %s\n", str_yes_no(xe->info.has_flat_ccs));
 	drm_printf(&p, "has_usm %s\n", str_yes_no(xe->info.has_usm));
 	drm_printf(&p, "skip_guc_pc %s\n", str_yes_no(xe->info.skip_guc_pc));
+	drm_printf(&p, "multi_lrc_engine_classes");
+	print_engine_class_mask(&p, xe->info.multi_lrc_mask);
 	for_each_gt(gt, xe, id) {
 		drm_printf(&p, "gt%d force wake %d\n", id,
 			   xe_force_wake_ref(gt_to_fw(gt), XE_FW_GT));
-		drm_printf(&p, "gt%d engine_mask 0x%llx\n", id,
-			   gt->info.engine_mask);
-		drm_printf(&p, "gt%d multi_queue_engine_class_mask 0x%x\n", id,
-			   gt->info.multi_queue_engine_class_mask);
+		drm_printf(&p, "gt%d engines", id);
+		print_engine_mask(&p, gt, gt->info.engine_mask);
+		drm_printf(&p, "gt%d multi_queue_engine_classes", id);
+		print_engine_class_mask(&p, gt->info.multi_queue_engine_class_mask);
 	}
 
 	return 0;
diff --git a/drivers/gpu/drm/xe/xe_dep_scheduler.h b/drivers/gpu/drm/xe/xe_dep_scheduler.h
index 853961eec64b..f314fb5d80f5 100644
--- a/drivers/gpu/drm/xe/xe_dep_scheduler.h
+++ b/drivers/gpu/drm/xe/xe_dep_scheduler.h
@@ -3,6 +3,9 @@
  * Copyright © 2025 Intel Corporation
  */
 
+#ifndef _XE_DEP_SCHEDULER_H_
+#define _XE_DEP_SCHEDULER_H_
+
 #include <linux/types.h>
 
 struct drm_sched_entity;
@@ -19,3 +22,5 @@ void xe_dep_scheduler_fini(struct xe_dep_scheduler *dep_scheduler);
 
 struct drm_sched_entity *
 xe_dep_scheduler_entity(struct xe_dep_scheduler *dep_scheduler);
+
+#endif
diff --git a/drivers/gpu/drm/xe/xe_devcoredump.c b/drivers/gpu/drm/xe/xe_devcoredump.c
index 558a1a9841a0..ec206f512795 100644
--- a/drivers/gpu/drm/xe/xe_devcoredump.c
+++ b/drivers/gpu/drm/xe/xe_devcoredump.c
@@ -149,7 +149,8 @@ static void xe_devcoredump_snapshot_free(struct xe_devcoredump_snapshot *ss)
 	xe_guc_ct_snapshot_free(ss->guc.ct);
 	ss->guc.ct = NULL;
 
-	xe_guc_capture_put_matched_nodes(&ss->gt->uc.guc);
+	if (!IS_ERR_OR_NULL(ss->gt))
+		xe_guc_capture_put_matched_nodes(&ss->gt->uc.guc);
 	ss->matched_node = NULL;
 
 	xe_guc_exec_queue_snapshot_free(ss->ge);
@@ -254,7 +255,8 @@ static void xe_devcoredump_free(void *data)
 	if (!data || !coredump_to_xe(coredump))
 		return;
 
-	cancel_work_sync(&coredump->snapshot.work);
+	if (coredump->captured)
+		cancel_work_sync(&coredump->snapshot.work);
 
 	mutex_lock(&coredump->lock);
 
diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c
index ffea4a453c01..4b45b617a039 100644
--- a/drivers/gpu/drm/xe/xe_device.c
+++ b/drivers/gpu/drm/xe/xe_device.c
@@ -17,6 +17,7 @@
 #include <drm/drm_managed.h>
 #include <drm/drm_pagemap_util.h>
 #include <drm/drm_print.h>
+#include <kunit/static_stub.h>
 #include <uapi/drm/xe_drm.h>
 
 #include "display/xe_display.h"
@@ -25,6 +26,7 @@
 #include "regs/xe_regs.h"
 #include "xe_bo.h"
 #include "xe_bo_evict.h"
+#include "xe_configfs.h"
 #include "xe_debugfs.h"
 #include "xe_defaults.h"
 #include "xe_devcoredump.h"
@@ -65,6 +67,7 @@
 #include "xe_survivability_mode.h"
 #include "xe_sriov.h"
 #include "xe_svm.h"
+#include "xe_sysctrl.h"
 #include "xe_tile.h"
 #include "xe_ttm_stolen_mgr.h"
 #include "xe_ttm_sys_mgr.h"
@@ -389,7 +392,7 @@ bool xe_is_xe_file(const struct file *file)
 	return file->f_op == &xe_driver_fops;
 }
 
-static struct drm_driver driver = {
+static struct drm_driver regular_driver = {
 	.driver_features =
 	    DRIVER_GEM |
 	    DRIVER_RENDER | DRIVER_SYNCOBJ |
@@ -414,6 +417,40 @@ static struct drm_driver driver = {
 	.patchlevel = DRIVER_PATCHLEVEL,
 };
 
+#ifdef CONFIG_PCI_IOV
+static const struct drm_ioctl_desc xe_ioctls_admin_only[] = {
+	DRM_IOCTL_DEF_DRV(XE_DEVICE_QUERY, xe_query_ioctl, DRM_RENDER_ALLOW),
+	DRM_IOCTL_DEF_DRV(XE_OBSERVATION, xe_observation_ioctl, DRM_RENDER_ALLOW),
+};
+
+static struct drm_driver admin_only_driver = {
+	.driver_features =
+	    DRIVER_GEM | DRIVER_RENDER | DRIVER_GEM_GPUVA,
+	.open = xe_file_open,
+	.postclose = xe_file_close,
+	.ioctls = xe_ioctls_admin_only,
+	.num_ioctls = ARRAY_SIZE(xe_ioctls_admin_only),
+	.fops = &xe_driver_fops,
+	.name = DRIVER_NAME,
+	.desc = DRIVER_DESC,
+	.major = DRIVER_MAJOR,
+	.minor = DRIVER_MINOR,
+	.patchlevel = DRIVER_PATCHLEVEL,
+};
+
+/**
+ * xe_device_is_admin_only() - Check whether device is admin only or not.
+ * @xe: the &xe_device to check
+ *
+ * Return: true if the device is admin only, false otherwise.
+ */
+bool xe_device_is_admin_only(const struct xe_device *xe)
+{
+	KUNIT_STATIC_STUB_REDIRECT(xe_device_is_admin_only, xe);
+	return xe->drm.driver == &admin_only_driver;
+}
+#endif
+
 static void xe_device_destroy(struct drm_device *dev, void *dummy)
 {
 	struct xe_device *xe = to_xe_device(dev);
@@ -438,16 +475,26 @@ static void xe_device_destroy(struct drm_device *dev, void *dummy)
 struct xe_device *xe_device_create(struct pci_dev *pdev,
 				   const struct pci_device_id *ent)
 {
+	struct drm_driver *driver = &regular_driver;
 	struct xe_device *xe;
 	int err;
 
-	xe_display_driver_set_hooks(&driver);
+#ifdef CONFIG_PCI_IOV
+	/*
+	 * Since XE device is not initialized yet, read from configfs
+	 * directly to decide whether we are in admin-only PF mode or not.
+	 */
+	if (xe_configfs_admin_only_pf(pdev))
+		driver = &admin_only_driver;
+#endif
+
+	xe_display_driver_set_hooks(driver);
 
-	err = aperture_remove_conflicting_pci_devices(pdev, driver.name);
+	err = aperture_remove_conflicting_pci_devices(pdev, driver->name);
 	if (err)
 		return ERR_PTR(err);
 
-	xe = devm_drm_dev_alloc(&pdev->dev, &driver, struct xe_device, drm);
+	xe = devm_drm_dev_alloc(&pdev->dev, driver, struct xe_device, drm);
 	if (IS_ERR(xe))
 		return xe;
 
@@ -707,6 +754,11 @@ int xe_device_probe_early(struct xe_device *xe)
 
 	xe_sriov_probe_early(xe);
 
+	if (xe_device_is_admin_only(xe) && !IS_SRIOV_PF(xe)) {
+		xe_err(xe, "Can't run Admin-only mode without SR-IOV PF mode!\n");
+		return -ENODEV;
+	}
+
 	if (IS_SRIOV_VF(xe))
 		vf_update_device_info(xe);
 
@@ -992,6 +1044,10 @@ int xe_device_probe(struct xe_device *xe)
 	if (err)
 		goto err_unregister_display;
 
+	err = xe_sysctrl_init(xe);
+	if (err)
+		goto err_unregister_display;
+
 	err = xe_device_sysfs_init(xe);
 	if (err)
 		goto err_unregister_display;
diff --git a/drivers/gpu/drm/xe/xe_device.h b/drivers/gpu/drm/xe/xe_device.h
index e4b9de8d8e95..555c191f7510 100644
--- a/drivers/gpu/drm/xe/xe_device.h
+++ b/drivers/gpu/drm/xe/xe_device.h
@@ -211,6 +211,15 @@ bool xe_is_xe_file(const struct file *file);
 
 struct xe_vm *xe_device_asid_to_vm(struct xe_device *xe, u32 asid);
 
+#ifdef CONFIG_PCI_IOV
+bool xe_device_is_admin_only(const struct xe_device *xe);
+#else
+static inline bool xe_device_is_admin_only(const struct xe_device *xe)
+{
+	return false;
+}
+#endif
+
 /*
  * Occasionally it is seen that the G2H worker starts running after a delay of more than
  * a second even after being queued and activated by the Linux workqueue subsystem. This
diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
index 615218d775b1..89437de3001a 100644
--- a/drivers/gpu/drm/xe/xe_device_types.h
+++ b/drivers/gpu/drm/xe/xe_device_types.h
@@ -27,6 +27,7 @@
 #include "xe_sriov_vf_ccs_types.h"
 #include "xe_step_types.h"
 #include "xe_survivability_mode_types.h"
+#include "xe_sysctrl_types.h"
 #include "xe_tile_types.h"
 #include "xe_validation.h"
 
@@ -196,6 +197,8 @@ struct xe_device {
 		u8 has_soc_remapper_telem:1;
 		/** @info.has_sriov: Supports SR-IOV */
 		u8 has_sriov:1;
+		/** @info.has_sysctrl: Supports System Controller */
+		u8 has_sysctrl:1;
 		/** @info.has_usm: Device has unified shared memory support */
 		u8 has_usm:1;
 		/** @info.has_64bit_timestamp: Device supports 64-bit timestamps */
@@ -215,8 +218,6 @@ struct xe_device {
 		u8 probe_display:1;
 		/** @info.skip_guc_pc: Skip GuC based PM feature init */
 		u8 skip_guc_pc:1;
-		/** @info.skip_mtcfg: skip Multi-Tile configuration from MTCFG register */
-		u8 skip_mtcfg:1;
 		/** @info.skip_pcode: skip access to PCODE uC */
 		u8 skip_pcode:1;
 		/** @info.needs_shared_vf_gt_wq: needs shared GT WQ on VF */
@@ -273,7 +274,7 @@ struct xe_device {
 		struct xe_vram_region *vram;
 		/** @mem.sys_mgr: system TTM manager */
 		struct ttm_resource_manager sys_mgr;
-		/** @mem.sys_mgr: system memory shrinker. */
+		/** @mem.shrinker: system memory shrinker. */
 		struct xe_shrinker *shrinker;
 	} mem;
 
@@ -295,7 +296,7 @@ struct xe_device {
 
 	/** @usm: unified memory state */
 	struct {
-		/** @usm.asid: convert a ASID to VM */
+		/** @usm.asid_to_vm: convert an ASID to VM */
 		struct xarray asid_to_vm;
 		/** @usm.next_asid: next ASID, used to cyclical alloc asids */
 		u32 next_asid;
@@ -312,7 +313,7 @@ struct xe_device {
 		/** @usm.pf_queue: Page fault queues */
 		struct xe_pagefault_queue pf_queue[XE_PAGEFAULT_QUEUE_COUNT];
 #if IS_ENABLED(CONFIG_DRM_XE_PAGEMAP)
-		/** @usm.pagemap_shrinker: Shrinker for unused pagemaps */
+		/** @usm.dpagemap_shrinker: Shrinker for unused pagemaps */
 		struct drm_pagemap_shrinker *dpagemap_shrinker;
 #endif
 	} usm;
@@ -334,7 +335,7 @@ struct xe_device {
 			struct list_head kernel_bo_present;
 			/** @pinned.late.evicted: pinned BO that have been evicted */
 			struct list_head evicted;
-			/** @pinned.external: pinned external and dma-buf. */
+			/** @pinned.late.external: pinned external and dma-buf. */
 			struct list_head external;
 		} late;
 	} pinned;
@@ -369,7 +370,7 @@ struct xe_device {
 		struct {
 			/**
 			 * @mem_access.vram_userfault.lock: Protects access to
-			 * @vram_usefault.list Using mutex instead of spinlock
+			 * @mem_access.vram_userfault.list Using mutex instead of spinlock
 			 * as lock is applied to entire list operation which
 			 * may sleep
 			 */
@@ -400,7 +401,7 @@ struct xe_device {
 		const struct xe_pat_table_entry *pat_primary_pta;
 		/** @pat.pat_media_pta: media GT PAT entry for page table accesses */
 		const struct xe_pat_table_entry *pat_media_pta;
-		u32 idx[__XE_CACHE_LEVEL_COUNT];
+		u16 idx[__XE_CACHE_LEVEL_COUNT];
 	} pat;
 
 	/** @d3cold: Encapsulate d3cold related stuff */
@@ -508,6 +509,9 @@ struct xe_device {
 	/** @i2c: I2C host controller */
 	struct xe_i2c *i2c;
 
+	/** @sc: System Controller */
+	struct xe_sysctrl sc;
+
 	/** @atomic_svm_timeslice_ms: Atomic SVM fault timeslice MS */
 	u32 atomic_svm_timeslice_ms;
 
@@ -578,7 +582,7 @@ struct xe_file {
 
 	/** @vm: VM state for file */
 	struct {
-		/** @vm.xe: xarray to store VMs */
+		/** @vm.xa: xarray to store VMs */
 		struct xarray xa;
 		/**
 		 * @vm.lock: Protects VM lookup + reference and removal from
diff --git a/drivers/gpu/drm/xe/xe_dma_buf.c b/drivers/gpu/drm/xe/xe_dma_buf.c
index 7f9602b3363d..b9828da15897 100644
--- a/drivers/gpu/drm/xe/xe_dma_buf.c
+++ b/drivers/gpu/drm/xe/xe_dma_buf.c
@@ -258,6 +258,13 @@ struct dma_buf *xe_gem_prime_export(struct drm_gem_object *obj, int flags)
 	return ERR_PTR(ret);
 }
 
+/*
+ * Takes ownership of @storage: on success it is transferred to the returned
+ * drm_gem_object; on failure it is freed before returning the error.
+ * This matches the contract of xe_bo_init_locked() which frees @storage on
+ * its error paths, so callers need not (and must not) free @storage after
+ * this call.
+ */
 static struct drm_gem_object *
 xe_dma_buf_init_obj(struct drm_device *dev, struct xe_bo *storage,
 		    struct dma_buf *dma_buf)
@@ -271,8 +278,10 @@ xe_dma_buf_init_obj(struct drm_device *dev, struct xe_bo *storage,
 	int ret = 0;
 
 	dummy_obj = drm_gpuvm_resv_object_alloc(&xe->drm);
-	if (!dummy_obj)
+	if (!dummy_obj) {
+		xe_bo_free(storage);
 		return ERR_PTR(-ENOMEM);
+	}
 
 	dummy_obj->resv = resv;
 	xe_validation_guard(&ctx, &xe->val, &exec, (struct xe_val_flags) {}, ret) {
@@ -281,6 +290,7 @@ xe_dma_buf_init_obj(struct drm_device *dev, struct xe_bo *storage,
 		if (ret)
 			break;
 
+		/* xe_bo_init_locked() frees storage on error */
 		bo = xe_bo_init_locked(xe, storage, NULL, resv, NULL, dma_buf->size,
 				       0, /* Will require 1way or 2way for vm_bind */
 				       ttm_bo_type_sg, XE_BO_FLAG_SYSTEM, &exec);
@@ -368,12 +378,15 @@ struct drm_gem_object *xe_gem_prime_import(struct drm_device *dev,
 		goto out_err;
 	}
 
-	/* Errors here will take care of freeing the bo. */
+	/*
+	 * xe_dma_buf_init_obj() takes ownership of bo on both success
+	 * and failure, so we must not touch bo after this call.
+	 */
 	obj = xe_dma_buf_init_obj(dev, bo, dma_buf);
-	if (IS_ERR(obj))
+	if (IS_ERR(obj)) {
+		dma_buf_detach(dma_buf, attach);
 		return obj;
-
-
+	}
 	get_dma_buf(dma_buf);
 	obj->import_attach = attach;
 	return obj;
diff --git a/drivers/gpu/drm/xe/xe_drm_ras.c b/drivers/gpu/drm/xe/xe_drm_ras.c
index e07dc23a155e..c21c8b428de6 100644
--- a/drivers/gpu/drm/xe/xe_drm_ras.c
+++ b/drivers/gpu/drm/xe/xe_drm_ras.c
@@ -27,6 +27,16 @@ static int hw_query_error_counter(struct xe_drm_ras_counter *info,
 	return 0;
 }
 
+static int hw_clear_error_counter(struct xe_drm_ras_counter *info, u32 error_id)
+{
+	if (!info || !info[error_id].name)
+		return -ENOENT;
+
+	atomic_set(&info[error_id].counter, 0);
+
+	return 0;
+}
+
 static int query_uncorrectable_error_counter(struct drm_ras_node *ep, u32 error_id,
 					     const char **name, u32 *val)
 {
@@ -37,6 +47,15 @@ static int query_uncorrectable_error_counter(struct drm_ras_node *ep, u32 error_
 	return hw_query_error_counter(info, error_id, name, val);
 }
 
+static int clear_uncorrectable_error_counter(struct drm_ras_node *node, u32 error_id)
+{
+	struct xe_device *xe = node->priv;
+	struct xe_drm_ras *ras = &xe->ras;
+	struct xe_drm_ras_counter *info = ras->info[DRM_XE_RAS_ERR_SEV_UNCORRECTABLE];
+
+	return hw_clear_error_counter(info, error_id);
+}
+
 static int query_correctable_error_counter(struct drm_ras_node *ep, u32 error_id,
 					   const char **name, u32 *val)
 {
@@ -47,6 +66,15 @@ static int query_correctable_error_counter(struct drm_ras_node *ep, u32 error_id
 	return hw_query_error_counter(info, error_id, name, val);
 }
 
+static int clear_correctable_error_counter(struct drm_ras_node *node, u32 error_id)
+{
+	struct xe_device *xe = node->priv;
+	struct xe_drm_ras *ras = &xe->ras;
+	struct xe_drm_ras_counter *info = ras->info[DRM_XE_RAS_ERR_SEV_CORRECTABLE];
+
+	return hw_clear_error_counter(info, error_id);
+}
+
 static struct xe_drm_ras_counter *allocate_and_copy_counters(struct xe_device *xe)
 {
 	struct xe_drm_ras_counter *counter;
@@ -92,10 +120,13 @@ static int assign_node_params(struct xe_device *xe, struct drm_ras_node *node,
 	if (IS_ERR(ras->info[severity]))
 		return PTR_ERR(ras->info[severity]);
 
-	if (severity == DRM_XE_RAS_ERR_SEV_CORRECTABLE)
+	if (severity == DRM_XE_RAS_ERR_SEV_CORRECTABLE) {
 		node->query_error_counter = query_correctable_error_counter;
-	else
+		node->clear_error_counter = clear_correctable_error_counter;
+	} else {
 		node->query_error_counter = query_uncorrectable_error_counter;
+		node->clear_error_counter = clear_uncorrectable_error_counter;
+	}
 
 	return 0;
 }
diff --git a/drivers/gpu/drm/xe/xe_drm_ras.h b/drivers/gpu/drm/xe/xe_drm_ras.h
index 5cc8f0124411..365c70e93e82 100644
--- a/drivers/gpu/drm/xe/xe_drm_ras.h
+++ b/drivers/gpu/drm/xe/xe_drm_ras.h
@@ -2,8 +2,8 @@
 /*
  * Copyright © 2026 Intel Corporation
  */
-#ifndef XE_DRM_RAS_H_
-#define XE_DRM_RAS_H_
+#ifndef _XE_DRM_RAS_H_
+#define _XE_DRM_RAS_H_
 
 struct xe_device;
 
diff --git a/drivers/gpu/drm/xe/xe_eu_stall.c b/drivers/gpu/drm/xe/xe_eu_stall.c
index c34408cfd292..dddcdd0bb7a3 100644
--- a/drivers/gpu/drm/xe/xe_eu_stall.c
+++ b/drivers/gpu/drm/xe/xe_eu_stall.c
@@ -869,14 +869,14 @@ static int xe_eu_stall_stream_close(struct inode *inode, struct file *file)
 	struct xe_eu_stall_data_stream *stream = file->private_data;
 	struct xe_gt *gt = stream->gt;
 
-	drm_dev_put(&gt->tile->xe->drm);
-
 	mutex_lock(&gt->eu_stall->stream_lock);
 	xe_eu_stall_disable_locked(stream);
 	xe_eu_stall_data_buf_destroy(stream);
 	xe_eu_stall_stream_free(stream);
 	mutex_unlock(&gt->eu_stall->stream_lock);
 
+	drm_dev_put(&gt->tile->xe->drm);
+
 	return 0;
 }
 
diff --git a/drivers/gpu/drm/xe/xe_eu_stall.h b/drivers/gpu/drm/xe/xe_eu_stall.h
index d1c76e503799..842bef9f6872 100644
--- a/drivers/gpu/drm/xe/xe_eu_stall.h
+++ b/drivers/gpu/drm/xe/xe_eu_stall.h
@@ -3,8 +3,8 @@
  * Copyright © 2025 Intel Corporation
  */
 
-#ifndef __XE_EU_STALL_H__
-#define __XE_EU_STALL_H__
+#ifndef _XE_EU_STALL_H_
+#define _XE_EU_STALL_H_
 
 #include "xe_gt_types.h"
 #include "xe_sriov.h"
diff --git a/drivers/gpu/drm/xe/xe_exec_queue.c b/drivers/gpu/drm/xe/xe_exec_queue.c
index b287d0e0e60a..071b8c41df43 100644
--- a/drivers/gpu/drm/xe/xe_exec_queue.c
+++ b/drivers/gpu/drm/xe/xe_exec_queue.c
@@ -1405,7 +1405,7 @@ int xe_exec_queue_create_ioctl(struct drm_device *dev, void *data,
 		if (q->vm && q->hwe->hw_engine_group) {
 			err = xe_hw_engine_group_add_exec_queue(q->hwe->hw_engine_group, q);
 			if (err)
-				goto put_exec_queue;
+				goto kill_exec_queue;
 		}
 	}
 
@@ -1416,12 +1416,15 @@ int xe_exec_queue_create_ioctl(struct drm_device *dev, void *data,
 	/* user id alloc must always be last in ioctl to prevent UAF */
 	err = xa_alloc(&xef->exec_queue.xa, &id, q, xa_limit_32b, GFP_KERNEL);
 	if (err)
-		goto kill_exec_queue;
+		goto del_hw_engine_group;
 
 	args->exec_queue_id = id;
 
 	return 0;
 
+del_hw_engine_group:
+	if (q->vm && q->hwe && q->hwe->hw_engine_group)
+		xe_hw_engine_group_del_exec_queue(q->hwe->hw_engine_group, q);
 kill_exec_queue:
 	xe_exec_queue_kill(q);
 delete_queue_group:
@@ -1760,7 +1763,7 @@ void xe_exec_queue_tlb_inval_last_fence_put(struct xe_exec_queue *q,
 void xe_exec_queue_tlb_inval_last_fence_put_unlocked(struct xe_exec_queue *q,
 						     unsigned int type)
 {
-	xe_assert(q->vm->xe, type == XE_EXEC_QUEUE_TLB_INVAL_MEDIA_GT ||
+	xe_assert(gt_to_xe(q->gt), type == XE_EXEC_QUEUE_TLB_INVAL_MEDIA_GT ||
 		  type == XE_EXEC_QUEUE_TLB_INVAL_PRIMARY_GT);
 
 	dma_fence_put(q->tlb_inval[type].last_fence);
diff --git a/drivers/gpu/drm/xe/xe_exec_queue_types.h b/drivers/gpu/drm/xe/xe_exec_queue_types.h
index 8ce78e0b1d50..2f5ccf294675 100644
--- a/drivers/gpu/drm/xe/xe_exec_queue_types.h
+++ b/drivers/gpu/drm/xe/xe_exec_queue_types.h
@@ -214,7 +214,7 @@ struct xe_exec_queue {
 		 */
 		struct xe_dep_scheduler *dep_scheduler;
 		/**
-		 * @last_fence: last fence for tlb invalidation, protected by
+		 * @tlb_inval.last_fence: last fence for tlb invalidation, protected by
 		 * vm->lock in write mode
 		 */
 		struct dma_fence *last_fence;
diff --git a/drivers/gpu/drm/xe/xe_ggtt.c b/drivers/gpu/drm/xe/xe_ggtt.c
index a848d1a41b9b..a351c578b170 100644
--- a/drivers/gpu/drm/xe/xe_ggtt.c
+++ b/drivers/gpu/drm/xe/xe_ggtt.c
@@ -24,6 +24,7 @@
 #include "xe_gt_types.h"
 #include "xe_map.h"
 #include "xe_mmio.h"
+#include "xe_pat.h"
 #include "xe_pm.h"
 #include "xe_res_cursor.h"
 #include "xe_sriov.h"
@@ -115,7 +116,6 @@ struct xe_ggtt {
 	/** @size: Total usable size of this GGTT */
 	u64 size;
 
-#define XE_GGTT_FLAGS_64K BIT(0)
 	/**
 	 * @flags: Flags for this GGTT
 	 * Acceptable flags:
@@ -259,7 +259,7 @@ static u64 xe_ggtt_get_pte(struct xe_ggtt *ggtt, u64 addr)
 
 static void xe_ggtt_clear(struct xe_ggtt *ggtt, u64 start, u64 size)
 {
-	u16 pat_index = tile_to_xe(ggtt->tile)->pat.idx[XE_CACHE_WB];
+	u16 pat_index = xe_cache_pat_idx(tile_to_xe(ggtt->tile), XE_CACHE_WB);
 	u64 end = start + size - 1;
 	u64 scratch_pte;
 
@@ -724,7 +724,7 @@ static void xe_ggtt_map_bo(struct xe_ggtt *ggtt, struct xe_ggtt_node *node,
 void xe_ggtt_map_bo_unlocked(struct xe_ggtt *ggtt, struct xe_bo *bo)
 {
 	u16 cache_mode = bo->flags & XE_BO_FLAG_NEEDS_UC ? XE_CACHE_NONE : XE_CACHE_WB;
-	u16 pat_index = tile_to_xe(ggtt->tile)->pat.idx[cache_mode];
+	u16 pat_index = xe_cache_pat_idx(tile_to_xe(ggtt->tile), cache_mode);
 	u64 pte;
 
 	mutex_lock(&ggtt->lock);
@@ -841,7 +841,7 @@ static int __xe_ggtt_insert_bo_at(struct xe_ggtt *ggtt, struct xe_bo *bo,
 		bo->ggtt_node[tile_id] = NULL;
 	} else {
 		u16 cache_mode = bo->flags & XE_BO_FLAG_NEEDS_UC ? XE_CACHE_NONE : XE_CACHE_WB;
-		u16 pat_index = tile_to_xe(ggtt->tile)->pat.idx[cache_mode];
+		u16 pat_index = xe_cache_pat_idx(tile_to_xe(ggtt->tile), cache_mode);
 		u64 pte = ggtt->pt_ops->pte_encode_flags(bo, pat_index);
 
 		xe_ggtt_map_bo(ggtt, bo->ggtt_node[tile_id], bo, pte);
diff --git a/drivers/gpu/drm/xe/xe_gsc.c b/drivers/gpu/drm/xe/xe_gsc.c
index e5c234f3d795..0d13e357fb43 100644
--- a/drivers/gpu/drm/xe/xe_gsc.c
+++ b/drivers/gpu/drm/xe/xe_gsc.c
@@ -166,7 +166,7 @@ static int query_compatibility_version(struct xe_gsc *gsc)
 				     &rd_offset);
 	if (err) {
 		xe_gt_err(gt, "HuC: invalid GSC reply for version query (err=%d)\n", err);
-		return err;
+		goto out_bo;
 	}
 
 	compat->major = version_query_rd(xe, &bo->vmap, rd_offset, proj_major);
diff --git a/drivers/gpu/drm/xe/xe_gt_sriov_pf.c b/drivers/gpu/drm/xe/xe_gt_sriov_pf.c
index fb5c9101e275..7868056841b3 100644
--- a/drivers/gpu/drm/xe/xe_gt_sriov_pf.c
+++ b/drivers/gpu/drm/xe/xe_gt_sriov_pf.c
@@ -219,6 +219,7 @@ static void pf_restart(struct xe_gt *gt)
 
 	xe_gt_assert(gt, !xe_pm_runtime_suspended(xe));
 
+	xe_gt_sriov_pf_policy_restart(gt);
 	xe_gt_sriov_pf_config_restart(gt);
 	xe_gt_sriov_pf_control_restart(gt);
 
diff --git a/drivers/gpu/drm/xe/xe_gt_sriov_pf_config.c b/drivers/gpu/drm/xe/xe_gt_sriov_pf_config.c
index 2f376b5fb088..2c9b85b84b1b 100644
--- a/drivers/gpu/drm/xe/xe_gt_sriov_pf_config.c
+++ b/drivers/gpu/drm/xe/xe_gt_sriov_pf_config.c
@@ -285,6 +285,13 @@ static u32 encode_config_ggtt(u32 *cfg, const struct xe_gt_sriov_config *config,
 	return encode_ggtt(cfg, xe_ggtt_node_addr(node), xe_ggtt_node_size(node), details);
 }
 
+static bool custom_sched_priority(struct xe_gt *gt, u32 priority)
+{
+	return xe_gt_sriov_pf_policy_get_sched_if_idle_locked(gt) ?
+		priority != GUC_SCHED_PRIORITY_NORMAL :
+		priority != GUC_SCHED_PRIORITY_LOW;
+}
+
 static u32 encode_config_sched(struct xe_gt *gt, u32 *cfg, u32 n,
 			       const struct xe_gt_sriov_config *config)
 {
@@ -313,6 +320,11 @@ static u32 encode_config_sched(struct xe_gt *gt, u32 *cfg, u32 n,
 		cfg[n++] = config->preempt_timeout[0];
 	}
 
+	if (custom_sched_priority(gt, config->sched_priority)) {
+		cfg[n++] = PREP_GUC_KLV_TAG(VF_CFG_SCHED_PRIORITY);
+		cfg[n++] = config->sched_priority;
+	}
+
 	return n;
 }
 
@@ -1922,29 +1934,45 @@ static u64 pf_profile_fair_lmem(struct xe_gt *gt, unsigned int num_vfs)
 	return ALIGN_DOWN(fair, alignment);
 }
 
-static void __pf_show_provisioning_lmem(struct xe_gt *gt, unsigned int first_vf,
-					unsigned int num_vfs, bool provisioned)
+static void __pf_show_provisioned(struct xe_gt *gt, unsigned int first_vf,
+				  unsigned int num_vfs, bool provisioned,
+				  u32 (*get32)(struct xe_gt *, unsigned int),
+				  u64 (*get64)(struct xe_gt *, unsigned int),
+				  const char *what)
 {
 	unsigned int allvfs = 1 + xe_gt_sriov_pf_get_totalvfs(gt); /* PF plus VFs */
 	unsigned long *bitmap __free(bitmap) = bitmap_zalloc(allvfs, GFP_KERNEL);
 	unsigned int weight;
 	unsigned int n;
+	bool pf;
+
+	xe_gt_assert(gt, get32 || get64);
 
 	if (!bitmap)
 		return;
 
 	for (n = first_vf; n < first_vf + num_vfs; n++) {
-		if (!!pf_get_vf_config_lmem(gt, VFID(n)) == provisioned)
+		if ((get32 && (!!get32(gt, VFID(n)) == provisioned)) ||
+		    (get64 && (!!get64(gt, VFID(n)) == provisioned)))
 			bitmap_set(bitmap, n, 1);
 	}
 
+	pf = test_and_clear_bit(0, bitmap);
 	weight = bitmap_weight(bitmap, allvfs);
-	if (!weight)
+	if (!pf && !weight)
 		return;
 
-	xe_gt_sriov_info(gt, "VF%s%*pbl %s provisioned with VRAM\n",
-			 weight > 1 ? "s " : "", allvfs, bitmap,
-			 provisioned ? "already" : "not");
+	xe_gt_sriov_info(gt, "%s%s%s%s%*pbl %s provisioned with %s\n",
+			 pf ? "PF" : "", pf && weight ? " and " : "",
+			 weight ? "VF" : "", weight > 1 ? "s " : "",
+			 allvfs, bitmap, provisioned ? "already" : "not", what);
+}
+
+static void __pf_show_provisioning_lmem(struct xe_gt *gt, unsigned int first_vf,
+					unsigned int num_vfs, bool provisioned)
+{
+	__pf_show_provisioned(gt, first_vf, num_vfs, provisioned,
+			      NULL, pf_get_vf_config_lmem, "VRAM");
 }
 
 static void pf_show_all_provisioned_lmem(struct xe_gt *gt)
@@ -2078,6 +2106,17 @@ static u32 pf_get_exec_quantum(struct xe_gt *gt, unsigned int vfid)
 	return config->exec_quantum[0];
 }
 
+static bool pf_non_default_exec_quantum(struct xe_gt *gt, unsigned int vfid)
+{
+	struct xe_gt_sriov_config *config = pf_pick_vf_config(gt, vfid);
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(config->exec_quantum); i++)
+		if (config->exec_quantum[i])
+			return true;
+	return false;
+}
+
 /**
  * xe_gt_sriov_pf_config_set_exec_quantum_locked() - Configure PF/VF execution quantum.
  * @gt: the &xe_gt
@@ -2154,34 +2193,41 @@ u32 xe_gt_sriov_pf_config_get_exec_quantum(struct xe_gt *gt, unsigned int vfid)
 	return pf_get_exec_quantum(gt, vfid);
 }
 
-/**
- * xe_gt_sriov_pf_config_bulk_set_exec_quantum_locked() - Configure EQ for PF and VFs.
- * @gt: the &xe_gt to configure
- * @exec_quantum: requested execution quantum in milliseconds (0 is infinity)
- *
- * This function can only be called on PF with the master mutex hold.
- *
- * Return: 0 on success or a negative error code on failure.
- */
-int xe_gt_sriov_pf_config_bulk_set_exec_quantum_locked(struct xe_gt *gt, u32 exec_quantum)
+static int pf_bulk_set_exec_quantum(struct xe_gt *gt, u32 exec_quantum,
+				    unsigned int first_vf, unsigned int num_vfs)
 {
-	unsigned int totalvfs = xe_gt_sriov_pf_get_totalvfs(gt);
 	unsigned int n;
 	int err = 0;
 
 	lockdep_assert_held(xe_gt_sriov_pf_master_mutex(gt));
 
-	for (n = 0; n <= totalvfs; n++) {
+	for (n = first_vf; n < first_vf + num_vfs; n++) {
 		err = pf_provision_exec_quantum(gt, VFID(n), exec_quantum);
 		if (err)
 			break;
 	}
 
-	return pf_config_bulk_set_u32_done(gt, 0, 1 + totalvfs, exec_quantum,
+	return pf_config_bulk_set_u32_done(gt, first_vf, num_vfs, exec_quantum,
 					   pf_get_exec_quantum, "execution quantum",
 					   exec_quantum_unit, n, err);
 }
 
+/**
+ * xe_gt_sriov_pf_config_bulk_set_exec_quantum_locked() - Configure EQ for PF and VFs.
+ * @gt: the &xe_gt to configure
+ * @exec_quantum: requested execution quantum in milliseconds (0 is infinity)
+ *
+ * This function can only be called on PF with the master mutex hold.
+ *
+ * Return: 0 on success or a negative error code on failure.
+ */
+int xe_gt_sriov_pf_config_bulk_set_exec_quantum_locked(struct xe_gt *gt, u32 exec_quantum)
+{
+	unsigned int totalvfs = xe_gt_sriov_pf_get_totalvfs(gt);
+
+	return pf_bulk_set_exec_quantum(gt, exec_quantum, PFID, 1 + totalvfs);
+}
+
 static int pf_provision_groups_exec_quantums(struct xe_gt *gt, unsigned int vfid,
 					     const u32 *exec_quantums, u32 count)
 {
@@ -2293,6 +2339,17 @@ static u32 pf_get_preempt_timeout(struct xe_gt *gt, unsigned int vfid)
 	return config->preempt_timeout[0];
 }
 
+static bool pf_non_default_preempt_timeout(struct xe_gt *gt, unsigned int vfid)
+{
+	struct xe_gt_sriov_config *config = pf_pick_vf_config(gt, vfid);
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(config->preempt_timeout); i++)
+		if (config->preempt_timeout[i])
+			return true;
+	return false;
+}
+
 /**
  * xe_gt_sriov_pf_config_set_preempt_timeout_locked() - Configure PF/VF preemption timeout.
  * @gt: the &xe_gt
@@ -2368,34 +2425,41 @@ u32 xe_gt_sriov_pf_config_get_preempt_timeout(struct xe_gt *gt, unsigned int vfi
 	return pf_get_preempt_timeout(gt, vfid);
 }
 
-/**
- * xe_gt_sriov_pf_config_bulk_set_preempt_timeout_locked() - Configure PT for PF and VFs.
- * @gt: the &xe_gt to configure
- * @preempt_timeout: requested preemption timeout in microseconds (0 is infinity)
- *
- * This function can only be called on PF with the master mutex hold.
- *
- * Return: 0 on success or a negative error code on failure.
- */
-int xe_gt_sriov_pf_config_bulk_set_preempt_timeout_locked(struct xe_gt *gt, u32 preempt_timeout)
+static int pf_bulk_set_preempt_timeout(struct xe_gt *gt, u32 preempt_timeout,
+				       unsigned int first_vf, unsigned int num_vfs)
 {
-	unsigned int totalvfs = xe_gt_sriov_pf_get_totalvfs(gt);
 	unsigned int n;
 	int err = 0;
 
 	lockdep_assert_held(xe_gt_sriov_pf_master_mutex(gt));
 
-	for (n = 0; n <= totalvfs; n++) {
+	for (n = first_vf; n < first_vf + num_vfs; n++) {
 		err = pf_provision_preempt_timeout(gt, VFID(n), preempt_timeout);
 		if (err)
 			break;
 	}
 
-	return pf_config_bulk_set_u32_done(gt, 0, 1 + totalvfs, preempt_timeout,
+	return pf_config_bulk_set_u32_done(gt, first_vf, num_vfs, preempt_timeout,
 					   pf_get_preempt_timeout, "preemption timeout",
 					   preempt_timeout_unit, n, err);
 }
 
+/**
+ * xe_gt_sriov_pf_config_bulk_set_preempt_timeout_locked() - Configure PT for PF and VFs.
+ * @gt: the &xe_gt to configure
+ * @preempt_timeout: requested preemption timeout in microseconds (0 is infinity)
+ *
+ * This function can only be called on PF with the master mutex hold.
+ *
+ * Return: 0 on success or a negative error code on failure.
+ */
+int xe_gt_sriov_pf_config_bulk_set_preempt_timeout_locked(struct xe_gt *gt, u32 preempt_timeout)
+{
+	unsigned int totalvfs = xe_gt_sriov_pf_get_totalvfs(gt);
+
+	return pf_bulk_set_preempt_timeout(gt, preempt_timeout, PFID, 1 + totalvfs);
+}
+
 static int pf_provision_groups_preempt_timeouts(struct xe_gt *gt, unsigned int vfid,
 						const u32 *preempt_timeouts, u32 count)
 {
@@ -2500,7 +2564,7 @@ static int pf_provision_sched_priority(struct xe_gt *gt, unsigned int vfid, u32
 	return 0;
 }
 
-static int pf_get_sched_priority(struct xe_gt *gt, unsigned int vfid)
+static u32 pf_get_sched_priority(struct xe_gt *gt, unsigned int vfid)
 {
 	struct xe_gt_sriov_config *config = pf_pick_vf_config(gt, vfid);
 
@@ -2550,6 +2614,35 @@ u32 xe_gt_sriov_pf_config_get_sched_priority(struct xe_gt *gt, unsigned int vfid
 	return priority;
 }
 
+/**
+ * xe_gt_sriov_pf_config_force_sched_priority_locked() - Force update scheduling priority.
+ * @gt: the &xe_gt
+ * @priority: new scheduling priority to set
+ *
+ * This function allows to update cached values of the scheduling priorities of all
+ * VFs (and PF) as result of applying the `GUC_KLV_VGT_POLICY_SCHED_IF_IDLE`_ policy.
+ *
+ * This function can only be called on PF.
+ */
+void xe_gt_sriov_pf_config_force_sched_priority_locked(struct xe_gt *gt, u32 priority)
+{
+	unsigned int total_vfs = xe_gt_sriov_pf_get_totalvfs(gt);
+	struct xe_gt_sriov_config *config;
+	unsigned int n;
+
+	xe_gt_assert(gt, IS_SRIOV_PF(gt_to_xe(gt)));
+	lockdep_assert_held(xe_gt_sriov_pf_master_mutex(gt));
+
+	for (n = 0; n <= total_vfs; n++) {
+		config = pf_pick_vf_config(gt, VFID(n));
+		config->sched_priority = priority;
+	}
+
+	pf_config_bulk_set_u32_done(gt, PFID, 1 + total_vfs, priority,
+				    pf_get_sched_priority, "scheduling priority",
+				    sched_priority_unit, n, 0);
+}
+
 static void pf_reset_config_sched(struct xe_gt *gt, struct xe_gt_sriov_config *config)
 {
 	int i;
@@ -2562,6 +2655,104 @@ static void pf_reset_config_sched(struct xe_gt *gt, struct xe_gt_sriov_config *c
 	}
 }
 
+static bool pf_non_default_sched(struct xe_gt *gt, unsigned int vfid)
+{
+	return pf_non_default_exec_quantum(gt, vfid) ||
+	       pf_non_default_preempt_timeout(gt, vfid) ||
+	       custom_sched_priority(gt, pf_get_sched_priority(gt, vfid));
+}
+
+static void __pf_show_provisioned_sched(struct xe_gt *gt, unsigned int first_vf,
+					unsigned int num_vfs, bool provisioned)
+{
+	__pf_show_provisioned(gt, first_vf, num_vfs, provisioned,
+			      pf_get_exec_quantum, NULL, "EQ");
+	__pf_show_provisioned(gt, first_vf, num_vfs, provisioned,
+			      pf_get_preempt_timeout, NULL, "PT");
+
+	/* we only care about non-default priorities */
+	if (provisioned)
+		__pf_show_provisioned(gt, first_vf, num_vfs, true,
+				      pf_get_sched_priority, NULL, "PRIORITY");
+}
+
+static void pf_show_all_provisioned_sched(struct xe_gt *gt)
+{
+	__pf_show_provisioned_sched(gt, PFID, 1 + xe_gt_sriov_pf_get_totalvfs(gt), true);
+}
+
+static void pf_show_unprovisioned_sched(struct xe_gt *gt, unsigned int num_vfs)
+{
+	__pf_show_provisioned_sched(gt, PFID, 1 + num_vfs, false);
+}
+
+static bool pf_needs_provision_sched(struct xe_gt *gt, unsigned int num_vfs)
+{
+	unsigned int vfid;
+
+	for (vfid = PFID; vfid <= PFID + num_vfs; vfid++) {
+		if (pf_non_default_sched(gt, vfid)) {
+			pf_show_all_provisioned_sched(gt);
+			pf_show_unprovisioned_sched(gt, num_vfs);
+			return false;
+		}
+	}
+
+	if (xe_gt_sriov_pf_policy_get_sched_if_idle_locked(gt)) {
+		pf_show_all_provisioned_sched(gt);
+		pf_show_unprovisioned_sched(gt, num_vfs);
+		return false;
+	}
+
+	pf_show_all_provisioned_sched(gt);
+	return true;
+}
+
+/* With 16ms EQ/PT GuC should be able to handle up to 63 VFs within 2s */
+#define XE_FAIR_EXEC_QUANTUM_MS		16
+#define XE_FAIR_PREEMPT_TIMEOUT_US	16000
+#define XE_FAIR_SCHED_PRIORITY		GUC_SCHED_PRIORITY_LOW
+#define XE_ADMIN_PF_SCHED_PRIORITY	GUC_SCHED_PRIORITY_HIGH
+
+/**
+ * xe_gt_sriov_pf_config_set_fair_sched() - Provision PF and VFs with fair scheduling.
+ * @gt: the &xe_gt
+ * @num_vfs: number of VFs to provision (can't be 0)
+ *
+ * This function can only be called on PF.
+ *
+ * Return: 0 on success or a negative error code on failure.
+ */
+int xe_gt_sriov_pf_config_set_fair_sched(struct xe_gt *gt, unsigned int num_vfs)
+{
+	int result = 0;
+	int err;
+
+	xe_gt_assert(gt, num_vfs);
+	xe_gt_assert(gt, XE_FAIR_EXEC_QUANTUM_MS);
+	xe_gt_assert(gt, XE_FAIR_PREEMPT_TIMEOUT_US);
+
+	guard(mutex)(xe_gt_sriov_pf_master_mutex(gt));
+
+	if (!pf_needs_provision_sched(gt, num_vfs))
+		return 0;
+
+	err = pf_bulk_set_exec_quantum(gt, XE_FAIR_EXEC_QUANTUM_MS, PFID, 1 + num_vfs);
+	result = result ?: err;
+	err = pf_bulk_set_preempt_timeout(gt, XE_FAIR_PREEMPT_TIMEOUT_US, PFID, 1 + num_vfs);
+	result = result ?: err;
+
+	xe_gt_assert(gt, XE_FAIR_SCHED_PRIORITY == GUC_SCHED_PRIORITY_LOW);
+	xe_gt_assert(gt, !xe_gt_sriov_pf_policy_get_sched_if_idle_locked(gt));
+
+	if (xe_sriov_pf_admin_only(gt_to_xe(gt))) {
+		err = pf_provision_sched_priority(gt, PFID, XE_ADMIN_PF_SCHED_PRIORITY);
+		result = result ?: err;
+	}
+
+	return result;
+}
+
 static int pf_provision_threshold(struct xe_gt *gt, unsigned int vfid,
 				  enum xe_guc_klv_threshold_index index, u32 value)
 {
@@ -2838,6 +3029,9 @@ static int pf_validate_vf_config(struct xe_gt *gt, unsigned int vfid)
 		valid_all = valid_all && valid_lmem;
 	}
 
+	/* also check optional EQ/PT/PRIO */
+	valid_any = valid_any || pf_non_default_sched(gt, vfid);
+
 	return valid_all ? 0 : valid_any ? -ENOKEY : -ENODATA;
 }
 
diff --git a/drivers/gpu/drm/xe/xe_gt_sriov_pf_config.h b/drivers/gpu/drm/xe/xe_gt_sriov_pf_config.h
index 4a004ecd6140..2ec62c12ad5c 100644
--- a/drivers/gpu/drm/xe/xe_gt_sriov_pf_config.h
+++ b/drivers/gpu/drm/xe/xe_gt_sriov_pf_config.h
@@ -71,12 +71,14 @@ int xe_gt_sriov_pf_config_set_groups_preempt_timeouts(struct xe_gt *gt, unsigned
 
 u32 xe_gt_sriov_pf_config_get_sched_priority(struct xe_gt *gt, unsigned int vfid);
 int xe_gt_sriov_pf_config_set_sched_priority(struct xe_gt *gt, unsigned int vfid, u32 priority);
+void xe_gt_sriov_pf_config_force_sched_priority_locked(struct xe_gt *gt, u32 priority);
 
 u32 xe_gt_sriov_pf_config_get_threshold(struct xe_gt *gt, unsigned int vfid,
 					enum xe_guc_klv_threshold_index index);
 int xe_gt_sriov_pf_config_set_threshold(struct xe_gt *gt, unsigned int vfid,
 					enum xe_guc_klv_threshold_index index, u32 value);
 
+int xe_gt_sriov_pf_config_set_fair_sched(struct xe_gt *gt, unsigned int num_vfs);
 int xe_gt_sriov_pf_config_set_fair(struct xe_gt *gt, unsigned int vfid, unsigned int num_vfs);
 int xe_gt_sriov_pf_config_sanitize(struct xe_gt *gt, unsigned int vfid, long timeout);
 int xe_gt_sriov_pf_config_release(struct xe_gt *gt, unsigned int vfid, bool force);
diff --git a/drivers/gpu/drm/xe/xe_gt_sriov_pf_policy.c b/drivers/gpu/drm/xe/xe_gt_sriov_pf_policy.c
index 848e24926ecd..e8458d63742d 100644
--- a/drivers/gpu/drm/xe/xe_gt_sriov_pf_policy.c
+++ b/drivers/gpu/drm/xe/xe_gt_sriov_pf_policy.c
@@ -8,6 +8,7 @@
 #include "abi/guc_actions_sriov_abi.h"
 
 #include "xe_gt.h"
+#include "xe_gt_sriov_pf_config.h"
 #include "xe_gt_sriov_pf_helpers.h"
 #include "xe_gt_sriov_pf_policy.h"
 #include "xe_gt_sriov_printk.h"
@@ -16,7 +17,6 @@
 #include "xe_guc_ct.h"
 #include "xe_guc_klv_helpers.h"
 #include "xe_guc_submit.h"
-#include "xe_pm.h"
 
 /*
  * Return: number of KLVs that were successfully parsed and saved,
@@ -67,6 +67,15 @@ static int pf_push_policy_buf_klvs(struct xe_gt *gt, u32 num_klvs,
 		return err;
 	}
 
+	if (IS_ENABLED(CONFIG_DRM_XE_DEBUG_SRIOV)) {
+		struct drm_printer p = xe_gt_dbg_printer(gt);
+		void *klvs = xe_guc_buf_cpu_ptr(buf);
+
+		xe_gt_sriov_dbg(gt, "pushed policy update with %u KLV%s:\n",
+				num_klvs, str_plural(num_klvs));
+		xe_guc_klv_print(klvs, num_dwords, &p);
+	}
+
 	return 0;
 }
 
@@ -153,33 +162,14 @@ static int pf_update_policy_u32(struct xe_gt *gt, u16 key, u32 *policy, u32 valu
 	return 0;
 }
 
-static void pf_bulk_reset_sched_priority(struct xe_gt *gt, u32 priority)
-{
-	unsigned int total_vfs = 1 + xe_gt_sriov_pf_get_totalvfs(gt);
-	unsigned int n;
-
-	xe_gt_assert(gt, IS_SRIOV_PF(gt_to_xe(gt)));
-	lockdep_assert_held(xe_gt_sriov_pf_master_mutex(gt));
-
-	for (n = 0; n < total_vfs; n++)
-		gt->sriov.pf.vfs[n].config.sched_priority = priority;
-}
-
 static int pf_provision_sched_if_idle(struct xe_gt *gt, bool enable)
 {
-	int err;
-
 	xe_gt_assert(gt, IS_SRIOV_PF(gt_to_xe(gt)));
 	lockdep_assert_held(xe_gt_sriov_pf_master_mutex(gt));
 
-	err = pf_update_policy_bool(gt, GUC_KLV_VGT_POLICY_SCHED_IF_IDLE_KEY,
-				    &gt->sriov.pf.policy.guc.sched_if_idle,
-				    enable);
-
-	if (!err)
-		pf_bulk_reset_sched_priority(gt, enable ? GUC_SCHED_PRIORITY_NORMAL :
-					     GUC_SCHED_PRIORITY_LOW);
-	return err;
+	return pf_update_policy_bool(gt, GUC_KLV_VGT_POLICY_SCHED_IF_IDLE_KEY,
+				     &gt->sriov.pf.policy.guc.sched_if_idle,
+				     enable);
 }
 
 static int pf_reprovision_sched_if_idle(struct xe_gt *gt)
@@ -187,6 +177,9 @@ static int pf_reprovision_sched_if_idle(struct xe_gt *gt)
 	xe_gt_assert(gt, IS_SRIOV_PF(gt_to_xe(gt)));
 	lockdep_assert_held(xe_gt_sriov_pf_master_mutex(gt));
 
+	if (!gt->sriov.pf.policy.guc.sched_if_idle)
+		return 0;
+
 	return pf_provision_sched_if_idle(gt, gt->sriov.pf.policy.guc.sched_if_idle);
 }
 
@@ -199,7 +192,7 @@ static void pf_sanitize_sched_if_idle(struct xe_gt *gt)
 }
 
 /**
- * xe_gt_sriov_pf_policy_set_sched_if_idle - Control the 'sched_if_idle' policy.
+ * xe_gt_sriov_pf_policy_set_sched_if_idle_locked() - Control the 'sched_if_idle' policy.
  * @gt: the &xe_gt where to apply the policy
  * @enable: the value of the 'sched_if_idle' policy
  *
@@ -207,15 +200,60 @@ static void pf_sanitize_sched_if_idle(struct xe_gt *gt)
  *
  * Return: 0 on success or a negative error code on failure.
  */
-int xe_gt_sriov_pf_policy_set_sched_if_idle(struct xe_gt *gt, bool enable)
+int xe_gt_sriov_pf_policy_set_sched_if_idle_locked(struct xe_gt *gt, bool enable)
 {
+	u32 priority;
 	int err;
 
-	mutex_lock(xe_gt_sriov_pf_master_mutex(gt));
+	lockdep_assert_held(xe_gt_sriov_pf_master_mutex(gt));
+
 	err = pf_provision_sched_if_idle(gt, enable);
-	mutex_unlock(xe_gt_sriov_pf_master_mutex(gt));
+	if (err)
+		return err;
 
-	return err;
+	/*
+	 * As of GuC 70.12 a change of this policy impacts individual configs
+	 * of all VFs. See `GUC_KLV_VGT_POLICY_SCHED_IF_IDLE`_ for details.
+	 */
+	xe_gt_assert(gt, GUC_FIRMWARE_VER_AT_LEAST(&gt->uc.guc, 70, 12));
+
+	priority = enable ? GUC_SCHED_PRIORITY_NORMAL : GUC_SCHED_PRIORITY_LOW;
+	xe_gt_sriov_pf_config_force_sched_priority_locked(gt, priority);
+
+	return 0;
+}
+
+/**
+ * xe_gt_sriov_pf_policy_set_sched_if_idle() - Control the 'sched_if_idle' policy.
+ * @gt: the &xe_gt where to apply the policy
+ * @enable: the value of the 'sched_if_idle' policy
+ *
+ * This function can only be called on PF.
+ *
+ * Return: 0 on success or a negative error code on failure.
+ */
+int xe_gt_sriov_pf_policy_set_sched_if_idle(struct xe_gt *gt, bool enable)
+{
+	xe_gt_assert(gt, IS_SRIOV_PF(gt_to_xe(gt)));
+	guard(mutex)(xe_gt_sriov_pf_master_mutex(gt));
+
+	return xe_gt_sriov_pf_policy_set_sched_if_idle_locked(gt, enable);
+}
+
+/**
+ * xe_gt_sriov_pf_policy_get_sched_if_idle_locked() - Retrieve value of 'sched_if_idle' policy.
+ * @gt: the &xe_gt where to read the policy from
+ *
+ * This function can only be called on PF.
+ *
+ * Return: last value of 'sched_if_idle' policy applied.
+ */
+bool xe_gt_sriov_pf_policy_get_sched_if_idle_locked(struct xe_gt *gt)
+{
+	xe_gt_assert(gt, IS_SRIOV_PF(gt_to_xe(gt)));
+	lockdep_assert_held(xe_gt_sriov_pf_master_mutex(gt));
+
+	return gt->sriov.pf.policy.guc.sched_if_idle;
 }
 
 /**
@@ -228,15 +266,10 @@ int xe_gt_sriov_pf_policy_set_sched_if_idle(struct xe_gt *gt, bool enable)
  */
 bool xe_gt_sriov_pf_policy_get_sched_if_idle(struct xe_gt *gt)
 {
-	bool enable;
-
 	xe_gt_assert(gt, IS_SRIOV_PF(gt_to_xe(gt)));
+	guard(mutex)(xe_gt_sriov_pf_master_mutex(gt));
 
-	mutex_lock(xe_gt_sriov_pf_master_mutex(gt));
-	enable = gt->sriov.pf.policy.guc.sched_if_idle;
-	mutex_unlock(xe_gt_sriov_pf_master_mutex(gt));
-
-	return enable;
+	return xe_gt_sriov_pf_policy_get_sched_if_idle_locked(gt);
 }
 
 static int pf_provision_reset_engine(struct xe_gt *gt, bool enable)
@@ -253,6 +286,9 @@ static int pf_reprovision_reset_engine(struct xe_gt *gt)
 	xe_gt_assert(gt, IS_SRIOV_PF(gt_to_xe(gt)));
 	lockdep_assert_held(xe_gt_sriov_pf_master_mutex(gt));
 
+	if (!gt->sriov.pf.policy.guc.reset_engine)
+		return 0;
+
 	return pf_provision_reset_engine(gt, gt->sriov.pf.policy.guc.reset_engine);
 }
 
@@ -319,6 +355,9 @@ static int pf_reprovision_sample_period(struct xe_gt *gt)
 	xe_gt_assert(gt, IS_SRIOV_PF(gt_to_xe(gt)));
 	lockdep_assert_held(xe_gt_sriov_pf_master_mutex(gt));
 
+	if (!gt->sriov.pf.policy.guc.sample_period)
+		return 0;
+
 	return pf_provision_sample_period(gt, gt->sriov.pf.policy.guc.sample_period);
 }
 
@@ -689,30 +728,23 @@ void xe_gt_sriov_pf_policy_sanitize(struct xe_gt *gt)
 }
 
 /**
- * xe_gt_sriov_pf_policy_reprovision - Reprovision (and optionally reset) policy settings.
+ * xe_gt_sriov_pf_policy_restart() - Reprovision policy settings.
  * @gt: the &xe_gt
- * @reset: if true will reprovision using default values instead of latest
  *
  * This function can only be called on PF.
  *
  * Return: 0 on success or a negative error code on failure.
  */
-int xe_gt_sriov_pf_policy_reprovision(struct xe_gt *gt, bool reset)
+int xe_gt_sriov_pf_policy_restart(struct xe_gt *gt)
 {
 	int err = 0;
 
-	xe_pm_runtime_get_noresume(gt_to_xe(gt));
+	guard(mutex)(xe_gt_sriov_pf_master_mutex(gt));
 
-	mutex_lock(xe_gt_sriov_pf_master_mutex(gt));
-	if (reset)
-		pf_sanitize_guc_policies(gt);
 	err |= pf_reprovision_sched_if_idle(gt);
 	err |= pf_reprovision_reset_engine(gt);
 	err |= pf_reprovision_sample_period(gt);
 	err |= pf_reprovision_sched_groups(gt);
-	mutex_unlock(xe_gt_sriov_pf_master_mutex(gt));
-
-	xe_pm_runtime_put(gt_to_xe(gt));
 
 	return err ? -ENXIO : 0;
 }
diff --git a/drivers/gpu/drm/xe/xe_gt_sriov_pf_policy.h b/drivers/gpu/drm/xe/xe_gt_sriov_pf_policy.h
index bd73aa58f9ca..d667d66897b1 100644
--- a/drivers/gpu/drm/xe/xe_gt_sriov_pf_policy.h
+++ b/drivers/gpu/drm/xe/xe_gt_sriov_pf_policy.h
@@ -14,7 +14,9 @@ struct drm_printer;
 struct xe_gt;
 
 int xe_gt_sriov_pf_policy_set_sched_if_idle(struct xe_gt *gt, bool enable);
+int xe_gt_sriov_pf_policy_set_sched_if_idle_locked(struct xe_gt *gt, bool enable);
 bool xe_gt_sriov_pf_policy_get_sched_if_idle(struct xe_gt *gt);
+bool xe_gt_sriov_pf_policy_get_sched_if_idle_locked(struct xe_gt *gt);
 int xe_gt_sriov_pf_policy_set_reset_engine(struct xe_gt *gt, bool enable);
 bool xe_gt_sriov_pf_policy_get_reset_engine(struct xe_gt *gt);
 int xe_gt_sriov_pf_policy_set_sample_period(struct xe_gt *gt, u32 value);
@@ -29,7 +31,7 @@ bool xe_gt_sriov_pf_policy_sched_groups_enabled(struct xe_gt *gt);
 
 void xe_gt_sriov_pf_policy_init(struct xe_gt *gt);
 void xe_gt_sriov_pf_policy_sanitize(struct xe_gt *gt);
-int xe_gt_sriov_pf_policy_reprovision(struct xe_gt *gt, bool reset);
+int xe_gt_sriov_pf_policy_restart(struct xe_gt *gt);
 int xe_gt_sriov_pf_policy_print(struct xe_gt *gt, struct drm_printer *p);
 
 #endif
diff --git a/drivers/gpu/drm/xe/xe_gt_sriov_pf_types.h b/drivers/gpu/drm/xe/xe_gt_sriov_pf_types.h
index 667b8310478d..6296483c44ec 100644
--- a/drivers/gpu/drm/xe/xe_gt_sriov_pf_types.h
+++ b/drivers/gpu/drm/xe/xe_gt_sriov_pf_types.h
@@ -49,7 +49,6 @@ struct xe_gt_sriov_pf_workers {
  * @service: service data.
  * @control: control data.
  * @policy: policy data.
- * @migration: migration data.
  * @spare: PF-only provisioning configuration.
  * @vfs: metadata for all VFs.
  */
diff --git a/drivers/gpu/drm/xe/xe_gt_stats.c b/drivers/gpu/drm/xe/xe_gt_stats.c
index 59b3b23a54c8..789397514f3e 100644
--- a/drivers/gpu/drm/xe/xe_gt_stats.c
+++ b/drivers/gpu/drm/xe/xe_gt_stats.c
@@ -9,6 +9,47 @@
 #include "xe_device.h"
 #include "xe_gt_stats.h"
 
+/**
+ * DOC: Xe GT Statistics
+ *
+ * Overview
+ * ========
+ *
+ * The Xe driver exposes per-GT statistics through the debugfs filesystem at::
+ *
+ *   /sys/kernel/debug/dri/<device>/gt<id>/stats
+ *
+ * This interface requires the kernel to be built with ``CONFIG_DEBUG_FS=y``.
+ *
+ * Reading statistics
+ * ==================
+ *
+ * Reading the file prints all available statistics, one per line, in
+ * ``name: value`` format::
+ *
+ *   $ cat /sys/kernel/debug/dri/0/gt0/stats
+ *   svm_pagefault_count: 0
+ *   tlb_inval_count: 1234
+ *   ...
+ *
+ * All values are 64-bit unsigned integers aggregated across all CPUs.
+ * Counters accumulate since the driver was loaded or since the last explicit
+ * reset.  Timing counters use microseconds as their unit; data volume counters
+ * use KiB.
+ *
+ * Resetting statistics
+ * ====================
+ *
+ * Writing a boolean true value to the file resets all counters to zero::
+ *
+ *   echo 1 > /sys/kernel/debug/dri/0/gt0/stats
+ *
+ * Any value accepted by ``kstrtobool()`` (e.g. ``1``, ``y``, ``yes``,
+ * ``on``) triggers the reset.  Resetting while the GPU is active may yield
+ * unpredictable intermediate values; it is recommended to reset only when
+ * the GPU is idle.
+ */
+
 static void xe_gt_stats_fini(struct drm_device *drm, void *arg)
 {
 	struct xe_gt *gt = arg;
diff --git a/drivers/gpu/drm/xe/xe_gt_stats_types.h b/drivers/gpu/drm/xe/xe_gt_stats_types.h
index 081c787ddcb6..425491bed6c4 100644
--- a/drivers/gpu/drm/xe/xe_gt_stats_types.h
+++ b/drivers/gpu/drm/xe/xe_gt_stats_types.h
@@ -8,6 +8,124 @@
 
 #include <linux/types.h>
 
+/**
+ * enum xe_gt_stats_id - GT statistics identifiers
+ * @XE_GT_STATS_ID_SVM_PAGEFAULT_COUNT: Total SVM page faults handled.
+ * @XE_GT_STATS_ID_TLB_INVAL: Total GPU Translation Lookaside Buffer (TLB)
+ *   invalidations issued.
+ * @XE_GT_STATS_ID_SVM_TLB_INVAL_COUNT: TLB invalidations issued during SVM
+ *   page-fault handling.
+ * @XE_GT_STATS_ID_SVM_TLB_INVAL_US: Cumulative time (µs) waiting for TLB
+ *   invalidations during SVM page-fault handling.
+ *
+ * @XE_GT_STATS_ID_VMA_PAGEFAULT_COUNT: Buffer-object (non-SVM) page faults
+ *   handled.
+ * @XE_GT_STATS_ID_VMA_PAGEFAULT_KB: Size (KiB) of VMAs involved in
+ *   buffer-object page fault handling.
+ * @XE_GT_STATS_ID_INVALID_PREFETCH_PAGEFAULT_COUNT: GPU prefetch faults for
+ *   addresses with no valid backing.
+ *
+ * @XE_GT_STATS_ID_SVM_4K_PAGEFAULT_COUNT: SVM page faults resolved by
+ *   mapping 4K pages.
+ * @XE_GT_STATS_ID_SVM_64K_PAGEFAULT_COUNT: SVM page faults resolved by
+ *   mapping 64K pages.
+ * @XE_GT_STATS_ID_SVM_2M_PAGEFAULT_COUNT: SVM page faults resolved by
+ *   mapping 2M pages.
+ * @XE_GT_STATS_ID_SVM_4K_VALID_PAGEFAULT_COUNT: Valid SVM page faults
+ *   at 4K page size, where the GPU mapping was already valid — resolved without
+ *   creating new mappings.
+ * @XE_GT_STATS_ID_SVM_64K_VALID_PAGEFAULT_COUNT: Valid SVM page faults at 64K
+ *   page size.
+ * @XE_GT_STATS_ID_SVM_2M_VALID_PAGEFAULT_COUNT: Valid SVM page faults at 2M
+ *   page size.
+ * @XE_GT_STATS_ID_SVM_4K_PAGEFAULT_US: Cumulative time (µs) handling 4K SVM
+ *   page faults.
+ * @XE_GT_STATS_ID_SVM_64K_PAGEFAULT_US: Cumulative time (µs) handling 64K
+ *   SVM page faults.
+ * @XE_GT_STATS_ID_SVM_2M_PAGEFAULT_US: Cumulative time (µs) handling 2M SVM
+ *   page faults.
+ *
+ * @XE_GT_STATS_ID_SVM_4K_MIGRATE_COUNT: 4K pages moved from CPU to device
+ *   memory.
+ * @XE_GT_STATS_ID_SVM_64K_MIGRATE_COUNT: 64K pages moved from CPU to device
+ *   memory.
+ * @XE_GT_STATS_ID_SVM_2M_MIGRATE_COUNT: 2M pages moved from CPU to device
+ *   memory.
+ * @XE_GT_STATS_ID_SVM_4K_MIGRATE_US: Cumulative time (µs) moving 4K pages
+ *   from CPU to device memory.
+ * @XE_GT_STATS_ID_SVM_64K_MIGRATE_US: Cumulative time (µs) moving 64K pages
+ *   from CPU to device memory.
+ * @XE_GT_STATS_ID_SVM_2M_MIGRATE_US: Cumulative time (µs) moving 2M pages
+ *   from CPU to device memory.
+ *
+ * @XE_GT_STATS_ID_SVM_DEVICE_COPY_US: Cumulative time (µs) for memory copies to
+ *   device, across all page sizes.
+ * @XE_GT_STATS_ID_SVM_4K_DEVICE_COPY_US: Cumulative time (µs) for memory copies
+ *   of 4K pages to device.
+ * @XE_GT_STATS_ID_SVM_64K_DEVICE_COPY_US: Cumulative time (µs) for memory
+ *   copies of 64K pages to device.
+ * @XE_GT_STATS_ID_SVM_2M_DEVICE_COPY_US: Cumulative time (µs) for memory copies
+ *   of 2M pages to device.
+ * @XE_GT_STATS_ID_SVM_CPU_COPY_US: Cumulative time (µs) for memory copies to
+ *   CPU, across all page sizes.
+ * @XE_GT_STATS_ID_SVM_4K_CPU_COPY_US: Cumulative time (µs) for memory copies of
+ *   4K pages to CPU.
+ * @XE_GT_STATS_ID_SVM_64K_CPU_COPY_US: Cumulative time (µs) for memory copies
+ *   of 64K pages to CPU.
+ * @XE_GT_STATS_ID_SVM_2M_CPU_COPY_US: Cumulative time (µs) for memory copies of
+ *   2M pages to CPU.
+ * @XE_GT_STATS_ID_SVM_DEVICE_COPY_KB: Data (KiB) copied to device across all
+ *   page sizes.
+ * @XE_GT_STATS_ID_SVM_4K_DEVICE_COPY_KB: Data (KiB) copied to device for 4K
+ *   pages.
+ * @XE_GT_STATS_ID_SVM_64K_DEVICE_COPY_KB: Data (KiB) copied to device for
+ *   64K pages.
+ * @XE_GT_STATS_ID_SVM_2M_DEVICE_COPY_KB: Data (KiB) copied to device for 2M
+ *   pages.
+ * @XE_GT_STATS_ID_SVM_CPU_COPY_KB: Data (KiB) copied to CPU across all page
+ *   sizes.
+ * @XE_GT_STATS_ID_SVM_4K_CPU_COPY_KB: Data (KiB) copied to CPU for 4K pages.
+ * @XE_GT_STATS_ID_SVM_64K_CPU_COPY_KB: Data (KiB) copied to CPU for 64K pages.
+ * @XE_GT_STATS_ID_SVM_2M_CPU_COPY_KB: Data (KiB) copied to CPU for 2M pages.
+ *
+ * @XE_GT_STATS_ID_SVM_4K_GET_PAGES_US: Cumulative time (µs) getting CPU
+ *   memory pages for GPU access at 4K page size.
+ * @XE_GT_STATS_ID_SVM_64K_GET_PAGES_US: Cumulative time (µs) getting CPU
+ *   memory pages for GPU access at 64K page size.
+ * @XE_GT_STATS_ID_SVM_2M_GET_PAGES_US: Cumulative time (µs) getting CPU
+ *   memory pages for GPU access at 2M page size.
+ * @XE_GT_STATS_ID_SVM_4K_BIND_US: Cumulative time (µs) binding 4K pages
+ *   into the GPU page table.
+ * @XE_GT_STATS_ID_SVM_64K_BIND_US: Cumulative time (µs) binding 64K pages
+ *   into the GPU page table.
+ * @XE_GT_STATS_ID_SVM_2M_BIND_US: Cumulative time (µs) binding 2M pages
+ *   into the GPU page table.
+ *
+ * @XE_GT_STATS_ID_HW_ENGINE_GROUP_SUSPEND_LR_QUEUE_COUNT: Times the
+ *   scheduler preempted a long-running (LR) GPU exec queue.
+ * @XE_GT_STATS_ID_HW_ENGINE_GROUP_SKIP_LR_QUEUE_COUNT: Times the scheduler
+ *   skipped suspend because the system was idle.
+ * @XE_GT_STATS_ID_HW_ENGINE_GROUP_WAIT_DMA_QUEUE_COUNT: Times the driver
+ *   stalled waiting for prior GPU work to complete before scheduling more.
+ * @XE_GT_STATS_ID_HW_ENGINE_GROUP_SUSPEND_LR_QUEUE_US: Cumulative time
+ *   (µs) spent preempting long-running (LR) GPU exec queues.
+ * @XE_GT_STATS_ID_HW_ENGINE_GROUP_WAIT_DMA_QUEUE_US: Cumulative time (µs)
+ *   stalled waiting for prior GPU work to complete.
+ *
+ * @XE_GT_STATS_ID_PRL_4K_ENTRY_COUNT: 4K-page entries from the page reclaim
+ *   list that were processed.
+ * @XE_GT_STATS_ID_PRL_64K_ENTRY_COUNT: 64K-page entries from the page reclaim
+ *   list that were processed.
+ * @XE_GT_STATS_ID_PRL_2M_ENTRY_COUNT: 2M-page entries from the page reclaim
+ *   list that were processed.
+ * @XE_GT_STATS_ID_PRL_ISSUED_COUNT: Times a page reclamation was issued.
+ * @XE_GT_STATS_ID_PRL_ABORTED_COUNT: Times the page reclaim process was
+ *   aborted.
+ *
+ * @__XE_GT_STATS_NUM_IDS: Number of valid IDs; not a real counter.
+ *
+ * See Documentation/gpu/xe/xe_gt_stats.rst.
+ */
 enum xe_gt_stats_id {
 	XE_GT_STATS_ID_SVM_PAGEFAULT_COUNT,
 	XE_GT_STATS_ID_TLB_INVAL,
diff --git a/drivers/gpu/drm/xe/xe_gt_types.h b/drivers/gpu/drm/xe/xe_gt_types.h
index 8b55cf25a75f..7351aadd238e 100644
--- a/drivers/gpu/drm/xe/xe_gt_types.h
+++ b/drivers/gpu/drm/xe/xe_gt_types.h
@@ -136,7 +136,7 @@ struct xe_gt {
 		/** @info.gmdid: raw GMD_ID value from hardware */
 		u32 gmdid;
 		/**
-		 * @multi_queue_engine_class_mask: Bitmask of engine classes with
+		 * @info.multi_queue_engine_class_mask: Bitmask of engine classes with
 		 * multi queue support enabled.
 		 */
 		u16 multi_queue_engine_class_mask;
@@ -355,7 +355,7 @@ struct xe_gt {
 	/** @user_engines: engines present in GT and available to userspace */
 	struct {
 		/**
-		 * @user_engines.mask: like @info->engine_mask, but take in
+		 * @user_engines.mask: like @info.engine_mask, but take in
 		 * consideration only engines available to userspace
 		 */
 		u64 mask;
diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
index ccebb437e37f..e762eada21db 100644
--- a/drivers/gpu/drm/xe/xe_guc.c
+++ b/drivers/gpu/drm/xe/xe_guc.c
@@ -780,6 +780,14 @@ int xe_guc_init(struct xe_guc *guc)
 	if (GUC_SUBMIT_VER(guc) < MAKE_GUC_VER(1, 14, 0))
 		xe->info.has_page_reclaim_hw_assist = false;
 
+	/* Disable indirect_ring_state if missing GuC 70.53+ WA 14025515070. */
+	if (gt->info.has_indirect_ring_state &&
+	    XE_GT_WA(gt, 14025515070) &&
+	    GUC_SUBMIT_VER(guc) < MAKE_GUC_VER(1, 26, 0)) {
+		gt->info.has_indirect_ring_state = 0;
+		xe_gt_notice(gt, "indirect ring state requires WA in GuC submit ver 1.26+\n");
+	}
+
 	if (IS_SRIOV_VF(xe)) {
 		ret = devm_add_action_or_reset(xe->drm.dev, vf_guc_fini_hw, guc);
 		if (ret)
diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c
index 81b5f01b1f65..92c6981fe220 100644
--- a/drivers/gpu/drm/xe/xe_guc_ads.c
+++ b/drivers/gpu/drm/xe/xe_guc_ads.c
@@ -360,6 +360,9 @@ static void guc_waklv_init(struct xe_guc_ads *ads)
 	if (XE_GT_WA(gt, 14020001231))
 		guc_waklv_enable(ads, NULL, 0, &offset, &remain,
 				 GUC_WORKAROUND_KLV_DISABLE_PSMI_INTERRUPTS_AT_C6_ENTRY_RESTORE_AT_EXIT);
+	if (XE_GT_WA(gt, 14025515070) && GUC_FIRMWARE_VER_AT_LEAST(&gt->uc.guc, 70, 53))
+		guc_waklv_enable(ads, NULL, 0, &offset, &remain,
+				 GUC_WA_KLV_CLR_CS_INDIRECT_RING_STATE_IF_IDLE_AT_CTX_REG);
 
 	size = guc_ads_waklv_size(ads) - remain;
 	if (!size)
diff --git a/drivers/gpu/drm/xe/xe_guc_capture.h b/drivers/gpu/drm/xe/xe_guc_capture.h
index 34d6fdc64f56..dca97d52b192 100644
--- a/drivers/gpu/drm/xe/xe_guc_capture.h
+++ b/drivers/gpu/drm/xe/xe_guc_capture.h
@@ -3,8 +3,8 @@
  * Copyright © 2021-2024 Intel Corporation
  */
 
-#ifndef _XE_GUC_CAPTURE_H
-#define _XE_GUC_CAPTURE_H
+#ifndef _XE_GUC_CAPTURE_H_
+#define _XE_GUC_CAPTURE_H_
 
 #include <linux/types.h>
 #include "abi/guc_capture_abi.h"
diff --git a/drivers/gpu/drm/xe/xe_guc_capture_types.h b/drivers/gpu/drm/xe/xe_guc_capture_types.h
index 6cb439115597..058a3f2eadce 100644
--- a/drivers/gpu/drm/xe/xe_guc_capture_types.h
+++ b/drivers/gpu/drm/xe/xe_guc_capture_types.h
@@ -3,8 +3,8 @@
  * Copyright © 2021-2024 Intel Corporation
  */
 
-#ifndef _XE_GUC_CAPTURE_TYPES_H
-#define _XE_GUC_CAPTURE_TYPES_H
+#ifndef _XE_GUC_CAPTURE_TYPES_H_
+#define _XE_GUC_CAPTURE_TYPES_H_
 
 #include <linux/types.h>
 #include "regs/xe_reg_defs.h"
@@ -32,7 +32,7 @@ struct __guc_mmio_reg_descr {
 	/**
 	 * @data_type: data type of the register
 	 * Could be 32 bit, low or hi dword of a 64 bit, see enum
-	 * register_data_type
+	 * capture_register_data_type
 	 */
 	enum capture_register_data_type data_type;
 	/** @flags: Flags for the register */
diff --git a/drivers/gpu/drm/xe/xe_guc_ct.c b/drivers/gpu/drm/xe/xe_guc_ct.c
index a11cff7a20be..21e0dad9a481 100644
--- a/drivers/gpu/drm/xe/xe_guc_ct.c
+++ b/drivers/gpu/drm/xe/xe_guc_ct.c
@@ -186,13 +186,16 @@ static void fast_req_track(struct xe_guc_ct *ct, u16 fence, u16 action) { }
 struct g2h_fence {
 	u32 *response_buffer;
 	u32 seqno;
+	/* fields below this point are setup based on the response */
 	u32 response_data;
 	u16 response_len;
 	u16 error;
 	u16 hint;
 	u16 reason;
+	u32 counter;
 	bool cancel;
 	bool retry;
+	bool wait;
 	bool fail;
 	bool done;
 };
@@ -204,6 +207,11 @@ static void g2h_fence_init(struct g2h_fence *g2h_fence, u32 *response_buffer)
 	g2h_fence->seqno = ~0x0;
 }
 
+static void g2h_fence_reinit(struct g2h_fence *g2h_fence)
+{
+	memset_after(g2h_fence, 0, seqno);
+}
+
 static void g2h_fence_cancel(struct g2h_fence *g2h_fence)
 {
 	g2h_fence->cancel = true;
@@ -1331,6 +1339,7 @@ static int guc_ct_send_recv(struct xe_guc_ct *ct, const u32 *action, u32 len,
 	/* READ_ONCEs pairs with WRITE_ONCEs in parse_g2h_response
 	 * and g2h_fence_cancel.
 	 */
+wait_again:
 	ret = wait_event_timeout(ct->g2h_fence_wq, READ_ONCE(g2h_fence.done), HZ);
 	if (!ret) {
 		LNL_FLUSH_WORK(&ct->g2h_worker);
@@ -1356,6 +1365,14 @@ static int guc_ct_send_recv(struct xe_guc_ct *ct, const u32 *action, u32 len,
 		return -ETIME;
 	}
 
+	if (g2h_fence.wait) {
+		xe_gt_dbg(gt, "H2G action %#x busy: counter %u\n",
+			  action[0], g2h_fence.counter);
+		/* we can't leave any response data if we want to wait again */
+		g2h_fence_reinit(&g2h_fence);
+		mutex_unlock(&ct->lock);
+		goto wait_again;
+	}
 	if (g2h_fence.retry) {
 		xe_gt_dbg(gt, "H2G action %#x retrying: reason %#x\n",
 			  action[0], g2h_fence.reason);
@@ -1508,7 +1525,12 @@ static int parse_g2h_response(struct xe_guc_ct *ct, u32 *msg, u32 len)
 		return -EPROTO;
 	}
 
-	g2h_fence = xa_erase(&ct->fence_lookup, fence);
+	/* don't erase as we still expect a final response with the same fence */
+	if (type == GUC_HXG_TYPE_NO_RESPONSE_BUSY)
+		g2h_fence = xa_load(&ct->fence_lookup, fence);
+	else
+		g2h_fence = xa_erase(&ct->fence_lookup, fence);
+
 	if (unlikely(!g2h_fence)) {
 		/* Don't tear down channel, as send could've timed out */
 		/* CT_DEAD(ct, NULL, PARSE_G2H_UNKNOWN); */
@@ -1519,6 +1541,12 @@ static int parse_g2h_response(struct xe_guc_ct *ct, u32 *msg, u32 len)
 
 	xe_gt_assert(gt, fence == g2h_fence->seqno);
 
+	/*
+	 * reinit as we might have already process this g2h_fence before
+	 * if we received a NO_RESPONSE_BUSY reply
+	 */
+	g2h_fence_reinit(g2h_fence);
+
 	if (type == GUC_HXG_TYPE_RESPONSE_FAILURE) {
 		g2h_fence->fail = true;
 		g2h_fence->error = FIELD_GET(GUC_HXG_FAILURE_MSG_0_ERROR, hxg[0]);
@@ -1526,6 +1554,9 @@ static int parse_g2h_response(struct xe_guc_ct *ct, u32 *msg, u32 len)
 	} else if (type == GUC_HXG_TYPE_NO_RESPONSE_RETRY) {
 		g2h_fence->retry = true;
 		g2h_fence->reason = FIELD_GET(GUC_HXG_RETRY_MSG_0_REASON, hxg[0]);
+	} else if (type == GUC_HXG_TYPE_NO_RESPONSE_BUSY) {
+		g2h_fence->wait = true;
+		g2h_fence->counter = FIELD_GET(GUC_HXG_BUSY_MSG_0_COUNTER, hxg[0]);
 	} else if (g2h_fence->response_buffer) {
 		g2h_fence->response_len = hxg_len;
 		memcpy(g2h_fence->response_buffer, hxg, hxg_len * sizeof(u32));
@@ -1533,7 +1564,9 @@ static int parse_g2h_response(struct xe_guc_ct *ct, u32 *msg, u32 len)
 		g2h_fence->response_data = FIELD_GET(GUC_HXG_RESPONSE_MSG_0_DATA0, hxg[0]);
 	}
 
-	g2h_release_space(ct, GUC_CTB_HXG_MSG_MAX_LEN);
+	/* don't release any space if it was an intermediate message */
+	if (!g2h_fence->wait)
+		g2h_release_space(ct, GUC_CTB_HXG_MSG_MAX_LEN);
 
 	/* WRITE_ONCE pairs with READ_ONCEs in guc_ct_send_recv. */
 	WRITE_ONCE(g2h_fence->done, true);
@@ -1570,6 +1603,7 @@ static int parse_g2h_msg(struct xe_guc_ct *ct, u32 *msg, u32 len)
 	case GUC_HXG_TYPE_RESPONSE_SUCCESS:
 	case GUC_HXG_TYPE_RESPONSE_FAILURE:
 	case GUC_HXG_TYPE_NO_RESPONSE_RETRY:
+	case GUC_HXG_TYPE_NO_RESPONSE_BUSY:
 		ret = parse_g2h_response(ct, msg, len);
 		break;
 	default:
diff --git a/drivers/gpu/drm/xe/xe_guc_ct_types.h b/drivers/gpu/drm/xe/xe_guc_ct_types.h
index 5da1ce5dc372..f88e588af0d3 100644
--- a/drivers/gpu/drm/xe/xe_guc_ct_types.h
+++ b/drivers/gpu/drm/xe/xe_guc_ct_types.h
@@ -102,9 +102,9 @@ struct xe_dead_ct {
 	bool reported;
 	/** @worker: worker thread to get out of interrupt context before dumping */
 	struct work_struct worker;
-	/** snapshot_ct: copy of CT state and CTB content at point of error */
+	/** @snapshot_ct: copy of CT state and CTB content at point of error */
 	struct xe_guc_ct_snapshot *snapshot_ct;
-	/** snapshot_log: copy of GuC log at point of error */
+	/** @snapshot_log: copy of GuC log at point of error */
 	struct xe_guc_log_snapshot *snapshot_log;
 };
 
@@ -134,9 +134,9 @@ struct xe_guc_ct {
 	spinlock_t fast_lock;
 	/** @ctbs: buffers for sending and receiving commands */
 	struct {
-		/** @ctbs.send: Host to GuC (H2G, send) channel */
+		/** @ctbs.h2g: Host to GuC (H2G, send) channel */
 		struct guc_ctb h2g;
-		/** @ctbs.recv: GuC to Host (G2H, receive) channel */
+		/** @ctbs.g2h: GuC to Host (G2H, receive) channel */
 		struct guc_ctb g2h;
 	} ctbs;
 	/** @g2h_outstanding: number of outstanding G2H */
diff --git a/drivers/gpu/drm/xe/xe_guc_fwif.h b/drivers/gpu/drm/xe/xe_guc_fwif.h
index b73fae063fac..3fbda4798cff 100644
--- a/drivers/gpu/drm/xe/xe_guc_fwif.h
+++ b/drivers/gpu/drm/xe/xe_guc_fwif.h
@@ -3,8 +3,8 @@
  * Copyright © 2022 Intel Corporation
  */
 
-#ifndef _XE_GUC_FWIF_H
-#define _XE_GUC_FWIF_H
+#ifndef _XE_GUC_FWIF_H_
+#define _XE_GUC_FWIF_H_
 
 #include <linux/bits.h>
 
diff --git a/drivers/gpu/drm/xe/xe_guc_pc.c b/drivers/gpu/drm/xe/xe_guc_pc.c
index bb8c4e793492..7ecd91ad6192 100644
--- a/drivers/gpu/drm/xe/xe_guc_pc.c
+++ b/drivers/gpu/drm/xe/xe_guc_pc.c
@@ -890,9 +890,26 @@ void xe_guc_pc_init_early(struct xe_guc_pc *pc)
 	pc_init_fused_rp_values(pc);
 }
 
+static bool pc_needs_min_freq_change(struct xe_guc_pc *pc)
+{
+	struct xe_device *xe = pc_to_xe(pc);
+	struct xe_gt *gt = pc_to_gt(pc);
+
+	if (XE_DEVICE_WA(xe, 14022085890))
+		return true;
+
+	if (xe_gt_is_media_type(gt))
+		return false;
+
+	if (xe->info.platform == XE_BATTLEMAGE ||
+	    xe->info.platform == XE_CRESCENTISLAND)
+		return true;
+
+	return false;
+}
+
 static int pc_adjust_freq_bounds(struct xe_guc_pc *pc)
 {
-	struct xe_tile *tile = gt_to_tile(pc_to_gt(pc));
 	int ret;
 
 	lockdep_assert_held(&pc->freq_lock);
@@ -919,7 +936,18 @@ static int pc_adjust_freq_bounds(struct xe_guc_pc *pc)
 	if (pc_get_min_freq(pc) > pc->rp0_freq)
 		ret = pc_set_min_freq(pc, pc->rp0_freq);
 
-	if (XE_DEVICE_WA(tile_to_xe(tile), 14022085890))
+	/*
+	 * Setting GT RP min frequency to 1.2GHz by default for
+	 * GT0(Graphics) Tile of BMG and CRI.
+	 *
+	 * While BMG G21 WA will apply min frequency for
+	 * both GT0(Graphics) and GT1(Media) Tile.
+	 *
+	 * This is an active frequency, so if the device is idle
+	 * we aren't expecting high power output across board
+	 *
+	 */
+	if (pc_needs_min_freq_change(pc))
 		ret = pc_set_min_freq(pc, max(BMG_MIN_FREQ, pc_get_min_freq(pc)));
 
 out:
diff --git a/drivers/gpu/drm/xe/xe_guc_relay_types.h b/drivers/gpu/drm/xe/xe_guc_relay_types.h
index 20eee10856b2..b99a6686416b 100644
--- a/drivers/gpu/drm/xe/xe_guc_relay_types.h
+++ b/drivers/gpu/drm/xe/xe_guc_relay_types.h
@@ -15,7 +15,7 @@
  * struct xe_guc_relay - Data used by the VF-PF Relay Communication over GuC.
  */
 struct xe_guc_relay {
-	/**@lock: protects all internal data. */
+	/** @lock: protects all internal data. */
 	spinlock_t lock;
 
 	/** @worker: dispatches incoming action messages. */
diff --git a/drivers/gpu/drm/xe/xe_guc_submit.c b/drivers/gpu/drm/xe/xe_guc_submit.c
index a145234f662b..b1222b42174c 100644
--- a/drivers/gpu/drm/xe/xe_guc_submit.c
+++ b/drivers/gpu/drm/xe/xe_guc_submit.c
@@ -259,24 +259,12 @@ static void guc_submit_sw_fini(struct drm_device *drm, void *arg)
 }
 
 static void guc_submit_fini(void *arg)
-{
-	struct xe_guc *guc = arg;
-
-	/* Forcefully kill any remaining exec queues */
-	xe_guc_ct_stop(&guc->ct);
-	guc_submit_reset_prepare(guc);
-	xe_guc_softreset(guc);
-	xe_guc_submit_stop(guc);
-	xe_uc_fw_sanitize(&guc->fw);
-	xe_guc_submit_pause_abort(guc);
-}
-
-static void guc_submit_wedged_fini(void *arg)
 {
 	struct xe_guc *guc = arg;
 	struct xe_exec_queue *q;
 	unsigned long index;
 
+	/* Drop any wedged queue refs */
 	mutex_lock(&guc->submission_state.lock);
 	xa_for_each(&guc->submission_state.exec_queue_lookup, index, q) {
 		if (exec_queue_wedged(q)) {
@@ -286,6 +274,14 @@ static void guc_submit_wedged_fini(void *arg)
 		}
 	}
 	mutex_unlock(&guc->submission_state.lock);
+
+	/* Forcefully kill any remaining exec queues */
+	xe_guc_ct_stop(&guc->ct);
+	guc_submit_reset_prepare(guc);
+	xe_guc_softreset(guc);
+	xe_guc_submit_stop(guc);
+	xe_uc_fw_sanitize(&guc->fw);
+	xe_guc_submit_pause_abort(guc);
 }
 
 static const struct xe_exec_queue_ops guc_exec_queue_ops;
@@ -1320,10 +1316,8 @@ static void disable_scheduling_deregister(struct xe_guc *guc,
 void xe_guc_submit_wedge(struct xe_guc *guc)
 {
 	struct xe_device *xe = guc_to_xe(guc);
-	struct xe_gt *gt = guc_to_gt(guc);
 	struct xe_exec_queue *q;
 	unsigned long index;
-	int err;
 
 	xe_gt_assert(guc_to_gt(guc), guc_to_xe(guc)->wedged.mode);
 
@@ -1335,15 +1329,6 @@ void xe_guc_submit_wedge(struct xe_guc *guc)
 		return;
 
 	if (xe->wedged.mode == XE_WEDGED_MODE_UPON_ANY_HANG_NO_RESET) {
-		err = devm_add_action_or_reset(guc_to_xe(guc)->drm.dev,
-					       guc_submit_wedged_fini, guc);
-		if (err) {
-			xe_gt_err(gt, "Failed to register clean-up on wedged.mode=%s; "
-				  "Although device is wedged.\n",
-				  xe_wedged_mode_to_string(XE_WEDGED_MODE_UPON_ANY_HANG_NO_RESET));
-			return;
-		}
-
 		mutex_lock(&guc->submission_state.lock);
 		xa_for_each(&guc->submission_state.exec_queue_lookup, index, q)
 			if (xe_exec_queue_get_unless_zero(q))
@@ -2983,9 +2968,10 @@ int xe_guc_exec_queue_reset_handler(struct xe_guc *guc, u32 *msg, u32 len)
 	if (unlikely(!q))
 		return -EPROTO;
 
-	xe_gt_info(gt, "Engine reset: engine_class=%s, logical_mask: 0x%x, guc_id=%d, state=0x%0x",
-		   xe_hw_engine_class_to_str(q->class), q->logical_mask, guc_id,
-		   atomic_read(&q->guc->state));
+	if (!exec_queue_killed(q))
+		xe_gt_info(gt, "Engine reset: engine_class=%s, logical_mask: 0x%x, guc_id=%d, state=0x%0x",
+			   xe_hw_engine_class_to_str(q->class), q->logical_mask, guc_id,
+			   atomic_read(&q->guc->state));
 
 	trace_xe_exec_queue_reset(q);
 
diff --git a/drivers/gpu/drm/xe/xe_guc_submit_types.h b/drivers/gpu/drm/xe/xe_guc_submit_types.h
index 5ccc5f959bb3..7824f61b1290 100644
--- a/drivers/gpu/drm/xe/xe_guc_submit_types.h
+++ b/drivers/gpu/drm/xe/xe_guc_submit_types.h
@@ -138,7 +138,7 @@ struct xe_guc_submit_exec_queue_snapshot {
 		u32 primary;
 		/** @multi_queue.pos: Position of the exec queue within the multi queue group */
 		u8 pos;
-		/** @valid: The exec queue is part of a multi queue group */
+		/** @multi_queue.valid: The exec queue is part of a multi queue group */
 		bool valid;
 	} multi_queue;
 };
diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
index 6dd05fac6595..2f9c1c063f16 100644
--- a/drivers/gpu/drm/xe/xe_hw_engine.c
+++ b/drivers/gpu/drm/xe/xe_hw_engine.c
@@ -1026,6 +1026,9 @@ bool xe_hw_engine_is_reserved(struct xe_hw_engine *hwe)
 	struct xe_gt *gt = hwe->gt;
 	struct xe_device *xe = gt_to_xe(gt);
 
+	if (xe_device_is_admin_only(xe))
+		return true;
+
 	if (hwe->class == XE_ENGINE_CLASS_OTHER)
 		return true;
 
diff --git a/drivers/gpu/drm/xe/xe_hw_engine_types.h b/drivers/gpu/drm/xe/xe_hw_engine_types.h
index e4191a7a2c31..0f87128c6529 100644
--- a/drivers/gpu/drm/xe/xe_hw_engine_types.h
+++ b/drivers/gpu/drm/xe/xe_hw_engine_types.h
@@ -79,7 +79,7 @@ struct xe_hw_engine_class_intf {
 	 * @defaults: default scheduling properties
 	 */
 	struct {
-		/** @sched_props.set_job_timeout: Set job timeout in ms for engine */
+		/** @sched_props.job_timeout_ms: Set job timeout in ms for engine */
 		u32 job_timeout_ms;
 		/** @sched_props.job_timeout_min: Min job timeout in ms for engine */
 		u32 job_timeout_min;
diff --git a/drivers/gpu/drm/xe/xe_hw_error.h b/drivers/gpu/drm/xe/xe_hw_error.h
index d86e28c5180c..5e3a11424108 100644
--- a/drivers/gpu/drm/xe/xe_hw_error.h
+++ b/drivers/gpu/drm/xe/xe_hw_error.h
@@ -2,8 +2,8 @@
 /*
  * Copyright © 2025 Intel Corporation
  */
-#ifndef XE_HW_ERROR_H_
-#define XE_HW_ERROR_H_
+#ifndef _XE_HW_ERROR_H_
+#define _XE_HW_ERROR_H_
 
 #include <linux/types.h>
 
diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c
index 92e423a339f1..de3f2aeffc3f 100644
--- a/drivers/gpu/drm/xe/xe_hwmon.c
+++ b/drivers/gpu/drm/xe/xe_hwmon.c
@@ -180,6 +180,18 @@ struct xe_hwmon {
 	struct xe_hwmon_thermal_info temp;
 };
 
+static inline int prepare_power_limit_param2(const struct xe_hwmon *hwmon)
+{
+	if (hwmon->boot_power_limit_read) {
+		if (hwmon->xe->info.platform >= XE_CRESCENTISLAND)
+			return READ_PL_ACCEPTED;
+		else
+			return READ_PL_FROM_PCODE;
+	} else {
+		return READ_PL_FROM_FW;
+	}
+}
+
 static int xe_hwmon_pcode_read_power_limit(const struct xe_hwmon *hwmon, u32 attr, int channel,
 					   u32 *uval)
 {
@@ -191,9 +203,7 @@ static int xe_hwmon_pcode_read_power_limit(const struct xe_hwmon *hwmon, u32 att
 						  (channel == CHANNEL_CARD) ?
 						  READ_PSYSGPU_POWER_LIMIT :
 						  READ_PACKAGE_POWER_LIMIT,
-						  hwmon->boot_power_limit_read ?
-						  READ_PL_FROM_PCODE : READ_PL_FROM_FW),
-						  &val0, &val1);
+						  prepare_power_limit_param2(hwmon)), &val0, &val1);
 
 	if (ret) {
 		drm_dbg(&hwmon->xe->drm, "read failed ch %d val0 0x%08x, val1 0x%08x, ret %d\n",
@@ -226,10 +236,7 @@ static int xe_hwmon_pcode_rmw_power_limit(const struct xe_hwmon *hwmon, u32 attr
 						  (channel == CHANNEL_CARD) ?
 						  READ_PSYSGPU_POWER_LIMIT :
 						  READ_PACKAGE_POWER_LIMIT,
-						  hwmon->boot_power_limit_read ?
-						  READ_PL_FROM_PCODE : READ_PL_FROM_FW),
-						  &val0, &val1);
-
+						  prepare_power_limit_param2(hwmon)), &val0, &val1);
 	if (ret)
 		drm_dbg(&hwmon->xe->drm, "read failed ch %d val0 0x%08x, val1 0x%08x, ret %d\n",
 			channel, val0, val1, ret);
@@ -296,7 +303,12 @@ static struct xe_reg xe_hwmon_get_reg(struct xe_hwmon *hwmon, enum xe_hwmon_reg
 			return GT_PERF_STATUS;
 		break;
 	case REG_PKG_ENERGY_STATUS:
-		if (xe->info.platform == XE_PVC && channel == CHANNEL_PKG) {
+		if (xe->info.platform == XE_CRESCENTISLAND) {
+			if (channel == CHANNEL_CARD)
+				return CRI_PLATFORM_ENERGY_STATUS;
+			else if (channel == CHANNEL_PKG)
+				return CRI_PACKAGE_ENERGY_STATUS;
+		} else if (xe->info.platform == XE_PVC && channel == CHANNEL_PKG) {
 			return PVC_GT0_PLATFORM_ENERGY_STATUS;
 		} else if ((xe->info.platform == XE_DG2) && (channel == CHANNEL_PKG)) {
 			return PCU_CR_PACKAGE_ENERGY_STATUS;
diff --git a/drivers/gpu/drm/xe/xe_lrc.c b/drivers/gpu/drm/xe/xe_lrc.c
index 9d12a0d2f0b5..c725cde4508d 100644
--- a/drivers/gpu/drm/xe/xe_lrc.c
+++ b/drivers/gpu/drm/xe/xe_lrc.c
@@ -1214,7 +1214,7 @@ static ssize_t setup_invalidate_state_cache_wa(struct xe_lrc *lrc,
 	if (xe_gt_WARN_ON(lrc->gt, max_len < 3))
 		return -ENOSPC;
 
-	*cmd++ = MI_LOAD_REGISTER_IMM | MI_LRI_NUM_REGS(1);
+	*cmd++ = MI_LOAD_REGISTER_IMM | MI_LRI_LRM_CS_MMIO | MI_LRI_NUM_REGS(1);
 	*cmd++ = CS_DEBUG_MODE2(0).addr;
 	*cmd++ = REG_MASKED_FIELD_ENABLE(INSTRUCTION_STATE_CACHE_INVALIDATE);
 
diff --git a/drivers/gpu/drm/xe/xe_mem_pool.c b/drivers/gpu/drm/xe/xe_mem_pool.c
new file mode 100644
index 000000000000..d5e24d6aa88d
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_mem_pool.c
@@ -0,0 +1,403 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#include <linux/kernel.h>
+
+#include <drm/drm_managed.h>
+
+#include "instructions/xe_mi_commands.h"
+#include "xe_bo.h"
+#include "xe_device_types.h"
+#include "xe_map.h"
+#include "xe_mem_pool.h"
+#include "xe_mem_pool_types.h"
+#include "xe_tile_printk.h"
+
+/**
+ * struct xe_mem_pool - DRM MM pool for sub-allocating memory from a BO on an
+ * XE tile.
+ *
+ * The XE memory pool is a DRM MM manager that provides sub-allocation of memory
+ * from a backing buffer object (BO) on a specific XE tile. It is designed to
+ * manage memory for GPU workloads, allowing for efficient allocation and
+ * deallocation of memory regions within the BO.
+ *
+ * The memory pool maintains a primary BO that is pinned in the GGTT and mapped
+ * into the CPU address space for direct access. Optionally, it can also maintain
+ * a shadow BO that can be used for atomic updates to the primary BO's contents.
+ *
+ * The API provided by the memory pool allows clients to allocate and free memory
+ * regions, retrieve GPU and CPU addresses, and synchronize data between the
+ * primary and shadow BOs as needed.
+ */
+struct xe_mem_pool {
+	/** @base: Range allocator over [0, @size) in bytes */
+	struct drm_mm base;
+	/** @bo: Active pool BO (GGTT-pinned, CPU-mapped). */
+	struct xe_bo *bo;
+	/** @shadow: Shadow BO for atomic command updates. */
+	struct xe_bo *shadow;
+	/** @swap_guard: Timeline guard updating @bo and @shadow */
+	struct mutex swap_guard;
+	/** @cpu_addr: CPU virtual address of the active BO. */
+	void *cpu_addr;
+	/** @is_iomem: Indicates if the BO mapping is I/O memory. */
+	bool is_iomem;
+};
+
+static struct xe_mem_pool *node_to_pool(struct xe_mem_pool_node *node)
+{
+	return container_of(node->sa_node.mm, struct xe_mem_pool, base);
+}
+
+static struct xe_tile *pool_to_tile(struct xe_mem_pool *pool)
+{
+	return pool->bo->tile;
+}
+
+static void fini_pool_action(struct drm_device *drm, void *arg)
+{
+	struct xe_mem_pool *pool = arg;
+
+	if (pool->is_iomem)
+		kvfree(pool->cpu_addr);
+
+	drm_mm_takedown(&pool->base);
+}
+
+static int pool_shadow_init(struct xe_mem_pool *pool)
+{
+	struct xe_tile *tile = pool->bo->tile;
+	struct xe_device *xe = tile_to_xe(tile);
+	struct xe_bo *shadow;
+	int ret;
+
+	xe_assert(xe, !pool->shadow);
+
+	ret = drmm_mutex_init(&xe->drm, &pool->swap_guard);
+	if (ret)
+		return ret;
+
+	if (IS_ENABLED(CONFIG_PROVE_LOCKING)) {
+		fs_reclaim_acquire(GFP_KERNEL);
+		might_lock(&pool->swap_guard);
+		fs_reclaim_release(GFP_KERNEL);
+	}
+	shadow = xe_managed_bo_create_pin_map(xe, tile,
+					      xe_bo_size(pool->bo),
+					      XE_BO_FLAG_VRAM_IF_DGFX(tile) |
+					      XE_BO_FLAG_GGTT |
+					      XE_BO_FLAG_GGTT_INVALIDATE |
+					      XE_BO_FLAG_PINNED_NORESTORE);
+	if (IS_ERR(shadow))
+		return PTR_ERR(shadow);
+
+	pool->shadow = shadow;
+
+	return 0;
+}
+
+/**
+ * xe_mem_pool_init() - Initialize memory pool.
+ * @tile: the &xe_tile where allocate.
+ * @size: number of bytes to allocate.
+ * @guard: the size of the guard region at the end of the BO that is not
+ * sub-allocated, in bytes.
+ * @flags: flags to use to create shadow pool.
+ *
+ * Initializes a memory pool for sub-allocating memory from a backing BO on the
+ * specified XE tile. The backing BO is pinned in the GGTT and mapped into
+ * the CPU address space for direct access. Optionally, a shadow BO can also be
+ * initialized for atomic updates to the primary BO's contents.
+ *
+ * Returns: a pointer to the &xe_mem_pool, or an error pointer on failure.
+ */
+struct xe_mem_pool *xe_mem_pool_init(struct xe_tile *tile, u32 size,
+				     u32 guard, int flags)
+{
+	struct xe_device *xe = tile_to_xe(tile);
+	struct xe_mem_pool *pool;
+	struct xe_bo *bo;
+	u32 managed_size;
+	int ret;
+
+	xe_tile_assert(tile, size > guard);
+	managed_size = size - guard;
+
+	pool = drmm_kzalloc(&xe->drm, sizeof(*pool), GFP_KERNEL);
+	if (!pool)
+		return ERR_PTR(-ENOMEM);
+
+	bo = xe_managed_bo_create_pin_map(xe, tile, size,
+					  XE_BO_FLAG_VRAM_IF_DGFX(tile) |
+					  XE_BO_FLAG_GGTT |
+					  XE_BO_FLAG_GGTT_INVALIDATE |
+					  XE_BO_FLAG_PINNED_NORESTORE);
+	if (IS_ERR(bo)) {
+		xe_tile_err(tile, "Failed to prepare %uKiB BO for mem pool (%pe)\n",
+			    size / SZ_1K, bo);
+		return ERR_CAST(bo);
+	}
+	pool->bo = bo;
+	pool->is_iomem = bo->vmap.is_iomem;
+
+	if (pool->is_iomem) {
+		pool->cpu_addr = kvzalloc(size, GFP_KERNEL);
+		if (!pool->cpu_addr)
+			return ERR_PTR(-ENOMEM);
+	} else {
+		pool->cpu_addr = bo->vmap.vaddr;
+	}
+
+	if (flags & XE_MEM_POOL_BO_FLAG_INIT_SHADOW_COPY) {
+		ret = pool_shadow_init(pool);
+
+		if (ret)
+			goto out_err;
+	}
+
+	drm_mm_init(&pool->base, 0, managed_size);
+	ret = drmm_add_action_or_reset(&xe->drm, fini_pool_action, pool);
+	if (ret)
+		return ERR_PTR(ret);
+
+	return pool;
+
+out_err:
+	if (flags & XE_MEM_POOL_BO_FLAG_INIT_SHADOW_COPY)
+		xe_tile_err(tile,
+			    "Failed to initialize shadow BO for mem pool (%d)\n", ret);
+	if (bo->vmap.is_iomem)
+		kvfree(pool->cpu_addr);
+	return ERR_PTR(ret);
+}
+
+/**
+ * xe_mem_pool_sync() - Copy the entire contents of the main pool to shadow pool.
+ * @pool: the memory pool containing the primary and shadow BOs.
+ *
+ * Copies the entire contents of the primary pool to the shadow pool. This must
+ * be done after xe_mem_pool_init() with the XE_MEM_POOL_BO_FLAG_INIT_SHADOW_COPY
+ * flag to ensure that the shadow pool has the same initial contents as the primary
+ * pool. After this initial synchronization, clients can choose to synchronize the
+ * shadow pool with the primary pool on a node  basis using
+ * xe_mem_pool_sync_shadow_locked() as needed.
+ *
+ * Return: None.
+ */
+void xe_mem_pool_sync(struct xe_mem_pool *pool)
+{
+	struct xe_tile *tile = pool_to_tile(pool);
+	struct xe_device *xe = tile_to_xe(tile);
+
+	xe_tile_assert(tile, pool->shadow);
+
+	xe_map_memcpy_to(xe, &pool->shadow->vmap, 0,
+			 pool->cpu_addr, xe_bo_size(pool->bo));
+}
+
+/**
+ * xe_mem_pool_swap_shadow_locked() - Swap the primary BO with the shadow BO.
+ * @pool: the memory pool containing the primary and shadow BOs.
+ *
+ * Swaps the primary buffer object with the shadow buffer object in the mem
+ * pool. This allows for atomic updates to the contents of the primary BO
+ * by first writing to the shadow BO and then swapping it with the primary BO.
+ * Swap_guard must be held to ensure synchronization with any concurrent swap
+ * operations.
+ *
+ * Return: None.
+ */
+void xe_mem_pool_swap_shadow_locked(struct xe_mem_pool *pool)
+{
+	struct xe_tile *tile = pool_to_tile(pool);
+
+	xe_tile_assert(tile, pool->shadow);
+	lockdep_assert_held(&pool->swap_guard);
+
+	swap(pool->bo, pool->shadow);
+	if (!pool->bo->vmap.is_iomem)
+		pool->cpu_addr = pool->bo->vmap.vaddr;
+}
+
+/**
+ * xe_mem_pool_sync_shadow_locked() - Copy node from primary pool to shadow pool.
+ * @node: the node allocated in the memory pool.
+ *
+ * Copies the specified batch buffer from the primary pool to the shadow pool.
+ * Swap_guard must be held to ensure synchronization with any concurrent swap
+ * operations.
+ *
+ * Return: None.
+ */
+void xe_mem_pool_sync_shadow_locked(struct xe_mem_pool_node *node)
+{
+	struct xe_mem_pool *pool = node_to_pool(node);
+	struct xe_tile *tile = pool_to_tile(pool);
+	struct xe_device *xe = tile_to_xe(tile);
+	struct drm_mm_node *sa_node = &node->sa_node;
+
+	xe_tile_assert(tile, pool->shadow);
+	lockdep_assert_held(&pool->swap_guard);
+
+	xe_map_memcpy_to(xe, &pool->shadow->vmap,
+			 sa_node->start,
+			 pool->cpu_addr + sa_node->start,
+			 sa_node->size);
+}
+
+/**
+ * xe_mem_pool_gpu_addr() - Retrieve GPU address of memory pool.
+ * @pool: the memory pool
+ *
+ * Returns: GGTT address of the memory pool.
+ */
+u64 xe_mem_pool_gpu_addr(struct xe_mem_pool *pool)
+{
+	return xe_bo_ggtt_addr(pool->bo);
+}
+
+/**
+ * xe_mem_pool_cpu_addr() - Retrieve CPU address of manager pool.
+ * @pool: the memory pool
+ *
+ * Returns: CPU virtual address of memory pool.
+ */
+void *xe_mem_pool_cpu_addr(struct xe_mem_pool *pool)
+{
+	return pool->cpu_addr;
+}
+
+/**
+ * xe_mem_pool_bo_swap_guard() - Retrieve the mutex used to guard swap
+ * operations on a memory pool.
+ * @pool: the memory pool
+ *
+ * Returns: Swap guard mutex or NULL if shadow pool is not created.
+ */
+struct mutex *xe_mem_pool_bo_swap_guard(struct xe_mem_pool *pool)
+{
+	if (!pool->shadow)
+		return NULL;
+
+	return &pool->swap_guard;
+}
+
+/**
+ * xe_mem_pool_bo_flush_write() - Copy the data from the sub-allocation
+ * to the GPU memory.
+ * @node: the node allocated in the memory pool to flush.
+ */
+void xe_mem_pool_bo_flush_write(struct xe_mem_pool_node *node)
+{
+	struct xe_mem_pool *pool = node_to_pool(node);
+	struct xe_tile *tile = pool_to_tile(pool);
+	struct xe_device *xe = tile_to_xe(tile);
+	struct drm_mm_node *sa_node = &node->sa_node;
+
+	if (!pool->bo->vmap.is_iomem)
+		return;
+
+	xe_map_memcpy_to(xe, &pool->bo->vmap, sa_node->start,
+			 pool->cpu_addr + sa_node->start,
+			 sa_node->size);
+}
+
+/**
+ * xe_mem_pool_bo_sync_read() - Copy the data from GPU memory to the
+ * sub-allocation.
+ * @node: the node allocated in the memory pool to read back.
+ */
+void xe_mem_pool_bo_sync_read(struct xe_mem_pool_node *node)
+{
+	struct xe_mem_pool *pool = node_to_pool(node);
+	struct xe_tile *tile = pool_to_tile(pool);
+	struct xe_device *xe = tile_to_xe(tile);
+	struct drm_mm_node *sa_node = &node->sa_node;
+
+	if (!pool->bo->vmap.is_iomem)
+		return;
+
+	xe_map_memcpy_from(xe, pool->cpu_addr + sa_node->start,
+			   &pool->bo->vmap, sa_node->start, sa_node->size);
+}
+
+/**
+ * xe_mem_pool_alloc_node() - Allocate a new node for use with xe_mem_pool.
+ *
+ * Returns: node structure or an ERR_PTR(-ENOMEM).
+ */
+struct xe_mem_pool_node *xe_mem_pool_alloc_node(void)
+{
+	struct xe_mem_pool_node *node = kzalloc_obj(*node);
+
+	if (!node)
+		return ERR_PTR(-ENOMEM);
+
+	return node;
+}
+
+/**
+ * xe_mem_pool_insert_node() - Insert a node into the memory pool.
+ * @pool: the memory pool to insert into
+ * @node: the node to insert
+ * @size: the size of the node to be allocated in bytes.
+ *
+ * Inserts a node into the specified memory pool using drm_mm for
+ * allocation.
+ *
+ * Returns: 0 on success or a negative error code on failure.
+ */
+int xe_mem_pool_insert_node(struct xe_mem_pool *pool,
+			    struct xe_mem_pool_node *node, u32 size)
+{
+	if (!pool)
+		return -EINVAL;
+
+	return drm_mm_insert_node(&pool->base, &node->sa_node, size);
+}
+
+/**
+ * xe_mem_pool_free_node() - Free a node allocated from the memory pool.
+ * @node: the node to free
+ *
+ * Returns: None.
+ */
+void xe_mem_pool_free_node(struct xe_mem_pool_node *node)
+{
+	if (!node)
+		return;
+
+	drm_mm_remove_node(&node->sa_node);
+	kfree(node);
+}
+
+/**
+ * xe_mem_pool_node_cpu_addr() - Retrieve CPU address of the node.
+ * @node: the node allocated in the memory pool
+ *
+ * Returns: CPU virtual address of the node.
+ */
+void *xe_mem_pool_node_cpu_addr(struct xe_mem_pool_node *node)
+{
+	struct xe_mem_pool *pool = node_to_pool(node);
+
+	return xe_mem_pool_cpu_addr(pool) + node->sa_node.start;
+}
+
+/**
+ * xe_mem_pool_dump() - Dump the state of the DRM MM manager for debugging.
+ * @pool: the memory pool info be dumped.
+ * @p: The DRM printer to use for output.
+ *
+ * Only the drm managed region is dumped, not the state of the BOs or any other
+ * pool information.
+ *
+ * Returns: None.
+ */
+void xe_mem_pool_dump(struct xe_mem_pool *pool, struct drm_printer *p)
+{
+	drm_mm_print(&pool->base, p);
+}
diff --git a/drivers/gpu/drm/xe/xe_mem_pool.h b/drivers/gpu/drm/xe/xe_mem_pool.h
new file mode 100644
index 000000000000..89cd2555fe91
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_mem_pool.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+#ifndef _XE_MEM_POOL_H_
+#define _XE_MEM_POOL_H_
+
+#include <linux/sizes.h>
+#include <linux/types.h>
+
+#include <drm/drm_mm.h>
+#include "xe_mem_pool_types.h"
+
+struct drm_printer;
+struct xe_mem_pool;
+struct xe_tile;
+
+struct xe_mem_pool *xe_mem_pool_init(struct xe_tile *tile, u32 size,
+				     u32 guard, int flags);
+void xe_mem_pool_sync(struct xe_mem_pool *pool);
+void xe_mem_pool_swap_shadow_locked(struct xe_mem_pool *pool);
+void xe_mem_pool_sync_shadow_locked(struct xe_mem_pool_node *node);
+u64 xe_mem_pool_gpu_addr(struct xe_mem_pool *pool);
+void *xe_mem_pool_cpu_addr(struct xe_mem_pool *pool);
+struct mutex *xe_mem_pool_bo_swap_guard(struct xe_mem_pool *pool);
+void xe_mem_pool_bo_flush_write(struct xe_mem_pool_node *node);
+void xe_mem_pool_bo_sync_read(struct xe_mem_pool_node *node);
+struct xe_mem_pool_node *xe_mem_pool_alloc_node(void);
+int xe_mem_pool_insert_node(struct xe_mem_pool *pool,
+			    struct xe_mem_pool_node *node, u32 size);
+void xe_mem_pool_free_node(struct xe_mem_pool_node *node);
+void *xe_mem_pool_node_cpu_addr(struct xe_mem_pool_node *node);
+void xe_mem_pool_dump(struct xe_mem_pool *pool, struct drm_printer *p);
+
+#endif
diff --git a/drivers/gpu/drm/xe/xe_mem_pool_types.h b/drivers/gpu/drm/xe/xe_mem_pool_types.h
new file mode 100644
index 000000000000..d5e926c93351
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_mem_pool_types.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#ifndef _XE_MEM_POOL_TYPES_H_
+#define _XE_MEM_POOL_TYPES_H_
+
+#include <drm/drm_mm.h>
+
+#define XE_MEM_POOL_BO_FLAG_INIT_SHADOW_COPY			BIT(0)
+
+/**
+ * struct xe_mem_pool_node - Sub-range allocations from mem pool.
+ */
+struct xe_mem_pool_node {
+	/** @sa_node: drm_mm_node for this allocation. */
+	struct drm_mm_node sa_node;
+};
+
+#endif
diff --git a/drivers/gpu/drm/xe/xe_migrate.c b/drivers/gpu/drm/xe/xe_migrate.c
index fc918b4fba54..a87fbc1e9fb1 100644
--- a/drivers/gpu/drm/xe/xe_migrate.c
+++ b/drivers/gpu/drm/xe/xe_migrate.c
@@ -29,7 +29,9 @@
 #include "xe_hw_engine.h"
 #include "xe_lrc.h"
 #include "xe_map.h"
+#include "xe_mem_pool.h"
 #include "xe_mocs.h"
+#include "xe_pat.h"
 #include "xe_printk.h"
 #include "xe_pt.h"
 #include "xe_res_cursor.h"
@@ -216,7 +218,7 @@ static void xe_migrate_prepare_vm(struct xe_tile *tile, struct xe_migrate *m,
 				  struct xe_vm *vm, u32 *ofs)
 {
 	struct xe_device *xe = tile_to_xe(tile);
-	u16 pat_index = xe->pat.idx[XE_CACHE_WB];
+	u16 pat_index = xe_cache_pat_idx(xe, XE_CACHE_WB);
 	u8 id = tile->id;
 	u32 num_entries = NUM_PT_SLOTS, num_level = vm->pt_root[id]->level;
 #define VRAM_IDENTITY_MAP_COUNT	2
@@ -336,7 +338,7 @@ static void xe_migrate_prepare_vm(struct xe_tile *tile, struct xe_migrate *m,
 		 * if flat ccs is enabled.
 		 */
 		if (GRAPHICS_VER(xe) >= 20 && xe_device_has_flat_ccs(xe)) {
-			u16 comp_pat_index = xe->pat.idx[XE_CACHE_NONE_COMPRESSION];
+			u16 comp_pat_index = xe_cache_pat_idx(xe, XE_CACHE_NONE_COMPRESSION);
 			u64 vram_offset = IDENTITY_OFFSET +
 				DIV_ROUND_UP_ULL(actual_phy_size, SZ_1G);
 			u64 pt31_ofs = xe_bo_size(bo) - XE_PAGE_SIZE;
@@ -636,10 +638,10 @@ static void emit_pte(struct xe_migrate *m,
 
 	/* Indirect access needs compression enabled uncached PAT index */
 	if (GRAPHICS_VERx100(xe) >= 2000)
-		pat_index = is_comp_pte ? xe->pat.idx[XE_CACHE_NONE_COMPRESSION] :
-					  xe->pat.idx[XE_CACHE_WB];
+		pat_index = is_comp_pte ? xe_cache_pat_idx(xe, XE_CACHE_NONE_COMPRESSION) :
+					  xe_cache_pat_idx(xe, XE_CACHE_WB);
 	else
-		pat_index = xe->pat.idx[XE_CACHE_WB];
+		pat_index = xe_cache_pat_idx(xe, XE_CACHE_WB);
 
 	ptes = DIV_ROUND_UP(size, XE_PAGE_SIZE);
 
@@ -1166,11 +1168,12 @@ int xe_migrate_ccs_rw_copy(struct xe_tile *tile, struct xe_exec_queue *q,
 	u32 batch_size, batch_size_allocated;
 	struct xe_device *xe = gt_to_xe(gt);
 	struct xe_res_cursor src_it, ccs_it;
+	struct xe_mem_pool *bb_pool;
 	struct xe_sriov_vf_ccs_ctx *ctx;
-	struct xe_sa_manager *bb_pool;
 	u64 size = xe_bo_size(src_bo);
-	struct xe_bb *bb = NULL;
+	struct xe_mem_pool_node *bb;
 	u64 src_L0, src_L0_ofs;
+	struct xe_bb xe_bb_tmp;
 	u32 src_L0_pt;
 	int err;
 
@@ -1208,18 +1211,18 @@ int xe_migrate_ccs_rw_copy(struct xe_tile *tile, struct xe_exec_queue *q,
 		size -= src_L0;
 	}
 
-	bb = xe_bb_alloc(gt);
+	bb = xe_mem_pool_alloc_node();
 	if (IS_ERR(bb))
 		return PTR_ERR(bb);
 
 	bb_pool = ctx->mem.ccs_bb_pool;
-	scoped_guard(mutex, xe_sa_bo_swap_guard(bb_pool)) {
-		xe_sa_bo_swap_shadow(bb_pool);
+	scoped_guard(mutex, xe_mem_pool_bo_swap_guard(bb_pool)) {
+		xe_mem_pool_swap_shadow_locked(bb_pool);
 
-		err = xe_bb_init(bb, bb_pool, batch_size);
+		err = xe_mem_pool_insert_node(bb_pool, bb, batch_size * sizeof(u32));
 		if (err) {
 			xe_gt_err(gt, "BB allocation failed.\n");
-			xe_bb_free(bb, NULL);
+			kfree(bb);
 			return err;
 		}
 
@@ -1227,6 +1230,7 @@ int xe_migrate_ccs_rw_copy(struct xe_tile *tile, struct xe_exec_queue *q,
 		size = xe_bo_size(src_bo);
 		batch_size = 0;
 
+		xe_bb_tmp = (struct xe_bb){ .cs = xe_mem_pool_node_cpu_addr(bb), .len = 0 };
 		/*
 		 * Emit PTE and copy commands here.
 		 * The CCS copy command can only support limited size. If the size to be
@@ -1255,24 +1259,27 @@ int xe_migrate_ccs_rw_copy(struct xe_tile *tile, struct xe_exec_queue *q,
 			xe_assert(xe, IS_ALIGNED(ccs_it.start, PAGE_SIZE));
 			batch_size += EMIT_COPY_CCS_DW;
 
-			emit_pte(m, bb, src_L0_pt, false, true, &src_it, src_L0, src);
+			emit_pte(m, &xe_bb_tmp, src_L0_pt, false, true, &src_it, src_L0, src);
 
-			emit_pte(m, bb, ccs_pt, false, false, &ccs_it, ccs_size, src);
+			emit_pte(m, &xe_bb_tmp, ccs_pt, false, false, &ccs_it, ccs_size, src);
 
-			bb->len = emit_flush_invalidate(bb->cs, bb->len, flush_flags);
-			flush_flags = xe_migrate_ccs_copy(m, bb, src_L0_ofs, src_is_pltt,
+			xe_bb_tmp.len = emit_flush_invalidate(xe_bb_tmp.cs, xe_bb_tmp.len,
+							      flush_flags);
+			flush_flags = xe_migrate_ccs_copy(m, &xe_bb_tmp, src_L0_ofs, src_is_pltt,
 							  src_L0_ofs, dst_is_pltt,
 							  src_L0, ccs_ofs, true);
-			bb->len = emit_flush_invalidate(bb->cs, bb->len, flush_flags);
+			xe_bb_tmp.len = emit_flush_invalidate(xe_bb_tmp.cs, xe_bb_tmp.len,
+							      flush_flags);
 
 			size -= src_L0;
 		}
 
-		xe_assert(xe, (batch_size_allocated == bb->len));
+		xe_assert(xe, (batch_size_allocated == xe_bb_tmp.len));
+		xe_assert(xe, bb->sa_node.size == xe_bb_tmp.len * sizeof(u32));
 		src_bo->bb_ccs[read_write] = bb;
 
 		xe_sriov_vf_ccs_rw_update_bb_addr(ctx);
-		xe_sa_bo_sync_shadow(bb->bo);
+		xe_mem_pool_sync_shadow_locked(bb);
 	}
 
 	return 0;
@@ -1297,10 +1304,10 @@ int xe_migrate_ccs_rw_copy(struct xe_tile *tile, struct xe_exec_queue *q,
 void xe_migrate_ccs_rw_copy_clear(struct xe_bo *src_bo,
 				  enum xe_sriov_vf_ccs_rw_ctxs read_write)
 {
-	struct xe_bb *bb = src_bo->bb_ccs[read_write];
+	struct xe_mem_pool_node *bb = src_bo->bb_ccs[read_write];
 	struct xe_device *xe = xe_bo_device(src_bo);
+	struct xe_mem_pool *bb_pool;
 	struct xe_sriov_vf_ccs_ctx *ctx;
-	struct xe_sa_manager *bb_pool;
 	u32 *cs;
 
 	xe_assert(xe, IS_SRIOV_VF(xe));
@@ -1308,17 +1315,17 @@ void xe_migrate_ccs_rw_copy_clear(struct xe_bo *src_bo,
 	ctx = &xe->sriov.vf.ccs.contexts[read_write];
 	bb_pool = ctx->mem.ccs_bb_pool;
 
-	guard(mutex) (xe_sa_bo_swap_guard(bb_pool));
-	xe_sa_bo_swap_shadow(bb_pool);
-
-	cs = xe_sa_bo_cpu_addr(bb->bo);
-	memset(cs, MI_NOOP, bb->len * sizeof(u32));
-	xe_sriov_vf_ccs_rw_update_bb_addr(ctx);
+	scoped_guard(mutex, xe_mem_pool_bo_swap_guard(bb_pool)) {
+		xe_mem_pool_swap_shadow_locked(bb_pool);
 
-	xe_sa_bo_sync_shadow(bb->bo);
+		cs = xe_mem_pool_node_cpu_addr(bb);
+		memset(cs, MI_NOOP, bb->sa_node.size);
+		xe_sriov_vf_ccs_rw_update_bb_addr(ctx);
 
-	xe_bb_free(bb, NULL);
-	src_bo->bb_ccs[read_write] = NULL;
+		xe_mem_pool_sync_shadow_locked(bb);
+		xe_mem_pool_free_node(bb);
+		src_bo->bb_ccs[read_write] = NULL;
+	}
 }
 
 /**
@@ -1870,7 +1877,7 @@ __xe_migrate_update_pgtables(struct xe_migrate *m,
 
 	/* For sysmem PTE's, need to map them in our hole.. */
 	if (!IS_DGFX(xe)) {
-		u16 pat_index = xe->pat.idx[XE_CACHE_WB];
+		u16 pat_index = xe_cache_pat_idx(xe, XE_CACHE_WB);
 		u32 ptes, ofs;
 
 		ppgtt_ofs = NUM_KERNEL_PDE - 1;
@@ -2092,7 +2099,7 @@ static void build_pt_update_batch_sram(struct xe_migrate *m,
 				       struct drm_pagemap_addr *sram_addr,
 				       u32 size, int level)
 {
-	u16 pat_index = tile_to_xe(m->tile)->pat.idx[XE_CACHE_WB];
+	u16 pat_index = xe_cache_pat_idx(tile_to_xe(m->tile), XE_CACHE_WB);
 	u64 gpu_page_size = 0x1ull << xe_pt_shift(level);
 	u32 ptes;
 	int i = 0;
diff --git a/drivers/gpu/drm/xe/xe_migrate.h b/drivers/gpu/drm/xe/xe_migrate.h
index 169279d9d8c2..965c45889c72 100644
--- a/drivers/gpu/drm/xe/xe_migrate.h
+++ b/drivers/gpu/drm/xe/xe_migrate.h
@@ -3,8 +3,8 @@
  * Copyright © 2020 Intel Corporation
  */
 
-#ifndef _XE_MIGRATE_
-#define _XE_MIGRATE_
+#ifndef _XE_MIGRATE_H_
+#define _XE_MIGRATE_H_
 
 #include <linux/types.h>
 
diff --git a/drivers/gpu/drm/xe/xe_nvm.h b/drivers/gpu/drm/xe/xe_nvm.h
index fd3467ad35a4..b14722103f81 100644
--- a/drivers/gpu/drm/xe/xe_nvm.h
+++ b/drivers/gpu/drm/xe/xe_nvm.h
@@ -3,8 +3,8 @@
  * Copyright(c) 2019-2025 Intel Corporation. All rights reserved.
  */
 
-#ifndef __XE_NVM_H__
-#define __XE_NVM_H__
+#ifndef _XE_NVM_H_
+#define _XE_NVM_H_
 
 struct xe_device;
 
diff --git a/drivers/gpu/drm/xe/xe_oa_types.h b/drivers/gpu/drm/xe/xe_oa_types.h
index b03ffd513483..8906c3084b5f 100644
--- a/drivers/gpu/drm/xe/xe_oa_types.h
+++ b/drivers/gpu/drm/xe/xe_oa_types.h
@@ -67,7 +67,7 @@ struct xe_oa_format {
 	u32 counter_select;
 	/** @size: record size as written by HW (multiple of 64 byte cachelines) */
 	int size;
-	/** @type: of enum @drm_xe_oa_format_type */
+	/** @type: of enum drm_xe_oa_format_type */
 	int type;
 	/** @header: 32 or 64 bit report headers */
 	enum xe_oa_report_header header;
@@ -154,12 +154,14 @@ struct xe_oa {
 	u16 oa_unit_ids;
 };
 
-/** @xe_oa_buffer: State of the stream OA buffer */
+/**
+ * struct xe_oa_buffer - State of the stream OA buffer
+ */
 struct xe_oa_buffer {
 	/** @format: data format */
 	const struct xe_oa_format *format;
 
-	/** @format: xe_bo backing the OA buffer */
+	/** @bo: xe_bo backing the OA buffer */
 	struct xe_bo *bo;
 
 	/** @vaddr: mapped vaddr of the OA buffer */
diff --git a/drivers/gpu/drm/xe/xe_pagefault_types.h b/drivers/gpu/drm/xe/xe_pagefault_types.h
index b3289219b1be..c4ee625b93dd 100644
--- a/drivers/gpu/drm/xe/xe_pagefault_types.h
+++ b/drivers/gpu/drm/xe/xe_pagefault_types.h
@@ -86,7 +86,7 @@ struct xe_pagefault {
 		u8 engine_class;
 		/** @consumer.engine_instance: engine instance */
 		u8 engine_instance;
-		/** consumer.reserved: reserved bits for future expansion */
+		/** @consumer.reserved: reserved bits for future expansion */
 		u64 reserved;
 	} consumer;
 	/**
@@ -112,7 +112,7 @@ struct xe_pagefault {
 };
 
 /**
- * struct xe_pagefault_queue: Xe pagefault queue (consumer)
+ * struct xe_pagefault_queue - Xe pagefault queue (consumer)
  *
  * Used to capture all device page faults for deferred processing. Size this
  * queue to absorb the device’s worst-case number of outstanding faults.
diff --git a/drivers/gpu/drm/xe/xe_pat.c b/drivers/gpu/drm/xe/xe_pat.c
index 356f53bdb83c..fad5b5a5ed4a 100644
--- a/drivers/gpu/drm/xe/xe_pat.c
+++ b/drivers/gpu/drm/xe/xe_pat.c
@@ -531,6 +531,14 @@ static int xe2_dump(struct xe_gt *gt, struct drm_printer *p)
 	drm_printf(p, "Page Table Access:\n");
 	xe->pat.ops->entry_dump(p, "PTA_MODE", pat, false);
 
+	if (xe_gt_is_media_type(gt))
+		pat = xe_mmio_read32(&gt->mmio, XE_REG(_PAT_ATS));
+	else
+		pat = xe_gt_mcr_unicast_read_any(gt, XE_REG_MCR(_PAT_ATS));
+
+	drm_printf(p, "PCIe ATS/PASID:\n");
+	xe->pat.ops->entry_dump(p, "PAT_ATS ", pat, false);
+
 	return 0;
 }
 
@@ -551,6 +559,7 @@ static const struct xe_pat_ops xe3p_xpc_pat_ops = {
 void xe_pat_init_early(struct xe_device *xe)
 {
 	xe->pat.idx[XE_CACHE_WB_COMPRESSION] = XE_PAT_INVALID_IDX;
+	xe->pat.idx[XE_CACHE_NONE_COMPRESSION] = XE_PAT_INVALID_IDX;
 	if (GRAPHICS_VERx100(xe) == 3511) {
 		xe->pat.ops = &xe3p_xpc_pat_ops;
 		xe->pat.table = xe3p_xpc_pat_table;
diff --git a/drivers/gpu/drm/xe/xe_pat.h b/drivers/gpu/drm/xe/xe_pat.h
index a1e287c08f57..7060f66e1d63 100644
--- a/drivers/gpu/drm/xe/xe_pat.h
+++ b/drivers/gpu/drm/xe/xe_pat.h
@@ -82,4 +82,12 @@ bool xe_pat_index_get_comp_en(struct xe_device *xe, u16 pat_index);
  */
 u16 xe_pat_index_get_l3_policy(struct xe_device *xe, u16 pat_index);
 
+#define xe_cache_pat_idx(xe, cache_mode) ({					\
+	const struct xe_device *__xedev = (xe);					\
+	enum xe_cache_level __mode = (cache_mode);				\
+	xe_assert(__xedev, __mode < __XE_CACHE_LEVEL_COUNT);			\
+	xe_assert(__xedev, __xedev->pat.idx[__mode] != XE_PAT_INVALID_IDX);	\
+	__xedev->pat.idx[__mode];						\
+})
+
 #endif
diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index 01673d2b2464..41435f84aeb2 100644
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -118,6 +118,7 @@ static const struct xe_graphics_desc graphics_xe2 = {
 
 static const struct xe_graphics_desc graphics_xe3p_lpg = {
 	XE2_GFX_FEATURES,
+	.has_indirect_ring_state = 1,
 	.multi_queue_engine_class_mask = BIT(XE_ENGINE_CLASS_COPY) | BIT(XE_ENGINE_CLASS_COMPUTE),
 	.num_geometry_xecore_fuse_regs = 3,
 	.num_compute_xecore_fuse_regs = 3,
@@ -465,6 +466,7 @@ static const struct xe_device_desc cri_desc = {
 	.has_soc_remapper_sysctrl = true,
 	.has_soc_remapper_telem = true,
 	.has_sriov = true,
+	.has_sysctrl = true,
 	.max_gt_per_tile = 2,
 	MULTI_LRC_MASK,
 	.require_force_probe = true,
@@ -763,8 +765,8 @@ static int xe_info_init_early(struct xe_device *xe,
 	xe->info.has_soc_remapper_telem = desc->has_soc_remapper_telem;
 	xe->info.has_sriov = xe_configfs_primary_gt_allowed(to_pci_dev(xe->drm.dev)) &&
 		desc->has_sriov;
+	xe->info.has_sysctrl = desc->has_sysctrl;
 	xe->info.skip_guc_pc = desc->skip_guc_pc;
-	xe->info.skip_mtcfg = desc->skip_mtcfg;
 	xe->info.skip_pcode = desc->skip_pcode;
 	xe->info.needs_scratch = desc->needs_scratch;
 	xe->info.needs_shared_vf_gt_wq = desc->needs_shared_vf_gt_wq;
@@ -806,9 +808,6 @@ static void xe_info_probe_tile_count(struct xe_device *xe)
 	if (xe->info.tile_count == 1)
 		return;
 
-	if (xe->info.skip_mtcfg)
-		return;
-
 	mmio = xe_root_tile_mmio(xe);
 
 	/*
@@ -959,6 +958,12 @@ static int xe_info_init(struct xe_device *xe,
 	xe->info.has_64bit_timestamp = graphics_desc->has_64bit_timestamp;
 	xe->info.has_mem_copy_instr = GRAPHICS_VER(xe) >= 20;
 
+	if (IS_SRIOV_VF(xe)) {
+		xe->info.has_sysctrl = 0;
+		xe->info.has_soc_remapper_sysctrl = 0;
+		xe->info.has_soc_remapper_telem = 0;
+	}
+
 	xe_info_probe_tile_count(xe);
 
 	for_each_remote_tile(tile, xe, id) {
diff --git a/drivers/gpu/drm/xe/xe_pci_sriov.c b/drivers/gpu/drm/xe/xe_pci_sriov.c
index 3fd22034f03e..35e6b53e18ce 100644
--- a/drivers/gpu/drm/xe/xe_pci_sriov.c
+++ b/drivers/gpu/drm/xe/xe_pci_sriov.c
@@ -191,6 +191,8 @@ static int pf_disable_vfs(struct xe_device *xe)
 
 	pci_disable_sriov(pdev);
 
+	xe_sriov_pf_reprovision_default(xe);
+
 	pf_reset_vfs(xe, num_vfs);
 
 	xe_sriov_pf_unprovision_vfs(xe, num_vfs);
diff --git a/drivers/gpu/drm/xe/xe_pci_types.h b/drivers/gpu/drm/xe/xe_pci_types.h
index 8eee4fb1c57c..5b85e2c24b7b 100644
--- a/drivers/gpu/drm/xe/xe_pci_types.h
+++ b/drivers/gpu/drm/xe/xe_pci_types.h
@@ -57,9 +57,9 @@ struct xe_device_desc {
 	u8 has_soc_remapper_sysctrl:1;
 	u8 has_soc_remapper_telem:1;
 	u8 has_sriov:1;
+	u8 has_sysctrl:1;
 	u8 needs_scratch:1;
 	u8 skip_guc_pc:1;
-	u8 skip_mtcfg:1;
 	u8 skip_pcode:1;
 	u8 needs_shared_vf_gt_wq:1;
 };
diff --git a/drivers/gpu/drm/xe/xe_pcode_api.h b/drivers/gpu/drm/xe/xe_pcode_api.h
index 85cc7478b787..94575c476e3d 100644
--- a/drivers/gpu/drm/xe/xe_pcode_api.h
+++ b/drivers/gpu/drm/xe/xe_pcode_api.h
@@ -3,6 +3,9 @@
  * Copyright © 2022 Intel Corporation
  */
 
+#ifndef _XE_PCODE_API_H_
+#define _XE_PCODE_API_H_
+
 /* Internal to xe_pcode */
 
 #include "regs/xe_reg_defs.h"
@@ -47,8 +50,9 @@
 #define	WRITE_PSYSGPU_POWER_LIMIT		0x7
 #define	READ_PACKAGE_POWER_LIMIT		0x8
 #define	WRITE_PACKAGE_POWER_LIMIT		0x9
-#define	READ_PL_FROM_FW				0x1
 #define	READ_PL_FROM_PCODE			0x0
+#define	READ_PL_FROM_FW				0x1
+#define	READ_PL_ACCEPTED			0x2
 
 #define   PCODE_THERMAL_INFO			0x25
 #define     READ_THERMAL_LIMITS			0x0
@@ -101,3 +105,5 @@
 #define BMG_PCIE_CAP			XE_REG(0x138340)
 #define   LINK_DOWNGRADE		REG_GENMASK(1, 0)
 #define     DOWNGRADE_CAPABLE		2
+
+#endif
diff --git a/drivers/gpu/drm/xe/xe_pm.c b/drivers/gpu/drm/xe/xe_pm.c
index 01185f10a883..d4672eb07476 100644
--- a/drivers/gpu/drm/xe/xe_pm.c
+++ b/drivers/gpu/drm/xe/xe_pm.c
@@ -26,6 +26,7 @@
 #include "xe_pcode.h"
 #include "xe_pxp.h"
 #include "xe_sriov_vf_ccs.h"
+#include "xe_sysctrl.h"
 #include "xe_trace.h"
 #include "xe_vm.h"
 #include "xe_wa.h"
@@ -259,6 +260,8 @@ int xe_pm_resume(struct xe_device *xe)
 
 	xe_i2c_pm_resume(xe, true);
 
+	xe_sysctrl_pm_resume(xe);
+
 	xe_irq_resume(xe);
 
 	for_each_gt(gt, xe, id) {
@@ -670,6 +673,9 @@ int xe_pm_runtime_resume(struct xe_device *xe)
 
 	xe_i2c_pm_resume(xe, xe->d3cold.allowed);
 
+	if (xe->d3cold.allowed)
+		xe_sysctrl_pm_resume(xe);
+
 	xe_irq_resume(xe);
 
 	for_each_gt(gt, xe, id) {
diff --git a/drivers/gpu/drm/xe/xe_pt.c b/drivers/gpu/drm/xe/xe_pt.c
index 8e5f4f0dea3f..2669ff5ee747 100644
--- a/drivers/gpu/drm/xe/xe_pt.c
+++ b/drivers/gpu/drm/xe/xe_pt.c
@@ -14,6 +14,7 @@
 #include "xe_gt_stats.h"
 #include "xe_migrate.h"
 #include "xe_page_reclaim.h"
+#include "xe_pat.h"
 #include "xe_pt_types.h"
 #include "xe_pt_walk.h"
 #include "xe_res_cursor.h"
@@ -62,7 +63,7 @@ static u64 __xe_pt_empty_pte(struct xe_tile *tile, struct xe_vm *vm,
 			     unsigned int level)
 {
 	struct xe_device *xe = tile_to_xe(tile);
-	u16 pat_index = xe->pat.idx[XE_CACHE_WB];
+	u16 pat_index = xe_cache_pat_idx(xe, XE_CACHE_WB);
 	u8 id = tile->id;
 
 	if (!xe_vm_has_scratch(vm))
diff --git a/drivers/gpu/drm/xe/xe_pt_types.h b/drivers/gpu/drm/xe/xe_pt_types.h
index 84b51d3762a4..a7d1bb708b69 100644
--- a/drivers/gpu/drm/xe/xe_pt_types.h
+++ b/drivers/gpu/drm/xe/xe_pt_types.h
@@ -34,7 +34,7 @@ struct xe_pt {
 	bool rebind;
 	bool is_compact;
 #if IS_ENABLED(CONFIG_DRM_XE_DEBUG_VM)
-	/** addr: Virtual address start address of the PT. */
+	/** @addr: Virtual address start address of the PT. */
 	u64 addr;
 #endif
 };
diff --git a/drivers/gpu/drm/xe/xe_pt_walk.h b/drivers/gpu/drm/xe/xe_pt_walk.h
index 5c02c244f7de..e91995fa703b 100644
--- a/drivers/gpu/drm/xe/xe_pt_walk.h
+++ b/drivers/gpu/drm/xe/xe_pt_walk.h
@@ -2,8 +2,8 @@
 /*
  * Copyright © 2022 Intel Corporation
  */
-#ifndef __XE_PT_WALK__
-#define __XE_PT_WALK__
+#ifndef _XE_PT_WALK_H_
+#define _XE_PT_WALK_H_
 
 #include <linux/pagewalk.h>
 #include <linux/types.h>
@@ -34,7 +34,7 @@ struct xe_pt_walk {
 	 * changed during the walk.
 	 */
 	const u64 *shifts;
-	/** @max_level: Highest populated level in @sizes */
+	/** @max_level: Highest populated level in @shifts */
 	unsigned int max_level;
 	/**
 	 * @shared_pt_mode: Whether to skip all entries that are private
@@ -49,7 +49,7 @@ struct xe_pt_walk {
 
 /**
  * typedef xe_pt_entry_fn - gpu page-table-walk callback-function
- * @parent: The parent page.table.
+ * @parent: The parent page table.
  * @offset: The offset (number of entries) into the page table.
  * @level: The level of @parent.
  * @addr: The virtual address.
@@ -111,14 +111,14 @@ static inline bool xe_pt_covers(u64 addr, u64 end, unsigned int level,
 }
 
 /**
- * xe_pt_num_entries: Number of page-table entries of a given range at this
+ * xe_pt_num_entries - Number of page-table entries of a given range at this
  * level
  * @addr: Start address.
  * @end: End address.
  * @level: Page table level.
  * @walk: Walk info.
  *
- * Return: The number of page table entries at this level between @start and
+ * Return: The number of page table entries at this level between @addr and
  * @end.
  */
 static inline pgoff_t
@@ -132,7 +132,7 @@ xe_pt_num_entries(u64 addr, u64 end, unsigned int level,
 }
 
 /**
- * xe_pt_offset: Offset of the page-table entry for a given address.
+ * xe_pt_offset - Offset of the page-table entry for a given address.
  * @addr: The address.
  * @level: Page table level.
  * @walk: Walk info.
diff --git a/drivers/gpu/drm/xe/xe_pxp.c b/drivers/gpu/drm/xe/xe_pxp.c
index 7244090b0782..968b7e70b3f9 100644
--- a/drivers/gpu/drm/xe/xe_pxp.c
+++ b/drivers/gpu/drm/xe/xe_pxp.c
@@ -13,10 +13,12 @@
 #include "xe_device_types.h"
 #include "xe_exec_queue.h"
 #include "xe_force_wake.h"
+#include "xe_guc_exec_queue_types.h"
 #include "xe_guc_submit.h"
 #include "xe_gsc_proxy.h"
 #include "xe_gt_types.h"
 #include "xe_huc.h"
+#include "xe_hw_engine.h"
 #include "xe_mmio.h"
 #include "xe_pm.h"
 #include "xe_pxp_submit.h"
@@ -740,6 +742,10 @@ static void pxp_invalidate_queues(struct xe_pxp *pxp)
 	spin_unlock_irq(&pxp->queues.lock);
 
 	list_for_each_entry_safe(q, tmp, &to_clean, pxp.link) {
+		drm_dbg(&pxp->xe->drm,
+			"Killing queue due to PXP termination: eclass=%s, guc_id=%d\n",
+			xe_hw_engine_class_to_str(q->class), q->guc->id);
+
 		xe_exec_queue_kill(q);
 
 		/*
diff --git a/drivers/gpu/drm/xe/xe_pxp.h b/drivers/gpu/drm/xe/xe_pxp.h
index 71a23280b900..4fb6e0afffd2 100644
--- a/drivers/gpu/drm/xe/xe_pxp.h
+++ b/drivers/gpu/drm/xe/xe_pxp.h
@@ -3,8 +3,8 @@
  * Copyright(c) 2024, Intel Corporation. All rights reserved.
  */
 
-#ifndef __XE_PXP_H__
-#define __XE_PXP_H__
+#ifndef _XE_PXP_H_
+#define _XE_PXP_H_
 
 #include <linux/types.h>
 
@@ -32,4 +32,4 @@ int xe_pxp_key_assign(struct xe_pxp *pxp, struct xe_bo *bo);
 int xe_pxp_bo_key_check(struct xe_pxp *pxp, struct xe_bo *bo);
 int xe_pxp_obj_key_check(struct drm_gem_object *obj);
 
-#endif /* __XE_PXP_H__ */
+#endif /* _XE_PXP_H_ */
diff --git a/drivers/gpu/drm/xe/xe_pxp_debugfs.h b/drivers/gpu/drm/xe/xe_pxp_debugfs.h
index 988466aad50b..2997de0c90b2 100644
--- a/drivers/gpu/drm/xe/xe_pxp_debugfs.h
+++ b/drivers/gpu/drm/xe/xe_pxp_debugfs.h
@@ -3,11 +3,11 @@
  * Copyright © 2024 Intel Corporation
  */
 
-#ifndef __XE_PXP_DEBUGFS_H__
-#define __XE_PXP_DEBUGFS_H__
+#ifndef _XE_PXP_DEBUGFS_H_
+#define _XE_PXP_DEBUGFS_H_
 
 struct xe_pxp;
 
 void xe_pxp_debugfs_register(struct xe_pxp *pxp);
 
-#endif /* __XE_PXP_DEBUGFS_H__ */
+#endif /* _XE_PXP_DEBUGFS_H_ */
diff --git a/drivers/gpu/drm/xe/xe_pxp_submit.h b/drivers/gpu/drm/xe/xe_pxp_submit.h
index c9efda02f4b0..dbbbe6b92bb2 100644
--- a/drivers/gpu/drm/xe/xe_pxp_submit.h
+++ b/drivers/gpu/drm/xe/xe_pxp_submit.h
@@ -3,8 +3,8 @@
  * Copyright(c) 2024, Intel Corporation. All rights reserved.
  */
 
-#ifndef __XE_PXP_SUBMIT_H__
-#define __XE_PXP_SUBMIT_H__
+#ifndef _XE_PXP_SUBMIT_H_
+#define _XE_PXP_SUBMIT_H_
 
 #include <linux/types.h>
 
@@ -19,4 +19,4 @@ int xe_pxp_submit_session_termination(struct xe_pxp *pxp, u32 id);
 int xe_pxp_submit_session_invalidation(struct xe_pxp_gsc_client_resources *gsc_res,
 				       u32 id);
 
-#endif /* __XE_PXP_SUBMIT_H__ */
+#endif /* _XE_PXP_SUBMIT_H_ */
diff --git a/drivers/gpu/drm/xe/xe_pxp_types.h b/drivers/gpu/drm/xe/xe_pxp_types.h
index 53e9d48d10fb..ec86306e16f4 100644
--- a/drivers/gpu/drm/xe/xe_pxp_types.h
+++ b/drivers/gpu/drm/xe/xe_pxp_types.h
@@ -3,8 +3,8 @@
  * Copyright(c) 2024, Intel Corporation. All rights reserved.
  */
 
-#ifndef __XE_PXP_TYPES_H__
-#define __XE_PXP_TYPES_H__
+#ifndef _XE_PXP_TYPES_H_
+#define _XE_PXP_TYPES_H_
 
 #include <linux/completion.h>
 #include <linux/iosys-map.h>
@@ -132,4 +132,4 @@ struct xe_pxp {
 	u32 last_suspend_key_instance;
 };
 
-#endif /* __XE_PXP_TYPES_H__ */
+#endif /* _XE_PXP_TYPES_H_ */
diff --git a/drivers/gpu/drm/xe/xe_query.c b/drivers/gpu/drm/xe/xe_query.c
index d84d6a422c45..8c7d54498f38 100644
--- a/drivers/gpu/drm/xe/xe_query.c
+++ b/drivers/gpu/drm/xe/xe_query.c
@@ -231,6 +231,9 @@ static size_t calc_mem_regions_size(struct xe_device *xe)
 	u32 num_managers = 1;
 	int i;
 
+	if (xe_device_is_admin_only(xe))
+		return sizeof(struct drm_xe_query_mem_regions);
+
 	for (i = XE_PL_VRAM0; i <= XE_PL_VRAM1; ++i)
 		if (ttm_manager_type(&xe->ttm, i))
 			num_managers++;
@@ -259,6 +262,9 @@ static int query_mem_regions(struct xe_device *xe,
 	if (XE_IOCTL_DBG(xe, !mem_regions))
 		return -ENOMEM;
 
+	if (xe_device_is_admin_only(xe))
+		goto user_copy;
+
 	man = ttm_manager_type(&xe->ttm, XE_PL_TT);
 	mem_regions->mem_regions[0].mem_class = DRM_XE_MEM_REGION_CLASS_SYSMEM;
 	/*
@@ -297,6 +303,7 @@ static int query_mem_regions(struct xe_device *xe,
 		}
 	}
 
+user_copy:
 	if (!copy_to_user(query_ptr, mem_regions, size))
 		ret = 0;
 	else
diff --git a/drivers/gpu/drm/xe/xe_reg_sr.h b/drivers/gpu/drm/xe/xe_reg_sr.h
index 1ec6e8ecf278..d26cf4713383 100644
--- a/drivers/gpu/drm/xe/xe_reg_sr.h
+++ b/drivers/gpu/drm/xe/xe_reg_sr.h
@@ -3,8 +3,8 @@
  * Copyright © 2022 Intel Corporation
  */
 
-#ifndef _XE_REG_SR_
-#define _XE_REG_SR_
+#ifndef _XE_REG_SR_H_
+#define _XE_REG_SR_H_
 
 /*
  * Reg save/restore bookkeeping
diff --git a/drivers/gpu/drm/xe/xe_reg_sr_types.h b/drivers/gpu/drm/xe/xe_reg_sr_types.h
index ebe11f237fa2..0a6695db2967 100644
--- a/drivers/gpu/drm/xe/xe_reg_sr_types.h
+++ b/drivers/gpu/drm/xe/xe_reg_sr_types.h
@@ -3,8 +3,8 @@
  * Copyright © 2022 Intel Corporation
  */
 
-#ifndef _XE_REG_SR_TYPES_
-#define _XE_REG_SR_TYPES_
+#ifndef _XE_REG_SR_TYPES_H_
+#define _XE_REG_SR_TYPES_H_
 
 #include <linux/types.h>
 #include <linux/xarray.h>
diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.c b/drivers/gpu/drm/xe/xe_reg_whitelist.c
index 80577e4b7437..8cc313182968 100644
--- a/drivers/gpu/drm/xe/xe_reg_whitelist.c
+++ b/drivers/gpu/drm/xe/xe_reg_whitelist.c
@@ -226,7 +226,7 @@ void xe_reg_whitelist_print_entry(struct drm_printer *p, unsigned int indent,
 	}
 
 	range_start = reg & REG_GENMASK(25, range_bit);
-	range_end = range_start | REG_GENMASK(range_bit, 0);
+	range_end = range_start | REG_GENMASK(range_bit - 1, 0);
 
 	switch (val & RING_FORCE_TO_NONPRIV_ACCESS_MASK) {
 	case RING_FORCE_TO_NONPRIV_ACCESS_RW:
diff --git a/drivers/gpu/drm/xe/xe_reg_whitelist.h b/drivers/gpu/drm/xe/xe_reg_whitelist.h
index 69b121d377da..3b64b42fe96e 100644
--- a/drivers/gpu/drm/xe/xe_reg_whitelist.h
+++ b/drivers/gpu/drm/xe/xe_reg_whitelist.h
@@ -3,8 +3,8 @@
  * Copyright © 2023 Intel Corporation
  */
 
-#ifndef _XE_REG_WHITELIST_
-#define _XE_REG_WHITELIST_
+#ifndef _XE_REG_WHITELIST_H_
+#define _XE_REG_WHITELIST_H_
 
 #include <linux/types.h>
 
diff --git a/drivers/gpu/drm/xe/xe_rtp.h b/drivers/gpu/drm/xe/xe_rtp.h
index 7d6daa7eb1e4..4537ff46a17f 100644
--- a/drivers/gpu/drm/xe/xe_rtp.h
+++ b/drivers/gpu/drm/xe/xe_rtp.h
@@ -3,8 +3,8 @@
  * Copyright © 2022 Intel Corporation
  */
 
-#ifndef _XE_RTP_
-#define _XE_RTP_
+#ifndef _XE_RTP_H_
+#define _XE_RTP_H_
 
 #include <linux/types.h>
 #include <linux/xarray.h>
diff --git a/drivers/gpu/drm/xe/xe_rtp_helpers.h b/drivers/gpu/drm/xe/xe_rtp_helpers.h
index a33b0ae98bbc..ffa8b2f8828d 100644
--- a/drivers/gpu/drm/xe/xe_rtp_helpers.h
+++ b/drivers/gpu/drm/xe/xe_rtp_helpers.h
@@ -3,8 +3,8 @@
  * Copyright © 2023 Intel Corporation
  */
 
-#ifndef _XE_RTP_HELPERS_
-#define _XE_RTP_HELPERS_
+#ifndef _XE_RTP_HELPERS_H_
+#define _XE_RTP_HELPERS_H_
 
 #ifndef _XE_RTP_INCLUDE_PRIVATE_HELPERS
 #error "This header is supposed to be included by xe_rtp.h only"
@@ -66,6 +66,8 @@
 #define XE_RTP_PASTE_10(prefix_, sep_, args_) _XE_RTP_CONCAT(prefix_, FIRST_ARG args_) __XE_RTP_PASTE_SEP_ ## sep_ XE_RTP_PASTE_9(prefix_, sep_, _XE_TUPLE_TAIL args_)
 #define XE_RTP_PASTE_11(prefix_, sep_, args_) _XE_RTP_CONCAT(prefix_, FIRST_ARG args_) __XE_RTP_PASTE_SEP_ ## sep_ XE_RTP_PASTE_10(prefix_, sep_, _XE_TUPLE_TAIL args_)
 #define XE_RTP_PASTE_12(prefix_, sep_, args_) _XE_RTP_CONCAT(prefix_, FIRST_ARG args_) __XE_RTP_PASTE_SEP_ ## sep_ XE_RTP_PASTE_11(prefix_, sep_, _XE_TUPLE_TAIL args_)
+#define XE_RTP_PASTE_13(prefix_, sep_, args_) _XE_RTP_CONCAT(prefix_, FIRST_ARG args_) __XE_RTP_PASTE_SEP_ ## sep_ XE_RTP_PASTE_12(prefix_, sep_, _XE_TUPLE_TAIL args_)
+#define XE_RTP_PASTE_14(prefix_, sep_, args_) _XE_RTP_CONCAT(prefix_, FIRST_ARG args_) __XE_RTP_PASTE_SEP_ ## sep_ XE_RTP_PASTE_13(prefix_, sep_, _XE_TUPLE_TAIL args_)
 
 /*
  * XE_RTP_DROP_CAST - Drop cast to convert a compound statement to a initializer
diff --git a/drivers/gpu/drm/xe/xe_rtp_types.h b/drivers/gpu/drm/xe/xe_rtp_types.h
index 166251615be1..0265c16d2762 100644
--- a/drivers/gpu/drm/xe/xe_rtp_types.h
+++ b/drivers/gpu/drm/xe/xe_rtp_types.h
@@ -3,8 +3,8 @@
  * Copyright © 2022 Intel Corporation
  */
 
-#ifndef _XE_RTP_TYPES_
-#define _XE_RTP_TYPES_
+#ifndef _XE_RTP_TYPES_H_
+#define _XE_RTP_TYPES_H_
 
 #include <linux/types.h>
 
diff --git a/drivers/gpu/drm/xe/xe_sriov_pf.c b/drivers/gpu/drm/xe/xe_sriov_pf.c
index 47a6e0fd66e0..33bd754d138f 100644
--- a/drivers/gpu/drm/xe/xe_sriov_pf.c
+++ b/drivers/gpu/drm/xe/xe_sriov_pf.c
@@ -20,11 +20,6 @@
 #include "xe_sriov_pf_sysfs.h"
 #include "xe_sriov_printk.h"
 
-static bool wanted_admin_only(struct xe_device *xe)
-{
-	return xe_configfs_admin_only_pf(to_pci_dev(xe->drm.dev));
-}
-
 static unsigned int wanted_max_vfs(struct xe_device *xe)
 {
 	return xe_configfs_get_max_vfs(to_pci_dev(xe->drm.dev));
@@ -79,7 +74,6 @@ bool xe_sriov_pf_readiness(struct xe_device *xe)
 
 	pf_reduce_totalvfs(xe, newlimit);
 
-	xe->sriov.pf.admin_only = wanted_admin_only(xe);
 	xe->sriov.pf.device_total_vfs = totalvfs;
 	xe->sriov.pf.driver_max_vfs = newlimit;
 
diff --git a/drivers/gpu/drm/xe/xe_sriov_pf_helpers.h b/drivers/gpu/drm/xe/xe_sriov_pf_helpers.h
index 0fcc6cec4afc..19f6f8331c8d 100644
--- a/drivers/gpu/drm/xe/xe_sriov_pf_helpers.h
+++ b/drivers/gpu/drm/xe/xe_sriov_pf_helpers.h
@@ -7,6 +7,7 @@
 #define _XE_SRIOV_PF_HELPERS_H_
 
 #include "xe_assert.h"
+#include "xe_device.h"
 #include "xe_device_types.h"
 #include "xe_sriov.h"
 #include "xe_sriov_types.h"
@@ -57,7 +58,7 @@ static inline unsigned int xe_sriov_pf_num_vfs(const struct xe_device *xe)
 static inline bool xe_sriov_pf_admin_only(const struct xe_device *xe)
 {
 	xe_assert(xe, IS_SRIOV_PF(xe));
-	return xe->sriov.pf.admin_only;
+	return xe_device_is_admin_only(xe);
 }
 
 static inline struct mutex *xe_sriov_pf_master_mutex(struct xe_device *xe)
diff --git a/drivers/gpu/drm/xe/xe_sriov_pf_provision.c b/drivers/gpu/drm/xe/xe_sriov_pf_provision.c
index abe3677d33ed..0ec7ea83f12a 100644
--- a/drivers/gpu/drm/xe/xe_sriov_pf_provision.c
+++ b/drivers/gpu/drm/xe/xe_sriov_pf_provision.c
@@ -41,6 +41,8 @@ static int pf_provision_vfs(struct xe_device *xe, unsigned int num_vfs)
 	int err;
 
 	for_each_gt(gt, xe, id) {
+		err = xe_gt_sriov_pf_config_set_fair_sched(gt, num_vfs);
+		result = result ?: err;
 		err = xe_gt_sriov_pf_config_set_fair(gt, VFID(1), num_vfs);
 		result = result ?: err;
 	}
@@ -103,6 +105,45 @@ int xe_sriov_pf_unprovision_vfs(struct xe_device *xe, unsigned int num_vfs)
 	return 0;
 }
 
+static int pf_reprovision_default(struct xe_device *xe)
+{
+	struct xe_gt *gt;
+	unsigned int id;
+	int result = 0;
+	int err;
+
+	guard(mutex)(xe_sriov_pf_master_mutex(xe));
+
+	for_each_gt(gt, xe, id) {
+		err = xe_gt_sriov_pf_policy_set_sched_if_idle_locked(gt, false);
+		result = result ?: err;
+		err = xe_gt_sriov_pf_config_set_exec_quantum_locked(gt, PFID, 0);
+		result = result ?: err;
+		err = xe_gt_sriov_pf_config_set_preempt_timeout_locked(gt, PFID, 0);
+		result = result ?: err;
+	}
+
+	return result;
+}
+
+/**
+ * xe_sriov_pf_reprovision_default() - Reprovision default PF in auto-mode.
+ * @xe: the PF &xe_device
+ *
+ * This function can only be called on PF.
+ *
+ * Return: 0 on success or a negative error code on failure.
+ */
+int xe_sriov_pf_reprovision_default(struct xe_device *xe)
+{
+	xe_assert(xe, IS_SRIOV_PF(xe));
+
+	if (!pf_auto_provisioning_mode(xe))
+		return 0;
+
+	return pf_reprovision_default(xe);
+}
+
 /**
  * xe_sriov_pf_provision_set_mode() - Change VFs provision mode.
  * @xe: the PF &xe_device
diff --git a/drivers/gpu/drm/xe/xe_sriov_pf_provision.h b/drivers/gpu/drm/xe/xe_sriov_pf_provision.h
index f26f49539697..b15e4d7ad940 100644
--- a/drivers/gpu/drm/xe/xe_sriov_pf_provision.h
+++ b/drivers/gpu/drm/xe/xe_sriov_pf_provision.h
@@ -30,6 +30,7 @@ int xe_sriov_pf_provision_query_vf_vram(struct xe_device *xe, unsigned int vfid,
 
 int xe_sriov_pf_provision_vfs(struct xe_device *xe, unsigned int num_vfs);
 int xe_sriov_pf_unprovision_vfs(struct xe_device *xe, unsigned int num_vfs);
+int xe_sriov_pf_reprovision_default(struct xe_device *xe);
 
 int xe_sriov_pf_provision_set_mode(struct xe_device *xe, enum xe_sriov_provisioning_mode mode);
 
diff --git a/drivers/gpu/drm/xe/xe_sriov_pf_types.h b/drivers/gpu/drm/xe/xe_sriov_pf_types.h
index 080cf10512f4..b0253e1ae5da 100644
--- a/drivers/gpu/drm/xe/xe_sriov_pf_types.h
+++ b/drivers/gpu/drm/xe/xe_sriov_pf_types.h
@@ -36,9 +36,6 @@ struct xe_sriov_metadata {
  * @XE_SRIOV_MODE_PF mode.
  */
 struct xe_device_pf {
-	/** @admin_only: PF functionality focused on VFs management only. */
-	bool admin_only;
-
 	/** @device_total_vfs: Maximum number of VFs supported by the device. */
 	u16 device_total_vfs;
 
diff --git a/drivers/gpu/drm/xe/xe_sriov_vf_ccs.c b/drivers/gpu/drm/xe/xe_sriov_vf_ccs.c
index db023fb66a27..09b99fb2608b 100644
--- a/drivers/gpu/drm/xe/xe_sriov_vf_ccs.c
+++ b/drivers/gpu/drm/xe/xe_sriov_vf_ccs.c
@@ -14,9 +14,9 @@
 #include "xe_guc.h"
 #include "xe_guc_submit.h"
 #include "xe_lrc.h"
+#include "xe_mem_pool.h"
 #include "xe_migrate.h"
 #include "xe_pm.h"
-#include "xe_sa.h"
 #include "xe_sriov_printk.h"
 #include "xe_sriov_vf.h"
 #include "xe_sriov_vf_ccs.h"
@@ -141,43 +141,47 @@ static u64 get_ccs_bb_pool_size(struct xe_device *xe)
 
 static int alloc_bb_pool(struct xe_tile *tile, struct xe_sriov_vf_ccs_ctx *ctx)
 {
+	struct xe_mem_pool *pool;
 	struct xe_device *xe = tile_to_xe(tile);
-	struct xe_sa_manager *sa_manager;
+	u32 *pool_cpu_addr, *last_dw_addr;
 	u64 bb_pool_size;
-	int offset, err;
+	int err;
 
 	bb_pool_size = get_ccs_bb_pool_size(xe);
 	xe_sriov_info(xe, "Allocating %s CCS BB pool size = %lldMB\n",
 		      ctx->ctx_id ? "Restore" : "Save", bb_pool_size / SZ_1M);
 
-	sa_manager = __xe_sa_bo_manager_init(tile, bb_pool_size, SZ_4K, SZ_16,
-					     XE_SA_BO_MANAGER_FLAG_SHADOW);
-
-	if (IS_ERR(sa_manager)) {
-		xe_sriov_err(xe, "Suballocator init failed with error: %pe\n",
-			     sa_manager);
-		err = PTR_ERR(sa_manager);
+	pool = xe_mem_pool_init(tile, bb_pool_size, sizeof(u32),
+				XE_MEM_POOL_BO_FLAG_INIT_SHADOW_COPY);
+	if (IS_ERR(pool)) {
+		xe_sriov_err(xe, "xe_mem_pool_init failed with error: %pe\n",
+			     pool);
+		err = PTR_ERR(pool);
 		return err;
 	}
 
-	offset = 0;
-	xe_map_memset(xe, &sa_manager->bo->vmap, offset, MI_NOOP,
-		      bb_pool_size);
-	xe_map_memset(xe, &sa_manager->shadow->vmap, offset, MI_NOOP,
-		      bb_pool_size);
+	pool_cpu_addr = xe_mem_pool_cpu_addr(pool);
+	memset(pool_cpu_addr, 0, bb_pool_size);
 
-	offset = bb_pool_size - sizeof(u32);
-	xe_map_wr(xe, &sa_manager->bo->vmap, offset, u32, MI_BATCH_BUFFER_END);
-	xe_map_wr(xe, &sa_manager->shadow->vmap, offset, u32, MI_BATCH_BUFFER_END);
+	last_dw_addr = pool_cpu_addr + (bb_pool_size / sizeof(u32)) - 1;
+	*last_dw_addr = MI_BATCH_BUFFER_END;
 
-	ctx->mem.ccs_bb_pool = sa_manager;
+	/**
+	 * Sync the main copy and shadow copy so that the shadow copy is
+	 * replica of main copy. We sync only BBs after init part. So, we
+	 * need to make sure the main pool and shadow copy are in sync after
+	 * this point. This is needed as GuC may read the BB commands from
+	 * shadow copy.
+	 */
+	xe_mem_pool_sync(pool);
 
+	ctx->mem.ccs_bb_pool = pool;
 	return 0;
 }
 
 static void ccs_rw_update_ring(struct xe_sriov_vf_ccs_ctx *ctx)
 {
-	u64 addr = xe_sa_manager_gpu_addr(ctx->mem.ccs_bb_pool);
+	u64 addr = xe_mem_pool_gpu_addr(ctx->mem.ccs_bb_pool);
 	struct xe_lrc *lrc = xe_exec_queue_lrc(ctx->mig_q);
 	u32 dw[10], i = 0;
 
@@ -388,7 +392,7 @@ int xe_sriov_vf_ccs_init(struct xe_device *xe)
 #define XE_SRIOV_VF_CCS_RW_BB_ADDR_OFFSET	(2 * sizeof(u32))
 void xe_sriov_vf_ccs_rw_update_bb_addr(struct xe_sriov_vf_ccs_ctx *ctx)
 {
-	u64 addr = xe_sa_manager_gpu_addr(ctx->mem.ccs_bb_pool);
+	u64 addr = xe_mem_pool_gpu_addr(ctx->mem.ccs_bb_pool);
 	struct xe_lrc *lrc = xe_exec_queue_lrc(ctx->mig_q);
 	struct xe_device *xe = gt_to_xe(ctx->mig_q->gt);
 
@@ -412,8 +416,8 @@ int xe_sriov_vf_ccs_attach_bo(struct xe_bo *bo)
 	struct xe_device *xe = xe_bo_device(bo);
 	enum xe_sriov_vf_ccs_rw_ctxs ctx_id;
 	struct xe_sriov_vf_ccs_ctx *ctx;
+	struct xe_mem_pool_node *bb;
 	struct xe_tile *tile;
-	struct xe_bb *bb;
 	int err = 0;
 
 	xe_assert(xe, IS_VF_CCS_READY(xe));
@@ -445,7 +449,7 @@ int xe_sriov_vf_ccs_detach_bo(struct xe_bo *bo)
 {
 	struct xe_device *xe = xe_bo_device(bo);
 	enum xe_sriov_vf_ccs_rw_ctxs ctx_id;
-	struct xe_bb *bb;
+	struct xe_mem_pool_node *bb;
 
 	xe_assert(xe, IS_VF_CCS_READY(xe));
 
@@ -471,8 +475,8 @@ int xe_sriov_vf_ccs_detach_bo(struct xe_bo *bo)
  */
 void xe_sriov_vf_ccs_print(struct xe_device *xe, struct drm_printer *p)
 {
-	struct xe_sa_manager *bb_pool;
 	enum xe_sriov_vf_ccs_rw_ctxs ctx_id;
+	struct xe_mem_pool *bb_pool;
 
 	if (!IS_VF_CCS_READY(xe))
 		return;
@@ -485,7 +489,7 @@ void xe_sriov_vf_ccs_print(struct xe_device *xe, struct drm_printer *p)
 
 		drm_printf(p, "ccs %s bb suballoc info\n", ctx_id ? "write" : "read");
 		drm_printf(p, "-------------------------\n");
-		drm_suballoc_dump_debug_info(&bb_pool->base, p, xe_sa_manager_gpu_addr(bb_pool));
+		xe_mem_pool_dump(bb_pool, p);
 		drm_puts(p, "\n");
 	}
 }
diff --git a/drivers/gpu/drm/xe/xe_sriov_vf_ccs_types.h b/drivers/gpu/drm/xe/xe_sriov_vf_ccs_types.h
index 22c499943d2a..6fc8f97ef3f4 100644
--- a/drivers/gpu/drm/xe/xe_sriov_vf_ccs_types.h
+++ b/drivers/gpu/drm/xe/xe_sriov_vf_ccs_types.h
@@ -17,9 +17,6 @@ enum xe_sriov_vf_ccs_rw_ctxs {
 	XE_SRIOV_VF_CCS_CTX_COUNT
 };
 
-struct xe_migrate;
-struct xe_sa_manager;
-
 /**
  * struct xe_sriov_vf_ccs_ctx - VF CCS migration context data.
  */
@@ -33,7 +30,7 @@ struct xe_sriov_vf_ccs_ctx {
 	/** @mem: memory data */
 	struct {
 		/** @mem.ccs_bb_pool: Pool from which batch buffers are allocated. */
-		struct xe_sa_manager *ccs_bb_pool;
+		struct xe_mem_pool *ccs_bb_pool;
 	} mem;
 };
 
diff --git a/drivers/gpu/drm/xe/xe_step.c b/drivers/gpu/drm/xe/xe_step.c
index d0f888c31831..fb9c31613ca7 100644
--- a/drivers/gpu/drm/xe/xe_step.c
+++ b/drivers/gpu/drm/xe/xe_step.c
@@ -278,7 +278,7 @@ void xe_step_gmdid_get(struct xe_device *xe,
 	case STEP_##name:	\
 		return #name;
 
-const char *xe_step_name(enum xe_step step)
+const char *xe_step_name(enum intel_step step)
 {
 	switch (step) {
 	STEP_NAME_LIST(STEP_NAME_CASE);
diff --git a/drivers/gpu/drm/xe/xe_step.h b/drivers/gpu/drm/xe/xe_step.h
index 41f1c95c46e5..ea36b22cc297 100644
--- a/drivers/gpu/drm/xe/xe_step.h
+++ b/drivers/gpu/drm/xe/xe_step.h
@@ -18,8 +18,8 @@ void xe_step_pre_gmdid_get(struct xe_device *xe);
 void xe_step_gmdid_get(struct xe_device *xe,
 		       u32 graphics_gmdid_revid,
 		       u32 media_gmdid_revid);
-static inline u32 xe_step_to_gmdid(enum xe_step step) { return step - STEP_A0; }
+static inline u32 xe_step_to_gmdid(enum intel_step step) { return step - STEP_A0; }
 
-const char *xe_step_name(enum xe_step step);
+const char *xe_step_name(enum intel_step step);
 
 #endif
diff --git a/drivers/gpu/drm/xe/xe_step_types.h b/drivers/gpu/drm/xe/xe_step_types.h
index 43ca73850739..f60572b93523 100644
--- a/drivers/gpu/drm/xe/xe_step_types.h
+++ b/drivers/gpu/drm/xe/xe_step_types.h
@@ -8,6 +8,8 @@
 
 #include <linux/types.h>
 
+#include <drm/intel/step.h>
+
 struct xe_step_info {
 	u8 platform;
 	u8 graphics;
@@ -15,63 +17,4 @@ struct xe_step_info {
 	u8 basedie;
 };
 
-#define STEP_ENUM_VAL(name)  STEP_##name,
-
-/*
- * Always define four minor steppings 0-3 for each stepping to match GMD ID
- * spacing of values. See xe_step_gmdid_get().
- */
-#define STEP_NAME_LIST(func)		\
-	func(A0)			\
-	func(A1)			\
-	func(A2)			\
-	func(A3)			\
-	func(B0)			\
-	func(B1)			\
-	func(B2)			\
-	func(B3)			\
-	func(C0)			\
-	func(C1)			\
-	func(C2)			\
-	func(C3)			\
-	func(D0)			\
-	func(D1)			\
-	func(D2)			\
-	func(D3)			\
-	func(E0)			\
-	func(E1)			\
-	func(E2)			\
-	func(E3)			\
-	func(F0)			\
-	func(F1)			\
-	func(F2)			\
-	func(F3)			\
-	func(G0)			\
-	func(G1)			\
-	func(G2)			\
-	func(G3)			\
-	func(H0)			\
-	func(H1)			\
-	func(H2)			\
-	func(H3)			\
-	func(I0)			\
-	func(I1)			\
-	func(I2)			\
-	func(I3)			\
-	func(J0)			\
-	func(J1)			\
-	func(J2)			\
-	func(J3)
-
-/*
- * Symbolic steppings that do not match the hardware. These are valid both as gt
- * and display steppings as symbolic names.
- */
-enum xe_step {
-	STEP_NONE = 0,
-	STEP_NAME_LIST(STEP_ENUM_VAL)
-	STEP_FUTURE,
-	STEP_FOREVER,
-};
-
 #endif
diff --git a/drivers/gpu/drm/xe/xe_svm.c b/drivers/gpu/drm/xe/xe_svm.c
index 5933b2b6392b..ba67355f64cb 100644
--- a/drivers/gpu/drm/xe/xe_svm.c
+++ b/drivers/gpu/drm/xe/xe_svm.c
@@ -786,12 +786,12 @@ static int xe_svm_populate_devmem_pfn(struct drm_pagemap_devmem *devmem_allocati
 	struct xe_bo *bo = to_xe_bo(devmem_allocation);
 	struct ttm_resource *res = bo->ttm.resource;
 	struct list_head *blocks = &to_xe_ttm_vram_mgr_resource(res)->blocks;
+	struct xe_vram_region *vr = xe_map_resource_to_region(res);
+	struct gpu_buddy *buddy = vram_to_buddy(vr);
 	struct gpu_buddy_block *block;
 	int j = 0;
 
 	list_for_each_entry(block, blocks, link) {
-		struct xe_vram_region *vr = block->private;
-		struct gpu_buddy *buddy = vram_to_buddy(vr);
 		u64 block_pfn = block_offset_to_pfn(devmem_allocation->dpagemap,
 						    gpu_buddy_block_offset(block));
 		int i;
@@ -1061,9 +1061,7 @@ static int xe_drm_pagemap_populate_mm(struct drm_pagemap *dpagemap,
 	struct dma_fence *pre_migrate_fence = NULL;
 	struct xe_device *xe = vr->xe;
 	struct device *dev = xe->drm.dev;
-	struct gpu_buddy_block *block;
 	struct xe_validation_ctx vctx;
-	struct list_head *blocks;
 	struct drm_exec exec;
 	struct xe_bo *bo;
 	int err = 0, idx;
@@ -1100,10 +1098,6 @@ static int xe_drm_pagemap_populate_mm(struct drm_pagemap *dpagemap,
 					&dpagemap_devmem_ops, dpagemap, end - start,
 					pre_migrate_fence);
 
-		blocks = &to_xe_ttm_vram_mgr_resource(bo->ttm.resource)->blocks;
-		list_for_each_entry(block, blocks, link)
-			block->private = vr;
-
 		xe_bo_get(bo);
 
 		/* Ensure the device has a pm ref while there are device pages active. */
diff --git a/drivers/gpu/drm/xe/xe_sysctrl.c b/drivers/gpu/drm/xe/xe_sysctrl.c
new file mode 100644
index 000000000000..2bcef304eb9a
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_sysctrl.c
@@ -0,0 +1,101 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#include <linux/device.h>
+#include <linux/mutex.h>
+
+#include <drm/drm_managed.h>
+
+#include "regs/xe_sysctrl_regs.h"
+#include "xe_device.h"
+#include "xe_mmio.h"
+#include "xe_soc_remapper.h"
+#include "xe_sysctrl.h"
+#include "xe_sysctrl_mailbox.h"
+#include "xe_sysctrl_types.h"
+
+/**
+ * DOC: System Controller (sysctrl)
+ *
+ * System Controller (sysctrl) is a firmware-managed entity on Intel dGPUs
+ * responsible for selected low-level platform management functions.
+ * Communication between driver and System Controller is performed
+ * via a mailbox interface, enabling command and response exchange.
+ *
+ * This module provides initialization and support code for interacting
+ * with System Controller through the mailbox interface.
+ */
+static void sysctrl_fini(void *arg)
+{
+	struct xe_device *xe = arg;
+
+	xe->soc_remapper.set_sysctrl_region(xe, 0);
+}
+
+/**
+ * xe_sysctrl_init() - Initialize System Controller subsystem
+ * @xe: xe device instance
+ *
+ * Entry point for System Controller initialization, called from xe_device_probe.
+ * This function checks platform support and initializes the system controller.
+ *
+ * Return: 0 on success, error code on failure
+ */
+int xe_sysctrl_init(struct xe_device *xe)
+{
+	struct xe_tile *tile = xe_device_get_root_tile(xe);
+	struct xe_sysctrl *sc = &xe->sc;
+	int ret;
+
+	if (!xe->info.has_soc_remapper_sysctrl)
+		return 0;
+
+	if (!xe->info.has_sysctrl)
+		return 0;
+
+	xe->soc_remapper.set_sysctrl_region(xe, SYSCTRL_MAILBOX_INDEX);
+
+	ret = devm_add_action_or_reset(xe->drm.dev, sysctrl_fini, xe);
+	if (ret)
+		return ret;
+
+	sc->mmio = devm_kzalloc(xe->drm.dev, sizeof(*sc->mmio), GFP_KERNEL);
+	if (!sc->mmio)
+		return -ENOMEM;
+
+	xe_mmio_init(sc->mmio, tile, tile->mmio.regs, tile->mmio.regs_size);
+	sc->mmio->adj_offset = SYSCTRL_BASE;
+	sc->mmio->adj_limit = U32_MAX;
+
+	ret = devm_mutex_init(xe->drm.dev, &sc->cmd_lock);
+	if (ret)
+		return ret;
+
+	xe_sysctrl_mailbox_init(sc);
+
+	return 0;
+}
+
+/**
+ * xe_sysctrl_pm_resume() - System Controller resume handler
+ * @xe: xe device instance
+ *
+ * Invoked during system resume (S3/S4 to S0) and runtime resume from D3cold.
+ * Restores SoC remapper configuration and reinitializes mailbox interface.
+ */
+void xe_sysctrl_pm_resume(struct xe_device *xe)
+{
+	struct xe_sysctrl *sc = &xe->sc;
+
+	if (!xe->info.has_soc_remapper_sysctrl)
+		return;
+
+	if (!xe->info.has_sysctrl)
+		return;
+
+	xe->soc_remapper.set_sysctrl_region(xe, SYSCTRL_MAILBOX_INDEX);
+
+	xe_sysctrl_mailbox_init(sc);
+}
diff --git a/drivers/gpu/drm/xe/xe_sysctrl.h b/drivers/gpu/drm/xe/xe_sysctrl.h
new file mode 100644
index 000000000000..f3b0f3716b2f
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_sysctrl.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#ifndef _XE_SYSCTRL_H_
+#define _XE_SYSCTRL_H_
+
+#include <linux/container_of.h>
+
+#include "xe_device_types.h"
+#include "xe_sysctrl_types.h"
+
+static inline struct xe_device *sc_to_xe(struct xe_sysctrl *sc)
+{
+	return container_of(sc, struct xe_device, sc);
+}
+
+int xe_sysctrl_init(struct xe_device *xe);
+void xe_sysctrl_pm_resume(struct xe_device *xe);
+
+#endif
diff --git a/drivers/gpu/drm/xe/xe_sysctrl_mailbox.c b/drivers/gpu/drm/xe/xe_sysctrl_mailbox.c
new file mode 100644
index 000000000000..3caa9f15875f
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_sysctrl_mailbox.c
@@ -0,0 +1,371 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#include <linux/bitfield.h>
+#include <linux/cleanup.h>
+#include <linux/minmax.h>
+#include <linux/slab.h>
+#include <linux/string.h>
+
+#include "regs/xe_sysctrl_regs.h"
+#include "xe_device.h"
+#include "xe_mmio.h"
+#include "xe_pm.h"
+#include "xe_printk.h"
+#include "xe_sysctrl.h"
+#include "xe_sysctrl_mailbox.h"
+#include "xe_sysctrl_mailbox_types.h"
+
+struct xe_sysctrl_mailbox_msg_hdr {
+	__le32 data;
+} __packed;
+
+#define XE_SYSCTRL_HDR_GROUP_ID(hdr) \
+	FIELD_GET(SYSCTRL_HDR_GROUP_ID_MASK, le32_to_cpu((hdr)->data))
+
+#define XE_SYSCTRL_HDR_COMMAND(hdr) \
+	FIELD_GET(SYSCTRL_HDR_COMMAND_MASK, le32_to_cpu((hdr)->data))
+
+#define XE_SYSCTRL_HDR_IS_RESPONSE(hdr) \
+	FIELD_GET(SYSCTRL_HDR_IS_RESPONSE, le32_to_cpu((hdr)->data))
+
+#define XE_SYSCTRL_HDR_RESULT(hdr) \
+	FIELD_GET(SYSCTRL_HDR_RESULT_MASK, le32_to_cpu((hdr)->data))
+
+static bool sysctrl_wait_bit_clear(struct xe_sysctrl *sc, u32 bit_mask,
+				   unsigned int timeout_ms)
+{
+	int ret;
+
+	ret = xe_mmio_wait32_not(sc->mmio, SYSCTRL_MB_CTRL, bit_mask, bit_mask,
+				 timeout_ms * 1000, NULL, false);
+
+	return ret == 0;
+}
+
+static bool sysctrl_wait_bit_set(struct xe_sysctrl *sc, u32 bit_mask,
+				 unsigned int timeout_ms)
+{
+	int ret;
+
+	ret = xe_mmio_wait32(sc->mmio, SYSCTRL_MB_CTRL, bit_mask, bit_mask,
+			     timeout_ms * 1000, NULL, false);
+
+	return ret == 0;
+}
+
+static int sysctrl_write_frame(struct xe_sysctrl *sc, const void *frame,
+			       size_t len)
+{
+	static const struct xe_reg regs[] = {
+		SYSCTRL_MB_DATA0, SYSCTRL_MB_DATA1, SYSCTRL_MB_DATA2, SYSCTRL_MB_DATA3
+	};
+	struct xe_device *xe = sc_to_xe(sc);
+	u32 val[XE_SYSCTRL_MB_FRAME_SIZE / sizeof(u32)] = {0};
+	u32 dw = DIV_ROUND_UP(len, sizeof(u32));
+	u32 i;
+
+	xe_assert(xe, len > 0 && len <= XE_SYSCTRL_MB_FRAME_SIZE);
+
+	memcpy(val, frame, len);
+
+	for (i = 0; i < dw; i++)
+		xe_mmio_write32(sc->mmio, regs[i], val[i]);
+
+	return 0;
+}
+
+static int sysctrl_read_frame(struct xe_sysctrl *sc, void *frame,
+			      size_t len)
+{
+	static const struct xe_reg regs[] = {
+		SYSCTRL_MB_DATA0, SYSCTRL_MB_DATA1, SYSCTRL_MB_DATA2, SYSCTRL_MB_DATA3
+	};
+	struct xe_device *xe = sc_to_xe(sc);
+	u32 val[XE_SYSCTRL_MB_FRAME_SIZE / sizeof(u32)] = {0};
+	u32 dw = DIV_ROUND_UP(len, sizeof(u32));
+	u32 i;
+
+	xe_assert(xe, len > 0 && len <= XE_SYSCTRL_MB_FRAME_SIZE);
+
+	for (i = 0; i < dw; i++)
+		val[i] = xe_mmio_read32(sc->mmio, regs[i]);
+
+	memcpy(frame, val, len);
+
+	return 0;
+}
+
+static void sysctrl_clear_response(struct xe_sysctrl *sc)
+{
+	xe_mmio_rmw32(sc->mmio, SYSCTRL_MB_CTRL, SYSCTRL_MB_CTRL_RUN_BUSY_OUT, 0);
+}
+
+static int sysctrl_prepare_command(struct xe_device *xe,
+				   u8 group_id, u8 command,
+				   const void *data_in, size_t data_in_len,
+				   u8 **mbox_cmd, size_t *cmd_size)
+{
+	struct xe_sysctrl_mailbox_msg_hdr *hdr;
+	size_t size;
+	u8 *buffer;
+
+	xe_assert(xe, command <= SYSCTRL_HDR_COMMAND_MAX);
+
+	if (data_in_len > XE_SYSCTRL_MB_MAX_MESSAGE_SIZE - sizeof(*hdr)) {
+		xe_err(xe, "sysctrl: Input data too large: %zu bytes\n", data_in_len);
+		return -EINVAL;
+	}
+
+	size = sizeof(*hdr) + data_in_len;
+
+	buffer = kmalloc(size, GFP_KERNEL);
+	if (!buffer)
+		return -ENOMEM;
+
+	hdr = (struct xe_sysctrl_mailbox_msg_hdr *)buffer;
+	hdr->data = cpu_to_le32(FIELD_PREP(SYSCTRL_HDR_GROUP_ID_MASK, group_id) |
+				     FIELD_PREP(SYSCTRL_HDR_COMMAND_MASK, command));
+
+	if (data_in && data_in_len)
+		memcpy(buffer + sizeof(*hdr), data_in, data_in_len);
+
+	*mbox_cmd = buffer;
+	*cmd_size = size;
+
+	return 0;
+}
+
+static int sysctrl_send_frames(struct xe_sysctrl *sc,
+			       const u8 *mbox_cmd,
+			       size_t cmd_size, unsigned int timeout_ms)
+{
+	struct xe_device *xe = sc_to_xe(sc);
+	u32 ctrl_reg, total_frames, frame;
+	size_t bytes_sent, frame_size;
+
+	total_frames = DIV_ROUND_UP(cmd_size, XE_SYSCTRL_MB_FRAME_SIZE);
+
+	if (!sysctrl_wait_bit_clear(sc, SYSCTRL_MB_CTRL_RUN_BUSY, timeout_ms)) {
+		xe_err(xe, "sysctrl: Mailbox busy\n");
+		return -EBUSY;
+	}
+
+	sc->phase_bit ^= 1;
+	bytes_sent = 0;
+
+	for (frame = 0; frame < total_frames; frame++) {
+		frame_size = min_t(size_t, cmd_size - bytes_sent, XE_SYSCTRL_MB_FRAME_SIZE);
+
+		if (sysctrl_write_frame(sc, mbox_cmd + bytes_sent, frame_size)) {
+			xe_err(xe, "sysctrl: Failed to write frame %u\n", frame);
+			sc->phase_bit = 0;
+			return -EIO;
+		}
+
+		ctrl_reg = SYSCTRL_MB_CTRL_RUN_BUSY |
+			   REG_FIELD_PREP(SYSCTRL_FRAME_CURRENT_MASK, frame) |
+			   REG_FIELD_PREP(SYSCTRL_FRAME_TOTAL_MASK, total_frames - 1) |
+			   SYSCTRL_MB_CTRL_CMD |
+			   (sc->phase_bit ? SYSCTRL_FRAME_PHASE : 0);
+
+		xe_mmio_write32(sc->mmio, SYSCTRL_MB_CTRL, ctrl_reg);
+
+		if (!sysctrl_wait_bit_clear(sc, SYSCTRL_MB_CTRL_RUN_BUSY, timeout_ms)) {
+			xe_err(xe, "sysctrl: Frame %u acknowledgment timeout\n", frame);
+			sc->phase_bit = 0;
+			return -ETIMEDOUT;
+		}
+
+		bytes_sent += frame_size;
+	}
+
+	return 0;
+}
+
+static int sysctrl_process_frame(struct xe_sysctrl *sc, void *out,
+				 size_t frame_size, unsigned int timeout_ms,
+				 bool *done)
+{
+	u32 curr_frame, total_frames, ctrl_reg;
+	struct xe_device *xe = sc_to_xe(sc);
+	int ret;
+
+	if (!sysctrl_wait_bit_set(sc, SYSCTRL_MB_CTRL_RUN_BUSY_OUT, timeout_ms)) {
+		xe_err(xe, "sysctrl: Response frame timeout\n");
+		return -ETIMEDOUT;
+	}
+
+	ctrl_reg = xe_mmio_read32(sc->mmio, SYSCTRL_MB_CTRL);
+	total_frames = FIELD_GET(SYSCTRL_FRAME_TOTAL_MASK, ctrl_reg);
+	curr_frame = FIELD_GET(SYSCTRL_FRAME_CURRENT_MASK, ctrl_reg);
+
+	ret = sysctrl_read_frame(sc, out, frame_size);
+	if (ret)
+		return ret;
+
+	sysctrl_clear_response(sc);
+
+	if (curr_frame == total_frames)
+		*done = true;
+
+	return 0;
+}
+
+static int sysctrl_receive_frames(struct xe_sysctrl *sc,
+				  const struct xe_sysctrl_mailbox_msg_hdr *req,
+				  void *data_out, size_t data_out_len,
+				  size_t *rdata_len, unsigned int timeout_ms)
+{
+	struct xe_sysctrl_mailbox_msg_hdr *hdr;
+	struct xe_device *xe = sc_to_xe(sc);
+	size_t remain = sizeof(*hdr) + data_out_len;
+	u8 *buffer __free(kfree) = kzalloc(remain, GFP_KERNEL);
+	size_t frame_size;
+	bool done = false;
+	int ret = 0;
+	u8 *out;
+
+	if (!buffer)
+		return -ENOMEM;
+
+	out = buffer;
+	while (!done && remain) {
+		frame_size = min_t(size_t, remain, XE_SYSCTRL_MB_FRAME_SIZE);
+
+		ret = sysctrl_process_frame(sc, out, frame_size, timeout_ms,
+					    &done);
+		if (ret)
+			return ret;
+
+		remain -= frame_size;
+		out += frame_size;
+	}
+
+	hdr = (struct xe_sysctrl_mailbox_msg_hdr *)buffer;
+
+	if (!XE_SYSCTRL_HDR_IS_RESPONSE(hdr) ||
+	    XE_SYSCTRL_HDR_GROUP_ID(hdr) != XE_SYSCTRL_HDR_GROUP_ID(req) ||
+	    XE_SYSCTRL_HDR_COMMAND(hdr) != XE_SYSCTRL_HDR_COMMAND(req)) {
+		xe_err(xe, "sysctrl: Response header mismatch\n");
+		return -EPROTO;
+	}
+
+	if (XE_SYSCTRL_HDR_RESULT(hdr) != 0) {
+		xe_err(xe, "sysctrl: Firmware error: 0x%02lx\n",
+		       XE_SYSCTRL_HDR_RESULT(hdr));
+		return -EIO;
+	}
+
+	memcpy(data_out, hdr + 1, data_out_len);
+	*rdata_len = out - buffer - sizeof(*hdr);
+
+	return 0;
+}
+
+static int sysctrl_send_command(struct xe_sysctrl *sc,
+				const u8 *mbox_cmd, size_t cmd_size,
+				void *data_out, size_t data_out_len,
+				size_t *rdata_len, unsigned int timeout_ms)
+{
+	const struct xe_sysctrl_mailbox_msg_hdr *hdr;
+	size_t received;
+	int ret;
+
+	ret = sysctrl_send_frames(sc, mbox_cmd, cmd_size, timeout_ms);
+	if (ret)
+		return ret;
+
+	if (!data_out || !rdata_len)
+		return 0;
+
+	hdr = (const struct xe_sysctrl_mailbox_msg_hdr *)mbox_cmd;
+
+	ret = sysctrl_receive_frames(sc, hdr, data_out, data_out_len,
+				     &received, timeout_ms);
+	if (ret)
+		return ret;
+
+	*rdata_len = received;
+
+	return 0;
+}
+
+/**
+ * xe_sysctrl_mailbox_init - Initialize System Controller mailbox interface
+ * @sc: System controller structure
+ *
+ * Initialize system controller mailbox interface for communication.
+ */
+void xe_sysctrl_mailbox_init(struct xe_sysctrl *sc)
+{
+	u32 ctrl_reg;
+
+	ctrl_reg = xe_mmio_read32(sc->mmio, SYSCTRL_MB_CTRL);
+	sc->phase_bit = (ctrl_reg & SYSCTRL_FRAME_PHASE) ? 1 : 0;
+}
+
+/**
+ * xe_sysctrl_send_command() - Send mailbox command to System Controller
+ * @sc: System Controller instance
+ * @cmd: Command descriptor containing request header and payload buffers
+ * @rdata_len: Pointer to store actual response data length
+ *
+ * Sends a mailbox command to System Controller firmware using
+ * System Controller mailbox and waits for a response.
+ *
+ * Request payload is provided via @cmd->data_in and @cmd->data_in_len.
+ * If a response is expected, @cmd->data_out must point to a buffer of
+ * size @cmd->data_out_len supplied by caller.
+ *
+ * On success, @rdata_len is updated with number of valid response bytes
+ * returned by firmware, bounded by @cmd->data_out_len.
+ *
+ * Return: 0 on success, or negative errno on failure.
+ */
+int xe_sysctrl_send_command(struct xe_sysctrl *sc,
+			    struct xe_sysctrl_mailbox_command *cmd,
+			    size_t *rdata_len)
+{
+	struct xe_device *xe = sc_to_xe(sc);
+	u8 group_id, command_code;
+	u8 *mbox_cmd = NULL;
+	size_t cmd_size = 0;
+	int ret;
+
+	guard(xe_pm_runtime_noresume)(xe);
+
+	if (!xe->info.has_sysctrl)
+		return -ENODEV;
+
+	xe_assert(xe, cmd->data_in || cmd->data_out);
+	xe_assert(xe, !cmd->data_in || cmd->data_in_len);
+	xe_assert(xe, !cmd->data_out || cmd->data_out_len);
+
+	group_id = XE_SYSCTRL_APP_HDR_GROUP_ID(&cmd->header);
+	command_code = XE_SYSCTRL_APP_HDR_COMMAND(&cmd->header);
+
+	might_sleep();
+
+	ret = sysctrl_prepare_command(xe, group_id, command_code,
+				      cmd->data_in, cmd->data_in_len,
+				      &mbox_cmd, &cmd_size);
+	if (ret) {
+		xe_err(xe, "sysctrl: Failed to prepare command: %pe\n", ERR_PTR(ret));
+		return ret;
+	}
+
+	guard(mutex)(&sc->cmd_lock);
+
+	ret = sysctrl_send_command(sc, mbox_cmd, cmd_size,
+				   cmd->data_out, cmd->data_out_len, rdata_len,
+				   XE_SYSCTRL_MB_DEFAULT_TIMEOUT_MS);
+	if (ret)
+		xe_err(xe, "sysctrl: Mailbox command failed: %pe\n", ERR_PTR(ret));
+
+	kfree(mbox_cmd);
+
+	return ret;
+}
diff --git a/drivers/gpu/drm/xe/xe_sysctrl_mailbox.h b/drivers/gpu/drm/xe/xe_sysctrl_mailbox.h
new file mode 100644
index 000000000000..f67e9234de48
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_sysctrl_mailbox.h
@@ -0,0 +1,31 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#ifndef _XE_SYSCTRL_MAILBOX_H_
+#define _XE_SYSCTRL_MAILBOX_H_
+
+#include <linux/bitfield.h>
+#include <linux/types.h>
+
+#include "abi/xe_sysctrl_abi.h"
+
+struct xe_sysctrl;
+struct xe_sysctrl_mailbox_command;
+
+#define XE_SYSCTRL_APP_HDR_GROUP_ID(hdr) \
+	FIELD_GET(APP_HDR_GROUP_ID_MASK, (hdr)->data)
+
+#define XE_SYSCTRL_APP_HDR_COMMAND(hdr) \
+	FIELD_GET(APP_HDR_COMMAND_MASK, (hdr)->data)
+
+#define XE_SYSCTRL_APP_HDR_VERSION(hdr) \
+	FIELD_GET(APP_HDR_VERSION_MASK, (hdr)->data)
+
+void xe_sysctrl_mailbox_init(struct xe_sysctrl *sc);
+int xe_sysctrl_send_command(struct xe_sysctrl *sc,
+			    struct xe_sysctrl_mailbox_command *cmd,
+			    size_t *rdata_len);
+
+#endif
diff --git a/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h b/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h
new file mode 100644
index 000000000000..89456aec6097
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_sysctrl_mailbox_types.h
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#ifndef _XE_SYSCTRL_MAILBOX_TYPES_H_
+#define _XE_SYSCTRL_MAILBOX_TYPES_H_
+
+#include <linux/types.h>
+
+#include "abi/xe_sysctrl_abi.h"
+
+/**
+ * struct xe_sysctrl_mailbox_command - System Controller mailbox command
+ */
+struct xe_sysctrl_mailbox_command {
+	/** @header: Application message header containing command information */
+	struct xe_sysctrl_app_msg_hdr header;
+
+	/** @data_in: Pointer to input payload data (can be NULL if no input data) */
+	void *data_in;
+
+	/** @data_in_len: Size of input payload in bytes (0 if no input data) */
+	size_t data_in_len;
+
+	/** @data_out: Pointer to output buffer for response data (can be NULL if no response) */
+	void *data_out;
+
+	/** @data_out_len: Size of output buffer in bytes (0 if no response expected) */
+	size_t data_out_len;
+};
+
+#define XE_SYSCTRL_MB_FRAME_SIZE	16
+#define XE_SYSCTRL_MB_MAX_FRAMES	64
+#define XE_SYSCTRL_MB_MAX_MESSAGE_SIZE	\
+	(XE_SYSCTRL_MB_FRAME_SIZE * XE_SYSCTRL_MB_MAX_FRAMES)
+
+#define XE_SYSCTRL_MB_DEFAULT_TIMEOUT_MS	500
+
+#endif
diff --git a/drivers/gpu/drm/xe/xe_sysctrl_types.h b/drivers/gpu/drm/xe/xe_sysctrl_types.h
new file mode 100644
index 000000000000..8217f6befe70
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_sysctrl_types.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#ifndef _XE_SYSCTRL_TYPES_H_
+#define _XE_SYSCTRL_TYPES_H_
+
+#include <linux/mutex.h>
+#include <linux/types.h>
+
+struct xe_mmio;
+
+/**
+ * struct xe_sysctrl - System Controller driver context
+ *
+ * This structure maintains the runtime state for System Controller
+ * communication. All fields are initialized during xe_sysctrl_init()
+ * and protected appropriately for concurrent access.
+ */
+struct xe_sysctrl {
+	/** @mmio: MMIO region for system control registers */
+	struct xe_mmio *mmio;
+
+	/** @cmd_lock: Mutex protecting mailbox command operations */
+	struct mutex cmd_lock;
+
+	/** @phase_bit: Message boundary phase toggle bit (0 or 1) */
+	bool phase_bit;
+};
+
+#endif
diff --git a/drivers/gpu/drm/xe/xe_tlb_inval.c b/drivers/gpu/drm/xe/xe_tlb_inval.c
index 10dcd4abb00f..bbd21d393062 100644
--- a/drivers/gpu/drm/xe/xe_tlb_inval.c
+++ b/drivers/gpu/drm/xe/xe_tlb_inval.c
@@ -529,7 +529,7 @@ int xe_tlb_inval_range_tilemask_submit(struct xe_device *xe, u32 asid,
 	struct xe_tile *tile;
 	u32 fence_id = 0;
 	u8 id;
-	int err;
+	int err = 0;
 
 	batch->num_fences = 0;
 	if (!tile_mask)
diff --git a/drivers/gpu/drm/xe/xe_tuning.c b/drivers/gpu/drm/xe/xe_tuning.c
index f8de6a4bf189..ce39b77a084a 100644
--- a/drivers/gpu/drm/xe/xe_tuning.c
+++ b/drivers/gpu/drm/xe/xe_tuning.c
@@ -43,7 +43,7 @@ static const struct xe_rtp_entry_sr gt_tunings[] = {
 				   REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f)))
 	},
 	{ XE_RTP_NAME("Tuning: Compression Overfetch"),
-	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, XE_RTP_END_VERSION_UNDEFINED),
+	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 3499),
 		       FUNC(xe_rtp_match_has_flat_ccs)),
 	  XE_RTP_ACTIONS(CLR(CCCHKNREG1, ENCOMPPERFFIX),
 			 SET(CCCHKNREG1, L3CMPCTRL))
@@ -97,7 +97,7 @@ static const struct xe_rtp_entry_sr gt_tunings[] = {
 	{ XE_RTP_NAME("Tuning: Set STLB Bank Hash Mode to 4KB"),
 	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3510, XE_RTP_END_VERSION_UNDEFINED),
 		       IS_INTEGRATED),
-	  XE_RTP_ACTIONS(FIELD_SET(XEHP_GAMSTLB_CTRL, BANK_HASH_MODE,
+	  XE_RTP_ACTIONS(FIELD_SET(GAMSTLB_CTRL, BANK_HASH_MODE,
 				   BANK_HASH_4KB_MODE))
 	},
 };
@@ -124,6 +124,11 @@ static const struct xe_rtp_entry_sr engine_tunings[] = {
 			     GHWSP_CSB_REPORT_DIS,
 			     XE_RTP_ACTION_FLAG(ENGINE_BASE)))
 	},
+	{ XE_RTP_NAME("Tuning: TileY 2x2 Walk"),
+	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(3510, XE_RTP_END_VERSION_UNDEFINED),
+		       FUNC(xe_rtp_match_first_render_or_compute)),
+	  XE_RTP_ACTIONS(SET(TDL_TSL_CHICKEN2, TILEY_LOCALID))
+	},
 };
 
 static const struct xe_rtp_entry_sr lrc_tunings[] = {
diff --git a/drivers/gpu/drm/xe/xe_tuning.h b/drivers/gpu/drm/xe/xe_tuning.h
index c1cc5927fda7..d18e187debf6 100644
--- a/drivers/gpu/drm/xe/xe_tuning.h
+++ b/drivers/gpu/drm/xe/xe_tuning.h
@@ -3,8 +3,8 @@
  * Copyright © 2022 Intel Corporation
  */
 
-#ifndef _XE_TUNING_
-#define _XE_TUNING_
+#ifndef _XE_TUNING_H_
+#define _XE_TUNING_H_
 
 struct drm_printer;
 struct xe_gt;
diff --git a/drivers/gpu/drm/xe/xe_uc_fw.c b/drivers/gpu/drm/xe/xe_uc_fw.c
index 9cebb2490245..df2aa196f6f9 100644
--- a/drivers/gpu/drm/xe/xe_uc_fw.c
+++ b/drivers/gpu/drm/xe/xe_uc_fw.c
@@ -214,6 +214,17 @@ static struct xe_device *uc_fw_to_xe(struct xe_uc_fw *uc_fw)
 	return gt_to_xe(uc_fw_to_gt(uc_fw));
 }
 
+#if IS_ENABLED(CONFIG_DRM_XE_DEBUG_GUC)
+void xe_uc_fw_change_status(struct xe_uc_fw *uc_fw, enum xe_uc_fw_status status)
+{
+	xe_gt_dbg(uc_fw_to_gt(uc_fw), "%s %s->%s\n",
+		  xe_uc_fw_type_repr(uc_fw->type),
+		  xe_uc_fw_status_repr(uc_fw->status),
+		  xe_uc_fw_status_repr(status));
+	uc_fw->__status = status;
+}
+#endif
+
 static void
 uc_fw_auto_select(struct xe_device *xe, struct xe_uc_fw *uc_fw)
 {
diff --git a/drivers/gpu/drm/xe/xe_uc_fw.h b/drivers/gpu/drm/xe/xe_uc_fw.h
index 6195e353f269..bb281b72a677 100644
--- a/drivers/gpu/drm/xe/xe_uc_fw.h
+++ b/drivers/gpu/drm/xe/xe_uc_fw.h
@@ -25,11 +25,15 @@ static inline u32 xe_uc_fw_rsa_offset(struct xe_uc_fw *uc_fw)
 	return sizeof(struct uc_css_header) + uc_fw->ucode_size + uc_fw->css_offset;
 }
 
+#if IS_ENABLED(CONFIG_DRM_XE_DEBUG_GUC)
+void xe_uc_fw_change_status(struct xe_uc_fw *uc_fw, enum xe_uc_fw_status status);
+#else
 static inline void xe_uc_fw_change_status(struct xe_uc_fw *uc_fw,
 					  enum xe_uc_fw_status status)
 {
 	uc_fw->__status = status;
 }
+#endif
 
 static inline
 const char *xe_uc_fw_status_repr(enum xe_uc_fw_status status)
diff --git a/drivers/gpu/drm/xe/xe_uc_fw_abi.h b/drivers/gpu/drm/xe/xe_uc_fw_abi.h
index 3c9a63d13032..74b888904fdc 100644
--- a/drivers/gpu/drm/xe/xe_uc_fw_abi.h
+++ b/drivers/gpu/drm/xe/xe_uc_fw_abi.h
@@ -3,8 +3,8 @@
  * Copyright © 2022 Intel Corporation
  */
 
-#ifndef _XE_UC_FW_ABI_H
-#define _XE_UC_FW_ABI_H
+#ifndef _XE_UC_FW_ABI_H_
+#define _XE_UC_FW_ABI_H_
 
 #include <linux/build_bug.h>
 #include <linux/types.h>
diff --git a/drivers/gpu/drm/xe/xe_vm.c b/drivers/gpu/drm/xe/xe_vm.c
index 56e2db50bb36..c3836f6eab35 100644
--- a/drivers/gpu/drm/xe/xe_vm.c
+++ b/drivers/gpu/drm/xe/xe_vm.c
@@ -634,9 +634,9 @@ void xe_vm_add_fault_entry_pf(struct xe_vm *vm, struct xe_pagefault *pf)
 	e->address_precision = SZ_4K;
 	e->access_type = pf->consumer.access_type;
 	e->fault_type = FIELD_GET(XE_PAGEFAULT_TYPE_MASK,
-				  pf->consumer.fault_type_level),
+				  pf->consumer.fault_type_level);
 	e->fault_level = FIELD_GET(XE_PAGEFAULT_LEVEL_MASK,
-				   pf->consumer.fault_type_level),
+				   pf->consumer.fault_type_level);
 
 	list_add_tail(&e->list, &vm->faults.list);
 	vm->faults.len++;
@@ -1399,9 +1399,9 @@ static u16 pde_pat_index(struct xe_bo *bo)
 	 * something which is always safe).
 	 */
 	if (!xe_bo_is_vram(bo) && bo->ttm.ttm->caching == ttm_cached)
-		pat_index = xe->pat.idx[XE_CACHE_WB];
+		pat_index = xe_cache_pat_idx(xe, XE_CACHE_WB);
 	else
-		pat_index = xe->pat.idx[XE_CACHE_NONE];
+		pat_index = xe_cache_pat_idx(xe, XE_CACHE_NONE);
 
 	xe_assert(xe, pat_index <= 3);
 
@@ -3658,6 +3658,8 @@ static int vm_bind_ioctl_check_args(struct xe_device *xe, struct xe_vm *vm,
 				 op == DRM_XE_VM_BIND_OP_MAP_USERPTR) ||
 		    XE_IOCTL_DBG(xe, coh_mode == XE_COH_NONE &&
 				 op == DRM_XE_VM_BIND_OP_MAP_USERPTR) ||
+		    XE_IOCTL_DBG(xe, !IS_DGFX(xe) && coh_mode == XE_COH_NONE &&
+				 is_cpu_addr_mirror) ||
 		    XE_IOCTL_DBG(xe, xe_device_is_l2_flush_optimized(xe) &&
 				 (op == DRM_XE_VM_BIND_OP_MAP_USERPTR ||
 				  is_cpu_addr_mirror) &&
@@ -4156,7 +4158,8 @@ int xe_vm_get_property_ioctl(struct drm_device *drm, void *data,
 	int ret = 0;
 
 	if (XE_IOCTL_DBG(xe, (args->reserved[0] || args->reserved[1] ||
-			      args->reserved[2])))
+			      args->reserved[2] || args->extensions ||
+			      args->pad)))
 		return -EINVAL;
 
 	vm = xe_vm_lookup(xef, args->vm_id);
@@ -4203,7 +4206,7 @@ struct dma_fence *xe_vm_bind_kernel_bo(struct xe_vm *vm, struct xe_bo *bo,
 
 	ops = vm_bind_ioctl_ops_create(vm, &vops, bo, 0, addr, xe_bo_size(bo),
 				       DRM_XE_VM_BIND_OP_MAP, 0, 0,
-				       vm->xe->pat.idx[cache_lvl]);
+				       xe_cache_pat_idx(vm->xe, cache_lvl));
 	if (IS_ERR(ops)) {
 		err = PTR_ERR(ops);
 		goto release_vm_lock;
@@ -4406,7 +4409,7 @@ struct xe_vm_snapshot {
 #define XE_VM_SNAP_FLAG_IS_NULL		BIT(2)
 		unsigned long flags;
 		int uapi_mem_region;
-		int pat_index;
+		u16 pat_index;
 		int cpu_caching;
 		struct xe_bo *bo;
 		void *data;
diff --git a/drivers/gpu/drm/xe/xe_vm_madvise.c b/drivers/gpu/drm/xe/xe_vm_madvise.c
index 66f00d3f5c07..c78906dea82b 100644
--- a/drivers/gpu/drm/xe/xe_vm_madvise.c
+++ b/drivers/gpu/drm/xe/xe_vm_madvise.c
@@ -621,6 +621,45 @@ static int xe_madvise_purgeable_retained_to_user(const struct xe_madvise_details
 	return 0;
 }
 
+static bool check_pat_args_are_sane(struct xe_device *xe,
+				    struct xe_vmas_in_madvise_range *madvise_range,
+				    u16 pat_index)
+{
+	u16 coh_mode = xe_pat_index_get_coh_mode(xe, pat_index);
+	int i;
+
+	/*
+	 * Using coh_none with CPU cached buffers is not allowed on iGPU.
+	 * On iGPU the GPU shares the LLC with the CPU, so with coh_none
+	 * the GPU bypasses CPU caches and reads directly from DRAM,
+	 * potentially seeing stale sensitive data from previously freed
+	 * pages. On dGPU this restriction does not apply, because the
+	 * platform does not provide a non-coherent system memory access
+	 * path that would violate the DMA coherency contract.
+	 */
+	if (coh_mode != XE_COH_NONE || IS_DGFX(xe))
+		return true;
+
+	for (i = 0; i < madvise_range->num_vmas; i++) {
+		struct xe_vma *vma = madvise_range->vmas[i];
+		struct xe_bo *bo = xe_vma_bo(vma);
+
+		if (bo) {
+			/* BO with WB caching + COH_NONE is not allowed */
+			if (XE_IOCTL_DBG(xe, bo->cpu_caching == DRM_XE_GEM_CPU_CACHING_WB))
+				return false;
+			/* Imported dma-buf without caching info, assume cached */
+			if (XE_IOCTL_DBG(xe, !bo->cpu_caching))
+				return false;
+		} else if (XE_IOCTL_DBG(xe, xe_vma_is_cpu_addr_mirror(vma) ||
+					    xe_vma_is_userptr(vma)))
+			/* System memory (userptr/SVM) is always CPU cached */
+			return false;
+	}
+
+	return true;
+}
+
 static bool check_bo_args_are_sane(struct xe_vm *vm, struct xe_vma **vmas,
 				   int num_vmas, u32 atomic_val)
 {
@@ -750,6 +789,14 @@ int xe_vm_madvise_ioctl(struct drm_device *dev, void *data, struct drm_file *fil
 		}
 	}
 
+	if (args->type == DRM_XE_MEM_RANGE_ATTR_PAT) {
+		if (!check_pat_args_are_sane(xe, &madvise_range,
+					     args->pat_index.val)) {
+			err = -EINVAL;
+			goto free_vmas;
+		}
+	}
+
 	if (madvise_range.has_bo_vmas) {
 		if (args->type == DRM_XE_MEM_RANGE_ATTR_ATOMIC) {
 			if (!check_bo_args_are_sane(vm, madvise_range.vmas,
diff --git a/drivers/gpu/drm/xe/xe_vm_types.h b/drivers/gpu/drm/xe/xe_vm_types.h
index a94827d7fbec..635ed29b9a69 100644
--- a/drivers/gpu/drm/xe/xe_vm_types.h
+++ b/drivers/gpu/drm/xe/xe_vm_types.h
@@ -412,10 +412,11 @@ struct xe_vm {
 struct xe_vma_op_map {
 	/** @vma: VMA to map */
 	struct xe_vma *vma;
+	/** @vma_flags: VMA flags for this operation */
 	unsigned int vma_flags;
 	/** @immediate: Immediate bind */
 	bool immediate;
-	/** @read_only: Read only */
+	/** @invalidate_on_bind: Invalidate on bind */
 	bool invalidate_on_bind;
 	/** @request_decompress: schedule decompression for GPU map */
 	bool request_decompress;
diff --git a/drivers/gpu/drm/xe/xe_vram.c b/drivers/gpu/drm/xe/xe_vram.c
index 0538dcb8b18c..23eb7edbdd57 100644
--- a/drivers/gpu/drm/xe/xe_vram.c
+++ b/drivers/gpu/drm/xe/xe_vram.c
@@ -13,6 +13,7 @@
 #include "regs/xe_gt_regs.h"
 #include "regs/xe_regs.h"
 #include "xe_assert.h"
+#include "xe_bo.h"
 #include "xe_device.h"
 #include "xe_force_wake.h"
 #include "xe_gt_mcr.h"
@@ -249,6 +250,27 @@ static int vram_region_init(struct xe_device *xe, struct xe_vram_region *vram,
 	return 0;
 }
 
+/**
+ * xe_map_resource_to_region - Map ttm resource to vram memory region
+ * @res: The ttm resource
+ *
+ * Get vram memory region using vram memory manager managing this resource
+ *
+ * Returns: pointer to xe_vram_region
+ */
+struct xe_vram_region *xe_map_resource_to_region(struct ttm_resource *res)
+{
+	struct xe_device *xe = ttm_to_xe_device(res->bo->bdev);
+	struct ttm_resource_manager *mgr;
+	struct xe_ttm_vram_mgr *vram_mgr;
+
+	xe_assert(xe, mem_type_is_vram(res->mem_type));
+	mgr = ttm_manager_type(&xe->ttm, res->mem_type);
+	vram_mgr = to_xe_ttm_vram_mgr(mgr);
+
+	return container_of(vram_mgr, struct xe_vram_region, ttm);
+}
+
 /**
  * xe_vram_probe() - Probe VRAM configuration
  * @xe: the &xe_device
diff --git a/drivers/gpu/drm/xe/xe_vram.h b/drivers/gpu/drm/xe/xe_vram.h
index 72860f714fc6..dd1c8bf17922 100644
--- a/drivers/gpu/drm/xe/xe_vram.h
+++ b/drivers/gpu/drm/xe/xe_vram.h
@@ -10,7 +10,9 @@
 
 struct xe_device;
 struct xe_vram_region;
+struct ttm_resource;
 
+struct xe_vram_region *xe_map_resource_to_region(struct ttm_resource *res);
 int xe_vram_probe(struct xe_device *xe);
 
 struct xe_vram_region *xe_vram_region_alloc(struct xe_device *xe, u8 id, u32 placement);
diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
index 546296f0220b..49f5e3e4c7cc 100644
--- a/drivers/gpu/drm/xe/xe_wa.c
+++ b/drivers/gpu/drm/xe/xe_wa.c
@@ -601,6 +601,19 @@ static const struct xe_rtp_entry_sr engine_was[] = {
 		       FUNC(xe_rtp_match_first_render_or_compute)),
 	  XE_RTP_ACTIONS(SET(ROW_CHICKEN5, CPSS_AWARE_DIS))
 	},
+
+	/* Xe3p_XPC */
+
+	{ XE_RTP_NAME("14026999295"),
+	  XE_RTP_RULES(GRAPHICS_VERSION(3511),
+		       FUNC(xe_rtp_match_first_render_or_compute)),
+	  XE_RTP_ACTIONS(SET(ROW_CHICKEN3, DIS_EU_GRF_POISON_TO_LSC))
+	},
+	{ XE_RTP_NAME("18044193044"),
+	  XE_RTP_RULES(GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0),
+		       FUNC(xe_rtp_match_first_render_or_compute)),
+	  XE_RTP_ACTIONS(SET(TDL_CHICKEN, BIT_APQ_OPT_DIS))
+	},
 };
 
 static const struct xe_rtp_entry_sr lrc_was[] = {
@@ -743,14 +756,6 @@ static const struct xe_rtp_entry_sr lrc_was[] = {
 	  XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)),
 	  XE_RTP_ACTIONS(SET(WM_CHICKEN3, HIZ_PLANE_COMPRESSION_DIS))
 	},
-	{ XE_RTP_NAME("14019988906"),
-	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), ENGINE_CLASS(RENDER)),
-	  XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FLSH_IGNORES_PSD))
-	},
-	{ XE_RTP_NAME("14019877138"),
-	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(2001, 2002), ENGINE_CLASS(RENDER)),
-	  XE_RTP_ACTIONS(SET(XEHP_PSS_CHICKEN, FD_END_COLLECT))
-	},
 	{ XE_RTP_NAME("14021490052"),
 	  XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)),
 	  XE_RTP_ACTIONS(SET(FF_MODE,
diff --git a/drivers/gpu/drm/xe/xe_wa.h b/drivers/gpu/drm/xe/xe_wa.h
index 8fd6a5af0910..a5f7d33c1b32 100644
--- a/drivers/gpu/drm/xe/xe_wa.h
+++ b/drivers/gpu/drm/xe/xe_wa.h
@@ -3,8 +3,8 @@
  * Copyright © 2022 Intel Corporation
  */
 
-#ifndef _XE_WA_
-#define _XE_WA_
+#ifndef _XE_WA_H_
+#define _XE_WA_H_
 
 #include "xe_assert.h"
 
diff --git a/drivers/gpu/drm/xe/xe_wa_oob.rules b/drivers/gpu/drm/xe/xe_wa_oob.rules
index 80b54b195f20..f8a185103b80 100644
--- a/drivers/gpu/drm/xe/xe_wa_oob.rules
+++ b/drivers/gpu/drm/xe/xe_wa_oob.rules
@@ -51,6 +51,13 @@
 		MEDIA_VERSION_RANGE(2000, 3002), FUNC(xe_rtp_match_psmi_enabled)
 16023683509	MEDIA_VERSION(2000), FUNC(xe_rtp_match_psmi_enabled)
 		MEDIA_VERSION(3000), MEDIA_STEP(A0, B0), FUNC(xe_rtp_match_psmi_enabled)
+14025515070	GRAPHICS_VERSION(2004)
+		MEDIA_VERSION_RANGE(1301, 3000)
+		MEDIA_VERSION(3002)
+		GRAPHICS_VERSION_RANGE(3000, 3001)
+		GRAPHICS_VERSION_RANGE(3003, 3005)
+		MEDIA_VERSION(3500)
+		GRAPHICS_VERSION(3510), GRAPHICS_STEP(A0, B0)
 
 15015404425_disable	PLATFORM(PANTHERLAKE), MEDIA_STEP(B0, FOREVER)
 16026007364    MEDIA_VERSION(3000)
diff --git a/drivers/hid/hid-asus.c b/drivers/hid/hid-asus.c
index 3f5e96900b67..d34d74df3dc0 100644
--- a/drivers/hid/hid-asus.c
+++ b/drivers/hid/hid-asus.c
@@ -965,6 +965,12 @@ static int asus_input_configured(struct hid_device *hdev, struct hid_input *hi)
 		}
 	}
 
+	if (drvdata->quirks & QUIRK_HID_FN_LOCK) {
+		drvdata->fn_lock = true;
+		INIT_WORK(&drvdata->fn_lock_sync_work, asus_sync_fn_lock);
+		asus_kbd_set_fn_lock(hdev, true);
+	}
+
 	if (drvdata->tp) {
 		int ret;
 
diff --git a/drivers/iio/adc/xilinx-xadc-core.c b/drivers/iio/adc/xilinx-xadc-core.c
index e257c1b94a5f..3980dfacbcd7 100644
--- a/drivers/iio/adc/xilinx-xadc-core.c
+++ b/drivers/iio/adc/xilinx-xadc-core.c
@@ -817,6 +817,7 @@ static int xadc_postdisable(struct iio_dev *indio_dev)
 {
 	struct xadc *xadc = iio_priv(indio_dev);
 	unsigned long scan_mask;
+	int seq_mode;
 	int ret;
 	int i;
 
@@ -824,6 +825,12 @@ static int xadc_postdisable(struct iio_dev *indio_dev)
 	for (i = 0; i < indio_dev->num_channels; i++)
 		scan_mask |= BIT(indio_dev->channels[i].scan_index);
 
+	/*
+	 * Use the correct sequencer mode for the idle state: simultaneous
+	 * mode for dual external mux configurations, continuous otherwise.
+	 */
+	seq_mode = xadc_get_seq_mode(xadc, scan_mask);
+
 	/* Enable all channels and calibration */
 	ret = xadc_write_adc_reg(xadc, XADC_REG_SEQ(0), scan_mask & 0xffff);
 	if (ret)
@@ -834,11 +841,11 @@ static int xadc_postdisable(struct iio_dev *indio_dev)
 		return ret;
 
 	ret = xadc_update_adc_reg(xadc, XADC_REG_CONF1, XADC_CONF1_SEQ_MASK,
-		XADC_CONF1_SEQ_CONTINUOUS);
+				  seq_mode);
 	if (ret)
 		return ret;
 
-	return xadc_power_adc_b(xadc, XADC_CONF1_SEQ_CONTINUOUS);
+	return xadc_power_adc_b(xadc, seq_mode);
 }
 
 static int xadc_preenable(struct iio_dev *indio_dev)
diff --git a/drivers/iio/chemical/mhz19b.c b/drivers/iio/chemical/mhz19b.c
index 3c64154918b1..9d4cf432919e 100644
--- a/drivers/iio/chemical/mhz19b.c
+++ b/drivers/iio/chemical/mhz19b.c
@@ -52,6 +52,8 @@ struct mhz19b_state {
 	struct completion buf_ready;
 
 	u8 buf_idx;
+	bool buf_overflow;
+
 	/*
 	 * Serdev receive buffer.
 	 * When data is received from the MH-Z19B,
@@ -106,6 +108,10 @@ static int mhz19b_serdev_cmd(struct iio_dev *indio_dev, int cmd, u16 arg)
 	cmd_buf[8] = mhz19b_get_checksum(cmd_buf);
 
 	/* Write buf to uart ctrl synchronously */
+	st->buf_idx = 0;
+	st->buf_overflow = false;
+	reinit_completion(&st->buf_ready);
+
 	ret = serdev_device_write(serdev, cmd_buf, MHZ19B_CMD_SIZE, 0);
 	if (ret < 0)
 		return ret;
@@ -121,6 +127,9 @@ static int mhz19b_serdev_cmd(struct iio_dev *indio_dev, int cmd, u16 arg)
 		if (!ret)
 			return -ETIMEDOUT;
 
+		if (st->buf_overflow)
+			return -EMSGSIZE;
+
 		if (st->buf[8] != mhz19b_get_checksum(st->buf)) {
 			dev_err(dev, "checksum err");
 			return -EINVAL;
@@ -240,6 +249,14 @@ static size_t mhz19b_receive_buf(struct serdev_device *serdev,
 {
 	struct iio_dev *indio_dev = dev_get_drvdata(&serdev->dev);
 	struct mhz19b_state *st = iio_priv(indio_dev);
+	size_t remaining = MHZ19B_CMD_SIZE - st->buf_idx;
+
+	if (len > remaining) {
+		st->buf_idx = 0;
+		st->buf_overflow = true;
+		complete(&st->buf_ready);
+		return len;
+	}
 
 	memcpy(st->buf + st->buf_idx, data, len);
 	st->buf_idx += len;
diff --git a/drivers/input/joystick/xpad.c b/drivers/input/joystick/xpad.c
index 0549fdc5a985..19ce90da89e9 100644
--- a/drivers/input/joystick/xpad.c
+++ b/drivers/input/joystick/xpad.c
@@ -1077,10 +1077,10 @@ static void xpadone_process_packet(struct usb_xpad *xpad, u16 cmd, unsigned char
 		input_report_key(dev, BTN_START,  data[4] & BIT(2));
 		input_report_key(dev, BTN_SELECT, data[4] & BIT(3));
 		if (xpad->mapping & MAP_SHARE_BUTTON) {
-			if (xpad->mapping & MAP_SHARE_OFFSET)
-				input_report_key(dev, KEY_RECORD, data[len - 26] & BIT(0));
-			else
-				input_report_key(dev, KEY_RECORD, data[len - 18] & BIT(0));
+			u32 offset = (xpad->mapping & MAP_SHARE_OFFSET) ? 26 : 18;
+
+			if (len >= offset)
+				input_report_key(dev, KEY_RECORD, data[len - offset] & BIT(0));
 		}
 
 		/* buttons A,B,X,Y */
diff --git a/drivers/input/keyboard/lm8323.c b/drivers/input/keyboard/lm8323.c
index e19442c6f80f..d9df10484755 100644
--- a/drivers/input/keyboard/lm8323.c
+++ b/drivers/input/keyboard/lm8323.c
@@ -259,7 +259,7 @@ static void process_keys(struct lm8323_chip *lm)
 	ret = lm8323_read(lm, LM8323_CMD_READ_FIFO, key_fifo, LM8323_FIFO_LEN);
 
 	if (ret < 0) {
-		dev_err(&lm->client->dev, "Failed reading fifo \n");
+		dev_err(&lm->client->dev, "Failed reading fifo\n");
 		return;
 	}
 	key_fifo[ret] = 0;
diff --git a/drivers/input/mouse/elan_i2c_core.c b/drivers/input/mouse/elan_i2c_core.c
index fee1796da3d0..7475803c6ce4 100644
--- a/drivers/input/mouse/elan_i2c_core.c
+++ b/drivers/input/mouse/elan_i2c_core.c
@@ -162,6 +162,9 @@ static int elan_get_fwinfo(u16 ic_type, u8 iap_version, u16 *validpage_count,
 	case 0x15:
 		*validpage_count = 1024;
 		break;
+	case 0x19:
+		*validpage_count = 2032;
+		break;
 	default:
 		/* unknown ic type clear value */
 		*validpage_count = 0;
diff --git a/drivers/input/mouse/elan_i2c_i2c.c b/drivers/input/mouse/elan_i2c_i2c.c
index a9057d124a88..88d4070d4b44 100644
--- a/drivers/input/mouse/elan_i2c_i2c.c
+++ b/drivers/input/mouse/elan_i2c_i2c.c
@@ -690,7 +690,7 @@ static int elan_i2c_finish_fw_update(struct i2c_client *client,
 	if (error) {
 		dev_err(dev, "device reset failed: %d\n", error);
 	} else if (!wait_for_completion_timeout(completion,
-						msecs_to_jiffies(300))) {
+						msecs_to_jiffies(700))) {
 		dev_err(dev, "timeout waiting for device reset\n");
 		error = -ETIMEDOUT;
 	}
diff --git a/drivers/input/touchscreen/stmfts.c b/drivers/input/touchscreen/stmfts.c
index 8af87d0b6eb6..454f7e822e9c 100644
--- a/drivers/input/touchscreen/stmfts.c
+++ b/drivers/input/touchscreen/stmfts.c
@@ -5,6 +5,7 @@
 // Copyright (c) 2017 Andi Shyti <andi@etezian.org>
 
 #include <linux/delay.h>
+#include <linux/gpio/consumer.h>
 #include <linux/i2c.h>
 #include <linux/input/mt.h>
 #include <linux/input/touchscreen.h>
@@ -69,20 +70,21 @@
 #define STMFTS_MAX_FINGERS	10
 #define STMFTS_DEV_NAME		"stmfts"
 
-enum stmfts_regulators {
-	STMFTS_REGULATOR_VDD,
-	STMFTS_REGULATOR_AVDD,
+static const struct regulator_bulk_data stmfts_supplies[] = {
+	{ .supply = "vdd" },
+	{ .supply = "avdd" },
 };
 
 struct stmfts_data {
 	struct i2c_client *client;
 	struct input_dev *input;
+	struct gpio_desc *reset_gpio;
 	struct led_classdev led_cdev;
 	struct mutex mutex;
 
 	struct touchscreen_properties prop;
 
-	struct regulator_bulk_data regulators[2];
+	struct regulator_bulk_data *supplies;
 
 	/*
 	 * Presence of ledvdd will be used also to check
@@ -107,7 +109,7 @@ struct stmfts_data {
 };
 
 static int stmfts_brightness_set(struct led_classdev *led_cdev,
-					enum led_brightness value)
+				 enum led_brightness value)
 {
 	struct stmfts_data *sdata = container_of(led_cdev,
 					struct stmfts_data, led_cdev);
@@ -250,7 +252,6 @@ static void stmfts_parse_events(struct stmfts_data *sdata)
 		u8 *event = &sdata->data[i * STMFTS_EVENT_SIZE];
 
 		switch (event[0]) {
-
 		case STMFTS_EV_CONTROLLER_READY:
 		case STMFTS_EV_SLEEP_OUT_CONTROLLER_READY:
 		case STMFTS_EV_STATUS:
@@ -263,7 +264,6 @@ static void stmfts_parse_events(struct stmfts_data *sdata)
 		}
 
 		switch (event[0] & STMFTS_MASK_EVENT_ID) {
-
 		case STMFTS_EV_MULTI_TOUCH_ENTER:
 		case STMFTS_EV_MULTI_TOUCH_MOTION:
 			stmfts_report_contact_event(sdata, event);
@@ -285,9 +285,9 @@ static void stmfts_parse_events(struct stmfts_data *sdata)
 
 		case STMFTS_EV_ERROR:
 			dev_warn(&sdata->client->dev,
-					"error code: 0x%x%x%x%x%x%x",
-					event[6], event[5], event[4],
-					event[3], event[2], event[1]);
+				 "error code: 0x%x%x%x%x%x%x",
+				 event[6], event[5], event[4],
+				 event[3], event[2], event[1]);
 			break;
 
 		default:
@@ -404,7 +404,7 @@ static void stmfts_input_close(struct input_dev *dev)
 }
 
 static ssize_t stmfts_sysfs_chip_id(struct device *dev,
-				struct device_attribute *attr, char *buf)
+				    struct device_attribute *attr, char *buf)
 {
 	struct stmfts_data *sdata = dev_get_drvdata(dev);
 
@@ -412,7 +412,8 @@ static ssize_t stmfts_sysfs_chip_id(struct device *dev,
 }
 
 static ssize_t stmfts_sysfs_chip_version(struct device *dev,
-				struct device_attribute *attr, char *buf)
+					 struct device_attribute *attr,
+					 char *buf)
 {
 	struct stmfts_data *sdata = dev_get_drvdata(dev);
 
@@ -420,7 +421,7 @@ static ssize_t stmfts_sysfs_chip_version(struct device *dev,
 }
 
 static ssize_t stmfts_sysfs_fw_ver(struct device *dev,
-				struct device_attribute *attr, char *buf)
+				   struct device_attribute *attr, char *buf)
 {
 	struct stmfts_data *sdata = dev_get_drvdata(dev);
 
@@ -428,7 +429,7 @@ static ssize_t stmfts_sysfs_fw_ver(struct device *dev,
 }
 
 static ssize_t stmfts_sysfs_config_id(struct device *dev,
-				struct device_attribute *attr, char *buf)
+				      struct device_attribute *attr, char *buf)
 {
 	struct stmfts_data *sdata = dev_get_drvdata(dev);
 
@@ -436,7 +437,8 @@ static ssize_t stmfts_sysfs_config_id(struct device *dev,
 }
 
 static ssize_t stmfts_sysfs_config_version(struct device *dev,
-				struct device_attribute *attr, char *buf)
+					   struct device_attribute *attr,
+					   char *buf)
 {
 	struct stmfts_data *sdata = dev_get_drvdata(dev);
 
@@ -444,7 +446,8 @@ static ssize_t stmfts_sysfs_config_version(struct device *dev,
 }
 
 static ssize_t stmfts_sysfs_read_status(struct device *dev,
-				struct device_attribute *attr, char *buf)
+					struct device_attribute *attr,
+					char *buf)
 {
 	struct stmfts_data *sdata = dev_get_drvdata(dev);
 	u8 status[4];
@@ -459,7 +462,8 @@ static ssize_t stmfts_sysfs_read_status(struct device *dev,
 }
 
 static ssize_t stmfts_sysfs_hover_enable_read(struct device *dev,
-				struct device_attribute *attr, char *buf)
+					      struct device_attribute *attr,
+					      char *buf)
 {
 	struct stmfts_data *sdata = dev_get_drvdata(dev);
 
@@ -467,8 +471,8 @@ static ssize_t stmfts_sysfs_hover_enable_read(struct device *dev,
 }
 
 static ssize_t stmfts_sysfs_hover_enable_write(struct device *dev,
-				struct device_attribute *attr,
-				const char *buf, size_t len)
+					       struct device_attribute *attr,
+					       const char *buf, size_t len)
 {
 	struct stmfts_data *sdata = dev_get_drvdata(dev);
 	unsigned long value;
@@ -485,8 +489,8 @@ static ssize_t stmfts_sysfs_hover_enable_write(struct device *dev,
 	if (hover != sdata->hover_enabled) {
 		if (sdata->running) {
 			err = i2c_smbus_write_byte(sdata->client,
-					   value ? STMFTS_SS_HOVER_SENSE_ON :
-						   STMFTS_SS_HOVER_SENSE_OFF);
+						   value ? STMFTS_SS_HOVER_SENSE_ON :
+							   STMFTS_SS_HOVER_SENSE_OFF);
 			if (err)
 				return err;
 		}
@@ -518,22 +522,11 @@ static struct attribute *stmfts_sysfs_attrs[] = {
 };
 ATTRIBUTE_GROUPS(stmfts_sysfs);
 
-static int stmfts_power_on(struct stmfts_data *sdata)
+static int stmfts_read_system_info(struct stmfts_data *sdata)
 {
 	int err;
 	u8 reg[8];
 
-	err = regulator_bulk_enable(ARRAY_SIZE(sdata->regulators),
-				    sdata->regulators);
-	if (err)
-		return err;
-
-	/*
-	 * The datasheet does not specify the power on time, but considering
-	 * that the reset time is < 10ms, I sleep 20ms to be sure
-	 */
-	msleep(20);
-
 	err = i2c_smbus_read_i2c_block_data(sdata->client, STMFTS_READ_INFO,
 					    sizeof(reg), reg);
 	if (err < 0)
@@ -547,9 +540,21 @@ static int stmfts_power_on(struct stmfts_data *sdata)
 	sdata->config_id = reg[4];
 	sdata->config_ver = reg[5];
 
-	enable_irq(sdata->client->irq);
+	return 0;
+}
 
+static void stmfts_reset(struct stmfts_data *sdata)
+{
+	gpiod_set_value_cansleep(sdata->reset_gpio, 1);
+	msleep(20);
+
+	gpiod_set_value_cansleep(sdata->reset_gpio, 0);
 	msleep(50);
+}
+
+static int stmfts_configure(struct stmfts_data *sdata)
+{
+	int err;
 
 	err = stmfts_command(sdata, STMFTS_SYSTEM_RESET);
 	if (err)
@@ -575,13 +580,52 @@ static int stmfts_power_on(struct stmfts_data *sdata)
 	if (err)
 		return err;
 
+	return 0;
+}
+
+static int stmfts_power_on(struct stmfts_data *sdata)
+{
+	int err;
+
+	err = regulator_bulk_enable(ARRAY_SIZE(stmfts_supplies),
+				    sdata->supplies);
+	if (err)
+		return err;
+
+	/*
+	 * The datasheet does not specify the power on time, but considering
+	 * that the reset time is < 10ms, I sleep 20ms to be sure
+	 */
+	msleep(20);
+
+	if (sdata->reset_gpio)
+		stmfts_reset(sdata);
+
+	err = stmfts_read_system_info(sdata);
+	if (err)
+		goto err_disable_regulators;
+
+	enable_irq(sdata->client->irq);
+
+	msleep(50);
+
+	err = stmfts_configure(sdata);
+	if (err)
+		goto err_disable_irq;
+
 	/*
 	 * At this point no one is using the touchscreen
 	 * and I don't really care about the return value
 	 */
-	(void) i2c_smbus_write_byte(sdata->client, STMFTS_SLEEP_IN);
+	(void)i2c_smbus_write_byte(sdata->client, STMFTS_SLEEP_IN);
 
 	return 0;
+
+err_disable_irq:
+	disable_irq(sdata->client->irq);
+err_disable_regulators:
+	regulator_bulk_disable(ARRAY_SIZE(stmfts_supplies), sdata->supplies);
+	return err;
 }
 
 static void stmfts_power_off(void *data)
@@ -589,8 +633,11 @@ static void stmfts_power_off(void *data)
 	struct stmfts_data *sdata = data;
 
 	disable_irq(sdata->client->irq);
-	regulator_bulk_disable(ARRAY_SIZE(sdata->regulators),
-						sdata->regulators);
+
+	if (sdata->reset_gpio)
+		gpiod_set_value_cansleep(sdata->reset_gpio, 1);
+
+	regulator_bulk_disable(ARRAY_SIZE(stmfts_supplies), sdata->supplies);
 }
 
 static int stmfts_enable_led(struct stmfts_data *sdata)
@@ -619,6 +666,7 @@ static int stmfts_enable_led(struct stmfts_data *sdata)
 
 static int stmfts_probe(struct i2c_client *client)
 {
+	struct device *dev = &client->dev;
 	int err;
 	struct stmfts_data *sdata;
 
@@ -627,7 +675,7 @@ static int stmfts_probe(struct i2c_client *client)
 						I2C_FUNC_SMBUS_I2C_BLOCK))
 		return -ENODEV;
 
-	sdata = devm_kzalloc(&client->dev, sizeof(*sdata), GFP_KERNEL);
+	sdata = devm_kzalloc(dev, sizeof(*sdata), GFP_KERNEL);
 	if (!sdata)
 		return -ENOMEM;
 
@@ -637,15 +685,19 @@ static int stmfts_probe(struct i2c_client *client)
 	mutex_init(&sdata->mutex);
 	init_completion(&sdata->cmd_done);
 
-	sdata->regulators[STMFTS_REGULATOR_VDD].supply = "vdd";
-	sdata->regulators[STMFTS_REGULATOR_AVDD].supply = "avdd";
-	err = devm_regulator_bulk_get(&client->dev,
-				      ARRAY_SIZE(sdata->regulators),
-				      sdata->regulators);
+	err = devm_regulator_bulk_get_const(dev,
+					    ARRAY_SIZE(stmfts_supplies),
+					    stmfts_supplies,
+					    &sdata->supplies);
 	if (err)
 		return err;
 
-	sdata->input = devm_input_allocate_device(&client->dev);
+	sdata->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
+	if (IS_ERR(sdata->reset_gpio))
+		return dev_err_probe(dev, PTR_ERR(sdata->reset_gpio),
+				     "Failed to get GPIO 'reset'\n");
+
+	sdata->input = devm_input_allocate_device(dev);
 	if (!sdata->input)
 		return -ENOMEM;
 
@@ -664,8 +716,7 @@ static int stmfts_probe(struct i2c_client *client)
 	input_set_abs_params(sdata->input, ABS_MT_PRESSURE, 0, 255, 0, 0);
 	input_set_abs_params(sdata->input, ABS_DISTANCE, 0, 255, 0, 0);
 
-	sdata->use_key = device_property_read_bool(&client->dev,
-						   "touch-key-connected");
+	sdata->use_key = device_property_read_bool(dev, "touch-key-connected");
 	if (sdata->use_key) {
 		input_set_capability(sdata->input, EV_KEY, KEY_MENU);
 		input_set_capability(sdata->input, EV_KEY, KEY_BACK);
@@ -685,20 +736,20 @@ static int stmfts_probe(struct i2c_client *client)
 	 * interrupts. To be on the safe side it's better to not enable
 	 * the interrupts during their request.
 	 */
-	err = devm_request_threaded_irq(&client->dev, client->irq,
+	err = devm_request_threaded_irq(dev, client->irq,
 					NULL, stmfts_irq_handler,
 					IRQF_ONESHOT | IRQF_NO_AUTOEN,
 					"stmfts_irq", sdata);
 	if (err)
 		return err;
 
-	dev_dbg(&client->dev, "initializing ST-Microelectronics FTS...\n");
+	dev_dbg(dev, "initializing ST-Microelectronics FTS...\n");
 
 	err = stmfts_power_on(sdata);
 	if (err)
 		return err;
 
-	err = devm_add_action_or_reset(&client->dev, stmfts_power_off, sdata);
+	err = devm_add_action_or_reset(dev, stmfts_power_off, sdata);
 	if (err)
 		return err;
 
@@ -715,13 +766,13 @@ static int stmfts_probe(struct i2c_client *client)
 			 * without LEDs. The ledvdd regulator pointer will be
 			 * used as a flag.
 			 */
-			dev_warn(&client->dev, "unable to use touchkey leds\n");
+			dev_warn(dev, "unable to use touchkey leds\n");
 			sdata->ledvdd = NULL;
 		}
 	}
 
-	pm_runtime_enable(&client->dev);
-	device_enable_async_suspend(&client->dev);
+	pm_runtime_enable(dev);
+	device_enable_async_suspend(dev);
 
 	return 0;
 }
@@ -746,9 +797,10 @@ static int stmfts_runtime_suspend(struct device *dev)
 static int stmfts_runtime_resume(struct device *dev)
 {
 	struct stmfts_data *sdata = dev_get_drvdata(dev);
+	struct i2c_client *client = sdata->client;
 	int ret;
 
-	ret = i2c_smbus_write_byte(sdata->client, STMFTS_SLEEP_OUT);
+	ret = i2c_smbus_write_byte(client, STMFTS_SLEEP_OUT);
 	if (ret)
 		dev_err(dev, "failed to resume device: %d\n", ret);
 
@@ -807,4 +859,4 @@ module_i2c_driver(stmfts_driver);
 
 MODULE_AUTHOR("Andi Shyti <andi.shyti@samsung.com>");
 MODULE_DESCRIPTION("STMicroelectronics FTS Touch Screen");
-MODULE_LICENSE("GPL v2");
+MODULE_LICENSE("GPL");
diff --git a/drivers/input/touchscreen/usbtouchscreen.c b/drivers/input/touchscreen/usbtouchscreen.c
index daa28135f887..0bbacb517c28 100644
--- a/drivers/input/touchscreen/usbtouchscreen.c
+++ b/drivers/input/touchscreen/usbtouchscreen.c
@@ -1067,6 +1067,11 @@ static int nexio_read_data(struct usbtouch_usb *usbtouch, unsigned char *pkt)
 	if (x_len > 0xff)
 		x_len -= 0x80;
 
+	if (data_len > usbtouch->data_size - sizeof(*packet))
+		data_len = usbtouch->data_size - sizeof(*packet);
+	if (x_len > data_len)
+		x_len = data_len;
+
 	/* send ACK */
 	ret = usb_submit_urb(priv->ack, GFP_ATOMIC);
 	if (ret)
diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index e755a2a05209..753e8fc3b916 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -51,12 +51,6 @@ config ARM_GIC_V3_ITS
 	default ARM_GIC_V3
 	select IRQ_MSI_IOMMU
 
-config ARM_GIC_V3_ITS_FSL_MC
-	bool
-	depends on ARM_GIC_V3_ITS
-	depends on FSL_MC_BUS
-	default ARM_GIC_V3_ITS
-
 config ARM_GIC_V5
 	bool
 	select IRQ_DOMAIN_HIERARCHY
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 26aa3b6ec99f..d5a28cee0d8e 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -35,7 +35,6 @@ obj-$(CONFIG_ARM_GIC_V2M)		+= irq-gic-v2m.o
 obj-$(CONFIG_ARM_GIC_V3)		+= irq-gic-v3.o irq-gic-v3-mbi.o irq-gic-common.o
 obj-$(CONFIG_ARM_GIC_ITS_PARENT)	+= irq-gic-its-msi-parent.o
 obj-$(CONFIG_ARM_GIC_V3_ITS)		+= irq-gic-v3-its.o irq-gic-v4.o
-obj-$(CONFIG_ARM_GIC_V3_ITS_FSL_MC)	+= irq-gic-v3-its-fsl-mc-msi.o
 obj-$(CONFIG_ARM_GIC_V5)		+= irq-gic-v5.o irq-gic-v5-irs.o irq-gic-v5-its.o \
 					   irq-gic-v5-iwb.o
 obj-$(CONFIG_HISILICON_IRQ_MBIGEN)	+= irq-mbigen.o
diff --git a/drivers/irqchip/irq-gic-its-msi-parent.c b/drivers/irqchip/irq-gic-its-msi-parent.c
index a832cdb2e697..d36b278ae66c 100644
--- a/drivers/irqchip/irq-gic-its-msi-parent.c
+++ b/drivers/irqchip/irq-gic-its-msi-parent.c
@@ -5,6 +5,7 @@
 // Copyright (C) 2022 Intel
 
 #include <linux/acpi_iort.h>
+#include <linux/fsl/mc.h>
 #include <linux/of_address.h>
 #include <linux/pci.h>
 
@@ -187,9 +188,11 @@ static int its_pmsi_prepare(struct irq_domain *domain, struct device *dev,
 {
 	struct msi_domain_info *msi_info;
 	u32 dev_id;
-	int ret;
+	int ret = 0;
 
-	if (dev->of_node)
+	if (dev_is_fsl_mc(dev))
+		dev_id = fsl_mc_get_msi_id(dev);
+	else if (dev->of_node)
 		ret = of_pmsi_get_msi_info(domain->parent, dev, &dev_id, NULL);
 	else
 		ret = iort_pmsi_get_msi_info(dev, &dev_id, NULL);
diff --git a/drivers/irqchip/irq-gic-v3-its-fsl-mc-msi.c b/drivers/irqchip/irq-gic-v3-its-fsl-mc-msi.c
deleted file mode 100644
index b5785472765a..000000000000
--- a/drivers/irqchip/irq-gic-v3-its-fsl-mc-msi.c
+++ /dev/null
@@ -1,168 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Freescale Management Complex (MC) bus driver MSI support
- *
- * Copyright (C) 2015-2016 Freescale Semiconductor, Inc.
- * Author: German Rivera <German.Rivera@freescale.com>
- *
- */
-
-#include <linux/acpi.h>
-#include <linux/acpi_iort.h>
-#include <linux/irq.h>
-#include <linux/msi.h>
-#include <linux/of.h>
-#include <linux/of_irq.h>
-#include <linux/fsl/mc.h>
-
-static struct irq_chip its_msi_irq_chip = {
-	.name = "ITS-fMSI",
-	.irq_mask = irq_chip_mask_parent,
-	.irq_unmask = irq_chip_unmask_parent,
-	.irq_eoi = irq_chip_eoi_parent,
-	.irq_set_affinity = msi_domain_set_affinity
-};
-
-static u32 fsl_mc_msi_domain_get_msi_id(struct irq_domain *domain,
-					struct fsl_mc_device *mc_dev)
-{
-	struct device_node *of_node;
-	u32 out_id;
-
-	of_node = irq_domain_get_of_node(domain);
-	out_id = of_node ? of_msi_xlate(&mc_dev->dev, &of_node, mc_dev->icid) :
-			iort_msi_map_id(&mc_dev->dev, mc_dev->icid);
-
-	return out_id;
-}
-
-static int its_fsl_mc_msi_prepare(struct irq_domain *msi_domain,
-				  struct device *dev,
-				  int nvec, msi_alloc_info_t *info)
-{
-	struct fsl_mc_device *mc_bus_dev;
-	struct msi_domain_info *msi_info;
-
-	if (!dev_is_fsl_mc(dev))
-		return -EINVAL;
-
-	mc_bus_dev = to_fsl_mc_device(dev);
-	if (!(mc_bus_dev->flags & FSL_MC_IS_DPRC))
-		return -EINVAL;
-
-	/*
-	 * Set the device Id to be passed to the GIC-ITS:
-	 *
-	 * NOTE: This device id corresponds to the IOMMU stream ID
-	 * associated with the DPRC object (ICID).
-	 */
-	info->scratchpad[0].ul = fsl_mc_msi_domain_get_msi_id(msi_domain,
-							      mc_bus_dev);
-	msi_info = msi_get_domain_info(msi_domain->parent);
-
-	/* Allocate at least 32 MSIs, and always as a power of 2 */
-	nvec = max_t(int, 32, roundup_pow_of_two(nvec));
-	return msi_info->ops->msi_prepare(msi_domain->parent, dev, nvec, info);
-}
-
-static struct msi_domain_ops its_fsl_mc_msi_ops __ro_after_init = {
-	.msi_prepare = its_fsl_mc_msi_prepare,
-};
-
-static struct msi_domain_info its_fsl_mc_msi_domain_info = {
-	.flags	= (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS),
-	.ops	= &its_fsl_mc_msi_ops,
-	.chip	= &its_msi_irq_chip,
-};
-
-static const struct of_device_id its_device_id[] = {
-	{	.compatible	= "arm,gic-v3-its",	},
-	{},
-};
-
-static void __init its_fsl_mc_msi_init_one(struct fwnode_handle *handle,
-					  const char *name)
-{
-	struct irq_domain *parent;
-	struct irq_domain *mc_msi_domain;
-
-	parent = irq_find_matching_fwnode(handle, DOMAIN_BUS_NEXUS);
-	if (!parent || !msi_get_domain_info(parent)) {
-		pr_err("%s: unable to locate ITS domain\n", name);
-		return;
-	}
-
-	mc_msi_domain = fsl_mc_msi_create_irq_domain(handle,
-						&its_fsl_mc_msi_domain_info,
-						parent);
-	if (!mc_msi_domain) {
-		pr_err("%s: unable to create fsl-mc domain\n", name);
-		return;
-	}
-
-	pr_info("fsl-mc MSI: %s domain created\n", name);
-}
-
-#ifdef CONFIG_ACPI
-static int __init
-its_fsl_mc_msi_parse_madt(union acpi_subtable_headers *header,
-			  const unsigned long end)
-{
-	struct acpi_madt_generic_translator *its_entry;
-	struct fwnode_handle *dom_handle;
-	const char *node_name;
-	int err = 0;
-
-	its_entry = (struct acpi_madt_generic_translator *)header;
-	node_name = kasprintf(GFP_KERNEL, "ITS@0x%lx",
-			      (long)its_entry->base_address);
-
-	dom_handle = iort_find_domain_token(its_entry->translation_id);
-	if (!dom_handle) {
-		pr_err("%s: Unable to locate ITS domain handle\n", node_name);
-		err = -ENXIO;
-		goto out;
-	}
-
-	its_fsl_mc_msi_init_one(dom_handle, node_name);
-
-out:
-	kfree(node_name);
-	return err;
-}
-
-
-static void __init its_fsl_mc_acpi_msi_init(void)
-{
-	acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_TRANSLATOR,
-			      its_fsl_mc_msi_parse_madt, 0);
-}
-#else
-static inline void its_fsl_mc_acpi_msi_init(void) { }
-#endif
-
-static void __init its_fsl_mc_of_msi_init(void)
-{
-	struct device_node *np;
-
-	for (np = of_find_matching_node(NULL, its_device_id); np;
-	     np = of_find_matching_node(np, its_device_id)) {
-		if (!of_device_is_available(np))
-			continue;
-		if (!of_property_read_bool(np, "msi-controller"))
-			continue;
-
-		its_fsl_mc_msi_init_one(of_fwnode_handle(np),
-					np->full_name);
-	}
-}
-
-static int __init its_fsl_mc_msi_init(void)
-{
-	its_fsl_mc_of_msi_init();
-	its_fsl_mc_acpi_msi_init();
-
-	return 0;
-}
-
-early_initcall(its_fsl_mc_msi_init);
diff --git a/drivers/mailbox/cix-mailbox.c b/drivers/mailbox/cix-mailbox.c
index 443620e8ae37..43c76cdab24a 100644
--- a/drivers/mailbox/cix-mailbox.c
+++ b/drivers/mailbox/cix-mailbox.c
@@ -12,8 +12,6 @@
 #include <linux/module.h>
 #include <linux/platform_device.h>
 
-#include "mailbox.h"
-
 /*
  * The maximum transmission size is 32 words or 128 bytes.
  */
@@ -405,7 +403,7 @@ static int cix_mbox_startup(struct mbox_chan *chan)
 	int index = cp->index, ret;
 	u32 val;
 
-	ret = request_irq(priv->irq, cix_mbox_isr, 0,
+	ret = request_irq(priv->irq, cix_mbox_isr, IRQF_NO_SUSPEND,
 			  dev_name(priv->dev), chan);
 	if (ret) {
 		dev_err(priv->dev, "Unable to acquire IRQ %d\n", priv->irq);
@@ -415,7 +413,7 @@ static int cix_mbox_startup(struct mbox_chan *chan)
 	switch (cp->type) {
 	case CIX_MBOX_TYPE_DB:
 		/* Overwrite txdone_method for DB channel */
-		chan->txdone_method = TXDONE_BY_ACK;
+		chan->txdone_method = MBOX_TXDONE_BY_ACK;
 		fallthrough;
 	case CIX_MBOX_TYPE_REG:
 		if (priv->dir == CIX_MBOX_TX) {
diff --git a/drivers/mailbox/exynos-mailbox.c b/drivers/mailbox/exynos-mailbox.c
index 5f2d3b81c1db..d2355b128ba4 100644
--- a/drivers/mailbox/exynos-mailbox.c
+++ b/drivers/mailbox/exynos-mailbox.c
@@ -99,7 +99,6 @@ static int exynos_mbox_probe(struct platform_device *pdev)
 	struct mbox_controller *mbox;
 	struct mbox_chan *chans;
 	struct clk *pclk;
-	int i;
 
 	exynos_mbox = devm_kzalloc(dev, sizeof(*exynos_mbox), GFP_KERNEL);
 	if (!exynos_mbox)
@@ -129,9 +128,6 @@ static int exynos_mbox_probe(struct platform_device *pdev)
 	mbox->ops = &exynos_mbox_chan_ops;
 	mbox->of_xlate = exynos_mbox_of_xlate;
 
-	for (i = 0; i < EXYNOS_MBOX_CHAN_COUNT; i++)
-		chans[i].mbox = mbox;
-
 	exynos_mbox->mbox = mbox;
 
 	platform_set_drvdata(pdev, exynos_mbox);
diff --git a/drivers/mailbox/hi3660-mailbox.c b/drivers/mailbox/hi3660-mailbox.c
index 17c29e960fbf..9b727a2b54a5 100644
--- a/drivers/mailbox/hi3660-mailbox.c
+++ b/drivers/mailbox/hi3660-mailbox.c
@@ -15,8 +15,6 @@
 #include <linux/platform_device.h>
 #include <linux/slab.h>
 
-#include "mailbox.h"
-
 #define MBOX_CHAN_MAX			32
 
 #define MBOX_RX				0x0
diff --git a/drivers/mailbox/hi6220-mailbox.c b/drivers/mailbox/hi6220-mailbox.c
index f77741ce42e7..69d15b6283e9 100644
--- a/drivers/mailbox/hi6220-mailbox.c
+++ b/drivers/mailbox/hi6220-mailbox.c
@@ -79,12 +79,12 @@ struct hi6220_mbox {
 	/* region for mailbox */
 	void __iomem *base;
 
-	unsigned int chan_num;
-	struct hi6220_mbox_chan *mchan;
-
 	void *irq_map_chan[MBOX_CHAN_MAX];
 	struct mbox_chan *chan;
 	struct mbox_controller controller;
+
+	unsigned int chan_num;
+	struct hi6220_mbox_chan mchan[] __counted_by(chan_num);
 };
 
 static void mbox_set_state(struct hi6220_mbox *mbox,
@@ -267,16 +267,12 @@ static int hi6220_mbox_probe(struct platform_device *pdev)
 	struct hi6220_mbox *mbox;
 	int i, err;
 
-	mbox = devm_kzalloc(dev, sizeof(*mbox), GFP_KERNEL);
+	mbox = devm_kzalloc(dev, struct_size(mbox, mchan, MBOX_CHAN_MAX), GFP_KERNEL);
 	if (!mbox)
 		return -ENOMEM;
 
-	mbox->dev = dev;
 	mbox->chan_num = MBOX_CHAN_MAX;
-	mbox->mchan = devm_kcalloc(dev,
-		mbox->chan_num, sizeof(*mbox->mchan), GFP_KERNEL);
-	if (!mbox->mchan)
-		return -ENOMEM;
+	mbox->dev = dev;
 
 	mbox->chan = devm_kcalloc(dev,
 		mbox->chan_num, sizeof(*mbox->chan), GFP_KERNEL);
diff --git a/drivers/mailbox/imx-mailbox.c b/drivers/mailbox/imx-mailbox.c
index 003f9236c35e..246a9a9e3952 100644
--- a/drivers/mailbox/imx-mailbox.c
+++ b/drivers/mailbox/imx-mailbox.c
@@ -23,8 +23,6 @@
 #include <linux/slab.h>
 #include <linux/workqueue.h>
 
-#include "mailbox.h"
-
 #define IMX_MU_CHANS		24
 /* TX0/RX0/RXDB[0-3] */
 #define IMX_MU_SCU_CHANS	6
@@ -734,7 +732,7 @@ static struct mbox_chan * imx_mu_xlate(struct mbox_controller *mbox,
 	p_chan = &mbox->chans[chan];
 
 	if (type == IMX_MU_TYPE_TXDB_V2)
-		p_chan->txdone_method = TXDONE_BY_ACK;
+		p_chan->txdone_method = MBOX_TXDONE_BY_ACK;
 
 	return p_chan;
 }
diff --git a/drivers/mailbox/mailbox-sti.c b/drivers/mailbox/mailbox-sti.c
index b4b5bdd503cf..b6c9ecbbc8ec 100644
--- a/drivers/mailbox/mailbox-sti.c
+++ b/drivers/mailbox/mailbox-sti.c
@@ -21,8 +21,6 @@
 #include <linux/property.h>
 #include <linux/slab.h>
 
-#include "mailbox.h"
-
 #define STI_MBOX_INST_MAX	4      /* RAM saving: Max supported instances */
 #define STI_MBOX_CHAN_MAX	20     /* RAM saving: Max supported channels  */
 
diff --git a/drivers/mailbox/mailbox-test.c b/drivers/mailbox/mailbox-test.c
index 3a28ab5c42e5..7b6ef033e77a 100644
--- a/drivers/mailbox/mailbox-test.c
+++ b/drivers/mailbox/mailbox-test.c
@@ -28,8 +28,6 @@
 #define MBOX_HEXDUMP_MAX_LEN	(MBOX_HEXDUMP_LINE_LEN *		\
 				 (MBOX_MAX_MSG_LEN / MBOX_BYTES_PER_LINE))
 
-static bool mbox_data_ready;
-
 struct mbox_test_device {
 	struct device		*dev;
 	void __iomem		*tx_mmio;
@@ -42,6 +40,7 @@ struct mbox_test_device {
 	spinlock_t		lock;
 	struct mutex		mutex;
 	wait_queue_head_t	waitq;
+	bool			data_ready;
 	struct fasync_struct	*async_queue;
 	struct dentry		*root_debugfs_dir;
 };
@@ -162,7 +161,7 @@ static bool mbox_test_message_data_ready(struct mbox_test_device *tdev)
 	unsigned long flags;
 
 	spin_lock_irqsave(&tdev->lock, flags);
-	data_ready = mbox_data_ready;
+	data_ready = tdev->data_ready;
 	spin_unlock_irqrestore(&tdev->lock, flags);
 
 	return data_ready;
@@ -227,7 +226,7 @@ static ssize_t mbox_test_message_read(struct file *filp, char __user *userbuf,
 	*(touser + l) = '\0';
 
 	memset(tdev->rx_buffer, 0, MBOX_MAX_MSG_LEN);
-	mbox_data_ready = false;
+	tdev->data_ready = false;
 
 	spin_unlock_irqrestore(&tdev->lock, flags);
 
@@ -297,7 +296,7 @@ static void mbox_test_receive_message(struct mbox_client *client, void *message)
 				     message, MBOX_MAX_MSG_LEN);
 		memcpy(tdev->rx_buffer, message, MBOX_MAX_MSG_LEN);
 	}
-	mbox_data_ready = true;
+	tdev->data_ready = true;
 	spin_unlock_irqrestore(&tdev->lock, flags);
 
 	wake_up_interruptible(&tdev->waitq);
@@ -336,7 +335,7 @@ mbox_test_request_channel(struct platform_device *pdev, const char *name)
 
 	client = devm_kzalloc(&pdev->dev, sizeof(*client), GFP_KERNEL);
 	if (!client)
-		return ERR_PTR(-ENOMEM);
+		return NULL;
 
 	client->dev		= &pdev->dev;
 	client->rx_callback	= mbox_test_receive_message;
@@ -355,67 +354,80 @@ mbox_test_request_channel(struct platform_device *pdev, const char *name)
 	return channel;
 }
 
+static void __iomem *mbox_test_ioremap(struct platform_device *pdev, unsigned int res_num)
+{
+	struct resource *res;
+	void __iomem *mmio;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, res_num);
+	if (!res)
+		return NULL;
+
+	mmio = devm_ioremap_resource(&pdev->dev, res);
+	if (PTR_ERR(mmio) == -EBUSY) {
+		dev_info(&pdev->dev, "trying workaround with plain ioremap\n");
+		return devm_ioremap(&pdev->dev, res->start, resource_size(res));
+	}
+
+	return IS_ERR(mmio) ? NULL : mmio;
+}
+
 static int mbox_test_probe(struct platform_device *pdev)
 {
 	struct mbox_test_device *tdev;
-	struct resource *res;
-	resource_size_t size;
 	int ret;
 
 	tdev = devm_kzalloc(&pdev->dev, sizeof(*tdev), GFP_KERNEL);
 	if (!tdev)
 		return -ENOMEM;
 
+	tdev->dev = &pdev->dev;
+	spin_lock_init(&tdev->lock);
+	mutex_init(&tdev->mutex);
+	init_waitqueue_head(&tdev->waitq);
+	platform_set_drvdata(pdev, tdev);
+
 	/* It's okay for MMIO to be NULL */
-	tdev->tx_mmio = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
-	if (PTR_ERR(tdev->tx_mmio) == -EBUSY) {
-		/* if reserved area in SRAM, try just ioremap */
-		size = resource_size(res);
-		tdev->tx_mmio = devm_ioremap(&pdev->dev, res->start, size);
-	} else if (IS_ERR(tdev->tx_mmio)) {
-		tdev->tx_mmio = NULL;
-	}
+	tdev->tx_mmio = mbox_test_ioremap(pdev, 0);
 
 	/* If specified, second reg entry is Rx MMIO */
-	tdev->rx_mmio = devm_platform_get_and_ioremap_resource(pdev, 1, &res);
-	if (PTR_ERR(tdev->rx_mmio) == -EBUSY) {
-		size = resource_size(res);
-		tdev->rx_mmio = devm_ioremap(&pdev->dev, res->start, size);
-	} else if (IS_ERR(tdev->rx_mmio)) {
+	tdev->rx_mmio = mbox_test_ioremap(pdev, 1);
+	if (!tdev->rx_mmio)
 		tdev->rx_mmio = tdev->tx_mmio;
-	}
 
 	tdev->tx_channel = mbox_test_request_channel(pdev, "tx");
 	tdev->rx_channel = mbox_test_request_channel(pdev, "rx");
 
-	if (IS_ERR_OR_NULL(tdev->tx_channel) && IS_ERR_OR_NULL(tdev->rx_channel))
+	if (!tdev->tx_channel && !tdev->rx_channel)
 		return -EPROBE_DEFER;
 
 	/* If Rx is not specified but has Rx MMIO, then Rx = Tx */
 	if (!tdev->rx_channel && (tdev->rx_mmio != tdev->tx_mmio))
 		tdev->rx_channel = tdev->tx_channel;
 
-	tdev->dev = &pdev->dev;
-	platform_set_drvdata(pdev, tdev);
-
-	spin_lock_init(&tdev->lock);
-	mutex_init(&tdev->mutex);
-
 	if (tdev->rx_channel) {
 		tdev->rx_buffer = devm_kzalloc(&pdev->dev,
 					       MBOX_MAX_MSG_LEN, GFP_KERNEL);
-		if (!tdev->rx_buffer)
-			return -ENOMEM;
+		if (!tdev->rx_buffer) {
+			ret = -ENOMEM;
+			goto err_free_chans;
+		}
 	}
 
 	ret = mbox_test_add_debugfs(pdev, tdev);
 	if (ret)
-		return ret;
+		goto err_free_chans;
 
-	init_waitqueue_head(&tdev->waitq);
 	dev_info(&pdev->dev, "Successfully registered\n");
 
 	return 0;
+
+err_free_chans:
+	if (tdev->tx_channel)
+		mbox_free_channel(tdev->tx_channel);
+	if (tdev->rx_channel && tdev->rx_channel != tdev->tx_channel)
+		mbox_free_channel(tdev->rx_channel);
+	return ret;
 }
 
 static void mbox_test_remove(struct platform_device *pdev)
@@ -426,7 +438,7 @@ static void mbox_test_remove(struct platform_device *pdev)
 
 	if (tdev->tx_channel)
 		mbox_free_channel(tdev->tx_channel);
-	if (tdev->rx_channel)
+	if (tdev->rx_channel && tdev->rx_channel != tdev->tx_channel)
 		mbox_free_channel(tdev->rx_channel);
 }
 
diff --git a/drivers/mailbox/mailbox.c b/drivers/mailbox/mailbox.c
index 617ba505691d..bbc9fd75a95f 100644
--- a/drivers/mailbox/mailbox.c
+++ b/drivers/mailbox/mailbox.c
@@ -18,8 +18,6 @@
 #include <linux/property.h>
 #include <linux/spinlock.h>
 
-#include "mailbox.h"
-
 static LIST_HEAD(mbox_cons);
 static DEFINE_MUTEX(con_mutex);
 
@@ -52,7 +50,7 @@ static void msg_submit(struct mbox_chan *chan)
 	int err = -EBUSY;
 
 	scoped_guard(spinlock_irqsave, &chan->lock) {
-		if (!chan->msg_count || chan->active_req)
+		if (!chan->msg_count || chan->active_req != MBOX_NO_MSG)
 			break;
 
 		count = chan->msg_count;
@@ -74,7 +72,7 @@ static void msg_submit(struct mbox_chan *chan)
 		}
 	}
 
-	if (!err && (chan->txdone_method & TXDONE_BY_POLL)) {
+	if (!err && (chan->txdone_method & MBOX_TXDONE_BY_POLL)) {
 		/* kick start the timer immediately to avoid delays */
 		scoped_guard(spinlock_irqsave, &chan->mbox->poll_hrt_lock)
 			hrtimer_start(&chan->mbox->poll_hrt, 0, HRTIMER_MODE_REL);
@@ -87,13 +85,13 @@ static void tx_tick(struct mbox_chan *chan, int r)
 
 	scoped_guard(spinlock_irqsave, &chan->lock) {
 		mssg = chan->active_req;
-		chan->active_req = NULL;
+		chan->active_req = MBOX_NO_MSG;
 	}
 
 	/* Submit next message */
 	msg_submit(chan);
 
-	if (!mssg)
+	if (mssg == MBOX_NO_MSG)
 		return;
 
 	/* Notify the client */
@@ -114,7 +112,7 @@ static enum hrtimer_restart txdone_hrtimer(struct hrtimer *hrtimer)
 	for (i = 0; i < mbox->num_chans; i++) {
 		struct mbox_chan *chan = &mbox->chans[i];
 
-		if (chan->active_req && chan->cl) {
+		if (chan->active_req != MBOX_NO_MSG && chan->cl) {
 			txdone = chan->mbox->ops->last_tx_done(chan);
 			if (txdone)
 				tx_tick(chan, 0);
@@ -164,7 +162,7 @@ EXPORT_SYMBOL_GPL(mbox_chan_received_data);
  */
 void mbox_chan_txdone(struct mbox_chan *chan, int r)
 {
-	if (unlikely(!(chan->txdone_method & TXDONE_BY_IRQ))) {
+	if (unlikely(!(chan->txdone_method & MBOX_TXDONE_BY_IRQ))) {
 		dev_err(chan->mbox->dev,
 		       "Controller can't run the TX ticker\n");
 		return;
@@ -185,7 +183,7 @@ EXPORT_SYMBOL_GPL(mbox_chan_txdone);
  */
 void mbox_client_txdone(struct mbox_chan *chan, int r)
 {
-	if (unlikely(!(chan->txdone_method & TXDONE_BY_ACK))) {
+	if (unlikely(!(chan->txdone_method & MBOX_TXDONE_BY_ACK))) {
 		dev_err(chan->mbox->dev, "Client can't run the TX ticker\n");
 		return;
 	}
@@ -218,6 +216,29 @@ bool mbox_client_peek_data(struct mbox_chan *chan)
 }
 EXPORT_SYMBOL_GPL(mbox_client_peek_data);
 
+/**
+ * mbox_chan_tx_slots_available - Query the number of available TX queue slots.
+ * @chan: Mailbox channel to query.
+ *
+ * Clients may call this to check how many messages can be queued via
+ * mbox_send_message() before the channel's TX queue is full. This helps
+ * clients avoid the -ENOBUFS error without needing to increase
+ * MBOX_TX_QUEUE_LEN.
+ * This can be called from atomic context.
+ *
+ * Return: Number of available slots in the channel's TX queue.
+ */
+unsigned int mbox_chan_tx_slots_available(struct mbox_chan *chan)
+{
+	unsigned int ret;
+
+	guard(spinlock_irqsave)(&chan->lock);
+	ret = MBOX_TX_QUEUE_LEN - chan->msg_count;
+
+	return ret;
+}
+EXPORT_SYMBOL_GPL(mbox_chan_tx_slots_available);
+
 /**
  * mbox_send_message -	For client to submit a message to be
  *				sent to the remote.
@@ -246,7 +267,7 @@ int mbox_send_message(struct mbox_chan *chan, void *mssg)
 {
 	int t;
 
-	if (!chan || !chan->cl)
+	if (!chan || !chan->cl || mssg == MBOX_NO_MSG)
 		return -EINVAL;
 
 	t = add_to_rbuf(chan, mssg);
@@ -319,12 +340,12 @@ static int __mbox_bind_client(struct mbox_chan *chan, struct mbox_client *cl)
 	scoped_guard(spinlock_irqsave, &chan->lock) {
 		chan->msg_free = 0;
 		chan->msg_count = 0;
-		chan->active_req = NULL;
+		chan->active_req = MBOX_NO_MSG;
 		chan->cl = cl;
 		init_completion(&chan->tx_complete);
 
-		if (chan->txdone_method	== TXDONE_BY_POLL && cl->knows_txdone)
-			chan->txdone_method = TXDONE_BY_ACK;
+		if (chan->txdone_method	== MBOX_TXDONE_BY_POLL && cl->knows_txdone)
+			chan->txdone_method = MBOX_TXDONE_BY_ACK;
 	}
 
 	if (chan->mbox->ops->startup) {
@@ -341,7 +362,7 @@ static int __mbox_bind_client(struct mbox_chan *chan, struct mbox_client *cl)
 }
 
 /**
- * mbox_bind_client - Request a mailbox channel.
+ * mbox_bind_client - Bind client to a mailbox channel.
  * @chan: The mailbox channel to bind the client to.
  * @cl: Identity of the client requesting the channel.
  *
@@ -477,9 +498,9 @@ void mbox_free_channel(struct mbox_chan *chan)
 	/* The queued TX requests are simply aborted, no callbacks are made */
 	scoped_guard(spinlock_irqsave, &chan->lock) {
 		chan->cl = NULL;
-		chan->active_req = NULL;
-		if (chan->txdone_method == TXDONE_BY_ACK)
-			chan->txdone_method = TXDONE_BY_POLL;
+		chan->active_req = MBOX_NO_MSG;
+		if (chan->txdone_method == MBOX_TXDONE_BY_ACK)
+			chan->txdone_method = MBOX_TXDONE_BY_POLL;
 	}
 
 	module_put(chan->mbox->dev->driver->owner);
@@ -505,18 +526,17 @@ int mbox_controller_register(struct mbox_controller *mbox)
 {
 	int i, txdone;
 
-	/* Sanity check */
-	if (!mbox || !mbox->dev || !mbox->ops || !mbox->num_chans)
+	if (!mbox || !mbox->dev || !mbox->ops || !mbox->chans || !mbox->num_chans)
 		return -EINVAL;
 
 	if (mbox->txdone_irq)
-		txdone = TXDONE_BY_IRQ;
+		txdone = MBOX_TXDONE_BY_IRQ;
 	else if (mbox->txdone_poll)
-		txdone = TXDONE_BY_POLL;
+		txdone = MBOX_TXDONE_BY_POLL;
 	else /* It has to be ACK then */
-		txdone = TXDONE_BY_ACK;
+		txdone = MBOX_TXDONE_BY_ACK;
 
-	if (txdone == TXDONE_BY_POLL) {
+	if (txdone == MBOX_TXDONE_BY_POLL) {
 
 		if (!mbox->ops->last_tx_done) {
 			dev_err(mbox->dev, "last_tx_done method is absent\n");
@@ -532,6 +552,7 @@ int mbox_controller_register(struct mbox_controller *mbox)
 
 		chan->cl = NULL;
 		chan->mbox = mbox;
+		chan->active_req = MBOX_NO_MSG;
 		chan->txdone_method = txdone;
 		spin_lock_init(&chan->lock);
 	}
diff --git a/drivers/mailbox/mailbox.h b/drivers/mailbox/mailbox.h
deleted file mode 100644
index e1ec4efab693..000000000000
--- a/drivers/mailbox/mailbox.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-only */
-
-#ifndef __MAILBOX_H
-#define __MAILBOX_H
-
-#include <linux/bits.h>
-
-#define TXDONE_BY_IRQ	BIT(0) /* controller has remote RTR irq */
-#define TXDONE_BY_POLL	BIT(1) /* controller can read status of last TX */
-#define TXDONE_BY_ACK	BIT(2) /* S/W ACK received by Client ticks the TX */
-
-#endif /* __MAILBOX_H */
diff --git a/drivers/mailbox/mtk-cmdq-mailbox.c b/drivers/mailbox/mtk-cmdq-mailbox.c
index d7c6b38888a3..e523c84b4808 100644
--- a/drivers/mailbox/mtk-cmdq-mailbox.c
+++ b/drivers/mailbox/mtk-cmdq-mailbox.c
@@ -493,14 +493,14 @@ static int cmdq_mbox_send_data(struct mbox_chan *chan, void *data)
 		if (curr_pa == end_pa - CMDQ_INST_SIZE ||
 		    curr_pa == end_pa) {
 			/* set to this task directly */
-			writel(task->pa_base >> cmdq->pdata->shift,
-			       thread->base + CMDQ_THR_CURR_ADDR);
+			gce_addr = cmdq_convert_gce_addr(task->pa_base, cmdq->pdata);
+			writel(gce_addr, thread->base + CMDQ_THR_CURR_ADDR);
 		} else {
 			cmdq_task_insert_into_thread(task);
 			smp_mb(); /* modify jump before enable thread */
 		}
-		writel((task->pa_base + pkt->cmd_buf_size) >> cmdq->pdata->shift,
-		       thread->base + CMDQ_THR_END_ADDR);
+		gce_addr = cmdq_convert_gce_addr(task->pa_base + pkt->cmd_buf_size, cmdq->pdata);
+		writel(gce_addr, thread->base + CMDQ_THR_END_ADDR);
 		cmdq_thread_resume(thread);
 	}
 	list_move_tail(&task->list_entry, &thread->task_busy_list);
@@ -728,7 +728,7 @@ static int cmdq_probe(struct platform_device *pdev)
 	cmdq->mbox.ops = &cmdq_mbox_chan_ops;
 	cmdq->mbox.of_xlate = cmdq_xlate;
 
-	/* make use of TXDONE_BY_ACK */
+	/* make use of MBOX_TXDONE_BY_ACK */
 	cmdq->mbox.txdone_irq = false;
 	cmdq->mbox.txdone_poll = false;
 
diff --git a/drivers/mailbox/mtk-vcp-mailbox.c b/drivers/mailbox/mtk-vcp-mailbox.c
index cedad575528f..1b291b8ea15a 100644
--- a/drivers/mailbox/mtk-vcp-mailbox.c
+++ b/drivers/mailbox/mtk-vcp-mailbox.c
@@ -50,7 +50,7 @@ static struct mbox_chan *mtk_vcp_mbox_xlate(struct mbox_controller *mbox,
 					    const struct of_phandle_args *sp)
 {
 	if (sp->args_count)
-		return NULL;
+		return ERR_PTR(-EINVAL);
 
 	return &mbox->chans[0];
 }
diff --git a/drivers/mailbox/omap-mailbox.c b/drivers/mailbox/omap-mailbox.c
index d9f100c18895..535ca8020877 100644
--- a/drivers/mailbox/omap-mailbox.c
+++ b/drivers/mailbox/omap-mailbox.c
@@ -22,8 +22,6 @@
 #include <linux/pm_runtime.h>
 #include <linux/mailbox_controller.h>
 
-#include "mailbox.h"
-
 #define MAILBOX_REVISION		0x000
 #define MAILBOX_MESSAGE(m)		(0x040 + 4 * (m))
 #define MAILBOX_FIFOSTATUS(m)		(0x080 + 4 * (m))
@@ -240,7 +238,7 @@ static int omap_mbox_startup(struct omap_mbox *mbox)
 	}
 
 	if (mbox->send_no_irq)
-		mbox->chan->txdone_method = TXDONE_BY_ACK;
+		mbox->chan->txdone_method = MBOX_TXDONE_BY_ACK;
 
 	omap_mbox_enable_irq(mbox, IRQ_RX);
 
diff --git a/drivers/mailbox/pcc.c b/drivers/mailbox/pcc.c
index 22e70af1ae5d..636879ae1db7 100644
--- a/drivers/mailbox/pcc.c
+++ b/drivers/mailbox/pcc.c
@@ -59,8 +59,6 @@
 #include <linux/io-64-nonatomic-lo-hi.h>
 #include <acpi/pcc.h>
 
-#include "mailbox.h"
-
 #define MBOX_IRQ_NAME		"pcc-mbox"
 
 /**
diff --git a/drivers/mailbox/rockchip-mailbox.c b/drivers/mailbox/rockchip-mailbox.c
index 4d966cb2ed03..a1a7dee64356 100644
--- a/drivers/mailbox/rockchip-mailbox.c
+++ b/drivers/mailbox/rockchip-mailbox.c
@@ -46,7 +46,7 @@ struct rockchip_mbox {
 	/* The maximum size of buf for each channel */
 	u32 buf_size;
 
-	struct rockchip_mbox_chan *chans;
+	struct rockchip_mbox_chan chans[];
 };
 
 static int rockchip_mbox_send_data(struct mbox_chan *chan, void *data)
@@ -173,15 +173,10 @@ static int rockchip_mbox_probe(struct platform_device *pdev)
 
 	drv_data = (const struct rockchip_mbox_data *) device_get_match_data(&pdev->dev);
 
-	mb = devm_kzalloc(&pdev->dev, sizeof(*mb), GFP_KERNEL);
+	mb = devm_kzalloc(&pdev->dev, struct_size(mb, chans, drv_data->num_chans), GFP_KERNEL);
 	if (!mb)
 		return -ENOMEM;
 
-	mb->chans = devm_kcalloc(&pdev->dev, drv_data->num_chans,
-				 sizeof(*mb->chans), GFP_KERNEL);
-	if (!mb->chans)
-		return -ENOMEM;
-
 	mb->mbox.chans = devm_kcalloc(&pdev->dev, drv_data->num_chans,
 				      sizeof(*mb->mbox.chans), GFP_KERNEL);
 	if (!mb->mbox.chans)
diff --git a/drivers/mailbox/tegra-hsp.c b/drivers/mailbox/tegra-hsp.c
index ed9a0bb2bcd8..500fa77c7d53 100644
--- a/drivers/mailbox/tegra-hsp.c
+++ b/drivers/mailbox/tegra-hsp.c
@@ -16,8 +16,6 @@
 
 #include <dt-bindings/mailbox/tegra186-hsp.h>
 
-#include "mailbox.h"
-
 #define HSP_INT_IE(x)		(0x100 + ((x) * 4))
 #define HSP_INT_IV		0x300
 #define HSP_INT_IR		0x304
@@ -497,7 +495,7 @@ static int tegra_hsp_mailbox_flush(struct mbox_chan *chan,
 			mbox_chan_txdone(chan, 0);
 
 			/* Wait until channel is empty */
-			if (chan->active_req != NULL)
+			if (chan->active_req != MBOX_NO_MSG)
 				continue;
 
 			return 0;
@@ -516,7 +514,7 @@ static int tegra_hsp_mailbox_startup(struct mbox_chan *chan)
 	struct tegra_hsp *hsp = mb->channel.hsp;
 	unsigned long flags;
 
-	chan->txdone_method = TXDONE_BY_IRQ;
+	chan->txdone_method = MBOX_TXDONE_BY_IRQ;
 
 	/*
 	 * Shared mailboxes start out as consumers by default. FULL and EMPTY
diff --git a/drivers/mtd/ubi/ubi.h b/drivers/mtd/ubi/ubi.h
index af466cd83ae0..95548d5aa930 100644
--- a/drivers/mtd/ubi/ubi.h
+++ b/drivers/mtd/ubi/ubi.h
@@ -160,6 +160,7 @@ struct ubi_vid_io_buf {
  * struct ubi_wl_entry - wear-leveling entry.
  * @u.rb: link in the corresponding (free/used) RB-tree
  * @u.list: link in the protection queue
+ * @u: union of rb_node and list_head
  * @ec: erase counter
  * @pnum: physical eraseblock number
  *
@@ -282,6 +283,7 @@ struct ubi_eba_leb_desc {
  * @writers: number of users holding this volume in read-write mode
  * @exclusive: whether somebody holds this volume in exclusive mode
  * @metaonly: whether somebody is altering only meta data of this volume
+ * @is_dead: prevents taking a reference to the volume
  *
  * @reserved_pebs: how many physical eraseblocks are reserved for this volume
  * @vol_type: volume type (%UBI_DYNAMIC_VOLUME or %UBI_STATIC_VOLUME)
@@ -449,6 +451,7 @@ struct ubi_debug_info {
  *                @vol->eba_tbl.
  * @ref_count: count of references on the UBI device
  * @image_seq: image sequence number recorded on EC headers
+ * @is_dead: prevents taking a reference to the volume
  *
  * @rsvd_pebs: count of reserved physical eraseblocks
  * @avail_pebs: count of available physical eraseblocks
@@ -741,7 +744,7 @@ struct ubi_ainf_volume {
  * @highest_vol_id: highest volume ID
  * @is_empty: flag indicating whether the MTD device is empty or not
  * @force_full_scan: flag indicating whether we need to do a full scan and drop
-		     all existing Fastmap data structures
+ *		     all existing Fastmap data structures
  * @min_ec: lowest erase counter value
  * @max_ec: highest erase counter value
  * @max_sqnum: highest sequence number value
@@ -750,7 +753,7 @@ struct ubi_ainf_volume {
  * @ec_count: a temporary variable used when calculating @mean_ec
  * @aeb_slab_cache: slab cache for &struct ubi_ainf_peb objects
  * @ech: temporary EC header. Only available during scan
- * @vidh: temporary VID buffer. Only available during scan
+ * @vidb: temporary VID buffer. Only available during scan
  *
  * This data structure contains the result of attaching an MTD device and may
  * be used by other UBI sub-systems to build final UBI data structures, further
@@ -1090,7 +1093,7 @@ static inline void ubi_init_vid_buf(const struct ubi_device *ubi,
 }
 
 /**
- * ubi_init_vid_buf - Allocate a VID buffer
+ * ubi_alloc_vid_buf - Allocate a VID buffer
  * @ubi: the UBI device
  * @gfp_flags: GFP flags to use for the allocation
  */
diff --git a/drivers/net/wireless/intel/iwlwifi/mld/ptp.c b/drivers/net/wireless/intel/iwlwifi/mld/ptp.c
index c65f4b56a327..20ae338e5696 100644
--- a/drivers/net/wireless/intel/iwlwifi/mld/ptp.c
+++ b/drivers/net/wireless/intel/iwlwifi/mld/ptp.c
@@ -321,10 +321,10 @@ void iwl_mld_ptp_remove(struct iwl_mld *mld)
 			       mld->ptp_data.ptp_clock_info.name,
 			       ptp_clock_index(mld->ptp_data.ptp_clock));
 
+		cancel_delayed_work_sync(&mld->ptp_data.dwork);
 		ptp_clock_unregister(mld->ptp_data.ptp_clock);
 		mld->ptp_data.ptp_clock = NULL;
 		mld->ptp_data.last_gp2 = 0;
 		mld->ptp_data.wrap_counter = 0;
-		cancel_delayed_work_sync(&mld->ptp_data.dwork);
 	}
 }
diff --git a/drivers/net/wireless/intel/iwlwifi/mvm/ptp.c b/drivers/net/wireless/intel/iwlwifi/mvm/ptp.c
index f7b620136c85..e05e531b09f0 100644
--- a/drivers/net/wireless/intel/iwlwifi/mvm/ptp.c
+++ b/drivers/net/wireless/intel/iwlwifi/mvm/ptp.c
@@ -325,11 +325,11 @@ void iwl_mvm_ptp_remove(struct iwl_mvm *mvm)
 			       mvm->ptp_data.ptp_clock_info.name,
 			       ptp_clock_index(mvm->ptp_data.ptp_clock));
 
+		cancel_delayed_work_sync(&mvm->ptp_data.dwork);
 		ptp_clock_unregister(mvm->ptp_data.ptp_clock);
 		mvm->ptp_data.ptp_clock = NULL;
 		memset(&mvm->ptp_data.ptp_clock_info, 0,
 		       sizeof(mvm->ptp_data.ptp_clock_info));
 		mvm->ptp_data.last_gp2 = 0;
-		cancel_delayed_work_sync(&mvm->ptp_data.dwork);
 	}
 }
diff --git a/drivers/ntb/hw/amd/ntb_hw_amd.c b/drivers/ntb/hw/amd/ntb_hw_amd.c
index 1a163596ddf5..df9150669ad3 100644
--- a/drivers/ntb/hw/amd/ntb_hw_amd.c
+++ b/drivers/ntb/hw/amd/ntb_hw_amd.c
@@ -376,7 +376,7 @@ static int amd_ntb_link_disable(struct ntb_dev *ntb)
 
 	if (ndev->ntb.topo == NTB_TOPO_SEC)
 		return -EINVAL;
-	dev_dbg(&ntb->pdev->dev, "Enabling Link.\n");
+	dev_dbg(&ntb->pdev->dev, "Disabling Link.\n");
 
 	return 0;
 }
diff --git a/drivers/parisc/led.c b/drivers/parisc/led.c
index b299fcc48b08..016c9d5a60a8 100644
--- a/drivers/parisc/led.c
+++ b/drivers/parisc/led.c
@@ -543,10 +543,8 @@ static void __init register_led_regions(void)
 
 static int __init startup_leds(void)
 {
-	if (platform_device_register(&platform_leds)) {
-		pr_info("LED: failed to register LEDs\n");
-		platform_device_put(&platform_leds);
-	}
+	if (platform_device_register(&platform_leds))
+                printk(KERN_INFO "LED: failed to register LEDs\n");
 	register_led_regions();
 	return 0;
 }
diff --git a/drivers/platform/chrome/cros_ec_sensorhub.c b/drivers/platform/chrome/cros_ec_sensorhub.c
index 9bad8f72680e..f938c3fc84e4 100644
--- a/drivers/platform/chrome/cros_ec_sensorhub.c
+++ b/drivers/platform/chrome/cros_ec_sensorhub.c
@@ -122,8 +122,12 @@ static int cros_ec_sensorhub_register(struct device *dev,
 		sensor_type[sensorhub->resp->info.type]++;
 	}
 
-	if (sensor_type[MOTIONSENSE_TYPE_ACCEL] >= 2)
+	if (sensor_type[MOTIONSENSE_TYPE_ACCEL] >= 2) {
 		ec->has_kb_wake_angle = true;
+		if (ec->group && sysfs_update_group(&ec->class_dev.kobj,
+						    ec->group))
+			dev_warn(dev, "Unable to update sysfs");
+	}
 
 	if (cros_ec_check_features(ec,
 				   EC_FEATURE_REFINED_TABLET_MODE_HYSTERESIS)) {
diff --git a/drivers/platform/chrome/cros_ec_sysfs.c b/drivers/platform/chrome/cros_ec_sysfs.c
index f22e9523da3e..9d3767ab1548 100644
--- a/drivers/platform/chrome/cros_ec_sysfs.c
+++ b/drivers/platform/chrome/cros_ec_sysfs.c
@@ -405,7 +405,8 @@ static int cros_ec_sysfs_probe(struct platform_device *pd)
 	struct device *dev = &pd->dev;
 	int ret;
 
-	ret = sysfs_create_group(&ec_dev->class_dev.kobj, &cros_ec_attr_group);
+	ec_dev->group = &cros_ec_attr_group;
+	ret = sysfs_create_group(&ec_dev->class_dev.kobj, ec_dev->group);
 	if (ret < 0)
 		dev_err(dev, "failed to create attributes. err=%d\n", ret);
 
@@ -416,7 +417,7 @@ static void cros_ec_sysfs_remove(struct platform_device *pd)
 {
 	struct cros_ec_dev *ec_dev = dev_get_drvdata(pd->dev.parent);
 
-	sysfs_remove_group(&ec_dev->class_dev.kobj, &cros_ec_attr_group);
+	sysfs_remove_group(&ec_dev->class_dev.kobj, ec_dev->group);
 }
 
 static const struct platform_device_id cros_ec_sysfs_id[] = {
diff --git a/drivers/platform/chrome/cros_kbd_led_backlight.c b/drivers/platform/chrome/cros_kbd_led_backlight.c
index f4c2282129f5..80dc52833dc9 100644
--- a/drivers/platform/chrome/cros_kbd_led_backlight.c
+++ b/drivers/platform/chrome/cros_kbd_led_backlight.c
@@ -32,12 +32,11 @@ struct keyboard_led {
  * @brightness_set_blocking:	Set LED brightness level.  It can block the
  *				caller for the time required for accessing a
  *				LED device register
- * @max_brightness:		Maximum brightness.
  *
  * See struct led_classdev in include/linux/leds.h for more details.
  */
 struct keyboard_led_drvdata {
-	int (*init)(struct platform_device *pdev);
+	int (*init)(struct platform_device *pdev, struct keyboard_led *keyboard_led);
 
 	enum led_brightness (*brightness_get)(struct led_classdev *led_cdev);
 
@@ -45,12 +44,8 @@ struct keyboard_led_drvdata {
 			       enum led_brightness brightness);
 	int (*brightness_set_blocking)(struct led_classdev *led_cdev,
 				       enum led_brightness brightness);
-
-	enum led_brightness max_brightness;
 };
 
-#define KEYBOARD_BACKLIGHT_MAX 100
-
 #ifdef CONFIG_ACPI
 
 /* Keyboard LED ACPI Device must be defined in firmware */
@@ -94,7 +89,8 @@ keyboard_led_get_brightness_acpi(struct led_classdev *cdev)
 	return brightness;
 }
 
-static int keyboard_led_init_acpi(struct platform_device *pdev)
+static int keyboard_led_init_acpi(struct platform_device *pdev,
+				  struct keyboard_led *keyboard_led)
 {
 	acpi_handle handle;
 	acpi_status status;
@@ -116,17 +112,15 @@ static const struct keyboard_led_drvdata keyboard_led_drvdata_acpi = {
 	.init = keyboard_led_init_acpi,
 	.brightness_set = keyboard_led_set_brightness_acpi,
 	.brightness_get = keyboard_led_get_brightness_acpi,
-	.max_brightness = KEYBOARD_BACKLIGHT_MAX,
 };
 
 #endif /* CONFIG_ACPI */
 
-#if IS_ENABLED(CONFIG_MFD_CROS_EC_DEV)
-static int keyboard_led_init_ec_pwm_mfd(struct platform_device *pdev)
+static int keyboard_led_init_ec_pwm_mfd(struct platform_device *pdev,
+					struct keyboard_led *keyboard_led)
 {
 	struct cros_ec_dev *ec_dev = dev_get_drvdata(pdev->dev.parent);
 	struct cros_ec_device *cros_ec = ec_dev->ec_dev;
-	struct keyboard_led *keyboard_led = platform_get_drvdata(pdev);
 
 	keyboard_led->ec = cros_ec;
 
@@ -175,15 +169,8 @@ static const struct keyboard_led_drvdata keyboard_led_drvdata_ec_pwm_mfd = {
 	.init = keyboard_led_init_ec_pwm_mfd,
 	.brightness_set_blocking = keyboard_led_set_brightness_ec_pwm,
 	.brightness_get = keyboard_led_get_brightness_ec_pwm,
-	.max_brightness = KEYBOARD_BACKLIGHT_MAX,
 };
 
-#else /* IS_ENABLED(CONFIG_MFD_CROS_EC_DEV) */
-
-static const struct keyboard_led_drvdata keyboard_led_drvdata_ec_pwm_mfd = {};
-
-#endif /* IS_ENABLED(CONFIG_MFD_CROS_EC_DEV) */
-
 static int keyboard_led_is_mfd_device(struct platform_device *pdev)
 {
 	return IS_ENABLED(CONFIG_MFD_CROS_EC_DEV) && mfd_get_cell(pdev);
@@ -205,17 +192,16 @@ static int keyboard_led_probe(struct platform_device *pdev)
 	keyboard_led = devm_kzalloc(&pdev->dev, sizeof(*keyboard_led), GFP_KERNEL);
 	if (!keyboard_led)
 		return -ENOMEM;
-	platform_set_drvdata(pdev, keyboard_led);
 
 	if (drvdata->init) {
-		err = drvdata->init(pdev);
+		err = drvdata->init(pdev, keyboard_led);
 		if (err)
 			return err;
 	}
 
 	keyboard_led->cdev.name = "chromeos::kbd_backlight";
 	keyboard_led->cdev.flags |= LED_CORE_SUSPENDRESUME | LED_REJECT_NAME_CONFLICT;
-	keyboard_led->cdev.max_brightness = drvdata->max_brightness;
+	keyboard_led->cdev.max_brightness = 100;
 	keyboard_led->cdev.brightness_set = drvdata->brightness_set;
 	keyboard_led->cdev.brightness_set_blocking = drvdata->brightness_set_blocking;
 	keyboard_led->cdev.brightness_get = drvdata->brightness_get;
diff --git a/drivers/scsi/device_handler/scsi_dh_alua.c b/drivers/scsi/device_handler/scsi_dh_alua.c
index efb08b9b145a..80ab0ff921d4 100644
--- a/drivers/scsi/device_handler/scsi_dh_alua.c
+++ b/drivers/scsi/device_handler/scsi_dh_alua.c
@@ -37,7 +37,7 @@
 #define TPGS_MODE_EXPLICIT		0x2
 
 #define ALUA_RTPG_SIZE			128
-#define ALUA_FAILOVER_TIMEOUT		60
+#define ALUA_FAILOVER_TIMEOUT		255	/* max 255 (8-bit value) */
 #define ALUA_FAILOVER_RETRIES		5
 #define ALUA_RTPG_DELAY_MSECS		5
 #define ALUA_RTPG_RETRY_DELAY		2
diff --git a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
index fda07b193137..14d563e82d20 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_v3_hw.c
@@ -1491,7 +1491,7 @@ static void prep_ata_v3_hw(struct hisi_hba *hisi_hba,
 		phy_id = device->phy->identify.phy_identifier;
 		hdr->dw0 |= cpu_to_le32((1U << phy_id)
 				<< CMD_HDR_PHY_ID_OFF);
-		hdr->dw0 |= CMD_HDR_FORCE_PHY_MSK;
+		hdr->dw0 |= cpu_to_le32(CMD_HDR_FORCE_PHY_MSK);
 		hdr->dw0 |= cpu_to_le32(4U << CMD_HDR_CMD_OFF);
 	}
 
diff --git a/drivers/scsi/mpt3sas/mpt3sas_scsih.c b/drivers/scsi/mpt3sas/mpt3sas_scsih.c
index 6ff788557294..12caffeed3a0 100644
--- a/drivers/scsi/mpt3sas/mpt3sas_scsih.c
+++ b/drivers/scsi/mpt3sas/mpt3sas_scsih.c
@@ -2738,8 +2738,20 @@ scsih_sdev_configure(struct scsi_device *sdev, struct queue_limits *lim)
 				pcie_device->enclosure_level,
 				pcie_device->connector_name);
 
+		/*
+		 * The HBA firmware passes the NVMe drive's MDTS
+		 * (Maximum Data Transfer Size) up to the driver. However,
+		 * the driver hardcodes a 4K buffer size for the PRP list,
+		 * accommodating at most 512 entries. This strictly limits
+		 * the maximum supported NVMe I/O transfer to 2 MiB.
+		 *
+		 * Cap max_hw_sectors to the smaller of the drive's reported
+		 * MDTS or the 2 MiB driver limit to prevent kernel oopses.
+		 */
+		lim->max_hw_sectors = SZ_2M >> SECTOR_SHIFT;
 		if (pcie_device->nvme_mdts)
-			lim->max_hw_sectors = pcie_device->nvme_mdts / 512;
+			lim->max_hw_sectors = min(lim->max_hw_sectors,
+					pcie_device->nvme_mdts >> SECTOR_SHIFT);
 
 		pcie_device_put(pcie_device);
 		spin_unlock_irqrestore(&ioc->pcie_device_lock, flags);
diff --git a/drivers/scsi/pmcraid.h b/drivers/scsi/pmcraid.h
index 9f59930e8b4f..cd059b7599b4 100644
--- a/drivers/scsi/pmcraid.h
+++ b/drivers/scsi/pmcraid.h
@@ -657,7 +657,7 @@ struct pmcraid_hostrcb {
  */
 struct pmcraid_instance {
 	/* Array of allowed-to-be-exposed resources, initialized from
-	 * Configutation Table, later updated with CCNs
+	 * Configuration Table, later updated with CCNs
 	 */
 	struct pmcraid_resource_entry *res_entries;
 
diff --git a/drivers/scsi/sg.c b/drivers/scsi/sg.c
index 2b4b2a1a8e44..74cd4e8a61c2 100644
--- a/drivers/scsi/sg.c
+++ b/drivers/scsi/sg.c
@@ -1801,7 +1801,7 @@ sg_start_req(Sg_request *srp, unsigned char *cmd)
 	}
 
 	res = blk_rq_map_user_io(rq, md, hp->dxferp, hp->dxfer_len,
-			GFP_ATOMIC, iov_count, iov_count, 1, rw);
+			GFP_KERNEL, iov_count, iov_count, 1, rw);
 	if (!res) {
 		srp->bio = rq->bio;
 
diff --git a/drivers/scsi/smartpqi/smartpqi_init.c b/drivers/scsi/smartpqi/smartpqi_init.c
index b4ed991976d0..2026ac645d6a 100644
--- a/drivers/scsi/smartpqi/smartpqi_init.c
+++ b/drivers/scsi/smartpqi/smartpqi_init.c
@@ -9427,6 +9427,7 @@ static void pqi_shutdown(struct pci_dev *pci_dev)
 
 	pqi_crash_if_pending_command(ctrl_info);
 	pqi_reset(ctrl_info);
+	pqi_ctrl_unblock_device_reset(ctrl_info);
 }
 
 static void pqi_process_lockup_action_param(void)
diff --git a/drivers/soc/aspeed/Kconfig b/drivers/soc/aspeed/Kconfig
index f579ee0b5afa..63a656449a1a 100644
--- a/drivers/soc/aspeed/Kconfig
+++ b/drivers/soc/aspeed/Kconfig
@@ -46,7 +46,6 @@ config ASPEED_P2A_CTRL
 
 config ASPEED_SOCINFO
 	bool "ASPEED SoC Information driver"
-	default ARCH_ASPEED
 	select SOC_BUS
 	default ARCH_ASPEED
 	help
diff --git a/drivers/soc/fsl/qe/qe.c b/drivers/soc/fsl/qe/qe.c
index 70b6eddb867b..3ecc4ce9cfa2 100644
--- a/drivers/soc/fsl/qe/qe.c
+++ b/drivers/soc/fsl/qe/qe.c
@@ -89,6 +89,9 @@ void qe_reset(void)
 	if (qe_immr == NULL)
 		qe_immr = ioremap(get_qe_base(), QE_IMMAP_SIZE);
 
+	if (!qe_immr)
+		panic("QE:ioremap failed!");
+
 	qe_snums_init();
 
 	qe_issue_cmd(QE_RESET, QE_CR_SUBBLOCK_INVALID,
diff --git a/drivers/soc/fsl/qe/qe_ports_ic.c b/drivers/soc/fsl/qe/qe_ports_ic.c
index 8e2107e2cde5..9b0bba64e91e 100644
--- a/drivers/soc/fsl/qe/qe_ports_ic.c
+++ b/drivers/soc/fsl/qe/qe_ports_ic.c
@@ -17,6 +17,7 @@
 struct qepic_data {
 	void __iomem *reg;
 	struct irq_domain *host;
+	int irq;
 };
 
 static void qepic_mask(struct irq_data *d)
@@ -92,11 +93,18 @@ static const struct irq_domain_ops qepic_host_ops = {
 	.map = qepic_host_map,
 };
 
+static void qepic_remove(void *res)
+{
+	struct qepic_data *data = res;
+
+	irq_set_chained_handler_and_data(data->irq, NULL, NULL);
+	irq_domain_remove(data->host);
+}
+
 static int qepic_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
 	struct qepic_data *data;
-	int irq;
 
 	data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
 	if (!data)
@@ -106,17 +114,18 @@ static int qepic_probe(struct platform_device *pdev)
 	if (IS_ERR(data->reg))
 		return PTR_ERR(data->reg);
 
-	irq = platform_get_irq(pdev, 0);
-	if (irq < 0)
-		return irq;
+	data->irq = platform_get_irq(pdev, 0);
+	if (data->irq < 0)
+		return data->irq;
 
-	data->host = irq_domain_add_linear(dev->of_node, 32, &qepic_host_ops, data);
+	data->host = irq_domain_create_linear(dev_fwnode(dev), 32, &qepic_host_ops, data);
 	if (!data->host)
 		return -ENODEV;
 
-	irq_set_chained_handler_and_data(irq, qepic_cascade, data);
+	irq_set_chained_handler_and_data(data->irq, qepic_cascade, data);
+
+	return devm_add_action_or_reset(dev, qepic_remove, data);
 
-	return 0;
 }
 
 static const struct of_device_id qepic_match[] = {
diff --git a/drivers/soc/qcom/rpmh-rsc.c b/drivers/soc/qcom/rpmh-rsc.c
index c6f7d5c9c493..ad5ec5c0de0a 100644
--- a/drivers/soc/qcom/rpmh-rsc.c
+++ b/drivers/soc/qcom/rpmh-rsc.c
@@ -146,10 +146,10 @@ enum {
  *  +---------------------------------------------------+
  */
 
-#define USECS_TO_CYCLES(time_usecs)			\
-	xloops_to_cycles((time_usecs) * 0x10C7UL)
+#define RPMH_USECS_TO_CYCLES(time_usecs)		\
+	rpmh_xloops_to_cycles((time_usecs) * 0x10C7UL)
 
-static inline unsigned long xloops_to_cycles(u64 xloops)
+static inline unsigned long rpmh_xloops_to_cycles(u64 xloops)
 {
 	return (xloops * loops_per_jiffy * HZ) >> 32;
 }
@@ -819,7 +819,7 @@ void rpmh_rsc_write_next_wakeup(struct rsc_drv *drv)
 	wakeup_us = ktime_to_us(wakeup);
 
 	/* Convert the wakeup to arch timer scale */
-	wakeup_cycles = USECS_TO_CYCLES(wakeup_us);
+	wakeup_cycles = RPMH_USECS_TO_CYCLES(wakeup_us);
 	wakeup_cycles += arch_timer_read_counter();
 
 exit:
diff --git a/drivers/soc/xilinx/zynqmp_power.c b/drivers/soc/xilinx/zynqmp_power.c
index 9085db1b480a..370e61ac47d8 100644
--- a/drivers/soc/xilinx/zynqmp_power.c
+++ b/drivers/soc/xilinx/zynqmp_power.c
@@ -303,18 +303,18 @@ static int zynqmp_pm_probe(struct platform_device *pdev)
 	 * is not available to use) or -ENODEV(Xilinx Event Manager not compiled),
 	 * then use ipi-mailbox or interrupt method.
 	 */
+	zynqmp_pm_init_suspend_work = devm_kzalloc(&pdev->dev,
+						   sizeof(struct zynqmp_pm_work_struct),
+						   GFP_KERNEL);
+	if (!zynqmp_pm_init_suspend_work)
+		return -ENOMEM;
+
+	INIT_WORK(&zynqmp_pm_init_suspend_work->callback_work,
+		  zynqmp_pm_init_suspend_work_fn);
+
 	ret = register_event(&pdev->dev, PM_INIT_SUSPEND_CB, 0, 0, false,
 			     suspend_event_callback);
 	if (!ret) {
-		zynqmp_pm_init_suspend_work = devm_kzalloc(&pdev->dev,
-							   sizeof(struct zynqmp_pm_work_struct),
-							   GFP_KERNEL);
-		if (!zynqmp_pm_init_suspend_work)
-			return -ENOMEM;
-
-		INIT_WORK(&zynqmp_pm_init_suspend_work->callback_work,
-			  zynqmp_pm_init_suspend_work_fn);
-
 		ret = zynqmp_pm_get_family_info(&pm_family_code);
 		if (ret < 0)
 			return ret;
@@ -326,14 +326,6 @@ static int zynqmp_pm_probe(struct platform_device *pdev)
 		else
 			return -ENODEV;
 
-		ret = register_event(&pdev->dev, PM_NOTIFY_CB, node_id, EVENT_SUBSYSTEM_RESTART,
-				     false, subsystem_restart_event_callback);
-		if (ret) {
-			dev_err(&pdev->dev, "Failed to Register with Xilinx Event manager %d\n",
-				ret);
-			return ret;
-		}
-
 		zynqmp_pm_init_restart_work = devm_kzalloc(&pdev->dev,
 							   sizeof(struct zynqmp_pm_work_struct),
 							   GFP_KERNEL);
@@ -342,19 +334,18 @@ static int zynqmp_pm_probe(struct platform_device *pdev)
 
 		INIT_WORK(&zynqmp_pm_init_restart_work->callback_work,
 			  zynqmp_pm_subsystem_restart_work_fn);
+
+		ret = register_event(&pdev->dev, PM_NOTIFY_CB, node_id, EVENT_SUBSYSTEM_RESTART,
+				     false, subsystem_restart_event_callback);
+		if (ret) {
+			dev_err(&pdev->dev, "Failed to Register with Xilinx Event manager %d\n",
+				ret);
+			return ret;
+		}
 	} else if (ret != -EACCES && ret != -ENODEV) {
 		dev_err(&pdev->dev, "Failed to Register with Xilinx Event manager %d\n", ret);
 		return ret;
 	} else if (of_property_present(pdev->dev.of_node, "mboxes")) {
-		zynqmp_pm_init_suspend_work =
-			devm_kzalloc(&pdev->dev,
-				     sizeof(struct zynqmp_pm_work_struct),
-				     GFP_KERNEL);
-		if (!zynqmp_pm_init_suspend_work)
-			return -ENOMEM;
-
-		INIT_WORK(&zynqmp_pm_init_suspend_work->callback_work,
-			  zynqmp_pm_init_suspend_work_fn);
 		client = devm_kzalloc(&pdev->dev, sizeof(*client), GFP_KERNEL);
 		if (!client)
 			return -ENOMEM;
@@ -398,8 +389,10 @@ static void zynqmp_pm_remove(struct platform_device *pdev)
 {
 	sysfs_remove_file(&pdev->dev.kobj, &dev_attr_suspend_mode.attr);
 
-	if (!rx_chan)
+	if (rx_chan) {
 		mbox_free_channel(rx_chan);
+		rx_chan = NULL;
+	}
 }
 
 static const struct of_device_id pm_of_match[] = {
diff --git a/drivers/spi/spi-mpc52xx.c b/drivers/spi/spi-mpc52xx.c
index 924d820448fb..04c2270cd2cf 100644
--- a/drivers/spi/spi-mpc52xx.c
+++ b/drivers/spi/spi-mpc52xx.c
@@ -472,13 +472,15 @@ static int mpc52xx_spi_probe(struct platform_device *op)
 	if (ms->irq0 && ms->irq1) {
 		rc = request_irq(ms->irq0, mpc52xx_spi_irq, 0,
 				  "mpc5200-spi-modf", ms);
-		rc |= request_irq(ms->irq1, mpc52xx_spi_irq, 0,
-				  "mpc5200-spi-spif", ms);
-		if (rc) {
-			free_irq(ms->irq0, ms);
-			free_irq(ms->irq1, ms);
-			ms->irq0 = ms->irq1 = 0;
+		if (rc == 0) {
+			rc = request_irq(ms->irq1, mpc52xx_spi_irq, 0,
+					 "mpc5200-spi-spif", ms);
+			if (rc)
+				free_irq(ms->irq0, ms);
 		}
+
+		if (rc)
+			ms->irq0 = ms->irq1 = 0;
 	} else {
 		/* operate in polled mode */
 		ms->irq0 = ms->irq1 = 0;
@@ -498,8 +500,10 @@ static int mpc52xx_spi_probe(struct platform_device *op)
 
  err_register:
 	dev_err(&ms->host->dev, "initialization failed\n");
-	free_irq(ms->irq0, ms);
-	free_irq(ms->irq1, ms);
+	if (ms->irq0) {
+		free_irq(ms->irq0, ms);
+		free_irq(ms->irq1, ms);
+	}
 	cancel_work_sync(&ms->work);
  err_gpio:
 	while (i-- > 0)
@@ -522,8 +526,10 @@ static void mpc52xx_spi_remove(struct platform_device *op)
 
 	spi_unregister_controller(host);
 
-	free_irq(ms->irq0, ms);
-	free_irq(ms->irq1, ms);
+	if (ms->irq0) {
+		free_irq(ms->irq0, ms);
+		free_irq(ms->irq1, ms);
+	}
 
 	cancel_work_sync(&ms->work);
 
diff --git a/drivers/spi/spi-rockchip.c b/drivers/spi/spi-rockchip.c
index 14cd1b9d9793..231fbcf0e7aa 100644
--- a/drivers/spi/spi-rockchip.c
+++ b/drivers/spi/spi-rockchip.c
@@ -98,7 +98,6 @@
 #define CR0_FRF_MICROWIRE			0x2
 
 #define CR0_XFM_OFFSET				18
-#define CR0_XFM_MASK				(0x03 << SPI_XFM_OFFSET)
 #define CR0_XFM_TR					0x0
 #define CR0_XFM_TO					0x1
 #define CR0_XFM_RO					0x2
@@ -109,8 +108,6 @@
 
 #define CR0_SOI_OFFSET				23
 
-#define CR0_MTM_OFFSET				0x21
-
 /* Bit fields in SER, 2bit */
 #define SER_MASK					0x3
 
@@ -357,7 +354,8 @@ static irqreturn_t rockchip_spi_isr(int irq, void *dev_id)
 	struct rockchip_spi *rs = spi_controller_get_devdata(ctlr);
 
 	/* When int_cs_inactive comes, spi target abort */
-	if (rs->cs_inactive && readl_relaxed(rs->regs + ROCKCHIP_SPI_IMR) & INT_CS_INACTIVE) {
+	if (rs->cs_inactive &&
+	    (readl_relaxed(rs->regs + ROCKCHIP_SPI_ISR) & INT_CS_INACTIVE)) {
 		ctlr->target_abort(ctlr);
 		writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR);
 		writel_relaxed(0xffffffff, rs->regs + ROCKCHIP_SPI_ICR);
diff --git a/drivers/spi/spi-rzv2h-rspi.c b/drivers/spi/spi-rzv2h-rspi.c
index f45af5884638..1655efda7d20 100644
--- a/drivers/spi/spi-rzv2h-rspi.c
+++ b/drivers/spi/spi-rzv2h-rspi.c
@@ -579,7 +579,7 @@ static u32 rzv2h_rspi_setup_clock(struct rzv2h_rspi_priv *rspi, u32 hz)
 		rspi->info->find_pclk_rate(rspi->pclk, hz, &best_clock);
 
 	if (!best_clock.clk_rate)
-		return -EINVAL;
+		return 0;
 
 	ret = clk_set_rate(best_clock.clk, best_clock.clk_rate);
 	if (ret)
diff --git a/drivers/target/iscsi/iscsi_target.c b/drivers/target/iscsi/iscsi_target.c
index e80449f6ce15..cb832fd523af 100644
--- a/drivers/target/iscsi/iscsi_target.c
+++ b/drivers/target/iscsi/iscsi_target.c
@@ -995,6 +995,7 @@ int iscsit_setup_scsi_cmd(struct iscsit_conn *conn, struct iscsit_cmd *cmd,
 	int data_direction, payload_length;
 	struct iscsi_ecdb_ahdr *ecdb_ahdr;
 	struct iscsi_scsi_req *hdr;
+	u16 ahslength, cdb_length;
 	int iscsi_task_attr;
 	unsigned char *cdb;
 	int sam_task_attr;
@@ -1108,14 +1109,27 @@ int iscsit_setup_scsi_cmd(struct iscsit_conn *conn, struct iscsit_cmd *cmd,
 				ISCSI_REASON_CMD_NOT_SUPPORTED, buf);
 		}
 
-		cdb = kmalloc(be16_to_cpu(ecdb_ahdr->ahslength) + 15,
-			      GFP_KERNEL);
+		ahslength = be16_to_cpu(ecdb_ahdr->ahslength);
+		if (!ahslength) {
+			pr_err("Extended CDB AHS with zero length, protocol error.\n");
+			return iscsit_add_reject_cmd(cmd,
+				ISCSI_REASON_PROTOCOL_ERROR, buf);
+		}
+		if (ahslength > (hdr->hlength * 4) - 3) {
+			pr_err("Extended CDB AHS length %u exceeds available PDU buffer.\n",
+			       ahslength);
+			return iscsit_add_reject_cmd(cmd,
+				ISCSI_REASON_PROTOCOL_ERROR, buf);
+		}
+
+		cdb_length = ahslength - 1 + ISCSI_CDB_SIZE;
+
+		cdb = kmalloc(cdb_length, GFP_KERNEL);
 		if (cdb == NULL)
 			return iscsit_add_reject_cmd(cmd,
 				ISCSI_REASON_BOOKMARK_NO_RESOURCES, buf);
 		memcpy(cdb, hdr->cdb, ISCSI_CDB_SIZE);
-		memcpy(cdb + ISCSI_CDB_SIZE, ecdb_ahdr->ecdb,
-		       be16_to_cpu(ecdb_ahdr->ahslength) - 1);
+		memcpy(cdb + ISCSI_CDB_SIZE, ecdb_ahdr->ecdb, cdb_length - ISCSI_CDB_SIZE);
 	}
 
 	data_direction = (hdr->flags & ISCSI_FLAG_CMD_WRITE) ? DMA_TO_DEVICE :
diff --git a/drivers/target/target_core_configfs.c b/drivers/target/target_core_configfs.c
index d93773b3227c..2b19a956007b 100644
--- a/drivers/target/target_core_configfs.c
+++ b/drivers/target/target_core_configfs.c
@@ -3249,7 +3249,7 @@ static ssize_t target_tg_pt_gp_members_show(struct config_item *item,
 			config_item_name(&lun->lun_group.cg_item));
 		cur_len++; /* Extra byte for NULL terminator */
 
-		if ((cur_len + len) > PAGE_SIZE) {
+		if (cur_len > TG_PT_GROUP_NAME_BUF || (cur_len + len) > PAGE_SIZE) {
 			pr_warn("Ran out of lu_gp_show_attr"
 				"_members buffer\n");
 			break;
diff --git a/drivers/tee/optee/supp.c b/drivers/tee/optee/supp.c
index a3d11b1f90fa..06747e90c230 100644
--- a/drivers/tee/optee/supp.c
+++ b/drivers/tee/optee/supp.c
@@ -10,7 +10,11 @@
 struct optee_supp_req {
 	struct list_head link;
 
+	int id;
+
 	bool in_queue;
+	bool processed;
+
 	u32 func;
 	u32 ret;
 	size_t num_params;
@@ -19,6 +23,9 @@ struct optee_supp_req {
 	struct completion c;
 };
 
+/* It is temporary request used for revoked pending request in supp->idr. */
+#define INVALID_REQ_PTR ((struct optee_supp_req *)ERR_PTR(-EBADF))
+
 void optee_supp_init(struct optee_supp *supp)
 {
 	memset(supp, 0, sizeof(*supp));
@@ -39,21 +46,23 @@ void optee_supp_release(struct optee_supp *supp)
 {
 	int id;
 	struct optee_supp_req *req;
-	struct optee_supp_req *req_tmp;
 
 	mutex_lock(&supp->mutex);
 
-	/* Abort all request retrieved by supplicant */
+	/* Abort all request */
 	idr_for_each_entry(&supp->idr, req, id) {
 		idr_remove(&supp->idr, id);
-		req->ret = TEEC_ERROR_COMMUNICATION;
-		complete(&req->c);
-	}
+		/* Skip if request was already marked invalid */
+		if (IS_ERR(req))
+			continue;
 
-	/* Abort all queued requests */
-	list_for_each_entry_safe(req, req_tmp, &supp->reqs, link) {
-		list_del(&req->link);
-		req->in_queue = false;
+		/* For queued requests where supplicant has not seen it */
+		if (req->in_queue) {
+			list_del(&req->link);
+			req->in_queue = false;
+		}
+
+		req->processed = true;
 		req->ret = TEEC_ERROR_COMMUNICATION;
 		complete(&req->c);
 	}
@@ -100,8 +109,16 @@ u32 optee_supp_thrd_req(struct tee_context *ctx, u32 func, size_t num_params,
 
 	/* Insert the request in the request list */
 	mutex_lock(&supp->mutex);
+	req->id = idr_alloc(&supp->idr, req, 1, 0, GFP_KERNEL);
+	if (req->id < 0) {
+		mutex_unlock(&supp->mutex);
+		kfree(req);
+		return TEEC_ERROR_OUT_OF_MEMORY;
+	}
+
 	list_add_tail(&req->link, &supp->reqs);
 	req->in_queue = true;
+	req->processed = false;
 	mutex_unlock(&supp->mutex);
 
 	/* Tell an eventual waiter there's a new request */
@@ -117,21 +134,43 @@ u32 optee_supp_thrd_req(struct tee_context *ctx, u32 func, size_t num_params,
 	if (wait_for_completion_killable(&req->c)) {
 		mutex_lock(&supp->mutex);
 		if (req->in_queue) {
+			/* Supplicant has not seen this request yet. */
+			idr_remove(&supp->idr, req->id);
 			list_del(&req->link);
 			req->in_queue = false;
+
+			ret = TEEC_ERROR_COMMUNICATION;
+		} else if (req->processed) {
+			/*
+			 * Supplicant has processed this request. Ignore the
+			 * kill signal for now and submit the result. req is not
+			 * in supp->reqs (removed by supp_pop_entry()) nor in
+			 * supp->idr (removed by supp_pop_req()).
+			 */
+			ret = req->ret;
+		} else {
+			/*
+			 * Supplicant is in the middle of processing this
+			 * request. Replace req with INVALID_REQ_PTR so that
+			 * the ID remains busy, causing optee_supp_send() to
+			 * fail on the next call to supp_pop_req() with this ID.
+			 */
+			idr_replace(&supp->idr, INVALID_REQ_PTR, req->id);
+			ret = TEEC_ERROR_COMMUNICATION;
 		}
+
 		mutex_unlock(&supp->mutex);
-		req->ret = TEEC_ERROR_COMMUNICATION;
+	} else {
+		ret = req->ret;
 	}
 
-	ret = req->ret;
 	kfree(req);
 
 	return ret;
 }
 
 static struct optee_supp_req  *supp_pop_entry(struct optee_supp *supp,
-					      int num_params, int *id)
+					      int num_params)
 {
 	struct optee_supp_req *req;
 
@@ -153,10 +192,6 @@ static struct optee_supp_req  *supp_pop_entry(struct optee_supp *supp,
 		return ERR_PTR(-EINVAL);
 	}
 
-	*id = idr_alloc(&supp->idr, req, 1, 0, GFP_KERNEL);
-	if (*id < 0)
-		return ERR_PTR(-ENOMEM);
-
 	list_del(&req->link);
 	req->in_queue = false;
 
@@ -214,7 +249,6 @@ int optee_supp_recv(struct tee_context *ctx, u32 *func, u32 *num_params,
 	struct optee *optee = tee_get_drvdata(teedev);
 	struct optee_supp *supp = &optee->supp;
 	struct optee_supp_req *req = NULL;
-	int id;
 	size_t num_meta;
 	int rc;
 
@@ -224,15 +258,11 @@ int optee_supp_recv(struct tee_context *ctx, u32 *func, u32 *num_params,
 
 	while (true) {
 		mutex_lock(&supp->mutex);
-		req = supp_pop_entry(supp, *num_params - num_meta, &id);
+		req = supp_pop_entry(supp, *num_params - num_meta);
+		if (req)
+			break; /* Keep mutex held. */
 		mutex_unlock(&supp->mutex);
 
-		if (req) {
-			if (IS_ERR(req))
-				return PTR_ERR(req);
-			break;
-		}
-
 		/*
 		 * If we didn't get a request we'll block in
 		 * wait_for_completion() to avoid needless spinning.
@@ -245,6 +275,13 @@ int optee_supp_recv(struct tee_context *ctx, u32 *func, u32 *num_params,
 			return -ERESTARTSYS;
 	}
 
+	/* supp->mutex held and req != NULL. */
+
+	if (IS_ERR(req)) {
+		mutex_unlock(&supp->mutex);
+		return PTR_ERR(req);
+	}
+
 	if (num_meta) {
 		/*
 		 * tee-supplicant support meta parameters -> requsts can be
@@ -252,13 +289,11 @@ int optee_supp_recv(struct tee_context *ctx, u32 *func, u32 *num_params,
 		 */
 		param->attr = TEE_IOCTL_PARAM_ATTR_TYPE_VALUE_INOUT |
 			      TEE_IOCTL_PARAM_ATTR_META;
-		param->u.value.a = id;
+		param->u.value.a = req->id;
 		param->u.value.b = 0;
 		param->u.value.c = 0;
 	} else {
-		mutex_lock(&supp->mutex);
-		supp->req_id = id;
-		mutex_unlock(&supp->mutex);
+		supp->req_id = req->id;
 	}
 
 	*func = req->func;
@@ -266,6 +301,7 @@ int optee_supp_recv(struct tee_context *ctx, u32 *func, u32 *num_params,
 	memcpy(param + num_meta, req->param,
 	       sizeof(struct tee_param) * req->num_params);
 
+	mutex_unlock(&supp->mutex);
 	return 0;
 }
 
@@ -297,12 +333,17 @@ static struct optee_supp_req *supp_pop_req(struct optee_supp *supp,
 	if (!req)
 		return ERR_PTR(-ENOENT);
 
+	/* optee_supp_thrd_req() already returned to optee. */
+	if (IS_ERR(req))
+		goto failed_req;
+
 	if ((num_params - nm) != req->num_params)
 		return ERR_PTR(-EINVAL);
 
+	*num_meta = nm;
+failed_req:
 	idr_remove(&supp->idr, id);
 	supp->req_id = -1;
-	*num_meta = nm;
 
 	return req;
 }
@@ -328,10 +369,9 @@ int optee_supp_send(struct tee_context *ctx, u32 ret, u32 num_params,
 
 	mutex_lock(&supp->mutex);
 	req = supp_pop_req(supp, num_params, param, &num_meta);
-	mutex_unlock(&supp->mutex);
-
 	if (IS_ERR(req)) {
-		/* Something is wrong, let supplicant restart. */
+		mutex_unlock(&supp->mutex);
+		/* Something is wrong, let supplicant handel it. */
 		return PTR_ERR(req);
 	}
 
@@ -355,9 +395,10 @@ int optee_supp_send(struct tee_context *ctx, u32 ret, u32 num_params,
 		}
 	}
 	req->ret = ret;
-
+	req->processed = true;
 	/* Let the requesting thread continue */
 	complete(&req->c);
+	mutex_unlock(&supp->mutex);
 
 	return 0;
 }
diff --git a/drivers/thunderbolt/debugfs.c b/drivers/thunderbolt/debugfs.c
index 042f6a0d0f7f..d089d2decedd 100644
--- a/drivers/thunderbolt/debugfs.c
+++ b/drivers/thunderbolt/debugfs.c
@@ -2361,8 +2361,10 @@ static int sb_regs_show(struct tb_port *port, const struct sb_reg *sb_regs,
 		memset(data, 0, sizeof(data));
 		ret = usb4_port_sb_read(port, target, index, regs->reg, data,
 					regs->size);
-		if (ret)
-			return ret;
+		if (ret) {
+			seq_printf(s, "0x%02x <not accessible>\n", regs->reg);
+			continue;
+		}
 
 		seq_printf(s, "0x%02x", regs->reg);
 		for (j = 0; j < regs->size; j++)
diff --git a/drivers/ufs/core/ufshcd.c b/drivers/ufs/core/ufshcd.c
index 4805e40ed4d7..c3f08957d179 100644
--- a/drivers/ufs/core/ufshcd.c
+++ b/drivers/ufs/core/ufshcd.c
@@ -9259,6 +9259,30 @@ static void ufshcd_config_mcq(struct ufs_hba *hba)
 		 hba->nutrs);
 }
 
+/**
+ * ufshcd_get_op_mode - get UFS operating mode.
+ * @hba: per-adapter instance
+ *
+ * Use the PA_PWRMODE value to represent the operating mode of UFS.
+ *
+ */
+static enum ufs_op_mode ufshcd_get_op_mode(struct ufs_hba *hba)
+{
+	u32 mode;
+	u8 rx_mode;
+	u8 tx_mode;
+
+	ufshcd_dme_get(hba, UIC_ARG_MIB(PA_PWRMODE), &mode);
+	rx_mode = (mode >> PWRMODE_RX_OFFSET) & PWRMODE_MASK;
+	tx_mode = mode & PWRMODE_MASK;
+
+	if ((rx_mode == SLOW_MODE || rx_mode == SLOWAUTO_MODE) &&
+	    (tx_mode == SLOW_MODE || tx_mode == SLOWAUTO_MODE))
+		return LS_MODE;
+
+	return HS_MODE;
+}
+
 static int ufshcd_post_device_init(struct ufs_hba *hba)
 {
 	int ret;
@@ -9281,11 +9305,13 @@ static int ufshcd_post_device_init(struct ufs_hba *hba)
 		return 0;
 
 	/*
-	 * Set the right value to bRefClkFreq before attempting to
+	 * Set the right value to bRefClkFreq in LS_MODE before attempting to
 	 * switch to HS gears.
 	 */
-	if (hba->dev_ref_clk_freq != REF_CLK_FREQ_INVAL)
+	if (ufshcd_get_op_mode(hba) == LS_MODE &&
+	    hba->dev_ref_clk_freq != REF_CLK_FREQ_INVAL)
 		ufshcd_set_dev_ref_clk(hba);
+
 	/* Gear up to HS gear. */
 	ret = ufshcd_config_pwr_mode(hba, &hba->max_pwr_info.info,
 				     UFSHCD_PMC_POLICY_DONT_FORCE);
diff --git a/drivers/virt/vmgenid.c b/drivers/virt/vmgenid.c
index 66135eac3abf..2cf0096aa217 100644
--- a/drivers/virt/vmgenid.c
+++ b/drivers/virt/vmgenid.c
@@ -75,7 +75,8 @@ static int vmgenid_add_acpi(struct device *dev, struct vmgenid_state *state)
 	phys_addr = (obj->package.elements[0].integer.value << 0) |
 		    (obj->package.elements[1].integer.value << 32);
 
-	virt_addr = devm_memremap(&device->dev, phys_addr, VMGENID_SIZE, MEMREMAP_WB);
+	virt_addr = devm_memremap(&device->dev, phys_addr, VMGENID_SIZE,
+				  MEMREMAP_WB | MEMREMAP_DEC);
 	if (IS_ERR(virt_addr)) {
 		ret = PTR_ERR(virt_addr);
 		goto out;
diff --git a/fs/Kconfig b/fs/Kconfig
index 43cb06de297f..cf6ae64776e6 100644
--- a/fs/Kconfig
+++ b/fs/Kconfig
@@ -78,7 +78,7 @@ config FS_DAX
 	  --map=mem:
 	  https://docs.pmem.io/ndctl-user-guide/ndctl-man-pages/ndctl-create-namespace
 
-          For ndctl to work CONFIG_DEV_DAX needs to be enabled as well. For most
+	  For ndctl to work CONFIG_DEV_DAX needs to be enabled as well. For most
 	  file systems DAX support needs to be manually enabled globally or
 	  per-inode using a mount option as well.  See the file documentation in
 	  Documentation/filesystems/dax.rst for details.
@@ -116,8 +116,8 @@ config FILE_LOCKING
 	default y
 	help
 	  This option enables standard file locking support, required
-          for filesystems like NFS and for the flock() system
-          call. Disabling this option saves about 11k.
+	  for filesystems like NFS and for the flock() system
+	  call. Disabling this option saves about 11k.
 
 source "fs/crypto/Kconfig"
 
diff --git a/fs/btrfs/extent_io.c b/fs/btrfs/extent_io.c
index ca3e4b99aec2..2275189b7860 100644
--- a/fs/btrfs/extent_io.c
+++ b/fs/btrfs/extent_io.c
@@ -4641,7 +4641,8 @@ int try_release_extent_buffer(struct folio *folio)
  * to read the block we will not block on anything.
  */
 void btrfs_readahead_tree_block(struct btrfs_fs_info *fs_info,
-				u64 bytenr, u64 owner_root, u64 gen, int level)
+				u64 bytenr, u64 owner_root, u64 gen, int level,
+				const struct btrfs_key *first_key)
 {
 	struct btrfs_tree_parent_check check = {
 		.level = level,
@@ -4650,6 +4651,11 @@ void btrfs_readahead_tree_block(struct btrfs_fs_info *fs_info,
 	struct extent_buffer *eb;
 	int ret;
 
+	if (first_key) {
+		memcpy(&check.first_key, first_key, sizeof(struct btrfs_key));
+		check.has_first_key = true;
+	}
+
 	eb = btrfs_find_create_tree_block(fs_info, bytenr, owner_root, level);
 	if (IS_ERR(eb))
 		return;
@@ -4677,9 +4683,13 @@ void btrfs_readahead_tree_block(struct btrfs_fs_info *fs_info,
  */
 void btrfs_readahead_node_child(struct extent_buffer *node, int slot)
 {
+	struct btrfs_key node_key;
+
+	btrfs_node_key_to_cpu(node, &node_key, slot);
 	btrfs_readahead_tree_block(node->fs_info,
 				   btrfs_node_blockptr(node, slot),
 				   btrfs_header_owner(node),
 				   btrfs_node_ptr_generation(node, slot),
-				   btrfs_header_level(node) - 1);
+				   btrfs_header_level(node) - 1,
+				   &node_key);
 }
diff --git a/fs/btrfs/extent_io.h b/fs/btrfs/extent_io.h
index fd209233317f..b310a5145cf6 100644
--- a/fs/btrfs/extent_io.h
+++ b/fs/btrfs/extent_io.h
@@ -287,7 +287,8 @@ static inline void wait_on_extent_buffer_writeback(struct extent_buffer *eb)
 }
 
 void btrfs_readahead_tree_block(struct btrfs_fs_info *fs_info,
-				u64 bytenr, u64 owner_root, u64 gen, int level);
+				u64 bytenr, u64 owner_root, u64 gen, int level,
+				const struct btrfs_key *first_key);
 void btrfs_readahead_node_child(struct extent_buffer *node, int slot);
 
 /* Note: this can be used in for loops without caching the value in a variable. */
diff --git a/fs/btrfs/free-space-tree.c b/fs/btrfs/free-space-tree.c
index 9efd1ec90f03..472b3060e5ac 100644
--- a/fs/btrfs/free-space-tree.c
+++ b/fs/btrfs/free-space-tree.c
@@ -259,7 +259,11 @@ int btrfs_convert_free_space_to_bitmaps(struct btrfs_trans_handle *trans,
 				nr++;
 				path->slots[0]--;
 			} else {
-				ASSERT(0);
+				btrfs_err(fs_info, "unexpected free space tree key type %u",
+					  found_key.type);
+				ret = -EUCLEAN;
+				btrfs_abort_transaction(trans, ret);
+				goto out;
 			}
 		}
 
@@ -405,7 +409,11 @@ int btrfs_convert_free_space_to_extents(struct btrfs_trans_handle *trans,
 
 				nr++;
 			} else {
-				ASSERT(0);
+				btrfs_err(fs_info, "unexpected free space tree key type %u",
+					  found_key.type);
+				ret = -EUCLEAN;
+				btrfs_abort_transaction(trans, ret);
+				goto out;
 			}
 		}
 
@@ -1518,7 +1526,11 @@ int btrfs_remove_block_group_free_space(struct btrfs_trans_handle *trans,
 				nr++;
 				path->slots[0]--;
 			} else {
-				ASSERT(0);
+				btrfs_err(trans->fs_info, "unexpected free space tree key type %u",
+					  found_key.type);
+				ret = -EUCLEAN;
+				btrfs_abort_transaction(trans, ret);
+				return ret;
 			}
 		}
 
diff --git a/fs/btrfs/inode.c b/fs/btrfs/inode.c
index 40474014c03f..906d5c21ebc4 100644
--- a/fs/btrfs/inode.c
+++ b/fs/btrfs/inode.c
@@ -1153,7 +1153,7 @@ static void submit_one_async_extent(struct async_chunk *async_chunk,
 				     NULL, &cached,
 				     EXTENT_LOCKED | EXTENT_DELALLOC |
 				     EXTENT_DELALLOC_NEW |
-				     EXTENT_DEFRAG | EXTENT_DO_ACCOUNTING,
+				     EXTENT_DEFRAG | EXTENT_CLEAR_META_RESV,
 				     PAGE_UNLOCK | PAGE_START_WRITEBACK |
 				     PAGE_END_WRITEBACK);
 	if (async_extent->cb)
@@ -4959,6 +4959,8 @@ static int btrfs_rmdir(struct inode *vfs_dir, struct dentry *dentry)
 	if (ret)
 		goto out;
 
+	btrfs_record_unlink_dir(trans, dir, inode, false);
+
 	/* now the directory is empty */
 	ret = btrfs_unlink_inode(trans, dir, inode, &fname.disk_name);
 	if (!ret)
diff --git a/fs/btrfs/ioctl.c b/fs/btrfs/ioctl.c
index b2e447f5005c..a39460bf68a7 100644
--- a/fs/btrfs/ioctl.c
+++ b/fs/btrfs/ioctl.c
@@ -5102,7 +5102,6 @@ static int btrfs_ioctl_subvol_sync(struct btrfs_fs_info *fs_info, void __user *a
 	return 0;
 }
 
-#ifdef CONFIG_BTRFS_EXPERIMENTAL
 static int btrfs_ioctl_shutdown(struct btrfs_fs_info *fs_info, unsigned long arg)
 {
 	int ret = 0;
@@ -5134,10 +5133,12 @@ static int btrfs_ioctl_shutdown(struct btrfs_fs_info *fs_info, unsigned long arg
 	case BTRFS_SHUTDOWN_FLAGS_NOLOGFLUSH:
 		btrfs_force_shutdown(fs_info);
 		break;
+	default:
+		ret = -EINVAL;
+		break;
 	}
 	return ret;
 }
-#endif
 
 long btrfs_ioctl(struct file *file, unsigned int
 		cmd, unsigned long arg)
@@ -5294,10 +5295,8 @@ long btrfs_ioctl(struct file *file, unsigned int
 #endif
 	case BTRFS_IOC_SUBVOL_SYNC_WAIT:
 		return btrfs_ioctl_subvol_sync(fs_info, argp);
-#ifdef CONFIG_BTRFS_EXPERIMENTAL
 	case BTRFS_IOC_SHUTDOWN:
 		return btrfs_ioctl_shutdown(fs_info, arg);
-#endif
 	}
 
 	return -ENOTTY;
diff --git a/fs/btrfs/raid-stripe-tree.c b/fs/btrfs/raid-stripe-tree.c
index 638c4ad572c9..4b0186c83ad1 100644
--- a/fs/btrfs/raid-stripe-tree.c
+++ b/fs/btrfs/raid-stripe-tree.c
@@ -45,8 +45,11 @@ static int btrfs_partially_delete_raid_extent(struct btrfs_trans_handle *trans,
 
 	for (int i = 0; i < btrfs_num_raid_stripes(item_size); i++) {
 		struct btrfs_raid_stride *stride = &extent->strides[i];
+		u64 devid;
 		u64 phys;
 
+		devid = btrfs_raid_stride_devid(leaf, stride);
+		btrfs_set_stack_raid_stride_devid(&newitem->strides[i], devid);
 		phys = btrfs_raid_stride_physical(leaf, stride) + frontpad;
 		btrfs_set_stack_raid_stride_physical(&newitem->strides[i], phys);
 	}
@@ -95,14 +98,26 @@ int btrfs_delete_raid_extent(struct btrfs_trans_handle *trans, u64 start, u64 le
 	while (1) {
 		key.objectid = start;
 		key.type = BTRFS_RAID_STRIPE_KEY;
-		key.offset = 0;
+		key.offset = (u64)-1;
 
 		ret = btrfs_search_slot(trans, stripe_root, &key, path, -1, 1);
 		if (ret < 0)
 			break;
 
-		if (path->slots[0] == btrfs_header_nritems(path->nodes[0]))
-			path->slots[0]--;
+		/*
+		 * Search with offset=(u64)-1 ensures we land on the correct
+		 * leaf even when the target entry is the first item on a leaf.
+		 * Since no real entry has offset=(u64)-1, ret is always 1 and
+		 * slot points past the last entry with objectid==start (or
+		 * past the end of the leaf if that entry is the last item).
+		 * Back up one slot to find the actual entry.
+		 */
+		if (path->slots[0] == 0) {
+			/* No entry with objectid <= start exists. */
+			ret = 0;
+			break;
+		}
+		path->slots[0]--;
 
 		leaf = path->nodes[0];
 		slot = path->slots[0];
@@ -123,7 +138,7 @@ int btrfs_delete_raid_extent(struct btrfs_trans_handle *trans, u64 start, u64 le
 		 */
 		if (found_start > start) {
 			if (slot == 0) {
-				ret = btrfs_previous_item(stripe_root, path, start,
+				ret = btrfs_previous_item(stripe_root, path, 0,
 							  BTRFS_RAID_STRIPE_KEY);
 				if (ret) {
 					if (ret > 0)
@@ -139,7 +154,10 @@ int btrfs_delete_raid_extent(struct btrfs_trans_handle *trans, u64 start, u64 le
 			btrfs_item_key_to_cpu(leaf, &key, slot);
 			found_start = key.objectid;
 			found_end = found_start + key.offset;
-			ASSERT(found_start <= start);
+			if (found_start > start || found_end <= start) {
+				ret = -ENOENT;
+				break;
+			}
 		}
 
 		if (key.type != BTRFS_RAID_STRIPE_KEY)
@@ -176,9 +194,19 @@ int btrfs_delete_raid_extent(struct btrfs_trans_handle *trans, u64 start, u64 le
 
 			/* The "right" item. */
 			ret = btrfs_duplicate_item(trans, stripe_root, path, &newkey);
+			if (ret == -EAGAIN) {
+				btrfs_release_path(path);
+				continue;
+			}
 			if (ret)
 				break;
 
+			/*
+			 * btrfs_duplicate_item() may have triggered a leaf
+			 * split via setup_leaf_for_split(), so we must refresh
+			 * our leaf pointer from the path.
+			 */
+			leaf = path->nodes[0];
 			item_size = btrfs_item_size(leaf, path->slots[0]);
 			extent = btrfs_item_ptr(leaf, path->slots[0],
 						struct btrfs_stripe_extent);
@@ -195,8 +223,9 @@ int btrfs_delete_raid_extent(struct btrfs_trans_handle *trans, u64 start, u64 le
 			/* The "left" item. */
 			path->slots[0]--;
 			btrfs_item_key_to_cpu(leaf, &key, path->slots[0]);
-			btrfs_partially_delete_raid_extent(trans, path, &key,
-							   diff_start, 0);
+			ret = btrfs_partially_delete_raid_extent(trans, path,
+								 &key,
+								 diff_start, 0);
 			break;
 		}
 
@@ -212,8 +241,11 @@ int btrfs_delete_raid_extent(struct btrfs_trans_handle *trans, u64 start, u64 le
 		if (found_start < start) {
 			u64 diff_start = start - found_start;
 
-			btrfs_partially_delete_raid_extent(trans, path, &key,
-							   diff_start, 0);
+			ret = btrfs_partially_delete_raid_extent(trans, path,
+								 &key,
+								 diff_start, 0);
+			if (ret)
+				break;
 
 			start += (key.offset - diff_start);
 			length -= (key.offset - diff_start);
@@ -236,9 +268,10 @@ int btrfs_delete_raid_extent(struct btrfs_trans_handle *trans, u64 start, u64 le
 		if (found_end > end) {
 			u64 diff_end = found_end - end;
 
-			btrfs_partially_delete_raid_extent(trans, path, &key,
-							   key.offset - length,
-							   length);
+			ret = btrfs_partially_delete_raid_extent(trans, path,
+								 &key,
+								 key.offset - length,
+								 length);
 			ASSERT(key.offset - diff_end == length);
 			break;
 		}
diff --git a/fs/btrfs/relocation.c b/fs/btrfs/relocation.c
index 1c42c5180bdd..3ebaf5880125 100644
--- a/fs/btrfs/relocation.c
+++ b/fs/btrfs/relocation.c
@@ -2607,7 +2607,7 @@ int relocate_tree_blocks(struct btrfs_trans_handle *trans,
 		if (!block->key_ready)
 			btrfs_readahead_tree_block(fs_info, block->bytenr,
 						   block->owner, 0,
-						   block->level);
+						   block->level, NULL);
 	}
 
 	/* Get first keys */
@@ -3876,7 +3876,7 @@ static int add_remap_tree_entries(struct btrfs_trans_handle *trans, struct btrfs
 		ret = btrfs_insert_empty_items(trans, fs_info->remap_root, path, &batch);
 		btrfs_release_path(path);
 
-		if (num_entries <= max_items)
+		if (ret || num_entries <= max_items)
 			break;
 
 		num_entries -= max_items;
@@ -4174,6 +4174,12 @@ static int move_existing_remap(struct btrfs_fs_info *fs_info,
 		return ret;
 	}
 
+	if (ins.offset < length) {
+		spin_lock(&sinfo->lock);
+		btrfs_space_info_update_bytes_may_use(sinfo, ins.offset - length);
+		spin_unlock(&sinfo->lock);
+	}
+
 	dest_addr = ins.objectid;
 	dest_length = ins.offset;
 
@@ -5000,6 +5006,12 @@ static int do_remap_reloc_trans(struct btrfs_fs_info *fs_info,
 		return ret;
 	}
 
+	if (ins.offset < remap_length) {
+		spin_lock(&sinfo->lock);
+		btrfs_space_info_update_bytes_may_use(sinfo, ins.offset - remap_length);
+		spin_unlock(&sinfo->lock);
+	}
+
 	made_reservation = true;
 
 	new_addr = ins.objectid;
@@ -5023,21 +5035,27 @@ static int do_remap_reloc_trans(struct btrfs_fs_info *fs_info,
 
 	if (bg_needs_free_space) {
 		ret = btrfs_add_block_group_free_space(trans, dest_bg);
-		if (ret)
+		if (ret) {
+			btrfs_abort_transaction(trans, ret);
 			goto fail;
+		}
 	}
 
 	ret = copy_remapped_data(fs_info, start, new_addr, length);
-	if (ret)
+	if (ret) {
+		btrfs_abort_transaction(trans, ret);
 		goto fail;
+	}
 
 	ret = btrfs_remove_from_free_space_tree(trans, new_addr, length);
-	if (ret)
+	if (ret) {
+		btrfs_abort_transaction(trans, ret);
 		goto fail;
+	}
 
 	ret = add_remap_entry(trans, path, src_bg, start, new_addr, length);
 	if (ret) {
-		btrfs_add_to_free_space_tree(trans, new_addr, length);
+		btrfs_abort_transaction(trans, ret);
 		goto fail;
 	}
 
diff --git a/fs/coredump.c b/fs/coredump.c
index bb6fdb1f458e..5ca11f4d9046 100644
--- a/fs/coredump.c
+++ b/fs/coredump.c
@@ -403,6 +403,11 @@ static bool coredump_parse(struct core_name *cn, struct coredump_params *cprm,
 				err = cn_printf(cn, "%d",
 						cprm->siginfo->si_signo);
 				break;
+			/* code of the signal that caused the coredump */
+			case 'n':
+				err = cn_printf(cn, "%d",
+						cprm->siginfo->si_code);
+				break;
 			/* UNIX time of coredump */
 			case 't': {
 				time64_t time;
diff --git a/fs/ecryptfs/keystore.c b/fs/ecryptfs/keystore.c
index 0be746493e56..ebebc9551f1f 100644
--- a/fs/ecryptfs/keystore.c
+++ b/fs/ecryptfs/keystore.c
@@ -1718,7 +1718,6 @@ int ecryptfs_parse_packet_set(struct ecryptfs_crypt_stat *crypt_stat,
 			      struct dentry *ecryptfs_dentry)
 {
 	size_t i = 0;
-	size_t found_auth_tok;
 	size_t next_packet_is_auth_tok_packet;
 	LIST_HEAD(auth_tok_list);
 	struct ecryptfs_auth_tok *matching_auth_tok;
@@ -1822,7 +1821,6 @@ int ecryptfs_parse_packet_set(struct ecryptfs_crypt_stat *crypt_stat,
 	 * the metadata. There may be several potential matches, but
 	 * just one will be sufficient to decrypt to get the FEK. */
 find_next_matching_auth_tok:
-	found_auth_tok = 0;
 	list_for_each_entry(auth_tok_list_item, &auth_tok_list, list) {
 		candidate_auth_tok = &auth_tok_list_item->auth_tok;
 		if (unlikely(ecryptfs_verbosity > 0)) {
@@ -1843,17 +1841,13 @@ int ecryptfs_parse_packet_set(struct ecryptfs_crypt_stat *crypt_stat,
 					       &matching_auth_tok,
 					       crypt_stat->mount_crypt_stat,
 					       candidate_auth_tok_sig);
-		if (!rc) {
-			found_auth_tok = 1;
+		if (!rc)
 			goto found_matching_auth_tok;
-		}
-	}
-	if (!found_auth_tok) {
-		ecryptfs_printk(KERN_ERR, "Could not find a usable "
-				"authentication token\n");
-		rc = -EIO;
-		goto out_wipe_list;
 	}
+	ecryptfs_printk(KERN_ERR,
+			"Could not find a usable authentication token\n");
+	rc = -EIO;
+	goto out_wipe_list;
 found_matching_auth_tok:
 	if (candidate_auth_tok->token_type == ECRYPTFS_PRIVATE_KEY) {
 		memcpy(&(candidate_auth_tok->token.private_key),
diff --git a/fs/exfat/dir.c b/fs/exfat/dir.c
index ac008ccaa97d..561fd2349218 100644
--- a/fs/exfat/dir.c
+++ b/fs/exfat/dir.c
@@ -1027,12 +1027,12 @@ int exfat_find_dir_entry(struct super_block *sb, struct exfat_inode_info *ei,
 				continue;
 			}
 
-			brelse(bh);
 			if (entry_type == TYPE_EXTEND) {
 				unsigned short entry_uniname[16], unichar;
 
 				if (step != DIRENT_STEP_NAME ||
 				    name_len >= MAX_NAME_LENGTH) {
+					brelse(bh);
 					step = DIRENT_STEP_FILE;
 					continue;
 				}
@@ -1043,6 +1043,7 @@ int exfat_find_dir_entry(struct super_block *sb, struct exfat_inode_info *ei,
 					uniname += EXFAT_FILE_NAME_LEN;
 
 				len = exfat_extract_uni_name(ep, entry_uniname);
+				brelse(bh);
 				name_len += len;
 
 				unichar = *(uniname+len);
@@ -1061,6 +1062,7 @@ int exfat_find_dir_entry(struct super_block *sb, struct exfat_inode_info *ei,
 				continue;
 			}
 
+			brelse(bh);
 			if (entry_type &
 					(TYPE_CRITICAL_SEC | TYPE_BENIGN_SEC)) {
 				if (step == DIRENT_STEP_SECD) {
diff --git a/fs/exfat/nls.c b/fs/exfat/nls.c
index 57db08a5271c..055447edcf9a 100644
--- a/fs/exfat/nls.c
+++ b/fs/exfat/nls.c
@@ -769,13 +769,18 @@ int exfat_create_upcase_table(struct super_block *sb)
 
 			tbl_clu  = le32_to_cpu(ep->dentry.upcase.start_clu);
 			tbl_size = le64_to_cpu(ep->dentry.upcase.size);
-
-			sector = exfat_cluster_to_sector(sbi, tbl_clu);
-			num_sectors = ((tbl_size - 1) >> blksize_bits) + 1;
-			ret = exfat_load_upcase_table(sb, sector, num_sectors,
-				le32_to_cpu(ep->dentry.upcase.checksum));
-
+			if (tbl_size) {
+				sector = exfat_cluster_to_sector(sbi, tbl_clu);
+				num_sectors = ((tbl_size - 1) >> blksize_bits) + 1;
+				ret = exfat_load_upcase_table(sb, sector, num_sectors,
+					le32_to_cpu(ep->dentry.upcase.checksum));
+			} else {
+				exfat_fs_error(sb,
+					       "bad upcase table size (0 bytes). Please run fsck");
+				ret = -EINVAL;
+			}
 			brelse(bh);
+
 			if (ret && ret != -EIO) {
 				/* free memory from exfat_load_upcase_table call */
 				exfat_free_upcase_table(sbi);
@@ -790,6 +795,8 @@ int exfat_create_upcase_table(struct super_block *sb)
 			return -EIO;
 	}
 
+	exfat_fs_error(sb, "no upcase table entry. Please run fsck");
+
 load_default:
 	/* load default upcase table */
 	return exfat_load_default_upcase_table(sb);
diff --git a/fs/fat/fat_test.c b/fs/fat/fat_test.c
index 886bf044a9f1..4eeed9dca549 100644
--- a/fs/fat/fat_test.c
+++ b/fs/fat/fat_test.c
@@ -20,6 +20,37 @@ static void fat_checksum_test(struct kunit *test)
 	KUNIT_EXPECT_EQ(test, fat_checksum("ABCDEFGHA  "), (u8)98);
 }
 
+static void fat_clus_to_blknr_test(struct kunit *test)
+{
+	struct msdos_sb_info sbi = {
+		.sec_per_clus = 4,
+		.data_start = 100,
+	};
+
+	KUNIT_EXPECT_EQ(test, (sector_t)100,
+			fat_clus_to_blknr(&sbi, FAT_START_ENT));
+	KUNIT_EXPECT_EQ(test, (sector_t)112, fat_clus_to_blknr(&sbi, 5));
+}
+
+static void fat_get_blknr_offset_test(struct kunit *test)
+{
+	struct msdos_sb_info sbi = {
+		.dir_per_block = 16,
+		.dir_per_block_bits = 4,
+	};
+
+	sector_t blknr;
+	int offset;
+
+	fat_get_blknr_offset(&sbi, 0, &blknr, &offset);
+	KUNIT_EXPECT_EQ(test, (sector_t)0, blknr);
+	KUNIT_EXPECT_EQ(test, 0, offset);
+
+	fat_get_blknr_offset(&sbi, (10 << 4) | 7, &blknr, &offset);
+	KUNIT_EXPECT_EQ(test, (sector_t)10, blknr);
+	KUNIT_EXPECT_EQ(test, 7, offset);
+}
+
 struct fat_timestamp_testcase {
 	const char *name;
 	struct timespec64 ts;
@@ -341,6 +372,8 @@ static void fat_truncate_atime_test(struct kunit *test)
 
 static struct kunit_case fat_test_cases[] = {
 	KUNIT_CASE(fat_checksum_test),
+	KUNIT_CASE(fat_clus_to_blknr_test),
+	KUNIT_CASE(fat_get_blknr_offset_test),
 	KUNIT_CASE_PARAM(fat_time_fat2unix_test, fat_time_gen_params),
 	KUNIT_CASE_PARAM(fat_time_unix2fat_test, fat_time_gen_params),
 	KUNIT_CASE_PARAM(fat_time_unix2fat_clamp_test,
diff --git a/fs/fuse/Makefile b/fs/fuse/Makefile
index 22ad9538dfc4..245e67852b03 100644
--- a/fs/fuse/Makefile
+++ b/fs/fuse/Makefile
@@ -11,7 +11,8 @@ obj-$(CONFIG_CUSE) += cuse.o
 obj-$(CONFIG_VIRTIO_FS) += virtiofs.o
 
 fuse-y := trace.o	# put trace.o first so we see ftrace errors sooner
-fuse-y += dev.o dir.o file.o inode.o control.o xattr.o acl.o readdir.o ioctl.o
+fuse-y += dev.o dir.o file.o inode.o control.o xattr.o acl.o readdir.o ioctl.o req_timeout.o req.o
+fuse-y += poll.o notify.o
 fuse-y += iomode.o
 fuse-$(CONFIG_FUSE_DAX) += dax.o
 fuse-$(CONFIG_FUSE_PASSTHROUGH) += passthrough.o backing.o
diff --git a/fs/fuse/args.h b/fs/fuse/args.h
new file mode 100644
index 000000000000..ecfe51a192af
--- /dev/null
+++ b/fs/fuse/args.h
@@ -0,0 +1,65 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifndef _FS_FUSE_ARGS_H
+#define _FS_FUSE_ARGS_H
+
+#include <linux/types.h>
+
+struct fuse_mount;
+
+/** One input argument of a request */
+struct fuse_in_arg {
+	unsigned size;
+	const void *value;
+};
+
+/** One output argument of a request */
+struct fuse_arg {
+	unsigned size;
+	void *value;
+};
+
+struct fuse_args {
+	u64 nodeid;
+	u32 opcode;
+	u32 uid;
+	u32 gid;
+	u32 pid;
+	u8 in_numargs;
+	u8 out_numargs;
+	u8 ext_idx;
+	bool force:1;
+	bool noreply:1;
+	bool nocreds:1;
+	bool in_pages:1;
+	bool out_pages:1;
+	bool user_pages:1;
+	bool out_argvar:1;
+	bool page_zeroing:1;
+	bool page_replace:1;
+	bool may_block:1;
+	bool is_ext:1;
+	bool is_pinned:1;
+	bool invalidate_vmap:1;
+	bool abort_on_kill:1;
+	struct fuse_in_arg in_args[4];
+	struct fuse_arg out_args[2];
+	void (*end)(struct fuse_args *args, int error);
+	/* Used for kvec iter backed by vmalloc address */
+	void *vmap_base;
+};
+
+/** FUSE folio descriptor */
+struct fuse_folio_desc {
+	unsigned int length;
+	unsigned int offset;
+};
+
+struct fuse_args_pages {
+	struct fuse_args args;
+	struct folio **folios;
+	struct fuse_folio_desc *descs;
+	unsigned int num_folios;
+};
+
+#endif /* _FS_FUSE_ARGS_H */
diff --git a/fs/fuse/backing.c b/fs/fuse/backing.c
index d95dfa48483f..3d3f49c2dd42 100644
--- a/fs/fuse/backing.c
+++ b/fs/fuse/backing.c
@@ -5,6 +5,7 @@
  * Copyright (c) 2023 CTERA Networks.
  */
 
+#include "dev.h"
 #include "fuse_i.h"
 
 #include <linux/file.h>
diff --git a/fs/fuse/control.c b/fs/fuse/control.c
index f902a7fb4630..925a15488499 100644
--- a/fs/fuse/control.c
+++ b/fs/fuse/control.c
@@ -7,6 +7,7 @@
 */
 
 #include "fuse_i.h"
+#include "dev.h"
 
 #include <linux/init.h>
 #include <linux/module.h>
@@ -37,9 +38,7 @@ static ssize_t fuse_conn_abort_write(struct file *file, const char __user *buf,
 {
 	struct fuse_conn *fc = fuse_ctl_file_conn_get(file);
 	if (fc) {
-		if (fc->abort_err)
-			fc->aborted = true;
-		fuse_abort_conn(fc);
+		fuse_chan_abort(fc->chan, fc->abort_err);
 		fuse_conn_put(fc);
 	}
 	return count;
@@ -57,7 +56,7 @@ static ssize_t fuse_conn_waiting_read(struct file *file, char __user *buf,
 		if (!fc)
 			return 0;
 
-		value = atomic_read(&fc->num_waiting);
+		value = fuse_chan_num_waiting(fc->chan);
 		file->private_data = (void *)value;
 		fuse_conn_put(fc);
 	}
@@ -111,7 +110,7 @@ static ssize_t fuse_conn_max_background_read(struct file *file,
 	if (!fc)
 		return 0;
 
-	val = READ_ONCE(fc->max_background);
+	val = fuse_chan_max_background(fc->chan);
 	fuse_conn_put(fc);
 
 	return fuse_conn_limit_read(file, buf, len, ppos, val);
@@ -129,12 +128,7 @@ static ssize_t fuse_conn_max_background_write(struct file *file,
 	if (ret > 0) {
 		struct fuse_conn *fc = fuse_ctl_file_conn_get(file);
 		if (fc) {
-			spin_lock(&fc->bg_lock);
-			fc->max_background = val;
-			fc->blocked = fc->num_background >= fc->max_background;
-			if (!fc->blocked)
-				wake_up(&fc->blocked_waitq);
-			spin_unlock(&fc->bg_lock);
+			fuse_chan_max_background_set(fc->chan, val);
 			fuse_conn_put(fc);
 		}
 	}
diff --git a/fs/fuse/cuse.c b/fs/fuse/cuse.c
index 174333633471..bac327cfc7f1 100644
--- a/fs/fuse/cuse.c
+++ b/fs/fuse/cuse.c
@@ -51,6 +51,7 @@
 #include <linux/uio.h>
 #include <linux/user_namespace.h>
 
+#include "dev.h"
 #include "fuse_i.h"
 #include "fuse_dev_i.h"
 
@@ -306,6 +307,7 @@ struct cuse_init_args {
 	struct cuse_init_out out;
 	struct folio *folio;
 	struct fuse_folio_desc desc;
+	struct fuse_conn *fc;
 };
 
 /**
@@ -319,11 +321,10 @@ struct cuse_init_args {
  * required data structures for it.  Please read the comment at the
  * top of this file for high level overview.
  */
-static void cuse_process_init_reply(struct fuse_mount *fm,
-				    struct fuse_args *args, int error)
+static void cuse_process_init_reply(struct fuse_args *args, int error)
 {
-	struct fuse_conn *fc = fm->fc;
 	struct cuse_init_args *ia = container_of(args, typeof(*ia), ap.args);
+	struct fuse_conn *fc = ia->fc;
 	struct fuse_args_pages *ap = &ia->ap;
 	struct cuse_conn *cc = fc_to_cc(fc), *pos;
 	struct cuse_init_out *arg = &ia->out;
@@ -423,7 +424,7 @@ static void cuse_process_init_reply(struct fuse_mount *fm,
 err_region:
 	unregister_chrdev_region(devt, 1);
 err:
-	fuse_abort_conn(fc);
+	fuse_chan_abort(fc->chan, false);
 	goto out;
 }
 
@@ -466,6 +467,7 @@ static int cuse_send_init(struct cuse_conn *cc)
 	ap->descs = &ia->desc;
 	ia->folio = folio;
 	ia->desc.length = ap->args.out_args[1].size;
+	ia->fc = &cc->fc;
 	ap->args.end = cuse_process_init_reply;
 
 	rc = fuse_simple_background(fm, &ap->args, GFP_KERNEL);
@@ -502,8 +504,12 @@ static int cuse_channel_open(struct inode *inode, struct file *file)
 {
 	struct fuse_dev *fud;
 	struct cuse_conn *cc;
+	struct fuse_chan *fch __free(fuse_chan_free) = fuse_dev_chan_new();
 	int rc;
 
+	if (!fch)
+		return -ENOMEM;
+
 	/* set up cuse_conn */
 	cc = kzalloc_obj(*cc);
 	if (!cc)
@@ -513,18 +519,16 @@ static int cuse_channel_open(struct inode *inode, struct file *file)
 	 * Limit the cuse channel to requests that can
 	 * be represented in file->f_cred->user_ns.
 	 */
-	fuse_conn_init(&cc->fc, &cc->fm, file->f_cred->user_ns,
-		       &fuse_dev_fiq_ops, NULL);
-
+	fuse_conn_init(&cc->fc, &cc->fm, file->f_cred->user_ns, no_free_ptr(fch));
 	cc->fc.release = cuse_fc_release;
-	fud = fuse_dev_alloc_install(&cc->fc);
+	fud = fuse_dev_alloc_install(cc->fc.chan);
 	fuse_conn_put(&cc->fc);
 	if (!fud)
 		return -ENOMEM;
 
 	INIT_LIST_HEAD(&cc->list);
 
-	cc->fc.initialized = 1;
+	cc->fc.chan->initialized = 1;
 	rc = cuse_send_init(cc);
 	if (rc) {
 		fuse_dev_put(fud);
@@ -549,7 +553,7 @@ static int cuse_channel_open(struct inode *inode, struct file *file)
 static int cuse_channel_release(struct inode *inode, struct file *file)
 {
 	struct fuse_dev *fud = __fuse_get_dev(file);
-	struct cuse_conn *cc = fc_to_cc(fud->fc);
+	struct cuse_conn *cc = fc_to_cc(fud->chan->conn);
 
 	/* remove from the conntbl, no more access from this point on */
 	mutex_lock(&cuse_lock);
@@ -581,7 +585,7 @@ static ssize_t cuse_class_waiting_show(struct device *dev,
 {
 	struct cuse_conn *cc = dev_get_drvdata(dev);
 
-	return sprintf(buf, "%d\n", atomic_read(&cc->fc.num_waiting));
+	return sprintf(buf, "%d\n", atomic_read(&cc->fc.chan->num_waiting));
 }
 static DEVICE_ATTR(waiting, 0400, cuse_class_waiting_show, NULL);
 
@@ -591,7 +595,7 @@ static ssize_t cuse_class_abort_store(struct device *dev,
 {
 	struct cuse_conn *cc = dev_get_drvdata(dev);
 
-	fuse_abort_conn(&cc->fc);
+	fuse_chan_abort(cc->fc.chan, false);
 	return count;
 }
 static DEVICE_ATTR(abort, 0200, NULL, cuse_class_abort_store);
diff --git a/fs/fuse/dev.c b/fs/fuse/dev.c
index 5dda7080f4a9..6fe0d8c263df 100644
--- a/fs/fuse/dev.c
+++ b/fs/fuse/dev.c
@@ -6,9 +6,9 @@
   See the file COPYING.
 */
 
+#include "dev.h"
+#include "args.h"
 #include "dev_uring_i.h"
-#include "fuse_i.h"
-#include "fuse_dev_i.h"
 
 #include <linux/init.h>
 #include <linux/module.h>
@@ -30,118 +30,26 @@
 MODULE_ALIAS_MISCDEV(FUSE_MINOR);
 MODULE_ALIAS("devname:fuse");
 
-static struct kmem_cache *fuse_req_cachep;
-
-const unsigned long fuse_timeout_timer_freq =
-	secs_to_jiffies(FUSE_TIMEOUT_TIMER_FREQ);
+static DECLARE_WAIT_QUEUE_HEAD(fuse_dev_waitq);
 
-bool fuse_request_expired(struct fuse_conn *fc, struct list_head *list)
-{
-	struct fuse_req *req;
-
-	req = list_first_entry_or_null(list, struct fuse_req, list);
-	if (!req)
-		return false;
-	return time_is_before_jiffies(req->create_time + fc->timeout.req_timeout);
-}
-
-static bool fuse_fpq_processing_expired(struct fuse_conn *fc, struct list_head *processing)
-{
-	int i;
-
-	for (i = 0; i < FUSE_PQ_HASH_SIZE; i++)
-		if (fuse_request_expired(fc, &processing[i]))
-			return true;
-
-	return false;
-}
-
-/*
- * Check if any requests aren't being completed by the time the request timeout
- * elapses. To do so, we:
- * - check the fiq pending list
- * - check the bg queue
- * - check the fpq io and processing lists
- *
- * To make this fast, we only check against the head request on each list since
- * these are generally queued in order of creation time (eg newer requests get
- * queued to the tail). We might miss a few edge cases (eg requests transitioning
- * between lists, re-sent requests at the head of the pending list having a
- * later creation time than other requests on that list, etc.) but that is fine
- * since if the request never gets fulfilled, it will eventually be caught.
- */
-void fuse_check_timeout(struct work_struct *work)
-{
-	struct delayed_work *dwork = to_delayed_work(work);
-	struct fuse_conn *fc = container_of(dwork, struct fuse_conn,
-					    timeout.work);
-	struct fuse_iqueue *fiq = &fc->iq;
-	struct fuse_dev *fud;
-	struct fuse_pqueue *fpq;
-	bool expired = false;
-
-	if (!atomic_read(&fc->num_waiting))
-	    goto out;
-
-	spin_lock(&fiq->lock);
-	expired = fuse_request_expired(fc, &fiq->pending);
-	spin_unlock(&fiq->lock);
-	if (expired)
-		goto abort_conn;
-
-	spin_lock(&fc->bg_lock);
-	expired = fuse_request_expired(fc, &fc->bg_queue);
-	spin_unlock(&fc->bg_lock);
-	if (expired)
-		goto abort_conn;
-
-	spin_lock(&fc->lock);
-	if (!fc->connected) {
-		spin_unlock(&fc->lock);
-		return;
-	}
-	list_for_each_entry(fud, &fc->devices, entry) {
-		fpq = &fud->pq;
-		spin_lock(&fpq->lock);
-		if (fuse_request_expired(fc, &fpq->io) ||
-		    fuse_fpq_processing_expired(fc, fpq->processing)) {
-			spin_unlock(&fpq->lock);
-			spin_unlock(&fc->lock);
-			goto abort_conn;
-		}
-
-		spin_unlock(&fpq->lock);
-	}
-	spin_unlock(&fc->lock);
-
-	if (fuse_uring_request_expired(fc))
-	    goto abort_conn;
-
-out:
-	queue_delayed_work(system_percpu_wq, &fc->timeout.work,
-			   fuse_timeout_timer_freq);
-	return;
-
-abort_conn:
-	fuse_abort_conn(fc);
-}
+static struct kmem_cache *fuse_req_cachep;
 
-static void fuse_request_init(struct fuse_mount *fm, struct fuse_req *req)
+static void fuse_request_init(struct fuse_chan *fch, struct fuse_req *req)
 {
 	INIT_LIST_HEAD(&req->list);
 	INIT_LIST_HEAD(&req->intr_entry);
 	init_waitqueue_head(&req->waitq);
 	refcount_set(&req->count, 1);
 	__set_bit(FR_PENDING, &req->flags);
-	req->fm = fm;
+	req->chan = fch;
 	req->create_time = jiffies;
 }
 
-static struct fuse_req *fuse_request_alloc(struct fuse_mount *fm, gfp_t flags)
+static struct fuse_req *fuse_request_alloc(struct fuse_chan *fch, gfp_t flags)
 {
 	struct fuse_req *req = kmem_cache_zalloc(fuse_req_cachep, flags);
 	if (req)
-		fuse_request_init(fm, req);
+		fuse_request_init(fch, req);
 
 	return req;
 }
@@ -162,110 +70,86 @@ static void __fuse_put_request(struct fuse_req *req)
 	refcount_dec(&req->count);
 }
 
-void fuse_set_initialized(struct fuse_conn *fc)
+void fuse_chan_set_initialized(struct fuse_chan *fch, struct fuse_chan_param *param)
 {
+	if (param) {
+		fch->minor = param->minor;
+		fch->max_write = param->max_write;
+		fch->max_pages = param->max_pages;
+	}
+
 	/* Make sure stores before this are seen on another CPU */
 	smp_wmb();
-	fc->initialized = 1;
+	fch->initialized = 1;
+	wake_up_all(&fch->blocked_waitq);
 }
 
-static bool fuse_block_alloc(struct fuse_conn *fc, bool for_background)
+static bool fuse_block_alloc(struct fuse_chan *fch, bool for_background)
 {
-	return !fc->initialized || (for_background && fc->blocked) ||
-	       (fc->io_uring && fc->connected && !fuse_uring_ready(fc));
+	return !fch->initialized || (for_background && fch->blocked) ||
+	       (fch->io_uring && fch->connected && !fuse_uring_ready(fch));
 }
 
-static void fuse_drop_waiting(struct fuse_conn *fc)
+static void fuse_drop_waiting(struct fuse_chan *fch)
 {
 	/*
-	 * lockess check of fc->connected is okay, because atomic_dec_and_test()
-	 * provides a memory barrier matched with the one in fuse_wait_aborted()
+	 * lockess check of fch->connected is okay, because atomic_dec_and_test()
+	 * provides a memory barrier matched with the one in fuse_chan_wait_aborted()
 	 * to ensure no wake-up is missed.
 	 */
-	if (atomic_dec_and_test(&fc->num_waiting) &&
-	    !READ_ONCE(fc->connected)) {
+	if (atomic_dec_and_test(&fch->num_waiting) &&
+	    !READ_ONCE(fch->connected)) {
 		/* wake up aborters */
-		wake_up_all(&fc->blocked_waitq);
+		wake_up_all(&fch->blocked_waitq);
 	}
 }
 
 static void fuse_put_request(struct fuse_req *req);
 
-static struct fuse_req *fuse_get_req(struct mnt_idmap *idmap,
-				     struct fuse_mount *fm,
-				     bool for_background)
+static struct fuse_req *fuse_get_req(struct fuse_chan *fch, bool for_background)
 {
-	struct fuse_conn *fc = fm->fc;
 	struct fuse_req *req;
-	bool no_idmap = !fm->sb || (fm->sb->s_iflags & SB_I_NOIDMAP);
-	kuid_t fsuid;
-	kgid_t fsgid;
 	int err;
 
-	atomic_inc(&fc->num_waiting);
+	atomic_inc(&fch->num_waiting);
 
-	if (fuse_block_alloc(fc, for_background)) {
+	if (fuse_block_alloc(fch, for_background)) {
 		err = -EINTR;
-		if (wait_event_state_exclusive(fc->blocked_waitq,
-				!fuse_block_alloc(fc, for_background),
+		if (wait_event_state_exclusive(fch->blocked_waitq,
+				!fuse_block_alloc(fch, for_background),
 				(TASK_KILLABLE | TASK_FREEZABLE)))
 			goto out;
 	}
-	/* Matches smp_wmb() in fuse_set_initialized() */
+
+	/* Matches smp_wmb() in fuse_chan_set_initialized() */
 	smp_rmb();
 
 	err = -ENOTCONN;
-	if (!fc->connected)
+	if (!fch->connected)
 		goto out;
 
-	err = -ECONNREFUSED;
-	if (fc->conn_error)
-		goto out;
-
-	req = fuse_request_alloc(fm, GFP_KERNEL);
+	req = fuse_request_alloc(fch, GFP_KERNEL);
 	err = -ENOMEM;
 	if (!req) {
 		if (for_background)
-			wake_up(&fc->blocked_waitq);
+			wake_up(&fch->blocked_waitq);
 		goto out;
 	}
 
-	req->in.h.pid = pid_nr_ns(task_pid(current), fc->pid_ns);
-
 	__set_bit(FR_WAITING, &req->flags);
 	if (for_background)
 		__set_bit(FR_BACKGROUND, &req->flags);
 
-	/*
-	 * Keep the old behavior when idmappings support was not
-	 * declared by a FUSE server.
-	 *
-	 * For those FUSE servers who support idmapped mounts,
-	 * we send UID/GID only along with "inode creation"
-	 * fuse requests, otherwise idmap == &invalid_mnt_idmap and
-	 * req->in.h.{u,g}id will be equal to FUSE_INVALID_UIDGID.
-	 */
-	fsuid = no_idmap ? current_fsuid() : mapped_fsuid(idmap, fc->user_ns);
-	fsgid = no_idmap ? current_fsgid() : mapped_fsgid(idmap, fc->user_ns);
-	req->in.h.uid = from_kuid(fc->user_ns, fsuid);
-	req->in.h.gid = from_kgid(fc->user_ns, fsgid);
-
-	if (no_idmap && unlikely(req->in.h.uid == ((uid_t)-1) ||
-				 req->in.h.gid == ((gid_t)-1))) {
-		fuse_put_request(req);
-		return ERR_PTR(-EOVERFLOW);
-	}
-
 	return req;
 
  out:
-	fuse_drop_waiting(fc);
+	fuse_drop_waiting(fch);
 	return ERR_PTR(err);
 }
 
 static void fuse_put_request(struct fuse_req *req)
 {
-	struct fuse_conn *fc = req->fm->fc;
+	struct fuse_chan *fch = req->chan;
 
 	if (refcount_dec_and_test(&req->count)) {
 		if (test_bit(FR_BACKGROUND, &req->flags)) {
@@ -273,15 +157,15 @@ static void fuse_put_request(struct fuse_req *req)
 			 * We get here in the unlikely case that a background
 			 * request was allocated but not sent
 			 */
-			spin_lock(&fc->bg_lock);
-			if (!fc->blocked)
-				wake_up(&fc->blocked_waitq);
-			spin_unlock(&fc->bg_lock);
+			spin_lock(&fch->bg_lock);
+			if (!fch->blocked)
+				wake_up(&fch->blocked_waitq);
+			spin_unlock(&fch->bg_lock);
 		}
 
 		if (test_bit(FR_WAITING, &req->flags)) {
 			__clear_bit(FR_WAITING, &req->flags);
-			fuse_drop_waiting(fc);
+			fuse_drop_waiting(fch);
 		}
 
 		fuse_request_free(req);
@@ -335,6 +219,11 @@ __releases(fiq->lock)
 	spin_unlock(&fiq->lock);
 }
 
+struct fuse_forget_link *fuse_alloc_forget(void)
+{
+	return kzalloc_obj(struct fuse_forget_link, GFP_KERNEL_ACCOUNT);
+}
+
 void fuse_dev_queue_forget(struct fuse_iqueue *fiq,
 			   struct fuse_forget_link *forget)
 {
@@ -406,12 +295,271 @@ static void fuse_dev_queue_req(struct fuse_iqueue *fiq, struct fuse_req *req)
 	}
 }
 
-const struct fuse_iqueue_ops fuse_dev_fiq_ops = {
+static const struct fuse_iqueue_ops fuse_dev_fiq_ops = {
 	.send_forget	= fuse_dev_queue_forget,
 	.send_interrupt	= fuse_dev_queue_interrupt,
 	.send_req	= fuse_dev_queue_req,
 };
-EXPORT_SYMBOL_GPL(fuse_dev_fiq_ops);
+
+void fuse_iqueue_init(struct fuse_iqueue *fiq, const struct fuse_iqueue_ops *ops, void *priv)
+{
+	spin_lock_init(&fiq->lock);
+	init_waitqueue_head(&fiq->waitq);
+	INIT_LIST_HEAD(&fiq->pending);
+	INIT_LIST_HEAD(&fiq->interrupts);
+	fiq->forget_list_tail = &fiq->forget_list_head;
+	fiq->connected = 1;
+	fiq->ops = ops;
+	fiq->priv = priv;
+}
+EXPORT_SYMBOL_GPL(fuse_iqueue_init);
+
+void fuse_chan_release(struct fuse_chan *fch)
+{
+	struct fuse_iqueue *fiq = &fch->iq;
+
+	if (fiq->ops->release)
+		fiq->ops->release(fiq);
+
+	if (fch->timeout.req_timeout)
+		cancel_delayed_work_sync(&fch->timeout.work);
+}
+
+void fuse_chan_free(struct fuse_chan *fch)
+{
+	WARN_ON(!list_empty(&fch->devices));
+	kfree(fch->pq_prealloc);
+	kfree(fch);
+}
+EXPORT_SYMBOL_GPL(fuse_chan_free);
+
+struct fuse_chan *fuse_chan_new(void)
+{
+	struct fuse_chan *fch = kzalloc_obj(struct fuse_chan);
+	if (!fch)
+		return NULL;
+
+	spin_lock_init(&fch->lock);
+	INIT_LIST_HEAD(&fch->devices);
+	spin_lock_init(&fch->bg_lock);
+	INIT_LIST_HEAD(&fch->bg_queue);
+	init_waitqueue_head(&fch->blocked_waitq);
+	atomic_set(&fch->num_waiting, 0);
+	fch->max_background = FUSE_DEFAULT_MAX_BACKGROUND;
+	fch->initialized = 0;
+	fch->blocked = 0;
+	fch->connected = 1;
+	fch->timeout.req_timeout = 0;
+
+	return fch;
+}
+EXPORT_SYMBOL_GPL(fuse_chan_new);
+
+struct list_head *fuse_pqueue_alloc(void)
+{
+	struct list_head *pq = kzalloc_objs(struct list_head, FUSE_PQ_HASH_SIZE);
+
+	if (pq) {
+		for (int i = 0; i < FUSE_PQ_HASH_SIZE; i++)
+			INIT_LIST_HEAD(&pq[i]);
+	}
+	return pq;
+}
+
+struct fuse_chan *fuse_dev_chan_new(void)
+{
+	struct fuse_chan *fch __free(kfree) = fuse_chan_new();
+	if (!fch)
+		return NULL;
+
+	fch->pq_prealloc = fuse_pqueue_alloc();
+	if (!fch->pq_prealloc)
+		return NULL;
+
+	fuse_iqueue_init(&fch->iq, &fuse_dev_fiq_ops, NULL);
+
+	return no_free_ptr(fch);
+}
+EXPORT_SYMBOL_GPL(fuse_dev_chan_new);
+
+unsigned int fuse_chan_num_background(struct fuse_chan *fch)
+{
+	return fch->num_background;
+}
+
+unsigned int fuse_chan_max_background(struct fuse_chan *fch)
+{
+	return READ_ONCE(fch->max_background);
+}
+
+void fuse_chan_max_background_set(struct fuse_chan *fch, unsigned int val)
+{
+	spin_lock(&fch->bg_lock);
+	fch->max_background = val;
+	fch->blocked = fch->num_background >= fch->max_background;
+	if (!fch->blocked)
+		wake_up(&fch->blocked_waitq);
+	spin_unlock(&fch->bg_lock);
+}
+
+unsigned int fuse_chan_num_waiting(struct fuse_chan *fch)
+{
+	return atomic_read(&fch->num_waiting);
+}
+
+void fuse_chan_set_fc(struct fuse_chan *fch, struct fuse_conn *fc)
+{
+	fch->conn = fc;
+}
+
+void fuse_chan_io_uring_enable(struct fuse_chan *fch)
+{
+	fch->io_uring = 1;
+}
+
+void fuse_pqueue_init(struct fuse_pqueue *fpq)
+{
+	spin_lock_init(&fpq->lock);
+	INIT_LIST_HEAD(&fpq->io);
+	fpq->connected = 1;
+	fpq->processing = NULL;
+}
+
+static struct fuse_dev *fuse_dev_alloc_no_pq(void)
+{
+	struct fuse_dev *fud;
+
+	fud = kzalloc_obj(struct fuse_dev);
+	if (!fud)
+		return NULL;
+
+	refcount_set(&fud->ref, 1);
+	fuse_pqueue_init(&fud->pq);
+
+	return fud;
+}
+
+struct fuse_dev *fuse_dev_alloc(void)
+{
+	struct fuse_dev *fud __free(kfree) = fuse_dev_alloc_no_pq();
+	if (!fud)
+		return NULL;
+
+	fud->pq.processing = fuse_pqueue_alloc();
+	if (!fud->pq.processing)
+		return NULL;
+
+	return no_free_ptr(fud);
+}
+EXPORT_SYMBOL_GPL(fuse_dev_alloc);
+
+/*
+ * Installs @fch into @fud, return true on success.  "Consumes" @pq in either case.
+ */
+static bool fuse_dev_install_with_pq(struct fuse_dev *fud, struct fuse_chan *fch,
+				     struct list_head *pq)
+{
+	struct fuse_chan *old_fch;
+
+	guard(spinlock)(&fch->lock);
+	/*
+	 * Pairs with:
+	 *  - xchg() in fuse_dev_release()
+	 *  - smp_load_acquire() in fuse_dev_fc_get()
+	 */
+	old_fch = cmpxchg(&fud->chan, NULL, fch);
+	if (old_fch) {
+		/*
+		 * failed to set fud->chan because
+		 *  - it was already set to a different fc
+		 *  - it was set to disconneted
+		 */
+		kfree(pq);
+		return false;
+	}
+	if (pq) {
+		WARN_ON(fud->pq.processing);
+		fud->pq.processing = pq;
+	}
+	list_add_tail(&fud->entry, &fch->devices);
+	fuse_conn_get(fch->conn);
+	wake_up_all(&fuse_dev_waitq);
+	return true;
+}
+
+void fuse_dev_install(struct fuse_dev *fud, struct fuse_chan *fch)
+{
+	struct list_head *pq = fch->pq_prealloc;
+
+	fch->pq_prealloc = NULL;
+	if (!fuse_dev_install_with_pq(fud, fch, pq)) {
+		/* Channel is not usable without a dev */
+		fuse_chan_abort(fch, false);
+	}
+}
+EXPORT_SYMBOL_GPL(fuse_dev_install);
+
+struct fuse_dev *fuse_dev_alloc_install(struct fuse_chan *fch)
+{
+	struct fuse_dev *fud;
+
+	fud = fuse_dev_alloc_no_pq();
+	if (!fud)
+		return NULL;
+
+	fuse_dev_install(fud, fch);
+	return fud;
+}
+EXPORT_SYMBOL_GPL(fuse_dev_alloc_install);
+
+void fuse_dev_put(struct fuse_dev *fud)
+{
+	struct fuse_chan *fch;
+
+	if (!refcount_dec_and_test(&fud->ref))
+		return;
+
+	fch = fuse_dev_chan_get(fud);
+	if (fch && fch != FUSE_DEV_CHAN_DISCONNECTED) {
+		/* This is the virtiofs case (fuse_dev_release() not called) */
+		spin_lock(&fch->lock);
+		list_del(&fud->entry);
+		spin_unlock(&fch->lock);
+
+		fuse_conn_put(fch->conn);
+	}
+	kfree(fud->pq.processing);
+	kfree(fud);
+}
+EXPORT_SYMBOL_GPL(fuse_dev_put);
+
+bool fuse_dev_is_installed(struct fuse_dev *fud)
+{
+	struct fuse_chan *fch = fuse_dev_chan_get(fud);
+
+	return fch != NULL && fch != FUSE_DEV_CHAN_DISCONNECTED;
+}
+
+/*
+ * Checks if @fc matches the one installed in @fud
+ */
+bool fuse_dev_verify(struct fuse_dev *fud, struct fuse_chan *fch)
+{
+	return fuse_dev_chan_get(fud) == fch;
+}
+
+bool fuse_dev_is_sync_init(struct fuse_dev *fud)
+{
+	return fud->sync_init;
+}
+
+struct fuse_dev *fuse_dev_grab(struct file *file)
+{
+	struct fuse_dev *fud = fuse_file_to_fud(file);
+
+	refcount_inc(&fud->ref);
+	return fud;
+}
 
 static void fuse_send_one(struct fuse_iqueue *fiq, struct fuse_req *req)
 {
@@ -421,10 +569,10 @@ static void fuse_send_one(struct fuse_iqueue *fiq, struct fuse_req *req)
 	fiq->ops->send_req(fiq, req);
 }
 
-void fuse_queue_forget(struct fuse_conn *fc, struct fuse_forget_link *forget,
-		       u64 nodeid, u64 nlookup)
+void fuse_chan_queue_forget(struct fuse_chan *fch, struct fuse_forget_link *forget,
+			    u64 nodeid, u64 nlookup)
 {
-	struct fuse_iqueue *fiq = &fc->iq;
+	struct fuse_iqueue *fiq = &fch->iq;
 
 	forget->forget_one.nodeid = nodeid;
 	forget->forget_one.nlookup = nlookup;
@@ -432,17 +580,17 @@ void fuse_queue_forget(struct fuse_conn *fc, struct fuse_forget_link *forget,
 	fiq->ops->send_forget(fiq, forget);
 }
 
-static void flush_bg_queue(struct fuse_conn *fc)
+static void flush_bg_queue(struct fuse_chan *fch)
 {
-	struct fuse_iqueue *fiq = &fc->iq;
+	struct fuse_iqueue *fiq = &fch->iq;
 
-	while (fc->active_background < fc->max_background &&
-	       !list_empty(&fc->bg_queue)) {
+	while (fch->active_background < fch->max_background &&
+	       !list_empty(&fch->bg_queue)) {
 		struct fuse_req *req;
 
-		req = list_first_entry(&fc->bg_queue, struct fuse_req, list);
+		req = list_first_entry(&fch->bg_queue, struct fuse_req, list);
 		list_del(&req->list);
-		fc->active_background++;
+		fch->active_background++;
 		fuse_send_one(fiq, req);
 	}
 }
@@ -457,9 +605,8 @@ static void flush_bg_queue(struct fuse_conn *fc)
  */
 void fuse_request_end(struct fuse_req *req)
 {
-	struct fuse_mount *fm = req->fm;
-	struct fuse_conn *fc = fm->fc;
-	struct fuse_iqueue *fiq = &fc->iq;
+	struct fuse_chan *fch = req->chan;
+	struct fuse_iqueue *fiq = &fch->iq;
 
 	if (test_and_set_bit(FR_FINISHED, &req->flags))
 		goto put_request;
@@ -478,33 +625,33 @@ void fuse_request_end(struct fuse_req *req)
 	WARN_ON(test_bit(FR_PENDING, &req->flags));
 	WARN_ON(test_bit(FR_SENT, &req->flags));
 	if (test_bit(FR_BACKGROUND, &req->flags)) {
-		spin_lock(&fc->bg_lock);
+		spin_lock(&fch->bg_lock);
 		clear_bit(FR_BACKGROUND, &req->flags);
-		if (fc->num_background == fc->max_background) {
-			fc->blocked = 0;
-			wake_up(&fc->blocked_waitq);
-		} else if (!fc->blocked) {
+		if (fch->num_background == fch->max_background) {
+			fch->blocked = 0;
+			wake_up(&fch->blocked_waitq);
+		} else if (!fch->blocked) {
 			/*
 			 * Wake up next waiter, if any.  It's okay to use
 			 * waitqueue_active(), as we've already synced up
-			 * fc->blocked with waiters with the wake_up() call
+			 * fch->blocked with waiters with the wake_up() call
 			 * above.
 			 */
-			if (waitqueue_active(&fc->blocked_waitq))
-				wake_up(&fc->blocked_waitq);
+			if (waitqueue_active(&fch->blocked_waitq))
+				wake_up(&fch->blocked_waitq);
 		}
 
-		fc->num_background--;
-		fc->active_background--;
-		flush_bg_queue(fc);
-		spin_unlock(&fc->bg_lock);
+		fch->num_background--;
+		fch->active_background--;
+		flush_bg_queue(fch);
+		spin_unlock(&fch->bg_lock);
 	} else {
 		/* Wake up waiter sleeping in request_wait_answer() */
 		wake_up(&req->waitq);
 	}
 
 	if (test_bit(FR_ASYNC, &req->flags))
-		req->args->end(fm, req->args, req->out.h.error);
+		req->args->end(req->args, req->out.h.error);
 put_request:
 	fuse_put_request(req);
 }
@@ -512,7 +659,7 @@ EXPORT_SYMBOL_GPL(fuse_request_end);
 
 static int queue_interrupt(struct fuse_req *req)
 {
-	struct fuse_iqueue *fiq = &req->fm->fc->iq;
+	struct fuse_iqueue *fiq = &req->chan->iq;
 
 	/* Check for we've sent request to interrupt this req */
 	if (unlikely(!test_bit(FR_INTERRUPTED, &req->flags)))
@@ -543,11 +690,11 @@ bool fuse_remove_pending_req(struct fuse_req *req, spinlock_t *lock)
 
 static void request_wait_answer(struct fuse_req *req)
 {
-	struct fuse_conn *fc = req->fm->fc;
-	struct fuse_iqueue *fiq = &fc->iq;
+	struct fuse_chan *fch = req->chan;
+	struct fuse_iqueue *fiq = &fch->iq;
 	int err;
 
-	if (!fc->no_interrupt) {
+	if (!fch->no_interrupt) {
 		/* Any signal may interrupt this */
 		err = wait_event_interruptible(req->waitq,
 					test_bit(FR_FINISHED, &req->flags));
@@ -571,7 +718,7 @@ static void request_wait_answer(struct fuse_req *req)
 			return;
 
 		if (req->args->abort_on_kill) {
-			fuse_abort_conn(fc);
+			fuse_chan_abort(fch, false);
 			return;
 		}
 
@@ -592,7 +739,7 @@ static void request_wait_answer(struct fuse_req *req)
 
 static void __fuse_request_send(struct fuse_req *req)
 {
-	struct fuse_iqueue *fiq = &req->fm->fc->iq;
+	struct fuse_iqueue *fiq = &req->chan->iq;
 
 	BUG_ON(test_bit(FR_BACKGROUND, &req->flags));
 
@@ -606,12 +753,12 @@ static void __fuse_request_send(struct fuse_req *req)
 	smp_rmb();
 }
 
-static void fuse_adjust_compat(struct fuse_conn *fc, struct fuse_args *args)
+static void fuse_adjust_compat(struct fuse_chan *fch, struct fuse_args *args)
 {
-	if (fc->minor < 4 && args->opcode == FUSE_STATFS)
+	if (fch->minor < 4 && args->opcode == FUSE_STATFS)
 		args->out_args[0].size = FUSE_COMPAT_STATFS_SIZE;
 
-	if (fc->minor < 9) {
+	if (fch->minor < 9) {
 		switch (args->opcode) {
 		case FUSE_LOOKUP:
 		case FUSE_CREATE:
@@ -627,7 +774,7 @@ static void fuse_adjust_compat(struct fuse_conn *fc, struct fuse_args *args)
 			break;
 		}
 	}
-	if (fc->minor < 12) {
+	if (fch->minor < 12) {
 		switch (args->opcode) {
 		case FUSE_CREATE:
 			args->in_args[0].size = sizeof(struct fuse_open_in);
@@ -639,25 +786,13 @@ static void fuse_adjust_compat(struct fuse_conn *fc, struct fuse_args *args)
 	}
 }
 
-static void fuse_force_creds(struct fuse_req *req)
-{
-	struct fuse_conn *fc = req->fm->fc;
-
-	if (!req->fm->sb || req->fm->sb->s_iflags & SB_I_NOIDMAP) {
-		req->in.h.uid = from_kuid_munged(fc->user_ns, current_fsuid());
-		req->in.h.gid = from_kgid_munged(fc->user_ns, current_fsgid());
-	} else {
-		req->in.h.uid = FUSE_INVALID_UIDGID;
-		req->in.h.gid = FUSE_INVALID_UIDGID;
-	}
-
-	req->in.h.pid = pid_nr_ns(task_pid(current), fc->pid_ns);
-}
-
 static void fuse_args_to_req(struct fuse_req *req, struct fuse_args *args)
 {
 	req->in.h.opcode = args->opcode;
 	req->in.h.nodeid = args->nodeid;
+	req->in.h.uid = args->uid;
+	req->in.h.gid = args->gid;
+	req->in.h.pid = args->pid;
 	req->args = args;
 	if (args->is_ext)
 		req->in.h.total_extlen = args->in_args[args->ext_idx].size / 8;
@@ -665,33 +800,26 @@ static void fuse_args_to_req(struct fuse_req *req, struct fuse_args *args)
 		__set_bit(FR_ASYNC, &req->flags);
 }
 
-ssize_t __fuse_simple_request(struct mnt_idmap *idmap,
-			      struct fuse_mount *fm,
-			      struct fuse_args *args)
+ssize_t fuse_chan_send(struct fuse_chan *fch, struct fuse_args *args)
 {
-	struct fuse_conn *fc = fm->fc;
 	struct fuse_req *req;
 	ssize_t ret;
 
 	if (args->force) {
-		atomic_inc(&fc->num_waiting);
-		req = fuse_request_alloc(fm, GFP_KERNEL | __GFP_NOFAIL);
-
-		if (!args->nocreds)
-			fuse_force_creds(req);
+		atomic_inc(&fch->num_waiting);
+		req = fuse_request_alloc(fch, GFP_KERNEL | __GFP_NOFAIL);
 
 		__set_bit(FR_WAITING, &req->flags);
 		if (!args->abort_on_kill)
 			__set_bit(FR_FORCE, &req->flags);
 	} else {
-		WARN_ON(args->nocreds);
-		req = fuse_get_req(idmap, fm, false);
+		req = fuse_get_req(fch, false);
 		if (IS_ERR(req))
 			return PTR_ERR(req);
 	}
 
-	/* Needs to be done after fuse_get_req() so that fc->minor is valid */
-	fuse_adjust_compat(fc, args);
+	/* Needs to be done after fuse_get_req() so that fch->minor is valid */
+	fuse_adjust_compat(fch, args);
 	fuse_args_to_req(req, args);
 
 	if (!args->noreply)
@@ -708,10 +836,9 @@ ssize_t __fuse_simple_request(struct mnt_idmap *idmap,
 }
 
 #ifdef CONFIG_FUSE_IO_URING
-static bool fuse_request_queue_background_uring(struct fuse_conn *fc,
-					       struct fuse_req *req)
+static bool fuse_request_queue_background_uring(struct fuse_req *req)
 {
-	struct fuse_iqueue *fiq = &fc->iq;
+	struct fuse_iqueue *fiq = &req->chan->iq;
 
 	req->in.h.len = sizeof(struct fuse_in_header) +
 		fuse_len_args(req->args->in_numargs,
@@ -727,50 +854,46 @@ static bool fuse_request_queue_background_uring(struct fuse_conn *fc,
  */
 static int fuse_request_queue_background(struct fuse_req *req)
 {
-	struct fuse_mount *fm = req->fm;
-	struct fuse_conn *fc = fm->fc;
+	struct fuse_chan *fch = req->chan;
 	bool queued = false;
 
 	WARN_ON(!test_bit(FR_BACKGROUND, &req->flags));
 	if (!test_bit(FR_WAITING, &req->flags)) {
 		__set_bit(FR_WAITING, &req->flags);
-		atomic_inc(&fc->num_waiting);
+		atomic_inc(&fch->num_waiting);
 	}
 	__set_bit(FR_ISREPLY, &req->flags);
 
 #ifdef CONFIG_FUSE_IO_URING
-	if (fuse_uring_ready(fc))
-		return fuse_request_queue_background_uring(fc, req);
+	if (fuse_uring_ready(fch))
+		return fuse_request_queue_background_uring(req);
 #endif
 
-	spin_lock(&fc->bg_lock);
-	if (likely(fc->connected)) {
-		fc->num_background++;
-		if (fc->num_background == fc->max_background)
-			fc->blocked = 1;
-		list_add_tail(&req->list, &fc->bg_queue);
-		flush_bg_queue(fc);
+	spin_lock(&fch->bg_lock);
+	if (likely(fch->connected)) {
+		fch->num_background++;
+		if (fch->num_background == fch->max_background)
+			fch->blocked = 1;
+		list_add_tail(&req->list, &fch->bg_queue);
+		flush_bg_queue(fch);
 		queued = true;
 	}
-	spin_unlock(&fc->bg_lock);
+	spin_unlock(&fch->bg_lock);
 
 	return queued;
 }
 
-int fuse_simple_background(struct fuse_mount *fm, struct fuse_args *args,
-			    gfp_t gfp_flags)
+int fuse_chan_send_bg(struct fuse_chan *fch, struct fuse_args *args, gfp_t gfp_flags)
 {
 	struct fuse_req *req;
 
 	if (args->force) {
-		WARN_ON(!args->nocreds);
-		req = fuse_request_alloc(fm, gfp_flags);
+		req = fuse_request_alloc(fch, gfp_flags);
 		if (!req)
 			return -ENOMEM;
 		__set_bit(FR_BACKGROUND, &req->flags);
 	} else {
-		WARN_ON(args->nocreds);
-		req = fuse_get_req(&invalid_mnt_idmap, fm, true);
+		req = fuse_get_req(fch, true);
 		if (IS_ERR(req))
 			return PTR_ERR(req);
 	}
@@ -784,15 +907,13 @@ int fuse_simple_background(struct fuse_mount *fm, struct fuse_args *args,
 
 	return 0;
 }
-EXPORT_SYMBOL_GPL(fuse_simple_background);
 
-static int fuse_simple_notify_reply(struct fuse_mount *fm,
-				    struct fuse_args *args, u64 unique)
+int fuse_chan_send_notify_reply(struct fuse_chan *fch, struct fuse_args *args, u64 unique)
 {
 	struct fuse_req *req;
-	struct fuse_iqueue *fiq = &fm->fc->iq;
+	struct fuse_iqueue *fiq = &fch->iq;
 
-	req = fuse_get_req(&invalid_mnt_idmap, fm, false);
+	req = fuse_get_req(fch, false);
 	if (IS_ERR(req))
 		return PTR_ERR(req);
 
@@ -1122,8 +1243,8 @@ static int fuse_ref_folio(struct fuse_copy_state *cs, struct folio *folio,
  * Copy a folio in the request to/from the userspace buffer.  Must be
  * done atomically
  */
-static int fuse_copy_folio(struct fuse_copy_state *cs, struct folio **foliop,
-			   unsigned offset, unsigned count, int zeroing)
+int fuse_copy_folio(struct fuse_copy_state *cs, struct folio **foliop,
+		    unsigned offset, unsigned count, int zeroing)
 {
 	int err;
 	struct folio *folio = *foliop;
@@ -1204,7 +1325,7 @@ static int fuse_copy_folios(struct fuse_copy_state *cs, unsigned nbytes,
 }
 
 /* Copy a single argument in the request to/from userspace buffer */
-static int fuse_copy_one(struct fuse_copy_state *cs, void *val, unsigned size)
+int fuse_copy_one(struct fuse_copy_state *cs, void *val, unsigned size)
 {
 	while (size) {
 		if (!cs->len) {
@@ -1388,12 +1509,12 @@ __releases(fiq->lock)
 	return ih.len;
 }
 
-static int fuse_read_forget(struct fuse_conn *fc, struct fuse_iqueue *fiq,
+static int fuse_read_forget(struct fuse_chan *fch, struct fuse_iqueue *fiq,
 			    struct fuse_copy_state *cs,
 			    size_t nbytes)
 __releases(fiq->lock)
 {
-	if (fc->minor < 16 || fiq->forget_list_head.next->next == NULL)
+	if (fch->minor < 16 || fiq->forget_list_head.next->next == NULL)
 		return fuse_read_single_forget(fiq, cs, nbytes);
 	else
 		return fuse_read_batch_forget(fiq, cs, nbytes);
@@ -1412,8 +1533,8 @@ static ssize_t fuse_dev_do_read(struct fuse_dev *fud, struct file *file,
 				struct fuse_copy_state *cs, size_t nbytes)
 {
 	ssize_t err;
-	struct fuse_conn *fc = fud->fc;
-	struct fuse_iqueue *fiq = &fc->iq;
+	struct fuse_chan *fch = fud->chan;
+	struct fuse_iqueue *fiq = &fch->iq;
 	struct fuse_pqueue *fpq = &fud->pq;
 	struct fuse_req *req;
 	struct fuse_args *args;
@@ -1435,7 +1556,7 @@ static ssize_t fuse_dev_do_read(struct fuse_dev *fud, struct file *file,
 	if (nbytes < max_t(size_t, FUSE_MIN_READ_BUFFER,
 			   sizeof(struct fuse_in_header) +
 			   sizeof(struct fuse_write_in) +
-			   fc->max_write))
+			   fch->max_write))
 		return -EINVAL;
 
  restart:
@@ -1454,7 +1575,7 @@ static ssize_t fuse_dev_do_read(struct fuse_dev *fud, struct file *file,
 	}
 
 	if (!fiq->connected) {
-		err = fc->aborted ? -ECONNABORTED : -ENODEV;
+		err = fch->abort_with_err ? -ECONNABORTED : -ENODEV;
 		goto err_unlock;
 	}
 
@@ -1466,7 +1587,7 @@ static ssize_t fuse_dev_do_read(struct fuse_dev *fud, struct file *file,
 
 	if (forget_pending(fiq)) {
 		if (list_empty(&fiq->pending) || fiq->forget_batch-- > 0)
-			return fuse_read_forget(fc, fiq, cs, nbytes);
+			return fuse_read_forget(fch, fiq, cs, nbytes);
 
 		if (fiq->forget_batch <= -8)
 			fiq->forget_batch = 16;
@@ -1492,7 +1613,7 @@ static ssize_t fuse_dev_do_read(struct fuse_dev *fud, struct file *file,
 	spin_lock(&fpq->lock);
 	/*
 	 *  Must not put request on fpq->io queue after having been shut down by
-	 *  fuse_abort_conn()
+	 *  fuse_chan_abort()
 	 */
 	if (!fpq->connected) {
 		req->out.h.error = err = -ECONNABORTED;
@@ -1510,7 +1631,7 @@ static ssize_t fuse_dev_do_read(struct fuse_dev *fud, struct file *file,
 	spin_lock(&fpq->lock);
 	clear_bit(FR_LOCKED, &req->flags);
 	if (!fpq->connected) {
-		err = fc->aborted ? -ECONNABORTED : -ENODEV;
+		err = fch->abort_with_err ? -ECONNABORTED : -ENODEV;
 		goto out_end;
 	}
 	if (err) {
@@ -1548,7 +1669,7 @@ static ssize_t fuse_dev_do_read(struct fuse_dev *fud, struct file *file,
 
 static int fuse_dev_open(struct inode *inode, struct file *file)
 {
-	struct fuse_dev *fud = fuse_dev_alloc();
+	struct fuse_dev *fud = fuse_dev_alloc_no_pq();
 
 	if (!fud)
 		return -ENOMEM;
@@ -1562,9 +1683,15 @@ struct fuse_dev *fuse_get_dev(struct file *file)
 	struct fuse_dev *fud = fuse_file_to_fud(file);
 	int err;
 
-	err = wait_event_interruptible(fuse_dev_waitq, fuse_dev_fc_get(fud) != NULL);
-	if (err)
-		return ERR_PTR(err);
+	if (unlikely(!fuse_dev_chan_get(fud))) {
+		/* only block waiting for mount if sync init was requested */
+		if (!fud->sync_init)
+			return ERR_PTR(-EPERM);
+
+		err = wait_event_interruptible(fuse_dev_waitq, fuse_dev_chan_get(fud) != NULL);
+		if (err)
+			return ERR_PTR(err);
+	}
 
 	return fud;
 }
@@ -1636,344 +1763,6 @@ static ssize_t fuse_dev_splice_read(struct file *in, loff_t *ppos,
 	return ret;
 }
 
-static int fuse_notify_poll(struct fuse_conn *fc, unsigned int size,
-			    struct fuse_copy_state *cs)
-{
-	struct fuse_notify_poll_wakeup_out outarg;
-	int err;
-
-	if (size != sizeof(outarg))
-		return -EINVAL;
-
-	err = fuse_copy_one(cs, &outarg, sizeof(outarg));
-	if (err)
-		return err;
-
-	fuse_copy_finish(cs);
-	return fuse_notify_poll_wakeup(fc, &outarg);
-}
-
-static int fuse_notify_inval_inode(struct fuse_conn *fc, unsigned int size,
-				   struct fuse_copy_state *cs)
-{
-	struct fuse_notify_inval_inode_out outarg;
-	int err;
-
-	if (size != sizeof(outarg))
-		return -EINVAL;
-
-	err = fuse_copy_one(cs, &outarg, sizeof(outarg));
-	if (err)
-		return err;
-	fuse_copy_finish(cs);
-
-	down_read(&fc->killsb);
-	err = fuse_reverse_inval_inode(fc, outarg.ino,
-				       outarg.off, outarg.len);
-	up_read(&fc->killsb);
-	return err;
-}
-
-static int fuse_notify_inval_entry(struct fuse_conn *fc, unsigned int size,
-				   struct fuse_copy_state *cs)
-{
-	struct fuse_notify_inval_entry_out outarg;
-	int err;
-	char *buf;
-	struct qstr name;
-
-	if (size < sizeof(outarg))
-		return -EINVAL;
-
-	err = fuse_copy_one(cs, &outarg, sizeof(outarg));
-	if (err)
-		return err;
-
-	if (outarg.namelen > fc->name_max)
-		return -ENAMETOOLONG;
-
-	err = -EINVAL;
-	if (size != sizeof(outarg) + outarg.namelen + 1)
-		return -EINVAL;
-
-	buf = kzalloc(outarg.namelen + 1, GFP_KERNEL);
-	if (!buf)
-		return -ENOMEM;
-
-	name.name = buf;
-	name.len = outarg.namelen;
-	err = fuse_copy_one(cs, buf, outarg.namelen + 1);
-	if (err)
-		goto err;
-	fuse_copy_finish(cs);
-	buf[outarg.namelen] = 0;
-
-	down_read(&fc->killsb);
-	err = fuse_reverse_inval_entry(fc, outarg.parent, 0, &name, outarg.flags);
-	up_read(&fc->killsb);
-err:
-	kfree(buf);
-	return err;
-}
-
-static int fuse_notify_delete(struct fuse_conn *fc, unsigned int size,
-			      struct fuse_copy_state *cs)
-{
-	struct fuse_notify_delete_out outarg;
-	int err;
-	char *buf;
-	struct qstr name;
-
-	if (size < sizeof(outarg))
-		return -EINVAL;
-
-	err = fuse_copy_one(cs, &outarg, sizeof(outarg));
-	if (err)
-		return err;
-
-	if (outarg.namelen > fc->name_max)
-		return -ENAMETOOLONG;
-
-	if (size != sizeof(outarg) + outarg.namelen + 1)
-		return -EINVAL;
-
-	buf = kzalloc(outarg.namelen + 1, GFP_KERNEL);
-	if (!buf)
-		return -ENOMEM;
-
-	name.name = buf;
-	name.len = outarg.namelen;
-	err = fuse_copy_one(cs, buf, outarg.namelen + 1);
-	if (err)
-		goto err;
-	fuse_copy_finish(cs);
-	buf[outarg.namelen] = 0;
-
-	down_read(&fc->killsb);
-	err = fuse_reverse_inval_entry(fc, outarg.parent, outarg.child, &name, 0);
-	up_read(&fc->killsb);
-err:
-	kfree(buf);
-	return err;
-}
-
-static int fuse_notify_store(struct fuse_conn *fc, unsigned int size,
-			     struct fuse_copy_state *cs)
-{
-	struct fuse_notify_store_out outarg;
-	struct inode *inode;
-	struct address_space *mapping;
-	u64 nodeid;
-	int err;
-	unsigned int num;
-	loff_t file_size;
-	loff_t pos;
-	loff_t end;
-
-	if (size < sizeof(outarg))
-		return -EINVAL;
-
-	err = fuse_copy_one(cs, &outarg, sizeof(outarg));
-	if (err)
-		return err;
-
-	if (size - sizeof(outarg) != outarg.size)
-		return -EINVAL;
-
-	if (outarg.offset >= MAX_LFS_FILESIZE)
-		return -EINVAL;
-
-	nodeid = outarg.nodeid;
-	pos = outarg.offset;
-	num = min(outarg.size, MAX_LFS_FILESIZE - pos);
-
-	down_read(&fc->killsb);
-
-	err = -ENOENT;
-	inode = fuse_ilookup(fc, nodeid,  NULL);
-	if (!inode)
-		goto out_up_killsb;
-
-	mapping = inode->i_mapping;
-	file_size = i_size_read(inode);
-	end = pos + num;
-	if (end > file_size) {
-		file_size = end;
-		fuse_write_update_attr(inode, file_size, num);
-	}
-
-	while (num) {
-		struct folio *folio;
-		unsigned int folio_offset;
-		unsigned int nr_bytes;
-		pgoff_t index = pos >> PAGE_SHIFT;
-
-		folio = filemap_grab_folio(mapping, index);
-		err = PTR_ERR(folio);
-		if (IS_ERR(folio))
-			goto out_iput;
-
-		folio_offset = offset_in_folio(folio, pos);
-		nr_bytes = min(num, folio_size(folio) - folio_offset);
-
-		err = fuse_copy_folio(cs, &folio, folio_offset, nr_bytes, 0);
-		if (!folio_test_uptodate(folio) && !err && folio_offset == 0 &&
-		    (nr_bytes == folio_size(folio) || file_size == end)) {
-			folio_zero_segment(folio, nr_bytes, folio_size(folio));
-			folio_mark_uptodate(folio);
-		}
-		folio_unlock(folio);
-		folio_put(folio);
-
-		if (err)
-			goto out_iput;
-
-		pos += nr_bytes;
-		num -= nr_bytes;
-	}
-
-	err = 0;
-
-out_iput:
-	iput(inode);
-out_up_killsb:
-	up_read(&fc->killsb);
-	return err;
-}
-
-struct fuse_retrieve_args {
-	struct fuse_args_pages ap;
-	struct fuse_notify_retrieve_in inarg;
-};
-
-static void fuse_retrieve_end(struct fuse_mount *fm, struct fuse_args *args,
-			      int error)
-{
-	struct fuse_retrieve_args *ra =
-		container_of(args, typeof(*ra), ap.args);
-
-	release_pages(ra->ap.folios, ra->ap.num_folios);
-	kfree(ra);
-}
-
-static int fuse_retrieve(struct fuse_mount *fm, struct inode *inode,
-			 struct fuse_notify_retrieve_out *outarg)
-{
-	int err;
-	struct address_space *mapping = inode->i_mapping;
-	loff_t file_size;
-	unsigned int num;
-	unsigned int offset;
-	size_t total_len = 0;
-	unsigned int num_pages;
-	struct fuse_conn *fc = fm->fc;
-	struct fuse_retrieve_args *ra;
-	size_t args_size = sizeof(*ra);
-	struct fuse_args_pages *ap;
-	struct fuse_args *args;
-	loff_t pos = outarg->offset;
-
-	offset = offset_in_page(pos);
-	file_size = i_size_read(inode);
-
-	num = min(outarg->size, fc->max_write);
-	if (pos > file_size)
-		num = 0;
-	else if (num > file_size - pos)
-		num = file_size - pos;
-
-	num_pages = DIV_ROUND_UP(num + offset, PAGE_SIZE);
-	num_pages = min(num_pages, fc->max_pages);
-	num = min(num, num_pages << PAGE_SHIFT);
-
-	args_size += num_pages * (sizeof(ap->folios[0]) + sizeof(ap->descs[0]));
-
-	ra = kzalloc(args_size, GFP_KERNEL);
-	if (!ra)
-		return -ENOMEM;
-
-	ap = &ra->ap;
-	ap->folios = (void *) (ra + 1);
-	ap->descs = (void *) (ap->folios + num_pages);
-
-	args = &ap->args;
-	args->nodeid = outarg->nodeid;
-	args->opcode = FUSE_NOTIFY_REPLY;
-	args->in_numargs = 3;
-	args->in_pages = true;
-	args->end = fuse_retrieve_end;
-
-	while (num && ap->num_folios < num_pages) {
-		struct folio *folio;
-		unsigned int folio_offset;
-		unsigned int nr_bytes;
-		pgoff_t index = pos >> PAGE_SHIFT;
-
-		folio = filemap_get_folio(mapping, index);
-		if (IS_ERR(folio))
-			break;
-
-		folio_offset = offset_in_folio(folio, pos);
-		nr_bytes = min(folio_size(folio) - folio_offset, num);
-
-		ap->folios[ap->num_folios] = folio;
-		ap->descs[ap->num_folios].offset = folio_offset;
-		ap->descs[ap->num_folios].length = nr_bytes;
-		ap->num_folios++;
-
-		pos += nr_bytes;
-		num -= nr_bytes;
-		total_len += nr_bytes;
-	}
-	ra->inarg.offset = outarg->offset;
-	ra->inarg.size = total_len;
-	fuse_set_zero_arg0(args);
-	args->in_args[1].size = sizeof(ra->inarg);
-	args->in_args[1].value = &ra->inarg;
-	args->in_args[2].size = total_len;
-
-	err = fuse_simple_notify_reply(fm, args, outarg->notify_unique);
-	if (err)
-		fuse_retrieve_end(fm, args, err);
-
-	return err;
-}
-
-static int fuse_notify_retrieve(struct fuse_conn *fc, unsigned int size,
-				struct fuse_copy_state *cs)
-{
-	struct fuse_notify_retrieve_out outarg;
-	struct fuse_mount *fm;
-	struct inode *inode;
-	u64 nodeid;
-	int err;
-
-	if (size != sizeof(outarg))
-		return -EINVAL;
-
-	err = fuse_copy_one(cs, &outarg, sizeof(outarg));
-	if (err)
-		return err;
-
-	fuse_copy_finish(cs);
-
-	if (outarg.offset >= MAX_LFS_FILESIZE)
-		return -EINVAL;
-
-	down_read(&fc->killsb);
-	err = -ENOENT;
-	nodeid = outarg.nodeid;
-
-	inode = fuse_ilookup(fc, nodeid, &fm);
-	if (inode) {
-		err = fuse_retrieve(fm, inode, &outarg);
-		iput(inode);
-	}
-	up_read(&fc->killsb);
-
-	return err;
-}
-
 /*
  * Resending all processing queue requests.
  *
@@ -1987,21 +1776,21 @@ static int fuse_notify_retrieve(struct fuse_conn *fc, unsigned int size,
  * if the FUSE daemon takes careful measures to avoid processing duplicated
  * non-idempotent requests.
  */
-static void fuse_resend(struct fuse_conn *fc)
+void fuse_chan_resend(struct fuse_chan *fch)
 {
 	struct fuse_dev *fud;
 	struct fuse_req *req, *next;
-	struct fuse_iqueue *fiq = &fc->iq;
+	struct fuse_iqueue *fiq = &fch->iq;
 	LIST_HEAD(to_queue);
 	unsigned int i;
 
-	spin_lock(&fc->lock);
-	if (!fc->connected) {
-		spin_unlock(&fc->lock);
+	spin_lock(&fch->lock);
+	if (!fch->connected) {
+		spin_unlock(&fch->lock);
 		return;
 	}
 
-	list_for_each_entry(fud, &fc->devices, entry) {
+	list_for_each_entry(fud, &fch->devices, entry) {
 		struct fuse_pqueue *fpq = &fud->pq;
 
 		spin_lock(&fpq->lock);
@@ -2009,7 +1798,7 @@ static void fuse_resend(struct fuse_conn *fc)
 			list_splice_tail_init(&fpq->processing[i], &to_queue);
 		spin_unlock(&fpq->lock);
 	}
-	spin_unlock(&fc->lock);
+	spin_unlock(&fch->lock);
 
 	list_for_each_entry_safe(req, next, &to_queue, list) {
 		set_bit(FR_PENDING, &req->flags);
@@ -2031,108 +1820,6 @@ static void fuse_resend(struct fuse_conn *fc)
 	fuse_dev_wake_and_unlock(fiq);
 }
 
-static int fuse_notify_resend(struct fuse_conn *fc)
-{
-	fuse_resend(fc);
-	return 0;
-}
-
-/*
- * Increments the fuse connection epoch.  This will result of dentries from
- * previous epochs to be invalidated.  Additionally, if inval_wq is set, a work
- * queue is scheduled to trigger the invalidation.
- */
-static int fuse_notify_inc_epoch(struct fuse_conn *fc)
-{
-	atomic_inc(&fc->epoch);
-	if (inval_wq)
-		schedule_work(&fc->epoch_work);
-
-	return 0;
-}
-
-static int fuse_notify_prune(struct fuse_conn *fc, unsigned int size,
-			     struct fuse_copy_state *cs)
-{
-	struct fuse_notify_prune_out outarg;
-	const unsigned int batch = 512;
-	u64 *nodeids __free(kfree) = kmalloc(sizeof(u64) * batch, GFP_KERNEL);
-	unsigned int num, i;
-	int err;
-
-	if (!nodeids)
-		return -ENOMEM;
-
-	if (size < sizeof(outarg))
-		return -EINVAL;
-
-	err = fuse_copy_one(cs, &outarg, sizeof(outarg));
-	if (err)
-		return err;
-
-	if (size - sizeof(outarg) != outarg.count * sizeof(u64))
-		return -EINVAL;
-
-	for (; outarg.count; outarg.count -= num) {
-		num = min(batch, outarg.count);
-		err = fuse_copy_one(cs, nodeids, num * sizeof(u64));
-		if (err)
-			return err;
-
-		scoped_guard(rwsem_read, &fc->killsb) {
-			for (i = 0; i < num; i++)
-				fuse_try_prune_one_inode(fc, nodeids[i]);
-		}
-	}
-	return 0;
-}
-
-static int fuse_notify(struct fuse_conn *fc, enum fuse_notify_code code,
-		       unsigned int size, struct fuse_copy_state *cs)
-{
-	/*
-	 * Only allow notifications during while the connection is in an
-	 * initialized and connected state
-	 */
-	if (!fc->initialized || !fc->connected)
-		return -EINVAL;
-
-	/* Don't try to move folios (yet) */
-	cs->move_folios = false;
-
-	switch (code) {
-	case FUSE_NOTIFY_POLL:
-		return fuse_notify_poll(fc, size, cs);
-
-	case FUSE_NOTIFY_INVAL_INODE:
-		return fuse_notify_inval_inode(fc, size, cs);
-
-	case FUSE_NOTIFY_INVAL_ENTRY:
-		return fuse_notify_inval_entry(fc, size, cs);
-
-	case FUSE_NOTIFY_STORE:
-		return fuse_notify_store(fc, size, cs);
-
-	case FUSE_NOTIFY_RETRIEVE:
-		return fuse_notify_retrieve(fc, size, cs);
-
-	case FUSE_NOTIFY_DELETE:
-		return fuse_notify_delete(fc, size, cs);
-
-	case FUSE_NOTIFY_RESEND:
-		return fuse_notify_resend(fc);
-
-	case FUSE_NOTIFY_INC_EPOCH:
-		return fuse_notify_inc_epoch(fc);
-
-	case FUSE_NOTIFY_PRUNE:
-		return fuse_notify_prune(fc, size, cs);
-
-	default:
-		return -EINVAL;
-	}
-}
-
 /* Look up request on processing list by unique ID */
 struct fuse_req *fuse_request_find(struct fuse_pqueue *fpq, u64 unique)
 {
@@ -2185,7 +1872,7 @@ static ssize_t fuse_dev_do_write(struct fuse_dev *fud,
 				 struct fuse_copy_state *cs, size_t nbytes)
 {
 	int err;
-	struct fuse_conn *fc = fud->fc;
+	struct fuse_chan *fch = fud->chan;
 	struct fuse_pqueue *fpq = &fud->pq;
 	struct fuse_req *req;
 	struct fuse_out_header oh;
@@ -2207,7 +1894,18 @@ static ssize_t fuse_dev_do_write(struct fuse_dev *fud,
 	 * and error contains notification code.
 	 */
 	if (!oh.unique) {
-		err = fuse_notify(fc, oh.error, nbytes - sizeof(oh), cs);
+		/*
+		 * Only allow notifications during while the connection is in an
+		 * initialized and connected state
+		 */
+		err = -EINVAL;
+		if (!fch->initialized || !fch->connected)
+			goto copy_finish;
+
+		/* Don't try to move folios (yet) */
+		cs->move_folios = false;
+
+		err = fuse_notify(fch->conn, oh.error, nbytes - sizeof(oh), cs);
 		goto copy_finish;
 	}
 
@@ -2235,7 +1933,7 @@ static ssize_t fuse_dev_do_write(struct fuse_dev *fud,
 		if (nbytes != sizeof(struct fuse_out_header))
 			err = -EINVAL;
 		else if (oh.error == -ENOSYS)
-			fc->no_interrupt = 1;
+			fch->no_interrupt = 1;
 		else if (oh.error == -EAGAIN)
 			err = queue_interrupt(req);
 
@@ -2395,7 +2093,7 @@ static __poll_t fuse_dev_poll(struct file *file, poll_table *wait)
 	if (IS_ERR(fud))
 		return EPOLLERR;
 
-	fiq = &fud->fc->iq;
+	fiq = &fud->chan->iq;
 	poll_wait(file, &fiq->waitq, wait);
 
 	spin_lock(&fiq->lock);
@@ -2421,21 +2119,6 @@ void fuse_dev_end_requests(struct list_head *head)
 	}
 }
 
-static void end_polls(struct fuse_conn *fc)
-{
-	struct rb_node *p;
-
-	p = rb_first(&fc->polled_files);
-
-	while (p) {
-		struct fuse_file *ff;
-		ff = rb_entry(p, struct fuse_file, polled_node);
-		wake_up_interruptible_all(&ff->poll_wait);
-
-		p = rb_next(p);
-	}
-}
-
 /*
  * Abort all requests.
  *
@@ -2454,27 +2137,29 @@ static void end_polls(struct fuse_conn *fc)
  * is OK, the request will in that case be removed from the list before we touch
  * it.
  */
-void fuse_abort_conn(struct fuse_conn *fc)
+void fuse_chan_abort(struct fuse_chan *fch, bool abort_with_err)
 {
-	struct fuse_iqueue *fiq = &fc->iq;
+	struct fuse_iqueue *fiq = &fch->iq;
+
+	fch->abort_with_err = abort_with_err;
 
-	spin_lock(&fc->lock);
-	if (fc->connected) {
+	spin_lock(&fch->lock);
+	if (fch->connected) {
 		struct fuse_dev *fud;
 		struct fuse_req *req, *next;
 		LIST_HEAD(to_end);
 		unsigned int i;
 
-		if (fc->timeout.req_timeout)
-			cancel_delayed_work(&fc->timeout.work);
+		if (fch->timeout.req_timeout)
+			cancel_delayed_work(&fch->timeout.work);
 
-		/* Background queuing checks fc->connected under bg_lock */
-		spin_lock(&fc->bg_lock);
-		fc->connected = 0;
-		spin_unlock(&fc->bg_lock);
+		/* Background queuing checks fch->connected under bg_lock */
+		spin_lock(&fch->bg_lock);
+		fch->connected = 0;
+		spin_unlock(&fch->bg_lock);
 
-		fuse_set_initialized(fc);
-		list_for_each_entry(fud, &fc->devices, entry) {
+		fuse_chan_set_initialized(fch, 0);
+		list_for_each_entry(fud, &fch->devices, entry) {
 			struct fuse_pqueue *fpq = &fud->pq;
 
 			spin_lock(&fpq->lock);
@@ -2495,11 +2180,11 @@ void fuse_abort_conn(struct fuse_conn *fc)
 						      &to_end);
 			spin_unlock(&fpq->lock);
 		}
-		spin_lock(&fc->bg_lock);
-		fc->blocked = 0;
-		fc->max_background = UINT_MAX;
-		flush_bg_queue(fc);
-		spin_unlock(&fc->bg_lock);
+		spin_lock(&fch->bg_lock);
+		fch->blocked = 0;
+		fch->max_background = UINT_MAX;
+		flush_bg_queue(fch);
+		spin_unlock(&fch->bg_lock);
 
 		spin_lock(&fiq->lock);
 		fiq->connected = 0;
@@ -2511,39 +2196,39 @@ void fuse_abort_conn(struct fuse_conn *fc)
 		wake_up_all(&fiq->waitq);
 		spin_unlock(&fiq->lock);
 		kill_fasync(&fiq->fasync, SIGIO, POLL_IN);
-		end_polls(fc);
-		wake_up_all(&fc->blocked_waitq);
-		spin_unlock(&fc->lock);
+		fuse_end_polls(fch->conn);
+		wake_up_all(&fch->blocked_waitq);
+		spin_unlock(&fch->lock);
 
 		fuse_dev_end_requests(&to_end);
 
 		/*
-		 * fc->lock must not be taken to avoid conflicts with io-uring
+		 * fch->lock must not be taken to avoid conflicts with io-uring
 		 * locks
 		 */
-		fuse_uring_abort(fc);
+		fuse_uring_abort(fch);
 	} else {
-		spin_unlock(&fc->lock);
+		spin_unlock(&fch->lock);
 	}
 }
-EXPORT_SYMBOL_GPL(fuse_abort_conn);
+EXPORT_SYMBOL_GPL(fuse_chan_abort);
 
-void fuse_wait_aborted(struct fuse_conn *fc)
+void fuse_chan_wait_aborted(struct fuse_chan *fch)
 {
 	/* matches implicit memory barrier in fuse_drop_waiting() */
 	smp_mb();
-	wait_event(fc->blocked_waitq, atomic_read(&fc->num_waiting) == 0);
+	wait_event(fch->blocked_waitq, fuse_chan_num_waiting(fch) == 0);
 
-	fuse_uring_wait_stopped_queues(fc);
+	fuse_uring_wait_stopped_queues(fch);
 }
 
 int fuse_dev_release(struct inode *inode, struct file *file)
 {
 	struct fuse_dev *fud = fuse_file_to_fud(file);
 	/* Pairs with cmpxchg() in fuse_dev_install() */
-	struct fuse_conn *fc = xchg(&fud->fc, FUSE_DEV_FC_DISCONNECTED);
+	struct fuse_chan *fch = xchg(&fud->chan, FUSE_DEV_CHAN_DISCONNECTED);
 
-	if (fc) {
+	if (fch) {
 		struct fuse_pqueue *fpq = &fud->pq;
 		LIST_HEAD(to_end);
 		unsigned int i;
@@ -2557,17 +2242,17 @@ int fuse_dev_release(struct inode *inode, struct file *file)
 
 		fuse_dev_end_requests(&to_end);
 
-		spin_lock(&fc->lock);
+		spin_lock(&fch->lock);
 		list_del(&fud->entry);
 		/* Are we the last open device? */
-		last = list_empty(&fc->devices);
-		spin_unlock(&fc->lock);
+		last = list_empty(&fch->devices);
+		spin_unlock(&fch->lock);
 
 		if (last) {
-			WARN_ON(fc->iq.fasync != NULL);
-			fuse_abort_conn(fc);
+			WARN_ON(fch->iq.fasync != NULL);
+			fuse_chan_abort(fch, false);
 		}
-		fuse_conn_put(fc);
+		fuse_conn_put(fch->conn);
 	}
 	fuse_dev_put(fud);
 	return 0;
@@ -2582,13 +2267,14 @@ static int fuse_dev_fasync(int fd, struct file *file, int on)
 		return PTR_ERR(fud);
 
 	/* No locking - fasync_helper does its own locking */
-	return fasync_helper(fd, file, on, &fud->fc->iq.fasync);
+	return fasync_helper(fd, file, on, &fud->chan->iq.fasync);
 }
 
 static long fuse_dev_ioctl_clone(struct file *file, __u32 __user *argp)
 {
 	int oldfd;
 	struct fuse_dev *fud, *new_fud;
+	struct list_head *pq;
 
 	if (get_user(oldfd, argp))
 		return -EFAULT;
@@ -2608,12 +2294,14 @@ static long fuse_dev_ioctl_clone(struct file *file, __u32 __user *argp)
 	if (IS_ERR(fud))
 		return PTR_ERR(fud);
 
+	pq = fuse_pqueue_alloc();
+	if (!pq)
+		return -ENOMEM;
+
 	new_fud = fuse_file_to_fud(file);
-	if (fuse_dev_fc_get(new_fud))
+	if (!fuse_dev_install_with_pq(new_fud, fud->chan, pq))
 		return -EINVAL;
 
-	fuse_dev_install(new_fud, fud->fc);
-
 	return 0;
 }
 
@@ -2632,7 +2320,7 @@ static long fuse_dev_ioctl_backing_open(struct file *file,
 	if (copy_from_user(&map, argp, sizeof(map)))
 		return -EFAULT;
 
-	return fuse_backing_open(fud->fc, &map);
+	return fuse_backing_open(fud->chan->conn, &map);
 }
 
 static long fuse_dev_ioctl_backing_close(struct file *file, __u32 __user *argp)
@@ -2649,21 +2337,18 @@ static long fuse_dev_ioctl_backing_close(struct file *file, __u32 __user *argp)
 	if (get_user(backing_id, argp))
 		return -EFAULT;
 
-	return fuse_backing_close(fud->fc, backing_id);
+	return fuse_backing_close(fud->chan->conn, backing_id);
 }
 
 static long fuse_dev_ioctl_sync_init(struct file *file)
 {
-	int err = -EINVAL;
 	struct fuse_dev *fud = fuse_file_to_fud(file);
 
-	mutex_lock(&fuse_mutex);
-	if (!fuse_dev_fc_get(fud)) {
-		fud->sync_init = true;
-		err = 0;
-	}
-	mutex_unlock(&fuse_mutex);
-	return err;
+	if (fuse_dev_chan_get(fud))
+		return -EINVAL;
+
+	fud->sync_init = true;
+	return 0;
 }
 
 static long fuse_dev_ioctl(struct file *file, unsigned int cmd,
@@ -2696,7 +2381,7 @@ static void fuse_dev_show_fdinfo(struct seq_file *seq, struct file *file)
 	if (!fud)
 		return;
 
-	seq_printf(seq, "fuse_connection:\t%u\n", fud->fc->dev);
+	seq_printf(seq, "fuse_connection:\t%u\n", fuse_conn_get_id(fud->chan->conn));
 }
 #endif
 
diff --git a/fs/fuse/dev.h b/fs/fuse/dev.h
new file mode 100644
index 000000000000..aed69fd14c41
--- /dev/null
+++ b/fs/fuse/dev.h
@@ -0,0 +1,110 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifndef _FS_FUSE_DEV_H
+#define _FS_FUSE_DEV_H
+
+#include <linux/cleanup.h>
+
+/** Maximum number of outstanding background requests */
+#define FUSE_DEFAULT_MAX_BACKGROUND 12
+
+struct fuse_conn;
+struct fuse_chan;
+struct fuse_dev;
+struct fuse_args;
+struct fuse_copy_state;
+struct fuse_backing_map;
+struct file;
+struct folio;
+enum fuse_notify_code;
+
+struct fuse_chan_param {
+	unsigned int minor;
+	unsigned int max_write;
+	unsigned int max_pages;
+};
+
+struct fuse_chan *fuse_chan_new(void);
+struct fuse_chan *fuse_dev_chan_new(void);
+void fuse_chan_release(struct fuse_chan *fch);
+void fuse_chan_free(struct fuse_chan *fch);
+unsigned int fuse_chan_num_background(struct fuse_chan *fch);
+unsigned int fuse_chan_max_background(struct fuse_chan *fch);
+void fuse_chan_max_background_set(struct fuse_chan *fch, unsigned int val);
+unsigned int fuse_chan_num_waiting(struct fuse_chan *fch);
+void fuse_chan_set_fc(struct fuse_chan *fch, struct fuse_conn *fc);
+void fuse_chan_set_initialized(struct fuse_chan *fch, struct fuse_chan_param *param);
+void fuse_chan_io_uring_enable(struct fuse_chan *fch);
+ssize_t fuse_chan_send(struct fuse_chan *fch, struct fuse_args *args);
+int fuse_chan_send_bg(struct fuse_chan *fch, struct fuse_args *args, gfp_t gfp_flags);
+int fuse_chan_send_notify_reply(struct fuse_chan *fch, struct fuse_args *args, u64 unique);
+void fuse_chan_resend(struct fuse_chan *fch);
+
+struct fuse_forget_link *fuse_alloc_forget(void);
+void fuse_chan_queue_forget(struct fuse_chan *fch, struct fuse_forget_link *forget,
+			    u64 nodeid, u64 nlookup);
+
+DEFINE_FREE(fuse_chan_free, struct fuse_chan *, if (_T) fuse_chan_free(_T))
+
+/**
+ * Initialize the client device
+ */
+int fuse_dev_init(void);
+
+/**
+ * Cleanup the client device
+ */
+void fuse_dev_cleanup(void);
+
+void fuse_dev_install(struct fuse_dev *fud, struct fuse_chan *fch);
+bool fuse_dev_verify(struct fuse_dev *fud, struct fuse_chan *fch);
+void fuse_dev_put(struct fuse_dev *fud);
+bool fuse_dev_is_installed(struct fuse_dev *fud);
+bool fuse_dev_is_sync_init(struct fuse_dev *fud);
+struct fuse_dev *fuse_dev_grab(struct file *file);
+
+void fuse_init_server_timeout(struct fuse_chan *fch, unsigned int timeout);
+
+/* Abort all requests */
+void fuse_chan_abort(struct fuse_chan *fch, bool abort_with_err);
+void fuse_chan_wait_aborted(struct fuse_chan *fch);
+
+/**
+ * Acquire reference to fuse_conn
+ */
+struct fuse_conn *fuse_conn_get(struct fuse_conn *fc);
+
+/**
+ * Release reference to fuse_conn
+ */
+void fuse_conn_put(struct fuse_conn *fc);
+
+dev_t fuse_conn_get_id(struct fuse_conn *fc);
+
+void fuse_end_polls(struct fuse_conn *fc);
+int fuse_notify(struct fuse_conn *fc, enum fuse_notify_code code,
+		unsigned int size, struct fuse_copy_state *cs);
+
+int fuse_backing_open(struct fuse_conn *fc, struct fuse_backing_map *map);
+int fuse_backing_close(struct fuse_conn *fc, int backing_id);
+
+int fuse_copy_one(struct fuse_copy_state *cs, void *val, unsigned size);
+int fuse_copy_folio(struct fuse_copy_state *cs, struct folio **foliop,
+		    unsigned offset, unsigned count, int zeroing);
+void fuse_copy_finish(struct fuse_copy_state *cs);
+
+#ifdef CONFIG_FUSE_IO_URING
+bool fuse_uring_enabled(void);
+void fuse_uring_destruct(struct fuse_chan *fch);
+#else /* CONFIG_FUSE_IO_URING */
+static inline bool fuse_uring_enabled(void)
+{
+	return false;
+}
+
+static inline void fuse_uring_destruct(struct fuse_chan *fch)
+{
+}
+#endif /* CONFIG_FUSE_IO_URING */
+
+#endif /* _FS_FUSE_DEV_H */
diff --git a/fs/fuse/dev_uring.c b/fs/fuse/dev_uring.c
index 7b9822e8837b..e467b23e6895 100644
--- a/fs/fuse/dev_uring.c
+++ b/fs/fuse/dev_uring.c
@@ -4,9 +4,9 @@
  * Copyright (c) 2023-2024 DataDirect Networks.
  */
 
-#include "fuse_i.h"
+#include "dev.h"
+#include "args.h"
 #include "dev_uring_i.h"
-#include "fuse_dev_i.h"
 #include "fuse_trace.h"
 
 #include <linux/fs.h>
@@ -51,10 +51,10 @@ static struct fuse_ring_ent *uring_cmd_to_ring_ent(struct io_uring_cmd *cmd)
 static void fuse_uring_flush_bg(struct fuse_ring_queue *queue)
 {
 	struct fuse_ring *ring = queue->ring;
-	struct fuse_conn *fc = ring->fc;
+	struct fuse_chan *fch = ring->chan;
 
 	lockdep_assert_held(&queue->lock);
-	lockdep_assert_held(&fc->bg_lock);
+	lockdep_assert_held(&fch->bg_lock);
 
 	/*
 	 * Allow one bg request per queue, ignoring global fc limits.
@@ -62,14 +62,14 @@ static void fuse_uring_flush_bg(struct fuse_ring_queue *queue)
 	 * eliminates the need for remote queue wake-ups when global
 	 * limits are met but this queue has no more waiting requests.
 	 */
-	while ((fc->active_background < fc->max_background ||
+	while ((fch->active_background < fch->max_background ||
 		!queue->active_background) &&
 	       (!list_empty(&queue->fuse_req_bg_queue))) {
 		struct fuse_req *req;
 
 		req = list_first_entry(&queue->fuse_req_bg_queue,
 				       struct fuse_req, list);
-		fc->active_background++;
+		fch->active_background++;
 		queue->active_background++;
 
 		list_move_tail(&req->list, &queue->fuse_req_queue);
@@ -81,7 +81,7 @@ static void fuse_uring_req_end(struct fuse_ring_ent *ent, struct fuse_req *req,
 {
 	struct fuse_ring_queue *queue = ent->queue;
 	struct fuse_ring *ring = queue->ring;
-	struct fuse_conn *fc = ring->fc;
+	struct fuse_chan *fch = ring->chan;
 
 	lockdep_assert_not_held(&queue->lock);
 	spin_lock(&queue->lock);
@@ -89,9 +89,9 @@ static void fuse_uring_req_end(struct fuse_ring_ent *ent, struct fuse_req *req,
 	list_del_init(&req->list);
 	if (test_bit(FR_BACKGROUND, &req->flags)) {
 		queue->active_background--;
-		spin_lock(&fc->bg_lock);
+		spin_lock(&fch->bg_lock);
 		fuse_uring_flush_bg(queue);
-		spin_unlock(&fc->bg_lock);
+		spin_unlock(&fch->bg_lock);
 	}
 
 	spin_unlock(&queue->lock);
@@ -123,7 +123,7 @@ void fuse_uring_abort_end_requests(struct fuse_ring *ring)
 {
 	int qid;
 	struct fuse_ring_queue *queue;
-	struct fuse_conn *fc = ring->fc;
+	struct fuse_chan *fch = ring->chan;
 
 	for (qid = 0; qid < ring->nr_queues; qid++) {
 		queue = READ_ONCE(ring->queues[qid]);
@@ -132,17 +132,17 @@ void fuse_uring_abort_end_requests(struct fuse_ring *ring)
 
 		queue->stopped = true;
 
-		WARN_ON_ONCE(ring->fc->max_background != UINT_MAX);
+		WARN_ON_ONCE(fch->max_background != UINT_MAX);
 		spin_lock(&queue->lock);
-		spin_lock(&fc->bg_lock);
+		spin_lock(&fch->bg_lock);
 		fuse_uring_flush_bg(queue);
-		spin_unlock(&fc->bg_lock);
+		spin_unlock(&fch->bg_lock);
 		spin_unlock(&queue->lock);
 		fuse_uring_abort_end_queue_requests(queue);
 	}
 }
 
-static bool ent_list_request_expired(struct fuse_conn *fc, struct list_head *list)
+static bool ent_list_request_expired(struct fuse_chan *fch, struct list_head *list)
 {
 	struct fuse_ring_ent *ent;
 	struct fuse_req *req;
@@ -154,12 +154,12 @@ static bool ent_list_request_expired(struct fuse_conn *fc, struct list_head *lis
 	req = ent->fuse_req;
 
 	return time_is_before_jiffies(req->create_time +
-				      fc->timeout.req_timeout);
+				      fch->timeout.req_timeout);
 }
 
-bool fuse_uring_request_expired(struct fuse_conn *fc)
+bool fuse_uring_request_expired(struct fuse_chan *fch)
 {
-	struct fuse_ring *ring = fc->ring;
+	struct fuse_ring *ring = fch->ring;
 	struct fuse_ring_queue *queue;
 	int qid;
 
@@ -172,10 +172,10 @@ bool fuse_uring_request_expired(struct fuse_conn *fc)
 			continue;
 
 		spin_lock(&queue->lock);
-		if (fuse_request_expired(fc, &queue->fuse_req_queue) ||
-		    fuse_request_expired(fc, &queue->fuse_req_bg_queue) ||
-		    ent_list_request_expired(fc, &queue->ent_w_req_queue) ||
-		    ent_list_request_expired(fc, &queue->ent_in_userspace)) {
+		if (fuse_request_expired(fch, &queue->fuse_req_queue) ||
+		    fuse_request_expired(fch, &queue->fuse_req_bg_queue) ||
+		    ent_list_request_expired(fch, &queue->ent_w_req_queue) ||
+		    ent_list_request_expired(fch, &queue->ent_in_userspace)) {
 			spin_unlock(&queue->lock);
 			return true;
 		}
@@ -185,9 +185,9 @@ bool fuse_uring_request_expired(struct fuse_conn *fc)
 	return false;
 }
 
-void fuse_uring_destruct(struct fuse_conn *fc)
+void fuse_uring_destruct(struct fuse_chan *fch)
 {
-	struct fuse_ring *ring = fc->ring;
+	struct fuse_ring *ring = fch->ring;
 	int qid;
 
 	if (!ring)
@@ -218,20 +218,20 @@ void fuse_uring_destruct(struct fuse_conn *fc)
 
 	kfree(ring->queues);
 	kfree(ring);
-	fc->ring = NULL;
+	fch->ring = NULL;
 }
 
 /*
  * Basic ring setup for this connection based on the provided configuration
  */
-static struct fuse_ring *fuse_uring_create(struct fuse_conn *fc)
+static struct fuse_ring *fuse_uring_create(struct fuse_chan *fch)
 {
 	struct fuse_ring *ring;
 	size_t nr_queues = num_possible_cpus();
 	struct fuse_ring *res = NULL;
 	size_t max_payload_size;
 
-	ring = kzalloc_obj(*fc->ring, GFP_KERNEL_ACCOUNT);
+	ring = kzalloc_obj(*ring, GFP_KERNEL_ACCOUNT);
 	if (!ring)
 		return NULL;
 
@@ -240,25 +240,25 @@ static struct fuse_ring *fuse_uring_create(struct fuse_conn *fc)
 	if (!ring->queues)
 		goto out_err;
 
-	max_payload_size = max(FUSE_MIN_READ_BUFFER, fc->max_write);
-	max_payload_size = max(max_payload_size, fc->max_pages * PAGE_SIZE);
+	max_payload_size = max(FUSE_MIN_READ_BUFFER, fch->max_write);
+	max_payload_size = max(max_payload_size, fch->max_pages * PAGE_SIZE);
 
-	spin_lock(&fc->lock);
-	if (fc->ring) {
+	spin_lock(&fch->lock);
+	if (fch->ring) {
 		/* race, another thread created the ring in the meantime */
-		spin_unlock(&fc->lock);
-		res = fc->ring;
+		spin_unlock(&fch->lock);
+		res = fch->ring;
 		goto out_err;
 	}
 
 	init_waitqueue_head(&ring->stop_waitq);
 
 	ring->nr_queues = nr_queues;
-	ring->fc = fc;
+	ring->chan = fch;
 	ring->max_payload_sz = max_payload_size;
-	smp_store_release(&fc->ring, ring);
+	smp_store_release(&fch->ring, ring);
 
-	spin_unlock(&fc->lock);
+	spin_unlock(&fch->lock);
 	return ring;
 
 out_err:
@@ -270,14 +270,14 @@ static struct fuse_ring *fuse_uring_create(struct fuse_conn *fc)
 static struct fuse_ring_queue *fuse_uring_create_queue(struct fuse_ring *ring,
 						       int qid)
 {
-	struct fuse_conn *fc = ring->fc;
+	struct fuse_chan *fch = ring->chan;
 	struct fuse_ring_queue *queue;
 	struct list_head *pq;
 
 	queue = kzalloc_obj(*queue, GFP_KERNEL_ACCOUNT);
 	if (!queue)
 		return NULL;
-	pq = kzalloc_objs(struct list_head, FUSE_PQ_HASH_SIZE);
+	pq = fuse_pqueue_alloc();
 	if (!pq) {
 		kfree(queue);
 		return NULL;
@@ -295,12 +295,12 @@ static struct fuse_ring_queue *fuse_uring_create_queue(struct fuse_ring *ring,
 	INIT_LIST_HEAD(&queue->fuse_req_bg_queue);
 	INIT_LIST_HEAD(&queue->ent_released);
 
-	queue->fpq.processing = pq;
 	fuse_pqueue_init(&queue->fpq);
+	queue->fpq.processing = pq;
 
-	spin_lock(&fc->lock);
+	spin_lock(&fch->lock);
 	if (ring->queues[qid]) {
-		spin_unlock(&fc->lock);
+		spin_unlock(&fch->lock);
 		kfree(queue->fpq.processing);
 		kfree(queue);
 		return ring->queues[qid];
@@ -310,7 +310,7 @@ static struct fuse_ring_queue *fuse_uring_create_queue(struct fuse_ring *ring,
 	 * write_once and lock as the caller mostly doesn't take the lock at all
 	 */
 	WRITE_ONCE(ring->queues[qid], queue);
-	spin_unlock(&fc->lock);
+	spin_unlock(&fch->lock);
 
 	return queue;
 }
@@ -531,8 +531,7 @@ static void fuse_uring_prepare_cancel(struct io_uring_cmd *cmd, int issue_flags,
  * Checks for errors and stores it into the request
  */
 static int fuse_uring_out_header_has_err(struct fuse_out_header *oh,
-					 struct fuse_req *req,
-					 struct fuse_conn *fc)
+					 struct fuse_req *req)
 {
 	int err;
 
@@ -812,7 +811,6 @@ static void fuse_uring_commit(struct fuse_ring_ent *ent, struct fuse_req *req,
 			      unsigned int issue_flags)
 {
 	struct fuse_ring *ring = ent->queue->ring;
-	struct fuse_conn *fc = ring->fc;
 	ssize_t err = 0;
 
 	err = copy_from_user(&req->out.h, &ent->headers->in_out,
@@ -822,7 +820,7 @@ static void fuse_uring_commit(struct fuse_ring_ent *ent, struct fuse_req *req,
 		goto out;
 	}
 
-	err = fuse_uring_out_header_has_err(&req->out.h, req, fc);
+	err = fuse_uring_out_header_has_err(&req->out.h, req);
 	if (err) {
 		/* req->out.h.error already set */
 		goto out;
@@ -873,13 +871,13 @@ static int fuse_ring_ent_set_commit(struct fuse_ring_ent *ent)
 
 /* FUSE_URING_CMD_COMMIT_AND_FETCH handler */
 static int fuse_uring_commit_fetch(struct io_uring_cmd *cmd, int issue_flags,
-				   struct fuse_conn *fc)
+				   struct fuse_chan *fch)
 {
 	const struct fuse_uring_cmd_req *cmd_req = io_uring_sqe128_cmd(cmd->sqe,
 								       struct fuse_uring_cmd_req);
 	struct fuse_ring_ent *ent;
 	int err;
-	struct fuse_ring *ring = fc->ring;
+	struct fuse_ring *ring = fch->ring;
 	struct fuse_ring_queue *queue;
 	uint64_t commit_id = READ_ONCE(cmd_req->commit_id);
 	unsigned int qid = READ_ONCE(cmd_req->qid);
@@ -898,7 +896,7 @@ static int fuse_uring_commit_fetch(struct io_uring_cmd *cmd, int issue_flags,
 		return err;
 	fpq = &queue->fpq;
 
-	if (!READ_ONCE(fc->connected) || READ_ONCE(queue->stopped))
+	if (!READ_ONCE(fch->connected) || READ_ONCE(queue->stopped))
 		return err;
 
 	spin_lock(&queue->lock);
@@ -981,8 +979,8 @@ static void fuse_uring_do_register(struct fuse_ring_ent *ent,
 {
 	struct fuse_ring_queue *queue = ent->queue;
 	struct fuse_ring *ring = queue->ring;
-	struct fuse_conn *fc = ring->fc;
-	struct fuse_iqueue *fiq = &fc->iq;
+	struct fuse_chan *fch = ring->chan;
+	struct fuse_iqueue *fiq = &fch->iq;
 
 	fuse_uring_prepare_cancel(cmd, issue_flags, ent);
 
@@ -997,7 +995,7 @@ static void fuse_uring_do_register(struct fuse_ring_ent *ent,
 		if (ready) {
 			WRITE_ONCE(fiq->ops, &fuse_io_uring_ops);
 			WRITE_ONCE(ring->ready, true);
-			wake_up_all(&fc->blocked_waitq);
+			wake_up_all(&fch->blocked_waitq);
 		}
 	}
 }
@@ -1078,11 +1076,11 @@ fuse_uring_create_ring_ent(struct io_uring_cmd *cmd,
  * entry as "ready to get fuse requests" on the queue
  */
 static int fuse_uring_register(struct io_uring_cmd *cmd,
-			       unsigned int issue_flags, struct fuse_conn *fc)
+			       unsigned int issue_flags, struct fuse_chan *fch)
 {
 	const struct fuse_uring_cmd_req *cmd_req = io_uring_sqe128_cmd(cmd->sqe,
 								       struct fuse_uring_cmd_req);
-	struct fuse_ring *ring = smp_load_acquire(&fc->ring);
+	struct fuse_ring *ring = smp_load_acquire(&fch->ring);
 	struct fuse_ring_queue *queue;
 	struct fuse_ring_ent *ent;
 	int err;
@@ -1090,7 +1088,7 @@ static int fuse_uring_register(struct io_uring_cmd *cmd,
 
 	err = -ENOMEM;
 	if (!ring) {
-		ring = fuse_uring_create(fc);
+		ring = fuse_uring_create(fch);
 		if (!ring)
 			return err;
 	}
@@ -1128,7 +1126,7 @@ static int fuse_uring_register(struct io_uring_cmd *cmd,
 int fuse_uring_cmd(struct io_uring_cmd *cmd, unsigned int issue_flags)
 {
 	struct fuse_dev *fud;
-	struct fuse_conn *fc;
+	struct fuse_chan *fch;
 	u32 cmd_op = cmd->cmd_op;
 	int err;
 
@@ -1146,39 +1144,39 @@ int fuse_uring_cmd(struct io_uring_cmd *cmd, unsigned int issue_flags)
 		pr_info_ratelimited("No fuse device found\n");
 		return PTR_ERR(fud);
 	}
-	fc = fud->fc;
+	fch = fud->chan;
 
 	/* Once a connection has io-uring enabled on it, it can't be disabled */
-	if (!enable_uring && !fc->io_uring) {
+	if (!enable_uring && !fch->io_uring) {
 		pr_info_ratelimited("fuse-io-uring is disabled\n");
 		return -EOPNOTSUPP;
 	}
 
-	if (fc->aborted)
+	if (fch->abort_with_err)
 		return -ECONNABORTED;
-	if (!fc->connected)
+	if (!fch->connected)
 		return -ENOTCONN;
 
 	/*
 	 * fuse_uring_register() needs the ring to be initialized,
 	 * we need to know the max payload size
 	 */
-	if (!fc->initialized)
+	if (!fch->initialized)
 		return -EAGAIN;
 
 	switch (cmd_op) {
 	case FUSE_IO_URING_CMD_REGISTER:
-		err = fuse_uring_register(cmd, issue_flags, fc);
+		err = fuse_uring_register(cmd, issue_flags, fch);
 		if (err) {
 			pr_info_once("FUSE_IO_URING_CMD_REGISTER failed err=%d\n",
 				     err);
-			fc->io_uring = 0;
-			wake_up_all(&fc->blocked_waitq);
+			fch->io_uring = 0;
+			wake_up_all(&fch->blocked_waitq);
 			return err;
 		}
 		break;
 	case FUSE_IO_URING_CMD_COMMIT_AND_FETCH:
-		err = fuse_uring_commit_fetch(cmd, issue_flags, fc);
+		err = fuse_uring_commit_fetch(cmd, issue_flags, fch);
 		if (err) {
 			pr_info_once("FUSE_IO_URING_COMMIT_AND_FETCH failed err=%d\n",
 				     err);
@@ -1261,8 +1259,7 @@ static void fuse_uring_dispatch_ent(struct fuse_ring_ent *ent)
 /* queue a fuse request and send it if a ring entry is available */
 void fuse_uring_queue_fuse_req(struct fuse_iqueue *fiq, struct fuse_req *req)
 {
-	struct fuse_conn *fc = req->fm->fc;
-	struct fuse_ring *ring = fc->ring;
+	struct fuse_ring *ring = req->chan->ring;
 	struct fuse_ring_queue *queue;
 	struct fuse_ring_ent *ent = NULL;
 	int err;
@@ -1304,8 +1301,8 @@ void fuse_uring_queue_fuse_req(struct fuse_iqueue *fiq, struct fuse_req *req)
 
 bool fuse_uring_queue_bq_req(struct fuse_req *req)
 {
-	struct fuse_conn *fc = req->fm->fc;
-	struct fuse_ring *ring = fc->ring;
+	struct fuse_chan *fch = req->chan;
+	struct fuse_ring *ring = fch->ring;
 	struct fuse_ring_queue *queue;
 	struct fuse_ring_ent *ent = NULL;
 
@@ -1325,12 +1322,12 @@ bool fuse_uring_queue_bq_req(struct fuse_req *req)
 
 	ent = list_first_entry_or_null(&queue->ent_avail_queue,
 				       struct fuse_ring_ent, list);
-	spin_lock(&fc->bg_lock);
-	fc->num_background++;
-	if (fc->num_background == fc->max_background)
-		fc->blocked = 1;
+	spin_lock(&fch->bg_lock);
+	fch->num_background++;
+	if (fch->num_background == fch->max_background)
+		fch->blocked = 1;
 	fuse_uring_flush_bg(queue);
-	spin_unlock(&fc->bg_lock);
+	spin_unlock(&fch->bg_lock);
 
 	/*
 	 * Due to bg_queue flush limits there might be other bg requests
diff --git a/fs/fuse/dev_uring_i.h b/fs/fuse/dev_uring_i.h
index 51a563922ce1..368f4d0790eb 100644
--- a/fs/fuse/dev_uring_i.h
+++ b/fs/fuse/dev_uring_i.h
@@ -7,7 +7,7 @@
 #ifndef _FS_FUSE_DEV_URING_I_H
 #define _FS_FUSE_DEV_URING_I_H
 
-#include "fuse_i.h"
+#include "fuse_dev_i.h"
 
 #ifdef CONFIG_FUSE_IO_URING
 
@@ -101,13 +101,13 @@ struct fuse_ring_queue {
 	bool stopped;
 };
 
-/**
+/*
  * Describes if uring is for communication and holds alls the data needed
  * for uring communication
  */
 struct fuse_ring {
 	/* back pointer */
-	struct fuse_conn *fc;
+	struct fuse_chan *chan;
 
 	/* number of ring queues */
 	size_t nr_queues;
@@ -135,19 +135,17 @@ struct fuse_ring {
 	bool ready;
 };
 
-bool fuse_uring_enabled(void);
-void fuse_uring_destruct(struct fuse_conn *fc);
 void fuse_uring_stop_queues(struct fuse_ring *ring);
 void fuse_uring_abort_end_requests(struct fuse_ring *ring);
 int fuse_uring_cmd(struct io_uring_cmd *cmd, unsigned int issue_flags);
 void fuse_uring_queue_fuse_req(struct fuse_iqueue *fiq, struct fuse_req *req);
 bool fuse_uring_queue_bq_req(struct fuse_req *req);
 bool fuse_uring_remove_pending_req(struct fuse_req *req);
-bool fuse_uring_request_expired(struct fuse_conn *fc);
+bool fuse_uring_request_expired(struct fuse_chan *fch);
 
-static inline void fuse_uring_abort(struct fuse_conn *fc)
+static inline void fuse_uring_abort(struct fuse_chan *fch)
 {
-	struct fuse_ring *ring = fc->ring;
+	struct fuse_ring *ring = fch->ring;
 
 	if (ring == NULL)
 		return;
@@ -158,40 +156,31 @@ static inline void fuse_uring_abort(struct fuse_conn *fc)
 	}
 }
 
-static inline void fuse_uring_wait_stopped_queues(struct fuse_conn *fc)
+static inline void fuse_uring_wait_stopped_queues(struct fuse_chan *fch)
 {
-	struct fuse_ring *ring = fc->ring;
+	struct fuse_ring *ring = fch->ring;
 
 	if (ring)
 		wait_event(ring->stop_waitq,
 			   atomic_read(&ring->queue_refs) == 0);
 }
 
-static inline bool fuse_uring_ready(struct fuse_conn *fc)
+static inline bool fuse_uring_ready(struct fuse_chan *fch)
 {
-	return fc->ring && fc->ring->ready;
+	return fch->ring && fch->ring->ready;
 }
 
 #else /* CONFIG_FUSE_IO_URING */
 
-static inline void fuse_uring_destruct(struct fuse_conn *fc)
+static inline void fuse_uring_abort(struct fuse_chan *fch)
 {
 }
 
-static inline bool fuse_uring_enabled(void)
-{
-	return false;
-}
-
-static inline void fuse_uring_abort(struct fuse_conn *fc)
-{
-}
-
-static inline void fuse_uring_wait_stopped_queues(struct fuse_conn *fc)
+static inline void fuse_uring_wait_stopped_queues(struct fuse_chan *fch)
 {
 }
 
-static inline bool fuse_uring_ready(struct fuse_conn *fc)
+static inline bool fuse_uring_ready(struct fuse_chan *fch)
 {
 	return false;
 }
@@ -201,7 +190,7 @@ static inline bool fuse_uring_remove_pending_req(struct fuse_req *req)
 	return false;
 }
 
-static inline bool fuse_uring_request_expired(struct fuse_conn *fc)
+static inline bool fuse_uring_request_expired(struct fuse_chan *fch)
 {
 	return false;
 }
diff --git a/fs/fuse/dir.c b/fs/fuse/dir.c
index b658b6baf72f..be41c14ef329 100644
--- a/fs/fuse/dir.c
+++ b/fs/fuse/dir.c
@@ -6,6 +6,7 @@
   See the file COPYING.
 */
 
+#include "dev.h"
 #include "fuse_i.h"
 
 #include <linux/pagemap.h>
@@ -317,7 +318,7 @@ void fuse_invalidate_attr(struct inode *inode)
 
 static void fuse_dir_changed(struct inode *dir)
 {
-	fuse_invalidate_attr(dir);
+	fuse_invalidate_attr_mask(dir, FUSE_STATX_MODDIR);
 	inode_maybe_inc_iversion(dir, false);
 }
 
@@ -430,7 +431,7 @@ static int fuse_dentry_revalidate(struct inode *dir, const struct qstr *name,
 			fi = get_fuse_inode(inode);
 			if (outarg.nodeid != get_node_id(inode) ||
 			    (bool) IS_AUTOMOUNT(inode) != (bool) (outarg.attr.flags & FUSE_ATTR_SUBMOUNT)) {
-				fuse_queue_forget(fm->fc, forget,
+				fuse_chan_queue_forget(fm->fc->chan, forget,
 						  outarg.nodeid, 1);
 				goto invalid;
 			}
@@ -593,7 +594,7 @@ int fuse_lookup_name(struct super_block *sb, u64 nodeid, const struct qstr *name
 			   attr_version, evict_ctr);
 	err = -ENOMEM;
 	if (!*inode) {
-		fuse_queue_forget(fm->fc, forget, outarg->nodeid, 1);
+		fuse_chan_queue_forget(fm->fc->chan, forget, outarg->nodeid, 1);
 		goto out;
 	}
 	err = 0;
@@ -837,7 +838,6 @@ static int fuse_create_open(struct mnt_idmap *idmap, struct inode *dir,
 	if (!forget)
 		goto out_err;
 
-	err = -ENOMEM;
 	ff = fuse_file_alloc(fm, true);
 	if (!ff)
 		goto out_put_forget_req;
@@ -894,7 +894,7 @@ static int fuse_create_open(struct mnt_idmap *idmap, struct inode *dir,
 	if (!inode) {
 		flags &= ~(O_CREAT | O_EXCL | O_TRUNC);
 		fuse_sync_release(NULL, ff, flags);
-		fuse_queue_forget(fm->fc, forget, outentry.nodeid, 1);
+		fuse_chan_queue_forget(fm->fc->chan, forget, outentry.nodeid, 1);
 		err = -ENOMEM;
 		goto out_err;
 	}
@@ -1019,7 +1019,7 @@ static struct dentry *create_new_entry(struct mnt_idmap *idmap, struct fuse_moun
 	inode = fuse_iget(dir->i_sb, outarg.nodeid, outarg.generation,
 			  &outarg.attr, ATTR_TIMEOUT(&outarg), 0, 0);
 	if (!inode) {
-		fuse_queue_forget(fm->fc, forget, outarg.nodeid, 1);
+		fuse_chan_queue_forget(fm->fc->chan, forget, outarg.nodeid, 1);
 		return ERR_PTR(-ENOMEM);
 	}
 	kfree(forget);
diff --git a/fs/fuse/file.c b/fs/fuse/file.c
index c59452d60b8d..3bdab8d03373 100644
--- a/fs/fuse/file.c
+++ b/fs/fuse/file.c
@@ -7,6 +7,7 @@
 */
 
 #include "fuse_i.h"
+#include "dev.h"
 
 #include <linux/pagemap.h>
 #include <linux/slab.h>
@@ -91,8 +92,7 @@ static struct fuse_file *fuse_file_get(struct fuse_file *ff)
 	return ff;
 }
 
-static void fuse_release_end(struct fuse_mount *fm, struct fuse_args *args,
-			     int error)
+static void fuse_release_end(struct fuse_args *args, int error)
 {
 	struct fuse_release_args *ra = container_of(args, typeof(*ra), args);
 
@@ -112,10 +112,10 @@ static void fuse_file_put(struct fuse_file *ff, bool sync)
 		if (!args) {
 			/* Do nothing when server does not implement 'opendir' */
 		} else if (args->opcode == FUSE_RELEASE && ff->fm->fc->no_open) {
-			fuse_release_end(ff->fm, args, 0);
+			fuse_release_end(args, 0);
 		} else if (sync) {
 			fuse_simple_request(ff->fm, args);
-			fuse_release_end(ff->fm, args, 0);
+			fuse_release_end(args, 0);
 		} else {
 			/*
 			 * DAX inodes may need to issue a number of synchronous
@@ -126,7 +126,7 @@ static void fuse_file_put(struct fuse_file *ff, bool sync)
 			args->end = fuse_release_end;
 			if (fuse_simple_background(ff->fm, args,
 						   GFP_KERNEL | __GFP_NOFAIL))
-				fuse_release_end(ff->fm, args, -ENOTCONN);
+				fuse_release_end(args, -ENOTCONN);
 		}
 		kfree(ff);
 	}
@@ -709,8 +709,7 @@ static void fuse_io_free(struct fuse_io_args *ia)
 	kfree(ia);
 }
 
-static void fuse_aio_complete_req(struct fuse_mount *fm, struct fuse_args *args,
-				  int err)
+static void fuse_aio_complete_req(struct fuse_args *args, int err)
 {
 	struct fuse_io_args *ia = container_of(args, typeof(*ia), ap.args);
 	struct fuse_io_priv *io = ia->io;
@@ -758,7 +757,7 @@ static ssize_t fuse_async_req_send(struct fuse_mount *fm,
 	ia->ap.args.may_block = io->should_dirty;
 	err = fuse_simple_background(fm, &ia->ap.args, GFP_KERNEL);
 	if (err)
-		fuse_aio_complete_req(fm, &ia->ap.args, err);
+		fuse_aio_complete_req(&ia->ap.args, err);
 
 	return num_bytes;
 }
@@ -902,7 +901,7 @@ static int fuse_handle_readahead(struct folio *folio,
 		ia = NULL;
 	}
 	if (!ia) {
-		if (fc->num_background >= fc->congestion_threshold &&
+		if (fuse_chan_num_background(fc->chan) >= fc->congestion_threshold &&
 		    rac->ra->async_size >= readahead_count(rac))
 			/*
 			 * Congested and only async pages left, so skip the
@@ -1001,8 +1000,7 @@ static int fuse_iomap_read_folio_range(const struct iomap_iter *iter,
 	return fuse_do_readfolio(file, folio, off, len);
 }
 
-static void fuse_readpages_end(struct fuse_mount *fm, struct fuse_args *args,
-			       int err)
+static void fuse_readpages_end(struct fuse_args *args, int err)
 {
 	int i;
 	struct fuse_io_args *ia = container_of(args, typeof(*ia), ap.args);
@@ -1068,7 +1066,7 @@ static void fuse_send_readpages(struct fuse_io_args *ia, struct file *file,
 		res = fuse_simple_request(fm, &ap->args);
 		err = res < 0 ? res : 0;
 	}
-	fuse_readpages_end(fm, &ap->args, err);
+	fuse_readpages_end(&ap->args, err);
 }
 
 static void fuse_readahead(struct readahead_control *rac)
@@ -1985,8 +1983,7 @@ __acquires(fi->lock)
 	}
 }
 
-static void fuse_writepage_end(struct fuse_mount *fm, struct fuse_args *args,
-			       int error)
+static void fuse_writepage_end(struct fuse_args *args, int error)
 {
 	struct fuse_writepage_args *wpa =
 		container_of(args, typeof(*wpa), ia.ap.args);
@@ -2294,7 +2291,7 @@ static int fuse_writepages(struct address_space *mapping,
 		return -EIO;
 
 	if (wbc->sync_mode == WB_SYNC_NONE &&
-	    fc->num_background >= fc->congestion_threshold)
+	    fuse_chan_num_background(fc->chan) >= fc->congestion_threshold)
 		return 0;
 
 	return iomap_writepages(&wpc);
@@ -2680,125 +2677,6 @@ static loff_t fuse_file_llseek(struct file *file, loff_t offset, int whence)
 	return retval;
 }
 
-/*
- * All files which have been polled are linked to RB tree
- * fuse_conn->polled_files which is indexed by kh.  Walk the tree and
- * find the matching one.
- */
-static struct rb_node **fuse_find_polled_node(struct fuse_conn *fc, u64 kh,
-					      struct rb_node **parent_out)
-{
-	struct rb_node **link = &fc->polled_files.rb_node;
-	struct rb_node *last = NULL;
-
-	while (*link) {
-		struct fuse_file *ff;
-
-		last = *link;
-		ff = rb_entry(last, struct fuse_file, polled_node);
-
-		if (kh < ff->kh)
-			link = &last->rb_left;
-		else if (kh > ff->kh)
-			link = &last->rb_right;
-		else
-			return link;
-	}
-
-	if (parent_out)
-		*parent_out = last;
-	return link;
-}
-
-/*
- * The file is about to be polled.  Make sure it's on the polled_files
- * RB tree.  Note that files once added to the polled_files tree are
- * not removed before the file is released.  This is because a file
- * polled once is likely to be polled again.
- */
-static void fuse_register_polled_file(struct fuse_conn *fc,
-				      struct fuse_file *ff)
-{
-	spin_lock(&fc->lock);
-	if (RB_EMPTY_NODE(&ff->polled_node)) {
-		struct rb_node **link, *parent;
-
-		link = fuse_find_polled_node(fc, ff->kh, &parent);
-		BUG_ON(*link);
-		rb_link_node(&ff->polled_node, parent, link);
-		rb_insert_color(&ff->polled_node, &fc->polled_files);
-	}
-	spin_unlock(&fc->lock);
-}
-
-__poll_t fuse_file_poll(struct file *file, poll_table *wait)
-{
-	struct fuse_file *ff = file->private_data;
-	struct fuse_mount *fm = ff->fm;
-	struct fuse_poll_in inarg = { .fh = ff->fh, .kh = ff->kh };
-	struct fuse_poll_out outarg;
-	FUSE_ARGS(args);
-	int err;
-
-	if (fm->fc->no_poll)
-		return DEFAULT_POLLMASK;
-
-	poll_wait(file, &ff->poll_wait, wait);
-	inarg.events = mangle_poll(poll_requested_events(wait));
-
-	/*
-	 * Ask for notification iff there's someone waiting for it.
-	 * The client may ignore the flag and always notify.
-	 */
-	if (waitqueue_active(&ff->poll_wait)) {
-		inarg.flags |= FUSE_POLL_SCHEDULE_NOTIFY;
-		fuse_register_polled_file(fm->fc, ff);
-	}
-
-	args.opcode = FUSE_POLL;
-	args.nodeid = ff->nodeid;
-	args.in_numargs = 1;
-	args.in_args[0].size = sizeof(inarg);
-	args.in_args[0].value = &inarg;
-	args.out_numargs = 1;
-	args.out_args[0].size = sizeof(outarg);
-	args.out_args[0].value = &outarg;
-	err = fuse_simple_request(fm, &args);
-
-	if (!err)
-		return demangle_poll(outarg.revents);
-	if (err == -ENOSYS) {
-		fm->fc->no_poll = 1;
-		return DEFAULT_POLLMASK;
-	}
-	return EPOLLERR;
-}
-EXPORT_SYMBOL_GPL(fuse_file_poll);
-
-/*
- * This is called from fuse_handle_notify() on FUSE_NOTIFY_POLL and
- * wakes up the poll waiters.
- */
-int fuse_notify_poll_wakeup(struct fuse_conn *fc,
-			    struct fuse_notify_poll_wakeup_out *outarg)
-{
-	u64 kh = outarg->kh;
-	struct rb_node **link;
-
-	spin_lock(&fc->lock);
-
-	link = fuse_find_polled_node(fc, kh, NULL);
-	if (*link) {
-		struct fuse_file *ff;
-
-		ff = rb_entry(*link, struct fuse_file, polled_node);
-		wake_up_interruptible_sync(&ff->poll_wait);
-	}
-
-	spin_unlock(&fc->lock);
-	return 0;
-}
-
 static void fuse_do_truncate(struct file *file)
 {
 	struct inode *inode = file->f_mapping->host;
diff --git a/fs/fuse/fuse_dev_i.h b/fs/fuse/fuse_dev_i.h
index 910f883cd090..9ce987826ded 100644
--- a/fs/fuse/fuse_dev_i.h
+++ b/fs/fuse/fuse_dev_i.h
@@ -6,20 +6,311 @@
 #ifndef _FS_FUSE_DEV_I_H
 #define _FS_FUSE_DEV_I_H
 
+#include <linux/fuse.h>
 #include <linux/types.h>
+#include <linux/refcount.h>
+#include <linux/wait.h>
+#include <linux/workqueue.h>
+#include <linux/fs.h>
 
 /* Ordinary requests have even IDs, while interrupts IDs are odd */
 #define FUSE_INT_REQ_BIT (1ULL << 0)
 #define FUSE_REQ_ID_STEP (1ULL << 1)
 
-extern struct wait_queue_head fuse_dev_waitq;
-
 struct fuse_arg;
 struct fuse_args;
 struct fuse_pqueue;
-struct fuse_req;
 struct fuse_iqueue;
-struct fuse_forget_link;
+
+/**
+ * enum fuse_req_flag - Request flags
+ *
+ * @FR_ISREPLY:		set if the request has reply
+ * @FR_FORCE:		force sending of the request even if interrupted
+ * @FR_BACKGROUND:	request is sent in the background
+ * @FR_WAITING:		request is counted as "waiting"
+ * @FR_ABORTED:		the request was aborted
+ * @FR_INTERRUPTED:	the request has been interrupted
+ * @FR_LOCKED:		data is being copied to/from the request
+ * @FR_PENDING:		request is not yet in userspace
+ * @FR_SENT:		request is in userspace, waiting for an answer
+ * @FR_FINISHED:	request is finished
+ * @FR_PRIVATE:		request is on private list
+ * @FR_ASYNC:		request is asynchronous
+ * @FR_URING:		request is handled through fuse-io-uring
+ */
+enum fuse_req_flag {
+	FR_ISREPLY,
+	FR_FORCE,
+	FR_BACKGROUND,
+	FR_WAITING,
+	FR_ABORTED,
+	FR_INTERRUPTED,
+	FR_LOCKED,
+	FR_PENDING,
+	FR_SENT,
+	FR_FINISHED,
+	FR_PRIVATE,
+	FR_ASYNC,
+	FR_URING,
+};
+
+/**
+ * struct fuse_req - A request to the client
+ *
+ * .waitq.lock protects the following fields:
+ *   - FR_ABORTED
+ *   - FR_LOCKED (may also be modified under fpq->lock, tested under both)
+ */
+struct fuse_req {
+	/**
+	 * @list: This can be on either pending processing or io lists in
+	 * fuse_conn
+	 */
+	struct list_head list;
+
+	/** @intr_entry: Entry on the interrupts list  */
+	struct list_head intr_entry;
+
+	/** @args: Input/output arguments */
+	struct fuse_args *args;
+
+	/** @count: refcount */
+	refcount_t count;
+
+	/** @flags: Request flags, updated with test/set/clear_bit() */
+	unsigned long flags;
+
+	/** @in: The request input header */
+	struct {
+		/** @in.h: The request input header */
+		struct fuse_in_header h;
+	} in;
+
+	/** @out: The request output header */
+	struct {
+		/** @out.h: The request output header */
+		struct fuse_out_header h;
+	} out;
+
+	/** @waitq: Used to wake up the task waiting for completion of request */
+	wait_queue_head_t waitq;
+
+#if IS_ENABLED(CONFIG_VIRTIO_FS)
+	/**
+	 * @argbuf: virtio-fs's physically contiguous buffer for in and out
+	 * args
+	 */
+	void *argbuf;
+#endif
+
+	/** @chan: fuse_chan this request belongs to */
+	struct fuse_chan *chan;
+
+#ifdef CONFIG_FUSE_IO_URING
+	void *ring_entry;
+	void *ring_queue;
+#endif
+	/** @create_time: When (in jiffies) the request was created */
+	unsigned long create_time;
+};
+
+/* One forget request */
+struct fuse_forget_link {
+	struct fuse_forget_one forget_one;
+	struct fuse_forget_link *next;
+};
+
+/**
+ * struct fuse_iqueue_ops - Input queue callbacks
+ *
+ * Input queue signalling is device-specific.  For example, the /dev/fuse file
+ * uses fiq->waitq and fasync to wake processes that are waiting on queue
+ * readiness.  These callbacks allow other device types to respond to input
+ * queue activity.
+ */
+struct fuse_iqueue_ops {
+	/**
+	 * @send_forget: Send one forget
+	 */
+	void (*send_forget)(struct fuse_iqueue *fiq, struct fuse_forget_link *link);
+
+	/**
+	 * @send_interrupt: Send interrupt for request
+	 */
+	void (*send_interrupt)(struct fuse_iqueue *fiq, struct fuse_req *req);
+
+	/**
+	 * @send_req: Send one request
+	 */
+	void (*send_req)(struct fuse_iqueue *fiq, struct fuse_req *req);
+
+	/**
+	 * @release: Clean up when fuse_iqueue is destroyed
+	 */
+	void (*release)(struct fuse_iqueue *fiq);
+};
+
+struct fuse_iqueue {
+	/** Connection established */
+	unsigned connected;
+
+	/** Lock protecting accesses to members of this structure */
+	spinlock_t lock;
+
+	/** Readers of the connection are waiting on this */
+	wait_queue_head_t waitq;
+
+	/** The next unique request id */
+	u64 reqctr;
+
+	/** The list of pending requests */
+	struct list_head pending;
+
+	/** Pending interrupts */
+	struct list_head interrupts;
+
+	/** Queue of pending forgets */
+	struct fuse_forget_link forget_list_head;
+	struct fuse_forget_link *forget_list_tail;
+
+	/** Batching of FORGET requests (positive indicates FORGET batch) */
+	int forget_batch;
+
+	/** O_ASYNC requests */
+	struct fasync_struct *fasync;
+
+	/** Device-specific callbacks */
+	const struct fuse_iqueue_ops *ops;
+
+	/** Device-specific state */
+	void *priv;
+};
+
+struct fuse_chan {
+	/** Lock protecting:
+	    - devices
+	    - connected
+	    - ring
+	    - ring->queues[qid]
+	 */
+	spinlock_t lock;
+
+	/* back pointer: fc->chan->conn == fc */
+	struct fuse_conn *conn;
+
+	/** Input queue */
+	struct fuse_iqueue iq;
+
+	/** List of device instances belonging to this connection */
+	struct list_head devices;
+
+	/** Maximum number of outstanding background requests */
+	unsigned max_background;
+
+	/** Number of requests currently in the background */
+	unsigned num_background;
+
+	/** Number of background requests currently queued for userspace */
+	unsigned active_background;
+
+	/** The list of background requests set aside for later queuing */
+	struct list_head bg_queue;
+
+	/** Protects: max_background, num_background, active_background, bg_queue, blocked */
+	spinlock_t bg_lock;
+
+	/** Flag indicating that INIT reply has been received. Allocating
+	 * any fuse request will be suspended until the flag is set */
+	int initialized;
+
+	/** Flag indicating if connection is blocked.  This will be
+	    the case before the INIT reply is received, and if there
+	    are too many outstading backgrounds requests */
+	int blocked;
+
+	/** waitq for blocked connection */
+	wait_queue_head_t blocked_waitq;
+
+	/** Connection established, cleared on umount, connection
+	    abort and device release */
+	unsigned connected;
+
+	/** The number of requests waiting for completion */
+	atomic_t num_waiting;
+
+	/** Is interrupt not implemented by fs? */
+	bool no_interrupt;
+
+	/* Use io_uring for communication */
+	unsigned int io_uring;
+
+	/* Negotiated minor version */
+	unsigned int minor;
+
+	/* Maximum write size */
+	unsigned int max_write;
+
+	/* Maximum number of pages that can be used in a single request */
+	unsigned int max_pages;
+
+	/* Before being installed into fud, contains the preallocated pq array*/
+	struct list_head *pq_prealloc;
+
+	/** Connection aborted via sysfs, respond with ECONNABORTED on device I/O */
+	bool abort_with_err;
+
+#ifdef CONFIG_FUSE_IO_URING
+	/**  uring connection information*/
+	struct fuse_ring *ring;
+#endif
+
+	/** Only used if the connection opts into request timeouts */
+	struct {
+		/* Worker for checking if any requests have timed out */
+		struct delayed_work work;
+
+		/* Request timeout (in jiffies). 0 = no timeout */
+		unsigned int req_timeout;
+	} timeout;
+};
+
+#define FUSE_PQ_HASH_BITS 8
+#define FUSE_PQ_HASH_SIZE (1 << FUSE_PQ_HASH_BITS)
+
+struct fuse_pqueue {
+	/** Connection established */
+	unsigned connected;
+
+	/** Lock protecting accessess to  members of this structure */
+	spinlock_t lock;
+
+	/** Hash table of requests being processed */
+	struct list_head *processing;
+
+	/** The list of requests under I/O */
+	struct list_head io;
+};
+
+/**
+ * struct fuse_dev - Fuse device instance
+ */
+struct fuse_dev {
+	/** @ref: Reference count of this object */
+	refcount_t ref;
+
+	/** @sync_init: Issue FUSE_INIT synchronously */
+	bool sync_init;
+
+	/** @chan: Fuse channel for this device */
+	struct fuse_chan *chan;
+
+	/** @pq: Processing queue */
+	struct fuse_pqueue pq;
+
+	/** @entry: list entry on fch->devices */
+	struct list_head entry;
+};
 
 struct fuse_copy_state {
 	struct fuse_req *req;
@@ -39,21 +330,21 @@ struct fuse_copy_state {
 	} ring;
 };
 
-/* fud->fc gets assigned to this value when /dev/fuse is closed */
-#define FUSE_DEV_FC_DISCONNECTED ((struct fuse_conn *) 1)
+/* fud->chan gets assigned to this value when /dev/fuse is closed */
+#define FUSE_DEV_CHAN_DISCONNECTED ((struct fuse_chan *) 1)
 
 /*
- * Lockless access is OK, because fud->fc is set once during mount and is valid
+ * Lockless access is OK, because fud->chan is set once during mount and is valid
  * until the file is released.
  *
- * fud->fc is set to FUSE_DEV_FC_DISCONNECTED only after the containing file is
+ * fud->chan is set to FUSE_DEV_CHAN_DISCONNECTED only after the containing file is
  * released, so result is safe to dereference in most cases.  Exceptions are:
  * fuse_dev_put() and fuse_fill_super_common().
  */
-static inline struct fuse_conn *fuse_dev_fc_get(struct fuse_dev *fud)
+static inline struct fuse_chan *fuse_dev_chan_get(struct fuse_dev *fud)
 {
 	/* Pairs with xchg() in fuse_dev_install() */
-	return smp_load_acquire(&fud->fc);
+	return smp_load_acquire(&fud->chan);
 }
 
 static inline struct fuse_dev *fuse_file_to_fud(struct file *file)
@@ -65,12 +356,14 @@ static inline struct fuse_dev *__fuse_get_dev(struct file *file)
 {
 	struct fuse_dev *fud = fuse_file_to_fud(file);
 
-	if (!fuse_dev_fc_get(fud))
+	if (!fuse_dev_chan_get(fud))
 		return NULL;
 
 	return fud;
 }
 
+void fuse_iqueue_init(struct fuse_iqueue *fiq, const struct fuse_iqueue_ops *ops, void *priv);
+
 struct fuse_dev *fuse_get_dev(struct file *file);
 
 unsigned int fuse_req_hash(u64 unique);
@@ -80,7 +373,11 @@ void fuse_dev_end_requests(struct list_head *head);
 
 void fuse_copy_init(struct fuse_copy_state *cs, bool write,
 			   struct iov_iter *iter);
-void fuse_copy_finish(struct fuse_copy_state *cs);
+/*
+ * Return the number of bytes in an arguments list
+ */
+unsigned int fuse_len_args(unsigned int numargs, struct fuse_arg *args);
+
 int fuse_copy_args(struct fuse_copy_state *cs, unsigned int numargs,
 		   unsigned int argpages, struct fuse_arg *args,
 		   int zeroing);
@@ -91,7 +388,34 @@ void fuse_dev_queue_forget(struct fuse_iqueue *fiq,
 void fuse_dev_queue_interrupt(struct fuse_iqueue *fiq, struct fuse_req *req);
 bool fuse_remove_pending_req(struct fuse_req *req, spinlock_t *lock);
 
-bool fuse_request_expired(struct fuse_conn *fc, struct list_head *list);
+bool fuse_request_expired(struct fuse_chan *fch, struct list_head *list);
+
+/*
+ * Assign a unique id to a fuse request
+ */
+void fuse_request_assign_unique(struct fuse_iqueue *fiq, struct fuse_req *req);
+
+/*
+ * Get the next unique ID for a request
+ */
+u64 fuse_get_unique(struct fuse_iqueue *fiq);
+
+struct fuse_dev *fuse_dev_alloc_install(struct fuse_chan *fch);
+struct fuse_dev *fuse_dev_alloc(void);
+
+int fuse_dev_release(struct inode *inode, struct file *file);
+
+struct list_head *fuse_pqueue_alloc(void);
+
+/*
+ * Initialize the fuse processing queue
+ */
+void fuse_pqueue_init(struct fuse_pqueue *fpq);
+
+/*
+ * End a finished request
+ */
+void fuse_request_end(struct fuse_req *req);
 
 #endif
 
diff --git a/fs/fuse/fuse_i.h b/fs/fuse/fuse_i.h
index 17423d4e3cfa..3a7ac74a23ed 100644
--- a/fs/fuse/fuse_i.h
+++ b/fs/fuse/fuse_i.h
@@ -13,6 +13,7 @@
 # define pr_fmt(fmt) "fuse: " fmt
 #endif
 
+#include "args.h"
 #include <linux/fuse.h>
 #include <linux/fs.h>
 #include <linux/mount.h>
@@ -48,12 +49,6 @@
 /** Number of dentries for each connection in the control filesystem */
 #define FUSE_CTL_NUM_DENTRIES 5
 
-/* Frequency (in seconds) of request timeout checks, if opted into */
-#define FUSE_TIMEOUT_TIMER_FREQ 15
-
-/** Frequency (in jiffies) of request timeout checks, if opted into */
-extern const unsigned long fuse_timeout_timer_freq;
-
 /*
  * Dentries invalidation workqueue period, in seconds.  The value of this
  * parameter shall be >= FUSE_DENTRY_INVAL_FREQ_MIN seconds, or 0 (zero), in
@@ -63,16 +58,6 @@ extern unsigned inval_wq __read_mostly;
 
 /** Maximum of max_pages received in init_out */
 extern unsigned int fuse_max_pages_limit;
-/*
- * Default timeout (in seconds) for the server to reply to a request
- * before the connection is aborted, if no timeout was specified on mount.
- */
-extern unsigned int fuse_default_req_timeout;
-/*
- * Max timeout (in seconds) for the server to reply to a request before
- * the connection is aborted.
- */
-extern unsigned int fuse_max_req_timeout;
 
 /** List of active connections */
 extern struct list_head fuse_conn_list;
@@ -84,143 +69,168 @@ extern struct mutex fuse_mutex;
 extern unsigned int max_user_bgreq;
 extern unsigned int max_user_congthresh;
 
-/* One forget request */
-struct fuse_forget_link {
-	struct fuse_forget_one forget_one;
-	struct fuse_forget_link *next;
-};
+struct fuse_forget_link;
 
-/* Submount lookup tracking */
+/**
+ * struct fuse_submount_lookup - Submount lookup tracking
+ */
 struct fuse_submount_lookup {
-	/** Refcount */
+	/** @count: Refcount */
 	refcount_t count;
 
-	/** Unique ID, which identifies the inode between userspace
-	 * and kernel */
+	/**
+	 * @nodeid: Unique ID, which identifies the inode between userspace
+	 * and kernel
+	 */
 	u64 nodeid;
 
-	/** The request used for sending the FORGET message */
+	/** @forget: The request used for sending the FORGET message */
 	struct fuse_forget_link *forget;
 };
 
-/** Container for data related to mapping to backing file */
+/* Container for data related to mapping to backing file */
 struct fuse_backing {
 	struct file *file;
 	struct cred *cred;
 
-	/** refcount */
+	/* refcount */
 	refcount_t count;
 	struct rcu_head rcu;
 };
 
-/** FUSE inode */
+/**
+ * struct fuse_inode - FUSE inode
+ */
 struct fuse_inode {
-	/** Inode data */
+	/** @inode: Inode data */
 	struct inode inode;
 
-	/** Unique ID, which identifies the inode between userspace
-	 * and kernel */
+	/**
+	 * @nodeid: Unique ID, which identifies the inode between userspace
+	 * and kernel
+	 */
 	u64 nodeid;
 
-	/** Number of lookups on this inode */
+	/** @nlookup: Number of lookups on this inode */
 	u64 nlookup;
 
-	/** The request used for sending the FORGET message */
+	/** @forget: The request used for sending the FORGET message */
 	struct fuse_forget_link *forget;
 
-	/** Time in jiffies until the file attributes are valid */
+	/** @i_time: Time in jiffies until the file attributes are valid */
 	u64 i_time;
 
-	/* Which attributes are invalid */
+	/** @inval_mask: Which attributes are invalid */
 	u32 inval_mask;
 
-	/** The sticky bit in inode->i_mode may have been removed, so
-	    preserve the original mode */
+	/**
+	 * @orig_i_mode: The sticky bit in inode->i_mode may have been removed,
+	 * so preserve the original mode
+	 */
 	umode_t orig_i_mode;
 
-	/* Cache birthtime */
+	/** @i_btime: Cache birthtime */
 	struct timespec64 i_btime;
 
-	/** 64 bit inode number */
+	/** @orig_ino: 64-bit inode number */
 	u64 orig_ino;
 
-	/** Version of last attribute change */
+	/** @attr_version: Version of last attribute change */
 	u64 attr_version;
 
 	union {
 		/* read/write io cache (regular file only) */
 		struct {
-			/* Files usable in writepage.  Protected by fi->lock */
+			/**
+			 * @write_files: Files usable in writepage.
+			 * Protected by fi->lock
+			 */
 			struct list_head write_files;
 
-			/* Writepages pending on truncate or fsync */
+			/**
+			 * @queued_writes: Writepages pending on truncate or
+			 * fsync
+			 */
 			struct list_head queued_writes;
 
-			/* Number of sent writes, a negative bias
-			 * (FUSE_NOWRITE) means more writes are blocked */
+			/**
+			 * @writectr: Number of sent writes, a negative bias
+			 * (FUSE_NOWRITE) means more writes are blocked
+			 */
 			int writectr;
 
-			/** Number of files/maps using page cache */
+			/** @iocachectr: Number of files/maps using page cache */
 			int iocachectr;
 
-			/* Waitq for writepage completion */
+			/** @page_waitq: Waitq for writepage completion */
 			wait_queue_head_t page_waitq;
 
-			/* waitq for direct-io completion */
+			/** @direct_io_waitq: waitq for direct-io completion */
 			wait_queue_head_t direct_io_waitq;
 		};
 
-		/* readdir cache (directory only) */
+		/** @rdc: readdir cache (directory only) */
 		struct {
-			/* true if fully cached */
+			/** @cached: true if fully cached */
 			bool cached;
 
-			/* size of cache */
+			/** @size: size of cache */
 			loff_t size;
 
-			/* position at end of cache (position of next entry) */
+			/**
+			 * @pos: position at end of cache (position of next
+			 * entry)
+			 */
 			loff_t pos;
 
-			/* version of the cache */
+			/** @version: version of the cache */
 			u64 version;
 
-			/* modification time of directory when cache was
-			 * started */
+			/**
+			 * @mtime: modification time of directory when cache was
+			 * started
+			 */
 			struct timespec64 mtime;
 
-			/* iversion of directory when cache was started */
+			/**
+			 * @iversion: iversion of directory when cache was
+			 * started
+			 */
 			u64 iversion;
 
-			/* protects above fields */
+			/** @lock: protects above fields */
 			spinlock_t lock;
 		} rdc;
 	};
 
-	/** Miscellaneous bits describing inode state */
+	/** @state: Miscellaneous bits describing inode state */
 	unsigned long state;
 
-	/** Lock for serializing lookup and readdir for back compatibility*/
+	/**
+	 * @mutex: Lock for serializing lookup and readdir for back
+	 * compatibility
+	 */
 	struct mutex mutex;
 
-	/** Lock to protect write related fields */
+	/** @lock: Lock to protect write-related fields */
 	spinlock_t lock;
 
 #ifdef CONFIG_FUSE_DAX
-	/*
-	 * Dax specific inode data
+	/**
+	 * @dax: Dax specific inode data
 	 */
 	struct fuse_inode_dax *dax;
 #endif
-	/** Submount specific lookup tracking */
+	/** @submount_lookup: Submount specific lookup tracking */
 	struct fuse_submount_lookup *submount_lookup;
 #ifdef CONFIG_FUSE_PASSTHROUGH
-	/** Reference to backing file in passthrough mode */
+	/** @fb: Reference to backing file in passthrough mode */
 	struct fuse_backing *fb;
 #endif
 
-	/*
-	 * The underlying inode->i_blkbits value will not be modified,
-	 * so preserve the blocksize specified by the server.
+	/**
+	 * @cached_i_blkbits: The underlying inode->i_blkbits value will not
+	 * be modified, so preserve the blocksize specified by the server.
 	 */
 	u8 cached_i_blkbits;
 };
@@ -250,116 +260,67 @@ struct fuse_conn;
 struct fuse_mount;
 union fuse_file_args;
 
-/** FUSE specific file data */
+/**
+ * struct fuse_file - FUSE-specific file data
+ */
 struct fuse_file {
-	/** Fuse connection for this file */
+	/** @fm: Fuse connection for this file */
 	struct fuse_mount *fm;
 
-	/* Argument space reserved for open/release */
+	/** @args: Argument space reserved for open/release */
 	union fuse_file_args *args;
 
-	/** Kernel file handle guaranteed to be unique */
+	/** @kh: Kernel file handle guaranteed to be unique */
 	u64 kh;
 
-	/** File handle used by userspace */
+	/** @fh: File handle used by userspace */
 	u64 fh;
 
-	/** Node id of this file */
+	/** @nodeid: Node id of this file */
 	u64 nodeid;
 
-	/** Refcount */
+	/** @count: Refcount */
 	refcount_t count;
 
-	/** FOPEN_* flags returned by open */
+	/** @open_flags: FOPEN_* flags returned by open */
 	u32 open_flags;
 
-	/** Entry on inode's write_files list */
+	/** @write_entry: Entry on inode's write_files list */
 	struct list_head write_entry;
 
-	/* Readdir related */
+	/** @readdir: Readdir-related */
 	struct {
-		/* Dir stream position */
+		/** @pos: Dir stream position */
 		loff_t pos;
 
-		/* Offset in cache */
+		/** @cache_off: Offset in cache */
 		loff_t cache_off;
 
-		/* Version of cache we are reading */
+		/** @version: Version of cache we are reading */
 		u64 version;
 
 	} readdir;
 
-	/** RB node to be linked on fuse_conn->polled_files */
+	/** @polled_node: RB node to be linked on fuse_conn->polled_files */
 	struct rb_node polled_node;
 
-	/** Wait queue head for poll */
+	/** @poll_wait: Wait queue head for poll */
 	wait_queue_head_t poll_wait;
 
-	/** Does file hold a fi->iocachectr refcount? */
+	/** @iomode: Does file hold a fi->iocachectr refcount? */
 	enum { IOM_NONE, IOM_CACHED, IOM_UNCACHED } iomode;
 
 #ifdef CONFIG_FUSE_PASSTHROUGH
-	/** Reference to backing file in passthrough mode */
+	/** @passthrough: Reference to backing file in passthrough mode */
 	struct file *passthrough;
+	/** @cred: passthrough file credentials */
 	const struct cred *cred;
 #endif
 
-	/** Has flock been performed on this file? */
+	/** @flock: Has flock been performed on this file? */
 	bool flock:1;
 };
 
-/** One input argument of a request */
-struct fuse_in_arg {
-	unsigned size;
-	const void *value;
-};
-
-/** One output argument of a request */
-struct fuse_arg {
-	unsigned size;
-	void *value;
-};
-
-/** FUSE folio descriptor */
-struct fuse_folio_desc {
-	unsigned int length;
-	unsigned int offset;
-};
-
-struct fuse_args {
-	uint64_t nodeid;
-	uint32_t opcode;
-	uint8_t in_numargs;
-	uint8_t out_numargs;
-	uint8_t ext_idx;
-	bool force:1;
-	bool noreply:1;
-	bool nocreds:1;
-	bool in_pages:1;
-	bool out_pages:1;
-	bool user_pages:1;
-	bool out_argvar:1;
-	bool page_zeroing:1;
-	bool page_replace:1;
-	bool may_block:1;
-	bool is_ext:1;
-	bool is_pinned:1;
-	bool invalidate_vmap:1;
-	bool abort_on_kill:1;
-	struct fuse_in_arg in_args[4];
-	struct fuse_arg out_args[2];
-	void (*end)(struct fuse_mount *fm, struct fuse_args *args, int error);
-	/* Used for kvec iter backed by vmalloc address */
-	void *vmap_base;
-};
-
-struct fuse_args_pages {
-	struct fuse_args args;
-	struct folio **folios;
-	struct fuse_folio_desc *descs;
-	unsigned int num_folios;
-};
-
 struct fuse_release_args {
 	struct fuse_args args;
 	struct fuse_release_in inarg;
@@ -399,200 +360,6 @@ struct fuse_io_priv {
 	.iocb = i,			\
 }
 
-/**
- * Request flags
- *
- * FR_ISREPLY:		set if the request has reply
- * FR_FORCE:		force sending of the request even if interrupted
- * FR_BACKGROUND:	request is sent in the background
- * FR_WAITING:		request is counted as "waiting"
- * FR_ABORTED:		the request was aborted
- * FR_INTERRUPTED:	the request has been interrupted
- * FR_LOCKED:		data is being copied to/from the request
- * FR_PENDING:		request is not yet in userspace
- * FR_SENT:		request is in userspace, waiting for an answer
- * FR_FINISHED:		request is finished
- * FR_PRIVATE:		request is on private list
- * FR_ASYNC:		request is asynchronous
- * FR_URING:		request is handled through fuse-io-uring
- */
-enum fuse_req_flag {
-	FR_ISREPLY,
-	FR_FORCE,
-	FR_BACKGROUND,
-	FR_WAITING,
-	FR_ABORTED,
-	FR_INTERRUPTED,
-	FR_LOCKED,
-	FR_PENDING,
-	FR_SENT,
-	FR_FINISHED,
-	FR_PRIVATE,
-	FR_ASYNC,
-	FR_URING,
-};
-
-/**
- * A request to the client
- *
- * .waitq.lock protects the following fields:
- *   - FR_ABORTED
- *   - FR_LOCKED (may also be modified under fc->lock, tested under both)
- */
-struct fuse_req {
-	/** This can be on either pending processing or io lists in
-	    fuse_conn */
-	struct list_head list;
-
-	/** Entry on the interrupts list  */
-	struct list_head intr_entry;
-
-	/* Input/output arguments */
-	struct fuse_args *args;
-
-	/** refcount */
-	refcount_t count;
-
-	/* Request flags, updated with test/set/clear_bit() */
-	unsigned long flags;
-
-	/* The request input header */
-	struct {
-		struct fuse_in_header h;
-	} in;
-
-	/* The request output header */
-	struct {
-		struct fuse_out_header h;
-	} out;
-
-	/** Used to wake up the task waiting for completion of request*/
-	wait_queue_head_t waitq;
-
-#if IS_ENABLED(CONFIG_VIRTIO_FS)
-	/** virtio-fs's physically contiguous buffer for in and out args */
-	void *argbuf;
-#endif
-
-	/** fuse_mount this request belongs to */
-	struct fuse_mount *fm;
-
-#ifdef CONFIG_FUSE_IO_URING
-	void *ring_entry;
-	void *ring_queue;
-#endif
-	/** When (in jiffies) the request was created */
-	unsigned long create_time;
-};
-
-struct fuse_iqueue;
-
-/**
- * Input queue callbacks
- *
- * Input queue signalling is device-specific.  For example, the /dev/fuse file
- * uses fiq->waitq and fasync to wake processes that are waiting on queue
- * readiness.  These callbacks allow other device types to respond to input
- * queue activity.
- */
-struct fuse_iqueue_ops {
-	/**
-	 * Send one forget
-	 */
-	void (*send_forget)(struct fuse_iqueue *fiq, struct fuse_forget_link *link);
-
-	/**
-	 * Send interrupt for request
-	 */
-	void (*send_interrupt)(struct fuse_iqueue *fiq, struct fuse_req *req);
-
-	/**
-	 * Send one request
-	 */
-	void (*send_req)(struct fuse_iqueue *fiq, struct fuse_req *req);
-
-	/**
-	 * Clean up when fuse_iqueue is destroyed
-	 */
-	void (*release)(struct fuse_iqueue *fiq);
-};
-
-/** /dev/fuse input queue operations */
-extern const struct fuse_iqueue_ops fuse_dev_fiq_ops;
-
-struct fuse_iqueue {
-	/** Connection established */
-	unsigned connected;
-
-	/** Lock protecting accesses to members of this structure */
-	spinlock_t lock;
-
-	/** Readers of the connection are waiting on this */
-	wait_queue_head_t waitq;
-
-	/** The next unique request id */
-	u64 reqctr;
-
-	/** The list of pending requests */
-	struct list_head pending;
-
-	/** Pending interrupts */
-	struct list_head interrupts;
-
-	/** Queue of pending forgets */
-	struct fuse_forget_link forget_list_head;
-	struct fuse_forget_link *forget_list_tail;
-
-	/** Batching of FORGET requests (positive indicates FORGET batch) */
-	int forget_batch;
-
-	/** O_ASYNC requests */
-	struct fasync_struct *fasync;
-
-	/** Device-specific callbacks */
-	const struct fuse_iqueue_ops *ops;
-
-	/** Device-specific state */
-	void *priv;
-};
-
-#define FUSE_PQ_HASH_BITS 8
-#define FUSE_PQ_HASH_SIZE (1 << FUSE_PQ_HASH_BITS)
-
-struct fuse_pqueue {
-	/** Connection established */
-	unsigned connected;
-
-	/** Lock protecting accessess to  members of this structure */
-	spinlock_t lock;
-
-	/** Hash table of requests being processed */
-	struct list_head *processing;
-
-	/** The list of requests under I/O */
-	struct list_head io;
-};
-
-/**
- * Fuse device instance
- */
-struct fuse_dev {
-	/** Reference count of this object */
-	refcount_t ref;
-
-	/** Issue FUSE_INIT synchronously */
-	bool sync_init;
-
-	/** Fuse connection for this device */
-	struct fuse_conn *fc;
-
-	/** Processing queue */
-	struct fuse_pqueue pq;
-
-	/** list entry on fc->devices */
-	struct list_head entry;
-};
-
 enum fuse_dax_mode {
 	FUSE_DAX_INODE_DEFAULT,	/* default */
 	FUSE_DAX_ALWAYS,	/* "-o dax=always" */
@@ -637,133 +404,135 @@ struct fuse_sync_bucket {
 };
 
 /**
- * A Fuse connection.
+ * struct fuse_conn - A Fuse connection.
  *
  * This structure is created, when the root filesystem is mounted, and
  * is destroyed, when the client device is closed and the last
  * fuse_mount is destroyed.
  */
 struct fuse_conn {
-	/** Lock protecting accessess to  members of this structure */
+	/**
+	 * @lock: Lock protecting:
+	 * - polled_files
+	 * - backing_files_map
+	 * - curr_bucket
+	 */
 	spinlock_t lock;
 
-	/** Refcount */
+	/** @count: Refcount */
 	refcount_t count;
 
-	/** Current epoch for up-to-date dentries */
+	/** @epoch: Current epoch for up-to-date dentries */
 	atomic_t epoch;
 
+	/** @epoch_work: Used to invalidate dentries from old epochs */
 	struct work_struct epoch_work;
 
+	/** @rcu: Used to delay freeing fuse_conn, making it safe */
 	struct rcu_head rcu;
 
-	/** The user id for this mount */
+	/** @user_id: The user id for this mount */
 	kuid_t user_id;
 
-	/** The group id for this mount */
+	/** @group_id: The group id for this mount */
 	kgid_t group_id;
 
-	/** The pid namespace for this mount */
+	/** @pid_ns: The pid namespace for this mount */
 	struct pid_namespace *pid_ns;
 
-	/** The user namespace for this mount */
+	/** @user_ns: The user namespace for this mount */
 	struct user_namespace *user_ns;
 
-	/** Maximum read size */
+	/** @max_read: Maximum read size */
 	unsigned max_read;
 
-	/** Maximum write size */
+	/** @max_write: Maximum write size */
 	unsigned max_write;
 
-	/** Maximum number of pages that can be used in a single request */
+	/**
+	 * @max_pages: Maximum number of pages that can be used in a
+	 * single request
+	 */
 	unsigned int max_pages;
 
-	/** Constrain ->max_pages to this value during feature negotiation */
+	/**
+	 * @max_pages_limit: Constrain ->max_pages to this value during
+	 * feature negotiation
+	 */
 	unsigned int max_pages_limit;
 
-	/** Input queue */
-	struct fuse_iqueue iq;
+	/** @chan: transport layer object */
+	struct fuse_chan *chan;
 
-	/** The next unique kernel file handle */
+	/** @khctr: The next unique kernel file handle */
 	atomic64_t khctr;
 
-	/** rbtree of fuse_files waiting for poll events indexed by ph */
+	/**
+	 * @polled_files: rbtree of fuse_files waiting for poll events
+	 * indexed by ph
+	 */
 	struct rb_root polled_files;
 
-	/** Maximum number of outstanding background requests */
-	unsigned max_background;
-
-	/** Number of background requests at which congestion starts */
+	/**
+	 * @congestion_threshold: Number of background requests at which
+	 * congestion starts
+	 */
 	unsigned congestion_threshold;
 
-	/** Number of requests currently in the background */
-	unsigned num_background;
-
-	/** Number of background requests currently queued for userspace */
-	unsigned active_background;
-
-	/** The list of background requests set aside for later queuing */
-	struct list_head bg_queue;
-
-	/** Protects: max_background, congestion_threshold, num_background,
-	 * active_background, bg_queue, blocked */
-	spinlock_t bg_lock;
-
-	/** Flag indicating that INIT reply has been received. Allocating
-	 * any fuse request will be suspended until the flag is set */
-	int initialized;
-
-	/** Flag indicating if connection is blocked.  This will be
-	    the case before the INIT reply is received, and if there
-	    are too many outstading backgrounds requests */
-	int blocked;
-
-	/** waitq for blocked connection */
-	wait_queue_head_t blocked_waitq;
-
-	/** Connection established, cleared on umount, connection
-	    abort and device release */
-	unsigned connected;
-
-	/** Connection aborted via sysfs */
-	bool aborted;
-
-	/** Connection failed (version mismatch).  Cannot race with
-	    setting other bitfields since it is only set once in INIT
-	    reply, before any other request, and never cleared */
+	/**
+	 * @conn_error: Connection failed (version mismatch).  Cannot race with
+	 * setting other bitfields since it is only set once in INIT
+	 * reply, before any other request, and never cleared
+	 */
 	unsigned conn_error:1;
 
-	/** Connection successful.  Only set in INIT */
+	/** @conn_init: Connection successful.  Only set in INIT */
 	unsigned conn_init:1;
 
-	/** Do readahead asynchronously?  Only set in INIT */
+	/** @async_read: Do readahead asynchronously?  Only set in INIT */
 	unsigned async_read:1;
 
-	/** Return an unique read error after abort.  Only set in INIT */
+	/**
+	 * @abort_err: Return an unique read error after abort.
+	 * Only set in INIT
+	 */
 	unsigned abort_err:1;
 
-	/** Do not send separate SETATTR request before open(O_TRUNC)  */
+	/**
+	 * @atomic_o_trunc: Do not send separate SETATTR request before
+	 * open(O_TRUNC)
+	 */
 	unsigned atomic_o_trunc:1;
 
-	/** Filesystem supports NFS exporting.  Only set in INIT */
+	/**
+	 * @export_support: Filesystem supports NFS exporting.
+	 * Only set in INIT
+	 */
 	unsigned export_support:1;
 
-	/** write-back cache policy (default is write-through) */
+	/** @writeback_cache: write-back cache policy (default is write-through) */
 	unsigned writeback_cache:1;
 
-	/** allow parallel lookups and readdir (default is serialized) */
+	/**
+	 * @parallel_dirops: allow parallel lookups and readdir (default is
+	 * serialized)
+	 */
 	unsigned parallel_dirops:1;
 
-	/** handle fs handles killing suid/sgid/cap on write/chown/trunc */
+	/**
+	 * @handle_killpriv: handle fs handles killing suid/sgid/cap on
+	 * write/chown/trunc
+	 */
 	unsigned handle_killpriv:1;
 
-	/** cache READLINK responses in page cache */
+	/** @cache_symlinks: cache READLINK responses in page cache */
 	unsigned cache_symlinks:1;
 
-	/* show legacy mount options */
+	/** @legacy_opts_show: show legacy mount options */
 	unsigned int legacy_opts_show:1;
 
-	/*
+	/**
+	 * @handle_killpriv_v2:
 	 * fs kills suid/sgid/cap on write/chown/trunc. suid is killed on
 	 * write/trunc only if caller did not have CAP_FSETID.  sgid is killed
 	 * on write/truncate only if caller did not have CAP_FSETID as well as
@@ -776,224 +545,219 @@ struct fuse_conn {
 	 * and hence races in setting them will not cause malfunction
 	 */
 
-	/** Is open/release not implemented by fs? */
+	/** @no_open: Is open/release not implemented by fs? */
 	unsigned no_open:1;
 
-	/** Is opendir/releasedir not implemented by fs? */
+	/** @no_opendir: Is opendir/releasedir not implemented by fs? */
 	unsigned no_opendir:1;
 
-	/** Is fsync not implemented by fs? */
+	/** @no_fsync: Is fsync not implemented by fs? */
 	unsigned no_fsync:1;
 
-	/** Is fsyncdir not implemented by fs? */
+	/** @no_fsyncdir: Is fsyncdir not implemented by fs? */
 	unsigned no_fsyncdir:1;
 
-	/** Is flush not implemented by fs? */
+	/** @no_flush: Is flush not implemented by fs? */
 	unsigned no_flush:1;
 
-	/** Is setxattr not implemented by fs? */
+	/** @no_setxattr: Is setxattr not implemented by fs? */
 	unsigned no_setxattr:1;
 
-	/** Does file server support extended setxattr */
+	/** @setxattr_ext: Does file server support extended setxattr */
 	unsigned setxattr_ext:1;
 
-	/** Is getxattr not implemented by fs? */
+	/** @no_getxattr: Is getxattr not implemented by fs? */
 	unsigned no_getxattr:1;
 
-	/** Is listxattr not implemented by fs? */
+	/** @no_listxattr: Is listxattr not implemented by fs? */
 	unsigned no_listxattr:1;
 
-	/** Is removexattr not implemented by fs? */
+	/** @no_removexattr: Is removexattr not implemented by fs? */
 	unsigned no_removexattr:1;
 
-	/** Are posix file locking primitives not implemented by fs? */
+	/** @no_lock: Are posix file locking primitives not implemented by fs? */
 	unsigned no_lock:1;
 
-	/** Is access not implemented by fs? */
+	/** @no_access: Is access not implemented by fs? */
 	unsigned no_access:1;
 
-	/** Is create not implemented by fs? */
+	/** @no_create: Is create not implemented by fs? */
 	unsigned no_create:1;
 
-	/** Is interrupt not implemented by fs? */
-	unsigned no_interrupt:1;
-
-	/** Is bmap not implemented by fs? */
+	/** @no_bmap: Is bmap not implemented by fs? */
 	unsigned no_bmap:1;
 
-	/** Is poll not implemented by fs? */
+	/** @no_poll: Is poll not implemented by fs? */
 	unsigned no_poll:1;
 
-	/** Do multi-page cached writes */
+	/** @big_writes: Do multi-page cached writes */
 	unsigned big_writes:1;
 
-	/** Don't apply umask to creation modes */
+	/** @dont_mask: Don't apply umask to creation modes */
 	unsigned dont_mask:1;
 
-	/** Are BSD file locking primitives not implemented by fs? */
+	/** @no_flock: Are BSD file locking primitives not implemented by fs? */
 	unsigned no_flock:1;
 
-	/** Is fallocate not implemented by fs? */
+	/** @no_fallocate: Is fallocate not implemented by fs? */
 	unsigned no_fallocate:1;
 
-	/** Is rename with flags implemented by fs? */
+	/** @no_rename2: Is rename with flags implemented by fs? */
 	unsigned no_rename2:1;
 
-	/** Use enhanced/automatic page cache invalidation. */
+	/** @auto_inval_data: Use enhanced/automatic page cache invalidation. */
 	unsigned auto_inval_data:1;
 
-	/** Filesystem is fully responsible for page cache invalidation. */
+	/**
+	 * @explicit_inval_data: Filesystem is fully responsible for page cache
+	 * invalidation.
+	 */
 	unsigned explicit_inval_data:1;
 
-	/** Does the filesystem support readdirplus? */
+	/** @do_readdirplus: Does the filesystem support readdirplus? */
 	unsigned do_readdirplus:1;
 
-	/** Does the filesystem want adaptive readdirplus? */
+	/** @readdirplus_auto: Does the filesystem want adaptive readdirplus? */
 	unsigned readdirplus_auto:1;
 
-	/** Does the filesystem support asynchronous direct-IO submission? */
+	/**
+	 * @async_dio: Does the filesystem support asynchronous direct-IO
+	 * submission?
+	 */
 	unsigned async_dio:1;
 
-	/** Is lseek not implemented by fs? */
+	/** @no_lseek: Is lseek not implemented by fs? */
 	unsigned no_lseek:1;
 
-	/** Does the filesystem support posix acls? */
+	/** @posix_acl: Does the filesystem support posix acls? */
 	unsigned posix_acl:1;
 
-	/** Check permissions based on the file mode or not? */
+	/**
+	 * @default_permissions: Check permissions based on the file mode
+	 * or not?
+	 */
 	unsigned default_permissions:1;
 
-	/** Allow other than the mounter user to access the filesystem ? */
+	/**
+	 * @allow_other: Allow other than the mounter user to access the
+	 * filesystem ?
+	 */
 	unsigned allow_other:1;
 
-	/** Does the filesystem support copy_file_range? */
+	/** @no_copy_file_range: Does the filesystem support copy_file_range? */
 	unsigned no_copy_file_range:1;
 
-	/** Does the filesystem support copy_file_range_64? */
+	/**
+	 * @no_copy_file_range_64: Does the filesystem support
+	 * copy_file_range_64?
+	 */
 	unsigned no_copy_file_range_64:1;
 
-	/* Send DESTROY request */
+	/** @destroy: Send DESTROY request */
 	unsigned int destroy:1;
 
-	/* Delete dentries that have gone stale */
+	/** @delete_stale: Delete dentries that have gone stale */
 	unsigned int delete_stale:1;
 
-	/** Do not create entry in fusectl fs */
+	/** @no_control: Do not create entry in fusectl fs */
 	unsigned int no_control:1;
 
-	/** Do not allow MNT_FORCE umount */
+	/** @no_force_umount: Do not allow MNT_FORCE umount */
 	unsigned int no_force_umount:1;
 
-	/* Auto-mount submounts announced by the server */
+	/** @auto_submounts: Auto-mount submounts announced by the server */
 	unsigned int auto_submounts:1;
 
-	/* Propagate syncfs() to server */
+	/** @sync_fs: Propagate syncfs() to server */
 	unsigned int sync_fs:1;
 
-	/* Initialize security xattrs when creating a new inode */
+	/** @init_security: Initialize security xattrs when creating a new inode */
 	unsigned int init_security:1;
 
-	/* Add supplementary group info when creating a new inode */
+	/**
+	 * @create_supp_group: Add supplementary group info when creating
+	 * a new inode
+	 */
 	unsigned int create_supp_group:1;
 
-	/* Does the filesystem support per inode DAX? */
+	/** @inode_dax: Does the filesystem support per inode DAX? */
 	unsigned int inode_dax:1;
 
-	/* Is tmpfile not implemented by fs? */
+	/** @no_tmpfile: Is tmpfile not implemented by fs? */
 	unsigned int no_tmpfile:1;
 
-	/* Relax restrictions to allow shared mmap in FOPEN_DIRECT_IO mode */
+	/**
+	 * @direct_io_allow_mmap: Relax restrictions to allow shared mmap
+	 * in FOPEN_DIRECT_IO mode
+	 */
 	unsigned int direct_io_allow_mmap:1;
 
-	/* Is statx not implemented by fs? */
+	/** @no_statx: Is statx not implemented by fs? */
 	unsigned int no_statx:1;
 
-	/** Passthrough support for read/write IO */
+	/** @passthrough: Passthrough support for read/write IO */
 	unsigned int passthrough:1;
 
-	/* Use pages instead of pointer for kernel I/O */
+	/** @use_pages_for_kvec_io: Use pages instead of pointer for kernel I/O */
 	unsigned int use_pages_for_kvec_io:1;
 
-	/* Is link not implemented by fs? */
+	/** @no_link: Is link not implemented by fs? */
 	unsigned int no_link:1;
 
-	/* Is synchronous FUSE_INIT allowed? */
+	/** @sync_init: Is synchronous FUSE_INIT allowed? */
 	unsigned int sync_init:1;
 
-	/* Use io_uring for communication */
-	unsigned int io_uring;
-
-	/** Maximum stack depth for passthrough backing files */
+	/** @max_stack_depth: Maximum stack depth for passthrough backing files */
 	int max_stack_depth;
 
-	/** The number of requests waiting for completion */
-	atomic_t num_waiting;
-
-	/** Negotiated minor version */
+	/** @minor: Negotiated minor version */
 	unsigned minor;
 
-	/** Entry on the fuse_conn_list */
+	/** @entry: Entry on the fuse_conn_list */
 	struct list_head entry;
 
-	/** Device ID from the root super block */
+	/** @dev: Device ID from the root super block */
 	dev_t dev;
 
-	/** Key for lock owner ID scrambling */
+	/** @scramble_key: Key for lock owner ID scrambling */
 	u32 scramble_key[4];
 
-	/** Version counter for attribute changes */
+	/** @attr_version: Version counter for attribute changes */
 	atomic64_t attr_version;
 
-	/** Version counter for evict inode */
+	/** @evict_ctr: Version counter for evict inode */
 	atomic64_t evict_ctr;
 
-	/* maximum file name length */
+	/** @name_max: maximum file name length */
 	u32 name_max;
 
-	/** Called on final put */
+	/** @release: Called on final put */
 	void (*release)(struct fuse_conn *);
 
 	/**
-	 * Read/write semaphore to hold when accessing the sb of any
+	 * @killsb: Read/write semaphore to hold when accessing the sb of any
 	 * fuse_mount belonging to this connection
 	 */
 	struct rw_semaphore killsb;
 
-	/** List of device instances belonging to this connection */
-	struct list_head devices;
-
 #ifdef CONFIG_FUSE_DAX
-	/* Dax mode */
+	/** @dax_mode: Dax mode */
 	enum fuse_dax_mode dax_mode;
 
-	/* Dax specific conn data, non-NULL if DAX is enabled */
+	/** @dax: Dax specific conn data, non-NULL if DAX is enabled */
 	struct fuse_conn_dax *dax;
 #endif
 
-	/** List of filesystems using this connection */
+	/** @mounts: List of filesystems using this connection */
 	struct list_head mounts;
 
-	/* New writepages go into this bucket */
+	/** @curr_bucket: New writepages go into this bucket */
 	struct fuse_sync_bucket __rcu *curr_bucket;
 
 #ifdef CONFIG_FUSE_PASSTHROUGH
-	/** IDR for backing files ids */
+	/** @backing_files_map: IDR for backing files ids */
 	struct idr backing_files_map;
 #endif
-
-#ifdef CONFIG_FUSE_IO_URING
-	/**  uring connection information*/
-	struct fuse_ring *ring;
-#endif
-
-	/** Only used if the connection opts into request timeouts */
-	struct {
-		/* Worker for checking if any requests have timed out */
-		struct delayed_work work;
-
-		/* Request timeout (in jiffies). 0 = no timeout */
-		unsigned int req_timeout;
-	} timeout;
 };
 
 /*
@@ -1136,7 +900,7 @@ extern const struct file_operations fuse_dev_operations;
 
 extern const struct dentry_operations fuse_dentry_operations;
 
-/**
+/*
  * Get a filled in inode
  */
 struct inode *fuse_iget(struct super_block *sb, u64 nodeid,
@@ -1147,14 +911,6 @@ struct inode *fuse_iget(struct super_block *sb, u64 nodeid,
 int fuse_lookup_name(struct super_block *sb, u64 nodeid, const struct qstr *name,
 		     struct fuse_entry_out *outarg, struct inode **inode);
 
-/**
- * Send FORGET command
- */
-void fuse_queue_forget(struct fuse_conn *fc, struct fuse_forget_link *forget,
-		       u64 nodeid, u64 nlookup);
-
-struct fuse_forget_link *fuse_alloc_forget(void);
-
 /*
  * Initialize READ or READDIR request
  */
@@ -1186,44 +942,44 @@ int fuse_finish_open(struct inode *inode, struct file *file);
 void fuse_sync_release(struct fuse_inode *fi, struct fuse_file *ff,
 		       unsigned int flags);
 
-/**
+/*
  * Send RELEASE or RELEASEDIR request
  */
 void fuse_release_common(struct file *file, bool isdir);
 
-/**
+/*
  * Send FSYNC or FSYNCDIR request
  */
 int fuse_fsync_common(struct file *file, loff_t start, loff_t end,
 		      int datasync, int opcode);
 
-/**
+/*
  * Notify poll wakeup
  */
 int fuse_notify_poll_wakeup(struct fuse_conn *fc,
 			    struct fuse_notify_poll_wakeup_out *outarg);
 
-/**
+/*
  * Initialize file operations on a regular file
  */
 void fuse_init_file_inode(struct inode *inode, unsigned int flags);
 
-/**
+/*
  * Initialize inode operations on regular files and special files
  */
 void fuse_init_common(struct inode *inode);
 
-/**
+/*
  * Initialize inode and file operations on a directory
  */
 void fuse_init_dir(struct inode *inode);
 
-/**
+/*
  * Initialize inode operations on a symlink
  */
 void fuse_init_symlink(struct inode *inode);
 
-/**
+/*
  * Change attributes of an inode
  */
 void fuse_change_attributes(struct inode *inode, struct fuse_attr *attr,
@@ -1237,20 +993,10 @@ void fuse_change_attributes_common(struct inode *inode, struct fuse_attr *attr,
 
 u32 fuse_get_cache_mask(struct inode *inode);
 
-/**
- * Initialize the client device
- */
-int fuse_dev_init(void);
-
-/**
- * Cleanup the client device
- */
-void fuse_dev_cleanup(void);
-
 int fuse_ctl_init(void);
 void __exit fuse_ctl_cleanup(void);
 
-/**
+/*
  * Simple request sending that does request allocation and freeing
  */
 ssize_t __fuse_simple_request(struct mnt_idmap *idmap,
@@ -1271,30 +1017,14 @@ static inline ssize_t fuse_simple_idmap_request(struct mnt_idmap *idmap,
 
 int fuse_simple_background(struct fuse_mount *fm, struct fuse_args *args,
 			   gfp_t gfp_flags);
-
-/**
- * Assign a unique id to a fuse request
- */
-void fuse_request_assign_unique(struct fuse_iqueue *fiq, struct fuse_req *req);
-
-/**
- * End a finished request
- */
-void fuse_request_end(struct fuse_req *req);
-
-/* Abort all requests */
-void fuse_abort_conn(struct fuse_conn *fc);
-void fuse_wait_aborted(struct fuse_conn *fc);
-
-/* Check if any requests timed out */
-void fuse_check_timeout(struct work_struct *work);
+int fuse_simple_notify_reply(struct fuse_mount *fm, struct fuse_args *args, u64 unique);
 
 void fuse_dentry_tree_init(void);
 void fuse_dentry_tree_cleanup(void);
 
 void fuse_epoch_work(struct work_struct *work);
 
-/**
+/*
  * Invalidate inode attributes
  */
 
@@ -1304,6 +1034,9 @@ void fuse_epoch_work(struct work_struct *work);
 /* Attributes possibly changed on data and/or size modification */
 #define FUSE_STATX_MODSIZE	(FUSE_STATX_MODIFY | STATX_SIZE)
 
+/* Attributes possibly changed on directory modification */
+#define FUSE_STATX_MODDIR	(FUSE_STATX_MODSIZE | STATX_NLINK)
+
 void fuse_invalidate_attr(struct inode *inode);
 void fuse_invalidate_attr_mask(struct inode *inode, u32 mask);
 
@@ -1317,45 +1050,26 @@ u64 fuse_time_to_jiffies(u64 sec, u32 nsec);
 
 void fuse_change_entry_timeout(struct dentry *entry, struct fuse_entry_out *o);
 
-/**
- * Acquire reference to fuse_conn
- */
-struct fuse_conn *fuse_conn_get(struct fuse_conn *fc);
-
-/**
- * Initialize the fuse processing queue
- */
-void fuse_pqueue_init(struct fuse_pqueue *fpq);
-
-/**
+/*
  * Initialize fuse_conn
  */
 void fuse_conn_init(struct fuse_conn *fc, struct fuse_mount *fm,
-		    struct user_namespace *user_ns,
-		    const struct fuse_iqueue_ops *fiq_ops, void *fiq_priv);
+		    struct user_namespace *user_ns, struct fuse_chan *fch);
 
-/**
- * Release reference to fuse_conn
- */
-void fuse_conn_put(struct fuse_conn *fc);
-
-struct fuse_dev *fuse_dev_alloc_install(struct fuse_conn *fc);
-struct fuse_dev *fuse_dev_alloc(void);
-void fuse_dev_install(struct fuse_dev *fud, struct fuse_conn *fc);
-void fuse_dev_put(struct fuse_dev *fud);
 int fuse_send_init(struct fuse_mount *fm);
 
 /**
- * Fill in superblock and initialize fuse connection
+ * fuse_fill_super_common - Fill in superblock and initialize fuse connection
  * @sb: partially-initialized superblock to fill in
  * @ctx: mount context
  */
 int fuse_fill_super_common(struct super_block *sb, struct fuse_fs_context *ctx);
 
-/*
- * Remove the mount from the connection
+/**
+ * fuse_mount_remove - Remove the mount from the connection
+ * @fm: fuse_mount to remove
  *
- * Returns whether this was the last mount
+ * Returns: whether this was the last mount
  */
 bool fuse_mount_remove(struct fuse_mount *fm);
 
@@ -1373,23 +1087,25 @@ void fuse_conn_destroy(struct fuse_mount *fm);
 void fuse_mount_destroy(struct fuse_mount *fm);
 
 /**
- * Add connection to control filesystem
+ * fuse_ctl_add_conn - Add connection to control filesystem
+ * @fc: Fuse connection to add
  */
 int fuse_ctl_add_conn(struct fuse_conn *fc);
 
 /**
- * Remove connection from control filesystem
+ * fuse_ctl_remove_conn - Remove connection from control filesystem
+ * @fc: Fuse connection to remove
  */
 void fuse_ctl_remove_conn(struct fuse_conn *fc);
 
-/**
+/*
  * Is file type valid?
  */
 int fuse_valid_type(int m);
 
 bool fuse_invalid_attr(struct fuse_attr *attr);
 
-/**
+/*
  * Is current process allowed to perform filesystem operation?
  */
 bool fuse_allow_current_process(struct fuse_conn *fc);
@@ -1406,7 +1122,7 @@ void fuse_flush_writepages(struct inode *inode);
 void fuse_set_nowrite(struct inode *inode);
 void fuse_release_nowrite(struct inode *inode);
 
-/**
+/*
  * Scan all fuse_mounts belonging to fc to find the first where
  * ilookup5() returns a result.  Return that result and the
  * respective fuse_mount in *fm (unless fm is NULL).
@@ -1416,13 +1132,13 @@ void fuse_release_nowrite(struct inode *inode);
 struct inode *fuse_ilookup(struct fuse_conn *fc, u64 nodeid,
 			   struct fuse_mount **fm);
 
-/**
+/*
  * File-system tells the kernel to invalidate cache for the given node id.
  */
 int fuse_reverse_inval_inode(struct fuse_conn *fc, u64 nodeid,
 			     loff_t offset, loff_t len);
 
-/**
+/*
  * File-system tells the kernel to invalidate parent attributes and
  * the dentry matching parent/name.
  *
@@ -1444,7 +1160,7 @@ void fuse_try_prune_one_inode(struct fuse_conn *fc, u64 nodeid);
 int fuse_do_open(struct fuse_mount *fm, u64 nodeid, struct file *file,
 		 bool isdir);
 
-/**
+/*
  * fuse_direct_io() flags
  */
 
@@ -1461,7 +1177,6 @@ long fuse_do_ioctl(struct file *file, unsigned int cmd, unsigned long arg,
 long fuse_ioctl_common(struct file *file, unsigned int cmd,
 		       unsigned long arg, unsigned int flags);
 __poll_t fuse_file_poll(struct file *file, poll_table *wait);
-int fuse_dev_release(struct inode *inode, struct file *file);
 
 bool fuse_write_update_attr(struct inode *inode, loff_t pos, ssize_t written);
 
@@ -1471,8 +1186,6 @@ int fuse_write_inode(struct inode *inode, struct writeback_control *wbc);
 int fuse_do_setattr(struct mnt_idmap *idmap, struct dentry *dentry,
 		    struct iattr *attr, struct file *file);
 
-void fuse_set_initialized(struct fuse_conn *fc);
-
 void fuse_unlock_inode(struct inode *inode, bool locked);
 bool fuse_lock_inode(struct inode *inode);
 
@@ -1494,15 +1207,6 @@ int fuse_set_acl(struct mnt_idmap *, struct dentry *dentry,
 /* readdir.c */
 int fuse_readdir(struct file *file, struct dir_context *ctx);
 
-/**
- * Return the number of bytes in an arguments list
- */
-unsigned int fuse_len_args(unsigned int numargs, struct fuse_arg *args);
-
-/**
- * Get the next unique ID for a request
- */
-u64 fuse_get_unique(struct fuse_iqueue *fiq);
 void fuse_free_conn(struct fuse_conn *fc);
 
 /* dax.c */
@@ -1570,8 +1274,6 @@ static inline struct fuse_backing *fuse_backing_lookup(struct fuse_conn *fc,
 
 void fuse_backing_files_init(struct fuse_conn *fc);
 void fuse_backing_files_free(struct fuse_conn *fc);
-int fuse_backing_open(struct fuse_conn *fc, struct fuse_backing_map *map);
-int fuse_backing_close(struct fuse_conn *fc, int backing_id);
 
 /* passthrough.c */
 static inline struct fuse_backing *fuse_inode_backing(struct fuse_inode *fi)
diff --git a/fs/fuse/fuse_trace.h b/fs/fuse/fuse_trace.h
index bbe9ddd8c716..4e34ddb172ed 100644
--- a/fs/fuse/fuse_trace.h
+++ b/fs/fuse/fuse_trace.h
@@ -90,7 +90,7 @@ TRACE_EVENT(fuse_request_send,
 	),
 
 	TP_fast_assign(
-		__entry->connection	=	req->fm->fc->dev;
+		__entry->connection	=	req->chan->conn->dev;
 		__entry->unique		=	req->in.h.unique;
 		__entry->opcode		=	req->in.h.opcode;
 		__entry->len		=	req->in.h.len;
@@ -114,7 +114,7 @@ TRACE_EVENT(fuse_request_end,
 	),
 
 	TP_fast_assign(
-		__entry->connection	=	req->fm->fc->dev;
+		__entry->connection	=	req->chan->conn->dev;
 		__entry->unique		=	req->in.h.unique;
 		__entry->len		=	req->out.h.len;
 		__entry->error		=	req->out.h.error;
diff --git a/fs/fuse/inode.c b/fs/fuse/inode.c
index deddfffb037f..e90a6bf25b27 100644
--- a/fs/fuse/inode.c
+++ b/fs/fuse/inode.c
@@ -6,9 +6,8 @@
   See the file COPYING.
 */
 
+#include "dev.h"
 #include "fuse_i.h"
-#include "fuse_dev_i.h"
-#include "dev_uring_i.h"
 
 #include <linux/dax.h>
 #include <linux/pagemap.h>
@@ -35,14 +34,11 @@ MODULE_LICENSE("GPL");
 static struct kmem_cache *fuse_inode_cachep;
 struct list_head fuse_conn_list;
 DEFINE_MUTEX(fuse_mutex);
-DECLARE_WAIT_QUEUE_HEAD(fuse_dev_waitq);
 
 static int set_global_limit(const char *val, const struct kernel_param *kp);
 
 unsigned int fuse_max_pages_limit = 256;
 /* default is no timeout */
-unsigned int fuse_default_req_timeout;
-unsigned int fuse_max_req_timeout;
 
 unsigned int max_user_bgreq;
 module_param_call(max_user_bgreq, set_global_limit, param_get_uint,
@@ -62,9 +58,6 @@ MODULE_PARM_DESC(max_user_congthresh,
 
 #define FUSE_DEFAULT_BLKSIZE 512
 
-/** Maximum number of outstanding background requests */
-#define FUSE_DEFAULT_MAX_BACKGROUND 12
-
 /** Congestion starts at 75% of maximum */
 #define FUSE_DEFAULT_CONGESTION_THRESHOLD (FUSE_DEFAULT_MAX_BACKGROUND * 3 / 4)
 
@@ -72,11 +65,6 @@ MODULE_PARM_DESC(max_user_congthresh,
 static struct file_system_type fuseblk_fs_type;
 #endif
 
-struct fuse_forget_link *fuse_alloc_forget(void)
-{
-	return kzalloc_obj(struct fuse_forget_link, GFP_KERNEL_ACCOUNT);
-}
-
 static struct fuse_submount_lookup *fuse_alloc_submount_lookup(void)
 {
 	struct fuse_submount_lookup *sl;
@@ -150,7 +138,7 @@ static void fuse_cleanup_submount_lookup(struct fuse_conn *fc,
 	if (!refcount_dec_and_test(&sl->count))
 		return;
 
-	fuse_queue_forget(fc, sl->forget, sl->nodeid, 1);
+	fuse_chan_queue_forget(fc->chan, sl->forget, sl->nodeid, 1);
 	sl->forget = NULL;
 	kfree(sl);
 }
@@ -173,8 +161,8 @@ static void fuse_evict_inode(struct inode *inode)
 		if (FUSE_IS_DAX(inode))
 			fuse_dax_inode_cleanup(inode);
 		if (fi->nlookup) {
-			fuse_queue_forget(fc, fi->forget, fi->nodeid,
-					  fi->nlookup);
+			fuse_chan_queue_forget(fc->chan, fi->forget, fi->nodeid,
+					       fi->nlookup);
 			fi->forget = NULL;
 		}
 
@@ -624,7 +612,7 @@ static void fuse_umount_begin(struct super_block *sb)
 	if (fc->no_force_umount)
 		return;
 
-	fuse_abort_conn(fc);
+	fuse_chan_abort(fc->chan, false);
 
 	// Only retire block-device-based superblocks.
 	if (sb->s_bdev != NULL)
@@ -816,8 +804,7 @@ static int fuse_opt_fd(struct fs_context *fsc, struct file *file)
 	if (file->f_cred->user_ns != fsc->user_ns)
 		return invalfc(fsc, "wrong user namespace for fuse device");
 
-	ctx->fud = file->private_data;
-	refcount_inc(&ctx->fud->ref);
+	ctx->fud = fuse_dev_grab(file);
 
 	return 0;
 }
@@ -970,56 +957,19 @@ static int fuse_show_options(struct seq_file *m, struct dentry *root)
 	return 0;
 }
 
-static void fuse_iqueue_init(struct fuse_iqueue *fiq,
-			     const struct fuse_iqueue_ops *ops,
-			     void *priv)
-{
-	memset(fiq, 0, sizeof(struct fuse_iqueue));
-	spin_lock_init(&fiq->lock);
-	init_waitqueue_head(&fiq->waitq);
-	INIT_LIST_HEAD(&fiq->pending);
-	INIT_LIST_HEAD(&fiq->interrupts);
-	fiq->forget_list_tail = &fiq->forget_list_head;
-	fiq->connected = 1;
-	fiq->ops = ops;
-	fiq->priv = priv;
-}
-
-void fuse_pqueue_init(struct fuse_pqueue *fpq)
-{
-	unsigned int i;
-
-	spin_lock_init(&fpq->lock);
-	for (i = 0; i < FUSE_PQ_HASH_SIZE; i++)
-		INIT_LIST_HEAD(&fpq->processing[i]);
-	INIT_LIST_HEAD(&fpq->io);
-	fpq->connected = 1;
-}
-
 void fuse_conn_init(struct fuse_conn *fc, struct fuse_mount *fm,
-		    struct user_namespace *user_ns,
-		    const struct fuse_iqueue_ops *fiq_ops, void *fiq_priv)
+		    struct user_namespace *user_ns, struct fuse_chan *fch)
 {
 	memset(fc, 0, sizeof(*fc));
 	spin_lock_init(&fc->lock);
-	spin_lock_init(&fc->bg_lock);
 	init_rwsem(&fc->killsb);
 	refcount_set(&fc->count, 1);
 	atomic_set(&fc->epoch, 1);
 	INIT_WORK(&fc->epoch_work, fuse_epoch_work);
-	init_waitqueue_head(&fc->blocked_waitq);
-	fuse_iqueue_init(&fc->iq, fiq_ops, fiq_priv);
-	INIT_LIST_HEAD(&fc->bg_queue);
 	INIT_LIST_HEAD(&fc->entry);
-	INIT_LIST_HEAD(&fc->devices);
-	atomic_set(&fc->num_waiting, 0);
-	fc->max_background = FUSE_DEFAULT_MAX_BACKGROUND;
 	fc->congestion_threshold = FUSE_DEFAULT_CONGESTION_THRESHOLD;
 	atomic64_set(&fc->khctr, 0);
 	fc->polled_files = RB_ROOT;
-	fc->blocked = 0;
-	fc->initialized = 0;
-	fc->connected = 1;
 	atomic64_set(&fc->attr_version, 1);
 	atomic64_set(&fc->evict_ctr, 1);
 	get_random_bytes(&fc->scramble_key, sizeof(fc->scramble_key));
@@ -1028,7 +978,6 @@ void fuse_conn_init(struct fuse_conn *fc, struct fuse_mount *fm,
 	fc->max_pages = FUSE_DEFAULT_MAX_PAGES_PER_REQ;
 	fc->max_pages_limit = fuse_max_pages_limit;
 	fc->name_max = FUSE_NAME_LOW_MAX;
-	fc->timeout.req_timeout = 0;
 
 	if (IS_ENABLED(CONFIG_FUSE_PASSTHROUGH))
 		fuse_backing_files_init(fc);
@@ -1036,6 +985,8 @@ void fuse_conn_init(struct fuse_conn *fc, struct fuse_mount *fm,
 	INIT_LIST_HEAD(&fc->mounts);
 	list_add(&fm->fc_entry, &fc->mounts);
 	fm->fc = fc;
+	fuse_chan_set_fc(fch, fc);
+	fc->chan = fch;
 }
 EXPORT_SYMBOL_GPL(fuse_conn_init);
 
@@ -1043,7 +994,8 @@ static void delayed_release(struct rcu_head *p)
 {
 	struct fuse_conn *fc = container_of(p, struct fuse_conn, rcu);
 
-	fuse_uring_destruct(fc);
+	fuse_uring_destruct(fc->chan);
+	fuse_chan_free(fc->chan);
 
 	put_user_ns(fc->user_ns);
 	fc->release(fc);
@@ -1051,7 +1003,6 @@ static void delayed_release(struct rcu_head *p)
 
 void fuse_conn_put(struct fuse_conn *fc)
 {
-	struct fuse_iqueue *fiq = &fc->iq;
 	struct fuse_sync_bucket *bucket;
 
 	if (!refcount_dec_and_test(&fc->count))
@@ -1059,11 +1010,8 @@ void fuse_conn_put(struct fuse_conn *fc)
 
 	if (IS_ENABLED(CONFIG_FUSE_DAX))
 		fuse_dax_conn_free(fc);
-	if (fc->timeout.req_timeout)
-		cancel_delayed_work_sync(&fc->timeout.work);
 	cancel_work_sync(&fc->epoch_work);
-	if (fiq->ops->release)
-		fiq->ops->release(fiq);
+	fuse_chan_release(fc->chan);
 	put_pid_ns(fc->pid_ns);
 	bucket = rcu_dereference_protected(fc->curr_bucket, 1);
 	if (bucket) {
@@ -1083,6 +1031,11 @@ struct fuse_conn *fuse_conn_get(struct fuse_conn *fc)
 }
 EXPORT_SYMBOL_GPL(fuse_conn_get);
 
+dev_t fuse_conn_get_id(struct fuse_conn *fc)
+{
+	return fc->dev;
+}
+
 static struct inode *fuse_get_root_inode(struct super_block *sb, unsigned int mode)
 {
 	struct fuse_attr attr;
@@ -1294,12 +1247,13 @@ static void process_init_limits(struct fuse_conn *fc, struct fuse_init_out *arg)
 	sanitize_global_limit(&max_user_bgreq);
 	sanitize_global_limit(&max_user_congthresh);
 
-	spin_lock(&fc->bg_lock);
 	if (arg->max_background) {
-		fc->max_background = arg->max_background;
+		unsigned int max_background = max_background = arg->max_background;
+
+		if (!cap_sys_admin && max_background > max_user_bgreq)
+			max_background = max_user_bgreq;
 
-		if (!cap_sys_admin && fc->max_background > max_user_bgreq)
-			fc->max_background = max_user_bgreq;
+		fuse_chan_max_background_set(fc->chan, max_background);
 	}
 	if (arg->congestion_threshold) {
 		fc->congestion_threshold = arg->congestion_threshold;
@@ -1308,48 +1262,20 @@ static void process_init_limits(struct fuse_conn *fc, struct fuse_init_out *arg)
 		    fc->congestion_threshold > max_user_congthresh)
 			fc->congestion_threshold = max_user_congthresh;
 	}
-	spin_unlock(&fc->bg_lock);
-}
-
-static void set_request_timeout(struct fuse_conn *fc, unsigned int timeout)
-{
-	fc->timeout.req_timeout = secs_to_jiffies(timeout);
-	INIT_DELAYED_WORK(&fc->timeout.work, fuse_check_timeout);
-	queue_delayed_work(system_percpu_wq, &fc->timeout.work,
-			   fuse_timeout_timer_freq);
-}
-
-static void init_server_timeout(struct fuse_conn *fc, unsigned int timeout)
-{
-	if (!timeout && !fuse_max_req_timeout && !fuse_default_req_timeout)
-		return;
-
-	if (!timeout)
-		timeout = fuse_default_req_timeout;
-
-	if (fuse_max_req_timeout) {
-		if (timeout)
-			timeout = min(fuse_max_req_timeout, timeout);
-		else
-			timeout = fuse_max_req_timeout;
-	}
-
-	timeout = max(FUSE_TIMEOUT_TIMER_FREQ, timeout);
-
-	set_request_timeout(fc, timeout);
 }
 
 struct fuse_init_args {
 	struct fuse_args args;
 	struct fuse_init_in in;
 	struct fuse_init_out out;
+	struct fuse_mount *fm;
 };
 
-static void process_init_reply(struct fuse_mount *fm, struct fuse_args *args,
-			       int error)
+static void process_init_reply(struct fuse_args *args, int error)
 {
-	struct fuse_conn *fc = fm->fc;
 	struct fuse_init_args *ia = container_of(args, typeof(*ia), args);
+	struct fuse_mount *fm = ia->fm;
+	struct fuse_conn *fc = fm->fc;
 	struct fuse_init_out *arg = &ia->out;
 	bool ok = true;
 
@@ -1481,7 +1407,7 @@ static void process_init_reply(struct fuse_mount *fm, struct fuse_args *args,
 					ok = false;
 			}
 			if (flags & FUSE_OVER_IO_URING && fuse_uring_enabled())
-				fc->io_uring = 1;
+				fuse_chan_io_uring_enable(fc->chan);
 
 			if (flags & FUSE_REQUEST_TIMEOUT)
 				timeout = arg->request_timeout;
@@ -1491,7 +1417,7 @@ static void process_init_reply(struct fuse_mount *fm, struct fuse_args *args,
 			fc->no_flock = 1;
 		}
 
-		init_server_timeout(fc, timeout);
+		fuse_init_server_timeout(fc->chan, timeout);
 
 		fm->sb->s_bdi->ra_pages =
 				min(fm->sb->s_bdi->ra_pages, ra_pages);
@@ -1505,10 +1431,15 @@ static void process_init_reply(struct fuse_mount *fm, struct fuse_args *args,
 	if (!ok) {
 		fc->conn_init = 0;
 		fc->conn_error = 1;
+		fuse_chan_set_initialized(fc->chan, NULL);
+	} else {
+		struct fuse_chan_param cp = {
+			.minor = fc->minor,
+			.max_write = fc->max_write,
+			.max_pages = fc->max_pages,
+		};
+		fuse_chan_set_initialized(fc->chan, &cp);
 	}
-
-	fuse_set_initialized(fc);
-	wake_up_all(&fc->blocked_waitq);
 }
 
 static struct fuse_init_args *fuse_new_init(struct fuse_mount *fm)
@@ -1518,6 +1449,7 @@ static struct fuse_init_args *fuse_new_init(struct fuse_mount *fm)
 
 	ia = kzalloc_obj(*ia, GFP_KERNEL | __GFP_NOFAIL);
 
+	ia->fm = fm;
 	ia->in.major = FUSE_KERNEL_VERSION;
 	ia->in.minor = FUSE_KERNEL_MINOR_VERSION;
 	ia->in.max_readahead = fm->sb->s_bdi->ra_pages * PAGE_SIZE;
@@ -1591,7 +1523,7 @@ int fuse_send_init(struct fuse_mount *fm)
 		if (!err)
 			return 0;
 	}
-	process_init_reply(fm, &ia->args, err);
+	process_init_reply(&ia->args, err);
 	if (fm->fc->conn_error)
 		return -ENOTCONN;
 	return 0;
@@ -1600,7 +1532,6 @@ EXPORT_SYMBOL_GPL(fuse_send_init);
 
 void fuse_free_conn(struct fuse_conn *fc)
 {
-	WARN_ON(!list_empty(&fc->devices));
 	kfree(fc);
 }
 EXPORT_SYMBOL_GPL(fuse_free_conn);
@@ -1643,89 +1574,6 @@ static int fuse_bdi_init(struct fuse_conn *fc, struct super_block *sb)
 	return 0;
 }
 
-struct fuse_dev *fuse_dev_alloc(void)
-{
-	struct fuse_dev *fud;
-	struct list_head *pq;
-
-	fud = kzalloc_obj(struct fuse_dev);
-	if (!fud)
-		return NULL;
-
-	refcount_set(&fud->ref, 1);
-	pq = kzalloc_objs(struct list_head, FUSE_PQ_HASH_SIZE);
-	if (!pq) {
-		kfree(fud);
-		return NULL;
-	}
-
-	fud->pq.processing = pq;
-	fuse_pqueue_init(&fud->pq);
-
-	return fud;
-}
-EXPORT_SYMBOL_GPL(fuse_dev_alloc);
-
-void fuse_dev_install(struct fuse_dev *fud, struct fuse_conn *fc)
-{
-	struct fuse_conn *old_fc;
-
-	spin_lock(&fc->lock);
-	/*
-	 * Pairs with:
-	 *  - xchg() in fuse_dev_release()
-	 *  - smp_load_acquire() in fuse_dev_fc_get()
-	 */
-	old_fc = cmpxchg(&fud->fc, NULL, fc);
-	if (old_fc) {
-		/*
-		 * failed to set fud->fc because
-		 *  - it was already set to a different fc
-		 *  - it was set to disconneted
-		 */
-		fc->connected = 0;
-	} else {
-		list_add_tail(&fud->entry, &fc->devices);
-		fuse_conn_get(fc);
-	}
-	spin_unlock(&fc->lock);
-}
-EXPORT_SYMBOL_GPL(fuse_dev_install);
-
-struct fuse_dev *fuse_dev_alloc_install(struct fuse_conn *fc)
-{
-	struct fuse_dev *fud;
-
-	fud = fuse_dev_alloc();
-	if (!fud)
-		return NULL;
-
-	fuse_dev_install(fud, fc);
-	return fud;
-}
-EXPORT_SYMBOL_GPL(fuse_dev_alloc_install);
-
-void fuse_dev_put(struct fuse_dev *fud)
-{
-	struct fuse_conn *fc;
-
-	if (!refcount_dec_and_test(&fud->ref))
-		return;
-
-	fc = fuse_dev_fc_get(fud);
-	if (fc && fc != FUSE_DEV_FC_DISCONNECTED) {
-		/* This is the virtiofs case (fuse_dev_release() not called) */
-		spin_lock(&fc->lock);
-		list_del(&fud->entry);
-		spin_unlock(&fc->lock);
-
-		fuse_conn_put(fc);
-	}
-	kfree(fud->pq.processing);
-	kfree(fud);
-}
-EXPORT_SYMBOL_GPL(fuse_dev_put);
-
 static void fuse_fill_attr_from_inode(struct fuse_attr *attr,
 				      const struct fuse_inode *fi)
 {
@@ -1941,9 +1789,9 @@ int fuse_fill_super_common(struct super_block *sb, struct fuse_fs_context *ctx)
 	mutex_lock(&fuse_mutex);
 	err = -EINVAL;
 	if (fud) {
-		if (fuse_dev_fc_get(fud))
+		if (fuse_dev_is_installed(fud))
 			goto err_unlock;
-		if (fud->sync_init)
+		if (fuse_dev_is_sync_init(fud))
 			fc->sync_init = 1;
 	}
 
@@ -1953,10 +1801,9 @@ int fuse_fill_super_common(struct super_block *sb, struct fuse_fs_context *ctx)
 
 	list_add_tail(&fc->entry, &fuse_conn_list);
 	sb->s_root = root_dentry;
-	if (fud) {
-		fuse_dev_install(fud, fc);
-		wake_up_all(&fuse_dev_waitq);
-	}
+	if (fud)
+		fuse_dev_install(fud, fc->chan);
+
 	mutex_unlock(&fuse_mutex);
 	return 0;
 
@@ -2001,9 +1848,7 @@ static int fuse_set_no_super(struct super_block *sb, struct fs_context *fsc)
 
 static int fuse_test_super(struct super_block *sb, struct fs_context *fsc)
 {
-	struct fuse_dev *fud = fsc->sget_key;
-
-	return fuse_dev_fc_get(fud) == get_fuse_conn_super(sb);
+	return fuse_dev_verify(fsc->sget_key, get_fuse_conn_super(sb)->chan);
 }
 
 static int fuse_get_tree(struct fs_context *fsc)
@@ -2012,8 +1857,12 @@ static int fuse_get_tree(struct fs_context *fsc)
 	struct fuse_conn *fc;
 	struct fuse_mount *fm;
 	struct super_block *sb;
+	struct fuse_chan *fch __free(fuse_chan_free) = fuse_dev_chan_new();
 	int err;
 
+	if (!fch)
+		return -ENOMEM;
+
 	fc = kmalloc_obj(*fc);
 	if (!fc)
 		return -ENOMEM;
@@ -2024,7 +1873,7 @@ static int fuse_get_tree(struct fs_context *fsc)
 		return -ENOMEM;
 	}
 
-	fuse_conn_init(fc, fm, fsc->user_ns, &fuse_dev_fiq_ops, NULL);
+	fuse_conn_init(fc, fm, fsc->user_ns, no_free_ptr(fch));
 	fc->release = fuse_free_conn;
 
 	fsc->s_fs_info = fm;
@@ -2045,7 +1894,7 @@ static int fuse_get_tree(struct fs_context *fsc)
 	 * Allow creating a fuse mount with an already initialized fuse
 	 * connection
 	 */
-	if (fuse_dev_fc_get(ctx->fud)) {
+	if (fuse_dev_is_installed(ctx->fud)) {
 		fsc->sget_key = ctx->fud;
 		sb = sget_fc(fsc, fuse_test_super, fuse_set_no_super);
 		err = PTR_ERR_OR_ZERO(sb);
@@ -2116,8 +1965,8 @@ void fuse_conn_destroy(struct fuse_mount *fm)
 	if (fc->destroy)
 		fuse_send_destroy(fm);
 
-	fuse_abort_conn(fc);
-	fuse_wait_aborted(fc);
+	fuse_chan_abort(fc->chan, false);
+	fuse_chan_wait_aborted(fc->chan);
 
 	if (!list_empty(&fc->entry)) {
 		mutex_lock(&fuse_mutex);
diff --git a/fs/fuse/notify.c b/fs/fuse/notify.c
new file mode 100644
index 000000000000..f200a33f0533
--- /dev/null
+++ b/fs/fuse/notify.c
@@ -0,0 +1,434 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include "dev.h"
+#include "fuse_i.h"
+#include <linux/pagemap.h>
+
+static int fuse_notify_poll(struct fuse_conn *fc, unsigned int size,
+			    struct fuse_copy_state *cs)
+{
+	struct fuse_notify_poll_wakeup_out outarg;
+	int err;
+
+	if (size != sizeof(outarg))
+		return -EINVAL;
+
+	err = fuse_copy_one(cs, &outarg, sizeof(outarg));
+	if (err)
+		return err;
+
+	fuse_copy_finish(cs);
+	return fuse_notify_poll_wakeup(fc, &outarg);
+}
+
+static int fuse_notify_inval_inode(struct fuse_conn *fc, unsigned int size,
+				   struct fuse_copy_state *cs)
+{
+	struct fuse_notify_inval_inode_out outarg;
+	int err;
+
+	if (size != sizeof(outarg))
+		return -EINVAL;
+
+	err = fuse_copy_one(cs, &outarg, sizeof(outarg));
+	if (err)
+		return err;
+	fuse_copy_finish(cs);
+
+	down_read(&fc->killsb);
+	err = fuse_reverse_inval_inode(fc, outarg.ino,
+				       outarg.off, outarg.len);
+	up_read(&fc->killsb);
+	return err;
+}
+
+static int fuse_notify_inval_entry(struct fuse_conn *fc, unsigned int size,
+				   struct fuse_copy_state *cs)
+{
+	struct fuse_notify_inval_entry_out outarg;
+	int err;
+	char *buf;
+	struct qstr name;
+
+	if (size < sizeof(outarg))
+		return -EINVAL;
+
+	err = fuse_copy_one(cs, &outarg, sizeof(outarg));
+	if (err)
+		return err;
+
+	if (outarg.namelen > fc->name_max)
+		return -ENAMETOOLONG;
+
+	err = -EINVAL;
+	if (size != sizeof(outarg) + outarg.namelen + 1)
+		return -EINVAL;
+
+	buf = kzalloc(outarg.namelen + 1, GFP_KERNEL);
+	if (!buf)
+		return -ENOMEM;
+
+	name.name = buf;
+	name.len = outarg.namelen;
+	err = fuse_copy_one(cs, buf, outarg.namelen + 1);
+	if (err)
+		goto err;
+	fuse_copy_finish(cs);
+	buf[outarg.namelen] = 0;
+
+	down_read(&fc->killsb);
+	err = fuse_reverse_inval_entry(fc, outarg.parent, 0, &name, outarg.flags);
+	up_read(&fc->killsb);
+err:
+	kfree(buf);
+	return err;
+}
+
+static int fuse_notify_delete(struct fuse_conn *fc, unsigned int size,
+			      struct fuse_copy_state *cs)
+{
+	struct fuse_notify_delete_out outarg;
+	int err;
+	char *buf;
+	struct qstr name;
+
+	if (size < sizeof(outarg))
+		return -EINVAL;
+
+	err = fuse_copy_one(cs, &outarg, sizeof(outarg));
+	if (err)
+		return err;
+
+	if (outarg.namelen > fc->name_max)
+		return -ENAMETOOLONG;
+
+	if (size != sizeof(outarg) + outarg.namelen + 1)
+		return -EINVAL;
+
+	buf = kzalloc(outarg.namelen + 1, GFP_KERNEL);
+	if (!buf)
+		return -ENOMEM;
+
+	name.name = buf;
+	name.len = outarg.namelen;
+	err = fuse_copy_one(cs, buf, outarg.namelen + 1);
+	if (err)
+		goto err;
+	fuse_copy_finish(cs);
+	buf[outarg.namelen] = 0;
+
+	down_read(&fc->killsb);
+	err = fuse_reverse_inval_entry(fc, outarg.parent, outarg.child, &name, 0);
+	up_read(&fc->killsb);
+err:
+	kfree(buf);
+	return err;
+}
+
+static int fuse_notify_store(struct fuse_conn *fc, unsigned int size,
+			     struct fuse_copy_state *cs)
+{
+	struct fuse_notify_store_out outarg;
+	struct inode *inode;
+	struct address_space *mapping;
+	u64 nodeid;
+	int err;
+	unsigned int num;
+	loff_t file_size;
+	loff_t pos;
+	loff_t end;
+
+	if (size < sizeof(outarg))
+		return -EINVAL;
+
+	err = fuse_copy_one(cs, &outarg, sizeof(outarg));
+	if (err)
+		return err;
+
+	if (size - sizeof(outarg) != outarg.size)
+		return -EINVAL;
+
+	if (outarg.offset >= MAX_LFS_FILESIZE)
+		return -EINVAL;
+
+	nodeid = outarg.nodeid;
+	pos = outarg.offset;
+	num = min(outarg.size, MAX_LFS_FILESIZE - pos);
+
+	down_read(&fc->killsb);
+
+	err = -ENOENT;
+	inode = fuse_ilookup(fc, nodeid,  NULL);
+	if (!inode)
+		goto out_up_killsb;
+
+	mapping = inode->i_mapping;
+	file_size = i_size_read(inode);
+	end = pos + num;
+	if (end > file_size) {
+		file_size = end;
+		fuse_write_update_attr(inode, file_size, num);
+	}
+
+	while (num) {
+		struct folio *folio;
+		unsigned int folio_offset;
+		unsigned int nr_bytes;
+		pgoff_t index = pos >> PAGE_SHIFT;
+
+		folio = filemap_grab_folio(mapping, index);
+		err = PTR_ERR(folio);
+		if (IS_ERR(folio))
+			goto out_iput;
+
+		folio_offset = offset_in_folio(folio, pos);
+		nr_bytes = min(num, folio_size(folio) - folio_offset);
+
+		err = fuse_copy_folio(cs, &folio, folio_offset, nr_bytes, 0);
+		if (!folio_test_uptodate(folio) && !err && folio_offset == 0 &&
+		    (nr_bytes == folio_size(folio) || file_size == end)) {
+			folio_zero_segment(folio, nr_bytes, folio_size(folio));
+			folio_mark_uptodate(folio);
+		}
+		folio_unlock(folio);
+		folio_put(folio);
+
+		if (err)
+			goto out_iput;
+
+		pos += nr_bytes;
+		num -= nr_bytes;
+	}
+
+	err = 0;
+
+out_iput:
+	iput(inode);
+out_up_killsb:
+	up_read(&fc->killsb);
+	return err;
+}
+
+struct fuse_retrieve_args {
+	struct fuse_args_pages ap;
+	struct fuse_notify_retrieve_in inarg;
+};
+
+static void fuse_retrieve_end(struct fuse_args *args, int error)
+{
+	struct fuse_retrieve_args *ra =
+		container_of(args, typeof(*ra), ap.args);
+
+	release_pages(ra->ap.folios, ra->ap.num_folios);
+	kfree(ra);
+}
+
+static int fuse_retrieve(struct fuse_mount *fm, struct inode *inode,
+			 struct fuse_notify_retrieve_out *outarg)
+{
+	int err;
+	struct address_space *mapping = inode->i_mapping;
+	loff_t file_size;
+	unsigned int num;
+	unsigned int offset;
+	size_t total_len = 0;
+	unsigned int num_pages;
+	struct fuse_conn *fc = fm->fc;
+	struct fuse_retrieve_args *ra;
+	size_t args_size = sizeof(*ra);
+	struct fuse_args_pages *ap;
+	struct fuse_args *args;
+	loff_t pos = outarg->offset;
+
+	offset = offset_in_page(pos);
+	file_size = i_size_read(inode);
+
+	num = min(outarg->size, fc->max_write);
+	if (pos > file_size)
+		num = 0;
+	else if (num > file_size - pos)
+		num = file_size - pos;
+
+	num_pages = DIV_ROUND_UP(num + offset, PAGE_SIZE);
+	num_pages = min(num_pages, fc->max_pages);
+	num = min(num, num_pages << PAGE_SHIFT);
+
+	args_size += num_pages * (sizeof(ap->folios[0]) + sizeof(ap->descs[0]));
+
+	ra = kzalloc(args_size, GFP_KERNEL);
+	if (!ra)
+		return -ENOMEM;
+
+	ap = &ra->ap;
+	ap->folios = (void *) (ra + 1);
+	ap->descs = (void *) (ap->folios + num_pages);
+
+	args = &ap->args;
+	args->nodeid = outarg->nodeid;
+	args->opcode = FUSE_NOTIFY_REPLY;
+	args->in_numargs = 3;
+	args->in_pages = true;
+	args->end = fuse_retrieve_end;
+
+	while (num && ap->num_folios < num_pages) {
+		struct folio *folio;
+		unsigned int folio_offset;
+		unsigned int nr_bytes;
+		pgoff_t index = pos >> PAGE_SHIFT;
+
+		folio = filemap_get_folio(mapping, index);
+		if (IS_ERR(folio))
+			break;
+
+		folio_offset = offset_in_folio(folio, pos);
+		nr_bytes = min(folio_size(folio) - folio_offset, num);
+
+		ap->folios[ap->num_folios] = folio;
+		ap->descs[ap->num_folios].offset = folio_offset;
+		ap->descs[ap->num_folios].length = nr_bytes;
+		ap->num_folios++;
+
+		pos += nr_bytes;
+		num -= nr_bytes;
+		total_len += nr_bytes;
+	}
+	ra->inarg.offset = outarg->offset;
+	ra->inarg.size = total_len;
+	fuse_set_zero_arg0(args);
+	args->in_args[1].size = sizeof(ra->inarg);
+	args->in_args[1].value = &ra->inarg;
+	args->in_args[2].size = total_len;
+
+	err = fuse_simple_notify_reply(fm, args, outarg->notify_unique);
+	if (err)
+		fuse_retrieve_end(args, err);
+
+	return err;
+}
+
+static int fuse_notify_retrieve(struct fuse_conn *fc, unsigned int size,
+				struct fuse_copy_state *cs)
+{
+	struct fuse_notify_retrieve_out outarg;
+	struct fuse_mount *fm;
+	struct inode *inode;
+	u64 nodeid;
+	int err;
+
+	if (size != sizeof(outarg))
+		return -EINVAL;
+
+	err = fuse_copy_one(cs, &outarg, sizeof(outarg));
+	if (err)
+		return err;
+
+	fuse_copy_finish(cs);
+
+	if (outarg.offset >= MAX_LFS_FILESIZE)
+		return -EINVAL;
+
+	down_read(&fc->killsb);
+	err = -ENOENT;
+	nodeid = outarg.nodeid;
+
+	inode = fuse_ilookup(fc, nodeid, &fm);
+	if (inode) {
+		err = fuse_retrieve(fm, inode, &outarg);
+		iput(inode);
+	}
+	up_read(&fc->killsb);
+
+	return err;
+}
+
+static int fuse_notify_resend(struct fuse_conn *fc)
+{
+	fuse_chan_resend(fc->chan);
+	return 0;
+}
+
+/*
+ * Increments the fuse connection epoch.  This will result of dentries from
+ * previous epochs to be invalidated.  Additionally, if inval_wq is set, a work
+ * queue is scheduled to trigger the invalidation.
+ */
+static int fuse_notify_inc_epoch(struct fuse_conn *fc)
+{
+	atomic_inc(&fc->epoch);
+	if (inval_wq)
+		schedule_work(&fc->epoch_work);
+
+	return 0;
+}
+
+static int fuse_notify_prune(struct fuse_conn *fc, unsigned int size,
+			     struct fuse_copy_state *cs)
+{
+	struct fuse_notify_prune_out outarg;
+	const unsigned int batch = 512;
+	u64 *nodeids __free(kfree) = kmalloc(sizeof(u64) * batch, GFP_KERNEL);
+	unsigned int num, i;
+	int err;
+
+	if (!nodeids)
+		return -ENOMEM;
+
+	if (size < sizeof(outarg))
+		return -EINVAL;
+
+	err = fuse_copy_one(cs, &outarg, sizeof(outarg));
+	if (err)
+		return err;
+
+	if (size - sizeof(outarg) != outarg.count * sizeof(u64))
+		return -EINVAL;
+
+	for (; outarg.count; outarg.count -= num) {
+		num = min(batch, outarg.count);
+		err = fuse_copy_one(cs, nodeids, num * sizeof(u64));
+		if (err)
+			return err;
+
+		scoped_guard(rwsem_read, &fc->killsb) {
+			for (i = 0; i < num; i++)
+				fuse_try_prune_one_inode(fc, nodeids[i]);
+		}
+	}
+	return 0;
+}
+
+int fuse_notify(struct fuse_conn *fc, enum fuse_notify_code code,
+		unsigned int size, struct fuse_copy_state *cs)
+{
+	switch (code) {
+	case FUSE_NOTIFY_POLL:
+		return fuse_notify_poll(fc, size, cs);
+
+	case FUSE_NOTIFY_INVAL_INODE:
+		return fuse_notify_inval_inode(fc, size, cs);
+
+	case FUSE_NOTIFY_INVAL_ENTRY:
+		return fuse_notify_inval_entry(fc, size, cs);
+
+	case FUSE_NOTIFY_STORE:
+		return fuse_notify_store(fc, size, cs);
+
+	case FUSE_NOTIFY_RETRIEVE:
+		return fuse_notify_retrieve(fc, size, cs);
+
+	case FUSE_NOTIFY_DELETE:
+		return fuse_notify_delete(fc, size, cs);
+
+	case FUSE_NOTIFY_RESEND:
+		return fuse_notify_resend(fc);
+
+	case FUSE_NOTIFY_INC_EPOCH:
+		return fuse_notify_inc_epoch(fc);
+
+	case FUSE_NOTIFY_PRUNE:
+		return fuse_notify_prune(fc, size, cs);
+
+	default:
+		return -EINVAL;
+	}
+}
diff --git a/fs/fuse/poll.c b/fs/fuse/poll.c
new file mode 100644
index 000000000000..bce3ee2e861e
--- /dev/null
+++ b/fs/fuse/poll.c
@@ -0,0 +1,141 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include "dev.h"
+#include "fuse_i.h"
+
+void fuse_end_polls(struct fuse_conn *fc)
+{
+	struct rb_node *p;
+
+	spin_lock(&fc->lock);
+	p = rb_first(&fc->polled_files);
+
+	while (p) {
+		struct fuse_file *ff;
+		ff = rb_entry(p, struct fuse_file, polled_node);
+		wake_up_interruptible_all(&ff->poll_wait);
+
+		p = rb_next(p);
+	}
+	spin_unlock(&fc->lock);
+}
+
+/*
+ * All files which have been polled are linked to RB tree
+ * fuse_conn->polled_files which is indexed by kh.  Walk the tree and
+ * find the matching one.
+ */
+static struct rb_node **fuse_find_polled_node(struct fuse_conn *fc, u64 kh,
+					      struct rb_node **parent_out)
+{
+	struct rb_node **link = &fc->polled_files.rb_node;
+	struct rb_node *last = NULL;
+
+	while (*link) {
+		struct fuse_file *ff;
+
+		last = *link;
+		ff = rb_entry(last, struct fuse_file, polled_node);
+
+		if (kh < ff->kh)
+			link = &last->rb_left;
+		else if (kh > ff->kh)
+			link = &last->rb_right;
+		else
+			return link;
+	}
+
+	if (parent_out)
+		*parent_out = last;
+	return link;
+}
+
+/*
+ * The file is about to be polled.  Make sure it's on the polled_files
+ * RB tree.  Note that files once added to the polled_files tree are
+ * not removed before the file is released.  This is because a file
+ * polled once is likely to be polled again.
+ */
+static void fuse_register_polled_file(struct fuse_conn *fc,
+				      struct fuse_file *ff)
+{
+	spin_lock(&fc->lock);
+	if (RB_EMPTY_NODE(&ff->polled_node)) {
+		struct rb_node **link, *parent;
+
+		link = fuse_find_polled_node(fc, ff->kh, &parent);
+		BUG_ON(*link);
+		rb_link_node(&ff->polled_node, parent, link);
+		rb_insert_color(&ff->polled_node, &fc->polled_files);
+	}
+	spin_unlock(&fc->lock);
+}
+
+__poll_t fuse_file_poll(struct file *file, poll_table *wait)
+{
+	struct fuse_file *ff = file->private_data;
+	struct fuse_mount *fm = ff->fm;
+	struct fuse_poll_in inarg = { .fh = ff->fh, .kh = ff->kh };
+	struct fuse_poll_out outarg;
+	FUSE_ARGS(args);
+	int err;
+
+	if (fm->fc->no_poll)
+		return DEFAULT_POLLMASK;
+
+	poll_wait(file, &ff->poll_wait, wait);
+	inarg.events = mangle_poll(poll_requested_events(wait));
+
+	/*
+	 * Ask for notification iff there's someone waiting for it.
+	 * The client may ignore the flag and always notify.
+	 */
+	if (waitqueue_active(&ff->poll_wait)) {
+		inarg.flags |= FUSE_POLL_SCHEDULE_NOTIFY;
+		fuse_register_polled_file(fm->fc, ff);
+	}
+
+	args.opcode = FUSE_POLL;
+	args.nodeid = ff->nodeid;
+	args.in_numargs = 1;
+	args.in_args[0].size = sizeof(inarg);
+	args.in_args[0].value = &inarg;
+	args.out_numargs = 1;
+	args.out_args[0].size = sizeof(outarg);
+	args.out_args[0].value = &outarg;
+	err = fuse_simple_request(fm, &args);
+
+	if (!err)
+		return demangle_poll(outarg.revents);
+	if (err == -ENOSYS) {
+		fm->fc->no_poll = 1;
+		return DEFAULT_POLLMASK;
+	}
+	return EPOLLERR;
+}
+EXPORT_SYMBOL_GPL(fuse_file_poll);
+
+/*
+ * This is called from fuse_handle_notify() on FUSE_NOTIFY_POLL and
+ * wakes up the poll waiters.
+ */
+int fuse_notify_poll_wakeup(struct fuse_conn *fc,
+			    struct fuse_notify_poll_wakeup_out *outarg)
+{
+	u64 kh = outarg->kh;
+	struct rb_node **link;
+
+	spin_lock(&fc->lock);
+
+	link = fuse_find_polled_node(fc, kh, NULL);
+	if (*link) {
+		struct fuse_file *ff;
+
+		ff = rb_entry(*link, struct fuse_file, polled_node);
+		wake_up_interruptible_sync(&ff->poll_wait);
+	}
+
+	spin_unlock(&fc->lock);
+	return 0;
+}
+
diff --git a/fs/fuse/req.c b/fs/fuse/req.c
new file mode 100644
index 000000000000..a01ee743d31e
--- /dev/null
+++ b/fs/fuse/req.c
@@ -0,0 +1,99 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include "dev.h"
+#include "fuse_i.h"
+
+static int fuse_fill_creds(struct fuse_mount *fm, struct fuse_args *args, struct mnt_idmap *idmap)
+{
+	struct fuse_conn *fc = fm->fc;
+	bool no_idmap = !fm->sb || (fm->sb->s_iflags & SB_I_NOIDMAP);
+	kuid_t fsuid = mapped_fsuid(idmap, fc->user_ns);
+	kgid_t fsgid = mapped_fsgid(idmap, fc->user_ns);
+
+	args->pid = pid_nr_ns(task_pid(current), fc->pid_ns);
+
+	if (args->force) {
+		if (args->nocreds)
+			return 0;
+
+		if (no_idmap) {
+			args->uid = from_kuid_munged(fc->user_ns, current_fsuid());
+			args->gid = from_kgid_munged(fc->user_ns, current_fsgid());
+		} else {
+			args->uid = FUSE_INVALID_UIDGID;
+			args->gid = FUSE_INVALID_UIDGID;
+		}
+		return 0;
+	}
+
+	WARN_ON(args->nocreds);
+	/*
+	 * Keep the old behavior when idmappings support was not
+	 * declared by a FUSE server.
+	 *
+	 * For those FUSE servers who support idmapped mounts, we send UID/GID
+	 * only along with "inode creation" fuse requests, otherwise idmap ==
+	 * &invalid_mnt_idmap and req->in.h.{u,g}id will be equal to
+	 * FUSE_INVALID_UIDGID.
+	 */
+	if (no_idmap) {
+		fsuid = current_fsuid();
+		fsgid = current_fsgid();
+	}
+	args->uid = from_kuid(fc->user_ns, fsuid);
+	args->gid = from_kgid(fc->user_ns, fsgid);
+
+	if (no_idmap && unlikely(args->uid == ((uid_t)-1) || args->gid == ((gid_t)-1)))
+		return -EOVERFLOW;
+
+	return 0;
+}
+
+static int fuse_req_prep(struct fuse_mount *fm, struct fuse_args *args, struct mnt_idmap *idmap)
+{
+	if (!args->force && fm->fc->conn_error)
+		return -ECONNREFUSED;
+
+	return fuse_fill_creds(fm, args, idmap);
+}
+
+ssize_t __fuse_simple_request(struct mnt_idmap *idmap, struct fuse_mount *fm,
+			      struct fuse_args *args)
+{
+	struct fuse_conn *fc = fm->fc;
+	int err = fuse_req_prep(fm, args, idmap);
+
+	if (err)
+		return err;
+
+	return fuse_chan_send(fc->chan, args);
+}
+
+int fuse_simple_background(struct fuse_mount *fm, struct fuse_args *args, gfp_t gfp_flags)
+{
+	struct fuse_conn *fc = fm->fc;
+	int err;
+
+	WARN_ON(args->force && !args->nocreds);
+
+	err = fuse_req_prep(fm, args, &invalid_mnt_idmap);
+	if (err)
+		return err;
+
+	return fuse_chan_send_bg(fc->chan, args, gfp_flags);
+}
+EXPORT_SYMBOL_GPL(fuse_simple_background);
+
+int fuse_simple_notify_reply(struct fuse_mount *fm, struct fuse_args *args, u64 unique)
+{
+	struct fuse_conn *fc = fm->fc;
+	int err;
+
+	WARN_ON(args->force && !args->nocreds);
+
+	err = fuse_req_prep(fm, args, &invalid_mnt_idmap);
+	if (err)
+		return err;
+
+	return fuse_chan_send_notify_reply(fc->chan, args, unique);
+}
diff --git a/fs/fuse/req_timeout.c b/fs/fuse/req_timeout.c
new file mode 100644
index 000000000000..6cc6fc491343
--- /dev/null
+++ b/fs/fuse/req_timeout.c
@@ -0,0 +1,148 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include "dev.h"
+#include "sysctl.h"
+#include "fuse_dev_i.h"
+#include "dev_uring_i.h"
+
+/* Frequency (in seconds) of request timeout checks, if opted into */
+#define FUSE_TIMEOUT_TIMER_FREQ 15
+
+/* Frequency (in jiffies) of request timeout checks, if opted into */
+static const unsigned long fuse_timeout_timer_freq =
+	secs_to_jiffies(FUSE_TIMEOUT_TIMER_FREQ);
+
+/*
+ * Default timeout (in seconds) for the server to reply to a request
+ * before the connection is aborted, if no timeout was specified on mount.
+ *
+ * Exported via sysctl
+ */
+unsigned int fuse_default_req_timeout;
+
+/*
+ * Max timeout (in seconds) for the server to reply to a request before
+ * the connection is aborted.
+ *
+ * Exported via sysctl
+ */
+unsigned int fuse_max_req_timeout;
+
+bool fuse_request_expired(struct fuse_chan *fch, struct list_head *list)
+{
+	struct fuse_req *req;
+
+	req = list_first_entry_or_null(list, struct fuse_req, list);
+	if (!req)
+		return false;
+	return time_is_before_jiffies(req->create_time + fch->timeout.req_timeout);
+}
+
+static bool fuse_fpq_processing_expired(struct fuse_chan *fch, struct list_head *processing)
+{
+	int i;
+
+	for (i = 0; i < FUSE_PQ_HASH_SIZE; i++)
+		if (fuse_request_expired(fch, &processing[i]))
+			return true;
+
+	return false;
+}
+
+/*
+ * Check if any requests aren't being completed by the time the request timeout
+ * elapses. To do so, we:
+ * - check the fiq pending list
+ * - check the bg queue
+ * - check the fpq io and processing lists
+ *
+ * To make this fast, we only check against the head request on each list since
+ * these are generally queued in order of creation time (eg newer requests get
+ * queued to the tail). We might miss a few edge cases (eg requests transitioning
+ * between lists, re-sent requests at the head of the pending list having a
+ * later creation time than other requests on that list, etc.) but that is fine
+ * since if the request never gets fulfilled, it will eventually be caught.
+ */
+static void fuse_check_timeout(struct work_struct *work)
+{
+	struct delayed_work *dwork = to_delayed_work(work);
+	struct fuse_chan *fch = container_of(dwork, struct fuse_chan, timeout.work);
+	struct fuse_iqueue *fiq = &fch->iq;
+	struct fuse_dev *fud;
+	struct fuse_pqueue *fpq;
+	bool expired = false;
+
+	if (!atomic_read(&fch->num_waiting))
+		goto out;
+
+	spin_lock(&fiq->lock);
+	expired = fuse_request_expired(fch, &fiq->pending);
+	spin_unlock(&fiq->lock);
+	if (expired)
+		goto chan_abort;
+
+	spin_lock(&fch->bg_lock);
+	expired = fuse_request_expired(fch, &fch->bg_queue);
+	spin_unlock(&fch->bg_lock);
+	if (expired)
+		goto chan_abort;
+
+	spin_lock(&fch->lock);
+	if (!fch->connected) {
+		spin_unlock(&fch->lock);
+		return;
+	}
+	list_for_each_entry(fud, &fch->devices, entry) {
+		fpq = &fud->pq;
+		spin_lock(&fpq->lock);
+		if (fuse_request_expired(fch, &fpq->io) ||
+		    fuse_fpq_processing_expired(fch, fpq->processing)) {
+			spin_unlock(&fpq->lock);
+			spin_unlock(&fch->lock);
+			goto chan_abort;
+		}
+
+		spin_unlock(&fpq->lock);
+	}
+	spin_unlock(&fch->lock);
+
+	if (fuse_uring_request_expired(fch))
+		goto chan_abort;
+
+out:
+	queue_delayed_work(system_percpu_wq, &fch->timeout.work,
+			   fuse_timeout_timer_freq);
+	return;
+
+chan_abort:
+	fuse_chan_abort(fch, false);
+}
+
+static void set_request_timeout(struct fuse_chan *fch, unsigned int timeout)
+{
+	fch->timeout.req_timeout = secs_to_jiffies(timeout);
+	INIT_DELAYED_WORK(&fch->timeout.work, fuse_check_timeout);
+	queue_delayed_work(system_percpu_wq, &fch->timeout.work,
+			   fuse_timeout_timer_freq);
+}
+
+void fuse_init_server_timeout(struct fuse_chan *fch, unsigned int timeout)
+{
+	if (!timeout && !fuse_max_req_timeout && !fuse_default_req_timeout)
+		return;
+
+	if (!timeout)
+		timeout = fuse_default_req_timeout;
+
+	if (fuse_max_req_timeout) {
+		if (timeout)
+			timeout = min(fuse_max_req_timeout, timeout);
+		else
+			timeout = fuse_max_req_timeout;
+	}
+
+	timeout = max(FUSE_TIMEOUT_TIMER_FREQ, timeout);
+
+	set_request_timeout(fch, timeout);
+}
+
diff --git a/fs/fuse/sysctl.c b/fs/fuse/sysctl.c
index e2d921abcb88..74eca5ce9a2c 100644
--- a/fs/fuse/sysctl.c
+++ b/fs/fuse/sysctl.c
@@ -6,6 +6,7 @@
  */
 #include <linux/sysctl.h>
 
+#include "sysctl.h"
 #include "fuse_i.h"
 
 static struct ctl_table_header *fuse_table_header;
diff --git a/fs/fuse/sysctl.h b/fs/fuse/sysctl.h
new file mode 100644
index 000000000000..948d88417133
--- /dev/null
+++ b/fs/fuse/sysctl.h
@@ -0,0 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifndef _FS_FUSE_SYSCTL_H
+#define _FS_FUSE_SYSCTL_H
+
+extern unsigned int fuse_default_req_timeout;
+extern unsigned int fuse_max_req_timeout;
+
+#endif /* _FS_FUSE_SYSCTL_H */
diff --git a/fs/fuse/virtio_fs.c b/fs/fuse/virtio_fs.c
index 12300651a0f1..a4cf813cebfc 100644
--- a/fs/fuse/virtio_fs.c
+++ b/fs/fuse/virtio_fs.c
@@ -19,6 +19,7 @@
 #include <linux/highmem.h>
 #include <linux/cleanup.h>
 #include <linux/uio.h>
+#include "dev.h"
 #include "fuse_i.h"
 #include "fuse_dev_i.h"
 
@@ -1519,7 +1520,7 @@ static void virtio_fs_send_req(struct fuse_iqueue *fiq, struct fuse_req *req)
 		if (ret == -ENOSPC) {
 			/*
 			 * Virtqueue full. Retry submission from worker
-			 * context as we might be holding fc->bg_lock.
+			 * context as we might be holding fc->chan->bg_lock.
 			 */
 			spin_lock(&fsvq->lock);
 			list_add_tail(&req->list, &fsvq->queued_reqs);
@@ -1562,7 +1563,7 @@ static int virtio_fs_fill_super(struct super_block *sb, struct fs_context *fsc)
 {
 	struct fuse_mount *fm = get_fuse_mount_super(sb);
 	struct fuse_conn *fc = fm->fc;
-	struct virtio_fs *fs = fc->iq.priv;
+	struct virtio_fs *fs = fc->chan->iq.priv;
 	struct fuse_fs_context *ctx = fsc->fs_private;
 	unsigned int i;
 	int err;
@@ -1606,7 +1607,7 @@ static int virtio_fs_fill_super(struct super_block *sb, struct fs_context *fsc)
 	for (i = 0; i < fs->nvqs; i++) {
 		struct virtio_fs_vq *fsvq = &fs->vqs[i];
 
-		fuse_dev_install(fsvq->fud, fc);
+		fuse_dev_install(fsvq->fud, fc->chan);
 	}
 
 	/* Previous unmount will stop all queues. Start these again */
@@ -1625,7 +1626,7 @@ static int virtio_fs_fill_super(struct super_block *sb, struct fs_context *fsc)
 static void virtio_fs_conn_destroy(struct fuse_mount *fm)
 {
 	struct fuse_conn *fc = fm->fc;
-	struct virtio_fs *vfs = fc->iq.priv;
+	struct virtio_fs *vfs = fc->chan->iq.priv;
 	struct virtio_fs_vq *fsvq = &vfs->vqs[VQ_HIPRIO];
 
 	/* Stop dax worker. Soon evict_inodes() will be called which
@@ -1673,7 +1674,7 @@ static int virtio_fs_test_super(struct super_block *sb,
 	struct fuse_mount *fsc_fm = fsc->s_fs_info;
 	struct fuse_mount *sb_fm = get_fuse_mount_super(sb);
 
-	return fsc_fm->fc->iq.priv == sb_fm->fc->iq.priv;
+	return fsc_fm->fc->chan->iq.priv == sb_fm->fc->chan->iq.priv;
 }
 
 static int virtio_fs_get_tree(struct fs_context *fsc)
@@ -1683,13 +1684,17 @@ static int virtio_fs_get_tree(struct fs_context *fsc)
 	struct fuse_conn *fc = NULL;
 	struct fuse_mount *fm;
 	unsigned int virtqueue_size;
+	struct fuse_chan *fch __free(fuse_chan_free) = fuse_chan_new();
 	int err = -EIO;
 
+	if (!fch)
+		return -ENOMEM;
+
 	if (!fsc->source)
 		return invalf(fsc, "No source specified");
 
 	/* This gets a reference on virtio_fs object. This ptr gets installed
-	 * in fc->iq->priv. Once fuse_conn is going away, it calls ->put()
+	 * in chan->iq->priv. Once fuse_conn is going away, it calls ->put()
 	 * to drop the reference to this object.
 	 */
 	fs = virtio_fs_find_instance(fsc->source);
@@ -1711,7 +1716,9 @@ static int virtio_fs_get_tree(struct fs_context *fsc)
 	if (!fm)
 		goto out_err;
 
-	fuse_conn_init(fc, fm, fsc->user_ns, &virtio_fs_fiq_ops, fs);
+	fuse_iqueue_init(&fch->iq, &virtio_fs_fiq_ops, fs);
+	fuse_conn_init(fc, fm, fsc->user_ns, no_free_ptr(fch));
+
 	fc->release = fuse_free_conn;
 	fc->delete_stale = true;
 	fc->auto_submounts = true;
diff --git a/fs/isofs/export.c b/fs/isofs/export.c
index 421d247fae52..78f80c1a5c54 100644
--- a/fs/isofs/export.c
+++ b/fs/isofs/export.c
@@ -24,7 +24,7 @@ isofs_export_iget(struct super_block *sb,
 {
 	struct inode *inode;
 
-	if (block == 0)
+	if (block == 0 || block >= ISOFS_SB(sb)->s_nzones)
 		return ERR_PTR(-ESTALE);
 	inode = isofs_iget(sb, block, offset);
 	if (IS_ERR(inode))
diff --git a/fs/isofs/namei.c b/fs/isofs/namei.c
index 8dd3911717e0..3ace3d6a55e7 100644
--- a/fs/isofs/namei.c
+++ b/fs/isofs/namei.c
@@ -10,20 +10,13 @@
 #include <linux/gfp.h>
 #include "isofs.h"
 
-/*
- * ok, we cannot use strncmp, as the name is not in our data space.
- * Thus we'll have to use isofs_match. No big problem. Match also makes
- * some sanity tests.
- */
 static int
 isofs_cmp(struct dentry *dentry, const char *compare, int dlen)
 {
-	struct qstr qstr;
-	qstr.name = compare;
-	qstr.len = dlen;
 	if (likely(!dentry->d_op))
 		return dentry->d_name.len != dlen || memcmp(dentry->d_name.name, compare, dlen);
-	return dentry->d_op->d_compare(NULL, dentry->d_name.len, dentry->d_name.name, &qstr);
+	return dentry->d_op->d_compare(NULL, dentry->d_name.len, dentry->d_name.name,
+				       &QSTR_LEN(compare, dlen));
 }
 
 /*
diff --git a/fs/isofs/rock.c b/fs/isofs/rock.c
index 6fe6dbd0c740..1232fab59a4e 100644
--- a/fs/isofs/rock.c
+++ b/fs/isofs/rock.c
@@ -101,6 +101,15 @@ static int rock_continue(struct rock_state *rs)
 		goto out;
 	}
 
+	if ((unsigned)rs->cont_extent >= ISOFS_SB(rs->inode->i_sb)->s_nzones) {
+		printk(KERN_NOTICE "rock: corrupted directory entry. "
+			"extent=%u out of volume (nzones=%lu)\n",
+			(unsigned)rs->cont_extent,
+			ISOFS_SB(rs->inode->i_sb)->s_nzones);
+		ret = -EIO;
+		goto out;
+	}
+
 	if (rs->cont_extent) {
 		struct buffer_head *bh;
 
diff --git a/fs/netfs/buffered_read.c b/fs/netfs/buffered_read.c
index a8c0d86118c5..c23173a061e8 100644
--- a/fs/netfs/buffered_read.c
+++ b/fs/netfs/buffered_read.c
@@ -397,6 +397,7 @@ static int netfs_read_gaps(struct file *file, struct folio *folio)
 {
 	struct netfs_io_request *rreq;
 	struct address_space *mapping = folio->mapping;
+	struct netfs_group *group = netfs_folio_group(folio);
 	struct netfs_folio *finfo = netfs_folio_info(folio);
 	struct netfs_inode *ctx = netfs_inode(mapping->host);
 	struct folio *sink = NULL;
@@ -463,6 +464,10 @@ static int netfs_read_gaps(struct file *file, struct folio *folio)
 
 	ret = netfs_wait_for_read(rreq);
 	if (ret >= 0) {
+		folio_detach_private(folio);
+		netfs_put_group(group);
+		kfree(finfo);
+		trace_netfs_folio(folio, netfs_folio_trace_filled_gaps);
 		flush_dcache_folio(folio);
 		folio_mark_uptodate(folio);
 	}
@@ -498,10 +503,8 @@ int netfs_read_folio(struct file *file, struct folio *folio)
 	struct netfs_inode *ctx = netfs_inode(mapping->host);
 	int ret;
 
-	if (folio_test_dirty(folio)) {
-		trace_netfs_folio(folio, netfs_folio_trace_read_gaps);
+	if (folio_test_dirty(folio))
 		return netfs_read_gaps(file, folio);
-	}
 
 	_enter("%lx", folio->index);
 
diff --git a/fs/netfs/buffered_write.c b/fs/netfs/buffered_write.c
index 05ea5b0cc0e8..7b9e24cd30ac 100644
--- a/fs/netfs/buffered_write.c
+++ b/fs/netfs/buffered_write.c
@@ -245,18 +245,34 @@ ssize_t netfs_perform_write(struct kiocb *iocb, struct iov_iter *iter,
 		/* See if we can write a whole folio in one go. */
 		if (!maybe_trouble && offset == 0 && part >= flen) {
 			copied = copy_folio_from_iter_atomic(folio, offset, part, iter);
-			if (unlikely(copied == 0))
+			if (likely(copied == part)) {
+				if (finfo)
+					goto folio_now_filled;
+				__netfs_set_group(folio, netfs_group);
+				folio_mark_uptodate(folio);
+				trace_netfs_folio(folio, netfs_whole_folio_modify);
+				goto copied;
+			}
+			if (copied == 0)
 				goto copy_failed;
-			if (unlikely(copied < part)) {
+			if (!finfo || copied <= finfo->dirty_offset) {
 				maybe_trouble = true;
 				iov_iter_revert(iter, copied);
 				copied = 0;
 				folio_unlock(folio);
 				goto retry;
 			}
-			__netfs_set_group(folio, netfs_group);
-			folio_mark_uptodate(folio);
-			trace_netfs_folio(folio, netfs_whole_folio_modify);
+
+			/* We overwrote some existing dirty data, so we have to
+			 * accept the partial write.
+			 */
+			finfo->dirty_len += finfo->dirty_offset;
+			if (finfo->dirty_len == flen)
+				goto folio_now_filled;
+			if (copied > finfo->dirty_len)
+				finfo->dirty_len = copied;
+			finfo->dirty_offset = 0;
+			trace_netfs_folio(folio, netfs_whole_folio_modify_efault);
 			goto copied;
 		}
 
@@ -266,8 +282,7 @@ ssize_t netfs_perform_write(struct kiocb *iocb, struct iov_iter *iter,
 		 * a file that's open for reading as ->read_folio() then has to
 		 * be able to flush it.
 		 */
-		if ((file->f_mode & FMODE_READ) ||
-		    netfs_is_cache_enabled(ctx)) {
+		if (netfs_is_cache_enabled(ctx)) {
 			if (finfo) {
 				netfs_stat(&netfs_n_wh_wstream_conflict);
 				goto flush_content;
@@ -325,17 +340,9 @@ ssize_t netfs_perform_write(struct kiocb *iocb, struct iov_iter *iter,
 			if (unlikely(copied == 0))
 				goto copy_failed;
 			finfo->dirty_len += copied;
-			if (finfo->dirty_offset == 0 && finfo->dirty_len == flen) {
-				if (finfo->netfs_group)
-					folio_change_private(folio, finfo->netfs_group);
-				else
-					folio_detach_private(folio);
-				folio_mark_uptodate(folio);
-				kfree(finfo);
-				trace_netfs_folio(folio, netfs_streaming_cont_filled_page);
-			} else {
-				trace_netfs_folio(folio, netfs_streaming_write_cont);
-			}
+			if (finfo->dirty_offset == 0 && finfo->dirty_len == flen)
+				goto folio_now_filled;
+			trace_netfs_folio(folio, netfs_streaming_write_cont);
 			goto copied;
 		}
 
@@ -349,6 +356,14 @@ ssize_t netfs_perform_write(struct kiocb *iocb, struct iov_iter *iter,
 			goto out;
 		continue;
 
+	folio_now_filled:
+		if (finfo->netfs_group)
+			folio_change_private(folio, finfo->netfs_group);
+		else
+			folio_detach_private(folio);
+		folio_mark_uptodate(folio);
+		kfree(finfo);
+		trace_netfs_folio(folio, netfs_streaming_cont_filled_page);
 	copied:
 		flush_dcache_folio(folio);
 
diff --git a/fs/netfs/iterator.c b/fs/netfs/iterator.c
index 154a14bb2d7f..adca78747f23 100644
--- a/fs/netfs/iterator.c
+++ b/fs/netfs/iterator.c
@@ -22,7 +22,7 @@
  *
  * Extract the page fragments from the given amount of the source iterator and
  * build up a second iterator that refers to all of those bits.  This allows
- * the original iterator to disposed of.
+ * the original iterator to be disposed of.
  *
  * @extraction_flags can have ITER_ALLOW_P2PDMA set to request peer-to-peer DMA be
  * allowed on the pages extracted.
@@ -67,8 +67,8 @@ ssize_t netfs_extract_user_iter(struct iov_iter *orig, size_t orig_len,
 		ret = iov_iter_extract_pages(orig, &pages, count,
 					     max_pages - npages, extraction_flags,
 					     &offset);
-		if (ret < 0) {
-			pr_err("Couldn't get user pages (rc=%zd)\n", ret);
+		if (unlikely(ret <= 0)) {
+			ret = ret ?: -EIO;
 			break;
 		}
 
@@ -97,6 +97,13 @@ ssize_t netfs_extract_user_iter(struct iov_iter *orig, size_t orig_len,
 		npages += cur_npages;
 	}
 
+	if (ret < 0 && (ret == -ENOMEM || npages == 0)) {
+		for (i = 0; i < npages; i++)
+			unpin_user_page(bv[i].bv_page);
+		kvfree(bv);
+		return ret;
+	}
+
 	iov_iter_bvec(new, orig->data_source, bv, npages, orig_len - count);
 	return npages;
 }
diff --git a/fs/netfs/misc.c b/fs/netfs/misc.c
index 6df89c92b10b..e386cf31eb1e 100644
--- a/fs/netfs/misc.c
+++ b/fs/netfs/misc.c
@@ -256,6 +256,7 @@ void netfs_invalidate_folio(struct folio *folio, size_t offset, size_t length)
 			/* Move the start of the data. */
 			finfo->dirty_len = fend - iend;
 			finfo->dirty_offset = offset;
+			trace_netfs_folio(folio, netfs_folio_trace_invalidate_front);
 			return;
 		}
 
@@ -264,12 +265,14 @@ void netfs_invalidate_folio(struct folio *folio, size_t offset, size_t length)
 		 */
 		if (iend >= fend) {
 			finfo->dirty_len = offset - fstart;
+			trace_netfs_folio(folio, netfs_folio_trace_invalidate_tail);
 			return;
 		}
 
 		/* A partial write was split.  The caller has already zeroed
 		 * it, so just absorb the hole.
 		 */
+		trace_netfs_folio(folio, netfs_folio_trace_invalidate_middle);
 	}
 	return;
 
@@ -277,8 +280,9 @@ void netfs_invalidate_folio(struct folio *folio, size_t offset, size_t length)
 	netfs_put_group(netfs_folio_group(folio));
 	folio_detach_private(folio);
 	folio_clear_uptodate(folio);
+	folio_cancel_dirty(folio);
 	kfree(finfo);
-	return;
+	trace_netfs_folio(folio, netfs_folio_trace_invalidate_all);
 }
 EXPORT_SYMBOL(netfs_invalidate_folio);
 
@@ -298,7 +302,7 @@ bool netfs_release_folio(struct folio *folio, gfp_t gfp)
 	if (folio_test_dirty(folio))
 		return false;
 
-	end = umin(folio_next_pos(folio), i_size_read(&ctx->inode));
+	end = umin(folio_next_pos(folio), ctx->remote_i_size);
 	if (end > ctx->zero_point)
 		ctx->zero_point = end;
 
diff --git a/fs/netfs/read_retry.c b/fs/netfs/read_retry.c
index cca9ac43c077..68fc869513ef 100644
--- a/fs/netfs/read_retry.c
+++ b/fs/netfs/read_retry.c
@@ -288,8 +288,15 @@ void netfs_unlock_abandoned_read_pages(struct netfs_io_request *rreq)
 			struct folio *folio = folioq_folio(p, slot);
 
 			if (folio && !folioq_is_marked2(p, slot)) {
-				trace_netfs_folio(folio, netfs_folio_trace_abandon);
-				folio_unlock(folio);
+				if (folio->index == rreq->no_unlock_folio &&
+				    test_bit(NETFS_RREQ_NO_UNLOCK_FOLIO,
+					     &rreq->flags)) {
+					_debug("no unlock");
+				} else {
+					trace_netfs_folio(folio,
+						netfs_folio_trace_abandon);
+					folio_unlock(folio);
+				}
 			}
 		}
 	}
diff --git a/fs/nfs/dns_resolve.c b/fs/nfs/dns_resolve.c
index 2ed2126201f4..acd3511c04a6 100644
--- a/fs/nfs/dns_resolve.c
+++ b/fs/nfs/dns_resolve.c
@@ -156,7 +156,7 @@ static int nfs_dns_upcall(struct cache_detail *cd,
 	if (!nfs_cache_upcall(cd, key->hostname))
 		return 0;
 	clear_bit(CACHE_PENDING, &ch->flags);
-	return sunrpc_cache_pipe_upcall_timeout(cd, ch);
+	return sunrpc_cache_upcall_warn(cd, ch);
 }
 
 static int nfs_dns_match(struct cache_head *ca,
diff --git a/fs/nfsd/export.c b/fs/nfsd/export.c
index 665153f1720e..15972919e1e9 100644
--- a/fs/nfsd/export.c
+++ b/fs/nfsd/export.c
@@ -17,6 +17,8 @@
 #include <linux/module.h>
 #include <linux/exportfs.h>
 #include <linux/sunrpc/svc_xprt.h>
+#include <net/genetlink.h>
+#include <uapi/linux/nfsd_netlink.h>
 
 #include "nfsd.h"
 #include "nfsfh.h"
@@ -24,6 +26,7 @@
 #include "pnfs.h"
 #include "filecache.h"
 #include "trace.h"
+#include "netlink.h"
 
 #define NFSDDBG_FACILITY	NFSDDBG_EXPORT
 
@@ -64,7 +67,7 @@ static void expkey_put(struct kref *ref)
 
 static int expkey_upcall(struct cache_detail *cd, struct cache_head *h)
 {
-	return sunrpc_cache_pipe_upcall(cd, h);
+	return sunrpc_cache_upcall(cd, h);
 }
 
 static void expkey_request(struct cache_detail *cd,
@@ -263,12 +266,18 @@ static void expkey_flush(void)
 	mutex_unlock(&nfsd_mutex);
 }
 
+static int expkey_notify(struct cache_detail *cd, struct cache_head *h)
+{
+	return nfsd_cache_notify(cd, h, NFSD_CACHE_TYPE_EXPKEY);
+}
+
 static const struct cache_detail svc_expkey_cache_template = {
 	.owner		= THIS_MODULE,
 	.hash_size	= EXPKEY_HASHMAX,
 	.name		= "nfsd.fh",
 	.cache_put	= expkey_put,
 	.cache_upcall	= expkey_upcall,
+	.cache_notify	= expkey_notify,
 	.cache_request	= expkey_request,
 	.cache_parse	= expkey_parse,
 	.cache_show	= expkey_show,
@@ -319,6 +328,266 @@ svc_expkey_update(struct cache_detail *cd, struct svc_expkey *new,
 		return NULL;
 }
 
+/**
+ * nfsd_nl_expkey_get_reqs_dumpit - dump pending expkey requests
+ * @skb: reply buffer
+ * @cb: netlink metadata and command arguments
+ *
+ * Walk the expkey cache's pending request list and create a netlink
+ * message with a nested entry for each cache_request, containing the
+ * seqno, client string, fsidtype and fsid.
+ *
+ * Uses cb->args[0] as a seqno cursor for dump continuation across
+ * multiple netlink messages.
+ *
+ * Returns the size of the reply or a negative errno.
+ */
+int nfsd_nl_expkey_get_reqs_dumpit(struct sk_buff *skb,
+				   struct netlink_callback *cb)
+{
+	struct nfsd_net *nn;
+	struct cache_detail *cd;
+	struct cache_head **items;
+	u64 *seqnos;
+	int cnt, i, emitted;
+	void *hdr;
+	int ret;
+
+	nn = net_generic(sock_net(skb->sk), nfsd_net_id);
+
+	mutex_lock(&nfsd_mutex);
+
+	cd = nn->svc_expkey_cache;
+	if (!cd) {
+		ret = -ENODEV;
+		goto out_unlock;
+	}
+
+	cnt = sunrpc_cache_requests_count(cd);
+	if (!cnt) {
+		ret = 0;
+		goto out_unlock;
+	}
+
+	items = kcalloc(cnt, sizeof(*items), GFP_KERNEL);
+	seqnos = kcalloc(cnt, sizeof(*seqnos), GFP_KERNEL);
+	if (!items || !seqnos) {
+		ret = -ENOMEM;
+		goto out_alloc;
+	}
+
+	cnt = sunrpc_cache_requests_snapshot(cd, items, seqnos, cnt,
+					     cb->args[0]);
+	if (!cnt) {
+		ret = 0;
+		goto out_alloc;
+	}
+
+	hdr = genlmsg_put(skb, NETLINK_CB(cb->skb).portid,
+			  cb->nlh->nlmsg_seq, &nfsd_nl_family,
+			  NLM_F_MULTI, NFSD_CMD_EXPKEY_GET_REQS);
+	if (!hdr) {
+		ret = -ENOBUFS;
+		goto out_put;
+	}
+
+	emitted = 0;
+	for (i = 0; i < cnt; i++) {
+		struct svc_expkey *ek;
+		struct nlattr *nest;
+
+		ek = container_of(items[i], struct svc_expkey, h);
+
+		nest = nla_nest_start(skb, NFSD_A_EXPKEY_REQS_REQUESTS);
+		if (!nest)
+			break;
+
+		if (nla_put_u64_64bit(skb, NFSD_A_EXPKEY_SEQNO,
+				      seqnos[i], 0) ||
+		    nla_put_string(skb, NFSD_A_EXPKEY_CLIENT,
+				   ek->ek_client->name) ||
+		    nla_put_u8(skb, NFSD_A_EXPKEY_FSIDTYPE,
+			       ek->ek_fsidtype) ||
+		    nla_put(skb, NFSD_A_EXPKEY_FSID,
+			    key_len(ek->ek_fsidtype), ek->ek_fsid)) {
+			nla_nest_cancel(skb, nest);
+			break;
+		}
+
+		nla_nest_end(skb, nest);
+		cb->args[0] = seqnos[i];
+		emitted++;
+	}
+
+	if (!emitted) {
+		genlmsg_cancel(skb, hdr);
+		ret = -EMSGSIZE;
+		goto out_put;
+	}
+
+	genlmsg_end(skb, hdr);
+	ret = skb->len;
+out_put:
+	for (i = 0; i < cnt; i++)
+		cache_put(items[i], cd);
+out_alloc:
+	kfree(seqnos);
+	kfree(items);
+out_unlock:
+	mutex_unlock(&nfsd_mutex);
+	return ret;
+}
+
+/**
+ * nfsd_nl_parse_one_expkey - parse one expkey entry from netlink
+ * @cd: cache_detail for the expkey cache
+ * @attr: nested attribute containing expkey fields
+ *
+ * Parses one expkey entry from a netlink message and updates the
+ * cache. Mirrors the logic in expkey_parse().
+ *
+ * Returns 0 on success or a negative errno.
+ */
+static int nfsd_nl_parse_one_expkey(struct cache_detail *cd,
+				    struct nlattr *attr)
+{
+	struct nlattr *tb[NFSD_A_EXPKEY_PATH + 1];
+	struct auth_domain *dom = NULL;
+	struct svc_expkey key;
+	struct svc_expkey *ek = NULL;
+	struct timespec64 boot;
+	int err;
+	u8 fsidtype;
+	int fsid_len;
+
+	err = nla_parse_nested(tb, NFSD_A_EXPKEY_PATH, attr,
+			       nfsd_expkey_nl_policy, NULL);
+	if (err)
+		return err;
+
+	/* client (required) */
+	if (!tb[NFSD_A_EXPKEY_CLIENT])
+		return -EINVAL;
+
+	dom = auth_domain_find(nla_data(tb[NFSD_A_EXPKEY_CLIENT]));
+	if (!dom)
+		return -ENOENT;
+
+	/* fsidtype (required) */
+	if (!tb[NFSD_A_EXPKEY_FSIDTYPE]) {
+		err = -EINVAL;
+		goto out_dom;
+	}
+	fsidtype = nla_get_u8(tb[NFSD_A_EXPKEY_FSIDTYPE]);
+	if (key_len(fsidtype) == 0) {
+		err = -EINVAL;
+		goto out_dom;
+	}
+
+	/* fsid (required) */
+	if (!tb[NFSD_A_EXPKEY_FSID]) {
+		err = -EINVAL;
+		goto out_dom;
+	}
+	fsid_len = nla_len(tb[NFSD_A_EXPKEY_FSID]);
+	if (fsid_len != key_len(fsidtype)) {
+		err = -EINVAL;
+		goto out_dom;
+	}
+
+	/* expiry (required, wallclock seconds) */
+	if (!tb[NFSD_A_EXPKEY_EXPIRY]) {
+		err = -EINVAL;
+		goto out_dom;
+	}
+
+	key.h.flags = 0;
+	getboottime64(&boot);
+	key.h.expiry_time = nla_get_u64(tb[NFSD_A_EXPKEY_EXPIRY]) -
+			    boot.tv_sec;
+	key.ek_client = dom;
+	key.ek_fsidtype = fsidtype;
+	memcpy(key.ek_fsid, nla_data(tb[NFSD_A_EXPKEY_FSID]), fsid_len);
+
+	ek = svc_expkey_lookup(cd, &key);
+	if (!ek) {
+		err = -ENOMEM;
+		goto out_dom;
+	}
+
+	if (tb[NFSD_A_EXPKEY_NEGATIVE]) {
+		set_bit(CACHE_NEGATIVE, &key.h.flags);
+		ek = svc_expkey_update(cd, &key, ek);
+		if (ek)
+			trace_nfsd_expkey_update(ek, NULL);
+		else
+			err = -ENOMEM;
+	} else if (tb[NFSD_A_EXPKEY_PATH]) {
+		err = kern_path(nla_data(tb[NFSD_A_EXPKEY_PATH]), 0,
+				&key.ek_path);
+		if (err)
+			goto out_ek;
+		ek = svc_expkey_update(cd, &key, ek);
+		if (ek)
+			trace_nfsd_expkey_update(ek,
+					nla_data(tb[NFSD_A_EXPKEY_PATH]));
+		else
+			err = -ENOMEM;
+		path_put(&key.ek_path);
+	} else {
+		err = -EINVAL;
+		goto out_ek;
+	}
+
+	cache_flush();
+
+out_ek:
+	if (ek)
+		cache_put(&ek->h, cd);
+out_dom:
+	auth_domain_put(dom);
+	return err;
+}
+
+/**
+ * nfsd_nl_expkey_set_reqs_doit - respond to expkey requests
+ * @skb: reply buffer
+ * @info: netlink metadata and command arguments
+ *
+ * Parse one or more expkey cache responses from userspace and
+ * update the expkey cache accordingly.
+ *
+ * Returns 0 on success or a negative errno.
+ */
+int nfsd_nl_expkey_set_reqs_doit(struct sk_buff *skb,
+				 struct genl_info *info)
+{
+	struct nfsd_net *nn;
+	struct cache_detail *cd;
+	const struct nlattr *attr;
+	int rem, ret = 0;
+
+	nn = net_generic(genl_info_net(info), nfsd_net_id);
+
+	mutex_lock(&nfsd_mutex);
+
+	cd = nn->svc_expkey_cache;
+	if (!cd) {
+		ret = -ENODEV;
+		goto out_unlock;
+	}
+
+	nlmsg_for_each_attr_type(attr, NFSD_A_EXPKEY_REQS_REQUESTS,
+				 info->nlhdr, GENL_HDRLEN, rem) {
+		ret = nfsd_nl_parse_one_expkey(cd, (struct nlattr *)attr);
+		if (ret)
+			break;
+	}
+
+out_unlock:
+	mutex_unlock(&nfsd_mutex);
+	return ret;
+}
 
 #define	EXPORT_HASHBITS		8
 #define	EXPORT_HASHMAX		(1<< EXPORT_HASHBITS)
@@ -386,9 +655,444 @@ static void svc_export_put(struct kref *ref)
 	queue_rcu_work(nfsd_export_wq, &exp->ex_rwork);
 }
 
+/**
+ * nfsd_nl_svc_export_get_reqs_dumpit - dump pending svc_export requests
+ * @skb: reply buffer
+ * @cb: netlink metadata and command arguments
+ *
+ * Walk the svc_export cache's pending request list and create a netlink
+ * message with a nested entry for each cache_request, containing the
+ * seqno, client string, and path.
+ *
+ * Uses cb->args[0] as a seqno cursor for dump continuation across
+ * multiple netlink messages.
+ *
+ * Returns the size of the reply or a negative errno.
+ */
+int nfsd_nl_svc_export_get_reqs_dumpit(struct sk_buff *skb,
+				       struct netlink_callback *cb)
+{
+	struct nfsd_net *nn;
+	struct cache_detail *cd;
+	struct cache_head **items;
+	u64 *seqnos;
+	int cnt, i, emitted;
+	char *pathbuf;
+	void *hdr;
+	int ret;
+
+	nn = net_generic(sock_net(skb->sk), nfsd_net_id);
+
+	mutex_lock(&nfsd_mutex);
+
+	cd = nn->svc_export_cache;
+	if (!cd) {
+		ret = -ENODEV;
+		goto out_unlock;
+	}
+
+	cnt = sunrpc_cache_requests_count(cd);
+	if (!cnt) {
+		ret = 0;
+		goto out_unlock;
+	}
+
+	items = kcalloc(cnt, sizeof(*items), GFP_KERNEL);
+	seqnos = kcalloc(cnt, sizeof(*seqnos), GFP_KERNEL);
+	pathbuf = kmalloc(PATH_MAX, GFP_KERNEL);
+	if (!items || !seqnos || !pathbuf) {
+		ret = -ENOMEM;
+		goto out_alloc;
+	}
+
+	cnt = sunrpc_cache_requests_snapshot(cd, items, seqnos, cnt,
+					     cb->args[0]);
+	if (!cnt) {
+		ret = 0;
+		goto out_alloc;
+	}
+
+	hdr = genlmsg_put(skb, NETLINK_CB(cb->skb).portid,
+			  cb->nlh->nlmsg_seq, &nfsd_nl_family,
+			  NLM_F_MULTI, NFSD_CMD_SVC_EXPORT_GET_REQS);
+	if (!hdr) {
+		ret = -ENOBUFS;
+		goto out_put;
+	}
+
+	emitted = 0;
+	for (i = 0; i < cnt; i++) {
+		struct svc_export *exp;
+		struct nlattr *nest;
+		char *pth;
+
+		exp = container_of(items[i], struct svc_export, h);
+
+		pth = d_path(&exp->ex_path, pathbuf, PATH_MAX);
+		if (IS_ERR(pth))
+			continue;
+
+		nest = nla_nest_start(skb,
+				      NFSD_A_SVC_EXPORT_REQS_REQUESTS);
+		if (!nest)
+			break;
+
+		if (nla_put_u64_64bit(skb, NFSD_A_SVC_EXPORT_SEQNO,
+				      seqnos[i], 0) ||
+		    nla_put_string(skb, NFSD_A_SVC_EXPORT_CLIENT,
+				   exp->ex_client->name) ||
+		    nla_put_string(skb, NFSD_A_SVC_EXPORT_PATH, pth)) {
+			nla_nest_cancel(skb, nest);
+			break;
+		}
+
+		nla_nest_end(skb, nest);
+		cb->args[0] = seqnos[i];
+		emitted++;
+	}
+
+	if (!emitted) {
+		genlmsg_cancel(skb, hdr);
+		ret = -EMSGSIZE;
+		goto out_put;
+	}
+
+	genlmsg_end(skb, hdr);
+	ret = skb->len;
+out_put:
+	for (i = 0; i < cnt; i++)
+		cache_put(items[i], cd);
+out_alloc:
+	kfree(pathbuf);
+	kfree(seqnos);
+	kfree(items);
+out_unlock:
+	mutex_unlock(&nfsd_mutex);
+	return ret;
+}
+
+/**
+ * nfsd_nl_parse_fslocations - parse fslocations from netlink
+ * @attr: NFSD_A_SVC_EXPORT_FSLOCATIONS nested attribute
+ * @fsloc: fslocations struct to fill in
+ *
+ * Returns 0 on success or a negative errno.
+ */
+static int nfsd_nl_parse_fslocations(struct nlattr *attr,
+				     struct nfsd4_fs_locations *fsloc)
+{
+	struct nlattr *loc_attr;
+	int rem, count = 0;
+	int err;
+
+	if (fsloc->locations)
+		return -EINVAL;
+
+	/* Count locations first */
+	nla_for_each_nested_type(loc_attr, NFSD_A_FSLOCATIONS_LOCATION,
+				 attr, rem)
+		count++;
+
+	if (count > MAX_FS_LOCATIONS)
+		return -EINVAL;
+	if (!count)
+		return 0;
+
+	fsloc->locations = kcalloc(count, sizeof(struct nfsd4_fs_location),
+				   GFP_KERNEL);
+	if (!fsloc->locations)
+		return -ENOMEM;
+
+	nla_for_each_nested_type(loc_attr, NFSD_A_FSLOCATIONS_LOCATION,
+				 attr, rem) {
+		struct nlattr *tb[NFSD_A_FSLOCATION_PATH + 1];
+		struct nfsd4_fs_location *loc;
+
+		err = nla_parse_nested(tb, NFSD_A_FSLOCATION_PATH, loc_attr,
+				       nfsd_fslocation_nl_policy, NULL);
+		if (err)
+			goto out_free;
+
+		if (!tb[NFSD_A_FSLOCATION_HOST] ||
+		    !tb[NFSD_A_FSLOCATION_PATH]) {
+			err = -EINVAL;
+			goto out_free;
+		}
+
+		loc = &fsloc->locations[fsloc->locations_count++];
+		loc->hosts = kstrdup(nla_data(tb[NFSD_A_FSLOCATION_HOST]),
+				     GFP_KERNEL);
+		loc->path = kstrdup(nla_data(tb[NFSD_A_FSLOCATION_PATH]),
+				    GFP_KERNEL);
+		if (!loc->hosts || !loc->path) {
+			err = -ENOMEM;
+			goto out_free;
+		}
+	}
+
+	return 0;
+out_free:
+	nfsd4_fslocs_free(fsloc);
+	return err;
+}
+
+static struct svc_export *svc_export_update(struct svc_export *new,
+					    struct svc_export *old);
+static struct svc_export *svc_export_lookup(struct svc_export *);
+static int check_export(const struct path *path, int *flags,
+			unsigned char *uuid);
+
+/**
+ * @cd: cache_detail for the svc_export cache
+ * @attr: nested attribute containing svc-export fields
+ *
+ * Parses one svc-export entry from a netlink message and updates the
+ * cache. Mirrors the logic in svc_export_parse().
+ *
+ * Returns 0 on success or a negative errno.
+ */
+static int nfsd_nl_parse_one_export(struct cache_detail *cd,
+				    struct nlattr *attr)
+{
+	struct nlattr *tb[NFSD_A_SVC_EXPORT_FSID + 1];
+	struct auth_domain *dom = NULL;
+	struct svc_export exp = {}, *expp;
+	struct nlattr *secinfo_attr;
+	struct timespec64 boot;
+	int err, rem;
+
+	err = nla_parse_nested(tb, NFSD_A_SVC_EXPORT_FSID, attr,
+			       nfsd_svc_export_nl_policy, NULL);
+	if (err)
+		return err;
+
+	/* client (required) */
+	if (!tb[NFSD_A_SVC_EXPORT_CLIENT])
+		return -EINVAL;
+
+	dom = auth_domain_find(nla_data(tb[NFSD_A_SVC_EXPORT_CLIENT]));
+	if (!dom)
+		return -ENOENT;
+
+	/* path (required) */
+	if (!tb[NFSD_A_SVC_EXPORT_PATH]) {
+		err = -EINVAL;
+		goto out_dom;
+	}
+
+	err = kern_path(nla_data(tb[NFSD_A_SVC_EXPORT_PATH]), 0,
+			&exp.ex_path);
+	if (err)
+		goto out_dom;
+
+	exp.ex_client = dom;
+	exp.cd = cd;
+	exp.ex_devid_map = NULL;
+	exp.ex_xprtsec_modes = NFSEXP_XPRTSEC_ALL;
+
+	/* expiry (required, wallclock seconds) */
+	if (!tb[NFSD_A_SVC_EXPORT_EXPIRY]) {
+		err = -EINVAL;
+		goto out_path;
+	}
+	getboottime64(&boot);
+	exp.h.expiry_time = nla_get_u64(tb[NFSD_A_SVC_EXPORT_EXPIRY]) -
+			    boot.tv_sec;
+
+	if (tb[NFSD_A_SVC_EXPORT_NEGATIVE]) {
+		set_bit(CACHE_NEGATIVE, &exp.h.flags);
+	} else {
+		/* flags */
+		if (tb[NFSD_A_SVC_EXPORT_FLAGS])
+			exp.ex_flags = nla_get_u32(tb[NFSD_A_SVC_EXPORT_FLAGS]);
+
+		/* anon uid */
+		if (tb[NFSD_A_SVC_EXPORT_ANON_UID]) {
+			u32 uid = nla_get_u32(tb[NFSD_A_SVC_EXPORT_ANON_UID]);
+
+			exp.ex_anon_uid = make_kuid(current_user_ns(), uid);
+		}
+
+		/* anon gid */
+		if (tb[NFSD_A_SVC_EXPORT_ANON_GID]) {
+			u32 gid = nla_get_u32(tb[NFSD_A_SVC_EXPORT_ANON_GID]);
+
+			exp.ex_anon_gid = make_kgid(current_user_ns(), gid);
+		}
+
+		/* fsid */
+		if (tb[NFSD_A_SVC_EXPORT_FSID])
+			exp.ex_fsid = nla_get_s32(tb[NFSD_A_SVC_EXPORT_FSID]);
+
+		/* fslocations */
+		if (tb[NFSD_A_SVC_EXPORT_FSLOCATIONS]) {
+			struct nlattr *fsl = tb[NFSD_A_SVC_EXPORT_FSLOCATIONS];
+
+			err = nfsd_nl_parse_fslocations(fsl,
+							&exp.ex_fslocs);
+			if (err)
+				goto out_path;
+		}
+
+		/* uuid */
+		if (tb[NFSD_A_SVC_EXPORT_UUID]) {
+			if (nla_len(tb[NFSD_A_SVC_EXPORT_UUID]) !=
+			    EX_UUID_LEN) {
+				err = -EINVAL;
+				goto out_fslocs;
+			}
+			exp.ex_uuid = kmemdup(nla_data(tb[NFSD_A_SVC_EXPORT_UUID]),
+					      EX_UUID_LEN, GFP_KERNEL);
+			if (!exp.ex_uuid) {
+				err = -ENOMEM;
+				goto out_fslocs;
+			}
+		}
+
+		/* secinfo (multi-attr) */
+		nla_for_each_nested_type(secinfo_attr,
+					 NFSD_A_SVC_EXPORT_SECINFO,
+					 attr, rem) {
+			struct nlattr *ftb[NFSD_A_AUTH_FLAVOR_FLAGS + 1];
+			struct exp_flavor_info *f;
+
+			if (exp.ex_nflavors >= MAX_SECINFO_LIST) {
+				err = -EINVAL;
+				goto out_uuid;
+			}
+
+			err = nla_parse_nested(ftb,
+					       NFSD_A_AUTH_FLAVOR_FLAGS,
+					       secinfo_attr,
+					       nfsd_auth_flavor_nl_policy,
+					       NULL);
+			if (err)
+				goto out_uuid;
+
+			f = &exp.ex_flavors[exp.ex_nflavors++];
+
+			if (ftb[NFSD_A_AUTH_FLAVOR_PSEUDOFLAVOR])
+				f->pseudoflavor = nla_get_u32(ftb[NFSD_A_AUTH_FLAVOR_PSEUDOFLAVOR]);
+
+			if (ftb[NFSD_A_AUTH_FLAVOR_FLAGS])
+				f->flags = nla_get_u32(ftb[NFSD_A_AUTH_FLAVOR_FLAGS]);
+
+			/* Only some flags are allowed to differ between flavors: */
+			if (~NFSEXP_SECINFO_FLAGS & (f->flags ^ exp.ex_flags)) {
+				err = -EINVAL;
+				goto out_uuid;
+			}
+		}
+
+		/* xprtsec (multi-attr u32) */
+		if (tb[NFSD_A_SVC_EXPORT_XPRTSEC]) {
+			struct nlattr *xp_attr;
+
+			exp.ex_xprtsec_modes = 0;
+			nla_for_each_nested_type(xp_attr,
+						 NFSD_A_SVC_EXPORT_XPRTSEC,
+						 attr, rem) {
+				u32 mode = nla_get_u32(xp_attr);
+
+				if (mode > NFSEXP_XPRTSEC_MTLS) {
+					err = -EINVAL;
+					goto out_uuid;
+				}
+				exp.ex_xprtsec_modes |= mode;
+			}
+		}
+
+		err = check_export(&exp.ex_path, &exp.ex_flags,
+				   exp.ex_uuid);
+		if (err)
+			goto out_uuid;
+
+		if (exp.h.expiry_time < seconds_since_boot())
+			goto out_uuid;
+
+		err = -EINVAL;
+		if (!uid_valid(exp.ex_anon_uid))
+			goto out_uuid;
+		if (!gid_valid(exp.ex_anon_gid))
+			goto out_uuid;
+		err = 0;
+
+		nfsd4_setup_layout_type(&exp);
+	}
+
+	expp = svc_export_lookup(&exp);
+	if (!expp) {
+		err = -ENOMEM;
+		goto out_uuid;
+	}
+	expp = svc_export_update(&exp, expp);
+	if (expp) {
+		trace_nfsd_export_update(expp);
+		cache_flush();
+		exp_put(expp);
+	} else {
+		err = -ENOMEM;
+	}
+
+out_uuid:
+	kfree(exp.ex_uuid);
+out_fslocs:
+	nfsd4_fslocs_free(&exp.ex_fslocs);
+out_path:
+	path_put(&exp.ex_path);
+out_dom:
+	auth_domain_put(dom);
+	return err;
+}
+
+/**
+ * nfsd_nl_svc_export_set_reqs_doit - respond to svc_export requests
+ * @skb: reply buffer
+ * @info: netlink metadata and command arguments
+ *
+ * Parse one or more svc_export cache responses from userspace and
+ * update the export cache accordingly.
+ *
+ * Returns 0 on success or a negative errno.
+ */
+int nfsd_nl_svc_export_set_reqs_doit(struct sk_buff *skb,
+				     struct genl_info *info)
+{
+	struct nfsd_net *nn;
+	struct cache_detail *cd;
+	const struct nlattr *attr;
+	int rem, ret = 0;
+
+	nn = net_generic(genl_info_net(info), nfsd_net_id);
+
+	mutex_lock(&nfsd_mutex);
+
+	cd = nn->svc_export_cache;
+	if (!cd) {
+		ret = -ENODEV;
+		goto out_unlock;
+	}
+
+	nlmsg_for_each_attr_type(attr, NFSD_A_SVC_EXPORT_REQS_REQUESTS,
+				 info->nlhdr, GENL_HDRLEN, rem) {
+		ret = nfsd_nl_parse_one_export(cd, (struct nlattr *)attr);
+		if (ret)
+			break;
+	}
+
+out_unlock:
+	mutex_unlock(&nfsd_mutex);
+	return ret;
+}
+
 static int svc_export_upcall(struct cache_detail *cd, struct cache_head *h)
 {
-	return sunrpc_cache_pipe_upcall(cd, h);
+	return sunrpc_cache_upcall(cd, h);
+}
+
+static int svc_export_notify(struct cache_detail *cd, struct cache_head *h)
+{
+	return nfsd_cache_notify(cd, h, NFSD_CACHE_TYPE_SVC_EXPORT);
 }
 
 static void svc_export_request(struct cache_detail *cd,
@@ -410,10 +1114,6 @@ static void svc_export_request(struct cache_detail *cd,
 	(*bpp)[-1] = '\n';
 }
 
-static struct svc_export *svc_export_update(struct svc_export *new,
-					    struct svc_export *old);
-static struct svc_export *svc_export_lookup(struct svc_export *);
-
 static int check_export(const struct path *path, int *flags, unsigned char *uuid)
 {
 	struct inode *inode = d_inode(path->dentry);
@@ -907,6 +1607,7 @@ static const struct cache_detail svc_export_cache_template = {
 	.name		= "nfsd.export",
 	.cache_put	= svc_export_put,
 	.cache_upcall	= svc_export_upcall,
+	.cache_notify	= svc_export_notify,
 	.cache_request	= svc_export_request,
 	.cache_parse	= svc_export_parse,
 	.cache_show	= svc_export_show,
diff --git a/fs/nfsd/netlink.c b/fs/nfsd/netlink.c
index 81c943345d13..f99add477cc7 100644
--- a/fs/nfsd/netlink.c
+++ b/fs/nfsd/netlink.c
@@ -12,11 +12,51 @@
 #include <uapi/linux/nfsd_netlink.h>
 
 /* Common nested types */
+const struct nla_policy nfsd_auth_flavor_nl_policy[NFSD_A_AUTH_FLAVOR_FLAGS + 1] = {
+	[NFSD_A_AUTH_FLAVOR_PSEUDOFLAVOR] = { .type = NLA_U32, },
+	[NFSD_A_AUTH_FLAVOR_FLAGS] = NLA_POLICY_MASK(NLA_U32, 0x3ffff),
+};
+
+const struct nla_policy nfsd_expkey_nl_policy[NFSD_A_EXPKEY_PATH + 1] = {
+	[NFSD_A_EXPKEY_SEQNO] = { .type = NLA_U64, },
+	[NFSD_A_EXPKEY_CLIENT] = { .type = NLA_NUL_STRING, },
+	[NFSD_A_EXPKEY_FSIDTYPE] = { .type = NLA_U8, },
+	[NFSD_A_EXPKEY_FSID] = { .type = NLA_BINARY, },
+	[NFSD_A_EXPKEY_NEGATIVE] = { .type = NLA_FLAG, },
+	[NFSD_A_EXPKEY_EXPIRY] = { .type = NLA_U64, },
+	[NFSD_A_EXPKEY_PATH] = { .type = NLA_NUL_STRING, },
+};
+
+const struct nla_policy nfsd_fslocation_nl_policy[NFSD_A_FSLOCATION_PATH + 1] = {
+	[NFSD_A_FSLOCATION_HOST] = { .type = NLA_NUL_STRING, },
+	[NFSD_A_FSLOCATION_PATH] = { .type = NLA_NUL_STRING, },
+};
+
+const struct nla_policy nfsd_fslocations_nl_policy[NFSD_A_FSLOCATIONS_LOCATION + 1] = {
+	[NFSD_A_FSLOCATIONS_LOCATION] = NLA_POLICY_NESTED(nfsd_fslocation_nl_policy),
+};
+
 const struct nla_policy nfsd_sock_nl_policy[NFSD_A_SOCK_TRANSPORT_NAME + 1] = {
 	[NFSD_A_SOCK_ADDR] = { .type = NLA_BINARY, },
 	[NFSD_A_SOCK_TRANSPORT_NAME] = { .type = NLA_NUL_STRING, },
 };
 
+const struct nla_policy nfsd_svc_export_nl_policy[NFSD_A_SVC_EXPORT_FSID + 1] = {
+	[NFSD_A_SVC_EXPORT_SEQNO] = { .type = NLA_U64, },
+	[NFSD_A_SVC_EXPORT_CLIENT] = { .type = NLA_NUL_STRING, },
+	[NFSD_A_SVC_EXPORT_PATH] = { .type = NLA_NUL_STRING, },
+	[NFSD_A_SVC_EXPORT_NEGATIVE] = { .type = NLA_FLAG, },
+	[NFSD_A_SVC_EXPORT_EXPIRY] = { .type = NLA_U64, },
+	[NFSD_A_SVC_EXPORT_ANON_UID] = { .type = NLA_U32, },
+	[NFSD_A_SVC_EXPORT_ANON_GID] = { .type = NLA_U32, },
+	[NFSD_A_SVC_EXPORT_FSLOCATIONS] = NLA_POLICY_NESTED(nfsd_fslocations_nl_policy),
+	[NFSD_A_SVC_EXPORT_UUID] = { .type = NLA_BINARY, },
+	[NFSD_A_SVC_EXPORT_SECINFO] = NLA_POLICY_NESTED(nfsd_auth_flavor_nl_policy),
+	[NFSD_A_SVC_EXPORT_XPRTSEC] = NLA_POLICY_MASK(NLA_U32, 0x7),
+	[NFSD_A_SVC_EXPORT_FLAGS] = NLA_POLICY_MASK(NLA_U32, 0x3ffff),
+	[NFSD_A_SVC_EXPORT_FSID] = { .type = NLA_S32, },
+};
+
 const struct nla_policy nfsd_version_nl_policy[NFSD_A_VERSION_ENABLED + 1] = {
 	[NFSD_A_VERSION_MAJOR] = { .type = NLA_U32, },
 	[NFSD_A_VERSION_MINOR] = { .type = NLA_U32, },
@@ -48,6 +88,21 @@ static const struct nla_policy nfsd_pool_mode_set_nl_policy[NFSD_A_POOL_MODE_MOD
 	[NFSD_A_POOL_MODE_MODE] = { .type = NLA_NUL_STRING, },
 };
 
+/* NFSD_CMD_SVC_EXPORT_SET_REQS - do */
+static const struct nla_policy nfsd_svc_export_set_reqs_nl_policy[NFSD_A_SVC_EXPORT_REQS_REQUESTS + 1] = {
+	[NFSD_A_SVC_EXPORT_REQS_REQUESTS] = NLA_POLICY_NESTED(nfsd_svc_export_nl_policy),
+};
+
+/* NFSD_CMD_EXPKEY_SET_REQS - do */
+static const struct nla_policy nfsd_expkey_set_reqs_nl_policy[NFSD_A_EXPKEY_REQS_REQUESTS + 1] = {
+	[NFSD_A_EXPKEY_REQS_REQUESTS] = NLA_POLICY_NESTED(nfsd_expkey_nl_policy),
+};
+
+/* NFSD_CMD_CACHE_FLUSH - do */
+static const struct nla_policy nfsd_cache_flush_nl_policy[NFSD_A_CACHE_FLUSH_MASK + 1] = {
+	[NFSD_A_CACHE_FLUSH_MASK] = NLA_POLICY_MASK(NLA_U32, 0x3),
+};
+
 /* Ops table for nfsd */
 static const struct genl_split_ops nfsd_nl_ops[] = {
 	{
@@ -103,6 +158,42 @@ static const struct genl_split_ops nfsd_nl_ops[] = {
 		.doit	= nfsd_nl_pool_mode_get_doit,
 		.flags	= GENL_CMD_CAP_DO,
 	},
+	{
+		.cmd	= NFSD_CMD_SVC_EXPORT_GET_REQS,
+		.dumpit	= nfsd_nl_svc_export_get_reqs_dumpit,
+		.flags	= GENL_ADMIN_PERM | GENL_CMD_CAP_DUMP,
+	},
+	{
+		.cmd		= NFSD_CMD_SVC_EXPORT_SET_REQS,
+		.doit		= nfsd_nl_svc_export_set_reqs_doit,
+		.policy		= nfsd_svc_export_set_reqs_nl_policy,
+		.maxattr	= NFSD_A_SVC_EXPORT_REQS_REQUESTS,
+		.flags		= GENL_ADMIN_PERM | GENL_CMD_CAP_DO,
+	},
+	{
+		.cmd	= NFSD_CMD_EXPKEY_GET_REQS,
+		.dumpit	= nfsd_nl_expkey_get_reqs_dumpit,
+		.flags	= GENL_ADMIN_PERM | GENL_CMD_CAP_DUMP,
+	},
+	{
+		.cmd		= NFSD_CMD_EXPKEY_SET_REQS,
+		.doit		= nfsd_nl_expkey_set_reqs_doit,
+		.policy		= nfsd_expkey_set_reqs_nl_policy,
+		.maxattr	= NFSD_A_EXPKEY_REQS_REQUESTS,
+		.flags		= GENL_ADMIN_PERM | GENL_CMD_CAP_DO,
+	},
+	{
+		.cmd		= NFSD_CMD_CACHE_FLUSH,
+		.doit		= nfsd_nl_cache_flush_doit,
+		.policy		= nfsd_cache_flush_nl_policy,
+		.maxattr	= NFSD_A_CACHE_FLUSH_MASK,
+		.flags		= GENL_ADMIN_PERM | GENL_CMD_CAP_DO,
+	},
+};
+
+static const struct genl_multicast_group nfsd_nl_mcgrps[] = {
+	[NFSD_NLGRP_NONE] = { "none", },
+	[NFSD_NLGRP_EXPORTD] = { "exportd", },
 };
 
 struct genl_family nfsd_nl_family __ro_after_init = {
@@ -113,4 +204,6 @@ struct genl_family nfsd_nl_family __ro_after_init = {
 	.module		= THIS_MODULE,
 	.split_ops	= nfsd_nl_ops,
 	.n_split_ops	= ARRAY_SIZE(nfsd_nl_ops),
+	.mcgrps		= nfsd_nl_mcgrps,
+	.n_mcgrps	= ARRAY_SIZE(nfsd_nl_mcgrps),
 };
diff --git a/fs/nfsd/netlink.h b/fs/nfsd/netlink.h
index 478117ff6b8c..cc89732ed71b 100644
--- a/fs/nfsd/netlink.h
+++ b/fs/nfsd/netlink.h
@@ -13,7 +13,12 @@
 #include <uapi/linux/nfsd_netlink.h>
 
 /* Common nested types */
+extern const struct nla_policy nfsd_auth_flavor_nl_policy[NFSD_A_AUTH_FLAVOR_FLAGS + 1];
+extern const struct nla_policy nfsd_expkey_nl_policy[NFSD_A_EXPKEY_PATH + 1];
+extern const struct nla_policy nfsd_fslocation_nl_policy[NFSD_A_FSLOCATION_PATH + 1];
+extern const struct nla_policy nfsd_fslocations_nl_policy[NFSD_A_FSLOCATIONS_LOCATION + 1];
 extern const struct nla_policy nfsd_sock_nl_policy[NFSD_A_SOCK_TRANSPORT_NAME + 1];
+extern const struct nla_policy nfsd_svc_export_nl_policy[NFSD_A_SVC_EXPORT_FSID + 1];
 extern const struct nla_policy nfsd_version_nl_policy[NFSD_A_VERSION_ENABLED + 1];
 
 int nfsd_nl_rpc_status_get_dumpit(struct sk_buff *skb,
@@ -26,6 +31,19 @@ int nfsd_nl_listener_set_doit(struct sk_buff *skb, struct genl_info *info);
 int nfsd_nl_listener_get_doit(struct sk_buff *skb, struct genl_info *info);
 int nfsd_nl_pool_mode_set_doit(struct sk_buff *skb, struct genl_info *info);
 int nfsd_nl_pool_mode_get_doit(struct sk_buff *skb, struct genl_info *info);
+int nfsd_nl_svc_export_get_reqs_dumpit(struct sk_buff *skb,
+				       struct netlink_callback *cb);
+int nfsd_nl_svc_export_set_reqs_doit(struct sk_buff *skb,
+				     struct genl_info *info);
+int nfsd_nl_expkey_get_reqs_dumpit(struct sk_buff *skb,
+				   struct netlink_callback *cb);
+int nfsd_nl_expkey_set_reqs_doit(struct sk_buff *skb, struct genl_info *info);
+int nfsd_nl_cache_flush_doit(struct sk_buff *skb, struct genl_info *info);
+
+enum {
+	NFSD_NLGRP_NONE,
+	NFSD_NLGRP_EXPORTD,
+};
 
 extern struct genl_family nfsd_nl_family;
 
diff --git a/fs/nfsd/nfs4idmap.c b/fs/nfsd/nfs4idmap.c
index ba06d3d3e6dd..71ba61b5d0a3 100644
--- a/fs/nfsd/nfs4idmap.c
+++ b/fs/nfsd/nfs4idmap.c
@@ -126,7 +126,7 @@ idtoname_hash(struct ent *ent)
 static int
 idtoname_upcall(struct cache_detail *cd, struct cache_head *h)
 {
-	return sunrpc_cache_pipe_upcall_timeout(cd, h);
+	return sunrpc_cache_upcall_warn(cd, h);
 }
 
 static void
@@ -306,7 +306,7 @@ nametoid_hash(struct ent *ent)
 static int
 nametoid_upcall(struct cache_detail *cd, struct cache_head *h)
 {
-	return sunrpc_cache_pipe_upcall_timeout(cd, h);
+	return sunrpc_cache_upcall_warn(cd, h);
 }
 
 static void
diff --git a/fs/nfsd/nfs4proc.c b/fs/nfsd/nfs4proc.c
index 85e94c30285a..2797da8cc950 100644
--- a/fs/nfsd/nfs4proc.c
+++ b/fs/nfsd/nfs4proc.c
@@ -2535,10 +2535,6 @@ nfsd4_get_dir_delegation(struct svc_rqst *rqstp,
 	dd = nfsd_get_dir_deleg(cstate, gdd, nf);
 	nfsd_file_put(nf);
 	if (IS_ERR(dd)) {
-		int err = PTR_ERR(dd);
-
-		if (err != -EAGAIN)
-			return nfserrno(err);
 		gdd->gddrnf_status = GDD4_UNAVAIL;
 		return nfs_ok;
 	}
diff --git a/fs/nfsd/nfs4state.c b/fs/nfsd/nfs4state.c
index c2d13b26a687..024d2cb9bedb 100644
--- a/fs/nfsd/nfs4state.c
+++ b/fs/nfsd/nfs4state.c
@@ -1390,7 +1390,8 @@ static void destroy_delegation(struct nfs4_delegation *dp)
  * stateid or it's called from a laundromat thread (nfsd4_landromat()) that
  * determined that this specific state has expired and needs to be revoked
  * (both mark state with the appropriate stid sc_status mode). It is also
- * assumed that a reference was taken on the @dp state.
+ * assumed that a reference was taken on the @dp state. This function
+ * consumes that reference.
  *
  * If this function finds that the @dp state is SC_STATUS_FREED it means
  * that a FREE_STATEID operation for this stateid has been processed and
@@ -1853,6 +1854,10 @@ void nfsd4_revoke_states(struct nfsd_net *nn, struct super_block *sb)
 					mutex_unlock(&stp->st_mutex);
 					break;
 				case SC_TYPE_DELEG:
+					/* Extra reference guards against concurrent
+					 * FREE_STATEID; revoke_delegation() consumes
+					 * it, otherwise release it directly.
+					 */
 					refcount_inc(&stid->sc_count);
 					dp = delegstateid(stid);
 					spin_lock(&nn->deleg_lock);
@@ -1862,6 +1867,8 @@ void nfsd4_revoke_states(struct nfsd_net *nn, struct super_block *sb)
 					spin_unlock(&nn->deleg_lock);
 					if (dp)
 						revoke_delegation(dp);
+					else
+						nfs4_put_stid(stid);
 					break;
 				case SC_TYPE_LAYOUT:
 					ls = layoutstateid(stid);
diff --git a/fs/nfsd/nfsctl.c b/fs/nfsd/nfsctl.c
index 39e7012a60d8..92f958509399 100644
--- a/fs/nfsd/nfsctl.c
+++ b/fs/nfsd/nfsctl.c
@@ -10,6 +10,7 @@
 #include <linux/ctype.h>
 #include <linux/fs_context.h>
 
+#include <linux/sunrpc/cache.h>
 #include <linux/sunrpc/svcsock.h>
 #include <linux/lockd/bind.h>
 #include <linux/sunrpc/addr.h>
@@ -1412,6 +1413,21 @@ static int create_proc_exports_entry(void)
 
 unsigned int nfsd_net_id;
 
+struct nfsd_genl_rqstp {
+	struct sockaddr		rq_daddr;
+	struct sockaddr		rq_saddr;
+	unsigned long		rq_flags;
+	ktime_t			rq_stime;
+	__be32			rq_xid;
+	u32			rq_vers;
+	u32			rq_prog;
+	u32			rq_proc;
+
+	/* NFSv4 compound */
+	u32			rq_opcnt;
+	u32			rq_opnum[16];
+};
+
 static int nfsd_genl_rpc_status_compose_msg(struct sk_buff *skb,
 					    struct netlink_callback *cb,
 					    struct nfsd_genl_rqstp *genl_rqstp)
@@ -2187,6 +2203,69 @@ int nfsd_nl_pool_mode_get_doit(struct sk_buff *skb, struct genl_info *info)
 	return err;
 }
 
+/**
+ * nfsd_nl_cache_flush_doit - flush nfsd caches via netlink
+ * @skb: reply buffer
+ * @info: netlink metadata and command arguments
+ *
+ * Flush the svc_export and/or expkey caches. If NFSD_A_CACHE_FLUSH_MASK
+ * is provided, only flush the caches indicated by the bitmask (bit 0 =
+ * svc_export, bit 1 = expkey). If omitted, flush both.
+ *
+ * Return 0 on success or a negative errno.
+ */
+int nfsd_nl_cache_flush_doit(struct sk_buff *skb, struct genl_info *info)
+{
+	struct net *net = genl_info_net(info);
+	struct nfsd_net *nn = net_generic(net, nfsd_net_id);
+	u32 mask = ~0U;
+
+	if (info->attrs[NFSD_A_CACHE_FLUSH_MASK])
+		mask = nla_get_u32(info->attrs[NFSD_A_CACHE_FLUSH_MASK]);
+
+	mutex_lock(&nfsd_mutex);
+
+	if ((mask & NFSD_CACHE_TYPE_SVC_EXPORT) &&
+	    nn->svc_export_cache)
+		cache_purge(nn->svc_export_cache);
+
+	if ((mask & NFSD_CACHE_TYPE_EXPKEY) &&
+	    nn->svc_expkey_cache)
+		cache_purge(nn->svc_expkey_cache);
+
+	mutex_unlock(&nfsd_mutex);
+
+	return 0;
+}
+
+int nfsd_cache_notify(struct cache_detail *cd, struct cache_head *h, u32 cache_type)
+{
+	struct genlmsghdr *hdr;
+	struct sk_buff *msg;
+
+	if (!genl_has_listeners(&nfsd_nl_family, cd->net, NFSD_NLGRP_EXPORTD))
+		return -ENOLINK;
+
+	msg = genlmsg_new(nla_total_size(sizeof(u32)), GFP_KERNEL);
+	if (!msg)
+		return -ENOMEM;
+
+	hdr = genlmsg_put(msg, 0, 0, &nfsd_nl_family, 0, NFSD_CMD_CACHE_NOTIFY);
+	if (!hdr) {
+		nlmsg_free(msg);
+		return -ENOMEM;
+	}
+
+	if (nla_put_u32(msg, NFSD_A_CACHE_NOTIFY_CACHE_TYPE, cache_type)) {
+		nlmsg_free(msg);
+		return -ENOMEM;
+	}
+
+	genlmsg_end(msg, hdr);
+	return genlmsg_multicast_netns(&nfsd_nl_family, cd->net, msg, 0,
+				       NFSD_NLGRP_EXPORTD, GFP_KERNEL);
+}
+
 /**
  * nfsd_net_init - Prepare the nfsd_net portion of a new net namespace
  * @net: a freshly-created network namespace
diff --git a/fs/nfsd/nfsd.h b/fs/nfsd/nfsd.h
index 7c009f07c90b..709da3c7a5fa 100644
--- a/fs/nfsd/nfsd.h
+++ b/fs/nfsd/nfsd.h
@@ -60,21 +60,6 @@ struct readdir_cd {
 /* Maximum number of operations per session compound */
 #define NFSD_MAX_OPS_PER_COMPOUND	200
 
-struct nfsd_genl_rqstp {
-	struct sockaddr		rq_daddr;
-	struct sockaddr		rq_saddr;
-	unsigned long		rq_flags;
-	ktime_t			rq_stime;
-	__be32			rq_xid;
-	u32			rq_vers;
-	u32			rq_prog;
-	u32			rq_proc;
-
-	/* NFSv4 compound */
-	u32			rq_opcnt;
-	u32			rq_opnum[16];
-};
-
 extern struct svc_program	nfsd_programs[];
 extern const struct svc_version	nfsd_version2, nfsd_version3, nfsd_version4;
 extern struct mutex		nfsd_mutex;
@@ -123,7 +108,7 @@ struct dentry *nfsd_client_mkdir(struct nfsd_net *nn,
 				 const struct tree_descr *,
 				 struct dentry **fdentries);
 void nfsd_client_rmdir(struct dentry *dentry);
-
+int nfsd_cache_notify(struct cache_detail *cd, struct cache_head *h, u32 cache_type);
 
 #if defined(CONFIG_NFSD_V2_ACL) || defined(CONFIG_NFSD_V3_ACL)
 #ifdef CONFIG_NFSD_V2_ACL
diff --git a/fs/notify/fanotify/fanotify.c b/fs/notify/fanotify/fanotify.c
index bfe884d624e7..38290b9c07f7 100644
--- a/fs/notify/fanotify/fanotify.c
+++ b/fs/notify/fanotify/fanotify.c
@@ -457,7 +457,7 @@ static int fanotify_encode_fh(struct fanotify_fh *fh, struct inode *inode,
 	/*
 	 * Unlike file_handle, type and len of struct fanotify_fh are u8.
 	 * Traditionally, filesystem return handle_type < 0xff, but there
-	 * is no enforecement for that in vfs.
+	 * is no enforcement for that in vfs.
 	 */
 	BUILD_BUG_ON(MAX_HANDLE_SZ > 0xff || FILEID_INVALID > 0xff);
 	if (type <= 0 || type >= FILEID_INVALID || fh_len != dwords << 2)
diff --git a/fs/notify/fsnotify.c b/fs/notify/fsnotify.c
index b7198c4744e3..2dac70b99b0d 100644
--- a/fs/notify/fsnotify.c
+++ b/fs/notify/fsnotify.c
@@ -388,7 +388,7 @@ static struct fsnotify_mark *fsnotify_first_mark(struct fsnotify_mark_connector
 	return hlist_entry_safe(node, struct fsnotify_mark, obj_list);
 }
 
-static struct fsnotify_mark *fsnotify_next_mark(struct fsnotify_mark *mark)
+struct fsnotify_mark *fsnotify_next_mark(struct fsnotify_mark *mark)
 {
 	struct hlist_node *node = NULL;
 
diff --git a/fs/notify/mark.c b/fs/notify/mark.c
index c2ed5b11b0fe..e256b420100d 100644
--- a/fs/notify/mark.c
+++ b/fs/notify/mark.c
@@ -238,7 +238,12 @@ static struct inode *fsnotify_update_iref(struct fsnotify_mark_connector *conn,
 	return inode;
 }
 
-static void *__fsnotify_recalc_mask(struct fsnotify_mark_connector *conn)
+/*
+ * Calculate mask of events for a list of marks.
+ *
+ * Return true if any of the attached marks want to hold an inode reference.
+ */
+static bool __fsnotify_recalc_mask(struct fsnotify_mark_connector *conn)
 {
 	u32 new_mask = 0;
 	bool want_iref = false;
@@ -262,6 +267,34 @@ static void *__fsnotify_recalc_mask(struct fsnotify_mark_connector *conn)
 	 */
 	WRITE_ONCE(*fsnotify_conn_mask_p(conn), new_mask);
 
+	return want_iref;
+}
+
+/*
+ * Calculate mask of events for a list of marks after attach/modify mark
+ * and get an inode reference for the connector if needed.
+ *
+ * A concurrent add of evictable mark and detach of non-evictable mark can
+ * lead to __fsnotify_recalc_mask() returning false want_iref, but in this
+ * case we defer clearing iref to fsnotify_recalc_mask_clear_iref() called
+ * from fsnotify_put_mark().
+ */
+static void fsnotify_recalc_mask_set_iref(struct fsnotify_mark_connector *conn)
+{
+	bool has_iref = conn->flags & FSNOTIFY_CONN_FLAG_HAS_IREF;
+	bool want_iref = __fsnotify_recalc_mask(conn) || has_iref;
+
+	(void) fsnotify_update_iref(conn, want_iref);
+}
+
+/*
+ * Calculate mask of events for a list of marks after detach mark
+ * and return the inode object if its reference is no longer needed.
+ */
+static void *fsnotify_recalc_mask_clear_iref(struct fsnotify_mark_connector *conn)
+{
+	bool want_iref = __fsnotify_recalc_mask(conn);
+
 	return fsnotify_update_iref(conn, want_iref);
 }
 
@@ -298,7 +331,7 @@ void fsnotify_recalc_mask(struct fsnotify_mark_connector *conn)
 
 	spin_lock(&conn->lock);
 	update_children = !fsnotify_conn_watches_children(conn);
-	__fsnotify_recalc_mask(conn);
+	fsnotify_recalc_mask_set_iref(conn);
 	update_children &= fsnotify_conn_watches_children(conn);
 	spin_unlock(&conn->lock);
 	/*
@@ -419,7 +452,7 @@ void fsnotify_put_mark(struct fsnotify_mark *mark)
 		/* Update watched objects after detaching mark */
 		if (sb)
 			fsnotify_update_sb_watchers(sb, conn);
-		objp = __fsnotify_recalc_mask(conn);
+		objp = fsnotify_recalc_mask_clear_iref(conn);
 		type = conn->type;
 	}
 	WRITE_ONCE(mark->connector, NULL);
@@ -457,9 +490,6 @@ EXPORT_SYMBOL_GPL(fsnotify_put_mark);
  */
 static bool fsnotify_get_mark_safe(struct fsnotify_mark *mark)
 {
-	if (!mark)
-		return true;
-
 	if (refcount_inc_not_zero(&mark->refcnt)) {
 		spin_lock(&mark->lock);
 		if (mark->flags & FSNOTIFY_MARK_FLAG_ATTACHED) {
@@ -500,15 +530,22 @@ bool fsnotify_prepare_user_wait(struct fsnotify_iter_info *iter_info)
 	int type;
 
 	fsnotify_foreach_iter_type(type) {
+		struct fsnotify_mark *mark = iter_info->marks[type];
+
 		/* This can fail if mark is being removed */
-		if (!fsnotify_get_mark_safe(iter_info->marks[type])) {
-			__release(&fsnotify_mark_srcu);
-			goto fail;
+		while (mark && !fsnotify_get_mark_safe(mark)) {
+			if (mark->group == iter_info->current_group) {
+				__release(&fsnotify_mark_srcu);
+				goto fail;
+			}
+			/* This is a mark in an unrelated group, skip */
+			mark = fsnotify_next_mark(mark);
+			iter_info->marks[type] = mark;
 		}
 	}
 
 	/*
-	 * Now that both marks are pinned by refcount in the inode / vfsmount
+	 * Now that all marks are pinned by refcount in the inode / vfsmount / etc
 	 * lists, we can drop SRCU lock, and safely resume the list iteration
 	 * once userspace returns.
 	 */
diff --git a/fs/ntfs/dir.c b/fs/ntfs/dir.c
index bfa904d2ce66..20f5c7074bdd 100644
--- a/fs/ntfs/dir.c
+++ b/fs/ntfs/dir.c
@@ -911,8 +911,8 @@ static int ntfs_readdir(struct file *file, struct dir_context *actor)
 
 	if (next->flags & INDEX_ENTRY_NODE) {
 		next = ntfs_index_walk_down(next, ictx);
-		if (!next) {
-			err = -EIO;
+		if (IS_ERR(next)) {
+			err = PTR_ERR(next);
 			goto out;
 		}
 	}
@@ -920,7 +920,14 @@ static int ntfs_readdir(struct file *file, struct dir_context *actor)
 	if (next && !(next->flags & INDEX_ENTRY_END))
 		goto nextdir;
 
-	while ((next = ntfs_index_next(next, ictx)) != NULL) {
+	while (1) {
+		next = ntfs_index_next(next, ictx);
+		if (IS_ERR(next)) {
+			err = PTR_ERR(next);
+			goto out;
+		}
+		if (!next)
+			break;
 nextdir:
 		/* Check the consistency of an index entry */
 		if (ntfs_index_entry_inconsistent(ictx, vol, next, COLLATION_FILE_NAME,
diff --git a/fs/ntfs/index.c b/fs/ntfs/index.c
index 2080f3969137..a547bdcfa456 100644
--- a/fs/ntfs/index.c
+++ b/fs/ntfs/index.c
@@ -1969,15 +1969,19 @@ int ntfs_index_remove(struct ntfs_inode *dir_ni, const void *key, const u32 keyl
 struct index_entry *ntfs_index_walk_down(struct index_entry *ie, struct ntfs_index_context *ictx)
 {
 	struct index_entry *entry;
+	struct index_block *ib;
 	s64 vcn;
 
 	entry = ie;
 	do {
 		vcn = ntfs_ie_get_vcn(entry);
 		if (ictx->is_in_root) {
+			ib = kvzalloc(ictx->block_size, GFP_NOFS);
+			if (!ib)
+				return ERR_PTR(-ENOMEM);
 			/* down from level zero */
 			ictx->ir = NULL;
-			ictx->ib = kvzalloc(ictx->block_size, GFP_NOFS);
+			ictx->ib = ib;
 			ictx->pindex = 1;
 			ictx->is_in_root = false;
 		} else {
@@ -1991,8 +1995,8 @@ struct index_entry *ntfs_index_walk_down(struct index_entry *ie, struct ntfs_ind
 			ictx->entry = ntfs_ie_get_first(&ictx->ib->index);
 			entry = ictx->entry;
 		} else
-			entry = NULL;
-	} while (entry && (entry->flags & INDEX_ENTRY_NODE));
+			entry = ERR_PTR(-EIO);
+	} while (!IS_ERR(entry) && (entry->flags & INDEX_ENTRY_NODE));
 
 	return entry;
 }
@@ -2097,10 +2101,15 @@ struct index_entry *ntfs_index_next(struct index_entry *ie, struct ntfs_index_co
 
 		/* walk down if it has a subnode */
 		if (flags & INDEX_ENTRY_NODE) {
-			if (!ictx->ia_ni)
+			if (!ictx->ia_ni) {
 				ictx->ia_ni = ntfs_ia_open(ictx, ictx->idx_ni);
+				if (!ictx->ia_ni)
+					return ERR_PTR(-EIO);
+			}
 
 			next = ntfs_index_walk_down(next, ictx);
+			if (IS_ERR(next))
+				return next;
 		} else {
 
 			/* walk up it has no subnode, nor data */
diff --git a/fs/ntfs/reparse.c b/fs/ntfs/reparse.c
index 8f60ec6f66c1..74713716813f 100644
--- a/fs/ntfs/reparse.c
+++ b/fs/ntfs/reparse.c
@@ -505,7 +505,6 @@ int ntfs_reparse_set_wsl_symlink(struct ntfs_inode *ni,
 	struct reparse_point *reparse;
 	struct wsl_link_reparse_data *data;
 
-	utarget = (char *)NULL;
 	len = ntfs_ucstonls(ni->vol, target, target_len, &utarget, 0);
 	if (len <= 0)
 		return -EINVAL;
@@ -514,7 +513,7 @@ int ntfs_reparse_set_wsl_symlink(struct ntfs_inode *ni,
 	reparse = kvzalloc(reparse_len, GFP_NOFS);
 	if (!reparse) {
 		err = -ENOMEM;
-		kvfree(utarget);
+		kfree(utarget);
 	} else {
 		data = (struct wsl_link_reparse_data *)reparse->reparse_data;
 		reparse->reparse_tag = IO_REPARSE_TAG_LX_SYMLINK;
@@ -528,6 +527,8 @@ int ntfs_reparse_set_wsl_symlink(struct ntfs_inode *ni,
 		kvfree(reparse);
 		if (!err)
 			ni->target = utarget;
+		else
+			kfree(utarget);
 	}
 	return err;
 }
diff --git a/fs/ocfs2/quota_local.c b/fs/ocfs2/quota_local.c
index 12cbb4fccda0..f55810c59b1b 100644
--- a/fs/ocfs2/quota_local.c
+++ b/fs/ocfs2/quota_local.c
@@ -302,7 +302,7 @@ static int ocfs2_add_recovery_chunk(struct super_block *sb,
 	if (!rc)
 		return -ENOMEM;
 	rc->rc_chunk = chunk;
-	rc->rc_bitmap = kmalloc(sb->s_blocksize, GFP_NOFS);
+	rc->rc_bitmap = kzalloc(sb->s_blocksize, GFP_NOFS);
 	if (!rc->rc_bitmap) {
 		kfree(rc);
 		return -ENOMEM;
diff --git a/fs/proc/base.c b/fs/proc/base.c
index d9acfa89c894..49344de10158 100644
--- a/fs/proc/base.c
+++ b/fs/proc/base.c
@@ -3543,28 +3543,42 @@ struct dentry *proc_pid_lookup(struct dentry *dentry, unsigned int flags)
 struct tgid_iter {
 	unsigned int tgid;
 	struct task_struct *task;
+	struct pid_namespace *const pid_ns;
 };
-static struct tgid_iter next_tgid(struct pid_namespace *ns, struct tgid_iter iter)
+
+static struct tgid_iter
+make_tgid_iter(unsigned int init_tgid, struct pid_namespace *pid_ns)
 {
-	struct pid *pid;
+	return (struct tgid_iter){
+		.tgid = init_tgid - 1,
+		.pid_ns = pid_ns,
+	};
+}
+
+static bool next_tgid(struct tgid_iter *it)
+{
+	if (it->task) {
+		put_task_struct(it->task);
+		it->task = NULL;
+	}
 
-	if (iter.task)
-		put_task_struct(iter.task);
 	rcu_read_lock();
-retry:
-	iter.task = NULL;
-	pid = find_ge_pid(iter.tgid, ns);
-	if (pid) {
-		iter.tgid = pid_nr_ns(pid, ns);
-		iter.task = pid_task(pid, PIDTYPE_TGID);
-		if (!iter.task) {
-			iter.tgid += 1;
-			goto retry;
+	while (1) {
+		it->tgid += 1;
+		const auto pid = find_ge_pid(it->tgid, it->pid_ns);
+		if (pid) {
+			it->tgid = pid_nr_ns(pid, it->pid_ns);
+			it->task = pid_task(pid, PIDTYPE_TGID);
+			if (it->task) {
+				get_task_struct(it->task);
+				rcu_read_unlock();
+				return true;
+			}
+		} else {
+			rcu_read_unlock();
+			return false;
 		}
-		get_task_struct(iter.task);
 	}
-	rcu_read_unlock();
-	return iter;
 }
 
 #define TGID_OFFSET (FIRST_PROCESS_ENTRY + 2)
@@ -3572,9 +3586,8 @@ static struct tgid_iter next_tgid(struct pid_namespace *ns, struct tgid_iter ite
 /* for the /proc/ directory itself, after non-process stuff has been done */
 int proc_pid_readdir(struct file *file, struct dir_context *ctx)
 {
-	struct tgid_iter iter;
 	struct proc_fs_info *fs_info = proc_sb_info(file_inode(file)->i_sb);
-	struct pid_namespace *ns = proc_pid_ns(file_inode(file)->i_sb);
+	struct pid_namespace *pid_ns = proc_pid_ns(file_inode(file)->i_sb);
 	loff_t pos = ctx->pos;
 
 	if (pos >= PID_MAX_LIMIT + TGID_OFFSET)
@@ -3590,11 +3603,9 @@ int proc_pid_readdir(struct file *file, struct dir_context *ctx)
 			return 0;
 		ctx->pos = pos = pos + 1;
 	}
-	iter.tgid = pos - TGID_OFFSET;
-	iter.task = NULL;
-	for (iter = next_tgid(ns, iter);
-	     iter.task;
-	     iter.tgid += 1, iter = next_tgid(ns, iter)) {
+
+	auto iter = make_tgid_iter(pos - TGID_OFFSET, pid_ns);
+	while (next_tgid(&iter)) {
 		char name[10 + 1];
 		unsigned int len;
 
diff --git a/fs/proc/generic.c b/fs/proc/generic.c
index 8bb81e58c9d8..3063080f3bb2 100644
--- a/fs/proc/generic.c
+++ b/fs/proc/generic.c
@@ -427,9 +427,13 @@ static struct proc_dir_entry *__proc_create(struct proc_dir_entry **parent,
 	if (xlate_proc_name(name, parent, &fn) != 0)
 		goto out;
 	qstr.name = fn;
-	qstr.len = strlen(fn);
-	if (qstr.len == 0 || qstr.len >= 256) {
-		WARN(1, "name len %u\n", qstr.len);
+	qstr.len = strnlen(fn, NAME_MAX + 1);
+	if (qstr.len == 0) {
+		WARN(1, "empty name\n");
+		return NULL;
+	}
+	if (qstr.len > NAME_MAX) {
+		WARN(1, "name too long\n");
 		return NULL;
 	}
 	if (qstr.len == 1 && fn[0] == '.') {
diff --git a/fs/smb/client/cifsproto.h b/fs/smb/client/cifsproto.h
index 4a25afda9448..79d891f7df1a 100644
--- a/fs/smb/client/cifsproto.h
+++ b/fs/smb/client/cifsproto.h
@@ -89,7 +89,6 @@ int cifs_handle_standard(struct TCP_Server_Info *server,
 			 struct mid_q_entry *mid);
 char *smb3_fs_context_fullpath(const struct smb3_fs_context *ctx, char dirsep);
 int smb3_parse_devname(const char *devname, struct smb3_fs_context *ctx);
-int smb3_parse_opt(const char *options, const char *key, char **val);
 int cifs_ipaddr_cmp(struct sockaddr *srcaddr, struct sockaddr *rhs);
 bool cifs_match_ipaddr(struct sockaddr *srcaddr, struct sockaddr *rhs);
 int cifs_discard_remaining_data(struct TCP_Server_Info *server);
diff --git a/fs/smb/client/fs_context.c b/fs/smb/client/fs_context.c
index b9544eb0381b..b63ec7ab6e51 100644
--- a/fs/smb/client/fs_context.c
+++ b/fs/smb/client/fs_context.c
@@ -536,37 +536,6 @@ cifs_parse_smb_version(struct fs_context *fc, char *value, struct smb3_fs_contex
 	return 0;
 }
 
-int smb3_parse_opt(const char *options, const char *key, char **val)
-{
-	int rc = -ENOENT;
-	char *opts, *orig, *p;
-
-	orig = opts = kstrdup(options, GFP_KERNEL);
-	if (!opts)
-		return -ENOMEM;
-
-	while ((p = strsep(&opts, ","))) {
-		char *nval;
-
-		if (!*p)
-			continue;
-		if (strncasecmp(p, key, strlen(key)))
-			continue;
-		nval = strchr(p, '=');
-		if (nval) {
-			if (nval == p)
-				continue;
-			*nval++ = 0;
-			*val = kstrdup(nval, GFP_KERNEL);
-			rc = !*val ? -ENOMEM : 0;
-			goto out;
-		}
-	}
-out:
-	kfree(orig);
-	return rc;
-}
-
 /*
  * Remove duplicate path delimiters. Windows is supposed to do that
  * but there are some bugs that prevent rename from working if there are
diff --git a/fs/udf/misc.c b/fs/udf/misc.c
index 0788593b6a1d..6928e378fbbd 100644
--- a/fs/udf/misc.c
+++ b/fs/udf/misc.c
@@ -230,8 +230,12 @@ struct buffer_head *udf_read_tagged(struct super_block *sb, uint32_t block,
 	}
 
 	/* Verify the descriptor CRC */
-	if (le16_to_cpu(tag_p->descCRCLength) + sizeof(struct tag) > sb->s_blocksize ||
-	    le16_to_cpu(tag_p->descCRC) == crc_itu_t(0,
+	if (le16_to_cpu(tag_p->descCRCLength) + sizeof(struct tag) > sb->s_blocksize) {
+		udf_err(sb, "block %u: CRC length %u exceeds block size\n",
+			block, le16_to_cpu(tag_p->descCRCLength));
+		goto error_out;
+	}
+	if (le16_to_cpu(tag_p->descCRC) == crc_itu_t(0,
 					bh->b_data + sizeof(struct tag),
 					le16_to_cpu(tag_p->descCRCLength)))
 		return bh;
diff --git a/fs/udf/super.c b/fs/udf/super.c
index cad2e15d633b..be4085da2104 100644
--- a/fs/udf/super.c
+++ b/fs/udf/super.c
@@ -2321,7 +2321,7 @@ static int udf_fill_super(struct super_block *sb, struct fs_context *fc)
 
 error_out:
 	iput(sbi->s_vat_inode);
-	unload_nls(uopt->nls_map);
+	unload_nls(sbi->s_nls_map);
 	if (lvid_open)
 		udf_close_lvid(sb);
 	brelse(sbi->s_lvid_bh);
diff --git a/fs/unicode/utf8-core.c b/fs/unicode/utf8-core.c
index 543c60c12461..8c4b8e27e956 100644
--- a/fs/unicode/utf8-core.c
+++ b/fs/unicode/utf8-core.c
@@ -138,28 +138,6 @@ int utf8_casefold_hash(const struct unicode_map *um, const void *salt,
 }
 EXPORT_SYMBOL(utf8_casefold_hash);
 
-int utf8_normalize(const struct unicode_map *um, const struct qstr *str,
-		   unsigned char *dest, size_t dlen)
-{
-	struct utf8cursor cur;
-	ssize_t nlen = 0;
-
-	if (utf8ncursor(&cur, um, UTF8_NFDI, str->name, str->len) < 0)
-		return -EINVAL;
-
-	for (nlen = 0; nlen < dlen; nlen++) {
-		int c = utf8byte(&cur);
-
-		dest[nlen] = c;
-		if (!c)
-			return nlen;
-		if (c == -1)
-			break;
-	}
-	return -EINVAL;
-}
-EXPORT_SYMBOL(utf8_normalize);
-
 static const struct utf8data *find_table_version(const struct utf8data *table,
 		size_t nr_entries, unsigned int version)
 {
diff --git a/include/asm-generic/barrier.h b/include/asm-generic/barrier.h
index d4f581c1e21d..68d9e7108f4a 100644
--- a/include/asm-generic/barrier.h
+++ b/include/asm-generic/barrier.h
@@ -273,6 +273,101 @@ do {									\
 })
 #endif
 
+/*
+ * Number of times we iterate in the loop before doing the time check.
+ * Note that the iteration count assumes that the loop condition is
+ * relatively cheap.
+ */
+#ifndef SMP_TIMEOUT_POLL_COUNT
+#define SMP_TIMEOUT_POLL_COUNT		200
+#endif
+
+/*
+ * Platforms with ARCH_HAS_CPU_RELAX have a cpu_poll_relax() implementation
+ * that is expected to be cheaper (lower power) than pure polling.
+ */
+#ifndef cpu_poll_relax
+#define cpu_poll_relax(ptr, val, timeout_ns)	cpu_relax()
+#endif
+
+/**
+ * smp_cond_load_relaxed_timeout() - (Spin) wait for cond with no ordering
+ * guarantees until a timeout expires.
+ * @ptr: pointer to the variable to wait on.
+ * @cond_expr: boolean expression to wait for.
+ * @time_expr_ns: expression that evaluates to monotonic time (in ns) or,
+ *  on failure, returns a negative value.
+ * @timeout_ns: timeout value in ns
+ * Both of the above are assumed to be compatible with s64; the signed
+ * value is used to handle the failure case in @time_expr_ns.
+ *
+ * Equivalent to using READ_ONCE() on the condition variable.
+ *
+ * Callers that expect to wait for prolonged durations might want
+ * to take into account the availability of ARCH_HAS_CPU_RELAX.
+ *
+ * Note that @ptr is expected to point to a memory address. Using this
+ * interface with MMIO will be slower (since SMP_TIMEOUT_POLL_COUNT is
+ * tuned for memory) and might also break in interesting architecture
+ * dependent ways.
+ */
+#ifndef smp_cond_load_relaxed_timeout
+#define smp_cond_load_relaxed_timeout(ptr, cond_expr,			\
+				      time_expr_ns, timeout_ns)		\
+({									\
+	typeof(ptr) __PTR = (ptr);					\
+	__unqual_scalar_typeof(*ptr) VAL;				\
+	u32 __n = 0, __spin = SMP_TIMEOUT_POLL_COUNT;			\
+	s64 __timeout = (s64)timeout_ns;				\
+	s64 __time_now, __time_end = 0;					\
+									\
+	for (;;) {							\
+		VAL = READ_ONCE(*__PTR);				\
+		if (cond_expr)						\
+			break;						\
+		cpu_poll_relax(__PTR, VAL, (u64)__timeout);		\
+		if (++__n < __spin)					\
+			continue;					\
+		__time_now = (s64)(time_expr_ns);			\
+		if (unlikely(__time_end == 0))				\
+			__time_end = __time_now + __timeout;		\
+		__timeout = __time_end - __time_now;			\
+		if (__time_now <= 0 || __timeout <= 0) {		\
+			VAL = READ_ONCE(*__PTR);			\
+			break;						\
+		}							\
+		__n = 0;						\
+	}								\
+	(typeof(*ptr))VAL;						\
+})
+#endif
+
+/**
+ * smp_cond_load_acquire_timeout() - (Spin) wait for cond with ACQUIRE ordering
+ * until a timeout expires.
+ * @ptr: pointer to the variable to wait on.
+ * @cond_expr: boolean expression to wait for.
+ * @time_expr_ns: monotonic expression that evaluates to time in ns or,
+ *  on failure, returns a negative value.
+ * @timeout_ns: timeout value in ns
+ * (Both of the above are assumed to be compatible with s64.)
+ *
+ * Equivalent to using smp_cond_load_acquire() on the condition variable with
+ * a timeout.
+ */
+#ifndef smp_cond_load_acquire_timeout
+#define smp_cond_load_acquire_timeout(ptr, cond_expr,			\
+				      time_expr_ns, timeout_ns)		\
+({									\
+	__unqual_scalar_typeof(*ptr) _val;				\
+	_val = smp_cond_load_relaxed_timeout(ptr, cond_expr,		\
+					     time_expr_ns,		\
+					     timeout_ns);		\
+	smp_acquire__after_ctrl_dep();					\
+	(typeof(*ptr))_val;						\
+})
+#endif
+
 /*
  * pmem_wmb() ensures that all stores for which the modification
  * are written to persistent storage by preceding instructions have
diff --git a/include/drm/drm_fb_helper.h b/include/drm/drm_fb_helper.h
index bf391903443d..80c81fdb04a2 100644
--- a/include/drm/drm_fb_helper.h
+++ b/include/drm/drm_fb_helper.h
@@ -273,6 +273,14 @@ int drm_fb_helper_hotplug_event(struct drm_fb_helper *fb_helper);
 int drm_fb_helper_initial_config(struct drm_fb_helper *fb_helper);
 bool drm_fb_helper_gem_is_fb(const struct drm_fb_helper *fb_helper,
 			     const struct drm_gem_object *obj);
+#else
+static inline bool
+drm_fb_helper_gem_is_fb(const struct drm_fb_helper *fb_helper,
+			const struct drm_gem_object *obj)
+{
+	return false;
+}
+
 #endif
 
 #endif
diff --git a/include/drm/drm_ras.h b/include/drm/drm_ras.h
index 5d50209e51db..f2a787bc4f64 100644
--- a/include/drm/drm_ras.h
+++ b/include/drm/drm_ras.h
@@ -58,6 +58,17 @@ struct drm_ras_node {
 	int (*query_error_counter)(struct drm_ras_node *node, u32 error_id,
 				   const char **name, u32 *val);
 
+	/**
+	 * @clear_error_counter:
+	 *
+	 * This callback is used by drm_ras to clear a specific error counter.
+	 * Driver should implement this callback to support clearing error counters
+	 * of a node.
+	 *
+	 * Returns: 0 on success, negative error code on failure.
+	 */
+	int (*clear_error_counter)(struct drm_ras_node *node, u32 error_id);
+
 	/** @priv: Driver private data */
 	void *priv;
 };
diff --git a/include/keys/trusted-type.h b/include/keys/trusted-type.h
index 03527162613f..9f9940482da4 100644
--- a/include/keys/trusted-type.h
+++ b/include/keys/trusted-type.h
@@ -83,18 +83,21 @@ struct trusted_key_source {
 
 extern struct key_type key_type_trusted;
 
-#define TRUSTED_DEBUG 0
+#ifdef CONFIG_TRUSTED_KEYS_DEBUG
+extern bool trusted_debug;
 
-#if TRUSTED_DEBUG
 static inline void dump_payload(struct trusted_key_payload *p)
 {
-	pr_info("key_len %d\n", p->key_len);
-	print_hex_dump(KERN_INFO, "key ", DUMP_PREFIX_NONE,
-		       16, 1, p->key, p->key_len, 0);
-	pr_info("bloblen %d\n", p->blob_len);
-	print_hex_dump(KERN_INFO, "blob ", DUMP_PREFIX_NONE,
-		       16, 1, p->blob, p->blob_len, 0);
-	pr_info("migratable %d\n", p->migratable);
+	if (!trusted_debug)
+		return;
+
+	pr_debug("key_len %d\n", p->key_len);
+	print_hex_dump_debug("key ", DUMP_PREFIX_NONE,
+			     16, 1, p->key, p->key_len, 0);
+	pr_debug("bloblen %d\n", p->blob_len);
+	print_hex_dump_debug("blob ", DUMP_PREFIX_NONE,
+			     16, 1, p->blob, p->blob_len, 0);
+	pr_debug("migratable %d\n", p->migratable);
 }
 #else
 static inline void dump_payload(struct trusted_key_payload *p)
diff --git a/include/linux/atomic.h b/include/linux/atomic.h
index 8dd57c3a99e9..5bcb86e07784 100644
--- a/include/linux/atomic.h
+++ b/include/linux/atomic.h
@@ -31,6 +31,16 @@
 #define atomic64_cond_read_acquire(v, c) smp_cond_load_acquire(&(v)->counter, (c))
 #define atomic64_cond_read_relaxed(v, c) smp_cond_load_relaxed(&(v)->counter, (c))
 
+#define atomic_cond_read_acquire_timeout(v, c, e, t) \
+	smp_cond_load_acquire_timeout(&(v)->counter, (c), (e), (t))
+#define atomic_cond_read_relaxed_timeout(v, c, e, t) \
+	smp_cond_load_relaxed_timeout(&(v)->counter, (c), (e), (t))
+
+#define atomic64_cond_read_acquire_timeout(v, c, e, t) \
+	smp_cond_load_acquire_timeout(&(v)->counter, (c), (e), (t))
+#define atomic64_cond_read_relaxed_timeout(v, c, e, t) \
+	smp_cond_load_relaxed_timeout(&(v)->counter, (c), (e), (t))
+
 /*
  * The idea here is to build acquire/release variants by adding explicit
  * barriers on top of the relaxed variant. In the case where the relaxed
diff --git a/include/linux/atomic/atomic-long.h b/include/linux/atomic/atomic-long.h
index 6a4e47d2db35..553b6b0e0258 100644
--- a/include/linux/atomic/atomic-long.h
+++ b/include/linux/atomic/atomic-long.h
@@ -11,14 +11,18 @@
 
 #ifdef CONFIG_64BIT
 typedef atomic64_t atomic_long_t;
-#define ATOMIC_LONG_INIT(i)		ATOMIC64_INIT(i)
-#define atomic_long_cond_read_acquire	atomic64_cond_read_acquire
-#define atomic_long_cond_read_relaxed	atomic64_cond_read_relaxed
+#define ATOMIC_LONG_INIT(i)			ATOMIC64_INIT(i)
+#define atomic_long_cond_read_acquire		atomic64_cond_read_acquire
+#define atomic_long_cond_read_relaxed		atomic64_cond_read_relaxed
+#define atomic_long_cond_read_acquire_timeout	atomic64_cond_read_acquire_timeout
+#define atomic_long_cond_read_relaxed_timeout	atomic64_cond_read_relaxed_timeout
 #else
 typedef atomic_t atomic_long_t;
-#define ATOMIC_LONG_INIT(i)		ATOMIC_INIT(i)
-#define atomic_long_cond_read_acquire	atomic_cond_read_acquire
-#define atomic_long_cond_read_relaxed	atomic_cond_read_relaxed
+#define ATOMIC_LONG_INIT(i)			ATOMIC_INIT(i)
+#define atomic_long_cond_read_acquire		atomic_cond_read_acquire
+#define atomic_long_cond_read_relaxed		atomic_cond_read_relaxed
+#define atomic_long_cond_read_acquire_timeout	atomic_cond_read_acquire_timeout
+#define atomic_long_cond_read_relaxed_timeout	atomic_cond_read_relaxed_timeout
 #endif
 
 /**
@@ -1809,4 +1813,4 @@ raw_atomic_long_dec_if_positive(atomic_long_t *v)
 }
 
 #endif /* _LINUX_ATOMIC_LONG_H */
-// 4b882bf19018602c10816c52f8b4ae280adc887b
+// 79c1f4acb5774376ceed559843d5d9ed1348df99
diff --git a/include/linux/bio.h b/include/linux/bio.h
index 97d747320b35..0b6744557b42 100644
--- a/include/linux/bio.h
+++ b/include/linux/bio.h
@@ -256,6 +256,12 @@ static inline struct folio *bio_first_folio_all(struct bio *bio)
 	return page_folio(bio_first_page_all(bio));
 }
 
+static inline struct bio_vec *bio_last_bvec_all(struct bio *bio)
+{
+	WARN_ON_ONCE(bio_flagged(bio, BIO_CLONED));
+	return &bio->bi_io_vec[bio->bi_vcnt - 1];
+}
+
 /**
  * struct folio_iter - State for iterating all folios in a bio.
  * @folio: The current folio we're iterating.  NULL after the last folio.
diff --git a/include/linux/bpf.h b/include/linux/bpf.h
index b4b703c90ca9..01e203964892 100644
--- a/include/linux/bpf.h
+++ b/include/linux/bpf.h
@@ -3725,6 +3725,7 @@ extern const struct bpf_func_proto bpf_for_each_map_elem_proto;
 extern const struct bpf_func_proto bpf_btf_find_by_name_kind_proto;
 extern const struct bpf_func_proto bpf_sk_setsockopt_proto;
 extern const struct bpf_func_proto bpf_sk_getsockopt_proto;
+extern const struct bpf_func_proto bpf_sk_setsockopt_nodelay_proto;
 extern const struct bpf_func_proto bpf_unlocked_sk_setsockopt_proto;
 extern const struct bpf_func_proto bpf_unlocked_sk_getsockopt_proto;
 extern const struct bpf_func_proto bpf_find_vma_proto;
diff --git a/include/linux/codetag.h b/include/linux/codetag.h
index 8ea2a5f7c98a..ddae7484ca45 100644
--- a/include/linux/codetag.h
+++ b/include/linux/codetag.h
@@ -74,8 +74,9 @@ struct codetag_iterator {
 	.flags		= 0,				\
 }
 
-void codetag_lock_module_list(struct codetag_type *cttype, bool lock);
+void codetag_lock_module_list(struct codetag_type *cttype);
 bool codetag_trylock_module_list(struct codetag_type *cttype);
+void codetag_unlock_module_list(struct codetag_type *cttype);
 struct codetag_iterator codetag_get_ct_iter(struct codetag_type *cttype);
 struct codetag *codetag_next_ct(struct codetag_iterator *iter);
 
diff --git a/include/linux/dma-buf.h b/include/linux/dma-buf.h
index 166933b82e27..d1203da56fc5 100644
--- a/include/linux/dma-buf.h
+++ b/include/linux/dma-buf.h
@@ -322,13 +322,13 @@ struct dma_buf {
 	 * @vmapping_counter:
 	 *
 	 * Used internally to refcnt the vmaps returned by dma_buf_vmap().
-	 * Protected by @lock.
+	 * Protected by @resv.
 	 */
 	unsigned vmapping_counter;
 
 	/**
 	 * @vmap_ptr:
-	 * The current vmap ptr if @vmapping_counter > 0. Protected by @lock.
+	 * The current vmap ptr if @vmapping_counter > 0. Protected by @resv.
 	 */
 	struct iosys_map vmap_ptr;
 
diff --git a/include/linux/fsl/mc.h b/include/linux/fsl/mc.h
index 1da63f2d7040..9f671e87c80c 100644
--- a/include/linux/fsl/mc.h
+++ b/include/linux/fsl/mc.h
@@ -357,9 +357,11 @@ int mc_send_command(struct fsl_mc_io *mc_io, struct fsl_mc_command *cmd);
 
 #ifdef CONFIG_FSL_MC_BUS
 #define dev_is_fsl_mc(_dev) ((_dev)->bus == &fsl_mc_bus_type)
+u32 fsl_mc_get_msi_id(struct device *dev);
 #else
 /* If fsl-mc bus is not present device cannot belong to fsl-mc bus */
 #define dev_is_fsl_mc(_dev) (0)
+#define fsl_mc_get_msi_id(_dev)	(0)
 #endif
 
 /* Macro to check if a device is a container device */
@@ -419,10 +421,6 @@ int __must_check fsl_mc_object_allocate(struct fsl_mc_device *mc_dev,
 
 void fsl_mc_object_free(struct fsl_mc_device *mc_adev);
 
-struct irq_domain *fsl_mc_msi_create_irq_domain(struct fwnode_handle *fwnode,
-						struct msi_domain_info *info,
-						struct irq_domain *parent);
-
 int __must_check fsl_mc_allocate_irqs(struct fsl_mc_device *mc_dev);
 
 void fsl_mc_free_irqs(struct fsl_mc_device *mc_dev);
diff --git a/include/linux/fsnotify_backend.h b/include/linux/fsnotify_backend.h
index 95985400d3d8..e5cde39d6e85 100644
--- a/include/linux/fsnotify_backend.h
+++ b/include/linux/fsnotify_backend.h
@@ -915,6 +915,7 @@ extern void fsnotify_clear_marks_by_group(struct fsnotify_group *group,
 					  unsigned int obj_type);
 extern void fsnotify_get_mark(struct fsnotify_mark *mark);
 extern void fsnotify_put_mark(struct fsnotify_mark *mark);
+struct fsnotify_mark *fsnotify_next_mark(struct fsnotify_mark *mark);
 extern void fsnotify_finish_user_wait(struct fsnotify_iter_info *iter_info);
 extern bool fsnotify_prepare_user_wait(struct fsnotify_iter_info *iter_info);
 
diff --git a/include/linux/gfp_types.h b/include/linux/gfp_types.h
index 6c75df30a281..cd4972a7c97c 100644
--- a/include/linux/gfp_types.h
+++ b/include/linux/gfp_types.h
@@ -273,11 +273,11 @@ enum {
  *
  * %__GFP_ZERO returns a zeroed page on success.
  *
- * %__GFP_ZEROTAGS zeroes memory tags at allocation time if the memory itself
- * is being zeroed (either via __GFP_ZERO or via init_on_alloc, provided that
- * __GFP_SKIP_ZERO is not set). This flag is intended for optimization: setting
- * memory tags at the same time as zeroing memory has minimal additional
- * performance impact.
+ * %__GFP_ZEROTAGS zeroes memory tags at allocation time. Setting memory tags at
+ * the same time as zeroing memory (e.g., with __GFP_ZERO) has minimal
+ * additional performance impact. However, __GFP_ZEROTAGS also zeroes the tags
+ * even if memory is not getting zeroed at allocation time (e.g.,
+ * with init_on_free).
  *
  * %__GFP_SKIP_KASAN makes KASAN skip unpoisoning on page allocation.
  * Used for userspace and vmalloc pages; the latter are unpoisoned by
diff --git a/include/linux/highmem.h b/include/linux/highmem.h
index af03db851a1d..d7aac9de1c8a 100644
--- a/include/linux/highmem.h
+++ b/include/linux/highmem.h
@@ -347,10 +347,11 @@ static inline void clear_highpage_kasan_tagged(struct page *page)
 
 #ifndef __HAVE_ARCH_TAG_CLEAR_HIGHPAGES
 
-/* Return false to let people know we did not initialize the pages */
-static inline bool tag_clear_highpages(struct page *page, int numpages)
+/* Returns true if the caller has to initialize the pages */
+static inline bool tag_clear_highpages(struct page *page, int numpages,
+		bool clear_pages)
 {
-	return false;
+	return clear_pages;
 }
 
 #endif
diff --git a/include/linux/init.h b/include/linux/init.h
index 40331923b9f4..6326c61e2332 100644
--- a/include/linux/init.h
+++ b/include/linux/init.h
@@ -47,7 +47,7 @@
 #define __initdata	__section(".init.data")
 #define __initconst	__section(".init.rodata")
 #define __exitdata	__section(".exit.data")
-#define __exit_call	__used __section(".exitcall.exit")
+#define __exit_call	__maybe_unused __section(".exitcall.exit")
 
 /*
  * modpost check for section mismatches during the kernel build.
diff --git a/include/linux/irqdomain_defs.h b/include/linux/irqdomain_defs.h
index 36653e2ee1c9..3a03bdfeeee9 100644
--- a/include/linux/irqdomain_defs.h
+++ b/include/linux/irqdomain_defs.h
@@ -17,7 +17,6 @@ enum irq_domain_bus_token {
 	DOMAIN_BUS_PLATFORM_MSI,
 	DOMAIN_BUS_NEXUS,
 	DOMAIN_BUS_IPI,
-	DOMAIN_BUS_FSL_MC_MSI,
 	DOMAIN_BUS_TI_SCI_INTA_MSI,
 	DOMAIN_BUS_WAKEUP,
 	DOMAIN_BUS_VMD_MSI,
diff --git a/include/linux/kallsyms.h b/include/linux/kallsyms.h
index d5dd54c53ace..7d4c9dca06c8 100644
--- a/include/linux/kallsyms.h
+++ b/include/linux/kallsyms.h
@@ -16,10 +16,15 @@
 #include <asm/sections.h>
 
 #define KSYM_NAME_LEN 512
+
+/* Extra space for " (path/to/file.c:12345)" suffix when lineinfo is enabled */
+#define KSYM_LINEINFO_LEN (IS_ENABLED(CONFIG_KALLSYMS_LINEINFO) ? 128 : 0)
+
 #define KSYM_SYMBOL_LEN (sizeof("%s+%#lx/%#lx [%s %s]") + \
 			(KSYM_NAME_LEN - 1) + \
 			2*(BITS_PER_LONG*3/10) + (MODULE_NAME_LEN - 1) + \
-			(BUILD_ID_SIZE_MAX * 2) + 1)
+			(BUILD_ID_SIZE_MAX * 2) + 1 + \
+			KSYM_LINEINFO_LEN)
 
 struct cred;
 struct module;
@@ -96,6 +101,9 @@ extern int sprint_backtrace_build_id(char *buffer, unsigned long address);
 
 int lookup_symbol_name(unsigned long addr, char *symname);
 
+bool kallsyms_lookup_lineinfo(unsigned long addr,
+			      const char **file, unsigned int *line);
+
 #else /* !CONFIG_KALLSYMS */
 
 static inline unsigned long kallsyms_lookup_name(const char *name)
@@ -164,6 +172,13 @@ static inline int kallsyms_on_each_match_symbol(int (*fn)(void *, unsigned long)
 {
 	return -EOPNOTSUPP;
 }
+
+static inline bool kallsyms_lookup_lineinfo(unsigned long addr,
+					    const char **file,
+					    unsigned int *line)
+{
+	return false;
+}
 #endif /*CONFIG_KALLSYMS*/
 
 static inline void print_ip_sym(const char *loglvl, unsigned long ip)
diff --git a/include/linux/mailbox_client.h b/include/linux/mailbox_client.h
index c6eea9afb943..e5997120f45c 100644
--- a/include/linux/mailbox_client.h
+++ b/include/linux/mailbox_client.h
@@ -45,6 +45,7 @@ int mbox_send_message(struct mbox_chan *chan, void *mssg);
 int mbox_flush(struct mbox_chan *chan, unsigned long timeout);
 void mbox_client_txdone(struct mbox_chan *chan, int r); /* atomic */
 bool mbox_client_peek_data(struct mbox_chan *chan); /* atomic */
+unsigned int mbox_chan_tx_slots_available(struct mbox_chan *chan); /* atomic */
 void mbox_free_channel(struct mbox_chan *chan); /* may sleep */
 
 #endif /* __MAILBOX_CLIENT_H */
diff --git a/include/linux/mailbox_controller.h b/include/linux/mailbox_controller.h
index 80a427c7ca29..dc93287a2a01 100644
--- a/include/linux/mailbox_controller.h
+++ b/include/linux/mailbox_controller.h
@@ -3,6 +3,7 @@
 #ifndef __MAILBOX_CONTROLLER_H
 #define __MAILBOX_CONTROLLER_H
 
+#include <linux/bits.h>
 #include <linux/completion.h>
 #include <linux/device.h>
 #include <linux/hrtimer.h>
@@ -11,6 +12,13 @@
 
 struct mbox_chan;
 
+/* Sentinel value distinguishing "no active request" from "NULL message data" */
+#define MBOX_NO_MSG	((void *)-1)
+
+#define MBOX_TXDONE_BY_IRQ	BIT(0) /* controller has remote RTR irq */
+#define MBOX_TXDONE_BY_POLL	BIT(1) /* controller can read status of last TX */
+#define MBOX_TXDONE_BY_ACK	BIT(2) /* S/W ACK received by Client ticks the TX */
+
 /**
  * struct mbox_chan_ops - methods to control mailbox channels
  * @send_data:	The API asks the MBOX controller driver, in atomic
@@ -54,10 +62,10 @@ struct mbox_chan_ops {
 
 /**
  * struct mbox_controller - Controller of a class of communication channels
- * @dev:		Device backing this controller
- * @ops:		Operators that work on each communication chan
- * @chans:		Array of channels
- * @num_chans:		Number of channels in the 'chans' array.
+ * @dev:		Device backing this controller. Required.
+ * @ops:		Operators that work on each communication chan. Required.
+ * @chans:		Array of channels. Required.
+ * @num_chans:		Number of channels in the 'chans' array. Required.
  * @txdone_irq:		Indicates if the controller can report to API when
  *			the last transmitted data was read by the remote.
  *			Eg, if it has some TX ACK irq.
@@ -70,6 +78,7 @@ struct mbox_chan_ops {
  * @of_xlate:		Controller driver specific mapping of channel via DT
  * @poll_hrt:		API private. hrtimer used to poll for TXDONE on all
  *			channels.
+ * @poll_hrt_lock:	API private. Lock protecting access to poll_hrt.
  * @node:		API private. To hook into list of controllers.
  */
 struct mbox_controller {
diff --git a/include/linux/maple_tree.h b/include/linux/maple_tree.h
index 0c464eade1d6..4a5631906aff 100644
--- a/include/linux/maple_tree.h
+++ b/include/linux/maple_tree.h
@@ -4,7 +4,7 @@
 /*
  * Maple Tree - An RCU-safe adaptive tree for storing ranges
  * Copyright (c) 2018-2022 Oracle
- * Authors:     Liam R. Howlett <Liam.Howlett@Oracle.com>
+ * Authors:     Liam R. Howlett <liam@infradead.org>
  *              Matthew Wilcox <willy@infradead.org>
  */
 
diff --git a/include/linux/mm.h b/include/linux/mm.h
index 0b776907152e..af23453e9dbd 100644
--- a/include/linux/mm.h
+++ b/include/linux/mm.h
@@ -4391,7 +4391,7 @@ static inline void mmap_action_map_kernel_pages_full(struct vm_area_desc *desc,
 
 int mmap_action_prepare(struct vm_area_desc *desc);
 int mmap_action_complete(struct vm_area_struct *vma,
-			 struct mmap_action *action);
+			 struct mmap_action *action, bool is_compat);
 
 /* Look up the first VMA which exactly match the interval vm_start ... vm_end */
 static inline struct vm_area_struct *find_exact_vma(struct mm_struct *mm,
diff --git a/include/linux/mod_lineinfo.h b/include/linux/mod_lineinfo.h
new file mode 100644
index 000000000000..364e5d81fe5b
--- /dev/null
+++ b/include/linux/mod_lineinfo.h
@@ -0,0 +1,243 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * mod_lineinfo.h - Binary format for per-module source line information
+ *
+ * This header defines the layout of the .mod_lineinfo section embedded
+ * in loadable kernel modules.  It is dual-use: included from both the
+ * kernel and the userspace gen_lineinfo tool.
+ *
+ * Section layout (all values in target-native endianness):
+ *
+ *   struct mod_lineinfo_header
+ *   u32 block_addrs[num_blocks]    -- first addr per block, for binary search
+ *   u32 block_offsets[num_blocks]  -- byte offset into compressed data stream
+ *   u8  data[data_size]            -- LEB128 delta-compressed entries
+ *   u32 file_offsets[num_files]    -- byte offset into filenames[]
+ *   char filenames[filenames_size] -- concatenated NUL-terminated strings
+ *
+ * Each sub-array is located by an explicit (offset, size) pair in the
+ * header, similar to a flattened devicetree.  This makes bounds checking
+ * straightforward: validate offset + size <= section_size for each array.
+ *
+ * Compressed stream format (per block of LINEINFO_BLOCK_ENTRIES entries):
+ *   Entry 0: file_id (ULEB128), line (ULEB128)
+ *            addr is in block_addrs[]
+ *   Entry 1..N: addr_delta (ULEB128),
+ *               file_id_delta (SLEB128),
+ *               line_delta (SLEB128)
+ */
+#ifndef _LINUX_MOD_LINEINFO_H
+#define _LINUX_MOD_LINEINFO_H
+
+#ifdef __KERNEL__
+#include <linux/types.h>
+#else
+#include <stdint.h>
+typedef uint32_t u32;
+typedef uint16_t u16;
+typedef uint8_t  u8;
+#endif
+
+#define LINEINFO_BLOCK_ENTRIES 64
+
+struct mod_lineinfo_header {
+	u32 num_entries;
+	u32 num_blocks;
+	u32 num_files;
+	u32 blocks_offset;	/* offset to block_addrs[] from section start */
+	u32 blocks_size;	/* bytes: num_blocks * 2 * sizeof(u32) */
+	u32 data_offset;	/* offset to compressed stream */
+	u32 data_size;		/* bytes of compressed data */
+	u32 files_offset;	/* offset to file_offsets[] */
+	u32 files_size;		/* bytes: num_files * sizeof(u32) */
+	u32 filenames_offset;
+	u32 filenames_size;
+	u32 reserved;		/* must be 0 */
+};
+
+/*
+ * Descriptor for a lineinfo table, used by the shared lookup function.
+ * Callers populate this from either linker globals (vmlinux) or a
+ * validated mod_lineinfo_header (modules).
+ */
+struct lineinfo_table {
+	const u32 *blk_addrs;
+	const u32 *blk_offsets;
+	const u8  *data;
+	u32 data_size;
+	const u32 *file_offsets;
+	const char *filenames;
+	u32 num_entries;
+	u32 num_blocks;
+	u32 num_files;
+	u32 filenames_size;
+};
+
+/*
+ * Read a ULEB128 varint from a byte stream.
+ * Returns the decoded value and advances *pos past the encoded bytes.
+ * If *pos would exceed 'end', returns 0 and sets *pos = end (safe for
+ * NMI/panic context: no crash, just a missed annotation).
+ */
+static inline u32 lineinfo_read_uleb128(const u8 *data, u32 *pos, u32 end)
+{
+	u32 result = 0;
+	unsigned int shift = 0;
+
+	while (*pos < end) {
+		u8 byte = data[*pos];
+		(*pos)++;
+		result |= (u32)(byte & 0x7f) << shift;
+		if (!(byte & 0x80))
+			return result;
+		shift += 7;
+		if (shift >= 32) {
+			/* Malformed: skip remaining continuation bytes */
+			while (*pos < end && (data[*pos] & 0x80))
+				(*pos)++;
+			if (*pos < end)
+				(*pos)++;
+			return result;
+		}
+	}
+	return result;
+}
+
+/* Read an SLEB128 varint. Same safety guarantees as above. */
+static inline int32_t lineinfo_read_sleb128(const u8 *data, u32 *pos, u32 end)
+{
+	int32_t result = 0;
+	unsigned int shift = 0;
+	u8 byte = 0;
+
+	while (*pos < end) {
+		byte = data[*pos];
+		(*pos)++;
+		result |= (int32_t)(byte & 0x7f) << shift;
+		shift += 7;
+		if (!(byte & 0x80))
+			break;
+		if (shift >= 32) {
+			while (*pos < end && (data[*pos] & 0x80))
+				(*pos)++;
+			if (*pos < end)
+				(*pos)++;
+			return result;
+		}
+	}
+
+	/* Sign-extend if the high bit of the last byte was set */
+	if (shift < 32 && (byte & 0x40))
+		result |= -(1 << shift);
+
+	return result;
+}
+
+/*
+ * Search a lineinfo table for the source file and line corresponding to a
+ * given offset (from _text for vmlinux, from .text base for modules).
+ *
+ * Safe for NMI and panic context: no locks, no allocations, all state on stack.
+ * Returns true and sets @file and @line on success; false on any failure.
+ */
+static inline bool lineinfo_search(const struct lineinfo_table *tbl,
+				   unsigned int offset,
+				   const char **file, unsigned int *line)
+{
+	unsigned int low, high, mid, block;
+	unsigned int cur_addr, cur_file_id, cur_line;
+	unsigned int best_file_id = 0, best_line = 0;
+	unsigned int block_entries, data_end;
+	bool found = false;
+	u32 pos;
+
+	if (!tbl->num_entries || !tbl->num_blocks)
+		return false;
+
+	/* Binary search on blk_addrs[] to find the right block */
+	low = 0;
+	high = tbl->num_blocks;
+	while (low < high) {
+		mid = low + (high - low) / 2;
+		if (tbl->blk_addrs[mid] <= offset)
+			low = mid + 1;
+		else
+			high = mid;
+	}
+
+	if (low == 0)
+		return false;
+	block = low - 1;
+
+	/* How many entries in this block? */
+	block_entries = LINEINFO_BLOCK_ENTRIES;
+	if (block == tbl->num_blocks - 1) {
+		unsigned int remaining = tbl->num_entries -
+					block * LINEINFO_BLOCK_ENTRIES;
+
+		if (remaining < block_entries)
+			block_entries = remaining;
+	}
+
+	/* Determine end of this block's data in the compressed stream */
+	if (block + 1 < tbl->num_blocks)
+		data_end = tbl->blk_offsets[block + 1];
+	else
+		data_end = tbl->data_size;
+
+	/* Clamp data_end to actual data size */
+	if (data_end > tbl->data_size)
+		data_end = tbl->data_size;
+
+	/* Decode entry 0: addr from blk_addrs, file_id and line from stream */
+	pos = tbl->blk_offsets[block];
+	if (pos >= data_end)
+		return false;
+
+	cur_addr = tbl->blk_addrs[block];
+	cur_file_id = lineinfo_read_uleb128(tbl->data, &pos, data_end);
+	cur_line = lineinfo_read_uleb128(tbl->data, &pos, data_end);
+
+	/* Check entry 0 */
+	if (cur_addr <= offset) {
+		best_file_id = cur_file_id;
+		best_line = cur_line;
+		found = true;
+	}
+
+	/* Decode entries 1..N */
+	for (unsigned int i = 1; i < block_entries; i++) {
+		unsigned int addr_delta;
+		int32_t file_delta, line_delta;
+
+		addr_delta = lineinfo_read_uleb128(tbl->data, &pos, data_end);
+		file_delta = lineinfo_read_sleb128(tbl->data, &pos, data_end);
+		line_delta = lineinfo_read_sleb128(tbl->data, &pos, data_end);
+
+		cur_addr += addr_delta;
+		cur_file_id = (unsigned int)((int32_t)cur_file_id + file_delta);
+		cur_line = (unsigned int)((int32_t)cur_line + line_delta);
+
+		if (cur_addr > offset)
+			break;
+
+		best_file_id = cur_file_id;
+		best_line = cur_line;
+		found = true;
+	}
+
+	if (!found)
+		return false;
+
+	if (best_file_id >= tbl->num_files)
+		return false;
+
+	if (tbl->file_offsets[best_file_id] >= tbl->filenames_size)
+		return false;
+
+	*file = &tbl->filenames[tbl->file_offsets[best_file_id]];
+	*line = best_line;
+	return true;
+}
+
+#endif /* _LINUX_MOD_LINEINFO_H */
diff --git a/include/linux/module.h b/include/linux/module.h
index 7566815fabbe..428d5461a6be 100644
--- a/include/linux/module.h
+++ b/include/linux/module.h
@@ -507,6 +507,8 @@ struct module {
 	void *btf_data;
 	void *btf_base_data;
 #endif
+	void *lineinfo_data;		/* .mod_lineinfo section in MOD_RODATA */
+	unsigned int lineinfo_data_size;
 #ifdef CONFIG_JUMP_LABEL
 	struct jump_entry *jump_entries;
 	unsigned int num_jump_entries;
@@ -1020,6 +1022,9 @@ static inline unsigned long find_kallsyms_symbol_value(struct module *mod,
 
 #endif  /* CONFIG_MODULES && CONFIG_KALLSYMS */
 
+bool module_lookup_lineinfo(struct module *mod, unsigned long addr,
+			    const char **file, unsigned int *line);
+
 /* Define __free(module_put) macro for struct module *. */
 DEFINE_FREE(module_put, struct module *, if (_T) module_put(_T))
 
diff --git a/include/linux/netdevice.h b/include/linux/netdevice.h
index 0e1e581efc5a..99fcb5ac45bc 100644
--- a/include/linux/netdevice.h
+++ b/include/linux/netdevice.h
@@ -2119,6 +2119,8 @@ enum netdev_reg_state {
  *
  *	FIXME: cleanup struct net_device such that network protocol info
  *	moves out.
+ *
+ *	@netdev_trace_buffer_list: Linked list for debugging refcount leak.
  */
 
 struct net_device {
@@ -2275,6 +2277,9 @@ struct net_device {
 #if IS_ENABLED(CONFIG_TLS_DEVICE)
 	const struct tlsdev_ops *tlsdev_ops;
 #endif
+#ifdef CONFIG_NET_DEV_REFCNT_TRACKER
+	struct list_head	netdev_trace_buffer_list;
+#endif
 
 	unsigned int		operstate;
 	unsigned char		link_mode;
@@ -3219,6 +3224,7 @@ enum netdev_cmd {
 	NETDEV_OFFLOAD_XSTATS_REPORT_USED,
 	NETDEV_OFFLOAD_XSTATS_REPORT_DELTA,
 	NETDEV_XDP_FEAT_CHANGE,
+	NETDEV_DEBUG_UNREGISTER,
 };
 const char *netdev_cmd_to_name(enum netdev_cmd cmd);
 
@@ -4441,9 +4447,15 @@ static inline bool dev_nit_active(const struct net_device *dev)
 
 void dev_queue_xmit_nit(struct sk_buff *skb, struct net_device *dev);
 
+void save_netdev_trace_buffer(struct net_device *dev, int delta);
+int trim_netdev_trace(unsigned long *entries, int nr_entries);
+
 static inline void __dev_put(struct net_device *dev)
 {
 	if (dev) {
+#ifdef CONFIG_NET_DEV_REFCNT_TRACKER
+		save_netdev_trace_buffer(dev, -1);
+#endif
 #ifdef CONFIG_PCPU_DEV_REFCNT
 		this_cpu_dec(*dev->pcpu_refcnt);
 #else
@@ -4455,6 +4467,9 @@ static inline void __dev_put(struct net_device *dev)
 static inline void __dev_hold(struct net_device *dev)
 {
 	if (dev) {
+#ifdef CONFIG_NET_DEV_REFCNT_TRACKER
+		save_netdev_trace_buffer(dev, 1);
+#endif
 #ifdef CONFIG_PCPU_DEV_REFCNT
 		this_cpu_inc(*dev->pcpu_refcnt);
 #else
diff --git a/include/linux/platform_data/cros_ec_proto.h b/include/linux/platform_data/cros_ec_proto.h
index de14923720a5..6ed1c4c5ce2e 100644
--- a/include/linux/platform_data/cros_ec_proto.h
+++ b/include/linux/platform_data/cros_ec_proto.h
@@ -228,6 +228,7 @@ struct cros_ec_platform {
 /**
  * struct cros_ec_dev - ChromeOS EC device entry point.
  * @class_dev: Device structure used in sysfs.
+ * @group: sysfs attributes groups for this EC.
  * @ec_dev: cros_ec_device structure to talk to the physical device.
  * @dev: Pointer to the platform device.
  * @debug_info: cros_ec_debugfs structure for debugging information.
@@ -237,6 +238,7 @@ struct cros_ec_platform {
  */
 struct cros_ec_dev {
 	struct device class_dev;
+	const struct attribute_group *group;
 	struct cros_ec_device *ec_dev;
 	struct device *dev;
 	struct cros_ec_debugfs *debug_info;
diff --git a/include/linux/rhashtable-types.h b/include/linux/rhashtable-types.h
index 015c8298bebc..fc2f596a6df1 100644
--- a/include/linux/rhashtable-types.h
+++ b/include/linux/rhashtable-types.h
@@ -12,6 +12,7 @@
 #include <linux/alloc_tag.h>
 #include <linux/atomic.h>
 #include <linux/compiler.h>
+#include <linux/irq_work_types.h>
 #include <linux/mutex.h>
 #include <linux/workqueue_types.h>
 
@@ -49,6 +50,7 @@ typedef int (*rht_obj_cmpfn_t)(struct rhashtable_compare_arg *arg,
  * @head_offset: Offset of rhash_head in struct to be hashed
  * @max_size: Maximum size while expanding
  * @min_size: Minimum size while shrinking
+ * @insecure_elasticity: Set to true to disable chain length checks
  * @automatic_shrinking: Enable automatic shrinking of tables
  * @hashfn: Hash function (default: jhash2 if !(key_len % 4), or jhash)
  * @obj_hashfn: Function to hash object
@@ -61,6 +63,7 @@ struct rhashtable_params {
 	u16			head_offset;
 	unsigned int		max_size;
 	u16			min_size;
+	bool			insecure_elasticity;
 	bool			automatic_shrinking;
 	rht_hashfn_t		hashfn;
 	rht_obj_hashfn_t	obj_hashfn;
@@ -75,6 +78,7 @@ struct rhashtable_params {
  * @p: Configuration parameters
  * @rhlist: True if this is an rhltable
  * @run_work: Deferred worker to expand/shrink asynchronously
+ * @run_irq_work: Bounces the @run_work kick through hard IRQ context.
  * @mutex: Mutex to protect current/future table swapping
  * @lock: Spin lock to protect walker list
  * @nelems: Number of elements in table
@@ -86,6 +90,7 @@ struct rhashtable {
 	struct rhashtable_params	p;
 	bool				rhlist;
 	struct work_struct		run_work;
+	struct irq_work			run_irq_work;
 	struct mutex                    mutex;
 	spinlock_t			lock;
 	atomic_t			nelems;
diff --git a/include/linux/rhashtable.h b/include/linux/rhashtable.h
index 0480509a6339..ef5230cece36 100644
--- a/include/linux/rhashtable.h
+++ b/include/linux/rhashtable.h
@@ -20,6 +20,7 @@
 
 #include <linux/err.h>
 #include <linux/errno.h>
+#include <linux/irq_work.h>
 #include <linux/jhash.h>
 #include <linux/list_nulls.h>
 #include <linux/workqueue.h>
@@ -821,14 +822,15 @@ static __always_inline void *__rhashtable_insert_fast(
 		goto out;
 	}
 
-	if (elasticity <= 0)
+	if (elasticity <= 0 && !params.insecure_elasticity)
 		goto slow_path;
 
 	data = ERR_PTR(-E2BIG);
 	if (unlikely(rht_grow_above_max(ht, tbl)))
 		goto out_unlock;
 
-	if (unlikely(rht_grow_above_100(ht, tbl)))
+	if (unlikely(rht_grow_above_100(ht, tbl)) &&
+	    !params.insecure_elasticity)
 		goto slow_path;
 
 	/* Inserting at head of list makes unlocking free. */
@@ -846,7 +848,7 @@ static __always_inline void *__rhashtable_insert_fast(
 	rht_assign_unlock(tbl, bkt, obj, flags);
 
 	if (rht_grow_above_75(ht, tbl))
-		schedule_work(&ht->run_work);
+		irq_work_queue(&ht->run_irq_work);
 
 	data = NULL;
 out:
diff --git a/include/linux/sched/ext.h b/include/linux/sched/ext.h
index 1a3af2ea2a79..d05efcac794d 100644
--- a/include/linux/sched/ext.h
+++ b/include/linux/sched/ext.h
@@ -203,6 +203,15 @@ struct sched_ext_entity {
 	u64			core_sched_at;	/* see scx_prio_less() */
 #endif
 
+	/*
+	 * Unique non-zero task ID assigned at fork. Persists across exec and
+	 * is never reused. Lets BPF schedulers identify tasks without storing
+	 * kernel pointers - arena-backed schedulers being one example. See
+	 * scx_bpf_tid_to_task().
+	 */
+	u64			tid;
+	struct rhash_head	tid_hash_node;	/* see SCX_OPS_TID_TO_TASK */
+
 	/* BPF scheduler modifiable fields */
 
 	/*
diff --git a/include/linux/sched/idle.h b/include/linux/sched/idle.h
index 8465ff1f20d1..ddee9b019895 100644
--- a/include/linux/sched/idle.h
+++ b/include/linux/sched/idle.h
@@ -3,6 +3,7 @@
 #define _LINUX_SCHED_IDLE_H
 
 #include <linux/sched.h>
+#include <linux/sched/clock.h>
 
 enum cpu_idle_type {
 	__CPU_NOT_IDLE = 0,
@@ -113,4 +114,32 @@ static __always_inline void current_clr_polling(void)
 }
 #endif
 
+/*
+ * Caller needs to make sure that the thread context cannot be preempted
+ * or migrated, so current_thread_info() cannot change from under us.
+ *
+ * This also allows us to safely stay in the local_clock domain.
+ */
+static __always_inline bool tif_bitset_relaxed_wait(int tif, u64 timeout_ns)
+{
+	unsigned long flags;
+
+	flags = smp_cond_load_relaxed_timeout(&current_thread_info()->flags,
+					      (VAL & BIT(tif)),
+					      local_clock_noinstr(),
+					      timeout_ns);
+	return flags & BIT(tif);
+}
+
+/**
+ * tif_need_resched_relaxed_wait() - Wait for need-resched being set
+ * with no ordering guarantees until a timeout expires.
+ *
+ * @timeout_ns: timeout value.
+ */
+static __always_inline bool tif_need_resched_relaxed_wait(u64 timeout_ns)
+{
+	return tif_bitset_relaxed_wait(TIF_NEED_RESCHED, timeout_ns);
+}
+
 #endif /* _LINUX_SCHED_IDLE_H */
diff --git a/include/linux/scmi_imx_protocol.h b/include/linux/scmi_imx_protocol.h
index 2407d7693b6b..ab867463c08c 100644
--- a/include/linux/scmi_imx_protocol.h
+++ b/include/linux/scmi_imx_protocol.h
@@ -52,6 +52,17 @@ struct scmi_imx_misc_ctrl_notify_report {
 	unsigned int		flags;
 };
 
+
+#define MISC_EXT_INFO_LEN_MAX	4
+struct scmi_imx_misc_reset_reason {
+	bool valid:1;
+	bool orig_valid:1;
+	bool err_valid:1;
+	u32 reason;
+	u32 origin;
+	u32 errid;
+};
+
 struct scmi_imx_misc_proto_ops {
 	int (*misc_ctrl_set)(const struct scmi_protocol_handle *ph, u32 id,
 			     u32 num, u32 *val);
@@ -61,6 +72,9 @@ struct scmi_imx_misc_proto_ops {
 				    u32 ctrl_id, u32 evt_id, u32 flags);
 	int (*misc_syslog)(const struct scmi_protocol_handle *ph, u16 *size,
 			   void *array);
+	int (*misc_reset_reason)(const struct scmi_protocol_handle *ph,
+				 bool system, struct scmi_imx_misc_reset_reason *boot_r,
+				 struct scmi_imx_misc_reset_reason *shut_r, u32 *extinfo);
 };
 
 /* See LMM_ATTRIBUTES in imx95.rst */
diff --git a/include/linux/scmi_protocol.h b/include/linux/scmi_protocol.h
index aafaac1496b0..49cc39e0cbca 100644
--- a/include/linux/scmi_protocol.h
+++ b/include/linux/scmi_protocol.h
@@ -15,10 +15,9 @@
 
 #define SCMI_MAX_STR_SIZE		64
 #define SCMI_SHORT_NAME_MAX_SIZE	16
-#define SCMI_MAX_NUM_RATES		16
 
 /**
- * struct scmi_revision_info - version information structure
+ * struct scmi_base_info - version information structure
  *
  * @major_ver: Major ABI version. Change here implies risk of backward
  *	compatibility break.
@@ -31,7 +30,7 @@
  * @vendor_id: A vendor identifier(Null terminated ASCII string)
  * @sub_vendor_id: A sub-vendor identifier(Null terminated ASCII string)
  */
-struct scmi_revision_info {
+struct scmi_base_info {
 	u16 major_ver;
 	u16 minor_ver;
 	u8 num_protocols;
@@ -41,6 +40,12 @@ struct scmi_revision_info {
 	char sub_vendor_id[SCMI_SHORT_NAME_MAX_SIZE];
 };
 
+struct scmi_clock_rates {
+	bool rate_discrete;
+	unsigned int num_rates;
+	u64 *rates;
+};
+
 struct scmi_clock_info {
 	char name[SCMI_MAX_STR_SIZE];
 	unsigned int enable_latency;
@@ -51,17 +56,8 @@ struct scmi_clock_info {
 	bool rate_ctrl_forbidden;
 	bool parent_ctrl_forbidden;
 	bool extended_config;
-	union {
-		struct {
-			int num_rates;
-			u64 rates[SCMI_MAX_NUM_RATES];
-		} list;
-		struct {
-			u64 min_rate;
-			u64 max_rate;
-			u64 step_size;
-		} range;
-	};
+	u64 min_rate;
+	u64 max_rate;
 	int num_parents;
 	u32 *parents;
 };
@@ -91,6 +87,11 @@ enum scmi_clock_oem_config {
  * @info_get: get the information of the specified clock
  * @rate_get: request the current clock rate of a clock
  * @rate_set: set the clock rate of a clock
+ * @determine_rate: determine the effective rate that can be supported by a
+ *		    clock calculating the closest allowed rate.
+ *		    Note that @rate is an input/output parameter used both to
+ *		    describe the requested rate and report the closest match
+ * @all_rates_get: get the list of all available rates for the specified clock.
  * @enable: enables the specified clock
  * @disable: disables the specified clock
  * @state_get: get the status of the specified clock
@@ -108,6 +109,10 @@ struct scmi_clk_proto_ops {
 			u64 *rate);
 	int (*rate_set)(const struct scmi_protocol_handle *ph, u32 clk_id,
 			u64 rate);
+	int (*determine_rate)(const struct scmi_protocol_handle *ph, u32 clk_id,
+			      unsigned long *rate);
+	const struct scmi_clock_rates __must_check *(*all_rates_get)
+		(const struct scmi_protocol_handle *ph, u32 clk_id);
 	int (*enable)(const struct scmi_protocol_handle *ph, u32 clk_id,
 		      bool atomic);
 	int (*disable)(const struct scmi_protocol_handle *ph, u32 clk_id,
@@ -901,7 +906,7 @@ struct scmi_notify_ops {
  */
 struct scmi_handle {
 	struct device *dev;
-	struct scmi_revision_info *version;
+	struct scmi_base_info *version;
 
 	int __must_check (*devm_protocol_acquire)(struct scmi_device *sdev,
 						  u8 proto);
diff --git a/include/linux/sunrpc/cache.h b/include/linux/sunrpc/cache.h
index b1e595c2615b..2735c332ddb7 100644
--- a/include/linux/sunrpc/cache.h
+++ b/include/linux/sunrpc/cache.h
@@ -80,6 +80,9 @@ struct cache_detail {
 	int			(*cache_upcall)(struct cache_detail *,
 						struct cache_head *);
 
+	int			(*cache_notify)(struct cache_detail *cd,
+						struct cache_head *h);
+
 	void			(*cache_request)(struct cache_detail *cd,
 						 struct cache_head *ch,
 						 char **bpp, int *blen);
@@ -189,9 +192,9 @@ sunrpc_cache_update(struct cache_detail *detail,
 		    struct cache_head *new, struct cache_head *old, int hash);
 
 extern int
-sunrpc_cache_pipe_upcall(struct cache_detail *detail, struct cache_head *h);
+sunrpc_cache_upcall(struct cache_detail *detail, struct cache_head *h);
 extern int
-sunrpc_cache_pipe_upcall_timeout(struct cache_detail *detail,
+sunrpc_cache_upcall_warn(struct cache_detail *detail,
 				 struct cache_head *h);
 
 
@@ -248,6 +251,14 @@ extern int sunrpc_cache_register_pipefs(struct dentry *parent, const char *,
 extern void sunrpc_cache_unregister_pipefs(struct cache_detail *);
 extern void sunrpc_cache_unhash(struct cache_detail *, struct cache_head *);
 
+int sunrpc_cache_requests_count(struct cache_detail *cd);
+int sunrpc_cache_requests_snapshot(struct cache_detail *cd,
+				   struct cache_head **items,
+				   u64 *seqnos, int max,
+				   u64 min_seqno);
+int sunrpc_cache_notify(struct cache_detail *cd, struct cache_head *h,
+			u32 cache_type);
+
 /* Must store cache_detail in seq_file->private if using next three functions */
 extern void *cache_seq_start_rcu(struct seq_file *file, loff_t *pos);
 extern void *cache_seq_next_rcu(struct seq_file *file, void *p, loff_t *pos);
diff --git a/include/linux/swap.h b/include/linux/swap.h
index 7a09df6977a5..1930f81e6be4 100644
--- a/include/linux/swap.h
+++ b/include/linux/swap.h
@@ -213,6 +213,7 @@ enum {
 	SWP_PAGE_DISCARD = (1 << 10),	/* freed swap page-cluster discards */
 	SWP_STABLE_WRITES = (1 << 11),	/* no overwrite PG_writeback pages */
 	SWP_SYNCHRONOUS_IO = (1 << 12),	/* synchronous IO is efficient */
+	SWP_HIBERNATION = (1 << 13),	/* pinned for hibernation */
 					/* add others here before... */
 };
 
@@ -433,7 +434,9 @@ static inline long get_nr_swap_pages(void)
 }
 
 extern void si_swapinfo(struct sysinfo *);
-int swap_type_of(dev_t device, sector_t offset);
+extern int pin_hibernation_swap_type(dev_t device, sector_t offset);
+extern void unpin_hibernation_swap_type(int type);
+extern int find_hibernation_swap_type(dev_t device, sector_t offset);
 int find_first_swap(dev_t *device);
 extern unsigned int count_swap_pages(int, int);
 extern sector_t swapdev_block(int, pgoff_t);
diff --git a/include/linux/unicode.h b/include/linux/unicode.h
index 5e6b212a2aed..64fa44fe180c 100644
--- a/include/linux/unicode.h
+++ b/include/linux/unicode.h
@@ -66,9 +66,6 @@ int utf8_strncasecmp_folded(const struct unicode_map *um,
 			    const struct qstr *cf,
 			    const struct qstr *s1);
 
-int utf8_normalize(const struct unicode_map *um, const struct qstr *str,
-		   unsigned char *dest, size_t dlen);
-
 int utf8_casefold(const struct unicode_map *um, const struct qstr *str,
 		  unsigned char *dest, size_t dlen);
 
diff --git a/include/net/bluetooth/hci_core.h b/include/net/bluetooth/hci_core.h
index a7bffb908c1e..aa600fbf9a53 100644
--- a/include/net/bluetooth/hci_core.h
+++ b/include/net/bluetooth/hci_core.h
@@ -2495,7 +2495,7 @@ void mgmt_adv_monitor_device_lost(struct hci_dev *hdev, u16 handle,
 				  bdaddr_t *bdaddr, u8 addr_type);
 
 int hci_abort_conn(struct hci_conn *conn, u8 reason);
-u8 hci_le_conn_update(struct hci_conn *conn, u16 min, u16 max, u16 latency,
+void hci_le_conn_update(struct hci_conn *conn, u16 min, u16 max, u16 latency,
 		      u16 to_multiplier);
 void hci_le_start_enc(struct hci_conn *conn, __le16 ediv, __le64 rand,
 		      __u8 ltk[16], __u8 key_size);
diff --git a/include/net/dst.h b/include/net/dst.h
index 307073eae7f8..10b73fb45117 100644
--- a/include/net/dst.h
+++ b/include/net/dst.h
@@ -95,8 +95,19 @@ struct dst_entry {
 #ifdef CONFIG_64BIT
 	struct lwtunnel_state   *lwtstate;
 #endif
+#ifdef CONFIG_NET_DEV_REFCNT_TRACKER
+	atomic_t dst_trace_seq;
+#endif
 };
 
+#ifdef CONFIG_NET_DEV_REFCNT_TRACKER
+void save_dst_trace_buffer(struct dst_entry *dst, int delta);
+void dump_dst_trace_buffer(const struct net_device *dev);
+#else
+static inline void save_dst_trace_buffer(struct dst_entry *dst, int delta) { };
+static inline void dump_dst_trace_buffer(const struct net_device *dev) { };
+#endif
+
 struct dst_metrics {
 	u32		metrics[RTAX_MAX];
 	refcount_t	refcnt;
@@ -244,7 +255,10 @@ static inline void dst_hold(struct dst_entry *dst)
 	 * the placement of __rcuref in struct dst_entry
 	 */
 	BUILD_BUG_ON(offsetof(struct dst_entry, __rcuref) & 63);
-	WARN_ON(!rcuref_get(&dst->__rcuref));
+	if (!rcuref_get(&dst->__rcuref))
+		WARN_ON(1);
+	else
+		save_dst_trace_buffer(dst, 1);
 }
 
 static inline void dst_use_noref(struct dst_entry *dst, unsigned long time)
@@ -308,7 +322,11 @@ static inline void skb_dst_copy(struct sk_buff *nskb, const struct sk_buff *oskb
  */
 static inline bool dst_hold_safe(struct dst_entry *dst)
 {
-	return rcuref_get(&dst->__rcuref);
+	const bool ret = rcuref_get(&dst->__rcuref);
+
+	if (ret)
+		save_dst_trace_buffer(dst, 1);
+	return ret;
 }
 
 /**
diff --git a/include/net/sock.h b/include/net/sock.h
index dccd3738c368..f5ec656a9fb6 100644
--- a/include/net/sock.h
+++ b/include/net/sock.h
@@ -2196,8 +2196,12 @@ sk_dst_get(const struct sock *sk)
 
 	rcu_read_lock();
 	dst = rcu_dereference(sk->sk_dst_cache);
-	if (dst && !rcuref_get(&dst->__rcuref))
-		dst = NULL;
+	if (dst) {
+		if (!rcuref_get(&dst->__rcuref))
+			dst = NULL;
+		else
+			save_dst_trace_buffer(dst, 1);
+	}
 	rcu_read_unlock();
 	return dst;
 }
diff --git a/include/trace/events/damon.h b/include/trace/events/damon.h
index 24fc402ab3c8..7e25f4469b81 100644
--- a/include/trace/events/damon.h
+++ b/include/trace/events/damon.h
@@ -41,7 +41,7 @@ TRACE_EVENT(damos_stat_after_apply_interval,
 	),
 
 	TP_printk("ctx_idx=%u scheme_idx=%u nr_tried=%lu sz_tried=%lu "
-			"nr_applied=%lu sz_tried=%lu sz_ops_filter_passed=%lu "
+			"nr_applied=%lu sz_applied=%lu sz_ops_filter_passed=%lu "
 			"qt_exceeds=%lu nr_snapshots=%lu",
 			__entry->context_idx, __entry->scheme_idx,
 			__entry->nr_tried, __entry->sz_tried,
diff --git a/include/trace/events/netfs.h b/include/trace/events/netfs.h
index 8c936fc575d5..ee7fea84f055 100644
--- a/include/trace/events/netfs.h
+++ b/include/trace/events/netfs.h
@@ -177,6 +177,7 @@
 	EM(netfs_folio_is_uptodate,		"mod-uptodate")	\
 	EM(netfs_just_prefetch,			"mod-prefetch")	\
 	EM(netfs_whole_folio_modify,		"mod-whole-f")	\
+	EM(netfs_whole_folio_modify_efault,	"mod-whole-f!")	\
 	EM(netfs_modify_and_clear,		"mod-n-clear")	\
 	EM(netfs_streaming_write,		"mod-streamw")	\
 	EM(netfs_streaming_write_cont,		"mod-streamw+")	\
@@ -194,6 +195,10 @@
 	EM(netfs_folio_trace_copy_to_cache,	"mark-copy")	\
 	EM(netfs_folio_trace_end_copy,		"end-copy")	\
 	EM(netfs_folio_trace_filled_gaps,	"filled-gaps")	\
+	EM(netfs_folio_trace_invalidate_all,	"inval-all")	\
+	EM(netfs_folio_trace_invalidate_front,	"inval-front")	\
+	EM(netfs_folio_trace_invalidate_middle,	"inval-mid")	\
+	EM(netfs_folio_trace_invalidate_tail,	"inval-tail")	\
 	EM(netfs_folio_trace_kill,		"kill")		\
 	EM(netfs_folio_trace_kill_cc,		"kill-cc")	\
 	EM(netfs_folio_trace_kill_g,		"kill-g")	\
diff --git a/include/uapi/drm/drm_ras.h b/include/uapi/drm/drm_ras.h
index 5f40fa5b869d..218a3ee86805 100644
--- a/include/uapi/drm/drm_ras.h
+++ b/include/uapi/drm/drm_ras.h
@@ -41,6 +41,7 @@ enum {
 enum {
 	DRM_RAS_CMD_LIST_NODES = 1,
 	DRM_RAS_CMD_GET_ERROR_COUNTER,
+	DRM_RAS_CMD_CLEAR_ERROR_COUNTER,
 
 	__DRM_RAS_CMD_MAX,
 	DRM_RAS_CMD_MAX = (__DRM_RAS_CMD_MAX - 1)
diff --git a/include/uapi/drm/xe_drm.h b/include/uapi/drm/xe_drm.h
index ae2fda23ce7c..48e9f1fdb78d 100644
--- a/include/uapi/drm/xe_drm.h
+++ b/include/uapi/drm/xe_drm.h
@@ -83,6 +83,7 @@ extern "C" {
  *  - &DRM_IOCTL_XE_OBSERVATION
  *  - &DRM_IOCTL_XE_MADVISE
  *  - &DRM_IOCTL_XE_VM_QUERY_MEM_RANGE_ATTRS
+ *  - &DRM_IOCTL_XE_EXEC_QUEUE_SET_PROPERTY
  *  - &DRM_IOCTL_XE_VM_GET_PROPERTY
  */
 
@@ -167,7 +168,7 @@ extern "C" {
  * Typically the struct drm_xe_user_extension would be embedded in some uAPI
  * struct, and in this case we would feed it the head of the chain(i.e ext1),
  * which would then apply all of the above extensions.
-*/
+ */
 
 /**
  * struct drm_xe_user_extension - Base class for defining a chain of extensions
@@ -229,9 +230,9 @@ struct drm_xe_ext_set_property {
 /**
  * struct drm_xe_engine_class_instance - instance of an engine class
  *
- * It is returned as part of the @drm_xe_engine, but it also is used as
- * the input of engine selection for both @drm_xe_exec_queue_create and
- * @drm_xe_query_engine_cycles
+ * It is returned as part of the &struct drm_xe_engine, but it also is used as
+ * the input of engine selection for both &struct drm_xe_exec_queue_create and
+ * &struct drm_xe_query_engine_cycles
  *
  * The @engine_class can be:
  *  - %DRM_XE_ENGINE_CLASS_RENDER
@@ -264,7 +265,7 @@ struct drm_xe_engine_class_instance {
  * struct drm_xe_engine - describe hardware engine
  */
 struct drm_xe_engine {
-	/** @instance: The @drm_xe_engine_class_instance */
+	/** @instance: The &struct drm_xe_engine_class_instance */
 	struct drm_xe_engine_class_instance instance;
 
 	/** @reserved: Reserved */
@@ -274,9 +275,9 @@ struct drm_xe_engine {
 /**
  * struct drm_xe_query_engines - describe engines
  *
- * If a query is made with a struct @drm_xe_device_query where .query
+ * If a query is made with a &struct drm_xe_device_query where .query
  * is equal to %DRM_XE_DEVICE_QUERY_ENGINES, then the reply uses an array of
- * struct @drm_xe_query_engines in .data.
+ * &struct drm_xe_query_engines in .data.
  */
 struct drm_xe_query_engines {
 	/** @num_engines: number of engines returned in @engines */
@@ -349,7 +350,7 @@ struct drm_xe_mem_region {
 	 * is smaller than @total_size then this is referred to as a
 	 * small BAR system.
 	 *
-	 * On systems without small BAR (full BAR), the probed_size will
+	 * On systems without small BAR (full BAR), the @cpu_visible_size will
 	 * always equal the @total_size, since all of it will be CPU
 	 * accessible.
 	 *
@@ -410,7 +411,7 @@ struct drm_xe_query_mem_regions {
  *      device supports the userspace hint %DRM_XE_GEM_CREATE_FLAG_NO_COMPRESSION.
  *      This is exposed only on Xe2+.
  *    - %DRM_XE_QUERY_CONFIG_FLAG_HAS_DISABLE_STATE_CACHE_PERF_FIX - Flag is set
- *      if a queue can be creaed with
+ *      if a queue can be created with
  *      %DRM_XE_EXEC_QUEUE_SET_DISABLE_STATE_CACHE_PERF_FIX
  *  - %DRM_XE_QUERY_CONFIG_MIN_ALIGNMENT - Minimal memory alignment
  *    required by this device, typically SZ_4K or SZ_64K
@@ -705,7 +706,10 @@ struct drm_xe_query_pxp_status {
  *    attributes.
  *  - %DRM_XE_DEVICE_QUERY_GT_TOPOLOGY
  *  - %DRM_XE_DEVICE_QUERY_ENGINE_CYCLES
+ *  - %DRM_XE_DEVICE_QUERY_UC_FW_VERSION
+ *  - %DRM_XE_DEVICE_QUERY_OA_UNITS
  *  - %DRM_XE_DEVICE_QUERY_PXP_STATUS
+ *  - %DRM_XE_DEVICE_QUERY_EU_STALL
  *
  * If size is set to 0, the driver fills it with the required size for
  * the requested type of data to query. If size is equal to the required
@@ -825,7 +829,7 @@ struct drm_xe_device_query {
  *
  * This ioctl supports setting the following properties via the
  * %DRM_XE_GEM_CREATE_EXTENSION_SET_PROPERTY extension, which uses the
- * generic @drm_xe_ext_set_property struct:
+ * generic &struct drm_xe_ext_set_property:
  *
  *  - %DRM_XE_GEM_CREATE_SET_PROPERTY_PXP_TYPE - set the type of PXP session
  *    this object will be used with. Valid values are listed in enum
@@ -862,8 +866,7 @@ struct drm_xe_gem_create {
 #define DRM_XE_GEM_CREATE_FLAG_NEEDS_VISIBLE_VRAM	(1 << 2)
 #define DRM_XE_GEM_CREATE_FLAG_NO_COMPRESSION		(1 << 3)
 	/**
-	 * @flags: Flags, currently a mask of memory instances of where BO can
-	 * be placed
+	 * @flags: Flags for the GEM object, see DRM_XE_GEM_CREATE_FLAG_*
 	 */
 	__u32 flags;
 
@@ -888,7 +891,7 @@ struct drm_xe_gem_create {
 #define DRM_XE_GEM_CPU_CACHING_WC                      2
 	/**
 	 * @cpu_caching: The CPU caching mode to select for this object. If
-	 * mmaping the object the mode selected here will also be used. The
+	 * mmapping the object the mode selected here will also be used. The
 	 * exception is when mapping system memory (including data evicted
 	 * to system) on discrete GPUs. The caching mode selected will
 	 * then be overridden to DRM_XE_GEM_CPU_CACHING_WB, and coherency
@@ -931,7 +934,7 @@ struct drm_xe_gem_create {
  *
  *     err = ioctl(fd, DRM_IOCTL_XE_GEM_MMAP_OFFSET, &mmo);
  *     map = mmap(NULL, size, PROT_WRITE, MAP_SHARED, fd, mmo.offset);
- *     map[i] = 0xdeadbeaf; // issue barrier
+ *     map[i] = 0xdeadbeef; // issue barrier
  */
 struct drm_xe_gem_mmap_offset {
 	/** @extensions: Pointer to the first extension struct, if any */
@@ -958,8 +961,8 @@ struct drm_xe_gem_mmap_offset {
  *  - %DRM_XE_VM_CREATE_FLAG_SCRATCH_PAGE - Map the whole virtual address
  *    space of the VM to scratch page. A vm_bind would overwrite the scratch
  *    page mapping. This flag is mutually exclusive with the
- *    %DRM_XE_VM_CREATE_FLAG_FAULT_MODE flag, with an exception of on x2 and
- *    xe3 platform.
+ *    %DRM_XE_VM_CREATE_FLAG_FAULT_MODE flag, with an exception on Xe2 and
+ *    Xe3 platforms.
  *  - %DRM_XE_VM_CREATE_FLAG_LR_MODE - An LR, or Long Running VM accepts
  *    exec submissions to its exec_queues that don't have an upper time
  *    limit on the job execution time. But exec submissions to these
@@ -1045,7 +1048,7 @@ struct drm_xe_vm_destroy {
  *    set, no mappings are created rather the range is reserved for CPU address
  *    mirroring which will be populated on GPU page faults or prefetches. Only
  *    valid on VMs with DRM_XE_VM_CREATE_FLAG_FAULT_MODE set. The CPU address
- *    mirror flag are only valid for DRM_XE_VM_BIND_OP_MAP operations, the BO
+ *    mirror flag is only valid for DRM_XE_VM_BIND_OP_MAP operations, the BO
  *    handle MBZ, and the BO offset MBZ.
  *  - %DRM_XE_VM_BIND_FLAG_MADVISE_AUTORESET - Can be used in combination with
  *    %DRM_XE_VM_BIND_FLAG_CPU_ADDR_MIRROR to reset madvises when the underlying
@@ -1061,6 +1064,7 @@ struct drm_xe_vm_destroy {
  *    not invoke autoreset. Neither will stack variables going out of scope.
  *    Therefore it's recommended to always explicitly reset the madvises when
  *    freeing the memory backing a region used in a &DRM_IOCTL_XE_MADVISE call.
+ *
  *  - %DRM_XE_VM_BIND_FLAG_DECOMPRESS - Request on-device decompression for a MAP.
  *    When set on a MAP bind operation, request the driver schedule an on-device
  *    in-place decompression (via the migrate/resolve path) for the GPU mapping
@@ -1109,7 +1113,7 @@ struct drm_xe_vm_bind_op {
 	 *	ppGTT WT -> COH_NONE
 	 *	ppGTT WB -> COH_AT_LEAST_1WAY
 	 *
-	 * In practice UC/WC/WT should only ever used for scanout surfaces on
+	 * In practice UC/WC/WT should only ever be used for scanout surfaces on
 	 * such platforms (or perhaps in general for dma-buf if shared with
 	 * another device) since it is only the display engine that is actually
 	 * incoherent.  Everything else should typically use WB given that we
@@ -1199,10 +1203,10 @@ struct drm_xe_vm_bind_op {
 /**
  * struct drm_xe_vm_bind - Input of &DRM_IOCTL_XE_VM_BIND
  *
- * Below is an example of a minimal use of @drm_xe_vm_bind to
+ * Below is an example of a minimal use of &struct drm_xe_vm_bind to
  * asynchronously bind the buffer `data` at address `BIND_ADDRESS` to
  * illustrate `userptr`. It can be synchronized by using the example
- * provided for @drm_xe_sync.
+ * provided for &struct drm_xe_sync.
  *
  * .. code-block:: C
  *
@@ -1355,7 +1359,7 @@ struct drm_xe_vm_get_property {
  *
  * This ioctl supports setting the following properties via the
  * %DRM_XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY extension, which uses the
- * generic @drm_xe_ext_set_property struct:
+ * generic &struct drm_xe_ext_set_property:
  *
  *  - %DRM_XE_EXEC_QUEUE_SET_PROPERTY_PRIORITY - set the queue priority.
  *    CAP_SYS_NICE is required to set a value above normal.
@@ -1366,7 +1370,7 @@ struct drm_xe_vm_get_property {
  *    drm_xe_pxp_session_type. %DRM_XE_PXP_TYPE_NONE is the default behavior, so
  *    there is no need to explicitly set that. When a queue of type
  *    %DRM_XE_PXP_TYPE_HWDRM is created, the PXP default HWDRM session
- *    (%XE_PXP_HWDRM_DEFAULT_SESSION) will be started, if isn't already running.
+ *    (%DRM_XE_PXP_HWDRM_DEFAULT_SESSION) will be started, if it isn't already running.
  *    The user is expected to query the PXP status via the query ioctl (see
  *    %DRM_XE_DEVICE_QUERY_PXP_STATUS) and to wait for PXP to be ready before
  *    attempting to create a queue with this property. When a queue is created
@@ -1390,9 +1394,9 @@ struct drm_xe_vm_get_property {
  *    enable render color cache keying on BTP+BTI instead of just BTI
  *    (only valid for render queues).
  *
- * The example below shows how to use @drm_xe_exec_queue_create to create
+ * The example below shows how to use &struct drm_xe_exec_queue_create to create
  * a simple exec_queue (no parallel submission) of class
- * &DRM_XE_ENGINE_CLASS_RENDER.
+ * %DRM_XE_ENGINE_CLASS_RENDER.
  *
  * .. code-block:: C
  *
@@ -1402,23 +1406,25 @@ struct drm_xe_vm_get_property {
  *     struct drm_xe_exec_queue_create exec_queue_create = {
  *          .extensions = 0,
  *          .vm_id = vm,
- *          .num_bb_per_exec = 1,
- *          .num_eng_per_bb = 1,
+ *          .width = 1,
+ *          .num_placements = 1,
  *          .instances = to_user_pointer(&instance),
  *     };
  *     ioctl(fd, DRM_IOCTL_XE_EXEC_QUEUE_CREATE, &exec_queue_create);
  *
- *     Allow users to provide a hint to kernel for cases demanding low latency
- *     profile. Please note it will have impact on power consumption. User can
- *     indicate low latency hint with flag while creating exec queue as
- *     mentioned below,
+ * Allow users to provide a hint to kernel for cases demanding low latency
+ * profile. Please note it will have impact on power consumption. User can
+ * indicate low latency hint with flag while creating exec queue as
+ * mentioned below:
+ *
+ * .. code-block:: C
  *
  *     struct drm_xe_exec_queue_create exec_queue_create = {
  *          .flags = DRM_XE_EXEC_QUEUE_LOW_LATENCY_HINT,
  *          .extensions = 0,
  *          .vm_id = vm,
- *          .num_bb_per_exec = 1,
- *          .num_eng_per_bb = 1,
+ *          .width = 1,
+ *          .num_placements = 1,
  *          .instances = to_user_pointer(&instance),
  *     };
  *     ioctl(fd, DRM_IOCTL_XE_EXEC_QUEUE_CREATE, &exec_queue_create);
@@ -1515,7 +1521,7 @@ struct drm_xe_exec_queue_get_property {
  * and the @flags can be:
  *  - %DRM_XE_SYNC_FLAG_SIGNAL
  *
- * A minimal use of @drm_xe_sync looks like this:
+ * A minimal use of &struct drm_xe_sync looks like this:
  *
  * .. code-block:: C
  *
@@ -1546,7 +1552,7 @@ struct drm_xe_sync {
 #define DRM_XE_SYNC_TYPE_SYNCOBJ		0x0
 #define DRM_XE_SYNC_TYPE_TIMELINE_SYNCOBJ	0x1
 #define DRM_XE_SYNC_TYPE_USER_FENCE		0x2
-	/** @type: Type of the this sync object */
+	/** @type: Type of this sync object */
 	__u32 type;
 
 #define DRM_XE_SYNC_FLAG_SIGNAL	(1 << 0)
@@ -1559,9 +1565,9 @@ struct drm_xe_sync {
 
 		/**
 		 * @addr: Address of user fence. When sync is passed in via exec
-		 * IOCTL this is a GPU address in the VM. When sync passed in via
+		 * IOCTL this is a GPU address in the VM. When sync is passed in via
 		 * VM bind IOCTL this is a user pointer. In either case, it is
-		 * the users responsibility that this address is present and
+		 * the user's responsibility that this address is present and
 		 * mapped when the user fence is signalled. Must be qword
 		 * aligned.
 		 */
@@ -1581,10 +1587,10 @@ struct drm_xe_sync {
 /**
  * struct drm_xe_exec - Input of &DRM_IOCTL_XE_EXEC
  *
- * This is an example to use @drm_xe_exec for execution of the object
- * at BIND_ADDRESS (see example in @drm_xe_vm_bind) by an exec_queue
- * (see example in @drm_xe_exec_queue_create). It can be synchronized
- * by using the example provided for @drm_xe_sync.
+ * This is an example to use &struct drm_xe_exec for execution of the object
+ * at BIND_ADDRESS (see example in &struct drm_xe_vm_bind) by an exec_queue
+ * (see example in &struct drm_xe_exec_queue_create). It can be synchronized
+ * by using the example provided for &struct drm_xe_sync.
  *
  * .. code-block:: C
  *
@@ -1651,7 +1657,6 @@ struct drm_xe_exec {
  *
  * and the @flags can be:
  *  - %DRM_XE_UFENCE_WAIT_FLAG_ABSTIME
- *  - %DRM_XE_UFENCE_WAIT_FLAG_SOFT_OP
  *
  * The @mask values can be for example:
  *  - 0xffu for u8
@@ -1664,7 +1669,7 @@ struct drm_xe_wait_user_fence {
 	__u64 extensions;
 
 	/**
-	 * @addr: user pointer address to wait on, must qword aligned
+	 * @addr: user pointer address to wait on, must be qword aligned
 	 */
 	__u64 addr;
 
@@ -1695,9 +1700,9 @@ struct drm_xe_wait_user_fence {
 	 * Without DRM_XE_UFENCE_WAIT_FLAG_ABSTIME flag set (relative timeout)
 	 * it contains timeout expressed in nanoseconds to wait (fence will
 	 * expire at now() + timeout).
-	 * When DRM_XE_UFENCE_WAIT_FLAG_ABSTIME flat is set (absolute timeout) wait
-	 * will end at timeout (uses system MONOTONIC_CLOCK).
-	 * Passing negative timeout leads to neverending wait.
+	 * When DRM_XE_UFENCE_WAIT_FLAG_ABSTIME flag is set (absolute timeout) wait
+	 * will end at timeout (uses system CLOCK_MONOTONIC).
+	 * Passing negative timeout leads to never ending wait.
 	 *
 	 * On relative timeout this value is updated with timeout left
 	 * (for restarting the call in case of signal delivery).
@@ -1741,7 +1746,7 @@ enum drm_xe_observation_op {
 };
 
 /**
- * struct drm_xe_observation_param - Input of &DRM_XE_OBSERVATION
+ * struct drm_xe_observation_param - Input of &DRM_IOCTL_XE_OBSERVATION
  *
  * The observation layer enables multiplexing observation streams of
  * multiple types. The actual params for a particular stream operation are
@@ -1751,25 +1756,25 @@ enum drm_xe_observation_op {
 struct drm_xe_observation_param {
 	/** @extensions: Pointer to the first extension struct, if any */
 	__u64 extensions;
-	/** @observation_type: observation stream type, of enum @drm_xe_observation_type */
+	/** @observation_type: observation stream type, of &enum drm_xe_observation_type */
 	__u64 observation_type;
-	/** @observation_op: observation stream op, of enum @drm_xe_observation_op */
+	/** @observation_op: observation stream op, of &enum drm_xe_observation_op */
 	__u64 observation_op;
 	/** @param: Pointer to actual stream params */
 	__u64 param;
 };
 
 /**
- * enum drm_xe_observation_ioctls - Observation stream fd ioctl's
+ * enum drm_xe_observation_ioctls - Observation stream fd ioctls
  *
  * Information exchanged between userspace and kernel for observation fd
- * ioctl's is stream type specific
+ * ioctls is stream type specific
  */
 enum drm_xe_observation_ioctls {
 	/** @DRM_XE_OBSERVATION_IOCTL_ENABLE: Enable data capture for an observation stream */
 	DRM_XE_OBSERVATION_IOCTL_ENABLE = _IO('i', 0x0),
 
-	/** @DRM_XE_OBSERVATION_IOCTL_DISABLE: Disable data capture for a observation stream */
+	/** @DRM_XE_OBSERVATION_IOCTL_DISABLE: Disable data capture for an observation stream */
 	DRM_XE_OBSERVATION_IOCTL_DISABLE = _IO('i', 0x1),
 
 	/** @DRM_XE_OBSERVATION_IOCTL_CONFIG: Change observation stream configuration */
@@ -1812,7 +1817,7 @@ struct drm_xe_oa_unit {
 	/** @oa_unit_id: OA unit ID */
 	__u32 oa_unit_id;
 
-	/** @oa_unit_type: OA unit type of @drm_xe_oa_unit_type */
+	/** @oa_unit_type: OA unit type of &enum drm_xe_oa_unit_type */
 	__u32 oa_unit_type;
 
 	/** @capabilities: OA capabilities bit-mask */
@@ -1875,7 +1880,7 @@ struct drm_xe_query_oa_units {
 	/** @pad: MBZ */
 	__u32 pad;
 	/**
-	 * @oa_units: struct @drm_xe_oa_unit array returned for this device.
+	 * @oa_units: &struct drm_xe_oa_unit array returned for this device.
 	 * Written below as a u64 array to avoid problems with nested flexible
 	 * arrays with some compilers
 	 */
@@ -1902,24 +1907,24 @@ enum drm_xe_oa_format_type {
 };
 
 /**
- * enum drm_xe_oa_property_id - OA stream property id's
+ * enum drm_xe_oa_property_id - OA stream property IDs
  *
- * Stream params are specified as a chain of @drm_xe_ext_set_property
- * struct's, with @property values from enum @drm_xe_oa_property_id and
- * @drm_xe_user_extension base.name set to @DRM_XE_OA_EXTENSION_SET_PROPERTY.
- * @param field in struct @drm_xe_observation_param points to the first
- * @drm_xe_ext_set_property struct.
+ * Stream params are specified as a chain of &struct drm_xe_ext_set_property
+ * structs, with property values from &enum drm_xe_oa_property_id and
+ * &struct drm_xe_user_extension base.name set to %DRM_XE_OA_EXTENSION_SET_PROPERTY.
+ * The param field in &struct drm_xe_observation_param points to the first
+ * &struct drm_xe_ext_set_property struct.
  *
  * Exactly the same mechanism is also used for stream reconfiguration using the
- * @DRM_XE_OBSERVATION_IOCTL_CONFIG observation stream fd ioctl, though only a
+ * %DRM_XE_OBSERVATION_IOCTL_CONFIG observation stream fd ioctl, though only a
  * subset of properties below can be specified for stream reconfiguration.
  */
 enum drm_xe_oa_property_id {
 #define DRM_XE_OA_EXTENSION_SET_PROPERTY	0
 	/**
 	 * @DRM_XE_OA_PROPERTY_OA_UNIT_ID: ID of the OA unit on which to open
-	 * the OA stream, see @oa_unit_id in 'struct
-	 * drm_xe_query_oa_units'. Defaults to 0 if not provided.
+	 * the OA stream, see oa_unit_id in &struct drm_xe_oa_unit.
+	 * Defaults to 0 if not provided.
 	 */
 	DRM_XE_OA_PROPERTY_OA_UNIT_ID = 1,
 
@@ -1932,7 +1937,7 @@ enum drm_xe_oa_property_id {
 
 	/**
 	 * @DRM_XE_OA_PROPERTY_OA_METRIC_SET: OA metrics defining contents of OA
-	 * reports, previously added via @DRM_XE_OBSERVATION_OP_ADD_CONFIG.
+	 * reports, previously added via %DRM_XE_OBSERVATION_OP_ADD_CONFIG.
 	 */
 	DRM_XE_OA_PROPERTY_OA_METRIC_SET,
 
@@ -1940,7 +1945,7 @@ enum drm_xe_oa_property_id {
 	DRM_XE_OA_PROPERTY_OA_FORMAT,
 	/*
 	 * OA_FORMAT's are specified the same way as in PRM/Bspec 52198/60942,
-	 * in terms of the following quantities: a. enum @drm_xe_oa_format_type
+	 * in terms of the following quantities: a. &enum drm_xe_oa_format_type
 	 * b. Counter select c. Counter size and d. BC report. Also refer to the
 	 * oa_formats array in drivers/gpu/drm/xe/xe_oa.c.
 	 */
@@ -1957,19 +1962,19 @@ enum drm_xe_oa_property_id {
 
 	/**
 	 * @DRM_XE_OA_PROPERTY_OA_DISABLED: A value of 1 will open the OA
-	 * stream in a DISABLED state (see @DRM_XE_OBSERVATION_IOCTL_ENABLE).
+	 * stream in a DISABLED state (see %DRM_XE_OBSERVATION_IOCTL_ENABLE).
 	 */
 	DRM_XE_OA_PROPERTY_OA_DISABLED,
 
 	/**
 	 * @DRM_XE_OA_PROPERTY_EXEC_QUEUE_ID: Open the stream for a specific
-	 * @exec_queue_id. OA queries can be executed on this exec queue.
+	 * exec_queue_id. OA queries can be executed on this exec queue.
 	 */
 	DRM_XE_OA_PROPERTY_EXEC_QUEUE_ID,
 
 	/**
 	 * @DRM_XE_OA_PROPERTY_OA_ENGINE_INSTANCE: Optional engine instance to
-	 * pass along with @DRM_XE_OA_PROPERTY_EXEC_QUEUE_ID or will default to 0.
+	 * pass along with %DRM_XE_OA_PROPERTY_EXEC_QUEUE_ID or will default to 0.
 	 */
 	DRM_XE_OA_PROPERTY_OA_ENGINE_INSTANCE,
 
@@ -1981,16 +1986,16 @@ enum drm_xe_oa_property_id {
 
 	/**
 	 * @DRM_XE_OA_PROPERTY_NUM_SYNCS: Number of syncs in the sync array
-	 * specified in @DRM_XE_OA_PROPERTY_SYNCS
+	 * specified in %DRM_XE_OA_PROPERTY_SYNCS
 	 */
 	DRM_XE_OA_PROPERTY_NUM_SYNCS,
 
 	/**
-	 * @DRM_XE_OA_PROPERTY_SYNCS: Pointer to struct @drm_xe_sync array
-	 * with array size specified via @DRM_XE_OA_PROPERTY_NUM_SYNCS. OA
+	 * @DRM_XE_OA_PROPERTY_SYNCS: Pointer to &struct drm_xe_sync array
+	 * with array size specified via %DRM_XE_OA_PROPERTY_NUM_SYNCS. OA
 	 * configuration will wait till input fences signal. Output fences
 	 * will signal after the new OA configuration takes effect. For
-	 * @DRM_XE_SYNC_TYPE_USER_FENCE, @addr is a user pointer, similar
+	 * %DRM_XE_SYNC_TYPE_USER_FENCE, addr is a user pointer, similar
 	 * to the VM bind case.
 	 */
 	DRM_XE_OA_PROPERTY_SYNCS,
@@ -2013,15 +2018,15 @@ enum drm_xe_oa_property_id {
 /**
  * struct drm_xe_oa_config - OA metric configuration
  *
- * Multiple OA configs can be added using @DRM_XE_OBSERVATION_OP_ADD_CONFIG. A
+ * Multiple OA configs can be added using %DRM_XE_OBSERVATION_OP_ADD_CONFIG. A
  * particular config can be specified when opening an OA stream using
- * @DRM_XE_OA_PROPERTY_OA_METRIC_SET property.
+ * %DRM_XE_OA_PROPERTY_OA_METRIC_SET property.
  */
 struct drm_xe_oa_config {
 	/** @extensions: Pointer to the first extension struct, if any */
 	__u64 extensions;
 
-	/** @uuid: String formatted like "%\08x-%\04x-%\04x-%\04x-%\012x" */
+	/** @uuid: String formatted like "%08x-%04x-%04x-%04x-%012x" */
 	char uuid[36];
 
 	/** @n_regs: Number of regs in @regs_ptr */
@@ -2036,7 +2041,7 @@ struct drm_xe_oa_config {
 
 /**
  * struct drm_xe_oa_stream_status - OA stream status returned from
- * @DRM_XE_OBSERVATION_IOCTL_STATUS observation stream fd ioctl. Userspace can
+ * %DRM_XE_OBSERVATION_IOCTL_STATUS observation stream fd ioctl. Userspace can
  * call the ioctl to query stream status in response to EIO errno from
  * observation fd read().
  */
@@ -2057,7 +2062,7 @@ struct drm_xe_oa_stream_status {
 
 /**
  * struct drm_xe_oa_stream_info - OA stream info returned from
- * @DRM_XE_OBSERVATION_IOCTL_INFO observation stream fd ioctl
+ * %DRM_XE_OBSERVATION_IOCTL_INFO observation stream fd ioctl
  */
 struct drm_xe_oa_stream_info {
 	/** @extensions: Pointer to the first extension struct, if any */
@@ -2094,27 +2099,27 @@ enum drm_xe_pxp_session_type {
  * enum drm_xe_eu_stall_property_id - EU stall sampling input property ids.
  *
  * These properties are passed to the driver at open as a chain of
- * @drm_xe_ext_set_property structures with @property set to these
- * properties' enums and @value set to the corresponding values of these
- * properties. @drm_xe_user_extension base.name should be set to
- * @DRM_XE_EU_STALL_EXTENSION_SET_PROPERTY.
+ * &struct drm_xe_ext_set_property structures with property set to these
+ * properties' enums and value set to the corresponding values of these
+ * properties. &struct drm_xe_user_extension base.name should be set to
+ * %DRM_XE_EU_STALL_EXTENSION_SET_PROPERTY.
  *
  * With the file descriptor obtained from open, user space must enable
- * the EU stall stream fd with @DRM_XE_OBSERVATION_IOCTL_ENABLE before
+ * the EU stall stream fd with %DRM_XE_OBSERVATION_IOCTL_ENABLE before
  * calling read(). EIO errno from read() indicates HW dropped data
  * due to full buffer.
  */
 enum drm_xe_eu_stall_property_id {
 #define DRM_XE_EU_STALL_EXTENSION_SET_PROPERTY		0
 	/**
-	 * @DRM_XE_EU_STALL_PROP_GT_ID: @gt_id of the GT on which
+	 * @DRM_XE_EU_STALL_PROP_GT_ID: gt_id of the GT on which
 	 * EU stall data will be captured.
 	 */
 	DRM_XE_EU_STALL_PROP_GT_ID = 1,
 
 	/**
 	 * @DRM_XE_EU_STALL_PROP_SAMPLE_RATE: Sampling rate in
-	 * GPU cycles from @sampling_rates in struct @drm_xe_query_eu_stall
+	 * GPU cycles from sampling_rates in &struct drm_xe_query_eu_stall
 	 */
 	DRM_XE_EU_STALL_PROP_SAMPLE_RATE,
 
@@ -2129,9 +2134,9 @@ enum drm_xe_eu_stall_property_id {
 /**
  * struct drm_xe_query_eu_stall - Information about EU stall sampling.
  *
- * If a query is made with a struct @drm_xe_device_query where .query
- * is equal to @DRM_XE_DEVICE_QUERY_EU_STALL, then the reply uses
- * struct @drm_xe_query_eu_stall in .data.
+ * If a query is made with a &struct drm_xe_device_query where .query
+ * is equal to %DRM_XE_DEVICE_QUERY_EU_STALL, then the reply uses
+ * &struct drm_xe_query_eu_stall in .data.
  */
 struct drm_xe_query_eu_stall {
 	/** @extensions: Pointer to the first extension struct, if any */
@@ -2183,7 +2188,7 @@ struct drm_xe_query_eu_stall {
  *         .start = 0x100000,
  *         .range = 0x2000,
  *         .type = DRM_XE_MEM_RANGE_ATTR_ATOMIC,
- *         .atomic_val = DRM_XE_ATOMIC_DEVICE,
+ *         .atomic.val = DRM_XE_ATOMIC_DEVICE,
  *    };
  *
  *    ioctl(fd, DRM_IOCTL_XE_MADVISE, &madvise);
@@ -2242,7 +2247,7 @@ struct drm_xe_madvise {
 
 			/**
 			 * @preferred_mem_loc.region_instance : Region instance.
-			 * MBZ if @devmem_fd <= &DRM_XE_PREFERRED_LOC_DEFAULT_DEVICE.
+			 * MBZ if @devmem_fd <= %DRM_XE_PREFERRED_LOC_DEFAULT_DEVICE.
 			 * Otherwise should point to the desired device
 			 * VRAM instance of the device indicated by
 			 * @preferred_mem_loc.devmem_fd.
@@ -2369,24 +2374,19 @@ struct drm_xe_madvise {
 };
 
 /**
- * struct drm_xe_mem_range_attr - Output of &DRM_IOCTL_XE_VM_QUERY_MEM_RANGES_ATTRS
+ * struct drm_xe_mem_range_attr - Output of &DRM_IOCTL_XE_VM_QUERY_MEM_RANGE_ATTRS
  *
  * This structure is provided by userspace and filled by KMD in response to the
- * DRM_IOCTL_XE_VM_QUERY_MEM_RANGES_ATTRS ioctl. It describes memory attributes of
- * a memory ranges within a user specified address range in a VM.
+ * DRM_IOCTL_XE_VM_QUERY_MEM_RANGE_ATTRS ioctl. It describes memory attributes of
+ * memory ranges within a user specified address range in a VM.
  *
  * The structure includes information such as atomic access policy,
  * page attribute table (PAT) index, and preferred memory location.
  * Userspace allocates an array of these structures and passes a pointer to the
- * ioctl to retrieve attributes for each memory ranges
- *
- * @extensions: Pointer to the first extension struct, if any
- * @start: Start address of the memory range
- * @end: End address of the virtual memory range
- *
+ * ioctl to retrieve attributes for each memory range.
  */
 struct drm_xe_mem_range_attr {
-	 /** @extensions: Pointer to the first extension struct, if any */
+	/** @extensions: Pointer to the first extension struct, if any */
 	__u64 extensions;
 
 	/** @start: start of the memory range */
@@ -2413,7 +2413,7 @@ struct drm_xe_mem_range_attr {
 		__u32 reserved;
 	} atomic;
 
-	 /** @pat_index: Page attribute table index */
+	/** @pat_index: Page attribute table index */
 	struct {
 		/** @pat_index.val: PAT index */
 		__u32 val;
@@ -2427,7 +2427,7 @@ struct drm_xe_mem_range_attr {
 };
 
 /**
- * struct drm_xe_vm_query_mem_range_attr - Input of &DRM_IOCTL_XE_VM_QUERY_MEM_ATTRIBUTES
+ * struct drm_xe_vm_query_mem_range_attr - Input of &DRM_IOCTL_XE_VM_QUERY_MEM_RANGE_ATTRS
  *
  * This structure is used to query memory attributes of memory regions
  * within a user specified address range in a VM. It provides detailed
@@ -2435,15 +2435,15 @@ struct drm_xe_mem_range_attr {
  * page attribute table (PAT) index, and preferred memory location.
  *
  * Userspace first calls the ioctl with @num_mem_ranges = 0,
- * @sizeof_mem_ranges_attr = 0 and @vector_of_vma_mem_attr = NULL to retrieve
+ * @sizeof_mem_range_attr = 0 and @vector_of_mem_attr = NULL to retrieve
  * the number of memory regions and size of each memory range attribute.
  * Then, it allocates a buffer of that size and calls the ioctl again to fill
  * the buffer with memory range attributes.
  *
  * If second call fails with -ENOSPC, it means memory ranges changed between
  * first call and now, retry IOCTL again with @num_mem_ranges = 0,
- * @sizeof_mem_ranges_attr = 0 and @vector_of_vma_mem_attr = NULL followed by
- * Second ioctl call.
+ * @sizeof_mem_range_attr = 0 and @vector_of_mem_attr = NULL followed by
+ * second ioctl call.
  *
  * Example:
  *
diff --git a/include/uapi/linux/fsl_hypervisor.h b/include/uapi/linux/fsl_hypervisor.h
index 1e237fba951f..ab4388441e80 100644
--- a/include/uapi/linux/fsl_hypervisor.h
+++ b/include/uapi/linux/fsl_hypervisor.h
@@ -114,9 +114,9 @@ struct fsl_hv_ioctl_stop {
  * @target: the partition ID of the target partition, or -1 for this
  *          partition
  * @reserved: reserved, must be set to 0
- * @local_addr: user-space virtual address of a buffer in the local
+ * @local_vaddr: user-space virtual address of a buffer in the local
  *              partition
- * @remote_addr: guest physical address of a buffer in the
+ * @remote_paddr: guest physical address of a buffer in the
  *           remote partition
  * @count: the number of bytes to copy.  Both the local and remote
  *         buffers must be at least 'count' bytes long
diff --git a/include/uapi/linux/nfsd_netlink.h b/include/uapi/linux/nfsd_netlink.h
index 97c7447f4d14..060c43675599 100644
--- a/include/uapi/linux/nfsd_netlink.h
+++ b/include/uapi/linux/nfsd_netlink.h
@@ -10,6 +10,53 @@
 #define NFSD_FAMILY_NAME	"nfsd"
 #define NFSD_FAMILY_VERSION	1
 
+enum nfsd_cache_type {
+	NFSD_CACHE_TYPE_SVC_EXPORT = 1,
+	NFSD_CACHE_TYPE_EXPKEY = 2,
+};
+
+/*
+ * These flags are ordered to match the NFSEXP_* flags in
+ * include/linux/nfsd/export.h
+ */
+enum nfsd_export_flags {
+	NFSD_EXPORT_FLAGS_READONLY = 1,
+	NFSD_EXPORT_FLAGS_INSECURE_PORT = 2,
+	NFSD_EXPORT_FLAGS_ROOTSQUASH = 4,
+	NFSD_EXPORT_FLAGS_ALLSQUASH = 8,
+	NFSD_EXPORT_FLAGS_ASYNC = 16,
+	NFSD_EXPORT_FLAGS_GATHERED_WRITES = 32,
+	NFSD_EXPORT_FLAGS_NOREADDIRPLUS = 64,
+	NFSD_EXPORT_FLAGS_SECURITY_LABEL = 128,
+	NFSD_EXPORT_FLAGS_SIGN_FH = 256,
+	NFSD_EXPORT_FLAGS_NOHIDE = 512,
+	NFSD_EXPORT_FLAGS_NOSUBTREECHECK = 1024,
+	NFSD_EXPORT_FLAGS_NOAUTHNLM = 2048,
+	NFSD_EXPORT_FLAGS_MSNFS = 4096,
+	NFSD_EXPORT_FLAGS_FSID = 8192,
+	NFSD_EXPORT_FLAGS_CROSSMOUNT = 16384,
+	NFSD_EXPORT_FLAGS_NOACL = 32768,
+	NFSD_EXPORT_FLAGS_V4ROOT = 65536,
+	NFSD_EXPORT_FLAGS_PNFS = 131072,
+};
+
+/*
+ * These flags are ordered to match the NFSEXP_XPRTSEC_* flags in
+ * include/linux/nfsd/export.h
+ */
+enum nfsd_xprtsec_mode {
+	NFSD_XPRTSEC_MODE_NONE = 1,
+	NFSD_XPRTSEC_MODE_TLS = 2,
+	NFSD_XPRTSEC_MODE_MTLS = 4,
+};
+
+enum {
+	NFSD_A_CACHE_NOTIFY_CACHE_TYPE = 1,
+
+	__NFSD_A_CACHE_NOTIFY_MAX,
+	NFSD_A_CACHE_NOTIFY_MAX = (__NFSD_A_CACHE_NOTIFY_MAX - 1)
+};
+
 enum {
 	NFSD_A_RPC_STATUS_XID = 1,
 	NFSD_A_RPC_STATUS_FLAGS,
@@ -81,6 +128,82 @@ enum {
 	NFSD_A_POOL_MODE_MAX = (__NFSD_A_POOL_MODE_MAX - 1)
 };
 
+enum {
+	NFSD_A_FSLOCATION_HOST = 1,
+	NFSD_A_FSLOCATION_PATH,
+
+	__NFSD_A_FSLOCATION_MAX,
+	NFSD_A_FSLOCATION_MAX = (__NFSD_A_FSLOCATION_MAX - 1)
+};
+
+enum {
+	NFSD_A_FSLOCATIONS_LOCATION = 1,
+
+	__NFSD_A_FSLOCATIONS_MAX,
+	NFSD_A_FSLOCATIONS_MAX = (__NFSD_A_FSLOCATIONS_MAX - 1)
+};
+
+enum {
+	NFSD_A_AUTH_FLAVOR_PSEUDOFLAVOR = 1,
+	NFSD_A_AUTH_FLAVOR_FLAGS,
+
+	__NFSD_A_AUTH_FLAVOR_MAX,
+	NFSD_A_AUTH_FLAVOR_MAX = (__NFSD_A_AUTH_FLAVOR_MAX - 1)
+};
+
+enum {
+	NFSD_A_SVC_EXPORT_SEQNO = 1,
+	NFSD_A_SVC_EXPORT_CLIENT,
+	NFSD_A_SVC_EXPORT_PATH,
+	NFSD_A_SVC_EXPORT_NEGATIVE,
+	NFSD_A_SVC_EXPORT_EXPIRY,
+	NFSD_A_SVC_EXPORT_ANON_UID,
+	NFSD_A_SVC_EXPORT_ANON_GID,
+	NFSD_A_SVC_EXPORT_FSLOCATIONS,
+	NFSD_A_SVC_EXPORT_UUID,
+	NFSD_A_SVC_EXPORT_SECINFO,
+	NFSD_A_SVC_EXPORT_XPRTSEC,
+	NFSD_A_SVC_EXPORT_FLAGS,
+	NFSD_A_SVC_EXPORT_FSID,
+
+	__NFSD_A_SVC_EXPORT_MAX,
+	NFSD_A_SVC_EXPORT_MAX = (__NFSD_A_SVC_EXPORT_MAX - 1)
+};
+
+enum {
+	NFSD_A_SVC_EXPORT_REQS_REQUESTS = 1,
+
+	__NFSD_A_SVC_EXPORT_REQS_MAX,
+	NFSD_A_SVC_EXPORT_REQS_MAX = (__NFSD_A_SVC_EXPORT_REQS_MAX - 1)
+};
+
+enum {
+	NFSD_A_EXPKEY_SEQNO = 1,
+	NFSD_A_EXPKEY_CLIENT,
+	NFSD_A_EXPKEY_FSIDTYPE,
+	NFSD_A_EXPKEY_FSID,
+	NFSD_A_EXPKEY_NEGATIVE,
+	NFSD_A_EXPKEY_EXPIRY,
+	NFSD_A_EXPKEY_PATH,
+
+	__NFSD_A_EXPKEY_MAX,
+	NFSD_A_EXPKEY_MAX = (__NFSD_A_EXPKEY_MAX - 1)
+};
+
+enum {
+	NFSD_A_EXPKEY_REQS_REQUESTS = 1,
+
+	__NFSD_A_EXPKEY_REQS_MAX,
+	NFSD_A_EXPKEY_REQS_MAX = (__NFSD_A_EXPKEY_REQS_MAX - 1)
+};
+
+enum {
+	NFSD_A_CACHE_FLUSH_MASK = 1,
+
+	__NFSD_A_CACHE_FLUSH_MAX,
+	NFSD_A_CACHE_FLUSH_MAX = (__NFSD_A_CACHE_FLUSH_MAX - 1)
+};
+
 enum {
 	NFSD_CMD_RPC_STATUS_GET = 1,
 	NFSD_CMD_THREADS_SET,
@@ -91,9 +214,18 @@ enum {
 	NFSD_CMD_LISTENER_GET,
 	NFSD_CMD_POOL_MODE_SET,
 	NFSD_CMD_POOL_MODE_GET,
+	NFSD_CMD_CACHE_NOTIFY,
+	NFSD_CMD_SVC_EXPORT_GET_REQS,
+	NFSD_CMD_SVC_EXPORT_SET_REQS,
+	NFSD_CMD_EXPKEY_GET_REQS,
+	NFSD_CMD_EXPKEY_SET_REQS,
+	NFSD_CMD_CACHE_FLUSH,
 
 	__NFSD_CMD_MAX,
 	NFSD_CMD_MAX = (__NFSD_CMD_MAX - 1)
 };
 
+#define NFSD_MCGRP_NONE		"none"
+#define NFSD_MCGRP_EXPORTD	"exportd"
+
 #endif /* _UAPI_LINUX_NFSD_NETLINK_H */
diff --git a/include/uapi/linux/sunrpc_netlink.h b/include/uapi/linux/sunrpc_netlink.h
new file mode 100644
index 000000000000..34677f0ec2f9
--- /dev/null
+++ b/include/uapi/linux/sunrpc_netlink.h
@@ -0,0 +1,84 @@
+/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) */
+/* Do not edit directly, auto-generated from: */
+/*	Documentation/netlink/specs/sunrpc_cache.yaml */
+/* YNL-GEN uapi header */
+/* To regenerate run: tools/net/ynl/ynl-regen.sh */
+
+#ifndef _UAPI_LINUX_SUNRPC_NETLINK_H
+#define _UAPI_LINUX_SUNRPC_NETLINK_H
+
+#define SUNRPC_FAMILY_NAME	"sunrpc"
+#define SUNRPC_FAMILY_VERSION	1
+
+enum sunrpc_cache_type {
+	SUNRPC_CACHE_TYPE_IP_MAP = 1,
+	SUNRPC_CACHE_TYPE_UNIX_GID = 2,
+};
+
+enum {
+	SUNRPC_A_CACHE_NOTIFY_CACHE_TYPE = 1,
+
+	__SUNRPC_A_CACHE_NOTIFY_MAX,
+	SUNRPC_A_CACHE_NOTIFY_MAX = (__SUNRPC_A_CACHE_NOTIFY_MAX - 1)
+};
+
+enum {
+	SUNRPC_A_IP_MAP_SEQNO = 1,
+	SUNRPC_A_IP_MAP_CLASS,
+	SUNRPC_A_IP_MAP_ADDR,
+	SUNRPC_A_IP_MAP_DOMAIN,
+	SUNRPC_A_IP_MAP_NEGATIVE,
+	SUNRPC_A_IP_MAP_EXPIRY,
+
+	__SUNRPC_A_IP_MAP_MAX,
+	SUNRPC_A_IP_MAP_MAX = (__SUNRPC_A_IP_MAP_MAX - 1)
+};
+
+enum {
+	SUNRPC_A_IP_MAP_REQS_REQUESTS = 1,
+
+	__SUNRPC_A_IP_MAP_REQS_MAX,
+	SUNRPC_A_IP_MAP_REQS_MAX = (__SUNRPC_A_IP_MAP_REQS_MAX - 1)
+};
+
+enum {
+	SUNRPC_A_UNIX_GID_SEQNO = 1,
+	SUNRPC_A_UNIX_GID_UID,
+	SUNRPC_A_UNIX_GID_GIDS,
+	SUNRPC_A_UNIX_GID_NEGATIVE,
+	SUNRPC_A_UNIX_GID_EXPIRY,
+
+	__SUNRPC_A_UNIX_GID_MAX,
+	SUNRPC_A_UNIX_GID_MAX = (__SUNRPC_A_UNIX_GID_MAX - 1)
+};
+
+enum {
+	SUNRPC_A_UNIX_GID_REQS_REQUESTS = 1,
+
+	__SUNRPC_A_UNIX_GID_REQS_MAX,
+	SUNRPC_A_UNIX_GID_REQS_MAX = (__SUNRPC_A_UNIX_GID_REQS_MAX - 1)
+};
+
+enum {
+	SUNRPC_A_CACHE_FLUSH_MASK = 1,
+
+	__SUNRPC_A_CACHE_FLUSH_MAX,
+	SUNRPC_A_CACHE_FLUSH_MAX = (__SUNRPC_A_CACHE_FLUSH_MAX - 1)
+};
+
+enum {
+	SUNRPC_CMD_CACHE_NOTIFY = 1,
+	SUNRPC_CMD_IP_MAP_GET_REQS,
+	SUNRPC_CMD_IP_MAP_SET_REQS,
+	SUNRPC_CMD_UNIX_GID_GET_REQS,
+	SUNRPC_CMD_UNIX_GID_SET_REQS,
+	SUNRPC_CMD_CACHE_FLUSH,
+
+	__SUNRPC_CMD_MAX,
+	SUNRPC_CMD_MAX = (__SUNRPC_CMD_MAX - 1)
+};
+
+#define SUNRPC_MCGRP_NONE	"none"
+#define SUNRPC_MCGRP_EXPORTD	"exportd"
+
+#endif /* _UAPI_LINUX_SUNRPC_NETLINK_H */
diff --git a/include/ufs/unipro.h b/include/ufs/unipro.h
index f849a2a101ae..9c168703b104 100644
--- a/include/ufs/unipro.h
+++ b/include/ufs/unipro.h
@@ -333,6 +333,11 @@ enum ufs_eom_eye_mask {
 #define DME_LocalTC0ReplayTimeOutVal		0xD042
 #define DME_LocalAFC0ReqTimeOutVal		0xD043
 
+enum ufs_op_mode {
+	LS_MODE = 1,
+	HS_MODE = 2,
+};
+
 /* PA power modes */
 enum ufs_pa_pwr_mode {
 	FAST_MODE	= 1,
diff --git a/init/Kconfig b/init/Kconfig
index 2937c4d308ae..42a16624a625 100644
--- a/init/Kconfig
+++ b/init/Kconfig
@@ -1050,14 +1050,14 @@ config PAGE_COUNTER
 	bool
 
 config CGROUP_FAVOR_DYNMODS
-        bool "Favor dynamic modification latency reduction by default"
-        help
-          This option enables the "favordynmods" mount option by default
-          which reduces the latencies of dynamic cgroup modifications such
-          as task migrations and controller on/offs at the cost of making
-          hot path operations such as forks and exits more expensive.
+	bool "Favor dynamic modification latency reduction by default"
+	help
+	  This option enables the "favordynmods" mount option by default
+	  which reduces the latencies of dynamic cgroup modifications such
+	  as task migrations and controller on/offs at the cost of making
+	  hot path operations such as forks and exits more expensive.
 
-          Say N if unsure.
+	  Say N if unsure.
 
 config MEMCG
 	bool "Memory controller"
@@ -1139,7 +1139,7 @@ config GROUP_SCHED_WEIGHT
 	def_bool n
 
 config GROUP_SCHED_BANDWIDTH
-        def_bool n
+	def_bool n
 
 config FAIR_GROUP_SCHED
 	bool "Group scheduling for SCHED_OTHER"
@@ -1645,10 +1645,10 @@ config LD_ORPHAN_WARN
 	depends on $(ld-option,--orphan-handling=error)
 
 config LD_ORPHAN_WARN_LEVEL
-        string
-        depends on LD_ORPHAN_WARN
-        default "error" if WERROR
-        default "warn"
+	string
+	depends on LD_ORPHAN_WARN
+	default "error" if WERROR
+	default "warn"
 
 config SYSCTL
 	bool
@@ -2070,6 +2070,41 @@ config KALLSYMS_ALL
 
 	  Say N unless you really need all symbols, or kernel live patching.
 
+config KALLSYMS_LINEINFO
+	bool "Embed source file:line information in stack traces"
+	depends on KALLSYMS && DEBUG_INFO
+	help
+	  Embeds an address-to-source-line mapping table in the kernel
+	  image so that stack traces directly include file:line information,
+	  similar to what scripts/decode_stacktrace.sh provides but without
+	  needing external tools or a vmlinux with debug info at runtime.
+
+	  When enabled, stack traces will look like:
+
+	    kmem_cache_alloc_noprof+0x60/0x630 (mm/slub.c:3456)
+	    anon_vma_clone+0x2ed/0xcf0 (mm/rmap.c:412)
+
+	  This requires elfutils (libdw-dev/elfutils-devel) on the build host.
+	  Adds approximately 10-15MB to a typical kernel image (~2-3 bytes
+	  per entry after delta compression, ~4.6M entries for a typical
+	  config).
+
+	  If unsure, say N.
+
+config KALLSYMS_LINEINFO_MODULES
+	bool "Embed source file:line information in module stack traces"
+	depends on KALLSYMS_LINEINFO && MODULES
+	help
+	  Extends KALLSYMS_LINEINFO to loadable kernel modules.  Each .ko
+	  gets a lineinfo table generated from its DWARF data at build time,
+	  so stack traces from module code include (file.c:123) annotations.
+
+	  Requires elfutils (libdw-dev/elfutils-devel) on the build host.
+	  Increases .ko sizes by approximately 2-3 bytes per DWARF line
+	  entry after delta compression.
+
+	  If unsure, say N.
+
 # end of the "standard kernel features (expert users)" menu
 
 config ARCH_HAS_MEMBARRIER_CALLBACKS
diff --git a/kernel/bpf/rqspinlock.c b/kernel/bpf/rqspinlock.c
index e4e338cdb437..e5e27266b813 100644
--- a/kernel/bpf/rqspinlock.c
+++ b/kernel/bpf/rqspinlock.c
@@ -196,8 +196,12 @@ static noinline int check_deadlock_ABBA(rqspinlock_t *lock, u32 mask)
 	return 0;
 }
 
-static noinline int check_timeout(rqspinlock_t *lock, u32 mask,
-				  struct rqspinlock_timeout *ts)
+/*
+ * Returns current monotonic time in ns on success or, negative errno
+ * value on failure due to timeout expiration or detection of deadlock.
+ */
+static noinline s64 clock_deadlock(rqspinlock_t *lock, u32 mask,
+				   struct rqspinlock_timeout *ts)
 {
 	u64 prev = ts->cur;
 	u64 time;
@@ -207,11 +211,11 @@ static noinline int check_timeout(rqspinlock_t *lock, u32 mask,
 			return -EDEADLK;
 		ts->cur = ktime_get_mono_fast_ns();
 		ts->timeout_end = ts->cur + ts->duration;
-		return 0;
+		return (s64)ts->cur;
 	}
 
 	time = ktime_get_mono_fast_ns();
-	if (time > ts->timeout_end)
+	if (time >= ts->timeout_end)
 		return -ETIMEDOUT;
 
 	/*
@@ -219,28 +223,37 @@ static noinline int check_timeout(rqspinlock_t *lock, u32 mask,
 	 * checks.
 	 */
 	if (prev + NSEC_PER_MSEC < time) {
+		int ret;
 		ts->cur = time;
-		return check_deadlock_ABBA(lock, mask);
+		ret = check_deadlock_ABBA(lock, mask);
+		if (ret)
+			return ret;
+
 	}
 
-	return 0;
+	return (s64)time;
 }
 
 /*
- * Do not amortize with spins when res_smp_cond_load_acquire is defined,
- * as the macro does internal amortization for us.
+ * Spin amortized version of RES_CHECK_TIMEOUT. Used when busy-waiting in
+ * atomic_try_cmpxchg().
  */
-#ifndef res_smp_cond_load_acquire
-#define RES_CHECK_TIMEOUT(ts, ret, mask)                              \
-	({                                                            \
-		if (!(ts).spin++)                                     \
-			(ret) = check_timeout((lock), (mask), &(ts)); \
-		(ret);                                                \
+#define RES_CHECK_TIMEOUT_AMORTIZED(ts, ret, mask)				\
+	({									\
+		s64 __timeval_err = 0;						\
+		if (!(ts).spin++)						\
+			__timeval_err = clock_deadlock((lock), (mask), &(ts));	\
+		(ret) = __timeval_err < 0 ? __timeval_err : 0;			\
+		__timeval_err;							\
+	})
+
+#define RES_CHECK_TIMEOUT(ts, ret, mask)					\
+	({									\
+		s64 __timeval_err;						\
+		__timeval_err = clock_deadlock((lock), (mask), &(ts));		\
+		(ret) = __timeval_err < 0 ? __timeval_err : 0;			\
+		__timeval_err;							\
 	})
-#else
-#define RES_CHECK_TIMEOUT(ts, ret, mask)			      \
-	({ (ret) = check_timeout((lock), (mask), &(ts)); })
-#endif
 
 /*
  * Initialize the 'spin' member.
@@ -254,6 +267,17 @@ static noinline int check_timeout(rqspinlock_t *lock, u32 mask,
  */
 #define RES_RESET_TIMEOUT(ts, _duration) ({ (ts).timeout_end = 0; (ts).duration = _duration; })
 
+/*
+ * Limit how often we invoke clock_deadlock() while spin-waiting in
+ * smp_cond_load_acquire_timeout() or atomic_cond_read_acquire_timeout().
+ *
+ * We only override the default value not superceding ARM64's override.
+ */
+#ifndef CONFIG_ARM64
+#undef SMP_TIMEOUT_POLL_COUNT
+#define SMP_TIMEOUT_POLL_COUNT	(16*1024)
+#endif
+
 /*
  * Provide a test-and-set fallback for cases when queued spin lock support is
  * absent from the architecture.
@@ -281,7 +305,7 @@ int __lockfunc resilient_tas_spin_lock(rqspinlock_t *lock)
 	val = atomic_read(&lock->val);
 
 	if (val || !atomic_try_cmpxchg(&lock->val, &val, 1)) {
-		if (RES_CHECK_TIMEOUT(ts, ret, ~0u))
+		if (RES_CHECK_TIMEOUT_AMORTIZED(ts, ret, ~0u) < 0)
 			goto out;
 		cpu_relax();
 		goto retry;
@@ -304,12 +328,6 @@ EXPORT_SYMBOL_GPL(resilient_tas_spin_lock);
  */
 static DEFINE_PER_CPU_ALIGNED(struct qnode, rqnodes[_Q_MAX_NODES]);
 
-#ifndef res_smp_cond_load_acquire
-#define res_smp_cond_load_acquire(v, c) smp_cond_load_acquire(v, c)
-#endif
-
-#define res_atomic_cond_read_acquire(v, c) res_smp_cond_load_acquire(&(v)->counter, (c))
-
 /**
  * resilient_queued_spin_lock_slowpath - acquire the queued spinlock
  * @lock: Pointer to queued spinlock structure
@@ -406,7 +424,9 @@ int __lockfunc resilient_queued_spin_lock_slowpath(rqspinlock_t *lock, u32 val)
 	 */
 	if (val & _Q_LOCKED_MASK) {
 		RES_RESET_TIMEOUT(ts, RES_DEF_TIMEOUT);
-		res_smp_cond_load_acquire(&lock->locked, !VAL || RES_CHECK_TIMEOUT(ts, ret, _Q_LOCKED_MASK));
+		smp_cond_load_acquire_timeout(&lock->locked, !VAL,
+					      RES_CHECK_TIMEOUT(ts, ret, _Q_LOCKED_MASK),
+					      ts.duration);
 	}
 
 	if (ret) {
@@ -567,8 +587,9 @@ int __lockfunc resilient_queued_spin_lock_slowpath(rqspinlock_t *lock, u32 val)
 	 * us.
 	 */
 	RES_RESET_TIMEOUT(ts, RES_DEF_TIMEOUT * 2);
-	val = res_atomic_cond_read_acquire(&lock->val, !(VAL & _Q_LOCKED_PENDING_MASK) ||
-					   RES_CHECK_TIMEOUT(ts, ret, _Q_LOCKED_PENDING_MASK));
+	val = atomic_cond_read_acquire_timeout(&lock->val, !(VAL & _Q_LOCKED_PENDING_MASK),
+					       RES_CHECK_TIMEOUT(ts, ret, _Q_LOCKED_PENDING_MASK),
+					       ts.duration);
 
 	/* Disable queue destruction when we detect deadlocks. */
 	if (ret == -EDEADLK) {
diff --git a/kernel/cgroup/cgroup.c b/kernel/cgroup/cgroup.c
index 43adc96c7f1a..45c0b1ed687a 100644
--- a/kernel/cgroup/cgroup.c
+++ b/kernel/cgroup/cgroup.c
@@ -3934,33 +3934,41 @@ static int cgroup_cpu_pressure_show(struct seq_file *seq, void *v)
 static ssize_t pressure_write(struct kernfs_open_file *of, char *buf,
 			      size_t nbytes, enum psi_res res)
 {
-	struct cgroup_file_ctx *ctx = of->priv;
+	struct cgroup_file_ctx *ctx;
 	struct psi_trigger *new;
 	struct cgroup *cgrp;
 	struct psi_group *psi;
+	ssize_t ret = 0;
 
 	cgrp = cgroup_kn_lock_live(of->kn, false);
 	if (!cgrp)
 		return -ENODEV;
 
-	cgroup_get(cgrp);
-	cgroup_kn_unlock(of->kn);
+	ctx = of->priv;
+	if (!ctx) {
+		ret = -ENODEV;
+		goto out_unlock;
+	}
 
 	/* Allow only one trigger per file descriptor */
 	if (ctx->psi.trigger) {
-		cgroup_put(cgrp);
-		return -EBUSY;
+		ret = -EBUSY;
+		goto out_unlock;
 	}
 
 	psi = cgroup_psi(cgrp);
 	new = psi_trigger_create(psi, buf, res, of->file, of);
 	if (IS_ERR(new)) {
-		cgroup_put(cgrp);
-		return PTR_ERR(new);
+		ret = PTR_ERR(new);
+		goto out_unlock;
 	}
 
 	smp_store_release(&ctx->psi.trigger, new);
-	cgroup_put(cgrp);
+
+out_unlock:
+	cgroup_kn_unlock(of->kn);
+	if (ret)
+		return ret;
 
 	return nbytes;
 }
@@ -5716,16 +5724,6 @@ static void offline_css(struct cgroup_subsys_state *css)
 	RCU_INIT_POINTER(css->cgroup->subsys[ss->id], NULL);
 
 	wake_up_all(&css->cgroup->offline_waitq);
-
-	css->cgroup->nr_dying_subsys[ss->id]++;
-	/*
-	 * Parent css and cgroup cannot be freed until after the freeing
-	 * of child css, see css_free_rwork_fn().
-	 */
-	while ((css = css->parent)) {
-		css->nr_descendants--;
-		css->cgroup->nr_dying_subsys[ss->id]++;
-	}
 }
 
 /**
@@ -6038,6 +6036,8 @@ static void css_killed_ref_fn(struct percpu_ref *ref)
  */
 static void kill_css(struct cgroup_subsys_state *css)
 {
+	struct cgroup_subsys *ss = css->ss;
+
 	lockdep_assert_held(&cgroup_mutex);
 
 	if (css->flags & CSS_DYING)
@@ -6074,6 +6074,16 @@ static void kill_css(struct cgroup_subsys_state *css)
 	 * css is confirmed to be seen as killed on all CPUs.
 	 */
 	percpu_ref_kill_and_confirm(&css->refcnt, css_killed_ref_fn);
+
+	css->cgroup->nr_dying_subsys[ss->id]++;
+	/*
+	 * Parent css and cgroup cannot be freed until after the freeing
+	 * of child css, see css_free_rwork_fn().
+	 */
+	while ((css = css->parent)) {
+		css->nr_descendants--;
+		css->cgroup->nr_dying_subsys[ss->id]++;
+	}
 }
 
 /**
diff --git a/kernel/cgroup/cpuset-internal.h b/kernel/cgroup/cpuset-internal.h
index fd7d19842ded..bb4e692bea30 100644
--- a/kernel/cgroup/cpuset-internal.h
+++ b/kernel/cgroup/cpuset-internal.h
@@ -168,6 +168,11 @@ struct cpuset {
 	int nr_deadline_tasks;
 	int nr_migrate_dl_tasks;
 	u64 sum_migrate_dl_bw;
+	/*
+	 * CPU used for temporary DL bandwidth allocation during attach;
+	 * -1 if no DL bandwidth was allocated in the current attach.
+	 */
+	int dl_bw_cpu;
 
 	/* Invalid partition error code, not lock protected */
 	enum prs_errcode prs_err;
diff --git a/kernel/cgroup/cpuset.c b/kernel/cgroup/cpuset.c
index 1335e437098e..e3a081a07c6d 100644
--- a/kernel/cgroup/cpuset.c
+++ b/kernel/cgroup/cpuset.c
@@ -288,6 +288,7 @@ struct cpuset top_cpuset = {
 	.flags = BIT(CS_CPU_EXCLUSIVE) |
 		 BIT(CS_MEM_EXCLUSIVE) | BIT(CS_SCHED_LOAD_BALANCE),
 	.partition_root_state = PRS_ROOT,
+	.dl_bw_cpu = -1,
 };
 
 /**
@@ -579,6 +580,8 @@ static struct cpuset *dup_or_alloc_cpuset(struct cpuset *cs)
 	if (!trial)
 		return NULL;
 
+	trial->dl_bw_cpu = -1;
+
 	/* Setup cpumask pointer array */
 	cpumask_var_t *pmask[4] = {
 		&trial->cpus_allowed,
@@ -2980,6 +2983,7 @@ static void reset_migrate_dl_data(struct cpuset *cs)
 {
 	cs->nr_migrate_dl_tasks = 0;
 	cs->sum_migrate_dl_bw = 0;
+	cs->dl_bw_cpu = -1;
 }
 
 /* Called by cgroups to determine if a cpuset is usable; cpuset_mutex held */
@@ -3056,6 +3060,8 @@ static int cpuset_can_attach(struct cgroup_taskset *tset)
 			reset_migrate_dl_data(cs);
 			goto out_unlock;
 		}
+
+		cs->dl_bw_cpu = cpu;
 	}
 
 out_success:
@@ -3080,12 +3086,11 @@ static void cpuset_cancel_attach(struct cgroup_taskset *tset)
 	mutex_lock(&cpuset_mutex);
 	dec_attach_in_progress_locked(cs);
 
-	if (cs->nr_migrate_dl_tasks) {
-		int cpu = cpumask_any(cs->effective_cpus);
+	if (cs->dl_bw_cpu >= 0)
+		dl_bw_free(cs->dl_bw_cpu, cs->sum_migrate_dl_bw);
 
-		dl_bw_free(cpu, cs->sum_migrate_dl_bw);
+	if (cs->nr_migrate_dl_tasks)
 		reset_migrate_dl_data(cs);
-	}
 
 	mutex_unlock(&cpuset_mutex);
 }
diff --git a/kernel/cgroup/rdma.c b/kernel/cgroup/rdma.c
index 9967fb25c563..3df7c38ce481 100644
--- a/kernel/cgroup/rdma.c
+++ b/kernel/cgroup/rdma.c
@@ -9,6 +9,7 @@
  */
 
 #include <linux/bitops.h>
+#include <linux/limits.h>
 #include <linux/slab.h>
 #include <linux/seq_file.h>
 #include <linux/cgroup.h>
@@ -17,6 +18,22 @@
 
 #define RDMACG_MAX_STR "max"
 
+enum rdmacg_limit_tokens {
+	RDMACG_HCA_HANDLE_VAL,
+	RDMACG_HCA_HANDLE_MAX,
+	RDMACG_HCA_OBJECT_VAL,
+	RDMACG_HCA_OBJECT_MAX,
+	NR_RDMACG_LIMIT_TOKENS,
+};
+
+static const match_table_t rdmacg_limit_tokens = {
+	{ RDMACG_HCA_HANDLE_VAL,	"hca_handle=%d"	},
+	{ RDMACG_HCA_HANDLE_MAX,	"hca_handle=max"	},
+	{ RDMACG_HCA_OBJECT_VAL,	"hca_object=%d"	},
+	{ RDMACG_HCA_OBJECT_MAX,	"hca_object=max"	},
+	{ NR_RDMACG_LIMIT_TOKENS,	NULL			},
+};
+
 /*
  * Protects list of resource pools maintained on per cgroup basis
  * and rdma device list.
@@ -283,7 +300,7 @@ int rdmacg_try_charge(struct rdma_cgroup **rdmacg,
 			ret = PTR_ERR(rpool);
 			goto err;
 		} else {
-			new = rpool->resources[index].usage + 1;
+			new = (s64)rpool->resources[index].usage + 1;
 			if (new > rpool->resources[index].max) {
 				ret = -EAGAIN;
 				goto err;
@@ -355,62 +372,6 @@ void rdmacg_unregister_device(struct rdmacg_device *device)
 }
 EXPORT_SYMBOL(rdmacg_unregister_device);
 
-static int parse_resource(char *c, int *intval)
-{
-	substring_t argstr;
-	char *name, *value = c;
-	size_t len;
-	int ret, i;
-
-	name = strsep(&value, "=");
-	if (!name || !value)
-		return -EINVAL;
-
-	i = match_string(rdmacg_resource_names, RDMACG_RESOURCE_MAX, name);
-	if (i < 0)
-		return i;
-
-	len = strlen(value);
-
-	argstr.from = value;
-	argstr.to = value + len;
-
-	ret = match_int(&argstr, intval);
-	if (ret >= 0) {
-		if (*intval < 0)
-			return -EINVAL;
-		return i;
-	}
-	if (strncmp(value, RDMACG_MAX_STR, len) == 0) {
-		*intval = S32_MAX;
-		return i;
-	}
-	return -EINVAL;
-}
-
-static int rdmacg_parse_limits(char *options,
-			       int *new_limits, unsigned long *enables)
-{
-	char *c;
-	int err = -EINVAL;
-
-	/* parse resource options */
-	while ((c = strsep(&options, " ")) != NULL) {
-		int index, intval;
-
-		index = parse_resource(c, &intval);
-		if (index < 0)
-			goto err;
-
-		new_limits[index] = intval;
-		*enables |= BIT(index);
-	}
-	return 0;
-
-err:
-	return err;
-}
-
 static struct rdmacg_device *rdmacg_get_device_locked(const char *name)
 {
 	struct rdmacg_device *device;
@@ -432,6 +393,7 @@ static ssize_t rdmacg_resource_set_max(struct kernfs_open_file *of,
 	struct rdmacg_resource_pool *rpool;
 	struct rdmacg_device *device;
 	char *options = strstrip(buf);
+	char *p;
 	int *new_limits;
 	unsigned long enables = 0;
 	int i = 0, ret = 0;
@@ -449,9 +411,45 @@ static ssize_t rdmacg_resource_set_max(struct kernfs_open_file *of,
 		goto err;
 	}
 
-	ret = rdmacg_parse_limits(options, new_limits, &enables);
-	if (ret)
-		goto parse_err;
+	/* parse resource limit tokens */
+	while ((p = strsep(&options, " \t\n"))) {
+		substring_t args[MAX_OPT_ARGS];
+		int tok, intval;
+
+		if (!*p)
+			continue;
+
+		tok = match_token(p, rdmacg_limit_tokens, args);
+		switch (tok) {
+		case RDMACG_HCA_HANDLE_VAL:
+			if (match_int(&args[0], &intval) || intval < 0) {
+				ret = -EINVAL;
+				goto parse_err;
+			}
+			new_limits[RDMACG_RESOURCE_HCA_HANDLE] = intval;
+			enables |= BIT(RDMACG_RESOURCE_HCA_HANDLE);
+			break;
+		case RDMACG_HCA_HANDLE_MAX:
+			new_limits[RDMACG_RESOURCE_HCA_HANDLE] = S32_MAX;
+			enables |= BIT(RDMACG_RESOURCE_HCA_HANDLE);
+			break;
+		case RDMACG_HCA_OBJECT_VAL:
+			if (match_int(&args[0], &intval) || intval < 0) {
+				ret = -EINVAL;
+				goto parse_err;
+			}
+			new_limits[RDMACG_RESOURCE_HCA_OBJECT] = intval;
+			enables |= BIT(RDMACG_RESOURCE_HCA_OBJECT);
+			break;
+		case RDMACG_HCA_OBJECT_MAX:
+			new_limits[RDMACG_RESOURCE_HCA_OBJECT] = S32_MAX;
+			enables |= BIT(RDMACG_RESOURCE_HCA_OBJECT);
+			break;
+		default:
+			ret = -EINVAL;
+			goto parse_err;
+		}
+	}
 
 	/* acquire lock to synchronize with hot plug devices */
 	mutex_lock(&rdmacg_mutex);
diff --git a/kernel/fork.c b/kernel/fork.c
index f1ad69c6dc2d..f43503f78477 100644
--- a/kernel/fork.c
+++ b/kernel/fork.c
@@ -2666,8 +2666,6 @@ struct task_struct *create_io_thread(int (*fn)(void *), void *arg, int node)
  *
  * It copies the process, and if successful kick-starts
  * it and waits for it to finish using the VM if required.
- *
- * args->exit_signal is expected to be checked for sanity by the caller.
  */
 pid_t kernel_clone(struct kernel_clone_args *args)
 {
@@ -2702,6 +2700,9 @@ pid_t kernel_clone(struct kernel_clone_args *args)
 	    (args->pidfd == args->parent_tid))
 		return -EINVAL;
 
+	if (!valid_signal(args->exit_signal))
+		return -EINVAL;
+
 	/*
 	 * Determine whether and which event to report to ptracer.  When
 	 * called from kernel_thread or CLONE_UNTRACED is explicitly
@@ -2900,11 +2901,9 @@ static noinline int copy_clone_args_from_user(struct kernel_clone_args *kargs,
 		return -EINVAL;
 
 	/*
-	 * Verify that higher 32bits of exit_signal are unset and that
-	 * it is a valid signal
+	 * Verify that higher 32bits of exit_signal are unset
 	 */
-	if (unlikely((args.exit_signal & ~((u64)CSIGNAL)) ||
-		     !valid_signal(args.exit_signal)))
+	if (unlikely(args.exit_signal & ~((u64)CSIGNAL)))
 		return -EINVAL;
 
 	if ((args.flags & CLONE_INTO_CGROUP) &&
diff --git a/kernel/kallsyms.c b/kernel/kallsyms.c
index aec2f06858af..e6f796d43dd7 100644
--- a/kernel/kallsyms.c
+++ b/kernel/kallsyms.c
@@ -467,6 +467,40 @@ static int append_buildid(char *buffer,   const char *modname,
 
 #endif /* CONFIG_STACKTRACE_BUILD_ID */
 
+#include <linux/mod_lineinfo.h>
+
+bool kallsyms_lookup_lineinfo(unsigned long addr,
+			      const char **file, unsigned int *line)
+{
+	struct lineinfo_table tbl;
+	unsigned long long raw_offset;
+
+	if (!IS_ENABLED(CONFIG_KALLSYMS_LINEINFO) ||
+	    !lineinfo_num_entries || !lineinfo_num_blocks)
+		return false;
+
+	/* Compute offset from _text */
+	if (addr < (unsigned long)_text)
+		return false;
+
+	raw_offset = addr - (unsigned long)_text;
+	if (raw_offset > UINT_MAX)
+		return false;
+
+	tbl.blk_addrs	= lineinfo_block_addrs;
+	tbl.blk_offsets	= lineinfo_block_offsets;
+	tbl.data	= lineinfo_data;
+	tbl.data_size	= lineinfo_data_size;
+	tbl.file_offsets = lineinfo_file_offsets;
+	tbl.filenames	= lineinfo_filenames;
+	tbl.num_entries	= lineinfo_num_entries;
+	tbl.num_blocks	= lineinfo_num_blocks;
+	tbl.num_files	= lineinfo_num_files;
+	tbl.filenames_size = lineinfo_filenames_size;
+
+	return lineinfo_search(&tbl, (unsigned int)raw_offset, file, line);
+}
+
 /* Look up a kernel symbol and return it in a text buffer. */
 static int __sprint_symbol(char *buffer, unsigned long address,
 			   int symbol_offset, int add_offset, int add_buildid)
@@ -497,6 +531,28 @@ static int __sprint_symbol(char *buffer, unsigned long address,
 		len += sprintf(buffer + len, "]");
 	}
 
+	if (IS_ENABLED(CONFIG_KALLSYMS_LINEINFO)) {
+		const char *li_file;
+		unsigned int li_line;
+		bool found = false;
+
+		if (!modname)
+			found = kallsyms_lookup_lineinfo(address,
+							 &li_file, &li_line);
+		else if (IS_ENABLED(CONFIG_KALLSYMS_LINEINFO_MODULES)) {
+			struct module *mod = __module_address(address);
+
+			if (mod)
+				found = module_lookup_lineinfo(mod, address,
+							      &li_file,
+							      &li_line);
+		}
+
+		if (found)
+			len += snprintf(buffer + len, KSYM_SYMBOL_LEN - len,
+					" (%s:%u)", li_file, li_line);
+	}
+
 	return len;
 }
 
@@ -569,6 +625,7 @@ int sprint_backtrace(char *buffer, unsigned long address)
 {
 	return __sprint_symbol(buffer, address, -1, 1, 0);
 }
+EXPORT_SYMBOL_GPL(sprint_backtrace);
 
 /**
  * sprint_backtrace_build_id - Look up a backtrace symbol and return it in a text buffer
@@ -589,6 +646,7 @@ int sprint_backtrace_build_id(char *buffer, unsigned long address)
 {
 	return __sprint_symbol(buffer, address, -1, 1, 1);
 }
+EXPORT_SYMBOL_GPL(sprint_backtrace_build_id);
 
 /* To avoid using get_symbol_offset for every symbol, we carry prefix along. */
 struct kallsym_iter {
diff --git a/kernel/kallsyms_internal.h b/kernel/kallsyms_internal.h
index 81a867dbe57d..ffe4c658067e 100644
--- a/kernel/kallsyms_internal.h
+++ b/kernel/kallsyms_internal.h
@@ -15,4 +15,15 @@ extern const u16 kallsyms_token_index[];
 extern const unsigned int kallsyms_markers[];
 extern const u8 kallsyms_seqs_of_names[];
 
+extern const u32 lineinfo_num_entries;
+extern const u32 lineinfo_num_files;
+extern const u32 lineinfo_num_blocks;
+extern const u32 lineinfo_block_addrs[];
+extern const u32 lineinfo_block_offsets[];
+extern const u32 lineinfo_data_size;
+extern const u8  lineinfo_data[];
+extern const u32 lineinfo_file_offsets[];
+extern const u32 lineinfo_filenames_size;
+extern const char lineinfo_filenames[];
+
 #endif // LINUX_KALLSYMS_INTERNAL_H_
diff --git a/kernel/liveupdate/kexec_handover.c b/kernel/liveupdate/kexec_handover.c
index 94762de1fe5f..18509d8082ea 100644
--- a/kernel/liveupdate/kexec_handover.c
+++ b/kernel/liveupdate/kexec_handover.c
@@ -762,19 +762,24 @@ int kho_add_subtree(const char *name, void *blob, size_t size)
 		goto out_pack;
 	}
 
-	err = fdt_setprop(root_fdt, off, KHO_SUB_TREE_PROP_NAME,
-			  &phys, sizeof(phys));
-	if (err < 0)
-		goto out_pack;
+	fdt_err = fdt_setprop(root_fdt, off, KHO_SUB_TREE_PROP_NAME,
+			      &phys, sizeof(phys));
+	if (fdt_err < 0)
+		goto out_del_node;
 
-	err = fdt_setprop(root_fdt, off, KHO_SUB_TREE_SIZE_PROP_NAME,
-			  &size_u64, sizeof(size_u64));
-	if (err < 0)
-		goto out_pack;
+	fdt_err = fdt_setprop(root_fdt, off, KHO_SUB_TREE_SIZE_PROP_NAME,
+			      &size_u64, sizeof(size_u64));
+	if (fdt_err < 0)
+		goto out_del_node;
 
 	WARN_ON_ONCE(kho_debugfs_blob_add(&kho_out.dbg, name, blob,
 					  size, false));
 
+	err = 0;
+	goto out_pack;
+
+out_del_node:
+	fdt_del_node(root_fdt, off);
 out_pack:
 	fdt_pack(root_fdt);
 
diff --git a/kernel/liveupdate/luo_session.c b/kernel/liveupdate/luo_session.c
index a3327a28fc1f..7a42385dabe2 100644
--- a/kernel/liveupdate/luo_session.c
+++ b/kernel/liveupdate/luo_session.c
@@ -514,11 +514,12 @@ int luo_session_deserialize(void)
 {
 	struct luo_session_header *sh = &luo_session_global.incoming;
 	static bool is_deserialized;
-	static int err;
+	static int saved_err;
+	int err;
 
 	/* If has been deserialized, always return the same error code */
 	if (is_deserialized)
-		return err;
+		return saved_err;
 
 	is_deserialized = true;
 	if (!sh->active)
@@ -547,7 +548,8 @@ int luo_session_deserialize(void)
 			pr_warn("Failed to allocate session [%.*s] during deserialization %pe\n",
 				(int)sizeof(sh->ser[i].name),
 				sh->ser[i].name, session);
-			return PTR_ERR(session);
+			err = PTR_ERR(session);
+			goto save_err;
 		}
 
 		err = luo_session_insert(sh, session);
@@ -555,7 +557,7 @@ int luo_session_deserialize(void)
 			pr_warn("Failed to insert session [%s] %pe\n",
 				session->name, ERR_PTR(err));
 			luo_session_free(session);
-			return err;
+			goto save_err;
 		}
 
 		scoped_guard(mutex, &session->mutex) {
@@ -565,7 +567,7 @@ int luo_session_deserialize(void)
 		if (err) {
 			pr_warn("Failed to deserialize files for session [%s] %pe\n",
 				session->name, ERR_PTR(err));
-			return err;
+			goto save_err;
 		}
 	}
 
@@ -574,6 +576,9 @@ int luo_session_deserialize(void)
 	sh->ser = NULL;
 
 	return 0;
+save_err:
+	saved_err = err;
+	return err;
 }
 
 int luo_session_serialize(void)
diff --git a/kernel/locking/lockdep.c b/kernel/locking/lockdep.c
index 2d4c5bab5af8..f13883162cfe 100644
--- a/kernel/locking/lockdep.c
+++ b/kernel/locking/lockdep.c
@@ -796,8 +796,10 @@ static void lockdep_print_held_locks(struct task_struct *p)
 	 * It's not reliable to print a task's held locks if it's not sleeping
 	 * and it's not the current task.
 	 */
+#ifndef CONFIG_DEBUG_AID_FOR_SYZBOT
 	if (p != current && task_is_running(p))
 		return;
+#endif
 	for (i = 0; i < depth; i++) {
 		printk(" #%d: ", i);
 		print_lock(p->held_locks + i);
diff --git a/kernel/module/kallsyms.c b/kernel/module/kallsyms.c
index 0fc11e45df9b..8715a923ba53 100644
--- a/kernel/module/kallsyms.c
+++ b/kernel/module/kallsyms.c
@@ -494,3 +494,83 @@ int module_kallsyms_on_each_symbol(const char *modname,
 	mutex_unlock(&module_mutex);
 	return ret;
 }
+
+#include <linux/mod_lineinfo.h>
+
+/*
+ * Look up source file:line for an address within a loaded module.
+ * Uses the .mod_lineinfo section embedded in the .ko at build time.
+ *
+ * Safe in NMI/panic context: no locks, no allocations.
+ * Caller must hold RCU read lock (or be in a context where the module
+ * cannot be unloaded).
+ */
+bool module_lookup_lineinfo(struct module *mod, unsigned long addr,
+			    const char **file, unsigned int *line)
+{
+	const struct mod_lineinfo_header *hdr;
+	struct lineinfo_table tbl;
+	const void *base;
+	u32 section_size;
+	unsigned long text_base;
+	unsigned long long raw_offset;
+
+	if (!IS_ENABLED(CONFIG_KALLSYMS_LINEINFO_MODULES))
+		return false;
+
+	base = mod->lineinfo_data;
+	if (!base)
+		return false;
+
+	section_size = mod->lineinfo_data_size;
+	if (section_size < sizeof(*hdr))
+		return false;
+
+	hdr = base;
+
+	if (hdr->num_entries == 0 || hdr->num_blocks == 0)
+		return false;
+
+	/* Validate each sub-array fits within the section */
+	if (hdr->blocks_offset + hdr->blocks_size > section_size)
+		return false;
+	if (hdr->data_offset + hdr->data_size > section_size)
+		return false;
+	if (hdr->files_offset + hdr->files_size > section_size)
+		return false;
+	if (hdr->filenames_offset + hdr->filenames_size > section_size)
+		return false;
+
+	/* Validate array sizes match declared counts */
+	if (hdr->blocks_size < hdr->num_blocks * 2 * sizeof(u32))
+		return false;
+	if (hdr->files_size < hdr->num_files * sizeof(u32))
+		return false;
+
+	/*
+	 * Compute offset from module .text base.
+	 * NOTE: This assumes .text is at the start of the MOD_TEXT segment.
+	 * A proper fix would use ELF relocations to reference .text directly.
+	 */
+	text_base = (unsigned long)mod->mem[MOD_TEXT].base;
+	if (addr < text_base)
+		return false;
+
+	raw_offset = addr - text_base;
+	if (raw_offset > U32_MAX)
+		return false;
+
+	tbl.blk_addrs	= base + hdr->blocks_offset;
+	tbl.blk_offsets	= base + hdr->blocks_offset +
+			  hdr->num_blocks * sizeof(u32);
+	tbl.data	= base + hdr->data_offset;
+	tbl.data_size	= hdr->data_size;
+	tbl.file_offsets = base + hdr->files_offset;
+	tbl.filenames	= base + hdr->filenames_offset;
+	tbl.num_entries	= hdr->num_entries;
+	tbl.num_blocks	= hdr->num_blocks;
+	tbl.num_files	= hdr->num_files;
+	tbl.filenames_size = hdr->filenames_size;
+
+	return lineinfo_search(&tbl, (unsigned int)raw_offset, file, line);
+}
diff --git a/kernel/module/main.c b/kernel/module/main.c
index 46dd8d25a605..4824f310e2d9 100644
--- a/kernel/module/main.c
+++ b/kernel/module/main.c
@@ -2712,6 +2712,9 @@ static int find_module_sections(struct module *mod, struct load_info *info)
 	mod->btf_base_data = any_section_objs(info, ".BTF.base", 1,
 					      &mod->btf_base_data_size);
 #endif
+	if (IS_ENABLED(CONFIG_KALLSYMS_LINEINFO_MODULES))
+		mod->lineinfo_data = any_section_objs(info, ".mod_lineinfo", 1,
+						      &mod->lineinfo_data_size);
 #ifdef CONFIG_JUMP_LABEL
 	mod->jump_entries = section_objs(info, "__jump_table",
 					sizeof(*mod->jump_entries),
diff --git a/kernel/nsproxy.c b/kernel/nsproxy.c
index d9d3d5973bf5..71bf31308767 100644
--- a/kernel/nsproxy.c
+++ b/kernel/nsproxy.c
@@ -215,7 +215,7 @@ int unshare_nsproxy_namespaces(unsigned long unshare_flags,
 	u64 flags = unshare_flags;
 	int err = 0;
 
-	if (!(flags & (CLONE_NS_ALL & ~CLONE_NEWUSER)))
+	if (!(flags & (CLONE_NS_ALL & ~(CLONE_NEWUSER | UNSHARE_EMPTY_MNTNS))))
 		return 0;
 
 	user_ns = new_cred ? new_cred->user_ns : current_user_ns();
diff --git a/kernel/power/swap.c b/kernel/power/swap.c
index 2e64869bb5a0..cc4764149e8f 100644
--- a/kernel/power/swap.c
+++ b/kernel/power/swap.c
@@ -341,7 +341,7 @@ static int swsusp_swap_check(void)
 	 * This is called before saving the image.
 	 */
 	if (swsusp_resume_device)
-		res = swap_type_of(swsusp_resume_device, swsusp_resume_block);
+		res = find_hibernation_swap_type(swsusp_resume_device, swsusp_resume_block);
 	else
 		res = find_first_swap(&swsusp_resume_device);
 	if (res < 0)
diff --git a/kernel/power/user.c b/kernel/power/user.c
index be77f3556bd7..d0fcfba7ac23 100644
--- a/kernel/power/user.c
+++ b/kernel/power/user.c
@@ -71,7 +71,7 @@ static int snapshot_open(struct inode *inode, struct file *filp)
 	memset(&data->handle, 0, sizeof(struct snapshot_handle));
 	if ((filp->f_flags & O_ACCMODE) == O_RDONLY) {
 		/* Hibernating.  The image device should be accessible. */
-		data->swap = swap_type_of(swsusp_resume_device, 0);
+		data->swap = pin_hibernation_swap_type(swsusp_resume_device, 0);
 		data->mode = O_RDONLY;
 		data->free_bitmaps = false;
 		error = pm_notifier_call_chain_robust(PM_HIBERNATION_PREPARE, PM_POST_HIBERNATION);
@@ -90,8 +90,10 @@ static int snapshot_open(struct inode *inode, struct file *filp)
 			data->free_bitmaps = !error;
 		}
 	}
-	if (error)
+	if (error) {
+		unpin_hibernation_swap_type(data->swap);
 		hibernate_release();
+	}
 
 	data->frozen = false;
 	data->ready = false;
@@ -115,6 +117,7 @@ static int snapshot_release(struct inode *inode, struct file *filp)
 	data = filp->private_data;
 	data->dev = 0;
 	free_all_swap_pages(data->swap);
+	unpin_hibernation_swap_type(data->swap);
 	if (data->frozen) {
 		pm_restore_gfp_mask();
 		free_basic_memory_bitmaps();
@@ -235,11 +238,17 @@ static int snapshot_set_swap_area(struct snapshot_data *data,
 		offset = swap_area.offset;
 	}
 
+	/*
+	 * Unpin the swap device if a swap area was already
+	 * set by SNAPSHOT_SET_SWAP_AREA.
+	 */
+	unpin_hibernation_swap_type(data->swap);
+
 	/*
 	 * User space encodes device types as two-byte values,
 	 * so we need to recode them
 	 */
-	data->swap = swap_type_of(swdev, offset);
+	data->swap = pin_hibernation_swap_type(swdev, offset);
 	if (data->swap < 0)
 		return swdev ? -ENODEV : -EINVAL;
 	data->dev = swdev;
diff --git a/kernel/sched/ext.c b/kernel/sched/ext.c
index e426e27b6794..ac41eab29e3d 100644
--- a/kernel/sched/ext.c
+++ b/kernel/sched/ext.c
@@ -32,11 +32,21 @@ static const struct rhashtable_params scx_sched_hash_params = {
 	.key_len		= sizeof_field(struct scx_sched, ops.sub_cgroup_id),
 	.key_offset		= offsetof(struct scx_sched, ops.sub_cgroup_id),
 	.head_offset		= offsetof(struct scx_sched, hash_node),
+	.insecure_elasticity	= true,	/* inserted under scx_sched_lock */
 };
 
 static struct rhashtable scx_sched_hash;
 #endif
 
+/* see SCX_OPS_TID_TO_TASK */
+static const struct rhashtable_params scx_tid_hash_params = {
+	.key_len		= sizeof_field(struct sched_ext_entity, tid),
+	.key_offset		= offsetof(struct sched_ext_entity, tid),
+	.head_offset		= offsetof(struct sched_ext_entity, tid_hash_node),
+	.insecure_elasticity	= true,	/* inserted/removed under scx_tasks_lock */
+};
+static struct rhashtable scx_tid_hash;
+
 /*
  * During exit, a task may schedule after losing its PIDs. When disabling the
  * BPF scheduler, we need to be able to iterate tasks in every state to
@@ -52,15 +62,28 @@ DEFINE_STATIC_KEY_FALSE(__scx_enabled);
 DEFINE_STATIC_PERCPU_RWSEM(scx_fork_rwsem);
 static atomic_t scx_enable_state_var = ATOMIC_INIT(SCX_DISABLED);
 static DEFINE_RAW_SPINLOCK(scx_bypass_lock);
-static cpumask_var_t scx_bypass_lb_donee_cpumask;
-static cpumask_var_t scx_bypass_lb_resched_cpumask;
 static bool scx_init_task_enabled;
 static bool scx_switching_all;
 DEFINE_STATIC_KEY_FALSE(__scx_switched_all);
+static DEFINE_STATIC_KEY_FALSE(__scx_tid_to_task_enabled);
+
+/*
+ * True once SCX_OPS_TID_TO_TASK has been negotiated with the root scheduler
+ * and the tid->task table is live. Wraps the static key so callers don't
+ * take the address, and hints "likely enabled" for the common case where
+ * the feature is in use.
+ */
+static inline bool scx_tid_to_task_enabled(void)
+{
+	return static_branch_likely(&__scx_tid_to_task_enabled);
+}
 
 static atomic_long_t scx_nr_rejected = ATOMIC_LONG_INIT(0);
 static atomic_long_t scx_hotplug_seq = ATOMIC_LONG_INIT(0);
 
+/* Global cursor for the per-CPU tid allocator. Starts at 1; tid 0 is reserved. */
+static atomic64_t scx_tid_cursor = ATOMIC64_INIT(1);
+
 #ifdef CONFIG_EXT_SUB_SCHED
 /*
  * The sub sched being enabled. Used by scx_disable_and_exit_task() to exit
@@ -109,6 +132,17 @@ struct scx_kick_syncs {
 
 static DEFINE_PER_CPU(struct scx_kick_syncs __rcu *, scx_kick_syncs);
 
+/*
+ * Per-CPU buffered allocator state for p->scx.tid. Each CPU pulls a chunk of
+ * SCX_TID_CHUNK ids from scx_tid_cursor and hands them out locally without
+ * further synchronization. See scx_alloc_tid().
+ */
+struct scx_tid_alloc {
+	u64	next;
+	u64	end;
+};
+static DEFINE_PER_CPU(struct scx_tid_alloc, scx_tid_alloc);
+
 /*
  * Direct dispatch marker.
  *
@@ -469,24 +503,35 @@ static inline void update_locked_rq(struct rq *rq)
 	__this_cpu_write(scx_locked_rq_state, rq);
 }
 
-#define SCX_CALL_OP(sch, op, rq, args...)					\
+/*
+ * SCX ops can recurse via scx_bpf_sub_dispatch() - the inner call must not
+ * clobber the outer's scx_locked_rq_state. Save it on entry, restore on exit.
+ */
+#define SCX_CALL_OP(sch, op, locked_rq, args...)				\
 do {										\
-	if (rq)									\
-		update_locked_rq(rq);						\
+	struct rq *__prev_locked_rq;						\
+										\
+	if (locked_rq) {							\
+		__prev_locked_rq = scx_locked_rq();				\
+		update_locked_rq(locked_rq);					\
+	}									\
 	(sch)->ops.op(args);							\
-	if (rq)									\
-		update_locked_rq(NULL);						\
+	if (locked_rq)								\
+		update_locked_rq(__prev_locked_rq);				\
 } while (0)
 
-#define SCX_CALL_OP_RET(sch, op, rq, args...)					\
+#define SCX_CALL_OP_RET(sch, op, locked_rq, args...)				\
 ({										\
+	struct rq *__prev_locked_rq;						\
 	__typeof__((sch)->ops.op(args)) __ret;					\
 										\
-	if (rq)									\
-		update_locked_rq(rq);						\
+	if (locked_rq) {							\
+		__prev_locked_rq = scx_locked_rq();				\
+		update_locked_rq(locked_rq);					\
+	}									\
 	__ret = (sch)->ops.op(args);						\
-	if (rq)									\
-		update_locked_rq(NULL);						\
+	if (locked_rq)								\
+		update_locked_rq(__prev_locked_rq);				\
 	__ret;									\
 })
 
@@ -498,39 +543,39 @@ do {										\
  * those subject tasks.
  *
  * Every SCX_CALL_OP_TASK*() call site invokes its op with @p's rq lock held -
- * either via the @rq argument here, or (for ops.select_cpu()) via @p's pi_lock
- * held by try_to_wake_up() with rq tracking via scx_rq.in_select_cpu. So if
- * kf_tasks[] is set, @p's scheduler-protected fields are stable.
+ * either via the @locked_rq argument here, or (for ops.select_cpu()) via @p's
+ * pi_lock held by try_to_wake_up() with rq tracking via scx_rq.in_select_cpu.
+ * So if kf_tasks[] is set, @p's scheduler-protected fields are stable.
  *
  * kf_tasks[] can not stack, so task-based SCX ops must not nest. The
  * WARN_ON_ONCE() in each macro catches a re-entry of any of the three variants
  * while a previous one is still in progress.
  */
-#define SCX_CALL_OP_TASK(sch, op, rq, task, args...)				\
+#define SCX_CALL_OP_TASK(sch, op, locked_rq, task, args...)			\
 do {										\
 	WARN_ON_ONCE(current->scx.kf_tasks[0]);					\
 	current->scx.kf_tasks[0] = task;					\
-	SCX_CALL_OP((sch), op, rq, task, ##args);				\
+	SCX_CALL_OP((sch), op, locked_rq, task, ##args);			\
 	current->scx.kf_tasks[0] = NULL;					\
 } while (0)
 
-#define SCX_CALL_OP_TASK_RET(sch, op, rq, task, args...)			\
+#define SCX_CALL_OP_TASK_RET(sch, op, locked_rq, task, args...)			\
 ({										\
 	__typeof__((sch)->ops.op(task, ##args)) __ret;				\
 	WARN_ON_ONCE(current->scx.kf_tasks[0]);					\
 	current->scx.kf_tasks[0] = task;					\
-	__ret = SCX_CALL_OP_RET((sch), op, rq, task, ##args);			\
+	__ret = SCX_CALL_OP_RET((sch), op, locked_rq, task, ##args);		\
 	current->scx.kf_tasks[0] = NULL;					\
 	__ret;									\
 })
 
-#define SCX_CALL_OP_2TASKS_RET(sch, op, rq, task0, task1, args...)		\
+#define SCX_CALL_OP_2TASKS_RET(sch, op, locked_rq, task0, task1, args...)	\
 ({										\
 	__typeof__((sch)->ops.op(task0, task1, ##args)) __ret;			\
 	WARN_ON_ONCE(current->scx.kf_tasks[0]);					\
 	current->scx.kf_tasks[0] = task0;					\
 	current->scx.kf_tasks[1] = task1;					\
-	__ret = SCX_CALL_OP_RET((sch), op, rq, task0, task1, ##args);		\
+	__ret = SCX_CALL_OP_RET((sch), op, locked_rq, task0, task1, ##args);	\
 	current->scx.kf_tasks[0] = NULL;					\
 	current->scx.kf_tasks[1] = NULL;					\
 	__ret;									\
@@ -1388,13 +1433,13 @@ static void call_task_dequeue(struct scx_sched *sch, struct rq *rq,
 	p->scx.flags &= ~SCX_TASK_IN_CUSTODY;
 }
 
-static void local_dsq_post_enq(struct scx_dispatch_q *dsq, struct task_struct *p,
-			       u64 enq_flags)
+static void local_dsq_post_enq(struct scx_sched *sch, struct scx_dispatch_q *dsq,
+			       struct task_struct *p, u64 enq_flags)
 {
 	struct rq *rq = container_of(dsq, struct rq, scx.local_dsq);
 	bool preempt = false;
 
-	call_task_dequeue(scx_root, rq, p, 0);
+	call_task_dequeue(sch, rq, p, 0);
 
 	/*
 	 * If @rq is in balance, the CPU is already vacant and looking for the
@@ -1494,11 +1539,13 @@ static void dispatch_enqueue(struct scx_sched *sch, struct rq *rq,
 			if (!(dsq->id & SCX_DSQ_FLAG_BUILTIN))
 				rcu_assign_pointer(dsq->first_task, p);
 		} else {
-			bool was_empty;
-
-			was_empty = list_empty(&dsq->list);
+			/*
+			 * dsq->list can contain parked BPF iterator cursors, so
+			 * list_empty() here isn't a reliable proxy for "no real
+			 * task in the DSQ". Test dsq->first_task directly.
+			 */
 			list_add_tail(&p->scx.dsq_list.node, &dsq->list);
-			if (was_empty && !(dsq->id & SCX_DSQ_FLAG_BUILTIN))
+			if (!dsq->first_task && !(dsq->id & SCX_DSQ_FLAG_BUILTIN))
 				rcu_assign_pointer(dsq->first_task, p);
 		}
 	}
@@ -1518,7 +1565,7 @@ static void dispatch_enqueue(struct scx_sched *sch, struct rq *rq,
 	 * concurrently in a non-atomic way.
 	 */
 	if (is_local) {
-		local_dsq_post_enq(dsq, p, enq_flags);
+		local_dsq_post_enq(sch, dsq, p, enq_flags);
 	} else {
 		/*
 		 * Task on global/bypass DSQ: leave custody, task on
@@ -2129,7 +2176,8 @@ static void wakeup_preempt_scx(struct rq *rq, struct task_struct *p, int wake_fl
 		schedule_reenq_local(rq, 0);
 }
 
-static void move_local_task_to_local_dsq(struct task_struct *p, u64 enq_flags,
+static void move_local_task_to_local_dsq(struct scx_sched *sch,
+					 struct task_struct *p, u64 enq_flags,
 					 struct scx_dispatch_q *src_dsq,
 					 struct rq *dst_rq)
 {
@@ -2149,7 +2197,7 @@ static void move_local_task_to_local_dsq(struct task_struct *p, u64 enq_flags,
 	dsq_inc_nr(dst_dsq, p, enq_flags);
 	p->scx.dsq = dst_dsq;
 
-	local_dsq_post_enq(dst_dsq, p, enq_flags);
+	local_dsq_post_enq(sch, dst_dsq, p, enq_flags);
 }
 
 /**
@@ -2370,7 +2418,7 @@ static struct rq *move_task_between_dsqs(struct scx_sched *sch,
 		/* @p is going from a non-local DSQ to a local DSQ */
 		if (src_rq == dst_rq) {
 			task_unlink_from_dsq(p, src_dsq);
-			move_local_task_to_local_dsq(p, enq_flags,
+			move_local_task_to_local_dsq(sch, p, enq_flags,
 						     src_dsq, dst_rq);
 			raw_spin_unlock(&src_dsq->lock);
 		} else {
@@ -2423,7 +2471,7 @@ static bool consume_dispatch_q(struct scx_sched *sch, struct rq *rq,
 
 		if (rq == task_rq) {
 			task_unlink_from_dsq(p, dsq);
-			move_local_task_to_local_dsq(p, enq_flags, dsq, rq);
+			move_local_task_to_local_dsq(sch, p, enq_flags, dsq, rq);
 			raw_spin_unlock(&dsq->lock);
 			return true;
 		}
@@ -3183,7 +3231,7 @@ bool scx_prio_less(const struct task_struct *a, const struct task_struct *b,
 	if (sch_a == sch_b && SCX_HAS_OP(sch_a, core_sched_before) &&
 	    !scx_bypassing(sch_a, task_cpu(a)))
 		return SCX_CALL_OP_2TASKS_RET(sch_a, core_sched_before,
-					      NULL,
+					      task_rq(a),
 					      (struct task_struct *)a,
 					      (struct task_struct *)b);
 	else
@@ -3631,6 +3679,22 @@ static void __scx_disable_and_exit_task(struct scx_sched *sch,
 		SCX_CALL_OP_TASK(sch, exit_task, task_rq(p), p, &args);
 }
 
+/*
+ * Undo a completed __scx_init_task(sch, p, false) when scx_enable_task() never
+ * ran. The task state has not been transitioned, so this mirrors the
+ * SCX_TASK_INIT branch in __scx_disable_and_exit_task().
+ */
+static void scx_sub_init_cancel_task(struct scx_sched *sch, struct task_struct *p)
+{
+	struct scx_exit_task_args args = { .cancelled = true };
+
+	lockdep_assert_held(&p->pi_lock);
+	lockdep_assert_rq_held(task_rq(p));
+
+	if (SCX_HAS_OP(sch, exit_task))
+		SCX_CALL_OP_TASK(sch, exit_task, task_rq(p), p, &args);
+}
+
 static void scx_disable_and_exit_task(struct scx_sched *sch,
 				      struct task_struct *p)
 {
@@ -3639,11 +3703,12 @@ static void scx_disable_and_exit_task(struct scx_sched *sch,
 	/*
 	 * If set, @p exited between __scx_init_task() and scx_enable_task() in
 	 * scx_sub_enable() and is initialized for both the associated sched and
-	 * its parent. Disable and exit for the child too.
+	 * its parent. Exit for the child too - scx_enable_task() never ran for
+	 * it, so undo only init_task.
 	 */
-	if ((p->scx.flags & SCX_TASK_SUB_INIT) &&
-	    !WARN_ON_ONCE(!scx_enabling_sub_sched)) {
-		__scx_disable_and_exit_task(scx_enabling_sub_sched, p);
+	if (p->scx.flags & SCX_TASK_SUB_INIT) {
+		if (!WARN_ON_ONCE(!scx_enabling_sub_sched))
+			scx_sub_init_cancel_task(scx_enabling_sub_sched, p);
 		p->scx.flags &= ~SCX_TASK_SUB_INIT;
 	}
 
@@ -3664,6 +3729,33 @@ void init_scx_entity(struct sched_ext_entity *scx)
 	scx->slice = SCX_SLICE_DFL;
 }
 
+/* See scx_tid_alloc / scx_tid_cursor. */
+static u64 scx_alloc_tid(void)
+{
+	struct scx_tid_alloc *ta;
+
+	guard(preempt)();
+	ta = this_cpu_ptr(&scx_tid_alloc);
+
+	if (unlikely(ta->next >= ta->end)) {
+		ta->next = atomic64_fetch_add(SCX_TID_CHUNK, &scx_tid_cursor);
+		ta->end = ta->next + SCX_TID_CHUNK;
+	}
+	return ta->next++;
+}
+
+static void scx_tid_hash_insert(struct task_struct *p)
+{
+	int ret;
+
+	lockdep_assert_held(&scx_tasks_lock);
+
+	ret = rhashtable_lookup_insert_fast(&scx_tid_hash,
+					    &p->scx.tid_hash_node,
+					    scx_tid_hash_params);
+	WARN_ON_ONCE(ret);
+}
+
 void scx_pre_fork(struct task_struct *p)
 {
 	/*
@@ -3681,6 +3773,8 @@ int scx_fork(struct task_struct *p, struct kernel_clone_args *kargs)
 
 	percpu_rwsem_assert_held(&scx_fork_rwsem);
 
+	p->scx.tid = scx_alloc_tid();
+
 	if (scx_init_task_enabled) {
 #ifdef CONFIG_EXT_SUB_SCHED
 		struct scx_sched *sch = kargs->cset->dfl_cgrp->scx_sched;
@@ -3716,9 +3810,11 @@ void scx_post_fork(struct task_struct *p)
 		}
 	}
 
-	raw_spin_lock_irq(&scx_tasks_lock);
-	list_add_tail(&p->scx.tasks_node, &scx_tasks);
-	raw_spin_unlock_irq(&scx_tasks_lock);
+	scoped_guard(raw_spinlock_irq, &scx_tasks_lock) {
+		list_add_tail(&p->scx.tasks_node, &scx_tasks);
+		if (scx_tid_to_task_enabled())
+			scx_tid_hash_insert(p);
+	}
 
 	percpu_up_read(&scx_fork_rwsem);
 }
@@ -3769,17 +3865,19 @@ static bool task_dead_and_done(struct task_struct *p)
 
 void sched_ext_dead(struct task_struct *p)
 {
-	unsigned long flags;
-
 	/*
 	 * By the time control reaches here, @p has %TASK_DEAD set, switched out
 	 * for the last time and then dropped the rq lock - task_dead_and_done()
 	 * should be returning %true nullifying the straggling sched_class ops.
 	 * Remove from scx_tasks and exit @p.
 	 */
-	raw_spin_lock_irqsave(&scx_tasks_lock, flags);
-	list_del_init(&p->scx.tasks_node);
-	raw_spin_unlock_irqrestore(&scx_tasks_lock, flags);
+	scoped_guard(raw_spinlock_irqsave, &scx_tasks_lock) {
+		list_del_init(&p->scx.tasks_node);
+		if (scx_tid_to_task_enabled())
+			rhashtable_remove_fast(&scx_tid_hash,
+					       &p->scx.tid_hash_node,
+					       scx_tid_hash_params);
+	}
 
 	/*
 	 * @p is off scx_tasks and wholly ours. scx_root_enable()'s READY ->
@@ -4324,9 +4422,10 @@ void scx_cgroup_cancel_attach(struct cgroup_taskset *tset)
 
 void scx_group_set_weight(struct task_group *tg, unsigned long weight)
 {
-	struct scx_sched *sch = scx_root;
+	struct scx_sched *sch;
 
 	percpu_down_read(&scx_cgroup_ops_rwsem);
+	sch = scx_root;
 
 	if (scx_cgroup_enabled && SCX_HAS_OP(sch, cgroup_set_weight) &&
 	    tg->scx.weight != weight)
@@ -4339,9 +4438,10 @@ void scx_group_set_weight(struct task_group *tg, unsigned long weight)
 
 void scx_group_set_idle(struct task_group *tg, bool idle)
 {
-	struct scx_sched *sch = scx_root;
+	struct scx_sched *sch;
 
 	percpu_down_read(&scx_cgroup_ops_rwsem);
+	sch = scx_root;
 
 	if (scx_cgroup_enabled && SCX_HAS_OP(sch, cgroup_set_idle))
 		SCX_CALL_OP(sch, cgroup_set_idle, NULL, tg_cgrp(tg), idle);
@@ -4355,9 +4455,10 @@ void scx_group_set_idle(struct task_group *tg, bool idle)
 void scx_group_set_bandwidth(struct task_group *tg,
 			     u64 period_us, u64 quota_us, u64 burst_us)
 {
-	struct scx_sched *sch = scx_root;
+	struct scx_sched *sch;
 
 	percpu_down_read(&scx_cgroup_ops_rwsem);
+	sch = scx_root;
 
 	if (scx_cgroup_enabled && SCX_HAS_OP(sch, cgroup_set_bandwidth) &&
 	    (tg->scx.bw_period_us != period_us ||
@@ -4380,21 +4481,6 @@ static struct cgroup *root_cgroup(void)
 	return &cgrp_dfl_root.cgrp;
 }
 
-static struct cgroup *sch_cgroup(struct scx_sched *sch)
-{
-	return sch->cgrp;
-}
-
-/* for each descendant of @cgrp including self, set ->scx_sched to @sch */
-static void set_cgroup_sched(struct cgroup *cgrp, struct scx_sched *sch)
-{
-	struct cgroup *pos;
-	struct cgroup_subsys_state *css;
-
-	cgroup_for_each_live_descendant_pre(pos, css, cgrp)
-		rcu_assign_pointer(pos->scx_sched, sch);
-}
-
 static void scx_cgroup_lock(void)
 {
 #ifdef CONFIG_EXT_GROUP_SCHED
@@ -4412,12 +4498,30 @@ static void scx_cgroup_unlock(void)
 }
 #else	/* CONFIG_EXT_GROUP_SCHED || CONFIG_EXT_SUB_SCHED */
 static struct cgroup *root_cgroup(void) { return NULL; }
-static struct cgroup *sch_cgroup(struct scx_sched *sch) { return NULL; }
-static void set_cgroup_sched(struct cgroup *cgrp, struct scx_sched *sch) {}
 static void scx_cgroup_lock(void) {}
 static void scx_cgroup_unlock(void) {}
 #endif	/* CONFIG_EXT_GROUP_SCHED || CONFIG_EXT_SUB_SCHED */
 
+#ifdef CONFIG_EXT_SUB_SCHED
+static struct cgroup *sch_cgroup(struct scx_sched *sch)
+{
+	return sch->cgrp;
+}
+
+/* for each descendant of @cgrp including self, set ->scx_sched to @sch */
+static void set_cgroup_sched(struct cgroup *cgrp, struct scx_sched *sch)
+{
+	struct cgroup *pos;
+	struct cgroup_subsys_state *css;
+
+	cgroup_for_each_live_descendant_pre(pos, css, cgrp)
+		rcu_assign_pointer(pos->scx_sched, sch);
+}
+#else	/* CONFIG_EXT_SUB_SCHED */
+static struct cgroup *sch_cgroup(struct scx_sched *sch) { return NULL; }
+static void set_cgroup_sched(struct cgroup *cgrp, struct scx_sched *sch) {}
+#endif	/* CONFIG_EXT_SUB_SCHED */
+
 /*
  * Omitted operations:
  *
@@ -4712,6 +4816,8 @@ static void scx_sched_free_rcu_work(struct work_struct *work)
 	irq_work_sync(&sch->disable_irq_work);
 	kthread_destroy_worker(sch->helper);
 	timer_shutdown_sync(&sch->bypass_lb_timer);
+	free_cpumask_var(sch->bypass_lb_donee_cpumask);
+	free_cpumask_var(sch->bypass_lb_resched_cpumask);
 
 #ifdef CONFIG_EXT_SUB_SCHED
 	kfree(sch->cgrp_path);
@@ -4938,6 +5044,25 @@ void scx_softlockup(u32 dur_s)
 			smp_processor_id(), dur_s);
 }
 
+/*
+ * scx_hardlockup() runs from NMI and eventually calls scx_claim_exit(),
+ * which takes scx_sched_lock. scx_sched_lock isn't NMI-safe and grabbing
+ * it from NMI context can lead to deadlocks. Defer via irq_work; the
+ * disable path runs off irq_work anyway.
+ */
+static atomic_t scx_hardlockup_cpu = ATOMIC_INIT(-1);
+
+static void scx_hardlockup_irq_workfn(struct irq_work *work)
+{
+	int cpu = atomic_xchg(&scx_hardlockup_cpu, -1);
+
+	if (cpu >= 0 && handle_lockup("hard lockup - CPU %d", cpu))
+		printk_deferred(KERN_ERR "sched_ext: Hard lockup - CPU %d, disabling BPF scheduler\n",
+				cpu);
+}
+
+static DEFINE_IRQ_WORK(scx_hardlockup_irq_work, scx_hardlockup_irq_workfn);
+
 /**
  * scx_hardlockup - sched_ext hardlockup handler
  *
@@ -4946,17 +5071,19 @@ void scx_softlockup(u32 dur_s)
  * Try kicking out the current scheduler in an attempt to recover the system to
  * a good state before taking more drastic actions.
  *
- * Returns %true if sched_ext is enabled and abort was initiated, which may
- * resolve the reported hardlockup. %false if sched_ext is not enabled or
- * someone else already initiated abort.
+ * Queues an irq_work; the handle_lockup() call happens in IRQ context (see
+ * scx_hardlockup_irq_workfn).
+ *
+ * Returns %true if sched_ext is enabled and the work was queued, %false
+ * otherwise.
  */
 bool scx_hardlockup(int cpu)
 {
-	if (!handle_lockup("hard lockup - CPU %d", cpu))
+	if (!rcu_access_pointer(scx_root))
 		return false;
 
-	printk_deferred(KERN_ERR "sched_ext: Hard lockup - CPU %d, disabling BPF scheduler\n",
-			cpu);
+	atomic_cmpxchg(&scx_hardlockup_cpu, -1, cpu);
+	irq_work_queue(&scx_hardlockup_irq_work);
 	return true;
 }
 
@@ -5000,6 +5127,15 @@ static u32 bypass_lb_cpu(struct scx_sched *sch, s32 donor,
 		if (cpumask_empty(donee_mask))
 			break;
 
+		/*
+		 * If an earlier pass placed @p on @donor_dsq from a different
+		 * CPU and the donee hasn't consumed it yet, @p is still on the
+		 * previous CPU and task_rq(@p) != @donor_rq. @p can't be moved
+		 * without its rq locked. Skip.
+		 */
+		if (task_rq(p) != donor_rq)
+			continue;
+
 		donee = cpumask_any_and_distribute(donee_mask, p->cpus_ptr);
 		if (donee >= nr_cpu_ids)
 			continue;
@@ -5058,8 +5194,8 @@ static u32 bypass_lb_cpu(struct scx_sched *sch, s32 donor,
 static void bypass_lb_node(struct scx_sched *sch, int node)
 {
 	const struct cpumask *node_mask = cpumask_of_node(node);
-	struct cpumask *donee_mask = scx_bypass_lb_donee_cpumask;
-	struct cpumask *resched_mask = scx_bypass_lb_resched_cpumask;
+	struct cpumask *donee_mask = sch->bypass_lb_donee_cpumask;
+	struct cpumask *resched_mask = sch->bypass_lb_resched_cpumask;
 	u32 nr_tasks = 0, nr_cpus = 0, nr_balanced = 0;
 	u32 nr_target, nr_donor_target;
 	u32 before_min = U32_MAX, before_max = 0;
@@ -5526,6 +5662,26 @@ static void scx_disable_dump(struct scx_sched *sch)
 	sch->dump_disabled = true;
 }
 
+static void scx_log_sched_disable(struct scx_sched *sch)
+{
+	struct scx_exit_info *ei = sch->exit_info;
+	const char *type = scx_parent(sch) ? "sub-scheduler" : "scheduler";
+
+	if (ei->kind >= SCX_EXIT_ERROR) {
+		pr_err("sched_ext: BPF %s \"%s\" disabled (%s)\n", type,
+		       sch->ops.name, ei->reason);
+
+		if (ei->msg[0] != '\0')
+			pr_err("sched_ext: %s: %s\n", sch->ops.name, ei->msg);
+#ifdef CONFIG_STACKTRACE
+		stack_trace_print(ei->bt, ei->bt_len, 2);
+#endif
+	} else {
+		pr_info("sched_ext: BPF %s \"%s\" disabled (%s)\n", type,
+			sch->ops.name, ei->reason);
+	}
+}
+
 #ifdef CONFIG_EXT_SUB_SCHED
 static DECLARE_WAIT_QUEUE_HEAD(scx_unlink_waitq);
 
@@ -5696,8 +5852,12 @@ static void scx_sub_disable(struct scx_sched *sch)
 			    &sub_detach_args);
 	}
 
+	scx_log_sched_disable(sch);
+
 	if (sch->ops.exit)
 		SCX_CALL_OP(sch, exit, NULL, sch->exit_info);
+	if (sch->sub_kset)
+		kset_unregister(sch->sub_kset);
 	kobject_del(&sch->kobj);
 }
 #else	/* CONFIG_EXT_SUB_SCHED */
@@ -5707,7 +5867,6 @@ static void scx_sub_disable(struct scx_sched *sch) { }
 
 static void scx_root_disable(struct scx_sched *sch)
 {
-	struct scx_exit_info *ei = sch->exit_info;
 	struct scx_task_iter sti;
 	struct task_struct *p;
 	int cpu;
@@ -5793,26 +5952,18 @@ static void scx_root_disable(struct scx_sched *sch)
 
 	/* no task is on scx, turn off all the switches and flush in-progress calls */
 	static_branch_disable(&__scx_enabled);
+	if (sch->ops.flags & SCX_OPS_TID_TO_TASK)
+		static_branch_disable(&__scx_tid_to_task_enabled);
 	bitmap_zero(sch->has_op, SCX_OPI_END);
 	scx_idle_disable();
 	synchronize_rcu();
+	if (sch->ops.flags & SCX_OPS_TID_TO_TASK)
+		rhashtable_free_and_destroy(&scx_tid_hash, NULL, NULL);
 
-	if (ei->kind >= SCX_EXIT_ERROR) {
-		pr_err("sched_ext: BPF scheduler \"%s\" disabled (%s)\n",
-		       sch->ops.name, ei->reason);
-
-		if (ei->msg[0] != '\0')
-			pr_err("sched_ext: %s: %s\n", sch->ops.name, ei->msg);
-#ifdef CONFIG_STACKTRACE
-		stack_trace_print(ei->bt, ei->bt_len, 2);
-#endif
-	} else {
-		pr_info("sched_ext: BPF scheduler \"%s\" disabled (%s)\n",
-			sch->ops.name, ei->reason);
-	}
+	scx_log_sched_disable(sch);
 
 	if (sch->ops.exit)
-		SCX_CALL_OP(sch, exit, NULL, ei);
+		SCX_CALL_OP(sch, exit, NULL, sch->exit_info);
 
 	scx_unlink_sched(sch);
 
@@ -5829,6 +5980,10 @@ static void scx_root_disable(struct scx_sched *sch)
 	 * could observe an object of the same name still in the hierarchy when
 	 * the next scheduler is loaded.
 	 */
+#ifdef CONFIG_EXT_SUB_SCHED
+	if (sch->sub_kset)
+		kset_unregister(sch->sub_kset);
+#endif
 	kobject_del(&sch->kobj);
 
 	free_kick_syncs();
@@ -5921,6 +6076,20 @@ static void scx_disable(struct scx_sched *sch, enum scx_exit_kind kind)
 		irq_work_queue(&sch->disable_irq_work);
 }
 
+/**
+ * scx_flush_disable_work - flush the disable work and wait for it to finish
+ * @sch: the scheduler
+ *
+ * sch->disable_work might still not queued, causing kthread_flush_work()
+ * as a noop. Syncing the irq_work first is required to guarantee the
+ * kthread work has been queued before waiting for it.
+ */
+static void scx_flush_disable_work(struct scx_sched *sch)
+{
+	irq_work_sync(&sch->disable_irq_work);
+	kthread_flush_work(&sch->disable_work);
+}
+
 static void dump_newline(struct seq_buf *s)
 {
 	trace_sched_ext_dump("");
@@ -6032,9 +6201,8 @@ static void ops_dump_exit(void)
 	scx_dump_data.cpu = -1;
 }
 
-static void scx_dump_task(struct scx_sched *sch,
-			  struct seq_buf *s, struct scx_dump_ctx *dctx,
-			  struct task_struct *p, char marker)
+static void scx_dump_task(struct scx_sched *sch, struct seq_buf *s, struct scx_dump_ctx *dctx,
+			  struct rq *rq, struct task_struct *p, char marker)
 {
 	static unsigned long bt[SCX_EXIT_BT_LEN];
 	struct scx_sched *task_sch = scx_task_sched(p);
@@ -6075,7 +6243,7 @@ static void scx_dump_task(struct scx_sched *sch,
 
 	if (SCX_HAS_OP(sch, dump_task)) {
 		ops_dump_init(s, "    ");
-		SCX_CALL_OP(sch, dump_task, NULL, dctx, p);
+		SCX_CALL_OP(sch, dump_task, rq, dctx, p);
 		ops_dump_exit();
 	}
 
@@ -6199,8 +6367,7 @@ static void scx_dump_state(struct scx_sched *sch, struct scx_exit_info *ei,
 		used = seq_buf_used(&ns);
 		if (SCX_HAS_OP(sch, dump_cpu)) {
 			ops_dump_init(&ns, "  ");
-			SCX_CALL_OP(sch, dump_cpu, NULL,
-				    &dctx, cpu, idle);
+			SCX_CALL_OP(sch, dump_cpu, rq, &dctx, cpu, idle);
 			ops_dump_exit();
 		}
 
@@ -6223,11 +6390,11 @@ static void scx_dump_state(struct scx_sched *sch, struct scx_exit_info *ei,
 
 		if (rq->curr->sched_class == &ext_sched_class &&
 		    (dump_all_tasks || scx_task_on_sched(sch, rq->curr)))
-			scx_dump_task(sch, &s, &dctx, rq->curr, '*');
+			scx_dump_task(sch, &s, &dctx, rq, rq->curr, '*');
 
 		list_for_each_entry(p, &rq->scx.runnable_list, scx.runnable_node)
 			if (dump_all_tasks || scx_task_on_sched(sch, p))
-				scx_dump_task(sch, &s, &dctx, p, ' ');
+				scx_dump_task(sch, &s, &dctx, rq, p, ' ');
 	next:
 		rq_unlock_irqrestore(rq, &rf);
 	}
@@ -6437,6 +6604,15 @@ static struct scx_sched *scx_alloc_and_add_sched(struct sched_ext_ops *ops,
 	init_irq_work(&sch->disable_irq_work, scx_disable_irq_workfn);
 	kthread_init_work(&sch->disable_work, scx_disable_workfn);
 	timer_setup(&sch->bypass_lb_timer, scx_bypass_lb_timerfn, 0);
+
+	if (!alloc_cpumask_var(&sch->bypass_lb_donee_cpumask, GFP_KERNEL)) {
+		ret = -ENOMEM;
+		goto err_stop_helper;
+	}
+	if (!alloc_cpumask_var(&sch->bypass_lb_resched_cpumask, GFP_KERNEL)) {
+		ret = -ENOMEM;
+		goto err_free_lb_cpumask;
+	}
 	sch->ops = *ops;
 	rcu_assign_pointer(ops->priv, sch);
 
@@ -6446,14 +6622,14 @@ static struct scx_sched *scx_alloc_and_add_sched(struct sched_ext_ops *ops,
 	char *buf = kzalloc(PATH_MAX, GFP_KERNEL);
 	if (!buf) {
 		ret = -ENOMEM;
-		goto err_stop_helper;
+		goto err_free_lb_resched;
 	}
 	cgroup_path(cgrp, buf, PATH_MAX);
 	sch->cgrp_path = kstrdup(buf, GFP_KERNEL);
 	kfree(buf);
 	if (!sch->cgrp_path) {
 		ret = -ENOMEM;
-		goto err_stop_helper;
+		goto err_free_lb_resched;
 	}
 
 	sch->cgrp = cgrp;
@@ -6488,10 +6664,12 @@ static struct scx_sched *scx_alloc_and_add_sched(struct sched_ext_ops *ops,
 #endif	/* CONFIG_EXT_SUB_SCHED */
 	return sch;
 
-#ifdef CONFIG_EXT_SUB_SCHED
+err_free_lb_resched:
+	free_cpumask_var(sch->bypass_lb_resched_cpumask);
+err_free_lb_cpumask:
+	free_cpumask_var(sch->bypass_lb_donee_cpumask);
 err_stop_helper:
 	kthread_destroy_worker(sch->helper);
-#endif
 err_free_pcpu:
 	for_each_possible_cpu(cpu) {
 		if (cpu == bypass_fail_cpu)
@@ -6510,7 +6688,7 @@ static struct scx_sched *scx_alloc_and_add_sched(struct sched_ext_ops *ops,
 err_free_sch:
 	kfree(sch);
 err_put_cgrp:
-#if defined(CONFIG_EXT_GROUP_SCHED) || defined(CONFIG_EXT_SUB_SCHED)
+#ifdef CONFIG_EXT_SUB_SCHED
 	cgroup_put(cgrp);
 #endif
 	return ERR_PTR(ret);
@@ -6551,6 +6729,17 @@ static int validate_ops(struct scx_sched *sch, const struct sched_ext_ops *ops)
 		return -EINVAL;
 	}
 
+	/*
+	 * SCX_OPS_TID_TO_TASK is enabled by the root scheduler. A sub-sched
+	 * may set it to declare a dependency; reject if the root hasn't
+	 * enabled it.
+	 */
+	if ((ops->flags & SCX_OPS_TID_TO_TASK) && scx_parent(sch) &&
+	    !(scx_root->ops.flags & SCX_OPS_TID_TO_TASK)) {
+		scx_error(sch, "SCX_OPS_TID_TO_TASK requires root scheduler to enable it");
+		return -EINVAL;
+	}
+
 	/*
 	 * SCX_OPS_BUILTIN_IDLE_PER_NODE requires built-in CPU idle
 	 * selection policy to be enabled.
@@ -6601,13 +6790,19 @@ static void scx_root_enable_workfn(struct kthread_work *work)
 	if (ret)
 		goto err_unlock;
 
-#if defined(CONFIG_EXT_GROUP_SCHED) || defined(CONFIG_EXT_SUB_SCHED)
+	if (ops->flags & SCX_OPS_TID_TO_TASK) {
+		ret = rhashtable_init(&scx_tid_hash, &scx_tid_hash_params);
+		if (ret)
+			goto err_free_ksyncs;
+	}
+
+#ifdef CONFIG_EXT_SUB_SCHED
 	cgroup_get(cgrp);
 #endif
 	sch = scx_alloc_and_add_sched(ops, cgrp, NULL);
 	if (IS_ERR(sch)) {
 		ret = PTR_ERR(sch);
-		goto err_free_ksyncs;
+		goto err_free_tid_hash;
 	}
 
 	/*
@@ -6639,8 +6834,10 @@ static void scx_root_enable_workfn(struct kthread_work *work)
 	rcu_assign_pointer(scx_root, sch);
 
 	ret = scx_link_sched(sch);
-	if (ret)
+	if (ret) {
+		cpus_read_unlock();
 		goto err_disable;
+	}
 
 	scx_idle_enable(ops);
 
@@ -6696,6 +6893,10 @@ static void scx_root_enable_workfn(struct kthread_work *work)
 	WARN_ON_ONCE(scx_init_task_enabled);
 	scx_init_task_enabled = true;
 
+	/* flip under fork_rwsem; the iter below covers existing tasks */
+	if (ops->flags & SCX_OPS_TID_TO_TASK)
+		static_branch_enable(&__scx_tid_to_task_enabled);
+
 	/*
 	 * Enable ops for every task. Fork is excluded by scx_fork_rwsem
 	 * preventing new tasks from being added. No need to exclude tasks
@@ -6739,6 +6940,17 @@ static void scx_root_enable_workfn(struct kthread_work *work)
 		scx_set_task_sched(p, sch);
 		scx_set_task_state(p, SCX_TASK_READY);
 
+		/*
+		 * Insert into the tid hash under scx_tasks_lock so we can't
+		 * race sched_ext_dead() and leave a stale entry for an already
+		 * exited task.
+		 */
+		if (scx_tid_to_task_enabled()) {
+			guard(raw_spinlock_irq)(&scx_tasks_lock);
+			if (!list_empty(&p->scx.tasks_node))
+				scx_tid_hash_insert(p);
+		}
+
 		put_task_struct(p);
 	}
 	scx_task_iter_stop(&sti);
@@ -6798,6 +7010,9 @@ static void scx_root_enable_workfn(struct kthread_work *work)
 	cmd->ret = 0;
 	return;
 
+err_free_tid_hash:
+	if (ops->flags & SCX_OPS_TID_TO_TASK)
+		rhashtable_free_and_destroy(&scx_tid_hash, NULL, NULL);
 err_free_ksyncs:
 	free_kick_syncs();
 err_unlock:
@@ -6821,7 +7036,7 @@ static void scx_root_enable_workfn(struct kthread_work *work)
 	 * completion. sch's base reference will be put by bpf_scx_unreg().
 	 */
 	scx_error(sch, "scx_root_enable() failed (%d)", ret);
-	kthread_flush_work(&sch->disable_work);
+	scx_flush_disable_work(sch);
 	cmd->ret = 0;
 }
 
@@ -7072,23 +7287,30 @@ static void scx_sub_enable_workfn(struct kthread_work *work)
 abort:
 	put_task_struct(p);
 	scx_task_iter_stop(&sti);
-	scx_enabling_sub_sched = NULL;
 
+	/*
+	 * Undo __scx_init_task() for tasks we marked. scx_enable_task() never
+	 * ran for @sch on them, so calling scx_disable_task() here would invoke
+	 * ops.disable() without a matching ops.enable(). scx_enabling_sub_sched
+	 * must stay set until SUB_INIT is cleared from every marked task -
+	 * scx_disable_and_exit_task() reads it when a task exits concurrently.
+	 */
 	scx_task_iter_start(&sti, sch->cgrp);
 	while ((p = scx_task_iter_next_locked(&sti))) {
 		if (p->scx.flags & SCX_TASK_SUB_INIT) {
-			__scx_disable_and_exit_task(sch, p);
+			scx_sub_init_cancel_task(sch, p);
 			p->scx.flags &= ~SCX_TASK_SUB_INIT;
 		}
 	}
 	scx_task_iter_stop(&sti);
+	scx_enabling_sub_sched = NULL;
 err_unlock_and_disable:
 	/* we'll soon enter disable path, keep bypass on */
 	scx_cgroup_unlock();
 	percpu_up_write(&scx_fork_rwsem);
 err_disable:
 	mutex_unlock(&scx_enable_mutex);
-	kthread_flush_work(&sch->disable_work);
+	scx_flush_disable_work(sch);
 	cmd->ret = 0;
 }
 
@@ -7349,7 +7571,7 @@ static void bpf_scx_unreg(void *kdata, struct bpf_link *link)
 	struct scx_sched *sch = rcu_dereference_protected(ops->priv, true);
 
 	scx_disable(sch, SCX_EXIT_UNREG);
-	kthread_flush_work(&sch->disable_work);
+	scx_flush_disable_work(sch);
 	RCU_INIT_POINTER(ops->priv, NULL);
 	kobject_put(&sch->kobj);
 }
@@ -8033,12 +8255,22 @@ static bool scx_dsq_move(struct bpf_iter_scx_dsq_kern *kit,
 			 struct task_struct *p, u64 dsq_id, u64 enq_flags)
 {
 	struct scx_dispatch_q *src_dsq = kit->dsq, *dst_dsq;
-	struct scx_sched *sch = src_dsq->sched;
+	struct scx_sched *sch;
 	struct rq *this_rq, *src_rq, *locked_rq;
 	bool dispatched = false;
 	bool in_balance;
 	unsigned long flags;
 
+	/*
+	 * The verifier considers an iterator slot initialized on any
+	 * KF_ITER_NEW return, so a BPF program may legally reach here after
+	 * bpf_iter_scx_dsq_new() failed and left @kit->dsq NULL.
+	 */
+	if (unlikely(!src_dsq))
+		return false;
+
+	sch = src_dsq->sched;
+
 	if (!scx_vet_enq_flags(sch, dsq_id, &enq_flags))
 		return false;
 
@@ -8526,7 +8758,7 @@ __bpf_kfunc bool scx_bpf_task_set_slice(struct task_struct *p, u64 slice,
 
 	guard(rcu)();
 	sch = scx_prog_sched(aux);
-	if (unlikely(!scx_task_on_sched(sch, p)))
+	if (unlikely(!sch || !scx_task_on_sched(sch, p)))
 		return false;
 
 	p->scx.slice = slice;
@@ -8549,7 +8781,7 @@ __bpf_kfunc bool scx_bpf_task_set_dsq_vtime(struct task_struct *p, u64 vtime,
 
 	guard(rcu)();
 	sch = scx_prog_sched(aux);
-	if (unlikely(!scx_task_on_sched(sch, p)))
+	if (unlikely(!sch || !scx_task_on_sched(sch, p)))
 		return false;
 
 	p->scx.dsq_vtime = vtime;
@@ -8633,11 +8865,12 @@ __bpf_kfunc void scx_bpf_kick_cpu(s32 cpu, u64 flags, const struct bpf_prog_aux
 /**
  * scx_bpf_dsq_nr_queued - Return the number of queued tasks
  * @dsq_id: id of the DSQ
+ * @aux: implicit BPF argument to access bpf_prog_aux hidden from BPF progs
  *
  * Return the number of tasks in the DSQ matching @dsq_id. If not found,
  * -%ENOENT is returned.
  */
-__bpf_kfunc s32 scx_bpf_dsq_nr_queued(u64 dsq_id)
+__bpf_kfunc s32 scx_bpf_dsq_nr_queued(u64 dsq_id, const struct bpf_prog_aux *aux)
 {
 	struct scx_sched *sch;
 	struct scx_dispatch_q *dsq;
@@ -8645,7 +8878,7 @@ __bpf_kfunc s32 scx_bpf_dsq_nr_queued(u64 dsq_id)
 
 	preempt_disable();
 
-	sch = rcu_dereference_sched(scx_root);
+	sch = scx_prog_sched(aux);
 	if (unlikely(!sch)) {
 		ret = -ENODEV;
 		goto out;
@@ -8677,21 +8910,21 @@ __bpf_kfunc s32 scx_bpf_dsq_nr_queued(u64 dsq_id)
 /**
  * scx_bpf_destroy_dsq - Destroy a custom DSQ
  * @dsq_id: DSQ to destroy
+ * @aux: implicit BPF argument to access bpf_prog_aux hidden from BPF progs
  *
  * Destroy the custom DSQ identified by @dsq_id. Only DSQs created with
  * scx_bpf_create_dsq() can be destroyed. The caller must ensure that the DSQ is
  * empty and no further tasks are dispatched to it. Ignored if called on a DSQ
  * which doesn't exist. Can be called from any online scx_ops operations.
  */
-__bpf_kfunc void scx_bpf_destroy_dsq(u64 dsq_id)
+__bpf_kfunc void scx_bpf_destroy_dsq(u64 dsq_id, const struct bpf_prog_aux *aux)
 {
 	struct scx_sched *sch;
 
-	rcu_read_lock();
-	sch = rcu_dereference(scx_root);
+	guard(rcu)();
+	sch = scx_prog_sched(aux);
 	if (sch)
 		destroy_dsq(sch, dsq_id);
-	rcu_read_unlock();
 }
 
 /**
@@ -9286,6 +9519,34 @@ __bpf_kfunc struct task_struct *scx_bpf_cpu_curr(s32 cpu, const struct bpf_prog_
 	return rcu_dereference(cpu_rq(cpu)->curr);
 }
 
+/**
+ * scx_bpf_tid_to_task - Look up a task by its scx tid
+ * @tid: task ID previously read from p->scx.tid
+ *
+ * Returns the task with the given tid, or NULL if no such task exists. The
+ * returned pointer is valid until the end of the current RCU read section
+ * (KF_RCU_PROTECTED). Requires SCX_OPS_TID_TO_TASK to be set on the root
+ * scheduler; otherwise an error is raised and NULL returned.
+ */
+__bpf_kfunc struct task_struct *scx_bpf_tid_to_task(u64 tid)
+{
+	struct sched_ext_entity *scx;
+
+	if (!scx_tid_to_task_enabled()) {
+		struct scx_sched *sch = rcu_dereference(scx_root);
+
+		if (sch)
+			scx_error(sch, "scx_bpf_tid_to_task() called without SCX_OPS_TID_TO_TASK");
+		return NULL;
+	}
+
+	scx = rhashtable_lookup(&scx_tid_hash, &tid, scx_tid_hash_params);
+	if (!scx)
+		return NULL;
+
+	return container_of(scx, struct task_struct, scx);
+}
+
 /**
  * scx_bpf_now - Returns a high-performance monotonically non-decreasing
  * clock for the current CPU. The clock returned is in nanoseconds.
@@ -9445,8 +9706,8 @@ BTF_KFUNCS_START(scx_kfunc_ids_any)
 BTF_ID_FLAGS(func, scx_bpf_task_set_slice, KF_IMPLICIT_ARGS | KF_RCU);
 BTF_ID_FLAGS(func, scx_bpf_task_set_dsq_vtime, KF_IMPLICIT_ARGS | KF_RCU);
 BTF_ID_FLAGS(func, scx_bpf_kick_cpu, KF_IMPLICIT_ARGS)
-BTF_ID_FLAGS(func, scx_bpf_dsq_nr_queued)
-BTF_ID_FLAGS(func, scx_bpf_destroy_dsq)
+BTF_ID_FLAGS(func, scx_bpf_dsq_nr_queued, KF_IMPLICIT_ARGS)
+BTF_ID_FLAGS(func, scx_bpf_destroy_dsq, KF_IMPLICIT_ARGS)
 BTF_ID_FLAGS(func, scx_bpf_dsq_peek, KF_IMPLICIT_ARGS | KF_RCU_PROTECTED | KF_RET_NULL)
 BTF_ID_FLAGS(func, scx_bpf_dsq_reenq, KF_IMPLICIT_ARGS)
 BTF_ID_FLAGS(func, scx_bpf_reenqueue_local___v2, KF_IMPLICIT_ARGS)
@@ -9469,6 +9730,7 @@ BTF_ID_FLAGS(func, scx_bpf_task_cpu, KF_RCU)
 BTF_ID_FLAGS(func, scx_bpf_cpu_rq, KF_IMPLICIT_ARGS)
 BTF_ID_FLAGS(func, scx_bpf_locked_rq, KF_IMPLICIT_ARGS | KF_RET_NULL)
 BTF_ID_FLAGS(func, scx_bpf_cpu_curr, KF_IMPLICIT_ARGS | KF_RET_NULL | KF_RCU_PROTECTED)
+BTF_ID_FLAGS(func, scx_bpf_tid_to_task, KF_RET_NULL | KF_RCU_PROTECTED)
 BTF_ID_FLAGS(func, scx_bpf_now)
 BTF_ID_FLAGS(func, scx_bpf_events)
 #ifdef CONFIG_CGROUP_SCHED
@@ -9479,6 +9741,7 @@ BTF_KFUNCS_END(scx_kfunc_ids_any)
 static const struct btf_kfunc_id_set scx_kfunc_set_any = {
 	.owner			= THIS_MODULE,
 	.set			= &scx_kfunc_ids_any,
+	.filter			= scx_kfunc_context_filter,
 };
 
 /*
@@ -9526,13 +9789,12 @@ static const u32 scx_kf_allow_flags[] = {
 };
 
 /*
- * Verifier-time filter for context-sensitive SCX kfuncs. Registered via the
- * .filter field on each per-group btf_kfunc_id_set. The BPF core invokes this
- * for every kfunc call in the registered hook (BPF_PROG_TYPE_STRUCT_OPS or
+ * Verifier-time filter for SCX kfuncs. Registered via the .filter field on
+ * each per-group btf_kfunc_id_set. The BPF core invokes this for every kfunc
+ * call in the registered hook (BPF_PROG_TYPE_STRUCT_OPS or
  * BPF_PROG_TYPE_SYSCALL), regardless of which set originally introduced the
- * kfunc - so the filter must short-circuit on kfuncs it doesn't govern (e.g.
- * scx_kfunc_ids_any) by falling through to "allow" when none of the
- * context-sensitive sets contain the kfunc.
+ * kfunc - so the filter must short-circuit on kfuncs it doesn't govern by
+ * falling through to "allow" when none of the SCX sets contain the kfunc.
  */
 int scx_kfunc_context_filter(const struct bpf_prog *prog, u32 kfunc_id)
 {
@@ -9541,18 +9803,21 @@ int scx_kfunc_context_filter(const struct bpf_prog *prog, u32 kfunc_id)
 	bool in_enqueue = btf_id_set8_contains(&scx_kfunc_ids_enqueue_dispatch, kfunc_id);
 	bool in_dispatch = btf_id_set8_contains(&scx_kfunc_ids_dispatch, kfunc_id);
 	bool in_cpu_release = btf_id_set8_contains(&scx_kfunc_ids_cpu_release, kfunc_id);
+	bool in_idle = btf_id_set8_contains(&scx_kfunc_ids_idle, kfunc_id);
+	bool in_any = btf_id_set8_contains(&scx_kfunc_ids_any, kfunc_id);
 	u32 moff, flags;
 
-	/* Not a context-sensitive kfunc (e.g. from scx_kfunc_ids_any) - allow. */
-	if (!(in_unlocked || in_select_cpu || in_enqueue || in_dispatch || in_cpu_release))
+	/* Not an SCX kfunc - allow. */
+	if (!(in_unlocked || in_select_cpu || in_enqueue || in_dispatch ||
+	      in_cpu_release || in_idle || in_any))
 		return 0;
 
 	/* SYSCALL progs (e.g. BPF test_run()) may call unlocked and select_cpu kfuncs. */
 	if (prog->type == BPF_PROG_TYPE_SYSCALL)
-		return (in_unlocked || in_select_cpu) ? 0 : -EACCES;
+		return (in_unlocked || in_select_cpu || in_idle || in_any) ? 0 : -EACCES;
 
 	if (prog->type != BPF_PROG_TYPE_STRUCT_OPS)
-		return -EACCES;
+		return (in_any || in_idle) ? 0 : -EACCES;
 
 	/*
 	 * add_subprog_and_kfunc() collects all kfunc calls, including dead code
@@ -9565,14 +9830,15 @@ int scx_kfunc_context_filter(const struct bpf_prog *prog, u32 kfunc_id)
 		return 0;
 
 	/*
-	 * Non-SCX struct_ops: only unlocked kfuncs are safe. The other
-	 * context-sensitive kfuncs assume the rq lock is held by the SCX
-	 * dispatch path, which doesn't apply to other struct_ops users.
+	 * Non-SCX struct_ops: SCX kfuncs are not permitted.
 	 */
 	if (prog->aux->st_ops != &bpf_sched_ext_ops)
-		return in_unlocked ? 0 : -EACCES;
+		return -EACCES;
 
 	/* SCX struct_ops: check the per-op allow list. */
+	if (in_any || in_idle)
+		return 0;
+
 	moff = prog->aux->attach_st_ops_member_off;
 	flags = scx_kf_allow_flags[SCX_MOFF_IDX(moff)];
 
@@ -9656,12 +9922,6 @@ static int __init scx_init(void)
 		return ret;
 	}
 
-	if (!alloc_cpumask_var(&scx_bypass_lb_donee_cpumask, GFP_KERNEL) ||
-	    !alloc_cpumask_var(&scx_bypass_lb_resched_cpumask, GFP_KERNEL)) {
-		pr_err("sched_ext: Failed to allocate cpumasks\n");
-		return -ENOMEM;
-	}
-
 	return 0;
 }
 __initcall(scx_init);
diff --git a/kernel/sched/ext_idle.c b/kernel/sched/ext_idle.c
index 443d12a3df67..7468560a6d80 100644
--- a/kernel/sched/ext_idle.c
+++ b/kernel/sched/ext_idle.c
@@ -927,14 +927,24 @@ static s32 select_cpu_from_kfunc(struct scx_sched *sch, struct task_struct *p,
 	 * Accessing p->cpus_ptr / p->nr_cpus_allowed needs either @p's rq
 	 * lock or @p's pi_lock. Three cases:
 	 *
-	 *  - inside ops.select_cpu(): try_to_wake_up() holds @p's pi_lock.
+	 *  - inside ops.select_cpu(): try_to_wake_up() holds the wake-up
+	 *    task's pi_lock; the wake-up task is recorded in kf_tasks[0]
+	 *    by SCX_CALL_OP_TASK_RET().
 	 *  - other rq-locked SCX op: scx_locked_rq() points at the held rq.
 	 *  - truly unlocked (UNLOCKED ops, SYSCALL, non-SCX struct_ops):
 	 *    nothing held, take pi_lock ourselves.
+	 *
+	 * In the first two cases, BPF schedulers may pass an arbitrary task
+	 * that the held lock doesn't cover. Refuse those.
 	 */
 	if (this_rq()->scx.in_select_cpu) {
+		if (!scx_kf_arg_task_ok(sch, p))
+			return -EINVAL;
 		lockdep_assert_held(&p->pi_lock);
-	} else if (!scx_locked_rq()) {
+	} else if (scx_locked_rq()) {
+		if (task_rq(p) != scx_locked_rq())
+			goto cross_task;
+	} else {
 		raw_spin_lock_irqsave(&p->pi_lock, irq_flags);
 		we_locked = true;
 	}
@@ -960,6 +970,11 @@ static s32 select_cpu_from_kfunc(struct scx_sched *sch, struct task_struct *p,
 		raw_spin_unlock_irqrestore(&p->pi_lock, irq_flags);
 
 	return cpu;
+
+cross_task:
+	scx_error(sch, "select_cpu kfunc called cross-task on %s[%d]",
+		  p->comm, p->pid);
+	return -EINVAL;
 }
 
 /**
@@ -1467,6 +1482,7 @@ BTF_KFUNCS_END(scx_kfunc_ids_idle)
 static const struct btf_kfunc_id_set scx_kfunc_set_idle = {
 	.owner			= THIS_MODULE,
 	.set			= &scx_kfunc_ids_idle,
+	.filter			= scx_kfunc_context_filter,
 };
 
 /*
diff --git a/kernel/sched/ext_idle.h b/kernel/sched/ext_idle.h
index dc35f850481e..8d169d3bbdf9 100644
--- a/kernel/sched/ext_idle.h
+++ b/kernel/sched/ext_idle.h
@@ -12,6 +12,7 @@
 
 struct sched_ext_ops;
 
+extern struct btf_id_set8 scx_kfunc_ids_idle;
 extern struct btf_id_set8 scx_kfunc_ids_select_cpu;
 
 void scx_idle_update_selcpu_topology(struct sched_ext_ops *ops);
diff --git a/kernel/sched/ext_internal.h b/kernel/sched/ext_internal.h
index 62ce4eaf6a3f..a54903bb74b3 100644
--- a/kernel/sched/ext_internal.h
+++ b/kernel/sched/ext_internal.h
@@ -13,6 +13,9 @@ enum scx_consts {
 	SCX_DSP_MAX_LOOPS		= 32,
 	SCX_WATCHDOG_MAX_TIMEOUT	= 30 * HZ,
 
+	/* per-CPU chunk size for p->scx.tid allocation, see scx_alloc_tid() */
+	SCX_TID_CHUNK			= 1024,
+
 	SCX_EXIT_BT_LEN			= 64,
 	SCX_EXIT_MSG_LEN		= 1024,
 	SCX_EXIT_DUMP_DFL_LEN		= 32768,
@@ -138,7 +141,8 @@ enum scx_ops_flags {
 	 * To mask this problem, by default, unhashed tasks are automatically
 	 * dispatched to the local DSQ on enqueue. If the BPF scheduler doesn't
 	 * depend on pid lookups and wants to handle these tasks directly, the
-	 * following flag can be used.
+	 * following flag can be used. With %SCX_OPS_TID_TO_TASK,
+	 * scx_bpf_tid_to_task() can find exiting tasks reliably.
 	 */
 	SCX_OPS_ENQ_EXITING		= 1LLU << 2,
 
@@ -189,6 +193,17 @@ enum scx_ops_flags {
 	 */
 	SCX_OPS_ALWAYS_ENQ_IMMED	= 1LLU << 7,
 
+	/*
+	 * Maintain a mapping from p->scx.tid to task_struct so the BPF
+	 * scheduler can recover task pointers from stored tids via
+	 * scx_bpf_tid_to_task().
+	 *
+	 * Only the root scheduler turns this on. A sub-sched may set the flag
+	 * to declare a dependency on the lookup; if the root scheduler hasn't
+	 * enabled it, attaching the sub-sched is rejected.
+	 */
+	SCX_OPS_TID_TO_TASK		= 1LLU << 8,
+
 	SCX_OPS_ALL_FLAGS		= SCX_OPS_KEEP_BUILTIN_IDLE |
 					  SCX_OPS_ENQ_LAST |
 					  SCX_OPS_ENQ_EXITING |
@@ -196,7 +211,8 @@ enum scx_ops_flags {
 					  SCX_OPS_ALLOW_QUEUED_WAKEUP |
 					  SCX_OPS_SWITCH_PARTIAL |
 					  SCX_OPS_BUILTIN_IDLE_PER_NODE |
-					  SCX_OPS_ALWAYS_ENQ_IMMED,
+					  SCX_OPS_ALWAYS_ENQ_IMMED |
+					  SCX_OPS_TID_TO_TASK,
 
 	/* high 8 bits are internal, don't include in SCX_OPS_ALL_FLAGS */
 	__SCX_OPS_INTERNAL_MASK		= 0xffLLU << 56,
@@ -1075,6 +1091,8 @@ struct scx_sched {
 	struct irq_work		disable_irq_work;
 	struct kthread_work	disable_work;
 	struct timer_list	bypass_lb_timer;
+	cpumask_var_t		bypass_lb_donee_cpumask;
+	cpumask_var_t		bypass_lb_resched_cpumask;
 	struct rcu_work		rcu_work;
 
 	/* all ancestors including self */
diff --git a/kernel/softirq.c b/kernel/softirq.c
index 4425d8dce44b..a3bd54de8259 100644
--- a/kernel/softirq.c
+++ b/kernel/softirq.c
@@ -576,6 +576,10 @@ static inline bool lockdep_softirq_start(void) { return false; }
 static inline void lockdep_softirq_end(bool in_hardirq) { }
 #endif
 
+#ifdef CONFIG_NET_DEV_REFCNT_TRACKER
+static noinline void handle_softirqs(bool ksirqd);
+#endif
+
 static void handle_softirqs(bool ksirqd)
 {
 	unsigned long end = jiffies + MAX_SOFTIRQ_TIME;
diff --git a/kernel/taskstats.c b/kernel/taskstats.c
index 73bd6a6a7893..2cd0172d0516 100644
--- a/kernel/taskstats.c
+++ b/kernel/taskstats.c
@@ -210,13 +210,39 @@ static int fill_stats_for_pid(pid_t pid, struct taskstats *stats)
 	return 0;
 }
 
+static void tgid_stats_add_task(struct taskstats *stats,
+				struct task_struct *tsk, u64 now_ns)
+{
+	u64 delta, utime, stime;
+
+	/*
+	 * Each accounting subsystem calls its functions here to
+	 * accumulate its per-task stats for tsk, into the per-tgid structure
+	 *
+	 *	per-task-foo(stats, tsk);
+	 */
+	delayacct_add_tsk(stats, tsk);
+
+	/* calculate task elapsed time in nsec */
+	delta = now_ns - tsk->start_time;
+	/* Convert to micro seconds */
+	do_div(delta, NSEC_PER_USEC);
+	stats->ac_etime += delta;
+
+	task_cputime(tsk, &utime, &stime);
+	stats->ac_utime += div_u64(utime, NSEC_PER_USEC);
+	stats->ac_stime += div_u64(stime, NSEC_PER_USEC);
+
+	stats->nvcsw += tsk->nvcsw;
+	stats->nivcsw += tsk->nivcsw;
+}
+
 static int fill_stats_for_tgid(pid_t tgid, struct taskstats *stats)
 {
 	struct task_struct *tsk, *first;
 	unsigned long flags;
 	int rc = -ESRCH;
-	u64 delta, utime, stime;
-	u64 start_time;
+	u64 now_ns;
 
 	/*
 	 * Add additional stats from live tasks except zombie thread group
@@ -233,30 +259,12 @@ static int fill_stats_for_tgid(pid_t tgid, struct taskstats *stats)
 	else
 		memset(stats, 0, sizeof(*stats));
 
-	start_time = ktime_get_ns();
+	now_ns = ktime_get_ns();
 	for_each_thread(first, tsk) {
 		if (tsk->exit_state)
 			continue;
-		/*
-		 * Accounting subsystem can call its functions here to
-		 * fill in relevant parts of struct taskstsats as follows
-		 *
-		 *	per-task-foo(stats, tsk);
-		 */
-		delayacct_add_tsk(stats, tsk);
-
-		/* calculate task elapsed time in nsec */
-		delta = start_time - tsk->start_time;
-		/* Convert to micro seconds */
-		do_div(delta, NSEC_PER_USEC);
-		stats->ac_etime += delta;
 
-		task_cputime(tsk, &utime, &stime);
-		stats->ac_utime += div_u64(utime, NSEC_PER_USEC);
-		stats->ac_stime += div_u64(stime, NSEC_PER_USEC);
-
-		stats->nvcsw += tsk->nvcsw;
-		stats->nivcsw += tsk->nivcsw;
+		tgid_stats_add_task(stats, tsk, now_ns);
 	}
 
 	unlock_task_sighand(first, &flags);
@@ -275,18 +283,14 @@ static int fill_stats_for_tgid(pid_t tgid, struct taskstats *stats)
 static void fill_tgid_exit(struct task_struct *tsk)
 {
 	unsigned long flags;
+	u64 now_ns;
 
 	spin_lock_irqsave(&tsk->sighand->siglock, flags);
 	if (!tsk->signal->stats)
 		goto ret;
 
-	/*
-	 * Each accounting subsystem calls its functions here to
-	 * accumalate its per-task stats for tsk, into the per-tgid structure
-	 *
-	 *	per-task-foo(tsk->signal->stats, tsk);
-	 */
-	delayacct_add_tsk(tsk->signal->stats, tsk);
+	now_ns = ktime_get_ns();
+	tgid_stats_add_task(tsk->signal->stats, tsk, now_ns);
 ret:
 	spin_unlock_irqrestore(&tsk->sighand->siglock, flags);
 	return;
diff --git a/kernel/workqueue.c b/kernel/workqueue.c
index 5f747f241a5f..bdf0879f4caf 100644
--- a/kernel/workqueue.c
+++ b/kernel/workqueue.c
@@ -3183,6 +3183,10 @@ static bool manage_workers(struct worker *worker)
 	return true;
 }
 
+#ifdef CONFIG_NET_DEV_REFCNT_TRACKER
+static noinline void process_one_work(struct worker *worker, struct work_struct *work);
+#endif
+
 /**
  * process_one_work - process single work
  * @worker: self
@@ -3206,6 +3210,9 @@ __acquires(&pool->lock)
 	unsigned long work_data;
 	int lockdep_start_depth, rcu_start_depth;
 	bool bh_draining = pool->flags & POOL_BH_DRAINING;
+#ifdef CONFIG_KCOV
+	unsigned int old_kcov_mode, new_kcov_mode;
+#endif
 #ifdef CONFIG_LOCKDEP
 	/*
 	 * It is permissible to free the struct work_struct from
@@ -3299,7 +3306,13 @@ __acquires(&pool->lock)
 	 */
 	lockdep_invariant_state(true);
 	trace_workqueue_execute_start(work);
+#ifdef CONFIG_KCOV
+	old_kcov_mode = READ_ONCE(current->kcov_mode);
+#endif
 	worker->current_func(work);
+#ifdef CONFIG_KCOV
+	new_kcov_mode = READ_ONCE(current->kcov_mode);
+#endif
 	/*
 	 * While we must be careful to not use "work" after this, the trace
 	 * point will only record its address.
@@ -3322,6 +3335,11 @@ __acquires(&pool->lock)
 		debug_show_held_locks(current);
 		dump_stack();
 	}
+#ifdef CONFIG_KCOV
+	if (unlikely((old_kcov_mode & ~(1 << 30)) != (new_kcov_mode & ~(1 << 30))))
+		pr_err("BUG: workqueue function %ps changed kcov_mode from %u to %u\n",
+		       worker->current_func, old_kcov_mode, new_kcov_mode);
+#endif
 
 	/*
 	 * The following prevents a kworker from hogging CPU on !PREEMPTION
@@ -3413,6 +3431,11 @@ static int worker_thread(void *__worker)
 	struct worker *worker = __worker;
 	struct worker_pool *pool = worker->pool;
 
+#ifdef CONFIG_KCOV
+	if (unlikely(current->kcov_mode & ~(1 << 30)))
+		pr_err("BUG: %s started with kcov_mode=%u\n", __func__, current->kcov_mode);
+#endif
+
 	/* tell the scheduler that this is a workqueue worker */
 	set_pf_worker(true);
 woke_up:
@@ -3565,6 +3588,11 @@ static int rescuer_thread(void *__rescuer)
 	struct workqueue_struct *wq = rescuer->rescue_wq;
 	bool should_stop;
 
+#ifdef CONFIG_KCOV
+	if (unlikely(current->kcov_mode & ~(1 << 30)))
+		pr_err("BUG: %s started with kcov_mode=%u\n", __func__, current->kcov_mode);
+#endif
+
 	set_user_nice(current, RESCUER_NICE_LEVEL);
 
 	/*
diff --git a/lib/Kconfig b/lib/Kconfig
index 00a9509636c1..ed31919a5a0b 100644
--- a/lib/Kconfig
+++ b/lib/Kconfig
@@ -590,7 +590,7 @@ config OBJAGG
 config LWQ_TEST
 	bool "Boot-time test for lwq queuing"
 	help
-          Run boot-time test of light-weight queuing.
+	  Run boot-time test of light-weight queuing.
 
 endmenu
 
diff --git a/lib/Kconfig.debug b/lib/Kconfig.debug
index 8ff5adcfe1e0..9f5e658bf05f 100644
--- a/lib/Kconfig.debug
+++ b/lib/Kconfig.debug
@@ -2261,6 +2261,13 @@ config KCOV_SELFTEST
 	  On test failure, causes the kernel to panic. Recommended to be
 	  enabled, ensuring critical functionality works as intended.
 
+config DEBUG_AID_FOR_SYZBOT
+       bool "Additional debug code for syzbot"
+       default n
+       select PREEMPT_RT if EXPERT && ARCH_SUPPORTS_RT && !COMPILE_TEST
+       help
+         This option is intended for testing by syzbot.
+
 menuconfig RUNTIME_TESTING_MENU
 	bool "Runtime Testing"
 	default y
@@ -2406,6 +2413,16 @@ config FPROBE_SANITY_TEST
 
 	  Say N if you are unsure.
 
+config BARRIER_TIMEOUT_TEST
+	tristate "KUnit tests for smp_cond_load_relaxed_timeout()"
+	depends on KUNIT
+	default KUNIT_ALL_TESTS
+	help
+	  Builds KUnit tests that validate wake-up and timeout handling paths
+	  in smp_cond_load_relaxed_timeout().
+
+	  Say N if you are unsure.
+
 config BACKTRACE_SELF_TEST
 	tristate "Self test for the backtrace code"
 	depends on DEBUG_KERNEL
@@ -3077,6 +3094,16 @@ config LONGEST_SYM_KUNIT_TEST
 
 	  If unsure, say N.
 
+config LINEINFO_KUNIT_TEST
+	tristate "KUnit tests for kallsyms lineinfo" if !KUNIT_ALL_TESTS
+	depends on KUNIT && KALLSYMS_LINEINFO
+	default KUNIT_ALL_TESTS
+	help
+	  KUnit tests for the kallsyms source line info feature.
+	  Verifies that stack traces include correct (file.c:line) annotations.
+
+	  If unsure, say N.
+
 config HW_BREAKPOINT_KUNIT_TEST
 	bool "Test hw_breakpoint constraints accounting" if !KUNIT_ALL_TESTS
 	depends on HAVE_HW_BREAKPOINT
diff --git a/lib/alloc_tag.c b/lib/alloc_tag.c
index ed1bdcf1f8ab..a6c58e07bb71 100644
--- a/lib/alloc_tag.c
+++ b/lib/alloc_tag.c
@@ -54,7 +54,7 @@ static void *allocinfo_start(struct seq_file *m, loff_t *pos)
 	loff_t node = *pos;
 
 	priv = (struct allocinfo_private *)m->private;
-	codetag_lock_module_list(alloc_tag_cttype, true);
+	codetag_lock_module_list(alloc_tag_cttype);
 	if (node == 0) {
 		priv->print_header = true;
 		priv->iter = codetag_get_ct_iter(alloc_tag_cttype);
@@ -77,7 +77,7 @@ static void *allocinfo_next(struct seq_file *m, void *arg, loff_t *pos)
 
 static void allocinfo_stop(struct seq_file *m, void *arg)
 {
-	codetag_lock_module_list(alloc_tag_cttype, false);
+	codetag_unlock_module_list(alloc_tag_cttype);
 }
 
 static void print_allocinfo_header(struct seq_buf *buf)
@@ -136,7 +136,7 @@ size_t alloc_tag_top_users(struct codetag_bytes *tags, size_t count, bool can_sl
 		return 0;
 
 	if (can_sleep)
-		codetag_lock_module_list(alloc_tag_cttype, true);
+		codetag_lock_module_list(alloc_tag_cttype);
 	else if (!codetag_trylock_module_list(alloc_tag_cttype))
 		return 0;
 
@@ -161,7 +161,7 @@ size_t alloc_tag_top_users(struct codetag_bytes *tags, size_t count, bool can_sl
 		}
 	}
 
-	codetag_lock_module_list(alloc_tag_cttype, false);
+	codetag_unlock_module_list(alloc_tag_cttype);
 
 	return nr;
 }
diff --git a/lib/base64.c b/lib/base64.c
index 41961a444028..325c7332b049 100644
--- a/lib/base64.c
+++ b/lib/base64.c
@@ -122,7 +122,7 @@ EXPORT_SYMBOL_GPL(base64_encode);
  * @src: the string to decode.  Doesn't need to be NUL-terminated.
  * @srclen: the length of @src in bytes
  * @dst: (output) the decoded binary data
- * @padding: whether to append '=' padding characters
+ * @padding: whether the input is expected to include '=' padding characters
  * @variant: which base64 variant to use
  *
  * Decodes a string using the selected Base64 variant.
@@ -168,15 +168,16 @@ int base64_decode(const char *src, int srclen, u8 *dst, bool padding, enum base6
 		return -1;
 
 	val = (base64_rev_tables[s[0]] << 12) | (base64_rev_tables[s[1]] << 6);
-	*bp++ = val >> 10;
 
 	if (srclen == 2) {
 		if (val & 0x800003ff)
 			return -1;
+		*bp++ = val >> 10;
 	} else {
 		val |= base64_rev_tables[s[2]];
 		if (val & 0x80000003)
 			return -1;
+		*bp++ = val >> 10;
 		*bp++ = val >> 2;
 	}
 	return bp - dst;
diff --git a/lib/cmdline.c b/lib/cmdline.c
index 90ed997d9570..16cce6621cec 100644
--- a/lib/cmdline.c
+++ b/lib/cmdline.c
@@ -43,7 +43,7 @@ static int get_range(char **str, int *pint, int n)
  *	When @pint is NULL the function can be used as a validator of
  *	the current option in the string.
  *
- *	Return values:
+ *	Return:
  *	0 - no int in string
  *	1 - int found, no subsequent comma
  *	2 - int found including a subsequent comma
@@ -145,44 +145,54 @@ EXPORT_SYMBOL(get_options);
  *
  *	Parses a string into a number.  The number stored at @ptr is
  *	potentially suffixed with K, M, G, T, P, E.
+ *
+ *	Return: The value as recognized by simple_strtoull() multiplied
+ *	by the value as specified by suffix, if any.
  */
 
 unsigned long long memparse(const char *ptr, char **retptr)
 {
 	char *endptr;	/* local pointer to end of parsed string */
-
 	unsigned long long ret = simple_strtoull(ptr, &endptr, 0);
+	unsigned int shl = 0;
 
+	/* Consume valid suffix even in case of overflow. */
 	switch (*endptr) {
 	case 'E':
 	case 'e':
-		ret <<= 10;
+		shl += 10;
 		fallthrough;
 	case 'P':
 	case 'p':
-		ret <<= 10;
+		shl += 10;
 		fallthrough;
 	case 'T':
 	case 't':
-		ret <<= 10;
+		shl += 10;
 		fallthrough;
 	case 'G':
 	case 'g':
-		ret <<= 10;
+		shl += 10;
 		fallthrough;
 	case 'M':
 	case 'm':
-		ret <<= 10;
+		shl += 10;
 		fallthrough;
 	case 'K':
 	case 'k':
-		ret <<= 10;
-		endptr++;
+		shl += 10;
 		fallthrough;
 	default:
 		break;
 	}
 
+	if (shl && likely(ptr != endptr)) {
+		/* Have valid suffix with preceding number. */
+		if (unlikely(check_shl_overflow(ret, shl, &ret)))
+			ret = ULLONG_MAX;
+		endptr++;
+	}
+
 	if (retptr)
 		*retptr = endptr;
 
@@ -198,7 +208,7 @@ EXPORT_SYMBOL(memparse);
  *	This function parses a string containing a comma-separated list of
  *	strings like a=b,c.
  *
- *	Return true if there's such option in the string, or return false.
+ *	Return: True if there's such option in the string or false otherwise.
  */
 bool parse_option_str(const char *str, const char *option)
 {
diff --git a/lib/codetag.c b/lib/codetag.c
index 304667897ad4..4001a7ea6675 100644
--- a/lib/codetag.c
+++ b/lib/codetag.c
@@ -35,12 +35,9 @@ struct codetag_module {
 static DEFINE_MUTEX(codetag_lock);
 static LIST_HEAD(codetag_types);
 
-void codetag_lock_module_list(struct codetag_type *cttype, bool lock)
+void codetag_lock_module_list(struct codetag_type *cttype)
 {
-	if (lock)
-		down_read(&cttype->mod_lock);
-	else
-		up_read(&cttype->mod_lock);
+	down_read(&cttype->mod_lock);
 }
 
 bool codetag_trylock_module_list(struct codetag_type *cttype)
@@ -48,6 +45,11 @@ bool codetag_trylock_module_list(struct codetag_type *cttype)
 	return down_read_trylock(&cttype->mod_lock) != 0;
 }
 
+void codetag_unlock_module_list(struct codetag_type *cttype)
+{
+	up_read(&cttype->mod_lock);
+}
+
 struct codetag_iterator codetag_get_ct_iter(struct codetag_type *cttype)
 {
 	struct codetag_iterator iter = {
diff --git a/lib/idr.c b/lib/idr.c
index 69bee5369670..1649f41016e7 100644
--- a/lib/idr.c
+++ b/lib/idr.c
@@ -495,10 +495,9 @@ int ida_find_first_range(struct ida *ida, unsigned int min, unsigned int max)
 	unsigned long index = min / IDA_BITMAP_BITS;
 	unsigned int offset = min % IDA_BITMAP_BITS;
 	unsigned long *addr, size, bit;
-	unsigned long tmp = 0;
+	unsigned long tmp;
 	unsigned long flags;
 	void *entry;
-	int ret;
 
 	if ((int)min < 0)
 		return -EINVAL;
@@ -508,40 +507,34 @@ int ida_find_first_range(struct ida *ida, unsigned int min, unsigned int max)
 	xa_lock_irqsave(&ida->xa, flags);
 
 	entry = xa_find(&ida->xa, &index, max / IDA_BITMAP_BITS, XA_PRESENT);
-	if (!entry) {
-		ret = -ENOENT;
-		goto err_unlock;
-	}
-
-	if (index > min / IDA_BITMAP_BITS)
-		offset = 0;
-	if (index * IDA_BITMAP_BITS + offset > max) {
-		ret = -ENOENT;
-		goto err_unlock;
-	}
-
-	if (xa_is_value(entry)) {
-		tmp = xa_to_value(entry);
-		addr = &tmp;
-		size = BITS_PER_XA_VALUE;
-	} else {
-		addr = ((struct ida_bitmap *)entry)->bitmap;
-		size = IDA_BITMAP_BITS;
-	}
-
-	bit = find_next_bit(addr, size, offset);
+	while (entry) {
+		if (index > min / IDA_BITMAP_BITS)
+			offset = 0;
+		if (index * IDA_BITMAP_BITS + offset > max)
+			break;
 
-	xa_unlock_irqrestore(&ida->xa, flags);
+		if (xa_is_value(entry)) {
+			tmp = xa_to_value(entry);
+			addr = &tmp;
+			size = BITS_PER_XA_VALUE;
+		} else {
+			addr = ((struct ida_bitmap *)entry)->bitmap;
+			size = IDA_BITMAP_BITS;
+		}
 
-	if (bit == size ||
-	    index * IDA_BITMAP_BITS + bit > max)
-		return -ENOENT;
+		bit = find_next_bit(addr, size, offset);
+		if (bit < size &&
+		    index * IDA_BITMAP_BITS + bit <= max) {
+			xa_unlock_irqrestore(&ida->xa, flags);
+			return index * IDA_BITMAP_BITS + bit;
+		}
 
-	return index * IDA_BITMAP_BITS + bit;
+		entry = xa_find_after(&ida->xa, &index,
+				      max / IDA_BITMAP_BITS, XA_PRESENT);
+	}
 
-err_unlock:
 	xa_unlock_irqrestore(&ida->xa, flags);
-	return ret;
+	return -ENOENT;
 }
 EXPORT_SYMBOL(ida_find_first_range);
 
diff --git a/lib/kstrtox.c b/lib/kstrtox.c
index 97be2a39f537..edc4eb7c1bca 100644
--- a/lib/kstrtox.c
+++ b/lib/kstrtox.c
@@ -39,25 +39,30 @@ const char *_parse_integer_fixup_radix(const char *s, unsigned int *base)
 	return s;
 }
 
-/*
- * Convert non-negative integer string representation in explicitly given radix
- * to an integer. A maximum of max_chars characters will be converted.
+/**
+ * _parse_integer_limit - Convert integer string representation to an integer
+ * @s: Integer string representation
+ * @base: Radix
+ * @p: Where to store result
+ * @max_chars: Maximum amount of characters to convert
+ *
+ * Convert non-negative integer string representation in explicitly given
+ * radix to an integer. If overflow occurs, value at @p is set to ULLONG_MAX.
  *
- * Return number of characters consumed maybe or-ed with overflow bit.
- * If overflow occurs, result integer (incorrect) is still returned.
+ * This function is the workhorse of other string conversion functions and it
+ * is discouraged to use it explicitly. Consider kstrto*() family instead.
  *
- * Don't you dare use this function.
+ * Return: Number of characters consumed, maybe ORed with overflow bit
  */
 noinline
 unsigned int _parse_integer_limit(const char *s, unsigned int base, unsigned long long *p,
 				  size_t max_chars)
 {
+	unsigned int rv, overflow = 0;
 	unsigned long long res;
-	unsigned int rv;
 
 	res = 0;
-	rv = 0;
-	while (max_chars--) {
+	for (rv = 0; rv < max_chars; rv++, s++) {
 		unsigned int c = *s;
 		unsigned int lc = _tolower(c);
 		unsigned int val;
@@ -76,15 +81,17 @@ unsigned int _parse_integer_limit(const char *s, unsigned int base, unsigned lon
 		 * it in the max base we support (16)
 		 */
 		if (unlikely(res & (~0ull << 60))) {
-			if (res > div_u64(ULLONG_MAX - val, base))
-				rv |= KSTRTOX_OVERFLOW;
+			if (check_mul_overflow(res, base, &res) ||
+			    check_add_overflow(res, val, &res)) {
+				res = ULLONG_MAX;
+				overflow = KSTRTOX_OVERFLOW;
+			}
+		} else {
+			res = res * base + val;
 		}
-		res = res * base + val;
-		rv++;
-		s++;
 	}
 	*p = res;
-	return rv;
+	return rv | overflow;
 }
 
 noinline
diff --git a/lib/maple_tree.c b/lib/maple_tree.c
index d18d7ed9ab67..60ae5e6fc1ee 100644
--- a/lib/maple_tree.c
+++ b/lib/maple_tree.c
@@ -2,7 +2,7 @@
 /*
  * Maple Tree implementation
  * Copyright (c) 2018-2022 Oracle Corporation
- * Authors: Liam R. Howlett <Liam.Howlett@oracle.com>
+ * Authors: Liam R. Howlett <liam@infradead.org>
  *	    Matthew Wilcox <willy@infradead.org>
  * Copyright (c) 2023 ByteDance
  * Author: Peng Zhang <zhangpeng.00@bytedance.com>
diff --git a/lib/rhashtable.c b/lib/rhashtable.c
index 6074ed5f66f3..7a67ef5b67b6 100644
--- a/lib/rhashtable.c
+++ b/lib/rhashtable.c
@@ -441,10 +441,33 @@ static void rht_deferred_worker(struct work_struct *work)
 
 	mutex_unlock(&ht->mutex);
 
+	/*
+	 * Re-arm via @run_work, not @run_irq_work.
+	 * rhashtable_free_and_destroy() drains async work as irq_work_sync()
+	 * followed by cancel_work_sync(). If this site queued irq_work while
+	 * cancel_work_sync() was waiting for us, irq_work_sync() would already
+	 * have returned and the stale irq_work could fire post-teardown.
+	 * cancel_work_sync() natively handles self-requeue on @run_work.
+	 */
 	if (err)
 		schedule_work(&ht->run_work);
 }
 
+/*
+ * Insert-path callers can run under a raw spinlock (e.g. an insecure_elasticity
+ * user). Calling schedule_work() under that lock records caller_lock ->
+ * pool->lock -> pi_lock -> rq->__lock, closing a locking cycle if any of
+ * these is acquired in the reverse direction elsewhere. Bounce through
+ * irq_work so the schedule_work() runs with the caller's lock no longer held.
+ */
+static void rht_deferred_irq_work(struct irq_work *irq_work)
+{
+	struct rhashtable *ht = container_of(irq_work, struct rhashtable,
+					     run_irq_work);
+
+	schedule_work(&ht->run_work);
+}
+
 static int rhashtable_insert_rehash(struct rhashtable *ht,
 				    struct bucket_table *tbl)
 {
@@ -477,7 +500,7 @@ static int rhashtable_insert_rehash(struct rhashtable *ht,
 		if (err == -EEXIST)
 			err = 0;
 	} else
-		schedule_work(&ht->run_work);
+		irq_work_queue(&ht->run_irq_work);
 
 	return err;
 
@@ -488,7 +511,7 @@ static int rhashtable_insert_rehash(struct rhashtable *ht,
 
 	/* Schedule async rehash to retry allocation in process context. */
 	if (err == -ENOMEM)
-		schedule_work(&ht->run_work);
+		irq_work_queue(&ht->run_irq_work);
 
 	return err;
 }
@@ -538,7 +561,7 @@ static void *rhashtable_lookup_one(struct rhashtable *ht,
 		return NULL;
 	}
 
-	if (elasticity <= 0)
+	if (elasticity <= 0 && !ht->p.insecure_elasticity)
 		return ERR_PTR(-EAGAIN);
 
 	return ERR_PTR(-ENOENT);
@@ -568,7 +591,8 @@ static struct bucket_table *rhashtable_insert_one(
 	if (unlikely(rht_grow_above_max(ht, tbl)))
 		return ERR_PTR(-E2BIG);
 
-	if (unlikely(rht_grow_above_100(ht, tbl)))
+	if (unlikely(rht_grow_above_100(ht, tbl)) &&
+	    !ht->p.insecure_elasticity)
 		return ERR_PTR(-EAGAIN);
 
 	head = rht_ptr(bkt, tbl, hash);
@@ -629,7 +653,7 @@ static void *rhashtable_try_insert(struct rhashtable *ht, const void *key,
 			rht_unlock(tbl, bkt, flags);
 
 			if (inserted && rht_grow_above_75(ht, tbl))
-				schedule_work(&ht->run_work);
+				irq_work_queue(&ht->run_irq_work);
 		}
 	} while (!IS_ERR_OR_NULL(new_tbl));
 
@@ -1084,6 +1108,7 @@ int rhashtable_init_noprof(struct rhashtable *ht,
 	RCU_INIT_POINTER(ht->tbl, tbl);
 
 	INIT_WORK(&ht->run_work, rht_deferred_worker);
+	init_irq_work(&ht->run_irq_work, rht_deferred_irq_work);
 
 	return 0;
 }
@@ -1149,6 +1174,7 @@ void rhashtable_free_and_destroy(struct rhashtable *ht,
 	struct bucket_table *tbl, *next_tbl;
 	unsigned int i;
 
+	irq_work_sync(&ht->run_irq_work);
 	cancel_work_sync(&ht->run_work);
 
 	mutex_lock(&ht->mutex);
diff --git a/lib/seq_buf.c b/lib/seq_buf.c
index f3f3436d60a9..b59488fa8135 100644
--- a/lib/seq_buf.c
+++ b/lib/seq_buf.c
@@ -298,6 +298,7 @@ int seq_buf_putmem_hex(struct seq_buf *s, const void *mem,
 	}
 	return 0;
 }
+EXPORT_SYMBOL_GPL(seq_buf_putmem_hex);
 
 /**
  * seq_buf_path - copy a path into the sequence buffer
diff --git a/lib/test-kstrtox.c b/lib/test-kstrtox.c
index ee87fef66cb5..811128d0df16 100644
--- a/lib/test-kstrtox.c
+++ b/lib/test-kstrtox.c
@@ -198,6 +198,7 @@ static void __init test_kstrtoull_fail(void)
 		{"10000000000000000000000000000000000000000000000000000000000000000",	2},
 		{"2000000000000000000000",	8},
 		{"18446744073709551616",	10},
+		{"569202370375329612767",	10},
 		{"10000000000000000",	16},
 		/* negative */
 		{"-0", 0},
@@ -275,9 +276,11 @@ static void __init test_kstrtoll_fail(void)
 		{"9223372036854775809",	10},
 		{"18446744073709551614",	10},
 		{"18446744073709551615",	10},
+		{"569202370375329612767",	10},
 		{"-9223372036854775809",	10},
 		{"-18446744073709551614",	10},
 		{"-18446744073709551615",	10},
+		{"-569202370375329612767",	10},
 		/* sign is first character if any */
 		{"-+1", 0},
 		{"-+1", 8},
@@ -334,6 +337,7 @@ static void __init test_kstrtou64_fail(void)
 		{"-1",	10},
 		{"18446744073709551616",	10},
 		{"18446744073709551617",	10},
+		{"569202370375329612767",	10},
 	};
 	TEST_FAIL(kstrtou64, u64, "%llu", test_u64_fail);
 }
@@ -386,6 +390,8 @@ static void __init test_kstrtos64_fail(void)
 		{"18446744073709551615",	10},
 		{"18446744073709551616",	10},
 		{"18446744073709551617",	10},
+		{"569202370375329612767",	10},
+		{"-569202370375329612767",	10},
 	};
 	TEST_FAIL(kstrtos64, s64, "%lld", test_s64_fail);
 }
diff --git a/lib/test_ida.c b/lib/test_ida.c
index 63078f8dc13f..c400b24f88b6 100644
--- a/lib/test_ida.c
+++ b/lib/test_ida.c
@@ -256,6 +256,20 @@ static void ida_check_find_first(struct ida *ida)
 	ida_free(ida, (1 << 20) - 1);
 
 	IDA_BUG_ON(ida, !ida_is_empty(ida));
+
+	/*
+	 * Test cross-chunk search.
+	 * Allocate ID in chunk 0 and ID in chunk 1.
+	 * Search for ID >= 1. min=1 maps to chunk 0. Chunk 0 has no IDs >= 1.
+	 * It should continue to chunk 1 and return 1024.
+	 */
+	IDA_BUG_ON(ida, ida_alloc_min(ida, 0, GFP_KERNEL) != 0);
+	IDA_BUG_ON(ida, ida_alloc_min(ida, 1024, GFP_KERNEL) != 1024);
+	IDA_BUG_ON(ida, ida_find_first_range(ida, 1, INT_MAX) != 1024);
+	ida_free(ida, 0);
+	ida_free(ida, 1024);
+
+	IDA_BUG_ON(ida, !ida_is_empty(ida));
 }
 
 static DEFINE_IDA(ida);
diff --git a/lib/test_maple_tree.c b/lib/test_maple_tree.c
index 434d8a2fdd99..b9367c61e8b5 100644
--- a/lib/test_maple_tree.c
+++ b/lib/test_maple_tree.c
@@ -2,7 +2,7 @@
 /*
  * test_maple_tree.c: Test the maple tree API
  * Copyright (c) 2018-2022 Oracle Corporation
- * Author: Liam R. Howlett <Liam.Howlett@Oracle.com>
+ * Author: Liam R. Howlett <liam@infradead.org>
  *
  * Any tests that only require the interface of the tree.
  */
@@ -4021,6 +4021,6 @@ static void __exit maple_tree_harvest(void)
 
 module_init(maple_tree_seed);
 module_exit(maple_tree_harvest);
-MODULE_AUTHOR("Liam R. Howlett <Liam.Howlett@Oracle.com>");
+MODULE_AUTHOR("Liam R. Howlett <liam@infradead.org>");
 MODULE_DESCRIPTION("maple tree API test module");
 MODULE_LICENSE("GPL");
diff --git a/lib/tests/Makefile b/lib/tests/Makefile
index 7e9c2fa52e35..1082f76d3fe1 100644
--- a/lib/tests/Makefile
+++ b/lib/tests/Makefile
@@ -20,6 +20,7 @@ CFLAGS_fortify_kunit.o += $(DISABLE_STRUCTLEAK_PLUGIN)
 obj-$(CONFIG_FORTIFY_KUNIT_TEST) += fortify_kunit.o
 CFLAGS_test_fprobe.o += $(CC_FLAGS_FTRACE)
 obj-$(CONFIG_FPROBE_SANITY_TEST) += test_fprobe.o
+obj-$(CONFIG_BARRIER_TIMEOUT_TEST) += barrier-timeout-test.o
 obj-$(CONFIG_GLOB_KUNIT_TEST) += glob_kunit.o
 obj-$(CONFIG_HASHTABLE_KUNIT_TEST) += hashtable_test.o
 obj-$(CONFIG_HASH_KUNIT_TEST) += test_hash.o
@@ -36,6 +37,9 @@ obj-$(CONFIG_LIVEUPDATE_TEST) += liveupdate.o
 CFLAGS_longest_symbol_kunit.o += $(call cc-disable-warning, missing-prototypes)
 obj-$(CONFIG_LONGEST_SYM_KUNIT_TEST) += longest_symbol_kunit.o
 
+CFLAGS_lineinfo_kunit.o += $(call cc-option,-fno-inline-functions-called-once)
+obj-$(CONFIG_LINEINFO_KUNIT_TEST) += lineinfo_kunit.o
+
 obj-$(CONFIG_MEMCPY_KUNIT_TEST) += memcpy_kunit.o
 obj-$(CONFIG_MIN_HEAP_KUNIT_TEST) += min_heap_kunit.o
 CFLAGS_overflow_kunit.o = $(call cc-disable-warning, tautological-constant-out-of-range-compare)
diff --git a/lib/tests/barrier-timeout-test.c b/lib/tests/barrier-timeout-test.c
new file mode 100644
index 000000000000..41a069743834
--- /dev/null
+++ b/lib/tests/barrier-timeout-test.c
@@ -0,0 +1,125 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * KUnit tests exercising smp_cond_load_relaxed_timeout().
+ *
+ * Copyright (c) 2026, Oracle Corp.
+ * Author: Ankur Arora <ankur.a.arora@oracle.com>
+ */
+
+#include <linux/bitops.h>
+#include <linux/types.h>
+#include <linux/sched/clock.h>
+#include <linux/delay.h>
+#include <linux/kthread.h>
+#include <asm/barrier.h>
+#include <kunit/test.h>
+#include <kunit/visibility.h>
+
+MODULE_IMPORT_NS("EXPORTED_FOR_KUNIT_TESTING");
+
+struct clock_state {
+	s64 start_time;
+	s64 end_time;
+};
+
+#define TIMEOUT_MSEC	2
+#define TEST_FLAG_VAL	BIT(2)
+static unsigned int flag;
+
+static s64 basic_clock(struct clock_state *clk)
+{
+	clk->end_time = local_clock();
+	return clk->end_time;
+}
+
+static void update_flags(void)
+{
+	WRITE_ONCE(flag, TEST_FLAG_VAL);
+}
+
+static s64 mock_clock(struct clock_state *clk)
+{
+	s64 clk_mid = clk->start_time + (TIMEOUT_MSEC * NSEC_PER_MSEC)/2;
+
+	clk->end_time = local_clock();
+	if (clk->end_time >= clk_mid)
+		update_flags();
+	return clk->end_time;
+}
+
+typedef s64 (*clkfn_t)(struct clock_state *);
+
+static void test_smp_cond_relaxed_timeout(struct kunit *test,
+					  clkfn_t clock, bool succeeds)
+{
+	struct clock_state clk = {
+		.start_time = local_clock(),
+		.end_time = local_clock(),
+	};
+	s64 runtime, timeout_ns = TIMEOUT_MSEC * NSEC_PER_MSEC;
+	unsigned int result;
+
+	result = smp_cond_load_relaxed_timeout(&flag,
+					       (VAL & TEST_FLAG_VAL),
+					       clock(&clk),
+					       timeout_ns);
+
+	runtime = clk.end_time - clk.start_time;
+	KUNIT_EXPECT_EQ(test, (bool)(result & TEST_FLAG_VAL), succeeds);
+	KUNIT_EXPECT_EQ(test, runtime <= timeout_ns, succeeds);
+}
+
+static int smp_cond_threadfn(void *data)
+{
+	udelay(TIMEOUT_MSEC * USEC_PER_MSEC / 4);
+
+	/*
+	 * Update flags after a delay to give smp_cond_relaxed_timeout()
+	 * time to get started.
+	 */
+	update_flags();
+	return 0;
+}
+
+static void smp_cond_relaxed_timeout_succeeds(struct kunit *test)
+{
+	struct task_struct *task;
+
+	flag = 0;
+
+	task = kthread_run(smp_cond_threadfn, &flag, "smp_cond_thread");
+
+	KUNIT_ASSERT_NOT_ERR_OR_NULL(test, task);
+	test_smp_cond_relaxed_timeout(test, &basic_clock, true);
+
+	kthread_stop(task);
+}
+
+static void smp_cond_relaxed_timeout_mocked(struct kunit *test)
+{
+	flag = 0;
+	test_smp_cond_relaxed_timeout(test, &mock_clock, true);
+}
+
+static void smp_cond_relaxed_timeout_expires(struct kunit *test)
+{
+	flag = 0;
+	test_smp_cond_relaxed_timeout(test, &basic_clock, false);
+}
+
+static struct kunit_case barrier_timeout_test_cases[] = {
+	KUNIT_CASE(smp_cond_relaxed_timeout_mocked),
+	KUNIT_CASE(smp_cond_relaxed_timeout_succeeds),
+	KUNIT_CASE(smp_cond_relaxed_timeout_expires),
+	{}
+};
+
+static struct kunit_suite barrier_timeout_test_suite = {
+	.name = "smp-cond-load-relaxed-timeout",
+	.test_cases = barrier_timeout_test_cases,
+};
+
+kunit_test_suite(barrier_timeout_test_suite);
+
+MODULE_DESCRIPTION("KUnit tests for smp_cond_load_relaxed_timeout()");
+MODULE_LICENSE("GPL");
diff --git a/lib/tests/cmdline_kunit.c b/lib/tests/cmdline_kunit.c
index c1602f797637..c7024cffa16c 100644
--- a/lib/tests/cmdline_kunit.c
+++ b/lib/tests/cmdline_kunit.c
@@ -6,6 +6,7 @@
 #include <kunit/test.h>
 #include <linux/kernel.h>
 #include <linux/random.h>
+#include <linux/sizes.h>
 #include <linux/string.h>
 
 static const char *cmdline_test_strings[] = {
@@ -139,11 +140,128 @@ static void cmdline_test_range(struct kunit *test)
 	} while (++i < ARRAY_SIZE(cmdline_test_range_strings));
 }
 
+struct cmdline_test_memparse_entry {
+	const char *input;
+	const char *unrecognized;
+	unsigned long long result;
+};
+
+static const struct cmdline_test_memparse_entry testdata[] = {
+	{ "0",				"",	0ULL },
+	{ "1",				"",	1ULL },
+	{ "a",				"a",	0ULL },
+	{ "k",				"k",	0ULL },
+	{ "E",				"E",	0ULL },
+	{ "0xb",			"",	11ULL },
+	{ "0xz",			"x",	0ULL },
+	{ "1234",			"",	1234ULL },
+	{ "04567",			"",	2423ULL },
+	{ "0x9876",			"",	39030LL },
+	{ "05678",			"8",	375ULL },
+	{ "0xabcdefz",			"z",	11259375ULL },
+	{ "0cdba",			"c",	0ULL },
+	{ "4K",				"",	SZ_4K },
+	{ "0x10k@0xaaaabbbb",		"@",	SZ_16K },
+	{ "32M",			"",	SZ_32M },
+	{ "067m:foo",			":",	55 * SZ_1M },
+	{ "2G;bar=baz",			";",	SZ_2G },
+	{ "07gz",			"z",	7ULL * SZ_1G },
+	{ "3T+data",			"+",	3 * SZ_1T },
+	{ "04t,ro",			",",	SZ_4T },
+	{ "012p",			"",	11258999068426240ULL },
+	{ "7P,sync",			",",	7881299347898368ULL },
+	{ "0x2e",			"",	46ULL },
+	{ "2E and more",		" ",	2305843009213693952ULL },
+	{ "18446744073709551615",	"",	ULLONG_MAX },
+	{ "0xffffffffffffffff0",	"",	ULLONG_MAX },
+	{ "1111111111111111111T",	"",	ULLONG_MAX },
+	{ "222222222222222222222G",	"",	ULLONG_MAX },
+	{ "3333333333333333333333M",	"",	ULLONG_MAX },
+};
+
+static void cmdline_test_memparse(struct kunit *test)
+{
+	const struct cmdline_test_memparse_entry *e;
+	unsigned long long ret;
+	char *retptr;
+
+	for (e = testdata; e < testdata + ARRAY_SIZE(testdata); e++) {
+		ret = memparse(e->input, &retptr);
+		KUNIT_EXPECT_EQ_MSG(test, ret, e->result,
+				    "    when parsing '%s'", e->input);
+		KUNIT_EXPECT_EQ_MSG(test, *retptr, *e->unrecognized,
+				    "    when parsing '%s'", e->input);
+	}
+}
+
+static void cmdline_test_next_arg_quoted_value(struct kunit *test)
+{
+	char in[] = "foo=\"bar baz\" qux=1";
+	char *next, *param, *val;
+
+	next = next_arg(in, &param, &val);
+	KUNIT_EXPECT_STREQ(test, param, "foo");
+	KUNIT_ASSERT_NOT_NULL(test, val);
+	KUNIT_EXPECT_STREQ(test, val, "bar baz");
+	KUNIT_EXPECT_STREQ(test, next, "qux=1");
+
+	next = next_arg(next, &param, &val);
+	KUNIT_EXPECT_STREQ(test, param, "qux");
+	KUNIT_ASSERT_NOT_NULL(test, val);
+	KUNIT_EXPECT_STREQ(test, val, "1");
+	KUNIT_EXPECT_STREQ(test, next, "");
+}
+
+static void cmdline_test_next_arg_bare_quote_regression(struct kunit *test)
+{
+	char in[] = "foo=bar \"";
+	char *next, *param, *val;
+
+	next = next_arg(in, &param, &val);
+	KUNIT_EXPECT_STREQ(test, param, "foo");
+	KUNIT_ASSERT_NOT_NULL(test, val);
+	KUNIT_EXPECT_STREQ(test, val, "bar");
+	KUNIT_EXPECT_STREQ(test, next, "\"");
+
+	/* This hits the i == 0 quoted-token case fixed by 9847f21225c4. */
+	next = next_arg(next, &param, &val);
+	KUNIT_EXPECT_STREQ(test, param, "");
+	KUNIT_EXPECT_PTR_EQ(test, val, NULL);
+	KUNIT_EXPECT_STREQ(test, next, "");
+}
+
+static void cmdline_test_next_arg_mixed_tokens(struct kunit *test)
+{
+	char in[] = "bbb= jjj kkk=\"a=b\"";
+	char *next, *param, *val;
+
+	next = next_arg(in, &param, &val);
+	KUNIT_EXPECT_STREQ(test, param, "bbb");
+	KUNIT_ASSERT_NOT_NULL(test, val);
+	KUNIT_EXPECT_STREQ(test, val, "");
+	KUNIT_EXPECT_STREQ(test, next, "jjj kkk=\"a=b\"");
+
+	next = next_arg(next, &param, &val);
+	KUNIT_EXPECT_STREQ(test, param, "jjj");
+	KUNIT_EXPECT_NULL(test, val);
+	KUNIT_EXPECT_STREQ(test, next, "kkk=\"a=b\"");
+
+	next = next_arg(next, &param, &val);
+	KUNIT_EXPECT_STREQ(test, param, "kkk");
+	KUNIT_ASSERT_NOT_NULL(test, val);
+	KUNIT_EXPECT_STREQ(test, val, "a=b");
+	KUNIT_EXPECT_STREQ(test, next, "");
+}
+
 static struct kunit_case cmdline_test_cases[] = {
 	KUNIT_CASE(cmdline_test_noint),
 	KUNIT_CASE(cmdline_test_lead_int),
 	KUNIT_CASE(cmdline_test_tail_int),
 	KUNIT_CASE(cmdline_test_range),
+	KUNIT_CASE(cmdline_test_memparse),
+	KUNIT_CASE(cmdline_test_next_arg_quoted_value),
+	KUNIT_CASE(cmdline_test_next_arg_bare_quote_regression),
+	KUNIT_CASE(cmdline_test_next_arg_mixed_tokens),
 	{}
 };
 
diff --git a/lib/tests/kunit_iov_iter.c b/lib/tests/kunit_iov_iter.c
index 37bd6eb25896..f02f7b7aa796 100644
--- a/lib/tests/kunit_iov_iter.c
+++ b/lib/tests/kunit_iov_iter.c
@@ -1128,7 +1128,7 @@ static void __init iov_kunit_iter_to_sg_kvec(struct kunit *test)
 	struct kvec kvec;
 	size_t bufsize;
 
-	bufsize = 0x100000;
+	bufsize = 0x200000;
 	iov_kunit_iter_to_sg_init(test, bufsize, false, &data);
 
 	kvec.iov_base = data.buffer;
@@ -1146,7 +1146,7 @@ static void __init iov_kunit_iter_to_sg_bvec(struct kunit *test)
 	struct bio_vec *bvec;
 	struct iov_iter iter;
 
-	bufsize = 0x100000;
+	bufsize = 0x200000;
 	iov_kunit_iter_to_sg_init(test, bufsize, false, &data);
 
 	bvec = kunit_kmalloc_array(test, data.npages, sizeof(*bvec),
@@ -1173,7 +1173,7 @@ static void __init iov_kunit_iter_to_sg_folioq(struct kunit *test)
 	struct iov_iter iter;
 	size_t bufsize;
 
-	bufsize = 0x100000;
+	bufsize = 0x200000;
 	iov_kunit_iter_to_sg_init(test, bufsize, false, &data);
 
 	folioq = iov_kunit_create_folioq(test);
@@ -1190,7 +1190,7 @@ static void __init iov_kunit_iter_to_sg_xarray(struct kunit *test)
 	struct iov_iter iter;
 	size_t bufsize;
 
-	bufsize = 0x100000;
+	bufsize = 0x200000;
 	iov_kunit_iter_to_sg_init(test, bufsize, false, &data);
 
 	xarray = iov_kunit_create_xarray(test);
@@ -1206,7 +1206,7 @@ static void __init iov_kunit_iter_to_sg_ubuf(struct kunit *test)
 	struct iov_iter iter;
 	size_t bufsize;
 
-	bufsize = 0x100000;
+	bufsize = 0x200000;
 	iov_kunit_iter_to_sg_init(test, bufsize, true, &data);
 
 	iov_iter_ubuf(&iter, READ, data.ubuf, bufsize);
diff --git a/lib/tests/lineinfo_kunit.c b/lib/tests/lineinfo_kunit.c
new file mode 100644
index 000000000000..81696fa0000a
--- /dev/null
+++ b/lib/tests/lineinfo_kunit.c
@@ -0,0 +1,813 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * KUnit tests for kallsyms lineinfo (CONFIG_KALLSYMS_LINEINFO).
+ *
+ * Copyright (c) 2026 Sasha Levin <sashal@kernel.org>
+ *
+ * Verifies that sprint_symbol() and related APIs append correct
+ * " (file.c:NNN)" annotations to kernel symbol lookups.
+ *
+ * Build with: CONFIG_LINEINFO_KUNIT_TEST=m (or =y)
+ * Run with:   ./tools/testing/kunit/kunit.py run lineinfo
+ */
+
+#include <kunit/test.h>
+#include <linux/kallsyms.h>
+#include <linux/module.h>
+#include <linux/smp.h>
+#include <linux/string.h>
+#include <linux/slab.h>
+#include <linux/mod_lineinfo.h>
+
+/* --------------- helpers --------------- */
+
+static char *alloc_sym_buf(struct kunit *test)
+{
+	return kunit_kzalloc(test, KSYM_SYMBOL_LEN, GFP_KERNEL);
+}
+
+/*
+ * Return true if @buf contains a lineinfo annotation matching
+ * the pattern " (<path>:<digits>)".
+ *
+ * The path may be a full path like "lib/tests/lineinfo_kunit.c" or
+ * a shortened form from module lineinfo (e.g., just a directory name).
+ */
+static bool has_lineinfo(const char *buf)
+{
+	const char *p, *colon, *end;
+
+	p = strstr(buf, " (");
+	if (!p)
+		return false;
+	p += 2; /* skip " (" */
+
+	colon = strchr(p, ':');
+	if (!colon || colon == p)
+		return false;
+
+	/* After colon: one or more digits then ')' */
+	end = colon + 1;
+	if (*end < '0' || *end > '9')
+		return false;
+	while (*end >= '0' && *end <= '9')
+		end++;
+	return *end == ')';
+}
+
+/*
+ * Extract line number from a lineinfo annotation.
+ * Returns 0 if not found.
+ */
+static unsigned int extract_line(const char *buf)
+{
+	const char *p, *colon;
+	unsigned int line = 0;
+
+	p = strstr(buf, " (");
+	if (!p)
+		return 0;
+
+	colon = strchr(p + 2, ':');
+	if (!colon)
+		return 0;
+
+	colon++;
+	while (*colon >= '0' && *colon <= '9') {
+		line = line * 10 + (*colon - '0');
+		colon++;
+	}
+	return line;
+}
+
+/*
+ * Check if the lineinfo annotation contains the given filename substring.
+ */
+static bool lineinfo_contains_file(const char *buf, const char *name)
+{
+	const char *p, *colon;
+
+	p = strstr(buf, " (");
+	if (!p)
+		return false;
+
+	colon = strchr(p + 2, ':');
+	if (!colon)
+		return false;
+
+	/* Search for @name between '(' and ':' */
+	return strnstr(p + 1, name, colon - p - 1) != NULL;
+}
+
+/* --------------- target functions --------------- */
+
+static noinline int lineinfo_target_normal(void)
+{
+	barrier();
+	return 42;
+}
+
+static noinline int lineinfo_target_short(void)
+{
+	barrier();
+	return 1;
+}
+
+static noinline int lineinfo_target_with_arg(int x)
+{
+	barrier();
+	return x + 1;
+}
+
+static noinline int lineinfo_target_many_lines(void)
+{
+	int a = 0;
+
+	barrier();
+	a += 1;
+	a += 2;
+	a += 3;
+	a += 4;
+	a += 5;
+	a += 6;
+	a += 7;
+	a += 8;
+	a += 9;
+	a += 10;
+	barrier();
+	return a;
+}
+
+static __always_inline int lineinfo_inline_helper(void)
+{
+	return 99;
+}
+
+static noinline int lineinfo_inline_caller(void)
+{
+	barrier();
+	return lineinfo_inline_helper();
+}
+
+/* 10-deep call chain */
+static noinline int lineinfo_chain_10(void) { barrier(); return 10; }
+static noinline int lineinfo_chain_9(void)  { barrier(); return lineinfo_chain_10(); }
+static noinline int lineinfo_chain_8(void)  { barrier(); return lineinfo_chain_9(); }
+static noinline int lineinfo_chain_7(void)  { barrier(); return lineinfo_chain_8(); }
+static noinline int lineinfo_chain_6(void)  { barrier(); return lineinfo_chain_7(); }
+static noinline int lineinfo_chain_5(void)  { barrier(); return lineinfo_chain_6(); }
+static noinline int lineinfo_chain_4(void)  { barrier(); return lineinfo_chain_5(); }
+static noinline int lineinfo_chain_3(void)  { barrier(); return lineinfo_chain_4(); }
+static noinline int lineinfo_chain_2(void)  { barrier(); return lineinfo_chain_3(); }
+static noinline int lineinfo_chain_1(void)  { barrier(); return lineinfo_chain_2(); }
+
+/* --------------- Group A: Basic lineinfo presence --------------- */
+
+static void test_normal_function(struct kunit *test)
+{
+	char *buf = alloc_sym_buf(test);
+	unsigned long addr = (unsigned long)lineinfo_target_normal;
+
+	sprint_symbol(buf, addr);
+	KUNIT_EXPECT_TRUE_MSG(test, has_lineinfo(buf),
+			      "No lineinfo in: %s", buf);
+	KUNIT_EXPECT_TRUE_MSG(test,
+			      lineinfo_contains_file(buf, "lineinfo_kunit.c"),
+			      "Wrong file in: %s", buf);
+}
+
+static void test_static_function(struct kunit *test)
+{
+	char *buf = alloc_sym_buf(test);
+	unsigned long addr = (unsigned long)lineinfo_target_short;
+
+	sprint_symbol(buf, addr);
+	KUNIT_EXPECT_TRUE_MSG(test, has_lineinfo(buf),
+			      "No lineinfo in: %s", buf);
+}
+
+static void test_noinline_function(struct kunit *test)
+{
+	char *buf = alloc_sym_buf(test);
+	unsigned long addr = (unsigned long)lineinfo_target_with_arg;
+
+	sprint_symbol(buf, addr);
+	KUNIT_EXPECT_TRUE_MSG(test, has_lineinfo(buf),
+			      "No lineinfo in: %s", buf);
+}
+
+static void test_inline_function(struct kunit *test)
+{
+	char *buf = alloc_sym_buf(test);
+	unsigned long addr = (unsigned long)lineinfo_inline_caller;
+
+	sprint_symbol(buf, addr);
+	KUNIT_EXPECT_TRUE_MSG(test, has_lineinfo(buf),
+			      "No lineinfo for inline caller in: %s", buf);
+	KUNIT_EXPECT_TRUE_MSG(test,
+			      lineinfo_contains_file(buf, "lineinfo_kunit.c"),
+			      "Wrong file in: %s", buf);
+}
+
+static void test_short_function(struct kunit *test)
+{
+	char *buf = alloc_sym_buf(test);
+	unsigned long addr = (unsigned long)lineinfo_target_short;
+
+	sprint_symbol(buf, addr);
+	KUNIT_EXPECT_TRUE_MSG(test, has_lineinfo(buf),
+			      "No lineinfo for short function in: %s", buf);
+}
+
+static void test_many_lines_function(struct kunit *test)
+{
+	char *buf = alloc_sym_buf(test);
+	unsigned long addr = (unsigned long)lineinfo_target_many_lines;
+	unsigned int line;
+
+	sprint_symbol(buf, addr);
+	KUNIT_EXPECT_TRUE_MSG(test, has_lineinfo(buf),
+			      "No lineinfo in: %s", buf);
+	line = extract_line(buf);
+	KUNIT_EXPECT_GT_MSG(test, line, (unsigned int)0,
+			    "Line number should be > 0 in: %s", buf);
+}
+
+/* --------------- Group B: Deep call chain --------------- */
+
+typedef int (*chain_fn_t)(void);
+
+static void test_deep_call_chain(struct kunit *test)
+{
+	static const chain_fn_t chain_fns[] = {
+		lineinfo_chain_1,  lineinfo_chain_2,
+		lineinfo_chain_3,  lineinfo_chain_4,
+		lineinfo_chain_5,  lineinfo_chain_6,
+		lineinfo_chain_7,  lineinfo_chain_8,
+		lineinfo_chain_9,  lineinfo_chain_10,
+	};
+	char *buf = alloc_sym_buf(test);
+	int i, found = 0;
+
+	/* Call chain to prevent dead-code elimination */
+	KUNIT_ASSERT_EQ(test, lineinfo_chain_1(), 10);
+
+	for (i = 0; i < ARRAY_SIZE(chain_fns); i++) {
+		unsigned long addr = (unsigned long)chain_fns[i];
+
+		sprint_symbol(buf, addr);
+		if (has_lineinfo(buf))
+			found++;
+	}
+
+	/*
+	 * Not every tiny function gets DWARF line info (compiler may
+	 * omit it for very small stubs), but at least some should.
+	 */
+	KUNIT_EXPECT_GT_MSG(test, found, 0,
+			    "None of the 10 chain functions had lineinfo");
+}
+
+/* --------------- Group C: sprint_symbol API variants --------------- */
+
+static void test_sprint_symbol_format(struct kunit *test)
+{
+	char *buf = alloc_sym_buf(test);
+	unsigned long addr = (unsigned long)lineinfo_target_normal;
+
+	sprint_symbol(buf, addr);
+
+	/* Should contain +0x and /0x for offset/size */
+	KUNIT_EXPECT_NOT_NULL_MSG(test, strstr(buf, "+0x"),
+				  "Missing offset in: %s", buf);
+	KUNIT_EXPECT_NOT_NULL_MSG(test, strstr(buf, "/0x"),
+				  "Missing size in: %s", buf);
+	KUNIT_EXPECT_TRUE_MSG(test, has_lineinfo(buf),
+			      "No lineinfo in: %s", buf);
+}
+
+static void test_sprint_backtrace(struct kunit *test)
+{
+	char *buf = alloc_sym_buf(test);
+	unsigned long addr = (unsigned long)lineinfo_target_normal;
+
+	/* sprint_backtrace subtracts 1 internally to handle tail calls */
+	sprint_backtrace(buf, addr + 1);
+	KUNIT_EXPECT_TRUE_MSG(test, has_lineinfo(buf),
+			      "No lineinfo in backtrace: %s", buf);
+	KUNIT_EXPECT_TRUE_MSG(test,
+			      lineinfo_contains_file(buf, "lineinfo_kunit.c"),
+			      "Wrong file in backtrace: %s", buf);
+}
+
+static void test_sprint_backtrace_build_id(struct kunit *test)
+{
+	char *buf = alloc_sym_buf(test);
+	unsigned long addr = (unsigned long)lineinfo_target_normal;
+
+	sprint_backtrace_build_id(buf, addr + 1);
+	KUNIT_EXPECT_TRUE_MSG(test, has_lineinfo(buf),
+			      "No lineinfo in backtrace_build_id: %s", buf);
+}
+
+static void test_sprint_symbol_no_offset(struct kunit *test)
+{
+	char *buf = alloc_sym_buf(test);
+	unsigned long addr = (unsigned long)lineinfo_target_normal;
+
+	sprint_symbol_no_offset(buf, addr);
+	/* No "+0x" in output */
+	KUNIT_EXPECT_NULL_MSG(test, strstr(buf, "+0x"),
+			      "Unexpected offset in no_offset: %s", buf);
+	KUNIT_EXPECT_TRUE_MSG(test, has_lineinfo(buf),
+			      "No lineinfo in no_offset: %s", buf);
+}
+
+/* --------------- Group D: printk format specifiers --------------- */
+
+static void test_pS_format(struct kunit *test)
+{
+	char *buf = alloc_sym_buf(test);
+	void *addr = lineinfo_target_normal;
+
+	snprintf(buf, KSYM_SYMBOL_LEN, "%pS", addr);
+	KUNIT_EXPECT_TRUE_MSG(test, has_lineinfo(buf),
+			      "No lineinfo in %%pS: %s", buf);
+}
+
+static void test_pBb_format(struct kunit *test)
+{
+	char *buf = alloc_sym_buf(test);
+	/*
+	 * %pBb uses sprint_backtrace_build_id which subtracts 1 from the
+	 * address, so pass addr+1 to resolve back to the function.
+	 */
+	void *addr = (void *)((unsigned long)lineinfo_target_normal + 1);
+
+	snprintf(buf, KSYM_SYMBOL_LEN, "%pBb", addr);
+	KUNIT_EXPECT_TRUE_MSG(test, has_lineinfo(buf),
+			      "No lineinfo in %%pBb: %s", buf);
+}
+
+static void test_pSR_format(struct kunit *test)
+{
+	char *buf = alloc_sym_buf(test);
+	void *addr = lineinfo_target_normal;
+
+	snprintf(buf, KSYM_SYMBOL_LEN, "%pSR", addr);
+	KUNIT_EXPECT_TRUE_MSG(test, has_lineinfo(buf),
+			      "No lineinfo in %%pSR: %s", buf);
+}
+
+/* --------------- Group E: Address edge cases --------------- */
+
+static void test_symbol_start_addr(struct kunit *test)
+{
+	char *buf = alloc_sym_buf(test);
+	unsigned long addr = (unsigned long)lineinfo_target_normal;
+
+	sprint_symbol(buf, addr);
+	KUNIT_EXPECT_NOT_NULL_MSG(test, strstr(buf, "+0x0/"),
+				  "Expected +0x0/ at function start: %s", buf);
+	KUNIT_EXPECT_TRUE_MSG(test, has_lineinfo(buf),
+			      "No lineinfo at function start: %s", buf);
+}
+
+static void test_symbol_nonzero_offset(struct kunit *test)
+{
+	char *buf = alloc_sym_buf(test);
+	unsigned long addr = (unsigned long)lineinfo_target_normal;
+
+	/*
+	 * sprint_backtrace subtracts 1 internally.
+	 * Passing addr+2 resolves to addr+1 which is inside the function
+	 * at a non-zero offset.
+	 */
+	sprint_backtrace(buf, addr + 2);
+	KUNIT_EXPECT_TRUE_MSG(test,
+			      strnstr(buf, "lineinfo_target_normal",
+				      KSYM_SYMBOL_LEN) != NULL,
+			      "Didn't resolve to expected function: %s", buf);
+	KUNIT_EXPECT_TRUE_MSG(test, has_lineinfo(buf),
+			      "No lineinfo at non-zero offset: %s", buf);
+}
+
+static void test_unknown_address(struct kunit *test)
+{
+	char *buf = alloc_sym_buf(test);
+
+	sprint_symbol(buf, 1UL);
+	/* Should be "0x1" with no lineinfo */
+	KUNIT_EXPECT_NOT_NULL_MSG(test, strstr(buf, "0x1"),
+				  "Expected hex address for bogus addr: %s", buf);
+	KUNIT_EXPECT_FALSE_MSG(test, has_lineinfo(buf),
+			       "Unexpected lineinfo for bogus addr: %s", buf);
+}
+
+static void test_kernel_function_lineinfo(struct kunit *test)
+{
+	char *buf = alloc_sym_buf(test);
+	unsigned long addr = (unsigned long)sprint_symbol;
+
+	sprint_symbol(buf, addr);
+	KUNIT_EXPECT_TRUE_MSG(test, has_lineinfo(buf),
+			      "No lineinfo for sprint_symbol: %s", buf);
+	KUNIT_EXPECT_TRUE_MSG(test,
+			      lineinfo_contains_file(buf, "kallsyms.c"),
+			      "Expected kallsyms.c in: %s", buf);
+}
+
+static void test_assembly_no_lineinfo(struct kunit *test)
+{
+#if IS_BUILTIN(CONFIG_LINEINFO_KUNIT_TEST)
+	char *buf = alloc_sym_buf(test);
+	unsigned long addr = (unsigned long)_text;
+
+	sprint_symbol(buf, addr);
+	/*
+	 * _text is typically an asm entry point with no DWARF line info.
+	 * If it has lineinfo, it's a C-based entry — skip in that case.
+	 */
+	if (has_lineinfo(buf))
+		kunit_skip(test, "_text has lineinfo (C entry?): %s", buf);
+
+	KUNIT_EXPECT_FALSE_MSG(test, has_lineinfo(buf),
+			       "Unexpected lineinfo for asm symbol: %s", buf);
+#else
+	kunit_skip(test, "_text not accessible from modules");
+#endif
+}
+
+/* --------------- Group F: Module path --------------- */
+
+static void test_module_function_lineinfo(struct kunit *test)
+{
+	char *buf = alloc_sym_buf(test);
+	unsigned long addr = (unsigned long)lineinfo_target_normal;
+
+	if (!IS_MODULE(CONFIG_LINEINFO_KUNIT_TEST)) {
+		kunit_skip(test, "Test only meaningful when built as module");
+		return;
+	}
+
+	sprint_symbol(buf, addr);
+	KUNIT_EXPECT_NOT_NULL_MSG(test,
+				  strstr(buf, "[lineinfo_kunit"),
+				  "Missing module name in: %s", buf);
+	KUNIT_EXPECT_TRUE_MSG(test, has_lineinfo(buf),
+			      "No lineinfo for module function: %s", buf);
+	KUNIT_EXPECT_TRUE_MSG(test,
+			      lineinfo_contains_file(buf, "lineinfo_kunit.c"),
+			      "Wrong file for module function: %s", buf);
+}
+
+/* --------------- Group G: Stress --------------- */
+
+struct lineinfo_stress_data {
+	unsigned long addr;
+	atomic_t failures;
+};
+
+static void lineinfo_stress_fn(void *info)
+{
+	struct lineinfo_stress_data *data = info;
+	char buf[KSYM_SYMBOL_LEN];
+	int i;
+
+	for (i = 0; i < 100; i++) {
+		sprint_symbol(buf, data->addr);
+		if (!has_lineinfo(buf))
+			atomic_inc(&data->failures);
+	}
+}
+
+static void test_concurrent_sprint_symbol(struct kunit *test)
+{
+	struct lineinfo_stress_data data;
+
+	data.addr = (unsigned long)lineinfo_target_normal;
+	atomic_set(&data.failures, 0);
+
+	on_each_cpu(lineinfo_stress_fn, &data, 1);
+
+	KUNIT_EXPECT_EQ_MSG(test, atomic_read(&data.failures), 0,
+			    "Concurrent lineinfo failures detected");
+}
+
+static void test_rapid_sprint_symbol(struct kunit *test)
+{
+	char *buf = alloc_sym_buf(test);
+	unsigned long addr = (unsigned long)lineinfo_target_normal;
+	int i, failures = 0;
+
+	for (i = 0; i < 1000; i++) {
+		sprint_symbol(buf, addr);
+		if (!has_lineinfo(buf))
+			failures++;
+	}
+
+	KUNIT_EXPECT_EQ_MSG(test, failures, 0,
+			    "Rapid sprint_symbol failures: %d/1000", failures);
+}
+
+/* --------------- Group H: Safety and plausibility --------------- */
+
+static void test_line_number_plausible(struct kunit *test)
+{
+	char *buf = alloc_sym_buf(test);
+	unsigned long addr = (unsigned long)lineinfo_target_normal;
+	unsigned int line;
+
+	sprint_symbol(buf, addr);
+	KUNIT_ASSERT_TRUE(test, has_lineinfo(buf));
+
+	line = extract_line(buf);
+	KUNIT_EXPECT_GT_MSG(test, line, (unsigned int)0,
+			    "Line number should be > 0");
+	KUNIT_EXPECT_LT_MSG(test, line, (unsigned int)10000,
+			    "Line number %u implausibly large for this file",
+			    line);
+}
+
+static void test_buffer_no_overflow(struct kunit *test)
+{
+	const size_t canary_size = 16;
+	char *buf;
+	int i;
+
+	buf = kunit_kzalloc(test, KSYM_SYMBOL_LEN + canary_size, GFP_KERNEL);
+	KUNIT_ASSERT_NOT_NULL(test, buf);
+
+	/* Fill canary area past KSYM_SYMBOL_LEN with 0xAA */
+	memset(buf + KSYM_SYMBOL_LEN, 0xAA, canary_size);
+
+	sprint_symbol(buf, (unsigned long)lineinfo_target_normal);
+
+	/* Verify canary bytes are untouched */
+	for (i = 0; i < canary_size; i++) {
+		KUNIT_EXPECT_EQ_MSG(test,
+				    (unsigned char)buf[KSYM_SYMBOL_LEN + i],
+				    (unsigned char)0xAA,
+				    "Buffer overflow at offset %d past KSYM_SYMBOL_LEN",
+				    i);
+	}
+}
+
+static void test_dump_stack_no_crash(struct kunit *test)
+{
+	/* Just verify dump_stack() completes without panic */
+	dump_stack();
+	KUNIT_SUCCEED(test);
+}
+
+static void test_sprint_symbol_build_id(struct kunit *test)
+{
+	char *buf = alloc_sym_buf(test);
+	unsigned long addr = (unsigned long)lineinfo_target_normal;
+
+	sprint_symbol_build_id(buf, addr);
+	KUNIT_EXPECT_TRUE_MSG(test, has_lineinfo(buf),
+			      "No lineinfo in sprint_symbol_build_id: %s", buf);
+}
+
+static void test_sleb128_edge_cases(struct kunit *test)
+{
+	u32 pos;
+	int32_t result;
+
+	/* Value 0: single byte 0x00 */
+	{
+		static const u8 data[] = { 0x00 };
+
+		pos = 0;
+		result = lineinfo_read_sleb128(data, &pos, sizeof(data));
+		KUNIT_EXPECT_EQ(test, result, (int32_t)0);
+		KUNIT_EXPECT_EQ(test, pos, (u32)1);
+	}
+
+	/* Value -1: single byte 0x7F */
+	{
+		static const u8 data[] = { 0x7f };
+
+		pos = 0;
+		result = lineinfo_read_sleb128(data, &pos, sizeof(data));
+		KUNIT_EXPECT_EQ(test, result, (int32_t)-1);
+		KUNIT_EXPECT_EQ(test, pos, (u32)1);
+	}
+
+	/* Value 1: single byte 0x01 */
+	{
+		static const u8 data[] = { 0x01 };
+
+		pos = 0;
+		result = lineinfo_read_sleb128(data, &pos, sizeof(data));
+		KUNIT_EXPECT_EQ(test, result, (int32_t)1);
+		KUNIT_EXPECT_EQ(test, pos, (u32)1);
+	}
+
+	/* Value -64: single byte 0x40 */
+	{
+		static const u8 data[] = { 0x40 };
+
+		pos = 0;
+		result = lineinfo_read_sleb128(data, &pos, sizeof(data));
+		KUNIT_EXPECT_EQ(test, result, (int32_t)-64);
+		KUNIT_EXPECT_EQ(test, pos, (u32)1);
+	}
+
+	/* Value 63: single byte 0x3F */
+	{
+		static const u8 data[] = { 0x3f };
+
+		pos = 0;
+		result = lineinfo_read_sleb128(data, &pos, sizeof(data));
+		KUNIT_EXPECT_EQ(test, result, (int32_t)63);
+		KUNIT_EXPECT_EQ(test, pos, (u32)1);
+	}
+
+	/* Value -128: two bytes 0x80 0x7F */
+	{
+		static const u8 data[] = { 0x80, 0x7f };
+
+		pos = 0;
+		result = lineinfo_read_sleb128(data, &pos, sizeof(data));
+		KUNIT_EXPECT_EQ(test, result, (int32_t)-128);
+		KUNIT_EXPECT_EQ(test, pos, (u32)2);
+	}
+}
+
+static void test_uleb128_edge_cases(struct kunit *test)
+{
+	u32 pos, result;
+
+	/* Value 0: single byte 0x00 */
+	{
+		static const u8 data[] = { 0x00 };
+
+		pos = 0;
+		result = lineinfo_read_uleb128(data, &pos, sizeof(data));
+		KUNIT_EXPECT_EQ(test, result, (u32)0);
+		KUNIT_EXPECT_EQ(test, pos, (u32)1);
+	}
+
+	/* Value 127: single byte 0x7F */
+	{
+		static const u8 data[] = { 0x7F };
+
+		pos = 0;
+		result = lineinfo_read_uleb128(data, &pos, sizeof(data));
+		KUNIT_EXPECT_EQ(test, result, (u32)127);
+		KUNIT_EXPECT_EQ(test, pos, (u32)1);
+	}
+
+	/* Value 128: two bytes 0x80 0x01 */
+	{
+		static const u8 data[] = { 0x80, 0x01 };
+
+		pos = 0;
+		result = lineinfo_read_uleb128(data, &pos, sizeof(data));
+		KUNIT_EXPECT_EQ(test, result, (u32)128);
+		KUNIT_EXPECT_EQ(test, pos, (u32)2);
+	}
+
+	/* Max u32 0xFFFFFFFF: 5 bytes */
+	{
+		static const u8 data[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0x0F };
+
+		pos = 0;
+		result = lineinfo_read_uleb128(data, &pos, sizeof(data));
+		KUNIT_EXPECT_EQ(test, result, (u32)0xFFFFFFFF);
+		KUNIT_EXPECT_EQ(test, pos, (u32)5);
+	}
+
+	/* Truncated input: pos >= end returns 0 */
+	{
+		static const u8 data[] = { 0x80 };
+
+		pos = 0;
+		result = lineinfo_read_uleb128(data, &pos, 0);
+		KUNIT_EXPECT_EQ_MSG(test, result, (u32)0,
+				    "Expected 0 for empty input");
+	}
+
+	/* Truncated mid-varint: continuation byte but end reached */
+	{
+		static const u8 data[] = { 0x80 };
+
+		pos = 0;
+		result = lineinfo_read_uleb128(data, &pos, 1);
+		KUNIT_EXPECT_EQ_MSG(test, result, (u32)0,
+				    "Expected 0 for truncated varint");
+		KUNIT_EXPECT_EQ(test, pos, (u32)1);
+	}
+}
+
+static void test_line_number_accuracy(struct kunit *test)
+{
+	char *buf = alloc_sym_buf(test);
+	unsigned long addr = (unsigned long)lineinfo_target_normal;
+	unsigned int line;
+
+	sprint_symbol(buf, addr);
+	KUNIT_ASSERT_TRUE(test, has_lineinfo(buf));
+
+	line = extract_line(buf);
+
+	/*
+	 * lineinfo_target_normal is defined around line 103-107.
+	 * Allow wide range: KASAN instrumentation and module lineinfo
+	 * address mapping can shift the reported line significantly.
+	 */
+	KUNIT_EXPECT_GE_MSG(test, line, (unsigned int)50,
+			    "Line %u too low for lineinfo_target_normal", line);
+	KUNIT_EXPECT_LE_MSG(test, line, (unsigned int)300,
+			    "Line %u too high for lineinfo_target_normal", line);
+}
+
+static void test_many_lines_mid_function(struct kunit *test)
+{
+	char *buf = alloc_sym_buf(test);
+	unsigned long addr = (unsigned long)lineinfo_target_many_lines;
+	unsigned int line;
+	unsigned long mid_addr;
+
+	/* Get function size from sprint_symbol output */
+	sprint_symbol(buf, addr);
+	KUNIT_ASSERT_TRUE(test, has_lineinfo(buf));
+
+	/* Try an address 8 bytes into the function (past prologue) */
+	mid_addr = addr + 8;
+	sprint_symbol(buf, mid_addr);
+
+	/*
+	 * Should still resolve to lineinfo_target_many_lines.
+	 * Lineinfo should be present with a plausible line number.
+	 */
+	KUNIT_EXPECT_TRUE_MSG(test,
+			      strnstr(buf, "lineinfo_target_many_lines",
+				      KSYM_SYMBOL_LEN) != NULL,
+			      "Mid-function addr resolved to wrong symbol: %s",
+			      buf);
+	if (has_lineinfo(buf)) {
+		line = extract_line(buf);
+		KUNIT_EXPECT_GE_MSG(test, line, (unsigned int)50,
+				    "Line %u too low for mid-function", line);
+		KUNIT_EXPECT_LE_MSG(test, line, (unsigned int)700,
+				    "Line %u too high for mid-function", line);
+	}
+}
+
+/* --------------- Suite registration --------------- */
+
+static struct kunit_case lineinfo_test_cases[] = {
+	/* Group A: Basic lineinfo presence */
+	KUNIT_CASE(test_normal_function),
+	KUNIT_CASE(test_static_function),
+	KUNIT_CASE(test_noinline_function),
+	KUNIT_CASE(test_inline_function),
+	KUNIT_CASE(test_short_function),
+	KUNIT_CASE(test_many_lines_function),
+	/* Group B: Deep call chain */
+	KUNIT_CASE(test_deep_call_chain),
+	/* Group C: sprint_symbol API variants */
+	KUNIT_CASE(test_sprint_symbol_format),
+	KUNIT_CASE(test_sprint_backtrace),
+	KUNIT_CASE(test_sprint_backtrace_build_id),
+	KUNIT_CASE(test_sprint_symbol_no_offset),
+	/* Group D: printk format specifiers */
+	KUNIT_CASE(test_pS_format),
+	KUNIT_CASE(test_pBb_format),
+	KUNIT_CASE(test_pSR_format),
+	/* Group E: Address edge cases */
+	KUNIT_CASE(test_symbol_start_addr),
+	KUNIT_CASE(test_symbol_nonzero_offset),
+	KUNIT_CASE(test_unknown_address),
+	KUNIT_CASE(test_kernel_function_lineinfo),
+	KUNIT_CASE(test_assembly_no_lineinfo),
+	/* Group F: Module path */
+	KUNIT_CASE(test_module_function_lineinfo),
+	/* Group G: Stress */
+	KUNIT_CASE_SLOW(test_concurrent_sprint_symbol),
+	KUNIT_CASE_SLOW(test_rapid_sprint_symbol),
+	/* Group H: Safety and plausibility */
+	KUNIT_CASE(test_line_number_plausible),
+	KUNIT_CASE(test_buffer_no_overflow),
+	KUNIT_CASE(test_dump_stack_no_crash),
+	KUNIT_CASE(test_sprint_symbol_build_id),
+	/* Group I: Encoding/decoding and accuracy */
+	KUNIT_CASE(test_sleb128_edge_cases),
+	KUNIT_CASE(test_uleb128_edge_cases),
+	KUNIT_CASE(test_line_number_accuracy),
+	KUNIT_CASE(test_many_lines_mid_function),
+	{}
+};
+
+static struct kunit_suite lineinfo_test_suite = {
+	.name = "lineinfo",
+	.test_cases = lineinfo_test_cases,
+};
+kunit_test_suites(&lineinfo_test_suite);
+
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("KUnit tests for kallsyms lineinfo");
+MODULE_AUTHOR("Sasha Levin");
diff --git a/lib/tests/seq_buf_kunit.c b/lib/tests/seq_buf_kunit.c
index 8a01579a978e..eb466386bbef 100644
--- a/lib/tests/seq_buf_kunit.c
+++ b/lib/tests/seq_buf_kunit.c
@@ -184,6 +184,38 @@ static void seq_buf_get_buf_commit_test(struct kunit *test)
 	KUNIT_EXPECT_TRUE(test, seq_buf_has_overflowed(&s));
 }
 
+static void seq_buf_putmem_hex_test(struct kunit *test)
+{
+	DECLARE_SEQ_BUF(s, 24);
+	const u8 data[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 };
+#ifdef __BIG_ENDIAN
+	const char *expected = "0001020304050607 0809 ";
+#else
+	const char *expected = "0706050403020100 0908 ";
+#endif
+
+	KUNIT_EXPECT_EQ(test, seq_buf_putmem_hex(&s, data, sizeof(data)), 0);
+	KUNIT_EXPECT_FALSE(test, seq_buf_has_overflowed(&s));
+	KUNIT_EXPECT_EQ(test, seq_buf_used(&s), strlen(expected));
+	KUNIT_EXPECT_STREQ(test, seq_buf_str(&s), expected);
+}
+
+static void seq_buf_putmem_hex_overflow_test(struct kunit *test)
+{
+	DECLARE_SEQ_BUF(s, 20);
+	const u8 data[] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 };
+#ifdef __BIG_ENDIAN
+	const char *expected = "0001020304050607 ";
+#else
+	const char *expected = "0706050403020100 ";
+#endif
+
+	KUNIT_EXPECT_EQ(test, seq_buf_putmem_hex(&s, data, sizeof(data)), -1);
+	KUNIT_EXPECT_TRUE(test, seq_buf_has_overflowed(&s));
+	KUNIT_EXPECT_EQ(test, seq_buf_used(&s), 20);
+	KUNIT_EXPECT_STREQ(test, seq_buf_str(&s), expected);
+}
+
 static struct kunit_case seq_buf_test_cases[] = {
 	KUNIT_CASE(seq_buf_init_test),
 	KUNIT_CASE(seq_buf_declare_test),
@@ -194,6 +226,8 @@ static struct kunit_case seq_buf_test_cases[] = {
 	KUNIT_CASE(seq_buf_printf_test),
 	KUNIT_CASE(seq_buf_printf_overflow_test),
 	KUNIT_CASE(seq_buf_get_buf_commit_test),
+	KUNIT_CASE(seq_buf_putmem_hex_test),
+	KUNIT_CASE(seq_buf_putmem_hex_overflow_test),
 	{}
 };
 
diff --git a/lib/tests/string_helpers_kunit.c b/lib/tests/string_helpers_kunit.c
index c853046183d2..9fbe91079c7e 100644
--- a/lib/tests/string_helpers_kunit.c
+++ b/lib/tests/string_helpers_kunit.c
@@ -5,11 +5,16 @@
 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
 
 #include <kunit/test.h>
+
 #include <linux/array_size.h>
-#include <linux/kernel.h>
+#include <linux/bug.h>
+#include <linux/limits.h>
+#include <linux/module.h>
 #include <linux/random.h>
-#include <linux/string.h>
+#include <linux/slab.h>
+#include <linux/sprintf.h>
 #include <linux/string_helpers.h>
+#include <linux/types.h>
 
 static void test_string_check_buf(struct kunit *test,
 				  const char *name, unsigned int flags,
@@ -601,6 +606,11 @@ static void test_unescape(struct kunit *test)
 		test_string_unescape(test, "unescape", i, false);
 	test_string_unescape(test, "unescape inplace",
 			     get_random_u32_below(UNESCAPE_ALL_MASK + 1), true);
+}
+
+static void test_escape(struct kunit *test)
+{
+	unsigned int i;
 
 	/* Without dictionary */
 	for (i = 0; i < ESCAPE_ALL_MASK + 1; i++)
@@ -615,6 +625,7 @@ static struct kunit_case string_helpers_test_cases[] = {
 	KUNIT_CASE(test_get_size),
 	KUNIT_CASE(test_upper_lower),
 	KUNIT_CASE(test_unescape),
+	KUNIT_CASE(test_escape),
 	{}
 };
 
diff --git a/localversion-next b/localversion-next
new file mode 100644
index 000000000000..694f89dee69d
--- /dev/null
+++ b/localversion-next
@@ -0,0 +1 @@
+-next-20260427
diff --git a/mm/Kconfig b/mm/Kconfig
index e8bf1e9e6ad9..6c2217ea3523 100644
--- a/mm/Kconfig
+++ b/mm/Kconfig
@@ -1303,7 +1303,7 @@ config ARCH_HAS_PTE_SPECIAL
 	bool
 
 config MAPPING_DIRTY_HELPERS
-        bool
+	bool
 
 config KMAP_LOCAL
 	bool
@@ -1434,7 +1434,7 @@ config ARCH_HAS_USER_SHADOW_STACK
 	bool
 	help
 	  The architecture has hardware support for userspace shadow call
-          stacks (eg, x86 CET, arm64 GCS or RISC-V Zicfiss).
+	  stacks (eg, x86 CET, arm64 GCS or RISC-V Zicfiss).
 
 config HAVE_ARCH_TLB_REMOVE_TABLE
 	def_bool n
diff --git a/mm/damon/lru_sort.c b/mm/damon/lru_sort.c
index 554559d72976..8494040b1ee4 100644
--- a/mm/damon/lru_sort.c
+++ b/mm/damon/lru_sort.c
@@ -161,15 +161,6 @@ module_param(monitor_region_end, ulong, 0600);
  */
 static unsigned long addr_unit __read_mostly = 1;
 
-/*
- * PID of the DAMON thread
- *
- * If DAMON_LRU_SORT is enabled, this becomes the PID of the worker thread.
- * Else, -1.
- */
-static int kdamond_pid __read_mostly = -1;
-module_param(kdamond_pid, int, 0400);
-
 static struct damos_stat damon_lru_sort_hot_stat;
 DEFINE_DAMON_MODULES_DAMOS_STATS_PARAMS(damon_lru_sort_hot_stat,
 		lru_sort_tried_hot_regions, lru_sorted_hot_regions,
@@ -386,12 +377,8 @@ static int damon_lru_sort_turn(bool on)
 {
 	int err;
 
-	if (!on) {
-		err = damon_stop(&ctx, 1);
-		if (!err)
-			kdamond_pid = -1;
-		return err;
-	}
+	if (!on)
+		return damon_stop(&ctx, 1);
 
 	err = damon_lru_sort_apply_parameters();
 	if (err)
@@ -400,9 +387,6 @@ static int damon_lru_sort_turn(bool on)
 	err = damon_start(&ctx, 1, true);
 	if (err)
 		return err;
-	kdamond_pid = damon_kdamond_pid(ctx);
-	if (kdamond_pid < 0)
-		return kdamond_pid;
 	return damon_call(ctx, &call_control);
 }
 
@@ -430,42 +414,83 @@ module_param_cb(addr_unit, &addr_unit_param_ops, &addr_unit, 0600);
 MODULE_PARM_DESC(addr_unit,
 	"Scale factor for DAMON_LRU_SORT to ops address conversion (default: 1)");
 
+static bool damon_lru_sort_enabled(void)
+{
+	if (!ctx)
+		return false;
+	return damon_is_running(ctx);
+}
+
 static int damon_lru_sort_enabled_store(const char *val,
 		const struct kernel_param *kp)
 {
-	bool is_enabled = enabled;
-	bool enable;
 	int err;
 
-	err = kstrtobool(val, &enable);
+	err = kstrtobool(val, &enabled);
 	if (err)
 		return err;
 
-	if (is_enabled == enable)
+	if (damon_lru_sort_enabled() == enabled)
 		return 0;
 
 	/* Called before init function.  The function will handle this. */
 	if (!damon_initialized())
-		goto set_param_out;
+		return 0;
 
-	err = damon_lru_sort_turn(enable);
-	if (err)
-		return err;
+	return damon_lru_sort_turn(enabled);
+}
 
-set_param_out:
-	enabled = enable;
-	return err;
+static int damon_lru_sort_enabled_load(char *buffer,
+		const struct kernel_param *kp)
+{
+	return sprintf(buffer, "%c\n", damon_lru_sort_enabled() ? 'Y' : 'N');
 }
 
 static const struct kernel_param_ops enabled_param_ops = {
 	.set = damon_lru_sort_enabled_store,
-	.get = param_get_bool,
+	.get = damon_lru_sort_enabled_load,
 };
 
 module_param_cb(enabled, &enabled_param_ops, &enabled, 0600);
 MODULE_PARM_DESC(enabled,
 	"Enable or disable DAMON_LRU_SORT (default: disabled)");
 
+static int damon_lru_sort_kdamond_pid_store(const char *val,
+		const struct kernel_param *kp)
+{
+	/*
+	 * kdamond_pid is read-only, but kernel command line could write it.
+	 * Do nothing here.
+	 */
+	return 0;
+}
+
+static int damon_lru_sort_kdamond_pid_load(char *buffer,
+		const struct kernel_param *kp)
+{
+	int kdamond_pid = -1;
+
+	if (ctx) {
+		kdamond_pid = damon_kdamond_pid(ctx);
+		if (kdamond_pid < 0)
+			kdamond_pid = -1;
+	}
+	return sprintf(buffer, "%d\n", kdamond_pid);
+}
+
+static const struct kernel_param_ops kdamond_pid_param_ops = {
+	.set = damon_lru_sort_kdamond_pid_store,
+	.get = damon_lru_sort_kdamond_pid_load,
+};
+
+/*
+ * PID of the DAMON thread
+ *
+ * If DAMON_LRU_SORT is enabled, this becomes the PID of the worker thread.
+ * Else, -1.
+ */
+module_param_cb(kdamond_pid, &kdamond_pid_param_ops, NULL, 0400);
+
 static int __init damon_lru_sort_init(void)
 {
 	int err;
diff --git a/mm/damon/reclaim.c b/mm/damon/reclaim.c
index 86da14778658..fe7fce26cf6c 100644
--- a/mm/damon/reclaim.c
+++ b/mm/damon/reclaim.c
@@ -144,15 +144,6 @@ static unsigned long addr_unit __read_mostly = 1;
 static bool skip_anon __read_mostly;
 module_param(skip_anon, bool, 0600);
 
-/*
- * PID of the DAMON thread
- *
- * If DAMON_RECLAIM is enabled, this becomes the PID of the worker thread.
- * Else, -1.
- */
-static int kdamond_pid __read_mostly = -1;
-module_param(kdamond_pid, int, 0400);
-
 static struct damos_stat damon_reclaim_stat;
 DEFINE_DAMON_MODULES_DAMOS_STATS_PARAMS(damon_reclaim_stat,
 		reclaim_tried_regions, reclaimed_regions, quota_exceeds);
@@ -288,12 +279,8 @@ static int damon_reclaim_turn(bool on)
 {
 	int err;
 
-	if (!on) {
-		err = damon_stop(&ctx, 1);
-		if (!err)
-			kdamond_pid = -1;
-		return err;
-	}
+	if (!on)
+		return damon_stop(&ctx, 1);
 
 	err = damon_reclaim_apply_parameters();
 	if (err)
@@ -302,9 +289,6 @@ static int damon_reclaim_turn(bool on)
 	err = damon_start(&ctx, 1, true);
 	if (err)
 		return err;
-	kdamond_pid = damon_kdamond_pid(ctx);
-	if (kdamond_pid < 0)
-		return kdamond_pid;
 	return damon_call(ctx, &call_control);
 }
 
@@ -332,42 +316,83 @@ module_param_cb(addr_unit, &addr_unit_param_ops, &addr_unit, 0600);
 MODULE_PARM_DESC(addr_unit,
 	"Scale factor for DAMON_RECLAIM to ops address conversion (default: 1)");
 
+static bool damon_reclaim_enabled(void)
+{
+	if (!ctx)
+		return false;
+	return damon_is_running(ctx);
+}
+
 static int damon_reclaim_enabled_store(const char *val,
 		const struct kernel_param *kp)
 {
-	bool is_enabled = enabled;
-	bool enable;
 	int err;
 
-	err = kstrtobool(val, &enable);
+	err = kstrtobool(val, &enabled);
 	if (err)
 		return err;
 
-	if (is_enabled == enable)
+	if (damon_reclaim_enabled() == enabled)
 		return 0;
 
 	/* Called before init function.  The function will handle this. */
 	if (!damon_initialized())
-		goto set_param_out;
+		return 0;
 
-	err = damon_reclaim_turn(enable);
-	if (err)
-		return err;
+	return damon_reclaim_turn(enabled);
+}
 
-set_param_out:
-	enabled = enable;
-	return err;
+static int damon_reclaim_enabled_load(char *buffer,
+		const struct kernel_param *kp)
+{
+	return sprintf(buffer, "%c\n", damon_reclaim_enabled() ? 'Y' : 'N');
 }
 
 static const struct kernel_param_ops enabled_param_ops = {
 	.set = damon_reclaim_enabled_store,
-	.get = param_get_bool,
+	.get = damon_reclaim_enabled_load,
 };
 
 module_param_cb(enabled, &enabled_param_ops, &enabled, 0600);
 MODULE_PARM_DESC(enabled,
 	"Enable or disable DAMON_RECLAIM (default: disabled)");
 
+static int damon_reclaim_kdamond_pid_store(const char *val,
+		const struct kernel_param *kp)
+{
+	/*
+	 * kdamond_pid is read-only, but kernel command line could write it.
+	 * Do nothing here.
+	 */
+	return 0;
+}
+
+static int damon_reclaim_kdamond_pid_load(char *buffer,
+		const struct kernel_param *kp)
+{
+	int kdamond_pid = -1;
+
+	if (ctx) {
+		kdamond_pid = damon_kdamond_pid(ctx);
+		if (kdamond_pid < 0)
+			kdamond_pid = -1;
+	}
+	return sprintf(buffer, "%d\n", kdamond_pid);
+}
+
+static const struct kernel_param_ops kdamond_pid_param_ops = {
+	.set = damon_reclaim_kdamond_pid_store,
+	.get = damon_reclaim_kdamond_pid_load,
+};
+
+/*
+ * PID of the DAMON thread
+ *
+ * If DAMON_RECLAIM is enabled, this becomes the PID of the worker thread.
+ * Else, -1.
+ */
+module_param_cb(kdamond_pid, &kdamond_pid_param_ops, NULL, 0400);
+
 static int __init damon_reclaim_init(void)
 {
 	int err;
diff --git a/mm/damon/stat.c b/mm/damon/stat.c
index 99ba346f9e32..3951b762cbdd 100644
--- a/mm/damon/stat.c
+++ b/mm/damon/stat.c
@@ -19,14 +19,17 @@
 static int damon_stat_enabled_store(
 		const char *val, const struct kernel_param *kp);
 
+static int damon_stat_enabled_load(char *buffer,
+		const struct kernel_param *kp);
+
 static const struct kernel_param_ops enabled_param_ops = {
 	.set = damon_stat_enabled_store,
-	.get = param_get_bool,
+	.get = damon_stat_enabled_load,
 };
 
 static bool enabled __read_mostly = IS_ENABLED(
 	CONFIG_DAMON_STAT_ENABLED_DEFAULT);
-module_param_cb(enabled, &enabled_param_ops, &enabled, 0600);
+module_param_cb(enabled, &enabled_param_ops, NULL, 0600);
 MODULE_PARM_DESC(enabled, "Enable of disable DAMON_STAT");
 
 static unsigned long estimated_memory_bandwidth __read_mostly;
@@ -273,17 +276,23 @@ static void damon_stat_stop(void)
 	damon_stat_context = NULL;
 }
 
+static bool damon_stat_enabled(void)
+{
+	if (!damon_stat_context)
+		return false;
+	return damon_is_running(damon_stat_context);
+}
+
 static int damon_stat_enabled_store(
 		const char *val, const struct kernel_param *kp)
 {
-	bool is_enabled = enabled;
 	int err;
 
 	err = kstrtobool(val, &enabled);
 	if (err)
 		return err;
 
-	if (is_enabled == enabled)
+	if (damon_stat_enabled() == enabled)
 		return 0;
 
 	if (!damon_initialized())
@@ -293,16 +302,17 @@ static int damon_stat_enabled_store(
 		 */
 		return 0;
 
-	if (enabled) {
-		err = damon_stat_start();
-		if (err)
-			enabled = false;
-		return err;
-	}
+	if (enabled)
+		return damon_stat_start();
 	damon_stat_stop();
 	return 0;
 }
 
+static int damon_stat_enabled_load(char *buffer, const struct kernel_param *kp)
+{
+	return sprintf(buffer, "%c\n", damon_stat_enabled() ? 'Y' : 'N');
+}
+
 static int __init damon_stat_init(void)
 {
 	int err = 0;
diff --git a/mm/damon/sysfs-schemes.c b/mm/damon/sysfs-schemes.c
index 5186966dafb3..04746cbb3327 100644
--- a/mm/damon/sysfs-schemes.c
+++ b/mm/damon/sysfs-schemes.c
@@ -533,9 +533,14 @@ static ssize_t memcg_path_show(struct kobject *kobj,
 {
 	struct damon_sysfs_scheme_filter *filter = container_of(kobj,
 			struct damon_sysfs_scheme_filter, kobj);
+	int len;
 
-	return sysfs_emit(buf, "%s\n",
+	if (!mutex_trylock(&damon_sysfs_lock))
+		return -EBUSY;
+	len = sysfs_emit(buf, "%s\n",
 			filter->memcg_path ? filter->memcg_path : "");
+	mutex_unlock(&damon_sysfs_lock);
+	return len;
 }
 
 static ssize_t memcg_path_store(struct kobject *kobj,
@@ -550,8 +555,13 @@ static ssize_t memcg_path_store(struct kobject *kobj,
 		return -ENOMEM;
 
 	strscpy(path, buf, count + 1);
+	if (!mutex_trylock(&damon_sysfs_lock)) {
+		kfree(path);
+		return -EBUSY;
+	}
 	kfree(filter->memcg_path);
 	filter->memcg_path = path;
+	mutex_unlock(&damon_sysfs_lock);
 	return count;
 }
 
@@ -1187,8 +1197,13 @@ static ssize_t path_show(struct kobject *kobj,
 {
 	struct damos_sysfs_quota_goal *goal = container_of(kobj,
 			struct damos_sysfs_quota_goal, kobj);
+	int len;
 
-	return sysfs_emit(buf, "%s\n", goal->path ? goal->path : "");
+	if (!mutex_trylock(&damon_sysfs_lock))
+		return -EBUSY;
+	len = sysfs_emit(buf, "%s\n", goal->path ? goal->path : "");
+	mutex_unlock(&damon_sysfs_lock);
+	return len;
 }
 
 static ssize_t path_store(struct kobject *kobj,
@@ -1203,8 +1218,13 @@ static ssize_t path_store(struct kobject *kobj,
 		return -ENOMEM;
 
 	strscpy(path, buf, count + 1);
+	if (!mutex_trylock(&damon_sysfs_lock)) {
+		kfree(path);
+		return -EBUSY;
+	}
 	kfree(goal->path);
 	goal->path = path;
+	mutex_unlock(&damon_sysfs_lock);
 	return count;
 }
 
@@ -2574,6 +2594,7 @@ static int damon_sysfs_memcg_path_to_id(char *memcg_path, u64 *id)
 		if (damon_sysfs_memcg_path_eq(memcg, path, memcg_path)) {
 			*id = mem_cgroup_id(memcg);
 			found = true;
+			mem_cgroup_iter_break(NULL, memcg);
 			break;
 		}
 	}
diff --git a/mm/hugetlb.c b/mm/hugetlb.c
index f24bf49be047..a22202f72bac 100644
--- a/mm/hugetlb.c
+++ b/mm/hugetlb.c
@@ -6290,6 +6290,7 @@ int hugetlb_mfill_atomic_pte(pte_t *dst_pte,
 		folio_put(*foliop);
 		*foliop = NULL;
 		if (ret) {
+			restore_reserve_on_error(h, dst_vma, dst_addr, folio);
 			folio_put(folio);
 			goto out;
 		}
diff --git a/mm/hugetlb_cma.c b/mm/hugetlb_cma.c
index f83ae4998990..7693ccefd0c6 100644
--- a/mm/hugetlb_cma.c
+++ b/mm/hugetlb_cma.c
@@ -204,6 +204,7 @@ void __init hugetlb_cma_reserve(void)
 		 */
 		per_node = DIV_ROUND_UP(hugetlb_cma_size,
 					nodes_weight(hugetlb_bootmem_nodes));
+		per_node = round_up(per_node, PAGE_SIZE << order);
 		pr_info("hugetlb_cma: reserve %lu MiB, up to %lu MiB per node\n",
 			hugetlb_cma_size / SZ_1M, per_node / SZ_1M);
 	}
diff --git a/mm/memory_hotplug.c b/mm/memory_hotplug.c
index 2a943ec57c85..4426abb05655 100644
--- a/mm/memory_hotplug.c
+++ b/mm/memory_hotplug.c
@@ -1422,6 +1422,7 @@ static void remove_memory_blocks_and_altmaps(u64 start, u64 size)
 
 		altmap = mem->altmap;
 		mem->altmap = NULL;
+		put_device(&mem->dev);
 
 		remove_memory_block_devices(cur_start, memblock_size);
 
diff --git a/mm/migrate_device.c b/mm/migrate_device.c
index fbfe5715f635..7a40a91cfb77 100644
--- a/mm/migrate_device.c
+++ b/mm/migrate_device.c
@@ -850,7 +850,7 @@ static int migrate_vma_insert_huge_pmd_page(struct migrate_vma *migrate,
 	ptl = pmd_lock(vma->vm_mm, pmdp);
 	csa_ret = check_stable_address_space(vma->vm_mm);
 	if (csa_ret)
-		goto abort;
+		goto unlock_abort;
 
 	/*
 	 * Check for userfaultfd but do not deliver the fault. Instead,
@@ -893,6 +893,7 @@ static int migrate_vma_insert_huge_pmd_page(struct migrate_vma *migrate,
 
 unlock_abort:
 	spin_unlock(ptl);
+	pte_free(vma->vm_mm, pgtable);
 abort:
 	for (i = 0; i < HPAGE_PMD_NR; i++)
 		src[i] &= ~MIGRATE_PFN_MIGRATE;
diff --git a/mm/numa_emulation.c b/mm/numa_emulation.c
index 703c8fa05048..55f26b22bb0b 100644
--- a/mm/numa_emulation.c
+++ b/mm/numa_emulation.c
@@ -214,7 +214,7 @@ static u64 uniform_size(u64 max_addr, u64 base, u64 hole, int nr_nodes)
  * Sets up fake nodes of `size' interleaved over physical nodes ranging from
  * `addr' to `max_addr'.
  *
- * Returns zero on success or negative on error.
+ * Returns node ID of the next node on success or negative error code.
  */
 static int __init split_nodes_size_interleave_uniform(struct numa_meminfo *ei,
 					      struct numa_meminfo *pi,
@@ -398,7 +398,7 @@ void __init numa_emulation(struct numa_meminfo *numa_meminfo, int numa_dist_cnt)
 	 */
 	if (strchr(emu_cmdline, 'U')) {
 		unsigned long n;
-		int nid = 0;
+		int nid = 0, nr_created;
 
 		n = simple_strtoul(emu_cmdline, &emu_cmdline, 0);
 		ret = -1;
@@ -416,9 +416,18 @@ void __init numa_emulation(struct numa_meminfo *numa_meminfo, int numa_dist_cnt)
 					n, &pi.blk[0], nid);
 			if (ret < 0)
 				break;
-			if (ret < n) {
+
+			/*
+			 * If no memory was found for this physical node,
+			 * skip the under-allocation check.
+			 */
+			if (ret == nid)
+				continue;
+
+			nr_created = ret - nid;
+			if (nr_created < n) {
 				pr_info("%s: phys: %d only got %d of %ld nodes, failing\n",
-						__func__, i, ret, n);
+						__func__, i, nr_created, n);
 				ret = -1;
 				break;
 			}
diff --git a/mm/page-writeback.c b/mm/page-writeback.c
index 88cd53d4ba09..833f743f309f 100644
--- a/mm/page-writeback.c
+++ b/mm/page-writeback.c
@@ -1835,7 +1835,9 @@ static int balance_dirty_pages(struct bdi_writeback *wb,
 			balance_domain_limits(mdtc, strictlimit);
 		}
 
-		if (nr_dirty > gdtc->bg_thresh && !writeback_in_progress(wb))
+		if (!writeback_in_progress(wb) &&
+		    (nr_dirty > gdtc->bg_thresh ||
+		     (strictlimit && gdtc->wb_dirty > gdtc->wb_bg_thresh)))
 			wb_start_background_writeback(wb);
 
 		/*
@@ -1862,15 +1864,9 @@ static int balance_dirty_pages(struct bdi_writeback *wb,
 		 * Unconditionally start background writeback if it's not
 		 * already in progress. We need to do this because the global
 		 * dirty threshold check above (nr_dirty > gdtc->bg_thresh)
-		 * doesn't account for these cases:
-		 *
-		 * a) strictlimit BDIs: throttling is calculated using per-wb
-		 * thresholds. The per-wb threshold can be exceeded even when
-		 * nr_dirty < gdtc->bg_thresh
-		 *
-		 * b) memcg-based throttling: memcg uses its own dirty count and
-		 * thresholds and can trigger throttling even when global
-		 * nr_dirty < gdtc->bg_thresh
+		 * doesn't account for the memcg-based throttling case. memcg
+		 * uses its own dirty count and thresholds and can trigger
+		 * throttling even when global nr_dirty < gdtc->bg_thresh
 		 *
 		 * Writeback needs to be started else the writer stalls in the
 		 * throttle loop waiting for dirty pages to be written back
diff --git a/mm/page_alloc.c b/mm/page_alloc.c
index 65e205111553..71859993dd54 100644
--- a/mm/page_alloc.c
+++ b/mm/page_alloc.c
@@ -1808,9 +1808,9 @@ static inline bool should_skip_init(gfp_t flags)
 inline void post_alloc_hook(struct page *page, unsigned int order,
 				gfp_t gfp_flags)
 {
+	const bool zero_tags = gfp_flags & __GFP_ZEROTAGS;
 	bool init = !want_init_on_free() && want_init_on_alloc(gfp_flags) &&
 			!should_skip_init(gfp_flags);
-	bool zero_tags = init && (gfp_flags & __GFP_ZEROTAGS);
 	int i;
 
 	set_page_private(page, 0);
@@ -1832,11 +1832,11 @@ inline void post_alloc_hook(struct page *page, unsigned int order,
 	 */
 
 	/*
-	 * If memory tags should be zeroed
-	 * (which happens only when memory should be initialized as well).
+	 * Clearing tags can efficiently clear the memory for us as well, if
+	 * required.
 	 */
 	if (zero_tags)
-		init = !tag_clear_highpages(page, 1 << order);
+		init = tag_clear_highpages(page, 1 << order, /* clear_pages= */init);
 
 	if (!should_skip_kasan_unpoison(gfp_flags) &&
 	    kasan_unpoison_pages(page, order, init)) {
diff --git a/mm/swapfile.c b/mm/swapfile.c
index 9174f1eeffb0..c7e173b93e11 100644
--- a/mm/swapfile.c
+++ b/mm/swapfile.c
@@ -133,7 +133,7 @@ static DEFINE_PER_CPU(struct percpu_swap_cluster, percpu_swap_cluster) = {
 /* May return NULL on invalid type, caller must check for NULL return */
 static struct swap_info_struct *swap_type_to_info(int type)
 {
-	if (type >= MAX_SWAPFILES)
+	if (type < 0 || type >= MAX_SWAPFILES)
 		return NULL;
 	return READ_ONCE(swap_info[type]); /* rcu_dereference() */
 }
@@ -2077,7 +2077,16 @@ void swap_put_entries_direct(swp_entry_t entry, int nr)
 }
 
 #ifdef CONFIG_HIBERNATION
-/* Allocate a slot for hibernation */
+/**
+ * swap_alloc_hibernation_slot() - Allocate a swap slot for hibernation.
+ * @type: swap device type index to allocate from.
+ *
+ * The caller must ensure the swap device is stable, either by pinning
+ * it (SWP_HIBERNATION) or by freezing user-space.
+ *
+ * Return: a valid swp_entry_t on success, or an empty entry (val == 0)
+ * on failure.
+ */
 swp_entry_t swap_alloc_hibernation_slot(int type)
 {
 	struct swap_info_struct *pcp_si, *si = swap_type_to_info(type);
@@ -2088,46 +2097,42 @@ swp_entry_t swap_alloc_hibernation_slot(int type)
 	if (!si)
 		goto fail;
 
-	/* This is called for allocating swap entry, not cache */
-	if (get_swap_device_info(si)) {
-		if (si->flags & SWP_WRITEOK) {
-			/*
-			 * Try the local cluster first if it matches the device. If
-			 * not, try grab a new cluster and override local cluster.
-			 */
-			local_lock(&percpu_swap_cluster.lock);
-			pcp_si = this_cpu_read(percpu_swap_cluster.si[0]);
-			pcp_offset = this_cpu_read(percpu_swap_cluster.offset[0]);
-			if (pcp_si == si && pcp_offset) {
-				ci = swap_cluster_lock(si, pcp_offset);
-				if (cluster_is_usable(ci, 0))
-					offset = alloc_swap_scan_cluster(si, ci, NULL, pcp_offset);
-				else
-					swap_cluster_unlock(ci);
-			}
-			if (!offset)
-				offset = cluster_alloc_swap_entry(si, NULL);
-			local_unlock(&percpu_swap_cluster.lock);
-			if (offset)
-				entry = swp_entry(si->type, offset);
-		}
-		put_swap_device(si);
+	/*
+	 * Try the local cluster first if it matches the device. If
+	 * not, try grab a new cluster and override local cluster.
+	 */
+	local_lock(&percpu_swap_cluster.lock);
+	pcp_si = this_cpu_read(percpu_swap_cluster.si[0]);
+	pcp_offset = this_cpu_read(percpu_swap_cluster.offset[0]);
+	if (pcp_si == si && pcp_offset) {
+		ci = swap_cluster_lock(si, pcp_offset);
+		if (cluster_is_usable(ci, 0))
+			offset = alloc_swap_scan_cluster(si, ci, NULL, pcp_offset);
+		else
+			swap_cluster_unlock(ci);
 	}
+	if (!offset)
+		offset = cluster_alloc_swap_entry(si, NULL);
+	local_unlock(&percpu_swap_cluster.lock);
+	if (offset)
+		entry = swp_entry(si->type, offset);
+
 fail:
 	return entry;
 }
 
-/* Free a slot allocated by swap_alloc_hibernation_slot */
+/**
+ * swap_free_hibernation_slot() - Free a swap slot allocated for hibernation.
+ * @entry: swap entry to free.
+ *
+ * The caller must ensure the swap device is stable.
+ */
 void swap_free_hibernation_slot(swp_entry_t entry)
 {
-	struct swap_info_struct *si;
+	struct swap_info_struct *si = __swap_entry_to_info(entry);
 	struct swap_cluster_info *ci;
 	pgoff_t offset = swp_offset(entry);
 
-	si = get_swap_device(entry);
-	if (WARN_ON(!si))
-		return;
-
 	ci = swap_cluster_lock(si, offset);
 	__swap_cluster_put_entry(ci, offset % SWAPFILE_CLUSTER);
 	__swap_cluster_free_entries(si, ci, offset % SWAPFILE_CLUSTER, 1);
@@ -2135,25 +2140,17 @@ void swap_free_hibernation_slot(swp_entry_t entry)
 
 	/* In theory readahead might add it to the swap cache by accident */
 	__try_to_reclaim_swap(si, offset, TTRS_ANYWAY);
-	put_swap_device(si);
 }
 
-/*
- * Find the swap type that corresponds to given device (if any).
- *
- * @offset - number of the PAGE_SIZE-sized block of the device, starting
- * from 0, in which the swap header is expected to be located.
- *
- * This is needed for the suspend to disk (aka swsusp).
- */
-int swap_type_of(dev_t device, sector_t offset)
+static int __find_hibernation_swap_type(dev_t device, sector_t offset)
 {
 	int type;
 
+	lockdep_assert_held(&swap_lock);
+
 	if (!device)
-		return -1;
+		return -EINVAL;
 
-	spin_lock(&swap_lock);
 	for (type = 0; type < nr_swapfiles; type++) {
 		struct swap_info_struct *sis = swap_info[type];
 
@@ -2163,16 +2160,118 @@ int swap_type_of(dev_t device, sector_t offset)
 		if (device == sis->bdev->bd_dev) {
 			struct swap_extent *se = first_se(sis);
 
-			if (se->start_block == offset) {
-				spin_unlock(&swap_lock);
+			if (se->start_block == offset)
 				return type;
-			}
 		}
 	}
-	spin_unlock(&swap_lock);
 	return -ENODEV;
 }
 
+/**
+ * pin_hibernation_swap_type - Pin the swap device for hibernation
+ * @device: Block device containing the resume image
+ * @offset: Offset identifying the swap area
+ *
+ * Locate the swap device for @device/@offset and mark it as pinned
+ * for hibernation. While pinned, swapoff() is prevented.
+ *
+ * Only one uswsusp context may pin a swap device at a time.
+ * If already pinned, this function returns -EBUSY.
+ *
+ * Return:
+ * >= 0 on success (swap type).
+ * -EINVAL if @device is invalid.
+ * -ENODEV if the swap device is not found.
+ * -EBUSY if the device is already pinned for hibernation.
+ */
+int pin_hibernation_swap_type(dev_t device, sector_t offset)
+{
+	int type;
+	struct swap_info_struct *si;
+
+	spin_lock(&swap_lock);
+
+	type = __find_hibernation_swap_type(device, offset);
+	if (type < 0) {
+		spin_unlock(&swap_lock);
+		return type;
+	}
+
+	si = swap_type_to_info(type);
+	if (WARN_ON_ONCE(!si)) {
+		spin_unlock(&swap_lock);
+		return -ENODEV;
+	}
+
+	/*
+	 * hibernate_acquire() prevents concurrent hibernation sessions.
+	 * This check additionally guards against double-pinning within
+	 * the same session.
+	 */
+	if (WARN_ON_ONCE(si->flags & SWP_HIBERNATION)) {
+		spin_unlock(&swap_lock);
+		return -EBUSY;
+	}
+
+	si->flags |= SWP_HIBERNATION;
+
+	spin_unlock(&swap_lock);
+	return type;
+}
+
+/**
+ * unpin_hibernation_swap_type - Unpin the swap device for hibernation
+ * @type: Swap type previously returned by pin_hibernation_swap_type()
+ *
+ * Clear the hibernation pin on the given swap device, allowing
+ * swapoff() to proceed normally.
+ *
+ * If @type does not refer to a valid swap device, this function
+ * does nothing.
+ */
+void unpin_hibernation_swap_type(int type)
+{
+	struct swap_info_struct *si;
+
+	spin_lock(&swap_lock);
+	si = swap_type_to_info(type);
+	if (!si) {
+		spin_unlock(&swap_lock);
+		return;
+	}
+	si->flags &= ~SWP_HIBERNATION;
+	spin_unlock(&swap_lock);
+}
+
+/**
+ * find_hibernation_swap_type - Find swap type for hibernation
+ * @device: Block device containing the resume image
+ * @offset: Offset within the device identifying the swap area
+ *
+ * Locate the swap device corresponding to @device and @offset.
+ *
+ * Unlike pin_hibernation_swap_type(), this function only performs a
+ * lookup and does not mark the swap device as pinned for hibernation.
+ *
+ * This is safe in the sysfs-based hibernation path where user space
+ * is already frozen and swapoff() cannot run concurrently.
+ *
+ * Return:
+ * A non-negative swap type on success.
+ * -EINVAL if @device is invalid.
+ * -ENODEV if no matching swap device is found.
+ */
+int find_hibernation_swap_type(dev_t device, sector_t offset)
+{
+	int type;
+
+	spin_lock(&swap_lock);
+	type = __find_hibernation_swap_type(device, offset);
+	spin_unlock(&swap_lock);
+
+	return type;
+}
+
 int find_first_swap(dev_t *device)
 {
 	int type;
@@ -2936,6 +3035,14 @@ SYSCALL_DEFINE1(swapoff, const char __user *, specialfile)
 		spin_unlock(&swap_lock);
 		goto out_dput;
 	}
+
+	/* Refuse swapoff while the device is pinned for hibernation */
+	if (p->flags & SWP_HIBERNATION) {
+		err = -EBUSY;
+		spin_unlock(&swap_lock);
+		goto out_dput;
+	}
+
 	if (!security_vm_enough_memory_mm(current->mm, p->pages))
 		vm_unacct_memory(p->pages);
 	else {
diff --git a/mm/userfaultfd.c b/mm/userfaultfd.c
index 885da1e56466..180bad42fc79 100644
--- a/mm/userfaultfd.c
+++ b/mm/userfaultfd.c
@@ -443,8 +443,10 @@ static int mfill_copy_folio_locked(struct folio *folio, unsigned long src_addr)
 	return ret;
 }
 
-static int mfill_copy_folio_retry(struct mfill_state *state, struct folio *folio)
+static int mfill_copy_folio_retry(struct mfill_state *state,
+				  struct folio *folio)
 {
+	const struct vm_uffd_ops *orig_ops = vma_uffd_ops(state->vma);
 	unsigned long src_addr = state->src_addr;
 	void *kaddr;
 	int err;
@@ -465,6 +467,14 @@ static int mfill_copy_folio_retry(struct mfill_state *state, struct folio *folio
 	if (err)
 		return err;
 
+	/*
+	 * The VMA type may have changed while the lock was dropped
+	 * (e.g. replaced with a hugetlb mapping), making the caller's
+	 * ops pointer stale.
+	 */
+	if (vma_uffd_ops(state->vma) != orig_ops)
+		return -EAGAIN;
+
 	err = mfill_establish_pmd(state);
 	if (err)
 		return err;
diff --git a/mm/util.c b/mm/util.c
index 232c3930a662..3cc949a0b7ed 100644
--- a/mm/util.c
+++ b/mm/util.c
@@ -1232,7 +1232,7 @@ int __compat_vma_mmap(struct vm_area_desc *desc,
 	/* Update the VMA from the descriptor. */
 	compat_set_vma_from_desc(vma, desc);
 	/* Complete any specified mmap actions. */
-	return mmap_action_complete(vma, &desc->action);
+	return mmap_action_complete(vma, &desc->action, /*is_compat=*/true);
 }
 EXPORT_SYMBOL(__compat_vma_mmap);
 
@@ -1389,7 +1389,8 @@ static int call_vma_mapped(struct vm_area_struct *vma)
 }
 
 static int mmap_action_finish(struct vm_area_struct *vma,
-			      struct mmap_action *action, int err)
+			      struct mmap_action *action, int err,
+			      bool is_compat)
 {
 	size_t len;
 
@@ -1400,8 +1401,12 @@ static int mmap_action_finish(struct vm_area_struct *vma,
 
 	/* do_munmap() might take rmap lock, so release if held. */
 	maybe_rmap_unlock_action(vma, action);
-	if (!err)
-		return 0;
+	/*
+	 * If this is invoked from the compatibility layer, post-mmap() hook
+	 * logic will handle cleanup for us.
+	 */
+	if (!err || is_compat)
+		return err;
 
 	/*
 	 * If an error occurs, unmap the VMA altogether and return an error. We
@@ -1451,13 +1456,15 @@ EXPORT_SYMBOL(mmap_action_prepare);
  * mmap_action_complete - Execute VMA descriptor action.
  * @vma: The VMA to perform the action upon.
  * @action: The action to perform.
+ * @is_compat: Is this being invoked from the compatibility layer?
  *
  * Similar to mmap_action_prepare().
  *
- * Return: 0 on success, or error, at which point the VMA will be unmapped.
+ * Return: 0 on success, or error, at which point the VMA will be unmapped if
+ * !@is_compat.
  */
 int mmap_action_complete(struct vm_area_struct *vma,
-			 struct mmap_action *action)
+			 struct mmap_action *action, bool is_compat)
 {
 	int err = 0;
 
@@ -1478,7 +1485,7 @@ int mmap_action_complete(struct vm_area_struct *vma,
 		break;
 	}
 
-	return mmap_action_finish(vma, action, err);
+	return mmap_action_finish(vma, action, err, is_compat);
 }
 EXPORT_SYMBOL(mmap_action_complete);
 #else
@@ -1500,7 +1507,8 @@ int mmap_action_prepare(struct vm_area_desc *desc)
 EXPORT_SYMBOL(mmap_action_prepare);
 
 int mmap_action_complete(struct vm_area_struct *vma,
-			 struct mmap_action *action)
+			 struct mmap_action *action,
+			 bool is_compat)
 {
 	int err = 0;
 
@@ -1517,7 +1525,7 @@ int mmap_action_complete(struct vm_area_struct *vma,
 		break;
 	}
 
-	return mmap_action_finish(vma, action, err);
+	return mmap_action_finish(vma, action, err, is_compat);
 }
 EXPORT_SYMBOL(mmap_action_complete);
 #endif
diff --git a/mm/vma.c b/mm/vma.c
index 377321b48734..d90791b00a7b 100644
--- a/mm/vma.c
+++ b/mm/vma.c
@@ -2780,7 +2780,8 @@ static unsigned long __mmap_region(struct file *file, unsigned long addr,
 	__mmap_complete(&map, vma);
 
 	if (have_mmap_prepare && allocated_new) {
-		error = mmap_action_complete(vma, &desc.action);
+		error = mmap_action_complete(vma, &desc.action,
+					     /*is_compat=*/false);
 		if (error)
 			return error;
 	}
diff --git a/mm/vmalloc.c b/mm/vmalloc.c
index aa08651ec0df..c31a8615a832 100644
--- a/mm/vmalloc.c
+++ b/mm/vmalloc.c
@@ -4361,7 +4361,7 @@ void *vrealloc_node_align_noprof(const void *p, size_t size, unsigned long align
 		return NULL;
 
 	if (p) {
-		memcpy(n, p, old_size);
+		memcpy(n, p, min(size, old_size));
 		vfree(p);
 	}
 
diff --git a/net/bluetooth/6lowpan.c b/net/bluetooth/6lowpan.c
index 2f03b780b40d..23a229ab6a33 100644
--- a/net/bluetooth/6lowpan.c
+++ b/net/bluetooth/6lowpan.c
@@ -758,13 +758,33 @@ static inline struct l2cap_chan *chan_new_conn_cb(struct l2cap_chan *pchan)
 	return chan;
 }
 
+static void unregister_dev(struct lowpan_btle_dev *dev)
+{
+	struct hci_dev *hdev = READ_ONCE(dev->hdev);
+
+	/* If netdev holds last reference to hci_dev (its parent device), this
+	 * leads to theoretical cyclic locking on lowpan_unregister_netdev:
+	 *
+	 * rtnl_lock -> put_device(parent) -> hci_release_dev ->
+	 * destroy_workqueue -> hci_rx_work -> l2cap_recv_acldata ->
+	 * chan_ready_cb -> ifup -> rtnl_lock
+	 *
+	 * However, hci_rx_work is disabled in hci_unregister_dev, so this
+	 * should not occur. Make lockdep happy by postponing hdev release after
+	 * netdev put.
+	 */
+	hci_dev_hold(hdev);
+	lowpan_unregister_netdev(dev->netdev);
+	hci_dev_put(hdev);
+}
+
 static void delete_netdev(struct work_struct *work)
 {
 	struct lowpan_btle_dev *entry = container_of(work,
 						     struct lowpan_btle_dev,
 						     delete_netdev);
 
-	lowpan_unregister_netdev(entry->netdev);
+	unregister_dev(entry);
 
 	/* The entry pointer is deleted by the netdev destructor. */
 }
@@ -1250,6 +1270,7 @@ static void disconnect_devices(void)
 			break;
 
 		new_dev->netdev = entry->netdev;
+		new_dev->hdev = entry->hdev;
 		INIT_LIST_HEAD(&new_dev->list);
 
 		list_add_rcu(&new_dev->list, &devices);
@@ -1261,7 +1282,7 @@ static void disconnect_devices(void)
 		ifdown(entry->netdev);
 		BT_DBG("Unregistering netdev %s %p",
 		       entry->netdev->name, entry->netdev);
-		lowpan_unregister_netdev(entry->netdev);
+		unregister_dev(entry);
 		kfree(entry);
 	}
 }
diff --git a/net/bluetooth/bnep/core.c b/net/bluetooth/bnep/core.c
index d44987d4515c..853c8d7644b5 100644
--- a/net/bluetooth/bnep/core.c
+++ b/net/bluetooth/bnep/core.c
@@ -330,11 +330,18 @@ static int bnep_rx_frame(struct bnep_session *s, struct sk_buff *skb)
 				goto badframe;
 			break;
 		case BNEP_FILTER_MULTI_ADDR_SET:
-		case BNEP_FILTER_NET_TYPE_SET:
-			/* Pull: ctrl type (1 b), len (2 b), data (len bytes) */
-			if (!skb_pull(skb, 3 + *(u16 *)(skb->data + 1) * 2))
+		case BNEP_FILTER_NET_TYPE_SET: {
+			u8 *hdr;
+
+			/* Pull ctrl type (1 b) + len (2 b) */
+			hdr = skb_pull_data(skb, 3);
+			if (!hdr)
+				goto badframe;
+			/* Pull data (len bytes); length is big-endian */
+			if (!skb_pull(skb, get_unaligned_be16(&hdr[1])))
 				goto badframe;
 			break;
+		}
 		default:
 			kfree_skb(skb);
 			return 0;
diff --git a/net/bluetooth/hci_conn.c b/net/bluetooth/hci_conn.c
index 3a0592599086..17b46ad6a349 100644
--- a/net/bluetooth/hci_conn.c
+++ b/net/bluetooth/hci_conn.c
@@ -480,40 +480,107 @@ bool hci_setup_sync(struct hci_conn *conn, __u16 handle)
 	return hci_setup_sync_conn(conn, handle);
 }
 
-u8 hci_le_conn_update(struct hci_conn *conn, u16 min, u16 max, u16 latency,
-		      u16 to_multiplier)
+struct le_conn_update_data {
+	struct hci_conn *conn;
+	u16	min;
+	u16	max;
+	u16	latency;
+	u16	to_multiplier;
+};
+
+static int le_conn_update_sync(struct hci_dev *hdev, void *data)
 {
-	struct hci_dev *hdev = conn->hdev;
+	struct le_conn_update_data *d = data;
+	struct hci_conn *conn = d->conn;
 	struct hci_conn_params *params;
 	struct hci_cp_le_conn_update cp;
+	u16 timeout;
+	u8 store_hint;
+	int err;
 
+	/* Verify connection is still alive and read conn fields under
+	 * the same lock to prevent a concurrent disconnect from freeing
+	 * or reusing the connection while we build the HCI command.
+	 */
 	hci_dev_lock(hdev);
 
-	params = hci_conn_params_lookup(hdev, &conn->dst, conn->dst_type);
-	if (params) {
-		params->conn_min_interval = min;
-		params->conn_max_interval = max;
-		params->conn_latency = latency;
-		params->supervision_timeout = to_multiplier;
+	if (!hci_conn_valid(hdev, conn)) {
+		hci_dev_unlock(hdev);
+		return -ECANCELED;
 	}
 
-	hci_dev_unlock(hdev);
-
 	memset(&cp, 0, sizeof(cp));
 	cp.handle		= cpu_to_le16(conn->handle);
-	cp.conn_interval_min	= cpu_to_le16(min);
-	cp.conn_interval_max	= cpu_to_le16(max);
-	cp.conn_latency		= cpu_to_le16(latency);
-	cp.supervision_timeout	= cpu_to_le16(to_multiplier);
+	cp.conn_interval_min	= cpu_to_le16(d->min);
+	cp.conn_interval_max	= cpu_to_le16(d->max);
+	cp.conn_latency		= cpu_to_le16(d->latency);
+	cp.supervision_timeout	= cpu_to_le16(d->to_multiplier);
 	cp.min_ce_len		= cpu_to_le16(0x0000);
 	cp.max_ce_len		= cpu_to_le16(0x0000);
+	timeout			= conn->conn_timeout;
+
+	hci_dev_unlock(hdev);
 
-	hci_send_cmd(hdev, HCI_OP_LE_CONN_UPDATE, sizeof(cp), &cp);
+	err = __hci_cmd_sync_status_sk(hdev, HCI_OP_LE_CONN_UPDATE,
+				       sizeof(cp), &cp,
+				       HCI_EV_LE_CONN_UPDATE_COMPLETE,
+				       timeout, NULL);
+	if (err)
+		return err;
+
+	/* Update stored connection parameters after the controller has
+	 * confirmed the update via the LE Connection Update Complete event.
+	 */
+	hci_dev_lock(hdev);
+
+	params = hci_conn_params_lookup(hdev, &conn->dst, conn->dst_type);
+	if (params) {
+		params->conn_min_interval = d->min;
+		params->conn_max_interval = d->max;
+		params->conn_latency = d->latency;
+		params->supervision_timeout = d->to_multiplier;
+		store_hint = 0x01;
+	} else {
+		store_hint = 0x00;
+	}
 
-	if (params)
-		return 0x01;
+	hci_dev_unlock(hdev);
 
-	return 0x00;
+	mgmt_new_conn_param(hdev, &conn->dst, conn->dst_type, store_hint,
+			    d->min, d->max, d->latency, d->to_multiplier);
+
+	return 0;
+}
+
+static void le_conn_update_complete(struct hci_dev *hdev, void *data, int err)
+{
+	struct le_conn_update_data *d = data;
+
+	hci_conn_put(d->conn);
+	kfree(d);
+}
+
+void hci_le_conn_update(struct hci_conn *conn, u16 min, u16 max, u16 latency,
+			u16 to_multiplier)
+{
+	struct le_conn_update_data *d;
+
+	d = kzalloc_obj(*d);
+	if (!d)
+		return;
+
+	hci_conn_get(conn);
+	d->conn = conn;
+	d->min = min;
+	d->max = max;
+	d->latency = latency;
+	d->to_multiplier = to_multiplier;
+
+	if (hci_cmd_sync_queue(conn->hdev, le_conn_update_sync, d,
+			       le_conn_update_complete) < 0) {
+		hci_conn_put(conn);
+		kfree(d);
+	}
 }
 
 void hci_le_start_enc(struct hci_conn *conn, __le16 ediv, __le64 rand,
@@ -2130,6 +2197,9 @@ static int create_big_sync(struct hci_dev *hdev, void *data)
 	u32 flags = 0;
 	int err;
 
+	if (!hci_conn_valid(hdev, conn))
+		return -ECANCELED;
+
 	if (qos->bcast.out.phys == BIT(1))
 		flags |= MGMT_ADV_FLAG_SEC_2M;
 
@@ -2204,11 +2274,24 @@ static void create_big_complete(struct hci_dev *hdev, void *data, int err)
 
 	bt_dev_dbg(hdev, "conn %p", conn);
 
+	if (err == -ECANCELED)
+		goto done;
+
+	hci_dev_lock(hdev);
+
+	if (!hci_conn_valid(hdev, conn))
+		goto unlock;
+
 	if (err) {
 		bt_dev_err(hdev, "Unable to create BIG: %d", err);
 		hci_connect_cfm(conn, err);
 		hci_conn_del(conn);
 	}
+
+unlock:
+	hci_dev_unlock(hdev);
+done:
+	hci_conn_put(conn);
 }
 
 struct hci_conn *hci_bind_bis(struct hci_dev *hdev, bdaddr_t *dst, __u8 sid,
@@ -2336,10 +2419,11 @@ struct hci_conn *hci_connect_bis(struct hci_dev *hdev, bdaddr_t *dst,
 				 BT_BOUND, &data);
 
 	/* Queue start periodic advertising and create BIG */
-	err = hci_cmd_sync_queue(hdev, create_big_sync, conn,
+	err = hci_cmd_sync_queue(hdev, create_big_sync, hci_conn_get(conn),
 				 create_big_complete);
 	if (err < 0) {
 		hci_conn_drop(conn);
+		hci_conn_put(conn);
 		return ERR_PTR(err);
 	}
 
diff --git a/net/bluetooth/hci_event.c b/net/bluetooth/hci_event.c
index b2ee6b6a0f56..1b3b9131affa 100644
--- a/net/bluetooth/hci_event.c
+++ b/net/bluetooth/hci_event.c
@@ -7118,9 +7118,29 @@ static void hci_le_create_big_complete_evt(struct hci_dev *hdev, void *data,
 			continue;
 		}
 
+		if (ev->num_bis <= i) {
+			bt_dev_err(hdev,
+				   "Not enough BIS handles for BIG 0x%2.2x",
+				   ev->handle);
+			ev->status = HCI_ERROR_UNSPECIFIED;
+			hci_connect_cfm(conn, ev->status);
+			hci_conn_del(conn);
+			continue;
+		}
+
 		if (hci_conn_set_handle(conn,
-					__le16_to_cpu(ev->bis_handle[i++])))
+					__le16_to_cpu(ev->bis_handle[i++]))) {
+			bt_dev_err(hdev,
+				   "Failed to set BIS handle for BIG 0x%2.2x",
+				   ev->handle);
+			/* Force error so BIG gets terminated as not all BIS
+			 * could be connected.
+			 */
+			ev->status = HCI_ERROR_UNSPECIFIED;
+			hci_connect_cfm(conn, ev->status);
+			hci_conn_del(conn);
 			continue;
+		}
 
 		conn->state = BT_CONNECTED;
 		set_bit(HCI_CONN_BIG_CREATED, &conn->flags);
@@ -7129,7 +7149,10 @@ static void hci_le_create_big_complete_evt(struct hci_dev *hdev, void *data,
 		hci_iso_setup_path(conn);
 	}
 
-	if (!ev->status && !i)
+	/* If there is an unexpected error or if no BISes have been connected
+	 * for the BIG, terminate it.
+	 */
+	if (ev->status == HCI_ERROR_UNSPECIFIED || (!ev->status && !i))
 		/* If no BISes have been connected for the BIG,
 		 * terminate. This is in case all bound connections
 		 * have been closed before the BIG creation
diff --git a/net/bluetooth/iso.c b/net/bluetooth/iso.c
index be145e2736b7..7cb2864fe872 100644
--- a/net/bluetooth/iso.c
+++ b/net/bluetooth/iso.c
@@ -347,6 +347,7 @@ static int iso_connect_bis(struct sock *sk)
 		return -EHOSTUNREACH;
 
 	hci_dev_lock(hdev);
+	lock_sock(sk);
 
 	if (!bis_capable(hdev)) {
 		err = -EOPNOTSUPP;
@@ -399,13 +400,9 @@ static int iso_connect_bis(struct sock *sk)
 		goto unlock;
 	}
 
-	lock_sock(sk);
-
 	err = iso_chan_add(conn, sk, NULL);
-	if (err) {
-		release_sock(sk);
+	if (err)
 		goto unlock;
-	}
 
 	/* Update source addr of the socket */
 	bacpy(&iso_pi(sk)->src, &hcon->src);
@@ -421,9 +418,8 @@ static int iso_connect_bis(struct sock *sk)
 		iso_sock_set_timer(sk, READ_ONCE(sk->sk_sndtimeo));
 	}
 
-	release_sock(sk);
-
 unlock:
+	release_sock(sk);
 	hci_dev_unlock(hdev);
 	hci_dev_put(hdev);
 	return err;
@@ -444,6 +440,7 @@ static int iso_connect_cis(struct sock *sk)
 		return -EHOSTUNREACH;
 
 	hci_dev_lock(hdev);
+	lock_sock(sk);
 
 	if (!cis_central_capable(hdev)) {
 		err = -EOPNOTSUPP;
@@ -498,13 +495,9 @@ static int iso_connect_cis(struct sock *sk)
 		goto unlock;
 	}
 
-	lock_sock(sk);
-
 	err = iso_chan_add(conn, sk, NULL);
-	if (err) {
-		release_sock(sk);
+	if (err)
 		goto unlock;
-	}
 
 	/* Update source addr of the socket */
 	bacpy(&iso_pi(sk)->src, &hcon->src);
@@ -520,9 +513,8 @@ static int iso_connect_cis(struct sock *sk)
 		iso_sock_set_timer(sk, READ_ONCE(sk->sk_sndtimeo));
 	}
 
-	release_sock(sk);
-
 unlock:
+	release_sock(sk);
 	hci_dev_unlock(hdev);
 	hci_dev_put(hdev);
 	return err;
@@ -1193,7 +1185,7 @@ static int iso_sock_connect(struct socket *sock, struct sockaddr_unsized *addr,
 
 	release_sock(sk);
 
-	if (bacmp(&iso_pi(sk)->dst, BDADDR_ANY))
+	if (bacmp(&sa->iso_bdaddr, BDADDR_ANY))
 		err = iso_connect_cis(sk);
 	else
 		err = iso_connect_bis(sk);
@@ -2256,8 +2248,10 @@ int iso_connect_ind(struct hci_dev *hdev, bdaddr_t *bdaddr, __u8 *flags)
 		sk = iso_get_sock(hdev, &hdev->bdaddr, bdaddr, BT_LISTEN,
 				  iso_match_sid, ev1);
 		if (sk && !ev1->status) {
+			lock_sock(sk);
 			iso_pi(sk)->sync_handle = le16_to_cpu(ev1->handle);
 			iso_pi(sk)->bc_sid = ev1->sid;
+			release_sock(sk);
 		}
 
 		goto done;
@@ -2268,8 +2262,10 @@ int iso_connect_ind(struct hci_dev *hdev, bdaddr_t *bdaddr, __u8 *flags)
 		sk = iso_get_sock(hdev, &hdev->bdaddr, bdaddr, BT_LISTEN,
 				  iso_match_sid_past, ev1a);
 		if (sk && !ev1a->status) {
+			lock_sock(sk);
 			iso_pi(sk)->sync_handle = le16_to_cpu(ev1a->sync_handle);
 			iso_pi(sk)->bc_sid = ev1a->sid;
+			release_sock(sk);
 		}
 
 		goto done;
@@ -2296,27 +2292,35 @@ int iso_connect_ind(struct hci_dev *hdev, bdaddr_t *bdaddr, __u8 *flags)
 					  ev2);
 
 		if (sk) {
-			int err;
-			struct hci_conn	*hcon = iso_pi(sk)->conn->hcon;
+			int err = 0;
+			bool big_sync;
+			struct hci_conn *hcon;
 
+			lock_sock(sk);
+
+			hcon = iso_pi(sk)->conn->hcon;
 			iso_pi(sk)->qos.bcast.encryption = ev2->encryption;
 
 			if (ev2->num_bis < iso_pi(sk)->bc_num_bis)
 				iso_pi(sk)->bc_num_bis = ev2->num_bis;
 
-			if (!test_bit(BT_SK_DEFER_SETUP, &bt_sk(sk)->flags) &&
-			    !test_and_set_bit(BT_SK_BIG_SYNC, &iso_pi(sk)->flags)) {
+			big_sync = !test_bit(BT_SK_DEFER_SETUP, &bt_sk(sk)->flags) &&
+				   !test_and_set_bit(BT_SK_BIG_SYNC, &iso_pi(sk)->flags);
+
+			if (big_sync)
 				err = hci_conn_big_create_sync(hdev, hcon,
 							       &iso_pi(sk)->qos,
 							       iso_pi(sk)->sync_handle,
 							       iso_pi(sk)->bc_num_bis,
 							       iso_pi(sk)->bc_bis);
-				if (err) {
-					bt_dev_err(hdev, "hci_le_big_create_sync: %d",
-						   err);
-					sock_put(sk);
-					sk = NULL;
-				}
+
+			release_sock(sk);
+
+			if (big_sync && err) {
+				bt_dev_err(hdev, "hci_le_big_create_sync: %d",
+					   err);
+				sock_put(sk);
+				sk = NULL;
 			}
 		}
 
@@ -2370,8 +2374,10 @@ int iso_connect_ind(struct hci_dev *hdev, bdaddr_t *bdaddr, __u8 *flags)
 			if (!base || base_len > BASE_MAX_LENGTH)
 				goto done;
 
+			lock_sock(sk);
 			memcpy(iso_pi(sk)->base, base, base_len);
 			iso_pi(sk)->base_len = base_len;
+			release_sock(sk);
 		} else {
 			/* This is a PA data fragment. Keep pa_data_len set to 0
 			 * until all data has been reassembled.
diff --git a/net/bluetooth/l2cap_core.c b/net/bluetooth/l2cap_core.c
index 77dec104a9c3..7701528f1167 100644
--- a/net/bluetooth/l2cap_core.c
+++ b/net/bluetooth/l2cap_core.c
@@ -4706,16 +4706,8 @@ static inline int l2cap_conn_param_update_req(struct l2cap_conn *conn,
 	l2cap_send_cmd(conn, cmd->ident, L2CAP_CONN_PARAM_UPDATE_RSP,
 		       sizeof(rsp), &rsp);
 
-	if (!err) {
-		u8 store_hint;
-
-		store_hint = hci_le_conn_update(hcon, min, max, latency,
-						to_multiplier);
-		mgmt_new_conn_param(hcon->hdev, &hcon->dst, hcon->dst_type,
-				    store_hint, min, max, latency,
-				    to_multiplier);
-
-	}
+	if (!err)
+		hci_le_conn_update(hcon, min, max, latency, to_multiplier);
 
 	return 0;
 }
@@ -5428,7 +5420,7 @@ static inline int l2cap_ecred_reconf_req(struct l2cap_conn *conn,
 		 * configured, the MPS field may be less than the current MPS
 		 * of that channel.
 		 */
-		if (chan[i]->remote_mps >= mps && i) {
+		if (chan[i]->remote_mps > mps && num_scid > 1) {
 			BT_ERR("chan %p decreased MPS %u -> %u", chan[i],
 			       chan[i]->remote_mps, mps);
 			result = L2CAP_RECONF_INVALID_MPS;
diff --git a/net/bluetooth/l2cap_sock.c b/net/bluetooth/l2cap_sock.c
index 71e8c1b45bce..cf590a67d364 100644
--- a/net/bluetooth/l2cap_sock.c
+++ b/net/bluetooth/l2cap_sock.c
@@ -1498,6 +1498,9 @@ static struct l2cap_chan *l2cap_sock_new_connection_cb(struct l2cap_chan *chan)
 {
 	struct sock *sk, *parent = chan->data;
 
+	if (!parent)
+		return NULL;
+
 	lock_sock(parent);
 
 	/* Check for backlog size */
@@ -1657,6 +1660,9 @@ static void l2cap_sock_state_change_cb(struct l2cap_chan *chan, int state,
 {
 	struct sock *sk = chan->data;
 
+	if (!sk)
+		return;
+
 	sk->sk_state = state;
 
 	if (err)
@@ -1758,6 +1764,9 @@ static long l2cap_sock_get_sndtimeo_cb(struct l2cap_chan *chan)
 {
 	struct sock *sk = chan->data;
 
+	if (!sk)
+		return 0;
+
 	return READ_ONCE(sk->sk_sndtimeo);
 }
 
diff --git a/net/bluetooth/rfcomm/core.c b/net/bluetooth/rfcomm/core.c
index 611a9a94151e..d11bd5337d57 100644
--- a/net/bluetooth/rfcomm/core.c
+++ b/net/bluetooth/rfcomm/core.c
@@ -1715,9 +1715,12 @@ static int rfcomm_recv_data(struct rfcomm_session *s, u8 dlci, int pf, struct sk
 	}
 
 	if (pf && d->cfc) {
-		u8 credits = *(u8 *) skb->data; skb_pull(skb, 1);
+		u8 *credits = skb_pull_data(skb, 1);
 
-		d->tx_credits += credits;
+		if (!credits)
+			goto drop;
+
+		d->tx_credits += *credits;
 		if (d->tx_credits)
 			clear_bit(RFCOMM_TX_THROTTLED, &d->flags);
 	}
diff --git a/net/bluetooth/sco.c b/net/bluetooth/sco.c
index 18826d4b9c0b..eba44525d41d 100644
--- a/net/bluetooth/sco.c
+++ b/net/bluetooth/sco.c
@@ -472,9 +472,13 @@ static struct sock *sco_get_sock_listen(bdaddr_t *src)
 			sk1 = sk;
 	}
 
+	sk = sk ? sk : sk1;
+	if (sk)
+		sock_hold(sk);
+
 	read_unlock(&sco_sk_list.lock);
 
-	return sk ? sk : sk1;
+	return sk;
 }
 
 static void sco_sock_destruct(struct sock *sk)
@@ -515,11 +519,13 @@ static void sco_sock_kill(struct sock *sk)
 	BT_DBG("sk %p state %d", sk, sk->sk_state);
 
 	/* Sock is dead, so set conn->sk to NULL to avoid possible UAF */
+	lock_sock(sk);
 	if (sco_pi(sk)->conn) {
 		sco_conn_lock(sco_pi(sk)->conn);
 		sco_pi(sk)->conn->sk = NULL;
 		sco_conn_unlock(sco_pi(sk)->conn);
 	}
+	release_sock(sk);
 
 	/* Kill poor orphan */
 	bt_sock_unlink(&sco_sk_list, sk);
@@ -1365,40 +1371,51 @@ static int sco_sock_release(struct socket *sock)
 
 static void sco_conn_ready(struct sco_conn *conn)
 {
-	struct sock *parent;
-	struct sock *sk = conn->sk;
+	struct sock *parent, *sk;
+
+	sco_conn_lock(conn);
+	sk = sco_sock_hold(conn);
+	sco_conn_unlock(conn);
 
 	BT_DBG("conn %p", conn);
 
 	if (sk) {
 		lock_sock(sk);
-		sco_sock_clear_timer(sk);
-		sk->sk_state = BT_CONNECTED;
-		sk->sk_state_change(sk);
+
+		/* conn->sk may have become NULL if racing with sk close, but
+		 * due to held hdev->lock, it can't become different sk.
+		 */
+		if (conn->sk) {
+			sco_sock_clear_timer(sk);
+			sk->sk_state = BT_CONNECTED;
+			sk->sk_state_change(sk);
+		}
+
 		release_sock(sk);
+		sock_put(sk);
 	} else {
-		sco_conn_lock(conn);
-
-		if (!conn->hcon) {
-			sco_conn_unlock(conn);
+		if (!conn->hcon)
 			return;
-		}
+
+		lockdep_assert_held(&conn->hcon->hdev->lock);
 
 		parent = sco_get_sock_listen(&conn->hcon->src);
-		if (!parent) {
-			sco_conn_unlock(conn);
+		if (!parent)
 			return;
-		}
 
 		lock_sock(parent);
 
+		sco_conn_lock(conn);
+
+		/* hdev->lock guarantees conn->sk == NULL still here */
+
+		if (parent->sk_state != BT_LISTEN)
+			goto release;
+
 		sk = sco_sock_alloc(sock_net(parent), NULL,
 				    BTPROTO_SCO, GFP_ATOMIC, 0);
-		if (!sk) {
-			release_sock(parent);
-			sco_conn_unlock(conn);
-			return;
-		}
+		if (!sk)
+			goto release;
 
 		sco_sock_init(sk, parent);
 
@@ -1417,9 +1434,10 @@ static void sco_conn_ready(struct sco_conn *conn)
 		/* Wake up parent */
 		parent->sk_data_ready(parent);
 
-		release_sock(parent);
-
+release:
 		sco_conn_unlock(conn);
+		release_sock(parent);
+		sock_put(parent);
 	}
 }
 
diff --git a/net/bridge/br_nf_core.c b/net/bridge/br_nf_core.c
index a8c67035e23c..5b3a85b4be8f 100644
--- a/net/bridge/br_nf_core.c
+++ b/net/bridge/br_nf_core.c
@@ -70,6 +70,7 @@ void br_netfilter_rtable_init(struct net_bridge *br)
 	struct rtable *rt = &br->fake_rtable;
 
 	rcuref_init(&rt->dst.__rcuref, 1);
+	save_dst_trace_buffer(&rt->dst, 1);
 	rt->dst.dev = br->dev;
 	dst_init_metrics(&rt->dst, br->metrics, false);
 	dst_metric_set(&rt->dst, RTAX_MTU, br->dev->mtu);
diff --git a/net/ceph/crush/crush.c b/net/ceph/crush/crush.c
index 254ded0b05f6..521aec1d5fc0 100644
--- a/net/ceph/crush/crush.c
+++ b/net/ceph/crush/crush.c
@@ -47,7 +47,6 @@ int crush_get_bucket_item_weight(const struct crush_bucket *b, int p)
 void crush_destroy_bucket_uniform(struct crush_bucket_uniform *b)
 {
 	kfree(b->h.items);
-	kfree(b);
 }
 
 void crush_destroy_bucket_list(struct crush_bucket_list *b)
@@ -55,14 +54,12 @@ void crush_destroy_bucket_list(struct crush_bucket_list *b)
 	kfree(b->item_weights);
 	kfree(b->sum_weights);
 	kfree(b->h.items);
-	kfree(b);
 }
 
 void crush_destroy_bucket_tree(struct crush_bucket_tree *b)
 {
 	kfree(b->h.items);
 	kfree(b->node_weights);
-	kfree(b);
 }
 
 void crush_destroy_bucket_straw(struct crush_bucket_straw *b)
@@ -70,14 +67,12 @@ void crush_destroy_bucket_straw(struct crush_bucket_straw *b)
 	kfree(b->straws);
 	kfree(b->item_weights);
 	kfree(b->h.items);
-	kfree(b);
 }
 
 void crush_destroy_bucket_straw2(struct crush_bucket_straw2 *b)
 {
 	kfree(b->item_weights);
 	kfree(b->h.items);
-	kfree(b);
 }
 
 void crush_destroy_bucket(struct crush_bucket *b)
@@ -99,6 +94,7 @@ void crush_destroy_bucket(struct crush_bucket *b)
 		crush_destroy_bucket_straw2((struct crush_bucket_straw2 *)b);
 		break;
 	}
+	kfree(b);
 }
 
 /**
diff --git a/net/ceph/osdmap.c b/net/ceph/osdmap.c
index c89e66d4fcb7..669348d883f0 100644
--- a/net/ceph/osdmap.c
+++ b/net/ceph/osdmap.c
@@ -72,8 +72,7 @@ static int crush_decode_uniform_bucket(void **p, void *end,
 				       struct crush_bucket_uniform *b)
 {
 	dout("crush_decode_uniform_bucket %p to %p\n", *p, end);
-	ceph_decode_need(p, end, (1+b->h.size) * sizeof(u32), bad);
-	b->item_weight = ceph_decode_32(p);
+	ceph_decode_32_safe(p, end, b->item_weight, bad);
 	return 0;
 bad:
 	return -EINVAL;
@@ -516,6 +515,10 @@ static struct crush_map *crush_decode(void *pbyval, void *end)
 		b->id = ceph_decode_32(p);
 		b->type = ceph_decode_16(p);
 		b->alg = ceph_decode_8(p);
+		if (b->alg != alg) {
+			b->alg = 0;
+			goto bad;
+		}
 		b->hash = ceph_decode_8(p);
 		b->weight = ceph_decode_32(p);
 		b->size = ceph_decode_32(p);
diff --git a/net/core/bpf_sk_storage.c b/net/core/bpf_sk_storage.c
index 14eb7812bda4..ecd659f79fd4 100644
--- a/net/core/bpf_sk_storage.c
+++ b/net/core/bpf_sk_storage.c
@@ -172,7 +172,7 @@ int bpf_sk_storage_clone(const struct sock *sk, struct sock *newsk)
 		struct bpf_map *map;
 
 		smap = rcu_dereference(SDATA(selem)->smap);
-		if (!(smap->map.map_flags & BPF_F_CLONE))
+		if (!smap || !(smap->map.map_flags & BPF_F_CLONE))
 			continue;
 
 		/* Note that for lockless listeners adding new element
@@ -531,10 +531,10 @@ bpf_sk_storage_diag_alloc(const struct nlattr *nla_stgs)
 }
 EXPORT_SYMBOL_GPL(bpf_sk_storage_diag_alloc);
 
-static int diag_get(struct bpf_local_storage_data *sdata, struct sk_buff *skb)
+static int diag_get(struct bpf_local_storage_map *smap,
+		    struct bpf_local_storage_data *sdata, struct sk_buff *skb)
 {
 	struct nlattr *nla_stg, *nla_value;
-	struct bpf_local_storage_map *smap;
 
 	/* It cannot exceed max nlattr's payload */
 	BUILD_BUG_ON(U16_MAX - NLA_HDRLEN < BPF_LOCAL_STORAGE_MAX_VALUE_SIZE);
@@ -543,7 +543,6 @@ static int diag_get(struct bpf_local_storage_data *sdata, struct sk_buff *skb)
 	if (!nla_stg)
 		return -EMSGSIZE;
 
-	smap = rcu_dereference(sdata->smap);
 	if (nla_put_u32(skb, SK_DIAG_BPF_STORAGE_MAP_ID, smap->map.id))
 		goto errout;
 
@@ -558,6 +557,7 @@ static int diag_get(struct bpf_local_storage_data *sdata, struct sk_buff *skb)
 				      sdata->data, true);
 	else
 		copy_map_value(&smap->map, nla_data(nla_value), sdata->data);
+	check_and_init_map_value(&smap->map, nla_data(nla_value));
 
 	nla_nest_end(skb, nla_stg);
 	return 0;
@@ -596,9 +596,11 @@ static int bpf_sk_storage_diag_put_all(struct sock *sk, struct sk_buff *skb,
 	saved_len = skb->len;
 	hlist_for_each_entry_rcu(selem, &sk_storage->list, snode) {
 		smap = rcu_dereference(SDATA(selem)->smap);
+		if (!smap)
+			continue;
 		diag_size += nla_value_size(smap->map.value_size);
 
-		if (nla_stgs && diag_get(SDATA(selem), skb))
+		if (nla_stgs && diag_get(smap, SDATA(selem), skb))
 			/* Continue to learn diag_size */
 			err = -EMSGSIZE;
 	}
@@ -665,7 +667,7 @@ int bpf_sk_storage_diag_put(struct bpf_sk_storage_diag *diag,
 
 		diag_size += nla_value_size(diag->maps[i]->value_size);
 
-		if (nla_stgs && diag_get(sdata, skb))
+		if (nla_stgs && diag_get((struct bpf_local_storage_map *)diag->maps[i], sdata, skb))
 			/* Continue to learn diag_size */
 			err = -EMSGSIZE;
 	}
diff --git a/net/core/dev.c b/net/core/dev.c
index 06c195906231..0e8db7db171b 100644
--- a/net/core/dev.c
+++ b/net/core/dev.c
@@ -1874,6 +1874,7 @@ const char *netdev_cmd_to_name(enum netdev_cmd cmd)
 	N(PRE_CHANGEADDR) N(OFFLOAD_XSTATS_ENABLE) N(OFFLOAD_XSTATS_DISABLE)
 	N(OFFLOAD_XSTATS_REPORT_USED) N(OFFLOAD_XSTATS_REPORT_DELTA)
 	N(XDP_FEAT_CHANGE)
+	N(DEBUG_UNREGISTER)
 	}
 #undef N
 	return "UNKNOWN_NETDEV_EVENT";
@@ -11555,6 +11556,14 @@ int netdev_refcnt_read(const struct net_device *dev)
 }
 EXPORT_SYMBOL(netdev_refcnt_read);
 
+#ifdef CONFIG_NET_DEV_REFCNT_TRACKER
+static void dump_netdev_trace_buffer(const struct net_device *dev);
+static void erase_netdev_trace_buffer(const struct net_device *dev);
+#else
+static inline void dump_netdev_trace_buffer(const struct net_device *dev) { }
+static inline void erase_netdev_trace_buffer(const struct net_device *dev) { }
+#endif
+
 int netdev_unregister_timeout_secs __read_mostly = 10;
 
 #define WAIT_REFS_MIN_MSECS 1
@@ -11628,11 +11637,16 @@ static struct net_device *netdev_wait_allrefs_any(struct list_head *list)
 
 		if (time_after(jiffies, warning_time +
 			       READ_ONCE(netdev_unregister_timeout_secs) * HZ)) {
+			rtnl_lock();
 			list_for_each_entry(dev, list, todo_list) {
 				pr_emerg("unregister_netdevice: waiting for %s to become free. Usage count = %d\n",
 					 dev->name, netdev_refcnt_read(dev));
 				ref_tracker_dir_print(&dev->refcnt_tracker, 10);
+				call_netdevice_notifiers(NETDEV_DEBUG_UNREGISTER, dev);
+				dump_netdev_trace_buffer(dev);
 			}
+			__rtnl_unlock();
+			rcu_barrier();
 
 			warning_time = jiffies;
 		}
@@ -12030,6 +12044,9 @@ struct net_device *alloc_netdev_mqs(int sizeof_priv, const char *name,
 
 	dev->priv_len = sizeof_priv;
 
+#ifdef CONFIG_NET_DEV_REFCNT_TRACKER
+	INIT_LIST_HEAD(&dev->netdev_trace_buffer_list);
+#endif
 	ref_tracker_dir_init(&dev->refcnt_tracker, 128, "netdev");
 #ifdef CONFIG_PCPU_DEV_REFCNT
 	dev->pcpu_refcnt = alloc_percpu(int);
@@ -12206,6 +12223,8 @@ void free_netdev(struct net_device *dev)
 
 	mutex_destroy(&dev->lock);
 
+	erase_netdev_trace_buffer(dev);
+
 	/*  Compatibility with error handling in drivers */
 	if (dev->reg_state == NETREG_UNINITIALIZED ||
 	    dev->reg_state == NETREG_DUMMY) {
@@ -13312,3 +13331,172 @@ static int __init net_dev_init(void)
 }
 
 subsys_initcall(net_dev_init);
+
+#ifdef CONFIG_NET_DEV_REFCNT_TRACKER
+
+#define NETDEV_TRACE_BUFFER_SIZE 32768
+static struct netdev_trace_buffer {
+	struct list_head list;
+	int prev_count;
+	atomic_t count;
+	int nr_entries;
+	unsigned long entries[20];
+} netdev_trace_buffer[NETDEV_TRACE_BUFFER_SIZE];
+static LIST_HEAD(netdev_trace_buffer_list);
+static DEFINE_SPINLOCK(netdev_trace_buffer_lock);
+static bool netdev_trace_buffer_exhausted;
+
+static int netdev_trace_buffer_init(void)
+{
+	int i;
+
+	for (i = 0; i < NETDEV_TRACE_BUFFER_SIZE; i++)
+		list_add_tail(&netdev_trace_buffer[i].list, &netdev_trace_buffer_list);
+	return 0;
+}
+pure_initcall(netdev_trace_buffer_init);
+
+static void dump_netdev_trace_buffer(const struct net_device *dev)
+{
+	struct netdev_trace_buffer *ptr;
+	int count, balance = 0, pos = 0;
+
+	dump_dst_trace_buffer(dev);
+	list_for_each_entry_rcu(ptr, &dev->netdev_trace_buffer_list, list,
+				/* list elements can't go away. */ 1) {
+		pos++;
+		count = atomic_read(&ptr->count);
+		balance += count;
+		if (ptr->prev_count == count)
+			continue;
+		ptr->prev_count = count;
+		pr_info("Call trace for %s[%d] %+d at\n", dev->name, pos, count);
+		stack_trace_print(ptr->entries, ptr->nr_entries, 4);
+		cond_resched();
+	}
+	if (!netdev_trace_buffer_exhausted)
+		pr_info("balance as of %s[%d] is %d\n", dev->name, pos, balance);
+}
+
+static void erase_netdev_trace_buffer(const struct net_device *dev)
+{
+	struct netdev_trace_buffer *ptr;
+	unsigned long flags;
+
+	spin_lock_irqsave(&netdev_trace_buffer_lock, flags);
+	while (!list_empty(&dev->netdev_trace_buffer_list)) {
+		ptr = list_first_entry(&dev->netdev_trace_buffer_list, typeof(*ptr), list);
+		list_del(&ptr->list);
+		list_add_tail(&ptr->list, &netdev_trace_buffer_list);
+	}
+	spin_unlock_irqrestore(&netdev_trace_buffer_lock, flags);
+}
+
+int trim_netdev_trace(unsigned long *entries, int nr_entries)
+{
+#ifdef CONFIG_KALLSYMS
+	char buffer[32] = { };
+	char *cp;
+	int i;
+
+	if (in_softirq()) {
+		static unsigned long __data_racy caller;
+
+		if (!caller) {
+			for (i = 0; i < nr_entries; i++) {
+				snprintf(buffer, sizeof(buffer) - 1, "%ps", (void *)entries[i]);
+				cp = strchr(buffer, ' ');
+				if (cp)
+					*cp = '\0';
+				if (!strcmp(buffer, "handle_softirqs")) {
+					caller = entries[i];
+					break;
+				}
+			}
+		}
+		for (i = 0; i < nr_entries; i++)
+			if (entries[i] == caller)
+				return i + 1;
+	} else if (current->flags & PF_WQ_WORKER) {
+		static unsigned long __data_racy caller;
+
+		if (!caller) {
+			for (i = 0; i < nr_entries; i++) {
+				snprintf(buffer, sizeof(buffer) - 1, "%ps", (void *)entries[i]);
+				cp = strchr(buffer, ' ');
+				if (cp)
+					*cp = '\0';
+				if (!strcmp(buffer, "process_one_work")) {
+					caller = entries[i];
+					break;
+				}
+			}
+		}
+		for (i = 0; i < nr_entries; i++)
+			if (entries[i] == caller)
+				return i + 1;
+	} else {
+		for (i = 0; i < nr_entries; i++) {
+			snprintf(buffer, sizeof(buffer) - 1, "%ps", (void *)entries[i]);
+			cp = strchr(buffer, ' ');
+			if (cp)
+				*cp = '\0';
+			if (buffer[0] == 'k') {
+				if (!strcmp(buffer, "ksys_unshare"))
+					return i + 1;
+			} else if (buffer[0] == 's') {
+				if (!strcmp(buffer, "sock_sendmsg_nosec") ||
+				    !strcmp(buffer, "sock_recvmsg_nosec"))
+					return i + 1;
+			} else if (buffer[0] == '_') {
+				if (!strcmp(buffer, "__sys_bind") ||
+				    !strcmp(buffer, "__sock_release") ||
+				    !strcmp(buffer, "__sys_bpf"))
+					return i + 1;
+			} else {
+				if (!strcmp(buffer, "do_sock_setsockopt"))
+					return i + 1;
+			}
+		}
+	}
+#endif
+	return nr_entries;
+}
+EXPORT_SYMBOL(trim_netdev_trace);
+
+void save_netdev_trace_buffer(struct net_device *dev, int delta)
+{
+	struct netdev_trace_buffer *ptr;
+	unsigned long entries[ARRAY_SIZE(ptr->entries)];
+	unsigned long nr_entries;
+	unsigned long flags;
+
+	if (in_nmi())
+		return;
+	nr_entries = stack_trace_save(entries, ARRAY_SIZE(ptr->entries), 1);
+	nr_entries = trim_netdev_trace(entries, nr_entries);
+	list_for_each_entry_rcu(ptr, &dev->netdev_trace_buffer_list, list,
+				/* list elements can't go away. */ 1) {
+		if (ptr->nr_entries == nr_entries &&
+		    !memcmp(ptr->entries, entries, nr_entries * sizeof(unsigned long))) {
+			atomic_add(delta, &ptr->count);
+			return;
+		}
+	}
+	spin_lock_irqsave(&netdev_trace_buffer_lock, flags);
+	if (!list_empty(&netdev_trace_buffer_list)) {
+		ptr = list_first_entry(&netdev_trace_buffer_list, typeof(*ptr), list);
+		list_del(&ptr->list);
+		ptr->prev_count = 0;
+		atomic_set(&ptr->count, delta);
+		ptr->nr_entries = nr_entries;
+		memmove(ptr->entries, entries, nr_entries * sizeof(unsigned long));
+		list_add_tail_rcu(&ptr->list, &dev->netdev_trace_buffer_list);
+	} else {
+		netdev_trace_buffer_exhausted = true;
+	}
+	spin_unlock_irqrestore(&netdev_trace_buffer_lock, flags);
+}
+EXPORT_SYMBOL(save_netdev_trace_buffer);
+
+#endif
diff --git a/net/core/dst.c b/net/core/dst.c
index 092861133023..45452fa62e24 100644
--- a/net/core/dst.c
+++ b/net/core/dst.c
@@ -44,6 +44,82 @@ const struct dst_metrics dst_default_metrics = {
 };
 EXPORT_SYMBOL(dst_default_metrics);
 
+#ifdef CONFIG_NET_DEV_REFCNT_TRACKER
+
+#define DST_TRACE_BUFFER_SIZE 8192
+static struct dst_trace_buffer {
+	struct dst_entry *dst; // no-ref
+	struct net_device *ndev; // no-ref
+	int seq;
+	int delta;
+	u32 caller_id;
+	int nr_entries;
+	unsigned long entries[20];
+} dst_trace_buffer[DST_TRACE_BUFFER_SIZE];
+static bool dst_trace_buffer_exhausted;
+
+void dump_dst_trace_buffer(const struct net_device *ndev)
+{
+	struct dst_trace_buffer *ptr;
+	int count, balance = 0;
+	int i;
+
+	for (i = 0; i < DST_TRACE_BUFFER_SIZE; i++) {
+		ptr = &dst_trace_buffer[i];
+		if (!ptr->dst || ptr->ndev != ndev)
+			continue;
+		count = ptr->delta;
+		balance += count;
+		pr_info("Call trace for %s@%p[%d] %+d %c%u at\n", ndev->name, ptr->dst, ptr->seq,
+			count, ptr->caller_id & 0x80000000 ? 'C' : 'T',
+			ptr->caller_id & ~0x80000000);
+		stack_trace_print(ptr->entries, ptr->nr_entries, 4);
+	}
+	if (!dst_trace_buffer_exhausted)
+		pr_info("balance for %s@dst_entry is %d\n", ndev->name, balance);
+	else
+		pr_info("balance for %s@dst_entry is unknown\n", ndev->name);
+}
+
+static void erase_dst_trace_buffer(struct dst_entry *dst)
+{
+	int i;
+
+	for (i = 0; i < DST_TRACE_BUFFER_SIZE; i++)
+		if (dst_trace_buffer[i].dst == dst)
+			dst_trace_buffer[i].dst = NULL;
+}
+
+void save_dst_trace_buffer(struct dst_entry *dst, int delta)
+{
+	struct dst_trace_buffer *ptr;
+	unsigned long entries[ARRAY_SIZE(ptr->entries)];
+	unsigned long nr_entries;
+	int i;
+
+	if (!dst->dev)
+		return;
+	nr_entries = stack_trace_save(entries, ARRAY_SIZE(ptr->entries), 1);
+	nr_entries = trim_netdev_trace(entries, nr_entries);
+	for (i = 0; i < DST_TRACE_BUFFER_SIZE; i++) {
+		ptr = &dst_trace_buffer[i];
+		if (!ptr->dst && !cmpxchg(&ptr->dst, NULL, dst)) {
+			ptr->ndev = dst->dev;
+			ptr->seq = atomic_inc_return(&dst->dst_trace_seq);
+			ptr->delta = delta;
+			ptr->caller_id = in_task() ? task_pid_nr(current) :
+				0x80000000 + raw_smp_processor_id();
+			ptr->nr_entries = nr_entries;
+			memmove(ptr->entries, entries, nr_entries * sizeof(unsigned long));
+			return;
+		}
+	}
+	dst_trace_buffer_exhausted = true;
+}
+EXPORT_SYMBOL(save_dst_trace_buffer);
+
+#endif
+
 void dst_init(struct dst_entry *dst, struct dst_ops *ops,
 	      struct net_device *dev, int initial_obsolete,
 	      unsigned short flags)
@@ -67,6 +143,7 @@ void dst_init(struct dst_entry *dst, struct dst_ops *ops,
 #endif
 	dst->lwtstate = NULL;
 	rcuref_init(&dst->__rcuref, 1);
+	save_dst_trace_buffer(dst, 1);
 	INIT_LIST_HEAD(&dst->rt_uncached);
 	dst->rt_uncached_list = NULL;
 	dst->__use = 0;
@@ -116,6 +193,10 @@ static void dst_destroy(struct dst_entry *dst)
 
 	lwtstate_put(dst->lwtstate);
 
+#ifdef CONFIG_NET_DEV_REFCNT_TRACKER
+	erase_dst_trace_buffer(dst);
+#endif
+
 	if (dst->flags & DST_METADATA)
 		metadata_dst_free((struct metadata_dst *)dst);
 	else
@@ -165,6 +246,8 @@ static void dst_count_dec(struct dst_entry *dst)
 
 void dst_release(struct dst_entry *dst)
 {
+	if (dst)
+		save_dst_trace_buffer(dst, -1);
 	if (dst && rcuref_put(&dst->__rcuref)) {
 #ifdef CONFIG_DST_CACHE
 		if (dst->flags & DST_METADATA) {
@@ -182,6 +265,8 @@ EXPORT_SYMBOL(dst_release);
 
 void dst_release_immediate(struct dst_entry *dst)
 {
+	if (dst)
+		save_dst_trace_buffer(dst, -1);
 	if (dst && rcuref_put(&dst->__rcuref)) {
 		dst_count_dec(dst);
 		dst_destroy(dst);
diff --git a/net/core/filter.c b/net/core/filter.c
index 80a3b702a2d4..7cb884ccd1c5 100644
--- a/net/core/filter.c
+++ b/net/core/filter.c
@@ -5688,6 +5688,30 @@ const struct bpf_func_proto bpf_sk_getsockopt_proto = {
 	.arg5_type	= ARG_CONST_SIZE,
 };
 
+BPF_CALL_5(bpf_sk_setsockopt_nodelay, struct sock *, sk, int, level,
+	   int, optname, char *, optval, int, optlen)
+{
+	/*
+	 * TCP_NODELAY triggers tcp_push_pending_frames() and re-enters
+	 * CA_EVENT_TX_START in bpf_tcp_cc.
+	 */
+	if (level == SOL_TCP && optname == TCP_NODELAY)
+		return -EOPNOTSUPP;
+
+	return _bpf_setsockopt(sk, level, optname, optval, optlen);
+}
+
+const struct bpf_func_proto bpf_sk_setsockopt_nodelay_proto = {
+	.func		= bpf_sk_setsockopt_nodelay,
+	.gpl_only	= false,
+	.ret_type	= RET_INTEGER,
+	.arg1_type	= ARG_PTR_TO_BTF_ID_SOCK_COMMON,
+	.arg2_type	= ARG_ANYTHING,
+	.arg3_type	= ARG_ANYTHING,
+	.arg4_type	= ARG_PTR_TO_MEM | MEM_RDONLY,
+	.arg5_type	= ARG_CONST_SIZE,
+};
+
 BPF_CALL_5(bpf_unlocked_sk_setsockopt, struct sock *, sk, int, level,
 	   int, optname, char *, optval, int, optlen)
 {
@@ -5833,6 +5857,12 @@ BPF_CALL_5(bpf_sock_ops_setsockopt, struct bpf_sock_ops_kern *, bpf_sock,
 	if (!is_locked_tcp_sock_ops(bpf_sock))
 		return -EOPNOTSUPP;
 
+	/* TCP_NODELAY triggers tcp_push_pending_frames() and re-enters these callbacks. */
+	if ((bpf_sock->op == BPF_SOCK_OPS_HDR_OPT_LEN_CB ||
+	     bpf_sock->op == BPF_SOCK_OPS_WRITE_HDR_OPT_CB) &&
+	    level == SOL_TCP && optname == TCP_NODELAY)
+		return -EOPNOTSUPP;
+
 	return _bpf_setsockopt(bpf_sock->sk, level, optname, optval, optlen);
 }
 
@@ -6443,6 +6473,8 @@ BPF_CALL_4(bpf_skb_fib_lookup, struct sk_buff *, skb,
 		 * against MTU of FIB lookup resulting net_device
 		 */
 		dev = dev_get_by_index_rcu(net, params->ifindex);
+		if (unlikely(!dev))
+			return -ENODEV;
 		if (!is_skb_forwardable(dev, skb))
 			rc = BPF_FIB_LKUP_RET_FRAG_NEEDED;
 
diff --git a/net/core/lock_debug.c b/net/core/lock_debug.c
index 9e9fb25314b9..78d611bb6d1c 100644
--- a/net/core/lock_debug.c
+++ b/net/core/lock_debug.c
@@ -29,6 +29,7 @@ int netdev_debug_event(struct notifier_block *nb, unsigned long event,
 	case NETDEV_DOWN:
 	case NETDEV_REBOOT:
 	case NETDEV_UNREGISTER:
+	case NETDEV_DEBUG_UNREGISTER:
 	case NETDEV_CHANGEMTU:
 	case NETDEV_CHANGEADDR:
 	case NETDEV_PRE_CHANGEADDR:
diff --git a/net/core/sock_map.c b/net/core/sock_map.c
index 02a68be3002a..99e3789492a0 100644
--- a/net/core/sock_map.c
+++ b/net/core/sock_map.c
@@ -1630,18 +1630,23 @@ void sock_map_unhash(struct sock *sk)
 	void (*saved_unhash)(struct sock *sk);
 	struct sk_psock *psock;
 
+retry:
 	rcu_read_lock();
 	psock = sk_psock(sk);
 	if (unlikely(!psock)) {
 		rcu_read_unlock();
 		saved_unhash = READ_ONCE(sk->sk_prot)->unhash;
+		if (unlikely(saved_unhash == sock_map_unhash))
+			goto retry;
 	} else {
 		saved_unhash = psock->saved_unhash;
 		sock_map_remove_links(sk, psock);
 		rcu_read_unlock();
+
+		if (WARN_ON_ONCE(saved_unhash == sock_map_unhash))
+			return;
 	}
-	if (WARN_ON_ONCE(saved_unhash == sock_map_unhash))
-		return;
+
 	if (saved_unhash)
 		saved_unhash(sk);
 }
@@ -1652,20 +1657,25 @@ void sock_map_destroy(struct sock *sk)
 	void (*saved_destroy)(struct sock *sk);
 	struct sk_psock *psock;
 
+retry:
 	rcu_read_lock();
 	psock = sk_psock_get(sk);
 	if (unlikely(!psock)) {
 		rcu_read_unlock();
 		saved_destroy = READ_ONCE(sk->sk_prot)->destroy;
+		if (unlikely(saved_destroy == sock_map_destroy))
+			goto retry;
 	} else {
 		saved_destroy = psock->saved_destroy;
 		sock_map_remove_links(sk, psock);
 		rcu_read_unlock();
 		sk_psock_stop(psock);
 		sk_psock_put(sk, psock);
+
+		if (WARN_ON_ONCE(saved_destroy == sock_map_destroy))
+			return;
 	}
-	if (WARN_ON_ONCE(saved_destroy == sock_map_destroy))
-		return;
+
 	if (saved_destroy)
 		saved_destroy(sk);
 }
@@ -1676,32 +1686,33 @@ void sock_map_close(struct sock *sk, long timeout)
 	void (*saved_close)(struct sock *sk, long timeout);
 	struct sk_psock *psock;
 
+retry:
 	lock_sock(sk);
 	rcu_read_lock();
-	psock = sk_psock(sk);
+	psock = sk_psock_get(sk);
 	if (likely(psock)) {
 		saved_close = psock->saved_close;
 		sock_map_remove_links(sk, psock);
-		psock = sk_psock_get(sk);
-		if (unlikely(!psock))
-			goto no_psock;
 		rcu_read_unlock();
 		sk_psock_stop(psock);
 		release_sock(sk);
 		cancel_delayed_work_sync(&psock->work);
 		sk_psock_put(sk, psock);
+
+		/* Make sure we do not recurse. This is a bug.
+		 * Leak the socket instead of crashing on a stack overflow.
+		 */
+		if (WARN_ON_ONCE(saved_close == sock_map_close))
+			return;
 	} else {
 		saved_close = READ_ONCE(sk->sk_prot)->close;
-no_psock:
 		rcu_read_unlock();
 		release_sock(sk);
+
+		if (unlikely(saved_close == sock_map_close))
+			goto retry;
 	}
 
-	/* Make sure we do not recurse. This is a bug.
-	 * Leak the socket instead of crashing on a stack overflow.
-	 */
-	if (WARN_ON_ONCE(saved_close == sock_map_close))
-		return;
 	saved_close(sk, timeout);
 }
 EXPORT_SYMBOL_GPL(sock_map_close);
diff --git a/net/ieee802154/core.c b/net/ieee802154/core.c
index 89b671b12600..c0b8712018a1 100644
--- a/net/ieee802154/core.c
+++ b/net/ieee802154/core.c
@@ -228,36 +228,43 @@ int cfg802154_switch_netns(struct cfg802154_registered_device *rdev,
 			continue;
 		wpan_dev->netdev->netns_immutable = false;
 		err = dev_change_net_namespace(wpan_dev->netdev, net, "wpan%d");
-		if (err)
+		if (err) {
+			WARN_ON(err && err != -ENOMEM);
 			break;
+		}
 		wpan_dev->netdev->netns_immutable = true;
 	}
 
-	if (err) {
-		/* failed -- clean up to old netns */
-		net = wpan_phy_net(&rdev->wpan_phy);
-
-		list_for_each_entry_continue_reverse(wpan_dev,
-						     &rdev->wpan_dev_list,
-						     list) {
-			if (!wpan_dev->netdev)
-				continue;
-			wpan_dev->netdev->netns_immutable = false;
-			err = dev_change_net_namespace(wpan_dev->netdev, net,
-						       "wpan%d");
-			WARN_ON(err);
-			wpan_dev->netdev->netns_immutable = true;
-		}
+	if (err)
+		goto errout;
 
-		return err;
-	}
+	err = device_rename(&rdev->wpan_phy.dev, dev_name(&rdev->wpan_phy.dev));
+	WARN_ON(err && err != -ENOMEM);
 
-	wpan_phy_net_set(&rdev->wpan_phy, net);
+	if (err)
+		goto errout;
 
-	err = device_rename(&rdev->wpan_phy.dev, dev_name(&rdev->wpan_phy.dev));
-	WARN_ON(err);
+	wpan_phy_net_set(&rdev->wpan_phy, net);
 
 	return 0;
+
+errout:
+	/* failed -- clean up to old netns */
+	net = wpan_phy_net(&rdev->wpan_phy);
+
+	list_for_each_entry_continue_reverse(wpan_dev,
+					     &rdev->wpan_dev_list,
+					     list) {
+		if (!wpan_dev->netdev)
+			continue;
+		wpan_dev->netdev->netns_immutable = false;
+		err = dev_change_net_namespace(wpan_dev->netdev, net,
+					       "wpan%d");
+		WARN_ON(err && err != -ENOMEM);
+		wpan_dev->netdev->netns_immutable = true;
+	}
+
+	return err;
 }
 
 void cfg802154_dev_free(struct cfg802154_registered_device *rdev)
@@ -351,7 +358,7 @@ static void __net_exit cfg802154_pernet_exit(struct net *net)
 	rtnl_lock();
 	list_for_each_entry(rdev, &cfg802154_rdev_list, list) {
 		if (net_eq(wpan_phy_net(&rdev->wpan_phy), net))
-			WARN_ON(cfg802154_switch_netns(rdev, &init_net));
+			cfg802154_switch_netns(rdev, &init_net);
 	}
 	rtnl_unlock();
 }
diff --git a/net/ipv4/ah4.c b/net/ipv4/ah4.c
index 5fb812443a08..4366cbac3f06 100644
--- a/net/ipv4/ah4.c
+++ b/net/ipv4/ah4.c
@@ -124,9 +124,14 @@ static void ah_output_done(void *data, int err)
 	struct iphdr *top_iph = ip_hdr(skb);
 	struct ip_auth_hdr *ah = ip_auth_hdr(skb);
 	int ihl = ip_hdrlen(skb);
+	int seqhi_len = 0;
+	__be32 *seqhi;
 
+	if (x->props.flags & XFRM_STATE_ESN)
+		seqhi_len = sizeof(*seqhi);
 	iph = AH_SKB_CB(skb)->tmp;
-	icv = ah_tmp_icv(iph, ihl);
+	seqhi = (__be32 *)((char *)iph + ihl);
+	icv = ah_tmp_icv(seqhi, seqhi_len);
 	memcpy(ah->auth_data, icv, ahp->icv_trunc_len);
 
 	top_iph->tos = iph->tos;
@@ -270,12 +275,17 @@ static void ah_input_done(void *data, int err)
 	struct ip_auth_hdr *ah = ip_auth_hdr(skb);
 	int ihl = ip_hdrlen(skb);
 	int ah_hlen = (ah->hdrlen + 2) << 2;
+	int seqhi_len = 0;
+	__be32 *seqhi;
 
 	if (err)
 		goto out;
 
+	if (x->props.flags & XFRM_STATE_ESN)
+		seqhi_len = sizeof(*seqhi);
 	work_iph = AH_SKB_CB(skb)->tmp;
-	auth_data = ah_tmp_auth(work_iph, ihl);
+	seqhi = (__be32 *)((char *)work_iph + ihl);
+	auth_data = ah_tmp_auth(seqhi, seqhi_len);
 	icv = ah_tmp_icv(auth_data, ahp->icv_trunc_len);
 
 	err = crypto_memneq(icv, auth_data, ahp->icv_trunc_len) ? -EBADMSG : 0;
diff --git a/net/ipv4/bpf_tcp_ca.c b/net/ipv4/bpf_tcp_ca.c
index 008edc7f6688..791e15063237 100644
--- a/net/ipv4/bpf_tcp_ca.c
+++ b/net/ipv4/bpf_tcp_ca.c
@@ -168,7 +168,7 @@ bpf_tcp_ca_get_func_proto(enum bpf_func_id func_id,
 		 */
 		if (prog_ops_moff(prog) !=
 		    offsetof(struct tcp_congestion_ops, release))
-			return &bpf_sk_setsockopt_proto;
+			return &bpf_sk_setsockopt_nodelay_proto;
 		return NULL;
 	case BPF_FUNC_getsockopt:
 		/* Since get/setsockopt is usually expected to
diff --git a/net/ipv6/ah6.c b/net/ipv6/ah6.c
index cb26beea4398..de1e68199a01 100644
--- a/net/ipv6/ah6.c
+++ b/net/ipv6/ah6.c
@@ -317,14 +317,19 @@ static void ah6_output_done(void *data, int err)
 	struct ipv6hdr *top_iph = ipv6_hdr(skb);
 	struct ip_auth_hdr *ah = ip_auth_hdr(skb);
 	struct tmp_ext *iph_ext;
+	int seqhi_len = 0;
+	__be32 *seqhi;
 
 	extlen = skb_network_header_len(skb) - sizeof(struct ipv6hdr);
 	if (extlen)
 		extlen += sizeof(*iph_ext);
 
+	if (x->props.flags & XFRM_STATE_ESN)
+		seqhi_len = sizeof(*seqhi);
 	iph_base = AH_SKB_CB(skb)->tmp;
 	iph_ext = ah_tmp_ext(iph_base);
-	icv = ah_tmp_icv(iph_ext, extlen);
+	seqhi = (__be32 *)((char *)iph_ext + extlen);
+	icv = ah_tmp_icv(seqhi, seqhi_len);
 
 	memcpy(ah->auth_data, icv, ahp->icv_trunc_len);
 	memcpy(top_iph, iph_base, IPV6HDR_BASELEN);
@@ -471,13 +476,18 @@ static void ah6_input_done(void *data, int err)
 	struct ip_auth_hdr *ah = ip_auth_hdr(skb);
 	int hdr_len = skb_network_header_len(skb);
 	int ah_hlen = ipv6_authlen(ah);
+	int seqhi_len = 0;
+	__be32 *seqhi;
 
 	if (err)
 		goto out;
 
+	if (x->props.flags & XFRM_STATE_ESN)
+		seqhi_len = sizeof(*seqhi);
 	work_iph = AH_SKB_CB(skb)->tmp;
 	auth_data = ah_tmp_auth(work_iph, hdr_len);
-	icv = ah_tmp_icv(auth_data, ahp->icv_trunc_len);
+	seqhi = (__be32 *)(auth_data + ahp->icv_trunc_len);
+	icv = ah_tmp_icv(seqhi, seqhi_len);
 
 	err = crypto_memneq(icv, auth_data, ahp->icv_trunc_len) ? -EBADMSG : 0;
 	if (err)
diff --git a/net/ipv6/xfrm6_protocol.c b/net/ipv6/xfrm6_protocol.c
index ea2f805d3b01..9b586fcec485 100644
--- a/net/ipv6/xfrm6_protocol.c
+++ b/net/ipv6/xfrm6_protocol.c
@@ -88,8 +88,10 @@ int xfrm6_rcv_encap(struct sk_buff *skb, int nexthdr, __be32 spi,
 
 		dst = ip6_route_input_lookup(dev_net(skb->dev), skb->dev, &fl6,
 					     skb, flags);
-		if (dst->error)
+		if (dst->error) {
+			dst_release(dst);
 			goto drop;
+		}
 		skb_dst_set(skb, dst);
 	}
 
diff --git a/net/socket.c b/net/socket.c
index 22a412fdec07..12324a9967c5 100644
--- a/net/socket.c
+++ b/net/socket.c
@@ -710,7 +710,11 @@ struct socket *sock_alloc(void)
 }
 EXPORT_SYMBOL(sock_alloc);
 
-static void __sock_release(struct socket *sock, struct inode *inode)
+static
+#ifdef CONFIG_NET_DEV_REFCNT_TRACKER
+noinline
+#endif
+void __sock_release(struct socket *sock, struct inode *inode)
 {
 	const struct proto_ops *ops = READ_ONCE(sock->ops);
 
@@ -782,7 +786,13 @@ static noinline void call_trace_sock_send_length(struct sock *sk, int ret,
 	trace_sock_send_length(sk, ret, 0);
 }
 
-static inline int sock_sendmsg_nosec(struct socket *sock, struct msghdr *msg)
+static
+#ifdef CONFIG_NET_DEV_REFCNT_TRACKER
+noinline
+#else
+inline
+#endif
+int sock_sendmsg_nosec(struct socket *sock, struct msghdr *msg)
 {
 	int ret = INDIRECT_CALL_INET(READ_ONCE(sock->ops)->sendmsg, inet6_sendmsg,
 				     inet_sendmsg, sock, msg,
@@ -1131,8 +1141,13 @@ static noinline void call_trace_sock_recv_length(struct sock *sk, int ret, int f
 	trace_sock_recv_length(sk, ret, flags);
 }
 
-static inline int sock_recvmsg_nosec(struct socket *sock, struct msghdr *msg,
-				     int flags)
+static
+#ifdef CONFIG_NET_DEV_REFCNT_TRACKER
+noinline
+#else
+inline
+#endif
+int sock_recvmsg_nosec(struct socket *sock, struct msghdr *msg, int flags)
 {
 	int ret = INDIRECT_CALL_INET(READ_ONCE(sock->ops)->recvmsg,
 				     inet6_recvmsg,
@@ -2638,9 +2653,12 @@ static int copy_msghdr_from_user(struct msghdr *kmsg,
 	return err < 0 ? err : 0;
 }
 
-static int ____sys_sendmsg(struct socket *sock, struct msghdr *msg_sys,
-			   unsigned int flags, struct used_address *used_address,
-			   unsigned int allowed_msghdr_flags)
+static
+#ifdef CONFIG_NET_DEV_REFCNT_TRACKER
+noinline
+#endif
+int ____sys_sendmsg(struct socket *sock, struct msghdr *msg_sys, unsigned int flags,
+		    struct used_address *used_address, unsigned int allowed_msghdr_flags)
 {
 	unsigned char ctl[sizeof(struct cmsghdr) + 20]
 				__aligned(sizeof(__kernel_size_t));
diff --git a/net/sunrpc/Makefile b/net/sunrpc/Makefile
index f89c10fe7e6a..96727df3aa85 100644
--- a/net/sunrpc/Makefile
+++ b/net/sunrpc/Makefile
@@ -14,7 +14,7 @@ sunrpc-y := clnt.o xprt.o socklib.o xprtsock.o sched.o \
 	    addr.o rpcb_clnt.o timer.o xdr.o \
 	    sunrpc_syms.o cache.o rpc_pipe.o sysfs.o \
 	    svc_xprt.o \
-	    xprtmultipath.o
+	    xprtmultipath.o netlink.o
 sunrpc-$(CONFIG_SUNRPC_DEBUG) += debugfs.o
 sunrpc-$(CONFIG_SUNRPC_BACKCHANNEL) += backchannel_rqst.o
 sunrpc-$(CONFIG_PROC_FS) += stats.o
diff --git a/net/sunrpc/auth_gss/svcauth_gss.c b/net/sunrpc/auth_gss/svcauth_gss.c
index 161d02cc1c2c..d14209031e18 100644
--- a/net/sunrpc/auth_gss/svcauth_gss.c
+++ b/net/sunrpc/auth_gss/svcauth_gss.c
@@ -206,7 +206,7 @@ static struct cache_head *rsi_alloc(void)
 
 static int rsi_upcall(struct cache_detail *cd, struct cache_head *h)
 {
-	return sunrpc_cache_pipe_upcall_timeout(cd, h);
+	return sunrpc_cache_upcall_warn(cd, h);
 }
 
 static void rsi_request(struct cache_detail *cd,
diff --git a/net/sunrpc/cache.c b/net/sunrpc/cache.c
index 7081c1214e6c..d477b19dbfa1 100644
--- a/net/sunrpc/cache.c
+++ b/net/sunrpc/cache.c
@@ -33,9 +33,11 @@
 #include <linux/sunrpc/cache.h>
 #include <linux/sunrpc/stats.h>
 #include <linux/sunrpc/rpc_pipe_fs.h>
+#include <net/genetlink.h>
 #include <trace/events/sunrpc.h>
 
 #include "netns.h"
+#include "netlink.h"
 #include "fail.h"
 
 #define	 RPCDBG_FACILITY RPCDBG_CACHE
@@ -1195,12 +1197,12 @@ static bool cache_listeners_exist(struct cache_detail *detail)
 }
 
 /*
- * register an upcall request to user-space and queue it up for read() by the
- * upcall daemon.
+ * register an upcall request to user-space and queue it up to be fetched by
+ * the upcall daemon.
  *
  * Each request is at most one page long.
  */
-static int cache_pipe_upcall(struct cache_detail *detail, struct cache_head *h)
+static int cache_do_upcall(struct cache_detail *detail, struct cache_head *h)
 {
 	char *buf;
 	struct cache_request *crq;
@@ -1233,6 +1235,8 @@ static int cache_pipe_upcall(struct cache_detail *detail, struct cache_head *h)
 		/* Lost a race, no longer PENDING, so don't enqueue */
 		ret = -EAGAIN;
 	spin_unlock(&detail->queue_lock);
+	if (ret != -EAGAIN && detail->cache_notify)
+		detail->cache_notify(detail, h);
 	wake_up(&detail->queue_wait);
 	if (ret == -EAGAIN) {
 		kfree(buf);
@@ -1241,25 +1245,25 @@ static int cache_pipe_upcall(struct cache_detail *detail, struct cache_head *h)
 	return ret;
 }
 
-int sunrpc_cache_pipe_upcall(struct cache_detail *detail, struct cache_head *h)
+int sunrpc_cache_upcall(struct cache_detail *detail, struct cache_head *h)
 {
 	if (test_and_set_bit(CACHE_PENDING, &h->flags))
 		return 0;
-	return cache_pipe_upcall(detail, h);
+	return cache_do_upcall(detail, h);
 }
-EXPORT_SYMBOL_GPL(sunrpc_cache_pipe_upcall);
+EXPORT_SYMBOL_GPL(sunrpc_cache_upcall);
 
-int sunrpc_cache_pipe_upcall_timeout(struct cache_detail *detail,
-				     struct cache_head *h)
+int sunrpc_cache_upcall_warn(struct cache_detail *detail,
+			     struct cache_head *h)
 {
 	if (!cache_listeners_exist(detail)) {
 		warn_no_listener(detail);
 		trace_cache_entry_no_listener(detail, h);
 		return -EINVAL;
 	}
-	return sunrpc_cache_pipe_upcall(detail, h);
+	return sunrpc_cache_upcall(detail, h);
 }
-EXPORT_SYMBOL_GPL(sunrpc_cache_pipe_upcall_timeout);
+EXPORT_SYMBOL_GPL(sunrpc_cache_upcall_warn);
 
 /*
  * parse a message from user-space and pass it
@@ -1897,3 +1901,106 @@ void sunrpc_cache_unhash(struct cache_detail *cd, struct cache_head *h)
 		spin_unlock(&cd->hash_lock);
 }
 EXPORT_SYMBOL_GPL(sunrpc_cache_unhash);
+
+/**
+ * sunrpc_cache_requests_count - count pending upcall requests
+ * @cd: cache_detail to query
+ *
+ * Returns the number of requests on the cache's request list that
+ * still have CACHE_PENDING set.
+ */
+int sunrpc_cache_requests_count(struct cache_detail *cd)
+{
+	struct cache_request *crq;
+	int cnt = 0;
+
+	spin_lock(&cd->queue_lock);
+	list_for_each_entry(crq, &cd->requests, list) {
+		if (test_bit(CACHE_PENDING, &crq->item->flags))
+			cnt++;
+	}
+	spin_unlock(&cd->queue_lock);
+	return cnt;
+}
+EXPORT_SYMBOL_GPL(sunrpc_cache_requests_count);
+
+/**
+ * sunrpc_cache_requests_snapshot - snapshot pending upcall requests
+ * @cd: cache_detail to query
+ * @items: array to fill with cache_head pointers (caller-allocated)
+ * @seqnos: array to fill with sequence numbers (caller-allocated)
+ * @max: size of the arrays
+ * @min_seqno: only include entries with seqno > min_seqno (0 for all)
+ *
+ * Only entries with CACHE_PENDING set are included. Takes a reference
+ * on each cache_head via cache_get(). Caller must call cache_put()
+ * on each returned item when done.
+ *
+ * Returns the number of entries filled.
+ */
+int sunrpc_cache_requests_snapshot(struct cache_detail *cd,
+				   struct cache_head **items,
+				   u64 *seqnos, int max,
+				   u64 min_seqno)
+{
+	struct cache_request *crq;
+	int i = 0;
+
+	spin_lock(&cd->queue_lock);
+	list_for_each_entry(crq, &cd->requests, list) {
+		if (i >= max)
+			break;
+		if (!test_bit(CACHE_PENDING, &crq->item->flags))
+			continue;
+		if (crq->seqno <= min_seqno)
+			continue;
+		items[i] = cache_get(crq->item);
+		seqnos[i] = crq->seqno;
+		i++;
+	}
+	spin_unlock(&cd->queue_lock);
+	return i;
+}
+EXPORT_SYMBOL_GPL(sunrpc_cache_requests_snapshot);
+
+/**
+ * sunrpc_cache_notify - send a netlink notification for a cache event
+ * @cd: cache_detail for the cache
+ * @h: cache_head entry (unused, reserved for future use)
+ * @cache_type: cache type identifier (e.g. SUNRPC_CACHE_TYPE_UNIX_GID)
+ *
+ * Sends a SUNRPC_CMD_CACHE_NOTIFY multicast message on the "exportd"
+ * group if any listeners are present. Returns 0 on success or a
+ * negative errno.
+ */
+int sunrpc_cache_notify(struct cache_detail *cd, struct cache_head *h,
+			u32 cache_type)
+{
+	struct genlmsghdr *hdr;
+	struct sk_buff *msg;
+
+	if (!genl_has_listeners(&sunrpc_nl_family, cd->net,
+				SUNRPC_NLGRP_EXPORTD))
+		return -ENOLINK;
+
+	msg = genlmsg_new(nla_total_size(sizeof(u32)), GFP_KERNEL);
+	if (!msg)
+		return -ENOMEM;
+
+	hdr = genlmsg_put(msg, 0, 0, &sunrpc_nl_family, 0,
+			  SUNRPC_CMD_CACHE_NOTIFY);
+	if (!hdr) {
+		nlmsg_free(msg);
+		return -ENOMEM;
+	}
+
+	if (nla_put_u32(msg, SUNRPC_A_CACHE_NOTIFY_CACHE_TYPE, cache_type)) {
+		nlmsg_free(msg);
+		return -ENOMEM;
+	}
+
+	genlmsg_end(msg, hdr);
+	return genlmsg_multicast_netns(&sunrpc_nl_family, cd->net, msg, 0,
+				       SUNRPC_NLGRP_EXPORTD, GFP_KERNEL);
+}
+EXPORT_SYMBOL_GPL(sunrpc_cache_notify);
diff --git a/net/sunrpc/netlink.c b/net/sunrpc/netlink.c
new file mode 100644
index 000000000000..ce09ecc0faa2
--- /dev/null
+++ b/net/sunrpc/netlink.c
@@ -0,0 +1,97 @@
+// SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause)
+/* Do not edit directly, auto-generated from: */
+/*	Documentation/netlink/specs/sunrpc_cache.yaml */
+/* YNL-GEN kernel source */
+/* To regenerate run: tools/net/ynl/ynl-regen.sh */
+
+#include <net/netlink.h>
+#include <net/genetlink.h>
+
+#include "netlink.h"
+
+#include <uapi/linux/sunrpc_netlink.h>
+
+/* Common nested types */
+const struct nla_policy sunrpc_ip_map_nl_policy[SUNRPC_A_IP_MAP_EXPIRY + 1] = {
+	[SUNRPC_A_IP_MAP_SEQNO] = { .type = NLA_U64, },
+	[SUNRPC_A_IP_MAP_CLASS] = { .type = NLA_NUL_STRING, },
+	[SUNRPC_A_IP_MAP_ADDR] = { .type = NLA_NUL_STRING, },
+	[SUNRPC_A_IP_MAP_DOMAIN] = { .type = NLA_NUL_STRING, },
+	[SUNRPC_A_IP_MAP_NEGATIVE] = { .type = NLA_FLAG, },
+	[SUNRPC_A_IP_MAP_EXPIRY] = { .type = NLA_U64, },
+};
+
+const struct nla_policy sunrpc_unix_gid_nl_policy[SUNRPC_A_UNIX_GID_EXPIRY + 1] = {
+	[SUNRPC_A_UNIX_GID_SEQNO] = { .type = NLA_U64, },
+	[SUNRPC_A_UNIX_GID_UID] = { .type = NLA_U32, },
+	[SUNRPC_A_UNIX_GID_GIDS] = { .type = NLA_U32, },
+	[SUNRPC_A_UNIX_GID_NEGATIVE] = { .type = NLA_FLAG, },
+	[SUNRPC_A_UNIX_GID_EXPIRY] = { .type = NLA_U64, },
+};
+
+/* SUNRPC_CMD_IP_MAP_SET_REQS - do */
+static const struct nla_policy sunrpc_ip_map_set_reqs_nl_policy[SUNRPC_A_IP_MAP_REQS_REQUESTS + 1] = {
+	[SUNRPC_A_IP_MAP_REQS_REQUESTS] = NLA_POLICY_NESTED(sunrpc_ip_map_nl_policy),
+};
+
+/* SUNRPC_CMD_UNIX_GID_SET_REQS - do */
+static const struct nla_policy sunrpc_unix_gid_set_reqs_nl_policy[SUNRPC_A_UNIX_GID_REQS_REQUESTS + 1] = {
+	[SUNRPC_A_UNIX_GID_REQS_REQUESTS] = NLA_POLICY_NESTED(sunrpc_unix_gid_nl_policy),
+};
+
+/* SUNRPC_CMD_CACHE_FLUSH - do */
+static const struct nla_policy sunrpc_cache_flush_nl_policy[SUNRPC_A_CACHE_FLUSH_MASK + 1] = {
+	[SUNRPC_A_CACHE_FLUSH_MASK] = NLA_POLICY_MASK(NLA_U32, 0x3),
+};
+
+/* Ops table for sunrpc */
+static const struct genl_split_ops sunrpc_nl_ops[] = {
+	{
+		.cmd	= SUNRPC_CMD_IP_MAP_GET_REQS,
+		.dumpit	= sunrpc_nl_ip_map_get_reqs_dumpit,
+		.flags	= GENL_ADMIN_PERM | GENL_CMD_CAP_DUMP,
+	},
+	{
+		.cmd		= SUNRPC_CMD_IP_MAP_SET_REQS,
+		.doit		= sunrpc_nl_ip_map_set_reqs_doit,
+		.policy		= sunrpc_ip_map_set_reqs_nl_policy,
+		.maxattr	= SUNRPC_A_IP_MAP_REQS_REQUESTS,
+		.flags		= GENL_ADMIN_PERM | GENL_CMD_CAP_DO,
+	},
+	{
+		.cmd	= SUNRPC_CMD_UNIX_GID_GET_REQS,
+		.dumpit	= sunrpc_nl_unix_gid_get_reqs_dumpit,
+		.flags	= GENL_ADMIN_PERM | GENL_CMD_CAP_DUMP,
+	},
+	{
+		.cmd		= SUNRPC_CMD_UNIX_GID_SET_REQS,
+		.doit		= sunrpc_nl_unix_gid_set_reqs_doit,
+		.policy		= sunrpc_unix_gid_set_reqs_nl_policy,
+		.maxattr	= SUNRPC_A_UNIX_GID_REQS_REQUESTS,
+		.flags		= GENL_ADMIN_PERM | GENL_CMD_CAP_DO,
+	},
+	{
+		.cmd		= SUNRPC_CMD_CACHE_FLUSH,
+		.doit		= sunrpc_nl_cache_flush_doit,
+		.policy		= sunrpc_cache_flush_nl_policy,
+		.maxattr	= SUNRPC_A_CACHE_FLUSH_MASK,
+		.flags		= GENL_ADMIN_PERM | GENL_CMD_CAP_DO,
+	},
+};
+
+static const struct genl_multicast_group sunrpc_nl_mcgrps[] = {
+	[SUNRPC_NLGRP_NONE] = { "none", },
+	[SUNRPC_NLGRP_EXPORTD] = { "exportd", },
+};
+
+struct genl_family sunrpc_nl_family __ro_after_init = {
+	.name		= SUNRPC_FAMILY_NAME,
+	.version	= SUNRPC_FAMILY_VERSION,
+	.netnsok	= true,
+	.parallel_ops	= true,
+	.module		= THIS_MODULE,
+	.split_ops	= sunrpc_nl_ops,
+	.n_split_ops	= ARRAY_SIZE(sunrpc_nl_ops),
+	.mcgrps		= sunrpc_nl_mcgrps,
+	.n_mcgrps	= ARRAY_SIZE(sunrpc_nl_mcgrps),
+};
diff --git a/net/sunrpc/netlink.h b/net/sunrpc/netlink.h
new file mode 100644
index 000000000000..2c1012303d48
--- /dev/null
+++ b/net/sunrpc/netlink.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) */
+/* Do not edit directly, auto-generated from: */
+/*	Documentation/netlink/specs/sunrpc_cache.yaml */
+/* YNL-GEN kernel header */
+/* To regenerate run: tools/net/ynl/ynl-regen.sh */
+
+#ifndef _LINUX_SUNRPC_GEN_H
+#define _LINUX_SUNRPC_GEN_H
+
+#include <net/netlink.h>
+#include <net/genetlink.h>
+
+#include <uapi/linux/sunrpc_netlink.h>
+
+/* Common nested types */
+extern const struct nla_policy sunrpc_ip_map_nl_policy[SUNRPC_A_IP_MAP_EXPIRY + 1];
+extern const struct nla_policy sunrpc_unix_gid_nl_policy[SUNRPC_A_UNIX_GID_EXPIRY + 1];
+
+int sunrpc_nl_ip_map_get_reqs_dumpit(struct sk_buff *skb,
+				     struct netlink_callback *cb);
+int sunrpc_nl_ip_map_set_reqs_doit(struct sk_buff *skb, struct genl_info *info);
+int sunrpc_nl_unix_gid_get_reqs_dumpit(struct sk_buff *skb,
+				       struct netlink_callback *cb);
+int sunrpc_nl_unix_gid_set_reqs_doit(struct sk_buff *skb,
+				     struct genl_info *info);
+int sunrpc_nl_cache_flush_doit(struct sk_buff *skb, struct genl_info *info);
+
+enum {
+	SUNRPC_NLGRP_NONE,
+	SUNRPC_NLGRP_EXPORTD,
+};
+
+extern struct genl_family sunrpc_nl_family;
+
+#endif /* _LINUX_SUNRPC_GEN_H */
diff --git a/net/sunrpc/sunrpc_syms.c b/net/sunrpc/sunrpc_syms.c
index bab6cab29405..ab88ce46afb5 100644
--- a/net/sunrpc/sunrpc_syms.c
+++ b/net/sunrpc/sunrpc_syms.c
@@ -23,9 +23,12 @@
 #include <linux/sunrpc/rpc_pipe_fs.h>
 #include <linux/sunrpc/xprtsock.h>
 
+#include <net/genetlink.h>
+
 #include "sunrpc.h"
 #include "sysfs.h"
 #include "netns.h"
+#include "netlink.h"
 
 unsigned int sunrpc_net_id;
 EXPORT_SYMBOL_GPL(sunrpc_net_id);
@@ -108,6 +111,10 @@ init_sunrpc(void)
 	if (err)
 		goto out5;
 
+	err = genl_register_family(&sunrpc_nl_family);
+	if (err)
+		goto out6;
+
 	sunrpc_debugfs_init();
 #if IS_ENABLED(CONFIG_SUNRPC_DEBUG)
 	rpc_register_sysctl();
@@ -116,6 +123,8 @@ init_sunrpc(void)
 	init_socket_xprt();	/* clnt sock transport */
 	return 0;
 
+out6:
+	rpc_sysfs_exit();
 out5:
 	unregister_rpc_pipefs();
 out4:
@@ -131,6 +140,7 @@ init_sunrpc(void)
 static void __exit
 cleanup_sunrpc(void)
 {
+	genl_unregister_family(&sunrpc_nl_family);
 	rpc_sysfs_exit();
 	rpc_cleanup_clids();
 	xprt_cleanup_ids();
diff --git a/net/sunrpc/svc_xprt.c b/net/sunrpc/svc_xprt.c
index b16e710926c1..63d1002e63e7 100644
--- a/net/sunrpc/svc_xprt.c
+++ b/net/sunrpc/svc_xprt.c
@@ -234,7 +234,19 @@ void svc_xprt_received(struct svc_xprt *xprt)
 	svc_xprt_get(xprt);
 	smp_mb__before_atomic();
 	clear_bit(XPT_BUSY, &xprt->xpt_flags);
-	svc_xprt_enqueue(xprt);
+
+	/*
+	 * Skip the enqueue when no actionable flags are set.
+	 * Each producer both sets its flag (XPT_DATA, XPT_CLOSE,
+	 * etc.) and calls svc_xprt_enqueue(); if a set_bit races
+	 * with this check, the producer's own enqueue observes
+	 * !XPT_BUSY and dispatches the transport.
+	 */
+	if (READ_ONCE(xprt->xpt_flags) &
+	    (BIT(XPT_CONN) | BIT(XPT_CLOSE) | BIT(XPT_HANDSHAKE) |
+	     BIT(XPT_DATA) | BIT(XPT_DEFERRED)))
+		svc_xprt_enqueue(xprt);
+
 	svc_xprt_put(xprt);
 }
 EXPORT_SYMBOL_GPL(svc_xprt_received);
@@ -425,13 +437,35 @@ static bool svc_xprt_reserve_slot(struct svc_rqst *rqstp, struct svc_xprt *xprt)
 	return true;
 }
 
+/*
+ * After a caller releases write-space or a request slot,
+ * re-enqueue the transport only when there is pending
+ * work that a thread could act on.  The smp_mb() pairs
+ * with the smp_rmb() in svc_xprt_ready() and orders the
+ * preceding counter update before the flags read so a
+ * concurrent set_bit(XPT_DATA) is visible here.
+ *
+ * When the transport is BUSY, the thread holding it will
+ * call svc_xprt_received() upon completion, which checks
+ * for pending work and re-enqueues as needed.
+ */
+static void svc_xprt_resource_released(struct svc_xprt *xprt)
+{
+	unsigned long xpt_flags;
+
+	smp_mb();
+	xpt_flags = READ_ONCE(xprt->xpt_flags);
+	if (xpt_flags & (BIT(XPT_DATA) | BIT(XPT_DEFERRED)) &&
+	    !(xpt_flags & BIT(XPT_BUSY)))
+		svc_xprt_enqueue(xprt);
+}
+
 static void svc_xprt_release_slot(struct svc_rqst *rqstp)
 {
 	struct svc_xprt	*xprt = rqstp->rq_xprt;
 	if (test_and_clear_bit(RQ_DATA, &rqstp->rq_flags)) {
 		atomic_dec(&xprt->xpt_nr_rqsts);
-		smp_wmb(); /* See smp_rmb() in svc_xprt_ready() */
-		svc_xprt_enqueue(xprt);
+		svc_xprt_resource_released(xprt);
 	}
 }
 
@@ -525,10 +559,10 @@ void svc_reserve(struct svc_rqst *rqstp, int space)
 	space += rqstp->rq_res.head[0].iov_len;
 
 	if (xprt && space < rqstp->rq_reserved) {
-		atomic_sub((rqstp->rq_reserved - space), &xprt->xpt_reserved);
+		atomic_sub((rqstp->rq_reserved - space),
+			   &xprt->xpt_reserved);
 		rqstp->rq_reserved = space;
-		smp_wmb(); /* See smp_rmb() in svc_xprt_ready() */
-		svc_xprt_enqueue(xprt);
+		svc_xprt_resource_released(xprt);
 	}
 }
 EXPORT_SYMBOL_GPL(svc_reserve);
diff --git a/net/sunrpc/svcauth_unix.c b/net/sunrpc/svcauth_unix.c
index 3be69c145d2a..64a2658faddb 100644
--- a/net/sunrpc/svcauth_unix.c
+++ b/net/sunrpc/svcauth_unix.c
@@ -17,11 +17,14 @@
 #include <net/ipv6.h>
 #include <linux/kernel.h>
 #include <linux/user_namespace.h>
+#include <net/genetlink.h>
+#include <uapi/linux/sunrpc_netlink.h>
 #include <trace/events/sunrpc.h>
 
 #define RPCDBG_FACILITY	RPCDBG_AUTH
 
 #include "netns.h"
+#include "netlink.h"
 
 /*
  * AUTHUNIX and AUTHNULL credentials are both handled here.
@@ -152,7 +155,7 @@ static struct cache_head *ip_map_alloc(void)
 
 static int ip_map_upcall(struct cache_detail *cd, struct cache_head *h)
 {
-	return sunrpc_cache_pipe_upcall(cd, h);
+	return sunrpc_cache_upcall(cd, h);
 }
 
 static void ip_map_request(struct cache_detail *cd,
@@ -467,7 +470,7 @@ static struct cache_head *unix_gid_alloc(void)
 
 static int unix_gid_upcall(struct cache_detail *cd, struct cache_head *h)
 {
-	return sunrpc_cache_pipe_upcall_timeout(cd, h);
+	return sunrpc_cache_upcall_warn(cd, h);
 }
 
 static void unix_gid_request(struct cache_detail *cd,
@@ -582,12 +585,278 @@ static int unix_gid_show(struct seq_file *m,
 	return 0;
 }
 
+static int unix_gid_notify(struct cache_detail *cd, struct cache_head *h)
+{
+	return sunrpc_cache_notify(cd, h, SUNRPC_CACHE_TYPE_UNIX_GID);
+}
+
+/**
+ * sunrpc_nl_unix_gid_get_reqs_dumpit - dump pending unix_gid requests
+ * @skb: reply buffer
+ * @cb: netlink metadata and command arguments
+ *
+ * Walk the unix_gid cache's pending request list and create a netlink
+ * message with a nested entry for each cache_request, containing the
+ * seqno and uid.
+ *
+ * Uses cb->args[0] as a seqno cursor for dump continuation across
+ * multiple netlink messages.
+ *
+ * Returns the size of the reply or a negative errno.
+ */
+int sunrpc_nl_unix_gid_get_reqs_dumpit(struct sk_buff *skb,
+					struct netlink_callback *cb)
+{
+	struct sunrpc_net *sn;
+	struct cache_detail *cd;
+	struct cache_head **items;
+	u64 *seqnos;
+	int cnt, i, emitted;
+	void *hdr;
+	int ret;
+
+	sn = net_generic(sock_net(skb->sk), sunrpc_net_id);
+
+	cd = sn->unix_gid_cache;
+	if (!cd)
+		return -ENODEV;
+
+	cnt = sunrpc_cache_requests_count(cd);
+	if (!cnt)
+		return 0;
+
+	items = kcalloc(cnt, sizeof(*items), GFP_KERNEL);
+	seqnos = kcalloc(cnt, sizeof(*seqnos), GFP_KERNEL);
+	if (!items || !seqnos) {
+		ret = -ENOMEM;
+		goto out_alloc;
+	}
+
+	cnt = sunrpc_cache_requests_snapshot(cd, items, seqnos, cnt,
+					     cb->args[0]);
+	if (!cnt) {
+		ret = 0;
+		goto out_alloc;
+	}
+
+	hdr = genlmsg_put(skb, NETLINK_CB(cb->skb).portid,
+			  cb->nlh->nlmsg_seq, &sunrpc_nl_family,
+			  NLM_F_MULTI, SUNRPC_CMD_UNIX_GID_GET_REQS);
+	if (!hdr) {
+		ret = -ENOBUFS;
+		goto out_put;
+	}
+
+	emitted = 0;
+	for (i = 0; i < cnt; i++) {
+		struct unix_gid *ug;
+		struct nlattr *nest;
+
+		ug = container_of(items[i], struct unix_gid, h);
+
+		nest = nla_nest_start(skb,
+				      SUNRPC_A_UNIX_GID_REQS_REQUESTS);
+		if (!nest)
+			break;
+
+		if (nla_put_u64_64bit(skb, SUNRPC_A_UNIX_GID_SEQNO,
+				      seqnos[i], 0) ||
+		    nla_put_u32(skb, SUNRPC_A_UNIX_GID_UID,
+				from_kuid(&init_user_ns, ug->uid))) {
+			nla_nest_cancel(skb, nest);
+			break;
+		}
+
+		nla_nest_end(skb, nest);
+		cb->args[0] = seqnos[i];
+		emitted++;
+	}
+
+	if (!emitted) {
+		genlmsg_cancel(skb, hdr);
+		ret = -EMSGSIZE;
+		goto out_put;
+	}
+
+	genlmsg_end(skb, hdr);
+	ret = skb->len;
+out_put:
+	for (i = 0; i < cnt; i++)
+		cache_put(items[i], cd);
+out_alloc:
+	kfree(seqnos);
+	kfree(items);
+	return ret;
+}
+
+/**
+ * sunrpc_nl_parse_one_unix_gid - parse one unix_gid entry from netlink
+ * @cd: cache_detail for the unix_gid cache
+ * @attr: nested attribute containing unix_gid fields
+ *
+ * Parses one unix_gid entry from a netlink message and updates the
+ * cache. Mirrors the logic in unix_gid_parse().
+ *
+ * Returns 0 on success or a negative errno.
+ */
+static int sunrpc_nl_parse_one_unix_gid(struct cache_detail *cd,
+					 struct nlattr *attr)
+{
+	struct nlattr *tb[SUNRPC_A_UNIX_GID_EXPIRY + 1];
+	struct unix_gid ug, *ugp;
+	struct timespec64 boot;
+	struct nlattr *gid_attr;
+	int err, rem, gids = 0;
+	kuid_t uid;
+
+	err = nla_parse_nested(tb, SUNRPC_A_UNIX_GID_EXPIRY, attr,
+			       sunrpc_unix_gid_nl_policy, NULL);
+	if (err)
+		return err;
+
+	/* uid (required) */
+	if (!tb[SUNRPC_A_UNIX_GID_UID])
+		return -EINVAL;
+	uid = make_kuid(current_user_ns(),
+			nla_get_u32(tb[SUNRPC_A_UNIX_GID_UID]));
+	ug.uid = uid;
+
+	/* expiry (required, wallclock seconds) */
+	if (!tb[SUNRPC_A_UNIX_GID_EXPIRY])
+		return -EINVAL;
+	getboottime64(&boot);
+	ug.h.flags = 0;
+	ug.h.expiry_time = nla_get_u64(tb[SUNRPC_A_UNIX_GID_EXPIRY]) -
+			   boot.tv_sec;
+
+	if (tb[SUNRPC_A_UNIX_GID_NEGATIVE]) {
+		ug.gi = groups_alloc(0);
+		if (!ug.gi)
+			return -ENOMEM;
+	} else {
+		/* Count gids */
+		nla_for_each_nested_type(gid_attr, SUNRPC_A_UNIX_GID_GIDS,
+					 attr, rem)
+			gids++;
+
+		if (gids > 8192)
+			return -EINVAL;
+
+		ug.gi = groups_alloc(gids);
+		if (!ug.gi)
+			return -ENOMEM;
+
+		gids = 0;
+		nla_for_each_nested_type(gid_attr, SUNRPC_A_UNIX_GID_GIDS,
+					 attr, rem) {
+			kgid_t kgid;
+
+			kgid = make_kgid(current_user_ns(),
+					 nla_get_u32(gid_attr));
+			if (!gid_valid(kgid)) {
+				err = -EINVAL;
+				goto out;
+			}
+			ug.gi->gid[gids++] = kgid;
+		}
+		groups_sort(ug.gi);
+	}
+
+	ugp = unix_gid_lookup(cd, uid);
+	if (ugp) {
+		struct cache_head *ch;
+
+		ch = sunrpc_cache_update(cd, &ug.h, &ugp->h,
+					 unix_gid_hash(uid));
+		if (!ch) {
+			err = -ENOMEM;
+		} else {
+			err = 0;
+			cache_put(ch, cd);
+		}
+	} else {
+		err = -ENOMEM;
+	}
+out:
+	if (ug.gi)
+		put_group_info(ug.gi);
+	return err;
+}
+
+/**
+ * sunrpc_nl_unix_gid_set_reqs_doit - respond to unix_gid requests
+ * @skb: reply buffer
+ * @info: netlink metadata and command arguments
+ *
+ * Parse one or more unix_gid cache responses from userspace and
+ * update the unix_gid cache accordingly.
+ *
+ * Returns 0 on success or a negative errno.
+ */
+int sunrpc_nl_unix_gid_set_reqs_doit(struct sk_buff *skb,
+				     struct genl_info *info)
+{
+	struct sunrpc_net *sn;
+	struct cache_detail *cd;
+	const struct nlattr *attr;
+	int rem, ret = 0;
+
+	sn = net_generic(genl_info_net(info), sunrpc_net_id);
+
+	cd = sn->unix_gid_cache;
+	if (!cd)
+		return -ENODEV;
+
+	nlmsg_for_each_attr_type(attr, SUNRPC_A_UNIX_GID_REQS_REQUESTS,
+				 info->nlhdr, GENL_HDRLEN, rem) {
+		ret = sunrpc_nl_parse_one_unix_gid(cd,
+						   (struct nlattr *)attr);
+		if (ret)
+			break;
+	}
+
+	return ret;
+}
+
+/**
+ * sunrpc_nl_cache_flush_doit - flush sunrpc caches via netlink
+ * @skb: reply buffer
+ * @info: netlink metadata and command arguments
+ *
+ * Flush the ip_map and/or unix_gid caches. If SUNRPC_A_CACHE_FLUSH_MASK
+ * is provided, only flush the caches indicated by the bitmask (bit 1 =
+ * ip_map, bit 2 = unix_gid). If omitted, flush both.
+ *
+ * Return 0 on success or a negative errno.
+ */
+int sunrpc_nl_cache_flush_doit(struct sk_buff *skb, struct genl_info *info)
+{
+	struct sunrpc_net *sn;
+	u32 mask = ~0U;
+
+	sn = net_generic(genl_info_net(info), sunrpc_net_id);
+
+	if (info->attrs[SUNRPC_A_CACHE_FLUSH_MASK])
+		mask = nla_get_u32(info->attrs[SUNRPC_A_CACHE_FLUSH_MASK]);
+
+	if ((mask & SUNRPC_CACHE_TYPE_IP_MAP) &&
+	    sn->ip_map_cache)
+		cache_purge(sn->ip_map_cache);
+
+	if ((mask & SUNRPC_CACHE_TYPE_UNIX_GID) &&
+	    sn->unix_gid_cache)
+		cache_purge(sn->unix_gid_cache);
+
+	return 0;
+}
+
 static const struct cache_detail unix_gid_cache_template = {
 	.owner		= THIS_MODULE,
 	.hash_size	= GID_HASHMAX,
 	.name		= "auth.unix.gid",
 	.cache_put	= unix_gid_put,
 	.cache_upcall	= unix_gid_upcall,
+	.cache_notify	= unix_gid_notify,
 	.cache_request	= unix_gid_request,
 	.cache_parse	= unix_gid_parse,
 	.cache_show	= unix_gid_show,
@@ -1017,12 +1286,255 @@ struct auth_ops svcauth_unix = {
 	.set_client	= svcauth_unix_set_client,
 };
 
+static int ip_map_notify(struct cache_detail *cd, struct cache_head *h)
+{
+	return sunrpc_cache_notify(cd, h, SUNRPC_CACHE_TYPE_IP_MAP);
+}
+
+/**
+ * sunrpc_nl_ip_map_get_reqs_dumpit - dump pending ip_map requests
+ * @skb: reply buffer
+ * @cb: netlink metadata and command arguments
+ *
+ * Walk the ip_map cache's pending request list and create a netlink
+ * message with a nested entry for each cache_request, containing the
+ * seqno, class and addr.
+ *
+ * Uses cb->args[0] as a seqno cursor for dump continuation across
+ * multiple netlink messages.
+ *
+ * Returns the size of the reply or a negative errno.
+ */
+int sunrpc_nl_ip_map_get_reqs_dumpit(struct sk_buff *skb,
+				     struct netlink_callback *cb)
+{
+	struct sunrpc_net *sn;
+	struct cache_detail *cd;
+	struct cache_head **items;
+	u64 *seqnos;
+	int cnt, i, emitted;
+	void *hdr;
+	int ret;
+
+	sn = net_generic(sock_net(skb->sk), sunrpc_net_id);
+
+	cd = sn->ip_map_cache;
+	if (!cd)
+		return -ENODEV;
+
+	cnt = sunrpc_cache_requests_count(cd);
+	if (!cnt)
+		return 0;
+
+	items = kcalloc(cnt, sizeof(*items), GFP_KERNEL);
+	seqnos = kcalloc(cnt, sizeof(*seqnos), GFP_KERNEL);
+	if (!items || !seqnos) {
+		ret = -ENOMEM;
+		goto out_alloc;
+	}
+
+	cnt = sunrpc_cache_requests_snapshot(cd, items, seqnos, cnt,
+					     cb->args[0]);
+	if (!cnt) {
+		ret = 0;
+		goto out_alloc;
+	}
+
+	hdr = genlmsg_put(skb, NETLINK_CB(cb->skb).portid,
+			  cb->nlh->nlmsg_seq, &sunrpc_nl_family,
+			  NLM_F_MULTI, SUNRPC_CMD_IP_MAP_GET_REQS);
+	if (!hdr) {
+		ret = -ENOBUFS;
+		goto out_put;
+	}
+
+	emitted = 0;
+	for (i = 0; i < cnt; i++) {
+		struct ip_map *im;
+		struct nlattr *nest;
+		char text_addr[40];
+
+		im = container_of(items[i], struct ip_map, h);
+
+		if (ipv6_addr_v4mapped(&im->m_addr))
+			snprintf(text_addr, 20, "%pI4",
+				 &im->m_addr.s6_addr32[3]);
+		else
+			snprintf(text_addr, 40, "%pI6", &im->m_addr);
+
+		nest = nla_nest_start(skb, SUNRPC_A_IP_MAP_REQS_REQUESTS);
+		if (!nest)
+			break;
+
+		if (nla_put_u64_64bit(skb, SUNRPC_A_IP_MAP_SEQNO,
+				      seqnos[i], 0) ||
+		    nla_put_string(skb, SUNRPC_A_IP_MAP_CLASS,
+				   im->m_class) ||
+		    nla_put_string(skb, SUNRPC_A_IP_MAP_ADDR, text_addr)) {
+			nla_nest_cancel(skb, nest);
+			break;
+		}
+
+		nla_nest_end(skb, nest);
+		cb->args[0] = seqnos[i];
+		emitted++;
+	}
+
+	if (!emitted) {
+		genlmsg_cancel(skb, hdr);
+		ret = -EMSGSIZE;
+		goto out_put;
+	}
+
+	genlmsg_end(skb, hdr);
+	ret = skb->len;
+out_put:
+	for (i = 0; i < cnt; i++)
+		cache_put(items[i], cd);
+out_alloc:
+	kfree(seqnos);
+	kfree(items);
+	return ret;
+}
+
+/**
+ * sunrpc_nl_parse_one_ip_map - parse one ip_map entry from netlink
+ * @cd: cache_detail for the ip_map cache
+ * @attr: nested attribute containing ip_map fields
+ *
+ * Parses one ip_map entry from a netlink message and updates the
+ * cache. Mirrors the logic in ip_map_parse().
+ *
+ * Returns 0 on success or a negative errno.
+ */
+static int sunrpc_nl_parse_one_ip_map(struct cache_detail *cd,
+				      struct nlattr *attr)
+{
+	struct nlattr *tb[SUNRPC_A_IP_MAP_EXPIRY + 1];
+	union {
+		struct sockaddr		sa;
+		struct sockaddr_in	s4;
+		struct sockaddr_in6	s6;
+	} address;
+	struct sockaddr_in6 sin6;
+	struct ip_map *ipmp;
+	struct auth_domain *dom = NULL;
+	struct unix_domain *udom = NULL;
+	struct timespec64 boot;
+	time64_t expiry;
+	char class[8];
+	int err;
+	int len;
+
+	err = nla_parse_nested(tb, SUNRPC_A_IP_MAP_EXPIRY, attr,
+			       sunrpc_ip_map_nl_policy, NULL);
+	if (err)
+		return err;
+
+	/* class (required) */
+	if (!tb[SUNRPC_A_IP_MAP_CLASS])
+		return -EINVAL;
+	len = nla_len(tb[SUNRPC_A_IP_MAP_CLASS]);
+	if (len <= 0 || len > sizeof(class))
+		return -EINVAL;
+	nla_strscpy(class, tb[SUNRPC_A_IP_MAP_CLASS], sizeof(class));
+
+	/* addr (required) */
+	if (!tb[SUNRPC_A_IP_MAP_ADDR])
+		return -EINVAL;
+	if (rpc_pton(cd->net, nla_data(tb[SUNRPC_A_IP_MAP_ADDR]),
+		     nla_len(tb[SUNRPC_A_IP_MAP_ADDR]) - 1,
+		     &address.sa, sizeof(address)) == 0)
+		return -EINVAL;
+
+	switch (address.sa.sa_family) {
+	case AF_INET:
+		sin6.sin6_family = AF_INET6;
+		ipv6_addr_set_v4mapped(address.s4.sin_addr.s_addr,
+				       &sin6.sin6_addr);
+		break;
+#if IS_ENABLED(CONFIG_IPV6)
+	case AF_INET6:
+		memcpy(&sin6, &address.s6, sizeof(sin6));
+		break;
+#endif
+	default:
+		return -EINVAL;
+	}
+
+	/* expiry (required, wallclock seconds) */
+	if (!tb[SUNRPC_A_IP_MAP_EXPIRY])
+		return -EINVAL;
+	getboottime64(&boot);
+	expiry = nla_get_u64(tb[SUNRPC_A_IP_MAP_EXPIRY]) - boot.tv_sec;
+
+	/* domain name or negative */
+	if (tb[SUNRPC_A_IP_MAP_NEGATIVE]) {
+		udom = NULL;
+	} else if (tb[SUNRPC_A_IP_MAP_DOMAIN]) {
+		dom = unix_domain_find(nla_data(tb[SUNRPC_A_IP_MAP_DOMAIN]));
+		if (!dom)
+			return -ENOENT;
+		udom = container_of(dom, struct unix_domain, h);
+	} else {
+		return -EINVAL;
+	}
+
+	ipmp = __ip_map_lookup(cd, class, &sin6.sin6_addr);
+	if (ipmp)
+		err = __ip_map_update(cd, ipmp, udom, expiry);
+	else
+		err = -ENOMEM;
+
+	if (dom)
+		auth_domain_put(dom);
+
+	cache_flush();
+	return err;
+}
+
+/**
+ * sunrpc_nl_ip_map_set_reqs_doit - respond to ip_map requests
+ * @skb: reply buffer
+ * @info: netlink metadata and command arguments
+ *
+ * Parse one or more ip_map cache responses from userspace and
+ * update the ip_map cache accordingly.
+ *
+ * Returns 0 on success or a negative errno.
+ */
+int sunrpc_nl_ip_map_set_reqs_doit(struct sk_buff *skb,
+				   struct genl_info *info)
+{
+	struct sunrpc_net *sn;
+	struct cache_detail *cd;
+	const struct nlattr *attr;
+	int rem, ret = 0;
+
+	sn = net_generic(genl_info_net(info), sunrpc_net_id);
+
+	cd = sn->ip_map_cache;
+	if (!cd)
+		return -ENODEV;
+
+	nlmsg_for_each_attr_type(attr, SUNRPC_A_IP_MAP_REQS_REQUESTS,
+				 info->nlhdr, GENL_HDRLEN, rem) {
+		ret = sunrpc_nl_parse_one_ip_map(cd,
+						 (struct nlattr *)attr);
+		if (ret)
+			break;
+	}
+
+	return ret;
+}
+
 static const struct cache_detail ip_map_cache_template = {
 	.owner		= THIS_MODULE,
 	.hash_size	= IP_HASHMAX,
 	.name		= "auth.unix.ip",
 	.cache_put	= ip_map_put,
 	.cache_upcall	= ip_map_upcall,
+	.cache_notify	= ip_map_notify,
 	.cache_request	= ip_map_request,
 	.cache_parse	= ip_map_parse,
 	.cache_show	= ip_map_show,
diff --git a/rust/kernel/drm/gem/shmem.rs b/rust/kernel/drm/gem/shmem.rs
index d025fb035195..e1b648920d2f 100644
--- a/rust/kernel/drm/gem/shmem.rs
+++ b/rust/kernel/drm/gem/shmem.rs
@@ -19,10 +19,8 @@
     },
     error::to_result,
     prelude::*,
-    types::{
-        ARef,
-        Opaque, //
-    }, //
+    sync::aref::ARef,
+    types::Opaque, //
 };
 use core::{
     ops::{
diff --git a/scripts/.gitignore b/scripts/.gitignore
index 4215c2208f7e..e175714c18b6 100644
--- a/scripts/.gitignore
+++ b/scripts/.gitignore
@@ -1,5 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0-only
 /asn1_compiler
+/gen_lineinfo
 /gen_packed_field_checks
 /generate_rust_target
 /insert-sys-cert
diff --git a/scripts/Makefile b/scripts/Makefile
index 3434a82a119f..55244ce95578 100644
--- a/scripts/Makefile
+++ b/scripts/Makefile
@@ -4,6 +4,7 @@
 # the kernel for the build process.
 
 hostprogs-always-$(CONFIG_KALLSYMS)			+= kallsyms
+hostprogs-always-$(CONFIG_KALLSYMS_LINEINFO)		+= gen_lineinfo
 hostprogs-always-$(BUILD_C_RECORDMCOUNT)		+= recordmcount
 hostprogs-always-$(CONFIG_BUILDTIME_TABLE_SORT)		+= sorttable
 hostprogs-always-$(CONFIG_ASN1)				+= asn1_compiler
@@ -37,6 +38,8 @@ HOSTCFLAGS_asn1_compiler.o = -I$(srctree)/include
 HOSTCFLAGS_sign-file.o = $(shell $(HOSTPKG_CONFIG) --cflags libcrypto 2> /dev/null)
 HOSTCFLAGS_sign-file.o += -I$(srctree)/tools/include/uapi/
 HOSTLDLIBS_sign-file = $(shell $(HOSTPKG_CONFIG) --libs libcrypto 2> /dev/null || echo -lcrypto)
+HOSTCFLAGS_gen_lineinfo.o = $(shell $(HOSTPKG_CONFIG) --cflags libdw 2> /dev/null)
+HOSTLDLIBS_gen_lineinfo = $(shell $(HOSTPKG_CONFIG) --libs libdw 2> /dev/null || echo -ldw -lelf -lz)
 
 ifdef CONFIG_UNWINDER_ORC
 ifeq ($(ARCH),x86_64)
diff --git a/scripts/Makefile.modfinal b/scripts/Makefile.modfinal
index adcbcde16a07..3941cf624526 100644
--- a/scripts/Makefile.modfinal
+++ b/scripts/Makefile.modfinal
@@ -46,6 +46,9 @@ quiet_cmd_btf_ko = BTF [M] $@
 		$(CONFIG_SHELL) $(srctree)/scripts/gen-btf.sh --btf_base $(objtree)/vmlinux $@; \
 	fi;
 
+quiet_cmd_lineinfo_ko = LINEINFO [M] $@
+      cmd_lineinfo_ko = $(CONFIG_SHELL) $(srctree)/scripts/gen-mod-lineinfo.sh $@
+
 # Same as newer-prereqs, but allows to exclude specified extra dependencies
 newer_prereqs_except = $(filter-out $(PHONY) $(1),$?)
 
@@ -59,6 +62,9 @@ if_changed_except = $(if $(call newer_prereqs_except,$(2))$(cmd-check),      \
 	+$(call if_changed_except,ld_ko_o,$(objtree)/vmlinux)
 ifdef CONFIG_DEBUG_INFO_BTF_MODULES
 	+$(if $(newer-prereqs),$(call cmd,btf_ko))
+endif
+ifdef CONFIG_KALLSYMS_LINEINFO_MODULES
+	+$(if $(newer-prereqs),$(call cmd,lineinfo_ko))
 endif
 	+$(call cmd,check_tracepoint)
 
diff --git a/scripts/atomic/gen-atomic-long.sh b/scripts/atomic/gen-atomic-long.sh
index 9826be3ba986..874643dc74bd 100755
--- a/scripts/atomic/gen-atomic-long.sh
+++ b/scripts/atomic/gen-atomic-long.sh
@@ -79,14 +79,18 @@ cat << EOF
 
 #ifdef CONFIG_64BIT
 typedef atomic64_t atomic_long_t;
-#define ATOMIC_LONG_INIT(i)		ATOMIC64_INIT(i)
-#define atomic_long_cond_read_acquire	atomic64_cond_read_acquire
-#define atomic_long_cond_read_relaxed	atomic64_cond_read_relaxed
+#define ATOMIC_LONG_INIT(i)			ATOMIC64_INIT(i)
+#define atomic_long_cond_read_acquire		atomic64_cond_read_acquire
+#define atomic_long_cond_read_relaxed		atomic64_cond_read_relaxed
+#define atomic_long_cond_read_acquire_timeout	atomic64_cond_read_acquire_timeout
+#define atomic_long_cond_read_relaxed_timeout	atomic64_cond_read_relaxed_timeout
 #else
 typedef atomic_t atomic_long_t;
-#define ATOMIC_LONG_INIT(i)		ATOMIC_INIT(i)
-#define atomic_long_cond_read_acquire	atomic_cond_read_acquire
-#define atomic_long_cond_read_relaxed	atomic_cond_read_relaxed
+#define ATOMIC_LONG_INIT(i)			ATOMIC_INIT(i)
+#define atomic_long_cond_read_acquire		atomic_cond_read_acquire
+#define atomic_long_cond_read_relaxed		atomic_cond_read_relaxed
+#define atomic_long_cond_read_acquire_timeout	atomic_cond_read_acquire_timeout
+#define atomic_long_cond_read_relaxed_timeout	atomic_cond_read_relaxed_timeout
 #endif
 
 EOF
diff --git a/scripts/checkpatch.pl b/scripts/checkpatch.pl
index 0492d6afc9a1..3727156e4cca 100755
--- a/scripts/checkpatch.pl
+++ b/scripts/checkpatch.pl
@@ -57,8 +57,12 @@ my %ignore_type = ();
 my @ignore = ();
 my $help = 0;
 my $configuration_file = ".checkpatch.conf";
+my $def_configuration_dirs_help = '.:$HOME:.scripts';
+(my $def_configuration_dirs = $def_configuration_dirs_help) =~ s/\$(\w+)/$ENV{$1}/g;
+my $env_config_dir = 'CHECKPATCH_CONFIG_DIR';
 my $max_line_length = 100;
 my $ignore_perl_version = 0;
+my $spdx_cxx_comments = 0;
 my $minimum_perl_version = 5.10.0;
 my $min_conf_desc_length = 4;
 my $spelling_file = "$D/spelling.txt";
@@ -135,6 +139,10 @@ Options:
                              file.  It's your fault if there's no backup or git
   --ignore-perl-version      override checking of perl version.  expect
                              runtime errors.
+  --spdx-cxx-comments        don't force C comments (/* */) for SPDX license
+                             (required by old toolchains), allow also C++
+                             comments (//).
+                             NOTE: it should *not* be used for Linux mainline.
   --codespell                Use the codespell dictionary for spelling/typos
                              (default:$codespellfile)
   --codespellfile            Use this codespell dictionary
@@ -146,6 +154,11 @@ Options:
   -h, --help, --version      display this help and exit
 
 When FILE is - read standard input.
+
+CONFIGURATION FILE
+Default configuration options can be stored in $configuration_file,
+search path: '$def_configuration_dirs_help' or in a directory specified by
+\$$env_config_dir environment variable (fallback to the default search path).
 EOM
 
 	exit($exitcode);
@@ -237,7 +250,7 @@ sub list_types {
 	exit($exitcode);
 }
 
-my $conf = which_conf($configuration_file);
+my $conf = which_conf($configuration_file, $env_config_dir, $def_configuration_dirs);
 if (-f $conf) {
 	my @conf_args;
 	open(my $conffile, '<', "$conf")
@@ -339,6 +352,7 @@ GetOptions(
 	'fix!'		=> \$fix,
 	'fix-inplace!'	=> \$fix_inplace,
 	'ignore-perl-version!' => \$ignore_perl_version,
+	'spdx-cxx-comments!' => \$spdx_cxx_comments,
 	'debug=s'	=> \%debug,
 	'test-only=s'	=> \$tst_only,
 	'codespell!'	=> \$codespell,
@@ -1531,9 +1545,15 @@ sub which {
 }
 
 sub which_conf {
-	my ($conf) = @_;
+	my ($conf, $env_key, $paths) = @_;
+	my $env_dir = $ENV{$env_key};
+
+	if (defined($env_dir) && $env_dir ne "") {
+		return "$env_dir/$conf" if (-e "$env_dir/$conf");
+		warn "$P: Can't find a readable $conf in '$env_dir', falling back to default search paths\n";
+	}
 
-	foreach my $path (split(/:/, ".:$ENV{HOME}:.scripts")) {
+	foreach my $path (split(/:/, $paths)) {
 		if (-e "$path/$conf") {
 			return "$path/$conf";
 		}
@@ -3801,26 +3821,33 @@ sub process {
 				$checklicenseline = 2;
 			} elsif ($rawline =~ /^\+/) {
 				my $comment = "";
-				if ($realfile =~ /\.(h|s|S)$/) {
-					$comment = '/*';
-				} elsif ($realfile =~ /\.(c|rs|dts|dtsi)$/) {
+				if ($realfile =~ /\.(c|rs|dts|dtsi)$/) {
 					$comment = '//';
 				} elsif (($checklicenseline == 2) || $realfile =~ /\.(sh|pl|py|awk|tc|yaml)$/) {
 					$comment = '#';
 				} elsif ($realfile =~ /\.rst$/) {
 					$comment = '..';
 				}
+				my $pattern = qr{\Q$comment\E};
+				if ($realfile =~ /\.(h|s|S)$/) {
+					$comment = '/*';
+					$pattern = qr{/\*};
+					if ($spdx_cxx_comments) {
+						$comment = '// or /*';
+						$pattern = qr{//|/\*};
+					}
+				}
 
 # check SPDX comment style for .[chsS] files
 				if ($realfile =~ /\.[chsS]$/ &&
 				    $rawline =~ /SPDX-License-Identifier:/ &&
-				    $rawline !~ m@^\+\s*\Q$comment\E\s*@) {
+				    $rawline !~ m@^\+\s*$pattern\s*@) {
 					WARN("SPDX_LICENSE_TAG",
 					     "Improper SPDX comment style for '$realfile', please use '$comment' instead\n" . $herecurr);
 				}
 
 				if ($comment !~ /^$/ &&
-				    $rawline !~ m@^\+\Q$comment\E SPDX-License-Identifier: @) {
+				    $rawline !~ m@^\+$pattern SPDX-License-Identifier: @) {
 					WARN("SPDX_LICENSE_TAG",
 					     "Missing or malformed SPDX-License-Identifier tag in line $checklicenseline\n" . $herecurr);
 				} elsif ($rawline =~ /(SPDX-License-Identifier: .*)/) {
@@ -4156,7 +4183,7 @@ sub process {
 			$pl =~ s/\b(?:$Attribute|$Sparse)\b//g;
 			if (($pl =~ /^\+\s+$Declare\s*$Ident\s*[=,;:\[]/ ||
 			# function pointer declarations
-			     $pl =~ /^\+\s+$Declare\s*\(\s*\*\s*$Ident\s*\)\s*[=,;:\[\(]/ ||
+			     $pl =~ /^\+\s+$Declare\s*\(\s*\*\s*$Ident(?:\s*\[\s*(?:$Ident|$Constant)?\s*\])?\s*\)\s*[=,;:\[\(]/ ||
 			# foo bar; where foo is some local typedef or #define
 			     $pl =~ /^\+\s+$Ident(?:\s+|\s*\*\s*)$Ident\s*[=,;\[]/ ||
 			# known declaration macros
@@ -4170,7 +4197,7 @@ sub process {
 			# looks like a declaration
 			    !($sl =~ /^\+\s+$Declare\s*$Ident\s*[=,;:\[]/ ||
 			# function pointer declarations
-			      $sl =~ /^\+\s+$Declare\s*\(\s*\*\s*$Ident\s*\)\s*[=,;:\[\(]/ ||
+			      $sl =~ /^\+\s+$Declare\s*\(\s*\*\s*$Ident(?:\s*\[\s*(?:$Ident|$Constant)?\s*\])?\s*\)\s*[=,;:\[\(]/ ||
 			# foo bar; where foo is some local typedef or #define
 			      $sl =~ /^\+\s+$Ident(?:\s+|\s*\*\s*)$Ident\s*[=,;\[]/ ||
 			# known declaration macros
diff --git a/scripts/empty_lineinfo.S b/scripts/empty_lineinfo.S
new file mode 100644
index 000000000000..edd5b1092f05
--- /dev/null
+++ b/scripts/empty_lineinfo.S
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2026 Sasha Levin <sashal@kernel.org>
+ *
+ * Empty lineinfo stub for the initial vmlinux link.
+ * The real lineinfo is generated from .tmp_vmlinux1 by gen_lineinfo.
+ */
+	.section .rodata, "a"
+	.globl lineinfo_num_entries
+	.balign 4
+lineinfo_num_entries:
+	.long 0
+	.globl lineinfo_num_files
+	.balign 4
+lineinfo_num_files:
+	.long 0
+	.globl lineinfo_num_blocks
+	.balign 4
+lineinfo_num_blocks:
+	.long 0
+	.globl lineinfo_block_addrs
+lineinfo_block_addrs:
+	.globl lineinfo_block_offsets
+lineinfo_block_offsets:
+	.globl lineinfo_data_size
+	.balign 4
+lineinfo_data_size:
+	.long 0
+	.globl lineinfo_data
+lineinfo_data:
+	.globl lineinfo_file_offsets
+lineinfo_file_offsets:
+	.globl lineinfo_filenames_size
+	.balign 4
+lineinfo_filenames_size:
+	.long 0
+	.globl lineinfo_filenames
+lineinfo_filenames:
diff --git a/scripts/gen-mod-lineinfo.sh b/scripts/gen-mod-lineinfo.sh
new file mode 100755
index 000000000000..d0663b862d31
--- /dev/null
+++ b/scripts/gen-mod-lineinfo.sh
@@ -0,0 +1,48 @@
+#!/bin/sh
+# SPDX-License-Identifier: GPL-2.0
+#
+# gen-mod-lineinfo.sh - Embed source line info into a kernel module (.ko)
+#
+# Reads DWARF from the .ko, generates a .mod_lineinfo section, and
+# embeds it back into the .ko.  Modeled on scripts/gen-btf.sh.
+
+set -e
+
+if [ $# -ne 1 ]; then
+	echo "Usage: $0 <module.ko>" >&2
+	exit 1
+fi
+
+KO="$1"
+
+cleanup() {
+	rm -f "${KO}.lineinfo.S" "${KO}.lineinfo.o" "${KO}.lineinfo.bin"
+}
+trap cleanup EXIT
+
+case "${KBUILD_VERBOSE}" in
+*1*)
+	set -x
+	;;
+esac
+
+# Generate assembly from DWARF -- if it fails (no DWARF), silently skip
+if ! ${objtree}/scripts/gen_lineinfo --module "${KO}" > "${KO}.lineinfo.S"; then
+	exit 0
+fi
+
+# Compile assembly to object file
+${CC} ${NOSTDINC_FLAGS} ${LINUXINCLUDE} ${KBUILD_CPPFLAGS} \
+	${KBUILD_AFLAGS} ${KBUILD_AFLAGS_MODULE} \
+	-c -o "${KO}.lineinfo.o" "${KO}.lineinfo.S"
+
+# Extract raw section content
+${OBJCOPY} -O binary --only-section=.mod_lineinfo \
+	"${KO}.lineinfo.o" "${KO}.lineinfo.bin"
+
+# Embed into the .ko with alloc,readonly flags
+${OBJCOPY} --add-section ".mod_lineinfo=${KO}.lineinfo.bin" \
+	--set-section-flags .mod_lineinfo=alloc,readonly \
+	"${KO}"
+
+exit 0
diff --git a/scripts/gen_lineinfo.c b/scripts/gen_lineinfo.c
new file mode 100644
index 000000000000..45b1c1081164
--- /dev/null
+++ b/scripts/gen_lineinfo.c
@@ -0,0 +1,848 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * gen_lineinfo.c - Generate address-to-source-line lookup tables from DWARF
+ *
+ * Copyright (C) 2026 Sasha Levin <sashal@kernel.org>
+ *
+ * Reads DWARF .debug_line from a vmlinux ELF file and outputs an assembly
+ * file containing sorted lookup tables that the kernel uses to annotate
+ * stack traces with source file:line information.
+ *
+ * Requires libdw from elfutils.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <errno.h>
+#include <fcntl.h>
+#include <unistd.h>
+#include <elfutils/libdw.h>
+#include <dwarf.h>
+#include <elf.h>
+#include <gelf.h>
+#include <limits.h>
+
+#include "../include/linux/mod_lineinfo.h"
+
+static int module_mode;
+
+static unsigned int skipped_overflow;
+
+/* .text range for module mode (keep only runtime code) */
+static unsigned long long text_section_start;
+static unsigned long long text_section_end;
+
+struct line_entry {
+	unsigned int offset;	/* offset from _text */
+	unsigned int file_id;
+	unsigned int line;
+};
+
+struct file_entry {
+	char *name;
+	unsigned int id;
+	unsigned int str_offset;
+};
+
+static struct line_entry *entries;
+static unsigned int num_entries;
+static unsigned int entries_capacity;
+
+static struct file_entry *files;
+static unsigned int num_files;
+static unsigned int files_capacity;
+
+#define FILE_HASH_BITS 13
+#define FILE_HASH_SIZE (1 << FILE_HASH_BITS)
+
+struct file_hash_entry {
+	const char *name;
+	unsigned int id;
+};
+
+static struct file_hash_entry file_hash[FILE_HASH_SIZE];
+
+static unsigned int hash_str(const char *s)
+{
+	unsigned int h = 5381;
+
+	for (; *s; s++)
+		h = h * 33 + (unsigned char)*s;
+	return h & (FILE_HASH_SIZE - 1);
+}
+
+static void add_entry(unsigned int offset, unsigned int file_id,
+		      unsigned int line)
+{
+	if (num_entries >= entries_capacity) {
+		entries_capacity = entries_capacity ? entries_capacity * 2 : 65536;
+		entries = realloc(entries, entries_capacity * sizeof(*entries));
+		if (!entries) {
+			fprintf(stderr, "out of memory\n");
+			exit(1);
+		}
+	}
+	entries[num_entries].offset = offset;
+	entries[num_entries].file_id = file_id;
+	entries[num_entries].line = line;
+	num_entries++;
+}
+
+static unsigned int find_or_add_file(const char *name)
+{
+	unsigned int h = hash_str(name);
+
+	/* Open-addressing lookup with linear probing */
+	while (file_hash[h].name) {
+		if (!strcmp(file_hash[h].name, name))
+			return file_hash[h].id;
+		h = (h + 1) & (FILE_HASH_SIZE - 1);
+	}
+
+	if (num_files >= 65535) {
+		fprintf(stderr,
+			"gen_lineinfo: too many source files (%u > 65535)\n",
+			num_files);
+		exit(1);
+	}
+
+	if (num_files >= files_capacity) {
+		files_capacity = files_capacity ? files_capacity * 2 : 4096;
+		files = realloc(files, files_capacity * sizeof(*files));
+		if (!files) {
+			fprintf(stderr, "out of memory\n");
+			exit(1);
+		}
+	}
+	files[num_files].name = strdup(name);
+	files[num_files].id = num_files;
+
+	/* Insert into hash table (points to files[] entry) */
+	file_hash[h].name = files[num_files].name;
+	file_hash[h].id = num_files;
+
+	num_files++;
+	return num_files - 1;
+}
+
+/*
+ * Well-known top-level directories in the kernel source tree.
+ * Used as a fallback to recover relative paths from absolute DWARF paths
+ * when comp_dir doesn't match (e.g. O= out-of-tree builds where comp_dir
+ * is the build directory but source paths point into the source tree).
+ */
+static const char * const kernel_dirs[] = {
+	"arch/", "block/", "certs/", "crypto/", "drivers/", "fs/",
+	"include/", "init/", "io_uring/", "ipc/", "kernel/", "lib/",
+	"mm/", "net/", "rust/", "samples/", "scripts/", "security/",
+	"sound/", "tools/", "usr/", "virt/",
+};
+
+/*
+ * Strip a filename to a kernel-relative path.
+ *
+ * For absolute paths, strip the comp_dir prefix (from DWARF) to get
+ * a kernel-tree-relative path.  When that fails (e.g. O= builds where
+ * comp_dir is the build directory), scan for a well-known kernel
+ * top-level directory name in the path to recover the relative path.
+ * Fall back to the basename as a last resort.
+ *
+ * For relative paths (common in modules), libdw may produce a bogus
+ * doubled path like "net/foo/bar.c/net/foo/bar.c" due to ET_REL DWARF
+ * quirks.  Detect and strip such duplicates.
+ */
+static const char *make_relative(const char *path, const char *comp_dir)
+{
+	const char *p;
+
+	if (path[0] == '/') {
+		/* Try comp_dir prefix from DWARF */
+		if (comp_dir) {
+			size_t len = strlen(comp_dir);
+
+			if (!strncmp(path, comp_dir, len) && path[len] == '/') {
+				const char *rel = path + len + 1;
+
+				/*
+				 * If comp_dir pointed to a subdirectory
+				 * (e.g. arch/parisc/kernel) rather than
+				 * the tree root, stripping it leaves a
+				 * bare filename.  Fall through to the
+				 * kernel_dirs scan so we recover the full
+				 * relative path instead.
+				 */
+				if (strchr(rel, '/'))
+					return rel;
+			}
+		}
+
+		/*
+		 * comp_dir prefix didn't help — either it didn't match
+		 * or it was too specific and left a bare filename.
+		 * Scan for a known kernel top-level directory component
+		 * to find where the relative path starts.  This handles
+		 * O= builds and arches where comp_dir is a subdirectory.
+		 */
+		for (p = path + 1; *p; p++) {
+			if (*(p - 1) == '/') {
+				for (unsigned int i = 0; i < sizeof(kernel_dirs) /
+				     sizeof(kernel_dirs[0]); i++) {
+					if (!strncmp(p, kernel_dirs[i],
+						     strlen(kernel_dirs[i])))
+						return p;
+				}
+			}
+		}
+
+		/* Fall back to basename */
+		p = strrchr(path, '/');
+		return p ? p + 1 : path;
+	}
+
+	/*
+	 * Relative path — check for duplicated-path quirk from libdw
+	 * on ET_REL files (e.g., "a/b.c/a/b.c" → "a/b.c").
+	 */
+	{
+		size_t len = strlen(path);
+		size_t mid = len / 2;
+
+		if (len > 1 && path[mid] == '/' &&
+		    !memcmp(path, path + mid + 1, mid))
+			return path + mid + 1;
+	}
+
+	/*
+	 * Bare filename with no directory component — try to recover the
+	 * relative path using comp_dir.  Some toolchains/elfutils combos
+	 * produce bare filenames where comp_dir holds the source directory.
+	 * Construct the absolute path and run the kernel_dirs scan.
+	 */
+	if (!strchr(path, '/') && comp_dir && comp_dir[0] == '/') {
+		static char buf[PATH_MAX];
+
+		snprintf(buf, sizeof(buf), "%s/%s", comp_dir, path);
+		for (p = buf + 1; *p; p++) {
+			if (*(p - 1) == '/') {
+				for (unsigned int i = 0; i < sizeof(kernel_dirs) /
+				     sizeof(kernel_dirs[0]); i++) {
+					if (!strncmp(p, kernel_dirs[i],
+						     strlen(kernel_dirs[i])))
+						return p;
+				}
+			}
+		}
+	}
+
+	return path;
+}
+
+static int compare_entries(const void *a, const void *b)
+{
+	const struct line_entry *ea = a;
+	const struct line_entry *eb = b;
+
+	if (ea->offset != eb->offset)
+		return ea->offset < eb->offset ? -1 : 1;
+	if (ea->file_id != eb->file_id)
+		return ea->file_id < eb->file_id ? -1 : 1;
+	if (ea->line != eb->line)
+		return ea->line < eb->line ? -1 : 1;
+	return 0;
+}
+
+static unsigned long long find_text_addr(Elf *elf)
+{
+	size_t nsyms, i;
+	Elf_Scn *scn = NULL;
+	GElf_Shdr shdr;
+
+	while ((scn = elf_nextscn(elf, scn)) != NULL) {
+		Elf_Data *data;
+
+		if (!gelf_getshdr(scn, &shdr))
+			continue;
+		if (shdr.sh_type != SHT_SYMTAB)
+			continue;
+
+		data = elf_getdata(scn, NULL);
+		if (!data)
+			continue;
+
+		nsyms = shdr.sh_size / shdr.sh_entsize;
+		for (i = 0; i < nsyms; i++) {
+			GElf_Sym sym;
+			const char *name;
+
+			if (!gelf_getsym(data, i, &sym))
+				continue;
+			name = elf_strptr(elf, shdr.sh_link, sym.st_name);
+			if (name && !strcmp(name, "_text"))
+				return sym.st_value;
+		}
+	}
+
+	fprintf(stderr, "Cannot find _text symbol\n");
+	exit(1);
+}
+
+static void find_text_section_range(Elf *elf)
+{
+	Elf_Scn *scn = NULL;
+	GElf_Shdr shdr;
+	size_t shstrndx;
+
+	if (elf_getshdrstrndx(elf, &shstrndx) != 0)
+		return;
+
+	while ((scn = elf_nextscn(elf, scn)) != NULL) {
+		const char *name;
+
+		if (!gelf_getshdr(scn, &shdr))
+			continue;
+		name = elf_strptr(elf, shstrndx, shdr.sh_name);
+		if (name && !strcmp(name, ".text")) {
+			text_section_start = shdr.sh_addr;
+			text_section_end = shdr.sh_addr + shdr.sh_size;
+			return;
+		}
+	}
+}
+
+/*
+ * Apply .rela.debug_line relocations to a mutable copy of .debug_line data.
+ *
+ * elfutils libdw (through at least 0.194) does NOT apply relocations for
+ * ET_REL files when using dwarf_begin_elf().  The internal libdwfl layer
+ * does this via __libdwfl_relocate(), but that API is not public.
+ *
+ * For DWARF5, the .debug_line file name table uses DW_FORM_line_strp
+ * references into .debug_line_str.  Without relocation, all these offsets
+ * resolve to 0 (or garbage), causing dwarf_linesrc()/dwarf_filesrc() to
+ * return wrong filenames (typically the comp_dir for every file).
+ *
+ * This function applies the relocations manually so that the patched
+ * .debug_line data can be fed to dwarf_begin_elf() and produce correct
+ * results.
+ *
+ * See elfutils bug https://sourceware.org/bugzilla/show_bug.cgi?id=31447
+ * A fix (dwelf_elf_apply_relocs) was proposed but not yet merged as of
+ * elfutils 0.194: https://sourceware.org/pipermail/elfutils-devel/2024q3/007388.html
+ */
+/*
+ * Determine the relocation type for a 32-bit absolute reference
+ * on the given architecture.  Returns 0 if unknown.
+ */
+static unsigned int r_type_abs32(unsigned int e_machine)
+{
+	switch (e_machine) {
+	case EM_X86_64:		return R_X86_64_32;
+	case EM_386:		return R_386_32;
+	case EM_AARCH64:	return R_AARCH64_ABS32;
+	case EM_ARM:		return R_ARM_ABS32;
+	case EM_RISCV:		return R_RISCV_32;
+	case EM_S390:		return R_390_32;
+	case EM_MIPS:		return R_MIPS_32;
+	case EM_PPC64:		return R_PPC64_ADDR32;
+	case EM_PPC:		return R_PPC_ADDR32;
+	case EM_LOONGARCH:	return R_LARCH_32;
+	case EM_PARISC:		return R_PARISC_DIR32;
+	default:		return 0;
+	}
+}
+
+static void apply_debug_line_relocations(Elf *elf)
+{
+	Elf_Scn *scn = NULL;
+	Elf_Scn *debug_line_scn = NULL;
+	Elf_Scn *rela_debug_line_scn = NULL;
+	Elf_Scn *symtab_scn = NULL;
+	GElf_Shdr shdr;
+	GElf_Ehdr ehdr;
+	unsigned int abs32_type;
+	size_t shstrndx;
+	Elf_Data *dl_data, *rela_data, *sym_data;
+	GElf_Shdr rela_shdr, sym_shdr;
+	size_t nrels, i;
+
+	if (gelf_getehdr(elf, &ehdr) == NULL)
+		return;
+
+	abs32_type = r_type_abs32(ehdr.e_machine);
+	if (!abs32_type)
+		return;
+
+	if (elf_getshdrstrndx(elf, &shstrndx) != 0)
+		return;
+
+	/* Find the relevant sections */
+	while ((scn = elf_nextscn(elf, scn)) != NULL) {
+		const char *name;
+
+		if (!gelf_getshdr(scn, &shdr))
+			continue;
+		name = elf_strptr(elf, shstrndx, shdr.sh_name);
+		if (!name)
+			continue;
+
+		if (!strcmp(name, ".debug_line"))
+			debug_line_scn = scn;
+		else if (!strcmp(name, ".rela.debug_line"))
+			rela_debug_line_scn = scn;
+		else if (shdr.sh_type == SHT_SYMTAB)
+			symtab_scn = scn;
+	}
+
+	if (!debug_line_scn || !rela_debug_line_scn || !symtab_scn)
+		return;
+
+	dl_data = elf_getdata(debug_line_scn, NULL);
+	rela_data = elf_getdata(rela_debug_line_scn, NULL);
+	sym_data = elf_getdata(symtab_scn, NULL);
+	if (!dl_data || !rela_data || !sym_data)
+		return;
+
+	if (!gelf_getshdr(rela_debug_line_scn, &rela_shdr))
+		return;
+	if (!gelf_getshdr(symtab_scn, &sym_shdr))
+		return;
+
+	nrels = rela_shdr.sh_size / rela_shdr.sh_entsize;
+
+	for (i = 0; i < nrels; i++) {
+		GElf_Rela rela;
+		GElf_Sym sym;
+		unsigned int r_type;
+		size_t r_sym;
+		uint32_t value;
+
+		if (!gelf_getrela(rela_data, i, &rela))
+			continue;
+
+		r_type = GELF_R_TYPE(rela.r_info);
+		r_sym = GELF_R_SYM(rela.r_info);
+
+		/* Only handle the 32-bit absolute reloc for this arch */
+		if (r_type != abs32_type)
+			continue;
+
+		if (!gelf_getsym(sym_data, r_sym, &sym))
+			continue;
+
+		/* Relocated value = sym.st_value + addend */
+		value = (uint32_t)(sym.st_value + rela.r_addend);
+
+		/* Patch the .debug_line data at the relocation offset */
+		if (rela.r_offset + 4 <= dl_data->d_size)
+			memcpy((char *)dl_data->d_buf + rela.r_offset,
+			       &value, sizeof(value));
+	}
+}
+
+static void process_dwarf(Dwarf *dwarf, unsigned long long text_addr)
+{
+	Dwarf_Off off = 0, next_off;
+	size_t hdr_size;
+
+	while (dwarf_nextcu(dwarf, off, &next_off, &hdr_size,
+			    NULL, NULL, NULL) == 0) {
+		Dwarf_Die cudie;
+		Dwarf_Lines *lines;
+		size_t nlines;
+		Dwarf_Attribute attr;
+		const char *comp_dir = NULL;
+
+		if (!dwarf_offdie(dwarf, off + hdr_size, &cudie))
+			goto next;
+
+		if (dwarf_attr(&cudie, DW_AT_comp_dir, &attr))
+			comp_dir = dwarf_formstring(&attr);
+
+		if (dwarf_getsrclines(&cudie, &lines, &nlines) != 0)
+			goto next;
+
+		for (size_t i = 0; i < nlines; i++) {
+			Dwarf_Line *line = dwarf_onesrcline(lines, i);
+			Dwarf_Addr addr;
+			const char *src;
+			const char *rel;
+			unsigned int file_id, loffset;
+			int lineno;
+
+			if (!line)
+				continue;
+
+			if (dwarf_lineaddr(line, &addr) != 0)
+				continue;
+			if (dwarf_lineno(line, &lineno) != 0)
+				continue;
+			if (lineno == 0)
+				continue;
+
+			src = dwarf_linesrc(line, NULL, NULL);
+			if (!src)
+				continue;
+
+			if (addr < text_addr)
+				continue;
+
+			/*
+			 * In module mode, keep only .text addresses.
+			 * In ET_REL .ko files, .text, .init.text and
+			 * .exit.text all have sh_addr == 0 and therefore
+			 * overlapping address ranges.  Explicitly check
+			 * against the .text bounds.
+			 */
+			if (module_mode && text_section_end > text_section_start &&
+			    (addr < text_section_start || addr >= text_section_end))
+				continue;
+
+			{
+				unsigned long long raw_offset = addr - text_addr;
+
+				if (raw_offset > UINT_MAX) {
+					skipped_overflow++;
+					continue;
+				}
+				loffset = (unsigned int)raw_offset;
+			}
+
+			rel = make_relative(src, comp_dir);
+			file_id = find_or_add_file(rel);
+
+			add_entry(loffset, file_id, (unsigned int)lineno);
+		}
+next:
+		off = next_off;
+	}
+}
+
+static void deduplicate(void)
+{
+	unsigned int i, j;
+
+	if (num_entries < 2)
+		return;
+
+	/* Sort by offset, then file_id, then line for stability */
+	qsort(entries, num_entries, sizeof(*entries), compare_entries);
+
+	/*
+	 * Remove duplicate entries:
+	 * - Same offset: keep first (deterministic from stable sort keys)
+	 * - Same file:line as previous kept entry: redundant for binary
+	 *   search -- any address between them resolves to the earlier one
+	 */
+	j = 0;
+	for (i = 1; i < num_entries; i++) {
+		if (entries[i].offset == entries[j].offset)
+			continue;
+		if (entries[i].file_id == entries[j].file_id &&
+		    entries[i].line == entries[j].line)
+			continue;
+		j++;
+		if (j != i)
+			entries[j] = entries[i];
+	}
+	num_entries = j + 1;
+}
+
+/*
+ * Emit the LEB128 delta-compressed data stream for one block.
+ * Uses .uleb128/.sleb128 assembler directives for encoding.
+ */
+static void emit_block_data(unsigned int block)
+{
+	unsigned int base = block * LINEINFO_BLOCK_ENTRIES;
+	unsigned int count = num_entries - base;
+
+	if (count > LINEINFO_BLOCK_ENTRIES)
+		count = LINEINFO_BLOCK_ENTRIES;
+
+	/* Entry 0: file_id, line (both unsigned) */
+	printf("\t.uleb128 %u\n", entries[base].file_id);
+	printf("\t.uleb128 %u\n", entries[base].line);
+
+	/* Entries 1..N: addr_delta (unsigned), file/line deltas (signed) */
+	for (unsigned int i = 1; i < count; i++) {
+		unsigned int idx = base + i;
+
+		printf("\t.uleb128 %u\n",
+		       entries[idx].offset - entries[idx - 1].offset);
+		printf("\t.sleb128 %d\n",
+		       (int)entries[idx].file_id - (int)entries[idx - 1].file_id);
+		printf("\t.sleb128 %d\n",
+		       (int)entries[idx].line - (int)entries[idx - 1].line);
+	}
+}
+
+static void compute_file_offsets(void)
+{
+	unsigned int offset = 0;
+
+	for (unsigned int i = 0; i < num_files; i++) {
+		files[i].str_offset = offset;
+		offset += strlen(files[i].name) + 1;
+	}
+}
+
+static void print_escaped_asciz(const char *s)
+{
+	printf("\t.asciz \"");
+	for (; *s; s++) {
+		if (*s == '"' || *s == '\\')
+			putchar('\\');
+		putchar(*s);
+	}
+	printf("\"\n");
+}
+
+static void output_assembly(void)
+{
+	unsigned int num_blocks;
+
+	num_blocks = num_entries ?
+		(num_entries + LINEINFO_BLOCK_ENTRIES - 1) / LINEINFO_BLOCK_ENTRIES : 0;
+
+	printf("/* SPDX-License-Identifier: GPL-2.0 */\n");
+	printf("/*\n");
+	printf(" * Automatically generated by scripts/gen_lineinfo\n");
+	printf(" * Do not edit.\n");
+	printf(" */\n\n");
+
+	printf("\t.section .rodata, \"a\"\n\n");
+
+	/* Number of entries */
+	printf("\t.globl lineinfo_num_entries\n");
+	printf("\t.balign 4\n");
+	printf("lineinfo_num_entries:\n");
+	printf("\t.long %u\n\n", num_entries);
+
+	/* Number of files */
+	printf("\t.globl lineinfo_num_files\n");
+	printf("\t.balign 4\n");
+	printf("lineinfo_num_files:\n");
+	printf("\t.long %u\n\n", num_files);
+
+	/* Number of blocks */
+	printf("\t.globl lineinfo_num_blocks\n");
+	printf("\t.balign 4\n");
+	printf("lineinfo_num_blocks:\n");
+	printf("\t.long %u\n\n", num_blocks);
+
+	/* Block first-addresses for binary search */
+	printf("\t.globl lineinfo_block_addrs\n");
+	printf("\t.balign 4\n");
+	printf("lineinfo_block_addrs:\n");
+	for (unsigned int i = 0; i < num_blocks; i++)
+		printf("\t.long 0x%x\n", entries[i * LINEINFO_BLOCK_ENTRIES].offset);
+
+	/* Block byte offsets into compressed stream */
+	printf("\t.globl lineinfo_block_offsets\n");
+	printf("\t.balign 4\n");
+	printf("lineinfo_block_offsets:\n");
+	for (unsigned int i = 0; i < num_blocks; i++)
+		printf("\t.long .Lblock_%u - lineinfo_data\n", i);
+
+	/* Compressed data size */
+	printf("\t.globl lineinfo_data_size\n");
+	printf("\t.balign 4\n");
+	printf("lineinfo_data_size:\n");
+	printf("\t.long .Ldata_end - lineinfo_data\n\n");
+
+	/* Compressed data stream */
+	printf("\t.globl lineinfo_data\n");
+	printf("lineinfo_data:\n");
+	for (unsigned int i = 0; i < num_blocks; i++) {
+		printf(".Lblock_%u:\n", i);
+		emit_block_data(i);
+	}
+	printf(".Ldata_end:\n\n");
+
+	/* File string offset table */
+	printf("\t.globl lineinfo_file_offsets\n");
+	printf("\t.balign 4\n");
+	printf("lineinfo_file_offsets:\n");
+	for (unsigned int i = 0; i < num_files; i++)
+		printf("\t.long %u\n", files[i].str_offset);
+
+	/* Filenames size */
+	printf("\t.globl lineinfo_filenames_size\n");
+	printf("\t.balign 4\n");
+	printf("lineinfo_filenames_size:\n");
+	printf("\t.long .Lfilenames_end - lineinfo_filenames\n\n");
+
+	/* Concatenated NUL-terminated filenames */
+	printf("\t.globl lineinfo_filenames\n");
+	printf("lineinfo_filenames:\n");
+	for (unsigned int i = 0; i < num_files; i++)
+		print_escaped_asciz(files[i].name);
+	printf(".Lfilenames_end:\n");
+}
+
+static void output_module_assembly(void)
+{
+	unsigned int num_blocks;
+
+	num_blocks = num_entries ?
+		(num_entries + LINEINFO_BLOCK_ENTRIES - 1) / LINEINFO_BLOCK_ENTRIES : 0;
+
+	printf("/* SPDX-License-Identifier: GPL-2.0 */\n");
+	printf("/*\n");
+	printf(" * Automatically generated by scripts/gen_lineinfo --module\n");
+	printf(" * Do not edit.\n");
+	printf(" */\n\n");
+
+	printf("\t.section .mod_lineinfo, \"a\"\n\n");
+
+	/*
+	 * Header -- offsets and sizes are assembler expressions so the
+	 * layout is self-describing without manual C arithmetic.
+	 */
+	printf(".Lhdr:\n");
+	printf("\t.balign 4\n");
+	printf("\t.long %u\t\t\t\t/* num_entries */\n", num_entries);
+	printf("\t.long %u\t\t\t\t/* num_blocks */\n", num_blocks);
+	printf("\t.long %u\t\t\t\t/* num_files */\n", num_files);
+	printf("\t.long .Lblk_addrs - .Lhdr\t\t/* blocks_offset */\n");
+	printf("\t.long .Lblk_offsets_end - .Lblk_addrs\t/* blocks_size */\n");
+	printf("\t.long .Ldata - .Lhdr\t\t\t/* data_offset */\n");
+	printf("\t.long .Ldata_end - .Ldata\t\t/* data_size */\n");
+	printf("\t.long .Lfile_offsets - .Lhdr\t\t/* files_offset */\n");
+	printf("\t.long .Lfile_offsets_end - .Lfile_offsets /* files_size */\n");
+	printf("\t.long .Lfilenames - .Lhdr\t\t/* filenames_offset */\n");
+	printf("\t.long .Lfilenames_end - .Lfilenames\t/* filenames_size */\n");
+	printf("\t.long 0\t\t\t\t\t/* reserved */\n\n");
+
+	/* block_addrs[] */
+	printf(".Lblk_addrs:\n");
+	for (unsigned int i = 0; i < num_blocks; i++)
+		printf("\t.long 0x%x\n", entries[i * LINEINFO_BLOCK_ENTRIES].offset);
+
+	/* block_offsets[] */
+	printf(".Lblk_offsets:\n");
+	for (unsigned int i = 0; i < num_blocks; i++)
+		printf("\t.long .Lblock_%u - .Ldata\n", i);
+	printf(".Lblk_offsets_end:\n\n");
+
+	/* compressed data stream */
+	printf(".Ldata:\n");
+	for (unsigned int i = 0; i < num_blocks; i++) {
+		printf(".Lblock_%u:\n", i);
+		emit_block_data(i);
+	}
+	printf(".Ldata_end:\n");
+
+	/* file_offsets[] */
+	printf("\t.balign 4\n");
+	printf(".Lfile_offsets:\n");
+	for (unsigned int i = 0; i < num_files; i++)
+		printf("\t.long %u\n", files[i].str_offset);
+	printf(".Lfile_offsets_end:\n\n");
+
+	/* filenames[] */
+	printf(".Lfilenames:\n");
+	for (unsigned int i = 0; i < num_files; i++)
+		print_escaped_asciz(files[i].name);
+	printf(".Lfilenames_end:\n");
+}
+
+int main(int argc, char *argv[])
+{
+	int fd;
+	Elf *elf;
+	Dwarf *dwarf;
+	unsigned long long text_addr;
+
+	if (argc >= 2 && !strcmp(argv[1], "--module")) {
+		module_mode = 1;
+		argv++;
+		argc--;
+	}
+
+	if (argc != 2) {
+		fprintf(stderr, "Usage: %s [--module] <ELF file>\n", argv[0]);
+		return 1;
+	}
+
+	/*
+	 * For module mode, open O_RDWR so we can apply debug section
+	 * relocations to the in-memory ELF data.  The modifications
+	 * are NOT written back to disk (no elf_update() call).
+	 */
+	fd = open(argv[1], module_mode ? O_RDWR : O_RDONLY);
+	if (fd < 0) {
+		fprintf(stderr, "Cannot open %s: %s\n", argv[1],
+			strerror(errno));
+		return 1;
+	}
+
+	elf_version(EV_CURRENT);
+	elf = elf_begin(fd, module_mode ? ELF_C_RDWR : ELF_C_READ, NULL);
+	if (!elf) {
+		fprintf(stderr, "elf_begin failed: %s\n",
+			elf_errmsg(elf_errno()));
+		close(fd);
+		return 1;
+	}
+
+	if (module_mode) {
+		/*
+		 * .ko files are ET_REL after ld -r.  libdw does NOT apply
+		 * relocations for ET_REL files, so DW_FORM_line_strp
+		 * references in .debug_line are not resolved.  Apply them
+		 * ourselves so that dwarf_linesrc() returns correct paths.
+		 *
+		 * DWARF addresses include the .text sh_addr.  Use .text
+		 * sh_addr as the base so offsets are .text-relative.
+		 */
+		apply_debug_line_relocations(elf);
+		find_text_section_range(elf);
+		text_addr = text_section_start;
+	} else {
+		text_addr = find_text_addr(elf);
+	}
+
+	dwarf = dwarf_begin_elf(elf, DWARF_C_READ, NULL);
+	if (!dwarf) {
+		fprintf(stderr, "dwarf_begin_elf failed: %s\n",
+			dwarf_errmsg(dwarf_errno()));
+		fprintf(stderr, "Is %s built with CONFIG_DEBUG_INFO?\n",
+			argv[1]);
+		elf_end(elf);
+		close(fd);
+		return 1;
+	}
+
+	process_dwarf(dwarf, text_addr);
+
+	if (skipped_overflow)
+		fprintf(stderr,
+			"lineinfo: warning: %u entries skipped (offset > 4 GiB from _text)\n",
+			skipped_overflow);
+
+	deduplicate();
+	compute_file_offsets();
+
+	fprintf(stderr, "lineinfo: %u entries, %u files, %u blocks\n",
+		num_entries, num_files,
+		num_entries ?
+		(num_entries + LINEINFO_BLOCK_ENTRIES - 1) / LINEINFO_BLOCK_ENTRIES : 0);
+
+	if (module_mode)
+		output_module_assembly();
+	else
+		output_assembly();
+
+	dwarf_end(dwarf);
+	elf_end(elf);
+	close(fd);
+
+	/* Cleanup */
+	free(entries);
+	for (unsigned int i = 0; i < num_files; i++)
+		free(files[i].name);
+	free(files);
+	return 0;
+}
diff --git a/scripts/get_maintainer.pl b/scripts/get_maintainer.pl
index f0ca0db6ddc2..16b80a700d4a 100755
--- a/scripts/get_maintainer.pl
+++ b/scripts/get_maintainer.pl
@@ -21,6 +21,7 @@ use Cwd;
 use File::Find;
 use File::Spec::Functions;
 use open qw(:std :encoding(UTF-8));
+use JSON::PP;
 
 my $cur_path = fastgetcwd() . '/';
 my $lk_path = "./";
@@ -68,6 +69,7 @@ my $pattern_depth = 0;
 my $self_test = undef;
 my $version = 0;
 my $help = 0;
+my $json = 0;
 my $find_maintainer_files = 0;
 my $maintainer_path;
 my $vcs_used = 0;
@@ -285,6 +287,7 @@ if (!GetOptions(
 		'find-maintainer-files' => \$find_maintainer_files,
 		'mpath|maintainer-path=s' => \$maintainer_path,
 		'self-test:s' => \$self_test,
+		'json!' => \$json,
 		'v|version' => \$version,
 		'h|help|usage' => \$help,
 		)) {
@@ -650,39 +653,48 @@ my %deduplicate_name_hash = ();
 my %deduplicate_address_hash = ();
 
 my @maintainers = get_maintainers();
-if (@maintainers) {
-    @maintainers = merge_email(@maintainers);
-    output(@maintainers);
-}
-
-if ($scm) {
-    @scm = uniq(@scm);
-    output(@scm);
-}
-
-if ($output_substatus) {
-    @substatus = uniq(@substatus);
-    output(@substatus);
-}
-
-if ($status) {
-    @status = uniq(@status);
-    output(@status);
-}
 
-if ($subsystem) {
-    @subsystem = uniq(@subsystem);
-    output(@subsystem);
-}
+@maintainers = merge_email(@maintainers) if (@maintainers);
+@scm = uniq(@scm) if ($scm);
+@substatus = uniq(@substatus) if ($output_substatus);
+@status = uniq(@status) if ($status);
+@subsystem = uniq(@subsystem) if ($subsystem);
+@web = uniq(@web) if ($web);
+@bug = uniq(@bug) if ($bug);
+
+if ($json) {
+    my @json_maintainers;
+    for my $m (@maintainers) {
+	my ($addr, $role);
+	if ($output_roles && $m =~ /^(.*?)\s+\((.+)\)\s*$/) {
+	    $addr = $1;
+	    $role = $2;
+	} else {
+	    $addr = $m;
+	}
+	my ($name, $email_addr) = parse_email($addr);
+	my %entry = (name => $name, email => $email_addr);
+	$entry{role} = $role if (defined $role && $role ne '');
+	push(@json_maintainers, \%entry);
+    }
 
-if ($web) {
-    @web = uniq(@web);
-    output(@web);
-}
+    my %result = (maintainers => \@json_maintainers);
+    $result{scm} = \@scm if ($scm);
+    $result{status} = \@status if ($status);
+    $result{subsystem} = \@subsystem if ($subsystem);
+    $result{web} = \@web if ($web);
+    $result{bug} = \@bug if ($bug);
 
-if ($bug) {
-    @bug = uniq(@bug);
-    output(@bug);
+    my $json_encoder = JSON::PP->new->canonical->utf8;
+    print($json_encoder->encode(\%result) . "\n");
+} else {
+    output(@maintainers) if (@maintainers);
+    output(@scm) if ($scm);
+    output(@substatus) if ($output_substatus);
+    output(@status) if ($status);
+    output(@subsystem) if ($subsystem);
+    output(@web) if ($web);
+    output(@bug) if ($bug);
 }
 
 exit($exit);
@@ -1104,6 +1116,7 @@ Output type options:
   --separator [, ] => separator for multiple entries on 1 line
     using --separator also sets --nomultiline if --separator is not [, ]
   --multiline => print 1 entry per line
+  --json => output results as JSON
 
 Other options:
   --pattern-depth => Number of pattern directory traversals (default: 0 (all))
diff --git a/scripts/kallsyms.c b/scripts/kallsyms.c
index 37d5c095ad22..94fbdad3df7c 100644
--- a/scripts/kallsyms.c
+++ b/scripts/kallsyms.c
@@ -78,6 +78,18 @@ static char *sym_name(const struct sym_entry *s)
 
 static bool is_ignored_symbol(const char *name, char type)
 {
+	/* Ignore lineinfo symbols for kallsyms pass stability */
+	static const char * const lineinfo_syms[] = {
+		"lineinfo_block_addrs",
+		"lineinfo_block_offsets",
+		"lineinfo_data",
+		"lineinfo_file_offsets",
+		"lineinfo_filenames",
+		"lineinfo_num_blocks",
+		"lineinfo_num_entries",
+		"lineinfo_num_files",
+	};
+
 	if (type == 'u' || type == 'n')
 		return true;
 
@@ -90,6 +102,11 @@ static bool is_ignored_symbol(const char *name, char type)
 			return true;
 	}
 
+	for (size_t i = 0; i < ARRAY_SIZE(lineinfo_syms); i++) {
+		if (!strcmp(name, lineinfo_syms[i]))
+			return true;
+	}
+
 	return false;
 }
 
diff --git a/scripts/link-vmlinux.sh b/scripts/link-vmlinux.sh
index f99e196abeea..39ca44fbb259 100755
--- a/scripts/link-vmlinux.sh
+++ b/scripts/link-vmlinux.sh
@@ -103,7 +103,7 @@ vmlinux_link()
 	${ld} ${ldflags} -o ${output}					\
 		${wl}--whole-archive ${objs} ${wl}--no-whole-archive	\
 		${wl}--start-group ${libs} ${wl}--end-group		\
-		${kallsymso} ${btf_vmlinux_bin_o} ${arch_vmlinux_o} ${ldlibs}
+		${kallsymso} ${lineinfo_o} ${btf_vmlinux_bin_o} ${arch_vmlinux_o} ${ldlibs}
 }
 
 # Create ${2}.o file with all symbols from the ${1} object file
@@ -129,6 +129,26 @@ kallsyms()
 	kallsymso=${2}.o
 }
 
+# Generate lineinfo tables from DWARF debug info in a temporary vmlinux.
+# ${1} - temporary vmlinux with debug info
+# Output: sets lineinfo_o to the generated .o file
+gen_lineinfo()
+{
+	info LINEINFO .tmp_lineinfo.S
+	if ! scripts/gen_lineinfo "${1}" > .tmp_lineinfo.S; then
+		echo >&2 "Failed to generate lineinfo from ${1}"
+		echo >&2 "Try to disable CONFIG_KALLSYMS_LINEINFO"
+		exit 1
+	fi
+
+	info AS .tmp_lineinfo.o
+	${CC} ${NOSTDINC_FLAGS} ${LINUXINCLUDE} ${KBUILD_CPPFLAGS} \
+	      ${KBUILD_AFLAGS} ${KBUILD_AFLAGS_KERNEL} \
+	      -c -o .tmp_lineinfo.o .tmp_lineinfo.S
+
+	lineinfo_o=.tmp_lineinfo.o
+}
+
 # Perform kallsyms for the given temporary vmlinux.
 sysmap_and_kallsyms()
 {
@@ -155,6 +175,7 @@ sorttable()
 cleanup()
 {
 	rm -f .btf.*
+	rm -f .tmp_lineinfo.*
 	rm -f .tmp_vmlinux.nm-sort
 	rm -f System.map
 	rm -f vmlinux
@@ -183,6 +204,7 @@ fi
 btf_vmlinux_bin_o=
 btfids_vmlinux=
 kallsymso=
+lineinfo_o=
 strip_debug=
 generate_map=
 
@@ -198,10 +220,21 @@ if is_enabled CONFIG_KALLSYMS; then
 	kallsyms .tmp_vmlinux0.syms .tmp_vmlinux0.kallsyms
 fi
 
+if is_enabled CONFIG_KALLSYMS_LINEINFO; then
+	# Assemble an empty lineinfo stub for the initial link.
+	# The real lineinfo is generated from .tmp_vmlinux1 by gen_lineinfo.
+	${CC} ${NOSTDINC_FLAGS} ${LINUXINCLUDE} ${KBUILD_CPPFLAGS} \
+	      ${KBUILD_AFLAGS} ${KBUILD_AFLAGS_KERNEL} \
+	      -c -o .tmp_lineinfo.o "${srctree}/scripts/empty_lineinfo.S"
+	lineinfo_o=.tmp_lineinfo.o
+fi
+
 if is_enabled CONFIG_KALLSYMS || is_enabled CONFIG_DEBUG_INFO_BTF; then
 
-	# The kallsyms linking does not need debug symbols, but the BTF does.
-	if ! is_enabled CONFIG_DEBUG_INFO_BTF; then
+	# The kallsyms linking does not need debug symbols, but BTF and
+	# lineinfo generation do.
+	if ! is_enabled CONFIG_DEBUG_INFO_BTF &&
+	   ! is_enabled CONFIG_KALLSYMS_LINEINFO; then
 		strip_debug=1
 	fi
 
@@ -219,6 +252,10 @@ if is_enabled CONFIG_DEBUG_INFO_BTF; then
 	btfids_vmlinux=.tmp_vmlinux1.BTF_ids
 fi
 
+if is_enabled CONFIG_KALLSYMS_LINEINFO; then
+	gen_lineinfo .tmp_vmlinux1
+fi
+
 if is_enabled CONFIG_KALLSYMS; then
 
 	# kallsyms support
diff --git a/security/keys/Kconfig b/security/keys/Kconfig
index 84f39e50ca36..f4510d8cb485 100644
--- a/security/keys/Kconfig
+++ b/security/keys/Kconfig
@@ -87,7 +87,6 @@ config ENCRYPTED_KEYS
 	select CRYPTO_AES
 	select CRYPTO_CBC
 	select CRYPTO_LIB_SHA256
-	select CRYPTO_RNG
 	help
 	  This option provides support for create/encrypting/decrypting keys
 	  in the kernel.  Encrypted keys are instantiated using kernel
diff --git a/security/keys/trusted-keys/Kconfig b/security/keys/trusted-keys/Kconfig
index 9e00482d886a..e5a4a53aeab2 100644
--- a/security/keys/trusted-keys/Kconfig
+++ b/security/keys/trusted-keys/Kconfig
@@ -1,10 +1,29 @@
 config HAVE_TRUSTED_KEYS
 	bool
 
+config HAVE_TRUSTED_KEYS_DEBUG
+	bool
+
+config TRUSTED_KEYS_DEBUG
+	bool "Debug trusted keys"
+	depends on HAVE_TRUSTED_KEYS_DEBUG
+	default n
+	help
+	  Trusted key backends and core code that support debug traces can
+	  opt-in that feature here. Traces must only use debug level output, as
+	  sensitive data may pass by. In the kernel-command line traces can be
+	  enabled via trusted.dyndbg='+p'.
+
+	  SAFETY: Debug dumps are inactive at runtime until trusted.debug is set
+	  to a true value on the kernel command-line. Use at your utmost
+	  consideration when enabling this feature on a production build. The
+	  general advice is not to do this.
+
 config TRUSTED_KEYS_TPM
 	bool "TPM-based trusted keys"
 	depends on TCG_TPM >= TRUSTED_KEYS
 	default y
+	select HAVE_TRUSTED_KEYS_DEBUG
 	select CRYPTO_HASH_INFO
 	select CRYPTO_LIB_SHA1
 	select CRYPTO_LIB_UTILS
@@ -23,6 +42,7 @@ config TRUSTED_KEYS_TEE
 	bool "TEE-based trusted keys"
 	depends on TEE >= TRUSTED_KEYS
 	default y
+	select HAVE_TRUSTED_KEYS_DEBUG
 	select HAVE_TRUSTED_KEYS
 	help
 	  Enable use of the Trusted Execution Environment (TEE) as trusted
@@ -33,6 +53,7 @@ config TRUSTED_KEYS_CAAM
 	depends on CRYPTO_DEV_FSL_CAAM_JR >= TRUSTED_KEYS
 	select CRYPTO_DEV_FSL_CAAM_BLOB_GEN
 	default y
+	select HAVE_TRUSTED_KEYS_DEBUG
 	select HAVE_TRUSTED_KEYS
 	help
 	  Enable use of NXP's Cryptographic Accelerator and Assurance Module
@@ -42,6 +63,7 @@ config TRUSTED_KEYS_DCP
 	bool "DCP-based trusted keys"
 	depends on CRYPTO_DEV_MXS_DCP >= TRUSTED_KEYS
 	default y
+	select HAVE_TRUSTED_KEYS_DEBUG
 	select HAVE_TRUSTED_KEYS
 	help
 	  Enable use of NXP's DCP (Data Co-Processor) as trusted key backend.
@@ -50,6 +72,7 @@ config TRUSTED_KEYS_PKWM
 	bool "PKWM-based trusted keys"
 	depends on PSERIES_PLPKS >= TRUSTED_KEYS
 	default y
+	select HAVE_TRUSTED_KEYS_DEBUG
 	select HAVE_TRUSTED_KEYS
 	help
 	  Enable use of IBM PowerVM Key Wrapping Module (PKWM) as a trusted key backend.
diff --git a/security/keys/trusted-keys/trusted_caam.c b/security/keys/trusted-keys/trusted_caam.c
index 601943ce0d60..6a33dbf2a7f5 100644
--- a/security/keys/trusted-keys/trusted_caam.c
+++ b/security/keys/trusted-keys/trusted_caam.c
@@ -28,10 +28,13 @@ static const match_table_t key_tokens = {
 	{opt_err, NULL}
 };
 
-#ifdef CAAM_DEBUG
+#ifdef CONFIG_TRUSTED_KEYS_DEBUG
 static inline void dump_options(const struct caam_pkey_info *pkey_info)
 {
-	pr_info("key encryption algo %d\n", pkey_info->key_enc_algo);
+	if (!trusted_debug)
+		return;
+
+	pr_debug("key encryption algo %d\n", pkey_info->key_enc_algo);
 }
 #else
 static inline void dump_options(const struct caam_pkey_info *pkey_info)
diff --git a/security/keys/trusted-keys/trusted_core.c b/security/keys/trusted-keys/trusted_core.c
index 0b142d941cd2..6aed17bee09d 100644
--- a/security/keys/trusted-keys/trusted_core.c
+++ b/security/keys/trusted-keys/trusted_core.c
@@ -31,6 +31,12 @@ static char *trusted_rng = "default";
 module_param_named(rng, trusted_rng, charp, 0);
 MODULE_PARM_DESC(rng, "Select trusted key RNG");
 
+#ifdef CONFIG_TRUSTED_KEYS_DEBUG
+bool trusted_debug;
+module_param_named(debug, trusted_debug, bool, 0);
+MODULE_PARM_DESC(debug, "Enable trusted keys debug traces (default: 0)");
+#endif
+
 static char *trusted_key_source;
 module_param_named(source, trusted_key_source, charp, 0);
 MODULE_PARM_DESC(source, "Select trusted keys source (tpm, tee, caam, dcp or pkwm)");
diff --git a/security/keys/trusted-keys/trusted_tpm1.c b/security/keys/trusted-keys/trusted_tpm1.c
index 6ea728f1eae6..13513819991e 100644
--- a/security/keys/trusted-keys/trusted_tpm1.c
+++ b/security/keys/trusted-keys/trusted_tpm1.c
@@ -46,38 +46,44 @@ enum {
 	SRK_keytype = 4
 };
 
-#define TPM_DEBUG 0
-
-#if TPM_DEBUG
+#ifdef CONFIG_TRUSTED_KEYS_DEBUG
 static inline void dump_options(struct trusted_key_options *o)
 {
-	pr_info("sealing key type %d\n", o->keytype);
-	pr_info("sealing key handle %0X\n", o->keyhandle);
-	pr_info("pcrlock %d\n", o->pcrlock);
-	pr_info("pcrinfo %d\n", o->pcrinfo_len);
-	print_hex_dump(KERN_INFO, "pcrinfo ", DUMP_PREFIX_NONE,
-		       16, 1, o->pcrinfo, o->pcrinfo_len, 0);
+	if (!trusted_debug)
+		return;
+
+	pr_debug("sealing key type %d\n", o->keytype);
+	pr_debug("sealing key handle %0X\n", o->keyhandle);
+	pr_debug("pcrlock %d\n", o->pcrlock);
+	pr_debug("pcrinfo %d\n", o->pcrinfo_len);
+	print_hex_dump_debug("pcrinfo ", DUMP_PREFIX_NONE,
+			     16, 1, o->pcrinfo, o->pcrinfo_len, 0);
 }
 
 static inline void dump_sess(struct osapsess *s)
 {
-	print_hex_dump(KERN_INFO, "trusted-key: handle ", DUMP_PREFIX_NONE,
-		       16, 1, &s->handle, 4, 0);
-	pr_info("secret:\n");
-	print_hex_dump(KERN_INFO, "", DUMP_PREFIX_NONE,
-		       16, 1, &s->secret, SHA1_DIGEST_SIZE, 0);
-	pr_info("trusted-key: enonce:\n");
-	print_hex_dump(KERN_INFO, "", DUMP_PREFIX_NONE,
-		       16, 1, &s->enonce, SHA1_DIGEST_SIZE, 0);
+	if (!trusted_debug)
+		return;
+
+	print_hex_dump_debug("trusted-key: handle ", DUMP_PREFIX_NONE,
+			     16, 1, &s->handle, 4, 0);
+	pr_debug("secret:\n");
+	print_hex_dump_debug("", DUMP_PREFIX_NONE,
+			     16, 1, &s->secret, SHA1_DIGEST_SIZE, 0);
+	pr_debug("trusted-key: enonce:\n");
+	print_hex_dump_debug("", DUMP_PREFIX_NONE,
+			     16, 1, &s->enonce, SHA1_DIGEST_SIZE, 0);
 }
 
 static inline void dump_tpm_buf(unsigned char *buf)
 {
 	int len;
 
-	pr_info("\ntpm buffer\n");
+	if (!trusted_debug)
+		return;
+	pr_debug("\ntpm buffer\n");
 	len = LOAD32(buf, TPM_SIZE_OFFSET);
-	print_hex_dump(KERN_INFO, "", DUMP_PREFIX_NONE, 16, 1, buf, len, 0);
+	print_hex_dump_debug("", DUMP_PREFIX_NONE, 16, 1, buf, len, 0);
 }
 #else
 static inline void dump_options(struct trusted_key_options *o)
diff --git a/security/smack/smack_lsm.c b/security/smack/smack_lsm.c
index 3f9ae05039a2..db9eb23ba517 100644
--- a/security/smack/smack_lsm.c
+++ b/security/smack/smack_lsm.c
@@ -1312,7 +1312,7 @@ static int smack_inode_getattr(const struct path *path)
  */
 static int smack_inode_xattr_skipcap(const char *name)
 {
-	if (strncmp(name, XATTR_SMACK_SUFFIX, strlen(XATTR_SMACK_SUFFIX)))
+	if (strncmp(name, XATTR_SMACK_SUFFIX, strlen(XATTR_SMACK_SUFFIX)) == 0)
 		return 0;
 
 	if (strcmp(name, XATTR_NAME_SMACK) == 0 ||
diff --git a/sound/soc/amd/acp/acp-legacy-mach.c b/sound/soc/amd/acp/acp-legacy-mach.c
index a7a551366a40..235d6cc83fa9 100644
--- a/sound/soc/amd/acp/acp-legacy-mach.c
+++ b/sound/soc/amd/acp/acp-legacy-mach.c
@@ -174,7 +174,7 @@ static int acp_asoc_probe(struct platform_device *pdev)
 		acp_card_drvdata->acp_rev = mach->mach_params.subsystem_rev;
 
 	dmi_id = dmi_first_match(acp_quirk_table);
-	if (dmi_id && dmi_id->driver_data)
+	if (dmi_id && dmi_id->driver_data == (void *)QUIRK_TDM_MODE_ENABLE)
 		acp_card_drvdata->tdm_mode = dmi_id->driver_data;
 
 	ret = acp_legacy_dai_links_create(card);
diff --git a/sound/soc/amd/acp/acp-mach-common.c b/sound/soc/amd/acp/acp-mach-common.c
index 09f6c9a2c041..ef784cca13f2 100644
--- a/sound/soc/amd/acp/acp-mach-common.c
+++ b/sound/soc/amd/acp/acp-mach-common.c
@@ -20,6 +20,7 @@
 #include <sound/soc.h>
 #include <linux/input.h>
 #include <linux/module.h>
+#include <linux/dmi.h>
 
 #include "../../codecs/rt5682.h"
 #include "../../codecs/rt1019.h"
@@ -37,15 +38,21 @@
 #define NAU8821_FREQ_OUT	12288000
 #define MAX98388_CODEC_DAI	"max98388-aif1"
 
-#define TDM_MODE_ENABLE 1
-
 const struct dmi_system_id acp_quirk_table[] = {
 	{
 		/* Google skyrim proto-0 */
 		.matches = {
 			DMI_EXACT_MATCH(DMI_PRODUCT_FAMILY, "Google_Skyrim"),
 		},
-		.driver_data = (void *)TDM_MODE_ENABLE,
+		.driver_data = (void *)QUIRK_TDM_MODE_ENABLE,
+	},
+	{
+		/* Valve Steam Deck OLED */
+		.matches = {
+			DMI_MATCH(DMI_SYS_VENDOR, "Valve"),
+			DMI_MATCH(DMI_PRODUCT_NAME, "Galileo"),
+		},
+		.driver_data = (void *)QUIRK_REMAP_DMIC_BT,
 	},
 	{}
 };
@@ -1401,6 +1408,7 @@ int acp_sofdsp_dai_links_create(struct snd_soc_card *card)
 	struct snd_soc_dai_link *links;
 	struct device *dev = card->dev;
 	struct acp_card_drvdata *drv_data = card->drvdata;
+	const struct dmi_system_id *dmi_id = dmi_first_match(acp_quirk_table);
 	int i = 0, num_links = 0;
 
 	if (drv_data->hs_cpu_id)
@@ -1572,6 +1580,9 @@ int acp_sofdsp_dai_links_create(struct snd_soc_card *card)
 			links[i].codecs = &snd_soc_dummy_dlc;
 			links[i].num_codecs = 1;
 		}
+
+		if (dmi_id && dmi_id->driver_data == (void *)QUIRK_REMAP_DMIC_BT)
+			links[i].id = DMIC_BE_ID;
 		i++;
 	}
 
@@ -1587,6 +1598,11 @@ int acp_sofdsp_dai_links_create(struct snd_soc_card *card)
 		links[i].capture_only = 1;
 		links[i].nonatomic = true;
 		links[i].no_pcm = 1;
+
+		if (dmi_id && dmi_id->driver_data == (void *)QUIRK_REMAP_DMIC_BT) {
+			links[i].id = BT_BE_ID;
+			dev_dbg(dev, "quirk REMAP_DMIC_BT enabled\n");
+		}
 	}
 
 	card->dai_link = links;
diff --git a/sound/soc/amd/acp/acp-mach.h b/sound/soc/amd/acp/acp-mach.h
index f94c30c20f20..7177d3fd9619 100644
--- a/sound/soc/amd/acp/acp-mach.h
+++ b/sound/soc/amd/acp/acp-mach.h
@@ -26,6 +26,10 @@
 
 #define acp_get_drvdata(card) ((struct acp_card_drvdata *)(card)->drvdata)
 
+/* List of DMI quirks - check acp-mach-common.c for usage. */
+#define QUIRK_TDM_MODE_ENABLE 1
+#define QUIRK_REMAP_DMIC_BT 2
+
 enum be_id {
 	HEADSET_BE_ID = 0,
 	AMP_BE_ID,
diff --git a/sound/soc/amd/acp/acp-sof-mach.c b/sound/soc/amd/acp/acp-sof-mach.c
index 6215e31ecedd..36ecef7013b9 100644
--- a/sound/soc/amd/acp/acp-sof-mach.c
+++ b/sound/soc/amd/acp/acp-sof-mach.c
@@ -110,7 +110,7 @@ static int acp_sof_probe(struct platform_device *pdev)
 
 	acp_card_drvdata = card->drvdata;
 	dmi_id = dmi_first_match(acp_quirk_table);
-	if (dmi_id && dmi_id->driver_data)
+	if (dmi_id && dmi_id->driver_data == (void *)QUIRK_TDM_MODE_ENABLE)
 		acp_card_drvdata->tdm_mode = dmi_id->driver_data;
 
 	acp_card_drvdata->acp_rev = mach->mach_params.subsystem_rev;
diff --git a/sound/soc/apple/mca.c b/sound/soc/apple/mca.c
index 39269cc7def6..492165c0e1ea 100644
--- a/sound/soc/apple/mca.c
+++ b/sound/soc/apple/mca.c
@@ -307,7 +307,7 @@ static bool mca_fe_clocks_in_use(struct mca_cluster *cl)
 	struct mca_cluster *be_cl;
 	int stream, i;
 
-	mutex_lock(&mca->port_mutex);
+	guard(mutex)(&mca->port_mutex);
 	for (i = 0; i < mca->nclusters; i++) {
 		be_cl = &mca->clusters[i];
 
@@ -316,12 +316,10 @@ static bool mca_fe_clocks_in_use(struct mca_cluster *cl)
 
 		for_each_pcm_streams(stream) {
 			if (be_cl->clocks_in_use[stream]) {
-				mutex_unlock(&mca->port_mutex);
 				return true;
 			}
 		}
 	}
-	mutex_unlock(&mca->port_mutex);
 	return false;
 }
 
@@ -765,9 +763,8 @@ static int mca_be_startup(struct snd_pcm_substream *substream,
 		       cl->base + REG_PORT_CLOCK_SEL);
 	writel_relaxed(PORT_DATA_SEL_TXA(fe_cl->no),
 		       cl->base + REG_PORT_DATA_SEL);
-	mutex_lock(&mca->port_mutex);
-	cl->port_driver = fe_cl->no;
-	mutex_unlock(&mca->port_mutex);
+	scoped_guard(mutex, &mca->port_mutex)
+		cl->port_driver = fe_cl->no;
 	cl->port_started[substream->stream] = true;
 
 	return 0;
@@ -788,9 +785,8 @@ static void mca_be_shutdown(struct snd_pcm_substream *substream,
 		 */
 		writel_relaxed(0, cl->base + REG_PORT_ENABLES);
 		writel_relaxed(0, cl->base + REG_PORT_DATA_SEL);
-		mutex_lock(&mca->port_mutex);
-		cl->port_driver = -1;
-		mutex_unlock(&mca->port_mutex);
+		scoped_guard(mutex, &mca->port_mutex)
+			cl->port_driver = -1;
 	}
 }
 
diff --git a/sound/soc/atmel/atmel-classd.c b/sound/soc/atmel/atmel-classd.c
index 1f8c60d2de82..6693bdcbb8f5 100644
--- a/sound/soc/atmel/atmel-classd.c
+++ b/sound/soc/atmel/atmel-classd.c
@@ -11,6 +11,7 @@
 #include <linux/module.h>
 #include <linux/platform_device.h>
 #include <linux/regmap.h>
+#include <linux/bitfield.h>
 #include <linux/string_choices.h>
 #include <sound/core.h>
 #include <sound/dmaengine_pcm.h>
@@ -236,34 +237,34 @@ static int atmel_classd_component_probe(struct snd_soc_component *component)
 	u32 mask, val;
 
 	mask = CLASSD_MR_PWMTYP_MASK;
-	val = pdata->pwm_type << CLASSD_MR_PWMTYP_SHIFT;
+	val = FIELD_PREP(CLASSD_MR_PWMTYP_MASK, pdata->pwm_type);
 
 	mask |= CLASSD_MR_NON_OVERLAP_MASK;
 	if (pdata->non_overlap_enable) {
-		val |= (CLASSD_MR_NON_OVERLAP_EN
-			<< CLASSD_MR_NON_OVERLAP_SHIFT);
+		val |= FIELD_PREP(CLASSD_MR_NON_OVERLAP_MASK,
+				CLASSD_MR_NON_OVERLAP_EN);
 
 		mask |= CLASSD_MR_NOVR_VAL_MASK;
 		switch (pdata->non_overlap_time) {
 		case 5:
-			val |= (CLASSD_MR_NOVR_VAL_5NS
-				<< CLASSD_MR_NOVR_VAL_SHIFT);
+			val |= FIELD_PREP(CLASSD_MR_NOVR_VAL_MASK,
+					CLASSD_MR_NOVR_VAL_5NS);
 			break;
 		case 10:
-			val |= (CLASSD_MR_NOVR_VAL_10NS
-				<< CLASSD_MR_NOVR_VAL_SHIFT);
+			val |= FIELD_PREP(CLASSD_MR_NOVR_VAL_MASK,
+					CLASSD_MR_NOVR_VAL_10NS);
 			break;
 		case 15:
-			val |= (CLASSD_MR_NOVR_VAL_15NS
-				<< CLASSD_MR_NOVR_VAL_SHIFT);
+			val |= FIELD_PREP(CLASSD_MR_NOVR_VAL_MASK,
+					CLASSD_MR_NOVR_VAL_15NS);
 			break;
 		case 20:
-			val |= (CLASSD_MR_NOVR_VAL_20NS
-				<< CLASSD_MR_NOVR_VAL_SHIFT);
+			val |= FIELD_PREP(CLASSD_MR_NOVR_VAL_MASK,
+					CLASSD_MR_NOVR_VAL_20NS);
 			break;
 		default:
-			val |= (CLASSD_MR_NOVR_VAL_10NS
-				<< CLASSD_MR_NOVR_VAL_SHIFT);
+			val |= FIELD_PREP(CLASSD_MR_NOVR_VAL_MASK,
+					CLASSD_MR_NOVR_VAL_10NS);
 			dev_warn(component->dev,
 				"non-overlapping value %d is invalid, the default value 10 is specified\n",
 				pdata->non_overlap_time);
@@ -370,8 +371,10 @@ atmel_classd_cpu_dai_hw_params(struct snd_pcm_substream *substream,
 		return ret;
 
 	mask = CLASSD_INTPMR_DSP_CLK_FREQ_MASK | CLASSD_INTPMR_FRAME_MASK;
-	val = (sample_rates[best].dsp_clk << CLASSD_INTPMR_DSP_CLK_FREQ_SHIFT)
-	| (sample_rates[best].sample_rate << CLASSD_INTPMR_FRAME_SHIFT);
+	val = FIELD_PREP(CLASSD_INTPMR_DSP_CLK_FREQ_MASK,
+			sample_rates[best].dsp_clk) |
+		FIELD_PREP(CLASSD_INTPMR_FRAME_MASK,
+			sample_rates[best].sample_rate);
 
 	snd_soc_component_update_bits(component, CLASSD_INTPMR, mask, val);
 
@@ -395,8 +398,8 @@ static int atmel_classd_cpu_dai_prepare(struct snd_pcm_substream *substream,
 
 	snd_soc_component_update_bits(component, CLASSD_MR,
 				CLASSD_MR_LEN_MASK | CLASSD_MR_REN_MASK,
-				(CLASSD_MR_LEN_DIS << CLASSD_MR_LEN_SHIFT)
-				|(CLASSD_MR_REN_DIS << CLASSD_MR_REN_SHIFT));
+				FIELD_PREP(CLASSD_MR_LEN_MASK, CLASSD_MR_LEN_DIS) |
+				FIELD_PREP(CLASSD_MR_REN_MASK, CLASSD_MR_REN_DIS));
 
 	return 0;
 }
@@ -418,8 +421,8 @@ static int atmel_classd_cpu_dai_trigger(struct snd_pcm_substream *substream,
 	case SNDRV_PCM_TRIGGER_STOP:
 	case SNDRV_PCM_TRIGGER_SUSPEND:
 	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
-		val = (CLASSD_MR_LEN_DIS << CLASSD_MR_LEN_SHIFT)
-			| (CLASSD_MR_REN_DIS << CLASSD_MR_REN_SHIFT);
+		val = FIELD_PREP(CLASSD_MR_LEN_MASK, CLASSD_MR_LEN_DIS) |
+			FIELD_PREP(CLASSD_MR_REN_MASK, CLASSD_MR_REN_DIS);
 		break;
 	default:
 		return -EINVAL;
diff --git a/sound/soc/atmel/mchp-spdifrx.c b/sound/soc/atmel/mchp-spdifrx.c
index 521bee4998f8..2c47aabdca95 100644
--- a/sound/soc/atmel/mchp-spdifrx.c
+++ b/sound/soc/atmel/mchp-spdifrx.c
@@ -6,6 +6,7 @@
 //
 // Author: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>
 
+#include <linux/bitfield.h>
 #include <linux/clk.h>
 #include <linux/io.h>
 #include <linux/module.h>
@@ -41,6 +42,13 @@
 
 #define SPDIFRX_VERSION			0xFC	/* Version Register */
 
+
+/* 32-bit word byte masks */
+#define SPDIFRX_BYTE_0_MASK         GENMASK(7, 0)
+#define SPDIFRX_BYTE_1_MASK         GENMASK(15, 8)
+#define SPDIFRX_BYTE_2_MASK         GENMASK(23, 16)
+#define SPDIFRX_BYTE_3_MASK         GENMASK(31, 24)
+
 /*
  * ---- Control Register (Write-only) ----
  */
@@ -55,7 +63,7 @@
 #define SPDIFRX_MR_RXEN_ENABLE		(1 << 0)	/* SPDIF Receiver Enabled */
 
 /* Validity Bit Mode */
-#define SPDIFRX_MR_VBMODE_MASK		GENAMSK(1, 1)
+#define SPDIFRX_MR_VBMODE_MASK		GENMASK(1, 1)
 #define SPDIFRX_MR_VBMODE_ALWAYS_LOAD \
 	(0 << 1)	/* Load sample regardless of validity bit value */
 #define SPDIFRX_MR_VBMODE_DISCARD_IF_VB1 \
@@ -74,7 +82,7 @@
 /* Sample Data Width */
 #define SPDIFRX_MR_DATAWIDTH_MASK	GENMASK(5, 4)
 #define SPDIFRX_MR_DATAWIDTH(width) \
-	(((6 - (width) / 4) << 4) & SPDIFRX_MR_DATAWIDTH_MASK)
+	FIELD_PREP(SPDIFRX_MR_DATAWIDTH_MASK, 6 - ((width) / 4))
 
 /* Packed Data Mode in Receive Holding Register */
 #define SPDIFRX_MR_PACK_MASK		GENMASK(7, 7)
@@ -118,15 +126,14 @@
 #define SPDIFRX_RSR_LOWF			BIT(2)
 #define SPDIFRX_RSR_NOSIGNAL			BIT(3)
 #define SPDIFRX_RSR_IFS_MASK			GENMASK(27, 16)
-#define SPDIFRX_RSR_IFS(reg)			\
-	(((reg) & SPDIFRX_RSR_IFS_MASK) >> 16)
+#define SPDIFRX_RSR_IFS(reg)			FIELD_GET(SPDIFRX_RSR_IFS_MASK, reg)
 
 /*
  *  ---- Version Register (Read-only) ----
  */
 #define SPDIFRX_VERSION_MASK		GENMASK(11, 0)
 #define SPDIFRX_VERSION_MFN_MASK	GENMASK(18, 16)
-#define SPDIFRX_VERSION_MFN(reg)	(((reg) & SPDIFRX_VERSION_MFN_MASK) >> 16)
+#define SPDIFRX_VERSION_MFN(reg)	FIELD_GET(SPDIFRX_VERSION_MFN_MASK, reg)
 
 static bool mchp_spdifrx_readable_reg(struct device *dev, unsigned int reg)
 {
@@ -317,10 +324,10 @@ static void mchp_spdifrx_channel_status_read(struct mchp_spdifrx_dev *dev,
 
 	for (i = 0; i < ARRAY_SIZE(ctrl->ch_stat[channel].data) / 4; i++) {
 		regmap_read(dev->regmap, SPDIFRX_CHSR(channel, i), &val);
-		*ch_stat++ = val & 0xFF;
-		*ch_stat++ = (val >> 8) & 0xFF;
-		*ch_stat++ = (val >> 16) & 0xFF;
-		*ch_stat++ = (val >> 24) & 0xFF;
+		*ch_stat++ = FIELD_GET(SPDIFRX_BYTE_0_MASK, val);
+		*ch_stat++ = FIELD_GET(SPDIFRX_BYTE_1_MASK, val);
+		*ch_stat++ = FIELD_GET(SPDIFRX_BYTE_2_MASK, val);
+		*ch_stat++ = FIELD_GET(SPDIFRX_BYTE_3_MASK, val);
 	}
 }
 
@@ -334,10 +341,10 @@ static void mchp_spdifrx_channel_user_data_read(struct mchp_spdifrx_dev *dev,
 
 	for (i = 0; i < ARRAY_SIZE(ctrl->user_data[channel].data) / 4; i++) {
 		regmap_read(dev->regmap, SPDIFRX_CHUD(channel, i), &val);
-		*user_data++ = val & 0xFF;
-		*user_data++ = (val >> 8) & 0xFF;
-		*user_data++ = (val >> 16) & 0xFF;
-		*user_data++ = (val >> 24) & 0xFF;
+		*user_data++ = FIELD_GET(SPDIFRX_BYTE_0_MASK, val);
+		*user_data++ = FIELD_GET(SPDIFRX_BYTE_1_MASK, val);
+		*user_data++ = FIELD_GET(SPDIFRX_BYTE_2_MASK, val);
+		*user_data++ = FIELD_GET(SPDIFRX_BYTE_3_MASK, val);
 	}
 }
 
diff --git a/sound/soc/codecs/tas2764.c b/sound/soc/codecs/tas2764.c
index 423b7073b302..6aab6d2b7419 100644
--- a/sound/soc/codecs/tas2764.c
+++ b/sound/soc/codecs/tas2764.c
@@ -904,6 +904,7 @@ static bool tas2764_volatile_register(struct device *dev, unsigned int reg)
 {
 	switch (reg) {
 	case TAS2764_SW_RST:
+	case TAS2764_TEMP:
 	case TAS2764_INT_LTCH0 ... TAS2764_INT_LTCH4:
 	case TAS2764_INT_CLK_CFG:
 		return true;
diff --git a/sound/soc/codecs/tas2770.c b/sound/soc/codecs/tas2770.c
index d4d7d056141b..50501bcbe916 100644
--- a/sound/soc/codecs/tas2770.c
+++ b/sound/soc/codecs/tas2770.c
@@ -624,7 +624,7 @@ static int tas2770_read_die_temp(struct tas2770_priv *tas2770, long *result)
 	/*
 	 * As per datasheet: divide register by 16 and subtract 93 to get
 	 * degrees Celsius. hwmon requires millidegrees. Let's avoid rounding
-	 * errors by subtracting 93 * 16 then multiplying by 1000 / 16.
+	 * errors by subtracting 93 * 16 and scaling before dividing.
 	 *
 	 * NOTE: The ADC registers are initialised to 0 on reset. This means
 	 * that the temperature will read -93 *C until the chip is brought out
@@ -633,7 +633,7 @@ static int tas2770_read_die_temp(struct tas2770_priv *tas2770, long *result)
 	 * value read back from its registers will be the last value sampled
 	 * before entering software shutdown.
 	 */
-	*result = (reading - (93 * 16)) * (1000 / 16);
+	*result = (reading - (93 * 16)) * 1000 / 16;
 	return 0;
 }
 
diff --git a/sound/soc/codecs/tlv320aic3x.c b/sound/soc/codecs/tlv320aic3x.c
index ce22298b43ef..b12c1952823b 100644
--- a/sound/soc/codecs/tlv320aic3x.c
+++ b/sound/soc/codecs/tlv320aic3x.c
@@ -1689,8 +1689,15 @@ static int aic3x_component_probe(struct snd_soc_component *component)
 	return 0;
 }
 
+static int aic3x_of_xlate_dai_id(struct snd_soc_component *component,
+				   struct device_node *endpoint)
+{
+	return 0;
+}
+
 static const struct snd_soc_component_driver soc_component_dev_aic3x = {
 	.set_bias_level		= aic3x_set_bias_level,
+	.of_xlate_dai_id	= aic3x_of_xlate_dai_id,
 	.probe			= aic3x_component_probe,
 	.controls		= aic3x_snd_controls,
 	.num_controls		= ARRAY_SIZE(aic3x_snd_controls),
diff --git a/sound/soc/fsl/fsl_micfil.c b/sound/soc/fsl/fsl_micfil.c
index 2e887f1f1f36..60ac8eabab9d 100644
--- a/sound/soc/fsl/fsl_micfil.c
+++ b/sound/soc/fsl/fsl_micfil.c
@@ -74,6 +74,7 @@ struct fsl_micfil {
 	int irq[MICFIL_IRQ_LINES];
 	enum quality quality;
 	int dc_remover;
+	int dc_out_remover;
 	int vad_init_mode;
 	int vad_enabled;
 	int vad_detected;
@@ -347,6 +348,11 @@ static const char * const micfil_dc_remover_texts[] = {
 	"Cut-off @152Hz", "Bypass",
 };
 
+static const char * const micfil_dc_out_remover_texts[] = {
+	"Cut-off @20Hz", "Cut-off @13.3Hz",
+	"Cut-off @40Hz", "Bypass",
+};
+
 static const struct soc_enum hwvad_enable_enum =
 	SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(micfil_hwvad_enable),
 			    micfil_hwvad_enable);
@@ -360,6 +366,9 @@ static const struct soc_enum hwvad_hpf_enum =
 static const struct soc_enum fsl_micfil_dc_remover_enum =
 	SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(micfil_dc_remover_texts),
 			    micfil_dc_remover_texts);
+static const struct soc_enum fsl_micfil_dc_out_remover_enum =
+	SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(micfil_dc_out_remover_texts),
+			    micfil_dc_out_remover_texts);
 
 static int micfil_put_dc_remover_state(struct snd_kcontrol *kcontrol,
 				       struct snd_ctl_elem_value *ucontrol)
@@ -405,6 +414,50 @@ static int micfil_get_dc_remover_state(struct snd_kcontrol *kcontrol,
 	return 0;
 }
 
+static int micfil_put_dc_out_remover_state(struct snd_kcontrol *kcontrol,
+					   struct snd_ctl_elem_value *ucontrol)
+{
+	struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
+	struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);
+	struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp);
+	unsigned int *item = ucontrol->value.enumerated.item;
+	int val = snd_soc_enum_item_to_val(e, item[0]);
+	int i = 0, ret = 0;
+	u32 reg_val = 0;
+
+	if (val < 0 || val > 3)
+		return -EINVAL;
+
+	ret = pm_runtime_resume_and_get(comp->dev);
+	if (ret)
+		return ret;
+
+	micfil->dc_out_remover = val;
+
+	/* Calculate total value for all channels */
+	for (i = 0; i < MICFIL_OUTPUT_CHANNELS; i++)
+		reg_val |= val << MICFIL_DC_CHX_SHIFT(i);
+
+	/* Update DC Remover mode for all channels */
+	ret = snd_soc_component_update_bits(comp, REG_MICFIL_DC_OUT_CTRL,
+					    MICFIL_DC_CTRL_CONFIG, reg_val);
+
+	pm_runtime_put_autosuspend(comp->dev);
+
+	return ret;
+}
+
+static int micfil_get_dc_out_remover_state(struct snd_kcontrol *kcontrol,
+					   struct snd_ctl_elem_value *ucontrol)
+{
+	struct snd_soc_component *comp = snd_kcontrol_chip(kcontrol);
+	struct fsl_micfil *micfil = snd_soc_component_get_drvdata(comp);
+
+	ucontrol->value.enumerated.item[0] = micfil->dc_out_remover;
+
+	return 0;
+}
+
 static int hwvad_put_enable(struct snd_kcontrol *kcontrol,
 			    struct snd_ctl_elem_value *ucontrol)
 {
@@ -525,6 +578,11 @@ static const struct snd_kcontrol_new fsl_micfil_volume_sx_controls[] = {
 			  MICFIL_OUTGAIN_CHX_SHIFT(7), 0x8, 0xF, gain_tlv),
 };
 
+static const struct snd_kcontrol_new fsl_micfil_dc_out_controls[] = {
+	SOC_ENUM_EXT("MICFIL DC Out Remover Control", fsl_micfil_dc_out_remover_enum,
+		     micfil_get_dc_out_remover_state, micfil_put_dc_out_remover_state),
+};
+
 static const struct snd_kcontrol_new fsl_micfil_snd_controls[] = {
 	SOC_ENUM_EXT("MICFIL Quality Select",
 		     fsl_micfil_quality_enum,
@@ -1047,6 +1105,19 @@ static int fsl_micfil_dai_probe(struct snd_soc_dai *cpu_dai)
 	}
 	micfil->dc_remover = MICFIL_DC_BYPASS;
 
+	if (micfil->soc->use_verid) {
+		val = 0;
+		for (i = 0; i < MICFIL_OUTPUT_CHANNELS; i++)
+			val |= MICFIL_DC_BYPASS << MICFIL_DC_CHX_SHIFT(i);
+		ret = regmap_update_bits(micfil->regmap, REG_MICFIL_DC_OUT_CTRL,
+					 MICFIL_DC_CTRL_CONFIG, val);
+		if (ret) {
+			dev_err(dev, "failed to set DC OUT Remover mode bits\n");
+			return ret;
+		}
+		micfil->dc_out_remover = MICFIL_DC_BYPASS;
+	}
+
 	snd_soc_dai_init_dma_data(cpu_dai, NULL,
 				  &micfil->dma_params_rx);
 
@@ -1071,6 +1142,10 @@ static int fsl_micfil_component_probe(struct snd_soc_component *component)
 		snd_soc_add_component_controls(component, fsl_micfil_range_controls,
 					       ARRAY_SIZE(fsl_micfil_range_controls));
 
+	if (micfil->soc->use_verid)
+		snd_soc_add_component_controls(component, fsl_micfil_dc_out_controls,
+					       ARRAY_SIZE(fsl_micfil_dc_out_controls));
+
 	return 0;
 }
 
@@ -1117,6 +1192,7 @@ static const struct reg_default fsl_micfil_reg_defaults[] = {
 	{REG_MICFIL_DATACH6,		0x00000000},
 	{REG_MICFIL_DATACH7,		0x00000000},
 	{REG_MICFIL_DC_CTRL,		0x00000000},
+	{REG_MICFIL_DC_OUT_CTRL,	0x00000000},
 	{REG_MICFIL_OUT_CTRL,		0x00000000},
 	{REG_MICFIL_OUT_STAT,		0x00000000},
 	{REG_MICFIL_VAD0_CTRL1,		0x00000000},
@@ -1143,6 +1219,7 @@ static const struct reg_default fsl_micfil_reg_defaults_v2[] = {
 	{REG_MICFIL_DATACH6 - 0x4,	0x00000000},
 	{REG_MICFIL_DATACH7 - 0x4,	0x00000000},
 	{REG_MICFIL_DC_CTRL,		0x00000000},
+	{REG_MICFIL_DC_OUT_CTRL,	0x00000000},
 	{REG_MICFIL_OUT_CTRL,		0x00000000},
 	{REG_MICFIL_OUT_STAT,		0x00000000},
 	{REG_MICFIL_VAD0_CTRL1,		0x00000000},
@@ -1179,6 +1256,7 @@ static bool fsl_micfil_readable_reg(struct device *dev, unsigned int reg)
 	case REG_MICFIL_VAD0_NDATA:
 	case REG_MICFIL_VAD0_ZCD:
 		return true;
+	case REG_MICFIL_DC_OUT_CTRL:
 	case REG_MICFIL_FSYNC_CTRL:
 	case REG_MICFIL_VERID:
 	case REG_MICFIL_PARAM:
@@ -1210,6 +1288,7 @@ static bool fsl_micfil_writeable_reg(struct device *dev, unsigned int reg)
 	case REG_MICFIL_VAD0_NCONFIG:
 	case REG_MICFIL_VAD0_ZCD:
 		return true;
+	case REG_MICFIL_DC_OUT_CTRL:
 	case REG_MICFIL_FSYNC_CTRL:
 		if (micfil->soc->use_verid)
 			return true;
diff --git a/sound/soc/fsl/fsl_micfil.h b/sound/soc/fsl/fsl_micfil.h
index fdfe4e7125bc..e271c6073f42 100644
--- a/sound/soc/fsl/fsl_micfil.h
+++ b/sound/soc/fsl/fsl_micfil.h
@@ -22,6 +22,7 @@
 #define REG_MICFIL_DATACH6		0x3C
 #define REG_MICFIL_DATACH7		0x40
 #define REG_MICFIL_DC_CTRL		0x64
+#define REG_MICFIL_DC_OUT_CTRL		0x68
 #define REG_MICFIL_OUT_CTRL		0x74
 #define REG_MICFIL_OUT_STAT		0x7C
 #define REG_MICFIL_FSYNC_CTRL		0x80
diff --git a/sound/soc/soc-ops.c b/sound/soc/soc-ops.c
index bbf277670718..c935571d43e9 100644
--- a/sound/soc/soc-ops.c
+++ b/sound/soc/soc-ops.c
@@ -461,6 +461,10 @@ int snd_soc_limit_volume(struct snd_soc_card *card, const char *name, int max)
 			mc->platform_max = max;
 			ret = snd_soc_clip_to_platform_max(kctl);
 		}
+	} else {
+		/* Some cards blindly add limits for multiple variants. */
+		dev_dbg(card->dev, "Volume limit for unknown control '%s'\n",
+			name);
 	}
 
 	return ret;
diff --git a/sound/soc/sof/intel/hda.c b/sound/soc/sof/intel/hda.c
index b3d61d973ce4..8662b422eb80 100644
--- a/sound/soc/sof/intel/hda.c
+++ b/sound/soc/sof/intel/hda.c
@@ -1412,7 +1412,8 @@ static struct snd_soc_acpi_mach *hda_sdw_machine_select(struct snd_sof_dev *sdev
 		link_mask |= BIT(peripherals->array[i]->bus->link_id);
 
 	link_num = hweight32(link_mask);
-	links = devm_kcalloc(sdev->dev, link_num, sizeof(*links), GFP_KERNEL);
+	/* An empty adr_link is needed to terminate the adr_link loop */
+	links = devm_kcalloc(sdev->dev, link_num + 1, sizeof(*links), GFP_KERNEL);
 	if (!links)
 		return NULL;
 
diff --git a/tools/accounting/getdelays.c b/tools/accounting/getdelays.c
index 368a622ca027..caa5fe9dd573 100644
--- a/tools/accounting/getdelays.c
+++ b/tools/accounting/getdelays.c
@@ -241,13 +241,7 @@ static const char *format_timespec(struct __kernel_timespec *ts)
 	if (localtime_r(&time_sec, &tm_info) == NULL)
 		return "N/A";
 
-	snprintf(buffer, sizeof(buffer), "%04d-%02d-%02dT%02d:%02d:%02d",
-		tm_info.tm_year + 1900,
-		tm_info.tm_mon + 1,
-		tm_info.tm_mday,
-		tm_info.tm_hour,
-		tm_info.tm_min,
-		tm_info.tm_sec);
+	strftime(buffer, sizeof(buffer), "%Y-%m-%dT%H:%M:%S", &tm_info);
 
 	return buffer;
 }
diff --git a/tools/lib/bpf/libbpf.c b/tools/lib/bpf/libbpf.c
index 3a80a018fc7d..83aae7a39d36 100644
--- a/tools/lib/bpf/libbpf.c
+++ b/tools/lib/bpf/libbpf.c
@@ -12280,7 +12280,7 @@ bpf_program__attach_kprobe_multi_opts(const struct bpf_program *prog,
 static int attach_kprobe(const struct bpf_program *prog, long cookie, struct bpf_link **link)
 {
 	DECLARE_LIBBPF_OPTS(bpf_kprobe_opts, opts);
-	unsigned long offset = 0;
+	long offset = 0;
 	const char *func_name;
 	char *func;
 	int n;
@@ -12302,6 +12302,13 @@ static int attach_kprobe(const struct bpf_program *prog, long cookie, struct bpf
 		pr_warn("kprobe name is invalid: %s\n", func_name);
 		return -EINVAL;
 	}
+
+	if (offset < 0) {
+		free(func);
+		pr_warn("kprobe offset must be a non-negative integer: %li\n", offset);
+		return -EINVAL;
+	}
+
 	if (opts.retprobe && offset != 0) {
 		free(func);
 		pr_warn("kretprobes do not support offset specification\n");
diff --git a/tools/perf/builtin-trace.c b/tools/perf/builtin-trace.c
index e58c49d047a2..d22e20a57b70 100644
--- a/tools/perf/builtin-trace.c
+++ b/tools/perf/builtin-trace.c
@@ -969,7 +969,7 @@ static bool syscall_arg__strtoul_btf_enum(char *bf, size_t size, struct syscall_
 	struct btf *btf = arg->trace->btf;
 	struct btf_enum *be = btf_enum(bt);
 
-	for (int i = 0; i < btf_vlen(bt); ++i, ++be) {
+	for (u32 i = 0; i < btf_vlen(bt); ++i, ++be) {
 		const char *name = btf__name_by_offset(btf, be->name_off);
 		int max_len = max(size, strlen(name));
 
diff --git a/tools/perf/util/btf.c b/tools/perf/util/btf.c
index bb163fe87767..50d98f3e83bf 100644
--- a/tools/perf/util/btf.c
+++ b/tools/perf/util/btf.c
@@ -14,7 +14,7 @@ const struct btf_member *__btf_type__find_member_by_name(struct btf *btf,
 {
 	const struct btf_type *t = btf__type_by_id(btf, type_id);
 	const struct btf_member *m;
-	int i;
+	u32 i;
 
 	for (i = 0, m = btf_members(t); i < btf_vlen(t); i++, m++) {
 		const char *current_member_name = btf__name_by_offset(btf, m->name_off);
diff --git a/tools/sched_ext/README.md b/tools/sched_ext/README.md
index 6e282bce453c..0ee5a3d997e5 100644
--- a/tools/sched_ext/README.md
+++ b/tools/sched_ext/README.md
@@ -168,9 +168,9 @@ well on single-socket systems with a unified L3 cache.
 
 Another simple, yet slightly more complex scheduler that provides an example of
 a basic weighted FIFO queuing policy. It also provides examples of some common
-useful BPF features, such as sleepable per-task storage allocation in the
-`ops.prep_enable()` callback, and using the `BPF_MAP_TYPE_QUEUE` map type to
-enqueue tasks. It also illustrates how core-sched support could be implemented.
+useful BPF features, such as arena-backed doubly-linked lists threaded through
+per-task context and `bpf_res_spin_lock` for per-queue synchronization. It also
+illustrates how core-sched support could be implemented.
 
 ## scx_central
 
diff --git a/tools/sched_ext/include/scx/common.bpf.h b/tools/sched_ext/include/scx/common.bpf.h
index 19459dedde41..67b4b179b422 100644
--- a/tools/sched_ext/include/scx/common.bpf.h
+++ b/tools/sched_ext/include/scx/common.bpf.h
@@ -99,6 +99,7 @@ s32 scx_bpf_task_cpu(const struct task_struct *p) __ksym;
 struct rq *scx_bpf_cpu_rq(s32 cpu) __ksym;
 struct rq *scx_bpf_locked_rq(void) __ksym;
 struct task_struct *scx_bpf_cpu_curr(s32 cpu) __ksym __weak;
+struct task_struct *scx_bpf_tid_to_task(u64 tid) __ksym __weak;
 u64 scx_bpf_now(void) __ksym __weak;
 void scx_bpf_events(struct scx_event_stats *events, size_t events__sz) __ksym __weak;
 
@@ -526,6 +527,10 @@ static inline bool is_migration_disabled(const struct task_struct *p)
 void bpf_rcu_read_lock(void) __ksym;
 void bpf_rcu_read_unlock(void) __ksym;
 
+/* resilient qspinlock */
+int bpf_res_spin_lock(struct bpf_res_spin_lock *lock) __ksym __weak;
+void bpf_res_spin_unlock(struct bpf_res_spin_lock *lock) __ksym __weak;
+
 /*
  * Time helpers, most of which are from jiffies.h.
  */
diff --git a/tools/sched_ext/include/scx/compat.bpf.h b/tools/sched_ext/include/scx/compat.bpf.h
index 8977b5a2caa1..2808003eef04 100644
--- a/tools/sched_ext/include/scx/compat.bpf.h
+++ b/tools/sched_ext/include/scx/compat.bpf.h
@@ -423,8 +423,10 @@ static inline void scx_bpf_dsq_reenq(u64 dsq_id, u64 reenq_flags)
 }
 
 /*
- * Define sched_ext_ops. This may be expanded to define multiple variants for
- * backward compatibility. See compat.h::SCX_OPS_LOAD/ATTACH().
+ * Define sched_ext_ops. See compat.h::SCX_OPS_OPEN() for how backward
+ * compatibility is handled (this macro can be expanded to emit multiple
+ * variants for incompatible op changes; SCX_OPS_OPEN() handles purely
+ * additive changes at load time).
  */
 #define SCX_OPS_DEFINE(__name, ...)						\
 	SEC(".struct_ops.link")							\
diff --git a/tools/sched_ext/include/scx/compat.h b/tools/sched_ext/include/scx/compat.h
index 039854c490d5..602f07061ee3 100644
--- a/tools/sched_ext/include/scx/compat.h
+++ b/tools/sched_ext/include/scx/compat.h
@@ -149,10 +149,24 @@ static inline long scx_hotplug_seq(void)
 }
 
 /*
- * struct sched_ext_ops can change over time. If compat.bpf.h::SCX_OPS_DEFINE()
- * is used to define ops and compat.h::SCX_OPS_LOAD/ATTACH() are used to load
- * and attach it, backward compatibility is automatically maintained where
- * reasonable.
+ * Open the sched_ext_ops skeleton.
+ *
+ * struct sched_ext_ops can change over time. Two complementary mechanisms
+ * keep BPF schedulers built against newer headers running on older kernels:
+ *
+ * 1. Load-time fix-up (this macro). For each optional ops callback or field
+ *    added to struct sched_ext_ops, an explicit stanza below probes the
+ *    running kernel's BTF via __COMPAT_struct_has_field() and, if the field
+ *    is missing, clears it in the in-memory struct_ops (with a warning to
+ *    stderr) before load. Handles additive changes - a new stanza must be
+ *    added here for each new optional field.
+ *
+ * 2. Multi-variant struct_ops via compat.bpf.h::SCX_OPS_DEFINE(). That
+ *    macro can be expanded to emit several variants of struct sched_ext_ops,
+ *    and SCX_OPS_LOAD()/ATTACH() can pick the right one based on what the
+ *    kernel supports. Needed when an existing operation has to change
+ *    incompatibly (e.g. a callback signature changes); the load-time
+ *    fix-up above only handles purely additive changes.
  *
  * ec7e3b0463e1 ("implement-ops") in https://github.com/sched-ext/sched_ext is
  * the current minimum required kernel version.
@@ -225,6 +239,7 @@ static inline void __scx_ops_assoc_prog(struct bpf_program *prog,
 }
 #endif
 
+/* See SCX_OPS_OPEN() above for backward-compatibility handling. */
 #define SCX_OPS_LOAD(__skel, __ops_name, __scx_name, __uei_name) ({		\
 	struct bpf_program *__prog;						\
 	UEI_SET_SIZE(__skel, __ops_name, __uei_name);				\
diff --git a/tools/sched_ext/scx_central.bpf.c b/tools/sched_ext/scx_central.bpf.c
index 4efcce099bd5..64dd60b3e922 100644
--- a/tools/sched_ext/scx_central.bpf.c
+++ b/tools/sched_ext/scx_central.bpf.c
@@ -149,10 +149,14 @@ static bool dispatch_to_cpu(s32 cpu)
 		}
 
 		/*
-		 * If we can't run the task at the top, do the dumb thing and
-		 * bounce it to the fallback dsq.
+		 * If we can't run the task at the top for whatever reason,
+		 * bounce it to the fallback dsq. Also check
+		 * is_migration_disabled() explicitly as p->cpus_ptr may not
+		 * reflect the migration-disabled state yet if
+		 * migrate_disable_switch() hasn't run.
 		 */
-		if (!bpf_cpumask_test_cpu(cpu, p->cpus_ptr)) {
+		if (!bpf_cpumask_test_cpu(cpu, p->cpus_ptr) ||
+		    (is_migration_disabled(p) && scx_bpf_task_cpu(p) != cpu)) {
 			__sync_fetch_and_add(&nr_mismatches, 1);
 			scx_bpf_dsq_insert(p, FALLBACK_DSQ_ID, SCX_SLICE_INF, 0);
 			bpf_task_release(p);
diff --git a/tools/sched_ext/scx_cpu0.bpf.c b/tools/sched_ext/scx_cpu0.bpf.c
index 0b1a7ce879b0..909d1be1bfe3 100644
--- a/tools/sched_ext/scx_cpu0.bpf.c
+++ b/tools/sched_ext/scx_cpu0.bpf.c
@@ -18,8 +18,6 @@
 
 char _license[] SEC("license") = "GPL";
 
-const volatile u32 nr_cpus = 32;	/* !0 for veristat, set during init */
-
 UEI_DEFINE(uei);
 
 /*
diff --git a/tools/sched_ext/scx_cpu0.c b/tools/sched_ext/scx_cpu0.c
index a6fba9978b9c..4966e3d4c724 100644
--- a/tools/sched_ext/scx_cpu0.c
+++ b/tools/sched_ext/scx_cpu0.c
@@ -72,8 +72,6 @@ int main(int argc, char **argv)
 	optind = 1;
 	skel = SCX_OPS_OPEN(cpu0_ops, scx_cpu0);
 
-	skel->rodata->nr_cpus = libbpf_num_possible_cpus();
-
 	while ((opt = getopt(argc, argv, "vh")) != -1) {
 		switch (opt) {
 		case 'v':
diff --git a/tools/sched_ext/scx_flatcg.c b/tools/sched_ext/scx_flatcg.c
index d865c381589b..de2bef86d64d 100644
--- a/tools/sched_ext/scx_flatcg.c
+++ b/tools/sched_ext/scx_flatcg.c
@@ -130,7 +130,6 @@ int main(int argc, char **argv)
 	struct scx_flatcg *skel;
 	struct bpf_link *link;
 	struct timespec intv_ts = { .tv_sec = 2, .tv_nsec = 0 };
-	bool dump_cgrps = false;
 	__u64 last_cpu_sum = 0, last_cpu_idle = 0;
 	__u64 last_stats[FCG_NR_STATS] = {};
 	unsigned long seq = 0;
@@ -148,7 +147,7 @@ int main(int argc, char **argv)
 	assert(skel->rodata->nr_cpus > 0);
 	skel->rodata->cgrp_slice_ns = __COMPAT_ENUM_OR_ZERO("scx_public_consts", "SCX_SLICE_DFL");
 
-	while ((opt = getopt(argc, argv, "s:i:dfvh")) != -1) {
+	while ((opt = getopt(argc, argv, "s:i:fvh")) != -1) {
 		double v;
 
 		switch (opt) {
@@ -161,9 +160,6 @@ int main(int argc, char **argv)
 			intv_ts.tv_sec = v;
 			intv_ts.tv_nsec = (v - (float)intv_ts.tv_sec) * 1000000000;
 			break;
-		case 'd':
-			dump_cgrps = true;
-			break;
 		case 'f':
 			skel->rodata->fifo_sched = true;
 			break;
@@ -177,10 +173,10 @@ int main(int argc, char **argv)
 		}
 	}
 
-	printf("slice=%.1lfms intv=%.1lfs dump_cgrps=%d",
+	printf("slice=%.1lfms intv=%.1lfs",
 	       (double)skel->rodata->cgrp_slice_ns / 1000000.0,
-	       (double)intv_ts.tv_sec + (double)intv_ts.tv_nsec / 1000000000.0,
-	       dump_cgrps);
+	       (double)intv_ts.tv_sec + (double)intv_ts.tv_nsec / 1000000000.0);
+
 
 	SCX_OPS_LOAD(skel, flatcg_ops, scx_flatcg, uei);
 	link = SCX_OPS_ATTACH(skel, flatcg_ops, scx_flatcg);
diff --git a/tools/sched_ext/scx_qmap.bpf.c b/tools/sched_ext/scx_qmap.bpf.c
index b68abb9e760b..ba4879031dac 100644
--- a/tools/sched_ext/scx_qmap.bpf.c
+++ b/tools/sched_ext/scx_qmap.bpf.c
@@ -2,15 +2,16 @@
 /*
  * A simple five-level FIFO queue scheduler.
  *
- * There are five FIFOs implemented using BPF_MAP_TYPE_QUEUE. A task gets
- * assigned to one depending on its compound weight. Each CPU round robins
- * through the FIFOs and dispatches more from FIFOs with higher indices - 1 from
- * queue0, 2 from queue1, 4 from queue2 and so on.
+ * There are five FIFOs implemented as arena-backed doubly-linked lists
+ * threaded through per-task context. A task gets assigned to one depending on
+ * its compound weight. Each CPU round robins through the FIFOs and dispatches
+ * more from FIFOs with higher indices - 1 from queue0, 2 from queue1, 4 from
+ * queue2 and so on.
  *
  * This scheduler demonstrates:
  *
- * - BPF-side queueing using PIDs.
- * - Sleepable per-task storage allocation using ops.prep_enable().
+ * - BPF-side queueing using TIDs.
+ * - BPF arena for scheduler state.
  * - Core-sched support.
  *
  * This scheduler is primarily for demonstration and testing of sched_ext
@@ -22,6 +23,8 @@
  */
 #include <scx/common.bpf.h>
 
+#include "scx_qmap.h"
+
 enum consts {
 	ONE_SEC_IN_NS		= 1000000000,
 	ONE_MSEC_IN_NS		= 1000000,
@@ -47,40 +50,46 @@ const volatile s32 disallow_tgid;
 const volatile bool suppress_dump;
 const volatile bool always_enq_immed;
 const volatile u32 immed_stress_nth;
-
-u64 nr_highpri_queued;
-u32 test_error_cnt;
-
-#define MAX_SUB_SCHEDS		8
-u64 sub_sched_cgroup_ids[MAX_SUB_SCHEDS];
+const volatile u32 max_tasks;
 
 UEI_DEFINE(uei);
 
-struct qmap {
-	__uint(type, BPF_MAP_TYPE_QUEUE);
-	__uint(max_entries, 4096);
-	__type(value, u32);
-} queue0 SEC(".maps"),
-  queue1 SEC(".maps"),
-  queue2 SEC(".maps"),
-  queue3 SEC(".maps"),
-  queue4 SEC(".maps"),
-  dump_store SEC(".maps");
-
+/*
+ * All scheduler state - per-cpu context, stats counters, core-sched sequence
+ * numbers, sub-sched cgroup ids - lives in this single BPF arena map. Userspace
+ * reaches it via skel->arena->qa.
+ */
 struct {
-	__uint(type, BPF_MAP_TYPE_ARRAY_OF_MAPS);
-	__uint(max_entries, 5);
-	__type(key, int);
-	__array(values, struct qmap);
-} queue_arr SEC(".maps") = {
-	.values = {
-		[0] = &queue0,
-		[1] = &queue1,
-		[2] = &queue2,
-		[3] = &queue3,
-		[4] = &queue4,
-	},
-};
+	__uint(type, BPF_MAP_TYPE_ARENA);
+	__uint(map_flags, BPF_F_MMAPABLE);
+	__uint(max_entries, 1 << 16);		/* upper bound in pages */
+#if defined(__TARGET_ARCH_arm64) || defined(__aarch64__)
+	__ulong(map_extra, 0x1ull << 32);	/* user/BPF mmap base */
+#else
+	__ulong(map_extra, 0x1ull << 44);
+#endif
+} arena SEC(".maps");
+
+struct qmap_arena __arena qa;
+
+/* Per-queue locks. Each in its own .data section as bpf_res_spin_lock requires. */
+__hidden struct bpf_res_spin_lock qa_q_lock0 SEC(".data.qa_q_lock0");
+__hidden struct bpf_res_spin_lock qa_q_lock1 SEC(".data.qa_q_lock1");
+__hidden struct bpf_res_spin_lock qa_q_lock2 SEC(".data.qa_q_lock2");
+__hidden struct bpf_res_spin_lock qa_q_lock3 SEC(".data.qa_q_lock3");
+__hidden struct bpf_res_spin_lock qa_q_lock4 SEC(".data.qa_q_lock4");
+
+static struct bpf_res_spin_lock *qa_q_lock(s32 qid)
+{
+	switch (qid) {
+	case 0:	return &qa_q_lock0;
+	case 1:	return &qa_q_lock1;
+	case 2:	return &qa_q_lock2;
+	case 3:	return &qa_q_lock3;
+	case 4:	return &qa_q_lock4;
+	default: return NULL;
+	}
+}
 
 /*
  * If enabled, CPU performance target is set according to the queue index
@@ -102,43 +111,55 @@ static const u32 qidx_to_cpuperf_target[] = {
  * task's seq and the associated queue's head seq is called the queue distance
  * and used when comparing two tasks for ordering. See qmap_core_sched_before().
  */
-static u64 core_sched_head_seqs[5];
-static u64 core_sched_tail_seqs[5];
 
-/* Per-task scheduling context */
+/*
+ * Per-task scheduling context. Allocated from the qa.task_ctxs[] slab in
+ * arena. While the task is alive the entry is referenced from task_ctx_stor;
+ * while it's free the entry sits on the free list singly-linked through
+ * @next_free.
+ *
+ * When the task is queued on one of the five priority FIFOs, @q_idx is the
+ * queue index and @q_next/@q_prev link it in the queue's doubly-linked list.
+ * @q_idx is -1 when the task isn't on any queue.
+ */
 struct task_ctx {
-	bool	force_local;	/* Dispatch directly to local_dsq */
-	bool	highpri;
-	u64	core_sched_seq;
+	struct task_ctx __arena	*next_free;	/* only valid on free list */
+	struct task_ctx __arena	*q_next;	/* queue link, NULL if tail */
+	struct task_ctx __arena	*q_prev;	/* queue link, NULL if head */
+	struct qmap_fifo __arena *fifo;		/* queue we're on, NULL if not queued */
+	u64			tid;
+	s32			pid;	/* for dump only */
+	bool			force_local;	/* Dispatch directly to local_dsq */
+	bool			highpri;
+	u64			core_sched_seq;
+};
+
+/* All task_ctx pointers are arena pointers. */
+typedef struct task_ctx __arena task_ctx_t;
+
+/* Holds an arena pointer to the task's slab entry. */
+struct task_ctx_stor_val {
+	task_ctx_t		*taskc;
 };
 
 struct {
 	__uint(type, BPF_MAP_TYPE_TASK_STORAGE);
 	__uint(map_flags, BPF_F_NO_PREALLOC);
 	__type(key, int);
-	__type(value, struct task_ctx);
+	__type(value, struct task_ctx_stor_val);
 } task_ctx_stor SEC(".maps");
 
-struct cpu_ctx {
-	u64	dsp_idx;	/* dispatch index */
-	u64	dsp_cnt;	/* remaining count */
-	u32	avg_weight;
-	u32	cpuperf_target;
-};
-
-struct {
-	__uint(type, BPF_MAP_TYPE_PERCPU_ARRAY);
-	__uint(max_entries, 1);
-	__type(key, u32);
-	__type(value, struct cpu_ctx);
-} cpu_ctx_stor SEC(".maps");
+/* Protects the task_ctx slab free list. */
+__hidden struct bpf_res_spin_lock qa_task_lock SEC(".data.qa_task_lock");
 
-/* Statistics */
-u64 nr_enqueued, nr_dispatched, nr_reenqueued, nr_reenqueued_cpu0, nr_dequeued, nr_ddsp_from_enq;
-u64 nr_core_sched_execed;
-u64 nr_expedited_local, nr_expedited_remote, nr_expedited_lost, nr_expedited_from_timer;
-u32 cpuperf_min, cpuperf_avg, cpuperf_max;
-u32 cpuperf_target_min, cpuperf_target_avg, cpuperf_target_max;
+static int qmap_spin_lock(struct bpf_res_spin_lock *lock)
+{
+	if (bpf_res_spin_lock(lock)) {
+		scx_bpf_error("res_spin_lock failed");
+		return -EBUSY;
+	}
+	return 0;
+}
 
 static s32 pick_direct_dispatch_cpu(struct task_struct *p, s32 prev_cpu)
 {
@@ -157,25 +178,110 @@ static s32 pick_direct_dispatch_cpu(struct task_struct *p, s32 prev_cpu)
 	return -1;
 }
 
-static struct task_ctx *lookup_task_ctx(struct task_struct *p)
+/*
+ * Force a reference to the arena map. The verifier associates an arena with
+ * a program by finding an LD_IMM64 instruction that loads the arena's BPF
+ * map; programs that only use arena pointers returned from task-local
+ * storage (like qmap_select_cpu) never reference @arena directly. Without
+ * this, the verifier rejects addr_space_cast with "addr_space_cast insn
+ * can only be used in a program that has an associated arena".
+ */
+#define QMAP_TOUCH_ARENA() do { asm volatile("" :: "r"(&arena)); } while (0)
+
+static task_ctx_t *lookup_task_ctx(struct task_struct *p)
 {
-	struct task_ctx *tctx;
+	struct task_ctx_stor_val *v;
 
-	if (!(tctx = bpf_task_storage_get(&task_ctx_stor, p, 0, 0))) {
-		scx_bpf_error("task_ctx lookup failed");
+	QMAP_TOUCH_ARENA();
+
+	v = bpf_task_storage_get(&task_ctx_stor, p, 0, 0);
+	if (!v || !v->taskc)
 		return NULL;
+	return v->taskc;
+}
+
+/* Append @taskc to the tail of @fifo. Must not already be queued. */
+static void qmap_fifo_enqueue(struct qmap_fifo __arena *fifo, task_ctx_t *taskc)
+{
+	struct bpf_res_spin_lock *lock = qa_q_lock(fifo->idx);
+
+	if (!lock || qmap_spin_lock(lock))
+		return;
+	taskc->fifo = fifo;
+	taskc->q_next = NULL;
+	taskc->q_prev = fifo->tail;
+	if (fifo->tail)
+		fifo->tail->q_next = taskc;
+	else
+		fifo->head = taskc;
+	fifo->tail = taskc;
+	bpf_res_spin_unlock(lock);
+}
+
+/* Pop the head of @fifo. Returns NULL if empty. */
+static task_ctx_t *qmap_fifo_pop(struct qmap_fifo __arena *fifo)
+{
+	struct bpf_res_spin_lock *lock = qa_q_lock(fifo->idx);
+	task_ctx_t *taskc;
+
+	if (!lock || qmap_spin_lock(lock))
+		return NULL;
+	taskc = fifo->head;
+	if (taskc) {
+		fifo->head = taskc->q_next;
+		if (taskc->q_next)
+			taskc->q_next->q_prev = NULL;
+		else
+			fifo->tail = NULL;
+		taskc->q_next = NULL;
+		taskc->q_prev = NULL;
+		taskc->fifo = NULL;
+	}
+	bpf_res_spin_unlock(lock);
+	return taskc;
+}
+
+/* Remove @taskc from its fifo. No-op if not queued. */
+static void qmap_fifo_remove(task_ctx_t *taskc)
+{
+	struct qmap_fifo __arena *fifo = taskc->fifo;
+	struct bpf_res_spin_lock *lock;
+
+	if (!fifo)
+		return;
+
+	lock = qa_q_lock(fifo->idx);
+	if (!lock || qmap_spin_lock(lock))
+		return;
+
+	/* Re-check under lock — a concurrent pop may have cleared fifo. */
+	if (taskc->fifo != fifo) {
+		bpf_res_spin_unlock(lock);
+		return;
 	}
-	return tctx;
+
+	if (taskc->q_next)
+		taskc->q_next->q_prev = taskc->q_prev;
+	else
+		fifo->tail = taskc->q_prev;
+	if (taskc->q_prev)
+		taskc->q_prev->q_next = taskc->q_next;
+	else
+		fifo->head = taskc->q_next;
+	taskc->q_next = NULL;
+	taskc->q_prev = NULL;
+	taskc->fifo = NULL;
+	bpf_res_spin_unlock(lock);
 }
 
 s32 BPF_STRUCT_OPS(qmap_select_cpu, struct task_struct *p,
 		   s32 prev_cpu, u64 wake_flags)
 {
-	struct task_ctx *tctx;
+	task_ctx_t *taskc;
 	s32 cpu;
 
-	if (!(tctx = lookup_task_ctx(p)))
-		return -ESRCH;
+	if (!(taskc = lookup_task_ctx(p)))
+		return prev_cpu;
 
 	if (p->scx.weight < 2 && !(p->flags & PF_KTHREAD))
 		return prev_cpu;
@@ -183,7 +289,7 @@ s32 BPF_STRUCT_OPS(qmap_select_cpu, struct task_struct *p,
 	cpu = pick_direct_dispatch_cpu(p, prev_cpu);
 
 	if (cpu >= 0) {
-		tctx->force_local = true;
+		taskc->force_local = true;
 		return cpu;
 	} else {
 		return prev_cpu;
@@ -208,16 +314,14 @@ static int weight_to_idx(u32 weight)
 void BPF_STRUCT_OPS(qmap_enqueue, struct task_struct *p, u64 enq_flags)
 {
 	static u32 user_cnt, kernel_cnt;
-	struct task_ctx *tctx;
-	u32 pid = p->pid;
+	task_ctx_t *taskc;
 	int idx = weight_to_idx(p->scx.weight);
-	void *ring;
 	s32 cpu;
 
 	if (enq_flags & SCX_ENQ_REENQ) {
-		__sync_fetch_and_add(&nr_reenqueued, 1);
+		__sync_fetch_and_add(&qa.nr_reenqueued, 1);
 		if (scx_bpf_task_cpu(p) == 0)
-			__sync_fetch_and_add(&nr_reenqueued_cpu0, 1);
+			__sync_fetch_and_add(&qa.nr_reenqueued_cpu0, 1);
 	}
 
 	if (p->flags & PF_KTHREAD) {
@@ -228,17 +332,17 @@ void BPF_STRUCT_OPS(qmap_enqueue, struct task_struct *p, u64 enq_flags)
 			return;
 	}
 
-	if (test_error_cnt && !--test_error_cnt)
+	if (qa.test_error_cnt && !--qa.test_error_cnt)
 		scx_bpf_error("test triggering error");
 
-	if (!(tctx = lookup_task_ctx(p)))
+	if (!(taskc = lookup_task_ctx(p)))
 		return;
 
 	/*
 	 * All enqueued tasks must have their core_sched_seq updated for correct
 	 * core-sched ordering. Also, take a look at the end of qmap_dispatch().
 	 */
-	tctx->core_sched_seq = core_sched_tail_seqs[idx]++;
+	taskc->core_sched_seq = qa.core_sched_tail_seqs[idx]++;
 
 	/*
 	 * IMMED stress testing: Every immed_stress_nth'th enqueue, dispatch
@@ -249,7 +353,7 @@ void BPF_STRUCT_OPS(qmap_enqueue, struct task_struct *p, u64 enq_flags)
 		static u32 immed_stress_cnt;
 
 		if (!(++immed_stress_cnt % immed_stress_nth)) {
-			tctx->force_local = false;
+			taskc->force_local = false;
 			scx_bpf_dsq_insert(p, SCX_DSQ_LOCAL_ON | scx_bpf_task_cpu(p),
 					   slice_ns, enq_flags);
 			return;
@@ -260,8 +364,8 @@ void BPF_STRUCT_OPS(qmap_enqueue, struct task_struct *p, u64 enq_flags)
 	 * If qmap_select_cpu() is telling us to or this is the last runnable
 	 * task on the CPU, enqueue locally.
 	 */
-	if (tctx->force_local) {
-		tctx->force_local = false;
+	if (taskc->force_local) {
+		taskc->force_local = false;
 		scx_bpf_dsq_insert(p, SCX_DSQ_LOCAL, slice_ns, enq_flags);
 		return;
 	}
@@ -276,7 +380,7 @@ void BPF_STRUCT_OPS(qmap_enqueue, struct task_struct *p, u64 enq_flags)
 	/* if select_cpu() wasn't called, try direct dispatch */
 	if (!__COMPAT_is_enq_cpu_selected(enq_flags) &&
 	    (cpu = pick_direct_dispatch_cpu(p, scx_bpf_task_cpu(p))) >= 0) {
-		__sync_fetch_and_add(&nr_ddsp_from_enq, 1);
+		__sync_fetch_and_add(&qa.nr_ddsp_from_enq, 1);
 		scx_bpf_dsq_insert(p, SCX_DSQ_LOCAL_ON | cpu, slice_ns, enq_flags);
 		return;
 	}
@@ -297,43 +401,39 @@ void BPF_STRUCT_OPS(qmap_enqueue, struct task_struct *p, u64 enq_flags)
 		return;
 	}
 
-	ring = bpf_map_lookup_elem(&queue_arr, &idx);
-	if (!ring) {
-		scx_bpf_error("failed to find ring %d", idx);
-		return;
-	}
-
-	/* Queue on the selected FIFO. If the FIFO overflows, punt to global. */
-	if (bpf_map_push_elem(ring, &pid, 0)) {
-		scx_bpf_dsq_insert(p, SHARED_DSQ, slice_ns, enq_flags);
-		return;
-	}
+	/* Queue on the selected FIFO. */
+	qmap_fifo_enqueue(&qa.fifos[idx], taskc);
 
 	if (highpri_boosting && p->scx.weight >= HIGHPRI_WEIGHT) {
-		tctx->highpri = true;
-		__sync_fetch_and_add(&nr_highpri_queued, 1);
+		taskc->highpri = true;
+		__sync_fetch_and_add(&qa.nr_highpri_queued, 1);
 	}
-	__sync_fetch_and_add(&nr_enqueued, 1);
+	__sync_fetch_and_add(&qa.nr_enqueued, 1);
 }
 
-/*
- * The BPF queue map doesn't support removal and sched_ext can handle spurious
- * dispatches. qmap_dequeue() is only used to collect statistics.
- */
 void BPF_STRUCT_OPS(qmap_dequeue, struct task_struct *p, u64 deq_flags)
 {
-	__sync_fetch_and_add(&nr_dequeued, 1);
+	task_ctx_t *taskc;
+
+	__sync_fetch_and_add(&qa.nr_dequeued, 1);
 	if (deq_flags & SCX_DEQ_CORE_SCHED_EXEC)
-		__sync_fetch_and_add(&nr_core_sched_execed, 1);
+		__sync_fetch_and_add(&qa.nr_core_sched_execed, 1);
+
+	taskc = lookup_task_ctx(p);
+	if (taskc && taskc->fifo) {
+		if (taskc->highpri)
+			__sync_fetch_and_sub(&qa.nr_highpri_queued, 1);
+		qmap_fifo_remove(taskc);
+	}
 }
 
 static void update_core_sched_head_seq(struct task_struct *p)
 {
 	int idx = weight_to_idx(p->scx.weight);
-	struct task_ctx *tctx;
+	task_ctx_t *taskc;
 
-	if ((tctx = lookup_task_ctx(p)))
-		core_sched_head_seqs[idx] = tctx->core_sched_seq;
+	if ((taskc = lookup_task_ctx(p)))
+		qa.core_sched_head_seqs[idx] = taskc->core_sched_seq;
 }
 
 /*
@@ -354,12 +454,12 @@ static bool dispatch_highpri(bool from_timer)
 	/* scan SHARED_DSQ and move highpri tasks to HIGHPRI_DSQ */
 	bpf_for_each(scx_dsq, p, SHARED_DSQ, 0) {
 		static u64 highpri_seq;
-		struct task_ctx *tctx;
+		task_ctx_t *taskc;
 
-		if (!(tctx = lookup_task_ctx(p)))
+		if (!(taskc = lookup_task_ctx(p)))
 			return false;
 
-		if (tctx->highpri) {
+		if (taskc->highpri) {
 			/* exercise the set_*() and vtime interface too */
 			scx_bpf_dsq_move_set_slice(BPF_FOR_EACH_ITER, slice_ns * 2);
 			scx_bpf_dsq_move_set_vtime(BPF_FOR_EACH_ITER, highpri_seq++);
@@ -384,14 +484,14 @@ static bool dispatch_highpri(bool from_timer)
 				     SCX_ENQ_PREEMPT)) {
 			if (cpu == this_cpu) {
 				dispatched = true;
-				__sync_fetch_and_add(&nr_expedited_local, 1);
+				__sync_fetch_and_add(&qa.nr_expedited_local, 1);
 			} else {
-				__sync_fetch_and_add(&nr_expedited_remote, 1);
+				__sync_fetch_and_add(&qa.nr_expedited_remote, 1);
 			}
 			if (from_timer)
-				__sync_fetch_and_add(&nr_expedited_from_timer, 1);
+				__sync_fetch_and_add(&qa.nr_expedited_from_timer, 1);
 		} else {
-			__sync_fetch_and_add(&nr_expedited_lost, 1);
+			__sync_fetch_and_add(&qa.nr_expedited_lost, 1);
 		}
 
 		if (dispatched)
@@ -404,19 +504,18 @@ static bool dispatch_highpri(bool from_timer)
 void BPF_STRUCT_OPS(qmap_dispatch, s32 cpu, struct task_struct *prev)
 {
 	struct task_struct *p;
-	struct cpu_ctx *cpuc;
-	struct task_ctx *tctx;
-	u32 zero = 0, batch = dsp_batch ?: 1;
-	void *fifo;
-	s32 i, pid;
+	struct cpu_ctx __arena *cpuc;
+	task_ctx_t *taskc;
+	u32 batch = dsp_batch ?: 1;
+	s32 i;
 
 	if (dispatch_highpri(false))
 		return;
 
-	if (!nr_highpri_queued && scx_bpf_dsq_move_to_local(SHARED_DSQ, 0))
+	if (!qa.nr_highpri_queued && scx_bpf_dsq_move_to_local(SHARED_DSQ, 0))
 		return;
 
-	if (dsp_inf_loop_after && nr_dispatched > dsp_inf_loop_after) {
+	if (dsp_inf_loop_after && qa.nr_dispatched > dsp_inf_loop_after) {
 		/*
 		 * PID 2 should be kthreadd which should mostly be idle and off
 		 * the scheduler. Let's keep dispatching it to force the kernel
@@ -430,10 +529,7 @@ void BPF_STRUCT_OPS(qmap_dispatch, s32 cpu, struct task_struct *prev)
 		}
 	}
 
-	if (!(cpuc = bpf_map_lookup_elem(&cpu_ctx_stor, &zero))) {
-		scx_bpf_error("failed to look up cpu_ctx");
-		return;
-	}
+	cpuc = &qa.cpu_ctxs[bpf_get_smp_processor_id()];
 
 	for (i = 0; i < 5; i++) {
 		/* Advance the dispatch cursor and pick the fifo. */
@@ -442,33 +538,23 @@ void BPF_STRUCT_OPS(qmap_dispatch, s32 cpu, struct task_struct *prev)
 			cpuc->dsp_cnt = 1 << cpuc->dsp_idx;
 		}
 
-		fifo = bpf_map_lookup_elem(&queue_arr, &cpuc->dsp_idx);
-		if (!fifo) {
-			scx_bpf_error("failed to find ring %llu", cpuc->dsp_idx);
-			return;
-		}
-
 		/* Dispatch or advance. */
 		bpf_repeat(BPF_MAX_LOOPS) {
-			struct task_ctx *tctx;
+			task_ctx_t *taskc;
 
-			if (bpf_map_pop_elem(fifo, &pid))
+			taskc = qmap_fifo_pop(&qa.fifos[cpuc->dsp_idx]);
+			if (!taskc)
 				break;
 
-			p = bpf_task_from_pid(pid);
+			p = scx_bpf_tid_to_task(taskc->tid);
 			if (!p)
 				continue;
 
-			if (!(tctx = lookup_task_ctx(p))) {
-				bpf_task_release(p);
-				return;
-			}
-
-			if (tctx->highpri)
-				__sync_fetch_and_sub(&nr_highpri_queued, 1);
+			if (taskc->highpri)
+				__sync_fetch_and_sub(&qa.nr_highpri_queued, 1);
 
 			update_core_sched_head_seq(p);
-			__sync_fetch_and_add(&nr_dispatched, 1);
+			__sync_fetch_and_add(&qa.nr_dispatched, 1);
 
 			scx_bpf_dsq_insert(p, SHARED_DSQ, slice_ns, 0);
 
@@ -511,8 +597,6 @@ void BPF_STRUCT_OPS(qmap_dispatch, s32 cpu, struct task_struct *prev)
 			if (!bpf_cpumask_test_cpu(cpu, p->cpus_ptr))
 				scx_bpf_kick_cpu(scx_bpf_task_cpu(p), 0);
 
-			bpf_task_release(p);
-
 			batch--;
 			cpuc->dsp_cnt--;
 			if (!batch || !scx_bpf_dispatch_nr_slots()) {
@@ -529,8 +613,8 @@ void BPF_STRUCT_OPS(qmap_dispatch, s32 cpu, struct task_struct *prev)
 	}
 
 	for (i = 0; i < MAX_SUB_SCHEDS; i++) {
-		if (sub_sched_cgroup_ids[i] &&
-		    scx_bpf_sub_dispatch(sub_sched_cgroup_ids[i]))
+		if (qa.sub_sched_cgroup_ids[i] &&
+		    scx_bpf_sub_dispatch(qa.sub_sched_cgroup_ids[i]))
 			return;
 	}
 
@@ -539,28 +623,20 @@ void BPF_STRUCT_OPS(qmap_dispatch, s32 cpu, struct task_struct *prev)
 	 * if the task were enqueued and dispatched immediately.
 	 */
 	if (prev) {
-		tctx = bpf_task_storage_get(&task_ctx_stor, prev, 0, 0);
-		if (!tctx) {
-			scx_bpf_error("task_ctx lookup failed");
+		taskc = lookup_task_ctx(prev);
+		if (!taskc)
 			return;
-		}
 
-		tctx->core_sched_seq =
-			core_sched_tail_seqs[weight_to_idx(prev->scx.weight)]++;
+		taskc->core_sched_seq =
+			qa.core_sched_tail_seqs[weight_to_idx(prev->scx.weight)]++;
 	}
 }
 
 void BPF_STRUCT_OPS(qmap_tick, struct task_struct *p)
 {
-	struct cpu_ctx *cpuc;
-	u32 zero = 0;
+	struct cpu_ctx __arena *cpuc = &qa.cpu_ctxs[bpf_get_smp_processor_id()];
 	int idx;
 
-	if (!(cpuc = bpf_map_lookup_elem(&cpu_ctx_stor, &zero))) {
-		scx_bpf_error("failed to look up cpu_ctx");
-		return;
-	}
-
 	/*
 	 * Use the running avg of weights to select the target cpuperf level.
 	 * This is a demonstration of the cpuperf feature rather than a
@@ -580,16 +656,14 @@ void BPF_STRUCT_OPS(qmap_tick, struct task_struct *p)
 static s64 task_qdist(struct task_struct *p)
 {
 	int idx = weight_to_idx(p->scx.weight);
-	struct task_ctx *tctx;
+	task_ctx_t *taskc;
 	s64 qdist;
 
-	tctx = bpf_task_storage_get(&task_ctx_stor, p, 0, 0);
-	if (!tctx) {
-		scx_bpf_error("task_ctx lookup failed");
+	taskc = lookup_task_ctx(p);
+	if (!taskc)
 		return 0;
-	}
 
-	qdist = tctx->core_sched_seq - core_sched_head_seqs[idx];
+	qdist = taskc->core_sched_seq - qa.core_sched_head_seqs[idx];
 
 	/*
 	 * As queue index increments, the priority doubles. The queue w/ index 3
@@ -622,70 +696,106 @@ bool BPF_STRUCT_OPS(qmap_core_sched_before,
  * tasks when a higher-priority scheduling class takes the CPU.
  */
 
-s32 BPF_STRUCT_OPS(qmap_init_task, struct task_struct *p,
-		   struct scx_init_task_args *args)
+s32 BPF_STRUCT_OPS_SLEEPABLE(qmap_init_task, struct task_struct *p,
+			     struct scx_init_task_args *args)
 {
+	struct task_ctx_stor_val *v;
+	task_ctx_t *taskc;
+
 	if (p->tgid == disallow_tgid)
 		p->scx.disallow = true;
 
-	/*
-	 * @p is new. Let's ensure that its task_ctx is available. We can sleep
-	 * in this function and the following will automatically use GFP_KERNEL.
-	 */
-	if (bpf_task_storage_get(&task_ctx_stor, p, 0,
-				 BPF_LOCAL_STORAGE_GET_F_CREATE))
-		return 0;
-	else
+	/* pop a slab entry off the free list */
+	if (qmap_spin_lock(&qa_task_lock))
+		return -EBUSY;
+	taskc = qa.task_free_head;
+	if (taskc)
+		qa.task_free_head = taskc->next_free;
+	bpf_res_spin_unlock(&qa_task_lock);
+	if (!taskc) {
+		scx_bpf_error("task_ctx slab exhausted (max_tasks=%u)", max_tasks);
+		return -ENOMEM;
+	}
+
+	taskc->next_free = NULL;
+	taskc->q_next = NULL;
+	taskc->q_prev = NULL;
+	taskc->fifo = NULL;
+	taskc->tid = p->scx.tid;
+	taskc->pid = p->pid;
+	taskc->force_local = false;
+	taskc->highpri = false;
+	taskc->core_sched_seq = 0;
+
+	v = bpf_task_storage_get(&task_ctx_stor, p, NULL,
+				 BPF_LOCAL_STORAGE_GET_F_CREATE);
+	if (!v) {
+		/* push back to the free list */
+		if (!qmap_spin_lock(&qa_task_lock)) {
+			taskc->next_free = qa.task_free_head;
+			qa.task_free_head = taskc;
+			bpf_res_spin_unlock(&qa_task_lock);
+		}
 		return -ENOMEM;
+	}
+	v->taskc = taskc;
+	return 0;
 }
 
-void BPF_STRUCT_OPS(qmap_dump, struct scx_dump_ctx *dctx)
+void BPF_STRUCT_OPS(qmap_exit_task, struct task_struct *p,
+		    struct scx_exit_task_args *args)
 {
-	s32 i, pid;
+	struct task_ctx_stor_val *v;
+	task_ctx_t *taskc;
 
-	if (suppress_dump)
+	v = bpf_task_storage_get(&task_ctx_stor, p, NULL, 0);
+	if (!v || !v->taskc)
 		return;
+	taskc = v->taskc;
+	v->taskc = NULL;
 
-	bpf_for(i, 0, 5) {
-		void *fifo;
+	if (qmap_spin_lock(&qa_task_lock))
+		return;
+	taskc->next_free = qa.task_free_head;
+	qa.task_free_head = taskc;
+	bpf_res_spin_unlock(&qa_task_lock);
+}
 
-		if (!(fifo = bpf_map_lookup_elem(&queue_arr, &i)))
-			return;
+void BPF_STRUCT_OPS(qmap_dump, struct scx_dump_ctx *dctx)
+{
+	task_ctx_t *taskc;
+	s32 i;
 
-		scx_bpf_dump("QMAP FIFO[%d]:", i);
+	QMAP_TOUCH_ARENA();
 
-		/*
-		 * Dump can be invoked anytime and there is no way to iterate in
-		 * a non-destructive way. Pop and store in dump_store and then
-		 * restore afterwards. If racing against new enqueues, ordering
-		 * can get mixed up.
-		 */
-		bpf_repeat(4096) {
-			if (bpf_map_pop_elem(fifo, &pid))
-				break;
-			bpf_map_push_elem(&dump_store, &pid, 0);
-			scx_bpf_dump(" %d", pid);
-		}
+	if (suppress_dump)
+		return;
 
+	/*
+	 * Walk the queue lists without locking - kfunc calls (scx_bpf_dump)
+	 * aren't in the verifier's kfunc_spin_allowed() list so we can't hold
+	 * a lock and dump. Best-effort; racing may print stale tids but the
+	 * walk is bounded by bpf_repeat() so it always terminates.
+	 */
+	bpf_for(i, 0, 5) {
+		scx_bpf_dump("QMAP FIFO[%d]:", i);
+		taskc = qa.fifos[i].head;
 		bpf_repeat(4096) {
-			if (bpf_map_pop_elem(&dump_store, &pid))
+			if (!taskc)
 				break;
-			bpf_map_push_elem(fifo, &pid, 0);
+			scx_bpf_dump(" %d:%llu", taskc->pid, taskc->tid);
+			taskc = taskc->q_next;
 		}
-
 		scx_bpf_dump("\n");
 	}
 }
 
 void BPF_STRUCT_OPS(qmap_dump_cpu, struct scx_dump_ctx *dctx, s32 cpu, bool idle)
 {
-	u32 zero = 0;
-	struct cpu_ctx *cpuc;
+	struct cpu_ctx __arena *cpuc = &qa.cpu_ctxs[cpu];
 
 	if (suppress_dump || idle)
 		return;
-	if (!(cpuc = bpf_map_lookup_percpu_elem(&cpu_ctx_stor, &zero, cpu)))
-		return;
 
 	scx_bpf_dump("QMAP: dsp_idx=%llu dsp_cnt=%llu avg_weight=%u cpuperf_target=%u",
 		     cpuc->dsp_idx, cpuc->dsp_cnt, cpuc->avg_weight,
@@ -694,12 +804,17 @@ void BPF_STRUCT_OPS(qmap_dump_cpu, struct scx_dump_ctx *dctx, s32 cpu, bool idle
 
 void BPF_STRUCT_OPS(qmap_dump_task, struct scx_dump_ctx *dctx, struct task_struct *p)
 {
-	struct task_ctx *taskc;
+	struct task_ctx_stor_val *v;
+	task_ctx_t *taskc;
+
+	QMAP_TOUCH_ARENA();
 
 	if (suppress_dump)
 		return;
-	if (!(taskc = bpf_task_storage_get(&task_ctx_stor, p, 0, 0)))
+	v = bpf_task_storage_get(&task_ctx_stor, p, NULL, 0);
+	if (!v || !v->taskc)
 		return;
+	taskc = v->taskc;
 
 	scx_bpf_dump("QMAP: force_local=%d core_sched_seq=%llu",
 		     taskc->force_local, taskc->core_sched_seq);
@@ -802,7 +917,7 @@ struct {
  */
 static void monitor_cpuperf(void)
 {
-	u32 zero = 0, nr_cpu_ids;
+	u32 nr_cpu_ids;
 	u64 cap_sum = 0, cur_sum = 0, cur_min = SCX_CPUPERF_ONE, cur_max = 0;
 	u64 target_sum = 0, target_min = SCX_CPUPERF_ONE, target_max = 0;
 	const struct cpumask *online;
@@ -812,7 +927,7 @@ static void monitor_cpuperf(void)
 	online = scx_bpf_get_online_cpumask();
 
 	bpf_for(i, 0, nr_cpu_ids) {
-		struct cpu_ctx *cpuc;
+		struct cpu_ctx __arena *cpuc = &qa.cpu_ctxs[i];
 		u32 cap, cur;
 
 		if (!bpf_cpumask_test_cpu(i, online))
@@ -834,11 +949,6 @@ static void monitor_cpuperf(void)
 		cur_sum += cur * cap / SCX_CPUPERF_ONE;
 		cap_sum += cap;
 
-		if (!(cpuc = bpf_map_lookup_percpu_elem(&cpu_ctx_stor, &zero, i))) {
-			scx_bpf_error("failed to look up cpu_ctx");
-			goto out;
-		}
-
 		/* collect target */
 		cur = cpuc->cpuperf_target;
 		target_sum += cur;
@@ -846,14 +956,14 @@ static void monitor_cpuperf(void)
 		target_max = cur > target_max ? cur : target_max;
 	}
 
-	cpuperf_min = cur_min;
-	cpuperf_avg = cur_sum * SCX_CPUPERF_ONE / cap_sum;
-	cpuperf_max = cur_max;
+	qa.cpuperf_min = cur_min;
+	qa.cpuperf_avg = cur_sum * SCX_CPUPERF_ONE / cap_sum;
+	qa.cpuperf_max = cur_max;
+
+	qa.cpuperf_target_min = target_min;
+	qa.cpuperf_target_avg = target_sum / nr_online_cpus;
+	qa.cpuperf_target_max = target_max;
 
-	cpuperf_target_min = target_min;
-	cpuperf_target_avg = target_sum / nr_online_cpus;
-	cpuperf_target_max = target_max;
-out:
 	scx_bpf_put_cpumask(online);
 }
 
@@ -939,10 +1049,35 @@ static int lowpri_timerfn(void *map, int *key, struct bpf_timer *timer)
 
 s32 BPF_STRUCT_OPS_SLEEPABLE(qmap_init)
 {
-	u32 key = 0;
+	task_ctx_t *slab;
+	u32 nr_pages, key = 0, i;
 	struct bpf_timer *timer;
 	s32 ret;
 
+	/*
+	 * Allocate the task_ctx slab in arena and thread the entire slab onto
+	 * the free list. max_tasks is set by userspace before load.
+	 */
+	if (!max_tasks) {
+		scx_bpf_error("max_tasks must be > 0");
+		return -EINVAL;
+	}
+
+	nr_pages = (max_tasks * sizeof(struct task_ctx) + PAGE_SIZE - 1) / PAGE_SIZE;
+	slab = bpf_arena_alloc_pages(&arena, NULL, nr_pages, NUMA_NO_NODE, 0);
+	if (!slab) {
+		scx_bpf_error("failed to allocate task_ctx slab");
+		return -ENOMEM;
+	}
+	qa.task_ctxs = slab;
+
+	bpf_for(i, 0, 5)
+		qa.fifos[i].idx = i;
+
+	bpf_for(i, 0, max_tasks)
+		slab[i].next_free = (i + 1 < max_tasks) ? &slab[i + 1] : NULL;
+	qa.task_free_head = &slab[0];
+
 	if (print_msgs && !sub_cgroup_id)
 		print_cpus();
 
@@ -996,8 +1131,8 @@ s32 BPF_STRUCT_OPS(qmap_sub_attach, struct scx_sub_attach_args *args)
 	s32 i;
 
 	for (i = 0; i < MAX_SUB_SCHEDS; i++) {
-		if (!sub_sched_cgroup_ids[i]) {
-			sub_sched_cgroup_ids[i] = args->ops->sub_cgroup_id;
+		if (!qa.sub_sched_cgroup_ids[i]) {
+			qa.sub_sched_cgroup_ids[i] = args->ops->sub_cgroup_id;
 			bpf_printk("attaching sub-sched[%d] on %s",
 				   i, args->cgroup_path);
 			return 0;
@@ -1012,8 +1147,8 @@ void BPF_STRUCT_OPS(qmap_sub_detach, struct scx_sub_detach_args *args)
 	s32 i;
 
 	for (i = 0; i < MAX_SUB_SCHEDS; i++) {
-		if (sub_sched_cgroup_ids[i] == args->ops->sub_cgroup_id) {
-			sub_sched_cgroup_ids[i] = 0;
+		if (qa.sub_sched_cgroup_ids[i] == args->ops->sub_cgroup_id) {
+			qa.sub_sched_cgroup_ids[i] = 0;
 			bpf_printk("detaching sub-sched[%d] on %s",
 				   i, args->cgroup_path);
 			break;
@@ -1022,6 +1157,7 @@ void BPF_STRUCT_OPS(qmap_sub_detach, struct scx_sub_detach_args *args)
 }
 
 SCX_OPS_DEFINE(qmap_ops,
+	       .flags			= SCX_OPS_ENQ_EXITING | SCX_OPS_TID_TO_TASK,
 	       .select_cpu		= (void *)qmap_select_cpu,
 	       .enqueue			= (void *)qmap_enqueue,
 	       .dequeue			= (void *)qmap_dequeue,
@@ -1029,6 +1165,7 @@ SCX_OPS_DEFINE(qmap_ops,
 	       .tick			= (void *)qmap_tick,
 	       .core_sched_before	= (void *)qmap_core_sched_before,
 	       .init_task		= (void *)qmap_init_task,
+	       .exit_task		= (void *)qmap_exit_task,
 	       .dump			= (void *)qmap_dump,
 	       .dump_cpu		= (void *)qmap_dump_cpu,
 	       .dump_task		= (void *)qmap_dump_task,
diff --git a/tools/sched_ext/scx_qmap.c b/tools/sched_ext/scx_qmap.c
index e7c89a2bc3d8..725c4880058d 100644
--- a/tools/sched_ext/scx_qmap.c
+++ b/tools/sched_ext/scx_qmap.c
@@ -10,9 +10,11 @@
 #include <inttypes.h>
 #include <signal.h>
 #include <libgen.h>
+#include <sys/mman.h>
 #include <sys/stat.h>
 #include <bpf/bpf.h>
 #include <scx/common.h>
+#include "scx_qmap.h"
 #include "scx_qmap.bpf.skel.h"
 
 const char help_fmt[] =
@@ -21,17 +23,20 @@ const char help_fmt[] =
 "See the top-level comment in .bpf.c for more details.\n"
 "\n"
 "Usage: %s [-s SLICE_US] [-e COUNT] [-t COUNT] [-T COUNT] [-l COUNT] [-b COUNT]\n"
-"       [-P] [-M] [-H] [-d PID] [-D LEN] [-S] [-p] [-I] [-F COUNT] [-v]\n"
+"       [-N COUNT] [-P] [-M] [-H] [-c CG_PATH] [-d PID] [-D LEN] [-S] [-p] [-I]\n"
+"       [-F COUNT] [-v]\n"
 "\n"
 "  -s SLICE_US   Override slice duration\n"
 "  -e COUNT      Trigger scx_bpf_error() after COUNT enqueues\n"
 "  -t COUNT      Stall every COUNT'th user thread\n"
 "  -T COUNT      Stall every COUNT'th kernel thread\n"
+"  -N COUNT      Size of the task_ctx arena slab (default 16384)\n"
 "  -l COUNT      Trigger dispatch infinite looping after COUNT dispatches\n"
 "  -b COUNT      Dispatch upto COUNT tasks together\n"
 "  -P            Print out DSQ content and event counters to trace_pipe every second\n"
 "  -M            Print out debug messages to trace_pipe\n"
 "  -H            Boost nice -20 tasks in SHARED_DSQ, use with -b\n"
+"  -c CG_PATH    Cgroup path to attach as sub-scheduler, must run parent scheduler first\n"
 "  -d PID        Disallow a process from switching into SCHED_EXT (-1 for self)\n"
 "  -D LEN        Set scx_exit_info.dump buffer length\n"
 "  -S            Suppress qmap-specific debug dump\n"
@@ -60,6 +65,8 @@ int main(int argc, char **argv)
 {
 	struct scx_qmap *skel;
 	struct bpf_link *link;
+	struct qmap_arena *qa;
+	__u32 test_error_cnt = 0;
 	int opt;
 
 	libbpf_set_print(libbpf_print_fn);
@@ -69,14 +76,15 @@ int main(int argc, char **argv)
 	skel = SCX_OPS_OPEN(qmap_ops, scx_qmap);
 
 	skel->rodata->slice_ns = __COMPAT_ENUM_OR_ZERO("scx_public_consts", "SCX_SLICE_DFL");
+	skel->rodata->max_tasks = 16384;
 
-	while ((opt = getopt(argc, argv, "s:e:t:T:l:b:PMHc:d:D:SpIF:vh")) != -1) {
+	while ((opt = getopt(argc, argv, "s:e:t:T:l:b:N:PMHc:d:D:SpIF:vh")) != -1) {
 		switch (opt) {
 		case 's':
 			skel->rodata->slice_ns = strtoull(optarg, NULL, 0) * 1000;
 			break;
 		case 'e':
-			skel->bss->test_error_cnt = strtoul(optarg, NULL, 0);
+			test_error_cnt = strtoul(optarg, NULL, 0);
 			break;
 		case 't':
 			skel->rodata->stall_user_nth = strtoul(optarg, NULL, 0);
@@ -90,6 +98,9 @@ int main(int argc, char **argv)
 		case 'b':
 			skel->rodata->dsp_batch = strtoul(optarg, NULL, 0);
 			break;
+		case 'N':
+			skel->rodata->max_tasks = strtoul(optarg, NULL, 0);
+			break;
 		case 'P':
 			skel->rodata->print_dsqs_and_events = true;
 			break;
@@ -142,29 +153,32 @@ int main(int argc, char **argv)
 	SCX_OPS_LOAD(skel, qmap_ops, scx_qmap, uei);
 	link = SCX_OPS_ATTACH(skel, qmap_ops, scx_qmap);
 
+	qa = &skel->arena->qa;
+	qa->test_error_cnt = test_error_cnt;
+
 	while (!exit_req && !UEI_EXITED(skel, uei)) {
-		long nr_enqueued = skel->bss->nr_enqueued;
-		long nr_dispatched = skel->bss->nr_dispatched;
+		long nr_enqueued = qa->nr_enqueued;
+		long nr_dispatched = qa->nr_dispatched;
 
-		printf("stats  : enq=%lu dsp=%lu delta=%ld reenq/cpu0=%"PRIu64"/%"PRIu64" deq=%"PRIu64" core=%"PRIu64" enq_ddsp=%"PRIu64"\n",
+		printf("stats  : enq=%lu dsp=%lu delta=%ld reenq/cpu0=%llu/%llu deq=%llu core=%llu enq_ddsp=%llu\n",
 		       nr_enqueued, nr_dispatched, nr_enqueued - nr_dispatched,
-		       skel->bss->nr_reenqueued, skel->bss->nr_reenqueued_cpu0,
-		       skel->bss->nr_dequeued,
-		       skel->bss->nr_core_sched_execed,
-		       skel->bss->nr_ddsp_from_enq);
-		printf("         exp_local=%"PRIu64" exp_remote=%"PRIu64" exp_timer=%"PRIu64" exp_lost=%"PRIu64"\n",
-		       skel->bss->nr_expedited_local,
-		       skel->bss->nr_expedited_remote,
-		       skel->bss->nr_expedited_from_timer,
-		       skel->bss->nr_expedited_lost);
+		       qa->nr_reenqueued, qa->nr_reenqueued_cpu0,
+		       qa->nr_dequeued,
+		       qa->nr_core_sched_execed,
+		       qa->nr_ddsp_from_enq);
+		printf("         exp_local=%llu exp_remote=%llu exp_timer=%llu exp_lost=%llu\n",
+		       qa->nr_expedited_local,
+		       qa->nr_expedited_remote,
+		       qa->nr_expedited_from_timer,
+		       qa->nr_expedited_lost);
 		if (__COMPAT_has_ksym("scx_bpf_cpuperf_cur"))
 			printf("cpuperf: cur min/avg/max=%u/%u/%u target min/avg/max=%u/%u/%u\n",
-			       skel->bss->cpuperf_min,
-			       skel->bss->cpuperf_avg,
-			       skel->bss->cpuperf_max,
-			       skel->bss->cpuperf_target_min,
-			       skel->bss->cpuperf_target_avg,
-			       skel->bss->cpuperf_target_max);
+			       qa->cpuperf_min,
+			       qa->cpuperf_avg,
+			       qa->cpuperf_max,
+			       qa->cpuperf_target_min,
+			       qa->cpuperf_target_avg,
+			       qa->cpuperf_target_max);
 		fflush(stdout);
 		sleep(1);
 	}
diff --git a/tools/sched_ext/scx_qmap.h b/tools/sched_ext/scx_qmap.h
new file mode 100644
index 000000000000..9d9af2ad90c6
--- /dev/null
+++ b/tools/sched_ext/scx_qmap.h
@@ -0,0 +1,73 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Shared definitions between scx_qmap.bpf.c and scx_qmap.c.
+ *
+ * The scheduler keeps all state in a single BPF arena map. struct
+ * qmap_arena is the one object that lives at the base of the arena and is
+ * mmap'd into userspace so the loader can read counters directly.
+ *
+ * Copyright (c) 2026 Meta Platforms, Inc. and affiliates.
+ * Copyright (c) 2026 Tejun Heo <tj@kernel.org>
+ */
+#ifndef __SCX_QMAP_H
+#define __SCX_QMAP_H
+
+#ifdef __BPF__
+#include <scx/bpf_arena_common.bpf.h>
+#else
+#include <linux/types.h>
+#include <scx/bpf_arena_common.h>
+#endif
+
+#define MAX_SUB_SCHEDS		8
+
+/*
+ * cpu_ctxs[] is sized to a fixed cap so the layout is shared between BPF and
+ * userspace. Keep this in sync with NR_CPUS used by the BPF side.
+ */
+#define SCX_QMAP_MAX_CPUS	1024
+
+struct cpu_ctx {
+	__u64 dsp_idx;		/* dispatch index */
+	__u64 dsp_cnt;		/* remaining count */
+	__u32 avg_weight;
+	__u32 cpuperf_target;
+};
+
+/* Opaque to userspace; defined in scx_qmap.bpf.c. */
+struct task_ctx;
+
+struct qmap_fifo {
+	struct task_ctx __arena *head;
+	struct task_ctx __arena *tail;
+	__s32 idx;
+};
+
+struct qmap_arena {
+	/* userspace-visible stats */
+	__u64 nr_enqueued, nr_dispatched, nr_reenqueued, nr_reenqueued_cpu0;
+	__u64 nr_dequeued, nr_ddsp_from_enq;
+	__u64 nr_core_sched_execed;
+	__u64 nr_expedited_local, nr_expedited_remote;
+	__u64 nr_expedited_lost, nr_expedited_from_timer;
+	__u64 nr_highpri_queued;
+	__u32 test_error_cnt;
+	__u32 cpuperf_min, cpuperf_avg, cpuperf_max;
+	__u32 cpuperf_target_min, cpuperf_target_avg, cpuperf_target_max;
+
+	/* kernel-side runtime state */
+	__u64 sub_sched_cgroup_ids[MAX_SUB_SCHEDS];
+	__u64 core_sched_head_seqs[5];
+	__u64 core_sched_tail_seqs[5];
+
+	struct cpu_ctx cpu_ctxs[SCX_QMAP_MAX_CPUS];
+
+	/* task_ctx slab; allocated and threaded by qmap_init() */
+	struct task_ctx __arena *task_ctxs;
+	struct task_ctx __arena *task_free_head;
+
+	/* five priority FIFOs, each a doubly-linked list through task_ctx */
+	struct qmap_fifo fifos[5];
+};
+
+#endif /* __SCX_QMAP_H */
diff --git a/tools/testing/radix-tree/maple.c b/tools/testing/radix-tree/maple.c
index feedd5ab7058..0607913a3022 100644
--- a/tools/testing/radix-tree/maple.c
+++ b/tools/testing/radix-tree/maple.c
@@ -2,7 +2,7 @@
 /*
  * maple_tree.c: Userspace testing for maple tree test-suite
  * Copyright (c) 2018-2022 Oracle Corporation
- * Author: Liam R. Howlett <Liam.Howlett@Oracle.com>
+ * Author: Liam R. Howlett <liam@infradead.org>
  *
  * Any tests that require internal knowledge of the tree or threads and other
  * difficult to handle in kernel tests.
diff --git a/tools/testing/selftests/acct/.gitignore b/tools/testing/selftests/acct/.gitignore
index 7e78aac19038..9e9c61c5bfd6 100644
--- a/tools/testing/selftests/acct/.gitignore
+++ b/tools/testing/selftests/acct/.gitignore
@@ -1,3 +1,4 @@
 acct_syscall
+taskstats_fill_stats_tgid
 config
-process_log
\ No newline at end of file
+process_log
diff --git a/tools/testing/selftests/acct/Makefile b/tools/testing/selftests/acct/Makefile
index 7e025099cf65..083cab5ddb72 100644
--- a/tools/testing/selftests/acct/Makefile
+++ b/tools/testing/selftests/acct/Makefile
@@ -1,5 +1,8 @@
 # SPDX-License-Identifier: GPL-2.0
 TEST_GEN_PROGS := acct_syscall
+TEST_GEN_PROGS += taskstats_fill_stats_tgid
+
 CFLAGS += -Wall
+LDLIBS += -lpthread
 
-include ../lib.mk
\ No newline at end of file
+include ../lib.mk
diff --git a/tools/testing/selftests/acct/taskstats_fill_stats_tgid.c b/tools/testing/selftests/acct/taskstats_fill_stats_tgid.c
new file mode 100644
index 000000000000..d6cab4ae26f2
--- /dev/null
+++ b/tools/testing/selftests/acct/taskstats_fill_stats_tgid.c
@@ -0,0 +1,375 @@
+// SPDX-License-Identifier: GPL-2.0
+#define _GNU_SOURCE
+
+#include <errno.h>
+#include <linux/genetlink.h>
+#include <linux/netlink.h>
+#include <linux/taskstats.h>
+#include <pthread.h>
+#include <stdbool.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+#include <sys/socket.h>
+#include <sys/types.h>
+#include <time.h>
+#include <unistd.h>
+
+#include "kselftest.h"
+
+#ifndef NLA_ALIGN
+#define NLA_ALIGNTO 4
+#define NLA_ALIGN(len) (((len) + NLA_ALIGNTO - 1) & ~(NLA_ALIGNTO - 1))
+#define NLA_HDRLEN ((int)NLA_ALIGN(sizeof(struct nlattr)))
+#endif
+
+#define BUSY_NS (200ULL * 1000 * 1000)
+
+struct worker_ctx {
+	pthread_mutex_t lock;
+	pthread_cond_t cond;
+	bool ready;
+	bool release;
+};
+
+static unsigned long busy_sink;
+
+static void *taskstats_nla_data(const struct nlattr *na)
+{
+	return (void *)((char *)na + NLA_HDRLEN);
+}
+
+static bool taskstats_nla_ok(const struct nlattr *na, int remaining)
+{
+	return remaining >= (int)sizeof(*na) &&
+	       na->nla_len >= sizeof(*na) &&
+	       na->nla_len <= remaining;
+}
+
+static struct nlattr *taskstats_nla_next(const struct nlattr *na, int *remaining)
+{
+	int aligned_len = NLA_ALIGN(na->nla_len);
+
+	*remaining -= aligned_len;
+	return (struct nlattr *)((char *)na + aligned_len);
+}
+
+static uint64_t timespec_diff_ns(const struct timespec *start,
+				 const struct timespec *end)
+{
+	return (uint64_t)(end->tv_sec - start->tv_sec) * 1000000000ULL +
+	       (uint64_t)(end->tv_nsec - start->tv_nsec);
+}
+
+static void burn_cpu_for_ns(uint64_t runtime_ns)
+{
+	struct timespec start, now;
+	unsigned long acc = 0;
+
+	if (clock_gettime(CLOCK_MONOTONIC, &start)) {
+		perror("clock_gettime");
+		exit(EXIT_FAILURE);
+	}
+
+	do {
+		for (int i = 0; i < 100000; i++)
+			acc += i;
+		if (clock_gettime(CLOCK_MONOTONIC, &now)) {
+			perror("clock_gettime");
+			exit(EXIT_FAILURE);
+		}
+	} while (timespec_diff_ns(&start, &now) < runtime_ns);
+
+	busy_sink = acc;
+}
+
+static int netlink_open(void)
+{
+	struct sockaddr_nl addr = {
+		.nl_family = AF_NETLINK,
+		.nl_pid = getpid(),
+	};
+	int fd;
+
+	fd = socket(AF_NETLINK, SOCK_RAW, NETLINK_GENERIC);
+	if (fd < 0)
+		return -errno;
+
+	if (bind(fd, (struct sockaddr *)&addr, sizeof(addr)) < 0) {
+		int err = -errno;
+
+		close(fd);
+		return err;
+	}
+
+	return fd;
+}
+
+static int send_request(int fd, void *buf, size_t len)
+{
+	struct sockaddr_nl addr = {
+		.nl_family = AF_NETLINK,
+	};
+
+	if (sendto(fd, buf, len, 0, (struct sockaddr *)&addr, sizeof(addr)) < 0)
+		return -errno;
+
+	return 0;
+}
+
+static int get_family_id(int fd, const char *name)
+{
+	struct {
+		struct nlmsghdr nlh;
+		struct genlmsghdr genl;
+		char buf[256];
+	} req = { 0 };
+	char resp[8192];
+	struct nlmsghdr *nlh;
+	struct genlmsghdr *genl;
+	struct nlattr *na;
+	int len;
+	int rem;
+	int ret;
+
+	req.nlh.nlmsg_len = NLMSG_LENGTH(GENL_HDRLEN);
+	req.nlh.nlmsg_type = GENL_ID_CTRL;
+	req.nlh.nlmsg_flags = NLM_F_REQUEST;
+	req.nlh.nlmsg_seq = 1;
+	req.nlh.nlmsg_pid = getpid();
+
+	req.genl.cmd = CTRL_CMD_GETFAMILY;
+	req.genl.version = 1;
+
+	na = (struct nlattr *)((char *)&req + NLMSG_ALIGN(req.nlh.nlmsg_len));
+	na->nla_type = CTRL_ATTR_FAMILY_NAME;
+	na->nla_len = NLA_HDRLEN + strlen(name) + 1;
+	memcpy(taskstats_nla_data(na), name, strlen(name) + 1);
+	req.nlh.nlmsg_len = NLMSG_ALIGN(req.nlh.nlmsg_len) + NLA_ALIGN(na->nla_len);
+
+	ret = send_request(fd, &req, req.nlh.nlmsg_len);
+	if (ret)
+		return ret;
+
+	len = recv(fd, resp, sizeof(resp), 0);
+	if (len < 0)
+		return -errno;
+
+	for (nlh = (struct nlmsghdr *)resp; NLMSG_OK(nlh, len);
+	     nlh = NLMSG_NEXT(nlh, len)) {
+		if (nlh->nlmsg_type == NLMSG_ERROR) {
+			struct nlmsgerr *err = NLMSG_DATA(nlh);
+
+			return err->error ? err->error : -ENOENT;
+		}
+
+		genl = (struct genlmsghdr *)NLMSG_DATA(nlh);
+		rem = nlh->nlmsg_len - NLMSG_HDRLEN - GENL_HDRLEN;
+		na = (struct nlattr *)((char *)genl + GENL_HDRLEN);
+		while (taskstats_nla_ok(na, rem)) {
+			if (na->nla_type == CTRL_ATTR_FAMILY_ID)
+				return *(uint16_t *)taskstats_nla_data(na);
+			na = taskstats_nla_next(na, &rem);
+		}
+	}
+
+	return -ENOENT;
+}
+
+static int get_taskstats(int fd, int family_id, uint16_t attr_type, uint32_t id,
+			 struct taskstats *stats)
+{
+	struct {
+		struct nlmsghdr nlh;
+		struct genlmsghdr genl;
+		char buf[256];
+	} req = { 0 };
+	char resp[16384];
+	struct nlmsghdr *nlh;
+	struct genlmsghdr *genl;
+	struct nlattr *na;
+	struct nlattr *nested;
+	int len;
+	int rem;
+	int nrem;
+	int ret;
+
+	memset(stats, 0, sizeof(*stats));
+
+	req.nlh.nlmsg_len = NLMSG_LENGTH(GENL_HDRLEN);
+	req.nlh.nlmsg_type = family_id;
+	req.nlh.nlmsg_flags = NLM_F_REQUEST;
+	req.nlh.nlmsg_seq = 2;
+	req.nlh.nlmsg_pid = getpid();
+
+	req.genl.cmd = TASKSTATS_CMD_GET;
+	req.genl.version = 1;
+
+	na = (struct nlattr *)((char *)&req + NLMSG_ALIGN(req.nlh.nlmsg_len));
+	na->nla_type = attr_type;
+	na->nla_len = NLA_HDRLEN + sizeof(id);
+	memcpy(taskstats_nla_data(na), &id, sizeof(id));
+	req.nlh.nlmsg_len = NLMSG_ALIGN(req.nlh.nlmsg_len) + NLA_ALIGN(na->nla_len);
+
+	ret = send_request(fd, &req, req.nlh.nlmsg_len);
+	if (ret)
+		return ret;
+
+	len = recv(fd, resp, sizeof(resp), 0);
+	if (len < 0)
+		return -errno;
+
+	for (nlh = (struct nlmsghdr *)resp; NLMSG_OK(nlh, len);
+	     nlh = NLMSG_NEXT(nlh, len)) {
+		if (nlh->nlmsg_type == NLMSG_ERROR) {
+			struct nlmsgerr *err = NLMSG_DATA(nlh);
+
+			return err->error ? err->error : -ENOENT;
+		}
+
+		genl = (struct genlmsghdr *)NLMSG_DATA(nlh);
+		rem = nlh->nlmsg_len - NLMSG_HDRLEN - GENL_HDRLEN;
+		na = (struct nlattr *)((char *)genl + GENL_HDRLEN);
+		while (taskstats_nla_ok(na, rem)) {
+			if (na->nla_type == TASKSTATS_TYPE_AGGR_PID ||
+			    na->nla_type == TASKSTATS_TYPE_AGGR_TGID) {
+				nested = (struct nlattr *)taskstats_nla_data(na);
+				nrem = na->nla_len - NLA_HDRLEN;
+				while (taskstats_nla_ok(nested, nrem)) {
+					if (nested->nla_type == TASKSTATS_TYPE_STATS) {
+						memcpy(stats, taskstats_nla_data(nested),
+						       sizeof(*stats));
+						return 0;
+					}
+					nested = taskstats_nla_next(nested, &nrem);
+				}
+			}
+			na = taskstats_nla_next(na, &rem);
+		}
+	}
+
+	return -ENOENT;
+}
+
+static uint64_t cpu_total(const struct taskstats *stats)
+{
+	return (uint64_t)stats->ac_utime + (uint64_t)stats->ac_stime;
+}
+
+static void print_stats(const char *label, const struct taskstats *stats)
+{
+	ksft_print_msg("%s: cpu_total=%llu nvcsw=%llu nivcsw=%llu\n",
+		       label, (unsigned long long)cpu_total(stats),
+		       (unsigned long long)stats->nvcsw,
+		       (unsigned long long)stats->nivcsw);
+}
+
+static void *worker_thread(void *arg)
+{
+	struct worker_ctx *ctx = arg;
+
+	burn_cpu_for_ns(BUSY_NS);
+
+	pthread_mutex_lock(&ctx->lock);
+	ctx->ready = true;
+	pthread_cond_broadcast(&ctx->cond);
+	while (!ctx->release)
+		pthread_cond_wait(&ctx->cond, &ctx->lock);
+	pthread_mutex_unlock(&ctx->lock);
+
+	return NULL;
+}
+
+int main(void)
+{
+	struct worker_ctx ctx = {
+		.lock = PTHREAD_MUTEX_INITIALIZER,
+		.cond = PTHREAD_COND_INITIALIZER,
+	};
+	struct taskstats before, after;
+	pthread_t thread;
+	pid_t tgid = getpid();
+	int family_id;
+	int fd;
+	int ret;
+
+	ksft_print_header();
+	ksft_set_plan(1);
+
+	if (geteuid())
+		ksft_exit_skip("taskstats_fill_stats_tgid needs root\n");
+
+	fd = netlink_open();
+	if (fd < 0)
+		ksft_exit_skip("failed to open generic netlink socket: %s\n",
+			       strerror(-fd));
+
+	family_id = get_family_id(fd, TASKSTATS_GENL_NAME);
+	if (family_id < 0)
+		ksft_exit_skip("taskstats generic netlink family unavailable: %s\n",
+			       strerror(-family_id));
+
+	/* Create worker thread that burns 200ms of CPU */
+	if (pthread_create(&thread, NULL, worker_thread, &ctx) != 0)
+		ksft_exit_fail_msg("pthread_create failed: %s\n", strerror(errno));
+
+	/* Wait for worker to finish generating activity */
+	pthread_mutex_lock(&ctx.lock);
+	while (!ctx.ready)
+		pthread_cond_wait(&ctx.cond, &ctx.lock);
+	pthread_mutex_unlock(&ctx.lock);
+
+	/*
+	 * Snapshot A: TGID stats while worker is alive and sleeping.
+	 * Contains main thread + worker contributions.
+	 */
+	ret = get_taskstats(fd, family_id, TASKSTATS_CMD_ATTR_TGID, tgid, &before);
+	if (ret)
+		ksft_exit_fail_msg("TGID query before exit failed: %s\n",
+				   strerror(-ret));
+
+	/* Release worker so it can exit, then join (deterministic wait).
+	 *
+	 * Kernel exit path ordering guarantees:
+	 *   do_exit()
+	 *     taskstats_exit() -> fill_tgid_exit()  (accumulates worker into signal->stats)
+	 *     exit_notify()                         (releases the thread)
+	 *     do_task_dead() -> __schedule()        (wakes joiner)
+	 *
+	 * So pthread_join() returns only after fill_tgid_exit() has completed.
+	 */
+	pthread_mutex_lock(&ctx.lock);
+	ctx.release = true;
+	pthread_cond_broadcast(&ctx.cond);
+	pthread_mutex_unlock(&ctx.lock);
+
+	pthread_join(thread, NULL);
+
+	/*
+	 * Snapshot B: TGID stats after worker has exited.
+	 * fill_stats_for_tgid() does:
+	 *   memcpy(signal->stats)   <- includes fill_tgid_exit accumulation
+	 *   + scan live threads      <- only main thread now
+	 */
+	ret = get_taskstats(fd, family_id, TASKSTATS_CMD_ATTR_TGID, tgid, &after);
+	if (ret)
+		ksft_exit_fail_msg("TGID query after exit failed: %s\n",
+				   strerror(-ret));
+
+	print_stats("TGID before worker exit", &before);
+	print_stats("TGID after  worker exit", &after);
+
+	/*
+	 * The worker burned 200ms of CPU before the first snapshot.
+	 * If the kernel correctly retained its contribution via
+	 * fill_tgid_exit(), then the TGID CPU total after exit must be at
+	 * least as large as the TGID CPU total before exit.
+	 */
+	ksft_test_result(cpu_total(&after) >= cpu_total(&before),
+			 "TGID CPU stats should not regress after thread exit\n");
+
+	close(fd);
+	ksft_finished();
+	return ksft_get_fail_cnt() ? KSFT_FAIL : KSFT_PASS;
+}
diff --git a/tools/testing/selftests/bpf/prog_tests/bpf_tcp_ca.c b/tools/testing/selftests/bpf/prog_tests/bpf_tcp_ca.c
index f829b6f09bc9..fe30181e6336 100644
--- a/tools/testing/selftests/bpf/prog_tests/bpf_tcp_ca.c
+++ b/tools/testing/selftests/bpf/prog_tests/bpf_tcp_ca.c
@@ -112,6 +112,10 @@ static void test_cubic(void)
 
 	ASSERT_EQ(cubic_skel->bss->bpf_cubic_acked_called, 1, "pkts_acked called");
 
+	ASSERT_TRUE(cubic_skel->bss->nodelay_init_reject, "init reject nodelay option");
+	ASSERT_TRUE(cubic_skel->bss->nodelay_cwnd_event_tx_start_reject,
+		    "cwnd_event_tx_start reject nodelay option");
+
 	bpf_link__destroy(link);
 	bpf_cubic__destroy(cubic_skel);
 }
diff --git a/tools/testing/selftests/bpf/prog_tests/cgrp_local_storage.c b/tools/testing/selftests/bpf/prog_tests/cgrp_local_storage.c
index 478a77cb67e6..c4398ccf3493 100644
--- a/tools/testing/selftests/bpf/prog_tests/cgrp_local_storage.c
+++ b/tools/testing/selftests/bpf/prog_tests/cgrp_local_storage.c
@@ -176,7 +176,7 @@ static void test_cgroup_iter_sleepable(int cgroup_fd, __u64 cgroup_id)
 	DECLARE_LIBBPF_OPTS(bpf_iter_attach_opts, opts);
 	union bpf_iter_link_info linfo;
 	struct cgrp_ls_sleepable *skel;
-	struct bpf_link *link;
+	struct bpf_link *link, *fexit_link;
 	int err, iter_fd;
 	char buf[16];
 
@@ -200,16 +200,27 @@ static void test_cgroup_iter_sleepable(int cgroup_fd, __u64 cgroup_id)
 	if (!ASSERT_OK_PTR(link, "attach_iter"))
 		goto out;
 
+	fexit_link = bpf_program__attach(skel->progs.fexit_update);
+	if (!ASSERT_OK_PTR(fexit_link, "attach_fexit"))
+		goto out_link;
+
 	iter_fd = bpf_iter_create(bpf_link__fd(link));
 	if (!ASSERT_GE(iter_fd, 0, "iter_create"))
-		goto out_link;
+		goto out_fexit_link;
+
+	skel->bss->target_pid = sys_gettid();
 
 	/* trigger the program run */
 	(void)read(iter_fd, buf, sizeof(buf));
 
+	skel->bss->target_pid = 0;
+
+	ASSERT_EQ(skel->bss->update_err, 0, "update_err");
 	ASSERT_EQ(skel->bss->cgroup_id, cgroup_id, "cgroup_id");
 
 	close(iter_fd);
+out_fexit_link:
+	bpf_link__destroy(fexit_link);
 out_link:
 	bpf_link__destroy(link);
 out:
diff --git a/tools/testing/selftests/bpf/prog_tests/task_local_storage.c b/tools/testing/selftests/bpf/prog_tests/task_local_storage.c
index 1b26c12f255a..5b2b56cc3a4f 100644
--- a/tools/testing/selftests/bpf/prog_tests/task_local_storage.c
+++ b/tools/testing/selftests/bpf/prog_tests/task_local_storage.c
@@ -47,6 +47,7 @@ static void test_sys_enter_exit(void)
 	skel->bss->target_pid = 0;
 
 	/* 2x gettid syscalls */
+	ASSERT_EQ(skel->bss->update_err, 0, "update_err");
 	ASSERT_EQ(skel->bss->enter_cnt, 2, "enter_cnt");
 	ASSERT_EQ(skel->bss->exit_cnt, 2, "exit_cnt");
 	ASSERT_EQ(skel->bss->mismatch_cnt, 0, "mismatch_cnt");
diff --git a/tools/testing/selftests/bpf/prog_tests/tcp_hdr_options.c b/tools/testing/selftests/bpf/prog_tests/tcp_hdr_options.c
index 56685fc03c7e..80e6315da2a5 100644
--- a/tools/testing/selftests/bpf/prog_tests/tcp_hdr_options.c
+++ b/tools/testing/selftests/bpf/prog_tests/tcp_hdr_options.c
@@ -507,6 +507,10 @@ static void misc(void)
 
 	ASSERT_EQ(misc_skel->bss->nr_hwtstamp, 0, "nr_hwtstamp");
 
+	ASSERT_TRUE(misc_skel->bss->nodelay_est_ok, "nodelay_est_ok");
+	ASSERT_TRUE(misc_skel->bss->nodelay_hdr_len_reject, "nodelay_hdr_len_reject");
+	ASSERT_TRUE(misc_skel->bss->nodelay_write_hdr_reject, "nodelay_write_hdr_reject");
+
 check_linum:
 	ASSERT_FALSE(check_error_linum(&sk_fds), "check_error_linum");
 	sk_fds_close(&sk_fds);
diff --git a/tools/testing/selftests/bpf/progs/bpf_cubic.c b/tools/testing/selftests/bpf/progs/bpf_cubic.c
index ce18a4db813f..ebd5a1e69f56 100644
--- a/tools/testing/selftests/bpf/progs/bpf_cubic.c
+++ b/tools/testing/selftests/bpf/progs/bpf_cubic.c
@@ -16,6 +16,7 @@
 
 #include "bpf_tracing_net.h"
 #include <bpf/bpf_tracing.h>
+#include <errno.h>
 
 char _license[] SEC("license") = "GPL";
 
@@ -170,10 +171,18 @@ static void bictcp_hystart_reset(struct sock *sk)
 	ca->sample_cnt = 0;
 }
 
+bool nodelay_init_reject = false;
+bool nodelay_cwnd_event_tx_start_reject = false;
+
 SEC("struct_ops")
 void BPF_PROG(bpf_cubic_init, struct sock *sk)
 {
 	struct bpf_bictcp *ca = inet_csk_ca(sk);
+	int true_val = 1, ret;
+
+	ret = bpf_setsockopt(sk, SOL_TCP, TCP_NODELAY, &true_val, sizeof(true_val));
+	if (ret == -EOPNOTSUPP)
+		nodelay_init_reject = true;
 
 	bictcp_reset(ca);
 
@@ -189,8 +198,13 @@ void BPF_PROG(bpf_cubic_cwnd_event_tx_start, struct sock *sk)
 {
 	struct bpf_bictcp *ca = inet_csk_ca(sk);
 	__u32 now = tcp_jiffies32;
+	int true_val = 1, ret;
 	__s32 delta;
 
+	ret = bpf_setsockopt(sk, SOL_TCP, TCP_NODELAY, &true_val, sizeof(true_val));
+	if (ret == -EOPNOTSUPP)
+		nodelay_cwnd_event_tx_start_reject = true;
+
 	delta = now - tcp_sk(sk)->lsndtime;
 
 	/* We were application limited (idle) for a while.
diff --git a/tools/testing/selftests/bpf/progs/cgrp_ls_sleepable.c b/tools/testing/selftests/bpf/progs/cgrp_ls_sleepable.c
index a2de95f85648..37bd6b03ba01 100644
--- a/tools/testing/selftests/bpf/progs/cgrp_ls_sleepable.c
+++ b/tools/testing/selftests/bpf/progs/cgrp_ls_sleepable.c
@@ -4,6 +4,7 @@
 #include <bpf/bpf_helpers.h>
 #include <bpf/bpf_tracing.h>
 #include "bpf_misc.h"
+#include "err.h"
 
 char _license[] SEC("license") = "GPL";
 
@@ -16,6 +17,7 @@ struct {
 
 __s32 target_pid;
 __u64 cgroup_id;
+long update_err;
 int target_hid;
 bool is_cgroup1;
 
@@ -123,3 +125,19 @@ int yes_rcu_lock(void *ctx)
 	bpf_rcu_read_unlock();
 	return 0;
 }
+
+SEC("fexit/bpf_local_storage_update")
+int BPF_PROG(fexit_update, void *owner, struct bpf_local_storage_map *smap,
+	     void *value, u64 map_flags, bool swap_uptrs,
+	     struct bpf_local_storage_data *ret)
+{
+	struct task_struct *task = bpf_get_current_task_btf();
+
+	if (task->pid != target_pid)
+		return 0;
+
+	if (IS_ERR_VALUE(ret))
+		update_err = PTR_ERR(ret);
+
+	return 0;
+}
diff --git a/tools/testing/selftests/bpf/progs/task_local_storage.c b/tools/testing/selftests/bpf/progs/task_local_storage.c
index 80a0a20db88d..34fa3d6451d2 100644
--- a/tools/testing/selftests/bpf/progs/task_local_storage.c
+++ b/tools/testing/selftests/bpf/progs/task_local_storage.c
@@ -14,12 +14,15 @@ struct {
 	__type(value, long);
 } enter_id SEC(".maps");
 
+#include "err.h"
+
 #define MAGIC_VALUE 0xabcd1234
 
 pid_t target_pid = 0;
 int mismatch_cnt = 0;
 int enter_cnt = 0;
 int exit_cnt = 0;
+long update_err = 0;
 
 SEC("tp_btf/sys_enter")
 int BPF_PROG(on_enter, struct pt_regs *regs, long id)
@@ -62,3 +65,19 @@ int BPF_PROG(on_exit, struct pt_regs *regs, long id)
 		__sync_fetch_and_add(&mismatch_cnt, 1);
 	return 0;
 }
+
+SEC("fexit/bpf_local_storage_update")
+int BPF_PROG(fexit_update, void *owner, struct bpf_local_storage_map *smap,
+	     void *value, u64 map_flags, bool swap_uptrs,
+	     struct bpf_local_storage_data *ret)
+{
+	struct task_struct *task = bpf_get_current_task_btf();
+
+	if (task->pid != target_pid)
+		return 0;
+
+	if (IS_ERR_VALUE(ret))
+		update_err = PTR_ERR(ret);
+
+	return 0;
+}
diff --git a/tools/testing/selftests/bpf/progs/test_misc_tcp_hdr_options.c b/tools/testing/selftests/bpf/progs/test_misc_tcp_hdr_options.c
index d487153a839d..ed5a0011b863 100644
--- a/tools/testing/selftests/bpf/progs/test_misc_tcp_hdr_options.c
+++ b/tools/testing/selftests/bpf/progs/test_misc_tcp_hdr_options.c
@@ -29,6 +29,10 @@ unsigned int nr_syn = 0;
 unsigned int nr_fin = 0;
 unsigned int nr_hwtstamp = 0;
 
+bool nodelay_est_ok = false;
+bool nodelay_hdr_len_reject = false;
+bool nodelay_write_hdr_reject = false;
+
 /* Check the header received from the active side */
 static int __check_active_hdr_in(struct bpf_sock_ops *skops, bool check_syn)
 {
@@ -300,7 +304,7 @@ static int handle_passive_estab(struct bpf_sock_ops *skops)
 SEC("sockops")
 int misc_estab(struct bpf_sock_ops *skops)
 {
-	int true_val = 1;
+	int true_val = 1, false_val = 0, ret;
 
 	switch (skops->op) {
 	case BPF_SOCK_OPS_TCP_LISTEN_CB:
@@ -316,10 +320,19 @@ int misc_estab(struct bpf_sock_ops *skops)
 	case BPF_SOCK_OPS_PARSE_HDR_OPT_CB:
 		return handle_parse_hdr(skops);
 	case BPF_SOCK_OPS_HDR_OPT_LEN_CB:
+		ret = bpf_setsockopt(skops, SOL_TCP, TCP_NODELAY, &true_val, sizeof(true_val));
+		if (ret == -EOPNOTSUPP)
+			nodelay_hdr_len_reject = true;
 		return handle_hdr_opt_len(skops);
 	case BPF_SOCK_OPS_WRITE_HDR_OPT_CB:
+		ret = bpf_setsockopt(skops, SOL_TCP, TCP_NODELAY, &true_val, sizeof(true_val));
+		if (ret == -EOPNOTSUPP)
+			nodelay_write_hdr_reject = true;
 		return handle_write_hdr_opt(skops);
 	case BPF_SOCK_OPS_PASSIVE_ESTABLISHED_CB:
+		ret = bpf_setsockopt(skops, SOL_TCP, TCP_NODELAY, &false_val, sizeof(false_val));
+		if (!ret)
+			nodelay_est_ok = true;
 		return handle_passive_estab(skops);
 	}
 
diff --git a/tools/testing/selftests/filelock/.gitignore b/tools/testing/selftests/filelock/.gitignore
new file mode 100644
index 000000000000..825e899a121b
--- /dev/null
+++ b/tools/testing/selftests/filelock/.gitignore
@@ -0,0 +1 @@
+ofdlocks
diff --git a/tools/testing/selftests/filelock/ofdlocks.c b/tools/testing/selftests/filelock/ofdlocks.c
index ff8d47fc373a..68bac28b234b 100644
--- a/tools/testing/selftests/filelock/ofdlocks.c
+++ b/tools/testing/selftests/filelock/ofdlocks.c
@@ -16,7 +16,7 @@ static int lock_set(int fd, struct flock *fl)
 	fl->l_whence = SEEK_SET;
 	ret = fcntl(fd, F_OFD_SETLK, fl);
 	if (ret)
-		perror("fcntl()");
+		ksft_perror("fcntl()");
 	return ret;
 }
 
@@ -28,7 +28,7 @@ static int lock_get(int fd, struct flock *fl)
 	fl->l_whence = SEEK_SET;
 	ret = fcntl(fd, F_OFD_GETLK, fl);
 	if (ret)
-		perror("fcntl()");
+		ksft_perror("fcntl()");
 	return ret;
 }
 
@@ -39,94 +39,82 @@ int main(void)
 	int fd = open("/tmp/aa", O_RDWR | O_CREAT | O_EXCL, 0600);
 	int fd2 = open("/tmp/aa", O_RDONLY);
 
+	ksft_print_header();
+	ksft_set_plan(4);
+
 	unlink("/tmp/aa");
 	assert(fd != -1);
 	assert(fd2 != -1);
-	ksft_print_msg("[INFO] opened fds %i %i\n", fd, fd2);
+	ksft_print_msg("opened fds %i %i\n", fd, fd2);
 
 	/* Set some read lock */
 	fl.l_type = F_RDLCK;
 	fl.l_start = 5;
 	fl.l_len = 3;
 	rc = lock_set(fd, &fl);
-	if (rc == 0) {
-		ksft_print_msg
-		    ("[SUCCESS] set OFD read lock on first fd\n");
-	} else {
-		ksft_print_msg("[FAIL] to set OFD read lock on first fd\n");
-		return -1;
-	}
+	ksft_test_result(rc == 0, "set OFD read lock on first fd\n");
+	if (rc != 0)
+		ksft_finished();
+
 	/* Make sure read locks do not conflict on different fds. */
 	fl.l_type = F_RDLCK;
 	fl.l_start = 5;
 	fl.l_len = 1;
 	rc = lock_get(fd2, &fl);
 	if (rc != 0)
-		return -1;
-	if (fl.l_type != F_UNLCK) {
-		ksft_print_msg("[FAIL] read locks conflicted\n");
-		return -1;
-	}
+		ksft_finished();
+	if (fl.l_type != F_UNLCK)
+		ksft_exit_fail_msg("read locks conflicted\n");
+
 	/* Make sure read/write locks do conflict on different fds. */
 	fl.l_type = F_WRLCK;
 	fl.l_start = 5;
 	fl.l_len = 1;
 	rc = lock_get(fd2, &fl);
 	if (rc != 0)
-		return -1;
-	if (fl.l_type != F_UNLCK) {
-		ksft_print_msg
-		    ("[SUCCESS] read and write locks conflicted\n");
-	} else {
-		ksft_print_msg
-		    ("[SUCCESS] read and write locks not conflicted\n");
-		return -1;
-	}
+		ksft_finished();
+	ksft_test_result(fl.l_type != F_UNLCK,
+			 "read and write locks conflicted\n");
+	if (fl.l_type == F_UNLCK)
+		ksft_finished();
+
 	/* Get info about the lock on first fd. */
 	fl.l_type = F_UNLCK;
 	fl.l_start = 5;
 	fl.l_len = 1;
 	rc = lock_get(fd, &fl);
-	if (rc != 0) {
-		ksft_print_msg
-		    ("[FAIL] F_OFD_GETLK with F_UNLCK not supported\n");
-		return -1;
-	}
-	if (fl.l_type != F_UNLCK) {
-		ksft_print_msg
-		    ("[SUCCESS] F_UNLCK test returns: locked, type %i pid %i len %zi\n",
-		     fl.l_type, fl.l_pid, fl.l_len);
-	} else {
-		ksft_print_msg
-		    ("[FAIL] F_OFD_GETLK with F_UNLCK did not return lock info\n");
-		return -1;
-	}
+	if (rc != 0)
+		ksft_exit_fail_msg("F_OFD_GETLK with F_UNLCK not supported\n");
+	ksft_test_result(fl.l_type != F_UNLCK,
+			 "F_OFD_GETLK with F_UNLCK returned lock info\n");
+	if (fl.l_type == F_UNLCK)
+		ksft_exit_fail();
+	ksft_print_msg("F_UNLCK test returns: locked, type %i pid %i len %zi\n",
+		       fl.l_type, fl.l_pid, fl.l_len);
+
 	/* Try the same but by locking everything by len==0. */
 	fl2.l_type = F_UNLCK;
 	fl2.l_start = 0;
 	fl2.l_len = 0;
 	rc = lock_get(fd, &fl2);
-	if (rc != 0) {
-		ksft_print_msg
-		    ("[FAIL] F_OFD_GETLK with F_UNLCK not supported\n");
-		return -1;
-	}
+	if (rc != 0)
+		ksft_exit_fail_msg
+		    ("F_OFD_GETLK with F_UNLCK not supported\n");
+	ksft_test_result(memcmp(&fl, &fl2, sizeof(fl)) == 0,
+			 "F_UNLCK with len==0 returned the same\n");
 	if (memcmp(&fl, &fl2, sizeof(fl))) {
-		ksft_print_msg
-		    ("[FAIL] F_UNLCK test returns: locked, type %i pid %i len %zi\n",
+		ksft_exit_fail_msg
+		    ("F_UNLCK test returns: locked, type %i pid %i len %zi\n",
 		     fl.l_type, fl.l_pid, fl.l_len);
-		return -1;
 	}
-	ksft_print_msg("[SUCCESS] F_UNLCK with len==0 returned the same\n");
+
 	/* Get info about the lock on second fd - no locks on it. */
 	fl.l_type = F_UNLCK;
 	fl.l_start = 0;
 	fl.l_len = 0;
 	lock_get(fd2, &fl);
-	if (fl.l_type != F_UNLCK) {
-		ksft_print_msg
-		    ("[FAIL] F_OFD_GETLK with F_UNLCK return lock info from another fd\n");
-		return -1;
-	}
-	return 0;
+	ksft_test_result(fl.l_type == F_UNLCK,
+			 "F_OFD_GETLK with F_UNLCK return lock info from another fd\n");
+
+	ksft_finished();
 }
diff --git a/tools/testing/selftests/kvm/access_tracking_perf_test.c b/tools/testing/selftests/kvm/access_tracking_perf_test.c
index b058f27b2141..e5bbdb5bbdc3 100644
--- a/tools/testing/selftests/kvm/access_tracking_perf_test.c
+++ b/tools/testing/selftests/kvm/access_tracking_perf_test.c
@@ -101,15 +101,15 @@ struct test_params {
 	enum vm_mem_backing_src_type backing_src;
 
 	/* The amount of memory to allocate for each vCPU. */
-	uint64_t vcpu_memory_bytes;
+	u64 vcpu_memory_bytes;
 
 	/* The number of vCPUs to create in the VM. */
 	int nr_vcpus;
 };
 
-static uint64_t pread_uint64(int fd, const char *filename, uint64_t index)
+static u64 pread_u64(int fd, const char *filename, u64 index)
 {
-	uint64_t value;
+	u64 value;
 	off_t offset = index * sizeof(value);
 
 	TEST_ASSERT(pread(fd, &value, sizeof(value), offset) == sizeof(value),
@@ -123,13 +123,13 @@ static uint64_t pread_uint64(int fd, const char *filename, uint64_t index)
 #define PAGEMAP_PRESENT (1ULL << 63)
 #define PAGEMAP_PFN_MASK ((1ULL << 55) - 1)
 
-static uint64_t lookup_pfn(int pagemap_fd, struct kvm_vm *vm, uint64_t gva)
+static u64 lookup_pfn(int pagemap_fd, struct kvm_vm *vm, gva_t gva)
 {
-	uint64_t hva = (uint64_t) addr_gva2hva(vm, gva);
-	uint64_t entry;
-	uint64_t pfn;
+	u64 hva = (u64)addr_gva2hva(vm, gva);
+	u64 entry;
+	u64 pfn;
 
-	entry = pread_uint64(pagemap_fd, "pagemap", hva / getpagesize());
+	entry = pread_u64(pagemap_fd, "pagemap", hva / getpagesize());
 	if (!(entry & PAGEMAP_PRESENT))
 		return 0;
 
@@ -139,16 +139,16 @@ static uint64_t lookup_pfn(int pagemap_fd, struct kvm_vm *vm, uint64_t gva)
 	return pfn;
 }
 
-static bool is_page_idle(int page_idle_fd, uint64_t pfn)
+static bool is_page_idle(int page_idle_fd, u64 pfn)
 {
-	uint64_t bits = pread_uint64(page_idle_fd, "page_idle", pfn / 64);
+	u64 bits = pread_u64(page_idle_fd, "page_idle", pfn / 64);
 
 	return !!((bits >> (pfn % 64)) & 1);
 }
 
-static void mark_page_idle(int page_idle_fd, uint64_t pfn)
+static void mark_page_idle(int page_idle_fd, u64 pfn)
 {
-	uint64_t bits = 1ULL << (pfn % 64);
+	u64 bits = 1ULL << (pfn % 64);
 
 	TEST_ASSERT(pwrite(page_idle_fd, &bits, 8, 8 * (pfn / 64)) == 8,
 		    "Set page_idle bits for PFN 0x%" PRIx64, pfn);
@@ -174,11 +174,11 @@ static void pageidle_mark_vcpu_memory_idle(struct kvm_vm *vm,
 					   struct memstress_vcpu_args *vcpu_args)
 {
 	int vcpu_idx = vcpu_args->vcpu_idx;
-	uint64_t base_gva = vcpu_args->gva;
-	uint64_t pages = vcpu_args->pages;
-	uint64_t page;
-	uint64_t still_idle = 0;
-	uint64_t no_pfn = 0;
+	gva_t base_gva = vcpu_args->gva;
+	u64 pages = vcpu_args->pages;
+	u64 page;
+	u64 still_idle = 0;
+	u64 no_pfn = 0;
 	int page_idle_fd;
 	int pagemap_fd;
 
@@ -193,8 +193,8 @@ static void pageidle_mark_vcpu_memory_idle(struct kvm_vm *vm,
 	TEST_ASSERT(pagemap_fd > 0, "Failed to open pagemap.");
 
 	for (page = 0; page < pages; page++) {
-		uint64_t gva = base_gva + page * memstress_args.guest_page_size;
-		uint64_t pfn = lookup_pfn(pagemap_fd, vm, gva);
+		gva_t gva = base_gva + page * memstress_args.guest_page_size;
+		u64 pfn = lookup_pfn(pagemap_fd, vm, gva);
 
 		if (!pfn) {
 			no_pfn++;
@@ -297,10 +297,10 @@ static void lru_gen_mark_memory_idle(struct kvm_vm *vm)
 	lru_gen_last_gen = new_gen;
 }
 
-static void assert_ucall(struct kvm_vcpu *vcpu, uint64_t expected_ucall)
+static void assert_ucall(struct kvm_vcpu *vcpu, u64 expected_ucall)
 {
 	struct ucall uc;
-	uint64_t actual_ucall = get_ucall(vcpu, &uc);
+	u64 actual_ucall = get_ucall(vcpu, &uc);
 
 	TEST_ASSERT(expected_ucall == actual_ucall,
 		    "Guest exited unexpectedly (expected ucall %" PRIu64
@@ -417,7 +417,7 @@ static void run_test(enum vm_guest_mode mode, void *arg)
 	 */
 	test_pages = params->nr_vcpus * params->vcpu_memory_bytes /
 		      max(memstress_args.guest_page_size,
-			  (uint64_t)getpagesize());
+			  (u64)getpagesize());
 
 	memstress_start_vcpu_threads(nr_vcpus, vcpu_thread_main);
 
diff --git a/tools/testing/selftests/kvm/arch_timer.c b/tools/testing/selftests/kvm/arch_timer.c
index cf8fb67104f1..90c475a61b22 100644
--- a/tools/testing/selftests/kvm/arch_timer.c
+++ b/tools/testing/selftests/kvm/arch_timer.c
@@ -78,9 +78,9 @@ static void *test_vcpu_run(void *arg)
 	return NULL;
 }
 
-static uint32_t test_get_pcpu(void)
+static u32 test_get_pcpu(void)
 {
-	uint32_t pcpu;
+	u32 pcpu;
 	unsigned int nproc_conf;
 	cpu_set_t online_cpuset;
 
@@ -98,7 +98,7 @@ static uint32_t test_get_pcpu(void)
 static int test_migrate_vcpu(unsigned int vcpu_idx)
 {
 	int ret;
-	uint32_t new_pcpu = test_get_pcpu();
+	u32 new_pcpu = test_get_pcpu();
 
 	pr_debug("Migrating vCPU: %u to pCPU: %u\n", vcpu_idx, new_pcpu);
 
diff --git a/tools/testing/selftests/kvm/arm64/aarch32_id_regs.c b/tools/testing/selftests/kvm/arm64/aarch32_id_regs.c
index 713005b6f508..8a019cbaf4c4 100644
--- a/tools/testing/selftests/kvm/arm64/aarch32_id_regs.c
+++ b/tools/testing/selftests/kvm/arm64/aarch32_id_regs.c
@@ -66,7 +66,7 @@ static void test_guest_raz(struct kvm_vcpu *vcpu)
 	}
 }
 
-static uint64_t raz_wi_reg_ids[] = {
+static u64 raz_wi_reg_ids[] = {
 	KVM_ARM64_SYS_REG(SYS_ID_PFR0_EL1),
 	KVM_ARM64_SYS_REG(SYS_ID_PFR1_EL1),
 	KVM_ARM64_SYS_REG(SYS_ID_DFR0_EL1),
@@ -94,8 +94,8 @@ static void test_user_raz_wi(struct kvm_vcpu *vcpu)
 	int i;
 
 	for (i = 0; i < ARRAY_SIZE(raz_wi_reg_ids); i++) {
-		uint64_t reg_id = raz_wi_reg_ids[i];
-		uint64_t val;
+		u64 reg_id = raz_wi_reg_ids[i];
+		u64 val;
 
 		val = vcpu_get_reg(vcpu, reg_id);
 		TEST_ASSERT_EQ(val, 0);
@@ -111,7 +111,7 @@ static void test_user_raz_wi(struct kvm_vcpu *vcpu)
 	}
 }
 
-static uint64_t raz_invariant_reg_ids[] = {
+static u64 raz_invariant_reg_ids[] = {
 	KVM_ARM64_SYS_REG(SYS_ID_AFR0_EL1),
 	KVM_ARM64_SYS_REG(sys_reg(3, 0, 0, 3, 3)),
 	KVM_ARM64_SYS_REG(SYS_ID_DFR1_EL1),
@@ -123,8 +123,8 @@ static void test_user_raz_invariant(struct kvm_vcpu *vcpu)
 	int i, r;
 
 	for (i = 0; i < ARRAY_SIZE(raz_invariant_reg_ids); i++) {
-		uint64_t reg_id = raz_invariant_reg_ids[i];
-		uint64_t val;
+		u64 reg_id = raz_invariant_reg_ids[i];
+		u64 val;
 
 		val = vcpu_get_reg(vcpu, reg_id);
 		TEST_ASSERT_EQ(val, 0);
@@ -142,7 +142,7 @@ static void test_user_raz_invariant(struct kvm_vcpu *vcpu)
 
 static bool vcpu_aarch64_only(struct kvm_vcpu *vcpu)
 {
-	uint64_t val, el0;
+	u64 val, el0;
 
 	val = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR0_EL1));
 
diff --git a/tools/testing/selftests/kvm/arm64/arch_timer.c b/tools/testing/selftests/kvm/arm64/arch_timer.c
index d592a4515399..5fa5c0ec2b3e 100644
--- a/tools/testing/selftests/kvm/arm64/arch_timer.c
+++ b/tools/testing/selftests/kvm/arm64/arch_timer.c
@@ -56,7 +56,7 @@ static void guest_validate_irq(unsigned int intid,
 				struct test_vcpu_shared_data *shared_data)
 {
 	enum guest_stage stage = shared_data->guest_stage;
-	uint64_t xcnt = 0, xcnt_diff_us, cval = 0;
+	u64 xcnt = 0, xcnt_diff_us, cval = 0;
 	unsigned long xctl = 0;
 	unsigned int timer_irq = 0;
 	unsigned int accessor;
@@ -105,7 +105,7 @@ static void guest_validate_irq(unsigned int intid,
 static void guest_irq_handler(struct ex_regs *regs)
 {
 	unsigned int intid = gic_get_and_ack_irq();
-	uint32_t cpu = guest_get_vcpuid();
+	u32 cpu = guest_get_vcpuid();
 	struct test_vcpu_shared_data *shared_data = &vcpu_shared_data[cpu];
 
 	guest_validate_irq(intid, shared_data);
@@ -116,7 +116,7 @@ static void guest_irq_handler(struct ex_regs *regs)
 static void guest_run_stage(struct test_vcpu_shared_data *shared_data,
 				enum guest_stage stage)
 {
-	uint32_t irq_iter, config_iter;
+	u32 irq_iter, config_iter;
 
 	shared_data->guest_stage = stage;
 	shared_data->nr_iter = 0;
@@ -140,7 +140,7 @@ static void guest_run_stage(struct test_vcpu_shared_data *shared_data,
 
 static void guest_code(void)
 {
-	uint32_t cpu = guest_get_vcpuid();
+	u32 cpu = guest_get_vcpuid();
 	struct test_vcpu_shared_data *shared_data = &vcpu_shared_data[cpu];
 
 	local_irq_disable();
diff --git a/tools/testing/selftests/kvm/arm64/arch_timer_edge_cases.c b/tools/testing/selftests/kvm/arm64/arch_timer_edge_cases.c
index 993c9e38e729..f7625eb711d6 100644
--- a/tools/testing/selftests/kvm/arm64/arch_timer_edge_cases.c
+++ b/tools/testing/selftests/kvm/arm64/arch_timer_edge_cases.c
@@ -23,25 +23,25 @@
 #include "vgic.h"
 
 /* Depends on counter width. */
-static uint64_t CVAL_MAX;
+static u64 CVAL_MAX;
 /* tval is a signed 32-bit int. */
-static const int32_t TVAL_MAX = INT32_MAX;
-static const int32_t TVAL_MIN = INT32_MIN;
+static const s32 TVAL_MAX = INT32_MAX;
+static const s32 TVAL_MIN = INT32_MIN;
 
 /* After how much time we say there is no IRQ. */
-static const uint32_t TIMEOUT_NO_IRQ_US = 50000;
+static const u32 TIMEOUT_NO_IRQ_US = 50000;
 
 /* Counter value to use as the starting one for most tests. Set to CVAL_MAX/2 */
-static uint64_t DEF_CNT;
+static u64 DEF_CNT;
 
 /* Number of runs. */
-static const uint32_t NR_TEST_ITERS_DEF = 5;
+static const u32 NR_TEST_ITERS_DEF = 5;
 
 /* Default wait test time in ms. */
-static const uint32_t WAIT_TEST_MS = 10;
+static const u32 WAIT_TEST_MS = 10;
 
 /* Default "long" wait test time in ms. */
-static const uint32_t LONG_WAIT_TEST_MS = 100;
+static const u32 LONG_WAIT_TEST_MS = 100;
 
 /* Shared with IRQ handler. */
 struct test_vcpu_shared_data {
@@ -53,9 +53,9 @@ struct test_args {
 	/* Virtual or physical timer and counter tests. */
 	enum arch_timer timer;
 	/* Delay used for most timer tests. */
-	uint64_t wait_ms;
+	u64 wait_ms;
 	/* Delay used in the test_long_timer_delays test. */
-	uint64_t long_wait_ms;
+	u64 long_wait_ms;
 	/* Number of iterations. */
 	int iterations;
 	/* Whether to test the physical timer. */
@@ -82,12 +82,12 @@ enum sync_cmd {
 	NO_USERSPACE_CMD,
 };
 
-typedef void (*sleep_method_t)(enum arch_timer timer, uint64_t usec);
+typedef void (*sleep_method_t)(enum arch_timer timer, u64 usec);
 
-static void sleep_poll(enum arch_timer timer, uint64_t usec);
-static void sleep_sched_poll(enum arch_timer timer, uint64_t usec);
-static void sleep_in_userspace(enum arch_timer timer, uint64_t usec);
-static void sleep_migrate(enum arch_timer timer, uint64_t usec);
+static void sleep_poll(enum arch_timer timer, u64 usec);
+static void sleep_sched_poll(enum arch_timer timer, u64 usec);
+static void sleep_in_userspace(enum arch_timer timer, u64 usec);
+static void sleep_migrate(enum arch_timer timer, u64 usec);
 
 sleep_method_t sleep_method[] = {
 	sleep_poll,
@@ -115,14 +115,14 @@ enum timer_view {
 	TIMER_TVAL,
 };
 
-static void assert_irqs_handled(uint32_t n)
+static void assert_irqs_handled(u32 n)
 {
 	int h = atomic_read(&shared_data.handled);
 
 	__GUEST_ASSERT(h == n, "Handled %d IRQS but expected %d", h, n);
 }
 
-static void userspace_cmd(uint64_t cmd)
+static void userspace_cmd(u64 cmd)
 {
 	GUEST_SYNC_ARGS(cmd, 0, 0, 0, 0);
 }
@@ -132,12 +132,12 @@ static void userspace_migrate_vcpu(void)
 	userspace_cmd(USERSPACE_MIGRATE_SELF);
 }
 
-static void userspace_sleep(uint64_t usecs)
+static void userspace_sleep(u64 usecs)
 {
 	GUEST_SYNC_ARGS(USERSPACE_USLEEP, usecs, 0, 0, 0);
 }
 
-static void set_counter(enum arch_timer timer, uint64_t counter)
+static void set_counter(enum arch_timer timer, u64 counter)
 {
 	GUEST_SYNC_ARGS(SET_COUNTER_VALUE, counter, timer, 0, 0);
 }
@@ -146,8 +146,8 @@ static void guest_irq_handler(struct ex_regs *regs)
 {
 	unsigned int intid = gic_get_and_ack_irq();
 	enum arch_timer timer;
-	uint64_t cnt, cval;
-	uint32_t ctl;
+	u64 cnt, cval;
+	u32 ctl;
 	bool timer_condition, istatus;
 
 	if (intid == IAR_SPURIOUS) {
@@ -178,8 +178,8 @@ static void guest_irq_handler(struct ex_regs *regs)
 	gic_set_eoi(intid);
 }
 
-static void set_cval_irq(enum arch_timer timer, uint64_t cval_cycles,
-			 uint32_t ctl)
+static void set_cval_irq(enum arch_timer timer, u64 cval_cycles,
+			 u32 ctl)
 {
 	atomic_set(&shared_data.handled, 0);
 	atomic_set(&shared_data.spurious, 0);
@@ -187,8 +187,8 @@ static void set_cval_irq(enum arch_timer timer, uint64_t cval_cycles,
 	timer_set_ctl(timer, ctl);
 }
 
-static void set_tval_irq(enum arch_timer timer, uint64_t tval_cycles,
-			 uint32_t ctl)
+static void set_tval_irq(enum arch_timer timer, u64 tval_cycles,
+			 u32 ctl)
 {
 	atomic_set(&shared_data.handled, 0);
 	atomic_set(&shared_data.spurious, 0);
@@ -196,7 +196,7 @@ static void set_tval_irq(enum arch_timer timer, uint64_t tval_cycles,
 	timer_set_ctl(timer, ctl);
 }
 
-static void set_xval_irq(enum arch_timer timer, uint64_t xval, uint32_t ctl,
+static void set_xval_irq(enum arch_timer timer, u64 xval, u32 ctl,
 			 enum timer_view tv)
 {
 	switch (tv) {
@@ -275,13 +275,13 @@ static void wait_migrate_poll_for_irq(void)
  * Sleep for usec microseconds by polling in the guest or in
  * userspace (e.g. userspace_cmd=USERSPACE_SCHEDULE).
  */
-static void guest_poll(enum arch_timer test_timer, uint64_t usec,
+static void guest_poll(enum arch_timer test_timer, u64 usec,
 		       enum sync_cmd usp_cmd)
 {
-	uint64_t cycles = usec_to_cycles(usec);
+	u64 cycles = usec_to_cycles(usec);
 	/* Whichever timer we are testing with, sleep with the other. */
 	enum arch_timer sleep_timer = 1 - test_timer;
-	uint64_t start = timer_get_cntct(sleep_timer);
+	u64 start = timer_get_cntct(sleep_timer);
 
 	while ((timer_get_cntct(sleep_timer) - start) < cycles) {
 		if (usp_cmd == NO_USERSPACE_CMD)
@@ -291,22 +291,22 @@ static void guest_poll(enum arch_timer test_timer, uint64_t usec,
 	}
 }
 
-static void sleep_poll(enum arch_timer timer, uint64_t usec)
+static void sleep_poll(enum arch_timer timer, u64 usec)
 {
 	guest_poll(timer, usec, NO_USERSPACE_CMD);
 }
 
-static void sleep_sched_poll(enum arch_timer timer, uint64_t usec)
+static void sleep_sched_poll(enum arch_timer timer, u64 usec)
 {
 	guest_poll(timer, usec, USERSPACE_SCHED_YIELD);
 }
 
-static void sleep_migrate(enum arch_timer timer, uint64_t usec)
+static void sleep_migrate(enum arch_timer timer, u64 usec)
 {
 	guest_poll(timer, usec, USERSPACE_MIGRATE_SELF);
 }
 
-static void sleep_in_userspace(enum arch_timer timer, uint64_t usec)
+static void sleep_in_userspace(enum arch_timer timer, u64 usec)
 {
 	userspace_sleep(usec);
 }
@@ -315,15 +315,15 @@ static void sleep_in_userspace(enum arch_timer timer, uint64_t usec)
  * Reset the timer state to some nice values like the counter not being close
  * to the edge, and the control register masked and disabled.
  */
-static void reset_timer_state(enum arch_timer timer, uint64_t cnt)
+static void reset_timer_state(enum arch_timer timer, u64 cnt)
 {
 	set_counter(timer, cnt);
 	timer_set_ctl(timer, CTL_IMASK);
 }
 
-static void test_timer_xval(enum arch_timer timer, uint64_t xval,
+static void test_timer_xval(enum arch_timer timer, u64 xval,
 			    enum timer_view tv, irq_wait_method_t wm, bool reset_state,
-			    uint64_t reset_cnt)
+			    u64 reset_cnt)
 {
 	local_irq_disable();
 
@@ -348,23 +348,23 @@ static void test_timer_xval(enum arch_timer timer, uint64_t xval,
  * the "runner", like: tools/testing/selftests/kselftest/runner.sh.
  */
 
-static void test_timer_cval(enum arch_timer timer, uint64_t cval,
+static void test_timer_cval(enum arch_timer timer, u64 cval,
 			    irq_wait_method_t wm, bool reset_state,
-			    uint64_t reset_cnt)
+			    u64 reset_cnt)
 {
 	test_timer_xval(timer, cval, TIMER_CVAL, wm, reset_state, reset_cnt);
 }
 
-static void test_timer_tval(enum arch_timer timer, int32_t tval,
+static void test_timer_tval(enum arch_timer timer, s32 tval,
 			    irq_wait_method_t wm, bool reset_state,
-			    uint64_t reset_cnt)
+			    u64 reset_cnt)
 {
-	test_timer_xval(timer, (uint64_t) tval, TIMER_TVAL, wm, reset_state,
+	test_timer_xval(timer, (u64)tval, TIMER_TVAL, wm, reset_state,
 			reset_cnt);
 }
 
-static void test_xval_check_no_irq(enum arch_timer timer, uint64_t xval,
-				   uint64_t usec, enum timer_view timer_view,
+static void test_xval_check_no_irq(enum arch_timer timer, u64 xval,
+				   u64 usec, enum timer_view timer_view,
 				   sleep_method_t guest_sleep)
 {
 	local_irq_disable();
@@ -379,17 +379,17 @@ static void test_xval_check_no_irq(enum arch_timer timer, uint64_t xval,
 	assert_irqs_handled(0);
 }
 
-static void test_cval_no_irq(enum arch_timer timer, uint64_t cval,
-			     uint64_t usec, sleep_method_t wm)
+static void test_cval_no_irq(enum arch_timer timer, u64 cval,
+			     u64 usec, sleep_method_t wm)
 {
 	test_xval_check_no_irq(timer, cval, usec, TIMER_CVAL, wm);
 }
 
-static void test_tval_no_irq(enum arch_timer timer, int32_t tval, uint64_t usec,
+static void test_tval_no_irq(enum arch_timer timer, s32 tval, u64 usec,
 			     sleep_method_t wm)
 {
-	/* tval will be cast to an int32_t in test_xval_check_no_irq */
-	test_xval_check_no_irq(timer, (uint64_t) tval, usec, TIMER_TVAL, wm);
+	/* tval will be cast to an s32 in test_xval_check_no_irq */
+	test_xval_check_no_irq(timer, (u64)tval, usec, TIMER_TVAL, wm);
 }
 
 /* Test masking/unmasking a timer using the timer mask (not the IRQ mask). */
@@ -463,7 +463,7 @@ static void test_timers_fired_multiple_times(enum arch_timer timer)
  * timeout for the wait: we use the wfi instruction.
  */
 static void test_reprogramming_timer(enum arch_timer timer, irq_wait_method_t wm,
-				     int32_t delta_1_ms, int32_t delta_2_ms)
+				     s32 delta_1_ms, s32 delta_2_ms)
 {
 	local_irq_disable();
 	reset_timer_state(timer, DEF_CNT);
@@ -488,7 +488,7 @@ static void test_reprogramming_timer(enum arch_timer timer, irq_wait_method_t wm
 static void test_reprogram_timers(enum arch_timer timer)
 {
 	int i;
-	uint64_t base_wait = test_args.wait_ms;
+	u64 base_wait = test_args.wait_ms;
 
 	for (i = 0; i < ARRAY_SIZE(irq_wait_method); i++) {
 		/*
@@ -504,8 +504,8 @@ static void test_reprogram_timers(enum arch_timer timer)
 
 static void test_basic_functionality(enum arch_timer timer)
 {
-	int32_t tval = (int32_t) msec_to_cycles(test_args.wait_ms);
-	uint64_t cval = DEF_CNT + msec_to_cycles(test_args.wait_ms);
+	s32 tval = (s32)msec_to_cycles(test_args.wait_ms);
+	u64 cval = DEF_CNT + msec_to_cycles(test_args.wait_ms);
 	int i;
 
 	for (i = 0; i < ARRAY_SIZE(irq_wait_method); i++) {
@@ -593,7 +593,7 @@ static void test_set_cnt_after_tval_max(enum arch_timer timer, irq_wait_method_t
 	reset_timer_state(timer, DEF_CNT);
 
 	set_cval_irq(timer,
-		     (uint64_t) TVAL_MAX +
+		     (u64)TVAL_MAX +
 		     msec_to_cycles(test_args.wait_ms) / 2, CTL_ENABLE);
 
 	set_counter(timer, TVAL_MAX);
@@ -608,7 +608,7 @@ static void test_set_cnt_after_tval_max(enum arch_timer timer, irq_wait_method_t
 /* Test timers set for: cval = now + TVAL_MAX + wait_ms / 2 */
 static void test_timers_above_tval_max(enum arch_timer timer)
 {
-	uint64_t cval;
+	u64 cval;
 	int i;
 
 	/*
@@ -638,8 +638,8 @@ static void test_timers_above_tval_max(enum arch_timer timer)
  * sets the counter to cnt_1, the [c|t]val, the counter to cnt_2, and
  * then waits for an IRQ.
  */
-static void test_set_cnt_after_xval(enum arch_timer timer, uint64_t cnt_1,
-				    uint64_t xval, uint64_t cnt_2,
+static void test_set_cnt_after_xval(enum arch_timer timer, u64 cnt_1,
+				    u64 xval, u64 cnt_2,
 				    irq_wait_method_t wm, enum timer_view tv)
 {
 	local_irq_disable();
@@ -662,8 +662,8 @@ static void test_set_cnt_after_xval(enum arch_timer timer, uint64_t cnt_1,
  * then waits for an IRQ.
  */
 static void test_set_cnt_after_xval_no_irq(enum arch_timer timer,
-					   uint64_t cnt_1, uint64_t xval,
-					   uint64_t cnt_2,
+					   u64 cnt_1, u64 xval,
+					   u64 cnt_2,
 					   sleep_method_t guest_sleep,
 					   enum timer_view tv)
 {
@@ -684,31 +684,31 @@ static void test_set_cnt_after_xval_no_irq(enum arch_timer timer,
 	timer_set_ctl(timer, CTL_IMASK);
 }
 
-static void test_set_cnt_after_tval(enum arch_timer timer, uint64_t cnt_1,
-				    int32_t tval, uint64_t cnt_2,
+static void test_set_cnt_after_tval(enum arch_timer timer, u64 cnt_1,
+				    s32 tval, u64 cnt_2,
 				    irq_wait_method_t wm)
 {
 	test_set_cnt_after_xval(timer, cnt_1, tval, cnt_2, wm, TIMER_TVAL);
 }
 
-static void test_set_cnt_after_cval(enum arch_timer timer, uint64_t cnt_1,
-				    uint64_t cval, uint64_t cnt_2,
+static void test_set_cnt_after_cval(enum arch_timer timer, u64 cnt_1,
+				    u64 cval, u64 cnt_2,
 				    irq_wait_method_t wm)
 {
 	test_set_cnt_after_xval(timer, cnt_1, cval, cnt_2, wm, TIMER_CVAL);
 }
 
 static void test_set_cnt_after_tval_no_irq(enum arch_timer timer,
-					   uint64_t cnt_1, int32_t tval,
-					   uint64_t cnt_2, sleep_method_t wm)
+					   u64 cnt_1, s32 tval,
+					   u64 cnt_2, sleep_method_t wm)
 {
 	test_set_cnt_after_xval_no_irq(timer, cnt_1, tval, cnt_2, wm,
 				       TIMER_TVAL);
 }
 
 static void test_set_cnt_after_cval_no_irq(enum arch_timer timer,
-					   uint64_t cnt_1, uint64_t cval,
-					   uint64_t cnt_2, sleep_method_t wm)
+					   u64 cnt_1, u64 cval,
+					   u64 cnt_2, sleep_method_t wm)
 {
 	test_set_cnt_after_xval_no_irq(timer, cnt_1, cval, cnt_2, wm,
 				       TIMER_CVAL);
@@ -718,7 +718,7 @@ static void test_set_cnt_after_cval_no_irq(enum arch_timer timer,
 static void test_move_counters_ahead_of_timers(enum arch_timer timer)
 {
 	int i;
-	int32_t tval;
+	s32 tval;
 
 	for (i = 0; i < ARRAY_SIZE(irq_wait_method); i++) {
 		irq_wait_method_t wm = irq_wait_method[i];
@@ -730,8 +730,7 @@ static void test_move_counters_ahead_of_timers(enum arch_timer timer)
 		test_set_cnt_after_tval(timer, 0, -1, DEF_CNT + 1, wm);
 		test_set_cnt_after_tval(timer, 0, -1, TVAL_MAX, wm);
 		tval = TVAL_MAX;
-		test_set_cnt_after_tval(timer, 0, tval, (uint64_t) tval + 1,
-					wm);
+		test_set_cnt_after_tval(timer, 0, tval, (u64)tval + 1, wm);
 	}
 }
 
@@ -754,8 +753,8 @@ static void test_move_counters_behind_timers(enum arch_timer timer)
 
 static void test_timers_in_the_past(enum arch_timer timer)
 {
-	int32_t tval = -1 * (int32_t) msec_to_cycles(test_args.wait_ms);
-	uint64_t cval;
+	s32 tval = -1 * (s32)msec_to_cycles(test_args.wait_ms);
+	u64 cval;
 	int i;
 
 	for (i = 0; i < ARRAY_SIZE(irq_wait_method); i++) {
@@ -790,8 +789,8 @@ static void test_timers_in_the_past(enum arch_timer timer)
 
 static void test_long_timer_delays(enum arch_timer timer)
 {
-	int32_t tval = (int32_t) msec_to_cycles(test_args.long_wait_ms);
-	uint64_t cval = DEF_CNT + msec_to_cycles(test_args.long_wait_ms);
+	s32 tval = (s32)msec_to_cycles(test_args.long_wait_ms);
+	u64 cval = DEF_CNT + msec_to_cycles(test_args.long_wait_ms);
 	int i;
 
 	for (i = 0; i < ARRAY_SIZE(irq_wait_method); i++) {
@@ -846,11 +845,11 @@ static void guest_code(enum arch_timer timer)
 
 static cpu_set_t default_cpuset;
 
-static uint32_t next_pcpu(void)
+static u32 next_pcpu(void)
 {
-	uint32_t max = get_nprocs();
-	uint32_t cur = sched_getcpu();
-	uint32_t next = cur;
+	u32 max = get_nprocs();
+	u32 cur = sched_getcpu();
+	u32 next = cur;
 	cpu_set_t cpuset = default_cpuset;
 
 	TEST_ASSERT(max > 1, "Need at least two physical cpus");
@@ -862,7 +861,7 @@ static uint32_t next_pcpu(void)
 	return next;
 }
 
-static void kvm_set_cntxct(struct kvm_vcpu *vcpu, uint64_t cnt,
+static void kvm_set_cntxct(struct kvm_vcpu *vcpu, u64 cnt,
 			   enum arch_timer timer)
 {
 	if (timer == PHYSICAL)
@@ -874,7 +873,7 @@ static void kvm_set_cntxct(struct kvm_vcpu *vcpu, uint64_t cnt,
 static void handle_sync(struct kvm_vcpu *vcpu, struct ucall *uc)
 {
 	enum sync_cmd cmd = uc->args[1];
-	uint64_t val = uc->args[2];
+	u64 val = uc->args[2];
 	enum arch_timer timer = uc->args[3];
 
 	switch (cmd) {
@@ -1018,8 +1017,8 @@ static bool parse_args(int argc, char *argv[])
 
 static void set_counter_defaults(void)
 {
-	const uint64_t MIN_ROLLOVER_SECS = 40ULL * 365 * 24 * 3600;
-	uint64_t freq = read_sysreg(CNTFRQ_EL0);
+	const u64 MIN_ROLLOVER_SECS = 40ULL * 365 * 24 * 3600;
+	u64 freq = read_sysreg(CNTFRQ_EL0);
 	int width = ilog2(MIN_ROLLOVER_SECS * freq);
 
 	width = clamp(width, 56, 64);
diff --git a/tools/testing/selftests/kvm/arm64/debug-exceptions.c b/tools/testing/selftests/kvm/arm64/debug-exceptions.c
index 1d431de8729c..3eb4b1b6682d 100644
--- a/tools/testing/selftests/kvm/arm64/debug-exceptions.c
+++ b/tools/testing/selftests/kvm/arm64/debug-exceptions.c
@@ -31,14 +31,14 @@
 
 extern unsigned char sw_bp, sw_bp2, hw_bp, hw_bp2, bp_svc, bp_brk, hw_wp, ss_start, hw_bp_ctx;
 extern unsigned char iter_ss_begin, iter_ss_end;
-static volatile uint64_t sw_bp_addr, hw_bp_addr;
-static volatile uint64_t wp_addr, wp_data_addr;
-static volatile uint64_t svc_addr;
-static volatile uint64_t ss_addr[4], ss_idx;
-#define  PC(v)  ((uint64_t)&(v))
+static volatile u64 sw_bp_addr, hw_bp_addr;
+static volatile u64 wp_addr, wp_data_addr;
+static volatile u64 svc_addr;
+static volatile u64 ss_addr[4], ss_idx;
+#define  PC(v)  ((u64)&(v))
 
 #define GEN_DEBUG_WRITE_REG(reg_name)			\
-static void write_##reg_name(int num, uint64_t val)	\
+static void write_##reg_name(int num, u64 val)	\
 {							\
 	switch (num) {					\
 	case 0:						\
@@ -102,8 +102,8 @@ GEN_DEBUG_WRITE_REG(dbgwvr)
 
 static void reset_debug_state(void)
 {
-	uint8_t brps, wrps, i;
-	uint64_t dfr0;
+	u8 brps, wrps, i;
+	u64 dfr0;
 
 	asm volatile("msr daifset, #8");
 
@@ -140,7 +140,7 @@ static void enable_os_lock(void)
 
 static void enable_monitor_debug_exceptions(void)
 {
-	uint64_t mdscr;
+	u64 mdscr;
 
 	asm volatile("msr daifclr, #8");
 
@@ -149,9 +149,9 @@ static void enable_monitor_debug_exceptions(void)
 	isb();
 }
 
-static void install_wp(uint8_t wpn, uint64_t addr)
+static void install_wp(u8 wpn, u64 addr)
 {
-	uint32_t wcr;
+	u32 wcr;
 
 	wcr = DBGWCR_LEN8 | DBGWCR_RD | DBGWCR_WR | DBGWCR_EL1 | DBGWCR_E;
 	write_dbgwcr(wpn, wcr);
@@ -162,9 +162,9 @@ static void install_wp(uint8_t wpn, uint64_t addr)
 	enable_monitor_debug_exceptions();
 }
 
-static void install_hw_bp(uint8_t bpn, uint64_t addr)
+static void install_hw_bp(u8 bpn, u64 addr)
 {
-	uint32_t bcr;
+	u32 bcr;
 
 	bcr = DBGBCR_LEN8 | DBGBCR_EXEC | DBGBCR_EL1 | DBGBCR_E;
 	write_dbgbcr(bpn, bcr);
@@ -174,11 +174,10 @@ static void install_hw_bp(uint8_t bpn, uint64_t addr)
 	enable_monitor_debug_exceptions();
 }
 
-static void install_wp_ctx(uint8_t addr_wp, uint8_t ctx_bp, uint64_t addr,
-			   uint64_t ctx)
+static void install_wp_ctx(u8 addr_wp, u8 ctx_bp, u64 addr, u64 ctx)
 {
-	uint32_t wcr;
-	uint64_t ctx_bcr;
+	u32 wcr;
+	u64 ctx_bcr;
 
 	/* Setup a context-aware breakpoint for Linked Context ID Match */
 	ctx_bcr = DBGBCR_LEN8 | DBGBCR_EXEC | DBGBCR_EL1 | DBGBCR_E |
@@ -188,7 +187,7 @@ static void install_wp_ctx(uint8_t addr_wp, uint8_t ctx_bp, uint64_t addr,
 
 	/* Setup a linked watchpoint (linked to the context-aware breakpoint) */
 	wcr = DBGWCR_LEN8 | DBGWCR_RD | DBGWCR_WR | DBGWCR_EL1 | DBGWCR_E |
-	      DBGWCR_WT_LINK | ((uint32_t)ctx_bp << DBGWCR_LBN_SHIFT);
+	      DBGWCR_WT_LINK | ((u32)ctx_bp << DBGWCR_LBN_SHIFT);
 	write_dbgwcr(addr_wp, wcr);
 	write_dbgwvr(addr_wp, addr);
 	isb();
@@ -196,10 +195,9 @@ static void install_wp_ctx(uint8_t addr_wp, uint8_t ctx_bp, uint64_t addr,
 	enable_monitor_debug_exceptions();
 }
 
-void install_hw_bp_ctx(uint8_t addr_bp, uint8_t ctx_bp, uint64_t addr,
-		       uint64_t ctx)
+void install_hw_bp_ctx(u8 addr_bp, u8 ctx_bp, u64 addr, u64 ctx)
 {
-	uint32_t addr_bcr, ctx_bcr;
+	u32 addr_bcr, ctx_bcr;
 
 	/* Setup a context-aware breakpoint for Linked Context ID Match */
 	ctx_bcr = DBGBCR_LEN8 | DBGBCR_EXEC | DBGBCR_EL1 | DBGBCR_E |
@@ -213,7 +211,7 @@ void install_hw_bp_ctx(uint8_t addr_bp, uint8_t ctx_bp, uint64_t addr,
 	 */
 	addr_bcr = DBGBCR_LEN8 | DBGBCR_EXEC | DBGBCR_EL1 | DBGBCR_E |
 		   DBGBCR_BT_ADDR_LINK_CTX |
-		   ((uint32_t)ctx_bp << DBGBCR_LBN_SHIFT);
+		   ((u32)ctx_bp << DBGBCR_LBN_SHIFT);
 	write_dbgbcr(addr_bp, addr_bcr);
 	write_dbgbvr(addr_bp, addr);
 	isb();
@@ -223,7 +221,7 @@ void install_hw_bp_ctx(uint8_t addr_bp, uint8_t ctx_bp, uint64_t addr,
 
 static void install_ss(void)
 {
-	uint64_t mdscr;
+	u64 mdscr;
 
 	asm volatile("msr daifclr, #8");
 
@@ -234,9 +232,9 @@ static void install_ss(void)
 
 static volatile char write_data;
 
-static void guest_code(uint8_t bpn, uint8_t wpn, uint8_t ctx_bpn)
+static void guest_code(u8 bpn, u8 wpn, u8 ctx_bpn)
 {
-	uint64_t ctx = 0xabcdef;	/* a random context number */
+	u64 ctx = 0xabcdef;	/* a random context number */
 
 	/* Software-breakpoint */
 	reset_debug_state();
@@ -377,8 +375,8 @@ static void guest_svc_handler(struct ex_regs *regs)
 
 static void guest_code_ss(int test_cnt)
 {
-	uint64_t i;
-	uint64_t bvr, wvr, w_bvr, w_wvr;
+	u64 i;
+	u64 bvr, wvr, w_bvr, w_wvr;
 
 	for (i = 0; i < test_cnt; i++) {
 		/* Bits [1:0] of dbg{b,w}vr are RES0 */
@@ -416,12 +414,12 @@ static void guest_code_ss(int test_cnt)
 	GUEST_DONE();
 }
 
-static int debug_version(uint64_t id_aa64dfr0)
+static int debug_version(u64 id_aa64dfr0)
 {
 	return FIELD_GET(ID_AA64DFR0_EL1_DebugVer, id_aa64dfr0);
 }
 
-static void test_guest_debug_exceptions(uint8_t bpn, uint8_t wpn, uint8_t ctx_bpn)
+static void test_guest_debug_exceptions(u8 bpn, u8 wpn, u8 ctx_bpn)
 {
 	struct kvm_vcpu *vcpu;
 	struct kvm_vm *vm;
@@ -468,8 +466,8 @@ void test_single_step_from_userspace(int test_cnt)
 	struct kvm_vm *vm;
 	struct ucall uc;
 	struct kvm_run *run;
-	uint64_t pc, cmd;
-	uint64_t test_pc = 0;
+	u64 pc, cmd;
+	u64 test_pc = 0;
 	bool ss_enable = false;
 	struct kvm_guest_debug debug = {};
 
@@ -506,7 +504,7 @@ void test_single_step_from_userspace(int test_cnt)
 			    "Unexpected pc 0x%lx (expected 0x%lx)",
 			    pc, test_pc);
 
-		if ((pc + 4) == (uint64_t)&iter_ss_end) {
+		if ((pc + 4) == (u64)&iter_ss_end) {
 			test_pc = 0;
 			debug.control = KVM_GUESTDBG_ENABLE;
 			ss_enable = false;
@@ -519,8 +517,8 @@ void test_single_step_from_userspace(int test_cnt)
 		 * iter_ss_end, the pc for the next KVM_EXIT_DEBUG should
 		 * be the current pc + 4.
 		 */
-		if ((pc >= (uint64_t)&iter_ss_begin) &&
-		    (pc < (uint64_t)&iter_ss_end))
+		if ((pc >= (u64)&iter_ss_begin) &&
+		    (pc < (u64)&iter_ss_end))
 			test_pc = pc + 4;
 		else
 			test_pc = 0;
@@ -533,9 +531,9 @@ void test_single_step_from_userspace(int test_cnt)
  * Run debug testing using the various breakpoint#, watchpoint# and
  * context-aware breakpoint# with the given ID_AA64DFR0_EL1 configuration.
  */
-void test_guest_debug_exceptions_all(uint64_t aa64dfr0)
+void test_guest_debug_exceptions_all(u64 aa64dfr0)
 {
-	uint8_t brp_num, wrp_num, ctx_brp_num, normal_brp_num, ctx_brp_base;
+	u8 brp_num, wrp_num, ctx_brp_num, normal_brp_num, ctx_brp_base;
 	int b, w, c;
 
 	/* Number of breakpoints */
@@ -580,7 +578,7 @@ int main(int argc, char *argv[])
 	struct kvm_vm *vm;
 	int opt;
 	int ss_iteration = 10000;
-	uint64_t aa64dfr0;
+	u64 aa64dfr0;
 
 	vm = vm_create_with_one_vcpu(&vcpu, guest_code);
 	aa64dfr0 = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64DFR0_EL1));
diff --git a/tools/testing/selftests/kvm/arm64/hypercalls.c b/tools/testing/selftests/kvm/arm64/hypercalls.c
index bf038a0371f4..5d96cdf382c4 100644
--- a/tools/testing/selftests/kvm/arm64/hypercalls.c
+++ b/tools/testing/selftests/kvm/arm64/hypercalls.c
@@ -29,9 +29,9 @@
 #define KVM_REG_ARM_VENDOR_HYP_BMAP_2_RESET_VAL 0
 
 struct kvm_fw_reg_info {
-	uint64_t reg;		/* Register definition */
-	uint64_t max_feat_bit;	/* Bit that represents the upper limit of the feature-map */
-	uint64_t reset_val;	/* Reset value for the register */
+	u64 reg;		/* Register definition */
+	u64 max_feat_bit;	/* Bit that represents the upper limit of the feature-map */
+	u64 reset_val;	/* Reset value for the register */
 };
 
 #define FW_REG_INFO(r)			\
@@ -59,8 +59,8 @@ enum test_stage {
 static int stage = TEST_STAGE_REG_IFACE;
 
 struct test_hvc_info {
-	uint32_t func_id;
-	uint64_t arg1;
+	u32 func_id;
+	u64 arg1;
 };
 
 #define TEST_HVC_INFO(f, a1)	\
@@ -152,9 +152,9 @@ static void guest_code(void)
 }
 
 struct st_time {
-	uint32_t rev;
-	uint32_t attr;
-	uint64_t st_time;
+	u32 rev;
+	u32 attr;
+	u64 st_time;
 };
 
 #define STEAL_TIME_SIZE		((sizeof(struct st_time) + 63) & ~63)
@@ -162,7 +162,7 @@ struct st_time {
 
 static void steal_time_init(struct kvm_vcpu *vcpu)
 {
-	uint64_t st_ipa = (ulong)ST_GPA_BASE;
+	u64 st_ipa = (ulong)ST_GPA_BASE;
 	unsigned int gpages;
 
 	gpages = vm_calc_num_guest_pages(VM_MODE_DEFAULT, STEAL_TIME_SIZE);
@@ -174,13 +174,13 @@ static void steal_time_init(struct kvm_vcpu *vcpu)
 
 static void test_fw_regs_before_vm_start(struct kvm_vcpu *vcpu)
 {
-	uint64_t val;
+	u64 val;
 	unsigned int i;
 	int ret;
 
 	for (i = 0; i < ARRAY_SIZE(fw_reg_info); i++) {
 		const struct kvm_fw_reg_info *reg_info = &fw_reg_info[i];
-		uint64_t set_val;
+		u64 set_val;
 
 		/* First 'read' should be the reset value for the reg  */
 		val = vcpu_get_reg(vcpu, reg_info->reg);
@@ -229,7 +229,7 @@ static void test_fw_regs_before_vm_start(struct kvm_vcpu *vcpu)
 
 static void test_fw_regs_after_vm_start(struct kvm_vcpu *vcpu)
 {
-	uint64_t val;
+	u64 val;
 	unsigned int i;
 	int ret;
 
diff --git a/tools/testing/selftests/kvm/arm64/idreg-idst.c b/tools/testing/selftests/kvm/arm64/idreg-idst.c
index 9ca9f125abdb..a3e84701d814 100644
--- a/tools/testing/selftests/kvm/arm64/idreg-idst.c
+++ b/tools/testing/selftests/kvm/arm64/idreg-idst.c
@@ -13,7 +13,7 @@ static volatile bool sys64, undef;
 
 #define __check_sr_read(r)					\
 	({							\
-		uint64_t val;					\
+		u64 val;					\
 								\
 		sys64 = false;					\
 		undef = false;					\
@@ -101,7 +101,7 @@ int main(int argc, char *argv[])
 {
 	struct kvm_vcpu *vcpu;
 	struct kvm_vm *vm;
-	uint64_t mmfr2;
+	u64 mmfr2;
 
 	test_disable_default_vgic();
 
diff --git a/tools/testing/selftests/kvm/arm64/no-vgic.c b/tools/testing/selftests/kvm/arm64/no-vgic.c
index b14686ef17d1..25b2e3222f68 100644
--- a/tools/testing/selftests/kvm/arm64/no-vgic.c
+++ b/tools/testing/selftests/kvm/arm64/no-vgic.c
@@ -15,7 +15,7 @@ static volatile bool handled;
 
 #define __check_sr_read(r)					\
 	({							\
-		uint64_t val;					\
+		u64 val;					\
 								\
 		handled = false;				\
 		dsb(sy);					\
@@ -33,7 +33,7 @@ static volatile bool handled;
 
 #define __check_gicv5_gicr_op(r)				\
 	({							\
-		uint64_t val;					\
+		u64 val;					\
 								\
 		handled = false;				\
 		dsb(sy);					\
@@ -82,7 +82,7 @@ static volatile bool handled;
 
 static void guest_code_gicv3(void)
 {
-	uint64_t val;
+	u64 val;
 
 	/*
 	 * Check that we advertise that ID_AA64PFR0_EL1.GIC == 0, having
@@ -262,7 +262,7 @@ int main(int argc, char *argv[])
 	struct kvm_vcpu *vcpu;
 	struct kvm_vm *vm;
 	bool has_v3, has_v5;
-	uint64_t pfr;
+	u64 pfr;
 
 	test_disable_default_vgic();
 
diff --git a/tools/testing/selftests/kvm/arm64/page_fault_test.c b/tools/testing/selftests/kvm/arm64/page_fault_test.c
index 4ccbd389d133..6bb3d82906b2 100644
--- a/tools/testing/selftests/kvm/arm64/page_fault_test.c
+++ b/tools/testing/selftests/kvm/arm64/page_fault_test.c
@@ -23,7 +23,7 @@
 #define TEST_PTE_GVA				0xb0000000
 #define TEST_DATA				0x0123456789ABCDEF
 
-static uint64_t *guest_test_memory = (uint64_t *)TEST_GVA;
+static u64 *guest_test_memory = (u64 *)TEST_GVA;
 
 #define CMD_NONE				(0)
 #define CMD_SKIP_TEST				(1ULL << 1)
@@ -48,7 +48,7 @@ static struct event_cnt {
 
 struct test_desc {
 	const char *name;
-	uint64_t mem_mark_cmd;
+	u64 mem_mark_cmd;
 	/* Skip the test if any prepare function returns false */
 	bool (*guest_prepare[PREPARE_FN_NR])(void);
 	void (*guest_test)(void);
@@ -59,8 +59,8 @@ struct test_desc {
 	void (*iabt_handler)(struct ex_regs *regs);
 	void (*mmio_handler)(struct kvm_vm *vm, struct kvm_run *run);
 	void (*fail_vcpu_run_handler)(int ret);
-	uint32_t pt_memslot_flags;
-	uint32_t data_memslot_flags;
+	u32 pt_memslot_flags;
+	u32 data_memslot_flags;
 	bool skip;
 	struct event_cnt expected_events;
 };
@@ -70,9 +70,9 @@ struct test_params {
 	struct test_desc *test_desc;
 };
 
-static inline void flush_tlb_page(uint64_t vaddr)
+static inline void flush_tlb_page(gva_t gva)
 {
-	uint64_t page = vaddr >> 12;
+	gva_t page = gva >> 12;
 
 	dsb(ishst);
 	asm volatile("tlbi vaae1is, %0" :: "r" (page));
@@ -82,7 +82,7 @@ static inline void flush_tlb_page(uint64_t vaddr)
 
 static void guest_write64(void)
 {
-	uint64_t val;
+	u64 val;
 
 	WRITE_ONCE(*guest_test_memory, TEST_DATA);
 	val = READ_ONCE(*guest_test_memory);
@@ -92,8 +92,8 @@ static void guest_write64(void)
 /* Check the system for atomic instructions. */
 static bool guest_check_lse(void)
 {
-	uint64_t isar0 = read_sysreg(id_aa64isar0_el1);
-	uint64_t atomic;
+	u64 isar0 = read_sysreg(id_aa64isar0_el1);
+	u64 atomic;
 
 	atomic = FIELD_GET(ID_AA64ISAR0_EL1_ATOMIC, isar0);
 	return atomic >= 2;
@@ -101,8 +101,8 @@ static bool guest_check_lse(void)
 
 static bool guest_check_dc_zva(void)
 {
-	uint64_t dczid = read_sysreg(dczid_el0);
-	uint64_t dzp = FIELD_GET(DCZID_EL0_DZP, dczid);
+	u64 dczid = read_sysreg(dczid_el0);
+	u64 dzp = FIELD_GET(DCZID_EL0_DZP, dczid);
 
 	return dzp == 0;
 }
@@ -110,7 +110,7 @@ static bool guest_check_dc_zva(void)
 /* Compare and swap instruction. */
 static void guest_cas(void)
 {
-	uint64_t val;
+	u64 val;
 
 	GUEST_ASSERT(guest_check_lse());
 	asm volatile(".arch_extension lse\n"
@@ -122,7 +122,7 @@ static void guest_cas(void)
 
 static void guest_read64(void)
 {
-	uint64_t val;
+	u64 val;
 
 	val = READ_ONCE(*guest_test_memory);
 	GUEST_ASSERT_EQ(val, 0);
@@ -131,7 +131,7 @@ static void guest_read64(void)
 /* Address translation instruction */
 static void guest_at(void)
 {
-	uint64_t par;
+	u64 par;
 
 	asm volatile("at s1e1r, %0" :: "r" (guest_test_memory));
 	isb();
@@ -148,7 +148,7 @@ static void guest_at(void)
  */
 static void guest_dc_zva(void)
 {
-	uint16_t val;
+	u16 val;
 
 	asm volatile("dc zva, %0" :: "r" (guest_test_memory));
 	dsb(ish);
@@ -164,8 +164,8 @@ static void guest_dc_zva(void)
  */
 static void guest_ld_preidx(void)
 {
-	uint64_t val;
-	uint64_t addr = TEST_GVA - 8;
+	u64 val;
+	u64 addr = TEST_GVA - 8;
 
 	/*
 	 * This ends up accessing "TEST_GVA + 8 - 8", where "TEST_GVA - 8" is
@@ -179,8 +179,8 @@ static void guest_ld_preidx(void)
 
 static void guest_st_preidx(void)
 {
-	uint64_t val = TEST_DATA;
-	uint64_t addr = TEST_GVA - 8;
+	u64 val = TEST_DATA;
+	u64 addr = TEST_GVA - 8;
 
 	asm volatile("str %0, [%1, #8]!"
 		     : "+r" (val), "+r" (addr));
@@ -191,8 +191,8 @@ static void guest_st_preidx(void)
 
 static bool guest_set_ha(void)
 {
-	uint64_t mmfr1 = read_sysreg(id_aa64mmfr1_el1);
-	uint64_t hadbs, tcr;
+	u64 mmfr1 = read_sysreg(id_aa64mmfr1_el1);
+	u64 hadbs, tcr;
 
 	/* Skip if HA is not supported. */
 	hadbs = FIELD_GET(ID_AA64MMFR1_EL1_HAFDBS, mmfr1);
@@ -208,7 +208,7 @@ static bool guest_set_ha(void)
 
 static bool guest_clear_pte_af(void)
 {
-	*((uint64_t *)TEST_PTE_GVA) &= ~PTE_AF;
+	*((u64 *)TEST_PTE_GVA) &= ~PTE_AF;
 	flush_tlb_page(TEST_GVA);
 
 	return true;
@@ -217,7 +217,7 @@ static bool guest_clear_pte_af(void)
 static void guest_check_pte_af(void)
 {
 	dsb(ish);
-	GUEST_ASSERT_EQ(*((uint64_t *)TEST_PTE_GVA) & PTE_AF, PTE_AF);
+	GUEST_ASSERT_EQ(*((u64 *)TEST_PTE_GVA) & PTE_AF, PTE_AF);
 }
 
 static void guest_check_write_in_dirty_log(void)
@@ -302,26 +302,26 @@ static void no_iabt_handler(struct ex_regs *regs)
 static struct uffd_args {
 	char *copy;
 	void *hva;
-	uint64_t paging_size;
+	u64 paging_size;
 } pt_args, data_args;
 
 /* Returns true to continue the test, and false if it should be skipped. */
 static int uffd_generic_handler(int uffd_mode, int uffd, struct uffd_msg *msg,
 				struct uffd_args *args)
 {
-	uint64_t addr = msg->arg.pagefault.address;
-	uint64_t flags = msg->arg.pagefault.flags;
+	u64 addr = msg->arg.pagefault.address;
+	u64 flags = msg->arg.pagefault.flags;
 	struct uffdio_copy copy;
 	int ret;
 
 	TEST_ASSERT(uffd_mode == UFFDIO_REGISTER_MODE_MISSING,
 		    "The only expected UFFD mode is MISSING");
-	TEST_ASSERT_EQ(addr, (uint64_t)args->hva);
+	TEST_ASSERT_EQ(addr, (u64)args->hva);
 
 	pr_debug("uffd fault: addr=%p write=%d\n",
 		 (void *)addr, !!(flags & UFFD_PAGEFAULT_FLAG_WRITE));
 
-	copy.src = (uint64_t)args->copy;
+	copy.src = (u64)args->copy;
 	copy.dst = addr;
 	copy.len = args->paging_size;
 	copy.mode = 0;
@@ -407,7 +407,7 @@ static bool punch_hole_in_backing_store(struct kvm_vm *vm,
 					struct userspace_mem_region *region)
 {
 	void *hva = (void *)region->region.userspace_addr;
-	uint64_t paging_size = region->region.memory_size;
+	u64 paging_size = region->region.memory_size;
 	int ret, fd = region->fd;
 
 	if (fd != -1) {
@@ -438,7 +438,7 @@ static void mmio_on_test_gpa_handler(struct kvm_vm *vm, struct kvm_run *run)
 
 static void mmio_no_handler(struct kvm_vm *vm, struct kvm_run *run)
 {
-	uint64_t data;
+	u64 data;
 
 	memcpy(&data, run->mmio.data, sizeof(data));
 	pr_debug("addr=%lld len=%d w=%d data=%lx\n",
@@ -449,11 +449,11 @@ static void mmio_no_handler(struct kvm_vm *vm, struct kvm_run *run)
 
 static bool check_write_in_dirty_log(struct kvm_vm *vm,
 				     struct userspace_mem_region *region,
-				     uint64_t host_pg_nr)
+				     u64 host_pg_nr)
 {
 	unsigned long *bmap;
 	bool first_page_dirty;
-	uint64_t size = region->region.memory_size;
+	u64 size = region->region.memory_size;
 
 	/* getpage_size() is not always equal to vm->page_size */
 	bmap = bitmap_zalloc(size / getpagesize());
@@ -468,7 +468,7 @@ static bool handle_cmd(struct kvm_vm *vm, int cmd)
 {
 	struct userspace_mem_region *data_region, *pt_region;
 	bool continue_test = true;
-	uint64_t pte_gpa, pte_pg;
+	u64 pte_gpa, pte_pg;
 
 	data_region = vm_get_mem_region(vm, MEM_REGION_TEST_DATA);
 	pt_region = vm_get_mem_region(vm, MEM_REGION_PT);
@@ -510,7 +510,7 @@ void fail_vcpu_run_mmio_no_syndrome_handler(int ret)
 	events.fail_vcpu_runs += 1;
 }
 
-typedef uint32_t aarch64_insn_t;
+typedef u32 aarch64_insn_t;
 extern aarch64_insn_t __exec_test[2];
 
 noinline void __return_0x77(void)
@@ -525,7 +525,7 @@ noinline void __return_0x77(void)
  */
 static void load_exec_code_for_test(struct kvm_vm *vm)
 {
-	uint64_t *code;
+	u64 *code;
 	struct userspace_mem_region *region;
 	void *hva;
 
@@ -552,7 +552,7 @@ static void setup_abort_handlers(struct kvm_vm *vm, struct kvm_vcpu *vcpu,
 static void setup_gva_maps(struct kvm_vm *vm)
 {
 	struct userspace_mem_region *region;
-	uint64_t pte_gpa;
+	u64 pte_gpa;
 
 	region = vm_get_mem_region(vm, MEM_REGION_TEST_DATA);
 	/* Map TEST_GVA first. This will install a new PTE. */
@@ -574,12 +574,12 @@ enum pf_test_memslots {
  */
 static void setup_memslots(struct kvm_vm *vm, struct test_params *p)
 {
-	uint64_t backing_src_pagesz = get_backing_src_pagesz(p->src_type);
-	uint64_t guest_page_size = vm->page_size;
-	uint64_t max_gfn = vm_compute_max_gfn(vm);
+	u64 backing_src_pagesz = get_backing_src_pagesz(p->src_type);
+	u64 guest_page_size = vm->page_size;
+	u64 max_gfn = vm_compute_max_gfn(vm);
 	/* Enough for 2M of code when using 4K guest pages. */
-	uint64_t code_npages = 512;
-	uint64_t pt_size, data_size, data_gpa;
+	u64 code_npages = 512;
+	u64 pt_size, data_size, data_gpa;
 
 	/*
 	 * This test requires 1 pgd, 2 pud, 4 pmd, and 6 pte pages when using
diff --git a/tools/testing/selftests/kvm/arm64/psci_test.c b/tools/testing/selftests/kvm/arm64/psci_test.c
index 98e49f710aef..e775faf20868 100644
--- a/tools/testing/selftests/kvm/arm64/psci_test.c
+++ b/tools/testing/selftests/kvm/arm64/psci_test.c
@@ -22,8 +22,7 @@
 #define CPU_ON_ENTRY_ADDR 0xfeedf00dul
 #define CPU_ON_CONTEXT_ID 0xdeadc0deul
 
-static uint64_t psci_cpu_on(uint64_t target_cpu, uint64_t entry_addr,
-			    uint64_t context_id)
+static u64 psci_cpu_on(u64 target_cpu, u64 entry_addr, u64 context_id)
 {
 	struct arm_smccc_res res;
 
@@ -33,8 +32,7 @@ static uint64_t psci_cpu_on(uint64_t target_cpu, uint64_t entry_addr,
 	return res.a0;
 }
 
-static uint64_t psci_affinity_info(uint64_t target_affinity,
-				   uint64_t lowest_affinity_level)
+static u64 psci_affinity_info(u64 target_affinity, u64 lowest_affinity_level)
 {
 	struct arm_smccc_res res;
 
@@ -44,7 +42,7 @@ static uint64_t psci_affinity_info(uint64_t target_affinity,
 	return res.a0;
 }
 
-static uint64_t psci_system_suspend(uint64_t entry_addr, uint64_t context_id)
+static u64 psci_system_suspend(u64 entry_addr, u64 context_id)
 {
 	struct arm_smccc_res res;
 
@@ -54,7 +52,7 @@ static uint64_t psci_system_suspend(uint64_t entry_addr, uint64_t context_id)
 	return res.a0;
 }
 
-static uint64_t psci_system_off2(uint64_t type, uint64_t cookie)
+static u64 psci_system_off2(u64 type, u64 cookie)
 {
 	struct arm_smccc_res res;
 
@@ -63,7 +61,7 @@ static uint64_t psci_system_off2(uint64_t type, uint64_t cookie)
 	return res.a0;
 }
 
-static uint64_t psci_features(uint32_t func_id)
+static u64 psci_features(u32 func_id)
 {
 	struct arm_smccc_res res;
 
@@ -110,7 +108,7 @@ static void enter_guest(struct kvm_vcpu *vcpu)
 
 static void assert_vcpu_reset(struct kvm_vcpu *vcpu)
 {
-	uint64_t obs_pc, obs_x0;
+	u64 obs_pc, obs_x0;
 
 	obs_pc = vcpu_get_reg(vcpu, ARM64_CORE_REG(regs.pc));
 	obs_x0 = vcpu_get_reg(vcpu, ARM64_CORE_REG(regs.regs[0]));
@@ -123,9 +121,9 @@ static void assert_vcpu_reset(struct kvm_vcpu *vcpu)
 		    obs_x0, CPU_ON_CONTEXT_ID);
 }
 
-static void guest_test_cpu_on(uint64_t target_cpu)
+static void guest_test_cpu_on(u64 target_cpu)
 {
-	uint64_t target_state;
+	u64 target_state;
 
 	GUEST_ASSERT(!psci_cpu_on(target_cpu, CPU_ON_ENTRY_ADDR, CPU_ON_CONTEXT_ID));
 
@@ -142,7 +140,7 @@ static void guest_test_cpu_on(uint64_t target_cpu)
 static void host_test_cpu_on(void)
 {
 	struct kvm_vcpu *source, *target;
-	uint64_t target_mpidr;
+	u64 target_mpidr;
 	struct kvm_vm *vm;
 	struct ucall uc;
 
@@ -166,7 +164,7 @@ static void host_test_cpu_on(void)
 
 static void guest_test_system_suspend(void)
 {
-	uint64_t ret;
+	u64 ret;
 
 	/* assert that SYSTEM_SUSPEND is discoverable */
 	GUEST_ASSERT(!psci_features(PSCI_1_0_FN_SYSTEM_SUSPEND));
@@ -200,7 +198,7 @@ static void host_test_system_suspend(void)
 
 static void guest_test_system_off2(void)
 {
-	uint64_t ret;
+	u64 ret;
 
 	/* assert that SYSTEM_OFF2 is discoverable */
 	GUEST_ASSERT(psci_features(PSCI_1_3_FN_SYSTEM_OFF2) &
@@ -238,7 +236,7 @@ static void host_test_system_off2(void)
 {
 	struct kvm_vcpu *source, *target;
 	struct kvm_mp_state mps;
-	uint64_t psci_version = 0;
+	u64 psci_version = 0;
 	int nr_shutdowns = 0;
 	struct kvm_run *run;
 	struct ucall uc;
diff --git a/tools/testing/selftests/kvm/arm64/sea_to_user.c b/tools/testing/selftests/kvm/arm64/sea_to_user.c
index 573dd790aeb8..e96d8982c28b 100644
--- a/tools/testing/selftests/kvm/arm64/sea_to_user.c
+++ b/tools/testing/selftests/kvm/arm64/sea_to_user.c
@@ -51,18 +51,16 @@
 #define EINJ_OFFSET		0x01234badUL
 #define EINJ_GVA		((START_GVA) + (EINJ_OFFSET))
 
-static vm_paddr_t einj_gpa;
+static gpa_t einj_gpa;
 static void *einj_hva;
-static uint64_t einj_hpa;
+static u64 einj_hpa;
 static bool far_invalid;
 
-static uint64_t translate_to_host_paddr(unsigned long vaddr)
+static u64 translate_hva_to_hpa(unsigned long hva)
 {
-	uint64_t pinfo;
-	int64_t offset = vaddr / getpagesize() * sizeof(pinfo);
+	u64 pinfo;
+	s64 offset = hva / getpagesize() * sizeof(pinfo);
 	int fd;
-	uint64_t page_addr;
-	uint64_t paddr;
 
 	fd = open("/proc/self/pagemap", O_RDONLY);
 	if (fd < 0)
@@ -77,12 +75,11 @@ static uint64_t translate_to_host_paddr(unsigned long vaddr)
 	if ((pinfo & PAGE_PRESENT) == 0)
 		ksft_exit_fail_perror("Page not present");
 
-	page_addr = (pinfo & PAGE_PHYSICAL) << MIN_PAGE_SHIFT;
-	paddr = page_addr + (vaddr & (getpagesize() - 1));
-	return paddr;
+	return ((pinfo & PAGE_PHYSICAL) << MIN_PAGE_SHIFT) +
+	       (hva & (getpagesize() - 1));
 }
 
-static void write_einj_entry(const char *einj_path, uint64_t val)
+static void write_einj_entry(const char *einj_path, u64 val)
 {
 	char cmd[256] = {0};
 	FILE *cmdfile = NULL;
@@ -96,7 +93,7 @@ static void write_einj_entry(const char *einj_path, uint64_t val)
 		ksft_exit_fail_perror("Failed to write EINJ entry");
 }
 
-static void inject_uer(uint64_t paddr)
+static void inject_uer(u64 hpa)
 {
 	if (access("/sys/firmware/acpi/tables/EINJ", R_OK) == -1)
 		ksft_test_result_skip("EINJ table no available in firmware");
@@ -106,7 +103,7 @@ static void inject_uer(uint64_t paddr)
 
 	write_einj_entry(EINJ_ETYPE, ERROR_TYPE_MEMORY_UER);
 	write_einj_entry(EINJ_FLAGS, MASK_MEMORY_UER);
-	write_einj_entry(EINJ_ADDR, paddr);
+	write_einj_entry(EINJ_ADDR, hpa);
 	write_einj_entry(EINJ_MASK, ~0x0UL);
 	write_einj_entry(EINJ_NOTRIGGER, 1);
 	write_einj_entry(EINJ_DOIT, 1);
@@ -145,10 +142,10 @@ static void setup_sigbus_handler(void)
 
 static void guest_code(void)
 {
-	uint64_t guest_data;
+	u64 guest_data;
 
 	/* Consumes error will cause a SEA. */
-	guest_data = *(uint64_t *)EINJ_GVA;
+	guest_data = *(u64 *)EINJ_GVA;
 
 	GUEST_FAIL("Poison not protected by SEA: gva=%#lx, guest_data=%#lx\n",
 		   EINJ_GVA, guest_data);
@@ -253,8 +250,8 @@ static struct kvm_vm *vm_create_with_sea_handler(struct kvm_vcpu **vcpu)
 	size_t backing_page_size;
 	size_t guest_page_size;
 	size_t alignment;
-	uint64_t num_guest_pages;
-	vm_paddr_t start_gpa;
+	u64 num_guest_pages;
+	gpa_t start_gpa;
 	enum vm_mem_backing_src_type src_type = VM_MEM_SRC_ANONYMOUS_HUGETLB_1GB;
 	struct kvm_vm *vm;
 
@@ -278,7 +275,7 @@ static struct kvm_vm *vm_create_with_sea_handler(struct kvm_vcpu **vcpu)
 	vm_userspace_mem_region_add(
 		/*vm=*/vm,
 		/*src_type=*/src_type,
-		/*guest_paddr=*/start_gpa,
+		/*gpa=*/start_gpa,
 		/*slot=*/1,
 		/*npages=*/num_guest_pages,
 		/*flags=*/0);
@@ -292,18 +289,18 @@ static struct kvm_vm *vm_create_with_sea_handler(struct kvm_vcpu **vcpu)
 
 static void vm_inject_memory_uer(struct kvm_vm *vm)
 {
-	uint64_t guest_data;
+	u64 guest_data;
 
 	einj_gpa = addr_gva2gpa(vm, EINJ_GVA);
 	einj_hva = addr_gva2hva(vm, EINJ_GVA);
 
 	/* Populate certain data before injecting UER. */
-	*(uint64_t *)einj_hva = 0xBAADCAFE;
-	guest_data = *(uint64_t *)einj_hva;
+	*(u64 *)einj_hva = 0xBAADCAFE;
+	guest_data = *(u64 *)einj_hva;
 	ksft_print_msg("Before EINJect: data=%#lx\n",
 		guest_data);
 
-	einj_hpa = translate_to_host_paddr((unsigned long)einj_hva);
+	einj_hpa = translate_hva_to_hpa((unsigned long)einj_hva);
 
 	ksft_print_msg("EINJ_GVA=%#lx, einj_gpa=%#lx, einj_hva=%p, einj_hpa=%#lx\n",
 		       EINJ_GVA, einj_gpa, einj_hva, einj_hpa);
diff --git a/tools/testing/selftests/kvm/arm64/set_id_regs.c b/tools/testing/selftests/kvm/arm64/set_id_regs.c
index 3a7e5fe9ae7a..7429a1055df5 100644
--- a/tools/testing/selftests/kvm/arm64/set_id_regs.c
+++ b/tools/testing/selftests/kvm/arm64/set_id_regs.c
@@ -30,20 +30,20 @@ struct reg_ftr_bits {
 	char *name;
 	bool sign;
 	enum ftr_type type;
-	uint8_t shift;
-	uint64_t mask;
+	u8 shift;
+	u64 mask;
 	/*
 	 * For FTR_EXACT, safe_val is used as the exact safe value.
 	 * For FTR_LOWER_SAFE, safe_val is used as the minimal safe value.
 	 */
-	int64_t safe_val;
+	s64 safe_val;
 
 	/* Allowed to be changed by the host after run */
 	bool mutable;
 };
 
 struct test_feature_reg {
-	uint32_t reg;
+	u32 reg;
 	const struct reg_ftr_bits *ftr_bits;
 };
 
@@ -275,9 +275,9 @@ static void guest_code(void)
 }
 
 /* Return a safe value to a given ftr_bits an ftr value */
-uint64_t get_safe_value(const struct reg_ftr_bits *ftr_bits, uint64_t ftr)
+u64 get_safe_value(const struct reg_ftr_bits *ftr_bits, u64 ftr)
 {
-	uint64_t ftr_max = ftr_bits->mask >> ftr_bits->shift;
+	u64 ftr_max = ftr_bits->mask >> ftr_bits->shift;
 
 	TEST_ASSERT(ftr_max > 1, "This test doesn't support single bit features");
 
@@ -329,16 +329,16 @@ uint64_t get_safe_value(const struct reg_ftr_bits *ftr_bits, uint64_t ftr)
 }
 
 /* Return an invalid value to a given ftr_bits an ftr value */
-uint64_t get_invalid_value(const struct reg_ftr_bits *ftr_bits, uint64_t ftr)
+u64 get_invalid_value(const struct reg_ftr_bits *ftr_bits, u64 ftr)
 {
-	uint64_t ftr_max = ftr_bits->mask >> ftr_bits->shift;
+	u64 ftr_max = ftr_bits->mask >> ftr_bits->shift;
 
 	TEST_ASSERT(ftr_max > 1, "This test doesn't support single bit features");
 
 	if (ftr_bits->sign == FTR_UNSIGNED) {
 		switch (ftr_bits->type) {
 		case FTR_EXACT:
-			ftr = max((uint64_t)ftr_bits->safe_val + 1, ftr + 1);
+			ftr = max((u64)ftr_bits->safe_val + 1, ftr + 1);
 			break;
 		case FTR_LOWER_SAFE:
 			ftr++;
@@ -358,7 +358,7 @@ uint64_t get_invalid_value(const struct reg_ftr_bits *ftr_bits, uint64_t ftr)
 	} else if (ftr != ftr_max) {
 		switch (ftr_bits->type) {
 		case FTR_EXACT:
-			ftr = max((uint64_t)ftr_bits->safe_val + 1, ftr + 1);
+			ftr = max((u64)ftr_bits->safe_val + 1, ftr + 1);
 			break;
 		case FTR_LOWER_SAFE:
 			ftr++;
@@ -382,12 +382,12 @@ uint64_t get_invalid_value(const struct reg_ftr_bits *ftr_bits, uint64_t ftr)
 	return ftr;
 }
 
-static uint64_t test_reg_set_success(struct kvm_vcpu *vcpu, uint64_t reg,
-				     const struct reg_ftr_bits *ftr_bits)
+static u64 test_reg_set_success(struct kvm_vcpu *vcpu, u64 reg,
+				const struct reg_ftr_bits *ftr_bits)
 {
-	uint8_t shift = ftr_bits->shift;
-	uint64_t mask = ftr_bits->mask;
-	uint64_t val, new_val, ftr;
+	u8 shift = ftr_bits->shift;
+	u64 mask = ftr_bits->mask;
+	u64 val, new_val, ftr;
 
 	val = vcpu_get_reg(vcpu, reg);
 	ftr = (val & mask) >> shift;
@@ -405,12 +405,12 @@ static uint64_t test_reg_set_success(struct kvm_vcpu *vcpu, uint64_t reg,
 	return new_val;
 }
 
-static void test_reg_set_fail(struct kvm_vcpu *vcpu, uint64_t reg,
+static void test_reg_set_fail(struct kvm_vcpu *vcpu, u64 reg,
 			      const struct reg_ftr_bits *ftr_bits)
 {
-	uint8_t shift = ftr_bits->shift;
-	uint64_t mask = ftr_bits->mask;
-	uint64_t val, old_val, ftr;
+	u8 shift = ftr_bits->shift;
+	u64 mask = ftr_bits->mask;
+	u64 val, old_val, ftr;
 	int r;
 
 	val = vcpu_get_reg(vcpu, reg);
@@ -431,7 +431,7 @@ static void test_reg_set_fail(struct kvm_vcpu *vcpu, uint64_t reg,
 	TEST_ASSERT_EQ(val, old_val);
 }
 
-static uint64_t test_reg_vals[KVM_ARM_FEATURE_ID_RANGE_SIZE];
+static u64 test_reg_vals[KVM_ARM_FEATURE_ID_RANGE_SIZE];
 
 #define encoding_to_range_idx(encoding)							\
 	KVM_ARM_FEATURE_ID_RANGE_IDX(sys_reg_Op0(encoding), sys_reg_Op1(encoding),	\
@@ -441,7 +441,7 @@ static uint64_t test_reg_vals[KVM_ARM_FEATURE_ID_RANGE_SIZE];
 
 static void test_vm_ftr_id_regs(struct kvm_vcpu *vcpu, bool aarch64_only)
 {
-	uint64_t masks[KVM_ARM_FEATURE_ID_RANGE_SIZE];
+	u64 masks[KVM_ARM_FEATURE_ID_RANGE_SIZE];
 	struct reg_mask_range range = {
 		.addr = (__u64)masks,
 	};
@@ -458,8 +458,8 @@ static void test_vm_ftr_id_regs(struct kvm_vcpu *vcpu, bool aarch64_only)
 
 	for (int i = 0; i < ARRAY_SIZE(test_regs); i++) {
 		const struct reg_ftr_bits *ftr_bits = test_regs[i].ftr_bits;
-		uint32_t reg_id = test_regs[i].reg;
-		uint64_t reg = KVM_ARM64_SYS_REG(reg_id);
+		u32 reg_id = test_regs[i].reg;
+		u64 reg = KVM_ARM64_SYS_REG(reg_id);
 		int idx;
 
 		/* Get the index to masks array for the idreg */
@@ -489,11 +489,11 @@ static void test_vm_ftr_id_regs(struct kvm_vcpu *vcpu, bool aarch64_only)
 #define MPAM_IDREG_TEST	6
 static void test_user_set_mpam_reg(struct kvm_vcpu *vcpu)
 {
-	uint64_t masks[KVM_ARM_FEATURE_ID_RANGE_SIZE];
+	u64 masks[KVM_ARM_FEATURE_ID_RANGE_SIZE];
 	struct reg_mask_range range = {
 		.addr = (__u64)masks,
 	};
-	uint64_t val;
+	u64 val;
 	int idx, err;
 
 	/*
@@ -584,13 +584,13 @@ static void test_user_set_mpam_reg(struct kvm_vcpu *vcpu)
 #define MTE_IDREG_TEST 1
 static void test_user_set_mte_reg(struct kvm_vcpu *vcpu)
 {
-	uint64_t masks[KVM_ARM_FEATURE_ID_RANGE_SIZE];
+	u64 masks[KVM_ARM_FEATURE_ID_RANGE_SIZE];
 	struct reg_mask_range range = {
 		.addr = (__u64)masks,
 	};
-	uint64_t val;
-	uint64_t mte;
-	uint64_t mte_frac;
+	u64 val;
+	u64 mte;
+	u64 mte_frac;
 	int idx, err;
 
 	val = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_ID_AA64PFR1_EL1));
@@ -644,7 +644,7 @@ static void test_user_set_mte_reg(struct kvm_vcpu *vcpu)
 		ksft_test_result_pass("ID_AA64PFR1_EL1.MTE_frac no longer 0xF\n");
 }
 
-static uint64_t reset_mutable_bits(uint32_t id, uint64_t val)
+static u64 reset_mutable_bits(u32 id, u64 val)
 {
 	struct test_feature_reg *reg = NULL;
 
@@ -674,7 +674,7 @@ static void test_guest_reg_read(struct kvm_vcpu *vcpu)
 	struct ucall uc;
 
 	while (!done) {
-		uint64_t val;
+		u64 val;
 
 		vcpu_run(vcpu);
 
@@ -707,7 +707,7 @@ static void test_guest_reg_read(struct kvm_vcpu *vcpu)
 
 static void test_clidr(struct kvm_vcpu *vcpu)
 {
-	uint64_t clidr;
+	u64 clidr;
 	int level;
 
 	clidr = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(SYS_CLIDR_EL1));
@@ -772,10 +772,10 @@ static void test_vcpu_non_ftr_id_regs(struct kvm_vcpu *vcpu)
 	ksft_test_result_pass("%s\n", __func__);
 }
 
-static void test_assert_id_reg_unchanged(struct kvm_vcpu *vcpu, uint32_t encoding)
+static void test_assert_id_reg_unchanged(struct kvm_vcpu *vcpu, u32 encoding)
 {
 	size_t idx = encoding_to_range_idx(encoding);
-	uint64_t observed;
+	u64 observed;
 
 	observed = vcpu_get_reg(vcpu, KVM_ARM64_SYS_REG(encoding));
 	TEST_ASSERT_EQ(reset_mutable_bits(encoding, test_reg_vals[idx]),
@@ -808,7 +808,7 @@ int main(void)
 	struct kvm_vcpu *vcpu;
 	struct kvm_vm *vm;
 	bool aarch64_only;
-	uint64_t val, el0;
+	u64 val, el0;
 	int test_cnt, i, j;
 
 	TEST_REQUIRE(kvm_has_cap(KVM_CAP_ARM_SUPPORTED_REG_MASK_RANGES));
diff --git a/tools/testing/selftests/kvm/arm64/smccc_filter.c b/tools/testing/selftests/kvm/arm64/smccc_filter.c
index 1763b9d45400..21e41880261b 100644
--- a/tools/testing/selftests/kvm/arm64/smccc_filter.c
+++ b/tools/testing/selftests/kvm/arm64/smccc_filter.c
@@ -37,7 +37,7 @@ static bool test_runs_at_el2(void)
 	for (conduit = test_runs_at_el2() ? SMC_INSN : HVC_INSN;	\
 	     conduit <= SMC_INSN; conduit++)
 
-static void guest_main(uint32_t func_id, enum smccc_conduit conduit)
+static void guest_main(u32 func_id, enum smccc_conduit conduit)
 {
 	struct arm_smccc_res res;
 
@@ -49,7 +49,7 @@ static void guest_main(uint32_t func_id, enum smccc_conduit conduit)
 	GUEST_SYNC(res.a0);
 }
 
-static int __set_smccc_filter(struct kvm_vm *vm, uint32_t start, uint32_t nr_functions,
+static int __set_smccc_filter(struct kvm_vm *vm, u32 start, u32 nr_functions,
 			      enum kvm_smccc_filter_action action)
 {
 	struct kvm_smccc_filter filter = {
@@ -62,7 +62,7 @@ static int __set_smccc_filter(struct kvm_vm *vm, uint32_t start, uint32_t nr_fun
 				     KVM_ARM_VM_SMCCC_FILTER, &filter);
 }
 
-static void set_smccc_filter(struct kvm_vm *vm, uint32_t start, uint32_t nr_functions,
+static void set_smccc_filter(struct kvm_vm *vm, u32 start, u32 nr_functions,
 			     enum kvm_smccc_filter_action action)
 {
 	int ret = __set_smccc_filter(vm, start, nr_functions, action);
@@ -112,7 +112,7 @@ static void test_filter_reserved_range(void)
 {
 	struct kvm_vcpu *vcpu;
 	struct kvm_vm *vm = setup_vm(&vcpu);
-	uint32_t smc64_fn;
+	u32 smc64_fn;
 	int r;
 
 	r = __set_smccc_filter(vm, ARM_SMCCC_ARCH_WORKAROUND_1,
@@ -217,7 +217,7 @@ static void test_filter_denied(void)
 	}
 }
 
-static void expect_call_fwd_to_user(struct kvm_vcpu *vcpu, uint32_t func_id,
+static void expect_call_fwd_to_user(struct kvm_vcpu *vcpu, u32 func_id,
 				    enum smccc_conduit conduit)
 {
 	struct kvm_run *run = vcpu->run;
diff --git a/tools/testing/selftests/kvm/arm64/vgic_init.c b/tools/testing/selftests/kvm/arm64/vgic_init.c
index 8d6d3a4ae4db..47e34b43afb2 100644
--- a/tools/testing/selftests/kvm/arm64/vgic_init.c
+++ b/tools/testing/selftests/kvm/arm64/vgic_init.c
@@ -19,7 +19,7 @@
 
 #define NR_VCPUS		4
 
-#define REG_OFFSET(vcpu, offset) (((uint64_t)vcpu << 32) | offset)
+#define REG_OFFSET(vcpu, offset) (((u64)vcpu << 32) | offset)
 
 #define VGIC_DEV_IS_V2(_d) ((_d) == KVM_DEV_TYPE_ARM_VGIC_V2)
 #define VGIC_DEV_IS_V3(_d) ((_d) == KVM_DEV_TYPE_ARM_VGIC_V3)
@@ -27,10 +27,10 @@
 struct vm_gic {
 	struct kvm_vm *vm;
 	int gic_fd;
-	uint32_t gic_dev_type;
+	u32 gic_dev_type;
 };
 
-static uint64_t max_phys_size;
+static u64 max_phys_size;
 
 /*
  * Helpers to access a redistributor register and verify the ioctl() failed or
@@ -39,17 +39,17 @@ static uint64_t max_phys_size;
 static void v3_redist_reg_get_errno(int gicv3_fd, int vcpu, int offset,
 				    int want, const char *msg)
 {
-	uint32_t ignored_val;
+	u32 ignored_val;
 	int ret = __kvm_device_attr_get(gicv3_fd, KVM_DEV_ARM_VGIC_GRP_REDIST_REGS,
 					REG_OFFSET(vcpu, offset), &ignored_val);
 
 	TEST_ASSERT(ret && errno == want, "%s; want errno = %d", msg, want);
 }
 
-static void v3_redist_reg_get(int gicv3_fd, int vcpu, int offset, uint32_t want,
+static void v3_redist_reg_get(int gicv3_fd, int vcpu, int offset, u32 want,
 			      const char *msg)
 {
-	uint32_t val;
+	u32 val;
 
 	kvm_device_attr_get(gicv3_fd, KVM_DEV_ARM_VGIC_GRP_REDIST_REGS,
 			    REG_OFFSET(vcpu, offset), &val);
@@ -71,8 +71,8 @@ static int run_vcpu(struct kvm_vcpu *vcpu)
 	return __vcpu_run(vcpu) ? -errno : 0;
 }
 
-static struct vm_gic vm_gic_create_with_vcpus(uint32_t gic_dev_type,
-					      uint32_t nr_vcpus,
+static struct vm_gic vm_gic_create_with_vcpus(u32 gic_dev_type,
+					      u32 nr_vcpus,
 					      struct kvm_vcpu *vcpus[])
 {
 	struct vm_gic v;
@@ -84,7 +84,7 @@ static struct vm_gic vm_gic_create_with_vcpus(uint32_t gic_dev_type,
 	return v;
 }
 
-static struct vm_gic vm_gic_create_barebones(uint32_t gic_dev_type)
+static struct vm_gic vm_gic_create_barebones(u32 gic_dev_type)
 {
 	struct vm_gic v;
 
@@ -103,9 +103,9 @@ static void vm_gic_destroy(struct vm_gic *v)
 }
 
 struct vgic_region_attr {
-	uint64_t attr;
-	uint64_t size;
-	uint64_t alignment;
+	u64 attr;
+	u64 size;
+	u64 alignment;
 };
 
 struct vgic_region_attr gic_v3_dist_region = {
@@ -143,7 +143,7 @@ struct vgic_region_attr gic_v2_cpu_region = {
 static void subtest_dist_rdist(struct vm_gic *v)
 {
 	int ret;
-	uint64_t addr;
+	u64 addr;
 	struct vgic_region_attr rdist; /* CPU interface in GICv2*/
 	struct vgic_region_attr dist;
 
@@ -223,7 +223,7 @@ static void subtest_dist_rdist(struct vm_gic *v)
 /* Test the new REDIST region API */
 static void subtest_v3_redist_regions(struct vm_gic *v)
 {
-	uint64_t addr, expected_addr;
+	u64 addr, expected_addr;
 	int ret;
 
 	ret = __kvm_has_device_attr(v->gic_fd, KVM_DEV_ARM_VGIC_GRP_ADDR,
@@ -332,7 +332,7 @@ static void subtest_v3_redist_regions(struct vm_gic *v)
  * VGIC KVM device is created and initialized before the secondary CPUs
  * get created
  */
-static void test_vgic_then_vcpus(uint32_t gic_dev_type)
+static void test_vgic_then_vcpus(u32 gic_dev_type)
 {
 	struct kvm_vcpu *vcpus[NR_VCPUS];
 	struct vm_gic v;
@@ -353,7 +353,7 @@ static void test_vgic_then_vcpus(uint32_t gic_dev_type)
 }
 
 /* All the VCPUs are created before the VGIC KVM device gets initialized */
-static void test_vcpus_then_vgic(uint32_t gic_dev_type)
+static void test_vcpus_then_vgic(u32 gic_dev_type)
 {
 	struct kvm_vcpu *vcpus[NR_VCPUS];
 	struct vm_gic v;
@@ -408,7 +408,7 @@ static void test_v3_new_redist_regions(void)
 	struct kvm_vcpu *vcpus[NR_VCPUS];
 	void *dummy = NULL;
 	struct vm_gic v;
-	uint64_t addr;
+	u64 addr;
 	int ret;
 
 	v = vm_gic_create_with_vcpus(KVM_DEV_TYPE_ARM_VGIC_V3, NR_VCPUS, vcpus);
@@ -460,7 +460,7 @@ static void test_v3_new_redist_regions(void)
 static void test_v3_typer_accesses(void)
 {
 	struct vm_gic v;
-	uint64_t addr;
+	u64 addr;
 	int ret, i;
 
 	v.vm = vm_create(NR_VCPUS);
@@ -518,7 +518,7 @@ static void test_v3_typer_accesses(void)
 }
 
 static struct vm_gic vm_gic_v3_create_with_vcpuids(int nr_vcpus,
-						   uint32_t vcpuids[])
+						   u32 vcpuids[])
 {
 	struct vm_gic v;
 	int i;
@@ -544,9 +544,9 @@ static struct vm_gic vm_gic_v3_create_with_vcpuids(int nr_vcpus,
  */
 static void test_v3_last_bit_redist_regions(void)
 {
-	uint32_t vcpuids[] = { 0, 3, 5, 4, 1, 2 };
+	u32 vcpuids[] = { 0, 3, 5, 4, 1, 2 };
 	struct vm_gic v;
-	uint64_t addr;
+	u64 addr;
 
 	v = vm_gic_v3_create_with_vcpuids(ARRAY_SIZE(vcpuids), vcpuids);
 
@@ -578,9 +578,9 @@ static void test_v3_last_bit_redist_regions(void)
 /* Test last bit with legacy region */
 static void test_v3_last_bit_single_rdist(void)
 {
-	uint32_t vcpuids[] = { 0, 3, 5, 4, 1, 2 };
+	u32 vcpuids[] = { 0, 3, 5, 4, 1, 2 };
 	struct vm_gic v;
-	uint64_t addr;
+	u64 addr;
 
 	v = vm_gic_v3_create_with_vcpuids(ARRAY_SIZE(vcpuids), vcpuids);
 
@@ -606,7 +606,7 @@ static void test_v3_redist_ipa_range_check_at_vcpu_run(void)
 	struct kvm_vcpu *vcpus[NR_VCPUS];
 	struct vm_gic v;
 	int ret, i;
-	uint64_t addr;
+	u64 addr;
 
 	v = vm_gic_create_with_vcpus(KVM_DEV_TYPE_ARM_VGIC_V3, 1, vcpus);
 
@@ -638,7 +638,7 @@ static void test_v3_its_region(void)
 {
 	struct kvm_vcpu *vcpus[NR_VCPUS];
 	struct vm_gic v;
-	uint64_t addr;
+	u64 addr;
 	int its_fd, ret;
 
 	v = vm_gic_create_with_vcpus(KVM_DEV_TYPE_ARM_VGIC_V3, NR_VCPUS, vcpus);
@@ -717,11 +717,11 @@ static void test_v3_nassgicap(void)
 /*
  * Returns 0 if it's possible to create GIC device of a given type (V2 or V3).
  */
-int test_kvm_device(uint32_t gic_dev_type)
+int test_kvm_device(u32 gic_dev_type)
 {
 	struct kvm_vcpu *vcpus[NR_VCPUS];
 	struct vm_gic v;
-	uint32_t other;
+	u32 other;
 	int ret;
 
 	v.vm = vm_create_with_vcpus(NR_VCPUS, guest_code, vcpus);
@@ -968,7 +968,7 @@ static void test_v3_sysregs(void)
 	kvm_vm_free(vm);
 }
 
-void run_tests(uint32_t gic_dev_type)
+void run_tests(u32 gic_dev_type)
 {
 	test_vcpus_then_vgic(gic_dev_type);
 	test_vgic_then_vcpus(gic_dev_type);
diff --git a/tools/testing/selftests/kvm/arm64/vgic_irq.c b/tools/testing/selftests/kvm/arm64/vgic_irq.c
index 2fb2c7939fe9..5e231998617e 100644
--- a/tools/testing/selftests/kvm/arm64/vgic_irq.c
+++ b/tools/testing/selftests/kvm/arm64/vgic_irq.c
@@ -24,12 +24,12 @@
  * function.
  */
 struct test_args {
-	uint32_t nr_irqs; /* number of KVM supported IRQs. */
+	u32 nr_irqs; /* number of KVM supported IRQs. */
 	bool eoi_split; /* 1 is eoir+dir, 0 is eoir only */
 	bool level_sensitive; /* 1 is level, 0 is edge */
 	int kvm_max_routes; /* output of KVM_CAP_IRQ_ROUTING */
 	bool kvm_supports_irqfd; /* output of KVM_CAP_IRQFD */
-	uint32_t shared_data;
+	u32 shared_data;
 };
 
 /*
@@ -64,15 +64,15 @@ typedef enum {
 
 struct kvm_inject_args {
 	kvm_inject_cmd cmd;
-	uint32_t first_intid;
-	uint32_t num;
+	u32 first_intid;
+	u32 num;
 	int level;
 	bool expect_failure;
 };
 
 /* Used on the guest side to perform the hypercall. */
-static void kvm_inject_call(kvm_inject_cmd cmd, uint32_t first_intid,
-		uint32_t num, int level, bool expect_failure);
+static void kvm_inject_call(kvm_inject_cmd cmd, u32 first_intid,
+			    u32 num, int level, bool expect_failure);
 
 /* Used on the host side to get the hypercall info. */
 static void kvm_inject_get_call(struct kvm_vm *vm, struct ucall *uc,
@@ -133,8 +133,8 @@ static struct kvm_inject_desc set_active_fns[] = {
 	for_each_supported_inject_fn((args), (t), (f))
 
 /* Shared between the guest main thread and the IRQ handlers. */
-volatile uint64_t irq_handled;
-volatile uint32_t irqnr_received[MAX_SPI + 1];
+volatile u64 irq_handled;
+volatile u32 irqnr_received[MAX_SPI + 1];
 
 static void reset_stats(void)
 {
@@ -145,25 +145,25 @@ static void reset_stats(void)
 		irqnr_received[i] = 0;
 }
 
-static uint64_t gic_read_ap1r0(void)
+static u64 gic_read_ap1r0(void)
 {
-	uint64_t reg = read_sysreg_s(SYS_ICC_AP1R0_EL1);
+	u64 reg = read_sysreg_s(SYS_ICC_AP1R0_EL1);
 
 	dsb(sy);
 	return reg;
 }
 
-static void gic_write_ap1r0(uint64_t val)
+static void gic_write_ap1r0(u64 val)
 {
 	write_sysreg_s(val, SYS_ICC_AP1R0_EL1);
 	isb();
 }
 
-static void guest_set_irq_line(uint32_t intid, uint32_t level);
+static void guest_set_irq_line(u32 intid, u32 level);
 
 static void guest_irq_generic_handler(bool eoi_split, bool level_sensitive)
 {
-	uint32_t intid = gic_get_and_ack_irq();
+	u32 intid = gic_get_and_ack_irq();
 
 	if (intid == IAR_SPURIOUS)
 		return;
@@ -189,8 +189,8 @@ static void guest_irq_generic_handler(bool eoi_split, bool level_sensitive)
 	GUEST_ASSERT(!gic_irq_get_pending(intid));
 }
 
-static void kvm_inject_call(kvm_inject_cmd cmd, uint32_t first_intid,
-		uint32_t num, int level, bool expect_failure)
+static void kvm_inject_call(kvm_inject_cmd cmd, u32 first_intid,
+			    u32 num, int level, bool expect_failure)
 {
 	struct kvm_inject_args args = {
 		.cmd = cmd,
@@ -204,7 +204,7 @@ static void kvm_inject_call(kvm_inject_cmd cmd, uint32_t first_intid,
 
 #define GUEST_ASSERT_IAR_EMPTY()						\
 do { 										\
-	uint32_t _intid;							\
+	u32 _intid;							\
 	_intid = gic_get_and_ack_irq();						\
 	GUEST_ASSERT(_intid == IAR_SPURIOUS);					\
 } while (0)
@@ -237,13 +237,13 @@ static void reset_priorities(struct test_args *args)
 		gic_set_priority(i, IRQ_DEFAULT_PRIO_REG);
 }
 
-static void guest_set_irq_line(uint32_t intid, uint32_t level)
+static void guest_set_irq_line(u32 intid, u32 level)
 {
 	kvm_inject_call(KVM_SET_IRQ_LINE, intid, 1, level, false);
 }
 
 static void test_inject_fail(struct test_args *args,
-		uint32_t intid, kvm_inject_cmd cmd)
+			     u32 intid, kvm_inject_cmd cmd)
 {
 	reset_stats();
 
@@ -255,10 +255,10 @@ static void test_inject_fail(struct test_args *args,
 }
 
 static void guest_inject(struct test_args *args,
-		uint32_t first_intid, uint32_t num,
-		kvm_inject_cmd cmd)
+			 u32 first_intid, u32 num,
+			 kvm_inject_cmd cmd)
 {
-	uint32_t i;
+	u32 i;
 
 	reset_stats();
 
@@ -292,10 +292,10 @@ static void guest_inject(struct test_args *args,
  * deactivated yet.
  */
 static void guest_restore_active(struct test_args *args,
-		uint32_t first_intid, uint32_t num,
-		kvm_inject_cmd cmd)
+				 u32 first_intid, u32 num,
+				 kvm_inject_cmd cmd)
 {
-	uint32_t prio, intid, ap1r;
+	u32 prio, intid, ap1r;
 	int i;
 
 	/*
@@ -342,9 +342,9 @@ static void guest_restore_active(struct test_args *args,
  * This function should only be used in test_inject_preemption (with IRQs
  * masked).
  */
-static uint32_t wait_for_and_activate_irq(void)
+static u32 wait_for_and_activate_irq(void)
 {
-	uint32_t intid;
+	u32 intid;
 
 	do {
 		asm volatile("wfi" : : : "memory");
@@ -360,11 +360,11 @@ static uint32_t wait_for_and_activate_irq(void)
  * interrupts for the whole test.
  */
 static void test_inject_preemption(struct test_args *args,
-				   uint32_t first_intid, int num,
+				   u32 first_intid, int num,
 				   const unsigned long *exclude,
 				   kvm_inject_cmd cmd)
 {
-	uint32_t intid, prio, step = KVM_PRIO_STEPS;
+	u32 intid, prio, step = KVM_PRIO_STEPS;
 	int i;
 
 	/* Set the priorities of the first (KVM_NUM_PRIOS - 1) IRQs
@@ -379,7 +379,7 @@ static void test_inject_preemption(struct test_args *args,
 	local_irq_disable();
 
 	for (i = 0; i < num; i++) {
-		uint32_t tmp;
+		u32 tmp;
 		intid = i + first_intid;
 
 		if (exclude && test_bit(i, exclude))
@@ -431,7 +431,7 @@ static void test_inject_preemption(struct test_args *args,
 
 static void test_injection(struct test_args *args, struct kvm_inject_desc *f)
 {
-	uint32_t nr_irqs = args->nr_irqs;
+	u32 nr_irqs = args->nr_irqs;
 
 	if (f->sgi) {
 		guest_inject(args, MIN_SGI, 1, f->cmd);
@@ -451,7 +451,7 @@ static void test_injection(struct test_args *args, struct kvm_inject_desc *f)
 static void test_injection_failure(struct test_args *args,
 		struct kvm_inject_desc *f)
 {
-	uint32_t bad_intid[] = { args->nr_irqs, 1020, 1024, 1120, 5120, ~0U, };
+	u32 bad_intid[] = { args->nr_irqs, 1020, 1024, 1120, 5120, ~0U, };
 	int i;
 
 	for (i = 0; i < ARRAY_SIZE(bad_intid); i++)
@@ -490,7 +490,7 @@ static void test_restore_active(struct test_args *args, struct kvm_inject_desc *
 
 static void guest_code(struct test_args *args)
 {
-	uint32_t i, nr_irqs = args->nr_irqs;
+	u32 i, nr_irqs = args->nr_irqs;
 	bool level_sensitive = args->level_sensitive;
 	struct kvm_inject_desc *f, *inject_fns;
 
@@ -529,8 +529,8 @@ static void guest_code(struct test_args *args)
 	GUEST_DONE();
 }
 
-static void kvm_irq_line_check(struct kvm_vm *vm, uint32_t intid, int level,
-			struct test_args *test_args, bool expect_failure)
+static void kvm_irq_line_check(struct kvm_vm *vm, u32 intid, int level,
+			       struct test_args *test_args, bool expect_failure)
 {
 	int ret;
 
@@ -548,8 +548,8 @@ static void kvm_irq_line_check(struct kvm_vm *vm, uint32_t intid, int level,
 	}
 }
 
-void kvm_irq_set_level_info_check(int gic_fd, uint32_t intid, int level,
-			bool expect_failure)
+void kvm_irq_set_level_info_check(int gic_fd, u32 intid, int level,
+				  bool expect_failure)
 {
 	if (!expect_failure) {
 		kvm_irq_set_level_info(gic_fd, intid, level);
@@ -573,17 +573,18 @@ void kvm_irq_set_level_info_check(int gic_fd, uint32_t intid, int level,
 }
 
 static void kvm_set_gsi_routing_irqchip_check(struct kvm_vm *vm,
-		uint32_t intid, uint32_t num, uint32_t kvm_max_routes,
-		bool expect_failure)
+					      u32 intid, u32 num,
+					      u32 kvm_max_routes,
+					      bool expect_failure)
 {
 	struct kvm_irq_routing *routing;
 	int ret;
-	uint64_t i;
+	u64 i;
 
 	assert(num <= kvm_max_routes && kvm_max_routes <= KVM_MAX_IRQ_ROUTES);
 
 	routing = kvm_gsi_routing_create();
-	for (i = intid; i < (uint64_t)intid + num; i++)
+	for (i = intid; i < (u64)intid + num; i++)
 		kvm_gsi_routing_irqchip_add(routing, i - MIN_SPI, i - MIN_SPI);
 
 	if (!expect_failure) {
@@ -591,7 +592,7 @@ static void kvm_set_gsi_routing_irqchip_check(struct kvm_vm *vm,
 	} else {
 		ret = _kvm_gsi_routing_write(vm, routing);
 		/* The kernel only checks e->irqchip.pin >= KVM_IRQCHIP_NUM_PINS */
-		if (((uint64_t)intid + num - 1 - MIN_SPI) >= KVM_IRQCHIP_NUM_PINS)
+		if (((u64)intid + num - 1 - MIN_SPI) >= KVM_IRQCHIP_NUM_PINS)
 			TEST_ASSERT(ret != 0 && errno == EINVAL,
 				"Bad intid %u did not cause KVM_SET_GSI_ROUTING "
 				"error: rc: %i errno: %i", intid, ret, errno);
@@ -602,7 +603,7 @@ static void kvm_set_gsi_routing_irqchip_check(struct kvm_vm *vm,
 	}
 }
 
-static void kvm_irq_write_ispendr_check(int gic_fd, uint32_t intid,
+static void kvm_irq_write_ispendr_check(int gic_fd, u32 intid,
 					struct kvm_vcpu *vcpu,
 					bool expect_failure)
 {
@@ -618,13 +619,13 @@ static void kvm_irq_write_ispendr_check(int gic_fd, uint32_t intid,
 }
 
 static void kvm_routing_and_irqfd_check(struct kvm_vm *vm,
-		uint32_t intid, uint32_t num, uint32_t kvm_max_routes,
-		bool expect_failure)
+					u32 intid, u32 num, u32 kvm_max_routes,
+					bool expect_failure)
 {
 	int fd[MAX_SPI];
-	uint64_t val;
+	u64 val;
 	int ret, f;
-	uint64_t i;
+	u64 i;
 
 	/*
 	 * There is no way to try injecting an SGI or PPI as the interface
@@ -643,29 +644,29 @@ static void kvm_routing_and_irqfd_check(struct kvm_vm *vm,
 	 * that no actual interrupt was injected for those cases.
 	 */
 
-	for (f = 0, i = intid; i < (uint64_t)intid + num; i++, f++)
+	for (f = 0, i = intid; i < (u64)intid + num; i++, f++)
 		fd[f] = kvm_new_eventfd();
 
-	for (f = 0, i = intid; i < (uint64_t)intid + num; i++, f++) {
-		assert(i <= (uint64_t)UINT_MAX);
+	for (f = 0, i = intid; i < (u64)intid + num; i++, f++) {
+		assert(i <= (u64)UINT_MAX);
 		kvm_assign_irqfd(vm, i - MIN_SPI, fd[f]);
 	}
 
-	for (f = 0, i = intid; i < (uint64_t)intid + num; i++, f++) {
+	for (f = 0, i = intid; i < (u64)intid + num; i++, f++) {
 		val = 1;
-		ret = write(fd[f], &val, sizeof(uint64_t));
-		TEST_ASSERT(ret == sizeof(uint64_t),
+		ret = write(fd[f], &val, sizeof(u64));
+		TEST_ASSERT(ret == sizeof(u64),
 			    __KVM_SYSCALL_ERROR("write()", ret));
 	}
 
-	for (f = 0, i = intid; i < (uint64_t)intid + num; i++, f++)
+	for (f = 0, i = intid; i < (u64)intid + num; i++, f++)
 		kvm_close(fd[f]);
 }
 
 /* handles the valid case: intid=0xffffffff num=1 */
 #define for_each_intid(first, num, tmp, i)					\
 	for ((tmp) = (i) = (first);						\
-		(tmp) < (uint64_t)(first) + (uint64_t)(num);			\
+		(tmp) < (u64)(first) + (u64)(num);			\
 		(tmp)++, (i)++)
 
 static void run_guest_cmd(struct kvm_vcpu *vcpu, int gic_fd,
@@ -673,13 +674,13 @@ static void run_guest_cmd(struct kvm_vcpu *vcpu, int gic_fd,
 			  struct test_args *test_args)
 {
 	kvm_inject_cmd cmd = inject_args->cmd;
-	uint32_t intid = inject_args->first_intid;
-	uint32_t num = inject_args->num;
+	u32 intid = inject_args->first_intid;
+	u32 num = inject_args->num;
 	int level = inject_args->level;
 	bool expect_failure = inject_args->expect_failure;
 	struct kvm_vm *vm = vcpu->vm;
-	uint64_t tmp;
-	uint32_t i;
+	u64 tmp;
+	u32 i;
 
 	/* handles the valid case: intid=0xffffffff num=1 */
 	assert(intid < UINT_MAX - num || num == 1);
@@ -731,7 +732,7 @@ static void kvm_inject_get_call(struct kvm_vm *vm, struct ucall *uc,
 		struct kvm_inject_args *args)
 {
 	struct kvm_inject_args *kvm_args_hva;
-	vm_vaddr_t kvm_args_gva;
+	gva_t kvm_args_gva;
 
 	kvm_args_gva = uc->args[1];
 	kvm_args_hva = (struct kvm_inject_args *)addr_gva2hva(vm, kvm_args_gva);
@@ -745,14 +746,14 @@ static void print_args(struct test_args *args)
 			args->eoi_split);
 }
 
-static void test_vgic(uint32_t nr_irqs, bool level_sensitive, bool eoi_split)
+static void test_vgic(u32 nr_irqs, bool level_sensitive, bool eoi_split)
 {
 	struct ucall uc;
 	int gic_fd;
 	struct kvm_vcpu *vcpu;
 	struct kvm_vm *vm;
 	struct kvm_inject_args inject_args;
-	vm_vaddr_t args_gva;
+	gva_t args_gva;
 
 	struct test_args args = {
 		.nr_irqs = nr_irqs,
@@ -770,7 +771,7 @@ static void test_vgic(uint32_t nr_irqs, bool level_sensitive, bool eoi_split)
 	vcpu_init_descriptor_tables(vcpu);
 
 	/* Setup the guest args page (so it gets the args). */
-	args_gva = vm_vaddr_alloc_page(vm);
+	args_gva = vm_alloc_page(vm);
 	memcpy(addr_gva2hva(vm, args_gva), &args, sizeof(args));
 	vcpu_args_set(vcpu, 1, args_gva);
 
@@ -810,7 +811,7 @@ static void guest_code_asym_dir(struct test_args *args, int cpuid)
 	gic_set_priority_mask(CPU_PRIO_MASK);
 
 	if (cpuid == 0) {
-		uint32_t intid;
+		u32 intid;
 
 		local_irq_disable();
 
@@ -848,7 +849,7 @@ static void guest_code_asym_dir(struct test_args *args, int cpuid)
 
 static void guest_code_group_en(struct test_args *args, int cpuid)
 {
-	uint32_t intid;
+	u32 intid;
 
 	gic_init(GIC_V3, 2);
 
@@ -896,7 +897,7 @@ static void guest_code_group_en(struct test_args *args, int cpuid)
 
 static void guest_code_timer_spi(struct test_args *args, int cpuid)
 {
-	uint32_t intid;
+	u32 intid;
 	u64 val;
 
 	gic_init(GIC_V3, 2);
@@ -986,7 +987,7 @@ static void test_vgic_two_cpus(void *gcode)
 	struct kvm_vcpu *vcpus[2];
 	struct test_args args = {};
 	struct kvm_vm *vm;
-	vm_vaddr_t args_gva;
+	gva_t args_gva;
 	int gic_fd, ret;
 
 	vm = vm_create_with_vcpus(2, gcode, vcpus);
@@ -996,7 +997,7 @@ static void test_vgic_two_cpus(void *gcode)
 	vcpu_init_descriptor_tables(vcpus[1]);
 
 	/* Setup the guest args page (so it gets the args). */
-	args_gva = vm_vaddr_alloc_page(vm);
+	args_gva = vm_alloc_page(vm);
 	memcpy(addr_gva2hva(vm, args_gva), &args, sizeof(args));
 	vcpu_args_set(vcpus[0], 2, args_gva, 0);
 	vcpu_args_set(vcpus[1], 2, args_gva, 1);
@@ -1033,7 +1034,7 @@ static void help(const char *name)
 
 int main(int argc, char **argv)
 {
-	uint32_t nr_irqs = 64;
+	u32 nr_irqs = 64;
 	bool default_args = true;
 	bool level_sensitive = false;
 	int opt;
diff --git a/tools/testing/selftests/kvm/arm64/vgic_lpi_stress.c b/tools/testing/selftests/kvm/arm64/vgic_lpi_stress.c
index e857a605f577..d64d434d3f06 100644
--- a/tools/testing/selftests/kvm/arm64/vgic_lpi_stress.c
+++ b/tools/testing/selftests/kvm/arm64/vgic_lpi_stress.c
@@ -23,7 +23,7 @@
 #define GIC_LPI_OFFSET	8192
 
 static size_t nr_iterations = 1000;
-static vm_paddr_t gpa_base;
+static gpa_t gpa_base;
 
 static struct kvm_vm *vm;
 static struct kvm_vcpu **vcpus;
@@ -35,14 +35,14 @@ static struct test_data {
 	u32		nr_devices;
 	u32		nr_event_ids;
 
-	vm_paddr_t	device_table;
-	vm_paddr_t	collection_table;
-	vm_paddr_t	cmdq_base;
+	gpa_t		device_table;
+	gpa_t		collection_table;
+	gpa_t		cmdq_base;
 	void		*cmdq_base_va;
-	vm_paddr_t	itt_tables;
+	gpa_t		itt_tables;
 
-	vm_paddr_t	lpi_prop_table;
-	vm_paddr_t	lpi_pend_tables;
+	gpa_t		lpi_prop_table;
+	gpa_t		lpi_pend_tables;
 } test_data =  {
 	.nr_cpus	= 1,
 	.nr_devices	= 1,
@@ -73,7 +73,7 @@ static void guest_setup_its_mappings(void)
 	/* Round-robin the LPIs to all of the vCPUs in the VM */
 	coll_id = 0;
 	for (device_id = 0; device_id < nr_devices; device_id++) {
-		vm_paddr_t itt_base = test_data.itt_tables + (device_id * SZ_64K);
+		gpa_t itt_base = test_data.itt_tables + (device_id * SZ_64K);
 
 		its_send_mapd_cmd(test_data.cmdq_base_va, device_id,
 				  itt_base, SZ_64K, true);
@@ -188,7 +188,7 @@ static void setup_test_data(void)
 	size_t pages_per_64k = vm_calc_num_guest_pages(vm->mode, SZ_64K);
 	u32 nr_devices = test_data.nr_devices;
 	u32 nr_cpus = test_data.nr_cpus;
-	vm_paddr_t cmdq_base;
+	gpa_t cmdq_base;
 
 	test_data.device_table = vm_phy_pages_alloc(vm, pages_per_64k,
 						    gpa_base,
@@ -224,7 +224,7 @@ static void setup_gic(void)
 
 static void signal_lpi(u32 device_id, u32 event_id)
 {
-	vm_paddr_t db_addr = GITS_BASE_GPA + GITS_TRANSLATER;
+	gpa_t db_addr = GITS_BASE_GPA + GITS_TRANSLATER;
 
 	struct kvm_msi msi = {
 		.address_lo	= db_addr,
diff --git a/tools/testing/selftests/kvm/arm64/vgic_v5.c b/tools/testing/selftests/kvm/arm64/vgic_v5.c
index 3ce6cf37a629..d785b660d847 100644
--- a/tools/testing/selftests/kvm/arm64/vgic_v5.c
+++ b/tools/testing/selftests/kvm/arm64/vgic_v5.c
@@ -17,10 +17,10 @@
 struct vm_gic {
 	struct kvm_vm *vm;
 	int gic_fd;
-	uint32_t gic_dev_type;
+	u32 gic_dev_type;
 };
 
-static uint64_t max_phys_size;
+static u64 max_phys_size;
 
 #define GUEST_CMD_IRQ_CDIA	10
 #define GUEST_CMD_IRQ_DIEOI	11
@@ -96,7 +96,7 @@ static void vm_gic_destroy(struct vm_gic *v)
 	kvm_vm_free(v->vm);
 }
 
-static void test_vgic_v5_ppis(uint32_t gic_dev_type)
+static void test_vgic_v5_ppis(u32 gic_dev_type)
 {
 	struct kvm_vcpu *vcpus[NR_VCPUS];
 	struct ucall uc;
@@ -173,7 +173,7 @@ static void test_vgic_v5_ppis(uint32_t gic_dev_type)
 /*
  * Returns 0 if it's possible to create GIC device of a given type (V5).
  */
-int test_kvm_device(uint32_t gic_dev_type)
+int test_kvm_device(u32 gic_dev_type)
 {
 	struct kvm_vcpu *vcpus[NR_VCPUS];
 	struct vm_gic v;
@@ -199,7 +199,7 @@ int test_kvm_device(uint32_t gic_dev_type)
 	return 0;
 }
 
-void run_tests(uint32_t gic_dev_type)
+void run_tests(u32 gic_dev_type)
 {
 	pr_info("Test VGICv5 PPIs\n");
 	test_vgic_v5_ppis(gic_dev_type);
diff --git a/tools/testing/selftests/kvm/arm64/vpmu_counter_access.c b/tools/testing/selftests/kvm/arm64/vpmu_counter_access.c
index ae36325c022f..22223395969e 100644
--- a/tools/testing/selftests/kvm/arm64/vpmu_counter_access.c
+++ b/tools/testing/selftests/kvm/arm64/vpmu_counter_access.c
@@ -33,20 +33,20 @@ struct vpmu_vm {
 static struct vpmu_vm vpmu_vm;
 
 struct pmreg_sets {
-	uint64_t set_reg_id;
-	uint64_t clr_reg_id;
+	u64 set_reg_id;
+	u64 clr_reg_id;
 };
 
 #define PMREG_SET(set, clr) {.set_reg_id = set, .clr_reg_id = clr}
 
-static uint64_t get_pmcr_n(uint64_t pmcr)
+static u64 get_pmcr_n(u64 pmcr)
 {
 	return FIELD_GET(ARMV8_PMU_PMCR_N, pmcr);
 }
 
-static uint64_t get_counters_mask(uint64_t n)
+static u64 get_counters_mask(u64 n)
 {
-	uint64_t mask = BIT(ARMV8_PMU_CYCLE_IDX);
+	u64 mask = BIT(ARMV8_PMU_CYCLE_IDX);
 
 	if (n)
 		mask |= GENMASK(n - 1, 0);
@@ -89,7 +89,7 @@ static inline void write_sel_evtyper(int sel, unsigned long val)
 
 static void pmu_disable_reset(void)
 {
-	uint64_t pmcr = read_sysreg(pmcr_el0);
+	u64 pmcr = read_sysreg(pmcr_el0);
 
 	/* Reset all counters, disabling them */
 	pmcr &= ~ARMV8_PMU_PMCR_E;
@@ -169,7 +169,7 @@ struct pmc_accessor pmc_accessors[] = {
 
 #define GUEST_ASSERT_BITMAP_REG(regname, mask, set_expected)			 \
 {										 \
-	uint64_t _tval = read_sysreg(regname);					 \
+	u64 _tval = read_sysreg(regname);					 \
 										 \
 	if (set_expected)							 \
 		__GUEST_ASSERT((_tval & mask),					 \
@@ -185,7 +185,7 @@ struct pmc_accessor pmc_accessors[] = {
  * Check if @mask bits in {PMCNTEN,PMINTEN,PMOVS}{SET,CLR} registers
  * are set or cleared as specified in @set_expected.
  */
-static void check_bitmap_pmu_regs(uint64_t mask, bool set_expected)
+static void check_bitmap_pmu_regs(u64 mask, bool set_expected)
 {
 	GUEST_ASSERT_BITMAP_REG(pmcntenset_el0, mask, set_expected);
 	GUEST_ASSERT_BITMAP_REG(pmcntenclr_el0, mask, set_expected);
@@ -207,7 +207,7 @@ static void check_bitmap_pmu_regs(uint64_t mask, bool set_expected)
  */
 static void test_bitmap_pmu_regs(int pmc_idx, bool set_op)
 {
-	uint64_t pmcr_n, test_bit = BIT(pmc_idx);
+	u64 pmcr_n, test_bit = BIT(pmc_idx);
 	bool set_expected = false;
 
 	if (set_op) {
@@ -232,7 +232,7 @@ static void test_bitmap_pmu_regs(int pmc_idx, bool set_op)
  */
 static void test_access_pmc_regs(struct pmc_accessor *acc, int pmc_idx)
 {
-	uint64_t write_data, read_data;
+	u64 write_data, read_data;
 
 	/* Disable all PMCs and reset all PMCs to zero. */
 	pmu_disable_reset();
@@ -287,11 +287,11 @@ static void test_access_pmc_regs(struct pmc_accessor *acc, int pmc_idx)
 }
 
 #define INVALID_EC	(-1ul)
-uint64_t expected_ec = INVALID_EC;
+u64 expected_ec = INVALID_EC;
 
 static void guest_sync_handler(struct ex_regs *regs)
 {
-	uint64_t esr, ec;
+	u64 esr, ec;
 
 	esr = read_sysreg(esr_el1);
 	ec = ESR_ELx_EC(esr);
@@ -351,9 +351,9 @@ static void test_access_invalid_pmc_regs(struct pmc_accessor *acc, int pmc_idx)
  * if reading/writing PMU registers for implemented or unimplemented
  * counters works as expected.
  */
-static void guest_code(uint64_t expected_pmcr_n)
+static void guest_code(u64 expected_pmcr_n)
 {
-	uint64_t pmcr, pmcr_n, unimp_mask;
+	u64 pmcr, pmcr_n, unimp_mask;
 	int i, pmc;
 
 	__GUEST_ASSERT(expected_pmcr_n <= ARMV8_PMU_MAX_GENERAL_COUNTERS,
@@ -402,12 +402,12 @@ static void guest_code(uint64_t expected_pmcr_n)
 static void create_vpmu_vm(void *guest_code)
 {
 	struct kvm_vcpu_init init;
-	uint8_t pmuver, ec;
-	uint64_t dfr0, irq = 23;
+	u8 pmuver, ec;
+	u64 dfr0, irq = 23;
 	struct kvm_device_attr irq_attr = {
 		.group = KVM_ARM_VCPU_PMU_V3_CTRL,
 		.attr = KVM_ARM_VCPU_PMU_V3_IRQ,
-		.addr = (uint64_t)&irq,
+		.addr = (u64)&irq,
 	};
 
 	/* The test creates the vpmu_vm multiple times. Ensure a clean state */
@@ -443,7 +443,7 @@ static void destroy_vpmu_vm(void)
 	kvm_vm_free(vpmu_vm.vm);
 }
 
-static void run_vcpu(struct kvm_vcpu *vcpu, uint64_t pmcr_n)
+static void run_vcpu(struct kvm_vcpu *vcpu, u64 pmcr_n)
 {
 	struct ucall uc;
 
@@ -489,9 +489,9 @@ static void test_create_vpmu_vm_with_nr_counters(unsigned int nr_counters, bool
  * Create a guest with one vCPU, set the PMCR_EL0.N for the vCPU to @pmcr_n,
  * and run the test.
  */
-static void run_access_test(uint64_t pmcr_n)
+static void run_access_test(u64 pmcr_n)
 {
-	uint64_t sp;
+	u64 sp;
 	struct kvm_vcpu *vcpu;
 	struct kvm_vcpu_init init;
 
@@ -514,7 +514,7 @@ static void run_access_test(uint64_t pmcr_n)
 	aarch64_vcpu_setup(vcpu, &init);
 	vcpu_init_descriptor_tables(vcpu);
 	vcpu_set_reg(vcpu, ctxt_reg_alias(vcpu, SYS_SP_EL1), sp);
-	vcpu_set_reg(vcpu, ARM64_CORE_REG(regs.pc), (uint64_t)guest_code);
+	vcpu_set_reg(vcpu, ARM64_CORE_REG(regs.pc), (u64)guest_code);
 
 	run_vcpu(vcpu, pmcr_n);
 
@@ -531,12 +531,12 @@ static struct pmreg_sets validity_check_reg_sets[] = {
  * Create a VM, and check if KVM handles the userspace accesses of
  * the PMU register sets in @validity_check_reg_sets[] correctly.
  */
-static void run_pmregs_validity_test(uint64_t pmcr_n)
+static void run_pmregs_validity_test(u64 pmcr_n)
 {
 	int i;
 	struct kvm_vcpu *vcpu;
-	uint64_t set_reg_id, clr_reg_id, reg_val;
-	uint64_t valid_counters_mask, max_counters_mask;
+	u64 set_reg_id, clr_reg_id, reg_val;
+	u64 valid_counters_mask, max_counters_mask;
 
 	test_create_vpmu_vm_with_nr_counters(pmcr_n, false);
 	vcpu = vpmu_vm.vcpu;
@@ -588,7 +588,7 @@ static void run_pmregs_validity_test(uint64_t pmcr_n)
  * the vCPU to @pmcr_n, which is larger than the host value.
  * The attempt should fail as @pmcr_n is too big to set for the vCPU.
  */
-static void run_error_test(uint64_t pmcr_n)
+static void run_error_test(u64 pmcr_n)
 {
 	pr_debug("Error test with pmcr_n %lu (larger than the host)\n", pmcr_n);
 
@@ -600,9 +600,9 @@ static void run_error_test(uint64_t pmcr_n)
  * Return the default number of implemented PMU event counters excluding
  * the cycle counter (i.e. PMCR_EL0.N value) for the guest.
  */
-static uint64_t get_pmcr_n_limit(void)
+static u64 get_pmcr_n_limit(void)
 {
-	uint64_t pmcr;
+	u64 pmcr;
 
 	create_vpmu_vm(guest_code);
 	pmcr = vcpu_get_reg(vpmu_vm.vcpu, KVM_ARM64_SYS_REG(SYS_PMCR_EL0));
@@ -624,7 +624,7 @@ static bool kvm_supports_nr_counters_attr(void)
 
 int main(void)
 {
-	uint64_t i, pmcr_n;
+	u64 i, pmcr_n;
 
 	TEST_REQUIRE(kvm_has_cap(KVM_CAP_ARM_PMU_V3));
 	TEST_REQUIRE(kvm_supports_vgic_v3());
diff --git a/tools/testing/selftests/kvm/coalesced_io_test.c b/tools/testing/selftests/kvm/coalesced_io_test.c
index 60cb25454899..df4ed5e3877c 100644
--- a/tools/testing/selftests/kvm/coalesced_io_test.c
+++ b/tools/testing/selftests/kvm/coalesced_io_test.c
@@ -14,16 +14,16 @@
 
 struct kvm_coalesced_io {
 	struct kvm_coalesced_mmio_ring *ring;
-	uint32_t ring_size;
-	uint64_t mmio_gpa;
-	uint64_t *mmio;
+	u32 ring_size;
+	u64 mmio_gpa;
+	u64 *mmio;
 
 	/*
 	 * x86-only, but define pio_port for all architectures to minimize the
 	 * amount of #ifdeffery and complexity, without having to sacrifice
 	 * verbose error messages.
 	 */
-	uint8_t pio_port;
+	u8 pio_port;
 };
 
 static struct kvm_coalesced_io kvm_builtin_io_ring;
@@ -70,13 +70,13 @@ static void guest_code(struct kvm_coalesced_io *io)
 
 static void vcpu_run_and_verify_io_exit(struct kvm_vcpu *vcpu,
 					struct kvm_coalesced_io *io,
-					uint32_t ring_start,
-					uint32_t expected_exit)
+					u32 ring_start,
+					u32 expected_exit)
 {
 	const bool want_pio = expected_exit == KVM_EXIT_IO;
 	struct kvm_coalesced_mmio_ring *ring = io->ring;
 	struct kvm_run *run = vcpu->run;
-	uint32_t pio_value;
+	u32 pio_value;
 
 	WRITE_ONCE(ring->first, ring_start);
 	WRITE_ONCE(ring->last, ring_start);
@@ -88,13 +88,13 @@ static void vcpu_run_and_verify_io_exit(struct kvm_vcpu *vcpu,
 	 * data_offset is garbage, e.g. an MMIO gpa.
 	 */
 	if (run->exit_reason == KVM_EXIT_IO)
-		pio_value = *(uint32_t *)((void *)run + run->io.data_offset);
+		pio_value = *(u32 *)((void *)run + run->io.data_offset);
 	else
 		pio_value = 0;
 
 	TEST_ASSERT((!want_pio && (run->exit_reason == KVM_EXIT_MMIO && run->mmio.is_write &&
 				   run->mmio.phys_addr == io->mmio_gpa && run->mmio.len == 8 &&
-				   *(uint64_t *)run->mmio.data == io->mmio_gpa + io->ring_size - 1)) ||
+				   *(u64 *)run->mmio.data == io->mmio_gpa + io->ring_size - 1)) ||
 		    (want_pio  && (run->exit_reason == KVM_EXIT_IO && run->io.port == io->pio_port &&
 				   run->io.direction == KVM_EXIT_IO_OUT && run->io.count == 1 &&
 				   pio_value == io->pio_port + io->ring_size - 1)),
@@ -105,14 +105,14 @@ static void vcpu_run_and_verify_io_exit(struct kvm_vcpu *vcpu,
 		    want_pio ? (unsigned long long)io->pio_port : io->mmio_gpa,
 		    (want_pio ? io->pio_port : io->mmio_gpa) + io->ring_size - 1, run->exit_reason,
 		    run->exit_reason == KVM_EXIT_MMIO ? "MMIO" : run->exit_reason == KVM_EXIT_IO ? "PIO" : "other",
-		    run->mmio.phys_addr, run->mmio.is_write, run->mmio.len, *(uint64_t *)run->mmio.data,
+		    run->mmio.phys_addr, run->mmio.is_write, run->mmio.len, *(u64 *)run->mmio.data,
 		    run->io.port, run->io.direction, run->io.size, run->io.count, pio_value);
 }
 
 static void vcpu_run_and_verify_coalesced_io(struct kvm_vcpu *vcpu,
 					     struct kvm_coalesced_io *io,
-					     uint32_t ring_start,
-					     uint32_t expected_exit)
+					     u32 ring_start,
+					     u32 expected_exit)
 {
 	struct kvm_coalesced_mmio_ring *ring = io->ring;
 	int i;
@@ -124,18 +124,18 @@ static void vcpu_run_and_verify_coalesced_io(struct kvm_vcpu *vcpu,
 		    ring->first, ring->last, io->ring_size, ring_start);
 
 	for (i = 0; i < io->ring_size - 1; i++) {
-		uint32_t idx = (ring->first + i) % io->ring_size;
+		u32 idx = (ring->first + i) % io->ring_size;
 		struct kvm_coalesced_mmio *entry = &ring->coalesced_mmio[idx];
 
 #ifdef __x86_64__
 		if (i & 1)
 			TEST_ASSERT(entry->phys_addr == io->pio_port &&
 				    entry->len == 4 && entry->pio &&
-				    *(uint32_t *)entry->data == io->pio_port + i,
+				    *(u32 *)entry->data == io->pio_port + i,
 				    "Wanted 4-byte port I/O 0x%x = 0x%x in entry %u, got %u-byte %s 0x%llx = 0x%x",
 				    io->pio_port, io->pio_port + i, i,
 				    entry->len, entry->pio ? "PIO" : "MMIO",
-				    entry->phys_addr, *(uint32_t *)entry->data);
+				    entry->phys_addr, *(u32 *)entry->data);
 		else
 #endif
 			TEST_ASSERT(entry->phys_addr == io->mmio_gpa &&
@@ -143,12 +143,12 @@ static void vcpu_run_and_verify_coalesced_io(struct kvm_vcpu *vcpu,
 				    "Wanted 8-byte MMIO to 0x%lx = %lx in entry %u, got %u-byte %s 0x%llx = 0x%lx",
 				    io->mmio_gpa, io->mmio_gpa + i, i,
 				    entry->len, entry->pio ? "PIO" : "MMIO",
-				    entry->phys_addr, *(uint64_t *)entry->data);
+				    entry->phys_addr, *(u64 *)entry->data);
 	}
 }
 
 static void test_coalesced_io(struct kvm_vcpu *vcpu,
-			      struct kvm_coalesced_io *io, uint32_t ring_start)
+			      struct kvm_coalesced_io *io, u32 ring_start)
 {
 	struct kvm_coalesced_mmio_ring *ring = io->ring;
 
@@ -219,11 +219,11 @@ int main(int argc, char *argv[])
 		 * the MMIO GPA identity mapped in the guest.
 		 */
 		.mmio_gpa = 4ull * SZ_1G,
-		.mmio = (uint64_t *)(4ull * SZ_1G),
+		.mmio = (u64 *)(4ull * SZ_1G),
 		.pio_port = 0x80,
 	};
 
-	virt_map(vm, (uint64_t)kvm_builtin_io_ring.mmio, kvm_builtin_io_ring.mmio_gpa, 1);
+	virt_map(vm, (u64)kvm_builtin_io_ring.mmio, kvm_builtin_io_ring.mmio_gpa, 1);
 
 	sync_global_to_guest(vm, kvm_builtin_io_ring);
 	vcpu_args_set(vcpu, 1, &kvm_builtin_io_ring);
diff --git a/tools/testing/selftests/kvm/demand_paging_test.c b/tools/testing/selftests/kvm/demand_paging_test.c
index 0202b78f8680..302c4923d093 100644
--- a/tools/testing/selftests/kvm/demand_paging_test.c
+++ b/tools/testing/selftests/kvm/demand_paging_test.c
@@ -24,7 +24,7 @@
 #ifdef __NR_userfaultfd
 
 static int nr_vcpus = 1;
-static uint64_t guest_percpu_mem_size = DEFAULT_PER_VCPU_MEM_SIZE;
+static u64 guest_percpu_mem_size = DEFAULT_PER_VCPU_MEM_SIZE;
 
 static size_t demand_paging_size;
 static char *guest_data_prototype;
@@ -58,7 +58,7 @@ static int handle_uffd_page_request(int uffd_mode, int uffd,
 		struct uffd_msg *msg)
 {
 	pid_t tid = syscall(__NR_gettid);
-	uint64_t addr = msg->arg.pagefault.address;
+	u64 addr = msg->arg.pagefault.address;
 	struct timespec start;
 	struct timespec ts_diff;
 	int r;
@@ -68,7 +68,7 @@ static int handle_uffd_page_request(int uffd_mode, int uffd,
 	if (uffd_mode == UFFDIO_REGISTER_MODE_MISSING) {
 		struct uffdio_copy copy;
 
-		copy.src = (uint64_t)guest_data_prototype;
+		copy.src = (u64)guest_data_prototype;
 		copy.dst = addr;
 		copy.len = demand_paging_size;
 		copy.mode = 0;
@@ -138,7 +138,7 @@ struct test_params {
 	bool partition_vcpu_memory_access;
 };
 
-static void prefault_mem(void *alias, uint64_t len)
+static void prefault_mem(void *alias, u64 len)
 {
 	size_t p;
 
@@ -154,7 +154,7 @@ static void run_test(enum vm_guest_mode mode, void *arg)
 	struct memstress_vcpu_args *vcpu_args;
 	struct test_params *p = arg;
 	struct uffd_desc **uffd_descs = NULL;
-	uint64_t uffd_region_size;
+	u64 uffd_region_size;
 	struct timespec start;
 	struct timespec ts_diff;
 	double vcpu_paging_rate;
diff --git a/tools/testing/selftests/kvm/dirty_log_perf_test.c b/tools/testing/selftests/kvm/dirty_log_perf_test.c
index 0a1ea1d1e2d8..ef779fa91827 100644
--- a/tools/testing/selftests/kvm/dirty_log_perf_test.c
+++ b/tools/testing/selftests/kvm/dirty_log_perf_test.c
@@ -24,7 +24,7 @@
 #define TEST_HOST_LOOP_N		2UL
 
 static int nr_vcpus = 1;
-static uint64_t guest_percpu_mem_size = DEFAULT_PER_VCPU_MEM_SIZE;
+static u64 guest_percpu_mem_size = DEFAULT_PER_VCPU_MEM_SIZE;
 static bool run_vcpus_while_disabling_dirty_logging;
 
 /* Host variables */
@@ -37,7 +37,7 @@ static void vcpu_worker(struct memstress_vcpu_args *vcpu_args)
 {
 	struct kvm_vcpu *vcpu = vcpu_args->vcpu;
 	int vcpu_idx = vcpu_args->vcpu_idx;
-	uint64_t pages_count = 0;
+	u64 pages_count = 0;
 	struct kvm_run *run;
 	struct timespec start;
 	struct timespec ts_diff;
@@ -93,11 +93,11 @@ static void vcpu_worker(struct memstress_vcpu_args *vcpu_args)
 
 struct test_params {
 	unsigned long iterations;
-	uint64_t phys_offset;
+	u64 phys_offset;
 	bool partition_vcpu_memory_access;
 	enum vm_mem_backing_src_type backing_src;
 	int slots;
-	uint32_t write_percent;
+	u32 write_percent;
 	bool random_access;
 };
 
@@ -106,9 +106,9 @@ static void run_test(enum vm_guest_mode mode, void *arg)
 	struct test_params *p = arg;
 	struct kvm_vm *vm;
 	unsigned long **bitmaps;
-	uint64_t guest_num_pages;
-	uint64_t host_num_pages;
-	uint64_t pages_per_slot;
+	u64 guest_num_pages;
+	u64 host_num_pages;
+	u64 pages_per_slot;
 	struct timespec start;
 	struct timespec ts_diff;
 	struct timespec get_dirty_log_total = (struct timespec){0};
diff --git a/tools/testing/selftests/kvm/dirty_log_test.c b/tools/testing/selftests/kvm/dirty_log_test.c
index 7627b328f18a..12446a4b6e8d 100644
--- a/tools/testing/selftests/kvm/dirty_log_test.c
+++ b/tools/testing/selftests/kvm/dirty_log_test.c
@@ -74,11 +74,11 @@
  * the host. READ/WRITE_ONCE() should also be used with anything
  * that may change.
  */
-static uint64_t host_page_size;
-static uint64_t guest_page_size;
-static uint64_t guest_num_pages;
-static uint64_t iteration;
-static uint64_t nr_writes;
+static u64 host_page_size;
+static u64 guest_page_size;
+static u64 guest_num_pages;
+static u64 iteration;
+static u64 nr_writes;
 static bool vcpu_stop;
 
 /*
@@ -86,13 +86,13 @@ static bool vcpu_stop;
  * This will be set to the topmost valid physical address minus
  * the test memory size.
  */
-static uint64_t guest_test_phys_mem;
+static u64 guest_test_phys_mem;
 
 /*
  * Guest virtual memory offset of the testing memory slot.
  * Must not conflict with identity mapped test code.
  */
-static uint64_t guest_test_virt_mem = DEFAULT_GUEST_TEST_MEM;
+static u64 guest_test_virt_mem = DEFAULT_GUEST_TEST_MEM;
 
 /*
  * Continuously write to the first 8 bytes of a random pages within
@@ -100,10 +100,10 @@ static uint64_t guest_test_virt_mem = DEFAULT_GUEST_TEST_MEM;
  */
 static void guest_code(void)
 {
-	uint64_t addr;
+	u64 addr;
 
 #ifdef __s390x__
-	uint64_t i;
+	u64 i;
 
 	/*
 	 * On s390x, all pages of a 1M segment are initially marked as dirty
@@ -113,7 +113,7 @@ static void guest_code(void)
 	 */
 	for (i = 0; i < guest_num_pages; i++) {
 		addr = guest_test_virt_mem + i * guest_page_size;
-		vcpu_arch_put_guest(*(uint64_t *)addr, READ_ONCE(iteration));
+		vcpu_arch_put_guest(*(u64 *)addr, READ_ONCE(iteration));
 		nr_writes++;
 	}
 #endif
@@ -125,7 +125,7 @@ static void guest_code(void)
 				* guest_page_size;
 			addr = align_down(addr, host_page_size);
 
-			vcpu_arch_put_guest(*(uint64_t *)addr, READ_ONCE(iteration));
+			vcpu_arch_put_guest(*(u64 *)addr, READ_ONCE(iteration));
 			nr_writes++;
 		}
 
@@ -138,11 +138,11 @@ static bool host_quit;
 
 /* Points to the test VM memory region on which we track dirty logs */
 static void *host_test_mem;
-static uint64_t host_num_pages;
+static u64 host_num_pages;
 
 /* For statistics only */
-static uint64_t host_dirty_count;
-static uint64_t host_clear_count;
+static u64 host_dirty_count;
+static u64 host_clear_count;
 
 /* Whether dirty ring reset is requested, or finished */
 static sem_t sem_vcpu_stop;
@@ -169,7 +169,7 @@ static bool dirty_ring_vcpu_ring_full;
  * dirty gfn we've collected, so that if a mismatch of data found later in the
  * verifying process, we let it pass.
  */
-static uint64_t dirty_ring_last_page = -1ULL;
+static u64 dirty_ring_last_page = -1ULL;
 
 /*
  * In addition to the above, it is possible (especially if this
@@ -213,7 +213,7 @@ static uint64_t dirty_ring_last_page = -1ULL;
  * and also don't fail when it is reported in the next iteration, together with
  * an outdated iteration count.
  */
-static uint64_t dirty_ring_prev_iteration_last_page;
+static u64 dirty_ring_prev_iteration_last_page;
 
 enum log_mode_t {
 	/* Only use KVM_GET_DIRTY_LOG for logging */
@@ -236,7 +236,7 @@ static enum log_mode_t host_log_mode_option = LOG_MODE_ALL;
 /* Logging mode for current run */
 static enum log_mode_t host_log_mode;
 static pthread_t vcpu_thread;
-static uint32_t test_dirty_ring_count = TEST_DIRTY_RING_COUNT;
+static u32 test_dirty_ring_count = TEST_DIRTY_RING_COUNT;
 
 static bool clear_log_supported(void)
 {
@@ -255,15 +255,15 @@ static void clear_log_create_vm_done(struct kvm_vm *vm)
 }
 
 static void dirty_log_collect_dirty_pages(struct kvm_vcpu *vcpu, int slot,
-					  void *bitmap, uint32_t num_pages,
-					  uint32_t *unused)
+					  void *bitmap, u32 num_pages,
+					  u32 *unused)
 {
 	kvm_vm_get_dirty_log(vcpu->vm, slot, bitmap);
 }
 
 static void clear_log_collect_dirty_pages(struct kvm_vcpu *vcpu, int slot,
-					  void *bitmap, uint32_t num_pages,
-					  uint32_t *unused)
+					  void *bitmap, u32 num_pages,
+					  u32 *unused)
 {
 	kvm_vm_get_dirty_log(vcpu->vm, slot, bitmap);
 	kvm_vm_clear_dirty_log(vcpu->vm, slot, bitmap, 0, num_pages);
@@ -297,8 +297,8 @@ static bool dirty_ring_supported(void)
 
 static void dirty_ring_create_vm_done(struct kvm_vm *vm)
 {
-	uint64_t pages;
-	uint32_t limit;
+	u64 pages;
+	u32 limit;
 
 	/*
 	 * We rely on vcpu exit due to full dirty ring state. Adjust
@@ -333,12 +333,12 @@ static inline void dirty_gfn_set_collected(struct kvm_dirty_gfn *gfn)
 	smp_store_release(&gfn->flags, KVM_DIRTY_GFN_F_RESET);
 }
 
-static uint32_t dirty_ring_collect_one(struct kvm_dirty_gfn *dirty_gfns,
-				       int slot, void *bitmap,
-				       uint32_t num_pages, uint32_t *fetch_index)
+static u32 dirty_ring_collect_one(struct kvm_dirty_gfn *dirty_gfns,
+				  int slot, void *bitmap,
+				  u32 num_pages, u32 *fetch_index)
 {
 	struct kvm_dirty_gfn *cur;
-	uint32_t count = 0;
+	u32 count = 0;
 
 	while (true) {
 		cur = &dirty_gfns[*fetch_index % test_dirty_ring_count];
@@ -359,10 +359,10 @@ static uint32_t dirty_ring_collect_one(struct kvm_dirty_gfn *dirty_gfns,
 }
 
 static void dirty_ring_collect_dirty_pages(struct kvm_vcpu *vcpu, int slot,
-					   void *bitmap, uint32_t num_pages,
-					   uint32_t *ring_buf_idx)
+					   void *bitmap, u32 num_pages,
+					   u32 *ring_buf_idx)
 {
-	uint32_t count, cleared;
+	u32 count, cleared;
 
 	/* Only have one vcpu */
 	count = dirty_ring_collect_one(vcpu_map_dirty_ring(vcpu),
@@ -404,8 +404,8 @@ struct log_mode {
 	void (*create_vm_done)(struct kvm_vm *vm);
 	/* Hook to collect the dirty pages into the bitmap provided */
 	void (*collect_dirty_pages) (struct kvm_vcpu *vcpu, int slot,
-				     void *bitmap, uint32_t num_pages,
-				     uint32_t *ring_buf_idx);
+				     void *bitmap, u32 num_pages,
+				     u32 *ring_buf_idx);
 	/* Hook to call when after each vcpu run */
 	void (*after_vcpu_run)(struct kvm_vcpu *vcpu);
 } log_modes[LOG_MODE_NUM] = {
@@ -459,8 +459,8 @@ static void log_mode_create_vm_done(struct kvm_vm *vm)
 }
 
 static void log_mode_collect_dirty_pages(struct kvm_vcpu *vcpu, int slot,
-					 void *bitmap, uint32_t num_pages,
-					 uint32_t *ring_buf_idx)
+					 void *bitmap, u32 num_pages,
+					 u32 *ring_buf_idx)
 {
 	struct log_mode *mode = &log_modes[host_log_mode];
 
@@ -494,11 +494,11 @@ static void *vcpu_worker(void *data)
 
 static void vm_dirty_log_verify(enum vm_guest_mode mode, unsigned long **bmap)
 {
-	uint64_t page, nr_dirty_pages = 0, nr_clean_pages = 0;
-	uint64_t step = vm_num_host_pages(mode, 1);
+	u64 page, nr_dirty_pages = 0, nr_clean_pages = 0;
+	u64 step = vm_num_host_pages(mode, 1);
 
 	for (page = 0; page < host_num_pages; page += step) {
-		uint64_t val = *(uint64_t *)(host_test_mem + page * host_page_size);
+		u64 val = *(u64 *)(host_test_mem + page * host_page_size);
 		bool bmap0_dirty = __test_and_clear_bit_le(page, bmap[0]);
 
 		/*
@@ -575,7 +575,7 @@ static void vm_dirty_log_verify(enum vm_guest_mode mode, unsigned long **bmap)
 }
 
 static struct kvm_vm *create_vm(enum vm_guest_mode mode, struct kvm_vcpu **vcpu,
-				uint64_t extra_mem_pages, void *guest_code)
+				u64 extra_mem_pages, void *guest_code)
 {
 	struct kvm_vm *vm;
 
@@ -592,7 +592,7 @@ static struct kvm_vm *create_vm(enum vm_guest_mode mode, struct kvm_vcpu **vcpu,
 struct test_params {
 	unsigned long iterations;
 	unsigned long interval;
-	uint64_t phys_offset;
+	u64 phys_offset;
 };
 
 static void run_test(enum vm_guest_mode mode, void *arg)
@@ -601,7 +601,7 @@ static void run_test(enum vm_guest_mode mode, void *arg)
 	struct kvm_vcpu *vcpu;
 	struct kvm_vm *vm;
 	unsigned long *bmap[2];
-	uint32_t ring_buf_idx = 0;
+	u32 ring_buf_idx = 0;
 	int sem_val;
 
 	if (!log_mode_supported()) {
@@ -667,7 +667,7 @@ static void run_test(enum vm_guest_mode mode, void *arg)
 	virt_map(vm, guest_test_virt_mem, guest_test_phys_mem, guest_num_pages);
 
 	/* Cache the HVA pointer of the region */
-	host_test_mem = addr_gpa2hva(vm, (vm_paddr_t)guest_test_phys_mem);
+	host_test_mem = addr_gpa2hva(vm, (gpa_t)guest_test_phys_mem);
 
 	/* Export the shared variables to the guest */
 	sync_global_to_guest(vm, host_page_size);
diff --git a/tools/testing/selftests/kvm/get-reg-list.c b/tools/testing/selftests/kvm/get-reg-list.c
index f4644c9d2d3b..216f10644c1a 100644
--- a/tools/testing/selftests/kvm/get-reg-list.c
+++ b/tools/testing/selftests/kvm/get-reg-list.c
@@ -216,7 +216,7 @@ static void run_test(struct vcpu_reg_list *c)
 	 * since we don't know the capabilities of any new registers.
 	 */
 	for_each_present_blessed_reg(i) {
-		uint8_t addr[2048 / 8];
+		u8 addr[2048 / 8];
 		struct kvm_one_reg reg = {
 			.id = reg_list->reg[i],
 			.addr = (__u64)&addr,
diff --git a/tools/testing/selftests/kvm/guest_memfd_test.c b/tools/testing/selftests/kvm/guest_memfd_test.c
index ec7644aae999..d6528c6f5e03 100644
--- a/tools/testing/selftests/kvm/guest_memfd_test.c
+++ b/tools/testing/selftests/kvm/guest_memfd_test.c
@@ -171,7 +171,7 @@ static void test_numa_allocation(int fd, size_t total_size)
 	kvm_munmap(mem, total_size);
 }
 
-static void test_collapse(int fd, uint64_t flags)
+static void test_collapse(int fd, u64 flags)
 {
 	const size_t pmd_size = get_trans_hugepagesz();
 	void *reserved_addr;
@@ -346,7 +346,7 @@ static void test_invalid_punch_hole(int fd, size_t total_size)
 }
 
 static void test_create_guest_memfd_invalid_sizes(struct kvm_vm *vm,
-						  uint64_t guest_memfd_flags)
+						  u64 guest_memfd_flags)
 {
 	size_t size;
 	int fd;
@@ -389,8 +389,8 @@ static void test_create_guest_memfd_multiple(struct kvm_vm *vm)
 
 static void test_guest_memfd_flags(struct kvm_vm *vm)
 {
-	uint64_t valid_flags = vm_check_cap(vm, KVM_CAP_GUEST_MEMFD_FLAGS);
-	uint64_t flag;
+	u64 valid_flags = vm_check_cap(vm, KVM_CAP_GUEST_MEMFD_FLAGS);
+	u64 flag;
 	int fd;
 
 	for (flag = BIT(0); flag; flag <<= 1) {
@@ -419,7 +419,7 @@ do {									\
 #define gmem_test(__test, __vm, __flags)				\
 	__gmem_test(__test, __vm, __flags, page_size * 4)
 
-static void __test_guest_memfd(struct kvm_vm *vm, uint64_t flags)
+static void __test_guest_memfd(struct kvm_vm *vm, u64 flags)
 {
 	test_create_guest_memfd_multiple(vm);
 	test_create_guest_memfd_invalid_sizes(vm, flags);
@@ -452,7 +452,7 @@ static void __test_guest_memfd(struct kvm_vm *vm, uint64_t flags)
 static void test_guest_memfd(unsigned long vm_type)
 {
 	struct kvm_vm *vm = vm_create_barebones_type(vm_type);
-	uint64_t flags;
+	u64 flags;
 
 	test_guest_memfd_flags(vm);
 
@@ -470,7 +470,7 @@ static void test_guest_memfd(unsigned long vm_type)
 	kvm_vm_free(vm);
 }
 
-static void guest_code(uint8_t *mem, uint64_t size)
+static void guest_code(u8 *mem, u64 size)
 {
 	size_t i;
 
@@ -489,12 +489,12 @@ static void test_guest_memfd_guest(void)
 	 * the guest's code, stack, and page tables, and low memory contains
 	 * the PCI hole and other MMIO regions that need to be avoided.
 	 */
-	const uint64_t gpa = SZ_4G;
+	const gpa_t gpa = SZ_4G;
 	const int slot = 1;
 
 	struct kvm_vcpu *vcpu;
 	struct kvm_vm *vm;
-	uint8_t *mem;
+	u8 *mem;
 	size_t size;
 	int fd, i;
 
diff --git a/tools/testing/selftests/kvm/guest_print_test.c b/tools/testing/selftests/kvm/guest_print_test.c
index bcf582852db9..79d3fc326e91 100644
--- a/tools/testing/selftests/kvm/guest_print_test.c
+++ b/tools/testing/selftests/kvm/guest_print_test.c
@@ -16,22 +16,22 @@
 #include "ucall_common.h"
 
 struct guest_vals {
-	uint64_t a;
-	uint64_t b;
-	uint64_t type;
+	u64 a;
+	u64 b;
+	u64 type;
 };
 
 static struct guest_vals vals;
 
 /* GUEST_PRINTF()/GUEST_ASSERT_FMT() does not support float or double. */
 #define TYPE_LIST					\
-TYPE(test_type_i64,  I64,  "%ld",   int64_t)		\
-TYPE(test_type_u64,  U64u, "%lu",   uint64_t)		\
-TYPE(test_type_x64,  U64x, "0x%lx", uint64_t)		\
-TYPE(test_type_X64,  U64X, "0x%lX", uint64_t)		\
-TYPE(test_type_u32,  U32u, "%u",    uint32_t)		\
-TYPE(test_type_x32,  U32x, "0x%x",  uint32_t)		\
-TYPE(test_type_X32,  U32X, "0x%X",  uint32_t)		\
+TYPE(test_type_i64,  I64,  "%ld",   s64)		\
+TYPE(test_type_u64,  U64u, "%lu",   u64)		\
+TYPE(test_type_x64,  U64x, "0x%lx", u64)		\
+TYPE(test_type_X64,  U64X, "0x%lX", u64)		\
+TYPE(test_type_u32,  U32u, "%u",    u32)		\
+TYPE(test_type_x32,  U32x, "0x%x",  u32)		\
+TYPE(test_type_X32,  U32X, "0x%X",  u32)		\
 TYPE(test_type_int,  INT,  "%d",    int)		\
 TYPE(test_type_char, CHAR, "%c",    char)		\
 TYPE(test_type_str,  STR,  "'%s'",  const char *)	\
@@ -56,7 +56,7 @@ static void fn(struct kvm_vcpu *vcpu, T a, T b)				     \
 									     \
 	snprintf(expected_printf, UCALL_BUFFER_LEN, PRINTF_FMT_##ext, a, b); \
 	snprintf(expected_assert, UCALL_BUFFER_LEN, ASSERT_FMT_##ext, a, b); \
-	vals = (struct guest_vals){ (uint64_t)a, (uint64_t)b, TYPE_##ext };  \
+	vals = (struct guest_vals){ (u64)a, (u64)b, TYPE_##ext };  \
 	sync_global_to_guest(vcpu->vm, vals);				     \
 	run_test(vcpu, expected_printf, expected_assert);		     \
 }
diff --git a/tools/testing/selftests/kvm/hardware_disable_test.c b/tools/testing/selftests/kvm/hardware_disable_test.c
index 94bd6ed24cf3..3147f5c97e94 100644
--- a/tools/testing/selftests/kvm/hardware_disable_test.c
+++ b/tools/testing/selftests/kvm/hardware_disable_test.c
@@ -80,7 +80,7 @@ static inline void check_join(pthread_t thread, void **retval)
 	TEST_ASSERT(r == 0, "%s: failed to join thread", __func__);
 }
 
-static void run_test(uint32_t run)
+static void run_test(u32 run)
 {
 	struct kvm_vcpu *vcpu;
 	struct kvm_vm *vm;
@@ -88,7 +88,7 @@ static void run_test(uint32_t run)
 	pthread_t threads[VCPU_NUM];
 	pthread_t throw_away;
 	void *b;
-	uint32_t i, j;
+	u32 i, j;
 
 	CPU_ZERO(&cpu_set);
 	for (i = 0; i < VCPU_NUM; i++)
@@ -149,7 +149,7 @@ void wait_for_child_setup(pid_t pid)
 
 int main(int argc, char **argv)
 {
-	uint32_t i;
+	u32 i;
 	int s, r;
 	pid_t pid;
 
diff --git a/tools/testing/selftests/kvm/include/arm64/arch_timer.h b/tools/testing/selftests/kvm/include/arm64/arch_timer.h
index e2c4e9f0010f..a5836d4ab7ee 100644
--- a/tools/testing/selftests/kvm/include/arm64/arch_timer.h
+++ b/tools/testing/selftests/kvm/include/arm64/arch_timer.h
@@ -18,20 +18,20 @@ enum arch_timer {
 #define CTL_ISTATUS	(1 << 2)
 
 #define msec_to_cycles(msec)	\
-	(timer_get_cntfrq() * (uint64_t)(msec) / 1000)
+	(timer_get_cntfrq() * (u64)(msec) / 1000)
 
 #define usec_to_cycles(usec)	\
-	(timer_get_cntfrq() * (uint64_t)(usec) / 1000000)
+	(timer_get_cntfrq() * (u64)(usec) / 1000000)
 
 #define cycles_to_usec(cycles) \
-	((uint64_t)(cycles) * 1000000 / timer_get_cntfrq())
+	((u64)(cycles) * 1000000 / timer_get_cntfrq())
 
-static inline uint32_t timer_get_cntfrq(void)
+static inline u32 timer_get_cntfrq(void)
 {
 	return read_sysreg(cntfrq_el0);
 }
 
-static inline uint64_t timer_get_cntct(enum arch_timer timer)
+static inline u64 timer_get_cntct(enum arch_timer timer)
 {
 	isb();
 
@@ -48,7 +48,7 @@ static inline uint64_t timer_get_cntct(enum arch_timer timer)
 	return 0;
 }
 
-static inline void timer_set_cval(enum arch_timer timer, uint64_t cval)
+static inline void timer_set_cval(enum arch_timer timer, u64 cval)
 {
 	switch (timer) {
 	case VIRTUAL:
@@ -64,7 +64,7 @@ static inline void timer_set_cval(enum arch_timer timer, uint64_t cval)
 	isb();
 }
 
-static inline uint64_t timer_get_cval(enum arch_timer timer)
+static inline u64 timer_get_cval(enum arch_timer timer)
 {
 	switch (timer) {
 	case VIRTUAL:
@@ -79,7 +79,7 @@ static inline uint64_t timer_get_cval(enum arch_timer timer)
 	return 0;
 }
 
-static inline void timer_set_tval(enum arch_timer timer, int32_t tval)
+static inline void timer_set_tval(enum arch_timer timer, s32 tval)
 {
 	switch (timer) {
 	case VIRTUAL:
@@ -95,7 +95,7 @@ static inline void timer_set_tval(enum arch_timer timer, int32_t tval)
 	isb();
 }
 
-static inline int32_t timer_get_tval(enum arch_timer timer)
+static inline s32 timer_get_tval(enum arch_timer timer)
 {
 	isb();
 	switch (timer) {
@@ -111,7 +111,7 @@ static inline int32_t timer_get_tval(enum arch_timer timer)
 	return 0;
 }
 
-static inline void timer_set_ctl(enum arch_timer timer, uint32_t ctl)
+static inline void timer_set_ctl(enum arch_timer timer, u32 ctl)
 {
 	switch (timer) {
 	case VIRTUAL:
@@ -127,7 +127,7 @@ static inline void timer_set_ctl(enum arch_timer timer, uint32_t ctl)
 	isb();
 }
 
-static inline uint32_t timer_get_ctl(enum arch_timer timer)
+static inline u32 timer_get_ctl(enum arch_timer timer)
 {
 	switch (timer) {
 	case VIRTUAL:
@@ -142,15 +142,15 @@ static inline uint32_t timer_get_ctl(enum arch_timer timer)
 	return 0;
 }
 
-static inline void timer_set_next_cval_ms(enum arch_timer timer, uint32_t msec)
+static inline void timer_set_next_cval_ms(enum arch_timer timer, u32 msec)
 {
-	uint64_t now_ct = timer_get_cntct(timer);
-	uint64_t next_ct = now_ct + msec_to_cycles(msec);
+	u64 now_ct = timer_get_cntct(timer);
+	u64 next_ct = now_ct + msec_to_cycles(msec);
 
 	timer_set_cval(timer, next_ct);
 }
 
-static inline void timer_set_next_tval_ms(enum arch_timer timer, uint32_t msec)
+static inline void timer_set_next_tval_ms(enum arch_timer timer, u32 msec)
 {
 	timer_set_tval(timer, msec_to_cycles(msec));
 }
diff --git a/tools/testing/selftests/kvm/include/arm64/delay.h b/tools/testing/selftests/kvm/include/arm64/delay.h
index 329e4f5079ea..6a5d4634af2c 100644
--- a/tools/testing/selftests/kvm/include/arm64/delay.h
+++ b/tools/testing/selftests/kvm/include/arm64/delay.h
@@ -8,10 +8,10 @@
 
 #include "arch_timer.h"
 
-static inline void __delay(uint64_t cycles)
+static inline void __delay(u64 cycles)
 {
 	enum arch_timer timer = VIRTUAL;
-	uint64_t start = timer_get_cntct(timer);
+	u64 start = timer_get_cntct(timer);
 
 	while ((timer_get_cntct(timer) - start) < cycles)
 		cpu_relax();
diff --git a/tools/testing/selftests/kvm/include/arm64/gic.h b/tools/testing/selftests/kvm/include/arm64/gic.h
index cc7a7f34ed37..615745093c98 100644
--- a/tools/testing/selftests/kvm/include/arm64/gic.h
+++ b/tools/testing/selftests/kvm/include/arm64/gic.h
@@ -48,8 +48,8 @@ void gic_set_dir(unsigned int intid);
  * split is true, EOI drops the priority and deactivates the interrupt.
  */
 void gic_set_eoi_split(bool split);
-void gic_set_priority_mask(uint64_t mask);
-void gic_set_priority(uint32_t intid, uint32_t prio);
+void gic_set_priority_mask(u64 mask);
+void gic_set_priority(u32 intid, u32 prio);
 void gic_irq_set_active(unsigned int intid);
 void gic_irq_clear_active(unsigned int intid);
 bool gic_irq_get_active(unsigned int intid);
@@ -59,7 +59,7 @@ bool gic_irq_get_pending(unsigned int intid);
 void gic_irq_set_config(unsigned int intid, bool is_edge);
 void gic_irq_set_group(unsigned int intid, bool group);
 
-void gic_rdist_enable_lpis(vm_paddr_t cfg_table, size_t cfg_table_size,
-			   vm_paddr_t pend_table);
+void gic_rdist_enable_lpis(gpa_t cfg_table, size_t cfg_table_size,
+			   gpa_t pend_table);
 
 #endif /* SELFTEST_KVM_GIC_H */
diff --git a/tools/testing/selftests/kvm/include/arm64/gic_v3_its.h b/tools/testing/selftests/kvm/include/arm64/gic_v3_its.h
index 58feef3eb386..a43a407e2d5c 100644
--- a/tools/testing/selftests/kvm/include/arm64/gic_v3_its.h
+++ b/tools/testing/selftests/kvm/include/arm64/gic_v3_its.h
@@ -5,11 +5,10 @@
 
 #include <linux/sizes.h>
 
-void its_init(vm_paddr_t coll_tbl, size_t coll_tbl_sz,
-	      vm_paddr_t device_tbl, size_t device_tbl_sz,
-	      vm_paddr_t cmdq, size_t cmdq_size);
+void its_init(gpa_t coll_tbl, size_t coll_tbl_sz, gpa_t device_tbl,
+	      size_t device_tbl_sz, gpa_t cmdq, size_t cmdq_size);
 
-void its_send_mapd_cmd(void *cmdq_base, u32 device_id, vm_paddr_t itt_base,
+void its_send_mapd_cmd(void *cmdq_base, u32 device_id, gpa_t itt_base,
 		       size_t itt_size, bool valid);
 void its_send_mapc_cmd(void *cmdq_base, u32 vcpu_id, u32 collection_id, bool valid);
 void its_send_mapti_cmd(void *cmdq_base, u32 device_id, u32 event_id,
diff --git a/tools/testing/selftests/kvm/include/arm64/processor.h b/tools/testing/selftests/kvm/include/arm64/processor.h
index ac97a1c436fc..b8a902ba8573 100644
--- a/tools/testing/selftests/kvm/include/arm64/processor.h
+++ b/tools/testing/selftests/kvm/include/arm64/processor.h
@@ -128,7 +128,7 @@
 #define PTE_ADDR_51_50_LPA2_SHIFT	8
 
 void aarch64_vcpu_setup(struct kvm_vcpu *vcpu, struct kvm_vcpu_init *init);
-struct kvm_vcpu *aarch64_vcpu_add(struct kvm_vm *vm, uint32_t vcpu_id,
+struct kvm_vcpu *aarch64_vcpu_add(struct kvm_vm *vm, u32 vcpu_id,
 				  struct kvm_vcpu_init *init, void *guest_code);
 
 struct ex_regs {
@@ -167,8 +167,8 @@ enum {
 			   (v) == VECTOR_SYNC_LOWER_64    || \
 			   (v) == VECTOR_SYNC_LOWER_32)
 
-void aarch64_get_supported_page_sizes(uint32_t ipa, uint32_t *ipa4k,
-					uint32_t *ipa16k, uint32_t *ipa64k);
+void aarch64_get_supported_page_sizes(u32 ipa, u32 *ipa4k,
+				      u32 *ipa16k, u32 *ipa64k);
 
 void vm_init_descriptor_tables(struct kvm_vm *vm);
 void vcpu_init_descriptor_tables(struct kvm_vcpu *vcpu);
@@ -179,8 +179,8 @@ void vm_install_exception_handler(struct kvm_vm *vm,
 void vm_install_sync_handler(struct kvm_vm *vm,
 		int vector, int ec, handler_fn handler);
 
-uint64_t *virt_get_pte_hva_at_level(struct kvm_vm *vm, vm_vaddr_t gva, int level);
-uint64_t *virt_get_pte_hva(struct kvm_vm *vm, vm_vaddr_t gva);
+u64 *virt_get_pte_hva_at_level(struct kvm_vm *vm, gva_t gva, int level);
+u64 *virt_get_pte_hva(struct kvm_vm *vm, gva_t gva);
 
 static inline void cpu_relax(void)
 {
@@ -287,9 +287,9 @@ struct arm_smccc_res {
  * @res: pointer to write the return values from registers x0-x3
  *
  */
-void smccc_hvc(uint32_t function_id, uint64_t arg0, uint64_t arg1,
-	       uint64_t arg2, uint64_t arg3, uint64_t arg4, uint64_t arg5,
-	       uint64_t arg6, struct arm_smccc_res *res);
+void smccc_hvc(u32 function_id, u64 arg0, u64 arg1,
+	       u64 arg2, u64 arg3, u64 arg4, u64 arg5,
+	       u64 arg6, struct arm_smccc_res *res);
 
 /**
  * smccc_smc - Invoke a SMCCC function using the smc conduit
@@ -298,9 +298,9 @@ void smccc_hvc(uint32_t function_id, uint64_t arg0, uint64_t arg1,
  * @res: pointer to write the return values from registers x0-x3
  *
  */
-void smccc_smc(uint32_t function_id, uint64_t arg0, uint64_t arg1,
-	       uint64_t arg2, uint64_t arg3, uint64_t arg4, uint64_t arg5,
-	       uint64_t arg6, struct arm_smccc_res *res);
+void smccc_smc(u32 function_id, u64 arg0, u64 arg1,
+	       u64 arg2, u64 arg3, u64 arg4, u64 arg5,
+	       u64 arg6, struct arm_smccc_res *res);
 
 /* Execute a Wait For Interrupt instruction. */
 void wfi(void);
diff --git a/tools/testing/selftests/kvm/include/arm64/ucall.h b/tools/testing/selftests/kvm/include/arm64/ucall.h
index 4ec801f37f00..2210d3d94c40 100644
--- a/tools/testing/selftests/kvm/include/arm64/ucall.h
+++ b/tools/testing/selftests/kvm/include/arm64/ucall.h
@@ -10,9 +10,9 @@
  * ucall_exit_mmio_addr holds per-VM values (global data is duplicated by each
  * VM), it must not be accessed from host code.
  */
-extern vm_vaddr_t *ucall_exit_mmio_addr;
+extern gva_t *ucall_exit_mmio_addr;
 
-static inline void ucall_arch_do_ucall(vm_vaddr_t uc)
+static inline void ucall_arch_do_ucall(gva_t uc)
 {
 	WRITE_ONCE(*ucall_exit_mmio_addr, uc);
 }
diff --git a/tools/testing/selftests/kvm/include/arm64/vgic.h b/tools/testing/selftests/kvm/include/arm64/vgic.h
index 688beccc9436..1f8b04373987 100644
--- a/tools/testing/selftests/kvm/include/arm64/vgic.h
+++ b/tools/testing/selftests/kvm/include/arm64/vgic.h
@@ -11,27 +11,27 @@
 #include "kvm_util.h"
 
 #define REDIST_REGION_ATTR_ADDR(count, base, flags, index) \
-	(((uint64_t)(count) << 52) | \
-	((uint64_t)((base) >> 16) << 16) | \
-	((uint64_t)(flags) << 12) | \
+	(((u64)(count) << 52) | \
+	((u64)((base) >> 16) << 16) | \
+	((u64)(flags) << 12) | \
 	index)
 
 bool kvm_supports_vgic_v3(void);
-int __vgic_v3_setup(struct kvm_vm *vm, unsigned int nr_vcpus, uint32_t nr_irqs);
+int __vgic_v3_setup(struct kvm_vm *vm, unsigned int nr_vcpus, u32 nr_irqs);
 void __vgic_v3_init(int fd);
-int vgic_v3_setup(struct kvm_vm *vm, unsigned int nr_vcpus, uint32_t nr_irqs);
+int vgic_v3_setup(struct kvm_vm *vm, unsigned int nr_vcpus, u32 nr_irqs);
 
 #define VGIC_MAX_RESERVED	1023
 
-void kvm_irq_set_level_info(int gic_fd, uint32_t intid, int level);
-int _kvm_irq_set_level_info(int gic_fd, uint32_t intid, int level);
+void kvm_irq_set_level_info(int gic_fd, u32 intid, int level);
+int _kvm_irq_set_level_info(int gic_fd, u32 intid, int level);
 
-void kvm_arm_irq_line(struct kvm_vm *vm, uint32_t intid, int level);
-int _kvm_arm_irq_line(struct kvm_vm *vm, uint32_t intid, int level);
+void kvm_arm_irq_line(struct kvm_vm *vm, u32 intid, int level);
+int _kvm_arm_irq_line(struct kvm_vm *vm, u32 intid, int level);
 
 /* The vcpu arg only applies to private interrupts. */
-void kvm_irq_write_ispendr(int gic_fd, uint32_t intid, struct kvm_vcpu *vcpu);
-void kvm_irq_write_isactiver(int gic_fd, uint32_t intid, struct kvm_vcpu *vcpu);
+void kvm_irq_write_ispendr(int gic_fd, u32 intid, struct kvm_vcpu *vcpu);
+void kvm_irq_write_isactiver(int gic_fd, u32 intid, struct kvm_vcpu *vcpu);
 
 #define KVM_IRQCHIP_NUM_PINS	(1020 - 32)
 
diff --git a/tools/testing/selftests/kvm/include/kvm_util.h b/tools/testing/selftests/kvm/include/kvm_util.h
index f861242b4ae8..2ecaaa0e9965 100644
--- a/tools/testing/selftests/kvm/include/kvm_util.h
+++ b/tools/testing/selftests/kvm/include/kvm_util.h
@@ -58,7 +58,7 @@ struct kvm_binary_stats {
 
 struct kvm_vcpu {
 	struct list_head list;
-	uint32_t id;
+	u32 id;
 	int fd;
 	struct kvm_vm *vm;
 	struct kvm_run *run;
@@ -70,8 +70,8 @@ struct kvm_vcpu {
 #endif
 	struct kvm_binary_stats stats;
 	struct kvm_dirty_gfn *dirty_gfns;
-	uint32_t fetch_index;
-	uint32_t dirty_gfns_count;
+	u32 fetch_index;
+	u32 dirty_gfns_count;
 };
 
 struct userspace_mem_regions {
@@ -90,7 +90,7 @@ enum kvm_mem_region_type {
 
 struct kvm_mmu {
 	bool pgd_created;
-	uint64_t pgd;
+	u64 pgd;
 	int pgtable_levels;
 
 	struct kvm_mmu_arch arch;
@@ -105,16 +105,16 @@ struct kvm_vm {
 	unsigned int page_shift;
 	unsigned int pa_bits;
 	unsigned int va_bits;
-	uint64_t max_gfn;
+	u64 max_gfn;
 	struct list_head vcpus;
 	struct userspace_mem_regions regions;
 	struct sparsebit *vpages_valid;
 	struct sparsebit *vpages_mapped;
 	bool has_irqchip;
-	vm_paddr_t ucall_mmio_addr;
-	vm_vaddr_t handlers;
-	uint32_t dirty_ring_size;
-	uint64_t gpa_tag_mask;
+	gpa_t ucall_mmio_addr;
+	gva_t handlers;
+	u32 dirty_ring_size;
+	gpa_t gpa_tag_mask;
 
 	/*
 	 * "mmu" is the guest's stage-1, with a short name because the vast
@@ -132,7 +132,7 @@ struct kvm_vm {
 	 * allocators, e.g., lib/elf uses the memslots[MEM_REGION_CODE]
 	 * memslot.
 	 */
-	uint32_t memslots[NR_MEM_REGIONS];
+	u32 memslots[NR_MEM_REGIONS];
 };
 
 struct vcpu_reg_sublist {
@@ -164,7 +164,7 @@ struct vcpu_reg_list {
 		else
 
 struct userspace_mem_region *
-memslot2region(struct kvm_vm *vm, uint32_t memslot);
+memslot2region(struct kvm_vm *vm, u32 memslot);
 
 static inline struct userspace_mem_region *vm_get_mem_region(struct kvm_vm *vm,
 							     enum kvm_mem_region_type type)
@@ -213,13 +213,13 @@ enum vm_guest_mode {
 };
 
 struct vm_shape {
-	uint32_t type;
-	uint8_t  mode;
-	uint8_t  pad0;
-	uint16_t pad1;
+	u32 type;
+	u8  mode;
+	u8  pad0;
+	u16 pad1;
 };
 
-kvm_static_assert(sizeof(struct vm_shape) == sizeof(uint64_t));
+kvm_static_assert(sizeof(struct vm_shape) == sizeof(u64));
 
 #define VM_TYPE_DEFAULT			0
 
@@ -404,21 +404,22 @@ static inline int vm_check_cap(struct kvm_vm *vm, long cap)
 	return ret;
 }
 
-static inline int __vm_enable_cap(struct kvm_vm *vm, uint32_t cap, uint64_t arg0)
+static inline int __vm_enable_cap(struct kvm_vm *vm, u32 cap, u64 arg0)
 {
 	struct kvm_enable_cap enable_cap = { .cap = cap, .args = { arg0 } };
 
 	return __vm_ioctl(vm, KVM_ENABLE_CAP, &enable_cap);
 }
-static inline void vm_enable_cap(struct kvm_vm *vm, uint32_t cap, uint64_t arg0)
+
+static inline void vm_enable_cap(struct kvm_vm *vm, u32 cap, u64 arg0)
 {
 	struct kvm_enable_cap enable_cap = { .cap = cap, .args = { arg0 } };
 
 	vm_ioctl(vm, KVM_ENABLE_CAP, &enable_cap);
 }
 
-static inline void vm_set_memory_attributes(struct kvm_vm *vm, uint64_t gpa,
-					    uint64_t size, uint64_t attributes)
+static inline void vm_set_memory_attributes(struct kvm_vm *vm, gpa_t gpa,
+					    u64 size, u64 attributes)
 {
 	struct kvm_memory_attributes attr = {
 		.attributes = attributes,
@@ -438,35 +439,35 @@ static inline void vm_set_memory_attributes(struct kvm_vm *vm, uint64_t gpa,
 }
 
 
-static inline void vm_mem_set_private(struct kvm_vm *vm, uint64_t gpa,
-				      uint64_t size)
+static inline void vm_mem_set_private(struct kvm_vm *vm, gpa_t gpa,
+				      u64 size)
 {
 	vm_set_memory_attributes(vm, gpa, size, KVM_MEMORY_ATTRIBUTE_PRIVATE);
 }
 
-static inline void vm_mem_set_shared(struct kvm_vm *vm, uint64_t gpa,
-				     uint64_t size)
+static inline void vm_mem_set_shared(struct kvm_vm *vm, gpa_t gpa,
+				     u64 size)
 {
 	vm_set_memory_attributes(vm, gpa, size, 0);
 }
 
-void vm_guest_mem_fallocate(struct kvm_vm *vm, uint64_t gpa, uint64_t size,
+void vm_guest_mem_fallocate(struct kvm_vm *vm, gpa_t gpa, u64 size,
 			    bool punch_hole);
 
-static inline void vm_guest_mem_punch_hole(struct kvm_vm *vm, uint64_t gpa,
-					   uint64_t size)
+static inline void vm_guest_mem_punch_hole(struct kvm_vm *vm, gpa_t gpa,
+					   u64 size)
 {
 	vm_guest_mem_fallocate(vm, gpa, size, true);
 }
 
-static inline void vm_guest_mem_allocate(struct kvm_vm *vm, uint64_t gpa,
-					 uint64_t size)
+static inline void vm_guest_mem_allocate(struct kvm_vm *vm, gpa_t gpa,
+					 u64 size)
 {
 	vm_guest_mem_fallocate(vm, gpa, size, false);
 }
 
-void vm_enable_dirty_ring(struct kvm_vm *vm, uint32_t ring_size);
-const char *vm_guest_mode_string(uint32_t i);
+void vm_enable_dirty_ring(struct kvm_vm *vm, u32 ring_size);
+const char *vm_guest_mode_string(u32 i);
 
 void kvm_vm_free(struct kvm_vm *vmp);
 void kvm_vm_restart(struct kvm_vm *vmp);
@@ -474,7 +475,7 @@ void kvm_vm_release(struct kvm_vm *vmp);
 void kvm_vm_elf_load(struct kvm_vm *vm, const char *filename);
 int kvm_memfd_alloc(size_t size, bool hugepages);
 
-void vm_dump(FILE *stream, struct kvm_vm *vm, uint8_t indent);
+void vm_dump(FILE *stream, struct kvm_vm *vm, u8 indent);
 
 static inline void kvm_vm_get_dirty_log(struct kvm_vm *vm, int slot, void *log)
 {
@@ -484,7 +485,7 @@ static inline void kvm_vm_get_dirty_log(struct kvm_vm *vm, int slot, void *log)
 }
 
 static inline void kvm_vm_clear_dirty_log(struct kvm_vm *vm, int slot, void *log,
-					  uint64_t first_page, uint32_t num_pages)
+					  u64 first_page, u32 num_pages)
 {
 	struct kvm_clear_dirty_log args = {
 		.dirty_bitmap = log,
@@ -496,14 +497,14 @@ static inline void kvm_vm_clear_dirty_log(struct kvm_vm *vm, int slot, void *log
 	vm_ioctl(vm, KVM_CLEAR_DIRTY_LOG, &args);
 }
 
-static inline uint32_t kvm_vm_reset_dirty_ring(struct kvm_vm *vm)
+static inline u32 kvm_vm_reset_dirty_ring(struct kvm_vm *vm)
 {
 	return __vm_ioctl(vm, KVM_RESET_DIRTY_RINGS, NULL);
 }
 
 static inline void kvm_vm_register_coalesced_io(struct kvm_vm *vm,
-						uint64_t address,
-						uint64_t size, bool pio)
+						u64 address,
+						u64 size, bool pio)
 {
 	struct kvm_coalesced_mmio_zone zone = {
 		.addr = address,
@@ -515,8 +516,8 @@ static inline void kvm_vm_register_coalesced_io(struct kvm_vm *vm,
 }
 
 static inline void kvm_vm_unregister_coalesced_io(struct kvm_vm *vm,
-						  uint64_t address,
-						  uint64_t size, bool pio)
+						  u64 address,
+						  u64 size, bool pio)
 {
 	struct kvm_coalesced_mmio_zone zone = {
 		.addr = address,
@@ -535,8 +536,8 @@ static inline int vm_get_stats_fd(struct kvm_vm *vm)
 	return fd;
 }
 
-static inline int __kvm_irqfd(struct kvm_vm *vm, uint32_t gsi, int eventfd,
-			      uint32_t flags)
+static inline int __kvm_irqfd(struct kvm_vm *vm, u32 gsi, int eventfd,
+			      u32 flags)
 {
 	struct kvm_irqfd irqfd = {
 		.fd = eventfd,
@@ -548,20 +549,19 @@ static inline int __kvm_irqfd(struct kvm_vm *vm, uint32_t gsi, int eventfd,
 	return __vm_ioctl(vm, KVM_IRQFD, &irqfd);
 }
 
-static inline void kvm_irqfd(struct kvm_vm *vm, uint32_t gsi, int eventfd,
-			      uint32_t flags)
+static inline void kvm_irqfd(struct kvm_vm *vm, u32 gsi, int eventfd, u32 flags)
 {
 	int ret = __kvm_irqfd(vm, gsi, eventfd, flags);
 
 	TEST_ASSERT_VM_VCPU_IOCTL(!ret, KVM_IRQFD, ret, vm);
 }
 
-static inline void kvm_assign_irqfd(struct kvm_vm *vm, uint32_t gsi, int eventfd)
+static inline void kvm_assign_irqfd(struct kvm_vm *vm, u32 gsi, int eventfd)
 {
 	kvm_irqfd(vm, gsi, eventfd, 0);
 }
 
-static inline void kvm_deassign_irqfd(struct kvm_vm *vm, uint32_t gsi, int eventfd)
+static inline void kvm_deassign_irqfd(struct kvm_vm *vm, u32 gsi, int eventfd)
 {
 	kvm_irqfd(vm, gsi, eventfd, KVM_IRQFD_FLAG_DEASSIGN);
 }
@@ -610,15 +610,15 @@ static inline struct kvm_stats_desc *get_stats_descriptor(struct kvm_stats_desc
 }
 
 void read_stat_data(int stats_fd, struct kvm_stats_header *header,
-		    struct kvm_stats_desc *desc, uint64_t *data,
+		    struct kvm_stats_desc *desc, u64 *data,
 		    size_t max_elements);
 
 void kvm_get_stat(struct kvm_binary_stats *stats, const char *name,
-		  uint64_t *data, size_t max_elements);
+		  u64 *data, size_t max_elements);
 
 #define __get_stat(stats, stat)							\
 ({										\
-	uint64_t data;								\
+	u64 data;								\
 										\
 	kvm_get_stat(stats, #stat, &data, 1);					\
 	data;									\
@@ -664,8 +664,8 @@ static inline bool is_smt_on(void)
 
 void vm_create_irqchip(struct kvm_vm *vm);
 
-static inline int __vm_create_guest_memfd(struct kvm_vm *vm, uint64_t size,
-					uint64_t flags)
+static inline int __vm_create_guest_memfd(struct kvm_vm *vm, u64 size,
+					  u64 flags)
 {
 	struct kvm_create_guest_memfd guest_memfd = {
 		.size = size,
@@ -675,8 +675,8 @@ static inline int __vm_create_guest_memfd(struct kvm_vm *vm, uint64_t size,
 	return __vm_ioctl(vm, KVM_CREATE_GUEST_MEMFD, &guest_memfd);
 }
 
-static inline int vm_create_guest_memfd(struct kvm_vm *vm, uint64_t size,
-					uint64_t flags)
+static inline int vm_create_guest_memfd(struct kvm_vm *vm, u64 size,
+					u64 flags)
 {
 	int fd = __vm_create_guest_memfd(vm, size, flags);
 
@@ -684,24 +684,23 @@ static inline int vm_create_guest_memfd(struct kvm_vm *vm, uint64_t size,
 	return fd;
 }
 
-void vm_set_user_memory_region(struct kvm_vm *vm, uint32_t slot, uint32_t flags,
-			       uint64_t gpa, uint64_t size, void *hva);
-int __vm_set_user_memory_region(struct kvm_vm *vm, uint32_t slot, uint32_t flags,
-				uint64_t gpa, uint64_t size, void *hva);
-void vm_set_user_memory_region2(struct kvm_vm *vm, uint32_t slot, uint32_t flags,
-				uint64_t gpa, uint64_t size, void *hva,
-				uint32_t guest_memfd, uint64_t guest_memfd_offset);
-int __vm_set_user_memory_region2(struct kvm_vm *vm, uint32_t slot, uint32_t flags,
-				 uint64_t gpa, uint64_t size, void *hva,
-				 uint32_t guest_memfd, uint64_t guest_memfd_offset);
+void vm_set_user_memory_region(struct kvm_vm *vm, u32 slot, u32 flags,
+			       gpa_t gpa, u64 size, void *hva);
+int __vm_set_user_memory_region(struct kvm_vm *vm, u32 slot, u32 flags,
+				gpa_t gpa, u64 size, void *hva);
+void vm_set_user_memory_region2(struct kvm_vm *vm, u32 slot, u32 flags,
+				gpa_t gpa, u64 size, void *hva,
+				u32 guest_memfd, u64 guest_memfd_offset);
+int __vm_set_user_memory_region2(struct kvm_vm *vm, u32 slot, u32 flags,
+				 gpa_t gpa, u64 size, void *hva,
+				 u32 guest_memfd, u64 guest_memfd_offset);
 
 void vm_userspace_mem_region_add(struct kvm_vm *vm,
 				 enum vm_mem_backing_src_type src_type,
-				 uint64_t gpa, uint32_t slot, uint64_t npages,
-				 uint32_t flags);
+				 gpa_t gpa, u32 slot, u64 npages, u32 flags);
 void vm_mem_add(struct kvm_vm *vm, enum vm_mem_backing_src_type src_type,
-		uint64_t gpa, uint32_t slot, uint64_t npages, uint32_t flags,
-		int guest_memfd_fd, uint64_t guest_memfd_offset);
+		gpa_t gpa, u32 slot, u64 npages, u32 flags,
+		int guest_memfd_fd, u64 guest_memfd_offset);
 
 #ifndef vm_arch_has_protected_memory
 static inline bool vm_arch_has_protected_memory(struct kvm_vm *vm)
@@ -710,36 +709,34 @@ static inline bool vm_arch_has_protected_memory(struct kvm_vm *vm)
 }
 #endif
 
-void vm_mem_region_set_flags(struct kvm_vm *vm, uint32_t slot, uint32_t flags);
-void vm_mem_region_reload(struct kvm_vm *vm, uint32_t slot);
-void vm_mem_region_move(struct kvm_vm *vm, uint32_t slot, uint64_t new_gpa);
-void vm_mem_region_delete(struct kvm_vm *vm, uint32_t slot);
-struct kvm_vcpu *__vm_vcpu_add(struct kvm_vm *vm, uint32_t vcpu_id);
-void vm_populate_vaddr_bitmap(struct kvm_vm *vm);
-vm_vaddr_t vm_vaddr_unused_gap(struct kvm_vm *vm, size_t sz, vm_vaddr_t vaddr_min);
-vm_vaddr_t vm_vaddr_alloc(struct kvm_vm *vm, size_t sz, vm_vaddr_t vaddr_min);
-vm_vaddr_t __vm_vaddr_alloc(struct kvm_vm *vm, size_t sz, vm_vaddr_t vaddr_min,
-			    enum kvm_mem_region_type type);
-vm_vaddr_t vm_vaddr_alloc_shared(struct kvm_vm *vm, size_t sz,
-				 vm_vaddr_t vaddr_min,
-				 enum kvm_mem_region_type type);
-vm_vaddr_t vm_vaddr_alloc_pages(struct kvm_vm *vm, int nr_pages);
-vm_vaddr_t __vm_vaddr_alloc_page(struct kvm_vm *vm,
-				 enum kvm_mem_region_type type);
-vm_vaddr_t vm_vaddr_alloc_page(struct kvm_vm *vm);
-
-void virt_map(struct kvm_vm *vm, uint64_t vaddr, uint64_t paddr,
+void vm_mem_region_set_flags(struct kvm_vm *vm, u32 slot, u32 flags);
+void vm_mem_region_reload(struct kvm_vm *vm, u32 slot);
+void vm_mem_region_move(struct kvm_vm *vm, u32 slot, u64 new_gpa);
+void vm_mem_region_delete(struct kvm_vm *vm, u32 slot);
+struct kvm_vcpu *__vm_vcpu_add(struct kvm_vm *vm, u32 vcpu_id);
+void vm_populate_gva_bitmap(struct kvm_vm *vm);
+gva_t vm_unused_gva_gap(struct kvm_vm *vm, size_t sz, gva_t min_gva);
+gva_t vm_alloc(struct kvm_vm *vm, size_t sz, gva_t min_gva);
+gva_t __vm_alloc(struct kvm_vm *vm, size_t sz, gva_t min_gva,
+		 enum kvm_mem_region_type type);
+gva_t vm_alloc_shared(struct kvm_vm *vm, size_t sz, gva_t min_gva,
+		      enum kvm_mem_region_type type);
+gva_t vm_alloc_pages(struct kvm_vm *vm, int nr_pages);
+gva_t __vm_alloc_page(struct kvm_vm *vm, enum kvm_mem_region_type type);
+gva_t vm_alloc_page(struct kvm_vm *vm);
+
+void virt_map(struct kvm_vm *vm, gva_t gva, gpa_t gpa,
 	      unsigned int npages);
-void *addr_gpa2hva(struct kvm_vm *vm, vm_paddr_t gpa);
-void *addr_gva2hva(struct kvm_vm *vm, vm_vaddr_t gva);
-vm_paddr_t addr_hva2gpa(struct kvm_vm *vm, void *hva);
-void *addr_gpa2alias(struct kvm_vm *vm, vm_paddr_t gpa);
+void *addr_gpa2hva(struct kvm_vm *vm, gpa_t gpa);
+void *addr_gva2hva(struct kvm_vm *vm, gva_t gva);
+gpa_t addr_hva2gpa(struct kvm_vm *vm, void *hva);
+void *addr_gpa2alias(struct kvm_vm *vm, gpa_t gpa);
 
 #ifndef vcpu_arch_put_guest
 #define vcpu_arch_put_guest(mem, val) do { (mem) = (val); } while (0)
 #endif
 
-static inline vm_paddr_t vm_untag_gpa(struct kvm_vm *vm, vm_paddr_t gpa)
+static inline gpa_t vm_untag_gpa(struct kvm_vm *vm, gpa_t gpa)
 {
 	return gpa & ~vm->gpa_tag_mask;
 }
@@ -755,8 +752,8 @@ static inline int __vcpu_run(struct kvm_vcpu *vcpu)
 void vcpu_run_complete_io(struct kvm_vcpu *vcpu);
 struct kvm_reg_list *vcpu_get_reg_list(struct kvm_vcpu *vcpu);
 
-static inline void vcpu_enable_cap(struct kvm_vcpu *vcpu, uint32_t cap,
-				   uint64_t arg0)
+static inline void vcpu_enable_cap(struct kvm_vcpu *vcpu, u32 cap,
+				   u64 arg0)
 {
 	struct kvm_enable_cap enable_cap = { .cap = cap, .args = { arg0 } };
 
@@ -811,31 +808,34 @@ static inline void vcpu_fpu_set(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
 	vcpu_ioctl(vcpu, KVM_SET_FPU, fpu);
 }
 
-static inline int __vcpu_get_reg(struct kvm_vcpu *vcpu, uint64_t id, void *addr)
+static inline int __vcpu_get_reg(struct kvm_vcpu *vcpu, u64 id, void *addr)
 {
-	struct kvm_one_reg reg = { .id = id, .addr = (uint64_t)addr };
+	struct kvm_one_reg reg = { .id = id, .addr = (u64)addr };
 
 	return __vcpu_ioctl(vcpu, KVM_GET_ONE_REG, &reg);
 }
-static inline int __vcpu_set_reg(struct kvm_vcpu *vcpu, uint64_t id, uint64_t val)
+
+static inline int __vcpu_set_reg(struct kvm_vcpu *vcpu, u64 id, u64 val)
 {
-	struct kvm_one_reg reg = { .id = id, .addr = (uint64_t)&val };
+	struct kvm_one_reg reg = { .id = id, .addr = (u64)&val };
 
 	return __vcpu_ioctl(vcpu, KVM_SET_ONE_REG, &reg);
 }
-static inline uint64_t vcpu_get_reg(struct kvm_vcpu *vcpu, uint64_t id)
+
+static inline u64 vcpu_get_reg(struct kvm_vcpu *vcpu, u64 id)
 {
-	uint64_t val;
-	struct kvm_one_reg reg = { .id = id, .addr = (uint64_t)&val };
+	u64 val;
+	struct kvm_one_reg reg = { .id = id, .addr = (u64)&val };
 
 	TEST_ASSERT(KVM_REG_SIZE(id) <= sizeof(val), "Reg %lx too big", id);
 
 	vcpu_ioctl(vcpu, KVM_GET_ONE_REG, &reg);
 	return val;
 }
-static inline void vcpu_set_reg(struct kvm_vcpu *vcpu, uint64_t id, uint64_t val)
+
+static inline void vcpu_set_reg(struct kvm_vcpu *vcpu, u64 id, u64 val)
 {
-	struct kvm_one_reg reg = { .id = id, .addr = (uint64_t)&val };
+	struct kvm_one_reg reg = { .id = id, .addr = (u64)&val };
 
 	TEST_ASSERT(KVM_REG_SIZE(id) <= sizeof(val), "Reg %lx too big", id);
 
@@ -880,75 +880,75 @@ static inline int vcpu_get_stats_fd(struct kvm_vcpu *vcpu)
 	return fd;
 }
 
-int __kvm_has_device_attr(int dev_fd, uint32_t group, uint64_t attr);
+int __kvm_has_device_attr(int dev_fd, u32 group, u64 attr);
 
-static inline void kvm_has_device_attr(int dev_fd, uint32_t group, uint64_t attr)
+static inline void kvm_has_device_attr(int dev_fd, u32 group, u64 attr)
 {
 	int ret = __kvm_has_device_attr(dev_fd, group, attr);
 
 	TEST_ASSERT(!ret, "KVM_HAS_DEVICE_ATTR failed, rc: %i errno: %i", ret, errno);
 }
 
-int __kvm_device_attr_get(int dev_fd, uint32_t group, uint64_t attr, void *val);
+int __kvm_device_attr_get(int dev_fd, u32 group, u64 attr, void *val);
 
-static inline void kvm_device_attr_get(int dev_fd, uint32_t group,
-				       uint64_t attr, void *val)
+static inline void kvm_device_attr_get(int dev_fd, u32 group,
+				       u64 attr, void *val)
 {
 	int ret = __kvm_device_attr_get(dev_fd, group, attr, val);
 
 	TEST_ASSERT(!ret, KVM_IOCTL_ERROR(KVM_GET_DEVICE_ATTR, ret));
 }
 
-int __kvm_device_attr_set(int dev_fd, uint32_t group, uint64_t attr, void *val);
+int __kvm_device_attr_set(int dev_fd, u32 group, u64 attr, void *val);
 
-static inline void kvm_device_attr_set(int dev_fd, uint32_t group,
-				       uint64_t attr, void *val)
+static inline void kvm_device_attr_set(int dev_fd, u32 group,
+				       u64 attr, void *val)
 {
 	int ret = __kvm_device_attr_set(dev_fd, group, attr, val);
 
 	TEST_ASSERT(!ret, KVM_IOCTL_ERROR(KVM_SET_DEVICE_ATTR, ret));
 }
 
-static inline int __vcpu_has_device_attr(struct kvm_vcpu *vcpu, uint32_t group,
-					 uint64_t attr)
+static inline int __vcpu_has_device_attr(struct kvm_vcpu *vcpu, u32 group,
+					 u64 attr)
 {
 	return __kvm_has_device_attr(vcpu->fd, group, attr);
 }
 
-static inline void vcpu_has_device_attr(struct kvm_vcpu *vcpu, uint32_t group,
-					uint64_t attr)
+static inline void vcpu_has_device_attr(struct kvm_vcpu *vcpu, u32 group,
+					u64 attr)
 {
 	kvm_has_device_attr(vcpu->fd, group, attr);
 }
 
-static inline int __vcpu_device_attr_get(struct kvm_vcpu *vcpu, uint32_t group,
-					 uint64_t attr, void *val)
+static inline int __vcpu_device_attr_get(struct kvm_vcpu *vcpu, u32 group,
+					 u64 attr, void *val)
 {
 	return __kvm_device_attr_get(vcpu->fd, group, attr, val);
 }
 
-static inline void vcpu_device_attr_get(struct kvm_vcpu *vcpu, uint32_t group,
-					uint64_t attr, void *val)
+static inline void vcpu_device_attr_get(struct kvm_vcpu *vcpu, u32 group,
+					u64 attr, void *val)
 {
 	kvm_device_attr_get(vcpu->fd, group, attr, val);
 }
 
-static inline int __vcpu_device_attr_set(struct kvm_vcpu *vcpu, uint32_t group,
-					 uint64_t attr, void *val)
+static inline int __vcpu_device_attr_set(struct kvm_vcpu *vcpu, u32 group,
+					 u64 attr, void *val)
 {
 	return __kvm_device_attr_set(vcpu->fd, group, attr, val);
 }
 
-static inline void vcpu_device_attr_set(struct kvm_vcpu *vcpu, uint32_t group,
-					uint64_t attr, void *val)
+static inline void vcpu_device_attr_set(struct kvm_vcpu *vcpu, u32 group,
+					u64 attr, void *val)
 {
 	kvm_device_attr_set(vcpu->fd, group, attr, val);
 }
 
-int __kvm_test_create_device(struct kvm_vm *vm, uint64_t type);
-int __kvm_create_device(struct kvm_vm *vm, uint64_t type);
+int __kvm_test_create_device(struct kvm_vm *vm, u64 type);
+int __kvm_create_device(struct kvm_vm *vm, u64 type);
 
-static inline int kvm_create_device(struct kvm_vm *vm, uint64_t type)
+static inline int kvm_create_device(struct kvm_vm *vm, u64 type)
 {
 	int fd = __kvm_create_device(vm, type);
 
@@ -964,7 +964,7 @@ void *vcpu_map_dirty_ring(struct kvm_vcpu *vcpu);
  * Input Args:
  *   vcpu - vCPU
  *   num - number of arguments
- *   ... - arguments, each of type uint64_t
+ *   ... - arguments, each of type u64
  *
  * Output Args: None
  *
@@ -972,40 +972,38 @@ void *vcpu_map_dirty_ring(struct kvm_vcpu *vcpu);
  *
  * Sets the first @num input parameters for the function at @vcpu's entry point,
  * per the C calling convention of the architecture, to the values given as
- * variable args. Each of the variable args is expected to be of type uint64_t.
+ * variable args. Each of the variable args is expected to be of type u64.
  * The maximum @num can be is specific to the architecture.
  */
 void vcpu_args_set(struct kvm_vcpu *vcpu, unsigned int num, ...);
 
-void kvm_irq_line(struct kvm_vm *vm, uint32_t irq, int level);
-int _kvm_irq_line(struct kvm_vm *vm, uint32_t irq, int level);
+void kvm_irq_line(struct kvm_vm *vm, u32 irq, int level);
+int _kvm_irq_line(struct kvm_vm *vm, u32 irq, int level);
 
 #define KVM_MAX_IRQ_ROUTES		4096
 
 struct kvm_irq_routing *kvm_gsi_routing_create(void);
 void kvm_gsi_routing_irqchip_add(struct kvm_irq_routing *routing,
-		uint32_t gsi, uint32_t pin);
+		u32 gsi, u32 pin);
 int _kvm_gsi_routing_write(struct kvm_vm *vm, struct kvm_irq_routing *routing);
 void kvm_gsi_routing_write(struct kvm_vm *vm, struct kvm_irq_routing *routing);
 
 const char *exit_reason_str(unsigned int exit_reason);
 
-vm_paddr_t vm_phy_page_alloc(struct kvm_vm *vm, vm_paddr_t paddr_min,
-			     uint32_t memslot);
-vm_paddr_t __vm_phy_pages_alloc(struct kvm_vm *vm, size_t num,
-				vm_paddr_t paddr_min, uint32_t memslot,
-				bool protected);
-vm_paddr_t vm_alloc_page_table(struct kvm_vm *vm);
+gpa_t vm_phy_page_alloc(struct kvm_vm *vm, gpa_t min_gpa, u32 memslot);
+gpa_t __vm_phy_pages_alloc(struct kvm_vm *vm, size_t num, gpa_t min_gpa,
+			   u32 memslot, bool protected);
+gpa_t vm_alloc_page_table(struct kvm_vm *vm);
 
-static inline vm_paddr_t vm_phy_pages_alloc(struct kvm_vm *vm, size_t num,
-					    vm_paddr_t paddr_min, uint32_t memslot)
+static inline gpa_t vm_phy_pages_alloc(struct kvm_vm *vm, size_t num,
+				       gpa_t min_gpa, u32 memslot)
 {
 	/*
 	 * By default, allocate memory as protected for VMs that support
 	 * protected memory, as the majority of memory for such VMs is
 	 * protected, i.e. using shared memory is effectively opt-in.
 	 */
-	return __vm_phy_pages_alloc(vm, num, paddr_min, memslot,
+	return __vm_phy_pages_alloc(vm, num, min_gpa, memslot,
 				    vm_arch_has_protected_memory(vm));
 }
 
@@ -1016,8 +1014,8 @@ static inline vm_paddr_t vm_phy_pages_alloc(struct kvm_vm *vm, size_t num,
  * calculate the amount of memory needed for per-vCPU data, e.g. stacks.
  */
 struct kvm_vm *____vm_create(struct vm_shape shape);
-struct kvm_vm *__vm_create(struct vm_shape shape, uint32_t nr_runnable_vcpus,
-			   uint64_t nr_extra_pages);
+struct kvm_vm *__vm_create(struct vm_shape shape, u32 nr_runnable_vcpus,
+			   u64 nr_extra_pages);
 
 static inline struct kvm_vm *vm_create_barebones(void)
 {
@@ -1034,16 +1032,16 @@ static inline struct kvm_vm *vm_create_barebones_type(unsigned long type)
 	return ____vm_create(shape);
 }
 
-static inline struct kvm_vm *vm_create(uint32_t nr_runnable_vcpus)
+static inline struct kvm_vm *vm_create(u32 nr_runnable_vcpus)
 {
 	return __vm_create(VM_SHAPE_DEFAULT, nr_runnable_vcpus, 0);
 }
 
-struct kvm_vm *__vm_create_with_vcpus(struct vm_shape shape, uint32_t nr_vcpus,
-				      uint64_t extra_mem_pages,
+struct kvm_vm *__vm_create_with_vcpus(struct vm_shape shape, u32 nr_vcpus,
+				      u64 extra_mem_pages,
 				      void *guest_code, struct kvm_vcpu *vcpus[]);
 
-static inline struct kvm_vm *vm_create_with_vcpus(uint32_t nr_vcpus,
+static inline struct kvm_vm *vm_create_with_vcpus(u32 nr_vcpus,
 						  void *guest_code,
 						  struct kvm_vcpu *vcpus[])
 {
@@ -1054,7 +1052,7 @@ static inline struct kvm_vm *vm_create_with_vcpus(uint32_t nr_vcpus,
 
 struct kvm_vm *__vm_create_shape_with_one_vcpu(struct vm_shape shape,
 					       struct kvm_vcpu **vcpu,
-					       uint64_t extra_mem_pages,
+					       u64 extra_mem_pages,
 					       void *guest_code);
 
 /*
@@ -1062,7 +1060,7 @@ struct kvm_vm *__vm_create_shape_with_one_vcpu(struct vm_shape shape,
  * additional pages of guest memory.  Returns the VM and vCPU (via out param).
  */
 static inline struct kvm_vm *__vm_create_with_one_vcpu(struct kvm_vcpu **vcpu,
-						       uint64_t extra_mem_pages,
+						       u64 extra_mem_pages,
 						       void *guest_code)
 {
 	return __vm_create_shape_with_one_vcpu(VM_SHAPE_DEFAULT, vcpu,
@@ -1084,7 +1082,7 @@ static inline struct kvm_vm *vm_create_shape_with_one_vcpu(struct vm_shape shape
 
 struct kvm_vcpu *vm_recreate_with_one_vcpu(struct kvm_vm *vm);
 
-void kvm_set_files_rlimit(uint32_t nr_vcpus);
+void kvm_set_files_rlimit(u32 nr_vcpus);
 
 int __pin_task_to_cpu(pthread_t task, int cpu);
 
@@ -1115,7 +1113,7 @@ static inline int pin_self_to_any_cpu(void)
 }
 
 void kvm_print_vcpu_pinning_help(void);
-void kvm_parse_vcpu_pinning(const char *pcpus_string, uint32_t vcpu_to_pcpu[],
+void kvm_parse_vcpu_pinning(const char *pcpus_string, u32 vcpu_to_pcpu[],
 			    int nr_vcpus);
 
 unsigned long vm_compute_max_gfn(struct kvm_vm *vm);
@@ -1131,12 +1129,12 @@ vm_adjust_num_guest_pages(enum vm_guest_mode mode, unsigned int num_guest_pages)
 }
 
 #define sync_global_to_guest(vm, g) ({				\
-	typeof(g) *_p = addr_gva2hva(vm, (vm_vaddr_t)&(g));	\
+	typeof(g) *_p = addr_gva2hva(vm, (gva_t)&(g));		\
 	memcpy(_p, &(g), sizeof(g));				\
 })
 
 #define sync_global_from_guest(vm, g) ({			\
-	typeof(g) *_p = addr_gva2hva(vm, (vm_vaddr_t)&(g));	\
+	typeof(g) *_p = addr_gva2hva(vm, (gva_t)&(g));		\
 	memcpy(&(g), _p, sizeof(g));				\
 })
 
@@ -1147,7 +1145,7 @@ vm_adjust_num_guest_pages(enum vm_guest_mode mode, unsigned int num_guest_pages)
  * undesirable to change the host's copy of the global.
  */
 #define write_guest_global(vm, g, val) ({			\
-	typeof(g) *_p = addr_gva2hva(vm, (vm_vaddr_t)&(g));	\
+	typeof(g) *_p = addr_gva2hva(vm, (gva_t)&(g));		\
 	typeof(g) _val = val;					\
 								\
 	memcpy(_p, &(_val), sizeof(g));				\
@@ -1156,10 +1154,10 @@ vm_adjust_num_guest_pages(enum vm_guest_mode mode, unsigned int num_guest_pages)
 void assert_on_unhandled_exception(struct kvm_vcpu *vcpu);
 
 void vcpu_arch_dump(FILE *stream, struct kvm_vcpu *vcpu,
-		    uint8_t indent);
+		    u8 indent);
 
 static inline void vcpu_dump(FILE *stream, struct kvm_vcpu *vcpu,
-			     uint8_t indent)
+			     u8 indent)
 {
 	vcpu_arch_dump(stream, vcpu, indent);
 }
@@ -1171,10 +1169,10 @@ static inline void vcpu_dump(FILE *stream, struct kvm_vcpu *vcpu,
  *   vm - Virtual Machine
  *   vcpu_id - The id of the VCPU to add to the VM.
  */
-struct kvm_vcpu *vm_arch_vcpu_add(struct kvm_vm *vm, uint32_t vcpu_id);
+struct kvm_vcpu *vm_arch_vcpu_add(struct kvm_vm *vm, u32 vcpu_id);
 void vcpu_arch_set_entry_point(struct kvm_vcpu *vcpu, void *guest_code);
 
-static inline struct kvm_vcpu *vm_vcpu_add(struct kvm_vm *vm, uint32_t vcpu_id,
+static inline struct kvm_vcpu *vm_vcpu_add(struct kvm_vm *vm, u32 vcpu_id,
 					   void *guest_code)
 {
 	struct kvm_vcpu *vcpu = vm_arch_vcpu_add(vm, vcpu_id);
@@ -1185,10 +1183,10 @@ static inline struct kvm_vcpu *vm_vcpu_add(struct kvm_vm *vm, uint32_t vcpu_id,
 }
 
 /* Re-create a vCPU after restarting a VM, e.g. for state save/restore tests. */
-struct kvm_vcpu *vm_arch_vcpu_recreate(struct kvm_vm *vm, uint32_t vcpu_id);
+struct kvm_vcpu *vm_arch_vcpu_recreate(struct kvm_vm *vm, u32 vcpu_id);
 
 static inline struct kvm_vcpu *vm_vcpu_recreate(struct kvm_vm *vm,
-						uint32_t vcpu_id)
+						u32 vcpu_id)
 {
 	return vm_arch_vcpu_recreate(vm, vcpu_id);
 }
@@ -1203,27 +1201,15 @@ static inline void virt_pgd_alloc(struct kvm_vm *vm)
 }
 
 /*
- * VM Virtual Page Map
- *
- * Input Args:
- *   vm - Virtual Machine
- *   vaddr - VM Virtual Address
- *   paddr - VM Physical Address
- *   memslot - Memory region slot for new virtual translation tables
- *
- * Output Args: None
- *
- * Return: None
- *
  * Within @vm, creates a virtual translation for the page starting
- * at @vaddr to the page starting at @paddr.
+ * at @gva to the page starting at @gpa.
  */
-void virt_arch_pg_map(struct kvm_vm *vm, uint64_t vaddr, uint64_t paddr);
+void virt_arch_pg_map(struct kvm_vm *vm, gva_t gva, gpa_t gpa);
 
-static inline void virt_pg_map(struct kvm_vm *vm, uint64_t vaddr, uint64_t paddr)
+static inline void virt_pg_map(struct kvm_vm *vm, gva_t gva, gpa_t gpa)
 {
-	virt_arch_pg_map(vm, vaddr, paddr);
-	sparsebit_set(vm->vpages_mapped, vaddr >> vm->page_shift);
+	virt_arch_pg_map(vm, gva, gpa);
+	sparsebit_set(vm->vpages_mapped, gva >> vm->page_shift);
 }
 
 
@@ -1242,9 +1228,9 @@ static inline void virt_pg_map(struct kvm_vm *vm, uint64_t vaddr, uint64_t paddr
  * Returns the VM physical address of the translated VM virtual
  * address given by @gva.
  */
-vm_paddr_t addr_arch_gva2gpa(struct kvm_vm *vm, vm_vaddr_t gva);
+gpa_t addr_arch_gva2gpa(struct kvm_vm *vm, gva_t gva);
 
-static inline vm_paddr_t addr_gva2gpa(struct kvm_vm *vm, vm_vaddr_t gva)
+static inline gpa_t addr_gva2gpa(struct kvm_vm *vm, gva_t gva)
 {
 	return addr_arch_gva2gpa(vm, gva);
 }
@@ -1264,9 +1250,9 @@ static inline vm_paddr_t addr_gva2gpa(struct kvm_vm *vm, vm_vaddr_t gva)
  * Dumps to the FILE stream given by @stream, the contents of all the
  * virtual translation tables for the VM given by @vm.
  */
-void virt_arch_dump(FILE *stream, struct kvm_vm *vm, uint8_t indent);
+void virt_arch_dump(FILE *stream, struct kvm_vm *vm, u8 indent);
 
-static inline void virt_dump(FILE *stream, struct kvm_vm *vm, uint8_t indent)
+static inline void virt_dump(FILE *stream, struct kvm_vm *vm, u8 indent)
 {
 	virt_arch_dump(stream, vm, indent);
 }
@@ -1277,7 +1263,7 @@ static inline int __vm_disable_nx_huge_pages(struct kvm_vm *vm)
 	return __vm_enable_cap(vm, KVM_CAP_VM_DISABLE_NX_HUGE_PAGES, 0);
 }
 
-static inline uint64_t vm_page_align(struct kvm_vm *vm, uint64_t v)
+static inline u64 vm_page_align(struct kvm_vm *vm, u64 v)
 {
 	return (v + vm->page_size - 1) & ~(vm->page_size - 1);
 }
@@ -1293,9 +1279,9 @@ void kvm_arch_vm_post_create(struct kvm_vm *vm, unsigned int nr_vcpus);
 void kvm_arch_vm_finalize_vcpus(struct kvm_vm *vm);
 void kvm_arch_vm_release(struct kvm_vm *vm);
 
-bool vm_is_gpa_protected(struct kvm_vm *vm, vm_paddr_t paddr);
+bool vm_is_gpa_protected(struct kvm_vm *vm, gpa_t gpa);
 
-uint32_t guest_get_vcpuid(void);
+u32 guest_get_vcpuid(void);
 
 bool kvm_arch_has_default_irqchip(void);
 
diff --git a/tools/testing/selftests/kvm/include/kvm_util_types.h b/tools/testing/selftests/kvm/include/kvm_util_types.h
index 0366e9bce7f9..ed0087e31674 100644
--- a/tools/testing/selftests/kvm/include/kvm_util_types.h
+++ b/tools/testing/selftests/kvm/include/kvm_util_types.h
@@ -2,6 +2,8 @@
 #ifndef SELFTEST_KVM_UTIL_TYPES_H
 #define SELFTEST_KVM_UTIL_TYPES_H
 
+#include <linux/types.h>
+
 /*
  * Provide a version of static_assert() that is guaranteed to have an optional
  * message param.  _GNU_SOURCE is defined for all KVM selftests, _GNU_SOURCE
@@ -14,9 +16,9 @@
 #define __kvm_static_assert(expr, msg, ...) _Static_assert(expr, msg)
 #define kvm_static_assert(expr, ...) __kvm_static_assert(expr, ##__VA_ARGS__, #expr)
 
-typedef uint64_t vm_paddr_t; /* Virtual Machine (Guest) physical address */
-typedef uint64_t vm_vaddr_t; /* Virtual Machine (Guest) virtual address */
+typedef u64 gpa_t; /* Virtual Machine (Guest) physical address */
+typedef u64 gva_t; /* Virtual Machine (Guest) virtual address */
 
-#define INVALID_GPA (~(uint64_t)0)
+#define INVALID_GPA (~(u64)0)
 
 #endif /* SELFTEST_KVM_UTIL_TYPES_H */
diff --git a/tools/testing/selftests/kvm/include/loongarch/arch_timer.h b/tools/testing/selftests/kvm/include/loongarch/arch_timer.h
index 2ed106b32c81..3888aeeb3524 100644
--- a/tools/testing/selftests/kvm/include/loongarch/arch_timer.h
+++ b/tools/testing/selftests/kvm/include/loongarch/arch_timer.h
@@ -70,9 +70,9 @@ static inline void timer_set_next_cmp_ms(unsigned int msec, bool period)
 	csr_write(val, LOONGARCH_CSR_TCFG);
 }
 
-static inline void __delay(uint64_t cycles)
+static inline void __delay(u64 cycles)
 {
-	uint64_t start = timer_get_cycles();
+	u64 start = timer_get_cycles();
 
 	while ((timer_get_cycles() - start) < cycles)
 		cpu_relax();
diff --git a/tools/testing/selftests/kvm/include/loongarch/ucall.h b/tools/testing/selftests/kvm/include/loongarch/ucall.h
index 4ec801f37f00..2210d3d94c40 100644
--- a/tools/testing/selftests/kvm/include/loongarch/ucall.h
+++ b/tools/testing/selftests/kvm/include/loongarch/ucall.h
@@ -10,9 +10,9 @@
  * ucall_exit_mmio_addr holds per-VM values (global data is duplicated by each
  * VM), it must not be accessed from host code.
  */
-extern vm_vaddr_t *ucall_exit_mmio_addr;
+extern gva_t *ucall_exit_mmio_addr;
 
-static inline void ucall_arch_do_ucall(vm_vaddr_t uc)
+static inline void ucall_arch_do_ucall(gva_t uc)
 {
 	WRITE_ONCE(*ucall_exit_mmio_addr, uc);
 }
diff --git a/tools/testing/selftests/kvm/include/memstress.h b/tools/testing/selftests/kvm/include/memstress.h
index 9071eb6dea60..0d1d6230cc05 100644
--- a/tools/testing/selftests/kvm/include/memstress.h
+++ b/tools/testing/selftests/kvm/include/memstress.h
@@ -20,9 +20,9 @@
 #define MEMSTRESS_MEM_SLOT_INDEX	1
 
 struct memstress_vcpu_args {
-	uint64_t gpa;
-	uint64_t gva;
-	uint64_t pages;
+	gpa_t gpa;
+	gva_t gva;
+	u64 pages;
 
 	/* Only used by the host userspace part of the vCPU thread */
 	struct kvm_vcpu *vcpu;
@@ -32,11 +32,11 @@ struct memstress_vcpu_args {
 struct memstress_args {
 	struct kvm_vm *vm;
 	/* The starting address and size of the guest test region. */
-	uint64_t gpa;
-	uint64_t size;
-	uint64_t guest_page_size;
-	uint32_t random_seed;
-	uint32_t write_percent;
+	gpa_t gpa;
+	u64 size;
+	u64 guest_page_size;
+	u32 random_seed;
+	u32 write_percent;
 
 	/* Run vCPUs in L2 instead of L1, if the architecture supports it. */
 	bool nested;
@@ -45,7 +45,7 @@ struct memstress_args {
 	/* True if all vCPUs are pinned to pCPUs */
 	bool pin_vcpus;
 	/* The vCPU=>pCPU pinning map. Only valid if pin_vcpus is true. */
-	uint32_t vcpu_to_pcpu[KVM_MAX_VCPUS];
+	u32 vcpu_to_pcpu[KVM_MAX_VCPUS];
 
  	/* Test is done, stop running vCPUs. */
  	bool stop_vcpus;
@@ -56,27 +56,27 @@ struct memstress_args {
 extern struct memstress_args memstress_args;
 
 struct kvm_vm *memstress_create_vm(enum vm_guest_mode mode, int nr_vcpus,
-				   uint64_t vcpu_memory_bytes, int slots,
+				   u64 vcpu_memory_bytes, int slots,
 				   enum vm_mem_backing_src_type backing_src,
 				   bool partition_vcpu_memory_access);
 void memstress_destroy_vm(struct kvm_vm *vm);
 
-void memstress_set_write_percent(struct kvm_vm *vm, uint32_t write_percent);
+void memstress_set_write_percent(struct kvm_vm *vm, u32 write_percent);
 void memstress_set_random_access(struct kvm_vm *vm, bool random_access);
 
 void memstress_start_vcpu_threads(int vcpus, void (*vcpu_fn)(struct memstress_vcpu_args *));
 void memstress_join_vcpu_threads(int vcpus);
-void memstress_guest_code(uint32_t vcpu_id);
+void memstress_guest_code(u32 vcpu_id);
 
-uint64_t memstress_nested_pages(int nr_vcpus);
+u64 memstress_nested_pages(int nr_vcpus);
 void memstress_setup_nested(struct kvm_vm *vm, int nr_vcpus, struct kvm_vcpu *vcpus[]);
 
 void memstress_enable_dirty_logging(struct kvm_vm *vm, int slots);
 void memstress_disable_dirty_logging(struct kvm_vm *vm, int slots);
 void memstress_get_dirty_log(struct kvm_vm *vm, unsigned long *bitmaps[], int slots);
 void memstress_clear_dirty_log(struct kvm_vm *vm, unsigned long *bitmaps[],
-			       int slots, uint64_t pages_per_slot);
-unsigned long **memstress_alloc_bitmaps(int slots, uint64_t pages_per_slot);
+			       int slots, u64 pages_per_slot);
+unsigned long **memstress_alloc_bitmaps(int slots, u64 pages_per_slot);
 void memstress_free_bitmaps(unsigned long *bitmaps[], int slots);
 
 #endif /* SELFTEST_KVM_MEMSTRESS_H */
diff --git a/tools/testing/selftests/kvm/include/riscv/arch_timer.h b/tools/testing/selftests/kvm/include/riscv/arch_timer.h
index 225d81dad064..28ffc014da2a 100644
--- a/tools/testing/selftests/kvm/include/riscv/arch_timer.h
+++ b/tools/testing/selftests/kvm/include/riscv/arch_timer.h
@@ -14,25 +14,25 @@
 static unsigned long timer_freq;
 
 #define msec_to_cycles(msec)	\
-	((timer_freq) * (uint64_t)(msec) / 1000)
+	((timer_freq) * (u64)(msec) / 1000)
 
 #define usec_to_cycles(usec)	\
-	((timer_freq) * (uint64_t)(usec) / 1000000)
+	((timer_freq) * (u64)(usec) / 1000000)
 
 #define cycles_to_usec(cycles) \
-	((uint64_t)(cycles) * 1000000 / (timer_freq))
+	((u64)(cycles) * 1000000 / (timer_freq))
 
-static inline uint64_t timer_get_cycles(void)
+static inline u64 timer_get_cycles(void)
 {
 	return csr_read(CSR_TIME);
 }
 
-static inline void timer_set_cmp(uint64_t cval)
+static inline void timer_set_cmp(u64 cval)
 {
 	csr_write(CSR_STIMECMP, cval);
 }
 
-static inline uint64_t timer_get_cmp(void)
+static inline u64 timer_get_cmp(void)
 {
 	return csr_read(CSR_STIMECMP);
 }
@@ -47,17 +47,17 @@ static inline void timer_irq_disable(void)
 	csr_clear(CSR_SIE, IE_TIE);
 }
 
-static inline void timer_set_next_cmp_ms(uint32_t msec)
+static inline void timer_set_next_cmp_ms(u32 msec)
 {
-	uint64_t now_ct = timer_get_cycles();
-	uint64_t next_ct = now_ct + msec_to_cycles(msec);
+	u64 now_ct = timer_get_cycles();
+	u64 next_ct = now_ct + msec_to_cycles(msec);
 
 	timer_set_cmp(next_ct);
 }
 
-static inline void __delay(uint64_t cycles)
+static inline void __delay(u64 cycles)
 {
-	uint64_t start = timer_get_cycles();
+	u64 start = timer_get_cycles();
 
 	while ((timer_get_cycles() - start) < cycles)
 		cpu_relax();
diff --git a/tools/testing/selftests/kvm/include/riscv/processor.h b/tools/testing/selftests/kvm/include/riscv/processor.h
index 4dade8c4d18e..e3acf2ae9881 100644
--- a/tools/testing/selftests/kvm/include/riscv/processor.h
+++ b/tools/testing/selftests/kvm/include/riscv/processor.h
@@ -25,8 +25,7 @@
 #define GET_RM(insn)            (((insn) & INSN_MASK_FUNCT3) >> INSN_SHIFT_FUNCT3)
 #define GET_CSR_NUM(insn)       (((insn) & INSN_CSR_MASK) >> INSN_CSR_SHIFT)
 
-static inline uint64_t __kvm_reg_id(uint64_t type, uint64_t subtype,
-				    uint64_t idx, uint64_t size)
+static inline u64 __kvm_reg_id(u64 type, u64 subtype, u64 idx, u64 size)
 {
 	return KVM_REG_RISCV | type | subtype | idx | size;
 }
@@ -62,14 +61,14 @@ static inline uint64_t __kvm_reg_id(uint64_t type, uint64_t subtype,
 						     KVM_REG_RISCV_SBI_SINGLE,		\
 						     idx, KVM_REG_SIZE_ULONG)
 
-bool __vcpu_has_ext(struct kvm_vcpu *vcpu, uint64_t ext);
+bool __vcpu_has_ext(struct kvm_vcpu *vcpu, u64 ext);
 
-static inline bool __vcpu_has_isa_ext(struct kvm_vcpu *vcpu, uint64_t isa_ext)
+static inline bool __vcpu_has_isa_ext(struct kvm_vcpu *vcpu, u64 isa_ext)
 {
 	return __vcpu_has_ext(vcpu, RISCV_ISA_EXT_REG(isa_ext));
 }
 
-static inline bool __vcpu_has_sbi_ext(struct kvm_vcpu *vcpu, uint64_t sbi_ext)
+static inline bool __vcpu_has_sbi_ext(struct kvm_vcpu *vcpu, u64 sbi_ext)
 {
 	return __vcpu_has_ext(vcpu, RISCV_SBI_EXT_REG(sbi_ext));
 }
diff --git a/tools/testing/selftests/kvm/include/riscv/ucall.h b/tools/testing/selftests/kvm/include/riscv/ucall.h
index a695ae36f3e0..2de7c6a36096 100644
--- a/tools/testing/selftests/kvm/include/riscv/ucall.h
+++ b/tools/testing/selftests/kvm/include/riscv/ucall.h
@@ -7,11 +7,11 @@
 
 #define UCALL_EXIT_REASON       KVM_EXIT_RISCV_SBI
 
-static inline void ucall_arch_init(struct kvm_vm *vm, vm_paddr_t mmio_gpa)
+static inline void ucall_arch_init(struct kvm_vm *vm, gpa_t mmio_gpa)
 {
 }
 
-static inline void ucall_arch_do_ucall(vm_vaddr_t uc)
+static inline void ucall_arch_do_ucall(gva_t uc)
 {
 	sbi_ecall(KVM_RISCV_SELFTESTS_SBI_EXT,
 		  KVM_RISCV_SELFTESTS_SBI_UCALL,
diff --git a/tools/testing/selftests/kvm/include/s390/diag318_test_handler.h b/tools/testing/selftests/kvm/include/s390/diag318_test_handler.h
index b0ed71302722..6deaf18fec22 100644
--- a/tools/testing/selftests/kvm/include/s390/diag318_test_handler.h
+++ b/tools/testing/selftests/kvm/include/s390/diag318_test_handler.h
@@ -8,6 +8,6 @@
 #ifndef SELFTEST_KVM_DIAG318_TEST_HANDLER
 #define SELFTEST_KVM_DIAG318_TEST_HANDLER
 
-uint64_t get_diag318_info(void);
+u64 get_diag318_info(void);
 
 #endif
diff --git a/tools/testing/selftests/kvm/include/s390/facility.h b/tools/testing/selftests/kvm/include/s390/facility.h
index 00a1ced6538b..41a265742666 100644
--- a/tools/testing/selftests/kvm/include/s390/facility.h
+++ b/tools/testing/selftests/kvm/include/s390/facility.h
@@ -16,7 +16,7 @@
 /* alt_stfle_fac_list[16] + stfle_fac_list[16] */
 #define NB_STFL_DOUBLEWORDS 32
 
-extern uint64_t stfl_doublewords[NB_STFL_DOUBLEWORDS];
+extern u64 stfl_doublewords[NB_STFL_DOUBLEWORDS];
 extern bool stfle_flag;
 
 static inline bool test_bit_inv(unsigned long nr, const unsigned long *ptr)
@@ -24,7 +24,7 @@ static inline bool test_bit_inv(unsigned long nr, const unsigned long *ptr)
 	return test_bit(nr ^ (BITS_PER_LONG - 1), ptr);
 }
 
-static inline void stfle(uint64_t *fac, unsigned int nb_doublewords)
+static inline void stfle(u64 *fac, unsigned int nb_doublewords)
 {
 	register unsigned long r0 asm("0") = nb_doublewords - 1;
 
diff --git a/tools/testing/selftests/kvm/include/s390/ucall.h b/tools/testing/selftests/kvm/include/s390/ucall.h
index 8035a872a351..3907d629304f 100644
--- a/tools/testing/selftests/kvm/include/s390/ucall.h
+++ b/tools/testing/selftests/kvm/include/s390/ucall.h
@@ -6,11 +6,11 @@
 
 #define UCALL_EXIT_REASON       KVM_EXIT_S390_SIEIC
 
-static inline void ucall_arch_init(struct kvm_vm *vm, vm_paddr_t mmio_gpa)
+static inline void ucall_arch_init(struct kvm_vm *vm, gpa_t mmio_gpa)
 {
 }
 
-static inline void ucall_arch_do_ucall(vm_vaddr_t uc)
+static inline void ucall_arch_do_ucall(gva_t uc)
 {
 	/* Exit via DIAGNOSE 0x501 (normally used for breakpoints) */
 	asm volatile ("diag 0,%0,0x501" : : "a"(uc) : "memory");
diff --git a/tools/testing/selftests/kvm/include/sparsebit.h b/tools/testing/selftests/kvm/include/sparsebit.h
index bc760761e1a3..e027e5790946 100644
--- a/tools/testing/selftests/kvm/include/sparsebit.h
+++ b/tools/testing/selftests/kvm/include/sparsebit.h
@@ -6,7 +6,7 @@
  *
  * Header file that describes API to the sparsebit library.
  * This library provides a memory efficient means of storing
- * the settings of bits indexed via a uint64_t.  Memory usage
+ * the settings of bits indexed via a u64.  Memory usage
  * is reasonable, significantly less than (2^64 / 8) bytes, as
  * long as bits that are mostly set or mostly cleared are close
  * to each other.  This library is efficient in memory usage
@@ -25,8 +25,8 @@ extern "C" {
 #endif
 
 struct sparsebit;
-typedef uint64_t sparsebit_idx_t;
-typedef uint64_t sparsebit_num_t;
+typedef u64 sparsebit_idx_t;
+typedef u64 sparsebit_num_t;
 
 struct sparsebit *sparsebit_alloc(void);
 void sparsebit_free(struct sparsebit **sbitp);
diff --git a/tools/testing/selftests/kvm/include/test_util.h b/tools/testing/selftests/kvm/include/test_util.h
index b4872ba8ed12..d9b433b834f1 100644
--- a/tools/testing/selftests/kvm/include/test_util.h
+++ b/tools/testing/selftests/kvm/include/test_util.h
@@ -22,6 +22,8 @@
 #include <sys/mman.h>
 #include "kselftest.h"
 
+#include <linux/types.h>
+
 #define msecs_to_usecs(msec)    ((msec) * 1000ULL)
 
 static inline __printf(1, 2) int _no_printf(const char *format, ...) { return 0; }
@@ -99,25 +101,25 @@ do {										\
 
 size_t parse_size(const char *size);
 
-int64_t timespec_to_ns(struct timespec ts);
-struct timespec timespec_add_ns(struct timespec ts, int64_t ns);
+s64 timespec_to_ns(struct timespec ts);
+struct timespec timespec_add_ns(struct timespec ts, s64 ns);
 struct timespec timespec_add(struct timespec ts1, struct timespec ts2);
 struct timespec timespec_sub(struct timespec ts1, struct timespec ts2);
 struct timespec timespec_elapsed(struct timespec start);
 struct timespec timespec_div(struct timespec ts, int divisor);
 
 struct guest_random_state {
-	uint32_t seed;
+	u32 seed;
 };
 
-extern uint32_t guest_random_seed;
+extern u32 guest_random_seed;
 extern struct guest_random_state guest_rng;
 
-struct guest_random_state new_guest_random_state(uint32_t seed);
-uint32_t guest_random_u32(struct guest_random_state *state);
+struct guest_random_state new_guest_random_state(u32 seed);
+u32 guest_random_u32(struct guest_random_state *state);
 
 static inline bool __guest_random_bool(struct guest_random_state *state,
-				       uint8_t percent)
+				       u8 percent)
 {
 	return (guest_random_u32(state) % 100) < percent;
 }
@@ -127,9 +129,9 @@ static inline bool guest_random_bool(struct guest_random_state *state)
 	return __guest_random_bool(state, 50);
 }
 
-static inline uint64_t guest_random_u64(struct guest_random_state *state)
+static inline u64 guest_random_u64(struct guest_random_state *state)
 {
-	return ((uint64_t)guest_random_u32(state) << 32) | guest_random_u32(state);
+	return ((u64)guest_random_u32(state) << 32) | guest_random_u32(state);
 }
 
 enum vm_mem_backing_src_type {
@@ -158,7 +160,7 @@ enum vm_mem_backing_src_type {
 
 struct vm_mem_backing_src_alias {
 	const char *name;
-	uint32_t flag;
+	u32 flag;
 };
 
 #define MIN_RUN_DELAY_NS	200000UL
@@ -166,9 +168,9 @@ struct vm_mem_backing_src_alias {
 bool thp_configured(void);
 size_t get_trans_hugepagesz(void);
 size_t get_def_hugetlb_pagesz(void);
-const struct vm_mem_backing_src_alias *vm_mem_backing_src_alias(uint32_t i);
-size_t get_backing_src_pagesz(uint32_t i);
-bool is_backing_src_hugetlb(uint32_t i);
+const struct vm_mem_backing_src_alias *vm_mem_backing_src_alias(u32 i);
+size_t get_backing_src_pagesz(u32 i);
+bool is_backing_src_hugetlb(u32 i);
 void backing_src_help(const char *flag);
 enum vm_mem_backing_src_type parse_backing_src_type(const char *type_name);
 long get_run_delay(void);
@@ -189,18 +191,18 @@ static inline bool backing_src_can_be_huge(enum vm_mem_backing_src_type t)
 }
 
 /* Aligns x up to the next multiple of size. Size must be a power of 2. */
-static inline uint64_t align_up(uint64_t x, uint64_t size)
+static inline u64 align_up(u64 x, u64 size)
 {
-	uint64_t mask = size - 1;
+	u64 mask = size - 1;
 
 	TEST_ASSERT(size != 0 && !(size & (size - 1)),
 		    "size not a power of 2: %lu", size);
 	return ((x + mask) & ~mask);
 }
 
-static inline uint64_t align_down(uint64_t x, uint64_t size)
+static inline u64 align_down(u64 x, u64 size)
 {
-	uint64_t x_aligned_up = align_up(x, size);
+	u64 x_aligned_up = align_up(x, size);
 
 	if (x == x_aligned_up)
 		return x;
@@ -215,7 +217,7 @@ static inline void *align_ptr_up(void *x, size_t size)
 
 int atoi_paranoid(const char *num_str);
 
-static inline uint32_t atoi_positive(const char *name, const char *num_str)
+static inline u32 atoi_positive(const char *name, const char *num_str)
 {
 	int num = atoi_paranoid(num_str);
 
@@ -223,7 +225,7 @@ static inline uint32_t atoi_positive(const char *name, const char *num_str)
 	return num;
 }
 
-static inline uint32_t atoi_non_negative(const char *name, const char *num_str)
+static inline u32 atoi_non_negative(const char *name, const char *num_str)
 {
 	int num = atoi_paranoid(num_str);
 
diff --git a/tools/testing/selftests/kvm/include/timer_test.h b/tools/testing/selftests/kvm/include/timer_test.h
index 9b6edaafe6d4..b7d5d2c84701 100644
--- a/tools/testing/selftests/kvm/include/timer_test.h
+++ b/tools/testing/selftests/kvm/include/timer_test.h
@@ -18,21 +18,21 @@
 
 /* Timer test cmdline parameters */
 struct test_args {
-	uint32_t nr_vcpus;
-	uint32_t nr_iter;
-	uint32_t timer_period_ms;
-	uint32_t migration_freq_ms;
-	uint32_t timer_err_margin_us;
+	u32 nr_vcpus;
+	u32 nr_iter;
+	u32 timer_period_ms;
+	u32 migration_freq_ms;
+	u32 timer_err_margin_us;
 	/* Members of struct kvm_arm_counter_offset */
-	uint64_t counter_offset;
-	uint64_t reserved;
+	u64 counter_offset;
+	u64 reserved;
 };
 
 /* Shared variables between host and guest */
 struct test_vcpu_shared_data {
-	uint32_t nr_iter;
+	u32 nr_iter;
 	int guest_stage;
-	uint64_t xcnt;
+	u64 xcnt;
 };
 
 extern struct test_args test_args;
diff --git a/tools/testing/selftests/kvm/include/ucall_common.h b/tools/testing/selftests/kvm/include/ucall_common.h
index d9d6581b8d4f..cbdcb0a50c4f 100644
--- a/tools/testing/selftests/kvm/include/ucall_common.h
+++ b/tools/testing/selftests/kvm/include/ucall_common.h
@@ -21,26 +21,26 @@ enum {
 #define UCALL_BUFFER_LEN 1024
 
 struct ucall {
-	uint64_t cmd;
-	uint64_t args[UCALL_MAX_ARGS];
+	u64 cmd;
+	u64 args[UCALL_MAX_ARGS];
 	char buffer[UCALL_BUFFER_LEN];
 
 	/* Host virtual address of this struct. */
 	struct ucall *hva;
 };
 
-void ucall_arch_init(struct kvm_vm *vm, vm_paddr_t mmio_gpa);
-void ucall_arch_do_ucall(vm_vaddr_t uc);
+void ucall_arch_init(struct kvm_vm *vm, gpa_t mmio_gpa);
+void ucall_arch_do_ucall(gva_t uc);
 void *ucall_arch_get_ucall(struct kvm_vcpu *vcpu);
 
-void ucall(uint64_t cmd, int nargs, ...);
-__printf(2, 3) void ucall_fmt(uint64_t cmd, const char *fmt, ...);
-__printf(5, 6) void ucall_assert(uint64_t cmd, const char *exp,
+void ucall(u64 cmd, int nargs, ...);
+__printf(2, 3) void ucall_fmt(u64 cmd, const char *fmt, ...);
+__printf(5, 6) void ucall_assert(u64 cmd, const char *exp,
 				 const char *file, unsigned int line,
 				 const char *fmt, ...);
-uint64_t get_ucall(struct kvm_vcpu *vcpu, struct ucall *uc);
-void ucall_init(struct kvm_vm *vm, vm_paddr_t mmio_gpa);
-int ucall_nr_pages_required(uint64_t page_size);
+u64 get_ucall(struct kvm_vcpu *vcpu, struct ucall *uc);
+void ucall_init(struct kvm_vm *vm, gpa_t mmio_gpa);
+int ucall_nr_pages_required(u64 page_size);
 
 /*
  * Perform userspace call without any associated data.  This bare call avoids
@@ -48,7 +48,7 @@ int ucall_nr_pages_required(uint64_t page_size);
  * the full ucall() are problematic and/or unwanted.  Note, this will come out
  * as UCALL_NONE on the backend.
  */
-#define GUEST_UCALL_NONE()	ucall_arch_do_ucall((vm_vaddr_t)NULL)
+#define GUEST_UCALL_NONE()	ucall_arch_do_ucall((gva_t)NULL)
 
 #define GUEST_SYNC_ARGS(stage, arg1, arg2, arg3, arg4)	\
 				ucall(UCALL_SYNC, 6, "hello", stage, arg1, arg2, arg3, arg4)
diff --git a/tools/testing/selftests/kvm/include/userfaultfd_util.h b/tools/testing/selftests/kvm/include/userfaultfd_util.h
index 60f7f9d435dc..0bc1dc16600e 100644
--- a/tools/testing/selftests/kvm/include/userfaultfd_util.h
+++ b/tools/testing/selftests/kvm/include/userfaultfd_util.h
@@ -25,7 +25,7 @@ struct uffd_reader_args {
 
 struct uffd_desc {
 	int uffd;
-	uint64_t num_readers;
+	u64 num_readers;
 	/* Holds the write ends of the pipes for killing the readers. */
 	int *pipefds;
 	pthread_t *readers;
@@ -33,8 +33,8 @@ struct uffd_desc {
 };
 
 struct uffd_desc *uffd_setup_demand_paging(int uffd_mode, useconds_t delay,
-					   void *hva, uint64_t len,
-					   uint64_t num_readers,
+					   void *hva, u64 len,
+					   u64 num_readers,
 					   uffd_handler_t handler);
 
 void uffd_stop_demand_paging(struct uffd_desc *uffd);
diff --git a/tools/testing/selftests/kvm/include/x86/apic.h b/tools/testing/selftests/kvm/include/x86/apic.h
index 5ca6bacbd70e..31887bdc3d6c 100644
--- a/tools/testing/selftests/kvm/include/x86/apic.h
+++ b/tools/testing/selftests/kvm/include/x86/apic.h
@@ -79,42 +79,42 @@ void apic_disable(void);
 void xapic_enable(void);
 void x2apic_enable(void);
 
-static inline uint32_t get_bsp_flag(void)
+static inline u32 get_bsp_flag(void)
 {
 	return rdmsr(MSR_IA32_APICBASE) & MSR_IA32_APICBASE_BSP;
 }
 
-static inline uint32_t xapic_read_reg(unsigned int reg)
+static inline u32 xapic_read_reg(unsigned int reg)
 {
-	return ((volatile uint32_t *)APIC_DEFAULT_GPA)[reg >> 2];
+	return ((volatile u32 *)APIC_DEFAULT_GPA)[reg >> 2];
 }
 
-static inline void xapic_write_reg(unsigned int reg, uint32_t val)
+static inline void xapic_write_reg(unsigned int reg, u32 val)
 {
-	((volatile uint32_t *)APIC_DEFAULT_GPA)[reg >> 2] = val;
+	((volatile u32 *)APIC_DEFAULT_GPA)[reg >> 2] = val;
 }
 
-static inline uint64_t x2apic_read_reg(unsigned int reg)
+static inline u64 x2apic_read_reg(unsigned int reg)
 {
 	return rdmsr(APIC_BASE_MSR + (reg >> 4));
 }
 
-static inline uint8_t x2apic_write_reg_safe(unsigned int reg, uint64_t value)
+static inline u8 x2apic_write_reg_safe(unsigned int reg, u64 value)
 {
 	return wrmsr_safe(APIC_BASE_MSR + (reg >> 4), value);
 }
 
-static inline void x2apic_write_reg(unsigned int reg, uint64_t value)
+static inline void x2apic_write_reg(unsigned int reg, u64 value)
 {
-	uint8_t fault = x2apic_write_reg_safe(reg, value);
+	u8 fault = x2apic_write_reg_safe(reg, value);
 
 	__GUEST_ASSERT(!fault, "Unexpected fault 0x%x on WRMSR(%x) = %lx\n",
 		       fault, APIC_BASE_MSR + (reg >> 4), value);
 }
 
-static inline void x2apic_write_reg_fault(unsigned int reg, uint64_t value)
+static inline void x2apic_write_reg_fault(unsigned int reg, u64 value)
 {
-	uint8_t fault = x2apic_write_reg_safe(reg, value);
+	u8 fault = x2apic_write_reg_safe(reg, value);
 
 	__GUEST_ASSERT(fault == GP_VECTOR,
 		       "Wanted #GP on WRMSR(%x) = %lx, got 0x%x\n",
diff --git a/tools/testing/selftests/kvm/include/x86/evmcs.h b/tools/testing/selftests/kvm/include/x86/evmcs.h
index 5a74bb30e2f8..be79bda024bf 100644
--- a/tools/testing/selftests/kvm/include/x86/evmcs.h
+++ b/tools/testing/selftests/kvm/include/x86/evmcs.h
@@ -10,9 +10,9 @@
 #include "hyperv.h"
 #include "vmx.h"
 
-#define u16 uint16_t
-#define u32 uint32_t
-#define u64 uint64_t
+#define u16 u16
+#define u32 u32
+#define u64 u64
 
 #define EVMCS_VERSION 1
 
@@ -245,7 +245,7 @@ static inline void evmcs_enable(void)
 	enable_evmcs = true;
 }
 
-static inline int evmcs_vmptrld(uint64_t vmcs_pa, void *vmcs)
+static inline int evmcs_vmptrld(u64 vmcs_pa, void *vmcs)
 {
 	current_vp_assist->current_nested_vmcs = vmcs_pa;
 	current_vp_assist->enlighten_vmentry = 1;
@@ -265,7 +265,7 @@ static inline bool load_evmcs(struct hyperv_test_pages *hv)
 	return true;
 }
 
-static inline int evmcs_vmptrst(uint64_t *value)
+static inline int evmcs_vmptrst(u64 *value)
 {
 	*value = current_vp_assist->current_nested_vmcs &
 		~HV_X64_MSR_VP_ASSIST_PAGE_ENABLE;
@@ -273,7 +273,7 @@ static inline int evmcs_vmptrst(uint64_t *value)
 	return 0;
 }
 
-static inline int evmcs_vmread(uint64_t encoding, uint64_t *value)
+static inline int evmcs_vmread(u64 encoding, u64 *value)
 {
 	switch (encoding) {
 	case GUEST_RIP:
@@ -672,7 +672,7 @@ static inline int evmcs_vmread(uint64_t encoding, uint64_t *value)
 	return 0;
 }
 
-static inline int evmcs_vmwrite(uint64_t encoding, uint64_t value)
+static inline int evmcs_vmwrite(u64 encoding, u64 value)
 {
 	switch (encoding) {
 	case GUEST_RIP:
@@ -1226,9 +1226,9 @@ static inline int evmcs_vmlaunch(void)
 			     "pop %%rbp;"
 			     : [ret]"=&a"(ret)
 			     : [host_rsp]"r"
-			       ((uint64_t)&current_evmcs->host_rsp),
+			       ((u64)&current_evmcs->host_rsp),
 			       [host_rip]"r"
-			       ((uint64_t)&current_evmcs->host_rip)
+			       ((u64)&current_evmcs->host_rip)
 			     : "memory", "cc", "rbx", "r8", "r9", "r10",
 			       "r11", "r12", "r13", "r14", "r15");
 	return ret;
@@ -1265,9 +1265,9 @@ static inline int evmcs_vmresume(void)
 			     "pop %%rbp;"
 			     : [ret]"=&a"(ret)
 			     : [host_rsp]"r"
-			       ((uint64_t)&current_evmcs->host_rsp),
+			       ((u64)&current_evmcs->host_rsp),
 			       [host_rip]"r"
-			       ((uint64_t)&current_evmcs->host_rip)
+			       ((u64)&current_evmcs->host_rip)
 			     : "memory", "cc", "rbx", "r8", "r9", "r10",
 			       "r11", "r12", "r13", "r14", "r15");
 	return ret;
diff --git a/tools/testing/selftests/kvm/include/x86/hyperv.h b/tools/testing/selftests/kvm/include/x86/hyperv.h
index f13e532be240..78003f5a22f3 100644
--- a/tools/testing/selftests/kvm/include/x86/hyperv.h
+++ b/tools/testing/selftests/kvm/include/x86/hyperv.h
@@ -254,12 +254,12 @@
  * Issue a Hyper-V hypercall. Returns exception vector raised or 0, 'hv_status'
  * is set to the hypercall status (if no exception occurred).
  */
-static inline uint8_t __hyperv_hypercall(u64 control, vm_vaddr_t input_address,
-					 vm_vaddr_t output_address,
-					 uint64_t *hv_status)
+static inline u8 __hyperv_hypercall(u64 control, gva_t input_address,
+				    gva_t output_address,
+				    u64 *hv_status)
 {
-	uint64_t error_code;
-	uint8_t vector;
+	u64 error_code;
+	u8 vector;
 
 	/* Note both the hypercall and the "asm safe" clobber r9-r11. */
 	asm volatile("mov %[output_address], %%r8\n\t"
@@ -274,11 +274,11 @@ static inline uint8_t __hyperv_hypercall(u64 control, vm_vaddr_t input_address,
 }
 
 /* Issue a Hyper-V hypercall and assert that it succeeded. */
-static inline void hyperv_hypercall(u64 control, vm_vaddr_t input_address,
-				    vm_vaddr_t output_address)
+static inline void hyperv_hypercall(u64 control, gva_t input_address,
+				    gva_t output_address)
 {
-	uint64_t hv_status;
-	uint8_t vector;
+	u64 hv_status;
+	u8 vector;
 
 	vector = __hyperv_hypercall(control, input_address, output_address, &hv_status);
 
@@ -327,27 +327,27 @@ struct hv_vp_assist_page {
 
 extern struct hv_vp_assist_page *current_vp_assist;
 
-int enable_vp_assist(uint64_t vp_assist_pa, void *vp_assist);
+int enable_vp_assist(u64 vp_assist_pa, void *vp_assist);
 
 struct hyperv_test_pages {
 	/* VP assist page */
 	void *vp_assist_hva;
-	uint64_t vp_assist_gpa;
+	u64 vp_assist_gpa;
 	void *vp_assist;
 
 	/* Partition assist page */
 	void *partition_assist_hva;
-	uint64_t partition_assist_gpa;
+	u64 partition_assist_gpa;
 	void *partition_assist;
 
 	/* Enlightened VMCS */
 	void *enlightened_vmcs_hva;
-	uint64_t enlightened_vmcs_gpa;
+	u64 enlightened_vmcs_gpa;
 	void *enlightened_vmcs;
 };
 
 struct hyperv_test_pages *vcpu_alloc_hyperv_test_pages(struct kvm_vm *vm,
-						       vm_vaddr_t *p_hv_pages_gva);
+						       gva_t *p_hv_pages_gva);
 
 /* HV_X64_MSR_TSC_INVARIANT_CONTROL bits */
 #define HV_INVARIANT_TSC_EXPOSED               BIT_ULL(0)
diff --git a/tools/testing/selftests/kvm/include/x86/kvm_util_arch.h b/tools/testing/selftests/kvm/include/x86/kvm_util_arch.h
index be35d26bb320..c33ab6e04171 100644
--- a/tools/testing/selftests/kvm/include/x86/kvm_util_arch.h
+++ b/tools/testing/selftests/kvm/include/x86/kvm_util_arch.h
@@ -11,19 +11,19 @@
 extern bool is_forced_emulation_enabled;
 
 struct pte_masks {
-	uint64_t present;
-	uint64_t writable;
-	uint64_t user;
-	uint64_t readable;
-	uint64_t executable;
-	uint64_t accessed;
-	uint64_t dirty;
-	uint64_t huge;
-	uint64_t nx;
-	uint64_t c;
-	uint64_t s;
+	u64 present;
+	u64 writable;
+	u64 user;
+	u64 readable;
+	u64 executable;
+	u64 accessed;
+	u64 dirty;
+	u64 huge;
+	u64 nx;
+	u64 c;
+	u64 s;
 
-	uint64_t always_set;
+	u64 always_set;
 };
 
 struct kvm_mmu_arch {
@@ -33,12 +33,12 @@ struct kvm_mmu_arch {
 struct kvm_mmu;
 
 struct kvm_vm_arch {
-	vm_vaddr_t gdt;
-	vm_vaddr_t tss;
-	vm_vaddr_t idt;
+	gva_t gdt;
+	gva_t tss;
+	gva_t idt;
 
-	uint64_t c_bit;
-	uint64_t s_bit;
+	u64 c_bit;
+	u64 s_bit;
 	int sev_fd;
 	bool is_pt_protected;
 };
@@ -62,7 +62,7 @@ do {											\
 				     : "+m" (mem)					\
 				     : "r" (val) : "memory");				\
 	} else {									\
-		uint64_t __old = READ_ONCE(mem);					\
+		u64 __old = READ_ONCE(mem);					\
 											\
 		__asm__ __volatile__(KVM_FEP LOCK_PREFIX "cmpxchg %[new], %[ptr]"	\
 				     : [ptr] "+m" (mem), [old] "+a" (__old)		\
diff --git a/tools/testing/selftests/kvm/include/x86/pmu.h b/tools/testing/selftests/kvm/include/x86/pmu.h
index 72575eadb63a..98537cc8840d 100644
--- a/tools/testing/selftests/kvm/include/x86/pmu.h
+++ b/tools/testing/selftests/kvm/include/x86/pmu.h
@@ -6,8 +6,8 @@
 #define SELFTEST_KVM_PMU_H
 
 #include <stdbool.h>
-#include <stdint.h>
 
+#include <linux/types.h>
 #include <linux/bits.h>
 
 #define KVM_PMU_EVENT_FILTER_MAX_EVENTS			300
@@ -104,14 +104,15 @@ enum amd_pmu_zen_events {
 	NR_AMD_ZEN_EVENTS,
 };
 
-extern const uint64_t intel_pmu_arch_events[];
-extern const uint64_t amd_pmu_zen_events[];
+extern const u64 intel_pmu_arch_events[];
+extern const u64 amd_pmu_zen_events[];
 
 enum pmu_errata {
 	INSTRUCTIONS_RETIRED_OVERCOUNT,
 	BRANCHES_RETIRED_OVERCOUNT,
 };
-extern uint64_t pmu_errata_mask;
+
+extern u64 pmu_errata_mask;
 
 void kvm_init_pmu_errata(void);
 
diff --git a/tools/testing/selftests/kvm/include/x86/processor.h b/tools/testing/selftests/kvm/include/x86/processor.h
index d8634a760a60..77f576ee7789 100644
--- a/tools/testing/selftests/kvm/include/x86/processor.h
+++ b/tools/testing/selftests/kvm/include/x86/processor.h
@@ -23,7 +23,7 @@ extern bool host_cpu_is_intel;
 extern bool host_cpu_is_amd;
 extern bool host_cpu_is_hygon;
 extern bool host_cpu_is_amd_compatible;
-extern uint64_t guest_tsc_khz;
+extern u64 guest_tsc_khz;
 
 #ifndef MAX_NR_CPUID_ENTRIES
 #define MAX_NR_CPUID_ENTRIES 100
@@ -399,17 +399,17 @@ struct gpr64_regs {
 };
 
 struct desc64 {
-	uint16_t limit0;
-	uint16_t base0;
+	u16 limit0;
+	u16 base0;
 	unsigned base1:8, type:4, s:1, dpl:2, p:1;
 	unsigned limit1:4, avl:1, l:1, db:1, g:1, base2:8;
-	uint32_t base3;
-	uint32_t zero1;
+	u32 base3;
+	u32 zero1;
 } __attribute__((packed));
 
 struct desc_ptr {
-	uint16_t size;
-	uint64_t address;
+	u16 size;
+	u64 address;
 } __attribute__((packed));
 
 struct kvm_x86_state {
@@ -427,18 +427,18 @@ struct kvm_x86_state {
 	struct kvm_msrs msrs;
 };
 
-static inline uint64_t get_desc64_base(const struct desc64 *desc)
+static inline u64 get_desc64_base(const struct desc64 *desc)
 {
-	return (uint64_t)desc->base3 << 32 |
-	       (uint64_t)desc->base2 << 24 |
-	       (uint64_t)desc->base1 << 16 |
-	       (uint64_t)desc->base0;
+	return (u64)desc->base3 << 32 |
+	       (u64)desc->base2 << 24 |
+	       (u64)desc->base1 << 16 |
+	       (u64)desc->base0;
 }
 
-static inline uint64_t rdtsc(void)
+static inline u64 rdtsc(void)
 {
-	uint32_t eax, edx;
-	uint64_t tsc_val;
+	u32 eax, edx;
+	u64 tsc_val;
 	/*
 	 * The lfence is to wait (on Intel CPUs) until all previous
 	 * instructions have been executed. If software requires RDTSC to be
@@ -446,39 +446,39 @@ static inline uint64_t rdtsc(void)
 	 * execute LFENCE immediately after RDTSC
 	 */
 	__asm__ __volatile__("lfence; rdtsc; lfence" : "=a"(eax), "=d"(edx));
-	tsc_val = ((uint64_t)edx) << 32 | eax;
+	tsc_val = ((u64)edx) << 32 | eax;
 	return tsc_val;
 }
 
-static inline uint64_t rdtscp(uint32_t *aux)
+static inline u64 rdtscp(u32 *aux)
 {
-	uint32_t eax, edx;
+	u32 eax, edx;
 
 	__asm__ __volatile__("rdtscp" : "=a"(eax), "=d"(edx), "=c"(*aux));
-	return ((uint64_t)edx) << 32 | eax;
+	return ((u64)edx) << 32 | eax;
 }
 
-static inline uint64_t rdmsr(uint32_t msr)
+static inline u64 rdmsr(u32 msr)
 {
-	uint32_t a, d;
+	u32 a, d;
 
 	__asm__ __volatile__("rdmsr" : "=a"(a), "=d"(d) : "c"(msr) : "memory");
 
-	return a | ((uint64_t) d << 32);
+	return a | ((u64)d << 32);
 }
 
-static inline void wrmsr(uint32_t msr, uint64_t value)
+static inline void wrmsr(u32 msr, u64 value)
 {
-	uint32_t a = value;
-	uint32_t d = value >> 32;
+	u32 a = value;
+	u32 d = value >> 32;
 
 	__asm__ __volatile__("wrmsr" :: "a"(a), "d"(d), "c"(msr) : "memory");
 }
 
 
-static inline uint16_t inw(uint16_t port)
+static inline u16 inw(u16 port)
 {
-	uint16_t tmp;
+	u16 tmp;
 
 	__asm__ __volatile__("in %%dx, %%ax"
 		: /* output */ "=a" (tmp)
@@ -487,120 +487,120 @@ static inline uint16_t inw(uint16_t port)
 	return tmp;
 }
 
-static inline uint16_t get_es(void)
+static inline u16 get_es(void)
 {
-	uint16_t es;
+	u16 es;
 
 	__asm__ __volatile__("mov %%es, %[es]"
 			     : /* output */ [es]"=rm"(es));
 	return es;
 }
 
-static inline uint16_t get_cs(void)
+static inline u16 get_cs(void)
 {
-	uint16_t cs;
+	u16 cs;
 
 	__asm__ __volatile__("mov %%cs, %[cs]"
 			     : /* output */ [cs]"=rm"(cs));
 	return cs;
 }
 
-static inline uint16_t get_ss(void)
+static inline u16 get_ss(void)
 {
-	uint16_t ss;
+	u16 ss;
 
 	__asm__ __volatile__("mov %%ss, %[ss]"
 			     : /* output */ [ss]"=rm"(ss));
 	return ss;
 }
 
-static inline uint16_t get_ds(void)
+static inline u16 get_ds(void)
 {
-	uint16_t ds;
+	u16 ds;
 
 	__asm__ __volatile__("mov %%ds, %[ds]"
 			     : /* output */ [ds]"=rm"(ds));
 	return ds;
 }
 
-static inline uint16_t get_fs(void)
+static inline u16 get_fs(void)
 {
-	uint16_t fs;
+	u16 fs;
 
 	__asm__ __volatile__("mov %%fs, %[fs]"
 			     : /* output */ [fs]"=rm"(fs));
 	return fs;
 }
 
-static inline uint16_t get_gs(void)
+static inline u16 get_gs(void)
 {
-	uint16_t gs;
+	u16 gs;
 
 	__asm__ __volatile__("mov %%gs, %[gs]"
 			     : /* output */ [gs]"=rm"(gs));
 	return gs;
 }
 
-static inline uint16_t get_tr(void)
+static inline u16 get_tr(void)
 {
-	uint16_t tr;
+	u16 tr;
 
 	__asm__ __volatile__("str %[tr]"
 			     : /* output */ [tr]"=rm"(tr));
 	return tr;
 }
 
-static inline uint64_t get_cr0(void)
+static inline u64 get_cr0(void)
 {
-	uint64_t cr0;
+	u64 cr0;
 
 	__asm__ __volatile__("mov %%cr0, %[cr0]"
 			     : /* output */ [cr0]"=r"(cr0));
 	return cr0;
 }
 
-static inline void set_cr0(uint64_t val)
+static inline void set_cr0(u64 val)
 {
 	__asm__ __volatile__("mov %0, %%cr0" : : "r" (val) : "memory");
 }
 
-static inline uint64_t get_cr3(void)
+static inline u64 get_cr3(void)
 {
-	uint64_t cr3;
+	u64 cr3;
 
 	__asm__ __volatile__("mov %%cr3, %[cr3]"
 			     : /* output */ [cr3]"=r"(cr3));
 	return cr3;
 }
 
-static inline void set_cr3(uint64_t val)
+static inline void set_cr3(u64 val)
 {
 	__asm__ __volatile__("mov %0, %%cr3" : : "r" (val) : "memory");
 }
 
-static inline uint64_t get_cr4(void)
+static inline u64 get_cr4(void)
 {
-	uint64_t cr4;
+	u64 cr4;
 
 	__asm__ __volatile__("mov %%cr4, %[cr4]"
 			     : /* output */ [cr4]"=r"(cr4));
 	return cr4;
 }
 
-static inline void set_cr4(uint64_t val)
+static inline void set_cr4(u64 val)
 {
 	__asm__ __volatile__("mov %0, %%cr4" : : "r" (val) : "memory");
 }
 
-static inline uint64_t get_cr8(void)
+static inline u64 get_cr8(void)
 {
-	uint64_t cr8;
+	u64 cr8;
 
 	__asm__ __volatile__("mov %%cr8, %[cr8]" : [cr8]"=r"(cr8));
 	return cr8;
 }
 
-static inline void set_cr8(uint64_t val)
+static inline void set_cr8(u64 val)
 {
 	__asm__ __volatile__("mov %0, %%cr8" : : "r" (val) : "memory");
 }
@@ -651,14 +651,14 @@ static inline struct desc_ptr get_idt(void)
 	return idt;
 }
 
-static inline void outl(uint16_t port, uint32_t value)
+static inline void outl(u16 port, u32 value)
 {
 	__asm__ __volatile__("outl %%eax, %%dx" : : "d"(port), "a"(value));
 }
 
-static inline void __cpuid(uint32_t function, uint32_t index,
-			   uint32_t *eax, uint32_t *ebx,
-			   uint32_t *ecx, uint32_t *edx)
+static inline void __cpuid(u32 function, u32 index,
+			   u32 *eax, u32 *ebx,
+			   u32 *ecx, u32 *edx)
 {
 	*eax = function;
 	*ecx = index;
@@ -672,35 +672,35 @@ static inline void __cpuid(uint32_t function, uint32_t index,
 	    : "memory");
 }
 
-static inline void cpuid(uint32_t function,
-			 uint32_t *eax, uint32_t *ebx,
-			 uint32_t *ecx, uint32_t *edx)
+static inline void cpuid(u32 function,
+			 u32 *eax, u32 *ebx,
+			 u32 *ecx, u32 *edx)
 {
 	return __cpuid(function, 0, eax, ebx, ecx, edx);
 }
 
-static inline uint32_t this_cpu_fms(void)
+static inline u32 this_cpu_fms(void)
 {
-	uint32_t eax, ebx, ecx, edx;
+	u32 eax, ebx, ecx, edx;
 
 	cpuid(1, &eax, &ebx, &ecx, &edx);
 	return eax;
 }
 
-static inline uint32_t this_cpu_family(void)
+static inline u32 this_cpu_family(void)
 {
 	return x86_family(this_cpu_fms());
 }
 
-static inline uint32_t this_cpu_model(void)
+static inline u32 this_cpu_model(void)
 {
 	return x86_model(this_cpu_fms());
 }
 
 static inline bool this_cpu_vendor_string_is(const char *vendor)
 {
-	const uint32_t *chunk = (const uint32_t *)vendor;
-	uint32_t eax, ebx, ecx, edx;
+	const u32 *chunk = (const u32 *)vendor;
+	u32 eax, ebx, ecx, edx;
 
 	cpuid(0, &eax, &ebx, &ecx, &edx);
 	return (ebx == chunk[0] && edx == chunk[1] && ecx == chunk[2]);
@@ -724,10 +724,9 @@ static inline bool this_cpu_is_hygon(void)
 	return this_cpu_vendor_string_is("HygonGenuine");
 }
 
-static inline uint32_t __this_cpu_has(uint32_t function, uint32_t index,
-				      uint8_t reg, uint8_t lo, uint8_t hi)
+static inline u32 __this_cpu_has(u32 function, u32 index, u8 reg, u8 lo, u8 hi)
 {
-	uint32_t gprs[4];
+	u32 gprs[4];
 
 	__cpuid(function, index,
 		&gprs[KVM_CPUID_EAX], &gprs[KVM_CPUID_EBX],
@@ -742,7 +741,7 @@ static inline bool this_cpu_has(struct kvm_x86_cpu_feature feature)
 			      feature.reg, feature.bit, feature.bit);
 }
 
-static inline uint32_t this_cpu_property(struct kvm_x86_cpu_property property)
+static inline u32 this_cpu_property(struct kvm_x86_cpu_property property)
 {
 	return __this_cpu_has(property.function, property.index,
 			      property.reg, property.lo_bit, property.hi_bit);
@@ -750,7 +749,7 @@ static inline uint32_t this_cpu_property(struct kvm_x86_cpu_property property)
 
 static __always_inline bool this_cpu_has_p(struct kvm_x86_cpu_property property)
 {
-	uint32_t max_leaf;
+	u32 max_leaf;
 
 	switch (property.function & 0xc0000000) {
 	case 0:
@@ -770,7 +769,7 @@ static __always_inline bool this_cpu_has_p(struct kvm_x86_cpu_property property)
 
 static inline bool this_pmu_has(struct kvm_x86_pmu_feature feature)
 {
-	uint32_t nr_bits;
+	u32 nr_bits;
 
 	if (feature.f.reg == KVM_CPUID_EBX) {
 		nr_bits = this_cpu_property(X86_PROPERTY_PMU_EBX_BIT_VECTOR_LENGTH);
@@ -782,13 +781,13 @@ static inline bool this_pmu_has(struct kvm_x86_pmu_feature feature)
 	return nr_bits > feature.f.bit || this_cpu_has(feature.f);
 }
 
-static __always_inline uint64_t this_cpu_supported_xcr0(void)
+static __always_inline u64 this_cpu_supported_xcr0(void)
 {
 	if (!this_cpu_has_p(X86_PROPERTY_SUPPORTED_XCR0_LO))
 		return 0;
 
 	return this_cpu_property(X86_PROPERTY_SUPPORTED_XCR0_LO) |
-	       ((uint64_t)this_cpu_property(X86_PROPERTY_SUPPORTED_XCR0_HI) << 32);
+	       ((u64)this_cpu_property(X86_PROPERTY_SUPPORTED_XCR0_HI) << 32);
 }
 
 typedef u32		__attribute__((vector_size(16))) sse128_t;
@@ -867,7 +866,7 @@ static inline void cpu_relax(void)
 
 static inline void udelay(unsigned long usec)
 {
-	uint64_t start, now, cycles;
+	u64 start, now, cycles;
 
 	GUEST_ASSERT(guest_tsc_khz);
 	cycles = guest_tsc_khz / 1000 * usec;
@@ -898,8 +897,8 @@ void kvm_x86_state_cleanup(struct kvm_x86_state *state);
 
 const struct kvm_msr_list *kvm_get_msr_index_list(void);
 const struct kvm_msr_list *kvm_get_feature_msr_index_list(void);
-bool kvm_msr_is_in_save_restore_list(uint32_t msr_index);
-uint64_t kvm_get_feature_msr(uint64_t msr_index);
+bool kvm_msr_is_in_save_restore_list(u32 msr_index);
+u64 kvm_get_feature_msr(u64 msr_index);
 
 static inline void vcpu_msrs_get(struct kvm_vcpu *vcpu,
 				 struct kvm_msrs *msrs)
@@ -954,20 +953,20 @@ static inline void vcpu_xcrs_set(struct kvm_vcpu *vcpu, struct kvm_xcrs *xcrs)
 }
 
 const struct kvm_cpuid_entry2 *get_cpuid_entry(const struct kvm_cpuid2 *cpuid,
-					       uint32_t function, uint32_t index);
+					       u32 function, u32 index);
 const struct kvm_cpuid2 *kvm_get_supported_cpuid(void);
 
-static inline uint32_t kvm_cpu_fms(void)
+static inline u32 kvm_cpu_fms(void)
 {
 	return get_cpuid_entry(kvm_get_supported_cpuid(), 0x1, 0)->eax;
 }
 
-static inline uint32_t kvm_cpu_family(void)
+static inline u32 kvm_cpu_family(void)
 {
 	return x86_family(kvm_cpu_fms());
 }
 
-static inline uint32_t kvm_cpu_model(void)
+static inline u32 kvm_cpu_model(void)
 {
 	return x86_model(kvm_cpu_fms());
 }
@@ -980,17 +979,17 @@ static inline bool kvm_cpu_has(struct kvm_x86_cpu_feature feature)
 	return kvm_cpuid_has(kvm_get_supported_cpuid(), feature);
 }
 
-uint32_t kvm_cpuid_property(const struct kvm_cpuid2 *cpuid,
-			    struct kvm_x86_cpu_property property);
+u32 kvm_cpuid_property(const struct kvm_cpuid2 *cpuid,
+		       struct kvm_x86_cpu_property property);
 
-static inline uint32_t kvm_cpu_property(struct kvm_x86_cpu_property property)
+static inline u32 kvm_cpu_property(struct kvm_x86_cpu_property property)
 {
 	return kvm_cpuid_property(kvm_get_supported_cpuid(), property);
 }
 
 static __always_inline bool kvm_cpu_has_p(struct kvm_x86_cpu_property property)
 {
-	uint32_t max_leaf;
+	u32 max_leaf;
 
 	switch (property.function & 0xc0000000) {
 	case 0:
@@ -1010,7 +1009,7 @@ static __always_inline bool kvm_cpu_has_p(struct kvm_x86_cpu_property property)
 
 static inline bool kvm_pmu_has(struct kvm_x86_pmu_feature feature)
 {
-	uint32_t nr_bits;
+	u32 nr_bits;
 
 	if (feature.f.reg == KVM_CPUID_EBX) {
 		nr_bits = kvm_cpu_property(X86_PROPERTY_PMU_EBX_BIT_VECTOR_LENGTH);
@@ -1022,13 +1021,13 @@ static inline bool kvm_pmu_has(struct kvm_x86_pmu_feature feature)
 	return nr_bits > feature.f.bit || kvm_cpu_has(feature.f);
 }
 
-static __always_inline uint64_t kvm_cpu_supported_xcr0(void)
+static __always_inline u64 kvm_cpu_supported_xcr0(void)
 {
 	if (!kvm_cpu_has_p(X86_PROPERTY_SUPPORTED_XCR0_LO))
 		return 0;
 
 	return kvm_cpu_property(X86_PROPERTY_SUPPORTED_XCR0_LO) |
-	       ((uint64_t)kvm_cpu_property(X86_PROPERTY_SUPPORTED_XCR0_HI) << 32);
+	       ((u64)kvm_cpu_property(X86_PROPERTY_SUPPORTED_XCR0_HI) << 32);
 }
 
 static inline size_t kvm_cpuid2_size(int nr_entries)
@@ -1062,8 +1061,8 @@ static inline void vcpu_get_cpuid(struct kvm_vcpu *vcpu)
 }
 
 static inline struct kvm_cpuid_entry2 *__vcpu_get_cpuid_entry(struct kvm_vcpu *vcpu,
-							      uint32_t function,
-							      uint32_t index)
+							      u32 function,
+							      u32 index)
 {
 	TEST_ASSERT(vcpu->cpuid, "Must do vcpu_init_cpuid() first (or equivalent)");
 
@@ -1074,7 +1073,7 @@ static inline struct kvm_cpuid_entry2 *__vcpu_get_cpuid_entry(struct kvm_vcpu *v
 }
 
 static inline struct kvm_cpuid_entry2 *vcpu_get_cpuid_entry(struct kvm_vcpu *vcpu,
-							    uint32_t function)
+							    u32 function)
 {
 	return __vcpu_get_cpuid_entry(vcpu, function, 0);
 }
@@ -1104,10 +1103,10 @@ static inline void vcpu_set_cpuid(struct kvm_vcpu *vcpu)
 
 void vcpu_set_cpuid_property(struct kvm_vcpu *vcpu,
 			     struct kvm_x86_cpu_property property,
-			     uint32_t value);
-void vcpu_set_cpuid_maxphyaddr(struct kvm_vcpu *vcpu, uint8_t maxphyaddr);
+			     u32 value);
+void vcpu_set_cpuid_maxphyaddr(struct kvm_vcpu *vcpu, u8 maxphyaddr);
 
-void vcpu_clear_cpuid_entry(struct kvm_vcpu *vcpu, uint32_t function);
+void vcpu_clear_cpuid_entry(struct kvm_vcpu *vcpu, u32 function);
 
 static inline bool vcpu_cpuid_has(struct kvm_vcpu *vcpu,
 				  struct kvm_x86_cpu_feature feature)
@@ -1135,8 +1134,8 @@ static inline void vcpu_clear_cpuid_feature(struct kvm_vcpu *vcpu,
 	vcpu_set_or_clear_cpuid_feature(vcpu, feature, false);
 }
 
-uint64_t vcpu_get_msr(struct kvm_vcpu *vcpu, uint64_t msr_index);
-int _vcpu_set_msr(struct kvm_vcpu *vcpu, uint64_t msr_index, uint64_t msr_value);
+u64 vcpu_get_msr(struct kvm_vcpu *vcpu, u64 msr_index);
+int _vcpu_set_msr(struct kvm_vcpu *vcpu, u64 msr_index, u64 msr_value);
 
 /*
  * Assert on an MSR access(es) and pretty print the MSR name when possible.
@@ -1161,14 +1160,14 @@ do {										\
  * is changing, etc.  This is NOT an exhaustive list!  The intent is to filter
  * out MSRs that are not durable _and_ that a selftest wants to write.
  */
-static inline bool is_durable_msr(uint32_t msr)
+static inline bool is_durable_msr(u32 msr)
 {
 	return msr != MSR_IA32_TSC;
 }
 
 #define vcpu_set_msr(vcpu, msr, val)							\
 do {											\
-	uint64_t r, v = val;								\
+	u64 r, v = val;								\
 											\
 	TEST_ASSERT_MSR(_vcpu_set_msr(vcpu, msr, v) == 1,				\
 			"KVM_SET_MSRS failed on %s, value = 0x%lx", msr, #msr, v);	\
@@ -1182,28 +1181,28 @@ void kvm_get_cpu_address_width(unsigned int *pa_bits, unsigned int *va_bits);
 void kvm_init_vm_address_properties(struct kvm_vm *vm);
 
 struct ex_regs {
-	uint64_t rax, rcx, rdx, rbx;
-	uint64_t rbp, rsi, rdi;
-	uint64_t r8, r9, r10, r11;
-	uint64_t r12, r13, r14, r15;
-	uint64_t vector;
-	uint64_t error_code;
-	uint64_t rip;
-	uint64_t cs;
-	uint64_t rflags;
+	u64 rax, rcx, rdx, rbx;
+	u64 rbp, rsi, rdi;
+	u64 r8, r9, r10, r11;
+	u64 r12, r13, r14, r15;
+	u64 vector;
+	u64 error_code;
+	u64 rip;
+	u64 cs;
+	u64 rflags;
 };
 
 struct idt_entry {
-	uint16_t offset0;
-	uint16_t selector;
-	uint16_t ist : 3;
-	uint16_t : 5;
-	uint16_t type : 4;
-	uint16_t : 1;
-	uint16_t dpl : 2;
-	uint16_t p : 1;
-	uint16_t offset1;
-	uint32_t offset2; uint32_t reserved;
+	u16 offset0;
+	u16 selector;
+	u16 ist : 3;
+	u16 : 5;
+	u16 type : 4;
+	u16 : 1;
+	u16 dpl : 2;
+	u16 p : 1;
+	u16 offset1;
+	u32 offset2; u32 reserved;
 };
 
 void vm_install_exception_handler(struct kvm_vm *vm, int vector,
@@ -1262,8 +1261,8 @@ void vm_install_exception_handler(struct kvm_vm *vm, int vector,
 
 #define kvm_asm_safe(insn, inputs...)					\
 ({									\
-	uint64_t ign_error_code;					\
-	uint8_t vector;							\
+	u64 ign_error_code;						\
+	u8 vector;							\
 									\
 	asm volatile(KVM_ASM_SAFE(insn)					\
 		     : KVM_ASM_SAFE_OUTPUTS(vector, ign_error_code)	\
@@ -1274,7 +1273,7 @@ void vm_install_exception_handler(struct kvm_vm *vm, int vector,
 
 #define kvm_asm_safe_ec(insn, error_code, inputs...)			\
 ({									\
-	uint8_t vector;							\
+	u8 vector;							\
 									\
 	asm volatile(KVM_ASM_SAFE(insn)					\
 		     : KVM_ASM_SAFE_OUTPUTS(vector, error_code)		\
@@ -1285,8 +1284,8 @@ void vm_install_exception_handler(struct kvm_vm *vm, int vector,
 
 #define kvm_asm_safe_fep(insn, inputs...)				\
 ({									\
-	uint64_t ign_error_code;					\
-	uint8_t vector;							\
+	u64 ign_error_code;						\
+	u8 vector;							\
 									\
 	asm volatile(KVM_ASM_SAFE_FEP(insn)				\
 		     : KVM_ASM_SAFE_OUTPUTS(vector, ign_error_code)	\
@@ -1297,7 +1296,7 @@ void vm_install_exception_handler(struct kvm_vm *vm, int vector,
 
 #define kvm_asm_safe_ec_fep(insn, error_code, inputs...)		\
 ({									\
-	uint8_t vector;							\
+	u8 vector;							\
 									\
 	asm volatile(KVM_ASM_SAFE_FEP(insn)				\
 		     : KVM_ASM_SAFE_OUTPUTS(vector, error_code)		\
@@ -1307,11 +1306,11 @@ void vm_install_exception_handler(struct kvm_vm *vm, int vector,
 })
 
 #define BUILD_READ_U64_SAFE_HELPER(insn, _fep, _FEP)			\
-static inline uint8_t insn##_safe ##_fep(uint32_t idx, uint64_t *val)	\
+static inline u8 insn##_safe ##_fep(u32 idx, u64 *val)			\
 {									\
-	uint64_t error_code;						\
-	uint8_t vector;							\
-	uint32_t a, d;							\
+	u64 error_code;							\
+	u8 vector;							\
+	u32 a, d;							\
 									\
 	asm volatile(KVM_ASM_SAFE##_FEP(#insn)				\
 		     : "=a"(a), "=d"(d),				\
@@ -1319,7 +1318,7 @@ static inline uint8_t insn##_safe ##_fep(uint32_t idx, uint64_t *val)	\
 		     : "c"(idx)						\
 		     : KVM_ASM_SAFE_CLOBBERS);				\
 									\
-	*val = (uint64_t)a | ((uint64_t)d << 32);			\
+	*val = (u64)a | ((u64)d << 32);			\
 	return vector;							\
 }
 
@@ -1335,12 +1334,12 @@ BUILD_READ_U64_SAFE_HELPERS(rdmsr)
 BUILD_READ_U64_SAFE_HELPERS(rdpmc)
 BUILD_READ_U64_SAFE_HELPERS(xgetbv)
 
-static inline uint8_t wrmsr_safe(uint32_t msr, uint64_t val)
+static inline u8 wrmsr_safe(u32 msr, u64 val)
 {
 	return kvm_asm_safe("wrmsr", "a"(val & -1u), "d"(val >> 32), "c"(msr));
 }
 
-static inline uint8_t xsetbv_safe(uint32_t index, uint64_t value)
+static inline u8 xsetbv_safe(u32 index, u64 value)
 {
 	u32 eax = value;
 	u32 edx = value >> 32;
@@ -1395,23 +1394,20 @@ static inline bool kvm_is_lbrv_enabled(void)
 	return !!get_kvm_amd_param_integer("lbrv");
 }
 
-uint64_t *vm_get_pte(struct kvm_vm *vm, uint64_t vaddr);
+u64 *vm_get_pte(struct kvm_vm *vm, gva_t gva);
 
-uint64_t kvm_hypercall(uint64_t nr, uint64_t a0, uint64_t a1, uint64_t a2,
-		       uint64_t a3);
-uint64_t __xen_hypercall(uint64_t nr, uint64_t a0, void *a1);
-void xen_hypercall(uint64_t nr, uint64_t a0, void *a1);
+u64 kvm_hypercall(u64 nr, u64 a0, u64 a1, u64 a2, u64 a3);
+u64 __xen_hypercall(u64 nr, u64 a0, void *a1);
+void xen_hypercall(u64 nr, u64 a0, void *a1);
 
-static inline uint64_t __kvm_hypercall_map_gpa_range(uint64_t gpa,
-						     uint64_t size, uint64_t flags)
+static inline u64 __kvm_hypercall_map_gpa_range(gpa_t gpa, u64 size, u64 flags)
 {
 	return kvm_hypercall(KVM_HC_MAP_GPA_RANGE, gpa, size >> PAGE_SHIFT, flags, 0);
 }
 
-static inline void kvm_hypercall_map_gpa_range(uint64_t gpa, uint64_t size,
-					       uint64_t flags)
+static inline void kvm_hypercall_map_gpa_range(gpa_t gpa, u64 size, u64 flags)
 {
-	uint64_t ret = __kvm_hypercall_map_gpa_range(gpa, size, flags);
+	u64 ret = __kvm_hypercall_map_gpa_range(gpa, size, flags);
 
 	GUEST_ASSERT(!ret);
 }
@@ -1456,7 +1452,7 @@ static inline void cli(void)
 	asm volatile ("cli");
 }
 
-void __vm_xsave_require_permission(uint64_t xfeature, const char *name);
+void __vm_xsave_require_permission(u64 xfeature, const char *name);
 
 #define vm_xsave_require_permission(xfeature)	\
 	__vm_xsave_require_permission(xfeature, #xfeature)
@@ -1511,17 +1507,17 @@ enum pg_level {
 void tdp_mmu_init(struct kvm_vm *vm, int pgtable_levels,
 		  struct pte_masks *pte_masks);
 
-void __virt_pg_map(struct kvm_vm *vm, struct kvm_mmu *mmu, uint64_t vaddr,
-		   uint64_t paddr,  int level);
-void virt_map_level(struct kvm_vm *vm, uint64_t vaddr, uint64_t paddr,
-		    uint64_t nr_bytes, int level);
+void __virt_pg_map(struct kvm_vm *vm, struct kvm_mmu *mmu, gva_t gva,
+		   gpa_t gpa,  int level);
+void virt_map_level(struct kvm_vm *vm, gva_t gva, gpa_t gpa,
+		    u64 nr_bytes, int level);
 
 void vm_enable_tdp(struct kvm_vm *vm);
 bool kvm_cpu_has_tdp(void);
-void tdp_map(struct kvm_vm *vm, uint64_t nested_paddr, uint64_t paddr, uint64_t size);
+void tdp_map(struct kvm_vm *vm, gpa_t l2_gpa, gpa_t gpa, u64 size);
 void tdp_identity_map_default_memslots(struct kvm_vm *vm);
-void tdp_identity_map_1g(struct kvm_vm *vm,  uint64_t addr, uint64_t size);
-uint64_t *tdp_get_pte(struct kvm_vm *vm, uint64_t l2_gpa);
+void tdp_identity_map_1g(struct kvm_vm *vm,  u64 addr, u64 size);
+u64 *tdp_get_pte(struct kvm_vm *vm, u64 l2_gpa);
 
 /*
  * Basic CPU control in CR0
diff --git a/tools/testing/selftests/kvm/include/x86/sev.h b/tools/testing/selftests/kvm/include/x86/sev.h
index 008b4169f5e2..1af44c151d60 100644
--- a/tools/testing/selftests/kvm/include/x86/sev.h
+++ b/tools/testing/selftests/kvm/include/x86/sev.h
@@ -46,16 +46,16 @@ static inline bool is_sev_vm(struct kvm_vm *vm)
 	return is_sev_es_vm(vm) || vm->type == KVM_X86_SEV_VM;
 }
 
-void sev_vm_launch(struct kvm_vm *vm, uint32_t policy);
-void sev_vm_launch_measure(struct kvm_vm *vm, uint8_t *measurement);
+void sev_vm_launch(struct kvm_vm *vm, u32 policy);
+void sev_vm_launch_measure(struct kvm_vm *vm, u8 *measurement);
 void sev_vm_launch_finish(struct kvm_vm *vm);
-void snp_vm_launch_start(struct kvm_vm *vm, uint64_t policy);
+void snp_vm_launch_start(struct kvm_vm *vm, u64 policy);
 void snp_vm_launch_update(struct kvm_vm *vm);
 void snp_vm_launch_finish(struct kvm_vm *vm);
 
-struct kvm_vm *vm_sev_create_with_one_vcpu(uint32_t type, void *guest_code,
+struct kvm_vm *vm_sev_create_with_one_vcpu(u32 type, void *guest_code,
 					   struct kvm_vcpu **cpu);
-void vm_sev_launch(struct kvm_vm *vm, uint64_t policy, uint8_t *measurement);
+void vm_sev_launch(struct kvm_vm *vm, u64 policy, u8 *measurement);
 
 kvm_static_assert(SEV_RET_SUCCESS == 0);
 
@@ -85,7 +85,7 @@ static inline u64 snp_default_policy(void)
 		unsigned long raw;					\
 	} sev_cmd = { .c = {						\
 		.id = (cmd),						\
-		.data = (uint64_t)(arg),				\
+		.data = (u64)(arg),				\
 		.sev_fd = (vm)->arch.sev_fd,				\
 	} };								\
 									\
@@ -120,8 +120,8 @@ static inline void sev_register_encrypted_memory(struct kvm_vm *vm,
 	vm_ioctl(vm, KVM_MEMORY_ENCRYPT_REG_REGION, &range);
 }
 
-static inline void sev_launch_update_data(struct kvm_vm *vm, vm_paddr_t gpa,
-					  uint64_t size)
+static inline void sev_launch_update_data(struct kvm_vm *vm, gpa_t gpa,
+					  u64 size)
 {
 	struct kvm_sev_launch_update_data update_data = {
 		.uaddr = (unsigned long)addr_gpa2hva(vm, gpa),
@@ -131,8 +131,8 @@ static inline void sev_launch_update_data(struct kvm_vm *vm, vm_paddr_t gpa,
 	vm_sev_ioctl(vm, KVM_SEV_LAUNCH_UPDATE_DATA, &update_data);
 }
 
-static inline void snp_launch_update_data(struct kvm_vm *vm, vm_paddr_t gpa,
-					  uint64_t hva, uint64_t size, uint8_t type)
+static inline void snp_launch_update_data(struct kvm_vm *vm, gpa_t gpa,
+					  u64 hva, u64 size, u8 type)
 {
 	struct kvm_sev_snp_launch_update update_data = {
 		.uaddr = hva,
diff --git a/tools/testing/selftests/kvm/include/x86/smm.h b/tools/testing/selftests/kvm/include/x86/smm.h
index 19337c34f13e..2d1afa09819b 100644
--- a/tools/testing/selftests/kvm/include/x86/smm.h
+++ b/tools/testing/selftests/kvm/include/x86/smm.h
@@ -8,8 +8,7 @@
 #define SMRAM_MEMSLOT	((1 << 16) | 1)
 #define SMRAM_PAGES	(SMRAM_SIZE / PAGE_SIZE)
 
-void setup_smram(struct kvm_vm *vm, struct kvm_vcpu *vcpu,
-		 uint64_t smram_gpa,
+void setup_smram(struct kvm_vm *vm, struct kvm_vcpu *vcpu, u64 smram_gpa,
 		 const void *smi_handler, size_t handler_size);
 
 void inject_smi(struct kvm_vcpu *vcpu);
diff --git a/tools/testing/selftests/kvm/include/x86/svm_util.h b/tools/testing/selftests/kvm/include/x86/svm_util.h
index 5d7c42534bc4..6c013eb838be 100644
--- a/tools/testing/selftests/kvm/include/x86/svm_util.h
+++ b/tools/testing/selftests/kvm/include/x86/svm_util.h
@@ -16,20 +16,20 @@ struct svm_test_data {
 	/* VMCB */
 	struct vmcb *vmcb; /* gva */
 	void *vmcb_hva;
-	uint64_t vmcb_gpa;
+	u64 vmcb_gpa;
 
 	/* host state-save area */
 	struct vmcb_save_area *save_area; /* gva */
 	void *save_area_hva;
-	uint64_t save_area_gpa;
+	u64 save_area_gpa;
 
 	/* MSR-Bitmap */
 	void *msr; /* gva */
 	void *msr_hva;
-	uint64_t msr_gpa;
+	u64 msr_gpa;
 
 	/* NPT */
-	uint64_t ncr3_gpa;
+	u64 ncr3_gpa;
 };
 
 static inline void vmmcall(void)
@@ -56,9 +56,9 @@ static inline void vmmcall(void)
 		"clgi\n"	\
 		)
 
-struct svm_test_data *vcpu_alloc_svm(struct kvm_vm *vm, vm_vaddr_t *p_svm_gva);
+struct svm_test_data *vcpu_alloc_svm(struct kvm_vm *vm, gva_t *p_svm_gva);
 void generic_svm_setup(struct svm_test_data *svm, void *guest_rip, void *guest_rsp);
-void run_guest(struct vmcb *vmcb, uint64_t vmcb_gpa);
+void run_guest(struct vmcb *vmcb, u64 vmcb_gpa);
 
 static inline bool kvm_cpu_has_npt(void)
 {
diff --git a/tools/testing/selftests/kvm/include/x86/ucall.h b/tools/testing/selftests/kvm/include/x86/ucall.h
index d3825dcc3cd9..0e4950041e3e 100644
--- a/tools/testing/selftests/kvm/include/x86/ucall.h
+++ b/tools/testing/selftests/kvm/include/x86/ucall.h
@@ -6,7 +6,7 @@
 
 #define UCALL_EXIT_REASON       KVM_EXIT_IO
 
-static inline void ucall_arch_init(struct kvm_vm *vm, vm_paddr_t mmio_gpa)
+static inline void ucall_arch_init(struct kvm_vm *vm, gpa_t mmio_gpa)
 {
 }
 
diff --git a/tools/testing/selftests/kvm/include/x86/vmx.h b/tools/testing/selftests/kvm/include/x86/vmx.h
index 92b918700d24..90fffaf91595 100644
--- a/tools/testing/selftests/kvm/include/x86/vmx.h
+++ b/tools/testing/selftests/kvm/include/x86/vmx.h
@@ -285,16 +285,16 @@ enum vmcs_field {
 };
 
 struct vmx_msr_entry {
-	uint32_t index;
-	uint32_t reserved;
-	uint64_t value;
+	u32 index;
+	u32 reserved;
+	u64 value;
 } __attribute__ ((aligned(16)));
 
 #include "evmcs.h"
 
-static inline int vmxon(uint64_t phys)
+static inline int vmxon(u64 phys)
 {
-	uint8_t ret;
+	u8 ret;
 
 	__asm__ __volatile__ ("vmxon %[pa]; setna %[ret]"
 		: [ret]"=rm"(ret)
@@ -309,9 +309,9 @@ static inline void vmxoff(void)
 	__asm__ __volatile__("vmxoff");
 }
 
-static inline int vmclear(uint64_t vmcs_pa)
+static inline int vmclear(u64 vmcs_pa)
 {
-	uint8_t ret;
+	u8 ret;
 
 	__asm__ __volatile__ ("vmclear %[pa]; setna %[ret]"
 		: [ret]"=rm"(ret)
@@ -321,9 +321,9 @@ static inline int vmclear(uint64_t vmcs_pa)
 	return ret;
 }
 
-static inline int vmptrld(uint64_t vmcs_pa)
+static inline int vmptrld(u64 vmcs_pa)
 {
-	uint8_t ret;
+	u8 ret;
 
 	if (enable_evmcs)
 		return -1;
@@ -336,10 +336,10 @@ static inline int vmptrld(uint64_t vmcs_pa)
 	return ret;
 }
 
-static inline int vmptrst(uint64_t *value)
+static inline int vmptrst(u64 *value)
 {
-	uint64_t tmp;
-	uint8_t ret;
+	u64 tmp;
+	u8 ret;
 
 	if (enable_evmcs)
 		return evmcs_vmptrst(value);
@@ -356,9 +356,9 @@ static inline int vmptrst(uint64_t *value)
  * A wrapper around vmptrst that ignores errors and returns zero if the
  * vmptrst instruction fails.
  */
-static inline uint64_t vmptrstz(void)
+static inline u64 vmptrstz(void)
 {
-	uint64_t value = 0;
+	u64 value = 0;
 	vmptrst(&value);
 	return value;
 }
@@ -391,8 +391,8 @@ static inline int vmlaunch(void)
 			     "pop %%rcx;"
 			     "pop %%rbp;"
 			     : [ret]"=&a"(ret)
-			     : [host_rsp]"r"((uint64_t)HOST_RSP),
-			       [host_rip]"r"((uint64_t)HOST_RIP)
+			     : [host_rsp]"r"((u64)HOST_RSP),
+			       [host_rip]"r"((u64)HOST_RIP)
 			     : "memory", "cc", "rbx", "r8", "r9", "r10",
 			       "r11", "r12", "r13", "r14", "r15");
 	return ret;
@@ -426,8 +426,8 @@ static inline int vmresume(void)
 			     "pop %%rcx;"
 			     "pop %%rbp;"
 			     : [ret]"=&a"(ret)
-			     : [host_rsp]"r"((uint64_t)HOST_RSP),
-			       [host_rip]"r"((uint64_t)HOST_RIP)
+			     : [host_rsp]"r"((u64)HOST_RSP),
+			       [host_rip]"r"((u64)HOST_RIP)
 			     : "memory", "cc", "rbx", "r8", "r9", "r10",
 			       "r11", "r12", "r13", "r14", "r15");
 	return ret;
@@ -447,10 +447,10 @@ static inline void vmcall(void)
 			       "r10", "r11", "r12", "r13", "r14", "r15");
 }
 
-static inline int vmread(uint64_t encoding, uint64_t *value)
+static inline int vmread(u64 encoding, u64 *value)
 {
-	uint64_t tmp;
-	uint8_t ret;
+	u64 tmp;
+	u8 ret;
 
 	if (enable_evmcs)
 		return evmcs_vmread(encoding, value);
@@ -468,16 +468,16 @@ static inline int vmread(uint64_t encoding, uint64_t *value)
  * A wrapper around vmread that ignores errors and returns zero if the
  * vmread instruction fails.
  */
-static inline uint64_t vmreadz(uint64_t encoding)
+static inline u64 vmreadz(u64 encoding)
 {
-	uint64_t value = 0;
+	u64 value = 0;
 	vmread(encoding, &value);
 	return value;
 }
 
-static inline int vmwrite(uint64_t encoding, uint64_t value)
+static inline int vmwrite(u64 encoding, u64 value)
 {
-	uint8_t ret;
+	u8 ret;
 
 	if (enable_evmcs)
 		return evmcs_vmwrite(encoding, value);
@@ -490,41 +490,41 @@ static inline int vmwrite(uint64_t encoding, uint64_t value)
 	return ret;
 }
 
-static inline uint32_t vmcs_revision(void)
+static inline u32 vmcs_revision(void)
 {
 	return rdmsr(MSR_IA32_VMX_BASIC);
 }
 
 struct vmx_pages {
 	void *vmxon_hva;
-	uint64_t vmxon_gpa;
+	u64 vmxon_gpa;
 	void *vmxon;
 
 	void *vmcs_hva;
-	uint64_t vmcs_gpa;
+	u64 vmcs_gpa;
 	void *vmcs;
 
 	void *msr_hva;
-	uint64_t msr_gpa;
+	u64 msr_gpa;
 	void *msr;
 
 	void *shadow_vmcs_hva;
-	uint64_t shadow_vmcs_gpa;
+	u64 shadow_vmcs_gpa;
 	void *shadow_vmcs;
 
 	void *vmread_hva;
-	uint64_t vmread_gpa;
+	u64 vmread_gpa;
 	void *vmread;
 
 	void *vmwrite_hva;
-	uint64_t vmwrite_gpa;
+	u64 vmwrite_gpa;
 	void *vmwrite;
 
 	void *apic_access_hva;
-	uint64_t apic_access_gpa;
+	u64 apic_access_gpa;
 	void *apic_access;
 
-	uint64_t eptp_gpa;
+	u64 eptp_gpa;
 };
 
 union vmx_basic {
@@ -550,7 +550,7 @@ union vmx_ctrl_msr {
 	};
 };
 
-struct vmx_pages *vcpu_alloc_vmx(struct kvm_vm *vm, vm_vaddr_t *p_vmx_gva);
+struct vmx_pages *vcpu_alloc_vmx(struct kvm_vm *vm, gva_t *p_vmx_gva);
 bool prepare_for_vmx_operation(struct vmx_pages *vmx);
 void prepare_vmcs(struct vmx_pages *vmx, void *guest_rip, void *guest_rsp);
 bool load_vmcs(struct vmx_pages *vmx);
diff --git a/tools/testing/selftests/kvm/kvm_page_table_test.c b/tools/testing/selftests/kvm/kvm_page_table_test.c
index c60a24a92829..fc5242fb956f 100644
--- a/tools/testing/selftests/kvm/kvm_page_table_test.c
+++ b/tools/testing/selftests/kvm/kvm_page_table_test.c
@@ -46,12 +46,12 @@ static const char * const test_stage_string[] = {
 
 struct test_args {
 	struct kvm_vm *vm;
-	uint64_t guest_test_virt_mem;
-	uint64_t host_page_size;
-	uint64_t host_num_pages;
-	uint64_t large_page_size;
-	uint64_t large_num_pages;
-	uint64_t host_pages_per_lpage;
+	u64 guest_test_virt_mem;
+	u64 host_page_size;
+	u64 host_num_pages;
+	u64 large_page_size;
+	u64 large_num_pages;
+	u64 host_pages_per_lpage;
 	enum vm_mem_backing_src_type src_type;
 	struct kvm_vcpu *vcpus[KVM_MAX_VCPUS];
 };
@@ -63,7 +63,7 @@ struct test_args {
 static enum test_stage guest_test_stage;
 
 /* Host variables */
-static uint32_t nr_vcpus = 1;
+static u32 nr_vcpus = 1;
 static struct test_args test_args;
 static enum test_stage *current_stage;
 static bool host_quit;
@@ -77,19 +77,19 @@ static sem_t test_stage_completed;
  * This will be set to the topmost valid physical address minus
  * the test memory size.
  */
-static uint64_t guest_test_phys_mem;
+static u64 guest_test_phys_mem;
 
 /*
  * Guest virtual memory offset of the testing memory slot.
  * Must not conflict with identity mapped test code.
  */
-static uint64_t guest_test_virt_mem = DEFAULT_GUEST_TEST_MEM;
+static u64 guest_test_virt_mem = DEFAULT_GUEST_TEST_MEM;
 
 static void guest_code(bool do_write)
 {
 	struct test_args *p = &test_args;
 	enum test_stage *current_stage = &guest_test_stage;
-	uint64_t addr;
+	u64 addr;
 	int i, j;
 
 	while (true) {
@@ -113,9 +113,9 @@ static void guest_code(bool do_write)
 		case KVM_CREATE_MAPPINGS:
 			for (i = 0; i < p->large_num_pages; i++) {
 				if (do_write)
-					*(uint64_t *)addr = 0x0123456789ABCDEF;
+					*(u64 *)addr = 0x0123456789ABCDEF;
 				else
-					READ_ONCE(*(uint64_t *)addr);
+					READ_ONCE(*(u64 *)addr);
 
 				addr += p->large_page_size;
 			}
@@ -131,7 +131,7 @@ static void guest_code(bool do_write)
 		case KVM_UPDATE_MAPPINGS:
 			if (p->src_type == VM_MEM_SRC_ANONYMOUS) {
 				for (i = 0; i < p->host_num_pages; i++) {
-					*(uint64_t *)addr = 0x0123456789ABCDEF;
+					*(u64 *)addr = 0x0123456789ABCDEF;
 					addr += p->host_page_size;
 				}
 				break;
@@ -142,7 +142,7 @@ static void guest_code(bool do_write)
 				 * Write to the first host page in each large
 				 * page region, and triger break of large pages.
 				 */
-				*(uint64_t *)addr = 0x0123456789ABCDEF;
+				*(u64 *)addr = 0x0123456789ABCDEF;
 
 				/*
 				 * Access the middle host pages in each large
@@ -152,7 +152,7 @@ static void guest_code(bool do_write)
 				 */
 				addr += p->large_page_size / 2;
 				for (j = 0; j < p->host_pages_per_lpage / 2; j++) {
-					READ_ONCE(*(uint64_t *)addr);
+					READ_ONCE(*(u64 *)addr);
 					addr += p->host_page_size;
 				}
 			}
@@ -167,7 +167,7 @@ static void guest_code(bool do_write)
 		 */
 		case KVM_ADJUST_MAPPINGS:
 			for (i = 0; i < p->host_num_pages; i++) {
-				READ_ONCE(*(uint64_t *)addr);
+				READ_ONCE(*(u64 *)addr);
 				addr += p->host_page_size;
 			}
 			break;
@@ -227,8 +227,8 @@ static void *vcpu_worker(void *data)
 }
 
 struct test_params {
-	uint64_t phys_offset;
-	uint64_t test_mem_size;
+	u64 phys_offset;
+	u64 test_mem_size;
 	enum vm_mem_backing_src_type src_type;
 };
 
@@ -237,12 +237,12 @@ static struct kvm_vm *pre_init_before_test(enum vm_guest_mode mode, void *arg)
 	int ret;
 	struct test_params *p = arg;
 	enum vm_mem_backing_src_type src_type = p->src_type;
-	uint64_t large_page_size = get_backing_src_pagesz(src_type);
-	uint64_t guest_page_size = vm_guest_mode_params[mode].page_size;
-	uint64_t host_page_size = getpagesize();
-	uint64_t test_mem_size = p->test_mem_size;
-	uint64_t guest_num_pages;
-	uint64_t alignment;
+	u64 large_page_size = get_backing_src_pagesz(src_type);
+	u64 guest_page_size = vm_guest_mode_params[mode].page_size;
+	u64 host_page_size = getpagesize();
+	u64 test_mem_size = p->test_mem_size;
+	u64 guest_num_pages;
+	u64 alignment;
 	void *host_test_mem;
 	struct kvm_vm *vm;
 
@@ -281,7 +281,7 @@ static struct kvm_vm *pre_init_before_test(enum vm_guest_mode mode, void *arg)
 	virt_map(vm, guest_test_virt_mem, guest_test_phys_mem, guest_num_pages);
 
 	/* Cache the HVA pointer of the region */
-	host_test_mem = addr_gpa2hva(vm, (vm_paddr_t)guest_test_phys_mem);
+	host_test_mem = addr_gpa2hva(vm, (gpa_t)guest_test_phys_mem);
 
 	/* Export shared structure test_args to guest */
 	sync_global_to_guest(vm, test_args);
@@ -292,7 +292,7 @@ static struct kvm_vm *pre_init_before_test(enum vm_guest_mode mode, void *arg)
 	ret = sem_init(&test_stage_completed, 0, 0);
 	TEST_ASSERT(ret == 0, "Error in sem_init");
 
-	current_stage = addr_gva2hva(vm, (vm_vaddr_t)(&guest_test_stage));
+	current_stage = addr_gva2hva(vm, (gva_t)(&guest_test_stage));
 	*current_stage = NUM_TEST_STAGES;
 
 	pr_info("Testing guest mode: %s\n", vm_guest_mode_string(mode));
@@ -304,7 +304,7 @@ static struct kvm_vm *pre_init_before_test(enum vm_guest_mode mode, void *arg)
 	pr_info("Guest physical test memory offset: 0x%lx\n",
 		guest_test_phys_mem);
 	pr_info("Host  virtual  test memory offset: 0x%lx\n",
-		(uint64_t)host_test_mem);
+		(u64)host_test_mem);
 	pr_info("Number of testing vCPUs: %d\n", nr_vcpus);
 
 	return vm;
diff --git a/tools/testing/selftests/kvm/lib/arm64/gic.c b/tools/testing/selftests/kvm/lib/arm64/gic.c
index b023868fe0b8..011dfe1dfcb3 100644
--- a/tools/testing/selftests/kvm/lib/arm64/gic.c
+++ b/tools/testing/selftests/kvm/lib/arm64/gic.c
@@ -50,7 +50,7 @@ static void gic_dist_init(enum gic_type type, unsigned int nr_cpus)
 
 void gic_init(enum gic_type type, unsigned int nr_cpus)
 {
-	uint32_t cpu = guest_get_vcpuid();
+	u32 cpu = guest_get_vcpuid();
 
 	GUEST_ASSERT(type < GIC_TYPE_MAX);
 	GUEST_ASSERT(nr_cpus);
@@ -73,7 +73,7 @@ void gic_irq_disable(unsigned int intid)
 
 unsigned int gic_get_and_ack_irq(void)
 {
-	uint64_t irqstat;
+	u64 irqstat;
 	unsigned int intid;
 
 	GUEST_ASSERT(gic_common_ops);
@@ -102,7 +102,7 @@ void gic_set_eoi_split(bool split)
 	gic_common_ops->gic_set_eoi_split(split);
 }
 
-void gic_set_priority_mask(uint64_t pmr)
+void gic_set_priority_mask(u64 pmr)
 {
 	GUEST_ASSERT(gic_common_ops);
 	gic_common_ops->gic_set_priority_mask(pmr);
diff --git a/tools/testing/selftests/kvm/lib/arm64/gic_private.h b/tools/testing/selftests/kvm/lib/arm64/gic_private.h
index b6a7e30c3eb1..6d393f5c5685 100644
--- a/tools/testing/selftests/kvm/lib/arm64/gic_private.h
+++ b/tools/testing/selftests/kvm/lib/arm64/gic_private.h
@@ -12,20 +12,20 @@ struct gic_common_ops {
 	void (*gic_cpu_init)(unsigned int cpu);
 	void (*gic_irq_enable)(unsigned int intid);
 	void (*gic_irq_disable)(unsigned int intid);
-	uint64_t (*gic_read_iar)(void);
-	void (*gic_write_eoir)(uint32_t irq);
-	void (*gic_write_dir)(uint32_t irq);
+	u64 (*gic_read_iar)(void);
+	void (*gic_write_eoir)(u32 irq);
+	void (*gic_write_dir)(u32 irq);
 	void (*gic_set_eoi_split)(bool split);
-	void (*gic_set_priority_mask)(uint64_t mask);
-	void (*gic_set_priority)(uint32_t intid, uint32_t prio);
-	void (*gic_irq_set_active)(uint32_t intid);
-	void (*gic_irq_clear_active)(uint32_t intid);
-	bool (*gic_irq_get_active)(uint32_t intid);
-	void (*gic_irq_set_pending)(uint32_t intid);
-	void (*gic_irq_clear_pending)(uint32_t intid);
-	bool (*gic_irq_get_pending)(uint32_t intid);
-	void (*gic_irq_set_config)(uint32_t intid, bool is_edge);
-	void (*gic_irq_set_group)(uint32_t intid, bool group);
+	void (*gic_set_priority_mask)(u64 mask);
+	void (*gic_set_priority)(u32 intid, u32 prio);
+	void (*gic_irq_set_active)(u32 intid);
+	void (*gic_irq_clear_active)(u32 intid);
+	bool (*gic_irq_get_active)(u32 intid);
+	void (*gic_irq_set_pending)(u32 intid);
+	void (*gic_irq_clear_pending)(u32 intid);
+	bool (*gic_irq_get_pending)(u32 intid);
+	void (*gic_irq_set_config)(u32 intid, bool is_edge);
+	void (*gic_irq_set_group)(u32 intid, bool group);
 };
 
 extern const struct gic_common_ops gicv3_ops;
diff --git a/tools/testing/selftests/kvm/lib/arm64/gic_v3.c b/tools/testing/selftests/kvm/lib/arm64/gic_v3.c
index 50754a27f493..a99a53accfe9 100644
--- a/tools/testing/selftests/kvm/lib/arm64/gic_v3.c
+++ b/tools/testing/selftests/kvm/lib/arm64/gic_v3.c
@@ -50,13 +50,13 @@ static void gicv3_gicd_wait_for_rwp(void)
 	}
 }
 
-static inline volatile void *gicr_base_cpu(uint32_t cpu)
+static inline volatile void *gicr_base_cpu(u32 cpu)
 {
 	/* Align all the redistributors sequentially */
 	return GICR_BASE_GVA + cpu * SZ_64K * 2;
 }
 
-static void gicv3_gicr_wait_for_rwp(uint32_t cpu)
+static void gicv3_gicr_wait_for_rwp(u32 cpu)
 {
 	unsigned int count = 100000; /* 1s */
 
@@ -66,7 +66,7 @@ static void gicv3_gicr_wait_for_rwp(uint32_t cpu)
 	}
 }
 
-static void gicv3_wait_for_rwp(uint32_t cpu_or_dist)
+static void gicv3_wait_for_rwp(u32 cpu_or_dist)
 {
 	if (cpu_or_dist & DIST_BIT)
 		gicv3_gicd_wait_for_rwp();
@@ -91,34 +91,34 @@ static enum gicv3_intid_range get_intid_range(unsigned int intid)
 	return INVALID_RANGE;
 }
 
-static uint64_t gicv3_read_iar(void)
+static u64 gicv3_read_iar(void)
 {
-	uint64_t irqstat = read_sysreg_s(SYS_ICC_IAR1_EL1);
+	u64 irqstat = read_sysreg_s(SYS_ICC_IAR1_EL1);
 
 	dsb(sy);
 	return irqstat;
 }
 
-static void gicv3_write_eoir(uint32_t irq)
+static void gicv3_write_eoir(u32 irq)
 {
 	write_sysreg_s(irq, SYS_ICC_EOIR1_EL1);
 	isb();
 }
 
-static void gicv3_write_dir(uint32_t irq)
+static void gicv3_write_dir(u32 irq)
 {
 	write_sysreg_s(irq, SYS_ICC_DIR_EL1);
 	isb();
 }
 
-static void gicv3_set_priority_mask(uint64_t mask)
+static void gicv3_set_priority_mask(u64 mask)
 {
 	write_sysreg_s(mask, SYS_ICC_PMR_EL1);
 }
 
 static void gicv3_set_eoi_split(bool split)
 {
-	uint32_t val;
+	u32 val;
 
 	/*
 	 * All other fields are read-only, so no need to read CTLR first. In
@@ -129,29 +129,29 @@ static void gicv3_set_eoi_split(bool split)
 	isb();
 }
 
-uint32_t gicv3_reg_readl(uint32_t cpu_or_dist, uint64_t offset)
+u32 gicv3_reg_readl(u32 cpu_or_dist, u64 offset)
 {
 	volatile void *base = cpu_or_dist & DIST_BIT ? GICD_BASE_GVA
 			: sgi_base_from_redist(gicr_base_cpu(cpu_or_dist));
 	return readl(base + offset);
 }
 
-void gicv3_reg_writel(uint32_t cpu_or_dist, uint64_t offset, uint32_t reg_val)
+void gicv3_reg_writel(u32 cpu_or_dist, u64 offset, u32 reg_val)
 {
 	volatile void *base = cpu_or_dist & DIST_BIT ? GICD_BASE_GVA
 			: sgi_base_from_redist(gicr_base_cpu(cpu_or_dist));
 	writel(reg_val, base + offset);
 }
 
-uint32_t gicv3_getl_fields(uint32_t cpu_or_dist, uint64_t offset, uint32_t mask)
+u32 gicv3_getl_fields(u32 cpu_or_dist, u64 offset, u32 mask)
 {
 	return gicv3_reg_readl(cpu_or_dist, offset) & mask;
 }
 
-void gicv3_setl_fields(uint32_t cpu_or_dist, uint64_t offset,
-		uint32_t mask, uint32_t reg_val)
+void gicv3_setl_fields(u32 cpu_or_dist, u64 offset,
+		       u32 mask, u32 reg_val)
 {
-	uint32_t tmp = gicv3_reg_readl(cpu_or_dist, offset) & ~mask;
+	u32 tmp = gicv3_reg_readl(cpu_or_dist, offset) & ~mask;
 
 	tmp |= (reg_val & mask);
 	gicv3_reg_writel(cpu_or_dist, offset, tmp);
@@ -165,14 +165,14 @@ void gicv3_setl_fields(uint32_t cpu_or_dist, uint64_t offset,
  * map that doesn't implement it; like GICR_WAKER's offset of 0x0014 being
  * marked as "Reserved" in the Distributor map.
  */
-static void gicv3_access_reg(uint32_t intid, uint64_t offset,
-		uint32_t reg_bits, uint32_t bits_per_field,
-		bool write, uint32_t *val)
+static void gicv3_access_reg(u32 intid, u64 offset,
+			     u32 reg_bits, u32 bits_per_field,
+			     bool write, u32 *val)
 {
-	uint32_t cpu = guest_get_vcpuid();
+	u32 cpu = guest_get_vcpuid();
 	enum gicv3_intid_range intid_range = get_intid_range(intid);
-	uint32_t fields_per_reg, index, mask, shift;
-	uint32_t cpu_or_dist;
+	u32 fields_per_reg, index, mask, shift;
+	u32 cpu_or_dist;
 
 	GUEST_ASSERT(bits_per_field <= reg_bits);
 	GUEST_ASSERT(!write || *val < (1U << bits_per_field));
@@ -197,32 +197,32 @@ static void gicv3_access_reg(uint32_t intid, uint64_t offset,
 	*val = gicv3_getl_fields(cpu_or_dist, offset, mask) >> shift;
 }
 
-static void gicv3_write_reg(uint32_t intid, uint64_t offset,
-		uint32_t reg_bits, uint32_t bits_per_field, uint32_t val)
+static void gicv3_write_reg(u32 intid, u64 offset,
+			    u32 reg_bits, u32 bits_per_field, u32 val)
 {
 	gicv3_access_reg(intid, offset, reg_bits,
 			bits_per_field, true, &val);
 }
 
-static uint32_t gicv3_read_reg(uint32_t intid, uint64_t offset,
-		uint32_t reg_bits, uint32_t bits_per_field)
+static u32 gicv3_read_reg(u32 intid, u64 offset,
+			  u32 reg_bits, u32 bits_per_field)
 {
-	uint32_t val;
+	u32 val;
 
 	gicv3_access_reg(intid, offset, reg_bits,
 			bits_per_field, false, &val);
 	return val;
 }
 
-static void gicv3_set_priority(uint32_t intid, uint32_t prio)
+static void gicv3_set_priority(u32 intid, u32 prio)
 {
 	gicv3_write_reg(intid, GICD_IPRIORITYR, 32, 8, prio);
 }
 
 /* Sets the intid to be level-sensitive or edge-triggered. */
-static void gicv3_irq_set_config(uint32_t intid, bool is_edge)
+static void gicv3_irq_set_config(u32 intid, bool is_edge)
 {
-	uint32_t val;
+	u32 val;
 
 	/* N/A for private interrupts. */
 	GUEST_ASSERT(get_intid_range(intid) == SPI_RANGE);
@@ -230,57 +230,57 @@ static void gicv3_irq_set_config(uint32_t intid, bool is_edge)
 	gicv3_write_reg(intid, GICD_ICFGR, 32, 2, val);
 }
 
-static void gicv3_irq_enable(uint32_t intid)
+static void gicv3_irq_enable(u32 intid)
 {
 	bool is_spi = get_intid_range(intid) == SPI_RANGE;
-	uint32_t cpu = guest_get_vcpuid();
+	u32 cpu = guest_get_vcpuid();
 
 	gicv3_write_reg(intid, GICD_ISENABLER, 32, 1, 1);
 	gicv3_wait_for_rwp(is_spi ? DIST_BIT : cpu);
 }
 
-static void gicv3_irq_disable(uint32_t intid)
+static void gicv3_irq_disable(u32 intid)
 {
 	bool is_spi = get_intid_range(intid) == SPI_RANGE;
-	uint32_t cpu = guest_get_vcpuid();
+	u32 cpu = guest_get_vcpuid();
 
 	gicv3_write_reg(intid, GICD_ICENABLER, 32, 1, 1);
 	gicv3_wait_for_rwp(is_spi ? DIST_BIT : cpu);
 }
 
-static void gicv3_irq_set_active(uint32_t intid)
+static void gicv3_irq_set_active(u32 intid)
 {
 	gicv3_write_reg(intid, GICD_ISACTIVER, 32, 1, 1);
 }
 
-static void gicv3_irq_clear_active(uint32_t intid)
+static void gicv3_irq_clear_active(u32 intid)
 {
 	gicv3_write_reg(intid, GICD_ICACTIVER, 32, 1, 1);
 }
 
-static bool gicv3_irq_get_active(uint32_t intid)
+static bool gicv3_irq_get_active(u32 intid)
 {
 	return gicv3_read_reg(intid, GICD_ISACTIVER, 32, 1);
 }
 
-static void gicv3_irq_set_pending(uint32_t intid)
+static void gicv3_irq_set_pending(u32 intid)
 {
 	gicv3_write_reg(intid, GICD_ISPENDR, 32, 1, 1);
 }
 
-static void gicv3_irq_clear_pending(uint32_t intid)
+static void gicv3_irq_clear_pending(u32 intid)
 {
 	gicv3_write_reg(intid, GICD_ICPENDR, 32, 1, 1);
 }
 
-static bool gicv3_irq_get_pending(uint32_t intid)
+static bool gicv3_irq_get_pending(u32 intid)
 {
 	return gicv3_read_reg(intid, GICD_ISPENDR, 32, 1);
 }
 
 static void gicv3_enable_redist(volatile void *redist_base)
 {
-	uint32_t val = readl(redist_base + GICR_WAKER);
+	u32 val = readl(redist_base + GICR_WAKER);
 	unsigned int count = 100000; /* 1s */
 
 	val &= ~GICR_WAKER_ProcessorSleep;
@@ -293,10 +293,10 @@ static void gicv3_enable_redist(volatile void *redist_base)
 	}
 }
 
-static void gicv3_set_group(uint32_t intid, bool grp)
+static void gicv3_set_group(u32 intid, bool grp)
 {
-	uint32_t cpu_or_dist;
-	uint32_t val;
+	u32 cpu_or_dist;
+	u32 val;
 
 	cpu_or_dist = (get_intid_range(intid) == SPI_RANGE) ? DIST_BIT : guest_get_vcpuid();
 	val = gicv3_reg_readl(cpu_or_dist, GICD_IGROUPR + (intid / 32) * 4);
@@ -424,8 +424,8 @@ const struct gic_common_ops gicv3_ops = {
 	.gic_irq_set_group = gicv3_set_group,
 };
 
-void gic_rdist_enable_lpis(vm_paddr_t cfg_table, size_t cfg_table_size,
-			   vm_paddr_t pend_table)
+void gic_rdist_enable_lpis(gpa_t cfg_table, size_t cfg_table_size,
+			   gpa_t pend_table)
 {
 	volatile void *rdist_base = gicr_base_cpu(guest_get_vcpuid());
 
diff --git a/tools/testing/selftests/kvm/lib/arm64/gic_v3_its.c b/tools/testing/selftests/kvm/lib/arm64/gic_v3_its.c
index 7f9fdcf42ae6..1188b578121d 100644
--- a/tools/testing/selftests/kvm/lib/arm64/gic_v3_its.c
+++ b/tools/testing/selftests/kvm/lib/arm64/gic_v3_its.c
@@ -54,7 +54,7 @@ static unsigned long its_find_baser(unsigned int type)
 	return -1;
 }
 
-static void its_install_table(unsigned int type, vm_paddr_t base, size_t size)
+static void its_install_table(unsigned int type, gpa_t base, size_t size)
 {
 	unsigned long offset = its_find_baser(type);
 	u64 baser;
@@ -69,7 +69,7 @@ static void its_install_table(unsigned int type, vm_paddr_t base, size_t size)
 	its_write_u64(offset, baser);
 }
 
-static void its_install_cmdq(vm_paddr_t base, size_t size)
+static void its_install_cmdq(gpa_t base, size_t size)
 {
 	u64 cbaser;
 
@@ -82,9 +82,8 @@ static void its_install_cmdq(vm_paddr_t base, size_t size)
 	its_write_u64(GITS_CBASER, cbaser);
 }
 
-void its_init(vm_paddr_t coll_tbl, size_t coll_tbl_sz,
-	      vm_paddr_t device_tbl, size_t device_tbl_sz,
-	      vm_paddr_t cmdq, size_t cmdq_size)
+void its_init(gpa_t coll_tbl, size_t coll_tbl_sz, gpa_t device_tbl,
+	      size_t device_tbl_sz, gpa_t cmdq, size_t cmdq_size)
 {
 	u32 ctlr;
 
@@ -204,7 +203,7 @@ static void its_send_cmd(void *cmdq_base, struct its_cmd_block *cmd)
 	}
 }
 
-void its_send_mapd_cmd(void *cmdq_base, u32 device_id, vm_paddr_t itt_base,
+void its_send_mapd_cmd(void *cmdq_base, u32 device_id, gpa_t itt_base,
 		       size_t itt_size, bool valid)
 {
 	struct its_cmd_block cmd = {};
diff --git a/tools/testing/selftests/kvm/lib/arm64/processor.c b/tools/testing/selftests/kvm/lib/arm64/processor.c
index 43ea40edc533..01325bf4d36f 100644
--- a/tools/testing/selftests/kvm/lib/arm64/processor.c
+++ b/tools/testing/selftests/kvm/lib/arm64/processor.c
@@ -19,20 +19,20 @@
 
 #define DEFAULT_ARM64_GUEST_STACK_VADDR_MIN	0xac0000
 
-static vm_vaddr_t exception_handlers;
+static gva_t exception_handlers;
 
-static uint64_t pgd_index(struct kvm_vm *vm, vm_vaddr_t gva)
+static u64 pgd_index(struct kvm_vm *vm, gva_t gva)
 {
 	unsigned int shift = (vm->mmu.pgtable_levels - 1) * (vm->page_shift - 3) + vm->page_shift;
-	uint64_t mask = (1UL << (vm->va_bits - shift)) - 1;
+	u64 mask = (1UL << (vm->va_bits - shift)) - 1;
 
 	return (gva >> shift) & mask;
 }
 
-static uint64_t pud_index(struct kvm_vm *vm, vm_vaddr_t gva)
+static u64 pud_index(struct kvm_vm *vm, gva_t gva)
 {
 	unsigned int shift = 2 * (vm->page_shift - 3) + vm->page_shift;
-	uint64_t mask = (1UL << (vm->page_shift - 3)) - 1;
+	u64 mask = (1UL << (vm->page_shift - 3)) - 1;
 
 	TEST_ASSERT(vm->mmu.pgtable_levels == 4,
 		"Mode %d does not have 4 page table levels", vm->mode);
@@ -40,10 +40,10 @@ static uint64_t pud_index(struct kvm_vm *vm, vm_vaddr_t gva)
 	return (gva >> shift) & mask;
 }
 
-static uint64_t pmd_index(struct kvm_vm *vm, vm_vaddr_t gva)
+static u64 pmd_index(struct kvm_vm *vm, gva_t gva)
 {
 	unsigned int shift = (vm->page_shift - 3) + vm->page_shift;
-	uint64_t mask = (1UL << (vm->page_shift - 3)) - 1;
+	u64 mask = (1UL << (vm->page_shift - 3)) - 1;
 
 	TEST_ASSERT(vm->mmu.pgtable_levels >= 3,
 		"Mode %d does not have >= 3 page table levels", vm->mode);
@@ -51,9 +51,9 @@ static uint64_t pmd_index(struct kvm_vm *vm, vm_vaddr_t gva)
 	return (gva >> shift) & mask;
 }
 
-static uint64_t pte_index(struct kvm_vm *vm, vm_vaddr_t gva)
+static u64 pte_index(struct kvm_vm *vm, gva_t gva)
 {
-	uint64_t mask = (1UL << (vm->page_shift - 3)) - 1;
+	u64 mask = (1UL << (vm->page_shift - 3)) - 1;
 	return (gva >> vm->page_shift) & mask;
 }
 
@@ -63,9 +63,9 @@ static inline bool use_lpa2_pte_format(struct kvm_vm *vm)
 	    (vm->pa_bits > 48 || vm->va_bits > 48);
 }
 
-static uint64_t addr_pte(struct kvm_vm *vm, uint64_t pa, uint64_t attrs)
+static u64 addr_pte(struct kvm_vm *vm, u64 pa, u64 attrs)
 {
-	uint64_t pte;
+	u64 pte;
 
 	if (use_lpa2_pte_format(vm)) {
 		pte = pa & PTE_ADDR_MASK_LPA2(vm->page_shift);
@@ -81,9 +81,9 @@ static uint64_t addr_pte(struct kvm_vm *vm, uint64_t pa, uint64_t attrs)
 	return pte;
 }
 
-static uint64_t pte_addr(struct kvm_vm *vm, uint64_t pte)
+static u64 pte_addr(struct kvm_vm *vm, u64 pte)
 {
-	uint64_t pa;
+	u64 pa;
 
 	if (use_lpa2_pte_format(vm)) {
 		pa = pte & PTE_ADDR_MASK_LPA2(vm->page_shift);
@@ -97,13 +97,13 @@ static uint64_t pte_addr(struct kvm_vm *vm, uint64_t pte)
 	return pa;
 }
 
-static uint64_t ptrs_per_pgd(struct kvm_vm *vm)
+static u64 ptrs_per_pgd(struct kvm_vm *vm)
 {
 	unsigned int shift = (vm->mmu.pgtable_levels - 1) * (vm->page_shift - 3) + vm->page_shift;
 	return 1 << (vm->va_bits - shift);
 }
 
-static uint64_t __maybe_unused ptrs_per_pte(struct kvm_vm *vm)
+static u64 __maybe_unused ptrs_per_pte(struct kvm_vm *vm)
 {
 	return 1 << (vm->page_shift - 3);
 }
@@ -121,47 +121,46 @@ void virt_arch_pgd_alloc(struct kvm_vm *vm)
 	vm->mmu.pgd_created = true;
 }
 
-static void _virt_pg_map(struct kvm_vm *vm, uint64_t vaddr, uint64_t paddr,
-			 uint64_t flags)
+static void _virt_pg_map(struct kvm_vm *vm, gva_t gva, gpa_t gpa,
+			 u64 flags)
 {
-	uint8_t attr_idx = flags & (PTE_ATTRINDX_MASK >> PTE_ATTRINDX_SHIFT);
-	uint64_t pg_attr;
-	uint64_t *ptep;
+	u8 attr_idx = flags & (PTE_ATTRINDX_MASK >> PTE_ATTRINDX_SHIFT);
+	u64 pg_attr;
+	u64 *ptep;
 
-	TEST_ASSERT((vaddr % vm->page_size) == 0,
+	TEST_ASSERT((gva % vm->page_size) == 0,
 		"Virtual address not on page boundary,\n"
-		"  vaddr: 0x%lx vm->page_size: 0x%x", vaddr, vm->page_size);
-	TEST_ASSERT(sparsebit_is_set(vm->vpages_valid,
-		(vaddr >> vm->page_shift)),
-		"Invalid virtual address, vaddr: 0x%lx", vaddr);
-	TEST_ASSERT((paddr % vm->page_size) == 0,
-		"Physical address not on page boundary,\n"
-		"  paddr: 0x%lx vm->page_size: 0x%x", paddr, vm->page_size);
-	TEST_ASSERT((paddr >> vm->page_shift) <= vm->max_gfn,
-		"Physical address beyond beyond maximum supported,\n"
-		"  paddr: 0x%lx vm->max_gfn: 0x%lx vm->page_size: 0x%x",
-		paddr, vm->max_gfn, vm->page_size);
-
-	ptep = addr_gpa2hva(vm, vm->mmu.pgd) + pgd_index(vm, vaddr) * 8;
+		"  gva: 0x%lx vm->page_size: 0x%x", gva, vm->page_size);
+	TEST_ASSERT(sparsebit_is_set(vm->vpages_valid, (gva >> vm->page_shift)),
+		    "Invalid virtual address, gva: 0x%lx", gva);
+	TEST_ASSERT((gpa % vm->page_size) == 0,
+		    "Physical address not on page boundary,\n"
+		    "  gpa: 0x%lx vm->page_size: 0x%x", gpa, vm->page_size);
+	TEST_ASSERT((gpa >> vm->page_shift) <= vm->max_gfn,
+		    "Physical address beyond beyond maximum supported,\n"
+		    "  gpa: 0x%lx vm->max_gfn: 0x%lx vm->page_size: 0x%x",
+		    gpa, vm->max_gfn, vm->page_size);
+
+	ptep = addr_gpa2hva(vm, vm->mmu.pgd) + pgd_index(vm, gva) * 8;
 	if (!*ptep)
 		*ptep = addr_pte(vm, vm_alloc_page_table(vm),
 				 PGD_TYPE_TABLE | PTE_VALID);
 
 	switch (vm->mmu.pgtable_levels) {
 	case 4:
-		ptep = addr_gpa2hva(vm, pte_addr(vm, *ptep)) + pud_index(vm, vaddr) * 8;
+		ptep = addr_gpa2hva(vm, pte_addr(vm, *ptep)) + pud_index(vm, gva) * 8;
 		if (!*ptep)
 			*ptep = addr_pte(vm, vm_alloc_page_table(vm),
 					 PUD_TYPE_TABLE | PTE_VALID);
 		/* fall through */
 	case 3:
-		ptep = addr_gpa2hva(vm, pte_addr(vm, *ptep)) + pmd_index(vm, vaddr) * 8;
+		ptep = addr_gpa2hva(vm, pte_addr(vm, *ptep)) + pmd_index(vm, gva) * 8;
 		if (!*ptep)
 			*ptep = addr_pte(vm, vm_alloc_page_table(vm),
 					 PMD_TYPE_TABLE | PTE_VALID);
 		/* fall through */
 	case 2:
-		ptep = addr_gpa2hva(vm, pte_addr(vm, *ptep)) + pte_index(vm, vaddr) * 8;
+		ptep = addr_gpa2hva(vm, pte_addr(vm, *ptep)) + pte_index(vm, gva) * 8;
 		break;
 	default:
 		TEST_FAIL("Page table levels must be 2, 3, or 4");
@@ -171,19 +170,19 @@ static void _virt_pg_map(struct kvm_vm *vm, uint64_t vaddr, uint64_t paddr,
 	if (!use_lpa2_pte_format(vm))
 		pg_attr |= PTE_SHARED;
 
-	*ptep = addr_pte(vm, paddr, pg_attr);
+	*ptep = addr_pte(vm, gpa, pg_attr);
 }
 
-void virt_arch_pg_map(struct kvm_vm *vm, uint64_t vaddr, uint64_t paddr)
+void virt_arch_pg_map(struct kvm_vm *vm, gva_t gva, gpa_t gpa)
 {
-	uint64_t attr_idx = MT_NORMAL;
+	u64 attr_idx = MT_NORMAL;
 
-	_virt_pg_map(vm, vaddr, paddr, attr_idx);
+	_virt_pg_map(vm, gva, gpa, attr_idx);
 }
 
-uint64_t *virt_get_pte_hva_at_level(struct kvm_vm *vm, vm_vaddr_t gva, int level)
+u64 *virt_get_pte_hva_at_level(struct kvm_vm *vm, gva_t gva, int level)
 {
-	uint64_t *ptep;
+	u64 *ptep;
 
 	if (!vm->mmu.pgd_created)
 		goto unmapped_gva;
@@ -225,23 +224,23 @@ uint64_t *virt_get_pte_hva_at_level(struct kvm_vm *vm, vm_vaddr_t gva, int level
 	exit(EXIT_FAILURE);
 }
 
-uint64_t *virt_get_pte_hva(struct kvm_vm *vm, vm_vaddr_t gva)
+u64 *virt_get_pte_hva(struct kvm_vm *vm, gva_t gva)
 {
 	return virt_get_pte_hva_at_level(vm, gva, 3);
 }
 
-vm_paddr_t addr_arch_gva2gpa(struct kvm_vm *vm, vm_vaddr_t gva)
+gpa_t addr_arch_gva2gpa(struct kvm_vm *vm, gva_t gva)
 {
-	uint64_t *ptep = virt_get_pte_hva(vm, gva);
+	u64 *ptep = virt_get_pte_hva(vm, gva);
 
 	return pte_addr(vm, *ptep) + (gva & (vm->page_size - 1));
 }
 
-static void pte_dump(FILE *stream, struct kvm_vm *vm, uint8_t indent, uint64_t page, int level)
+static void pte_dump(FILE *stream, struct kvm_vm *vm, u8 indent, u64 page, int level)
 {
 #ifdef DEBUG
 	static const char * const type[] = { "", "pud", "pmd", "pte" };
-	uint64_t pte, *ptep;
+	u64 pte, *ptep;
 
 	if (level == 4)
 		return;
@@ -256,10 +255,10 @@ static void pte_dump(FILE *stream, struct kvm_vm *vm, uint8_t indent, uint64_t p
 #endif
 }
 
-void virt_arch_dump(FILE *stream, struct kvm_vm *vm, uint8_t indent)
+void virt_arch_dump(FILE *stream, struct kvm_vm *vm, u8 indent)
 {
 	int level = 4 - (vm->mmu.pgtable_levels - 1);
-	uint64_t pgd, *ptep;
+	u64 pgd, *ptep;
 
 	if (!vm->mmu.pgd_created)
 		return;
@@ -298,7 +297,7 @@ void aarch64_vcpu_setup(struct kvm_vcpu *vcpu, struct kvm_vcpu_init *init)
 {
 	struct kvm_vcpu_init default_init = { .target = -1, };
 	struct kvm_vm *vm = vcpu->vm;
-	uint64_t sctlr_el1, tcr_el1, ttbr0_el1;
+	u64 sctlr_el1, tcr_el1, ttbr0_el1;
 
 	if (!init) {
 		kvm_get_default_vcpu_target(vm, &default_init);
@@ -397,9 +396,9 @@ void aarch64_vcpu_setup(struct kvm_vcpu *vcpu, struct kvm_vcpu_init *init)
 		     HCR_EL2_RW | HCR_EL2_TGE | HCR_EL2_E2H);
 }
 
-void vcpu_arch_dump(FILE *stream, struct kvm_vcpu *vcpu, uint8_t indent)
+void vcpu_arch_dump(FILE *stream, struct kvm_vcpu *vcpu, u8 indent)
 {
-	uint64_t pstate, pc;
+	u64 pstate, pc;
 
 	pstate = vcpu_get_reg(vcpu, ARM64_CORE_REG(regs.pstate));
 	pc = vcpu_get_reg(vcpu, ARM64_CORE_REG(regs.pc));
@@ -410,29 +409,29 @@ void vcpu_arch_dump(FILE *stream, struct kvm_vcpu *vcpu, uint8_t indent)
 
 void vcpu_arch_set_entry_point(struct kvm_vcpu *vcpu, void *guest_code)
 {
-	vcpu_set_reg(vcpu, ARM64_CORE_REG(regs.pc), (uint64_t)guest_code);
+	vcpu_set_reg(vcpu, ARM64_CORE_REG(regs.pc), (u64)guest_code);
 }
 
-static struct kvm_vcpu *__aarch64_vcpu_add(struct kvm_vm *vm, uint32_t vcpu_id,
+static struct kvm_vcpu *__aarch64_vcpu_add(struct kvm_vm *vm, u32 vcpu_id,
 					   struct kvm_vcpu_init *init)
 {
 	size_t stack_size;
-	uint64_t stack_vaddr;
+	gva_t stack_gva;
 	struct kvm_vcpu *vcpu = __vm_vcpu_add(vm, vcpu_id);
 
 	stack_size = vm->page_size == 4096 ? DEFAULT_STACK_PGS * vm->page_size :
 					     vm->page_size;
-	stack_vaddr = __vm_vaddr_alloc(vm, stack_size,
-				       DEFAULT_ARM64_GUEST_STACK_VADDR_MIN,
-				       MEM_REGION_DATA);
+	stack_gva = __vm_alloc(vm, stack_size,
+			       DEFAULT_ARM64_GUEST_STACK_VADDR_MIN,
+			       MEM_REGION_DATA);
 
 	aarch64_vcpu_setup(vcpu, init);
 
-	vcpu_set_reg(vcpu, ctxt_reg_alias(vcpu, SYS_SP_EL1), stack_vaddr + stack_size);
+	vcpu_set_reg(vcpu, ctxt_reg_alias(vcpu, SYS_SP_EL1), stack_gva + stack_size);
 	return vcpu;
 }
 
-struct kvm_vcpu *aarch64_vcpu_add(struct kvm_vm *vm, uint32_t vcpu_id,
+struct kvm_vcpu *aarch64_vcpu_add(struct kvm_vm *vm, u32 vcpu_id,
 				  struct kvm_vcpu_init *init, void *guest_code)
 {
 	struct kvm_vcpu *vcpu = __aarch64_vcpu_add(vm, vcpu_id, init);
@@ -442,7 +441,7 @@ struct kvm_vcpu *aarch64_vcpu_add(struct kvm_vm *vm, uint32_t vcpu_id,
 	return vcpu;
 }
 
-struct kvm_vcpu *vm_arch_vcpu_add(struct kvm_vm *vm, uint32_t vcpu_id)
+struct kvm_vcpu *vm_arch_vcpu_add(struct kvm_vm *vm, u32 vcpu_id)
 {
 	return __aarch64_vcpu_add(vm, vcpu_id, NULL);
 }
@@ -459,13 +458,13 @@ void vcpu_args_set(struct kvm_vcpu *vcpu, unsigned int num, ...)
 
 	for (i = 0; i < num; i++) {
 		vcpu_set_reg(vcpu, ARM64_CORE_REG(regs.regs[i]),
-			     va_arg(ap, uint64_t));
+			     va_arg(ap, u64));
 	}
 
 	va_end(ap);
 }
 
-void kvm_exit_unexpected_exception(int vector, uint64_t ec, bool valid_ec)
+void kvm_exit_unexpected_exception(int vector, u64 ec, bool valid_ec)
 {
 	ucall(UCALL_UNHANDLED, 3, vector, ec, valid_ec);
 	while (1)
@@ -498,7 +497,7 @@ void vcpu_init_descriptor_tables(struct kvm_vcpu *vcpu)
 {
 	extern char vectors;
 
-	vcpu_set_reg(vcpu, ctxt_reg_alias(vcpu, SYS_VBAR_EL1), (uint64_t)&vectors);
+	vcpu_set_reg(vcpu, ctxt_reg_alias(vcpu, SYS_VBAR_EL1), (u64)&vectors);
 }
 
 void route_exception(struct ex_regs *regs, int vector)
@@ -536,10 +535,10 @@ void route_exception(struct ex_regs *regs, int vector)
 
 void vm_init_descriptor_tables(struct kvm_vm *vm)
 {
-	vm->handlers = __vm_vaddr_alloc(vm, sizeof(struct handlers),
-					vm->page_size, MEM_REGION_DATA);
+	vm->handlers = __vm_alloc(vm, sizeof(struct handlers), vm->page_size,
+				  MEM_REGION_DATA);
 
-	*(vm_vaddr_t *)addr_gva2hva(vm, (vm_vaddr_t)(&exception_handlers)) = vm->handlers;
+	*(gva_t *)addr_gva2hva(vm, (gva_t)(&exception_handlers)) = vm->handlers;
 }
 
 void vm_install_sync_handler(struct kvm_vm *vm, int vector, int ec,
@@ -563,13 +562,13 @@ void vm_install_exception_handler(struct kvm_vm *vm, int vector,
 	handlers->exception_handlers[vector][0] = handler;
 }
 
-uint32_t guest_get_vcpuid(void)
+u32 guest_get_vcpuid(void)
 {
 	return read_sysreg(tpidr_el1);
 }
 
-static uint32_t max_ipa_for_page_size(uint32_t vm_ipa, uint32_t gran,
-				uint32_t not_sup_val, uint32_t ipa52_min_val)
+static u32 max_ipa_for_page_size(u32 vm_ipa, u32 gran,
+				 u32 not_sup_val, u32 ipa52_min_val)
 {
 	if (gran == not_sup_val)
 		return 0;
@@ -579,16 +578,16 @@ static uint32_t max_ipa_for_page_size(uint32_t vm_ipa, uint32_t gran,
 		return min(vm_ipa, 48U);
 }
 
-void aarch64_get_supported_page_sizes(uint32_t ipa, uint32_t *ipa4k,
-					uint32_t *ipa16k, uint32_t *ipa64k)
+void aarch64_get_supported_page_sizes(u32 ipa, u32 *ipa4k,
+				      u32 *ipa16k, u32 *ipa64k)
 {
 	struct kvm_vcpu_init preferred_init;
 	int kvm_fd, vm_fd, vcpu_fd, err;
-	uint64_t val;
-	uint32_t gran;
+	u64 val;
+	u32 gran;
 	struct kvm_one_reg reg = {
 		.id	= KVM_ARM64_SYS_REG(SYS_ID_AA64MMFR0_EL1),
-		.addr	= (uint64_t)&val,
+		.addr	= (u64)&val,
 	};
 
 	kvm_fd = open_kvm_dev_path_or_exit();
@@ -646,17 +645,17 @@ void aarch64_get_supported_page_sizes(uint32_t ipa, uint32_t *ipa4k,
 		     : "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7")
 
 
-void smccc_hvc(uint32_t function_id, uint64_t arg0, uint64_t arg1,
-	       uint64_t arg2, uint64_t arg3, uint64_t arg4, uint64_t arg5,
-	       uint64_t arg6, struct arm_smccc_res *res)
+void smccc_hvc(u32 function_id, u64 arg0, u64 arg1,
+	       u64 arg2, u64 arg3, u64 arg4, u64 arg5,
+	       u64 arg6, struct arm_smccc_res *res)
 {
 	__smccc_call(hvc, function_id, arg0, arg1, arg2, arg3, arg4, arg5,
 		     arg6, res);
 }
 
-void smccc_smc(uint32_t function_id, uint64_t arg0, uint64_t arg1,
-	       uint64_t arg2, uint64_t arg3, uint64_t arg4, uint64_t arg5,
-	       uint64_t arg6, struct arm_smccc_res *res)
+void smccc_smc(u32 function_id, u64 arg0, u64 arg1,
+	       u64 arg2, u64 arg3, u64 arg4, u64 arg5,
+	       u64 arg6, struct arm_smccc_res *res)
 {
 	__smccc_call(smc, function_id, arg0, arg1, arg2, arg3, arg4, arg5,
 		     arg6, res);
@@ -671,7 +670,7 @@ void kvm_selftest_arch_init(void)
 	guest_modes_append_default();
 }
 
-void vm_vaddr_populate_bitmap(struct kvm_vm *vm)
+void vm_populate_gva_bitmap(struct kvm_vm *vm)
 {
 	/*
 	 * arm64 selftests use only TTBR0_EL1, meaning that the valid VA space
diff --git a/tools/testing/selftests/kvm/lib/arm64/ucall.c b/tools/testing/selftests/kvm/lib/arm64/ucall.c
index ddab0ce89d4d..e0550ad5aa75 100644
--- a/tools/testing/selftests/kvm/lib/arm64/ucall.c
+++ b/tools/testing/selftests/kvm/lib/arm64/ucall.c
@@ -6,17 +6,17 @@
  */
 #include "kvm_util.h"
 
-vm_vaddr_t *ucall_exit_mmio_addr;
+gva_t *ucall_exit_mmio_addr;
 
-void ucall_arch_init(struct kvm_vm *vm, vm_paddr_t mmio_gpa)
+void ucall_arch_init(struct kvm_vm *vm, gpa_t mmio_gpa)
 {
-	vm_vaddr_t mmio_gva = vm_vaddr_unused_gap(vm, vm->page_size, KVM_UTIL_MIN_VADDR);
+	gva_t mmio_gva = vm_unused_gva_gap(vm, vm->page_size, KVM_UTIL_MIN_VADDR);
 
 	virt_map(vm, mmio_gva, mmio_gpa, 1);
 
 	vm->ucall_mmio_addr = mmio_gpa;
 
-	write_guest_global(vm, ucall_exit_mmio_addr, (vm_vaddr_t *)mmio_gva);
+	write_guest_global(vm, ucall_exit_mmio_addr, (gva_t *)mmio_gva);
 }
 
 void *ucall_arch_get_ucall(struct kvm_vcpu *vcpu)
@@ -25,9 +25,9 @@ void *ucall_arch_get_ucall(struct kvm_vcpu *vcpu)
 
 	if (run->exit_reason == KVM_EXIT_MMIO &&
 	    run->mmio.phys_addr == vcpu->vm->ucall_mmio_addr) {
-		TEST_ASSERT(run->mmio.is_write && run->mmio.len == sizeof(uint64_t),
+		TEST_ASSERT(run->mmio.is_write && run->mmio.len == sizeof(u64),
 			    "Unexpected ucall exit mmio address access");
-		return (void *)(*((uint64_t *)run->mmio.data));
+		return (void *)(*((u64 *)run->mmio.data));
 	}
 
 	return NULL;
diff --git a/tools/testing/selftests/kvm/lib/arm64/vgic.c b/tools/testing/selftests/kvm/lib/arm64/vgic.c
index d0f7bd0984b8..4ecebf3146a2 100644
--- a/tools/testing/selftests/kvm/lib/arm64/vgic.c
+++ b/tools/testing/selftests/kvm/lib/arm64/vgic.c
@@ -41,10 +41,10 @@ bool kvm_supports_vgic_v3(void)
  * redistributor regions of the guest. Since it depends on the number of
  * vCPUs for the VM, it must be called after all the vCPUs have been created.
  */
-int __vgic_v3_setup(struct kvm_vm *vm, unsigned int nr_vcpus, uint32_t nr_irqs)
+int __vgic_v3_setup(struct kvm_vm *vm, unsigned int nr_vcpus, u32 nr_irqs)
 {
 	int gic_fd;
-	uint64_t attr;
+	u64 attr;
 	unsigned int nr_gic_pages;
 
 	/* Distributor setup */
@@ -77,7 +77,7 @@ void __vgic_v3_init(int fd)
 			    KVM_DEV_ARM_VGIC_CTRL_INIT, NULL);
 }
 
-int vgic_v3_setup(struct kvm_vm *vm, unsigned int nr_vcpus, uint32_t nr_irqs)
+int vgic_v3_setup(struct kvm_vm *vm, unsigned int nr_vcpus, u32 nr_irqs)
 {
 	unsigned int nr_vcpus_created = 0;
 	struct list_head *iter;
@@ -104,11 +104,11 @@ int vgic_v3_setup(struct kvm_vm *vm, unsigned int nr_vcpus, uint32_t nr_irqs)
 }
 
 /* should only work for level sensitive interrupts */
-int _kvm_irq_set_level_info(int gic_fd, uint32_t intid, int level)
+int _kvm_irq_set_level_info(int gic_fd, u32 intid, int level)
 {
-	uint64_t attr = 32 * (intid / 32);
-	uint64_t index = intid % 32;
-	uint64_t val;
+	u64 attr = 32 * (intid / 32);
+	u64 index = intid % 32;
+	u64 val;
 	int ret;
 
 	ret = __kvm_device_attr_get(gic_fd, KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO,
@@ -122,16 +122,16 @@ int _kvm_irq_set_level_info(int gic_fd, uint32_t intid, int level)
 	return ret;
 }
 
-void kvm_irq_set_level_info(int gic_fd, uint32_t intid, int level)
+void kvm_irq_set_level_info(int gic_fd, u32 intid, int level)
 {
 	int ret = _kvm_irq_set_level_info(gic_fd, intid, level);
 
 	TEST_ASSERT(!ret, KVM_IOCTL_ERROR(KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO, ret));
 }
 
-int _kvm_arm_irq_line(struct kvm_vm *vm, uint32_t intid, int level)
+int _kvm_arm_irq_line(struct kvm_vm *vm, u32 intid, int level)
 {
-	uint32_t irq = intid & KVM_ARM_IRQ_NUM_MASK;
+	u32 irq = intid & KVM_ARM_IRQ_NUM_MASK;
 
 	TEST_ASSERT(!INTID_IS_SGI(intid), "KVM_IRQ_LINE's interface itself "
 		"doesn't allow injecting SGIs. There's no mask for it.");
@@ -144,23 +144,23 @@ int _kvm_arm_irq_line(struct kvm_vm *vm, uint32_t intid, int level)
 	return _kvm_irq_line(vm, irq, level);
 }
 
-void kvm_arm_irq_line(struct kvm_vm *vm, uint32_t intid, int level)
+void kvm_arm_irq_line(struct kvm_vm *vm, u32 intid, int level)
 {
 	int ret = _kvm_arm_irq_line(vm, intid, level);
 
 	TEST_ASSERT(!ret, KVM_IOCTL_ERROR(KVM_IRQ_LINE, ret));
 }
 
-static void vgic_poke_irq(int gic_fd, uint32_t intid, struct kvm_vcpu *vcpu,
-			  uint64_t reg_off)
+static void vgic_poke_irq(int gic_fd, u32 intid, struct kvm_vcpu *vcpu,
+			  u64 reg_off)
 {
-	uint64_t reg = intid / 32;
-	uint64_t index = intid % 32;
-	uint64_t attr = reg_off + reg * 4;
-	uint64_t val;
+	u64 reg = intid / 32;
+	u64 index = intid % 32;
+	u64 attr = reg_off + reg * 4;
+	u64 val;
 	bool intid_is_private = INTID_IS_SGI(intid) || INTID_IS_PPI(intid);
 
-	uint32_t group = intid_is_private ? KVM_DEV_ARM_VGIC_GRP_REDIST_REGS
+	u32 group = intid_is_private ? KVM_DEV_ARM_VGIC_GRP_REDIST_REGS
 					  : KVM_DEV_ARM_VGIC_GRP_DIST_REGS;
 
 	if (intid_is_private) {
@@ -183,12 +183,12 @@ static void vgic_poke_irq(int gic_fd, uint32_t intid, struct kvm_vcpu *vcpu,
 	kvm_device_attr_set(gic_fd, group, attr, &val);
 }
 
-void kvm_irq_write_ispendr(int gic_fd, uint32_t intid, struct kvm_vcpu *vcpu)
+void kvm_irq_write_ispendr(int gic_fd, u32 intid, struct kvm_vcpu *vcpu)
 {
 	vgic_poke_irq(gic_fd, intid, vcpu, GICD_ISPENDR);
 }
 
-void kvm_irq_write_isactiver(int gic_fd, uint32_t intid, struct kvm_vcpu *vcpu)
+void kvm_irq_write_isactiver(int gic_fd, u32 intid, struct kvm_vcpu *vcpu)
 {
 	vgic_poke_irq(gic_fd, intid, vcpu, GICD_ISACTIVER);
 }
diff --git a/tools/testing/selftests/kvm/lib/elf.c b/tools/testing/selftests/kvm/lib/elf.c
index f34d926d9735..b689c4df4a01 100644
--- a/tools/testing/selftests/kvm/lib/elf.c
+++ b/tools/testing/selftests/kvm/lib/elf.c
@@ -156,21 +156,20 @@ void kvm_vm_elf_load(struct kvm_vm *vm, const char *filename)
 		TEST_ASSERT(phdr.p_memsz > 0, "Unexpected loadable segment "
 			"memsize of 0,\n"
 			"  phdr index: %u p_memsz: 0x%" PRIx64,
-			n1, (uint64_t) phdr.p_memsz);
-		vm_vaddr_t seg_vstart = align_down(phdr.p_vaddr, vm->page_size);
-		vm_vaddr_t seg_vend = phdr.p_vaddr + phdr.p_memsz - 1;
+			n1, (u64)phdr.p_memsz);
+		gva_t seg_vstart = align_down(phdr.p_vaddr, vm->page_size);
+		gva_t seg_vend = phdr.p_vaddr + phdr.p_memsz - 1;
 		seg_vend |= vm->page_size - 1;
 		size_t seg_size = seg_vend - seg_vstart + 1;
 
-		vm_vaddr_t vaddr = __vm_vaddr_alloc(vm, seg_size, seg_vstart,
-						    MEM_REGION_CODE);
-		TEST_ASSERT(vaddr == seg_vstart, "Unable to allocate "
+		gva_t gva = __vm_alloc(vm, seg_size, seg_vstart, MEM_REGION_CODE);
+		TEST_ASSERT(gva == seg_vstart, "Unable to allocate "
 			"virtual memory for segment at requested min addr,\n"
 			"  segment idx: %u\n"
 			"  seg_vstart: 0x%lx\n"
-			"  vaddr: 0x%lx",
-			n1, seg_vstart, vaddr);
-		memset(addr_gva2hva(vm, vaddr), 0, seg_size);
+			"  gva: 0x%lx",
+			n1, seg_vstart, gva);
+		memset(addr_gva2hva(vm, gva), 0, seg_size);
 		/* TODO(lhuemill): Set permissions of each memory segment
 		 * based on the least-significant 3 bits of phdr.p_flags.
 		 */
diff --git a/tools/testing/selftests/kvm/lib/guest_modes.c b/tools/testing/selftests/kvm/lib/guest_modes.c
index ce3099630397..7a96c43b5704 100644
--- a/tools/testing/selftests/kvm/lib/guest_modes.c
+++ b/tools/testing/selftests/kvm/lib/guest_modes.c
@@ -20,7 +20,7 @@ void guest_modes_append_default(void)
 #ifdef __aarch64__
 	{
 		unsigned int limit = kvm_check_cap(KVM_CAP_ARM_VM_IPA_SIZE);
-		uint32_t ipa4k, ipa16k, ipa64k;
+		u32 ipa4k, ipa16k, ipa64k;
 		int i;
 
 		aarch64_get_supported_page_sizes(limit, &ipa4k, &ipa16k, &ipa64k);
diff --git a/tools/testing/selftests/kvm/lib/guest_sprintf.c b/tools/testing/selftests/kvm/lib/guest_sprintf.c
index 74627514c4d4..7a33965349a7 100644
--- a/tools/testing/selftests/kvm/lib/guest_sprintf.c
+++ b/tools/testing/selftests/kvm/lib/guest_sprintf.c
@@ -35,8 +35,8 @@ static int skip_atoi(const char **s)
 ({							\
 	int __res;					\
 							\
-	__res = ((uint64_t) n) % (uint32_t) base;	\
-	n = ((uint64_t) n) / (uint32_t) base;		\
+	__res = ((u64)n) % (u32)base;			\
+	n = ((u64)n) / (u32)base;			\
 	__res;						\
 })
 
@@ -119,7 +119,7 @@ int guest_vsnprintf(char *buf, int n, const char *fmt, va_list args)
 {
 	char *str, *end;
 	const char *s;
-	uint64_t num;
+	u64 num;
 	int i, base;
 	int len;
 
@@ -216,7 +216,7 @@ int guest_vsnprintf(char *buf, int n, const char *fmt, va_list args)
 				while (--field_width > 0)
 					APPEND_BUFFER_SAFE(str, end, ' ');
 			APPEND_BUFFER_SAFE(str, end,
-					    (uint8_t)va_arg(args, int));
+					    (u8)va_arg(args, int));
 			while (--field_width > 0)
 				APPEND_BUFFER_SAFE(str, end, ' ');
 			continue;
@@ -240,7 +240,7 @@ int guest_vsnprintf(char *buf, int n, const char *fmt, va_list args)
 				flags |= SPECIAL | SMALL | ZEROPAD;
 			}
 			str = number(str, end,
-				     (uint64_t)va_arg(args, void *), 16,
+				     (u64)va_arg(args, void *), 16,
 				     field_width, precision, flags);
 			continue;
 
@@ -284,15 +284,15 @@ int guest_vsnprintf(char *buf, int n, const char *fmt, va_list args)
 			continue;
 		}
 		if (qualifier == 'l')
-			num = va_arg(args, uint64_t);
+			num = va_arg(args, u64);
 		else if (qualifier == 'h') {
-			num = (uint16_t)va_arg(args, int);
+			num = (u16)va_arg(args, int);
 			if (flags & SIGN)
-				num = (int16_t)num;
+				num = (s16)num;
 		} else if (flags & SIGN)
 			num = va_arg(args, int);
 		else
-			num = va_arg(args, uint32_t);
+			num = va_arg(args, u32);
 		str = number(str, end, num, base, field_width, precision, flags);
 	}
 
diff --git a/tools/testing/selftests/kvm/lib/kvm_util.c b/tools/testing/selftests/kvm/lib/kvm_util.c
index f5e076591c64..2a76eca7029d 100644
--- a/tools/testing/selftests/kvm/lib/kvm_util.c
+++ b/tools/testing/selftests/kvm/lib/kvm_util.c
@@ -20,9 +20,9 @@
 
 #define KVM_UTIL_MIN_PFN	2
 
-uint32_t guest_random_seed;
+u32 guest_random_seed;
 struct guest_random_state guest_rng;
-static uint32_t last_guest_seed;
+static u32 last_guest_seed;
 
 static size_t vcpu_mmap_sz(void);
 
@@ -165,7 +165,7 @@ unsigned int kvm_check_cap(long cap)
 	return (unsigned int)ret;
 }
 
-void vm_enable_dirty_ring(struct kvm_vm *vm, uint32_t ring_size)
+void vm_enable_dirty_ring(struct kvm_vm *vm, u32 ring_size)
 {
 	if (vm_check_cap(vm, KVM_CAP_DIRTY_LOG_RING_ACQ_REL))
 		vm_enable_cap(vm, KVM_CAP_DIRTY_LOG_RING_ACQ_REL, ring_size);
@@ -189,7 +189,7 @@ static void vm_open(struct kvm_vm *vm)
 		vm->stats.fd = -1;
 }
 
-const char *vm_guest_mode_string(uint32_t i)
+const char *vm_guest_mode_string(u32 i)
 {
 	static const char * const strings[] = {
 		[VM_MODE_P52V48_4K]	= "PA-bits:52,  VA-bits:48,  4K pages",
@@ -267,7 +267,7 @@ _Static_assert(sizeof(vm_guest_mode_params)/sizeof(struct vm_guest_mode_params)
  * based on the MSB of the VA. On architectures with this behavior
  * the VA region spans [0, 2^(va_bits - 1)), [-(2^(va_bits - 1), -1].
  */
-__weak void vm_vaddr_populate_bitmap(struct kvm_vm *vm)
+__weak void vm_populate_gva_bitmap(struct kvm_vm *vm)
 {
 	sparsebit_set_num(vm->vpages_valid,
 		0, (1ULL << (vm->va_bits - 1)) >> vm->page_shift);
@@ -385,7 +385,7 @@ struct kvm_vm *____vm_create(struct vm_shape shape)
 
 	/* Limit to VA-bit canonical virtual addresses. */
 	vm->vpages_valid = sparsebit_alloc();
-	vm_vaddr_populate_bitmap(vm);
+	vm_populate_gva_bitmap(vm);
 
 	/* Limit physical addresses to PA-bits. */
 	vm->max_gfn = vm_compute_max_gfn(vm);
@@ -396,12 +396,12 @@ struct kvm_vm *____vm_create(struct vm_shape shape)
 	return vm;
 }
 
-static uint64_t vm_nr_pages_required(enum vm_guest_mode mode,
-				     uint32_t nr_runnable_vcpus,
-				     uint64_t extra_mem_pages)
+static u64 vm_nr_pages_required(enum vm_guest_mode mode,
+				u32 nr_runnable_vcpus,
+				u64 extra_mem_pages)
 {
-	uint64_t page_size = vm_guest_mode_params[mode].page_size;
-	uint64_t nr_pages;
+	u64 page_size = vm_guest_mode_params[mode].page_size;
+	u64 nr_pages;
 
 	TEST_ASSERT(nr_runnable_vcpus,
 		    "Use vm_create_barebones() for VMs that _never_ have vCPUs");
@@ -435,7 +435,7 @@ static uint64_t vm_nr_pages_required(enum vm_guest_mode mode,
 	return vm_adjust_num_guest_pages(mode, nr_pages);
 }
 
-void kvm_set_files_rlimit(uint32_t nr_vcpus)
+void kvm_set_files_rlimit(u32 nr_vcpus)
 {
 	/*
 	 * Each vCPU will open two file descriptors: the vCPU itself and the
@@ -476,10 +476,10 @@ static bool is_guest_memfd_required(struct vm_shape shape)
 #endif
 }
 
-struct kvm_vm *__vm_create(struct vm_shape shape, uint32_t nr_runnable_vcpus,
-			   uint64_t nr_extra_pages)
+struct kvm_vm *__vm_create(struct vm_shape shape, u32 nr_runnable_vcpus,
+			   u64 nr_extra_pages)
 {
-	uint64_t nr_pages = vm_nr_pages_required(shape.mode, nr_runnable_vcpus,
+	u64 nr_pages = vm_nr_pages_required(shape.mode, nr_runnable_vcpus,
 						 nr_extra_pages);
 	struct userspace_mem_region *slot0;
 	struct kvm_vm *vm;
@@ -546,8 +546,8 @@ struct kvm_vm *__vm_create(struct vm_shape shape, uint32_t nr_runnable_vcpus,
  * extra_mem_pages is only used to calculate the maximum page table size,
  * no real memory allocation for non-slot0 memory in this function.
  */
-struct kvm_vm *__vm_create_with_vcpus(struct vm_shape shape, uint32_t nr_vcpus,
-				      uint64_t extra_mem_pages,
+struct kvm_vm *__vm_create_with_vcpus(struct vm_shape shape, u32 nr_vcpus,
+				      u64 extra_mem_pages,
 				      void *guest_code, struct kvm_vcpu *vcpus[])
 {
 	struct kvm_vm *vm;
@@ -566,7 +566,7 @@ struct kvm_vm *__vm_create_with_vcpus(struct vm_shape shape, uint32_t nr_vcpus,
 
 struct kvm_vm *__vm_create_shape_with_one_vcpu(struct vm_shape shape,
 					       struct kvm_vcpu **vcpu,
-					       uint64_t extra_mem_pages,
+					       u64 extra_mem_pages,
 					       void *guest_code)
 {
 	struct kvm_vcpu *vcpus[1];
@@ -614,7 +614,7 @@ void kvm_vm_restart(struct kvm_vm *vmp)
 }
 
 __weak struct kvm_vcpu *vm_arch_vcpu_recreate(struct kvm_vm *vm,
-					      uint32_t vcpu_id)
+					      u32 vcpu_id)
 {
 	return __vm_vcpu_add(vm, vcpu_id);
 }
@@ -636,9 +636,9 @@ int __pin_task_to_cpu(pthread_t task, int cpu)
 	return pthread_setaffinity_np(task, sizeof(cpuset), &cpuset);
 }
 
-static uint32_t parse_pcpu(const char *cpu_str, const cpu_set_t *allowed_mask)
+static u32 parse_pcpu(const char *cpu_str, const cpu_set_t *allowed_mask)
 {
-	uint32_t pcpu = atoi_non_negative("CPU number", cpu_str);
+	u32 pcpu = atoi_non_negative("CPU number", cpu_str);
 
 	TEST_ASSERT(CPU_ISSET(pcpu, allowed_mask),
 		    "Not allowed to run on pCPU '%d', check cgroups?", pcpu);
@@ -662,7 +662,7 @@ void kvm_print_vcpu_pinning_help(void)
 	       "     (default: no pinning)\n", name, name);
 }
 
-void kvm_parse_vcpu_pinning(const char *pcpus_string, uint32_t vcpu_to_pcpu[],
+void kvm_parse_vcpu_pinning(const char *pcpus_string, u32 vcpu_to_pcpu[],
 			    int nr_vcpus)
 {
 	cpu_set_t allowed_mask;
@@ -715,15 +715,15 @@ void kvm_parse_vcpu_pinning(const char *pcpus_string, uint32_t vcpu_to_pcpu[],
  * region exists.
  */
 static struct userspace_mem_region *
-userspace_mem_region_find(struct kvm_vm *vm, uint64_t start, uint64_t end)
+userspace_mem_region_find(struct kvm_vm *vm, u64 start, u64 end)
 {
 	struct rb_node *node;
 
 	for (node = vm->regions.gpa_tree.rb_node; node; ) {
 		struct userspace_mem_region *region =
 			container_of(node, struct userspace_mem_region, gpa_node);
-		uint64_t existing_start = region->region.guest_phys_addr;
-		uint64_t existing_end = region->region.guest_phys_addr
+		u64 existing_start = region->region.guest_phys_addr;
+		u64 existing_end = region->region.guest_phys_addr
 			+ region->region.memory_size - 1;
 		if (start <= existing_end && end >= existing_start)
 			return region;
@@ -918,8 +918,8 @@ static void vm_userspace_mem_region_hva_insert(struct rb_root *hva_tree,
 }
 
 
-int __vm_set_user_memory_region(struct kvm_vm *vm, uint32_t slot, uint32_t flags,
-				uint64_t gpa, uint64_t size, void *hva)
+int __vm_set_user_memory_region(struct kvm_vm *vm, u32 slot, u32 flags,
+				gpa_t gpa, u64 size, void *hva)
 {
 	struct kvm_userspace_memory_region region = {
 		.slot = slot,
@@ -932,8 +932,8 @@ int __vm_set_user_memory_region(struct kvm_vm *vm, uint32_t slot, uint32_t flags
 	return ioctl(vm->fd, KVM_SET_USER_MEMORY_REGION, &region);
 }
 
-void vm_set_user_memory_region(struct kvm_vm *vm, uint32_t slot, uint32_t flags,
-			       uint64_t gpa, uint64_t size, void *hva)
+void vm_set_user_memory_region(struct kvm_vm *vm, u32 slot, u32 flags,
+			       gpa_t gpa, u64 size, void *hva)
 {
 	int ret = __vm_set_user_memory_region(vm, slot, flags, gpa, size, hva);
 
@@ -945,9 +945,9 @@ void vm_set_user_memory_region(struct kvm_vm *vm, uint32_t slot, uint32_t flags,
 	__TEST_REQUIRE(kvm_has_cap(KVM_CAP_USER_MEMORY2),	\
 		       "KVM selftests now require KVM_SET_USER_MEMORY_REGION2 (introduced in v6.8)")
 
-int __vm_set_user_memory_region2(struct kvm_vm *vm, uint32_t slot, uint32_t flags,
-				 uint64_t gpa, uint64_t size, void *hva,
-				 uint32_t guest_memfd, uint64_t guest_memfd_offset)
+int __vm_set_user_memory_region2(struct kvm_vm *vm, u32 slot, u32 flags,
+				 gpa_t gpa, u64 size, void *hva,
+				 u32 guest_memfd, u64 guest_memfd_offset)
 {
 	struct kvm_userspace_memory_region2 region = {
 		.slot = slot,
@@ -964,9 +964,9 @@ int __vm_set_user_memory_region2(struct kvm_vm *vm, uint32_t slot, uint32_t flag
 	return ioctl(vm->fd, KVM_SET_USER_MEMORY_REGION2, &region);
 }
 
-void vm_set_user_memory_region2(struct kvm_vm *vm, uint32_t slot, uint32_t flags,
-				uint64_t gpa, uint64_t size, void *hva,
-				uint32_t guest_memfd, uint64_t guest_memfd_offset)
+void vm_set_user_memory_region2(struct kvm_vm *vm, u32 slot, u32 flags,
+				gpa_t gpa, u64 size, void *hva,
+				u32 guest_memfd, u64 guest_memfd_offset)
 {
 	int ret = __vm_set_user_memory_region2(vm, slot, flags, gpa, size, hva,
 					       guest_memfd, guest_memfd_offset);
@@ -978,8 +978,8 @@ void vm_set_user_memory_region2(struct kvm_vm *vm, uint32_t slot, uint32_t flags
 
 /* FIXME: This thing needs to be ripped apart and rewritten. */
 void vm_mem_add(struct kvm_vm *vm, enum vm_mem_backing_src_type src_type,
-		uint64_t gpa, uint32_t slot, uint64_t npages, uint32_t flags,
-		int guest_memfd, uint64_t guest_memfd_offset)
+		gpa_t gpa, u32 slot, u64 npages, u32 flags,
+		int guest_memfd, u64 guest_memfd_offset)
 {
 	int ret;
 	struct userspace_mem_region *region;
@@ -1016,8 +1016,8 @@ void vm_mem_add(struct kvm_vm *vm, enum vm_mem_backing_src_type src_type,
 			"  requested gpa: 0x%lx npages: 0x%lx page_size: 0x%x\n"
 			"  existing gpa: 0x%lx size: 0x%lx",
 			gpa, npages, vm->page_size,
-			(uint64_t) region->region.guest_phys_addr,
-			(uint64_t) region->region.memory_size);
+			(u64)region->region.guest_phys_addr,
+			(u64)region->region.memory_size);
 
 	/* Confirm no region with the requested slot already exists. */
 	hash_for_each_possible(vm->regions.slot_hash, region, slot_node,
@@ -1027,11 +1027,11 @@ void vm_mem_add(struct kvm_vm *vm, enum vm_mem_backing_src_type src_type,
 
 		TEST_FAIL("A mem region with the requested slot "
 			"already exists.\n"
-			"  requested slot: %u paddr: 0x%lx npages: 0x%lx\n"
-			"  existing slot: %u paddr: 0x%lx size: 0x%lx",
+			"  requested slot: %u gpa: 0x%lx npages: 0x%lx\n"
+			"  existing slot: %u gpa: 0x%lx size: 0x%lx",
 			slot, gpa, npages, region->region.slot,
-			(uint64_t) region->region.guest_phys_addr,
-			(uint64_t) region->region.memory_size);
+			(u64)region->region.guest_phys_addr,
+			(u64)region->region.memory_size);
 	}
 
 	/* Allocate and initialize new mem region structure. */
@@ -1085,7 +1085,7 @@ void vm_mem_add(struct kvm_vm *vm, enum vm_mem_backing_src_type src_type,
 
 	if (flags & KVM_MEM_GUEST_MEMFD) {
 		if (guest_memfd < 0) {
-			uint32_t guest_memfd_flags = 0;
+			u32 guest_memfd_flags = 0;
 			TEST_ASSERT(!guest_memfd_offset,
 				    "Offset must be zero when creating new guest_memfd");
 			guest_memfd = vm_create_guest_memfd(vm, mem_size, guest_memfd_flags);
@@ -1141,8 +1141,7 @@ void vm_mem_add(struct kvm_vm *vm, enum vm_mem_backing_src_type src_type,
 
 void vm_userspace_mem_region_add(struct kvm_vm *vm,
 				 enum vm_mem_backing_src_type src_type,
-				 uint64_t gpa, uint32_t slot, uint64_t npages,
-				 uint32_t flags)
+				 gpa_t gpa, u32 slot, u64 npages, u32 flags)
 {
 	vm_mem_add(vm, src_type, gpa, slot, npages, flags, -1, 0);
 }
@@ -1163,7 +1162,7 @@ void vm_userspace_mem_region_add(struct kvm_vm *vm,
  *   memory slot ID).
  */
 struct userspace_mem_region *
-memslot2region(struct kvm_vm *vm, uint32_t memslot)
+memslot2region(struct kvm_vm *vm, u32 memslot)
 {
 	struct userspace_mem_region *region;
 
@@ -1194,7 +1193,7 @@ memslot2region(struct kvm_vm *vm, uint32_t memslot)
  * Sets the flags of the memory region specified by the value of slot,
  * to the values given by flags.
  */
-void vm_mem_region_set_flags(struct kvm_vm *vm, uint32_t slot, uint32_t flags)
+void vm_mem_region_set_flags(struct kvm_vm *vm, u32 slot, u32 flags)
 {
 	int ret;
 	struct userspace_mem_region *region;
@@ -1210,7 +1209,7 @@ void vm_mem_region_set_flags(struct kvm_vm *vm, uint32_t slot, uint32_t flags)
 		ret, errno, slot, flags);
 }
 
-void vm_mem_region_reload(struct kvm_vm *vm, uint32_t slot)
+void vm_mem_region_reload(struct kvm_vm *vm, u32 slot)
 {
 	struct userspace_mem_region *region = memslot2region(vm, slot);
 	struct kvm_userspace_memory_region2 tmp = region->region;
@@ -1234,7 +1233,7 @@ void vm_mem_region_reload(struct kvm_vm *vm, uint32_t slot)
  *
  * Change the gpa of a memory region.
  */
-void vm_mem_region_move(struct kvm_vm *vm, uint32_t slot, uint64_t new_gpa)
+void vm_mem_region_move(struct kvm_vm *vm, u32 slot, u64 new_gpa)
 {
 	struct userspace_mem_region *region;
 	int ret;
@@ -1263,7 +1262,7 @@ void vm_mem_region_move(struct kvm_vm *vm, uint32_t slot, uint64_t new_gpa)
  *
  * Delete a memory region.
  */
-void vm_mem_region_delete(struct kvm_vm *vm, uint32_t slot)
+void vm_mem_region_delete(struct kvm_vm *vm, u32 slot)
 {
 	struct userspace_mem_region *region = memslot2region(vm, slot);
 
@@ -1273,18 +1272,18 @@ void vm_mem_region_delete(struct kvm_vm *vm, uint32_t slot)
 	__vm_mem_region_delete(vm, region);
 }
 
-void vm_guest_mem_fallocate(struct kvm_vm *vm, uint64_t base, uint64_t size,
+void vm_guest_mem_fallocate(struct kvm_vm *vm, u64 base, u64 size,
 			    bool punch_hole)
 {
 	const int mode = FALLOC_FL_KEEP_SIZE | (punch_hole ? FALLOC_FL_PUNCH_HOLE : 0);
 	struct userspace_mem_region *region;
-	uint64_t end = base + size;
-	uint64_t gpa, len;
+	u64 end = base + size;
+	gpa_t gpa, len;
 	off_t fd_offset;
 	int ret;
 
 	for (gpa = base; gpa < end; gpa += len) {
-		uint64_t offset;
+		u64 offset;
 
 		region = userspace_mem_region_find(vm, gpa, gpa);
 		TEST_ASSERT(region && region->region.flags & KVM_MEM_GUEST_MEMFD,
@@ -1292,7 +1291,7 @@ void vm_guest_mem_fallocate(struct kvm_vm *vm, uint64_t base, uint64_t size,
 
 		offset = gpa - region->region.guest_phys_addr;
 		fd_offset = region->region.guest_memfd_offset + offset;
-		len = min_t(uint64_t, end - gpa, region->region.memory_size - offset);
+		len = min_t(u64, end - gpa, region->region.memory_size - offset);
 
 		ret = fallocate(region->region.guest_memfd, mode, fd_offset, len);
 		TEST_ASSERT(!ret, "fallocate() failed to %s at %lx (len = %lu), fd = %d, mode = %x, offset = %lx",
@@ -1317,7 +1316,7 @@ static size_t vcpu_mmap_sz(void)
 	return ret;
 }
 
-static bool vcpu_exists(struct kvm_vm *vm, uint32_t vcpu_id)
+static bool vcpu_exists(struct kvm_vm *vm, u32 vcpu_id)
 {
 	struct kvm_vcpu *vcpu;
 
@@ -1333,7 +1332,7 @@ static bool vcpu_exists(struct kvm_vm *vm, uint32_t vcpu_id)
  * Adds a virtual CPU to the VM specified by vm with the ID given by vcpu_id.
  * No additional vCPU setup is done.  Returns the vCPU.
  */
-struct kvm_vcpu *__vm_vcpu_add(struct kvm_vm *vm, uint32_t vcpu_id)
+struct kvm_vcpu *__vm_vcpu_add(struct kvm_vm *vm, u32 vcpu_id)
 {
 	struct kvm_vcpu *vcpu;
 
@@ -1367,33 +1366,18 @@ struct kvm_vcpu *__vm_vcpu_add(struct kvm_vm *vm, uint32_t vcpu_id)
 }
 
 /*
- * VM Virtual Address Unused Gap
- *
- * Input Args:
- *   vm - Virtual Machine
- *   sz - Size (bytes)
- *   vaddr_min - Minimum Virtual Address
- *
- * Output Args: None
- *
- * Return:
- *   Lowest virtual address at or above vaddr_min, with at least
- *   sz unused bytes.  TEST_ASSERT failure if no area of at least
- *   size sz is available.
- *
- * Within the VM specified by vm, locates the lowest starting virtual
- * address >= vaddr_min, that has at least sz unallocated bytes.  A
+ * Within the VM specified by @vm, locates the lowest starting guest virtual
+ * address >= @min_gva, that has at least @sz unallocated bytes.  A
  * TEST_ASSERT failure occurs for invalid input or no area of at least
- * sz unallocated bytes >= vaddr_min is available.
+ * @sz unallocated bytes >= @min_gva is available.
  */
-vm_vaddr_t vm_vaddr_unused_gap(struct kvm_vm *vm, size_t sz,
-			       vm_vaddr_t vaddr_min)
+gva_t vm_unused_gva_gap(struct kvm_vm *vm, size_t sz, gva_t min_gva)
 {
-	uint64_t pages = (sz + vm->page_size - 1) >> vm->page_shift;
+	u64 pages = (sz + vm->page_size - 1) >> vm->page_shift;
 
 	/* Determine lowest permitted virtual page index. */
-	uint64_t pgidx_start = (vaddr_min + vm->page_size - 1) >> vm->page_shift;
-	if ((pgidx_start * vm->page_size) < vaddr_min)
+	u64 pgidx_start = (min_gva + vm->page_size - 1) >> vm->page_shift;
+	if ((pgidx_start * vm->page_size) < min_gva)
 		goto no_va_found;
 
 	/* Loop over section with enough valid virtual page indexes. */
@@ -1430,7 +1414,7 @@ vm_vaddr_t vm_vaddr_unused_gap(struct kvm_vm *vm, size_t sz,
 	} while (pgidx_start != 0);
 
 no_va_found:
-	TEST_FAIL("No vaddr of specified pages available, pages: 0x%lx", pages);
+	TEST_FAIL("No gva of specified pages available, pages: 0x%lx", pages);
 
 	/* NOT REACHED */
 	return -1;
@@ -1452,145 +1436,91 @@ vm_vaddr_t vm_vaddr_unused_gap(struct kvm_vm *vm, size_t sz,
 	return pgidx_start * vm->page_size;
 }
 
-static vm_vaddr_t ____vm_vaddr_alloc(struct kvm_vm *vm, size_t sz,
-				     vm_vaddr_t vaddr_min,
-				     enum kvm_mem_region_type type,
-				     bool protected)
+static gva_t ____vm_alloc(struct kvm_vm *vm, size_t sz, gva_t min_gva,
+			  enum kvm_mem_region_type type, bool protected)
 {
-	uint64_t pages = (sz >> vm->page_shift) + ((sz % vm->page_size) != 0);
+	u64 pages = (sz >> vm->page_shift) + ((sz % vm->page_size) != 0);
 
 	virt_pgd_alloc(vm);
-	vm_paddr_t paddr = __vm_phy_pages_alloc(vm, pages,
-						KVM_UTIL_MIN_PFN * vm->page_size,
-						vm->memslots[type], protected);
+	gpa_t gpa = __vm_phy_pages_alloc(vm, pages,
+					   KVM_UTIL_MIN_PFN * vm->page_size,
+					   vm->memslots[type], protected);
 
 	/*
 	 * Find an unused range of virtual page addresses of at least
 	 * pages in length.
 	 */
-	vm_vaddr_t vaddr_start = vm_vaddr_unused_gap(vm, sz, vaddr_min);
+	gva_t gva_start = vm_unused_gva_gap(vm, sz, min_gva);
 
 	/* Map the virtual pages. */
-	for (vm_vaddr_t vaddr = vaddr_start; pages > 0;
-		pages--, vaddr += vm->page_size, paddr += vm->page_size) {
+	for (gva_t gva = gva_start; pages > 0;
+		pages--, gva += vm->page_size, gpa += vm->page_size) {
 
-		virt_pg_map(vm, vaddr, paddr);
+		virt_pg_map(vm, gva, gpa);
 	}
 
-	return vaddr_start;
+	return gva_start;
 }
 
-vm_vaddr_t __vm_vaddr_alloc(struct kvm_vm *vm, size_t sz, vm_vaddr_t vaddr_min,
-			    enum kvm_mem_region_type type)
+gva_t __vm_alloc(struct kvm_vm *vm, size_t sz, gva_t min_gva,
+		 enum kvm_mem_region_type type)
 {
-	return ____vm_vaddr_alloc(vm, sz, vaddr_min, type,
-				  vm_arch_has_protected_memory(vm));
+	return ____vm_alloc(vm, sz, min_gva, type,
+			    vm_arch_has_protected_memory(vm));
 }
 
-vm_vaddr_t vm_vaddr_alloc_shared(struct kvm_vm *vm, size_t sz,
-				 vm_vaddr_t vaddr_min,
-				 enum kvm_mem_region_type type)
+gva_t vm_alloc_shared(struct kvm_vm *vm, size_t sz, gva_t min_gva,
+		      enum kvm_mem_region_type type)
 {
-	return ____vm_vaddr_alloc(vm, sz, vaddr_min, type, false);
+	return ____vm_alloc(vm, sz, min_gva, type, false);
 }
 
 /*
- * VM Virtual Address Allocate
- *
- * Input Args:
- *   vm - Virtual Machine
- *   sz - Size in bytes
- *   vaddr_min - Minimum starting virtual address
- *
- * Output Args: None
- *
- * Return:
- *   Starting guest virtual address
- *
- * Allocates at least sz bytes within the virtual address space of the vm
- * given by vm.  The allocated bytes are mapped to a virtual address >=
- * the address given by vaddr_min.  Note that each allocation uses a
- * a unique set of pages, with the minimum real allocation being at least
- * a page. The allocated physical space comes from the TEST_DATA memory region.
+ * Allocates at least sz bytes within the virtual address space of the VM
+ * given by @vm.  The allocated bytes are mapped to a virtual address >= the
+ * address given by @min_gva.  Note that each allocation uses a a unique set
+ * of pages, with the minimum real allocation being at least a page. The
+ * allocated physical space comes from the TEST_DATA memory region.
  */
-vm_vaddr_t vm_vaddr_alloc(struct kvm_vm *vm, size_t sz, vm_vaddr_t vaddr_min)
+gva_t vm_alloc(struct kvm_vm *vm, size_t sz, gva_t min_gva)
 {
-	return __vm_vaddr_alloc(vm, sz, vaddr_min, MEM_REGION_TEST_DATA);
+	return __vm_alloc(vm, sz, min_gva, MEM_REGION_TEST_DATA);
 }
 
-/*
- * VM Virtual Address Allocate Pages
- *
- * Input Args:
- *   vm - Virtual Machine
- *
- * Output Args: None
- *
- * Return:
- *   Starting guest virtual address
- *
- * Allocates at least N system pages worth of bytes within the virtual address
- * space of the vm.
- */
-vm_vaddr_t vm_vaddr_alloc_pages(struct kvm_vm *vm, int nr_pages)
+gva_t vm_alloc_pages(struct kvm_vm *vm, int nr_pages)
 {
-	return vm_vaddr_alloc(vm, nr_pages * getpagesize(), KVM_UTIL_MIN_VADDR);
+	return vm_alloc(vm, nr_pages * getpagesize(), KVM_UTIL_MIN_VADDR);
 }
 
-vm_vaddr_t __vm_vaddr_alloc_page(struct kvm_vm *vm, enum kvm_mem_region_type type)
+gva_t __vm_alloc_page(struct kvm_vm *vm, enum kvm_mem_region_type type)
 {
-	return __vm_vaddr_alloc(vm, getpagesize(), KVM_UTIL_MIN_VADDR, type);
+	return __vm_alloc(vm, getpagesize(), KVM_UTIL_MIN_VADDR, type);
 }
 
-/*
- * VM Virtual Address Allocate Page
- *
- * Input Args:
- *   vm - Virtual Machine
- *
- * Output Args: None
- *
- * Return:
- *   Starting guest virtual address
- *
- * Allocates at least one system page worth of bytes within the virtual address
- * space of the vm.
- */
-vm_vaddr_t vm_vaddr_alloc_page(struct kvm_vm *vm)
+gva_t vm_alloc_page(struct kvm_vm *vm)
 {
-	return vm_vaddr_alloc_pages(vm, 1);
+	return vm_alloc_pages(vm, 1);
 }
 
 /*
- * Map a range of VM virtual address to the VM's physical address
- *
- * Input Args:
- *   vm - Virtual Machine
- *   vaddr - Virtuall address to map
- *   paddr - VM Physical Address
- *   npages - The number of pages to map
+ * Map a range of VM virtual address to the VM's physical address.
  *
- * Output Args: None
- *
- * Return: None
- *
- * Within the VM given by @vm, creates a virtual translation for
- * @npages starting at @vaddr to the page range starting at @paddr.
+ * Within the VM given by @vm, creates a virtual translation for @npages
+ * starting at @gva to the page range starting at @gpa.
  */
-void virt_map(struct kvm_vm *vm, uint64_t vaddr, uint64_t paddr,
-	      unsigned int npages)
+void virt_map(struct kvm_vm *vm, gva_t gva, gpa_t gpa, unsigned int npages)
 {
 	size_t page_size = vm->page_size;
 	size_t size = npages * page_size;
 
-	TEST_ASSERT(vaddr + size > vaddr, "Vaddr overflow");
-	TEST_ASSERT(paddr + size > paddr, "Paddr overflow");
+	TEST_ASSERT(gva + size > gva, "Vaddr overflow");
+	TEST_ASSERT(gpa + size > gpa, "Paddr overflow");
 
 	while (npages--) {
-		virt_pg_map(vm, vaddr, paddr);
+		virt_pg_map(vm, gva, gpa);
 
-		vaddr += page_size;
-		paddr += page_size;
+		gva += page_size;
+		gpa += page_size;
 	}
 }
 
@@ -1611,7 +1541,7 @@ void virt_map(struct kvm_vm *vm, uint64_t vaddr, uint64_t paddr,
  * address providing the memory to the vm physical address is returned.
  * A TEST_ASSERT failure occurs if no region containing gpa exists.
  */
-void *addr_gpa2hva(struct kvm_vm *vm, vm_paddr_t gpa)
+void *addr_gpa2hva(struct kvm_vm *vm, gpa_t gpa)
 {
 	struct userspace_mem_region *region;
 
@@ -1644,7 +1574,7 @@ void *addr_gpa2hva(struct kvm_vm *vm, vm_paddr_t gpa)
  * VM physical address is returned. A TEST_ASSERT failure occurs if no
  * region containing hva exists.
  */
-vm_paddr_t addr_hva2gpa(struct kvm_vm *vm, void *hva)
+gpa_t addr_hva2gpa(struct kvm_vm *vm, void *hva)
 {
 	struct rb_node *node;
 
@@ -1655,7 +1585,7 @@ vm_paddr_t addr_hva2gpa(struct kvm_vm *vm, void *hva)
 		if (hva >= region->host_mem) {
 			if (hva <= (region->host_mem
 				+ region->region.memory_size - 1))
-				return (vm_paddr_t)((uintptr_t)
+				return (gpa_t)((uintptr_t)
 					region->region.guest_phys_addr
 					+ (hva - (uintptr_t)region->host_mem));
 
@@ -1687,7 +1617,7 @@ vm_paddr_t addr_hva2gpa(struct kvm_vm *vm, void *hva)
  * memory without mapping said memory in the guest's address space. And, for
  * userfaultfd-based demand paging, to do so without triggering userfaults.
  */
-void *addr_gpa2alias(struct kvm_vm *vm, vm_paddr_t gpa)
+void *addr_gpa2alias(struct kvm_vm *vm, gpa_t gpa)
 {
 	struct userspace_mem_region *region;
 	uintptr_t offset;
@@ -1781,8 +1711,8 @@ struct kvm_reg_list *vcpu_get_reg_list(struct kvm_vcpu *vcpu)
 
 void *vcpu_map_dirty_ring(struct kvm_vcpu *vcpu)
 {
-	uint32_t page_size = getpagesize();
-	uint32_t size = vcpu->vm->dirty_ring_size;
+	u32 page_size = getpagesize();
+	u32 size = vcpu->vm->dirty_ring_size;
 
 	TEST_ASSERT(size > 0, "Should enable dirty ring first");
 
@@ -1811,7 +1741,7 @@ void *vcpu_map_dirty_ring(struct kvm_vcpu *vcpu)
  * Device Ioctl
  */
 
-int __kvm_has_device_attr(int dev_fd, uint32_t group, uint64_t attr)
+int __kvm_has_device_attr(int dev_fd, u32 group, u64 attr)
 {
 	struct kvm_device_attr attribute = {
 		.group = group,
@@ -1822,7 +1752,7 @@ int __kvm_has_device_attr(int dev_fd, uint32_t group, uint64_t attr)
 	return ioctl(dev_fd, KVM_HAS_DEVICE_ATTR, &attribute);
 }
 
-int __kvm_test_create_device(struct kvm_vm *vm, uint64_t type)
+int __kvm_test_create_device(struct kvm_vm *vm, u64 type)
 {
 	struct kvm_create_device create_dev = {
 		.type = type,
@@ -1832,7 +1762,7 @@ int __kvm_test_create_device(struct kvm_vm *vm, uint64_t type)
 	return __vm_ioctl(vm, KVM_CREATE_DEVICE, &create_dev);
 }
 
-int __kvm_create_device(struct kvm_vm *vm, uint64_t type)
+int __kvm_create_device(struct kvm_vm *vm, u64 type)
 {
 	struct kvm_create_device create_dev = {
 		.type = type,
@@ -1846,7 +1776,7 @@ int __kvm_create_device(struct kvm_vm *vm, uint64_t type)
 	return err ? : create_dev.fd;
 }
 
-int __kvm_device_attr_get(int dev_fd, uint32_t group, uint64_t attr, void *val)
+int __kvm_device_attr_get(int dev_fd, u32 group, u64 attr, void *val)
 {
 	struct kvm_device_attr kvmattr = {
 		.group = group,
@@ -1858,7 +1788,7 @@ int __kvm_device_attr_get(int dev_fd, uint32_t group, uint64_t attr, void *val)
 	return __kvm_ioctl(dev_fd, KVM_GET_DEVICE_ATTR, &kvmattr);
 }
 
-int __kvm_device_attr_set(int dev_fd, uint32_t group, uint64_t attr, void *val)
+int __kvm_device_attr_set(int dev_fd, u32 group, u64 attr, void *val)
 {
 	struct kvm_device_attr kvmattr = {
 		.group = group,
@@ -1874,7 +1804,7 @@ int __kvm_device_attr_set(int dev_fd, uint32_t group, uint64_t attr, void *val)
  * IRQ related functions.
  */
 
-int _kvm_irq_line(struct kvm_vm *vm, uint32_t irq, int level)
+int _kvm_irq_line(struct kvm_vm *vm, u32 irq, int level)
 {
 	struct kvm_irq_level irq_level = {
 		.irq    = irq,
@@ -1884,7 +1814,7 @@ int _kvm_irq_line(struct kvm_vm *vm, uint32_t irq, int level)
 	return __vm_ioctl(vm, KVM_IRQ_LINE, &irq_level);
 }
 
-void kvm_irq_line(struct kvm_vm *vm, uint32_t irq, int level)
+void kvm_irq_line(struct kvm_vm *vm, u32 irq, int level)
 {
 	int ret = _kvm_irq_line(vm, irq, level);
 
@@ -1906,7 +1836,7 @@ struct kvm_irq_routing *kvm_gsi_routing_create(void)
 }
 
 void kvm_gsi_routing_irqchip_add(struct kvm_irq_routing *routing,
-		uint32_t gsi, uint32_t pin)
+		u32 gsi, u32 pin)
 {
 	int i;
 
@@ -1956,7 +1886,7 @@ void kvm_gsi_routing_write(struct kvm_vm *vm, struct kvm_irq_routing *routing)
  * Dumps the current state of the VM given by vm, to the FILE stream
  * given by stream.
  */
-void vm_dump(FILE *stream, struct kvm_vm *vm, uint8_t indent)
+void vm_dump(FILE *stream, struct kvm_vm *vm, u8 indent)
 {
 	int ctr;
 	struct userspace_mem_region *region;
@@ -1969,8 +1899,8 @@ void vm_dump(FILE *stream, struct kvm_vm *vm, uint8_t indent)
 	hash_for_each(vm->regions.slot_hash, ctr, region, slot_node) {
 		fprintf(stream, "%*sguest_phys: 0x%lx size: 0x%lx "
 			"host_virt: %p\n", indent + 2, "",
-			(uint64_t) region->region.guest_phys_addr,
-			(uint64_t) region->region.memory_size,
+			(u64)region->region.guest_phys_addr,
+			(u64)region->region.memory_size,
 			region->host_mem);
 		fprintf(stream, "%*sunused_phy_pages: ", indent + 2, "");
 		sparsebit_dump(stream, region->unused_phy_pages, 0);
@@ -2077,7 +2007,7 @@ const char *exit_reason_str(unsigned int exit_reason)
  * Input Args:
  *   vm - Virtual Machine
  *   num - number of pages
- *   paddr_min - Physical address minimum
+ *   min_gpa - Physical address minimum
  *   memslot - Memory region to allocate page from
  *   protected - True if the pages will be used as protected/private memory
  *
@@ -2087,29 +2017,29 @@ const char *exit_reason_str(unsigned int exit_reason)
  *   Starting physical address
  *
  * Within the VM specified by vm, locates a range of available physical
- * pages at or above paddr_min. If found, the pages are marked as in use
+ * pages at or above min_gpa. If found, the pages are marked as in use
  * and their base address is returned. A TEST_ASSERT failure occurs if
- * not enough pages are available at or above paddr_min.
+ * not enough pages are available at or above min_gpa.
  */
-vm_paddr_t __vm_phy_pages_alloc(struct kvm_vm *vm, size_t num,
-				vm_paddr_t paddr_min, uint32_t memslot,
-				bool protected)
+gpa_t __vm_phy_pages_alloc(struct kvm_vm *vm, size_t num,
+			   gpa_t min_gpa, u32 memslot,
+			   bool protected)
 {
 	struct userspace_mem_region *region;
 	sparsebit_idx_t pg, base;
 
 	TEST_ASSERT(num > 0, "Must allocate at least one page");
 
-	TEST_ASSERT((paddr_min % vm->page_size) == 0, "Min physical address "
+	TEST_ASSERT((min_gpa % vm->page_size) == 0, "Min physical address "
 		"not divisible by page size.\n"
-		"  paddr_min: 0x%lx page_size: 0x%x",
-		paddr_min, vm->page_size);
+		"  min_gpa: 0x%lx page_size: 0x%x",
+		min_gpa, vm->page_size);
 
 	region = memslot2region(vm, memslot);
 	TEST_ASSERT(!protected || region->protected_phy_pages,
 		    "Region doesn't support protected memory");
 
-	base = pg = paddr_min >> vm->page_shift;
+	base = pg = min_gpa >> vm->page_shift;
 	do {
 		for (; pg < base + num; ++pg) {
 			if (!sparsebit_is_set(region->unused_phy_pages, pg)) {
@@ -2121,8 +2051,8 @@ vm_paddr_t __vm_phy_pages_alloc(struct kvm_vm *vm, size_t num,
 
 	if (pg == 0) {
 		fprintf(stderr, "No guest physical page available, "
-			"paddr_min: 0x%lx page_size: 0x%x memslot: %u\n",
-			paddr_min, vm->page_size, memslot);
+			"min_gpa: 0x%lx page_size: 0x%x memslot: %u\n",
+			min_gpa, vm->page_size, memslot);
 		fputs("---- vm dump ----\n", stderr);
 		vm_dump(stderr, vm, 2);
 		abort();
@@ -2137,13 +2067,12 @@ vm_paddr_t __vm_phy_pages_alloc(struct kvm_vm *vm, size_t num,
 	return base * vm->page_size;
 }
 
-vm_paddr_t vm_phy_page_alloc(struct kvm_vm *vm, vm_paddr_t paddr_min,
-			     uint32_t memslot)
+gpa_t vm_phy_page_alloc(struct kvm_vm *vm, gpa_t min_gpa, u32 memslot)
 {
-	return vm_phy_pages_alloc(vm, 1, paddr_min, memslot);
+	return vm_phy_pages_alloc(vm, 1, min_gpa, memslot);
 }
 
-vm_paddr_t vm_alloc_page_table(struct kvm_vm *vm)
+gpa_t vm_alloc_page_table(struct kvm_vm *vm)
 {
 	return vm_phy_page_alloc(vm, KVM_GUEST_PAGE_TABLE_MIN_PADDR,
 				 vm->memslots[MEM_REGION_PT]);
@@ -2161,7 +2090,7 @@ vm_paddr_t vm_alloc_page_table(struct kvm_vm *vm)
  * Return:
  *   Equivalent host virtual address
  */
-void *addr_gva2hva(struct kvm_vm *vm, vm_vaddr_t gva)
+void *addr_gva2hva(struct kvm_vm *vm, gva_t gva)
 {
 	return addr_gpa2hva(vm, addr_gva2gpa(vm, gva));
 }
@@ -2259,7 +2188,7 @@ struct kvm_stats_desc *read_stats_descriptors(int stats_fd,
  * Read the data values of a specified stat from the binary stats interface.
  */
 void read_stat_data(int stats_fd, struct kvm_stats_header *header,
-		    struct kvm_stats_desc *desc, uint64_t *data,
+		    struct kvm_stats_desc *desc, u64 *data,
 		    size_t max_elements)
 {
 	size_t nr_elements = min_t(ssize_t, desc->size, max_elements);
@@ -2280,7 +2209,7 @@ void read_stat_data(int stats_fd, struct kvm_stats_header *header,
 }
 
 void kvm_get_stat(struct kvm_binary_stats *stats, const char *name,
-		  uint64_t *data, size_t max_elements)
+		  u64 *data, size_t max_elements)
 {
 	struct kvm_stats_desc *desc;
 	size_t size_desc;
@@ -2357,7 +2286,7 @@ void __attribute((constructor)) kvm_selftest_init(void)
 	kvm_selftest_arch_init();
 }
 
-bool vm_is_gpa_protected(struct kvm_vm *vm, vm_paddr_t paddr)
+bool vm_is_gpa_protected(struct kvm_vm *vm, gpa_t gpa)
 {
 	sparsebit_idx_t pg = 0;
 	struct userspace_mem_region *region;
@@ -2365,10 +2294,10 @@ bool vm_is_gpa_protected(struct kvm_vm *vm, vm_paddr_t paddr)
 	if (!vm_arch_has_protected_memory(vm))
 		return false;
 
-	region = userspace_mem_region_find(vm, paddr, paddr);
-	TEST_ASSERT(region, "No vm physical memory at 0x%lx", paddr);
+	region = userspace_mem_region_find(vm, gpa, gpa);
+	TEST_ASSERT(region, "No vm physical memory at 0x%lx", gpa);
 
-	pg = paddr >> vm->page_shift;
+	pg = gpa >> vm->page_shift;
 	return sparsebit_is_set(region->protected_phy_pages, pg);
 }
 
diff --git a/tools/testing/selftests/kvm/lib/loongarch/processor.c b/tools/testing/selftests/kvm/lib/loongarch/processor.c
index ee4ad3b1d2a4..64d91fb76522 100644
--- a/tools/testing/selftests/kvm/lib/loongarch/processor.c
+++ b/tools/testing/selftests/kvm/lib/loongarch/processor.c
@@ -12,32 +12,32 @@
 #define LOONGARCH_PAGE_TABLE_PHYS_MIN		0x200000
 #define LOONGARCH_GUEST_STACK_VADDR_MIN		0x200000
 
-static vm_paddr_t invalid_pgtable[4];
-static vm_vaddr_t exception_handlers;
+static gpa_t invalid_pgtable[4];
+static gva_t exception_handlers;
 
-static uint64_t virt_pte_index(struct kvm_vm *vm, vm_vaddr_t gva, int level)
+static u64 virt_pte_index(struct kvm_vm *vm, gva_t gva, int level)
 {
 	unsigned int shift;
-	uint64_t mask;
+	u64 mask;
 
 	shift = level * (vm->page_shift - 3) + vm->page_shift;
 	mask = (1UL << (vm->page_shift - 3)) - 1;
 	return (gva >> shift) & mask;
 }
 
-static uint64_t pte_addr(struct kvm_vm *vm, uint64_t entry)
+static u64 pte_addr(struct kvm_vm *vm, u64 entry)
 {
 	return entry &  ~((0x1UL << vm->page_shift) - 1);
 }
 
-static uint64_t ptrs_per_pte(struct kvm_vm *vm)
+static u64 ptrs_per_pte(struct kvm_vm *vm)
 {
 	return 1 << (vm->page_shift - 3);
 }
 
-static void virt_set_pgtable(struct kvm_vm *vm, vm_paddr_t table, vm_paddr_t child)
+static void virt_set_pgtable(struct kvm_vm *vm, gpa_t table, gpa_t child)
 {
-	uint64_t *ptep;
+	u64 *ptep;
 	int i, ptrs_per_pte;
 
 	ptep = addr_gpa2hva(vm, table);
@@ -49,7 +49,7 @@ static void virt_set_pgtable(struct kvm_vm *vm, vm_paddr_t table, vm_paddr_t chi
 void virt_arch_pgd_alloc(struct kvm_vm *vm)
 {
 	int i;
-	vm_paddr_t child, table;
+	gpa_t child, table;
 
 	if (vm->mmu.pgd_created)
 		return;
@@ -67,16 +67,16 @@ void virt_arch_pgd_alloc(struct kvm_vm *vm)
 	vm->mmu.pgd_created = true;
 }
 
-static int virt_pte_none(uint64_t *ptep, int level)
+static int virt_pte_none(u64 *ptep, int level)
 {
 	return *ptep == invalid_pgtable[level];
 }
 
-static uint64_t *virt_populate_pte(struct kvm_vm *vm, vm_vaddr_t gva, int alloc)
+static u64 *virt_populate_pte(struct kvm_vm *vm, gva_t gva, int alloc)
 {
 	int level;
-	uint64_t *ptep;
-	vm_paddr_t child;
+	u64 *ptep;
+	gpa_t child;
 
 	if (!vm->mmu.pgd_created)
 		goto unmapped_gva;
@@ -106,43 +106,42 @@ static uint64_t *virt_populate_pte(struct kvm_vm *vm, vm_vaddr_t gva, int alloc)
 	exit(EXIT_FAILURE);
 }
 
-vm_paddr_t addr_arch_gva2gpa(struct kvm_vm *vm, vm_vaddr_t gva)
+gpa_t addr_arch_gva2gpa(struct kvm_vm *vm, gva_t gva)
 {
-	uint64_t *ptep;
+	u64 *ptep;
 
 	ptep = virt_populate_pte(vm, gva, 0);
-	TEST_ASSERT(*ptep != 0, "Virtual address vaddr: 0x%lx not mapped\n", gva);
+	TEST_ASSERT(*ptep != 0, "Virtual address gva: 0x%lx not mapped\n", gva);
 
 	return pte_addr(vm, *ptep) + (gva & (vm->page_size - 1));
 }
 
-void virt_arch_pg_map(struct kvm_vm *vm, uint64_t vaddr, uint64_t paddr)
+void virt_arch_pg_map(struct kvm_vm *vm, gva_t gva, gpa_t gpa)
 {
-	uint32_t prot_bits;
-	uint64_t *ptep;
+	u32 prot_bits;
+	u64 *ptep;
 
-	TEST_ASSERT((vaddr % vm->page_size) == 0,
+	TEST_ASSERT((gva % vm->page_size) == 0,
 			"Virtual address not on page boundary,\n"
-			"vaddr: 0x%lx vm->page_size: 0x%x", vaddr, vm->page_size);
-	TEST_ASSERT(sparsebit_is_set(vm->vpages_valid,
-			(vaddr >> vm->page_shift)),
-			"Invalid virtual address, vaddr: 0x%lx", vaddr);
-	TEST_ASSERT((paddr % vm->page_size) == 0,
+			"gva: 0x%lx vm->page_size: 0x%x", gva, vm->page_size);
+	TEST_ASSERT(sparsebit_is_set(vm->vpages_valid, (gva >> vm->page_shift)),
+			"Invalid virtual address, gva: 0x%lx", gva);
+	TEST_ASSERT((gpa % vm->page_size) == 0,
 			"Physical address not on page boundary,\n"
-			"paddr: 0x%lx vm->page_size: 0x%x", paddr, vm->page_size);
-	TEST_ASSERT((paddr >> vm->page_shift) <= vm->max_gfn,
+			"gpa: 0x%lx vm->page_size: 0x%x", gpa, vm->page_size);
+	TEST_ASSERT((gpa >> vm->page_shift) <= vm->max_gfn,
 			"Physical address beyond maximum supported,\n"
-			"paddr: 0x%lx vm->max_gfn: 0x%lx vm->page_size: 0x%x",
-			paddr, vm->max_gfn, vm->page_size);
+			"gpa: 0x%lx vm->max_gfn: 0x%lx vm->page_size: 0x%x",
+			gpa, vm->max_gfn, vm->page_size);
 
-	ptep = virt_populate_pte(vm, vaddr, 1);
+	ptep = virt_populate_pte(vm, gva, 1);
 	prot_bits = _PAGE_PRESENT | __READABLE | __WRITEABLE | _CACHE_CC | _PAGE_USER;
-	WRITE_ONCE(*ptep, paddr | prot_bits);
+	WRITE_ONCE(*ptep, gpa | prot_bits);
 }
 
-static void pte_dump(FILE *stream, struct kvm_vm *vm, uint8_t indent, uint64_t page, int level)
+static void pte_dump(FILE *stream, struct kvm_vm *vm, u8 indent, u64 page, int level)
 {
-	uint64_t pte, *ptep;
+	u64 pte, *ptep;
 	static const char * const type[] = { "pte", "pmd", "pud", "pgd"};
 
 	if (level < 0)
@@ -158,7 +157,7 @@ static void pte_dump(FILE *stream, struct kvm_vm *vm, uint8_t indent, uint64_t p
 	}
 }
 
-void virt_arch_dump(FILE *stream, struct kvm_vm *vm, uint8_t indent)
+void virt_arch_dump(FILE *stream, struct kvm_vm *vm, u8 indent)
 {
 	int level;
 
@@ -169,7 +168,7 @@ void virt_arch_dump(FILE *stream, struct kvm_vm *vm, uint8_t indent)
 	pte_dump(stream, vm, indent, vm->mmu.pgd, level);
 }
 
-void vcpu_arch_dump(FILE *stream, struct kvm_vcpu *vcpu, uint8_t indent)
+void vcpu_arch_dump(FILE *stream, struct kvm_vcpu *vcpu, u8 indent)
 {
 }
 
@@ -206,8 +205,9 @@ void vm_init_descriptor_tables(struct kvm_vm *vm)
 {
 	void *addr;
 
-	vm->handlers = __vm_vaddr_alloc(vm, sizeof(struct handlers),
-			LOONGARCH_GUEST_STACK_VADDR_MIN, MEM_REGION_DATA);
+	vm->handlers = __vm_alloc(vm, sizeof(struct handlers),
+				  LOONGARCH_GUEST_STACK_VADDR_MIN,
+				  MEM_REGION_DATA);
 
 	addr = addr_gva2hva(vm, vm->handlers);
 	memset(addr, 0, vm->page_size);
@@ -223,7 +223,7 @@ void vm_install_exception_handler(struct kvm_vm *vm, int vector, handler_fn hand
 	handlers->exception_handlers[vector] = handler;
 }
 
-uint32_t guest_get_vcpuid(void)
+u32 guest_get_vcpuid(void)
 {
 	return csr_read(LOONGARCH_CSR_CPUID);
 }
@@ -241,36 +241,36 @@ void vcpu_args_set(struct kvm_vcpu *vcpu, unsigned int num, ...)
 
 	va_start(ap, num);
 	for (i = 0; i < num; i++)
-		regs.gpr[i + 4] = va_arg(ap, uint64_t);
+		regs.gpr[i + 4] = va_arg(ap, u64);
 	va_end(ap);
 
 	vcpu_regs_set(vcpu, &regs);
 }
 
-static void loongarch_set_reg(struct kvm_vcpu *vcpu, uint64_t id, uint64_t val)
+static void loongarch_set_reg(struct kvm_vcpu *vcpu, u64 id, u64 val)
 {
 	__vcpu_set_reg(vcpu, id, val);
 }
 
-static void loongarch_set_cpucfg(struct kvm_vcpu *vcpu, uint64_t id, uint64_t val)
+static void loongarch_set_cpucfg(struct kvm_vcpu *vcpu, u64 id, u64 val)
 {
-	uint64_t cfgid;
+	u64 cfgid;
 
 	cfgid = KVM_REG_LOONGARCH_CPUCFG | KVM_REG_SIZE_U64 | 8 * id;
 	__vcpu_set_reg(vcpu, cfgid, val);
 }
 
-static void loongarch_get_csr(struct kvm_vcpu *vcpu, uint64_t id, void *addr)
+static void loongarch_get_csr(struct kvm_vcpu *vcpu, u64 id, void *addr)
 {
-	uint64_t csrid;
+	u64 csrid;
 
 	csrid = KVM_REG_LOONGARCH_CSR | KVM_REG_SIZE_U64 | 8 * id;
 	__vcpu_get_reg(vcpu, csrid, addr);
 }
 
-static void loongarch_set_csr(struct kvm_vcpu *vcpu, uint64_t id, uint64_t val)
+static void loongarch_set_csr(struct kvm_vcpu *vcpu, u64 id, u64 val)
 {
-	uint64_t csrid;
+	u64 csrid;
 
 	csrid = KVM_REG_LOONGARCH_CSR | KVM_REG_SIZE_U64 | 8 * id;
 	__vcpu_set_reg(vcpu, csrid, val);
@@ -354,8 +354,8 @@ void loongarch_vcpu_setup(struct kvm_vcpu *vcpu)
 	loongarch_set_csr(vcpu, LOONGARCH_CSR_STLBPGSIZE, PS_DEFAULT_SIZE);
 
 	/* LOONGARCH_CSR_KS1 is used for exception stack */
-	val = __vm_vaddr_alloc(vm, vm->page_size,
-			LOONGARCH_GUEST_STACK_VADDR_MIN, MEM_REGION_DATA);
+	val = __vm_alloc(vm, vm->page_size, LOONGARCH_GUEST_STACK_VADDR_MIN,
+			 MEM_REGION_DATA);
 	TEST_ASSERT(val != 0,  "No memory for exception stack");
 	val = val + vm->page_size;
 	loongarch_set_csr(vcpu, LOONGARCH_CSR_KS1, val);
@@ -369,23 +369,23 @@ void loongarch_vcpu_setup(struct kvm_vcpu *vcpu)
 	loongarch_set_csr(vcpu, LOONGARCH_CSR_TMID,  vcpu->id);
 }
 
-struct kvm_vcpu *vm_arch_vcpu_add(struct kvm_vm *vm, uint32_t vcpu_id)
+struct kvm_vcpu *vm_arch_vcpu_add(struct kvm_vm *vm, u32 vcpu_id)
 {
 	size_t stack_size;
-	uint64_t stack_vaddr;
+	u64 stack_gva;
 	struct kvm_regs regs;
 	struct kvm_vcpu *vcpu;
 
 	vcpu = __vm_vcpu_add(vm, vcpu_id);
 	stack_size = vm->page_size;
-	stack_vaddr = __vm_vaddr_alloc(vm, stack_size,
-			LOONGARCH_GUEST_STACK_VADDR_MIN, MEM_REGION_DATA);
-	TEST_ASSERT(stack_vaddr != 0,  "No memory for vm stack");
+	stack_gva = __vm_alloc(vm, stack_size,
+			       LOONGARCH_GUEST_STACK_VADDR_MIN, MEM_REGION_DATA);
+	TEST_ASSERT(stack_gva != 0,  "No memory for vm stack");
 
 	loongarch_vcpu_setup(vcpu);
 	/* Setup guest general purpose registers */
 	vcpu_regs_get(vcpu, &regs);
-	regs.gpr[3] = stack_vaddr + stack_size;
+	regs.gpr[3] = stack_gva + stack_size;
 	vcpu_regs_set(vcpu, &regs);
 
 	return vcpu;
@@ -397,6 +397,6 @@ void vcpu_arch_set_entry_point(struct kvm_vcpu *vcpu, void *guest_code)
 
 	/* Setup guest PC register */
 	vcpu_regs_get(vcpu, &regs);
-	regs.pc = (uint64_t)guest_code;
+	regs.pc = (u64)guest_code;
 	vcpu_regs_set(vcpu, &regs);
 }
diff --git a/tools/testing/selftests/kvm/lib/loongarch/ucall.c b/tools/testing/selftests/kvm/lib/loongarch/ucall.c
index fc6cbb50573f..cd49a3440ead 100644
--- a/tools/testing/selftests/kvm/lib/loongarch/ucall.c
+++ b/tools/testing/selftests/kvm/lib/loongarch/ucall.c
@@ -9,17 +9,17 @@
  * ucall_exit_mmio_addr holds per-VM values (global data is duplicated by each
  * VM), it must not be accessed from host code.
  */
-vm_vaddr_t *ucall_exit_mmio_addr;
+gva_t *ucall_exit_mmio_addr;
 
-void ucall_arch_init(struct kvm_vm *vm, vm_paddr_t mmio_gpa)
+void ucall_arch_init(struct kvm_vm *vm, gpa_t mmio_gpa)
 {
-	vm_vaddr_t mmio_gva = vm_vaddr_unused_gap(vm, vm->page_size, KVM_UTIL_MIN_VADDR);
+	gva_t mmio_gva = vm_unused_gva_gap(vm, vm->page_size, KVM_UTIL_MIN_VADDR);
 
 	virt_map(vm, mmio_gva, mmio_gpa, 1);
 
 	vm->ucall_mmio_addr = mmio_gpa;
 
-	write_guest_global(vm, ucall_exit_mmio_addr, (vm_vaddr_t *)mmio_gva);
+	write_guest_global(vm, ucall_exit_mmio_addr, (gva_t *)mmio_gva);
 }
 
 void *ucall_arch_get_ucall(struct kvm_vcpu *vcpu)
@@ -28,10 +28,10 @@ void *ucall_arch_get_ucall(struct kvm_vcpu *vcpu)
 
 	if (run->exit_reason == KVM_EXIT_MMIO &&
 	    run->mmio.phys_addr == vcpu->vm->ucall_mmio_addr) {
-		TEST_ASSERT(run->mmio.is_write && run->mmio.len == sizeof(uint64_t),
+		TEST_ASSERT(run->mmio.is_write && run->mmio.len == sizeof(u64),
 			    "Unexpected ucall exit mmio address access");
 
-		return (void *)(*((uint64_t *)run->mmio.data));
+		return (void *)(*((u64 *)run->mmio.data));
 	}
 
 	return NULL;
diff --git a/tools/testing/selftests/kvm/lib/memstress.c b/tools/testing/selftests/kvm/lib/memstress.c
index 1ea735d66e15..6dcd15910a06 100644
--- a/tools/testing/selftests/kvm/lib/memstress.c
+++ b/tools/testing/selftests/kvm/lib/memstress.c
@@ -16,7 +16,7 @@ struct memstress_args memstress_args;
  * Guest virtual memory offset of the testing memory slot.
  * Must not conflict with identity mapped test code.
  */
-static uint64_t guest_test_virt_mem = DEFAULT_GUEST_TEST_MEM;
+static u64 guest_test_virt_mem = DEFAULT_GUEST_TEST_MEM;
 
 struct vcpu_thread {
 	/* The index of the vCPU. */
@@ -44,15 +44,15 @@ static struct kvm_vcpu *vcpus[KVM_MAX_VCPUS];
  * Continuously write to the first 8 bytes of each page in the
  * specified region.
  */
-void memstress_guest_code(uint32_t vcpu_idx)
+void memstress_guest_code(u32 vcpu_idx)
 {
 	struct memstress_args *args = &memstress_args;
 	struct memstress_vcpu_args *vcpu_args = &args->vcpu_args[vcpu_idx];
 	struct guest_random_state rand_state;
-	uint64_t gva;
-	uint64_t pages;
-	uint64_t addr;
-	uint64_t page;
+	gva_t gva;
+	u64 pages;
+	u64 addr;
+	u64 page;
 	int i;
 
 	rand_state = new_guest_random_state(guest_random_seed + vcpu_idx);
@@ -76,9 +76,9 @@ void memstress_guest_code(uint32_t vcpu_idx)
 			addr = gva + (page * args->guest_page_size);
 
 			if (__guest_random_bool(&rand_state, args->write_percent))
-				*(uint64_t *)addr = 0x0123456789ABCDEF;
+				*(u64 *)addr = 0x0123456789ABCDEF;
 			else
-				READ_ONCE(*(uint64_t *)addr);
+				READ_ONCE(*(u64 *)addr);
 		}
 
 		GUEST_SYNC(1);
@@ -87,7 +87,7 @@ void memstress_guest_code(uint32_t vcpu_idx)
 
 void memstress_setup_vcpus(struct kvm_vm *vm, int nr_vcpus,
 			   struct kvm_vcpu *vcpus[],
-			   uint64_t vcpu_memory_bytes,
+			   u64 vcpu_memory_bytes,
 			   bool partition_vcpu_memory_access)
 {
 	struct memstress_args *args = &memstress_args;
@@ -122,15 +122,15 @@ void memstress_setup_vcpus(struct kvm_vm *vm, int nr_vcpus,
 }
 
 struct kvm_vm *memstress_create_vm(enum vm_guest_mode mode, int nr_vcpus,
-				   uint64_t vcpu_memory_bytes, int slots,
+				   u64 vcpu_memory_bytes, int slots,
 				   enum vm_mem_backing_src_type backing_src,
 				   bool partition_vcpu_memory_access)
 {
 	struct memstress_args *args = &memstress_args;
 	struct kvm_vm *vm;
-	uint64_t guest_num_pages, slot0_pages = 0;
-	uint64_t backing_src_pagesz = get_backing_src_pagesz(backing_src);
-	uint64_t region_end_gfn;
+	u64 guest_num_pages, slot0_pages = 0;
+	u64 backing_src_pagesz = get_backing_src_pagesz(backing_src);
+	u64 region_end_gfn;
 	int i;
 
 	pr_info("Testing guest mode: %s\n", vm_guest_mode_string(mode));
@@ -202,8 +202,8 @@ struct kvm_vm *memstress_create_vm(enum vm_guest_mode mode, int nr_vcpus,
 
 	/* Add extra memory slots for testing */
 	for (i = 0; i < slots; i++) {
-		uint64_t region_pages = guest_num_pages / slots;
-		vm_paddr_t region_start = args->gpa + region_pages * args->guest_page_size * i;
+		u64 region_pages = guest_num_pages / slots;
+		gpa_t region_start = args->gpa + region_pages * args->guest_page_size * i;
 
 		vm_userspace_mem_region_add(vm, backing_src, region_start,
 					    MEMSTRESS_MEM_SLOT_INDEX + i,
@@ -232,7 +232,7 @@ void memstress_destroy_vm(struct kvm_vm *vm)
 	kvm_vm_free(vm);
 }
 
-void memstress_set_write_percent(struct kvm_vm *vm, uint32_t write_percent)
+void memstress_set_write_percent(struct kvm_vm *vm, u32 write_percent)
 {
 	memstress_args.write_percent = write_percent;
 	sync_global_to_guest(vm, memstress_args.write_percent);
@@ -244,7 +244,7 @@ void memstress_set_random_access(struct kvm_vm *vm, bool random_access)
 	sync_global_to_guest(vm, memstress_args.random_access);
 }
 
-uint64_t __weak memstress_nested_pages(int nr_vcpus)
+u64 __weak memstress_nested_pages(int nr_vcpus)
 {
 	return 0;
 }
@@ -349,7 +349,7 @@ void memstress_get_dirty_log(struct kvm_vm *vm, unsigned long *bitmaps[], int sl
 }
 
 void memstress_clear_dirty_log(struct kvm_vm *vm, unsigned long *bitmaps[],
-			       int slots, uint64_t pages_per_slot)
+			       int slots, u64 pages_per_slot)
 {
 	int i;
 
@@ -360,7 +360,7 @@ void memstress_clear_dirty_log(struct kvm_vm *vm, unsigned long *bitmaps[],
 	}
 }
 
-unsigned long **memstress_alloc_bitmaps(int slots, uint64_t pages_per_slot)
+unsigned long **memstress_alloc_bitmaps(int slots, u64 pages_per_slot)
 {
 	unsigned long **bitmaps;
 	int i;
diff --git a/tools/testing/selftests/kvm/lib/riscv/processor.c b/tools/testing/selftests/kvm/lib/riscv/processor.c
index 067c6b2c15b0..ded5429f3448 100644
--- a/tools/testing/selftests/kvm/lib/riscv/processor.c
+++ b/tools/testing/selftests/kvm/lib/riscv/processor.c
@@ -15,9 +15,9 @@
 
 #define DEFAULT_RISCV_GUEST_STACK_VADDR_MIN	0xac0000
 
-static vm_vaddr_t exception_handlers;
+static gva_t exception_handlers;
 
-bool __vcpu_has_ext(struct kvm_vcpu *vcpu, uint64_t ext)
+bool __vcpu_has_ext(struct kvm_vcpu *vcpu, u64 ext)
 {
 	unsigned long value = 0;
 	int ret;
@@ -27,32 +27,32 @@ bool __vcpu_has_ext(struct kvm_vcpu *vcpu, uint64_t ext)
 	return !ret && !!value;
 }
 
-static uint64_t pte_addr(struct kvm_vm *vm, uint64_t entry)
+static u64 pte_addr(struct kvm_vm *vm, u64 entry)
 {
 	return ((entry & PGTBL_PTE_ADDR_MASK) >> PGTBL_PTE_ADDR_SHIFT) <<
 		PGTBL_PAGE_SIZE_SHIFT;
 }
 
-static uint64_t ptrs_per_pte(struct kvm_vm *vm)
+static u64 ptrs_per_pte(struct kvm_vm *vm)
 {
-	return PGTBL_PAGE_SIZE / sizeof(uint64_t);
+	return PGTBL_PAGE_SIZE / sizeof(u64);
 }
 
-static uint64_t pte_index_mask[] = {
+static u64 pte_index_mask[] = {
 	PGTBL_L0_INDEX_MASK,
 	PGTBL_L1_INDEX_MASK,
 	PGTBL_L2_INDEX_MASK,
 	PGTBL_L3_INDEX_MASK,
 };
 
-static uint32_t pte_index_shift[] = {
+static u32 pte_index_shift[] = {
 	PGTBL_L0_INDEX_SHIFT,
 	PGTBL_L1_INDEX_SHIFT,
 	PGTBL_L2_INDEX_SHIFT,
 	PGTBL_L3_INDEX_SHIFT,
 };
 
-static uint64_t pte_index(struct kvm_vm *vm, vm_vaddr_t gva, int level)
+static u64 pte_index(struct kvm_vm *vm, gva_t gva, int level)
 {
 	TEST_ASSERT(level > -1,
 		"Negative page table level (%d) not possible", level);
@@ -75,26 +75,25 @@ void virt_arch_pgd_alloc(struct kvm_vm *vm)
 	vm->mmu.pgd_created = true;
 }
 
-void virt_arch_pg_map(struct kvm_vm *vm, uint64_t vaddr, uint64_t paddr)
+void virt_arch_pg_map(struct kvm_vm *vm, gva_t gva, gpa_t gpa)
 {
-	uint64_t *ptep, next_ppn;
+	u64 *ptep, next_ppn;
 	int level = vm->mmu.pgtable_levels - 1;
 
-	TEST_ASSERT((vaddr % vm->page_size) == 0,
+	TEST_ASSERT((gva % vm->page_size) == 0,
 		"Virtual address not on page boundary,\n"
-		"  vaddr: 0x%lx vm->page_size: 0x%x", vaddr, vm->page_size);
-	TEST_ASSERT(sparsebit_is_set(vm->vpages_valid,
-		(vaddr >> vm->page_shift)),
-		"Invalid virtual address, vaddr: 0x%lx", vaddr);
-	TEST_ASSERT((paddr % vm->page_size) == 0,
+		"  gva: 0x%lx vm->page_size: 0x%x", gva, vm->page_size);
+	TEST_ASSERT(sparsebit_is_set(vm->vpages_valid, (gva >> vm->page_shift)),
+		    "Invalid virtual address, gva: 0x%lx", gva);
+	TEST_ASSERT((gpa % vm->page_size) == 0,
 		"Physical address not on page boundary,\n"
-		"  paddr: 0x%lx vm->page_size: 0x%x", paddr, vm->page_size);
-	TEST_ASSERT((paddr >> vm->page_shift) <= vm->max_gfn,
+		"  gpa: 0x%lx vm->page_size: 0x%x", gpa, vm->page_size);
+	TEST_ASSERT((gpa >> vm->page_shift) <= vm->max_gfn,
 		"Physical address beyond maximum supported,\n"
-		"  paddr: 0x%lx vm->max_gfn: 0x%lx vm->page_size: 0x%x",
-		paddr, vm->max_gfn, vm->page_size);
+		"  gpa: 0x%lx vm->max_gfn: 0x%lx vm->page_size: 0x%x",
+		gpa, vm->max_gfn, vm->page_size);
 
-	ptep = addr_gpa2hva(vm, vm->mmu.pgd) + pte_index(vm, vaddr, level) * 8;
+	ptep = addr_gpa2hva(vm, vm->mmu.pgd) + pte_index(vm, gva, level) * 8;
 	if (!*ptep) {
 		next_ppn = vm_alloc_page_table(vm) >> PGTBL_PAGE_SIZE_SHIFT;
 		*ptep = (next_ppn << PGTBL_PTE_ADDR_SHIFT) |
@@ -104,7 +103,7 @@ void virt_arch_pg_map(struct kvm_vm *vm, uint64_t vaddr, uint64_t paddr)
 
 	while (level > -1) {
 		ptep = addr_gpa2hva(vm, pte_addr(vm, *ptep)) +
-		       pte_index(vm, vaddr, level) * 8;
+		       pte_index(vm, gva, level) * 8;
 		if (!*ptep && level > 0) {
 			next_ppn = vm_alloc_page_table(vm) >>
 				   PGTBL_PAGE_SIZE_SHIFT;
@@ -114,14 +113,14 @@ void virt_arch_pg_map(struct kvm_vm *vm, uint64_t vaddr, uint64_t paddr)
 		level--;
 	}
 
-	paddr = paddr >> PGTBL_PAGE_SIZE_SHIFT;
-	*ptep = (paddr << PGTBL_PTE_ADDR_SHIFT) |
+	gpa = gpa >> PGTBL_PAGE_SIZE_SHIFT;
+	*ptep = (gpa << PGTBL_PTE_ADDR_SHIFT) |
 		PGTBL_PTE_PERM_MASK | PGTBL_PTE_VALID_MASK;
 }
 
-vm_paddr_t addr_arch_gva2gpa(struct kvm_vm *vm, vm_vaddr_t gva)
+gpa_t addr_arch_gva2gpa(struct kvm_vm *vm, gva_t gva)
 {
-	uint64_t *ptep;
+	u64 *ptep;
 	int level = vm->mmu.pgtable_levels - 1;
 
 	if (!vm->mmu.pgd_created)
@@ -148,12 +147,12 @@ vm_paddr_t addr_arch_gva2gpa(struct kvm_vm *vm, vm_vaddr_t gva)
 	exit(1);
 }
 
-static void pte_dump(FILE *stream, struct kvm_vm *vm, uint8_t indent,
-		     uint64_t page, int level)
+static void pte_dump(FILE *stream, struct kvm_vm *vm, u8 indent,
+		     u64 page, int level)
 {
 #ifdef DEBUG
 	static const char *const type[] = { "pte", "pmd", "pud", "p4d"};
-	uint64_t pte, *ptep;
+	u64 pte, *ptep;
 
 	if (level < 0)
 		return;
@@ -170,11 +169,11 @@ static void pte_dump(FILE *stream, struct kvm_vm *vm, uint8_t indent,
 #endif
 }
 
-void virt_arch_dump(FILE *stream, struct kvm_vm *vm, uint8_t indent)
+void virt_arch_dump(FILE *stream, struct kvm_vm *vm, u8 indent)
 {
 	struct kvm_mmu *mmu = &vm->mmu;
 	int level = mmu->pgtable_levels - 1;
-	uint64_t pgd, *ptep;
+	u64 pgd, *ptep;
 
 	if (!mmu->pgd_created)
 		return;
@@ -233,7 +232,7 @@ void riscv_vcpu_mmu_setup(struct kvm_vcpu *vcpu)
 	vcpu_set_reg(vcpu, RISCV_GENERAL_CSR_REG(satp), satp);
 }
 
-void vcpu_arch_dump(FILE *stream, struct kvm_vcpu *vcpu, uint8_t indent)
+void vcpu_arch_dump(FILE *stream, struct kvm_vcpu *vcpu, u8 indent)
 {
 	struct kvm_riscv_core core;
 
@@ -311,20 +310,20 @@ void vcpu_arch_set_entry_point(struct kvm_vcpu *vcpu, void *guest_code)
 	vcpu_set_reg(vcpu, RISCV_CORE_REG(regs.pc), (unsigned long)guest_code);
 }
 
-struct kvm_vcpu *vm_arch_vcpu_add(struct kvm_vm *vm, uint32_t vcpu_id)
+struct kvm_vcpu *vm_arch_vcpu_add(struct kvm_vm *vm, u32 vcpu_id)
 {
 	int r;
 	size_t stack_size;
-	unsigned long stack_vaddr;
+	unsigned long stack_gva;
 	unsigned long current_gp = 0;
 	struct kvm_mp_state mps;
 	struct kvm_vcpu *vcpu;
 
 	stack_size = vm->page_size == 4096 ? DEFAULT_STACK_PGS * vm->page_size :
 					     vm->page_size;
-	stack_vaddr = __vm_vaddr_alloc(vm, stack_size,
-				       DEFAULT_RISCV_GUEST_STACK_VADDR_MIN,
-				       MEM_REGION_DATA);
+	stack_gva = __vm_alloc(vm, stack_size,
+			       DEFAULT_RISCV_GUEST_STACK_VADDR_MIN,
+			       MEM_REGION_DATA);
 
 	vcpu = __vm_vcpu_add(vm, vcpu_id);
 	riscv_vcpu_mmu_setup(vcpu);
@@ -344,7 +343,7 @@ struct kvm_vcpu *vm_arch_vcpu_add(struct kvm_vm *vm, uint32_t vcpu_id)
 	vcpu_set_reg(vcpu, RISCV_CORE_REG(regs.gp), current_gp);
 
 	/* Setup stack pointer and program counter of guest */
-	vcpu_set_reg(vcpu, RISCV_CORE_REG(regs.sp), stack_vaddr + stack_size);
+	vcpu_set_reg(vcpu, RISCV_CORE_REG(regs.sp), stack_gva + stack_size);
 
 	/* Setup sscratch for guest_get_vcpuid() */
 	vcpu_set_reg(vcpu, RISCV_GENERAL_CSR_REG(sscratch), vcpu_id);
@@ -358,7 +357,7 @@ struct kvm_vcpu *vm_arch_vcpu_add(struct kvm_vm *vm, uint32_t vcpu_id)
 void vcpu_args_set(struct kvm_vcpu *vcpu, unsigned int num, ...)
 {
 	va_list ap;
-	uint64_t id = RISCV_CORE_REG(regs.a0);
+	u64 id = RISCV_CORE_REG(regs.a0);
 	int i;
 
 	TEST_ASSERT(num >= 1 && num <= 8, "Unsupported number of args,\n"
@@ -393,7 +392,7 @@ void vcpu_args_set(struct kvm_vcpu *vcpu, unsigned int num, ...)
 			id = RISCV_CORE_REG(regs.a7);
 			break;
 		}
-		vcpu_set_reg(vcpu, id, va_arg(ap, uint64_t));
+		vcpu_set_reg(vcpu, id, va_arg(ap, u64));
 	}
 
 	va_end(ap);
@@ -449,10 +448,10 @@ void vcpu_init_vector_tables(struct kvm_vcpu *vcpu)
 
 void vm_init_vector_tables(struct kvm_vm *vm)
 {
-	vm->handlers = __vm_vaddr_alloc(vm, sizeof(struct handlers),
-				   vm->page_size, MEM_REGION_DATA);
+	vm->handlers = __vm_alloc(vm, sizeof(struct handlers), vm->page_size,
+				  MEM_REGION_DATA);
 
-	*(vm_vaddr_t *)addr_gva2hva(vm, (vm_vaddr_t)(&exception_handlers)) = vm->handlers;
+	*(gva_t *)addr_gva2hva(vm, (gva_t)(&exception_handlers)) = vm->handlers;
 }
 
 void vm_install_exception_handler(struct kvm_vm *vm, int vector, exception_handler_fn handler)
@@ -470,7 +469,7 @@ void vm_install_interrupt_handler(struct kvm_vm *vm, exception_handler_fn handle
 	handlers->exception_handlers[1][0] = handler;
 }
 
-uint32_t guest_get_vcpuid(void)
+u32 guest_get_vcpuid(void)
 {
 	return csr_read(CSR_SSCRATCH);
 }
@@ -544,10 +543,10 @@ void kvm_selftest_arch_init(void)
 unsigned long riscv64_get_satp_mode(void)
 {
 	int kvm_fd, vm_fd, vcpu_fd, err;
-	uint64_t val;
+	u64 val;
 	struct kvm_one_reg reg = {
 		.id     = RISCV_CONFIG_REG(satp_mode),
-		.addr   = (uint64_t)&val,
+		.addr   = (u64)&val,
 	};
 
 	kvm_fd = open_kvm_dev_path_or_exit();
diff --git a/tools/testing/selftests/kvm/lib/s390/diag318_test_handler.c b/tools/testing/selftests/kvm/lib/s390/diag318_test_handler.c
index 2c432fa164f1..f5480473f192 100644
--- a/tools/testing/selftests/kvm/lib/s390/diag318_test_handler.c
+++ b/tools/testing/selftests/kvm/lib/s390/diag318_test_handler.c
@@ -13,7 +13,7 @@
 
 static void guest_code(void)
 {
-	uint64_t diag318_info = 0x12345678;
+	u64 diag318_info = 0x12345678;
 
 	asm volatile ("diag %0,0,0x318\n" : : "d" (diag318_info));
 }
@@ -23,13 +23,13 @@ static void guest_code(void)
  * we create an ad-hoc VM here to handle the instruction then extract the
  * necessary data. It is up to the caller to decide what to do with that data.
  */
-static uint64_t diag318_handler(void)
+static u64 diag318_handler(void)
 {
 	struct kvm_vcpu *vcpu;
 	struct kvm_vm *vm;
 	struct kvm_run *run;
-	uint64_t reg;
-	uint64_t diag318_info;
+	u64 reg;
+	u64 diag318_info;
 
 	vm = vm_create_with_one_vcpu(&vcpu, guest_code);
 	vcpu_run(vcpu);
@@ -51,9 +51,9 @@ static uint64_t diag318_handler(void)
 	return diag318_info;
 }
 
-uint64_t get_diag318_info(void)
+u64 get_diag318_info(void)
 {
-	static uint64_t diag318_info;
+	static u64 diag318_info;
 	static bool printed_skip;
 
 	/*
diff --git a/tools/testing/selftests/kvm/lib/s390/facility.c b/tools/testing/selftests/kvm/lib/s390/facility.c
index d540812d911a..9a778054f07f 100644
--- a/tools/testing/selftests/kvm/lib/s390/facility.c
+++ b/tools/testing/selftests/kvm/lib/s390/facility.c
@@ -10,5 +10,5 @@
 
 #include "facility.h"
 
-uint64_t stfl_doublewords[NB_STFL_DOUBLEWORDS];
+u64 stfl_doublewords[NB_STFL_DOUBLEWORDS];
 bool stfle_flag;
diff --git a/tools/testing/selftests/kvm/lib/s390/processor.c b/tools/testing/selftests/kvm/lib/s390/processor.c
index 6a9a660413a7..a9adb3782b35 100644
--- a/tools/testing/selftests/kvm/lib/s390/processor.c
+++ b/tools/testing/selftests/kvm/lib/s390/processor.c
@@ -12,7 +12,7 @@
 
 void virt_arch_pgd_alloc(struct kvm_vm *vm)
 {
-	vm_paddr_t paddr;
+	gpa_t gpa;
 
 	TEST_ASSERT(vm->page_size == PAGE_SIZE, "Unsupported page size: 0x%x",
 		    vm->page_size);
@@ -20,12 +20,12 @@ void virt_arch_pgd_alloc(struct kvm_vm *vm)
 	if (vm->mmu.pgd_created)
 		return;
 
-	paddr = vm_phy_pages_alloc(vm, PAGES_PER_REGION,
+	gpa = vm_phy_pages_alloc(vm, PAGES_PER_REGION,
 				   KVM_GUEST_PAGE_TABLE_MIN_PADDR,
 				   vm->memslots[MEM_REGION_PT]);
-	memset(addr_gpa2hva(vm, paddr), 0xff, PAGES_PER_REGION * vm->page_size);
+	memset(addr_gpa2hva(vm, gpa), 0xff, PAGES_PER_REGION * vm->page_size);
 
-	vm->mmu.pgd = paddr;
+	vm->mmu.pgd = gpa;
 	vm->mmu.pgd_created = true;
 }
 
@@ -34,9 +34,9 @@ void virt_arch_pgd_alloc(struct kvm_vm *vm)
  * a page table (ri == 4). Returns a suitable region/segment table entry
  * which points to the freshly allocated pages.
  */
-static uint64_t virt_alloc_region(struct kvm_vm *vm, int ri)
+static u64 virt_alloc_region(struct kvm_vm *vm, int ri)
 {
-	uint64_t taddr;
+	u64 taddr;
 
 	taddr = vm_phy_pages_alloc(vm,  ri < 4 ? PAGES_PER_REGION : 1,
 				   KVM_GUEST_PAGE_TABLE_MIN_PADDR, 0);
@@ -47,26 +47,24 @@ static uint64_t virt_alloc_region(struct kvm_vm *vm, int ri)
 		| ((ri < 4 ? (PAGES_PER_REGION - 1) : 0) & REGION_ENTRY_LENGTH);
 }
 
-void virt_arch_pg_map(struct kvm_vm *vm, uint64_t gva, uint64_t gpa)
+void virt_arch_pg_map(struct kvm_vm *vm, gva_t gva, gpa_t gpa)
 {
 	int ri, idx;
-	uint64_t *entry;
+	u64 *entry;
 
 	TEST_ASSERT((gva % vm->page_size) == 0,
-		"Virtual address not on page boundary,\n"
-		"  vaddr: 0x%lx vm->page_size: 0x%x",
-		gva, vm->page_size);
-	TEST_ASSERT(sparsebit_is_set(vm->vpages_valid,
-		(gva >> vm->page_shift)),
-		"Invalid virtual address, vaddr: 0x%lx",
-		gva);
+		    "Virtual address not on page boundary,\n"
+		    "  gva: 0x%lx vm->page_size: 0x%x",
+		    gva, vm->page_size);
+	TEST_ASSERT(sparsebit_is_set(vm->vpages_valid, (gva >> vm->page_shift)),
+		    "Invalid virtual address, gva: 0x%lx", gva);
 	TEST_ASSERT((gpa % vm->page_size) == 0,
 		"Physical address not on page boundary,\n"
-		"  paddr: 0x%lx vm->page_size: 0x%x",
+		"  gpa: 0x%lx vm->page_size: 0x%x",
 		gva, vm->page_size);
 	TEST_ASSERT((gpa >> vm->page_shift) <= vm->max_gfn,
 		"Physical address beyond beyond maximum supported,\n"
-		"  paddr: 0x%lx vm->max_gfn: 0x%lx vm->page_size: 0x%x",
+		"  gpa: 0x%lx vm->max_gfn: 0x%lx vm->page_size: 0x%x",
 		gva, vm->max_gfn, vm->page_size);
 
 	/* Walk through region and segment tables */
@@ -86,10 +84,10 @@ void virt_arch_pg_map(struct kvm_vm *vm, uint64_t gva, uint64_t gpa)
 	entry[idx] = gpa;
 }
 
-vm_paddr_t addr_arch_gva2gpa(struct kvm_vm *vm, vm_vaddr_t gva)
+gpa_t addr_arch_gva2gpa(struct kvm_vm *vm, gva_t gva)
 {
 	int ri, idx;
-	uint64_t *entry;
+	u64 *entry;
 
 	TEST_ASSERT(vm->page_size == PAGE_SIZE, "Unsupported page size: 0x%x",
 		    vm->page_size);
@@ -111,10 +109,10 @@ vm_paddr_t addr_arch_gva2gpa(struct kvm_vm *vm, vm_vaddr_t gva)
 	return (entry[idx] & ~0xffful) + (gva & 0xffful);
 }
 
-static void virt_dump_ptes(FILE *stream, struct kvm_vm *vm, uint8_t indent,
-			   uint64_t ptea_start)
+static void virt_dump_ptes(FILE *stream, struct kvm_vm *vm, u8 indent,
+			   u64 ptea_start)
 {
-	uint64_t *pte, ptea;
+	u64 *pte, ptea;
 
 	for (ptea = ptea_start; ptea < ptea_start + 0x100 * 8; ptea += 8) {
 		pte = addr_gpa2hva(vm, ptea);
@@ -125,10 +123,10 @@ static void virt_dump_ptes(FILE *stream, struct kvm_vm *vm, uint8_t indent,
 	}
 }
 
-static void virt_dump_region(FILE *stream, struct kvm_vm *vm, uint8_t indent,
-			     uint64_t reg_tab_addr)
+static void virt_dump_region(FILE *stream, struct kvm_vm *vm, u8 indent,
+			     u64 reg_tab_addr)
 {
-	uint64_t addr, *entry;
+	u64 addr, *entry;
 
 	for (addr = reg_tab_addr; addr < reg_tab_addr + 0x400 * 8; addr += 8) {
 		entry = addr_gpa2hva(vm, addr);
@@ -147,7 +145,7 @@ static void virt_dump_region(FILE *stream, struct kvm_vm *vm, uint8_t indent,
 	}
 }
 
-void virt_arch_dump(FILE *stream, struct kvm_vm *vm, uint8_t indent)
+void virt_arch_dump(FILE *stream, struct kvm_vm *vm, u8 indent)
 {
 	if (!vm->mmu.pgd_created)
 		return;
@@ -160,10 +158,10 @@ void vcpu_arch_set_entry_point(struct kvm_vcpu *vcpu, void *guest_code)
 	vcpu->run->psw_addr = (uintptr_t)guest_code;
 }
 
-struct kvm_vcpu *vm_arch_vcpu_add(struct kvm_vm *vm, uint32_t vcpu_id)
+struct kvm_vcpu *vm_arch_vcpu_add(struct kvm_vm *vm, u32 vcpu_id)
 {
 	size_t stack_size =  DEFAULT_STACK_PGS * getpagesize();
-	uint64_t stack_vaddr;
+	u64 stack_gva;
 	struct kvm_regs regs;
 	struct kvm_sregs sregs;
 	struct kvm_vcpu *vcpu;
@@ -171,15 +169,14 @@ struct kvm_vcpu *vm_arch_vcpu_add(struct kvm_vm *vm, uint32_t vcpu_id)
 	TEST_ASSERT(vm->page_size == PAGE_SIZE, "Unsupported page size: 0x%x",
 		    vm->page_size);
 
-	stack_vaddr = __vm_vaddr_alloc(vm, stack_size,
-				       DEFAULT_GUEST_STACK_VADDR_MIN,
-				       MEM_REGION_DATA);
+	stack_gva = __vm_alloc(vm, stack_size, DEFAULT_GUEST_STACK_VADDR_MIN,
+			       MEM_REGION_DATA);
 
 	vcpu = __vm_vcpu_add(vm, vcpu_id);
 
 	/* Setup guest registers */
 	vcpu_regs_get(vcpu, &regs);
-	regs.gprs[15] = stack_vaddr + (DEFAULT_STACK_PGS * getpagesize()) - 160;
+	regs.gprs[15] = stack_gva + (DEFAULT_STACK_PGS * getpagesize()) - 160;
 	vcpu_regs_set(vcpu, &regs);
 
 	vcpu_sregs_get(vcpu, &sregs);
@@ -206,13 +203,13 @@ void vcpu_args_set(struct kvm_vcpu *vcpu, unsigned int num, ...)
 	vcpu_regs_get(vcpu, &regs);
 
 	for (i = 0; i < num; i++)
-		regs.gprs[i + 2] = va_arg(ap, uint64_t);
+		regs.gprs[i + 2] = va_arg(ap, u64);
 
 	vcpu_regs_set(vcpu, &regs);
 	va_end(ap);
 }
 
-void vcpu_arch_dump(FILE *stream, struct kvm_vcpu *vcpu, uint8_t indent)
+void vcpu_arch_dump(FILE *stream, struct kvm_vcpu *vcpu, u8 indent)
 {
 	fprintf(stream, "%*spstate: psw: 0x%.16llx:0x%.16llx\n",
 		indent, "", vcpu->run->psw_mask, vcpu->run->psw_addr);
diff --git a/tools/testing/selftests/kvm/lib/sparsebit.c b/tools/testing/selftests/kvm/lib/sparsebit.c
index a99188f87a38..4d845000de15 100644
--- a/tools/testing/selftests/kvm/lib/sparsebit.c
+++ b/tools/testing/selftests/kvm/lib/sparsebit.c
@@ -76,11 +76,11 @@
  * the use of a binary-search tree, where each node contains at least
  * the following members:
  *
- *   typedef uint64_t sparsebit_idx_t;
- *   typedef uint64_t sparsebit_num_t;
+ *   typedef u64 sparsebit_idx_t;
+ *   typedef u64 sparsebit_num_t;
  *
  *   sparsebit_idx_t idx;
- *   uint32_t mask;
+ *   u32 mask;
  *   sparsebit_num_t num_after;
  *
  * The idx member contains the bit index of the first bit described by this
@@ -162,7 +162,7 @@
 
 #define DUMP_LINE_MAX 100 /* Does not include indent amount */
 
-typedef uint32_t mask_t;
+typedef u32 mask_t;
 #define MASK_BITS (sizeof(mask_t) * CHAR_BIT)
 
 struct node {
@@ -2056,9 +2056,9 @@ unsigned char get8(void)
 	return ch;
 }
 
-uint64_t get64(void)
+u64 get64(void)
 {
-	uint64_t x;
+	u64 x;
 
 	x = get8();
 	x = (x << 8) | get8();
@@ -2074,9 +2074,9 @@ int main(void)
 {
 	s = sparsebit_alloc();
 	for (;;) {
-		uint8_t op = get8() & 0xf;
-		uint64_t first = get64();
-		uint64_t last = get64();
+		u8 op = get8() & 0xf;
+		u64 first = get64();
+		u64 last = get64();
 
 		operate(op, first, last);
 	}
diff --git a/tools/testing/selftests/kvm/lib/test_util.c b/tools/testing/selftests/kvm/lib/test_util.c
index 8a1848586a85..bab1bd2b775b 100644
--- a/tools/testing/selftests/kvm/lib/test_util.c
+++ b/tools/testing/selftests/kvm/lib/test_util.c
@@ -30,15 +30,15 @@ void __attribute__((used)) expect_sigbus_handler(int signum)
  * Park-Miller LCG using standard constants.
  */
 
-struct guest_random_state new_guest_random_state(uint32_t seed)
+struct guest_random_state new_guest_random_state(u32 seed)
 {
 	struct guest_random_state s = {.seed = seed};
 	return s;
 }
 
-uint32_t guest_random_u32(struct guest_random_state *state)
+u32 guest_random_u32(struct guest_random_state *state)
 {
-	state->seed = (uint64_t)state->seed * 48271 % ((uint32_t)(1 << 31) - 1);
+	state->seed = (u64)state->seed * 48271 % ((u32)(1 << 31) - 1);
 	return state->seed;
 }
 
@@ -83,12 +83,12 @@ size_t parse_size(const char *size)
 	return base << shift;
 }
 
-int64_t timespec_to_ns(struct timespec ts)
+s64 timespec_to_ns(struct timespec ts)
 {
-	return (int64_t)ts.tv_nsec + 1000000000LL * (int64_t)ts.tv_sec;
+	return (s64)ts.tv_nsec + 1000000000LL * (s64)ts.tv_sec;
 }
 
-struct timespec timespec_add_ns(struct timespec ts, int64_t ns)
+struct timespec timespec_add_ns(struct timespec ts, s64 ns)
 {
 	struct timespec res;
 
@@ -101,15 +101,15 @@ struct timespec timespec_add_ns(struct timespec ts, int64_t ns)
 
 struct timespec timespec_add(struct timespec ts1, struct timespec ts2)
 {
-	int64_t ns1 = timespec_to_ns(ts1);
-	int64_t ns2 = timespec_to_ns(ts2);
+	s64 ns1 = timespec_to_ns(ts1);
+	s64 ns2 = timespec_to_ns(ts2);
 	return timespec_add_ns((struct timespec){0}, ns1 + ns2);
 }
 
 struct timespec timespec_sub(struct timespec ts1, struct timespec ts2)
 {
-	int64_t ns1 = timespec_to_ns(ts1);
-	int64_t ns2 = timespec_to_ns(ts2);
+	s64 ns1 = timespec_to_ns(ts1);
+	s64 ns2 = timespec_to_ns(ts2);
 	return timespec_add_ns((struct timespec){0}, ns1 - ns2);
 }
 
@@ -123,7 +123,7 @@ struct timespec timespec_elapsed(struct timespec start)
 
 struct timespec timespec_div(struct timespec ts, int divisor)
 {
-	int64_t ns = timespec_to_ns(ts) / divisor;
+	s64 ns = timespec_to_ns(ts) / divisor;
 
 	return timespec_add_ns((struct timespec){0}, ns);
 }
@@ -225,7 +225,7 @@ size_t get_def_hugetlb_pagesz(void)
 #define ANON_FLAGS	(MAP_PRIVATE | MAP_ANONYMOUS)
 #define ANON_HUGE_FLAGS	(ANON_FLAGS | MAP_HUGETLB)
 
-const struct vm_mem_backing_src_alias *vm_mem_backing_src_alias(uint32_t i)
+const struct vm_mem_backing_src_alias *vm_mem_backing_src_alias(u32 i)
 {
 	static const struct vm_mem_backing_src_alias aliases[] = {
 		[VM_MEM_SRC_ANONYMOUS] = {
@@ -317,9 +317,9 @@ const struct vm_mem_backing_src_alias *vm_mem_backing_src_alias(uint32_t i)
 
 #define MAP_HUGE_PAGE_SIZE(x) (1ULL << ((x >> MAP_HUGE_SHIFT) & MAP_HUGE_MASK))
 
-size_t get_backing_src_pagesz(uint32_t i)
+size_t get_backing_src_pagesz(u32 i)
 {
-	uint32_t flag = vm_mem_backing_src_alias(i)->flag;
+	u32 flag = vm_mem_backing_src_alias(i)->flag;
 
 	switch (i) {
 	case VM_MEM_SRC_ANONYMOUS:
@@ -335,7 +335,7 @@ size_t get_backing_src_pagesz(uint32_t i)
 	}
 }
 
-bool is_backing_src_hugetlb(uint32_t i)
+bool is_backing_src_hugetlb(u32 i)
 {
 	return !!(vm_mem_backing_src_alias(i)->flag & MAP_HUGETLB);
 }
diff --git a/tools/testing/selftests/kvm/lib/ucall_common.c b/tools/testing/selftests/kvm/lib/ucall_common.c
index 42151e571953..029ce21f9f2f 100644
--- a/tools/testing/selftests/kvm/lib/ucall_common.c
+++ b/tools/testing/selftests/kvm/lib/ucall_common.c
@@ -14,7 +14,7 @@ struct ucall_header {
 	struct ucall ucalls[KVM_MAX_VCPUS];
 };
 
-int ucall_nr_pages_required(uint64_t page_size)
+int ucall_nr_pages_required(u64 page_size)
 {
 	return align_up(sizeof(struct ucall_header), page_size) / page_size;
 }
@@ -25,16 +25,16 @@ int ucall_nr_pages_required(uint64_t page_size)
  */
 static struct ucall_header *ucall_pool;
 
-void ucall_init(struct kvm_vm *vm, vm_paddr_t mmio_gpa)
+void ucall_init(struct kvm_vm *vm, gpa_t mmio_gpa)
 {
 	struct ucall_header *hdr;
 	struct ucall *uc;
-	vm_vaddr_t vaddr;
+	gva_t gva;
 	int i;
 
-	vaddr = vm_vaddr_alloc_shared(vm, sizeof(*hdr), KVM_UTIL_MIN_VADDR,
-				      MEM_REGION_DATA);
-	hdr = (struct ucall_header *)addr_gva2hva(vm, vaddr);
+	gva = vm_alloc_shared(vm, sizeof(*hdr), KVM_UTIL_MIN_VADDR,
+				MEM_REGION_DATA);
+	hdr = (struct ucall_header *)addr_gva2hva(vm, gva);
 	memset(hdr, 0, sizeof(*hdr));
 
 	for (i = 0; i < KVM_MAX_VCPUS; ++i) {
@@ -42,7 +42,7 @@ void ucall_init(struct kvm_vm *vm, vm_paddr_t mmio_gpa)
 		uc->hva = uc;
 	}
 
-	write_guest_global(vm, ucall_pool, (struct ucall_header *)vaddr);
+	write_guest_global(vm, ucall_pool, (struct ucall_header *)gva);
 
 	ucall_arch_init(vm, mmio_gpa);
 }
@@ -79,7 +79,7 @@ static void ucall_free(struct ucall *uc)
 	clear_bit(uc - ucall_pool->ucalls, ucall_pool->in_use);
 }
 
-void ucall_assert(uint64_t cmd, const char *exp, const char *file,
+void ucall_assert(u64 cmd, const char *exp, const char *file,
 		  unsigned int line, const char *fmt, ...)
 {
 	struct ucall *uc;
@@ -88,20 +88,20 @@ void ucall_assert(uint64_t cmd, const char *exp, const char *file,
 	uc = ucall_alloc();
 	uc->cmd = cmd;
 
-	WRITE_ONCE(uc->args[GUEST_ERROR_STRING], (uint64_t)(exp));
-	WRITE_ONCE(uc->args[GUEST_FILE], (uint64_t)(file));
+	WRITE_ONCE(uc->args[GUEST_ERROR_STRING], (u64)(exp));
+	WRITE_ONCE(uc->args[GUEST_FILE], (u64)(file));
 	WRITE_ONCE(uc->args[GUEST_LINE], line);
 
 	va_start(va, fmt);
 	guest_vsnprintf(uc->buffer, UCALL_BUFFER_LEN, fmt, va);
 	va_end(va);
 
-	ucall_arch_do_ucall((vm_vaddr_t)uc->hva);
+	ucall_arch_do_ucall((gva_t)uc->hva);
 
 	ucall_free(uc);
 }
 
-void ucall_fmt(uint64_t cmd, const char *fmt, ...)
+void ucall_fmt(u64 cmd, const char *fmt, ...)
 {
 	struct ucall *uc;
 	va_list va;
@@ -113,12 +113,12 @@ void ucall_fmt(uint64_t cmd, const char *fmt, ...)
 	guest_vsnprintf(uc->buffer, UCALL_BUFFER_LEN, fmt, va);
 	va_end(va);
 
-	ucall_arch_do_ucall((vm_vaddr_t)uc->hva);
+	ucall_arch_do_ucall((gva_t)uc->hva);
 
 	ucall_free(uc);
 }
 
-void ucall(uint64_t cmd, int nargs, ...)
+void ucall(u64 cmd, int nargs, ...)
 {
 	struct ucall *uc;
 	va_list va;
@@ -132,15 +132,15 @@ void ucall(uint64_t cmd, int nargs, ...)
 
 	va_start(va, nargs);
 	for (i = 0; i < nargs; ++i)
-		WRITE_ONCE(uc->args[i], va_arg(va, uint64_t));
+		WRITE_ONCE(uc->args[i], va_arg(va, u64));
 	va_end(va);
 
-	ucall_arch_do_ucall((vm_vaddr_t)uc->hva);
+	ucall_arch_do_ucall((gva_t)uc->hva);
 
 	ucall_free(uc);
 }
 
-uint64_t get_ucall(struct kvm_vcpu *vcpu, struct ucall *uc)
+u64 get_ucall(struct kvm_vcpu *vcpu, struct ucall *uc)
 {
 	struct ucall ucall;
 	void *addr;
diff --git a/tools/testing/selftests/kvm/lib/userfaultfd_util.c b/tools/testing/selftests/kvm/lib/userfaultfd_util.c
index 5bde176cedd5..ef8d76f71f83 100644
--- a/tools/testing/selftests/kvm/lib/userfaultfd_util.c
+++ b/tools/testing/selftests/kvm/lib/userfaultfd_util.c
@@ -27,7 +27,7 @@ static void *uffd_handler_thread_fn(void *arg)
 {
 	struct uffd_reader_args *reader_args = (struct uffd_reader_args *)arg;
 	int uffd = reader_args->uffd;
-	int64_t pages = 0;
+	s64 pages = 0;
 	struct timespec start;
 	struct timespec ts_diff;
 	struct epoll_event evt;
@@ -100,8 +100,8 @@ static void *uffd_handler_thread_fn(void *arg)
 }
 
 struct uffd_desc *uffd_setup_demand_paging(int uffd_mode, useconds_t delay,
-					   void *hva, uint64_t len,
-					   uint64_t num_readers,
+					   void *hva, u64 len,
+					   u64 num_readers,
 					   uffd_handler_t handler)
 {
 	struct uffd_desc *uffd_desc;
@@ -109,7 +109,7 @@ struct uffd_desc *uffd_setup_demand_paging(int uffd_mode, useconds_t delay,
 	int uffd;
 	struct uffdio_api uffdio_api;
 	struct uffdio_register uffdio_register;
-	uint64_t expected_ioctls = ((uint64_t) 1) << _UFFDIO_COPY;
+	u64 expected_ioctls = ((u64)1) << _UFFDIO_COPY;
 	int ret, i;
 
 	PER_PAGE_DEBUG("Userfaultfd %s mode, faults resolved with %s\n",
@@ -132,7 +132,7 @@ struct uffd_desc *uffd_setup_demand_paging(int uffd_mode, useconds_t delay,
 
 	/* In order to get minor faults, prefault via the alias. */
 	if (is_minor)
-		expected_ioctls = ((uint64_t) 1) << _UFFDIO_CONTINUE;
+		expected_ioctls = ((u64)1) << _UFFDIO_CONTINUE;
 
 	uffd = syscall(__NR_userfaultfd, O_CLOEXEC | O_NONBLOCK);
 	TEST_ASSERT(uffd >= 0, "uffd creation failed, errno: %d", errno);
@@ -141,9 +141,9 @@ struct uffd_desc *uffd_setup_demand_paging(int uffd_mode, useconds_t delay,
 	uffdio_api.features = 0;
 	TEST_ASSERT(ioctl(uffd, UFFDIO_API, &uffdio_api) != -1,
 		    "ioctl UFFDIO_API failed: %" PRIu64,
-		    (uint64_t)uffdio_api.api);
+		    (u64)uffdio_api.api);
 
-	uffdio_register.range.start = (uint64_t)hva;
+	uffdio_register.range.start = (u64)hva;
 	uffdio_register.range.len = len;
 	uffdio_register.mode = uffd_mode;
 	TEST_ASSERT(ioctl(uffd, UFFDIO_REGISTER, &uffdio_register) != -1,
diff --git a/tools/testing/selftests/kvm/lib/x86/apic.c b/tools/testing/selftests/kvm/lib/x86/apic.c
index 89153a333e83..5182fd0d6a76 100644
--- a/tools/testing/selftests/kvm/lib/x86/apic.c
+++ b/tools/testing/selftests/kvm/lib/x86/apic.c
@@ -14,7 +14,7 @@ void apic_disable(void)
 
 void xapic_enable(void)
 {
-	uint64_t val = rdmsr(MSR_IA32_APICBASE);
+	u64 val = rdmsr(MSR_IA32_APICBASE);
 
 	/* Per SDM: to enable xAPIC when in x2APIC must first disable APIC */
 	if (val & MSR_IA32_APICBASE_EXTD) {
diff --git a/tools/testing/selftests/kvm/lib/x86/hyperv.c b/tools/testing/selftests/kvm/lib/x86/hyperv.c
index 15bc8cd583aa..d200c5c26e2e 100644
--- a/tools/testing/selftests/kvm/lib/x86/hyperv.c
+++ b/tools/testing/selftests/kvm/lib/x86/hyperv.c
@@ -76,23 +76,23 @@ bool kvm_hv_cpu_has(struct kvm_x86_cpu_feature feature)
 }
 
 struct hyperv_test_pages *vcpu_alloc_hyperv_test_pages(struct kvm_vm *vm,
-						       vm_vaddr_t *p_hv_pages_gva)
+						       gva_t *p_hv_pages_gva)
 {
-	vm_vaddr_t hv_pages_gva = vm_vaddr_alloc_page(vm);
+	gva_t hv_pages_gva = vm_alloc_page(vm);
 	struct hyperv_test_pages *hv = addr_gva2hva(vm, hv_pages_gva);
 
 	/* Setup of a region of guest memory for the VP Assist page. */
-	hv->vp_assist = (void *)vm_vaddr_alloc_page(vm);
+	hv->vp_assist = (void *)vm_alloc_page(vm);
 	hv->vp_assist_hva = addr_gva2hva(vm, (uintptr_t)hv->vp_assist);
 	hv->vp_assist_gpa = addr_gva2gpa(vm, (uintptr_t)hv->vp_assist);
 
 	/* Setup of a region of guest memory for the partition assist page. */
-	hv->partition_assist = (void *)vm_vaddr_alloc_page(vm);
+	hv->partition_assist = (void *)vm_alloc_page(vm);
 	hv->partition_assist_hva = addr_gva2hva(vm, (uintptr_t)hv->partition_assist);
 	hv->partition_assist_gpa = addr_gva2gpa(vm, (uintptr_t)hv->partition_assist);
 
 	/* Setup of a region of guest memory for the enlightened VMCS. */
-	hv->enlightened_vmcs = (void *)vm_vaddr_alloc_page(vm);
+	hv->enlightened_vmcs = (void *)vm_alloc_page(vm);
 	hv->enlightened_vmcs_hva = addr_gva2hva(vm, (uintptr_t)hv->enlightened_vmcs);
 	hv->enlightened_vmcs_gpa = addr_gva2gpa(vm, (uintptr_t)hv->enlightened_vmcs);
 
@@ -100,9 +100,9 @@ struct hyperv_test_pages *vcpu_alloc_hyperv_test_pages(struct kvm_vm *vm,
 	return hv;
 }
 
-int enable_vp_assist(uint64_t vp_assist_pa, void *vp_assist)
+int enable_vp_assist(u64 vp_assist_pa, void *vp_assist)
 {
-	uint64_t val = (vp_assist_pa & HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_MASK) |
+	u64 val = (vp_assist_pa & HV_X64_MSR_VP_ASSIST_PAGE_ADDRESS_MASK) |
 		HV_X64_MSR_VP_ASSIST_PAGE_ENABLE;
 
 	wrmsr(HV_X64_MSR_VP_ASSIST_PAGE, val);
diff --git a/tools/testing/selftests/kvm/lib/x86/memstress.c b/tools/testing/selftests/kvm/lib/x86/memstress.c
index f53414ba7103..61cf952cd2dc 100644
--- a/tools/testing/selftests/kvm/lib/x86/memstress.c
+++ b/tools/testing/selftests/kvm/lib/x86/memstress.c
@@ -16,7 +16,7 @@
 #include "svm_util.h"
 #include "vmx.h"
 
-void memstress_l2_guest_code(uint64_t vcpu_id)
+void memstress_l2_guest_code(u64 vcpu_id)
 {
 	memstress_guest_code(vcpu_id);
 	vmcall();
@@ -32,7 +32,7 @@ __asm__(
 
 #define L2_GUEST_STACK_SIZE 64
 
-static void l1_vmx_code(struct vmx_pages *vmx, uint64_t vcpu_id)
+static void l1_vmx_code(struct vmx_pages *vmx, u64 vcpu_id)
 {
 	unsigned long l2_guest_stack[L2_GUEST_STACK_SIZE];
 	unsigned long *rsp;
@@ -51,7 +51,7 @@ static void l1_vmx_code(struct vmx_pages *vmx, uint64_t vcpu_id)
 	GUEST_DONE();
 }
 
-static void l1_svm_code(struct svm_test_data *svm, uint64_t vcpu_id)
+static void l1_svm_code(struct svm_test_data *svm, u64 vcpu_id)
 {
 	unsigned long l2_guest_stack[L2_GUEST_STACK_SIZE];
 	unsigned long *rsp;
@@ -67,7 +67,7 @@ static void l1_svm_code(struct svm_test_data *svm, uint64_t vcpu_id)
 }
 
 
-static void memstress_l1_guest_code(void *data, uint64_t vcpu_id)
+static void memstress_l1_guest_code(void *data, u64 vcpu_id)
 {
 	if (this_cpu_has(X86_FEATURE_VMX))
 		l1_vmx_code(data, vcpu_id);
@@ -75,7 +75,7 @@ static void memstress_l1_guest_code(void *data, uint64_t vcpu_id)
 		l1_svm_code(data, vcpu_id);
 }
 
-uint64_t memstress_nested_pages(int nr_vcpus)
+u64 memstress_nested_pages(int nr_vcpus)
 {
 	/*
 	 * 513 page tables is enough to identity-map 256 TiB of L2 with 1G
@@ -87,7 +87,7 @@ uint64_t memstress_nested_pages(int nr_vcpus)
 
 static void memstress_setup_ept_mappings(struct kvm_vm *vm)
 {
-	uint64_t start, end;
+	u64 start, end;
 
 	/*
 	 * Identity map the first 4G and the test region with 1G pages so that
@@ -104,7 +104,7 @@ static void memstress_setup_ept_mappings(struct kvm_vm *vm)
 void memstress_setup_nested(struct kvm_vm *vm, int nr_vcpus, struct kvm_vcpu *vcpus[])
 {
 	struct kvm_regs regs;
-	vm_vaddr_t nested_gva;
+	gva_t nested_gva;
 	int vcpu_id;
 
 	TEST_REQUIRE(kvm_cpu_has_tdp());
diff --git a/tools/testing/selftests/kvm/lib/x86/pmu.c b/tools/testing/selftests/kvm/lib/x86/pmu.c
index 34cb57d1d671..0851b74b4e46 100644
--- a/tools/testing/selftests/kvm/lib/x86/pmu.c
+++ b/tools/testing/selftests/kvm/lib/x86/pmu.c
@@ -11,7 +11,7 @@
 #include "processor.h"
 #include "pmu.h"
 
-const uint64_t intel_pmu_arch_events[] = {
+const u64 intel_pmu_arch_events[] = {
 	INTEL_ARCH_CPU_CYCLES,
 	INTEL_ARCH_INSTRUCTIONS_RETIRED,
 	INTEL_ARCH_REFERENCE_CYCLES,
@@ -28,7 +28,7 @@ const uint64_t intel_pmu_arch_events[] = {
 };
 kvm_static_assert(ARRAY_SIZE(intel_pmu_arch_events) == NR_INTEL_ARCH_EVENTS);
 
-const uint64_t amd_pmu_zen_events[] = {
+const u64 amd_pmu_zen_events[] = {
 	AMD_ZEN_CORE_CYCLES,
 	AMD_ZEN_INSTRUCTIONS_RETIRED,
 	AMD_ZEN_BRANCHES_RETIRED,
@@ -50,7 +50,7 @@ kvm_static_assert(ARRAY_SIZE(amd_pmu_zen_events) == NR_AMD_ZEN_EVENTS);
  * be overcounted on these certain instructions, but for Clearwater Forest
  * only "Instruction Retired" event is overcounted on these instructions.
  */
-static uint64_t get_pmu_errata(void)
+static u64 get_pmu_errata(void)
 {
 	if (!this_cpu_is_intel())
 		return 0;
@@ -72,7 +72,7 @@ static uint64_t get_pmu_errata(void)
 	}
 }
 
-uint64_t pmu_errata_mask;
+u64 pmu_errata_mask;
 
 void kvm_init_pmu_errata(void)
 {
diff --git a/tools/testing/selftests/kvm/lib/x86/processor.c b/tools/testing/selftests/kvm/lib/x86/processor.c
index 01f0f97d4430..b51467d70f6e 100644
--- a/tools/testing/selftests/kvm/lib/x86/processor.c
+++ b/tools/testing/selftests/kvm/lib/x86/processor.c
@@ -21,13 +21,13 @@
 #define KERNEL_DS	0x10
 #define KERNEL_TSS	0x18
 
-vm_vaddr_t exception_handlers;
+gva_t exception_handlers;
 bool host_cpu_is_amd;
 bool host_cpu_is_intel;
 bool host_cpu_is_hygon;
 bool host_cpu_is_amd_compatible;
 bool is_forced_emulation_enabled;
-uint64_t guest_tsc_khz;
+u64 guest_tsc_khz;
 
 const char *ex_str(int vector)
 {
@@ -62,7 +62,7 @@ const char *ex_str(int vector)
 	}
 }
 
-static void regs_dump(FILE *stream, struct kvm_regs *regs, uint8_t indent)
+static void regs_dump(FILE *stream, struct kvm_regs *regs, u8 indent)
 {
 	fprintf(stream, "%*srax: 0x%.16llx rbx: 0x%.16llx "
 		"rcx: 0x%.16llx rdx: 0x%.16llx\n",
@@ -86,7 +86,7 @@ static void regs_dump(FILE *stream, struct kvm_regs *regs, uint8_t indent)
 }
 
 static void segment_dump(FILE *stream, struct kvm_segment *segment,
-			 uint8_t indent)
+			 u8 indent)
 {
 	fprintf(stream, "%*sbase: 0x%.16llx limit: 0x%.8x "
 		"selector: 0x%.4x type: 0x%.2x\n",
@@ -103,7 +103,7 @@ static void segment_dump(FILE *stream, struct kvm_segment *segment,
 }
 
 static void dtable_dump(FILE *stream, struct kvm_dtable *dtable,
-			uint8_t indent)
+			u8 indent)
 {
 	fprintf(stream, "%*sbase: 0x%.16llx limit: 0x%.4x "
 		"padding: 0x%.4x 0x%.4x 0x%.4x\n",
@@ -111,7 +111,7 @@ static void dtable_dump(FILE *stream, struct kvm_dtable *dtable,
 		dtable->padding[0], dtable->padding[1], dtable->padding[2]);
 }
 
-static void sregs_dump(FILE *stream, struct kvm_sregs *sregs, uint8_t indent)
+static void sregs_dump(FILE *stream, struct kvm_sregs *sregs, u8 indent)
 {
 	unsigned int i;
 
@@ -207,37 +207,37 @@ void tdp_mmu_init(struct kvm_vm *vm, int pgtable_levels,
 }
 
 static void *virt_get_pte(struct kvm_vm *vm, struct kvm_mmu *mmu,
-			  uint64_t *parent_pte, uint64_t vaddr, int level)
+			  u64 *parent_pte, gva_t gva, int level)
 {
-	uint64_t pt_gpa = PTE_GET_PA(*parent_pte);
-	uint64_t *page_table = addr_gpa2hva(vm, pt_gpa);
-	int index = (vaddr >> PG_LEVEL_SHIFT(level)) & 0x1ffu;
+	u64 pt_gpa = PTE_GET_PA(*parent_pte);
+	u64 *page_table = addr_gpa2hva(vm, pt_gpa);
+	int index = (gva >> PG_LEVEL_SHIFT(level)) & 0x1ffu;
 
 	TEST_ASSERT((*parent_pte == mmu->pgd) || is_present_pte(mmu, parent_pte),
 		    "Parent PTE (level %d) not PRESENT for gva: 0x%08lx",
-		    level + 1, vaddr);
+		    level + 1, gva);
 
 	return &page_table[index];
 }
 
-static uint64_t *virt_create_upper_pte(struct kvm_vm *vm,
-				       struct kvm_mmu *mmu,
-				       uint64_t *parent_pte,
-				       uint64_t vaddr,
-				       uint64_t paddr,
-				       int current_level,
-				       int target_level)
+static u64 *virt_create_upper_pte(struct kvm_vm *vm,
+				  struct kvm_mmu *mmu,
+				  u64 *parent_pte,
+				  gva_t gva,
+				  gpa_t gpa,
+				  int current_level,
+				  int target_level)
 {
-	uint64_t *pte = virt_get_pte(vm, mmu, parent_pte, vaddr, current_level);
+	u64 *pte = virt_get_pte(vm, mmu, parent_pte, gva, current_level);
 
-	paddr = vm_untag_gpa(vm, paddr);
+	gpa = vm_untag_gpa(vm, gpa);
 
 	if (!is_present_pte(mmu, pte)) {
 		*pte = PTE_PRESENT_MASK(mmu) | PTE_READABLE_MASK(mmu) |
 		       PTE_WRITABLE_MASK(mmu) | PTE_EXECUTABLE_MASK(mmu) |
 		       PTE_ALWAYS_SET_MASK(mmu);
 		if (current_level == target_level)
-			*pte |= PTE_HUGE_MASK(mmu) | (paddr & PHYSICAL_PAGE_MASK);
+			*pte |= PTE_HUGE_MASK(mmu) | (gpa & PHYSICAL_PAGE_MASK);
 		else
 			*pte |= vm_alloc_page_table(vm) & PHYSICAL_PAGE_MASK;
 	} else {
@@ -247,39 +247,39 @@ static uint64_t *virt_create_upper_pte(struct kvm_vm *vm,
 		 * this level.
 		 */
 		TEST_ASSERT(current_level != target_level,
-			    "Cannot create hugepage at level: %u, vaddr: 0x%lx",
-			    current_level, vaddr);
+			    "Cannot create hugepage at level: %u, gva: 0x%lx",
+			    current_level, gva);
 		TEST_ASSERT(!is_huge_pte(mmu, pte),
-			    "Cannot create page table at level: %u, vaddr: 0x%lx",
-			    current_level, vaddr);
+			    "Cannot create page table at level: %u, gva: 0x%lx",
+			    current_level, gva);
 	}
 	return pte;
 }
 
-void __virt_pg_map(struct kvm_vm *vm, struct kvm_mmu *mmu, uint64_t vaddr,
-		   uint64_t paddr, int level)
+void __virt_pg_map(struct kvm_vm *vm, struct kvm_mmu *mmu, gva_t gva,
+		   gpa_t gpa, int level)
 {
-	const uint64_t pg_size = PG_LEVEL_SIZE(level);
-	uint64_t *pte = &mmu->pgd;
+	const u64 pg_size = PG_LEVEL_SIZE(level);
+	u64 *pte = &mmu->pgd;
 	int current_level;
 
 	TEST_ASSERT(vm->mode == VM_MODE_PXXVYY_4K,
 		    "Unknown or unsupported guest mode: 0x%x", vm->mode);
 
-	TEST_ASSERT((vaddr % pg_size) == 0,
+	TEST_ASSERT((gva % pg_size) == 0,
 		    "Virtual address not aligned,\n"
-		    "vaddr: 0x%lx page size: 0x%lx", vaddr, pg_size);
-	TEST_ASSERT(sparsebit_is_set(vm->vpages_valid, (vaddr >> vm->page_shift)),
-		    "Invalid virtual address, vaddr: 0x%lx", vaddr);
-	TEST_ASSERT((paddr % pg_size) == 0,
+		    "gva: 0x%lx page size: 0x%lx", gva, pg_size);
+	TEST_ASSERT(sparsebit_is_set(vm->vpages_valid, (gva >> vm->page_shift)),
+		    "Invalid virtual address, gva: 0x%lx", gva);
+	TEST_ASSERT((gpa % pg_size) == 0,
 		    "Physical address not aligned,\n"
-		    "  paddr: 0x%lx page size: 0x%lx", paddr, pg_size);
-	TEST_ASSERT((paddr >> vm->page_shift) <= vm->max_gfn,
+		    "  gpa: 0x%lx page size: 0x%lx", gpa, pg_size);
+	TEST_ASSERT((gpa >> vm->page_shift) <= vm->max_gfn,
 		    "Physical address beyond maximum supported,\n"
-		    "  paddr: 0x%lx vm->max_gfn: 0x%lx vm->page_size: 0x%x",
-		    paddr, vm->max_gfn, vm->page_size);
-	TEST_ASSERT(vm_untag_gpa(vm, paddr) == paddr,
-		    "Unexpected bits in paddr: %lx", paddr);
+		    "  gpa: 0x%lx vm->max_gfn: 0x%lx vm->page_size: 0x%x",
+		    gpa, vm->max_gfn, vm->page_size);
+	TEST_ASSERT(vm_untag_gpa(vm, gpa) == gpa,
+		    "Unexpected bits in gpa: %lx", gpa);
 
 	TEST_ASSERT(!PTE_EXECUTABLE_MASK(mmu) || !PTE_NX_MASK(mmu),
 		    "X and NX bit masks cannot be used simultaneously");
@@ -291,40 +291,40 @@ void __virt_pg_map(struct kvm_vm *vm, struct kvm_mmu *mmu, uint64_t vaddr,
 	for (current_level = mmu->pgtable_levels;
 	     current_level > PG_LEVEL_4K;
 	     current_level--) {
-		pte = virt_create_upper_pte(vm, mmu, pte, vaddr, paddr,
+		pte = virt_create_upper_pte(vm, mmu, pte, gva, gpa,
 					    current_level, level);
 		if (is_huge_pte(mmu, pte))
 			return;
 	}
 
 	/* Fill in page table entry. */
-	pte = virt_get_pte(vm, mmu, pte, vaddr, PG_LEVEL_4K);
+	pte = virt_get_pte(vm, mmu, pte, gva, PG_LEVEL_4K);
 	TEST_ASSERT(!is_present_pte(mmu, pte),
-		    "PTE already present for 4k page at vaddr: 0x%lx", vaddr);
+		    "PTE already present for 4k page at gva: 0x%lx", gva);
 	*pte = PTE_PRESENT_MASK(mmu) | PTE_READABLE_MASK(mmu) |
 	       PTE_WRITABLE_MASK(mmu) | PTE_EXECUTABLE_MASK(mmu) |
-	       PTE_ALWAYS_SET_MASK(mmu) | (paddr & PHYSICAL_PAGE_MASK);
+	       PTE_ALWAYS_SET_MASK(mmu) | (gpa & PHYSICAL_PAGE_MASK);
 
 	/*
 	 * Neither SEV nor TDX supports shared page tables, so only the final
 	 * leaf PTE needs manually set the C/S-bit.
 	 */
-	if (vm_is_gpa_protected(vm, paddr))
+	if (vm_is_gpa_protected(vm, gpa))
 		*pte |= PTE_C_BIT_MASK(mmu);
 	else
 		*pte |= PTE_S_BIT_MASK(mmu);
 }
 
-void virt_arch_pg_map(struct kvm_vm *vm, uint64_t vaddr, uint64_t paddr)
+void virt_arch_pg_map(struct kvm_vm *vm, gva_t gva, gpa_t gpa)
 {
-	__virt_pg_map(vm, &vm->mmu, vaddr, paddr, PG_LEVEL_4K);
+	__virt_pg_map(vm, &vm->mmu, gva, gpa, PG_LEVEL_4K);
 }
 
-void virt_map_level(struct kvm_vm *vm, uint64_t vaddr, uint64_t paddr,
-		    uint64_t nr_bytes, int level)
+void virt_map_level(struct kvm_vm *vm, gva_t gva, gpa_t gpa,
+		    u64 nr_bytes, int level)
 {
-	uint64_t pg_size = PG_LEVEL_SIZE(level);
-	uint64_t nr_pages = nr_bytes / pg_size;
+	u64 pg_size = PG_LEVEL_SIZE(level);
+	u64 nr_pages = nr_bytes / pg_size;
 	int i;
 
 	TEST_ASSERT(nr_bytes % pg_size == 0,
@@ -332,16 +332,16 @@ void virt_map_level(struct kvm_vm *vm, uint64_t vaddr, uint64_t paddr,
 		    nr_bytes, pg_size);
 
 	for (i = 0; i < nr_pages; i++) {
-		__virt_pg_map(vm, &vm->mmu, vaddr, paddr, level);
-		sparsebit_set_num(vm->vpages_mapped, vaddr >> vm->page_shift,
+		__virt_pg_map(vm, &vm->mmu, gva, gpa, level);
+		sparsebit_set_num(vm->vpages_mapped, gva >> vm->page_shift,
 				  nr_bytes / PAGE_SIZE);
 
-		vaddr += pg_size;
-		paddr += pg_size;
+		gva += pg_size;
+		gpa += pg_size;
 	}
 }
 
-static bool vm_is_target_pte(struct kvm_mmu *mmu, uint64_t *pte,
+static bool vm_is_target_pte(struct kvm_mmu *mmu, u64 *pte,
 			     int *level, int current_level)
 {
 	if (is_huge_pte(mmu, pte)) {
@@ -354,13 +354,13 @@ static bool vm_is_target_pte(struct kvm_mmu *mmu, uint64_t *pte,
 	return *level == current_level;
 }
 
-static uint64_t *__vm_get_page_table_entry(struct kvm_vm *vm,
-					   struct kvm_mmu *mmu,
-					   uint64_t vaddr,
-					   int *level)
+static u64 *__vm_get_page_table_entry(struct kvm_vm *vm,
+				      struct kvm_mmu *mmu,
+				      gva_t gva,
+				      int *level)
 {
 	int va_width = 12 + (mmu->pgtable_levels) * 9;
-	uint64_t *pte = &mmu->pgd;
+	u64 *pte = &mmu->pgd;
 	int current_level;
 
 	TEST_ASSERT(!vm->arch.is_pt_protected,
@@ -371,49 +371,46 @@ static uint64_t *__vm_get_page_table_entry(struct kvm_vm *vm,
 
 	TEST_ASSERT(vm->mode == VM_MODE_PXXVYY_4K,
 		    "Unknown or unsupported guest mode: 0x%x", vm->mode);
-	TEST_ASSERT(sparsebit_is_set(vm->vpages_valid,
-		(vaddr >> vm->page_shift)),
-		"Invalid virtual address, vaddr: 0x%lx",
-		vaddr);
+	TEST_ASSERT(sparsebit_is_set(vm->vpages_valid, (gva >> vm->page_shift)),
+		    "Invalid virtual address, gva: 0x%lx", gva);
 	/*
-	 * Check that the vaddr is a sign-extended va_width value.
+	 * Check that the gva is a sign-extended va_width value.
 	 */
-	TEST_ASSERT(vaddr ==
-		    (((int64_t)vaddr << (64 - va_width) >> (64 - va_width))),
+	TEST_ASSERT(gva == (((s64)gva << (64 - va_width) >> (64 - va_width))),
 		    "Canonical check failed.  The virtual address is invalid.");
 
 	for (current_level = mmu->pgtable_levels;
 	     current_level > PG_LEVEL_4K;
 	     current_level--) {
-		pte = virt_get_pte(vm, mmu, pte, vaddr, current_level);
+		pte = virt_get_pte(vm, mmu, pte, gva, current_level);
 		if (vm_is_target_pte(mmu, pte, level, current_level))
 			return pte;
 	}
 
-	return virt_get_pte(vm, mmu, pte, vaddr, PG_LEVEL_4K);
+	return virt_get_pte(vm, mmu, pte, gva, PG_LEVEL_4K);
 }
 
-uint64_t *tdp_get_pte(struct kvm_vm *vm, uint64_t l2_gpa)
+u64 *tdp_get_pte(struct kvm_vm *vm, u64 l2_gpa)
 {
 	int level = PG_LEVEL_4K;
 
 	return __vm_get_page_table_entry(vm, &vm->stage2_mmu, l2_gpa, &level);
 }
 
-uint64_t *vm_get_pte(struct kvm_vm *vm, uint64_t vaddr)
+u64 *vm_get_pte(struct kvm_vm *vm, gva_t gva)
 {
 	int level = PG_LEVEL_4K;
 
-	return __vm_get_page_table_entry(vm, &vm->mmu, vaddr, &level);
+	return __vm_get_page_table_entry(vm, &vm->mmu, gva, &level);
 }
 
-void virt_arch_dump(FILE *stream, struct kvm_vm *vm, uint8_t indent)
+void virt_arch_dump(FILE *stream, struct kvm_vm *vm, u8 indent)
 {
 	struct kvm_mmu *mmu = &vm->mmu;
-	uint64_t *pml4e, *pml4e_start;
-	uint64_t *pdpe, *pdpe_start;
-	uint64_t *pde, *pde_start;
-	uint64_t *pte, *pte_start;
+	u64 *pml4e, *pml4e_start;
+	u64 *pdpe, *pdpe_start;
+	u64 *pde, *pde_start;
+	u64 *pte, *pte_start;
 
 	if (!mmu->pgd_created)
 		return;
@@ -423,8 +420,8 @@ void virt_arch_dump(FILE *stream, struct kvm_vm *vm, uint8_t indent)
 	fprintf(stream, "%*s      index hvaddr         gpaddr         "
 		"addr         w exec dirty\n",
 		indent, "");
-	pml4e_start = (uint64_t *) addr_gpa2hva(vm, mmu->pgd);
-	for (uint16_t n1 = 0; n1 <= 0x1ffu; n1++) {
+	pml4e_start = (u64 *)addr_gpa2hva(vm, mmu->pgd);
+	for (u16 n1 = 0; n1 <= 0x1ffu; n1++) {
 		pml4e = &pml4e_start[n1];
 		if (!is_present_pte(mmu, pml4e))
 			continue;
@@ -436,7 +433,7 @@ void virt_arch_dump(FILE *stream, struct kvm_vm *vm, uint8_t indent)
 			is_writable_pte(mmu, pml4e), is_nx_pte(mmu, pml4e));
 
 		pdpe_start = addr_gpa2hva(vm, *pml4e & PHYSICAL_PAGE_MASK);
-		for (uint16_t n2 = 0; n2 <= 0x1ffu; n2++) {
+		for (u16 n2 = 0; n2 <= 0x1ffu; n2++) {
 			pdpe = &pdpe_start[n2];
 			if (!is_present_pte(mmu, pdpe))
 				continue;
@@ -449,7 +446,7 @@ void virt_arch_dump(FILE *stream, struct kvm_vm *vm, uint8_t indent)
 				is_nx_pte(mmu, pdpe));
 
 			pde_start = addr_gpa2hva(vm, *pdpe & PHYSICAL_PAGE_MASK);
-			for (uint16_t n3 = 0; n3 <= 0x1ffu; n3++) {
+			for (u16 n3 = 0; n3 <= 0x1ffu; n3++) {
 				pde = &pde_start[n3];
 				if (!is_present_pte(mmu, pde))
 					continue;
@@ -461,7 +458,7 @@ void virt_arch_dump(FILE *stream, struct kvm_vm *vm, uint8_t indent)
 					is_nx_pte(mmu, pde));
 
 				pte_start = addr_gpa2hva(vm, *pde & PHYSICAL_PAGE_MASK);
-				for (uint16_t n4 = 0; n4 <= 0x1ffu; n4++) {
+				for (u16 n4 = 0; n4 <= 0x1ffu; n4++) {
 					pte = &pte_start[n4];
 					if (!is_present_pte(mmu, pte))
 						continue;
@@ -475,10 +472,10 @@ void virt_arch_dump(FILE *stream, struct kvm_vm *vm, uint8_t indent)
 						is_writable_pte(mmu, pte),
 						is_nx_pte(mmu, pte),
 						is_dirty_pte(mmu, pte),
-						((uint64_t) n1 << 27)
-							| ((uint64_t) n2 << 18)
-							| ((uint64_t) n3 << 9)
-							| ((uint64_t) n4));
+						((u64)n1 << 27)
+							| ((u64)n2 << 18)
+							| ((u64)n3 << 9)
+							| ((u64)n4));
 				}
 			}
 		}
@@ -498,26 +495,24 @@ bool kvm_cpu_has_tdp(void)
 	return kvm_cpu_has_ept() || kvm_cpu_has_npt();
 }
 
-void __tdp_map(struct kvm_vm *vm, uint64_t nested_paddr, uint64_t paddr,
-	       uint64_t size, int level)
+void __tdp_map(struct kvm_vm *vm, gpa_t l2_gpa, gpa_t gpa, u64 size, int level)
 {
 	size_t page_size = PG_LEVEL_SIZE(level);
 	size_t npages = size / page_size;
 
-	TEST_ASSERT(nested_paddr + size > nested_paddr, "Vaddr overflow");
-	TEST_ASSERT(paddr + size > paddr, "Paddr overflow");
+	TEST_ASSERT(l2_gpa + size > l2_gpa, "L2 GPA overflow");
+	TEST_ASSERT(gpa + size > gpa, "GPA overflow");
 
 	while (npages--) {
-		__virt_pg_map(vm, &vm->stage2_mmu, nested_paddr, paddr, level);
-		nested_paddr += page_size;
-		paddr += page_size;
+		__virt_pg_map(vm, &vm->stage2_mmu, l2_gpa, gpa, level);
+		l2_gpa += page_size;
+		gpa += page_size;
 	}
 }
 
-void tdp_map(struct kvm_vm *vm, uint64_t nested_paddr, uint64_t paddr,
-	     uint64_t size)
+void tdp_map(struct kvm_vm *vm, gpa_t l2_gpa, gpa_t gpa, u64 size)
 {
-	__tdp_map(vm, nested_paddr, paddr, size, PG_LEVEL_4K);
+	__tdp_map(vm, l2_gpa, gpa, size, PG_LEVEL_4K);
 }
 
 /* Prepare an identity extended page table that maps all the
@@ -525,7 +520,7 @@ void tdp_map(struct kvm_vm *vm, uint64_t nested_paddr, uint64_t paddr,
  */
 void tdp_identity_map_default_memslots(struct kvm_vm *vm)
 {
-	uint32_t s, memslot = 0;
+	u32 s, memslot = 0;
 	sparsebit_idx_t i, last;
 	struct userspace_mem_region *region = memslot2region(vm, memslot);
 
@@ -540,13 +535,13 @@ void tdp_identity_map_default_memslots(struct kvm_vm *vm)
 		if (i > last)
 			break;
 
-		tdp_map(vm, (uint64_t)i << vm->page_shift,
-			(uint64_t)i << vm->page_shift, 1 << vm->page_shift);
+		tdp_map(vm, (u64)i << vm->page_shift,
+			(u64)i << vm->page_shift, 1 << vm->page_shift);
 	}
 }
 
 /* Identity map a region with 1GiB Pages. */
-void tdp_identity_map_1g(struct kvm_vm *vm, uint64_t addr, uint64_t size)
+void tdp_identity_map_1g(struct kvm_vm *vm, u64 addr, u64 size)
 {
 	__tdp_map(vm, addr, addr, size, PG_LEVEL_1G);
 }
@@ -618,10 +613,10 @@ static void kvm_seg_set_kernel_data_64bit(struct kvm_segment *segp)
 	segp->present = true;
 }
 
-vm_paddr_t addr_arch_gva2gpa(struct kvm_vm *vm, vm_vaddr_t gva)
+gpa_t addr_arch_gva2gpa(struct kvm_vm *vm, gva_t gva)
 {
 	int level = PG_LEVEL_NONE;
-	uint64_t *pte = __vm_get_page_table_entry(vm, &vm->mmu, gva, &level);
+	u64 *pte = __vm_get_page_table_entry(vm, &vm->mmu, gva, &level);
 
 	TEST_ASSERT(is_present_pte(&vm->mmu, pte),
 		    "Leaf PTE not PRESENT for gva: 0x%08lx", gva);
@@ -633,7 +628,7 @@ vm_paddr_t addr_arch_gva2gpa(struct kvm_vm *vm, vm_vaddr_t gva)
 	return vm_untag_gpa(vm, PTE_GET_PA(*pte)) | (gva & ~HUGEPAGE_MASK(level));
 }
 
-static void kvm_seg_set_tss_64bit(vm_vaddr_t base, struct kvm_segment *segp)
+static void kvm_seg_set_tss_64bit(gva_t base, struct kvm_segment *segp)
 {
 	memset(segp, 0, sizeof(*segp));
 	segp->base = base;
@@ -746,16 +741,16 @@ static void vm_init_descriptor_tables(struct kvm_vm *vm)
 	struct kvm_segment seg;
 	int i;
 
-	vm->arch.gdt = __vm_vaddr_alloc_page(vm, MEM_REGION_DATA);
-	vm->arch.idt = __vm_vaddr_alloc_page(vm, MEM_REGION_DATA);
-	vm->handlers = __vm_vaddr_alloc_page(vm, MEM_REGION_DATA);
-	vm->arch.tss = __vm_vaddr_alloc_page(vm, MEM_REGION_DATA);
+	vm->arch.gdt = __vm_alloc_page(vm, MEM_REGION_DATA);
+	vm->arch.idt = __vm_alloc_page(vm, MEM_REGION_DATA);
+	vm->handlers = __vm_alloc_page(vm, MEM_REGION_DATA);
+	vm->arch.tss = __vm_alloc_page(vm, MEM_REGION_DATA);
 
 	/* Handlers have the same address in both address spaces.*/
 	for (i = 0; i < NUM_INTERRUPTS; i++)
 		set_idt_entry(vm, i, (unsigned long)(&idt_handlers)[i], 0, KERNEL_CS);
 
-	*(vm_vaddr_t *)addr_gva2hva(vm, (vm_vaddr_t)(&exception_handlers)) = vm->handlers;
+	*(gva_t *)addr_gva2hva(vm, (gva_t)(&exception_handlers)) = vm->handlers;
 
 	kvm_seg_set_kernel_code_64bit(&seg);
 	kvm_seg_fill_gdt_64bit(vm, &seg);
@@ -770,9 +765,9 @@ static void vm_init_descriptor_tables(struct kvm_vm *vm)
 void vm_install_exception_handler(struct kvm_vm *vm, int vector,
 			       void (*handler)(struct ex_regs *))
 {
-	vm_vaddr_t *handlers = (vm_vaddr_t *)addr_gva2hva(vm, vm->handlers);
+	gva_t *handlers = (gva_t *)addr_gva2hva(vm, vm->handlers);
 
-	handlers[vector] = (vm_vaddr_t)handler;
+	handlers[vector] = (gva_t)handler;
 }
 
 void assert_on_unhandled_exception(struct kvm_vcpu *vcpu)
@@ -821,18 +816,17 @@ void vcpu_arch_set_entry_point(struct kvm_vcpu *vcpu, void *guest_code)
 	vcpu_regs_set(vcpu, &regs);
 }
 
-struct kvm_vcpu *vm_arch_vcpu_add(struct kvm_vm *vm, uint32_t vcpu_id)
+struct kvm_vcpu *vm_arch_vcpu_add(struct kvm_vm *vm, u32 vcpu_id)
 {
 	struct kvm_mp_state mp_state;
 	struct kvm_regs regs;
-	vm_vaddr_t stack_vaddr;
+	gva_t stack_gva;
 	struct kvm_vcpu *vcpu;
 
-	stack_vaddr = __vm_vaddr_alloc(vm, DEFAULT_STACK_PGS * getpagesize(),
-				       DEFAULT_GUEST_STACK_VADDR_MIN,
-				       MEM_REGION_DATA);
+	stack_gva = __vm_alloc(vm, DEFAULT_STACK_PGS * getpagesize(),
+			       DEFAULT_GUEST_STACK_VADDR_MIN, MEM_REGION_DATA);
 
-	stack_vaddr += DEFAULT_STACK_PGS * getpagesize();
+	stack_gva += DEFAULT_STACK_PGS * getpagesize();
 
 	/*
 	 * Align stack to match calling sequence requirements in section "The
@@ -843,9 +837,9 @@ struct kvm_vcpu *vm_arch_vcpu_add(struct kvm_vm *vm, uint32_t vcpu_id)
 	 * If this code is ever used to launch a vCPU with 32-bit entry point it
 	 * may need to subtract 4 bytes instead of 8 bytes.
 	 */
-	TEST_ASSERT(IS_ALIGNED(stack_vaddr, PAGE_SIZE),
-		    "__vm_vaddr_alloc() did not provide a page-aligned address");
-	stack_vaddr -= 8;
+	TEST_ASSERT(IS_ALIGNED(stack_gva, PAGE_SIZE),
+		    "__vm_alloc() did not provide a page-aligned address");
+	stack_gva -= 8;
 
 	vcpu = __vm_vcpu_add(vm, vcpu_id);
 	vcpu_init_cpuid(vcpu, kvm_get_supported_cpuid());
@@ -855,7 +849,7 @@ struct kvm_vcpu *vm_arch_vcpu_add(struct kvm_vm *vm, uint32_t vcpu_id)
 	/* Setup guest general purpose registers */
 	vcpu_regs_get(vcpu, &regs);
 	regs.rflags = regs.rflags | 0x2;
-	regs.rsp = stack_vaddr;
+	regs.rsp = stack_gva;
 	vcpu_regs_set(vcpu, &regs);
 
 	/* Setup the MP state */
@@ -872,7 +866,7 @@ struct kvm_vcpu *vm_arch_vcpu_add(struct kvm_vm *vm, uint32_t vcpu_id)
 	return vcpu;
 }
 
-struct kvm_vcpu *vm_arch_vcpu_recreate(struct kvm_vm *vm, uint32_t vcpu_id)
+struct kvm_vcpu *vm_arch_vcpu_recreate(struct kvm_vm *vm, u32 vcpu_id)
 {
 	struct kvm_vcpu *vcpu = __vm_vcpu_add(vm, vcpu_id);
 
@@ -907,9 +901,9 @@ const struct kvm_cpuid2 *kvm_get_supported_cpuid(void)
 	return kvm_supported_cpuid;
 }
 
-static uint32_t __kvm_cpu_has(const struct kvm_cpuid2 *cpuid,
-			      uint32_t function, uint32_t index,
-			      uint8_t reg, uint8_t lo, uint8_t hi)
+static u32 __kvm_cpu_has(const struct kvm_cpuid2 *cpuid,
+			 u32 function, u32 index,
+			 u8 reg, u8 lo, u8 hi)
 {
 	const struct kvm_cpuid_entry2 *entry;
 	int i;
@@ -936,14 +930,14 @@ bool kvm_cpuid_has(const struct kvm_cpuid2 *cpuid,
 			     feature.reg, feature.bit, feature.bit);
 }
 
-uint32_t kvm_cpuid_property(const struct kvm_cpuid2 *cpuid,
-			    struct kvm_x86_cpu_property property)
+u32 kvm_cpuid_property(const struct kvm_cpuid2 *cpuid,
+		       struct kvm_x86_cpu_property property)
 {
 	return __kvm_cpu_has(cpuid, property.function, property.index,
 			     property.reg, property.lo_bit, property.hi_bit);
 }
 
-uint64_t kvm_get_feature_msr(uint64_t msr_index)
+u64 kvm_get_feature_msr(u64 msr_index)
 {
 	struct {
 		struct kvm_msrs header;
@@ -962,7 +956,7 @@ uint64_t kvm_get_feature_msr(uint64_t msr_index)
 	return buffer.entry.data;
 }
 
-void __vm_xsave_require_permission(uint64_t xfeature, const char *name)
+void __vm_xsave_require_permission(u64 xfeature, const char *name)
 {
 	int kvm_fd;
 	u64 bitmask;
@@ -1019,7 +1013,7 @@ void vcpu_init_cpuid(struct kvm_vcpu *vcpu, const struct kvm_cpuid2 *cpuid)
 
 void vcpu_set_cpuid_property(struct kvm_vcpu *vcpu,
 			     struct kvm_x86_cpu_property property,
-			     uint32_t value)
+			     u32 value)
 {
 	struct kvm_cpuid_entry2 *entry;
 
@@ -1034,7 +1028,7 @@ void vcpu_set_cpuid_property(struct kvm_vcpu *vcpu,
 	TEST_ASSERT_EQ(kvm_cpuid_property(vcpu->cpuid, property), value);
 }
 
-void vcpu_clear_cpuid_entry(struct kvm_vcpu *vcpu, uint32_t function)
+void vcpu_clear_cpuid_entry(struct kvm_vcpu *vcpu, u32 function)
 {
 	struct kvm_cpuid_entry2 *entry = vcpu_get_cpuid_entry(vcpu, function);
 
@@ -1063,7 +1057,7 @@ void vcpu_set_or_clear_cpuid_feature(struct kvm_vcpu *vcpu,
 	vcpu_set_cpuid(vcpu);
 }
 
-uint64_t vcpu_get_msr(struct kvm_vcpu *vcpu, uint64_t msr_index)
+u64 vcpu_get_msr(struct kvm_vcpu *vcpu, u64 msr_index)
 {
 	struct {
 		struct kvm_msrs header;
@@ -1078,7 +1072,7 @@ uint64_t vcpu_get_msr(struct kvm_vcpu *vcpu, uint64_t msr_index)
 	return buffer.entry.data;
 }
 
-int _vcpu_set_msr(struct kvm_vcpu *vcpu, uint64_t msr_index, uint64_t msr_value)
+int _vcpu_set_msr(struct kvm_vcpu *vcpu, u64 msr_index, u64 msr_value)
 {
 	struct {
 		struct kvm_msrs header;
@@ -1106,28 +1100,28 @@ void vcpu_args_set(struct kvm_vcpu *vcpu, unsigned int num, ...)
 	vcpu_regs_get(vcpu, &regs);
 
 	if (num >= 1)
-		regs.rdi = va_arg(ap, uint64_t);
+		regs.rdi = va_arg(ap, u64);
 
 	if (num >= 2)
-		regs.rsi = va_arg(ap, uint64_t);
+		regs.rsi = va_arg(ap, u64);
 
 	if (num >= 3)
-		regs.rdx = va_arg(ap, uint64_t);
+		regs.rdx = va_arg(ap, u64);
 
 	if (num >= 4)
-		regs.rcx = va_arg(ap, uint64_t);
+		regs.rcx = va_arg(ap, u64);
 
 	if (num >= 5)
-		regs.r8 = va_arg(ap, uint64_t);
+		regs.r8 = va_arg(ap, u64);
 
 	if (num >= 6)
-		regs.r9 = va_arg(ap, uint64_t);
+		regs.r9 = va_arg(ap, u64);
 
 	vcpu_regs_set(vcpu, &regs);
 	va_end(ap);
 }
 
-void vcpu_arch_dump(FILE *stream, struct kvm_vcpu *vcpu, uint8_t indent)
+void vcpu_arch_dump(FILE *stream, struct kvm_vcpu *vcpu, u8 indent)
 {
 	struct kvm_regs regs;
 	struct kvm_sregs sregs;
@@ -1196,7 +1190,7 @@ const struct kvm_msr_list *kvm_get_feature_msr_index_list(void)
 	return list;
 }
 
-bool kvm_msr_is_in_save_restore_list(uint32_t msr_index)
+bool kvm_msr_is_in_save_restore_list(u32 msr_index)
 {
 	const struct kvm_msr_list *list = kvm_get_msr_index_list();
 	int i;
@@ -1327,7 +1321,7 @@ void kvm_init_vm_address_properties(struct kvm_vm *vm)
 }
 
 const struct kvm_cpuid_entry2 *get_cpuid_entry(const struct kvm_cpuid2 *cpuid,
-					       uint32_t function, uint32_t index)
+					       u32 function, u32 index)
 {
 	int i;
 
@@ -1344,7 +1338,7 @@ const struct kvm_cpuid_entry2 *get_cpuid_entry(const struct kvm_cpuid2 *cpuid,
 
 #define X86_HYPERCALL(inputs...)					\
 ({									\
-	uint64_t r;							\
+	u64 r;							\
 									\
 	asm volatile("test %[use_vmmcall], %[use_vmmcall]\n\t"		\
 		     "jnz 1f\n\t"					\
@@ -1359,18 +1353,17 @@ const struct kvm_cpuid_entry2 *get_cpuid_entry(const struct kvm_cpuid2 *cpuid,
 	r;								\
 })
 
-uint64_t kvm_hypercall(uint64_t nr, uint64_t a0, uint64_t a1, uint64_t a2,
-		       uint64_t a3)
+u64 kvm_hypercall(u64 nr, u64 a0, u64 a1, u64 a2, u64 a3)
 {
 	return X86_HYPERCALL("a"(nr), "b"(a0), "c"(a1), "d"(a2), "S"(a3));
 }
 
-uint64_t __xen_hypercall(uint64_t nr, uint64_t a0, void *a1)
+u64 __xen_hypercall(u64 nr, u64 a0, void *a1)
 {
 	return X86_HYPERCALL("a"(nr), "D"(a0), "S"(a1));
 }
 
-void xen_hypercall(uint64_t nr, uint64_t a0, void *a1)
+void xen_hypercall(u64 nr, u64 a0, void *a1)
 {
 	GUEST_ASSERT(!__xen_hypercall(nr, a0, a1));
 }
@@ -1379,7 +1372,7 @@ unsigned long vm_compute_max_gfn(struct kvm_vm *vm)
 {
 	const unsigned long num_ht_pages = 12 << (30 - vm->page_shift); /* 12 GiB */
 	unsigned long ht_gfn, max_gfn, max_pfn;
-	uint8_t maxphyaddr, guest_maxphyaddr;
+	u8 maxphyaddr, guest_maxphyaddr;
 
 	/*
 	 * Use "guest MAXPHYADDR" from KVM if it's available.  Guest MAXPHYADDR
@@ -1453,8 +1446,7 @@ bool kvm_arch_has_default_irqchip(void)
 	return true;
 }
 
-void setup_smram(struct kvm_vm *vm, struct kvm_vcpu *vcpu,
-		 uint64_t smram_gpa,
+void setup_smram(struct kvm_vm *vm, struct kvm_vcpu *vcpu, u64 smram_gpa,
 		 const void *smi_handler, size_t handler_size)
 {
 	vm_userspace_mem_region_add(vm, VM_MEM_SRC_ANONYMOUS, smram_gpa,
diff --git a/tools/testing/selftests/kvm/lib/x86/sev.c b/tools/testing/selftests/kvm/lib/x86/sev.c
index c3a9838f4806..93f916903461 100644
--- a/tools/testing/selftests/kvm/lib/x86/sev.c
+++ b/tools/testing/selftests/kvm/lib/x86/sev.c
@@ -15,10 +15,10 @@
  * expression would cause us to quit the loop.
  */
 static void encrypt_region(struct kvm_vm *vm, struct userspace_mem_region *region,
-			   uint8_t page_type, bool private)
+			   u8 page_type, bool private)
 {
 	const struct sparsebit *protected_phy_pages = region->protected_phy_pages;
-	const vm_paddr_t gpa_base = region->region.guest_phys_addr;
+	const gpa_t gpa_base = region->region.guest_phys_addr;
 	const sparsebit_idx_t lowest_page_in_region = gpa_base >> vm->page_shift;
 	sparsebit_idx_t i, j;
 
@@ -29,15 +29,15 @@ static void encrypt_region(struct kvm_vm *vm, struct userspace_mem_region *regio
 		sev_register_encrypted_memory(vm, region);
 
 	sparsebit_for_each_set_range(protected_phy_pages, i, j) {
-		const uint64_t size = (j - i + 1) * vm->page_size;
-		const uint64_t offset = (i - lowest_page_in_region) * vm->page_size;
+		const u64 size = (j - i + 1) * vm->page_size;
+		const u64 offset = (i - lowest_page_in_region) * vm->page_size;
 
 		if (private)
 			vm_mem_set_private(vm, gpa_base + offset, size);
 
 		if (is_sev_snp_vm(vm))
 			snp_launch_update_data(vm, gpa_base + offset,
-					       (uint64_t)addr_gpa2hva(vm, gpa_base + offset),
+					       (u64)addr_gpa2hva(vm, gpa_base + offset),
 					       size, page_type);
 		else
 			sev_launch_update_data(vm, gpa_base + offset, size);
@@ -79,7 +79,7 @@ void snp_vm_init(struct kvm_vm *vm)
 	vm_sev_ioctl(vm, KVM_SEV_INIT2, &init);
 }
 
-void sev_vm_launch(struct kvm_vm *vm, uint32_t policy)
+void sev_vm_launch(struct kvm_vm *vm, u32 policy)
 {
 	struct kvm_sev_launch_start launch_start = {
 		.policy = policy,
@@ -103,7 +103,7 @@ void sev_vm_launch(struct kvm_vm *vm, uint32_t policy)
 	vm->arch.is_pt_protected = true;
 }
 
-void sev_vm_launch_measure(struct kvm_vm *vm, uint8_t *measurement)
+void sev_vm_launch_measure(struct kvm_vm *vm, u8 *measurement)
 {
 	struct kvm_sev_launch_measure launch_measure;
 	struct kvm_sev_guest_status guest_status;
@@ -131,7 +131,7 @@ void sev_vm_launch_finish(struct kvm_vm *vm)
 	TEST_ASSERT_EQ(status.state, SEV_GUEST_STATE_RUNNING);
 }
 
-void snp_vm_launch_start(struct kvm_vm *vm, uint64_t policy)
+void snp_vm_launch_start(struct kvm_vm *vm, u64 policy)
 {
 	struct kvm_sev_snp_launch_start launch_start = {
 		.policy = policy,
@@ -158,7 +158,7 @@ void snp_vm_launch_finish(struct kvm_vm *vm)
 	vm_sev_ioctl(vm, KVM_SEV_SNP_LAUNCH_FINISH, &launch_finish);
 }
 
-struct kvm_vm *vm_sev_create_with_one_vcpu(uint32_t type, void *guest_code,
+struct kvm_vm *vm_sev_create_with_one_vcpu(u32 type, void *guest_code,
 					   struct kvm_vcpu **cpu)
 {
 	struct vm_shape shape = {
@@ -174,7 +174,7 @@ struct kvm_vm *vm_sev_create_with_one_vcpu(uint32_t type, void *guest_code,
 	return vm;
 }
 
-void vm_sev_launch(struct kvm_vm *vm, uint64_t policy, uint8_t *measurement)
+void vm_sev_launch(struct kvm_vm *vm, u64 policy, u8 *measurement)
 {
 	if (is_sev_snp_vm(vm)) {
 		vm_enable_cap(vm, KVM_CAP_EXIT_HYPERCALL, BIT(KVM_HC_MAP_GPA_RANGE));
diff --git a/tools/testing/selftests/kvm/lib/x86/svm.c b/tools/testing/selftests/kvm/lib/x86/svm.c
index eb20b00112c7..3b01605ab016 100644
--- a/tools/testing/selftests/kvm/lib/x86/svm.c
+++ b/tools/testing/selftests/kvm/lib/x86/svm.c
@@ -28,20 +28,20 @@ u64 rflags;
  *   Pointer to structure with the addresses of the SVM areas.
  */
 struct svm_test_data *
-vcpu_alloc_svm(struct kvm_vm *vm, vm_vaddr_t *p_svm_gva)
+vcpu_alloc_svm(struct kvm_vm *vm, gva_t *p_svm_gva)
 {
-	vm_vaddr_t svm_gva = vm_vaddr_alloc_page(vm);
+	gva_t svm_gva = vm_alloc_page(vm);
 	struct svm_test_data *svm = addr_gva2hva(vm, svm_gva);
 
-	svm->vmcb = (void *)vm_vaddr_alloc_page(vm);
+	svm->vmcb = (void *)vm_alloc_page(vm);
 	svm->vmcb_hva = addr_gva2hva(vm, (uintptr_t)svm->vmcb);
 	svm->vmcb_gpa = addr_gva2gpa(vm, (uintptr_t)svm->vmcb);
 
-	svm->save_area = (void *)vm_vaddr_alloc_page(vm);
+	svm->save_area = (void *)vm_alloc_page(vm);
 	svm->save_area_hva = addr_gva2hva(vm, (uintptr_t)svm->save_area);
 	svm->save_area_gpa = addr_gva2gpa(vm, (uintptr_t)svm->save_area);
 
-	svm->msr = (void *)vm_vaddr_alloc_page(vm);
+	svm->msr = (void *)vm_alloc_page(vm);
 	svm->msr_hva = addr_gva2hva(vm, (uintptr_t)svm->msr);
 	svm->msr_gpa = addr_gva2gpa(vm, (uintptr_t)svm->msr);
 	memset(svm->msr_hva, 0, getpagesize());
@@ -84,14 +84,14 @@ void vm_enable_npt(struct kvm_vm *vm)
 void generic_svm_setup(struct svm_test_data *svm, void *guest_rip, void *guest_rsp)
 {
 	struct vmcb *vmcb = svm->vmcb;
-	uint64_t vmcb_gpa = svm->vmcb_gpa;
+	u64 vmcb_gpa = svm->vmcb_gpa;
 	struct vmcb_save_area *save = &vmcb->save;
 	struct vmcb_control_area *ctrl = &vmcb->control;
 	u32 data_seg_attr = 3 | SVM_SELECTOR_S_MASK | SVM_SELECTOR_P_MASK
 	      | SVM_SELECTOR_DB_MASK | SVM_SELECTOR_G_MASK;
 	u32 code_seg_attr = 9 | SVM_SELECTOR_S_MASK | SVM_SELECTOR_P_MASK
 		| SVM_SELECTOR_L_MASK | SVM_SELECTOR_G_MASK;
-	uint64_t efer;
+	u64 efer;
 
 	efer = rdmsr(MSR_EFER);
 	wrmsr(MSR_EFER, efer | EFER_SVME);
@@ -158,7 +158,7 @@ void generic_svm_setup(struct svm_test_data *svm, void *guest_rip, void *guest_r
  * for now. registers involved in LOAD/SAVE_GPR_C are eventually
  * unmodified so they do not need to be in the clobber list.
  */
-void run_guest(struct vmcb *vmcb, uint64_t vmcb_gpa)
+void run_guest(struct vmcb *vmcb, u64 vmcb_gpa)
 {
 	asm volatile (
 		"vmload %[vmcb_gpa]\n\t"
diff --git a/tools/testing/selftests/kvm/lib/x86/ucall.c b/tools/testing/selftests/kvm/lib/x86/ucall.c
index 1265cecc7dd1..e7dd5791959b 100644
--- a/tools/testing/selftests/kvm/lib/x86/ucall.c
+++ b/tools/testing/selftests/kvm/lib/x86/ucall.c
@@ -6,9 +6,9 @@
  */
 #include "kvm_util.h"
 
-#define UCALL_PIO_PORT ((uint16_t)0x1000)
+#define UCALL_PIO_PORT ((u16)0x1000)
 
-void ucall_arch_do_ucall(vm_vaddr_t uc)
+void ucall_arch_do_ucall(gva_t uc)
 {
 	/*
 	 * FIXME: Revert this hack (the entire commit that added it) once nVMX
diff --git a/tools/testing/selftests/kvm/lib/x86/vmx.c b/tools/testing/selftests/kvm/lib/x86/vmx.c
index c87b340362a9..67642759e4a0 100644
--- a/tools/testing/selftests/kvm/lib/x86/vmx.c
+++ b/tools/testing/selftests/kvm/lib/x86/vmx.c
@@ -27,7 +27,7 @@ struct hv_vp_assist_page *current_vp_assist;
 
 int vcpu_enable_evmcs(struct kvm_vcpu *vcpu)
 {
-	uint16_t evmcs_ver;
+	u16 evmcs_ver;
 
 	vcpu_enable_cap(vcpu, KVM_CAP_HYPERV_ENLIGHTENED_VMCS,
 			(unsigned long)&evmcs_ver);
@@ -79,39 +79,39 @@ void vm_enable_ept(struct kvm_vm *vm)
  *   Pointer to structure with the addresses of the VMX areas.
  */
 struct vmx_pages *
-vcpu_alloc_vmx(struct kvm_vm *vm, vm_vaddr_t *p_vmx_gva)
+vcpu_alloc_vmx(struct kvm_vm *vm, gva_t *p_vmx_gva)
 {
-	vm_vaddr_t vmx_gva = vm_vaddr_alloc_page(vm);
+	gva_t vmx_gva = vm_alloc_page(vm);
 	struct vmx_pages *vmx = addr_gva2hva(vm, vmx_gva);
 
 	/* Setup of a region of guest memory for the vmxon region. */
-	vmx->vmxon = (void *)vm_vaddr_alloc_page(vm);
+	vmx->vmxon = (void *)vm_alloc_page(vm);
 	vmx->vmxon_hva = addr_gva2hva(vm, (uintptr_t)vmx->vmxon);
 	vmx->vmxon_gpa = addr_gva2gpa(vm, (uintptr_t)vmx->vmxon);
 
 	/* Setup of a region of guest memory for a vmcs. */
-	vmx->vmcs = (void *)vm_vaddr_alloc_page(vm);
+	vmx->vmcs = (void *)vm_alloc_page(vm);
 	vmx->vmcs_hva = addr_gva2hva(vm, (uintptr_t)vmx->vmcs);
 	vmx->vmcs_gpa = addr_gva2gpa(vm, (uintptr_t)vmx->vmcs);
 
 	/* Setup of a region of guest memory for the MSR bitmap. */
-	vmx->msr = (void *)vm_vaddr_alloc_page(vm);
+	vmx->msr = (void *)vm_alloc_page(vm);
 	vmx->msr_hva = addr_gva2hva(vm, (uintptr_t)vmx->msr);
 	vmx->msr_gpa = addr_gva2gpa(vm, (uintptr_t)vmx->msr);
 	memset(vmx->msr_hva, 0, getpagesize());
 
 	/* Setup of a region of guest memory for the shadow VMCS. */
-	vmx->shadow_vmcs = (void *)vm_vaddr_alloc_page(vm);
+	vmx->shadow_vmcs = (void *)vm_alloc_page(vm);
 	vmx->shadow_vmcs_hva = addr_gva2hva(vm, (uintptr_t)vmx->shadow_vmcs);
 	vmx->shadow_vmcs_gpa = addr_gva2gpa(vm, (uintptr_t)vmx->shadow_vmcs);
 
 	/* Setup of a region of guest memory for the VMREAD and VMWRITE bitmaps. */
-	vmx->vmread = (void *)vm_vaddr_alloc_page(vm);
+	vmx->vmread = (void *)vm_alloc_page(vm);
 	vmx->vmread_hva = addr_gva2hva(vm, (uintptr_t)vmx->vmread);
 	vmx->vmread_gpa = addr_gva2gpa(vm, (uintptr_t)vmx->vmread);
 	memset(vmx->vmread_hva, 0, getpagesize());
 
-	vmx->vmwrite = (void *)vm_vaddr_alloc_page(vm);
+	vmx->vmwrite = (void *)vm_alloc_page(vm);
 	vmx->vmwrite_hva = addr_gva2hva(vm, (uintptr_t)vmx->vmwrite);
 	vmx->vmwrite_gpa = addr_gva2gpa(vm, (uintptr_t)vmx->vmwrite);
 	memset(vmx->vmwrite_hva, 0, getpagesize());
@@ -125,8 +125,8 @@ vcpu_alloc_vmx(struct kvm_vm *vm, vm_vaddr_t *p_vmx_gva)
 
 bool prepare_for_vmx_operation(struct vmx_pages *vmx)
 {
-	uint64_t feature_control;
-	uint64_t required;
+	u64 feature_control;
+	u64 required;
 	unsigned long cr0;
 	unsigned long cr4;
 
@@ -160,7 +160,7 @@ bool prepare_for_vmx_operation(struct vmx_pages *vmx)
 		wrmsr(MSR_IA32_FEAT_CTL, feature_control | required);
 
 	/* Enter VMX root operation. */
-	*(uint32_t *)(vmx->vmxon) = vmcs_revision();
+	*(u32 *)(vmx->vmxon) = vmcs_revision();
 	if (vmxon(vmx->vmxon_gpa))
 		return false;
 
@@ -170,7 +170,7 @@ bool prepare_for_vmx_operation(struct vmx_pages *vmx)
 bool load_vmcs(struct vmx_pages *vmx)
 {
 	/* Load a VMCS. */
-	*(uint32_t *)(vmx->vmcs) = vmcs_revision();
+	*(u32 *)(vmx->vmcs) = vmcs_revision();
 	if (vmclear(vmx->vmcs_gpa))
 		return false;
 
@@ -178,14 +178,14 @@ bool load_vmcs(struct vmx_pages *vmx)
 		return false;
 
 	/* Setup shadow VMCS, do not load it yet. */
-	*(uint32_t *)(vmx->shadow_vmcs) = vmcs_revision() | 0x80000000ul;
+	*(u32 *)(vmx->shadow_vmcs) = vmcs_revision() | 0x80000000ul;
 	if (vmclear(vmx->shadow_vmcs_gpa))
 		return false;
 
 	return true;
 }
 
-static bool ept_vpid_cap_supported(uint64_t mask)
+static bool ept_vpid_cap_supported(u64 mask)
 {
 	return rdmsr(MSR_IA32_VMX_EPT_VPID_CAP) & mask;
 }
@@ -200,7 +200,7 @@ bool ept_1g_pages_supported(void)
  */
 static inline void init_vmcs_control_fields(struct vmx_pages *vmx)
 {
-	uint32_t sec_exec_ctl = 0;
+	u32 sec_exec_ctl = 0;
 
 	vmwrite(VIRTUAL_PROCESSOR_ID, 0);
 	vmwrite(POSTED_INTR_NV, 0);
@@ -208,7 +208,7 @@ static inline void init_vmcs_control_fields(struct vmx_pages *vmx)
 	vmwrite(PIN_BASED_VM_EXEC_CONTROL, rdmsr(MSR_IA32_VMX_TRUE_PINBASED_CTLS));
 
 	if (vmx->eptp_gpa) {
-		uint64_t eptp = vmx->eptp_gpa | EPTP_WB | EPTP_PWL_4;
+		u64 eptp = vmx->eptp_gpa | EPTP_WB | EPTP_PWL_4;
 
 		TEST_ASSERT((vmx->eptp_gpa & ~PHYSICAL_PAGE_MASK) == 0,
 			    "Illegal bits set in vmx->eptp_gpa");
@@ -259,7 +259,7 @@ static inline void init_vmcs_control_fields(struct vmx_pages *vmx)
  */
 static inline void init_vmcs_host_state(void)
 {
-	uint32_t exit_controls = vmreadz(VM_EXIT_CONTROLS);
+	u32 exit_controls = vmreadz(VM_EXIT_CONTROLS);
 
 	vmwrite(HOST_ES_SELECTOR, get_es());
 	vmwrite(HOST_CS_SELECTOR, get_cs());
@@ -358,8 +358,8 @@ static inline void init_vmcs_guest_state(void *rip, void *rsp)
 	vmwrite(GUEST_GDTR_BASE, vmreadz(HOST_GDTR_BASE));
 	vmwrite(GUEST_IDTR_BASE, vmreadz(HOST_IDTR_BASE));
 	vmwrite(GUEST_DR7, 0x400);
-	vmwrite(GUEST_RSP, (uint64_t)rsp);
-	vmwrite(GUEST_RIP, (uint64_t)rip);
+	vmwrite(GUEST_RSP, (u64)rsp);
+	vmwrite(GUEST_RIP, (u64)rip);
 	vmwrite(GUEST_RFLAGS, 2);
 	vmwrite(GUEST_PENDING_DBG_EXCEPTIONS, 0);
 	vmwrite(GUEST_SYSENTER_ESP, vmreadz(HOST_IA32_SYSENTER_ESP));
@@ -375,7 +375,7 @@ void prepare_vmcs(struct vmx_pages *vmx, void *guest_rip, void *guest_rsp)
 
 bool kvm_cpu_has_ept(void)
 {
-	uint64_t ctrl;
+	u64 ctrl;
 
 	if (!kvm_cpu_has(X86_FEATURE_VMX))
 		return false;
@@ -390,7 +390,7 @@ bool kvm_cpu_has_ept(void)
 
 void prepare_virtualize_apic_accesses(struct vmx_pages *vmx, struct kvm_vm *vm)
 {
-	vmx->apic_access = (void *)vm_vaddr_alloc_page(vm);
+	vmx->apic_access = (void *)vm_alloc_page(vm);
 	vmx->apic_access_hva = addr_gva2hva(vm, (uintptr_t)vmx->apic_access);
 	vmx->apic_access_gpa = addr_gva2gpa(vm, (uintptr_t)vmx->apic_access);
 }
diff --git a/tools/testing/selftests/kvm/loongarch/arch_timer.c b/tools/testing/selftests/kvm/loongarch/arch_timer.c
index 355ecac30954..a7279ded8518 100644
--- a/tools/testing/selftests/kvm/loongarch/arch_timer.c
+++ b/tools/testing/selftests/kvm/loongarch/arch_timer.c
@@ -27,8 +27,8 @@ static void do_idle(void)
 static void guest_irq_handler(struct ex_regs *regs)
 {
 	unsigned int intid;
-	uint32_t cpu = guest_get_vcpuid();
-	uint64_t xcnt, val, cfg, xcnt_diff_us;
+	u32 cpu = guest_get_vcpuid();
+	u64 xcnt, val, cfg, xcnt_diff_us;
 	struct test_vcpu_shared_data *shared_data = &vcpu_shared_data[cpu];
 
 	intid = !!(regs->estat & BIT(INT_TI));
@@ -62,10 +62,10 @@ static void guest_irq_handler(struct ex_regs *regs)
 	WRITE_ONCE(shared_data->nr_iter, shared_data->nr_iter + 1);
 }
 
-static void guest_test_period_timer(uint32_t cpu)
+static void guest_test_period_timer(u32 cpu)
 {
-	uint32_t irq_iter, config_iter;
-	uint64_t us;
+	u32 irq_iter, config_iter;
+	u64 us;
 	struct test_vcpu_shared_data *shared_data = &vcpu_shared_data[cpu];
 
 	shared_data->nr_iter = test_args.nr_iter;
@@ -86,10 +86,10 @@ static void guest_test_period_timer(uint32_t cpu)
 			irq_iter);
 }
 
-static void guest_test_oneshot_timer(uint32_t cpu)
+static void guest_test_oneshot_timer(u32 cpu)
 {
-	uint32_t irq_iter, config_iter;
-	uint64_t us;
+	u32 irq_iter, config_iter;
+	u64 us;
 	struct test_vcpu_shared_data *shared_data = &vcpu_shared_data[cpu];
 
 	shared_data->nr_iter = 0;
@@ -112,10 +112,10 @@ static void guest_test_oneshot_timer(uint32_t cpu)
 	}
 }
 
-static void guest_test_emulate_timer(uint32_t cpu)
+static void guest_test_emulate_timer(u32 cpu)
 {
-	uint32_t config_iter;
-	uint64_t xcnt_diff_us, us;
+	u32 config_iter;
+	u64 xcnt_diff_us, us;
 	struct test_vcpu_shared_data *shared_data = &vcpu_shared_data[cpu];
 
 	local_irq_disable();
@@ -136,9 +136,9 @@ static void guest_test_emulate_timer(uint32_t cpu)
 	local_irq_enable();
 }
 
-static void guest_time_count_test(uint32_t cpu)
+static void guest_time_count_test(u32 cpu)
 {
-	uint32_t config_iter;
+	u32 config_iter;
 	unsigned long start, end, prev, us;
 
 	/* Assuming that test case starts to run in 1 second */
@@ -165,7 +165,7 @@ static void guest_time_count_test(uint32_t cpu)
 
 static void guest_code(void)
 {
-	uint32_t cpu = guest_get_vcpuid();
+	u32 cpu = guest_get_vcpuid();
 
 	/* must run at first */
 	guest_time_count_test(cpu);
diff --git a/tools/testing/selftests/kvm/loongarch/pmu_test.c b/tools/testing/selftests/kvm/loongarch/pmu_test.c
index 88bb530e336e..ec3fefb9ea97 100644
--- a/tools/testing/selftests/kvm/loongarch/pmu_test.c
+++ b/tools/testing/selftests/kvm/loongarch/pmu_test.c
@@ -15,7 +15,7 @@ static int pmu_irq_count;
 /* Check PMU support */
 static bool has_pmu_support(void)
 {
-	uint32_t cfg6;
+	u32 cfg6;
 
 	/* Read CPUCFG6 to check PMU */
 	cfg6 = read_cpucfg(LOONGARCH_CPUCFG6);
@@ -34,7 +34,7 @@ static bool has_pmu_support(void)
 /* Dump PMU capabilities */
 static void dump_pmu_caps(void)
 {
-	uint32_t cfg6;
+	u32 cfg6;
 	int nr_counters, counter_bits;
 
 	cfg6 = read_cpucfg(LOONGARCH_CPUCFG6);
@@ -51,8 +51,8 @@ static void dump_pmu_caps(void)
 static void guest_pmu_base_test(void)
 {
 	int i;
-	uint32_t cfg6, pmnum;
-	uint64_t cnt[4];
+	u32 cfg6, pmnum;
+	u64 cnt[4];
 
 	cfg6 = read_cpucfg(LOONGARCH_CPUCFG6);
 	pmnum = (cfg6 >> 4) & 0xf;
@@ -114,7 +114,7 @@ static void guest_irq_handler(struct ex_regs *regs)
 
 static void guest_pmu_interrupt_test(void)
 {
-	uint64_t cnt;
+	u64 cnt;
 
 	csr_write(PMU_OVERFLOW - 1, LOONGARCH_CSR_PERFCNTR0);
 	csr_write(PMU_ENVENT_ENABLED | CSR_PERFCTRL_PMIE | LOONGARCH_PMU_EVENT_CYCLES, LOONGARCH_CSR_PERFCTRL0);
diff --git a/tools/testing/selftests/kvm/memslot_modification_stress_test.c b/tools/testing/selftests/kvm/memslot_modification_stress_test.c
index 3cdfa3b19b85..9c7578a098c3 100644
--- a/tools/testing/selftests/kvm/memslot_modification_stress_test.c
+++ b/tools/testing/selftests/kvm/memslot_modification_stress_test.c
@@ -30,7 +30,7 @@
 
 
 static int nr_vcpus = 1;
-static uint64_t guest_percpu_mem_size = DEFAULT_PER_VCPU_MEM_SIZE;
+static u64 guest_percpu_mem_size = DEFAULT_PER_VCPU_MEM_SIZE;
 
 static void vcpu_worker(struct memstress_vcpu_args *vcpu_args)
 {
@@ -55,10 +55,10 @@ static void vcpu_worker(struct memstress_vcpu_args *vcpu_args)
 }
 
 static void add_remove_memslot(struct kvm_vm *vm, useconds_t delay,
-			       uint64_t nr_modifications)
+			       u64 nr_modifications)
 {
-	uint64_t pages = max_t(int, vm->page_size, getpagesize()) / vm->page_size;
-	uint64_t gpa;
+	u64 pages = max_t(int, vm->page_size, getpagesize()) / vm->page_size;
+	gpa_t gpa;
 	int i;
 
 	/*
@@ -78,7 +78,7 @@ static void add_remove_memslot(struct kvm_vm *vm, useconds_t delay,
 
 struct test_params {
 	useconds_t delay;
-	uint64_t nr_iterations;
+	u64 nr_iterations;
 	bool partition_vcpu_memory_access;
 	bool disable_slot_zap_quirk;
 };
diff --git a/tools/testing/selftests/kvm/memslot_perf_test.c b/tools/testing/selftests/kvm/memslot_perf_test.c
index 5087d082c4b0..3d02db371422 100644
--- a/tools/testing/selftests/kvm/memslot_perf_test.c
+++ b/tools/testing/selftests/kvm/memslot_perf_test.c
@@ -85,17 +85,17 @@ struct vm_data {
 	struct kvm_vm *vm;
 	struct kvm_vcpu *vcpu;
 	pthread_t vcpu_thread;
-	uint32_t nslots;
-	uint64_t npages;
-	uint64_t pages_per_slot;
+	u32 nslots;
+	u64 npages;
+	u64 pages_per_slot;
 	void **hva_slots;
 	bool mmio_ok;
-	uint64_t mmio_gpa_min;
-	uint64_t mmio_gpa_max;
+	u64 mmio_gpa_min;
+	u64 mmio_gpa_max;
 };
 
 struct sync_area {
-	uint32_t    guest_page_size;
+	u32    guest_page_size;
 	atomic_bool start_flag;
 	atomic_bool exit_flag;
 	atomic_bool sync_flag;
@@ -186,12 +186,12 @@ static void wait_for_vcpu(void)
 		    "sem_timedwait() failed: %d", errno);
 }
 
-static void *vm_gpa2hva(struct vm_data *data, uint64_t gpa, uint64_t *rempages)
+static void *vm_gpa2hva(struct vm_data *data, gpa_t gpa, u64 *rempages)
 {
-	uint64_t gpage, pgoffs;
-	uint32_t slot, slotoffs;
+	gpa_t gpage, pgoffs;
+	u32 slot, slotoffs;
 	void *base;
-	uint32_t guest_page_size = data->vm->page_size;
+	u32 guest_page_size = data->vm->page_size;
 
 	TEST_ASSERT(gpa >= MEM_GPA, "Too low gpa to translate");
 	TEST_ASSERT(gpa < MEM_GPA + data->npages * guest_page_size,
@@ -200,11 +200,11 @@ static void *vm_gpa2hva(struct vm_data *data, uint64_t gpa, uint64_t *rempages)
 
 	gpage = gpa / guest_page_size;
 	pgoffs = gpa % guest_page_size;
-	slot = min(gpage / data->pages_per_slot, (uint64_t)data->nslots - 1);
+	slot = min(gpage / data->pages_per_slot, (u64)data->nslots - 1);
 	slotoffs = gpage - (slot * data->pages_per_slot);
 
 	if (rempages) {
-		uint64_t slotpages;
+		u64 slotpages;
 
 		if (slot == data->nslots - 1)
 			slotpages = data->npages - slot * data->pages_per_slot;
@@ -217,12 +217,12 @@ static void *vm_gpa2hva(struct vm_data *data, uint64_t gpa, uint64_t *rempages)
 	}
 
 	base = data->hva_slots[slot];
-	return (uint8_t *)base + slotoffs * guest_page_size + pgoffs;
+	return (u8 *)base + slotoffs * guest_page_size + pgoffs;
 }
 
-static uint64_t vm_slot2gpa(struct vm_data *data, uint32_t slot)
+static u64 vm_slot2gpa(struct vm_data *data, u32 slot)
 {
-	uint32_t guest_page_size = data->vm->page_size;
+	u32 guest_page_size = data->vm->page_size;
 
 	TEST_ASSERT(slot < data->nslots, "Too high slot number");
 
@@ -243,8 +243,8 @@ static struct vm_data *alloc_vm(void)
 	return data;
 }
 
-static bool check_slot_pages(uint32_t host_page_size, uint32_t guest_page_size,
-			     uint64_t pages_per_slot, uint64_t rempages)
+static bool check_slot_pages(u32 host_page_size, u32 guest_page_size,
+			     u64 pages_per_slot, u64 rempages)
 {
 	if (!pages_per_slot)
 		return false;
@@ -259,11 +259,11 @@ static bool check_slot_pages(uint32_t host_page_size, uint32_t guest_page_size,
 }
 
 
-static uint64_t get_max_slots(struct vm_data *data, uint32_t host_page_size)
+static u64 get_max_slots(struct vm_data *data, u32 host_page_size)
 {
-	uint32_t guest_page_size = data->vm->page_size;
-	uint64_t mempages, pages_per_slot, rempages;
-	uint64_t slots;
+	u32 guest_page_size = data->vm->page_size;
+	u64 mempages, pages_per_slot, rempages;
+	u64 slots;
 
 	mempages = data->npages;
 	slots = data->nslots;
@@ -281,13 +281,13 @@ static uint64_t get_max_slots(struct vm_data *data, uint32_t host_page_size)
 	return 0;
 }
 
-static bool prepare_vm(struct vm_data *data, int nslots, uint64_t *maxslots,
-		       void *guest_code, uint64_t mem_size,
+static bool prepare_vm(struct vm_data *data, int nslots, u64 *maxslots,
+		       void *guest_code, u64 mem_size,
 		       struct timespec *slot_runtime)
 {
-	uint64_t mempages, rempages;
-	uint64_t guest_addr;
-	uint32_t slot, host_page_size, guest_page_size;
+	u64 mempages, rempages;
+	u64 guest_addr;
+	u32 slot, host_page_size, guest_page_size;
 	struct timespec tstart;
 	struct sync_area *sync;
 
@@ -317,7 +317,7 @@ static bool prepare_vm(struct vm_data *data, int nslots, uint64_t *maxslots,
 
 	clock_gettime(CLOCK_MONOTONIC, &tstart);
 	for (slot = 1, guest_addr = MEM_GPA; slot <= data->nslots; slot++) {
-		uint64_t npages;
+		u64 npages;
 
 		npages = data->pages_per_slot;
 		if (slot == data->nslots)
@@ -331,8 +331,8 @@ static bool prepare_vm(struct vm_data *data, int nslots, uint64_t *maxslots,
 	*slot_runtime = timespec_elapsed(tstart);
 
 	for (slot = 1, guest_addr = MEM_GPA; slot <= data->nslots; slot++) {
-		uint64_t npages;
-		uint64_t gpa;
+		u64 npages;
+		gpa_t gpa;
 
 		npages = data->pages_per_slot;
 		if (slot == data->nslots)
@@ -448,7 +448,7 @@ static bool guest_perform_sync(void)
 static void guest_code_test_memslot_move(void)
 {
 	struct sync_area *sync = (typeof(sync))MEM_SYNC_GPA;
-	uint32_t page_size = (typeof(page_size))READ_ONCE(sync->guest_page_size);
+	u32 page_size = (typeof(page_size))READ_ONCE(sync->guest_page_size);
 	uintptr_t base = (typeof(base))READ_ONCE(sync->move_area_ptr);
 
 	GUEST_SYNC(0);
@@ -460,7 +460,7 @@ static void guest_code_test_memslot_move(void)
 
 		for (ptr = base; ptr < base + MEM_TEST_MOVE_SIZE;
 		     ptr += page_size)
-			*(uint64_t *)ptr = MEM_TEST_VAL_1;
+			*(u64 *)ptr = MEM_TEST_VAL_1;
 
 		/*
 		 * No host sync here since the MMIO exits are so expensive
@@ -477,7 +477,7 @@ static void guest_code_test_memslot_move(void)
 static void guest_code_test_memslot_map(void)
 {
 	struct sync_area *sync = (typeof(sync))MEM_SYNC_GPA;
-	uint32_t page_size = (typeof(page_size))READ_ONCE(sync->guest_page_size);
+	u32 page_size = (typeof(page_size))READ_ONCE(sync->guest_page_size);
 
 	GUEST_SYNC(0);
 
@@ -489,7 +489,7 @@ static void guest_code_test_memslot_map(void)
 		for (ptr = MEM_TEST_GPA;
 		     ptr < MEM_TEST_GPA + MEM_TEST_MAP_SIZE / 2;
 		     ptr += page_size)
-			*(uint64_t *)ptr = MEM_TEST_VAL_1;
+			*(u64 *)ptr = MEM_TEST_VAL_1;
 
 		if (!guest_perform_sync())
 			break;
@@ -497,7 +497,7 @@ static void guest_code_test_memslot_map(void)
 		for (ptr = MEM_TEST_GPA + MEM_TEST_MAP_SIZE / 2;
 		     ptr < MEM_TEST_GPA + MEM_TEST_MAP_SIZE;
 		     ptr += page_size)
-			*(uint64_t *)ptr = MEM_TEST_VAL_2;
+			*(u64 *)ptr = MEM_TEST_VAL_2;
 
 		if (!guest_perform_sync())
 			break;
@@ -526,13 +526,13 @@ static void guest_code_test_memslot_unmap(void)
 		 *
 		 * Just access a single page to be on the safe side.
 		 */
-		*(uint64_t *)ptr = MEM_TEST_VAL_1;
+		*(u64 *)ptr = MEM_TEST_VAL_1;
 
 		if (!guest_perform_sync())
 			break;
 
 		ptr += MEM_TEST_UNMAP_SIZE / 2;
-		*(uint64_t *)ptr = MEM_TEST_VAL_2;
+		*(u64 *)ptr = MEM_TEST_VAL_2;
 
 		if (!guest_perform_sync())
 			break;
@@ -544,7 +544,7 @@ static void guest_code_test_memslot_unmap(void)
 static void guest_code_test_memslot_rw(void)
 {
 	struct sync_area *sync = (typeof(sync))MEM_SYNC_GPA;
-	uint32_t page_size = (typeof(page_size))READ_ONCE(sync->guest_page_size);
+	u32 page_size = (typeof(page_size))READ_ONCE(sync->guest_page_size);
 
 	GUEST_SYNC(0);
 
@@ -555,17 +555,17 @@ static void guest_code_test_memslot_rw(void)
 
 		for (ptr = MEM_TEST_GPA;
 		     ptr < MEM_TEST_GPA + MEM_TEST_SIZE; ptr += page_size)
-			*(uint64_t *)ptr = MEM_TEST_VAL_1;
+			*(u64 *)ptr = MEM_TEST_VAL_1;
 
 		if (!guest_perform_sync())
 			break;
 
 		for (ptr = MEM_TEST_GPA + page_size / 2;
 		     ptr < MEM_TEST_GPA + MEM_TEST_SIZE; ptr += page_size) {
-			uint64_t val = *(uint64_t *)ptr;
+			u64 val = *(u64 *)ptr;
 
 			GUEST_ASSERT_EQ(val, MEM_TEST_VAL_2);
-			*(uint64_t *)ptr = 0;
+			*(u64 *)ptr = 0;
 		}
 
 		if (!guest_perform_sync())
@@ -577,10 +577,10 @@ static void guest_code_test_memslot_rw(void)
 
 static bool test_memslot_move_prepare(struct vm_data *data,
 				      struct sync_area *sync,
-				      uint64_t *maxslots, bool isactive)
+				      u64 *maxslots, bool isactive)
 {
-	uint32_t guest_page_size = data->vm->page_size;
-	uint64_t movesrcgpa, movetestgpa;
+	u32 guest_page_size = data->vm->page_size;
+	u64 movesrcgpa, movetestgpa;
 
 #ifdef __x86_64__
 	if (disable_slot_zap_quirk)
@@ -590,7 +590,7 @@ static bool test_memslot_move_prepare(struct vm_data *data,
 	movesrcgpa = vm_slot2gpa(data, data->nslots - 1);
 
 	if (isactive) {
-		uint64_t lastpages;
+		u64 lastpages;
 
 		vm_gpa2hva(data, movesrcgpa, &lastpages);
 		if (lastpages * guest_page_size < MEM_TEST_MOVE_SIZE / 2) {
@@ -613,21 +613,21 @@ static bool test_memslot_move_prepare(struct vm_data *data,
 
 static bool test_memslot_move_prepare_active(struct vm_data *data,
 					     struct sync_area *sync,
-					     uint64_t *maxslots)
+					     u64 *maxslots)
 {
 	return test_memslot_move_prepare(data, sync, maxslots, true);
 }
 
 static bool test_memslot_move_prepare_inactive(struct vm_data *data,
 					       struct sync_area *sync,
-					       uint64_t *maxslots)
+					       u64 *maxslots)
 {
 	return test_memslot_move_prepare(data, sync, maxslots, false);
 }
 
 static void test_memslot_move_loop(struct vm_data *data, struct sync_area *sync)
 {
-	uint64_t movesrcgpa;
+	u64 movesrcgpa;
 
 	movesrcgpa = vm_slot2gpa(data, data->nslots - 1);
 	vm_mem_region_move(data->vm, data->nslots - 1 + 1,
@@ -636,13 +636,13 @@ static void test_memslot_move_loop(struct vm_data *data, struct sync_area *sync)
 }
 
 static void test_memslot_do_unmap(struct vm_data *data,
-				  uint64_t offsp, uint64_t count)
+				  u64 offsp, u64 count)
 {
-	uint64_t gpa, ctr;
-	uint32_t guest_page_size = data->vm->page_size;
+	gpa_t gpa, ctr;
+	u32 guest_page_size = data->vm->page_size;
 
 	for (gpa = MEM_TEST_GPA + offsp * guest_page_size, ctr = 0; ctr < count; ) {
-		uint64_t npages;
+		u64 npages;
 		void *hva;
 		int ret;
 
@@ -661,11 +661,11 @@ static void test_memslot_do_unmap(struct vm_data *data,
 }
 
 static void test_memslot_map_unmap_check(struct vm_data *data,
-					 uint64_t offsp, uint64_t valexp)
+					 u64 offsp, u64 valexp)
 {
-	uint64_t gpa;
-	uint64_t *val;
-	uint32_t guest_page_size = data->vm->page_size;
+	gpa_t gpa;
+	u64 *val;
+	u32 guest_page_size = data->vm->page_size;
 
 	if (!map_unmap_verify)
 		return;
@@ -680,8 +680,8 @@ static void test_memslot_map_unmap_check(struct vm_data *data,
 
 static void test_memslot_map_loop(struct vm_data *data, struct sync_area *sync)
 {
-	uint32_t guest_page_size = data->vm->page_size;
-	uint64_t guest_pages = MEM_TEST_MAP_SIZE / guest_page_size;
+	u32 guest_page_size = data->vm->page_size;
+	u64 guest_pages = MEM_TEST_MAP_SIZE / guest_page_size;
 
 	/*
 	 * Unmap the second half of the test area while guest writes to (maps)
@@ -718,11 +718,11 @@ static void test_memslot_map_loop(struct vm_data *data, struct sync_area *sync)
 
 static void test_memslot_unmap_loop_common(struct vm_data *data,
 					   struct sync_area *sync,
-					   uint64_t chunk)
+					   u64 chunk)
 {
-	uint32_t guest_page_size = data->vm->page_size;
-	uint64_t guest_pages = MEM_TEST_UNMAP_SIZE / guest_page_size;
-	uint64_t ctr;
+	u32 guest_page_size = data->vm->page_size;
+	u64 guest_pages = MEM_TEST_UNMAP_SIZE / guest_page_size;
+	u64 ctr;
 
 	/*
 	 * Wait for the guest to finish mapping page(s) in the first half
@@ -746,9 +746,9 @@ static void test_memslot_unmap_loop_common(struct vm_data *data,
 static void test_memslot_unmap_loop(struct vm_data *data,
 				    struct sync_area *sync)
 {
-	uint32_t host_page_size = getpagesize();
-	uint32_t guest_page_size = data->vm->page_size;
-	uint64_t guest_chunk_pages = guest_page_size >= host_page_size ?
+	u32 host_page_size = getpagesize();
+	u32 guest_page_size = data->vm->page_size;
+	u64 guest_chunk_pages = guest_page_size >= host_page_size ?
 					1 : host_page_size / guest_page_size;
 
 	test_memslot_unmap_loop_common(data, sync, guest_chunk_pages);
@@ -757,27 +757,27 @@ static void test_memslot_unmap_loop(struct vm_data *data,
 static void test_memslot_unmap_loop_chunked(struct vm_data *data,
 					    struct sync_area *sync)
 {
-	uint32_t guest_page_size = data->vm->page_size;
-	uint64_t guest_chunk_pages = MEM_TEST_UNMAP_CHUNK_SIZE / guest_page_size;
+	u32 guest_page_size = data->vm->page_size;
+	u64 guest_chunk_pages = MEM_TEST_UNMAP_CHUNK_SIZE / guest_page_size;
 
 	test_memslot_unmap_loop_common(data, sync, guest_chunk_pages);
 }
 
 static void test_memslot_rw_loop(struct vm_data *data, struct sync_area *sync)
 {
-	uint64_t gptr;
-	uint32_t guest_page_size = data->vm->page_size;
+	u64 gptr;
+	u32 guest_page_size = data->vm->page_size;
 
 	for (gptr = MEM_TEST_GPA + guest_page_size / 2;
 	     gptr < MEM_TEST_GPA + MEM_TEST_SIZE; gptr += guest_page_size)
-		*(uint64_t *)vm_gpa2hva(data, gptr, NULL) = MEM_TEST_VAL_2;
+		*(u64 *)vm_gpa2hva(data, gptr, NULL) = MEM_TEST_VAL_2;
 
 	host_perform_sync(sync);
 
 	for (gptr = MEM_TEST_GPA;
 	     gptr < MEM_TEST_GPA + MEM_TEST_SIZE; gptr += guest_page_size) {
-		uint64_t *vptr = (typeof(vptr))vm_gpa2hva(data, gptr, NULL);
-		uint64_t val = *vptr;
+		u64 *vptr = (typeof(vptr))vm_gpa2hva(data, gptr, NULL);
+		u64 val = *vptr;
 
 		TEST_ASSERT(val == MEM_TEST_VAL_1,
 			    "Guest written values should read back correctly (is %"PRIu64" @ %"PRIx64")",
@@ -790,21 +790,21 @@ static void test_memslot_rw_loop(struct vm_data *data, struct sync_area *sync)
 
 struct test_data {
 	const char *name;
-	uint64_t mem_size;
+	u64 mem_size;
 	void (*guest_code)(void);
 	bool (*prepare)(struct vm_data *data, struct sync_area *sync,
-			uint64_t *maxslots);
+			u64 *maxslots);
 	void (*loop)(struct vm_data *data, struct sync_area *sync);
 };
 
-static bool test_execute(int nslots, uint64_t *maxslots,
+static bool test_execute(int nslots, u64 *maxslots,
 			 unsigned int maxtime,
 			 const struct test_data *tdata,
-			 uint64_t *nloops,
+			 u64 *nloops,
 			 struct timespec *slot_runtime,
 			 struct timespec *guest_runtime)
 {
-	uint64_t mem_size = tdata->mem_size ? : MEM_SIZE;
+	u64 mem_size = tdata->mem_size ? : MEM_SIZE;
 	struct vm_data *data;
 	struct sync_area *sync;
 	struct timespec tstart;
@@ -924,8 +924,8 @@ static void help(char *name, struct test_args *targs)
 
 static bool check_memory_sizes(void)
 {
-	uint32_t host_page_size = getpagesize();
-	uint32_t guest_page_size = vm_guest_mode_params[VM_MODE_DEFAULT].page_size;
+	u32 host_page_size = getpagesize();
+	u32 guest_page_size = vm_guest_mode_params[VM_MODE_DEFAULT].page_size;
 
 	if (host_page_size > SZ_64K || guest_page_size > SZ_64K) {
 		pr_info("Unsupported page size on host (0x%x) or guest (0x%x)\n",
@@ -961,7 +961,7 @@ static bool check_memory_sizes(void)
 static bool parse_args(int argc, char *argv[],
 		       struct test_args *targs)
 {
-	uint32_t max_mem_slots;
+	u32 max_mem_slots;
 	int opt;
 
 	while ((opt = getopt(argc, argv, "hvdqs:f:e:l:r:")) != -1) {
@@ -1040,8 +1040,8 @@ static bool parse_args(int argc, char *argv[],
 
 struct test_result {
 	struct timespec slot_runtime, guest_runtime, iter_runtime;
-	int64_t slottimens, runtimens;
-	uint64_t nloops;
+	s64 slottimens, runtimens;
+	u64 nloops;
 };
 
 static bool test_loop(const struct test_data *data,
@@ -1049,7 +1049,7 @@ static bool test_loop(const struct test_data *data,
 		      struct test_result *rbestslottime,
 		      struct test_result *rbestruntime)
 {
-	uint64_t maxslots;
+	u64 maxslots;
 	struct test_result result = {};
 
 	if (!test_execute(targs->nslots, &maxslots, targs->seconds, data,
diff --git a/tools/testing/selftests/kvm/mmu_stress_test.c b/tools/testing/selftests/kvm/mmu_stress_test.c
index 51c070556f3e..54d281419d31 100644
--- a/tools/testing/selftests/kvm/mmu_stress_test.c
+++ b/tools/testing/selftests/kvm/mmu_stress_test.c
@@ -20,19 +20,19 @@
 static bool mprotect_ro_done;
 static bool all_vcpus_hit_ro_fault;
 
-static void guest_code(uint64_t start_gpa, uint64_t end_gpa, uint64_t stride)
+static void guest_code(u64 start_gpa, u64 end_gpa, u64 stride)
 {
-	uint64_t gpa;
+	gpa_t gpa;
 	int i;
 
 	for (i = 0; i < 2; i++) {
 		for (gpa = start_gpa; gpa < end_gpa; gpa += stride)
-			vcpu_arch_put_guest(*((volatile uint64_t *)gpa), gpa);
+			vcpu_arch_put_guest(*((volatile u64 *)gpa), gpa);
 		GUEST_SYNC(i);
 	}
 
 	for (gpa = start_gpa; gpa < end_gpa; gpa += stride)
-		*((volatile uint64_t *)gpa);
+		*((volatile u64 *)gpa);
 	GUEST_SYNC(2);
 
 	/*
@@ -55,7 +55,7 @@ static void guest_code(uint64_t start_gpa, uint64_t end_gpa, uint64_t stride)
 #elif defined(__aarch64__)
 			asm volatile("str %0, [%0]" :: "r" (gpa) : "memory");
 #else
-			vcpu_arch_put_guest(*((volatile uint64_t *)gpa), gpa);
+			vcpu_arch_put_guest(*((volatile u64 *)gpa), gpa);
 #endif
 	} while (!READ_ONCE(mprotect_ro_done) || !READ_ONCE(all_vcpus_hit_ro_fault));
 
@@ -68,7 +68,7 @@ static void guest_code(uint64_t start_gpa, uint64_t end_gpa, uint64_t stride)
 #endif
 
 	for (gpa = start_gpa; gpa < end_gpa; gpa += stride)
-		vcpu_arch_put_guest(*((volatile uint64_t *)gpa), gpa);
+		vcpu_arch_put_guest(*((volatile u64 *)gpa), gpa);
 	GUEST_SYNC(4);
 
 	GUEST_ASSERT(0);
@@ -76,8 +76,8 @@ static void guest_code(uint64_t start_gpa, uint64_t end_gpa, uint64_t stride)
 
 struct vcpu_info {
 	struct kvm_vcpu *vcpu;
-	uint64_t start_gpa;
-	uint64_t end_gpa;
+	u64 start_gpa;
+	u64 end_gpa;
 };
 
 static int nr_vcpus;
@@ -203,10 +203,10 @@ static void *vcpu_worker(void *data)
 }
 
 static pthread_t *spawn_workers(struct kvm_vm *vm, struct kvm_vcpu **vcpus,
-				uint64_t start_gpa, uint64_t end_gpa)
+				u64 start_gpa, u64 end_gpa)
 {
 	struct vcpu_info *info;
-	uint64_t gpa, nr_bytes;
+	gpa_t gpa, nr_bytes;
 	pthread_t *threads;
 	int i;
 
@@ -217,7 +217,7 @@ static pthread_t *spawn_workers(struct kvm_vm *vm, struct kvm_vcpu **vcpus,
 	TEST_ASSERT(info, "Failed to allocate vCPU gpa ranges");
 
 	nr_bytes = ((end_gpa - start_gpa) / nr_vcpus) &
-			~((uint64_t)vm->page_size - 1);
+			~((u64)vm->page_size - 1);
 	TEST_ASSERT(nr_bytes, "C'mon, no way you have %d CPUs", nr_vcpus);
 
 	for (i = 0, gpa = start_gpa; i < nr_vcpus; i++, gpa += nr_bytes) {
@@ -278,11 +278,11 @@ int main(int argc, char *argv[])
 	 * just below the 4gb boundary.  This test could create memory at
 	 * 1gb-3gb,but it's simpler to skip straight to 4gb.
 	 */
-	const uint64_t start_gpa = SZ_4G;
+	const u64 start_gpa = SZ_4G;
 	const int first_slot = 1;
 
 	struct timespec time_start, time_run1, time_reset, time_run2, time_ro, time_rw;
-	uint64_t max_gpa, gpa, slot_size, max_mem, i;
+	u64 max_gpa, gpa, slot_size, max_mem, i;
 	int max_slots, slot, opt, fd;
 	bool hugepages = false;
 	struct kvm_vcpu **vcpus;
@@ -347,7 +347,7 @@ int main(int argc, char *argv[])
 
 	/* Pre-fault the memory to avoid taking mmap_sem on guest page faults. */
 	for (i = 0; i < slot_size; i += vm->page_size)
-		((uint8_t *)mem)[i] = 0xaa;
+		((u8 *)mem)[i] = 0xaa;
 
 	gpa = 0;
 	for (slot = first_slot; slot < max_slots; slot++) {
diff --git a/tools/testing/selftests/kvm/pre_fault_memory_test.c b/tools/testing/selftests/kvm/pre_fault_memory_test.c
index f3de0386ba7b..fcb57fd034e6 100644
--- a/tools/testing/selftests/kvm/pre_fault_memory_test.c
+++ b/tools/testing/selftests/kvm/pre_fault_memory_test.c
@@ -17,13 +17,13 @@
 #define TEST_NPAGES		(TEST_SIZE / PAGE_SIZE)
 #define TEST_SLOT		10
 
-static void guest_code(uint64_t base_gva)
+static void guest_code(u64 base_gva)
 {
-	volatile uint64_t val __used;
+	volatile u64 val __used;
 	int i;
 
 	for (i = 0; i < TEST_NPAGES; i++) {
-		uint64_t *src = (uint64_t *)(base_gva + i * PAGE_SIZE);
+		u64 *src = (u64 *)(base_gva + i * PAGE_SIZE);
 
 		val = *src;
 	}
@@ -33,8 +33,8 @@ static void guest_code(uint64_t base_gva)
 
 struct slot_worker_data {
 	struct kvm_vm *vm;
-	u64 gpa;
-	uint32_t flags;
+	gpa_t gpa;
+	u32 flags;
 	bool worker_ready;
 	bool prefault_ready;
 	bool recreate_slot;
@@ -161,7 +161,7 @@ static void pre_fault_memory(struct kvm_vcpu *vcpu, u64 base_gpa, u64 offset,
 
 static void __test_pre_fault_memory(unsigned long vm_type, bool private)
 {
-	uint64_t gpa, gva, alignment, guest_page_size;
+	gpa_t gpa, gva, alignment, guest_page_size;
 	const struct vm_shape shape = {
 		.mode = VM_MODE_DEFAULT,
 		.type = vm_type,
diff --git a/tools/testing/selftests/kvm/riscv/arch_timer.c b/tools/testing/selftests/kvm/riscv/arch_timer.c
index f962fefc48fa..d67c918ee310 100644
--- a/tools/testing/selftests/kvm/riscv/arch_timer.c
+++ b/tools/testing/selftests/kvm/riscv/arch_timer.c
@@ -17,9 +17,9 @@ static int timer_irq = IRQ_S_TIMER;
 
 static void guest_irq_handler(struct pt_regs *regs)
 {
-	uint64_t xcnt, xcnt_diff_us, cmp;
+	u64 xcnt, xcnt_diff_us, cmp;
 	unsigned int intid = regs->cause & ~CAUSE_IRQ_FLAG;
-	uint32_t cpu = guest_get_vcpuid();
+	u32 cpu = guest_get_vcpuid();
 	struct test_vcpu_shared_data *shared_data = &vcpu_shared_data[cpu];
 
 	timer_irq_disable();
@@ -40,7 +40,7 @@ static void guest_irq_handler(struct pt_regs *regs)
 
 static void guest_run(struct test_vcpu_shared_data *shared_data)
 {
-	uint32_t irq_iter, config_iter;
+	u32 irq_iter, config_iter;
 
 	shared_data->nr_iter = 0;
 	shared_data->guest_stage = 0;
@@ -66,7 +66,7 @@ static void guest_run(struct test_vcpu_shared_data *shared_data)
 
 static void guest_code(void)
 {
-	uint32_t cpu = guest_get_vcpuid();
+	u32 cpu = guest_get_vcpuid();
 	struct test_vcpu_shared_data *shared_data = &vcpu_shared_data[cpu];
 
 	timer_irq_disable();
diff --git a/tools/testing/selftests/kvm/riscv/ebreak_test.c b/tools/testing/selftests/kvm/riscv/ebreak_test.c
index 739d17befb5a..3f44b045a22e 100644
--- a/tools/testing/selftests/kvm/riscv/ebreak_test.c
+++ b/tools/testing/selftests/kvm/riscv/ebreak_test.c
@@ -8,10 +8,10 @@
 #include "kvm_util.h"
 #include "ucall_common.h"
 
-#define LABEL_ADDRESS(v) ((uint64_t)&(v))
+#define LABEL_ADDRESS(v) ((u64)&(v))
 
 extern unsigned char sw_bp_1, sw_bp_2;
-static uint64_t sw_bp_addr;
+static u64 sw_bp_addr;
 
 static void guest_code(void)
 {
@@ -37,7 +37,7 @@ int main(void)
 {
 	struct kvm_vm *vm;
 	struct kvm_vcpu *vcpu;
-	uint64_t pc;
+	u64 pc;
 	struct kvm_guest_debug debug = {
 		.control = KVM_GUESTDBG_ENABLE,
 	};
diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testing/selftests/kvm/riscv/get-reg-list.c
index 8d6b951434eb..8d6fdb5d38b8 100644
--- a/tools/testing/selftests/kvm/riscv/get-reg-list.c
+++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c
@@ -162,7 +162,7 @@ bool check_reject_set(int err)
 }
 
 static int override_vector_reg_size(struct kvm_vcpu *vcpu, struct vcpu_reg_sublist *s,
-				    uint64_t feature)
+				    u64 feature)
 {
 	unsigned long vlenb_reg = 0;
 	int rc;
@@ -197,7 +197,7 @@ void finalize_vcpu(struct kvm_vcpu *vcpu, struct vcpu_reg_list *c)
 {
 	unsigned long isa_ext_state[KVM_RISCV_ISA_EXT_MAX] = { 0 };
 	struct vcpu_reg_sublist *s;
-	uint64_t feature;
+	u64 feature;
 	int rc;
 
 	for (int i = 0; i < KVM_RISCV_ISA_EXT_MAX; i++)
diff --git a/tools/testing/selftests/kvm/riscv/sbi_pmu_test.c b/tools/testing/selftests/kvm/riscv/sbi_pmu_test.c
index cec1621ace23..e56a3dd6a51e 100644
--- a/tools/testing/selftests/kvm/riscv/sbi_pmu_test.c
+++ b/tools/testing/selftests/kvm/riscv/sbi_pmu_test.c
@@ -24,7 +24,7 @@ union sbi_pmu_ctr_info ctrinfo_arr[RISCV_MAX_PMU_COUNTERS];
 /* Snapshot shared memory data */
 #define PMU_SNAPSHOT_GPA_BASE		BIT(30)
 static void *snapshot_gva;
-static vm_paddr_t snapshot_gpa;
+static gpa_t snapshot_gpa;
 
 static int vcpu_shared_irq_count;
 static int counter_in_use;
@@ -86,7 +86,7 @@ unsigned long pmu_csr_read_num(int csr_num)
 #undef switchcase_csr_read
 }
 
-static inline void dummy_func_loop(uint64_t iter)
+static inline void dummy_func_loop(u64 iter)
 {
 	int i = 0;
 
@@ -259,7 +259,7 @@ static inline void verify_sbi_requirement_assert(void)
 		__GUEST_ASSERT(0, "SBI implementation version doesn't support PMU Snapshot");
 }
 
-static void snapshot_set_shmem(vm_paddr_t gpa, unsigned long flags)
+static void snapshot_set_shmem(gpa_t gpa, unsigned long flags)
 {
 	unsigned long lo = (unsigned long)gpa;
 #if __riscv_xlen == 32
@@ -610,7 +610,7 @@ static void test_vm_setup_snapshot_mem(struct kvm_vm *vm, struct kvm_vcpu *vcpu)
 	virt_map(vm, PMU_SNAPSHOT_GPA_BASE, PMU_SNAPSHOT_GPA_BASE, 1);
 
 	snapshot_gva = (void *)(PMU_SNAPSHOT_GPA_BASE);
-	snapshot_gpa = addr_gva2gpa(vcpu->vm, (vm_vaddr_t)snapshot_gva);
+	snapshot_gpa = addr_gva2gpa(vcpu->vm, (gva_t)snapshot_gva);
 	sync_global_to_guest(vcpu->vm, snapshot_gva);
 	sync_global_to_guest(vcpu->vm, snapshot_gpa);
 }
diff --git a/tools/testing/selftests/kvm/s390/debug_test.c b/tools/testing/selftests/kvm/s390/debug_test.c
index ad8095968601..751c61c0f056 100644
--- a/tools/testing/selftests/kvm/s390/debug_test.c
+++ b/tools/testing/selftests/kvm/s390/debug_test.c
@@ -17,7 +17,7 @@ asm("int_handler:\n"
     "j .\n");
 
 static struct kvm_vm *test_step_int_1(struct kvm_vcpu **vcpu, void *guest_code,
-				      size_t new_psw_off, uint64_t *new_psw)
+				      size_t new_psw_off, u64 *new_psw)
 {
 	struct kvm_guest_debug debug = {};
 	struct kvm_regs regs;
@@ -27,7 +27,7 @@ static struct kvm_vm *test_step_int_1(struct kvm_vcpu **vcpu, void *guest_code,
 	vm = vm_create_with_one_vcpu(vcpu, guest_code);
 	lowcore = addr_gpa2hva(vm, 0);
 	new_psw[0] = (*vcpu)->run->psw_mask;
-	new_psw[1] = (uint64_t)int_handler;
+	new_psw[1] = (u64)int_handler;
 	memcpy(lowcore + new_psw_off, new_psw, 16);
 	vcpu_regs_get(*vcpu, &regs);
 	regs.gprs[2] = -1;
@@ -42,7 +42,7 @@ static struct kvm_vm *test_step_int_1(struct kvm_vcpu **vcpu, void *guest_code,
 static void test_step_int(void *guest_code, size_t new_psw_off)
 {
 	struct kvm_vcpu *vcpu;
-	uint64_t new_psw[2];
+	u64 new_psw[2];
 	struct kvm_vm *vm;
 
 	vm = test_step_int_1(&vcpu, guest_code, new_psw_off, new_psw);
@@ -79,7 +79,7 @@ static void test_step_pgm_diag(void)
 		.u.pgm.code = PGM_SPECIFICATION,
 	};
 	struct kvm_vcpu *vcpu;
-	uint64_t new_psw[2];
+	u64 new_psw[2];
 	struct kvm_vm *vm;
 
 	vm = test_step_int_1(&vcpu, test_step_pgm_diag_guest_code,
diff --git a/tools/testing/selftests/kvm/s390/irq_routing.c b/tools/testing/selftests/kvm/s390/irq_routing.c
index 7819a0af19a8..f3839284ac08 100644
--- a/tools/testing/selftests/kvm/s390/irq_routing.c
+++ b/tools/testing/selftests/kvm/s390/irq_routing.c
@@ -27,7 +27,7 @@ static void test(void)
 	struct kvm_irq_routing *routing;
 	struct kvm_vcpu *vcpu;
 	struct kvm_vm *vm;
-	vm_paddr_t mem;
+	gpa_t mem;
 	int ret;
 
 	struct kvm_irq_routing_entry ue = {
diff --git a/tools/testing/selftests/kvm/s390/memop.c b/tools/testing/selftests/kvm/s390/memop.c
index 4374b4cd2a80..0244848621b3 100644
--- a/tools/testing/selftests/kvm/s390/memop.c
+++ b/tools/testing/selftests/kvm/s390/memop.c
@@ -34,7 +34,7 @@ enum mop_access_mode {
 struct mop_desc {
 	uintptr_t gaddr;
 	uintptr_t gaddr_v;
-	uint64_t set_flags;
+	u64 set_flags;
 	unsigned int f_check : 1;
 	unsigned int f_inject : 1;
 	unsigned int f_key : 1;
@@ -42,19 +42,19 @@ struct mop_desc {
 	unsigned int _set_flags : 1;
 	unsigned int _sida_offset : 1;
 	unsigned int _ar : 1;
-	uint32_t size;
+	u32 size;
 	enum mop_target target;
 	enum mop_access_mode mode;
 	void *buf;
-	uint32_t sida_offset;
+	u32 sida_offset;
 	void *old;
-	uint8_t old_value[16];
+	u8 old_value[16];
 	bool *cmpxchg_success;
-	uint8_t ar;
-	uint8_t key;
+	u8 ar;
+	u8 key;
 };
 
-const uint8_t NO_KEY = 0xff;
+const u8 NO_KEY = 0xff;
 
 static struct kvm_s390_mem_op ksmo_from_desc(struct mop_desc *desc)
 {
@@ -85,7 +85,7 @@ static struct kvm_s390_mem_op ksmo_from_desc(struct mop_desc *desc)
 			ksmo.op = KVM_S390_MEMOP_ABSOLUTE_WRITE;
 		if (desc->mode == CMPXCHG) {
 			ksmo.op = KVM_S390_MEMOP_ABSOLUTE_CMPXCHG;
-			ksmo.old_addr = (uint64_t)desc->old;
+			ksmo.old_addr = (u64)desc->old;
 			memcpy(desc->old_value, desc->old, desc->size);
 		}
 		break;
@@ -230,8 +230,8 @@ static void memop_ioctl(struct test_info info, struct kvm_s390_mem_op *ksmo,
 #define CR0_FETCH_PROTECTION_OVERRIDE	(1UL << (63 - 38))
 #define CR0_STORAGE_PROTECTION_OVERRIDE	(1UL << (63 - 39))
 
-static uint8_t __aligned(PAGE_SIZE) mem1[65536];
-static uint8_t __aligned(PAGE_SIZE) mem2[65536];
+static u8 __aligned(PAGE_SIZE) mem1[65536];
+static u8 __aligned(PAGE_SIZE) mem2[65536];
 
 struct test_default {
 	struct kvm_vm *kvm_vm;
@@ -296,7 +296,7 @@ static void prepare_mem12(void)
 	TEST_ASSERT(!memcmp(p1, p2, size), "Memory contents do not match!")
 
 static void default_write_read(struct test_info copy_cpu, struct test_info mop_cpu,
-			       enum mop_target mop_target, uint32_t size, uint8_t key)
+			       enum mop_target mop_target, u32 size, u8 key)
 {
 	prepare_mem12();
 	CHECK_N_DO(MOP, mop_cpu, mop_target, WRITE, mem1, size,
@@ -308,7 +308,7 @@ static void default_write_read(struct test_info copy_cpu, struct test_info mop_c
 }
 
 static void default_read(struct test_info copy_cpu, struct test_info mop_cpu,
-			 enum mop_target mop_target, uint32_t size, uint8_t key)
+			 enum mop_target mop_target, u32 size, u8 key)
 {
 	prepare_mem12();
 	CHECK_N_DO(MOP, mop_cpu, mop_target, WRITE, mem1, size, GADDR_V(mem1));
@@ -318,12 +318,12 @@ static void default_read(struct test_info copy_cpu, struct test_info mop_cpu,
 	ASSERT_MEM_EQ(mem1, mem2, size);
 }
 
-static void default_cmpxchg(struct test_default *test, uint8_t key)
+static void default_cmpxchg(struct test_default *test, u8 key)
 {
 	for (int size = 1; size <= 16; size *= 2) {
 		for (int offset = 0; offset < 16; offset += size) {
-			uint8_t __aligned(16) new[16] = {};
-			uint8_t __aligned(16) old[16];
+			u8 __aligned(16) new[16] = {};
+			u8 __aligned(16) old[16];
 			bool succ;
 
 			prepare_mem12();
@@ -400,7 +400,7 @@ static void test_copy_access_register(void)
 	kvm_vm_free(t.kvm_vm);
 }
 
-static void set_storage_key_range(void *addr, size_t len, uint8_t key)
+static void set_storage_key_range(void *addr, size_t len, u8 key)
 {
 	uintptr_t _addr, abs, i;
 	int not_mapped = 0;
@@ -483,13 +483,13 @@ static __uint128_t cut_to_size(int size, __uint128_t val)
 {
 	switch (size) {
 	case 1:
-		return (uint8_t)val;
+		return (u8)val;
 	case 2:
-		return (uint16_t)val;
+		return (u16)val;
 	case 4:
-		return (uint32_t)val;
+		return (u32)val;
 	case 8:
-		return (uint64_t)val;
+		return (u64)val;
 	case 16:
 		return val;
 	}
@@ -501,10 +501,10 @@ static bool popcount_eq(__uint128_t a, __uint128_t b)
 {
 	unsigned int count_a, count_b;
 
-	count_a = __builtin_popcountl((uint64_t)(a >> 64)) +
-		  __builtin_popcountl((uint64_t)a);
-	count_b = __builtin_popcountl((uint64_t)(b >> 64)) +
-		  __builtin_popcountl((uint64_t)b);
+	count_a = __builtin_popcountl((u64)(a >> 64)) +
+		  __builtin_popcountl((u64)a);
+	count_b = __builtin_popcountl((u64)(b >> 64)) +
+		  __builtin_popcountl((u64)b);
 	return count_a == count_b;
 }
 
@@ -553,7 +553,7 @@ static __uint128_t permutate_bits(bool guest, int i, int size, __uint128_t old)
 	if (swap) {
 		int i, j;
 		__uint128_t new;
-		uint8_t byte0, byte1;
+		u8 byte0, byte1;
 
 		rand = rand * 3 + 1;
 		i = rand % size;
@@ -585,28 +585,28 @@ static bool _cmpxchg(int size, void *target, __uint128_t *old_addr, __uint128_t
 
 	switch (size) {
 	case 4: {
-			uint32_t old = *old_addr;
+			u32 old = *old_addr;
 
 			asm volatile ("cs %[old],%[new],%[address]"
 			    : [old] "+d" (old),
-			      [address] "+Q" (*(uint32_t *)(target))
-			    : [new] "d" ((uint32_t)new)
+			      [address] "+Q" (*(u32 *)(target))
+			    : [new] "d" ((u32)new)
 			    : "cc"
 			);
-			ret = old == (uint32_t)*old_addr;
+			ret = old == (u32)*old_addr;
 			*old_addr = old;
 			return ret;
 		}
 	case 8: {
-			uint64_t old = *old_addr;
+			u64 old = *old_addr;
 
 			asm volatile ("csg %[old],%[new],%[address]"
 			    : [old] "+d" (old),
-			      [address] "+Q" (*(uint64_t *)(target))
-			    : [new] "d" ((uint64_t)new)
+			      [address] "+Q" (*(u64 *)(target))
+			    : [new] "d" ((u64)new)
 			    : "cc"
 			);
-			ret = old == (uint64_t)*old_addr;
+			ret = old == (u64)*old_addr;
 			*old_addr = old;
 			return ret;
 		}
@@ -811,10 +811,10 @@ static void test_errors_cmpxchg_key(void)
 static void test_termination(void)
 {
 	struct test_default t = test_default_init(guest_error_key);
-	uint64_t prefix;
-	uint64_t teid;
-	uint64_t teid_mask = BIT(63 - 56) | BIT(63 - 60) | BIT(63 - 61);
-	uint64_t psw[2];
+	u64 prefix;
+	u64 teid;
+	u64 teid_mask = BIT(63 - 56) | BIT(63 - 60) | BIT(63 - 61);
+	u64 psw[2];
 
 	HOST_SYNC(t.vcpu, STAGE_INITED);
 	HOST_SYNC(t.vcpu, STAGE_SKEYS_SET);
@@ -855,7 +855,7 @@ static void test_errors_key_storage_prot_override(void)
 	kvm_vm_free(t.kvm_vm);
 }
 
-const uint64_t last_page_addr = -PAGE_SIZE;
+const u64 last_page_addr = -PAGE_SIZE;
 
 static void guest_copy_key_fetch_prot_override(void)
 {
@@ -878,10 +878,10 @@ static void guest_copy_key_fetch_prot_override(void)
 static void test_copy_key_fetch_prot_override(void)
 {
 	struct test_default t = test_default_init(guest_copy_key_fetch_prot_override);
-	vm_vaddr_t guest_0_page, guest_last_page;
+	gva_t guest_0_page, guest_last_page;
 
-	guest_0_page = vm_vaddr_alloc(t.kvm_vm, PAGE_SIZE, 0);
-	guest_last_page = vm_vaddr_alloc(t.kvm_vm, PAGE_SIZE, last_page_addr);
+	guest_0_page = vm_alloc(t.kvm_vm, PAGE_SIZE, 0);
+	guest_last_page = vm_alloc(t.kvm_vm, PAGE_SIZE, last_page_addr);
 	if (guest_0_page != 0 || guest_last_page != last_page_addr) {
 		print_skip("did not allocate guest pages at required positions");
 		goto out;
@@ -917,10 +917,10 @@ static void test_copy_key_fetch_prot_override(void)
 static void test_errors_key_fetch_prot_override_not_enabled(void)
 {
 	struct test_default t = test_default_init(guest_copy_key_fetch_prot_override);
-	vm_vaddr_t guest_0_page, guest_last_page;
+	gva_t guest_0_page, guest_last_page;
 
-	guest_0_page = vm_vaddr_alloc(t.kvm_vm, PAGE_SIZE, 0);
-	guest_last_page = vm_vaddr_alloc(t.kvm_vm, PAGE_SIZE, last_page_addr);
+	guest_0_page = vm_alloc(t.kvm_vm, PAGE_SIZE, 0);
+	guest_last_page = vm_alloc(t.kvm_vm, PAGE_SIZE, last_page_addr);
 	if (guest_0_page != 0 || guest_last_page != last_page_addr) {
 		print_skip("did not allocate guest pages at required positions");
 		goto out;
@@ -938,10 +938,10 @@ static void test_errors_key_fetch_prot_override_not_enabled(void)
 static void test_errors_key_fetch_prot_override_enabled(void)
 {
 	struct test_default t = test_default_init(guest_copy_key_fetch_prot_override);
-	vm_vaddr_t guest_0_page, guest_last_page;
+	gva_t guest_0_page, guest_last_page;
 
-	guest_0_page = vm_vaddr_alloc(t.kvm_vm, PAGE_SIZE, 0);
-	guest_last_page = vm_vaddr_alloc(t.kvm_vm, PAGE_SIZE, last_page_addr);
+	guest_0_page = vm_alloc(t.kvm_vm, PAGE_SIZE, 0);
+	guest_last_page = vm_alloc(t.kvm_vm, PAGE_SIZE, last_page_addr);
 	if (guest_0_page != 0 || guest_last_page != last_page_addr) {
 		print_skip("did not allocate guest pages at required positions");
 		goto out;
diff --git a/tools/testing/selftests/kvm/s390/resets.c b/tools/testing/selftests/kvm/s390/resets.c
index b58f75b381e5..e3c7a2f148f9 100644
--- a/tools/testing/selftests/kvm/s390/resets.c
+++ b/tools/testing/selftests/kvm/s390/resets.c
@@ -20,7 +20,7 @@
 
 struct kvm_s390_irq buf[ARBITRARY_NON_ZERO_VCPU_ID + LOCAL_IRQS];
 
-static uint8_t regs_null[512];
+static u8 regs_null[512];
 
 static void guest_code_initial(void)
 {
@@ -57,9 +57,9 @@ static void guest_code_initial(void)
 		);
 }
 
-static void test_one_reg(struct kvm_vcpu *vcpu, uint64_t id, uint64_t value)
+static void test_one_reg(struct kvm_vcpu *vcpu, u64 id, u64 value)
 {
-	uint64_t eval_reg;
+	u64 eval_reg;
 
 	eval_reg = vcpu_get_reg(vcpu, id);
 	TEST_ASSERT(eval_reg == value, "value == 0x%lx", value);
diff --git a/tools/testing/selftests/kvm/s390/shared_zeropage_test.c b/tools/testing/selftests/kvm/s390/shared_zeropage_test.c
index bba0d9a6dcc8..a9e5a01200b8 100644
--- a/tools/testing/selftests/kvm/s390/shared_zeropage_test.c
+++ b/tools/testing/selftests/kvm/s390/shared_zeropage_test.c
@@ -13,7 +13,7 @@
 #include "kselftest.h"
 #include "ucall_common.h"
 
-static void set_storage_key(void *addr, uint8_t skey)
+static void set_storage_key(void *addr, u8 skey)
 {
 	asm volatile("sske %0,%1" : : "d" (skey), "a" (addr));
 }
diff --git a/tools/testing/selftests/kvm/s390/tprot.c b/tools/testing/selftests/kvm/s390/tprot.c
index 12d5e1cb62e3..8054d2b178f0 100644
--- a/tools/testing/selftests/kvm/s390/tprot.c
+++ b/tools/testing/selftests/kvm/s390/tprot.c
@@ -14,12 +14,12 @@
 #define CR0_FETCH_PROTECTION_OVERRIDE	(1UL << (63 - 38))
 #define CR0_STORAGE_PROTECTION_OVERRIDE	(1UL << (63 - 39))
 
-static __aligned(PAGE_SIZE) uint8_t pages[2][PAGE_SIZE];
-static uint8_t *const page_store_prot = pages[0];
-static uint8_t *const page_fetch_prot = pages[1];
+static __aligned(PAGE_SIZE) u8 pages[2][PAGE_SIZE];
+static u8 *const page_store_prot = pages[0];
+static u8 *const page_fetch_prot = pages[1];
 
 /* Nonzero return value indicates that address not mapped */
-static int set_storage_key(void *addr, uint8_t key)
+static int set_storage_key(void *addr, u8 key)
 {
 	int not_mapped = 0;
 
@@ -44,9 +44,9 @@ enum permission {
 	TRANSL_UNAVAIL = 3,
 };
 
-static enum permission test_protection(void *addr, uint8_t key)
+static enum permission test_protection(void *addr, u8 key)
 {
-	uint64_t mask;
+	u64 mask;
 
 	asm volatile (
 		       "tprot	%[addr], 0(%[key])\n"
@@ -72,7 +72,7 @@ enum stage {
 struct test {
 	enum stage stage;
 	void *addr;
-	uint8_t key;
+	u8 key;
 	enum permission expected;
 } tests[] = {
 	/*
@@ -146,7 +146,7 @@ static enum stage perform_next_stage(int *i, bool mapped_0)
 		/*
 		 * Some fetch protection override tests require that page 0
 		 * be mapped, however, when the hosts tries to map that page via
-		 * vm_vaddr_alloc, it may happen that some other page gets mapped
+		 * vm_alloc, it may happen that some other page gets mapped
 		 * instead.
 		 * In order to skip these tests we detect this inside the guest
 		 */
@@ -207,7 +207,7 @@ int main(int argc, char *argv[])
 	struct kvm_vcpu *vcpu;
 	struct kvm_vm *vm;
 	struct kvm_run *run;
-	vm_vaddr_t guest_0_page;
+	gva_t guest_0_page;
 
 	ksft_print_header();
 	ksft_set_plan(STAGE_END);
@@ -216,10 +216,10 @@ int main(int argc, char *argv[])
 	run = vcpu->run;
 
 	HOST_SYNC(vcpu, STAGE_INIT_SIMPLE);
-	mprotect(addr_gva2hva(vm, (vm_vaddr_t)pages), PAGE_SIZE * 2, PROT_READ);
+	mprotect(addr_gva2hva(vm, (gva_t)pages), PAGE_SIZE * 2, PROT_READ);
 	HOST_SYNC(vcpu, TEST_SIMPLE);
 
-	guest_0_page = vm_vaddr_alloc(vm, PAGE_SIZE, 0);
+	guest_0_page = vm_alloc(vm, PAGE_SIZE, 0);
 	if (guest_0_page != 0) {
 		/* Use NO_TAP so we don't get a PASS print */
 		HOST_SYNC_NO_TAP(vcpu, STAGE_INIT_FETCH_PROT_OVERRIDE);
@@ -229,7 +229,7 @@ int main(int argc, char *argv[])
 		HOST_SYNC(vcpu, STAGE_INIT_FETCH_PROT_OVERRIDE);
 	}
 	if (guest_0_page == 0)
-		mprotect(addr_gva2hva(vm, (vm_vaddr_t)0), PAGE_SIZE, PROT_READ);
+		mprotect(addr_gva2hva(vm, (gva_t)0), PAGE_SIZE, PROT_READ);
 	run->s.regs.crs[0] |= CR0_FETCH_PROTECTION_OVERRIDE;
 	run->kvm_dirty_regs = KVM_SYNC_CRS;
 	HOST_SYNC(vcpu, TEST_FETCH_PROT_OVERRIDE);
diff --git a/tools/testing/selftests/kvm/s390/ucontrol_test.c b/tools/testing/selftests/kvm/s390/ucontrol_test.c
index 50bc1c38225a..b8c6f37b53e0 100644
--- a/tools/testing/selftests/kvm/s390/ucontrol_test.c
+++ b/tools/testing/selftests/kvm/s390/ucontrol_test.c
@@ -111,7 +111,7 @@ FIXTURE(uc_kvm)
 	uintptr_t base_hva;
 	uintptr_t code_hva;
 	int kvm_run_size;
-	vm_paddr_t pgd;
+	gpa_t pgd;
 	void *vm_mem;
 	int vcpu_fd;
 	int kvm_fd;
@@ -269,7 +269,7 @@ TEST(uc_cap_hpage)
 }
 
 /* calculate host virtual addr from guest physical addr */
-static void *gpa2hva(FIXTURE_DATA(uc_kvm) *self, u64 gpa)
+static void *gpa2hva(FIXTURE_DATA(uc_kvm) *self, gpa_t gpa)
 {
 	return (void *)(self->base_hva - self->base_gpa + gpa);
 }
@@ -571,7 +571,7 @@ TEST_F(uc_kvm, uc_skey)
 {
 	struct kvm_s390_sie_block *sie_block = self->sie_block;
 	struct kvm_sync_regs *sync_regs = &self->run->s.regs;
-	u64 test_vaddr = VM_MEM_SIZE - (SZ_1M / 2);
+	u64 test_gva = VM_MEM_SIZE - (SZ_1M / 2);
 	struct kvm_run *run = self->run;
 	const u8 skeyvalue = 0x34;
 
@@ -583,7 +583,7 @@ TEST_F(uc_kvm, uc_skey)
 	/* set register content for test_skey_asm to access not mapped memory */
 	sync_regs->gprs[1] = skeyvalue;
 	sync_regs->gprs[5] = self->base_gpa;
-	sync_regs->gprs[6] = test_vaddr;
+	sync_regs->gprs[6] = test_gva;
 	run->kvm_dirty_regs |= KVM_SYNC_GPRS;
 
 	/* DAT disabled + 64 bit mode */
diff --git a/tools/testing/selftests/kvm/set_memory_region_test.c b/tools/testing/selftests/kvm/set_memory_region_test.c
index a398dc3a8c4b..9b919a231c93 100644
--- a/tools/testing/selftests/kvm/set_memory_region_test.c
+++ b/tools/testing/selftests/kvm/set_memory_region_test.c
@@ -30,19 +30,19 @@
 #define MEM_REGION_GPA		0xc0000000
 #define MEM_REGION_SLOT		10
 
-static const uint64_t MMIO_VAL = 0xbeefull;
+static const u64 MMIO_VAL = 0xbeefull;
 
-extern const uint64_t final_rip_start;
-extern const uint64_t final_rip_end;
+extern const u64 final_rip_start;
+extern const u64 final_rip_end;
 
 static sem_t vcpu_ready;
 
-static inline uint64_t guest_spin_on_val(uint64_t spin_val)
+static inline u64 guest_spin_on_val(u64 spin_val)
 {
-	uint64_t val;
+	u64 val;
 
 	do {
-		val = READ_ONCE(*((uint64_t *)MEM_REGION_GPA));
+		val = READ_ONCE(*((u64 *)MEM_REGION_GPA));
 	} while (val == spin_val);
 
 	GUEST_SYNC(0);
@@ -54,7 +54,7 @@ static void *vcpu_worker(void *data)
 	struct kvm_vcpu *vcpu = data;
 	struct kvm_run *run = vcpu->run;
 	struct ucall uc;
-	uint64_t cmd;
+	u64 cmd;
 
 	/*
 	 * Loop until the guest is done.  Re-enter the guest on all MMIO exits,
@@ -111,8 +111,8 @@ static struct kvm_vm *spawn_vm(struct kvm_vcpu **vcpu, pthread_t *vcpu_thread,
 			       void *guest_code)
 {
 	struct kvm_vm *vm;
-	uint64_t *hva;
-	uint64_t gpa;
+	u64 *hva;
+	gpa_t gpa;
 
 	vm = vm_create_with_one_vcpu(vcpu, guest_code);
 
@@ -144,7 +144,7 @@ static struct kvm_vm *spawn_vm(struct kvm_vcpu **vcpu, pthread_t *vcpu_thread,
 
 static void guest_code_move_memory_region(void)
 {
-	uint64_t val;
+	u64 val;
 
 	GUEST_SYNC(0);
 
@@ -180,7 +180,7 @@ static void test_move_memory_region(bool disable_slot_zap_quirk)
 	pthread_t vcpu_thread;
 	struct kvm_vcpu *vcpu;
 	struct kvm_vm *vm;
-	uint64_t *hva;
+	u64 *hva;
 
 	vm = spawn_vm(&vcpu, &vcpu_thread, guest_code_move_memory_region);
 
@@ -224,7 +224,7 @@ static void test_move_memory_region(bool disable_slot_zap_quirk)
 static void guest_code_delete_memory_region(void)
 {
 	struct desc_ptr idt;
-	uint64_t val;
+	u64 val;
 
 	/*
 	 * Clobber the IDT so that a #PF due to the memory region being deleted
@@ -345,8 +345,8 @@ static void test_zero_memory_regions(void)
 
 static void test_invalid_memory_region_flags(void)
 {
-	uint32_t supported_flags = KVM_MEM_LOG_DIRTY_PAGES;
-	const uint32_t v2_only_flags = KVM_MEM_GUEST_MEMFD;
+	u32 supported_flags = KVM_MEM_LOG_DIRTY_PAGES;
+	const u32 v2_only_flags = KVM_MEM_GUEST_MEMFD;
 	struct kvm_vm *vm;
 	int r, i;
 
@@ -410,8 +410,8 @@ static void test_add_max_memory_regions(void)
 {
 	int ret;
 	struct kvm_vm *vm;
-	uint32_t max_mem_slots;
-	uint32_t slot;
+	u32 max_mem_slots;
+	u32 slot;
 	void *mem, *mem_aligned, *mem_extra;
 	size_t alignment = 1;
 
@@ -434,16 +434,16 @@ static void test_add_max_memory_regions(void)
 
 	for (slot = 0; slot < max_mem_slots; slot++)
 		vm_set_user_memory_region(vm, slot, 0,
-					  ((uint64_t)slot * MEM_REGION_SIZE),
+					  ((u64)slot * MEM_REGION_SIZE),
 					  MEM_REGION_SIZE,
-					  mem_aligned + (uint64_t)slot * MEM_REGION_SIZE);
+					  mem_aligned + (u64)slot * MEM_REGION_SIZE);
 
 	/* Check it cannot be added memory slots beyond the limit */
 	mem_extra = kvm_mmap(MEM_REGION_SIZE, PROT_READ | PROT_WRITE,
 			     MAP_PRIVATE | MAP_ANONYMOUS, -1);
 
 	ret = __vm_set_user_memory_region(vm, max_mem_slots, 0,
-					  (uint64_t)max_mem_slots * MEM_REGION_SIZE,
+					  (u64)max_mem_slots * MEM_REGION_SIZE,
 					  MEM_REGION_SIZE, mem_extra);
 	TEST_ASSERT(ret == -1 && errno == EINVAL,
 		    "Adding one more memory slot should fail with EINVAL");
@@ -556,7 +556,7 @@ static void guest_code_mmio_during_vectoring(void)
 	set_idt(&idt_desc);
 
 	/* Generate a #GP by dereferencing a non-canonical address */
-	*((uint8_t *)NONCANONICAL) = 0x1;
+	*((u8 *)NONCANONICAL) = 0x1;
 
 	GUEST_ASSERT(0);
 }
diff --git a/tools/testing/selftests/kvm/steal_time.c b/tools/testing/selftests/kvm/steal_time.c
index efe56a10d13e..d46968f5579e 100644
--- a/tools/testing/selftests/kvm/steal_time.c
+++ b/tools/testing/selftests/kvm/steal_time.c
@@ -25,7 +25,7 @@
 #define ST_GPA_BASE		(1 << 30)
 
 static void *st_gva[NR_VCPUS];
-static uint64_t guest_stolen_time[NR_VCPUS];
+static u64 guest_stolen_time[NR_VCPUS];
 
 #if defined(__x86_64__)
 
@@ -42,9 +42,9 @@ static void check_status(struct kvm_steal_time *st)
 static void guest_code(int cpu)
 {
 	struct kvm_steal_time *st = st_gva[cpu];
-	uint32_t version;
+	u32 version;
 
-	GUEST_ASSERT_EQ(rdmsr(MSR_KVM_STEAL_TIME), ((uint64_t)st_gva[cpu] | KVM_MSR_ENABLED));
+	GUEST_ASSERT_EQ(rdmsr(MSR_KVM_STEAL_TIME), ((u64)st_gva[cpu] | KVM_MSR_ENABLED));
 
 	memset(st, 0, sizeof(*st));
 	GUEST_SYNC(0);
@@ -67,7 +67,7 @@ static bool is_steal_time_supported(struct kvm_vcpu *vcpu)
 	return kvm_cpu_has(X86_FEATURE_KVM_STEAL_TIME);
 }
 
-static void steal_time_init(struct kvm_vcpu *vcpu, uint32_t i)
+static void steal_time_init(struct kvm_vcpu *vcpu, u32 i)
 {
 	/* ST_GPA_BASE is identity mapped */
 	st_gva[i] = (void *)(ST_GPA_BASE + i * STEAL_TIME_SIZE);
@@ -76,7 +76,7 @@ static void steal_time_init(struct kvm_vcpu *vcpu, uint32_t i)
 	vcpu_set_msr(vcpu, MSR_KVM_STEAL_TIME, (ulong)st_gva[i] | KVM_MSR_ENABLED);
 }
 
-static void steal_time_dump(struct kvm_vm *vm, uint32_t vcpu_idx)
+static void steal_time_dump(struct kvm_vm *vm, u32 vcpu_idx)
 {
 	struct kvm_steal_time *st = addr_gva2hva(vm, (ulong)st_gva[vcpu_idx]);
 
@@ -118,12 +118,12 @@ static void check_steal_time_uapi(void)
 #define PV_TIME_ST		0xc5000021
 
 struct st_time {
-	uint32_t rev;
-	uint32_t attr;
-	uint64_t st_time;
+	u32 rev;
+	u32 attr;
+	u64 st_time;
 };
 
-static int64_t smccc(uint32_t func, uint64_t arg)
+static s64 smccc(u32 func, u64 arg)
 {
 	struct arm_smccc_res res;
 
@@ -140,7 +140,7 @@ static void check_status(struct st_time *st)
 static void guest_code(int cpu)
 {
 	struct st_time *st;
-	int64_t status;
+	s64 status;
 
 	status = smccc(SMCCC_ARCH_FEATURES, PV_TIME_FEATURES);
 	GUEST_ASSERT_EQ(status, 0);
@@ -175,15 +175,15 @@ static bool is_steal_time_supported(struct kvm_vcpu *vcpu)
 	return !__vcpu_ioctl(vcpu, KVM_HAS_DEVICE_ATTR, &dev);
 }
 
-static void steal_time_init(struct kvm_vcpu *vcpu, uint32_t i)
+static void steal_time_init(struct kvm_vcpu *vcpu, u32 i)
 {
 	struct kvm_vm *vm = vcpu->vm;
-	uint64_t st_ipa;
+	u64 st_ipa;
 
 	struct kvm_device_attr dev = {
 		.group = KVM_ARM_VCPU_PVTIME_CTRL,
 		.attr = KVM_ARM_VCPU_PVTIME_IPA,
-		.addr = (uint64_t)&st_ipa,
+		.addr = (u64)&st_ipa,
 	};
 
 	/* ST_GPA_BASE is identity mapped */
@@ -194,7 +194,7 @@ static void steal_time_init(struct kvm_vcpu *vcpu, uint32_t i)
 	vcpu_ioctl(vcpu, KVM_SET_DEVICE_ATTR, &dev);
 }
 
-static void steal_time_dump(struct kvm_vm *vm, uint32_t vcpu_idx)
+static void steal_time_dump(struct kvm_vm *vm, u32 vcpu_idx)
 {
 	struct st_time *st = addr_gva2hva(vm, (ulong)st_gva[vcpu_idx]);
 
@@ -208,7 +208,7 @@ static void check_steal_time_uapi(void)
 {
 	struct kvm_vm *vm;
 	struct kvm_vcpu *vcpu;
-	uint64_t st_ipa;
+	u64 st_ipa;
 	int ret;
 
 	vm = vm_create_with_one_vcpu(&vcpu, NULL);
@@ -216,7 +216,7 @@ static void check_steal_time_uapi(void)
 	struct kvm_device_attr dev = {
 		.group = KVM_ARM_VCPU_PVTIME_CTRL,
 		.attr = KVM_ARM_VCPU_PVTIME_IPA,
-		.addr = (uint64_t)&st_ipa,
+		.addr = (u64)&st_ipa,
 	};
 
 	vcpu_ioctl(vcpu, KVM_HAS_DEVICE_ATTR, &dev);
@@ -239,17 +239,17 @@ static void check_steal_time_uapi(void)
 /* SBI STA shmem must have 64-byte alignment */
 #define STEAL_TIME_SIZE		((sizeof(struct sta_struct) + 63) & ~63)
 
-static vm_paddr_t st_gpa[NR_VCPUS];
+static gpa_t st_gpa[NR_VCPUS];
 
 struct sta_struct {
-	uint32_t sequence;
-	uint32_t flags;
-	uint64_t steal;
-	uint8_t preempted;
-	uint8_t pad[47];
+	u32 sequence;
+	u32 flags;
+	u64 steal;
+	u8 preempted;
+	u8 pad[47];
 } __packed;
 
-static void sta_set_shmem(vm_paddr_t gpa, unsigned long flags)
+static void sta_set_shmem(gpa_t gpa, unsigned long flags)
 {
 	unsigned long lo = (unsigned long)gpa;
 #if __riscv_xlen == 32
@@ -272,7 +272,7 @@ static void check_status(struct sta_struct *st)
 static void guest_code(int cpu)
 {
 	struct sta_struct *st = st_gva[cpu];
-	uint32_t sequence;
+	u32 sequence;
 	long out_val = 0;
 	bool probe;
 
@@ -297,7 +297,7 @@ static void guest_code(int cpu)
 
 static bool is_steal_time_supported(struct kvm_vcpu *vcpu)
 {
-	uint64_t id = RISCV_SBI_EXT_REG(KVM_RISCV_SBI_EXT_STA);
+	u64 id = RISCV_SBI_EXT_REG(KVM_RISCV_SBI_EXT_STA);
 	unsigned long enabled = vcpu_get_reg(vcpu, id);
 
 	TEST_ASSERT(enabled == 0 || enabled == 1, "Expected boolean result");
@@ -305,16 +305,16 @@ static bool is_steal_time_supported(struct kvm_vcpu *vcpu)
 	return enabled;
 }
 
-static void steal_time_init(struct kvm_vcpu *vcpu, uint32_t i)
+static void steal_time_init(struct kvm_vcpu *vcpu, u32 i)
 {
 	/* ST_GPA_BASE is identity mapped */
 	st_gva[i] = (void *)(ST_GPA_BASE + i * STEAL_TIME_SIZE);
-	st_gpa[i] = addr_gva2gpa(vcpu->vm, (vm_vaddr_t)st_gva[i]);
+	st_gpa[i] = addr_gva2gpa(vcpu->vm, (gva_t)st_gva[i]);
 	sync_global_to_guest(vcpu->vm, st_gva[i]);
 	sync_global_to_guest(vcpu->vm, st_gpa[i]);
 }
 
-static void steal_time_dump(struct kvm_vm *vm, uint32_t vcpu_idx)
+static void steal_time_dump(struct kvm_vm *vm, u32 vcpu_idx)
 {
 	struct sta_struct *st = addr_gva2hva(vm, (ulong)st_gva[vcpu_idx]);
 	int i;
@@ -335,7 +335,7 @@ static void check_steal_time_uapi(void)
 	struct kvm_vm *vm;
 	struct kvm_vcpu *vcpu;
 	struct kvm_one_reg reg;
-	uint64_t shmem;
+	u64 shmem;
 	int ret;
 
 	vm = vm_create_with_one_vcpu(&vcpu, NULL);
@@ -345,7 +345,7 @@ static void check_steal_time_uapi(void)
 			 KVM_REG_RISCV_SBI_STATE |
 			 KVM_REG_RISCV_SBI_STA |
 			 KVM_REG_RISCV_SBI_STA_REG(shmem_lo);
-	reg.addr = (uint64_t)&shmem;
+	reg.addr = (u64)&shmem;
 
 	shmem = ST_GPA_BASE + 1;
 	ret = __vcpu_ioctl(vcpu, KVM_SET_ONE_REG, &reg);
@@ -388,7 +388,7 @@ static void check_status(struct kvm_steal_time *st)
 
 static void guest_code(int cpu)
 {
-	uint32_t version;
+	u32 version;
 	struct kvm_steal_time *st = st_gva[cpu];
 
 	memset(st, 0, sizeof(*st));
@@ -410,11 +410,11 @@ static void guest_code(int cpu)
 static bool is_steal_time_supported(struct kvm_vcpu *vcpu)
 {
 	int err;
-	uint64_t val;
+	u64 val;
 	struct kvm_device_attr attr = {
 		.group = KVM_LOONGARCH_VCPU_CPUCFG,
 		.attr = CPUCFG_KVM_FEATURE,
-		.addr = (uint64_t)&val,
+		.addr = (u64)&val,
 	};
 
 	err = __vcpu_ioctl(vcpu, KVM_HAS_DEVICE_ATTR, &attr);
@@ -428,15 +428,15 @@ static bool is_steal_time_supported(struct kvm_vcpu *vcpu)
 	return val & BIT(KVM_FEATURE_STEAL_TIME);
 }
 
-static void steal_time_init(struct kvm_vcpu *vcpu, uint32_t i)
+static void steal_time_init(struct kvm_vcpu *vcpu, u32 i)
 {
 	int err;
-	uint64_t st_gpa;
+	u64 st_gpa;
 	struct kvm_vm *vm = vcpu->vm;
 	struct kvm_device_attr attr = {
 		.group = KVM_LOONGARCH_VCPU_PVTIME_CTRL,
 		.attr = KVM_LOONGARCH_VCPU_PVTIME_GPA,
-		.addr = (uint64_t)&st_gpa,
+		.addr = (u64)&st_gpa,
 	};
 
 	/* ST_GPA_BASE is identity mapped */
@@ -451,7 +451,7 @@ static void steal_time_init(struct kvm_vcpu *vcpu, uint32_t i)
 	TEST_ASSERT(err == 0, "Fail to set PV stealtime GPA");
 }
 
-static void steal_time_dump(struct kvm_vm *vm, uint32_t vcpu_idx)
+static void steal_time_dump(struct kvm_vm *vm, u32 vcpu_idx)
 {
 	struct kvm_steal_time *st = addr_gva2hva(vm, (ulong)st_gva[vcpu_idx]);
 
diff --git a/tools/testing/selftests/kvm/system_counter_offset_test.c b/tools/testing/selftests/kvm/system_counter_offset_test.c
index 513d421a9bff..dc5e30b7b77f 100644
--- a/tools/testing/selftests/kvm/system_counter_offset_test.c
+++ b/tools/testing/selftests/kvm/system_counter_offset_test.c
@@ -17,7 +17,7 @@
 #ifdef __x86_64__
 
 struct test_case {
-	uint64_t tsc_offset;
+	u64 tsc_offset;
 };
 
 static struct test_case test_cases[] = {
@@ -39,12 +39,12 @@ static void setup_system_counter(struct kvm_vcpu *vcpu, struct test_case *test)
 			     &test->tsc_offset);
 }
 
-static uint64_t guest_read_system_counter(struct test_case *test)
+static u64 guest_read_system_counter(struct test_case *test)
 {
 	return rdtsc();
 }
 
-static uint64_t host_read_guest_system_counter(struct test_case *test)
+static u64 host_read_guest_system_counter(struct test_case *test)
 {
 	return rdtsc() + test->tsc_offset;
 }
@@ -69,9 +69,9 @@ static void guest_main(void)
 	}
 }
 
-static void handle_sync(struct ucall *uc, uint64_t start, uint64_t end)
+static void handle_sync(struct ucall *uc, u64 start, u64 end)
 {
-	uint64_t obs = uc->args[2];
+	u64 obs = uc->args[2];
 
 	TEST_ASSERT(start <= obs && obs <= end,
 		    "unexpected system counter value: %"PRIu64" expected range: [%"PRIu64", %"PRIu64"]",
@@ -88,7 +88,7 @@ static void handle_abort(struct ucall *uc)
 
 static void enter_guest(struct kvm_vcpu *vcpu)
 {
-	uint64_t start, end;
+	u64 start, end;
 	struct ucall uc;
 	int i;
 
diff --git a/tools/testing/selftests/kvm/x86/amx_test.c b/tools/testing/selftests/kvm/x86/amx_test.c
index 37b166260ee3..4e63da2b1889 100644
--- a/tools/testing/selftests/kvm/x86/amx_test.c
+++ b/tools/testing/selftests/kvm/x86/amx_test.c
@@ -80,10 +80,10 @@ static inline void __tilerelease(void)
 	asm volatile(".byte 0xc4, 0xe2, 0x78, 0x49, 0xc0" ::);
 }
 
-static inline void __xsavec(struct xstate *xstate, uint64_t rfbm)
+static inline void __xsavec(struct xstate *xstate, u64 rfbm)
 {
-	uint32_t rfbm_lo = rfbm;
-	uint32_t rfbm_hi = rfbm >> 32;
+	u32 rfbm_lo = rfbm;
+	u32 rfbm_hi = rfbm >> 32;
 
 	asm volatile("xsavec (%%rdi)"
 		     : : "D" (xstate), "a" (rfbm_lo), "d" (rfbm_hi)
@@ -236,7 +236,7 @@ int main(int argc, char *argv[])
 	struct kvm_x86_state *state;
 	struct kvm_x86_state *tile_state = NULL;
 	int xsave_restore_size;
-	vm_vaddr_t amx_cfg, tiledata, xstate;
+	gva_t amx_cfg, tiledata, xstate;
 	struct ucall uc;
 	int ret;
 
@@ -263,15 +263,15 @@ int main(int argc, char *argv[])
 	vcpu_regs_get(vcpu, &regs1);
 
 	/* amx cfg for guest_code */
-	amx_cfg = vm_vaddr_alloc_page(vm);
+	amx_cfg = vm_alloc_page(vm);
 	memset(addr_gva2hva(vm, amx_cfg), 0x0, getpagesize());
 
 	/* amx tiledata for guest_code */
-	tiledata = vm_vaddr_alloc_pages(vm, 2);
+	tiledata = vm_alloc_pages(vm, 2);
 	memset(addr_gva2hva(vm, tiledata), rand() | 1, 2 * getpagesize());
 
 	/* XSAVE state for guest_code */
-	xstate = vm_vaddr_alloc_pages(vm, DIV_ROUND_UP(XSAVE_SIZE, PAGE_SIZE));
+	xstate = vm_alloc_pages(vm, DIV_ROUND_UP(XSAVE_SIZE, PAGE_SIZE));
 	memset(addr_gva2hva(vm, xstate), 0, PAGE_SIZE * DIV_ROUND_UP(XSAVE_SIZE, PAGE_SIZE));
 	vcpu_args_set(vcpu, 3, amx_cfg, tiledata, xstate);
 
diff --git a/tools/testing/selftests/kvm/x86/aperfmperf_test.c b/tools/testing/selftests/kvm/x86/aperfmperf_test.c
index 8b15a13df939..c91660103137 100644
--- a/tools/testing/selftests/kvm/x86/aperfmperf_test.c
+++ b/tools/testing/selftests/kvm/x86/aperfmperf_test.c
@@ -35,9 +35,9 @@ static int open_dev_msr(int cpu)
 	return open_path_or_exit(path, O_RDONLY);
 }
 
-static uint64_t read_dev_msr(int msr_fd, uint32_t msr)
+static u64 read_dev_msr(int msr_fd, u32 msr)
 {
-	uint64_t data;
+	u64 data;
 	ssize_t rc;
 
 	rc = pread(msr_fd, &data, sizeof(data), msr);
@@ -107,8 +107,8 @@ static void guest_code(void *nested_test_data)
 
 static void guest_no_aperfmperf(void)
 {
-	uint64_t msr_val;
-	uint8_t vector;
+	u64 msr_val;
+	u8 vector;
 
 	vector = rdmsr_safe(MSR_IA32_APERF, &msr_val);
 	GUEST_ASSERT(vector == GP_VECTOR);
@@ -122,8 +122,8 @@ static void guest_no_aperfmperf(void)
 int main(int argc, char *argv[])
 {
 	const bool has_nested = kvm_cpu_has(X86_FEATURE_SVM) || kvm_cpu_has(X86_FEATURE_VMX);
-	uint64_t host_aperf_before, host_mperf_before;
-	vm_vaddr_t nested_test_data_gva;
+	u64 host_aperf_before, host_mperf_before;
+	gva_t nested_test_data_gva;
 	struct kvm_vcpu *vcpu;
 	struct kvm_vm *vm;
 	int msr_fd, cpu, i;
@@ -166,8 +166,8 @@ int main(int argc, char *argv[])
 	host_mperf_before = read_dev_msr(msr_fd, MSR_IA32_MPERF);
 
 	for (i = 0; i <= NUM_ITERATIONS * (1 + has_nested); i++) {
-		uint64_t host_aperf_after, host_mperf_after;
-		uint64_t guest_aperf, guest_mperf;
+		u64 host_aperf_after, host_mperf_after;
+		u64 guest_aperf, guest_mperf;
 		struct ucall uc;
 
 		vcpu_run(vcpu);
diff --git a/tools/testing/selftests/kvm/x86/apic_bus_clock_test.c b/tools/testing/selftests/kvm/x86/apic_bus_clock_test.c
index f8916bb34405..404f0028e110 100644
--- a/tools/testing/selftests/kvm/x86/apic_bus_clock_test.c
+++ b/tools/testing/selftests/kvm/x86/apic_bus_clock_test.c
@@ -19,8 +19,8 @@
  * timer frequency.
  */
 static const struct {
-	const uint32_t tdcr;
-	const uint32_t divide_count;
+	const u32 tdcr;
+	const u32 divide_count;
 } tdcrs[] = {
 	{0x0, 2},
 	{0x1, 4},
@@ -42,12 +42,12 @@ static void apic_enable(void)
 		xapic_enable();
 }
 
-static uint32_t apic_read_reg(unsigned int reg)
+static u32 apic_read_reg(unsigned int reg)
 {
 	return is_x2apic ? x2apic_read_reg(reg) : xapic_read_reg(reg);
 }
 
-static void apic_write_reg(unsigned int reg, uint32_t val)
+static void apic_write_reg(unsigned int reg, u32 val)
 {
 	if (is_x2apic)
 		x2apic_write_reg(reg, val);
@@ -55,12 +55,12 @@ static void apic_write_reg(unsigned int reg, uint32_t val)
 		xapic_write_reg(reg, val);
 }
 
-static void apic_guest_code(uint64_t apic_hz, uint64_t delay_ms)
+static void apic_guest_code(u64 apic_hz, u64 delay_ms)
 {
-	uint64_t tsc_hz = guest_tsc_khz * 1000;
-	const uint32_t tmict = ~0u;
-	uint64_t tsc0, tsc1, freq;
-	uint32_t tmcct;
+	u64 tsc_hz = guest_tsc_khz * 1000;
+	const u32 tmict = ~0u;
+	u64 tsc0, tsc1, freq;
+	u32 tmcct;
 	int i;
 
 	apic_enable();
@@ -121,7 +121,7 @@ static void test_apic_bus_clock(struct kvm_vcpu *vcpu)
 	}
 }
 
-static void run_apic_bus_clock_test(uint64_t apic_hz, uint64_t delay_ms,
+static void run_apic_bus_clock_test(u64 apic_hz, u64 delay_ms,
 				    bool x2apic)
 {
 	struct kvm_vcpu *vcpu;
@@ -168,8 +168,8 @@ int main(int argc, char *argv[])
 	 * Arbitrarilty default to 25MHz for the APIC bus frequency, which is
 	 * different enough from the default 1GHz to be interesting.
 	 */
-	uint64_t apic_hz = 25 * 1000 * 1000;
-	uint64_t delay_ms = 100;
+	u64 apic_hz = 25 * 1000 * 1000;
+	u64 delay_ms = 100;
 	int opt;
 
 	TEST_REQUIRE(kvm_has_cap(KVM_CAP_X86_APIC_BUS_CYCLES_NS));
diff --git a/tools/testing/selftests/kvm/x86/cpuid_test.c b/tools/testing/selftests/kvm/x86/cpuid_test.c
index f9ed14996977..ef0ddd240887 100644
--- a/tools/testing/selftests/kvm/x86/cpuid_test.c
+++ b/tools/testing/selftests/kvm/x86/cpuid_test.c
@@ -140,10 +140,10 @@ static void run_vcpu(struct kvm_vcpu *vcpu, int stage)
 	}
 }
 
-struct kvm_cpuid2 *vcpu_alloc_cpuid(struct kvm_vm *vm, vm_vaddr_t *p_gva, struct kvm_cpuid2 *cpuid)
+struct kvm_cpuid2 *vcpu_alloc_cpuid(struct kvm_vm *vm, gva_t *p_gva, struct kvm_cpuid2 *cpuid)
 {
 	int size = sizeof(*cpuid) + cpuid->nent * sizeof(cpuid->entries[0]);
-	vm_vaddr_t gva = vm_vaddr_alloc(vm, size, KVM_UTIL_MIN_VADDR);
+	gva_t gva = vm_alloc(vm, size, KVM_UTIL_MIN_VADDR);
 	struct kvm_cpuid2 *guest_cpuids = addr_gva2hva(vm, gva);
 
 	memcpy(guest_cpuids, cpuid, size);
@@ -217,7 +217,7 @@ static void test_get_cpuid2(struct kvm_vcpu *vcpu)
 int main(void)
 {
 	struct kvm_vcpu *vcpu;
-	vm_vaddr_t cpuid_gva;
+	gva_t cpuid_gva;
 	struct kvm_vm *vm;
 	int stage;
 
diff --git a/tools/testing/selftests/kvm/x86/debug_regs.c b/tools/testing/selftests/kvm/x86/debug_regs.c
index 2d814c1d1dc4..0dfaf03cd0a0 100644
--- a/tools/testing/selftests/kvm/x86/debug_regs.c
+++ b/tools/testing/selftests/kvm/x86/debug_regs.c
@@ -16,7 +16,7 @@
 #define IRQ_VECTOR 0xAA
 
 /* For testing data access debug BP */
-uint32_t guest_value;
+u32 guest_value;
 
 extern unsigned char sw_bp, hw_bp, write_data, ss_start, bd_start;
 
@@ -86,7 +86,7 @@ int main(void)
 	struct kvm_run *run;
 	struct kvm_vm *vm;
 	struct ucall uc;
-	uint64_t cmd;
+	u64 cmd;
 	int i;
 	/* Instruction lengths starting at ss_start */
 	int ss_size[6] = {
diff --git a/tools/testing/selftests/kvm/x86/dirty_log_page_splitting_test.c b/tools/testing/selftests/kvm/x86/dirty_log_page_splitting_test.c
index b0d2b04a7ff2..388ba4101f97 100644
--- a/tools/testing/selftests/kvm/x86/dirty_log_page_splitting_test.c
+++ b/tools/testing/selftests/kvm/x86/dirty_log_page_splitting_test.c
@@ -23,7 +23,7 @@
 #define SLOTS		2
 #define ITERATIONS	2
 
-static uint64_t guest_percpu_mem_size = DEFAULT_PER_VCPU_MEM_SIZE;
+static u64 guest_percpu_mem_size = DEFAULT_PER_VCPU_MEM_SIZE;
 
 static enum vm_mem_backing_src_type backing_src = VM_MEM_SRC_ANONYMOUS_HUGETLB;
 
@@ -33,10 +33,10 @@ static int iteration;
 static int vcpu_last_completed_iteration[KVM_MAX_VCPUS];
 
 struct kvm_page_stats {
-	uint64_t pages_4k;
-	uint64_t pages_2m;
-	uint64_t pages_1g;
-	uint64_t hugepages;
+	u64 pages_4k;
+	u64 pages_2m;
+	u64 pages_1g;
+	u64 hugepages;
 };
 
 static void get_page_stats(struct kvm_vm *vm, struct kvm_page_stats *stats, const char *stage)
@@ -89,9 +89,9 @@ static void run_test(enum vm_guest_mode mode, void *unused)
 {
 	struct kvm_vm *vm;
 	unsigned long **bitmaps;
-	uint64_t guest_num_pages;
-	uint64_t host_num_pages;
-	uint64_t pages_per_slot;
+	u64 guest_num_pages;
+	u64 host_num_pages;
+	u64 pages_per_slot;
 	int i;
 	struct kvm_page_stats stats_populated;
 	struct kvm_page_stats stats_dirty_logging_enabled;
diff --git a/tools/testing/selftests/kvm/x86/evmcs_smm_controls_test.c b/tools/testing/selftests/kvm/x86/evmcs_smm_controls_test.c
index af7c90103396..5b3aef109cfc 100644
--- a/tools/testing/selftests/kvm/x86/evmcs_smm_controls_test.c
+++ b/tools/testing/selftests/kvm/x86/evmcs_smm_controls_test.c
@@ -29,13 +29,13 @@
  * SMI handler: runs in real-address mode.
  * Reports SMRAM_STAGE via port IO, then does RSM.
  */
-static uint8_t smi_handler[] = {
+static u8 smi_handler[] = {
 	0xb0, SMRAM_STAGE,    /* mov $SMRAM_STAGE, %al */
 	0xe4, SYNC_PORT,      /* in $SYNC_PORT, %al */
 	0x0f, 0xaa,           /* rsm */
 };
 
-static inline void sync_with_host(uint64_t phase)
+static inline void sync_with_host(u64 phase)
 {
 	asm volatile("in $" XSTR(SYNC_PORT) ", %%al \n"
 		     : "+a" (phase));
@@ -73,7 +73,7 @@ static void guest_code(struct vmx_pages *vmx_pages,
 
 int main(int argc, char *argv[])
 {
-	vm_vaddr_t vmx_pages_gva = 0, hv_pages_gva = 0;
+	gva_t vmx_pages_gva = 0, hv_pages_gva = 0;
 	struct hyperv_test_pages *hv;
 	struct hv_enlightened_vmcs *evmcs;
 	struct kvm_vcpu *vcpu;
diff --git a/tools/testing/selftests/kvm/x86/fastops_test.c b/tools/testing/selftests/kvm/x86/fastops_test.c
index 8926cfe0e209..c0d30ccd8767 100644
--- a/tools/testing/selftests/kvm/x86/fastops_test.c
+++ b/tools/testing/selftests/kvm/x86/fastops_test.c
@@ -15,7 +15,7 @@
 	"pop %[flags]\n\t"
 
 #define flags_constraint(flags_val) [flags]"=r"(flags_val)
-#define bt_constraint(__bt_val) [bt_val]"rm"((uint32_t)__bt_val)
+#define bt_constraint(__bt_val) [bt_val]"rm"((u32)__bt_val)
 
 #define guest_execute_fastop_1(FEP, insn, __val, __flags)				\
 ({											\
@@ -28,17 +28,17 @@
 #define guest_test_fastop_1(insn, type_t, __val)					\
 ({											\
 	type_t val = __val, ex_val = __val, input = __val;				\
-	uint64_t flags, ex_flags;							\
+	u64 flags, ex_flags;								\
 											\
 	guest_execute_fastop_1("", insn, ex_val, ex_flags);				\
 	guest_execute_fastop_1(KVM_FEP, insn, val, flags);				\
 											\
 	__GUEST_ASSERT(val == ex_val,							\
 		       "Wanted 0x%lx for '%s 0x%lx', got 0x%lx",			\
-		       (uint64_t)ex_val, insn, (uint64_t)input, (uint64_t)val);		\
+		       (u64)ex_val, insn, (u64)input, (u64)val);			\
 	__GUEST_ASSERT(flags == ex_flags,						\
 			"Wanted flags 0x%lx for '%s 0x%lx', got 0x%lx",			\
-			ex_flags, insn, (uint64_t)input, flags);			\
+			ex_flags, insn, (u64)input, flags);				\
 })
 
 #define guest_execute_fastop_2(FEP, insn, __input, __output, __flags)			\
@@ -52,18 +52,18 @@
 #define guest_test_fastop_2(insn, type_t, __val1, __val2)				\
 ({											\
 	type_t input = __val1, input2 = __val2, output = __val2, ex_output = __val2;	\
-	uint64_t flags, ex_flags;							\
+	u64 flags, ex_flags;								\
 											\
 	guest_execute_fastop_2("", insn, input, ex_output, ex_flags);			\
 	guest_execute_fastop_2(KVM_FEP, insn, input, output, flags);			\
 											\
 	__GUEST_ASSERT(output == ex_output,						\
 		       "Wanted 0x%lx for '%s 0x%lx 0x%lx', got 0x%lx",			\
-		       (uint64_t)ex_output, insn, (uint64_t)input,			\
-		       (uint64_t)input2, (uint64_t)output);				\
+		       (u64)ex_output, insn, (u64)input,				\
+		       (u64)input2, (u64)output);					\
 	__GUEST_ASSERT(flags == ex_flags,						\
 			"Wanted flags 0x%lx for '%s 0x%lx, 0x%lx', got 0x%lx",		\
-			ex_flags, insn, (uint64_t)input, (uint64_t)input2, flags);	\
+			ex_flags, insn, (u64)input, (u64)input2, flags);		\
 })
 
 #define guest_execute_fastop_cl(FEP, insn, __shift, __output, __flags)			\
@@ -77,25 +77,25 @@
 #define guest_test_fastop_cl(insn, type_t, __val1, __val2)				\
 ({											\
 	type_t output = __val2, ex_output = __val2, input = __val2;			\
-	uint8_t shift = __val1;								\
-	uint64_t flags, ex_flags;							\
+	u8 shift = __val1;								\
+	u64 flags, ex_flags;								\
 											\
 	guest_execute_fastop_cl("", insn, shift, ex_output, ex_flags);			\
 	guest_execute_fastop_cl(KVM_FEP, insn, shift, output, flags);			\
 											\
 	__GUEST_ASSERT(output == ex_output,						\
 		       "Wanted 0x%lx for '%s 0x%x, 0x%lx', got 0x%lx",			\
-		       (uint64_t)ex_output, insn, shift, (uint64_t)input,		\
-		       (uint64_t)output);						\
+		       (u64)ex_output, insn, shift, (u64)input,				\
+		       (u64)output);							\
 	__GUEST_ASSERT(flags == ex_flags,						\
 			"Wanted flags 0x%lx for '%s 0x%x, 0x%lx', got 0x%lx",		\
-			ex_flags, insn, shift, (uint64_t)input, flags);			\
+			ex_flags, insn, shift, (u64)input, flags);			\
 })
 
 #define guest_execute_fastop_div(__KVM_ASM_SAFE, insn, __a, __d, __rm, __flags)		\
 ({											\
-	uint64_t ign_error_code;							\
-	uint8_t vector;									\
+	u64 ign_error_code;								\
+	u8 vector;									\
 											\
 	__asm__ __volatile__(fastop(__KVM_ASM_SAFE(insn " %[denom]"))			\
 			     : "+a"(__a), "+d"(__d), flags_constraint(__flags),		\
@@ -109,8 +109,8 @@
 ({											\
 	type_t _a = __val1, _d = __val1, rm = __val2;					\
 	type_t a = _a, d = _d, ex_a = _a, ex_d = _d;					\
-	uint64_t flags, ex_flags;							\
-	uint8_t v, ex_v;								\
+	u64 flags, ex_flags;								\
+	u8 v, ex_v;									\
 											\
 	ex_v = guest_execute_fastop_div(KVM_ASM_SAFE, insn, ex_a, ex_d, rm, ex_flags);	\
 	v = guest_execute_fastop_div(KVM_ASM_SAFE_FEP, insn, a, d, rm, flags);		\
@@ -118,17 +118,17 @@
 	GUEST_ASSERT_EQ(v, ex_v);							\
 	__GUEST_ASSERT(v == ex_v,							\
 		       "Wanted vector 0x%x for '%s 0x%lx:0x%lx/0x%lx', got 0x%x",	\
-		       ex_v, insn, (uint64_t)_a, (uint64_t)_d, (uint64_t)rm, v);	\
+		       ex_v, insn, (u64)_a, (u64)_d, (u64)rm, v);			\
 	__GUEST_ASSERT(a == ex_a && d == ex_d,						\
 		       "Wanted 0x%lx:0x%lx for '%s 0x%lx:0x%lx/0x%lx', got 0x%lx:0x%lx",\
-		       (uint64_t)ex_a, (uint64_t)ex_d, insn, (uint64_t)_a,		\
-		       (uint64_t)_d, (uint64_t)rm, (uint64_t)a, (uint64_t)d);		\
+		       (u64)ex_a, (u64)ex_d, insn, (u64)_a,				\
+		       (u64)_d, (u64)rm, (u64)a, (u64)d);				\
 	__GUEST_ASSERT(v || ex_v || (flags == ex_flags),				\
 			"Wanted flags 0x%lx for '%s  0x%lx:0x%lx/0x%lx', got 0x%lx",	\
-			ex_flags, insn, (uint64_t)_a, (uint64_t)_d, (uint64_t)rm, flags);\
+			ex_flags, insn, (u64)_a, (u64)_d, (u64)rm, flags);\
 })
 
-static const uint64_t vals[] = {
+static const u64 vals[] = {
 	0,
 	1,
 	2,
@@ -185,10 +185,10 @@ if (sizeof(type_t) != 1) {							\
 
 static void guest_code(void)
 {
-	guest_test_fastops(uint8_t, "b");
-	guest_test_fastops(uint16_t, "w");
-	guest_test_fastops(uint32_t, "l");
-	guest_test_fastops(uint64_t, "q");
+	guest_test_fastops(u8, "b");
+	guest_test_fastops(u16, "w");
+	guest_test_fastops(u32, "l");
+	guest_test_fastops(u64, "q");
 
 	GUEST_DONE();
 }
diff --git a/tools/testing/selftests/kvm/x86/feature_msrs_test.c b/tools/testing/selftests/kvm/x86/feature_msrs_test.c
index a72f13ae2edb..158550701771 100644
--- a/tools/testing/selftests/kvm/x86/feature_msrs_test.c
+++ b/tools/testing/selftests/kvm/x86/feature_msrs_test.c
@@ -12,7 +12,7 @@
 #include "kvm_util.h"
 #include "processor.h"
 
-static bool is_kvm_controlled_msr(uint32_t msr)
+static bool is_kvm_controlled_msr(u32 msr)
 {
 	return msr == MSR_IA32_VMX_CR0_FIXED1 || msr == MSR_IA32_VMX_CR4_FIXED1;
 }
@@ -21,7 +21,7 @@ static bool is_kvm_controlled_msr(uint32_t msr)
  * For VMX MSRs with a "true" variant, KVM requires userspace to set the "true"
  * MSR, and doesn't allow setting the hidden version.
  */
-static bool is_hidden_vmx_msr(uint32_t msr)
+static bool is_hidden_vmx_msr(u32 msr)
 {
 	switch (msr) {
 	case MSR_IA32_VMX_PINBASED_CTLS:
@@ -34,15 +34,15 @@ static bool is_hidden_vmx_msr(uint32_t msr)
 	}
 }
 
-static bool is_quirked_msr(uint32_t msr)
+static bool is_quirked_msr(u32 msr)
 {
 	return msr != MSR_AMD64_DE_CFG;
 }
 
-static void test_feature_msr(uint32_t msr)
+static void test_feature_msr(u32 msr)
 {
-	const uint64_t supported_mask = kvm_get_feature_msr(msr);
-	uint64_t reset_value = is_quirked_msr(msr) ? supported_mask : 0;
+	const u64 supported_mask = kvm_get_feature_msr(msr);
+	u64 reset_value = is_quirked_msr(msr) ? supported_mask : 0;
 	struct kvm_vcpu *vcpu;
 	struct kvm_vm *vm;
 
diff --git a/tools/testing/selftests/kvm/x86/fix_hypercall_test.c b/tools/testing/selftests/kvm/x86/fix_hypercall_test.c
index 00b6e85735dd..753a0e730ea8 100644
--- a/tools/testing/selftests/kvm/x86/fix_hypercall_test.c
+++ b/tools/testing/selftests/kvm/x86/fix_hypercall_test.c
@@ -26,18 +26,18 @@ static void guest_ud_handler(struct ex_regs *regs)
 	regs->rip += HYPERCALL_INSN_SIZE;
 }
 
-static const uint8_t vmx_vmcall[HYPERCALL_INSN_SIZE]  = { 0x0f, 0x01, 0xc1 };
-static const uint8_t svm_vmmcall[HYPERCALL_INSN_SIZE] = { 0x0f, 0x01, 0xd9 };
+static const u8 vmx_vmcall[HYPERCALL_INSN_SIZE]  = { 0x0f, 0x01, 0xc1 };
+static const u8 svm_vmmcall[HYPERCALL_INSN_SIZE] = { 0x0f, 0x01, 0xd9 };
 
-extern uint8_t hypercall_insn[HYPERCALL_INSN_SIZE];
-static uint64_t do_sched_yield(uint8_t apic_id)
+extern u8 hypercall_insn[HYPERCALL_INSN_SIZE];
+static u64 do_sched_yield(u8 apic_id)
 {
-	uint64_t ret;
+	u64 ret;
 
 	asm volatile("hypercall_insn:\n\t"
 		     ".byte 0xcc,0xcc,0xcc\n\t"
 		     : "=a"(ret)
-		     : "a"((uint64_t)KVM_HC_SCHED_YIELD), "b"((uint64_t)apic_id)
+		     : "a"((u64)KVM_HC_SCHED_YIELD), "b"((u64)apic_id)
 		     : "memory");
 
 	return ret;
@@ -45,9 +45,9 @@ static uint64_t do_sched_yield(uint8_t apic_id)
 
 static void guest_main(void)
 {
-	const uint8_t *native_hypercall_insn;
-	const uint8_t *other_hypercall_insn;
-	uint64_t ret;
+	const u8 *native_hypercall_insn;
+	const u8 *other_hypercall_insn;
+	u64 ret;
 
 	if (host_cpu_is_intel) {
 		native_hypercall_insn = vmx_vmcall;
@@ -72,7 +72,7 @@ static void guest_main(void)
 	 * the "right" hypercall.
 	 */
 	if (quirk_disabled) {
-		GUEST_ASSERT(ret == (uint64_t)-EFAULT);
+		GUEST_ASSERT(ret == (u64)-EFAULT);
 		GUEST_ASSERT(!memcmp(other_hypercall_insn, hypercall_insn,
 			     HYPERCALL_INSN_SIZE));
 	} else {
diff --git a/tools/testing/selftests/kvm/x86/flds_emulation.h b/tools/testing/selftests/kvm/x86/flds_emulation.h
index 37b1a9f52864..fd6b6c67199a 100644
--- a/tools/testing/selftests/kvm/x86/flds_emulation.h
+++ b/tools/testing/selftests/kvm/x86/flds_emulation.h
@@ -12,7 +12,7 @@
  * KVM to emulate the instruction (e.g. by providing an MMIO address) to
  * exercise emulation failures.
  */
-static inline void flds(uint64_t address)
+static inline void flds(u64 address)
 {
 	__asm__ __volatile__(FLDS_MEM_EAX :: "a"(address));
 }
@@ -21,8 +21,8 @@ static inline void handle_flds_emulation_failure_exit(struct kvm_vcpu *vcpu)
 {
 	struct kvm_run *run = vcpu->run;
 	struct kvm_regs regs;
-	uint8_t *insn_bytes;
-	uint64_t flags;
+	u8 *insn_bytes;
+	u64 flags;
 
 	TEST_ASSERT_KVM_EXIT_REASON(vcpu, KVM_EXIT_INTERNAL_ERROR);
 
diff --git a/tools/testing/selftests/kvm/x86/hwcr_msr_test.c b/tools/testing/selftests/kvm/x86/hwcr_msr_test.c
index 10b1b0ba374e..8e20a03b3329 100644
--- a/tools/testing/selftests/kvm/x86/hwcr_msr_test.c
+++ b/tools/testing/selftests/kvm/x86/hwcr_msr_test.c
@@ -10,11 +10,11 @@
 
 void test_hwcr_bit(struct kvm_vcpu *vcpu, unsigned int bit)
 {
-	const uint64_t ignored = BIT_ULL(3) | BIT_ULL(6) | BIT_ULL(8);
-	const uint64_t valid = BIT_ULL(18) | BIT_ULL(24);
-	const uint64_t legal = ignored | valid;
-	uint64_t val = BIT_ULL(bit);
-	uint64_t actual;
+	const u64 ignored = BIT_ULL(3) | BIT_ULL(6) | BIT_ULL(8);
+	const u64 valid = BIT_ULL(18) | BIT_ULL(24);
+	const u64 legal = ignored | valid;
+	u64 val = BIT_ULL(bit);
+	u64 actual;
 	int r;
 
 	r = _vcpu_set_msr(vcpu, MSR_K7_HWCR, val);
diff --git a/tools/testing/selftests/kvm/x86/hyperv_clock.c b/tools/testing/selftests/kvm/x86/hyperv_clock.c
index e058bc676cd6..c083cea546dc 100644
--- a/tools/testing/selftests/kvm/x86/hyperv_clock.c
+++ b/tools/testing/selftests/kvm/x86/hyperv_clock.c
@@ -98,7 +98,7 @@ static inline void check_tsc_msr_tsc_page(struct ms_hyperv_tsc_page *tsc_page)
 	GUEST_ASSERT(r2 >= t1 && r2 - t2 < 100000);
 }
 
-static void guest_main(struct ms_hyperv_tsc_page *tsc_page, vm_paddr_t tsc_page_gpa)
+static void guest_main(struct ms_hyperv_tsc_page *tsc_page, gpa_t tsc_page_gpa)
 {
 	u64 tsc_scale, tsc_offset;
 
@@ -208,7 +208,7 @@ int main(void)
 	struct kvm_vcpu *vcpu;
 	struct kvm_vm *vm;
 	struct ucall uc;
-	vm_vaddr_t tsc_page_gva;
+	gva_t tsc_page_gva;
 	int stage;
 
 	TEST_REQUIRE(kvm_has_cap(KVM_CAP_HYPERV_TIME));
@@ -218,7 +218,7 @@ int main(void)
 
 	vcpu_set_hv_cpuid(vcpu);
 
-	tsc_page_gva = vm_vaddr_alloc_page(vm);
+	tsc_page_gva = vm_alloc_page(vm);
 	memset(addr_gva2hva(vm, tsc_page_gva), 0x0, getpagesize());
 	TEST_ASSERT((addr_gva2gpa(vm, tsc_page_gva) & (getpagesize() - 1)) == 0,
 		"TSC page has to be page aligned");
diff --git a/tools/testing/selftests/kvm/x86/hyperv_evmcs.c b/tools/testing/selftests/kvm/x86/hyperv_evmcs.c
index 74cf19661309..c7fa114aee20 100644
--- a/tools/testing/selftests/kvm/x86/hyperv_evmcs.c
+++ b/tools/testing/selftests/kvm/x86/hyperv_evmcs.c
@@ -30,7 +30,7 @@ static void guest_nmi_handler(struct ex_regs *regs)
 {
 }
 
-static inline void rdmsr_from_l2(uint32_t msr)
+static inline void rdmsr_from_l2(u32 msr)
 {
 	/* Currently, L1 doesn't preserve GPRs during vmexits. */
 	__asm__ __volatile__ ("rdmsr" : : "c"(msr) :
@@ -76,7 +76,7 @@ void l2_guest_code(void)
 }
 
 void guest_code(struct vmx_pages *vmx_pages, struct hyperv_test_pages *hv_pages,
-		vm_vaddr_t hv_hcall_page_gpa)
+		gpa_t hv_hcall_page_gpa)
 {
 #define L2_GUEST_STACK_SIZE 64
 	unsigned long l2_guest_stack[L2_GUEST_STACK_SIZE];
@@ -231,8 +231,8 @@ static struct kvm_vcpu *save_restore_vm(struct kvm_vm *vm,
 
 int main(int argc, char *argv[])
 {
-	vm_vaddr_t vmx_pages_gva = 0, hv_pages_gva = 0;
-	vm_vaddr_t hcall_page;
+	gva_t vmx_pages_gva = 0, hv_pages_gva = 0;
+	gva_t hcall_page;
 
 	struct kvm_vcpu *vcpu;
 	struct kvm_vm *vm;
@@ -246,7 +246,7 @@ int main(int argc, char *argv[])
 
 	vm = vm_create_with_one_vcpu(&vcpu, guest_code);
 
-	hcall_page = vm_vaddr_alloc_pages(vm, 1);
+	hcall_page = vm_alloc_pages(vm, 1);
 	memset(addr_gva2hva(vm, hcall_page), 0x0,  getpagesize());
 
 	vcpu_set_hv_cpuid(vcpu);
diff --git a/tools/testing/selftests/kvm/x86/hyperv_extended_hypercalls.c b/tools/testing/selftests/kvm/x86/hyperv_extended_hypercalls.c
index 949e08e98f31..ae047db7b1be 100644
--- a/tools/testing/selftests/kvm/x86/hyperv_extended_hypercalls.c
+++ b/tools/testing/selftests/kvm/x86/hyperv_extended_hypercalls.c
@@ -15,19 +15,19 @@
 /* Any value is fine */
 #define EXT_CAPABILITIES 0xbull
 
-static void guest_code(vm_paddr_t in_pg_gpa, vm_paddr_t out_pg_gpa,
-		       vm_vaddr_t out_pg_gva)
+static void guest_code(gpa_t in_pg_gpa, gpa_t out_pg_gpa,
+		       gva_t out_pg_gva)
 {
-	uint64_t *output_gva;
+	u64 *output_gva;
 
 	wrmsr(HV_X64_MSR_GUEST_OS_ID, HYPERV_LINUX_OS_ID);
 	wrmsr(HV_X64_MSR_HYPERCALL, in_pg_gpa);
 
-	output_gva = (uint64_t *)out_pg_gva;
+	output_gva = (u64 *)out_pg_gva;
 
 	hyperv_hypercall(HV_EXT_CALL_QUERY_CAPABILITIES, in_pg_gpa, out_pg_gpa);
 
-	/* TLFS states output will be a uint64_t value */
+	/* TLFS states output will be a u64 value */
 	GUEST_ASSERT_EQ(*output_gva, EXT_CAPABILITIES);
 
 	GUEST_DONE();
@@ -35,12 +35,12 @@ static void guest_code(vm_paddr_t in_pg_gpa, vm_paddr_t out_pg_gpa,
 
 int main(void)
 {
-	vm_vaddr_t hcall_out_page;
-	vm_vaddr_t hcall_in_page;
+	gva_t hcall_out_page;
+	gva_t hcall_in_page;
 	struct kvm_vcpu *vcpu;
 	struct kvm_run *run;
 	struct kvm_vm *vm;
-	uint64_t *outval;
+	u64 *outval;
 	struct ucall uc;
 
 	TEST_REQUIRE(kvm_has_cap(KVM_CAP_HYPERV_CPUID));
@@ -57,11 +57,11 @@ int main(void)
 	vcpu_set_hv_cpuid(vcpu);
 
 	/* Hypercall input */
-	hcall_in_page = vm_vaddr_alloc_pages(vm, 1);
+	hcall_in_page = vm_alloc_pages(vm, 1);
 	memset(addr_gva2hva(vm, hcall_in_page), 0x0, vm->page_size);
 
 	/* Hypercall output */
-	hcall_out_page = vm_vaddr_alloc_pages(vm, 1);
+	hcall_out_page = vm_alloc_pages(vm, 1);
 	memset(addr_gva2hva(vm, hcall_out_page), 0x0, vm->page_size);
 
 	vcpu_args_set(vcpu, 3, addr_gva2gpa(vm, hcall_in_page),
diff --git a/tools/testing/selftests/kvm/x86/hyperv_features.c b/tools/testing/selftests/kvm/x86/hyperv_features.c
index 130b9ce7e5dd..7347f1fe5157 100644
--- a/tools/testing/selftests/kvm/x86/hyperv_features.c
+++ b/tools/testing/selftests/kvm/x86/hyperv_features.c
@@ -22,27 +22,27 @@
 	KVM_X86_CPU_FEATURE(HYPERV_CPUID_ENLIGHTMENT_INFO, 0, EBX, 0)
 
 struct msr_data {
-	uint32_t idx;
+	u32 idx;
 	bool fault_expected;
 	bool write;
 	u64 write_val;
 };
 
 struct hcall_data {
-	uint64_t control;
-	uint64_t expect;
+	u64 control;
+	u64 expect;
 	bool ud_expected;
 };
 
-static bool is_write_only_msr(uint32_t msr)
+static bool is_write_only_msr(u32 msr)
 {
 	return msr == HV_X64_MSR_EOI;
 }
 
 static void guest_msr(struct msr_data *msr)
 {
-	uint8_t vector = 0;
-	uint64_t msr_val = 0;
+	u8 vector = 0;
+	u64 msr_val = 0;
 
 	GUEST_ASSERT(msr->idx);
 
@@ -82,10 +82,10 @@ static void guest_msr(struct msr_data *msr)
 	GUEST_DONE();
 }
 
-static void guest_hcall(vm_vaddr_t pgs_gpa, struct hcall_data *hcall)
+static void guest_hcall(gpa_t pgs_gpa, struct hcall_data *hcall)
 {
 	u64 res, input, output;
-	uint8_t vector;
+	u8 vector;
 
 	GUEST_ASSERT_NE(hcall->control, 0);
 
@@ -134,14 +134,14 @@ static void guest_test_msrs_access(void)
 	struct kvm_vm *vm;
 	struct ucall uc;
 	int stage = 0;
-	vm_vaddr_t msr_gva;
+	gva_t msr_gva;
 	struct msr_data *msr;
 	bool has_invtsc = kvm_cpu_has(X86_FEATURE_INVTSC);
 
 	while (true) {
 		vm = vm_create_with_one_vcpu(&vcpu, guest_msr);
 
-		msr_gva = vm_vaddr_alloc_page(vm);
+		msr_gva = vm_alloc_page(vm);
 		memset(addr_gva2hva(vm, msr_gva), 0x0, getpagesize());
 		msr = addr_gva2hva(vm, msr_gva);
 
@@ -523,17 +523,17 @@ static void guest_test_hcalls_access(void)
 	struct kvm_vm *vm;
 	struct ucall uc;
 	int stage = 0;
-	vm_vaddr_t hcall_page, hcall_params;
+	gva_t hcall_page, hcall_params;
 	struct hcall_data *hcall;
 
 	while (true) {
 		vm = vm_create_with_one_vcpu(&vcpu, guest_hcall);
 
 		/* Hypercall input/output */
-		hcall_page = vm_vaddr_alloc_pages(vm, 2);
+		hcall_page = vm_alloc_pages(vm, 2);
 		memset(addr_gva2hva(vm, hcall_page), 0x0, 2 * getpagesize());
 
-		hcall_params = vm_vaddr_alloc_page(vm);
+		hcall_params = vm_alloc_page(vm);
 		memset(addr_gva2hva(vm, hcall_params), 0x0, getpagesize());
 		hcall = addr_gva2hva(vm, hcall_params);
 
diff --git a/tools/testing/selftests/kvm/x86/hyperv_ipi.c b/tools/testing/selftests/kvm/x86/hyperv_ipi.c
index ca61836c4e32..771535f9aad3 100644
--- a/tools/testing/selftests/kvm/x86/hyperv_ipi.c
+++ b/tools/testing/selftests/kvm/x86/hyperv_ipi.c
@@ -18,7 +18,7 @@
 
 #define IPI_VECTOR	 0xfe
 
-static volatile uint64_t ipis_rcvd[RECEIVER_VCPU_ID_2 + 1];
+static volatile u64 ipis_rcvd[RECEIVER_VCPU_ID_2 + 1];
 
 struct hv_vpset {
 	u64 format;
@@ -45,13 +45,13 @@ struct hv_send_ipi_ex {
 	struct hv_vpset vp_set;
 };
 
-static inline void hv_init(vm_vaddr_t pgs_gpa)
+static inline void hv_init(gpa_t pgs_gpa)
 {
 	wrmsr(HV_X64_MSR_GUEST_OS_ID, HYPERV_LINUX_OS_ID);
 	wrmsr(HV_X64_MSR_HYPERCALL, pgs_gpa);
 }
 
-static void receiver_code(void *hcall_page, vm_vaddr_t pgs_gpa)
+static void receiver_code(void *hcall_page, gpa_t pgs_gpa)
 {
 	u32 vcpu_id;
 
@@ -85,7 +85,7 @@ static inline void nop_loop(void)
 		asm volatile("nop");
 }
 
-static void sender_guest_code(void *hcall_page, vm_vaddr_t pgs_gpa)
+static void sender_guest_code(void *hcall_page, gpa_t pgs_gpa)
 {
 	struct hv_send_ipi *ipi = (struct hv_send_ipi *)hcall_page;
 	struct hv_send_ipi_ex *ipi_ex = (struct hv_send_ipi_ex *)hcall_page;
@@ -243,7 +243,7 @@ int main(int argc, char *argv[])
 {
 	struct kvm_vm *vm;
 	struct kvm_vcpu *vcpu[3];
-	vm_vaddr_t hcall_page;
+	gva_t hcall_page;
 	pthread_t threads[2];
 	int stage = 1, r;
 	struct ucall uc;
@@ -253,7 +253,7 @@ int main(int argc, char *argv[])
 	vm = vm_create_with_one_vcpu(&vcpu[0], sender_guest_code);
 
 	/* Hypercall input/output */
-	hcall_page = vm_vaddr_alloc_pages(vm, 2);
+	hcall_page = vm_alloc_pages(vm, 2);
 	memset(addr_gva2hva(vm, hcall_page), 0x0, 2 * getpagesize());
 
 
diff --git a/tools/testing/selftests/kvm/x86/hyperv_svm_test.c b/tools/testing/selftests/kvm/x86/hyperv_svm_test.c
index 0ddb63229bcb..7a62f6a9d606 100644
--- a/tools/testing/selftests/kvm/x86/hyperv_svm_test.c
+++ b/tools/testing/selftests/kvm/x86/hyperv_svm_test.c
@@ -21,7 +21,7 @@
 #define L2_GUEST_STACK_SIZE 256
 
 /* Exit to L1 from L2 with RDMSR instruction */
-static inline void rdmsr_from_l2(uint32_t msr)
+static inline void rdmsr_from_l2(u32 msr)
 {
 	/* Currently, L1 doesn't preserve GPRs during vmexits. */
 	__asm__ __volatile__ ("rdmsr" : : "c"(msr) :
@@ -67,7 +67,7 @@ void l2_guest_code(void)
 
 static void __attribute__((__flatten__)) guest_code(struct svm_test_data *svm,
 						    struct hyperv_test_pages *hv_pages,
-						    vm_vaddr_t pgs_gpa)
+						    gpa_t pgs_gpa)
 {
 	unsigned long l2_guest_stack[L2_GUEST_STACK_SIZE];
 	struct vmcb *vmcb = svm->vmcb;
@@ -149,8 +149,8 @@ static void __attribute__((__flatten__)) guest_code(struct svm_test_data *svm,
 
 int main(int argc, char *argv[])
 {
-	vm_vaddr_t nested_gva = 0, hv_pages_gva = 0;
-	vm_vaddr_t hcall_page;
+	gva_t nested_gva = 0, hv_pages_gva = 0;
+	gva_t hcall_page;
 	struct kvm_vcpu *vcpu;
 	struct kvm_vm *vm;
 	struct ucall uc;
@@ -165,7 +165,7 @@ int main(int argc, char *argv[])
 	vcpu_alloc_svm(vm, &nested_gva);
 	vcpu_alloc_hyperv_test_pages(vm, &hv_pages_gva);
 
-	hcall_page = vm_vaddr_alloc_pages(vm, 1);
+	hcall_page = vm_alloc_pages(vm, 1);
 	memset(addr_gva2hva(vm, hcall_page), 0x0,  getpagesize());
 
 	vcpu_args_set(vcpu, 3, nested_gva, hv_pages_gva, addr_gva2gpa(vm, hcall_page));
diff --git a/tools/testing/selftests/kvm/x86/hyperv_tlb_flush.c b/tools/testing/selftests/kvm/x86/hyperv_tlb_flush.c
index c542cc4762b1..15ee8b7bfc11 100644
--- a/tools/testing/selftests/kvm/x86/hyperv_tlb_flush.c
+++ b/tools/testing/selftests/kvm/x86/hyperv_tlb_flush.c
@@ -61,14 +61,14 @@ struct hv_tlb_flush_ex {
  * - GVAs of the test pages' PTEs
  */
 struct test_data {
-	vm_vaddr_t hcall_gva;
-	vm_paddr_t hcall_gpa;
-	vm_vaddr_t test_pages;
-	vm_vaddr_t test_pages_pte[NTEST_PAGES];
+	gva_t hcall_gva;
+	gpa_t hcall_gpa;
+	gva_t test_pages;
+	gva_t test_pages_pte[NTEST_PAGES];
 };
 
 /* 'Worker' vCPU code checking the contents of the test page */
-static void worker_guest_code(vm_vaddr_t test_data)
+static void worker_guest_code(gva_t test_data)
 {
 	struct test_data *data = (struct test_data *)test_data;
 	u32 vcpu_id = rdmsr(HV_X64_MSR_VP_INDEX);
@@ -133,12 +133,12 @@ static void set_expected_val(void *addr, u64 val, int vcpu_id)
  * Update PTEs swapping two test pages.
  * TODO: use swap()/xchg() when these are provided.
  */
-static void swap_two_test_pages(vm_paddr_t pte_gva1, vm_paddr_t pte_gva2)
+static void swap_two_test_pages(gpa_t pte_gva1, gpa_t pte_gva2)
 {
-	uint64_t tmp = *(uint64_t *)pte_gva1;
+	u64 tmp = *(u64 *)pte_gva1;
 
-	*(uint64_t *)pte_gva1 = *(uint64_t *)pte_gva2;
-	*(uint64_t *)pte_gva2 = tmp;
+	*(u64 *)pte_gva1 = *(u64 *)pte_gva2;
+	*(u64 *)pte_gva2 = tmp;
 }
 
 /*
@@ -196,12 +196,12 @@ static inline void post_test(struct test_data *data, u64 exp1, u64 exp2)
 #define TESTVAL2 0x0202020202020202
 
 /* Main vCPU doing the test */
-static void sender_guest_code(vm_vaddr_t test_data)
+static void sender_guest_code(gva_t test_data)
 {
 	struct test_data *data = (struct test_data *)test_data;
 	struct hv_tlb_flush *flush = (struct hv_tlb_flush *)data->hcall_gva;
 	struct hv_tlb_flush_ex *flush_ex = (struct hv_tlb_flush_ex *)data->hcall_gva;
-	vm_paddr_t hcall_gpa = data->hcall_gpa;
+	gpa_t hcall_gpa = data->hcall_gpa;
 	int i, stage = 1;
 
 	wrmsr(HV_X64_MSR_GUEST_OS_ID, HYPERV_LINUX_OS_ID);
@@ -581,9 +581,9 @@ int main(int argc, char *argv[])
 	struct kvm_vm *vm;
 	struct kvm_vcpu *vcpu[3];
 	pthread_t threads[2];
-	vm_vaddr_t test_data_page, gva;
-	vm_paddr_t gpa;
-	uint64_t *pte;
+	gva_t test_data_page, gva;
+	gpa_t gpa;
+	u64 *pte;
 	struct test_data *data;
 	struct ucall uc;
 	int stage = 1, r, i;
@@ -593,11 +593,11 @@ int main(int argc, char *argv[])
 	vm = vm_create_with_one_vcpu(&vcpu[0], sender_guest_code);
 
 	/* Test data page */
-	test_data_page = vm_vaddr_alloc_page(vm);
+	test_data_page = vm_alloc_page(vm);
 	data = (struct test_data *)addr_gva2hva(vm, test_data_page);
 
 	/* Hypercall input/output */
-	data->hcall_gva = vm_vaddr_alloc_pages(vm, 2);
+	data->hcall_gva = vm_alloc_pages(vm, 2);
 	data->hcall_gpa = addr_gva2gpa(vm, data->hcall_gva);
 	memset(addr_gva2hva(vm, data->hcall_gva), 0x0, 2 * PAGE_SIZE);
 
@@ -606,7 +606,7 @@ int main(int argc, char *argv[])
 	 * and the test will swap their mappings. The third page keeps the indication
 	 * about the current state of mappings.
 	 */
-	data->test_pages = vm_vaddr_alloc_pages(vm, NTEST_PAGES + 1);
+	data->test_pages = vm_alloc_pages(vm, NTEST_PAGES + 1);
 	for (i = 0; i < NTEST_PAGES; i++)
 		memset(addr_gva2hva(vm, data->test_pages + PAGE_SIZE * i),
 		       (u8)(i + 1), PAGE_SIZE);
@@ -617,7 +617,7 @@ int main(int argc, char *argv[])
 	 * Get PTE pointers for test pages and map them inside the guest.
 	 * Use separate page for each PTE for simplicity.
 	 */
-	gva = vm_vaddr_unused_gap(vm, NTEST_PAGES * PAGE_SIZE, KVM_UTIL_MIN_VADDR);
+	gva = vm_unused_gva_gap(vm, NTEST_PAGES * PAGE_SIZE, KVM_UTIL_MIN_VADDR);
 	for (i = 0; i < NTEST_PAGES; i++) {
 		pte = vm_get_pte(vm, data->test_pages + i * PAGE_SIZE);
 		gpa = addr_hva2gpa(vm, pte);
diff --git a/tools/testing/selftests/kvm/x86/kvm_buslock_test.c b/tools/testing/selftests/kvm/x86/kvm_buslock_test.c
index d88500c118eb..52014a3210c8 100644
--- a/tools/testing/selftests/kvm/x86/kvm_buslock_test.c
+++ b/tools/testing/selftests/kvm/x86/kvm_buslock_test.c
@@ -73,7 +73,7 @@ static void guest_code(void *test_data)
 int main(int argc, char *argv[])
 {
 	const bool has_nested = kvm_cpu_has(X86_FEATURE_SVM) || kvm_cpu_has(X86_FEATURE_VMX);
-	vm_vaddr_t nested_test_data_gva;
+	gva_t nested_test_data_gva;
 	struct kvm_vcpu *vcpu;
 	struct kvm_run *run;
 	struct kvm_vm *vm;
diff --git a/tools/testing/selftests/kvm/x86/kvm_clock_test.c b/tools/testing/selftests/kvm/x86/kvm_clock_test.c
index 5bc12222d87a..5ad4aeb8e373 100644
--- a/tools/testing/selftests/kvm/x86/kvm_clock_test.c
+++ b/tools/testing/selftests/kvm/x86/kvm_clock_test.c
@@ -17,8 +17,8 @@
 #include "processor.h"
 
 struct test_case {
-	uint64_t kvmclock_base;
-	int64_t realtime_offset;
+	u64 kvmclock_base;
+	s64 realtime_offset;
 };
 
 static struct test_case test_cases[] = {
@@ -31,7 +31,7 @@ static struct test_case test_cases[] = {
 #define GUEST_SYNC_CLOCK(__stage, __val)			\
 		GUEST_SYNC_ARGS(__stage, __val, 0, 0, 0)
 
-static void guest_main(vm_paddr_t pvti_pa, struct pvclock_vcpu_time_info *pvti)
+static void guest_main(gpa_t pvti_pa, struct pvclock_vcpu_time_info *pvti)
 {
 	int i;
 
@@ -52,7 +52,7 @@ static inline void assert_flags(struct kvm_clock_data *data)
 static void handle_sync(struct ucall *uc, struct kvm_clock_data *start,
 			struct kvm_clock_data *end)
 {
-	uint64_t obs, exp_lo, exp_hi;
+	u64 obs, exp_lo, exp_hi;
 
 	obs = uc->args[2];
 	exp_lo = start->clock;
@@ -135,8 +135,8 @@ static void enter_guest(struct kvm_vcpu *vcpu)
 int main(void)
 {
 	struct kvm_vcpu *vcpu;
-	vm_vaddr_t pvti_gva;
-	vm_paddr_t pvti_gpa;
+	gva_t pvti_gva;
+	gpa_t pvti_gpa;
 	struct kvm_vm *vm;
 	int flags;
 
@@ -147,7 +147,7 @@ int main(void)
 
 	vm = vm_create_with_one_vcpu(&vcpu, guest_main);
 
-	pvti_gva = vm_vaddr_alloc(vm, getpagesize(), 0x10000);
+	pvti_gva = vm_alloc(vm, getpagesize(), 0x10000);
 	pvti_gpa = addr_gva2gpa(vm, pvti_gva);
 	vcpu_args_set(vcpu, 2, pvti_gpa, pvti_gva);
 
diff --git a/tools/testing/selftests/kvm/x86/kvm_pv_test.c b/tools/testing/selftests/kvm/x86/kvm_pv_test.c
index 1b805cbdb47b..8ed5fa635021 100644
--- a/tools/testing/selftests/kvm/x86/kvm_pv_test.c
+++ b/tools/testing/selftests/kvm/x86/kvm_pv_test.c
@@ -13,7 +13,7 @@
 #include "processor.h"
 
 struct msr_data {
-	uint32_t idx;
+	u32 idx;
 	const char *name;
 };
 
@@ -40,8 +40,8 @@ static struct msr_data msrs_to_test[] = {
 
 static void test_msr(struct msr_data *msr)
 {
-	uint64_t ignored;
-	uint8_t vector;
+	u64 ignored;
+	u8 vector;
 
 	PR_MSR(msr);
 
@@ -53,7 +53,7 @@ static void test_msr(struct msr_data *msr)
 }
 
 struct hcall_data {
-	uint64_t nr;
+	u64 nr;
 	const char *name;
 };
 
@@ -73,7 +73,7 @@ static struct hcall_data hcalls_to_test[] = {
 
 static void test_hcall(struct hcall_data *hc)
 {
-	uint64_t r;
+	u64 r;
 
 	PR_HCALL(hc);
 	r = kvm_hypercall(hc->nr, 0, 0, 0, 0);
diff --git a/tools/testing/selftests/kvm/x86/monitor_mwait_test.c b/tools/testing/selftests/kvm/x86/monitor_mwait_test.c
index e45c028d2a7e..9c156cf7db0e 100644
--- a/tools/testing/selftests/kvm/x86/monitor_mwait_test.c
+++ b/tools/testing/selftests/kvm/x86/monitor_mwait_test.c
@@ -67,7 +67,7 @@ static void guest_monitor_wait(void *arg)
 
 int main(int argc, char *argv[])
 {
-	uint64_t disabled_quirks;
+	u64 disabled_quirks;
 	struct kvm_vcpu *vcpu;
 	struct kvm_vm *vm;
 	struct ucall uc;
diff --git a/tools/testing/selftests/kvm/x86/nested_close_kvm_test.c b/tools/testing/selftests/kvm/x86/nested_close_kvm_test.c
index f001cb836bfa..761fec293408 100644
--- a/tools/testing/selftests/kvm/x86/nested_close_kvm_test.c
+++ b/tools/testing/selftests/kvm/x86/nested_close_kvm_test.c
@@ -67,7 +67,7 @@ static void l1_guest_code(void *data)
 
 int main(int argc, char *argv[])
 {
-	vm_vaddr_t guest_gva;
+	gva_t guest_gva;
 	struct kvm_vcpu *vcpu;
 	struct kvm_vm *vm;
 
diff --git a/tools/testing/selftests/kvm/x86/nested_dirty_log_test.c b/tools/testing/selftests/kvm/x86/nested_dirty_log_test.c
index 619229bbd693..0e67cce83570 100644
--- a/tools/testing/selftests/kvm/x86/nested_dirty_log_test.c
+++ b/tools/testing/selftests/kvm/x86/nested_dirty_log_test.c
@@ -47,10 +47,10 @@
 #define TEST_SYNC_WRITE_FAULT		BIT(1)
 #define TEST_SYNC_NO_FAULT		BIT(2)
 
-static void l2_guest_code(vm_vaddr_t base)
+static void l2_guest_code(gva_t base)
 {
-	vm_vaddr_t page0 = TEST_GUEST_ADDR(base, 0);
-	vm_vaddr_t page1 = TEST_GUEST_ADDR(base, 1);
+	gva_t page0 = TEST_GUEST_ADDR(base, 0);
+	gva_t page1 = TEST_GUEST_ADDR(base, 1);
 
 	READ_ONCE(*(u64 *)page0);
 	GUEST_SYNC(page0 | TEST_SYNC_READ_FAULT);
@@ -143,7 +143,7 @@ static void l1_guest_code(void *data)
 static void test_handle_ucall_sync(struct kvm_vm *vm, u64 arg,
 				   unsigned long *bmap)
 {
-	vm_vaddr_t gva = arg & ~(PAGE_SIZE - 1);
+	gva_t gva = arg & ~(PAGE_SIZE - 1);
 	int page_nr, i;
 
 	/*
@@ -198,7 +198,7 @@ static void test_handle_ucall_sync(struct kvm_vm *vm, u64 arg,
 
 static void test_dirty_log(bool nested_tdp)
 {
-	vm_vaddr_t nested_gva = 0;
+	gva_t nested_gva = 0;
 	unsigned long *bmap;
 	struct kvm_vcpu *vcpu;
 	struct kvm_vm *vm;
diff --git a/tools/testing/selftests/kvm/x86/nested_emulation_test.c b/tools/testing/selftests/kvm/x86/nested_emulation_test.c
index abc824dba04f..fb7dcbe53ac7 100644
--- a/tools/testing/selftests/kvm/x86/nested_emulation_test.c
+++ b/tools/testing/selftests/kvm/x86/nested_emulation_test.c
@@ -13,8 +13,8 @@ enum {
 
 struct emulated_instruction {
 	const char name[32];
-	uint8_t opcode[15];
-	uint32_t exit_reason[NR_VIRTUALIZATION_FLAVORS];
+	u8 opcode[15];
+	u32 exit_reason[NR_VIRTUALIZATION_FLAVORS];
 };
 
 static struct emulated_instruction instructions[] = {
@@ -32,13 +32,13 @@ static struct emulated_instruction instructions[] = {
 	},
 };
 
-static uint8_t kvm_fep[] = { 0x0f, 0x0b, 0x6b, 0x76, 0x6d };	/* ud2 ; .ascii "kvm" */
-static uint8_t l2_guest_code[sizeof(kvm_fep) + 15];
-static uint8_t *l2_instruction = &l2_guest_code[sizeof(kvm_fep)];
+static u8 kvm_fep[] = { 0x0f, 0x0b, 0x6b, 0x76, 0x6d };	/* ud2 ; .ascii "kvm" */
+static u8 l2_guest_code[sizeof(kvm_fep) + 15];
+static u8 *l2_instruction = &l2_guest_code[sizeof(kvm_fep)];
 
-static uint32_t get_instruction_length(struct emulated_instruction *insn)
+static u32 get_instruction_length(struct emulated_instruction *insn)
 {
-	uint32_t i;
+	u32 i;
 
 	for (i = 0; i < ARRAY_SIZE(insn->opcode) && insn->opcode[i]; i++)
 		;
@@ -81,8 +81,8 @@ static void guest_code(void *test_data)
 
 	for (i = 0; i < ARRAY_SIZE(instructions); i++) {
 		struct emulated_instruction *insn = &instructions[i];
-		uint32_t insn_len = get_instruction_length(insn);
-		uint32_t exit_insn_len;
+		u32 insn_len = get_instruction_length(insn);
+		u32 exit_insn_len;
 		u32 exit_reason;
 
 		/*
@@ -122,7 +122,7 @@ static void guest_code(void *test_data)
 
 int main(int argc, char *argv[])
 {
-	vm_vaddr_t nested_test_data_gva;
+	gva_t nested_test_data_gva;
 	struct kvm_vcpu *vcpu;
 	struct kvm_vm *vm;
 
diff --git a/tools/testing/selftests/kvm/x86/nested_exceptions_test.c b/tools/testing/selftests/kvm/x86/nested_exceptions_test.c
index 3641a42934ac..186e980aa8ee 100644
--- a/tools/testing/selftests/kvm/x86/nested_exceptions_test.c
+++ b/tools/testing/selftests/kvm/x86/nested_exceptions_test.c
@@ -72,7 +72,7 @@ static void l2_ss_injected_tf_test(void)
 }
 
 static void svm_run_l2(struct svm_test_data *svm, void *l2_code, int vector,
-		       uint32_t error_code)
+		       u32 error_code)
 {
 	struct vmcb *vmcb = svm->vmcb;
 	struct vmcb_control_area *ctrl = &vmcb->control;
@@ -111,7 +111,7 @@ static void l1_svm_code(struct svm_test_data *svm)
 	GUEST_DONE();
 }
 
-static void vmx_run_l2(void *l2_code, int vector, uint32_t error_code)
+static void vmx_run_l2(void *l2_code, int vector, u32 error_code)
 {
 	GUEST_ASSERT(!vmwrite(GUEST_RIP, (u64)l2_code));
 
@@ -216,7 +216,7 @@ static void queue_ss_exception(struct kvm_vcpu *vcpu, bool inject)
  */
 int main(int argc, char *argv[])
 {
-	vm_vaddr_t nested_test_data_gva;
+	gva_t nested_test_data_gva;
 	struct kvm_vcpu_events events;
 	struct kvm_vcpu *vcpu;
 	struct kvm_vm *vm;
diff --git a/tools/testing/selftests/kvm/x86/nested_invalid_cr3_test.c b/tools/testing/selftests/kvm/x86/nested_invalid_cr3_test.c
index a6b6da9cf7fe..11fd2467d823 100644
--- a/tools/testing/selftests/kvm/x86/nested_invalid_cr3_test.c
+++ b/tools/testing/selftests/kvm/x86/nested_invalid_cr3_test.c
@@ -78,7 +78,7 @@ int main(int argc, char *argv[])
 {
 	struct kvm_vcpu *vcpu;
 	struct kvm_vm *vm;
-	vm_vaddr_t guest_gva = 0;
+	gva_t guest_gva = 0;
 
 	TEST_REQUIRE(kvm_cpu_has(X86_FEATURE_VMX) ||
 		     kvm_cpu_has(X86_FEATURE_SVM));
diff --git a/tools/testing/selftests/kvm/x86/nested_set_state_test.c b/tools/testing/selftests/kvm/x86/nested_set_state_test.c
index 0f2102b43629..831380732671 100644
--- a/tools/testing/selftests/kvm/x86/nested_set_state_test.c
+++ b/tools/testing/selftests/kvm/x86/nested_set_state_test.c
@@ -250,14 +250,14 @@ void test_vmx_nested_state(struct kvm_vcpu *vcpu)
 
 static void vcpu_efer_enable_svm(struct kvm_vcpu *vcpu)
 {
-	uint64_t old_efer = vcpu_get_msr(vcpu, MSR_EFER);
+	u64 old_efer = vcpu_get_msr(vcpu, MSR_EFER);
 
 	vcpu_set_msr(vcpu, MSR_EFER, old_efer | EFER_SVME);
 }
 
 static void vcpu_efer_disable_svm(struct kvm_vcpu *vcpu)
 {
-	uint64_t old_efer = vcpu_get_msr(vcpu, MSR_EFER);
+	u64 old_efer = vcpu_get_msr(vcpu, MSR_EFER);
 
 	vcpu_set_msr(vcpu, MSR_EFER, old_efer & ~EFER_SVME);
 }
diff --git a/tools/testing/selftests/kvm/x86/nested_tsc_adjust_test.c b/tools/testing/selftests/kvm/x86/nested_tsc_adjust_test.c
index 2839f650e5c9..f0e4adac4751 100644
--- a/tools/testing/selftests/kvm/x86/nested_tsc_adjust_test.c
+++ b/tools/testing/selftests/kvm/x86/nested_tsc_adjust_test.c
@@ -53,9 +53,9 @@ enum {
 /* The virtual machine object. */
 static struct kvm_vm *vm;
 
-static void check_ia32_tsc_adjust(int64_t max)
+static void check_ia32_tsc_adjust(s64 max)
 {
-	int64_t adjust;
+	s64 adjust;
 
 	adjust = rdmsr(MSR_IA32_TSC_ADJUST);
 	GUEST_SYNC(adjust);
@@ -64,7 +64,7 @@ static void check_ia32_tsc_adjust(int64_t max)
 
 static void l2_guest_code(void)
 {
-	uint64_t l1_tsc = rdtsc() - TSC_OFFSET_VALUE;
+	u64 l1_tsc = rdtsc() - TSC_OFFSET_VALUE;
 
 	wrmsr(MSR_IA32_TSC, l1_tsc - TSC_ADJUST_VALUE);
 	check_ia32_tsc_adjust(-2 * TSC_ADJUST_VALUE);
@@ -88,7 +88,7 @@ static void l1_guest_code(void *data)
 	 */
 	if (this_cpu_has(X86_FEATURE_VMX)) {
 		struct vmx_pages *vmx_pages = data;
-		uint32_t control;
+		u32 control;
 
 		GUEST_ASSERT(prepare_for_vmx_operation(vmx_pages));
 		GUEST_ASSERT(load_vmcs(vmx_pages));
@@ -117,7 +117,7 @@ static void l1_guest_code(void *data)
 	GUEST_DONE();
 }
 
-static void report(int64_t val)
+static void report(s64 val)
 {
 	pr_info("IA32_TSC_ADJUST is %ld (%lld * TSC_ADJUST_VALUE + %lld).\n",
 		val, val / TSC_ADJUST_VALUE, val % TSC_ADJUST_VALUE);
@@ -125,7 +125,7 @@ static void report(int64_t val)
 
 int main(int argc, char *argv[])
 {
-	vm_vaddr_t nested_gva;
+	gva_t nested_gva;
 	struct kvm_vcpu *vcpu;
 
 	TEST_REQUIRE(kvm_cpu_has(X86_FEATURE_VMX) ||
diff --git a/tools/testing/selftests/kvm/x86/nested_tsc_scaling_test.c b/tools/testing/selftests/kvm/x86/nested_tsc_scaling_test.c
index 4260c9e4f489..190e93af20a1 100644
--- a/tools/testing/selftests/kvm/x86/nested_tsc_scaling_test.c
+++ b/tools/testing/selftests/kvm/x86/nested_tsc_scaling_test.c
@@ -19,7 +19,7 @@
 /* L2 is scaled up (from L1's perspective) by this factor */
 #define L2_SCALE_FACTOR 4ULL
 
-#define TSC_OFFSET_L2 ((uint64_t) -33125236320908)
+#define TSC_OFFSET_L2 ((u64)-33125236320908)
 #define TSC_MULTIPLIER_L2 (L2_SCALE_FACTOR << 48)
 
 #define L2_GUEST_STACK_SIZE 64
@@ -35,9 +35,9 @@ enum { USLEEP, UCHECK_L1, UCHECK_L2 };
  * measurements, a difference of 1% between the actual and the expected value
  * is tolerated.
  */
-static void compare_tsc_freq(uint64_t actual, uint64_t expected)
+static void compare_tsc_freq(u64 actual, u64 expected)
 {
-	uint64_t tolerance, thresh_low, thresh_high;
+	u64 tolerance, thresh_low, thresh_high;
 
 	tolerance = expected / 100;
 	thresh_low = expected - tolerance;
@@ -55,7 +55,7 @@ static void compare_tsc_freq(uint64_t actual, uint64_t expected)
 
 static void check_tsc_freq(int level)
 {
-	uint64_t tsc_start, tsc_end, tsc_freq;
+	u64 tsc_start, tsc_end, tsc_freq;
 
 	/*
 	 * Reading the TSC twice with about a second's difference should give
@@ -106,7 +106,7 @@ static void l1_svm_code(struct svm_test_data *svm)
 static void l1_vmx_code(struct vmx_pages *vmx_pages)
 {
 	unsigned long l2_guest_stack[L2_GUEST_STACK_SIZE];
-	uint32_t control;
+	u32 control;
 
 	/* check that L1's frequency looks alright before launching L2 */
 	check_tsc_freq(UCHECK_L1);
@@ -152,14 +152,14 @@ int main(int argc, char *argv[])
 {
 	struct kvm_vcpu *vcpu;
 	struct kvm_vm *vm;
-	vm_vaddr_t guest_gva = 0;
-
-	uint64_t tsc_start, tsc_end;
-	uint64_t tsc_khz;
-	uint64_t l1_scale_factor;
-	uint64_t l0_tsc_freq = 0;
-	uint64_t l1_tsc_freq = 0;
-	uint64_t l2_tsc_freq = 0;
+	gva_t guest_gva = 0;
+
+	u64 tsc_start, tsc_end;
+	u64 tsc_khz;
+	u64 l1_scale_factor;
+	u64 l0_tsc_freq = 0;
+	u64 l1_tsc_freq = 0;
+	u64 l2_tsc_freq = 0;
 
 	TEST_REQUIRE(kvm_cpu_has(X86_FEATURE_VMX) ||
 		     kvm_cpu_has(X86_FEATURE_SVM));
diff --git a/tools/testing/selftests/kvm/x86/nested_vmsave_vmload_test.c b/tools/testing/selftests/kvm/x86/nested_vmsave_vmload_test.c
index 71717118d692..85d3f4cc76f3 100644
--- a/tools/testing/selftests/kvm/x86/nested_vmsave_vmload_test.c
+++ b/tools/testing/selftests/kvm/x86/nested_vmsave_vmload_test.c
@@ -128,7 +128,7 @@ static void l1_guest_code(struct svm_test_data *svm)
 
 int main(int argc, char *argv[])
 {
-	vm_vaddr_t nested_gva = 0;
+	gva_t nested_gva = 0;
 	struct vmcb *test_vmcb[2];
 	struct kvm_vcpu *vcpu;
 	struct kvm_vm *vm;
diff --git a/tools/testing/selftests/kvm/x86/nx_huge_pages_test.c b/tools/testing/selftests/kvm/x86/nx_huge_pages_test.c
index c0d84827f736..70950067b989 100644
--- a/tools/testing/selftests/kvm/x86/nx_huge_pages_test.c
+++ b/tools/testing/selftests/kvm/x86/nx_huge_pages_test.c
@@ -32,7 +32,7 @@
 #define RETURN_OPCODE 0xC3
 
 /* Call the specified memory address. */
-static void guest_do_CALL(uint64_t target)
+static void guest_do_CALL(u64 target)
 {
 	((void (*)(void)) target)();
 }
@@ -46,14 +46,14 @@ static void guest_do_CALL(uint64_t target)
  */
 void guest_code(void)
 {
-	uint64_t hpage_1 = HPAGE_GVA;
-	uint64_t hpage_2 = hpage_1 + (PAGE_SIZE * 512);
-	uint64_t hpage_3 = hpage_2 + (PAGE_SIZE * 512);
+	u64 hpage_1 = HPAGE_GVA;
+	u64 hpage_2 = hpage_1 + (PAGE_SIZE * 512);
+	u64 hpage_3 = hpage_2 + (PAGE_SIZE * 512);
 
-	READ_ONCE(*(uint64_t *)hpage_1);
+	READ_ONCE(*(u64 *)hpage_1);
 	GUEST_SYNC(1);
 
-	READ_ONCE(*(uint64_t *)hpage_2);
+	READ_ONCE(*(u64 *)hpage_2);
 	GUEST_SYNC(2);
 
 	guest_do_CALL(hpage_1);
@@ -62,10 +62,10 @@ void guest_code(void)
 	guest_do_CALL(hpage_3);
 	GUEST_SYNC(4);
 
-	READ_ONCE(*(uint64_t *)hpage_1);
+	READ_ONCE(*(u64 *)hpage_1);
 	GUEST_SYNC(5);
 
-	READ_ONCE(*(uint64_t *)hpage_3);
+	READ_ONCE(*(u64 *)hpage_3);
 	GUEST_SYNC(6);
 }
 
@@ -107,7 +107,7 @@ void run_test(int reclaim_period_ms, bool disable_nx_huge_pages,
 {
 	struct kvm_vcpu *vcpu;
 	struct kvm_vm *vm;
-	uint64_t nr_bytes;
+	u64 nr_bytes;
 	void *hva;
 	int r;
 
diff --git a/tools/testing/selftests/kvm/x86/platform_info_test.c b/tools/testing/selftests/kvm/x86/platform_info_test.c
index 9cbf283ebc55..80bb07e6531c 100644
--- a/tools/testing/selftests/kvm/x86/platform_info_test.c
+++ b/tools/testing/selftests/kvm/x86/platform_info_test.c
@@ -23,8 +23,8 @@
 
 static void guest_code(void)
 {
-	uint64_t msr_platform_info;
-	uint8_t vector;
+	u64 msr_platform_info;
+	u8 vector;
 
 	GUEST_SYNC(true);
 	msr_platform_info = rdmsr(MSR_PLATFORM_INFO);
@@ -42,7 +42,7 @@ int main(int argc, char *argv[])
 {
 	struct kvm_vcpu *vcpu;
 	struct kvm_vm *vm;
-	uint64_t msr_platform_info;
+	u64 msr_platform_info;
 	struct ucall uc;
 
 	TEST_REQUIRE(kvm_has_cap(KVM_CAP_MSR_PLATFORM_INFO));
diff --git a/tools/testing/selftests/kvm/x86/pmu_counters_test.c b/tools/testing/selftests/kvm/x86/pmu_counters_test.c
index 3eaa216b96c0..dc6afac3aa91 100644
--- a/tools/testing/selftests/kvm/x86/pmu_counters_test.c
+++ b/tools/testing/selftests/kvm/x86/pmu_counters_test.c
@@ -30,9 +30,9 @@
 #define NUM_INSNS_RETIRED		(NUM_LOOPS * NUM_INSNS_PER_LOOP + NUM_EXTRA_INSNS)
 
 /* Track which architectural events are supported by hardware. */
-static uint32_t hardware_pmu_arch_events;
+static u32 hardware_pmu_arch_events;
 
-static uint8_t kvm_pmu_version;
+static u8 kvm_pmu_version;
 static bool kvm_has_perf_caps;
 
 #define X86_PMU_FEATURE_NULL						\
@@ -57,7 +57,7 @@ struct kvm_intel_pmu_event {
  * kvm_x86_pmu_feature use syntax that's only valid in function scope, and the
  * compiler often thinks the feature definitions aren't compile-time constants.
  */
-static struct kvm_intel_pmu_event intel_event_to_feature(uint8_t idx)
+static struct kvm_intel_pmu_event intel_event_to_feature(u8 idx)
 {
 	const struct kvm_intel_pmu_event __intel_event_to_feature[] = {
 		[INTEL_ARCH_CPU_CYCLES_INDEX]		 = { X86_PMU_FEATURE_CPU_CYCLES, X86_PMU_FEATURE_CPU_CYCLES_FIXED },
@@ -89,8 +89,8 @@ static struct kvm_intel_pmu_event intel_event_to_feature(uint8_t idx)
 
 static struct kvm_vm *pmu_vm_create_with_one_vcpu(struct kvm_vcpu **vcpu,
 						  void *guest_code,
-						  uint8_t pmu_version,
-						  uint64_t perf_capabilities)
+						  u8 pmu_version,
+						  u64 perf_capabilities)
 {
 	struct kvm_vm *vm;
 
@@ -132,7 +132,7 @@ static void run_vcpu(struct kvm_vcpu *vcpu)
 	} while (uc.cmd != UCALL_DONE);
 }
 
-static uint8_t guest_get_pmu_version(void)
+static u8 guest_get_pmu_version(void)
 {
 	/*
 	 * Return the effective PMU version, i.e. the minimum between what KVM
@@ -141,7 +141,7 @@ static uint8_t guest_get_pmu_version(void)
 	 * supported by KVM to verify KVM doesn't freak out and do something
 	 * bizarre with an architecturally valid, but unsupported, version.
 	 */
-	return min_t(uint8_t, kvm_pmu_version, this_cpu_property(X86_PROPERTY_PMU_VERSION));
+	return min_t(u8, kvm_pmu_version, this_cpu_property(X86_PROPERTY_PMU_VERSION));
 }
 
 /*
@@ -153,9 +153,9 @@ static uint8_t guest_get_pmu_version(void)
  * Sanity check that in all cases, the event doesn't count when it's disabled,
  * and that KVM correctly emulates the write of an arbitrary value.
  */
-static void guest_assert_event_count(uint8_t idx, uint32_t pmc, uint32_t pmc_msr)
+static void guest_assert_event_count(u8 idx, u32 pmc, u32 pmc_msr)
 {
-	uint64_t count;
+	u64 count;
 
 	count = _rdpmc(pmc);
 	if (!(hardware_pmu_arch_events & BIT(idx)))
@@ -236,7 +236,7 @@ do {										\
 			     FEP "xor %%eax, %%eax\n\t"				\
 			     FEP "xor %%edx, %%edx\n\t"				\
 			     "wrmsr\n\t"					\
-			     :: "a"((uint32_t)_value), "d"(_value >> 32),	\
+			     :: "a"((u32)_value), "d"(_value >> 32),	\
 				"c"(_msr), "D"(_msr), [m]"m"(kvm_pmu_version)	\
 	);									\
 } while (0)
@@ -255,8 +255,8 @@ do {										\
 	guest_assert_event_count(_idx, _pmc, _pmc_msr);				\
 } while (0)
 
-static void __guest_test_arch_event(uint8_t idx, uint32_t pmc, uint32_t pmc_msr,
-				    uint32_t ctrl_msr, uint64_t ctrl_msr_value)
+static void __guest_test_arch_event(u8 idx, u32 pmc, u32 pmc_msr,
+				    u32 ctrl_msr, u64 ctrl_msr_value)
 {
 	GUEST_TEST_EVENT(idx, pmc, pmc_msr, ctrl_msr, ctrl_msr_value, "");
 
@@ -264,14 +264,14 @@ static void __guest_test_arch_event(uint8_t idx, uint32_t pmc, uint32_t pmc_msr,
 		GUEST_TEST_EVENT(idx, pmc, pmc_msr, ctrl_msr, ctrl_msr_value, KVM_FEP);
 }
 
-static void guest_test_arch_event(uint8_t idx)
+static void guest_test_arch_event(u8 idx)
 {
-	uint32_t nr_gp_counters = this_cpu_property(X86_PROPERTY_PMU_NR_GP_COUNTERS);
-	uint32_t pmu_version = guest_get_pmu_version();
+	u32 nr_gp_counters = this_cpu_property(X86_PROPERTY_PMU_NR_GP_COUNTERS);
+	u32 pmu_version = guest_get_pmu_version();
 	/* PERF_GLOBAL_CTRL exists only for Architectural PMU Version 2+. */
 	bool guest_has_perf_global_ctrl = pmu_version >= 2;
 	struct kvm_x86_pmu_feature gp_event, fixed_event;
-	uint32_t base_pmc_msr;
+	u32 base_pmc_msr;
 	unsigned int i;
 
 	/* The host side shouldn't invoke this without a guest PMU. */
@@ -289,7 +289,7 @@ static void guest_test_arch_event(uint8_t idx)
 	GUEST_ASSERT(nr_gp_counters);
 
 	for (i = 0; i < nr_gp_counters; i++) {
-		uint64_t eventsel = ARCH_PERFMON_EVENTSEL_OS |
+		u64 eventsel = ARCH_PERFMON_EVENTSEL_OS |
 				    ARCH_PERFMON_EVENTSEL_ENABLE |
 				    intel_pmu_arch_events[idx];
 
@@ -320,7 +320,7 @@ static void guest_test_arch_event(uint8_t idx)
 
 static void guest_test_arch_events(void)
 {
-	uint8_t i;
+	u8 i;
 
 	for (i = 0; i < NR_INTEL_ARCH_EVENTS; i++)
 		guest_test_arch_event(i);
@@ -328,8 +328,8 @@ static void guest_test_arch_events(void)
 	GUEST_DONE();
 }
 
-static void test_arch_events(uint8_t pmu_version, uint64_t perf_capabilities,
-			     uint8_t length, uint32_t unavailable_mask)
+static void test_arch_events(u8 pmu_version, u64 perf_capabilities,
+			     u8 length, u32 unavailable_mask)
 {
 	struct kvm_vcpu *vcpu;
 	struct kvm_vm *vm;
@@ -373,11 +373,11 @@ __GUEST_ASSERT(expect_gp ? vector == GP_VECTOR : !vector,			\
 		       "Expected " #insn "(0x%x) to yield 0x%lx, got 0x%lx",	\
 		       msr, expected, val);
 
-static void guest_test_rdpmc(uint32_t rdpmc_idx, bool expect_success,
-			     uint64_t expected_val)
+static void guest_test_rdpmc(u32 rdpmc_idx, bool expect_success,
+			     u64 expected_val)
 {
-	uint8_t vector;
-	uint64_t val;
+	u8 vector;
+	u64 val;
 
 	vector = rdpmc_safe(rdpmc_idx, &val);
 	GUEST_ASSERT_PMC_MSR_ACCESS(RDPMC, rdpmc_idx, !expect_success, vector);
@@ -393,19 +393,19 @@ static void guest_test_rdpmc(uint32_t rdpmc_idx, bool expect_success,
 		GUEST_ASSERT_PMC_VALUE(RDPMC, rdpmc_idx, val, expected_val);
 }
 
-static void guest_rd_wr_counters(uint32_t base_msr, uint8_t nr_possible_counters,
-				 uint8_t nr_counters, uint32_t or_mask)
+static void guest_rd_wr_counters(u32 base_msr, u8 nr_possible_counters,
+				 u8 nr_counters, u32 or_mask)
 {
 	const bool pmu_has_fast_mode = !guest_get_pmu_version();
-	uint8_t i;
+	u8 i;
 
 	for (i = 0; i < nr_possible_counters; i++) {
 		/*
 		 * TODO: Test a value that validates full-width writes and the
 		 * width of the counters.
 		 */
-		const uint64_t test_val = 0xffff;
-		const uint32_t msr = base_msr + i;
+		const u64 test_val = 0xffff;
+		const u32 msr = base_msr + i;
 
 		/*
 		 * Fixed counters are supported if the counter is less than the
@@ -418,12 +418,12 @@ static void guest_rd_wr_counters(uint32_t base_msr, uint8_t nr_possible_counters
 		 * KVM drops writes to MSR_P6_PERFCTR[0|1] if the counters are
 		 * unsupported, i.e. doesn't #GP and reads back '0'.
 		 */
-		const uint64_t expected_val = expect_success ? test_val : 0;
+		const u64 expected_val = expect_success ? test_val : 0;
 		const bool expect_gp = !expect_success && msr != MSR_P6_PERFCTR0 &&
 				       msr != MSR_P6_PERFCTR1;
-		uint32_t rdpmc_idx;
-		uint8_t vector;
-		uint64_t val;
+		u32 rdpmc_idx;
+		u8 vector;
+		u64 val;
 
 		vector = wrmsr_safe(msr, test_val);
 		GUEST_ASSERT_PMC_MSR_ACCESS(WRMSR, msr, expect_gp, vector);
@@ -461,9 +461,9 @@ static void guest_rd_wr_counters(uint32_t base_msr, uint8_t nr_possible_counters
 
 static void guest_test_gp_counters(void)
 {
-	uint8_t pmu_version = guest_get_pmu_version();
-	uint8_t nr_gp_counters = 0;
-	uint32_t base_msr;
+	u8 pmu_version = guest_get_pmu_version();
+	u8 nr_gp_counters = 0;
+	u32 base_msr;
 
 	if (pmu_version)
 		nr_gp_counters = this_cpu_property(X86_PROPERTY_PMU_NR_GP_COUNTERS);
@@ -477,7 +477,7 @@ static void guest_test_gp_counters(void)
 	 * counters, of which there are none.
 	 */
 	if (pmu_version > 1) {
-		uint64_t global_ctrl = rdmsr(MSR_CORE_PERF_GLOBAL_CTRL);
+		u64 global_ctrl = rdmsr(MSR_CORE_PERF_GLOBAL_CTRL);
 
 		if (nr_gp_counters)
 			GUEST_ASSERT_EQ(global_ctrl, GENMASK_ULL(nr_gp_counters - 1, 0));
@@ -495,8 +495,8 @@ static void guest_test_gp_counters(void)
 	GUEST_DONE();
 }
 
-static void test_gp_counters(uint8_t pmu_version, uint64_t perf_capabilities,
-			     uint8_t nr_gp_counters)
+static void test_gp_counters(u8 pmu_version, u64 perf_capabilities,
+			     u8 nr_gp_counters)
 {
 	struct kvm_vcpu *vcpu;
 	struct kvm_vm *vm;
@@ -514,9 +514,9 @@ static void test_gp_counters(uint8_t pmu_version, uint64_t perf_capabilities,
 
 static void guest_test_fixed_counters(void)
 {
-	uint64_t supported_bitmask = 0;
-	uint8_t nr_fixed_counters = 0;
-	uint8_t i;
+	u64 supported_bitmask = 0;
+	u8 nr_fixed_counters = 0;
+	u8 i;
 
 	/* Fixed counters require Architectural vPMU Version 2+. */
 	if (guest_get_pmu_version() >= 2)
@@ -533,8 +533,8 @@ static void guest_test_fixed_counters(void)
 			     nr_fixed_counters, supported_bitmask);
 
 	for (i = 0; i < MAX_NR_FIXED_COUNTERS; i++) {
-		uint8_t vector;
-		uint64_t val;
+		u8 vector;
+		u64 val;
 
 		if (i >= nr_fixed_counters && !(supported_bitmask & BIT_ULL(i))) {
 			vector = wrmsr_safe(MSR_CORE_PERF_FIXED_CTR_CTRL,
@@ -561,9 +561,8 @@ static void guest_test_fixed_counters(void)
 	GUEST_DONE();
 }
 
-static void test_fixed_counters(uint8_t pmu_version, uint64_t perf_capabilities,
-				uint8_t nr_fixed_counters,
-				uint32_t supported_bitmask)
+static void test_fixed_counters(u8 pmu_version, u64 perf_capabilities,
+				u8 nr_fixed_counters, u32 supported_bitmask)
 {
 	struct kvm_vcpu *vcpu;
 	struct kvm_vm *vm;
@@ -583,14 +582,14 @@ static void test_fixed_counters(uint8_t pmu_version, uint64_t perf_capabilities,
 
 static void test_intel_counters(void)
 {
-	uint8_t nr_fixed_counters = kvm_cpu_property(X86_PROPERTY_PMU_NR_FIXED_COUNTERS);
-	uint8_t nr_gp_counters = kvm_cpu_property(X86_PROPERTY_PMU_NR_GP_COUNTERS);
-	uint8_t pmu_version = kvm_cpu_property(X86_PROPERTY_PMU_VERSION);
+	u8 nr_fixed_counters = kvm_cpu_property(X86_PROPERTY_PMU_NR_FIXED_COUNTERS);
+	u8 nr_gp_counters = kvm_cpu_property(X86_PROPERTY_PMU_NR_GP_COUNTERS);
+	u8 pmu_version = kvm_cpu_property(X86_PROPERTY_PMU_VERSION);
 	unsigned int i;
-	uint8_t v, j;
-	uint32_t k;
+	u8 v, j;
+	u32 k;
 
-	const uint64_t perf_caps[] = {
+	const u64 perf_caps[] = {
 		0,
 		PMU_CAP_FW_WRITES,
 	};
@@ -602,7 +601,7 @@ static void test_intel_counters(void)
 	 * as alternating bit sequencues, e.g. to detect if KVM is checking the
 	 * wrong bit(s).
 	 */
-	const uint32_t unavailable_masks[] = {
+	const u32 unavailable_masks[] = {
 		0x0,
 		0xffffffffu,
 		0xaaaaaaaau,
@@ -620,7 +619,7 @@ static void test_intel_counters(void)
 	 * Intel, i.e. is the last version that is guaranteed to be backwards
 	 * compatible with KVM's existing behavior.
 	 */
-	uint8_t max_pmu_version = max_t(typeof(pmu_version), pmu_version, 5);
+	u8 max_pmu_version = max_t(typeof(pmu_version), pmu_version, 5);
 
 	/*
 	 * Detect the existence of events that aren't supported by selftests.
diff --git a/tools/testing/selftests/kvm/x86/pmu_event_filter_test.c b/tools/testing/selftests/kvm/x86/pmu_event_filter_test.c
index 93b61c077991..c1232344fda8 100644
--- a/tools/testing/selftests/kvm/x86/pmu_event_filter_test.c
+++ b/tools/testing/selftests/kvm/x86/pmu_event_filter_test.c
@@ -53,11 +53,11 @@ static const struct __kvm_pmu_event_filter base_event_filter = {
 };
 
 struct {
-	uint64_t loads;
-	uint64_t stores;
-	uint64_t loads_stores;
-	uint64_t branches_retired;
-	uint64_t instructions_retired;
+	u64 loads;
+	u64 stores;
+	u64 loads_stores;
+	u64 branches_retired;
+	u64 instructions_retired;
 } pmc_results;
 
 /*
@@ -75,9 +75,9 @@ static void guest_gp_handler(struct ex_regs *regs)
  *
  * Return on success. GUEST_SYNC(0) on error.
  */
-static void check_msr(uint32_t msr, uint64_t bits_to_flip)
+static void check_msr(u32 msr, u64 bits_to_flip)
 {
-	uint64_t v = rdmsr(msr) ^ bits_to_flip;
+	u64 v = rdmsr(msr) ^ bits_to_flip;
 
 	wrmsr(msr, v);
 	if (rdmsr(msr) != v)
@@ -89,10 +89,10 @@ static void check_msr(uint32_t msr, uint64_t bits_to_flip)
 		GUEST_SYNC(-EIO);
 }
 
-static void run_and_measure_loop(uint32_t msr_base)
+static void run_and_measure_loop(u32 msr_base)
 {
-	const uint64_t branches_retired = rdmsr(msr_base + 0);
-	const uint64_t insn_retired = rdmsr(msr_base + 1);
+	const u64 branches_retired = rdmsr(msr_base + 0);
+	const u64 insn_retired = rdmsr(msr_base + 1);
 
 	__asm__ __volatile__("loop ." : "+c"((int){NUM_BRANCHES}));
 
@@ -147,7 +147,7 @@ static void amd_guest_code(void)
  * Run the VM to the next GUEST_SYNC(value), and return the value passed
  * to the sync. Any other exit from the guest is fatal.
  */
-static uint64_t run_vcpu_to_sync(struct kvm_vcpu *vcpu)
+static u64 run_vcpu_to_sync(struct kvm_vcpu *vcpu)
 {
 	struct ucall uc;
 
@@ -161,7 +161,7 @@ static uint64_t run_vcpu_to_sync(struct kvm_vcpu *vcpu)
 
 static void run_vcpu_and_sync_pmc_results(struct kvm_vcpu *vcpu)
 {
-	uint64_t r;
+	u64 r;
 
 	memset(&pmc_results, 0, sizeof(pmc_results));
 	sync_global_to_guest(vcpu->vm, pmc_results);
@@ -182,7 +182,7 @@ static void run_vcpu_and_sync_pmc_results(struct kvm_vcpu *vcpu)
  */
 static bool sanity_check_pmu(struct kvm_vcpu *vcpu)
 {
-	uint64_t r;
+	u64 r;
 
 	vm_install_exception_handler(vcpu->vm, GP_VECTOR, guest_gp_handler);
 	r = run_vcpu_to_sync(vcpu);
@@ -195,7 +195,7 @@ static bool sanity_check_pmu(struct kvm_vcpu *vcpu)
  * Remove the first occurrence of 'event' (if any) from the filter's
  * event list.
  */
-static void remove_event(struct __kvm_pmu_event_filter *f, uint64_t event)
+static void remove_event(struct __kvm_pmu_event_filter *f, u64 event)
 {
 	bool found = false;
 	int i;
@@ -212,8 +212,8 @@ static void remove_event(struct __kvm_pmu_event_filter *f, uint64_t event)
 
 #define ASSERT_PMC_COUNTING_INSTRUCTIONS()						\
 do {											\
-	uint64_t br = pmc_results.branches_retired;					\
-	uint64_t ir = pmc_results.instructions_retired;					\
+	u64 br = pmc_results.branches_retired;					\
+	u64 ir = pmc_results.instructions_retired;					\
 	bool br_matched = this_pmu_has_errata(BRANCHES_RETIRED_OVERCOUNT) ?		\
 			  br >= NUM_BRANCHES : br == NUM_BRANCHES;			\
 											\
@@ -228,8 +228,8 @@ do {											\
 
 #define ASSERT_PMC_NOT_COUNTING_INSTRUCTIONS()						\
 do {											\
-	uint64_t br = pmc_results.branches_retired;					\
-	uint64_t ir = pmc_results.instructions_retired;					\
+	u64 br = pmc_results.branches_retired;					\
+	u64 ir = pmc_results.instructions_retired;					\
 											\
 	TEST_ASSERT(!br, "%s: Branch instructions retired = %lu (expected 0)",		\
 		    __func__, br);							\
@@ -378,7 +378,7 @@ static bool use_amd_pmu(void)
 
 static bool supports_event_mem_inst_retired(void)
 {
-	uint32_t eax, ebx, ecx, edx;
+	u32 eax, ebx, ecx, edx;
 
 	cpuid(1, &eax, &ebx, &ecx, &edx);
 	if (x86_family(eax) == 0x6) {
@@ -415,15 +415,15 @@ static bool supports_event_mem_inst_retired(void)
 #define EXCLUDE_MASKED_ENTRY(event_select, mask, match) \
 	KVM_PMU_ENCODE_MASKED_ENTRY(event_select, mask, match, true)
 
-static void masked_events_guest_test(uint32_t msr_base)
+static void masked_events_guest_test(u32 msr_base)
 {
 	/*
 	 * The actual value of the counters don't determine the outcome of
 	 * the test.  Only that they are zero or non-zero.
 	 */
-	const uint64_t loads = rdmsr(msr_base + 0);
-	const uint64_t stores = rdmsr(msr_base + 1);
-	const uint64_t loads_stores = rdmsr(msr_base + 2);
+	const u64 loads = rdmsr(msr_base + 0);
+	const u64 stores = rdmsr(msr_base + 1);
+	const u64 loads_stores = rdmsr(msr_base + 2);
 	int val;
 
 
@@ -476,7 +476,7 @@ static void amd_masked_events_guest_code(void)
 }
 
 static void run_masked_events_test(struct kvm_vcpu *vcpu,
-				   const uint64_t masked_events[],
+				   const u64 masked_events[],
 				   const int nmasked_events)
 {
 	struct __kvm_pmu_event_filter f = {
@@ -485,7 +485,7 @@ static void run_masked_events_test(struct kvm_vcpu *vcpu,
 		.flags = KVM_PMU_EVENT_FLAG_MASKED_EVENTS,
 	};
 
-	memcpy(f.events, masked_events, sizeof(uint64_t) * nmasked_events);
+	memcpy(f.events, masked_events, sizeof(u64) * nmasked_events);
 	test_with_filter(vcpu, &f);
 }
 
@@ -494,12 +494,12 @@ static void run_masked_events_test(struct kvm_vcpu *vcpu,
 #define ALLOW_LOADS_STORES	BIT(2)
 
 struct masked_events_test {
-	uint64_t intel_events[MAX_TEST_EVENTS];
-	uint64_t intel_event_end;
-	uint64_t amd_events[MAX_TEST_EVENTS];
-	uint64_t amd_event_end;
+	u64 intel_events[MAX_TEST_EVENTS];
+	u64 intel_event_end;
+	u64 amd_events[MAX_TEST_EVENTS];
+	u64 amd_event_end;
 	const char *msg;
-	uint32_t flags;
+	u32 flags;
 };
 
 /*
@@ -582,9 +582,9 @@ const struct masked_events_test test_cases[] = {
 };
 
 static int append_test_events(const struct masked_events_test *test,
-			      uint64_t *events, int nevents)
+			      u64 *events, int nevents)
 {
-	const uint64_t *evts;
+	const u64 *evts;
 	int i;
 
 	evts = use_intel_pmu() ? test->intel_events : test->amd_events;
@@ -603,7 +603,7 @@ static bool bool_eq(bool a, bool b)
 	return a == b;
 }
 
-static void run_masked_events_tests(struct kvm_vcpu *vcpu, uint64_t *events,
+static void run_masked_events_tests(struct kvm_vcpu *vcpu, u64 *events,
 				    int nevents)
 {
 	int ntests = ARRAY_SIZE(test_cases);
@@ -630,7 +630,7 @@ static void run_masked_events_tests(struct kvm_vcpu *vcpu, uint64_t *events,
 	}
 }
 
-static void add_dummy_events(uint64_t *events, int nevents)
+static void add_dummy_events(u64 *events, int nevents)
 {
 	int i;
 
@@ -650,7 +650,7 @@ static void add_dummy_events(uint64_t *events, int nevents)
 static void test_masked_events(struct kvm_vcpu *vcpu)
 {
 	int nevents = KVM_PMU_EVENT_FILTER_MAX_EVENTS - MAX_TEST_EVENTS;
-	uint64_t events[KVM_PMU_EVENT_FILTER_MAX_EVENTS];
+	u64 events[KVM_PMU_EVENT_FILTER_MAX_EVENTS];
 
 	/* Run the test cases against a sparse PMU event filter. */
 	run_masked_events_tests(vcpu, events, 0);
@@ -668,8 +668,8 @@ static int set_pmu_event_filter(struct kvm_vcpu *vcpu,
 	return __vm_ioctl(vcpu->vm, KVM_SET_PMU_EVENT_FILTER, f);
 }
 
-static int set_pmu_single_event_filter(struct kvm_vcpu *vcpu, uint64_t event,
-				       uint32_t flags, uint32_t action)
+static int set_pmu_single_event_filter(struct kvm_vcpu *vcpu, u64 event,
+				       u32 flags, u32 action)
 {
 	struct __kvm_pmu_event_filter f = {
 		.nevents = 1,
@@ -685,9 +685,9 @@ static int set_pmu_single_event_filter(struct kvm_vcpu *vcpu, uint64_t event,
 
 static void test_filter_ioctl(struct kvm_vcpu *vcpu)
 {
-	uint8_t nr_fixed_counters = kvm_cpu_property(X86_PROPERTY_PMU_NR_FIXED_COUNTERS);
+	u8 nr_fixed_counters = kvm_cpu_property(X86_PROPERTY_PMU_NR_FIXED_COUNTERS);
 	struct __kvm_pmu_event_filter f;
-	uint64_t e = ~0ul;
+	u64 e = ~0ul;
 	int r;
 
 	/*
@@ -729,7 +729,7 @@ static void test_filter_ioctl(struct kvm_vcpu *vcpu)
 	TEST_ASSERT(!r, "Masking non-existent fixed counters should be allowed");
 }
 
-static void intel_run_fixed_counter_guest_code(uint8_t idx)
+static void intel_run_fixed_counter_guest_code(u8 idx)
 {
 	for (;;) {
 		wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, 0);
@@ -745,8 +745,8 @@ static void intel_run_fixed_counter_guest_code(uint8_t idx)
 	}
 }
 
-static uint64_t test_with_fixed_counter_filter(struct kvm_vcpu *vcpu,
-					       uint32_t action, uint32_t bitmap)
+static u64 test_with_fixed_counter_filter(struct kvm_vcpu *vcpu,
+					  u32 action, u32 bitmap)
 {
 	struct __kvm_pmu_event_filter f = {
 		.action = action,
@@ -757,9 +757,9 @@ static uint64_t test_with_fixed_counter_filter(struct kvm_vcpu *vcpu,
 	return run_vcpu_to_sync(vcpu);
 }
 
-static uint64_t test_set_gp_and_fixed_event_filter(struct kvm_vcpu *vcpu,
-						   uint32_t action,
-						   uint32_t bitmap)
+static u64 test_set_gp_and_fixed_event_filter(struct kvm_vcpu *vcpu,
+					      u32 action,
+					      u32 bitmap)
 {
 	struct __kvm_pmu_event_filter f = base_event_filter;
 
@@ -770,12 +770,12 @@ static uint64_t test_set_gp_and_fixed_event_filter(struct kvm_vcpu *vcpu,
 	return run_vcpu_to_sync(vcpu);
 }
 
-static void __test_fixed_counter_bitmap(struct kvm_vcpu *vcpu, uint8_t idx,
-					uint8_t nr_fixed_counters)
+static void __test_fixed_counter_bitmap(struct kvm_vcpu *vcpu, u8 idx,
+					u8 nr_fixed_counters)
 {
 	unsigned int i;
-	uint32_t bitmap;
-	uint64_t count;
+	u32 bitmap;
+	u64 count;
 
 	TEST_ASSERT(nr_fixed_counters < sizeof(bitmap) * 8,
 		    "Invalid nr_fixed_counters");
@@ -815,10 +815,10 @@ static void __test_fixed_counter_bitmap(struct kvm_vcpu *vcpu, uint8_t idx,
 
 static void test_fixed_counter_bitmap(void)
 {
-	uint8_t nr_fixed_counters = kvm_cpu_property(X86_PROPERTY_PMU_NR_FIXED_COUNTERS);
+	u8 nr_fixed_counters = kvm_cpu_property(X86_PROPERTY_PMU_NR_FIXED_COUNTERS);
 	struct kvm_vm *vm;
 	struct kvm_vcpu *vcpu;
-	uint8_t idx;
+	u8 idx;
 
 	/*
 	 * Check that pmu_event_filter works as expected when it's applied to
diff --git a/tools/testing/selftests/kvm/x86/private_mem_conversions_test.c b/tools/testing/selftests/kvm/x86/private_mem_conversions_test.c
index 1969f4ab9b28..1d2f5d4fd45d 100644
--- a/tools/testing/selftests/kvm/x86/private_mem_conversions_test.c
+++ b/tools/testing/selftests/kvm/x86/private_mem_conversions_test.c
@@ -23,13 +23,13 @@
 #include <processor.h>
 
 #define BASE_DATA_SLOT		10
-#define BASE_DATA_GPA		((uint64_t)(1ull << 32))
-#define PER_CPU_DATA_SIZE	((uint64_t)(SZ_2M + PAGE_SIZE))
+#define BASE_DATA_GPA		((u64)(1ull << 32))
+#define PER_CPU_DATA_SIZE	((u64)(SZ_2M + PAGE_SIZE))
 
 /* Horrific macro so that the line info is captured accurately :-( */
 #define memcmp_g(gpa, pattern,  size)								\
 do {												\
-	uint8_t *mem = (uint8_t *)gpa;								\
+	u8 *mem = (u8 *)gpa;									\
 	size_t i;										\
 												\
 	for (i = 0; i < size; i++)								\
@@ -38,7 +38,7 @@ do {												\
 			       pattern, i, gpa + i, mem[i]);					\
 } while (0)
 
-static void memcmp_h(uint8_t *mem, uint64_t gpa, uint8_t pattern, size_t size)
+static void memcmp_h(u8 *mem, gpa_t gpa, u8 pattern, size_t size)
 {
 	size_t i;
 
@@ -70,13 +70,13 @@ enum ucall_syncs {
 	SYNC_PRIVATE,
 };
 
-static void guest_sync_shared(uint64_t gpa, uint64_t size,
-			      uint8_t current_pattern, uint8_t new_pattern)
+static void guest_sync_shared(gpa_t gpa, u64 size,
+			      u8 current_pattern, u8 new_pattern)
 {
 	GUEST_SYNC5(SYNC_SHARED, gpa, size, current_pattern, new_pattern);
 }
 
-static void guest_sync_private(uint64_t gpa, uint64_t size, uint8_t pattern)
+static void guest_sync_private(gpa_t gpa, u64 size, u8 pattern)
 {
 	GUEST_SYNC4(SYNC_PRIVATE, gpa, size, pattern);
 }
@@ -86,10 +86,10 @@ static void guest_sync_private(uint64_t gpa, uint64_t size, uint8_t pattern)
 #define MAP_GPA_SHARED		BIT(1)
 #define MAP_GPA_DO_FALLOCATE	BIT(2)
 
-static void guest_map_mem(uint64_t gpa, uint64_t size, bool map_shared,
+static void guest_map_mem(gpa_t gpa, u64 size, bool map_shared,
 			  bool do_fallocate)
 {
-	uint64_t flags = MAP_GPA_SET_ATTRIBUTES;
+	u64 flags = MAP_GPA_SET_ATTRIBUTES;
 
 	if (map_shared)
 		flags |= MAP_GPA_SHARED;
@@ -98,19 +98,19 @@ static void guest_map_mem(uint64_t gpa, uint64_t size, bool map_shared,
 	kvm_hypercall_map_gpa_range(gpa, size, flags);
 }
 
-static void guest_map_shared(uint64_t gpa, uint64_t size, bool do_fallocate)
+static void guest_map_shared(gpa_t gpa, u64 size, bool do_fallocate)
 {
 	guest_map_mem(gpa, size, true, do_fallocate);
 }
 
-static void guest_map_private(uint64_t gpa, uint64_t size, bool do_fallocate)
+static void guest_map_private(gpa_t gpa, u64 size, bool do_fallocate)
 {
 	guest_map_mem(gpa, size, false, do_fallocate);
 }
 
 struct {
-	uint64_t offset;
-	uint64_t size;
+	u64 offset;
+	u64 size;
 } static const test_ranges[] = {
 	GUEST_STAGE(0, PAGE_SIZE),
 	GUEST_STAGE(0, SZ_2M),
@@ -119,11 +119,11 @@ struct {
 	GUEST_STAGE(SZ_2M, PAGE_SIZE),
 };
 
-static void guest_test_explicit_conversion(uint64_t base_gpa, bool do_fallocate)
+static void guest_test_explicit_conversion(u64 base_gpa, bool do_fallocate)
 {
-	const uint8_t def_p = 0xaa;
-	const uint8_t init_p = 0xcc;
-	uint64_t j;
+	const u8 def_p = 0xaa;
+	const u8 init_p = 0xcc;
+	u64 j;
 	int i;
 
 	/* Memory should be shared by default. */
@@ -134,12 +134,12 @@ static void guest_test_explicit_conversion(uint64_t base_gpa, bool do_fallocate)
 	memcmp_g(base_gpa, init_p, PER_CPU_DATA_SIZE);
 
 	for (i = 0; i < ARRAY_SIZE(test_ranges); i++) {
-		uint64_t gpa = base_gpa + test_ranges[i].offset;
-		uint64_t size = test_ranges[i].size;
-		uint8_t p1 = 0x11;
-		uint8_t p2 = 0x22;
-		uint8_t p3 = 0x33;
-		uint8_t p4 = 0x44;
+		gpa_t gpa = base_gpa + test_ranges[i].offset;
+		u64 size = test_ranges[i].size;
+		u8 p1 = 0x11;
+		u8 p2 = 0x22;
+		u8 p3 = 0x33;
+		u8 p4 = 0x44;
 
 		/*
 		 * Set the test region to pattern one to differentiate it from
@@ -214,10 +214,10 @@ static void guest_test_explicit_conversion(uint64_t base_gpa, bool do_fallocate)
 	}
 }
 
-static void guest_punch_hole(uint64_t gpa, uint64_t size)
+static void guest_punch_hole(gpa_t gpa, u64 size)
 {
 	/* "Mapping" memory shared via fallocate() is done via PUNCH_HOLE. */
-	uint64_t flags = MAP_GPA_SHARED | MAP_GPA_DO_FALLOCATE;
+	u64 flags = MAP_GPA_SHARED | MAP_GPA_DO_FALLOCATE;
 
 	kvm_hypercall_map_gpa_range(gpa, size, flags);
 }
@@ -227,9 +227,9 @@ static void guest_punch_hole(uint64_t gpa, uint64_t size)
  * proper conversion.  Freeing (PUNCH_HOLE) should zap SPTEs, and reallocating
  * (subsequent fault) should zero memory.
  */
-static void guest_test_punch_hole(uint64_t base_gpa, bool precise)
+static void guest_test_punch_hole(u64 base_gpa, bool precise)
 {
-	const uint8_t init_p = 0xcc;
+	const u8 init_p = 0xcc;
 	int i;
 
 	/*
@@ -239,8 +239,8 @@ static void guest_test_punch_hole(uint64_t base_gpa, bool precise)
 	guest_map_private(base_gpa, PER_CPU_DATA_SIZE, false);
 
 	for (i = 0; i < ARRAY_SIZE(test_ranges); i++) {
-		uint64_t gpa = base_gpa + test_ranges[i].offset;
-		uint64_t size = test_ranges[i].size;
+		gpa_t gpa = base_gpa + test_ranges[i].offset;
+		u64 size = test_ranges[i].size;
 
 		/*
 		 * Free all memory before each iteration, even for the !precise
@@ -268,7 +268,7 @@ static void guest_test_punch_hole(uint64_t base_gpa, bool precise)
 	}
 }
 
-static void guest_code(uint64_t base_gpa)
+static void guest_code(u64 base_gpa)
 {
 	/*
 	 * Run the conversion test twice, with and without doing fallocate() on
@@ -289,8 +289,8 @@ static void guest_code(uint64_t base_gpa)
 static void handle_exit_hypercall(struct kvm_vcpu *vcpu)
 {
 	struct kvm_run *run = vcpu->run;
-	uint64_t gpa = run->hypercall.args[0];
-	uint64_t size = run->hypercall.args[1] * PAGE_SIZE;
+	gpa_t gpa = run->hypercall.args[0];
+	u64 size = run->hypercall.args[1] * PAGE_SIZE;
 	bool set_attributes = run->hypercall.args[2] & MAP_GPA_SET_ATTRIBUTES;
 	bool map_shared = run->hypercall.args[2] & MAP_GPA_SHARED;
 	bool do_fallocate = run->hypercall.args[2] & MAP_GPA_DO_FALLOCATE;
@@ -337,7 +337,7 @@ static void *__test_mem_conversions(void *__vcpu)
 		case UCALL_ABORT:
 			REPORT_GUEST_ASSERT(uc);
 		case UCALL_SYNC: {
-			uint64_t gpa  = uc.args[1];
+			gpa_t gpa  = uc.args[1];
 			size_t size = uc.args[2];
 			size_t i;
 
@@ -347,7 +347,7 @@ static void *__test_mem_conversions(void *__vcpu)
 
 			for (i = 0; i < size; i += vm->page_size) {
 				size_t nr_bytes = min_t(size_t, vm->page_size, size - i);
-				uint8_t *hva = addr_gpa2hva(vm, gpa + i);
+				u8 *hva = addr_gpa2hva(vm, gpa + i);
 
 				/* In all cases, the host should observe the shared data. */
 				memcmp_h(hva, gpa + i, uc.args[3], nr_bytes);
@@ -366,8 +366,8 @@ static void *__test_mem_conversions(void *__vcpu)
 	}
 }
 
-static void test_mem_conversions(enum vm_mem_backing_src_type src_type, uint32_t nr_vcpus,
-				 uint32_t nr_memslots)
+static void test_mem_conversions(enum vm_mem_backing_src_type src_type, u32 nr_vcpus,
+				 u32 nr_memslots)
 {
 	/*
 	 * Allocate enough memory so that each vCPU's chunk of memory can be
@@ -402,7 +402,7 @@ static void test_mem_conversions(enum vm_mem_backing_src_type src_type, uint32_t
 			   KVM_MEM_GUEST_MEMFD, memfd, slot_size * i);
 
 	for (i = 0; i < nr_vcpus; i++) {
-		uint64_t gpa =  BASE_DATA_GPA + i * per_cpu_size;
+		gpa_t gpa =  BASE_DATA_GPA + i * per_cpu_size;
 
 		vcpu_args_set(vcpus[i], 1, gpa);
 
@@ -450,8 +450,8 @@ static void usage(const char *cmd)
 int main(int argc, char *argv[])
 {
 	enum vm_mem_backing_src_type src_type = DEFAULT_VM_MEM_SRC;
-	uint32_t nr_memslots = 1;
-	uint32_t nr_vcpus = 1;
+	u32 nr_memslots = 1;
+	u32 nr_vcpus = 1;
 	int opt;
 
 	TEST_REQUIRE(kvm_check_cap(KVM_CAP_VM_TYPES) & BIT(KVM_X86_SW_PROTECTED_VM));
diff --git a/tools/testing/selftests/kvm/x86/private_mem_kvm_exits_test.c b/tools/testing/selftests/kvm/x86/private_mem_kvm_exits_test.c
index 13e72fcec8dd..10db9fe6d906 100644
--- a/tools/testing/selftests/kvm/x86/private_mem_kvm_exits_test.c
+++ b/tools/testing/selftests/kvm/x86/private_mem_kvm_exits_test.c
@@ -17,17 +17,17 @@
 #define EXITS_TEST_SIZE (EXITS_TEST_NPAGES * PAGE_SIZE)
 #define EXITS_TEST_SLOT 10
 
-static uint64_t guest_repeatedly_read(void)
+static u64 guest_repeatedly_read(void)
 {
-	volatile uint64_t value;
+	volatile u64 value;
 
 	while (true)
-		value = *((uint64_t *) EXITS_TEST_GVA);
+		value = *((u64 *)EXITS_TEST_GVA);
 
 	return value;
 }
 
-static uint32_t run_vcpu_get_exit_reason(struct kvm_vcpu *vcpu)
+static u32 run_vcpu_get_exit_reason(struct kvm_vcpu *vcpu)
 {
 	int r;
 
@@ -50,7 +50,7 @@ static void test_private_access_memslot_deleted(void)
 	struct kvm_vcpu *vcpu;
 	pthread_t vm_thread;
 	void *thread_return;
-	uint32_t exit_reason;
+	u32 exit_reason;
 
 	vm = vm_create_shape_with_one_vcpu(protected_vm_shape, &vcpu,
 					   guest_repeatedly_read);
@@ -72,7 +72,7 @@ static void test_private_access_memslot_deleted(void)
 	vm_mem_region_delete(vm, EXITS_TEST_SLOT);
 
 	pthread_join(vm_thread, &thread_return);
-	exit_reason = (uint32_t)(uint64_t)thread_return;
+	exit_reason = (u32)(u64)thread_return;
 
 	TEST_ASSERT_EQ(exit_reason, KVM_EXIT_MEMORY_FAULT);
 	TEST_ASSERT_EQ(vcpu->run->memory_fault.flags, KVM_MEMORY_EXIT_FLAG_PRIVATE);
@@ -86,7 +86,7 @@ static void test_private_access_memslot_not_private(void)
 {
 	struct kvm_vm *vm;
 	struct kvm_vcpu *vcpu;
-	uint32_t exit_reason;
+	u32 exit_reason;
 
 	vm = vm_create_shape_with_one_vcpu(protected_vm_shape, &vcpu,
 					   guest_repeatedly_read);
diff --git a/tools/testing/selftests/kvm/x86/set_boot_cpu_id.c b/tools/testing/selftests/kvm/x86/set_boot_cpu_id.c
index 49913784bc82..8e3898646c69 100644
--- a/tools/testing/selftests/kvm/x86/set_boot_cpu_id.c
+++ b/tools/testing/selftests/kvm/x86/set_boot_cpu_id.c
@@ -86,11 +86,11 @@ static void run_vcpu(struct kvm_vcpu *vcpu)
 	}
 }
 
-static struct kvm_vm *create_vm(uint32_t nr_vcpus, uint32_t bsp_vcpu_id,
+static struct kvm_vm *create_vm(u32 nr_vcpus, u32 bsp_vcpu_id,
 				struct kvm_vcpu *vcpus[])
 {
 	struct kvm_vm *vm;
-	uint32_t i;
+	u32 i;
 
 	vm = vm_create(nr_vcpus);
 
@@ -104,7 +104,7 @@ static struct kvm_vm *create_vm(uint32_t nr_vcpus, uint32_t bsp_vcpu_id,
 	return vm;
 }
 
-static void run_vm_bsp(uint32_t bsp_vcpu_id)
+static void run_vm_bsp(u32 bsp_vcpu_id)
 {
 	struct kvm_vcpu *vcpus[2];
 	struct kvm_vm *vm;
diff --git a/tools/testing/selftests/kvm/x86/set_sregs_test.c b/tools/testing/selftests/kvm/x86/set_sregs_test.c
index f4095a3d1278..8e654cc9ab16 100644
--- a/tools/testing/selftests/kvm/x86/set_sregs_test.c
+++ b/tools/testing/selftests/kvm/x86/set_sregs_test.c
@@ -46,9 +46,9 @@ do {										\
 				X86_CR4_MCE | X86_CR4_PGE | X86_CR4_PCE |	\
 				X86_CR4_OSFXSR | X86_CR4_OSXMMEXCPT)
 
-static uint64_t calc_supported_cr4_feature_bits(void)
+static u64 calc_supported_cr4_feature_bits(void)
 {
-	uint64_t cr4 = KVM_ALWAYS_ALLOWED_CR4;
+	u64 cr4 = KVM_ALWAYS_ALLOWED_CR4;
 
 	if (kvm_cpu_has(X86_FEATURE_UMIP))
 		cr4 |= X86_CR4_UMIP;
@@ -74,7 +74,7 @@ static uint64_t calc_supported_cr4_feature_bits(void)
 	return cr4;
 }
 
-static void test_cr_bits(struct kvm_vcpu *vcpu, uint64_t cr4)
+static void test_cr_bits(struct kvm_vcpu *vcpu, u64 cr4)
 {
 	struct kvm_sregs sregs;
 	int rc, i;
diff --git a/tools/testing/selftests/kvm/x86/sev_init2_tests.c b/tools/testing/selftests/kvm/x86/sev_init2_tests.c
index b238615196ad..8eeba2327c7c 100644
--- a/tools/testing/selftests/kvm/x86/sev_init2_tests.c
+++ b/tools/testing/selftests/kvm/x86/sev_init2_tests.c
@@ -34,7 +34,7 @@ static int __sev_ioctl(int vm_fd, int cmd_id, void *data)
 {
 	struct kvm_sev_cmd cmd = {
 		.id = cmd_id,
-		.data = (uint64_t)data,
+		.data = (u64)data,
 		.sev_fd = open_sev_dev_path_or_exit(),
 	};
 	int ret;
@@ -94,7 +94,7 @@ void test_vm_types(void)
 				   "VM type is KVM_X86_SW_PROTECTED_VM");
 }
 
-void test_flags(uint32_t vm_type)
+void test_flags(u32 vm_type)
 {
 	int i;
 
@@ -104,7 +104,7 @@ void test_flags(uint32_t vm_type)
 			"invalid flag");
 }
 
-void test_features(uint32_t vm_type, uint64_t supported_features)
+void test_features(u32 vm_type, u64 supported_features)
 {
 	int i;
 
diff --git a/tools/testing/selftests/kvm/x86/sev_smoke_test.c b/tools/testing/selftests/kvm/x86/sev_smoke_test.c
index 8bd37a476f15..1a49ee391586 100644
--- a/tools/testing/selftests/kvm/x86/sev_smoke_test.c
+++ b/tools/testing/selftests/kvm/x86/sev_smoke_test.c
@@ -13,9 +13,9 @@
 #include "linux/psp-sev.h"
 #include "sev.h"
 
-static void guest_sev_test_msr(uint32_t msr)
+static void guest_sev_test_msr(u32 msr)
 {
-	uint64_t val = rdmsr(msr);
+	u64 val = rdmsr(msr);
 
 	wrmsr(msr, val);
 	GUEST_ASSERT(val == rdmsr(msr));
@@ -23,7 +23,7 @@ static void guest_sev_test_msr(uint32_t msr)
 
 #define guest_sev_test_reg(reg)			\
 do {						\
-	uint64_t val = get_##reg();		\
+	u64 val = get_##reg();			\
 						\
 	set_##reg(val);				\
 	GUEST_ASSERT(val == get_##reg());	\
@@ -42,7 +42,7 @@ static void guest_sev_test_regs(void)
 
 static void guest_snp_code(void)
 {
-	uint64_t sev_msr = rdmsr(MSR_AMD64_SEV);
+	u64 sev_msr = rdmsr(MSR_AMD64_SEV);
 
 	GUEST_ASSERT(sev_msr & MSR_AMD64_SEV_ENABLED);
 	GUEST_ASSERT(sev_msr & MSR_AMD64_SEV_ES_ENABLED);
@@ -104,19 +104,19 @@ static void compare_xsave(u8 *from_host, u8 *from_guest)
 		abort();
 }
 
-static void test_sync_vmsa(uint32_t type, uint64_t policy)
+static void test_sync_vmsa(u32 type, u64 policy)
 {
 	struct kvm_vcpu *vcpu;
 	struct kvm_vm *vm;
-	vm_vaddr_t gva;
+	gva_t gva;
 	void *hva;
 
 	double x87val = M_PI;
 	struct kvm_xsave __attribute__((aligned(64))) xsave = { 0 };
 
 	vm = vm_sev_create_with_one_vcpu(type, guest_code_xsave, &vcpu);
-	gva = vm_vaddr_alloc_shared(vm, PAGE_SIZE, KVM_UTIL_MIN_VADDR,
-				    MEM_REGION_TEST_DATA);
+	gva = vm_alloc_shared(vm, PAGE_SIZE, KVM_UTIL_MIN_VADDR,
+			      MEM_REGION_TEST_DATA);
 	hva = addr_gva2hva(vm, gva);
 
 	vcpu_args_set(vcpu, 1, gva);
@@ -150,7 +150,7 @@ static void test_sync_vmsa(uint32_t type, uint64_t policy)
 	kvm_vm_free(vm);
 }
 
-static void test_sev(void *guest_code, uint32_t type, uint64_t policy)
+static void test_sev(void *guest_code, u32 type, u64 policy)
 {
 	struct kvm_vcpu *vcpu;
 	struct kvm_vm *vm;
@@ -201,7 +201,7 @@ static void guest_shutdown_code(void)
 	__asm__ __volatile__("ud2");
 }
 
-static void test_sev_shutdown(uint32_t type, uint64_t policy)
+static void test_sev_shutdown(u32 type, u64 policy)
 {
 	struct kvm_vcpu *vcpu;
 	struct kvm_vm *vm;
@@ -218,7 +218,7 @@ static void test_sev_shutdown(uint32_t type, uint64_t policy)
 	kvm_vm_free(vm);
 }
 
-static void test_sev_smoke(void *guest, uint32_t type, uint64_t policy)
+static void test_sev_smoke(void *guest, u32 type, u64 policy)
 {
 	const u64 xf_mask = XFEATURE_MASK_X87_AVX;
 
diff --git a/tools/testing/selftests/kvm/x86/smaller_maxphyaddr_emulation_test.c b/tools/testing/selftests/kvm/x86/smaller_maxphyaddr_emulation_test.c
index 0e8aec568010..3dca85e95478 100644
--- a/tools/testing/selftests/kvm/x86/smaller_maxphyaddr_emulation_test.c
+++ b/tools/testing/selftests/kvm/x86/smaller_maxphyaddr_emulation_test.c
@@ -20,8 +20,8 @@
 
 static void guest_code(bool tdp_enabled)
 {
-	uint64_t error_code;
-	uint64_t vector;
+	u64 error_code;
+	u64 vector;
 
 	vector = kvm_asm_safe_ec(FLDS_MEM_EAX, error_code, "a"(MEM_REGION_GVA));
 
@@ -47,8 +47,8 @@ int main(int argc, char *argv[])
 	struct kvm_vcpu *vcpu;
 	struct kvm_vm *vm;
 	struct ucall uc;
-	uint64_t *hva;
-	uint64_t gpa;
+	u64 *hva;
+	gpa_t gpa;
 	int rc;
 
 	TEST_REQUIRE(kvm_has_cap(KVM_CAP_SMALLER_MAXPHYADDR));
diff --git a/tools/testing/selftests/kvm/x86/smm_test.c b/tools/testing/selftests/kvm/x86/smm_test.c
index ade8412bf94a..740051167dbd 100644
--- a/tools/testing/selftests/kvm/x86/smm_test.c
+++ b/tools/testing/selftests/kvm/x86/smm_test.c
@@ -34,13 +34,13 @@
  * independent subset of asm here.
  * SMI handler always report back fixed stage SMRAM_STAGE.
  */
-uint8_t smi_handler[] = {
+u8 smi_handler[] = {
 	0xb0, SMRAM_STAGE,    /* mov $SMRAM_STAGE, %al */
 	0xe4, SYNC_PORT,      /* in $SYNC_PORT, %al */
 	0x0f, 0xaa,           /* rsm */
 };
 
-static inline void sync_with_host(uint64_t phase)
+static inline void sync_with_host(u64 phase)
 {
 	asm volatile("in $" XSTR(SYNC_PORT)", %%al \n"
 		     : "+a" (phase));
@@ -65,7 +65,7 @@ static void guest_code(void *arg)
 {
 	#define L2_GUEST_STACK_SIZE 64
 	unsigned long l2_guest_stack[L2_GUEST_STACK_SIZE];
-	uint64_t apicbase = rdmsr(MSR_IA32_APICBASE);
+	u64 apicbase = rdmsr(MSR_IA32_APICBASE);
 	struct svm_test_data *svm = arg;
 	struct vmx_pages *vmx_pages = arg;
 
@@ -113,7 +113,7 @@ static void guest_code(void *arg)
 
 int main(int argc, char *argv[])
 {
-	vm_vaddr_t nested_gva = 0;
+	gva_t nested_gva = 0;
 
 	struct kvm_vcpu *vcpu;
 	struct kvm_regs regs;
diff --git a/tools/testing/selftests/kvm/x86/state_test.c b/tools/testing/selftests/kvm/x86/state_test.c
index 992a52504a4a..409c6cc9f921 100644
--- a/tools/testing/selftests/kvm/x86/state_test.c
+++ b/tools/testing/selftests/kvm/x86/state_test.c
@@ -144,8 +144,8 @@ static void __attribute__((__flatten__)) guest_code(void *arg)
 	GUEST_SYNC(1);
 
 	if (this_cpu_has(X86_FEATURE_XSAVE)) {
-		uint64_t supported_xcr0 = this_cpu_supported_xcr0();
-		uint8_t buffer[PAGE_SIZE];
+		u64 supported_xcr0 = this_cpu_supported_xcr0();
+		u8 buffer[PAGE_SIZE];
 
 		memset(buffer, 0xcc, sizeof(buffer));
 
@@ -172,8 +172,8 @@ static void __attribute__((__flatten__)) guest_code(void *arg)
 		}
 
 		if (this_cpu_has(X86_FEATURE_MPX)) {
-			uint64_t bounds[2] = { 10, 0xffffffffull };
-			uint64_t output[2] = { };
+			u64 bounds[2] = { 10, 0xffffffffull };
+			u64 output[2] = { };
 
 			GUEST_ASSERT(supported_xcr0 & XFEATURE_MASK_BNDREGS);
 			GUEST_ASSERT(supported_xcr0 & XFEATURE_MASK_BNDCSR);
@@ -257,8 +257,8 @@ void check_nested_state(int stage, struct kvm_x86_state *state)
 
 int main(int argc, char *argv[])
 {
-	uint64_t *xstate_bv, saved_xstate_bv;
-	vm_vaddr_t nested_gva = 0;
+	u64 *xstate_bv, saved_xstate_bv;
+	gva_t nested_gva = 0;
 	struct kvm_cpuid2 empty_cpuid = {};
 	struct kvm_regs regs1, regs2;
 	struct kvm_vcpu *vcpu, *vcpuN;
@@ -331,7 +331,7 @@ int main(int argc, char *argv[])
 		 * supported features, even if something goes awry in saving
 		 * the original snapshot.
 		 */
-		xstate_bv = (void *)&((uint8_t *)state->xsave->region)[512];
+		xstate_bv = (void *)&((u8 *)state->xsave->region)[512];
 		saved_xstate_bv = *xstate_bv;
 
 		vcpuN = __vm_vcpu_add(vm, vcpu->id + 1);
diff --git a/tools/testing/selftests/kvm/x86/svm_int_ctl_test.c b/tools/testing/selftests/kvm/x86/svm_int_ctl_test.c
index 917b6066cfc1..d3cc5e4f7883 100644
--- a/tools/testing/selftests/kvm/x86/svm_int_ctl_test.c
+++ b/tools/testing/selftests/kvm/x86/svm_int_ctl_test.c
@@ -82,7 +82,7 @@ static void l1_guest_code(struct svm_test_data *svm)
 int main(int argc, char *argv[])
 {
 	struct kvm_vcpu *vcpu;
-	vm_vaddr_t svm_gva;
+	gva_t svm_gva;
 	struct kvm_vm *vm;
 	struct ucall uc;
 
diff --git a/tools/testing/selftests/kvm/x86/svm_lbr_nested_state.c b/tools/testing/selftests/kvm/x86/svm_lbr_nested_state.c
index ff99438824d3..7fbfaa054c95 100644
--- a/tools/testing/selftests/kvm/x86/svm_lbr_nested_state.c
+++ b/tools/testing/selftests/kvm/x86/svm_lbr_nested_state.c
@@ -97,9 +97,9 @@ void test_lbrv_nested_state(bool nested_lbrv)
 {
 	struct kvm_x86_state *state = NULL;
 	struct kvm_vcpu *vcpu;
-	vm_vaddr_t svm_gva;
 	struct kvm_vm *vm;
 	struct ucall uc;
+	gva_t svm_gva;
 
 	pr_info("Testing with nested LBRV %s\n", nested_lbrv ? "enabled" : "disabled");
 
diff --git a/tools/testing/selftests/kvm/x86/svm_nested_clear_efer_svme.c b/tools/testing/selftests/kvm/x86/svm_nested_clear_efer_svme.c
index a521a9eed061..6a89eaffc657 100644
--- a/tools/testing/selftests/kvm/x86/svm_nested_clear_efer_svme.c
+++ b/tools/testing/selftests/kvm/x86/svm_nested_clear_efer_svme.c
@@ -38,7 +38,7 @@ int main(int argc, char *argv[])
 {
 	struct kvm_vcpu *vcpu;
 	struct kvm_vm *vm;
-	vm_vaddr_t nested_gva = 0;
+	gva_t nested_gva = 0;
 
 	TEST_REQUIRE(kvm_cpu_has(X86_FEATURE_SVM));
 
diff --git a/tools/testing/selftests/kvm/x86/svm_nested_shutdown_test.c b/tools/testing/selftests/kvm/x86/svm_nested_shutdown_test.c
index 00135cbba35e..c6ea3d609a62 100644
--- a/tools/testing/selftests/kvm/x86/svm_nested_shutdown_test.c
+++ b/tools/testing/selftests/kvm/x86/svm_nested_shutdown_test.c
@@ -42,7 +42,7 @@ static void l1_guest_code(struct svm_test_data *svm, struct idt_entry *idt)
 int main(int argc, char *argv[])
 {
 	struct kvm_vcpu *vcpu;
-	vm_vaddr_t svm_gva;
+	gva_t svm_gva;
 	struct kvm_vm *vm;
 
 	TEST_REQUIRE(kvm_cpu_has(X86_FEATURE_SVM));
diff --git a/tools/testing/selftests/kvm/x86/svm_nested_soft_inject_test.c b/tools/testing/selftests/kvm/x86/svm_nested_soft_inject_test.c
index 4bd1655f9e6d..f72f11d4c4f8 100644
--- a/tools/testing/selftests/kvm/x86/svm_nested_soft_inject_test.c
+++ b/tools/testing/selftests/kvm/x86/svm_nested_soft_inject_test.c
@@ -76,7 +76,7 @@ static void l2_guest_code_nmi(void)
 	ud2();
 }
 
-static void l1_guest_code(struct svm_test_data *svm, uint64_t is_nmi, uint64_t idt_alt)
+static void l1_guest_code(struct svm_test_data *svm, u64 is_nmi, u64 idt_alt)
 {
 	#define L2_GUEST_STACK_SIZE 64
 	unsigned long l2_guest_stack[L2_GUEST_STACK_SIZE];
@@ -144,8 +144,8 @@ static void run_test(bool is_nmi)
 {
 	struct kvm_vcpu *vcpu;
 	struct kvm_vm *vm;
-	vm_vaddr_t svm_gva;
-	vm_vaddr_t idt_alt_vm;
+	gva_t svm_gva;
+	gva_t idt_alt_vm;
 	struct kvm_guest_debug debug;
 
 	pr_info("Running %s test\n", is_nmi ? "NMI" : "soft int");
@@ -161,14 +161,14 @@ static void run_test(bool is_nmi)
 	if (!is_nmi) {
 		void *idt, *idt_alt;
 
-		idt_alt_vm = vm_vaddr_alloc_page(vm);
+		idt_alt_vm = vm_alloc_page(vm);
 		idt_alt = addr_gva2hva(vm, idt_alt_vm);
 		idt = addr_gva2hva(vm, vm->arch.idt);
 		memcpy(idt_alt, idt, getpagesize());
 	} else {
 		idt_alt_vm = 0;
 	}
-	vcpu_args_set(vcpu, 3, svm_gva, (uint64_t)is_nmi, (uint64_t)idt_alt_vm);
+	vcpu_args_set(vcpu, 3, svm_gva, (u64)is_nmi, (u64)idt_alt_vm);
 
 	memset(&debug, 0, sizeof(debug));
 	vcpu_guest_debug_set(vcpu, &debug);
diff --git a/tools/testing/selftests/kvm/x86/svm_nested_vmcb12_gpa.c b/tools/testing/selftests/kvm/x86/svm_nested_vmcb12_gpa.c
index 569869bed20b..a4935ce2fb99 100644
--- a/tools/testing/selftests/kvm/x86/svm_nested_vmcb12_gpa.c
+++ b/tools/testing/selftests/kvm/x86/svm_nested_vmcb12_gpa.c
@@ -28,28 +28,28 @@ static void l2_code(void)
 	vmcall();
 }
 
-static void l1_vmrun(struct svm_test_data *svm, u64 gpa)
+static void l1_vmrun(struct svm_test_data *svm, gpa_t gpa)
 {
 	generic_svm_setup(svm, l2_code, &l2_guest_stack[L2_GUEST_STACK_SIZE]);
 
 	asm volatile ("vmrun %[gpa]" : : [gpa] "a" (gpa) : "memory");
 }
 
-static void l1_vmload(struct svm_test_data *svm, u64 gpa)
+static void l1_vmload(struct svm_test_data *svm, gpa_t gpa)
 {
 	generic_svm_setup(svm, l2_code, &l2_guest_stack[L2_GUEST_STACK_SIZE]);
 
 	asm volatile ("vmload %[gpa]" : : [gpa] "a" (gpa) : "memory");
 }
 
-static void l1_vmsave(struct svm_test_data *svm, u64 gpa)
+static void l1_vmsave(struct svm_test_data *svm, gpa_t gpa)
 {
 	generic_svm_setup(svm, l2_code, &l2_guest_stack[L2_GUEST_STACK_SIZE]);
 
 	asm volatile ("vmsave %[gpa]" : : [gpa] "a" (gpa) : "memory");
 }
 
-static void l1_vmexit(struct svm_test_data *svm, u64 gpa)
+static void l1_vmexit(struct svm_test_data *svm, gpa_t gpa)
 {
 	generic_svm_setup(svm, l2_code, &l2_guest_stack[L2_GUEST_STACK_SIZE]);
 
@@ -74,7 +74,7 @@ static u64 unmappable_gpa(struct kvm_vcpu *vcpu)
 
 static void test_invalid_vmcb12(struct kvm_vcpu *vcpu)
 {
-	vm_vaddr_t nested_gva = 0;
+	gva_t nested_gva = 0;
 	struct ucall uc;
 
 
@@ -90,7 +90,7 @@ static void test_invalid_vmcb12(struct kvm_vcpu *vcpu)
 
 static void test_unmappable_vmcb12(struct kvm_vcpu *vcpu)
 {
-	vm_vaddr_t nested_gva = 0;
+	gva_t nested_gva = 0;
 
 	vcpu_alloc_svm(vcpu->vm, &nested_gva);
 	vcpu_args_set(vcpu, 2, nested_gva, unmappable_gpa(vcpu));
@@ -103,7 +103,7 @@ static void test_unmappable_vmcb12(struct kvm_vcpu *vcpu)
 static void test_unmappable_vmcb12_vmexit(struct kvm_vcpu *vcpu)
 {
 	struct kvm_x86_state *state;
-	vm_vaddr_t nested_gva = 0;
+	gva_t nested_gva = 0;
 	struct ucall uc;
 
 	/*
diff --git a/tools/testing/selftests/kvm/x86/svm_vmcall_test.c b/tools/testing/selftests/kvm/x86/svm_vmcall_test.c
index 8a62cca28cfb..b1887242f3b8 100644
--- a/tools/testing/selftests/kvm/x86/svm_vmcall_test.c
+++ b/tools/testing/selftests/kvm/x86/svm_vmcall_test.c
@@ -36,7 +36,7 @@ static void l1_guest_code(struct svm_test_data *svm)
 int main(int argc, char *argv[])
 {
 	struct kvm_vcpu *vcpu;
-	vm_vaddr_t svm_gva;
+	gva_t svm_gva;
 	struct kvm_vm *vm;
 
 	TEST_REQUIRE(kvm_cpu_has(X86_FEATURE_SVM));
diff --git a/tools/testing/selftests/kvm/x86/sync_regs_test.c b/tools/testing/selftests/kvm/x86/sync_regs_test.c
index 8fa3948b0170..e0c52321f87c 100644
--- a/tools/testing/selftests/kvm/x86/sync_regs_test.c
+++ b/tools/testing/selftests/kvm/x86/sync_regs_test.c
@@ -20,7 +20,7 @@
 #include "kvm_util.h"
 #include "processor.h"
 
-#define UCALL_PIO_PORT ((uint16_t)0x1000)
+#define UCALL_PIO_PORT ((u16)0x1000)
 
 struct ucall uc_none = {
 	.cmd = UCALL_NONE,
diff --git a/tools/testing/selftests/kvm/x86/triple_fault_event_test.c b/tools/testing/selftests/kvm/x86/triple_fault_event_test.c
index 56306a19144a..f1c488e0d497 100644
--- a/tools/testing/selftests/kvm/x86/triple_fault_event_test.c
+++ b/tools/testing/selftests/kvm/x86/triple_fault_event_test.c
@@ -72,13 +72,13 @@ int main(void)
 
 
 	if (has_vmx) {
-		vm_vaddr_t vmx_pages_gva;
+		gva_t vmx_pages_gva;
 
 		vm = vm_create_with_one_vcpu(&vcpu, l1_guest_code_vmx);
 		vcpu_alloc_vmx(vm, &vmx_pages_gva);
 		vcpu_args_set(vcpu, 1, vmx_pages_gva);
 	} else {
-		vm_vaddr_t svm_gva;
+		gva_t svm_gva;
 
 		vm = vm_create_with_one_vcpu(&vcpu, l1_guest_code_svm);
 		vcpu_alloc_svm(vm, &svm_gva);
diff --git a/tools/testing/selftests/kvm/x86/tsc_msrs_test.c b/tools/testing/selftests/kvm/x86/tsc_msrs_test.c
index 12b0964f4f13..91583969a14f 100644
--- a/tools/testing/selftests/kvm/x86/tsc_msrs_test.c
+++ b/tools/testing/selftests/kvm/x86/tsc_msrs_test.c
@@ -95,7 +95,7 @@ int main(void)
 {
 	struct kvm_vcpu *vcpu;
 	struct kvm_vm *vm;
-	uint64_t val;
+	u64 val;
 
 	ksft_print_header();
 	ksft_set_plan(5);
diff --git a/tools/testing/selftests/kvm/x86/tsc_scaling_sync.c b/tools/testing/selftests/kvm/x86/tsc_scaling_sync.c
index 59c7304f805e..59da8d4da607 100644
--- a/tools/testing/selftests/kvm/x86/tsc_scaling_sync.c
+++ b/tools/testing/selftests/kvm/x86/tsc_scaling_sync.c
@@ -21,10 +21,10 @@ pthread_spinlock_t create_lock;
 #define TEST_TSC_KHZ    2345678UL
 #define TEST_TSC_OFFSET 200000000
 
-uint64_t tsc_sync;
+u64 tsc_sync;
 static void guest_code(void)
 {
-	uint64_t start_tsc, local_tsc, tmp;
+	u64 start_tsc, local_tsc, tmp;
 
 	start_tsc = rdtsc();
 	do {
diff --git a/tools/testing/selftests/kvm/x86/ucna_injection_test.c b/tools/testing/selftests/kvm/x86/ucna_injection_test.c
index 1e5e564523b3..df1ec8209c76 100644
--- a/tools/testing/selftests/kvm/x86/ucna_injection_test.c
+++ b/tools/testing/selftests/kvm/x86/ucna_injection_test.c
@@ -45,7 +45,7 @@
 
 #define MCI_CTL2_RESERVED_BIT BIT_ULL(29)
 
-static uint64_t supported_mcg_caps;
+static u64 supported_mcg_caps;
 
 /*
  * Record states about the injected UCNA.
@@ -53,30 +53,30 @@ static uint64_t supported_mcg_caps;
  * handler. Variables without the 'i_' prefixes are recorded in guest main
  * execution thread.
  */
-static volatile uint64_t i_ucna_rcvd;
-static volatile uint64_t i_ucna_addr;
-static volatile uint64_t ucna_addr;
-static volatile uint64_t ucna_addr2;
+static volatile u64 i_ucna_rcvd;
+static volatile u64 i_ucna_addr;
+static volatile u64 ucna_addr;
+static volatile u64 ucna_addr2;
 
 struct thread_params {
 	struct kvm_vcpu *vcpu;
-	uint64_t *p_i_ucna_rcvd;
-	uint64_t *p_i_ucna_addr;
-	uint64_t *p_ucna_addr;
-	uint64_t *p_ucna_addr2;
+	u64 *p_i_ucna_rcvd;
+	u64 *p_i_ucna_addr;
+	u64 *p_ucna_addr;
+	u64 *p_ucna_addr2;
 };
 
 static void verify_apic_base_addr(void)
 {
-	uint64_t msr = rdmsr(MSR_IA32_APICBASE);
-	uint64_t base = GET_APIC_BASE(msr);
+	u64 msr = rdmsr(MSR_IA32_APICBASE);
+	u64 base = GET_APIC_BASE(msr);
 
 	GUEST_ASSERT(base == APIC_DEFAULT_GPA);
 }
 
 static void ucna_injection_guest_code(void)
 {
-	uint64_t ctl2;
+	u64 ctl2;
 	verify_apic_base_addr();
 	xapic_enable();
 
@@ -106,7 +106,7 @@ static void ucna_injection_guest_code(void)
 
 static void cmci_disabled_guest_code(void)
 {
-	uint64_t ctl2 = rdmsr(MSR_IA32_MCx_CTL2(UCNA_BANK));
+	u64 ctl2 = rdmsr(MSR_IA32_MCx_CTL2(UCNA_BANK));
 	wrmsr(MSR_IA32_MCx_CTL2(UCNA_BANK), ctl2 | MCI_CTL2_CMCI_EN);
 
 	GUEST_DONE();
@@ -114,7 +114,7 @@ static void cmci_disabled_guest_code(void)
 
 static void cmci_enabled_guest_code(void)
 {
-	uint64_t ctl2 = rdmsr(MSR_IA32_MCx_CTL2(UCNA_BANK));
+	u64 ctl2 = rdmsr(MSR_IA32_MCx_CTL2(UCNA_BANK));
 	wrmsr(MSR_IA32_MCx_CTL2(UCNA_BANK), ctl2 | MCI_CTL2_RESERVED_BIT);
 
 	GUEST_DONE();
@@ -145,14 +145,15 @@ static void run_vcpu_expect_gp(struct kvm_vcpu *vcpu)
 	printf("vCPU received GP in guest.\n");
 }
 
-static void inject_ucna(struct kvm_vcpu *vcpu, uint64_t addr) {
+static void inject_ucna(struct kvm_vcpu *vcpu, u64 addr)
+{
 	/*
 	 * A UCNA error is indicated with VAL=1, UC=1, PCC=0, S=0 and AR=0 in
 	 * the IA32_MCi_STATUS register.
 	 * MSCOD=1 (BIT[16] - MscodDataRdErr).
 	 * MCACOD=0x0090 (Memory controller error format, channel 0)
 	 */
-	uint64_t status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
+	u64 status = MCI_STATUS_VAL | MCI_STATUS_UC | MCI_STATUS_EN |
 			  MCI_STATUS_MISCV | MCI_STATUS_ADDRV | 0x10090;
 	struct kvm_x86_mce mce = {};
 	mce.status = status;
@@ -216,10 +217,10 @@ static void test_ucna_injection(struct kvm_vcpu *vcpu, struct thread_params *par
 {
 	struct kvm_vm *vm = vcpu->vm;
 	params->vcpu = vcpu;
-	params->p_i_ucna_rcvd = (uint64_t *)addr_gva2hva(vm, (uint64_t)&i_ucna_rcvd);
-	params->p_i_ucna_addr = (uint64_t *)addr_gva2hva(vm, (uint64_t)&i_ucna_addr);
-	params->p_ucna_addr = (uint64_t *)addr_gva2hva(vm, (uint64_t)&ucna_addr);
-	params->p_ucna_addr2 = (uint64_t *)addr_gva2hva(vm, (uint64_t)&ucna_addr2);
+	params->p_i_ucna_rcvd = (u64 *)addr_gva2hva(vm, (u64)&i_ucna_rcvd);
+	params->p_i_ucna_addr = (u64 *)addr_gva2hva(vm, (u64)&i_ucna_addr);
+	params->p_ucna_addr = (u64 *)addr_gva2hva(vm, (u64)&ucna_addr);
+	params->p_ucna_addr2 = (u64 *)addr_gva2hva(vm, (u64)&ucna_addr2);
 
 	run_ucna_injection(params);
 
@@ -242,7 +243,7 @@ static void test_ucna_injection(struct kvm_vcpu *vcpu, struct thread_params *par
 
 static void setup_mce_cap(struct kvm_vcpu *vcpu, bool enable_cmci_p)
 {
-	uint64_t mcg_caps = MCG_CTL_P | MCG_SER_P | MCG_LMCE_P | KVM_MAX_MCE_BANKS;
+	u64 mcg_caps = MCG_CTL_P | MCG_SER_P | MCG_LMCE_P | KVM_MAX_MCE_BANKS;
 	if (enable_cmci_p)
 		mcg_caps |= MCG_CMCI_P;
 
@@ -250,7 +251,7 @@ static void setup_mce_cap(struct kvm_vcpu *vcpu, bool enable_cmci_p)
 	vcpu_ioctl(vcpu, KVM_X86_SETUP_MCE, &mcg_caps);
 }
 
-static struct kvm_vcpu *create_vcpu_with_mce_cap(struct kvm_vm *vm, uint32_t vcpuid,
+static struct kvm_vcpu *create_vcpu_with_mce_cap(struct kvm_vm *vm, u32 vcpuid,
 						 bool enable_cmci_p, void *guest_code)
 {
 	struct kvm_vcpu *vcpu = vm_vcpu_add(vm, vcpuid, guest_code);
diff --git a/tools/testing/selftests/kvm/x86/userspace_io_test.c b/tools/testing/selftests/kvm/x86/userspace_io_test.c
index be7d72f3c029..9c5a87576c2e 100644
--- a/tools/testing/selftests/kvm/x86/userspace_io_test.c
+++ b/tools/testing/selftests/kvm/x86/userspace_io_test.c
@@ -10,7 +10,7 @@
 #include "kvm_util.h"
 #include "processor.h"
 
-static void guest_ins_port80(uint8_t *buffer, unsigned int count)
+static void guest_ins_port80(u8 *buffer, unsigned int count)
 {
 	unsigned long end;
 
@@ -26,7 +26,7 @@ static void guest_ins_port80(uint8_t *buffer, unsigned int count)
 
 static void guest_code(void)
 {
-	uint8_t buffer[8192];
+	u8 buffer[8192];
 	int i;
 
 	/*
diff --git a/tools/testing/selftests/kvm/x86/userspace_msr_exit_test.c b/tools/testing/selftests/kvm/x86/userspace_msr_exit_test.c
index 8463a9956410..2808ce727e5f 100644
--- a/tools/testing/selftests/kvm/x86/userspace_msr_exit_test.c
+++ b/tools/testing/selftests/kvm/x86/userspace_msr_exit_test.c
@@ -23,21 +23,21 @@ struct kvm_msr_filter filter_allow = {
 			.nmsrs = 1,
 			/* Test an MSR the kernel knows about. */
 			.base = MSR_IA32_XSS,
-			.bitmap = (uint8_t*)&deny_bits,
+			.bitmap = (u8 *)&deny_bits,
 		}, {
 			.flags = KVM_MSR_FILTER_READ |
 				 KVM_MSR_FILTER_WRITE,
 			.nmsrs = 1,
 			/* Test an MSR the kernel doesn't know about. */
 			.base = MSR_IA32_FLUSH_CMD,
-			.bitmap = (uint8_t*)&deny_bits,
+			.bitmap = (u8 *)&deny_bits,
 		}, {
 			.flags = KVM_MSR_FILTER_READ |
 				 KVM_MSR_FILTER_WRITE,
 			.nmsrs = 1,
 			/* Test a fabricated MSR that no one knows about. */
 			.base = MSR_NON_EXISTENT,
-			.bitmap = (uint8_t*)&deny_bits,
+			.bitmap = (u8 *)&deny_bits,
 		},
 	},
 };
@@ -49,7 +49,7 @@ struct kvm_msr_filter filter_fs = {
 			.flags = KVM_MSR_FILTER_READ,
 			.nmsrs = 1,
 			.base = MSR_FS_BASE,
-			.bitmap = (uint8_t*)&deny_bits,
+			.bitmap = (u8 *)&deny_bits,
 		},
 	},
 };
@@ -61,12 +61,12 @@ struct kvm_msr_filter filter_gs = {
 			.flags = KVM_MSR_FILTER_READ,
 			.nmsrs = 1,
 			.base = MSR_GS_BASE,
-			.bitmap = (uint8_t*)&deny_bits,
+			.bitmap = (u8 *)&deny_bits,
 		},
 	},
 };
 
-static uint64_t msr_non_existent_data;
+static u64 msr_non_existent_data;
 static int guest_exception_count;
 static u32 msr_reads, msr_writes;
 
@@ -77,7 +77,7 @@ static u8 bitmap_c0000000[KVM_MSR_FILTER_MAX_BITMAP_SIZE];
 static u8 bitmap_c0000000_read[KVM_MSR_FILTER_MAX_BITMAP_SIZE];
 static u8 bitmap_deadbeef[1] = { 0x1 };
 
-static void deny_msr(uint8_t *bitmap, u32 msr)
+static void deny_msr(u8 *bitmap, u32 msr)
 {
 	u32 idx = msr & (KVM_MSR_FILTER_MAX_BITMAP_SIZE - 1);
 
@@ -142,26 +142,26 @@ struct kvm_msr_filter no_filter_deny = {
  * Note: Force test_rdmsr() to not be inlined to prevent the labels,
  * rdmsr_start and rdmsr_end, from being defined multiple times.
  */
-static noinline uint64_t test_rdmsr(uint32_t msr)
+static noinline u64 test_rdmsr(u32 msr)
 {
-	uint32_t a, d;
+	u32 a, d;
 
 	guest_exception_count = 0;
 
 	__asm__ __volatile__("rdmsr_start: rdmsr; rdmsr_end:" :
 			"=a"(a), "=d"(d) : "c"(msr) : "memory");
 
-	return a | ((uint64_t) d << 32);
+	return a | ((u64)d << 32);
 }
 
 /*
  * Note: Force test_wrmsr() to not be inlined to prevent the labels,
  * wrmsr_start and wrmsr_end, from being defined multiple times.
  */
-static noinline void test_wrmsr(uint32_t msr, uint64_t value)
+static noinline void test_wrmsr(u32 msr, u64 value)
 {
-	uint32_t a = value;
-	uint32_t d = value >> 32;
+	u32 a = value;
+	u32 d = value >> 32;
 
 	guest_exception_count = 0;
 
@@ -176,26 +176,26 @@ extern char wrmsr_start, wrmsr_end;
  * Note: Force test_em_rdmsr() to not be inlined to prevent the labels,
  * rdmsr_start and rdmsr_end, from being defined multiple times.
  */
-static noinline uint64_t test_em_rdmsr(uint32_t msr)
+static noinline u64 test_em_rdmsr(u32 msr)
 {
-	uint32_t a, d;
+	u32 a, d;
 
 	guest_exception_count = 0;
 
 	__asm__ __volatile__(KVM_FEP "em_rdmsr_start: rdmsr; em_rdmsr_end:" :
 			"=a"(a), "=d"(d) : "c"(msr) : "memory");
 
-	return a | ((uint64_t) d << 32);
+	return a | ((u64)d << 32);
 }
 
 /*
  * Note: Force test_em_wrmsr() to not be inlined to prevent the labels,
  * wrmsr_start and wrmsr_end, from being defined multiple times.
  */
-static noinline void test_em_wrmsr(uint32_t msr, uint64_t value)
+static noinline void test_em_wrmsr(u32 msr, u64 value)
 {
-	uint32_t a = value;
-	uint32_t d = value >> 32;
+	u32 a = value;
+	u32 d = value >> 32;
 
 	guest_exception_count = 0;
 
@@ -208,7 +208,7 @@ extern char em_wrmsr_start, em_wrmsr_end;
 
 static void guest_code_filter_allow(void)
 {
-	uint64_t data;
+	u64 data;
 
 	/*
 	 * Test userspace intercepting rdmsr / wrmsr for MSR_IA32_XSS.
@@ -328,7 +328,7 @@ static void guest_code_filter_deny(void)
 
 static void guest_code_permission_bitmap(void)
 {
-	uint64_t data;
+	u64 data;
 
 	data = test_rdmsr(MSR_FS_BASE);
 	GUEST_ASSERT(data == MSR_FS_BASE);
@@ -391,7 +391,7 @@ static void check_for_guest_assert(struct kvm_vcpu *vcpu)
 	}
 }
 
-static void process_rdmsr(struct kvm_vcpu *vcpu, uint32_t msr_index)
+static void process_rdmsr(struct kvm_vcpu *vcpu, u32 msr_index)
 {
 	struct kvm_run *run = vcpu->run;
 
@@ -423,7 +423,7 @@ static void process_rdmsr(struct kvm_vcpu *vcpu, uint32_t msr_index)
 	}
 }
 
-static void process_wrmsr(struct kvm_vcpu *vcpu, uint32_t msr_index)
+static void process_wrmsr(struct kvm_vcpu *vcpu, u32 msr_index)
 {
 	struct kvm_run *run = vcpu->run;
 
@@ -464,7 +464,7 @@ static void process_ucall_done(struct kvm_vcpu *vcpu)
 		    uc.cmd, UCALL_DONE);
 }
 
-static uint64_t process_ucall(struct kvm_vcpu *vcpu)
+static u64 process_ucall(struct kvm_vcpu *vcpu)
 {
 	struct ucall uc = {};
 
@@ -489,20 +489,20 @@ static uint64_t process_ucall(struct kvm_vcpu *vcpu)
 }
 
 static void run_guest_then_process_rdmsr(struct kvm_vcpu *vcpu,
-					 uint32_t msr_index)
+					 u32 msr_index)
 {
 	vcpu_run(vcpu);
 	process_rdmsr(vcpu, msr_index);
 }
 
 static void run_guest_then_process_wrmsr(struct kvm_vcpu *vcpu,
-					 uint32_t msr_index)
+					 u32 msr_index)
 {
 	vcpu_run(vcpu);
 	process_wrmsr(vcpu, msr_index);
 }
 
-static uint64_t run_guest_then_process_ucall(struct kvm_vcpu *vcpu)
+static u64 run_guest_then_process_ucall(struct kvm_vcpu *vcpu)
 {
 	vcpu_run(vcpu);
 	return process_ucall(vcpu);
@@ -519,7 +519,7 @@ KVM_ONE_VCPU_TEST_SUITE(user_msr);
 KVM_ONE_VCPU_TEST(user_msr, msr_filter_allow, guest_code_filter_allow)
 {
 	struct kvm_vm *vm = vcpu->vm;
-	uint64_t cmd;
+	u64 cmd;
 	int rc;
 
 	rc = kvm_check_cap(KVM_CAP_X86_USER_SPACE_MSR);
@@ -732,7 +732,7 @@ static void run_msr_filter_flag_test(struct kvm_vm *vm)
 				.flags = KVM_MSR_FILTER_READ,
 				.nmsrs = 1,
 				.base = 0,
-				.bitmap = (uint8_t *)&deny_bits,
+				.bitmap = (u8 *)&deny_bits,
 			},
 		},
 	};
diff --git a/tools/testing/selftests/kvm/x86/vmx_apic_access_test.c b/tools/testing/selftests/kvm/x86/vmx_apic_access_test.c
index a81a24761aac..1720113eae79 100644
--- a/tools/testing/selftests/kvm/x86/vmx_apic_access_test.c
+++ b/tools/testing/selftests/kvm/x86/vmx_apic_access_test.c
@@ -38,7 +38,7 @@ static void l1_guest_code(struct vmx_pages *vmx_pages, unsigned long high_gpa)
 {
 #define L2_GUEST_STACK_SIZE 64
 	unsigned long l2_guest_stack[L2_GUEST_STACK_SIZE];
-	uint32_t control;
+	u32 control;
 
 	GUEST_ASSERT(prepare_for_vmx_operation(vmx_pages));
 	GUEST_ASSERT(load_vmcs(vmx_pages));
@@ -72,7 +72,7 @@ static void l1_guest_code(struct vmx_pages *vmx_pages, unsigned long high_gpa)
 int main(int argc, char *argv[])
 {
 	unsigned long apic_access_addr = ~0ul;
-	vm_vaddr_t vmx_pages_gva;
+	gva_t vmx_pages_gva;
 	unsigned long high_gpa;
 	struct vmx_pages *vmx;
 	bool done = false;
diff --git a/tools/testing/selftests/kvm/x86/vmx_apicv_updates_test.c b/tools/testing/selftests/kvm/x86/vmx_apicv_updates_test.c
index 337c53fddeff..80a4fd1e5bbb 100644
--- a/tools/testing/selftests/kvm/x86/vmx_apicv_updates_test.c
+++ b/tools/testing/selftests/kvm/x86/vmx_apicv_updates_test.c
@@ -33,7 +33,7 @@ static void l1_guest_code(struct vmx_pages *vmx_pages)
 {
 #define L2_GUEST_STACK_SIZE 64
 	unsigned long l2_guest_stack[L2_GUEST_STACK_SIZE];
-	uint32_t control;
+	u32 control;
 
 	GUEST_ASSERT(prepare_for_vmx_operation(vmx_pages));
 	GUEST_ASSERT(load_vmcs(vmx_pages));
@@ -110,7 +110,7 @@ static void l1_guest_code(struct vmx_pages *vmx_pages)
 
 int main(int argc, char *argv[])
 {
-	vm_vaddr_t vmx_pages_gva;
+	gva_t vmx_pages_gva;
 	struct vmx_pages *vmx;
 	struct kvm_vcpu *vcpu;
 	struct kvm_vm *vm;
diff --git a/tools/testing/selftests/kvm/x86/vmx_invalid_nested_guest_state.c b/tools/testing/selftests/kvm/x86/vmx_invalid_nested_guest_state.c
index a100ee5f0009..a2eaceed9ad5 100644
--- a/tools/testing/selftests/kvm/x86/vmx_invalid_nested_guest_state.c
+++ b/tools/testing/selftests/kvm/x86/vmx_invalid_nested_guest_state.c
@@ -52,7 +52,7 @@ static void l1_guest_code(struct vmx_pages *vmx_pages)
 
 int main(int argc, char *argv[])
 {
-	vm_vaddr_t vmx_pages_gva;
+	gva_t vmx_pages_gva;
 	struct kvm_sregs sregs;
 	struct kvm_vcpu *vcpu;
 	struct kvm_run *run;
diff --git a/tools/testing/selftests/kvm/x86/vmx_msrs_test.c b/tools/testing/selftests/kvm/x86/vmx_msrs_test.c
index 90720b6205f4..c1e8632a1bb6 100644
--- a/tools/testing/selftests/kvm/x86/vmx_msrs_test.c
+++ b/tools/testing/selftests/kvm/x86/vmx_msrs_test.c
@@ -12,11 +12,10 @@
 #include "kvm_util.h"
 #include "vmx.h"
 
-static void vmx_fixed1_msr_test(struct kvm_vcpu *vcpu, uint32_t msr_index,
-				  uint64_t mask)
+static void vmx_fixed1_msr_test(struct kvm_vcpu *vcpu, u32 msr_index, u64 mask)
 {
-	uint64_t val = vcpu_get_msr(vcpu, msr_index);
-	uint64_t bit;
+	u64 val = vcpu_get_msr(vcpu, msr_index);
+	u64 bit;
 
 	mask &= val;
 
@@ -26,11 +25,10 @@ static void vmx_fixed1_msr_test(struct kvm_vcpu *vcpu, uint32_t msr_index,
 	}
 }
 
-static void vmx_fixed0_msr_test(struct kvm_vcpu *vcpu, uint32_t msr_index,
-				uint64_t mask)
+static void vmx_fixed0_msr_test(struct kvm_vcpu *vcpu, u32 msr_index, u64 mask)
 {
-	uint64_t val = vcpu_get_msr(vcpu, msr_index);
-	uint64_t bit;
+	u64 val = vcpu_get_msr(vcpu, msr_index);
+	u64 bit;
 
 	mask = ~mask | val;
 
@@ -40,7 +38,7 @@ static void vmx_fixed0_msr_test(struct kvm_vcpu *vcpu, uint32_t msr_index,
 	}
 }
 
-static void vmx_fixed0and1_msr_test(struct kvm_vcpu *vcpu, uint32_t msr_index)
+static void vmx_fixed0and1_msr_test(struct kvm_vcpu *vcpu, u32 msr_index)
 {
 	vmx_fixed0_msr_test(vcpu, msr_index, GENMASK_ULL(31, 0));
 	vmx_fixed1_msr_test(vcpu, msr_index, GENMASK_ULL(63, 32));
@@ -68,10 +66,10 @@ static void vmx_save_restore_msrs_test(struct kvm_vcpu *vcpu)
 }
 
 static void __ia32_feature_control_msr_test(struct kvm_vcpu *vcpu,
-					    uint64_t msr_bit,
+					    u64 msr_bit,
 					    struct kvm_x86_cpu_feature feature)
 {
-	uint64_t val;
+	u64 val;
 
 	vcpu_clear_cpuid_feature(vcpu, feature);
 
@@ -90,7 +88,7 @@ static void __ia32_feature_control_msr_test(struct kvm_vcpu *vcpu,
 
 static void ia32_feature_control_msr_test(struct kvm_vcpu *vcpu)
 {
-	uint64_t supported_bits = FEAT_CTL_LOCKED |
+	u64 supported_bits = FEAT_CTL_LOCKED |
 				  FEAT_CTL_VMX_ENABLED_INSIDE_SMX |
 				  FEAT_CTL_VMX_ENABLED_OUTSIDE_SMX |
 				  FEAT_CTL_SGX_LC_ENABLED |
diff --git a/tools/testing/selftests/kvm/x86/vmx_nested_la57_state_test.c b/tools/testing/selftests/kvm/x86/vmx_nested_la57_state_test.c
index 915c42001dba..f13dee317383 100644
--- a/tools/testing/selftests/kvm/x86/vmx_nested_la57_state_test.c
+++ b/tools/testing/selftests/kvm/x86/vmx_nested_la57_state_test.c
@@ -30,7 +30,7 @@ static void l1_guest_code(struct vmx_pages *vmx_pages)
 #define L2_GUEST_STACK_SIZE 64
 	unsigned long l2_guest_stack[L2_GUEST_STACK_SIZE];
 	u64 guest_cr4;
-	vm_paddr_t pml5_pa, pml4_pa;
+	gpa_t pml5_pa, pml4_pa;
 	u64 *pml5;
 	u64 exit_reason;
 
@@ -73,7 +73,7 @@ void guest_code(struct vmx_pages *vmx_pages)
 
 int main(int argc, char *argv[])
 {
-	vm_vaddr_t vmx_pages_gva = 0;
+	gva_t vmx_pages_gva = 0;
 	struct kvm_vm *vm;
 	struct kvm_vcpu *vcpu;
 	struct kvm_x86_state *state;
diff --git a/tools/testing/selftests/kvm/x86/vmx_pmu_caps_test.c b/tools/testing/selftests/kvm/x86/vmx_pmu_caps_test.c
index 7ff6f62e20a3..d004108dbdc6 100644
--- a/tools/testing/selftests/kvm/x86/vmx_pmu_caps_test.c
+++ b/tools/testing/selftests/kvm/x86/vmx_pmu_caps_test.c
@@ -52,16 +52,16 @@ static const union perf_capabilities format_caps = {
 	.pebs_format = -1,
 };
 
-static void guest_test_perf_capabilities_gp(uint64_t val)
+static void guest_test_perf_capabilities_gp(u64 val)
 {
-	uint8_t vector = wrmsr_safe(MSR_IA32_PERF_CAPABILITIES, val);
+	u8 vector = wrmsr_safe(MSR_IA32_PERF_CAPABILITIES, val);
 
 	__GUEST_ASSERT(vector == GP_VECTOR,
 		       "Expected #GP for value '0x%lx', got %s",
 		       val, ex_str(vector));
 }
 
-static void guest_code(uint64_t current_val)
+static void guest_code(u64 current_val)
 {
 	int i;
 
@@ -129,7 +129,7 @@ KVM_ONE_VCPU_TEST(vmx_pmu_caps, basic_perf_capabilities, guest_code)
 
 KVM_ONE_VCPU_TEST(vmx_pmu_caps, fungible_perf_capabilities, guest_code)
 {
-	const uint64_t fungible_caps = host_cap.capabilities & ~immutable_caps.capabilities;
+	const u64 fungible_caps = host_cap.capabilities & ~immutable_caps.capabilities;
 	int bit;
 
 	for_each_set_bit(bit, &fungible_caps, 64) {
@@ -148,7 +148,7 @@ KVM_ONE_VCPU_TEST(vmx_pmu_caps, fungible_perf_capabilities, guest_code)
  */
 KVM_ONE_VCPU_TEST(vmx_pmu_caps, immutable_perf_capabilities, guest_code)
 {
-	const uint64_t reserved_caps = (~host_cap.capabilities |
+	const u64 reserved_caps = (~host_cap.capabilities |
 					immutable_caps.capabilities) &
 				       ~format_caps.capabilities;
 	union perf_capabilities val = host_cap;
@@ -210,7 +210,7 @@ KVM_ONE_VCPU_TEST(vmx_pmu_caps, lbr_perf_capabilities, guest_code)
 
 KVM_ONE_VCPU_TEST(vmx_pmu_caps, perf_capabilities_unsupported, guest_code)
 {
-	uint64_t val;
+	u64 val;
 	int i, r;
 
 	vcpu_set_msr(vcpu, MSR_IA32_PERF_CAPABILITIES, host_cap.capabilities);
diff --git a/tools/testing/selftests/kvm/x86/vmx_preemption_timer_test.c b/tools/testing/selftests/kvm/x86/vmx_preemption_timer_test.c
index 00dd2ac07a61..1b7b6ba23de7 100644
--- a/tools/testing/selftests/kvm/x86/vmx_preemption_timer_test.c
+++ b/tools/testing/selftests/kvm/x86/vmx_preemption_timer_test.c
@@ -152,7 +152,7 @@ void guest_code(struct vmx_pages *vmx_pages)
 
 int main(int argc, char *argv[])
 {
-	vm_vaddr_t vmx_pages_gva = 0;
+	gva_t vmx_pages_gva = 0;
 
 	struct kvm_regs regs1, regs2;
 	struct kvm_vm *vm;
diff --git a/tools/testing/selftests/kvm/x86/xapic_ipi_test.c b/tools/testing/selftests/kvm/x86/xapic_ipi_test.c
index ae4a4b6c05ca..39ce9a9369f5 100644
--- a/tools/testing/selftests/kvm/x86/xapic_ipi_test.c
+++ b/tools/testing/selftests/kvm/x86/xapic_ipi_test.c
@@ -48,20 +48,20 @@
  * Incremented in the IPI handler. Provides evidence to the sender that the IPI
  * arrived at the destination
  */
-static volatile uint64_t ipis_rcvd;
+static volatile u64 ipis_rcvd;
 
 /* Data struct shared between host main thread and vCPUs */
 struct test_data_page {
-	uint32_t halter_apic_id;
-	volatile uint64_t hlt_count;
-	volatile uint64_t wake_count;
-	uint64_t ipis_sent;
-	uint64_t migrations_attempted;
-	uint64_t migrations_completed;
-	uint32_t icr;
-	uint32_t icr2;
-	uint32_t halter_tpr;
-	uint32_t halter_ppr;
+	u32 halter_apic_id;
+	volatile u64 hlt_count;
+	volatile u64 wake_count;
+	u64 ipis_sent;
+	u64 migrations_attempted;
+	u64 migrations_completed;
+	u32 icr;
+	u32 icr2;
+	u32 halter_tpr;
+	u32 halter_ppr;
 
 	/*
 	 *  Record local version register as a cross-check that APIC access
@@ -69,19 +69,19 @@ struct test_data_page {
 	 *  arch/x86/kvm/lapic.c). If test is failing, check that values match
 	 *  to determine whether APIC access exits are working.
 	 */
-	uint32_t halter_lvr;
+	u32 halter_lvr;
 };
 
 struct thread_params {
 	struct test_data_page *data;
 	struct kvm_vcpu *vcpu;
-	uint64_t *pipis_rcvd; /* host address of ipis_rcvd global */
+	u64 *pipis_rcvd; /* host address of ipis_rcvd global */
 };
 
 void verify_apic_base_addr(void)
 {
-	uint64_t msr = rdmsr(MSR_IA32_APICBASE);
-	uint64_t base = GET_APIC_BASE(msr);
+	u64 msr = rdmsr(MSR_IA32_APICBASE);
+	u64 base = GET_APIC_BASE(msr);
 
 	GUEST_ASSERT(base == APIC_DEFAULT_GPA);
 }
@@ -125,12 +125,12 @@ static void guest_ipi_handler(struct ex_regs *regs)
 
 static void sender_guest_code(struct test_data_page *data)
 {
-	uint64_t last_wake_count;
-	uint64_t last_hlt_count;
-	uint64_t last_ipis_rcvd_count;
-	uint32_t icr_val;
-	uint32_t icr2_val;
-	uint64_t tsc_start;
+	u64 last_wake_count;
+	u64 last_hlt_count;
+	u64 last_ipis_rcvd_count;
+	u32 icr_val;
+	u32 icr2_val;
+	u64 tsc_start;
 
 	verify_apic_base_addr();
 	xapic_enable();
@@ -248,7 +248,7 @@ static void cancel_join_vcpu_thread(pthread_t thread, struct kvm_vcpu *vcpu)
 }
 
 void do_migrations(struct test_data_page *data, int run_secs, int delay_usecs,
-		   uint64_t *pipis_rcvd)
+		   u64 *pipis_rcvd)
 {
 	long pages_not_moved;
 	unsigned long nodemask = 0;
@@ -259,9 +259,9 @@ void do_migrations(struct test_data_page *data, int run_secs, int delay_usecs,
 	int i;
 	int from, to;
 	unsigned long bit;
-	uint64_t hlt_count;
-	uint64_t wake_count;
-	uint64_t ipis_sent;
+	u64 hlt_count;
+	u64 wake_count;
+	u64 ipis_sent;
 
 	fprintf(stderr, "Calling migrate_pages every %d microseconds\n",
 		delay_usecs);
@@ -393,12 +393,12 @@ int main(int argc, char *argv[])
 	int run_secs = 0;
 	int delay_usecs = 0;
 	struct test_data_page *data;
-	vm_vaddr_t test_data_page_vaddr;
+	gva_t test_data_page_gva;
 	bool migrate = false;
 	pthread_t threads[2];
 	struct thread_params params[2];
 	struct kvm_vm *vm;
-	uint64_t *pipis_rcvd;
+	u64 *pipis_rcvd;
 
 	get_cmdline_args(argc, argv, &run_secs, &migrate, &delay_usecs);
 	if (run_secs <= 0)
@@ -414,16 +414,16 @@ int main(int argc, char *argv[])
 
 	params[1].vcpu = vm_vcpu_add(vm, 1, sender_guest_code);
 
-	test_data_page_vaddr = vm_vaddr_alloc_page(vm);
-	data = addr_gva2hva(vm, test_data_page_vaddr);
+	test_data_page_gva = vm_alloc_page(vm);
+	data = addr_gva2hva(vm, test_data_page_gva);
 	memset(data, 0, sizeof(*data));
 	params[0].data = data;
 	params[1].data = data;
 
-	vcpu_args_set(params[0].vcpu, 1, test_data_page_vaddr);
-	vcpu_args_set(params[1].vcpu, 1, test_data_page_vaddr);
+	vcpu_args_set(params[0].vcpu, 1, test_data_page_gva);
+	vcpu_args_set(params[1].vcpu, 1, test_data_page_gva);
 
-	pipis_rcvd = (uint64_t *)addr_gva2hva(vm, (uint64_t)&ipis_rcvd);
+	pipis_rcvd = (u64 *)addr_gva2hva(vm, (u64)&ipis_rcvd);
 	params[0].pipis_rcvd = pipis_rcvd;
 	params[1].pipis_rcvd = pipis_rcvd;
 
diff --git a/tools/testing/selftests/kvm/x86/xapic_state_test.c b/tools/testing/selftests/kvm/x86/xapic_state_test.c
index 0c5e12f5f14e..637bb90c1d93 100644
--- a/tools/testing/selftests/kvm/x86/xapic_state_test.c
+++ b/tools/testing/selftests/kvm/x86/xapic_state_test.c
@@ -23,7 +23,7 @@ static void xapic_guest_code(void)
 	xapic_enable();
 
 	while (1) {
-		uint64_t val = (u64)xapic_read_reg(APIC_IRR) |
+		u64 val = (u64)xapic_read_reg(APIC_IRR) |
 			       (u64)xapic_read_reg(APIC_IRR + 0x10) << 32;
 
 		xapic_write_reg(APIC_ICR2, val >> 32);
@@ -43,7 +43,7 @@ static void x2apic_guest_code(void)
 	x2apic_enable();
 
 	do {
-		uint64_t val = x2apic_read_reg(APIC_IRR) |
+		u64 val = x2apic_read_reg(APIC_IRR) |
 			       x2apic_read_reg(APIC_IRR + 0x10) << 32;
 
 		if (val & X2APIC_RSVD_BITS_MASK) {
@@ -56,12 +56,12 @@ static void x2apic_guest_code(void)
 	} while (1);
 }
 
-static void ____test_icr(struct xapic_vcpu *x, uint64_t val)
+static void ____test_icr(struct xapic_vcpu *x, u64 val)
 {
 	struct kvm_vcpu *vcpu = x->vcpu;
 	struct kvm_lapic_state xapic;
 	struct ucall uc;
-	uint64_t icr;
+	u64 icr;
 
 	/*
 	 * Tell the guest what ICR value to write.  Use the IRR to pass info,
@@ -93,7 +93,7 @@ static void ____test_icr(struct xapic_vcpu *x, uint64_t val)
 		TEST_ASSERT_EQ(icr, val & ~APIC_ICR_BUSY);
 }
 
-static void __test_icr(struct xapic_vcpu *x, uint64_t val)
+static void __test_icr(struct xapic_vcpu *x, u64 val)
 {
 	/*
 	 * The BUSY bit is reserved on both AMD and Intel, but only AMD treats
@@ -109,7 +109,7 @@ static void __test_icr(struct xapic_vcpu *x, uint64_t val)
 static void test_icr(struct xapic_vcpu *x)
 {
 	struct kvm_vcpu *vcpu = x->vcpu;
-	uint64_t icr, i, j;
+	u64 icr, i, j;
 
 	icr = APIC_DEST_SELF | APIC_INT_ASSERT | APIC_DM_FIXED;
 	for (i = 0; i <= 0xff; i++)
@@ -142,9 +142,9 @@ static void test_icr(struct xapic_vcpu *x)
 	__test_icr(x, -1ull & ~APIC_DM_FIXED_MASK);
 }
 
-static void __test_apic_id(struct kvm_vcpu *vcpu, uint64_t apic_base)
+static void __test_apic_id(struct kvm_vcpu *vcpu, u64 apic_base)
 {
-	uint32_t apic_id, expected;
+	u32 apic_id, expected;
 	struct kvm_lapic_state xapic;
 
 	vcpu_set_msr(vcpu, MSR_IA32_APICBASE, apic_base);
@@ -170,9 +170,9 @@ static void __test_apic_id(struct kvm_vcpu *vcpu, uint64_t apic_base)
  */
 static void test_apic_id(void)
 {
-	const uint32_t NR_VCPUS = 3;
+	const u32 NR_VCPUS = 3;
 	struct kvm_vcpu *vcpus[NR_VCPUS];
-	uint64_t apic_base;
+	u64 apic_base;
 	struct kvm_vm *vm;
 	int i;
 
diff --git a/tools/testing/selftests/kvm/x86/xapic_tpr_test.c b/tools/testing/selftests/kvm/x86/xapic_tpr_test.c
index 3862134d9d40..ab25db2235d5 100644
--- a/tools/testing/selftests/kvm/x86/xapic_tpr_test.c
+++ b/tools/testing/selftests/kvm/x86/xapic_tpr_test.c
@@ -58,7 +58,7 @@ static void tpr_guest_irq_queue(void)
 	if (is_x2apic) {
 		x2apic_write_reg(APIC_SELF_IPI, IRQ_VECTOR);
 	} else {
-		uint32_t icr, icr2;
+		u32 icr, icr2;
 
 		icr = APIC_DEST_SELF | APIC_DEST_PHYSICAL | APIC_DM_FIXED |
 			IRQ_VECTOR;
@@ -69,9 +69,9 @@ static void tpr_guest_irq_queue(void)
 	}
 }
 
-static uint8_t tpr_guest_tpr_get(void)
+static u8 tpr_guest_tpr_get(void)
 {
-	uint32_t taskpri;
+	u32 taskpri;
 
 	if (is_x2apic)
 		taskpri = x2apic_read_reg(APIC_TASKPRI);
@@ -81,9 +81,9 @@ static uint8_t tpr_guest_tpr_get(void)
 	return GET_APIC_PRI(taskpri);
 }
 
-static uint8_t tpr_guest_ppr_get(void)
+static u8 tpr_guest_ppr_get(void)
 {
-	uint32_t procpri;
+	u32 procpri;
 
 	if (is_x2apic)
 		procpri = x2apic_read_reg(APIC_PROCPRI);
@@ -93,9 +93,9 @@ static uint8_t tpr_guest_ppr_get(void)
 	return GET_APIC_PRI(procpri);
 }
 
-static uint8_t tpr_guest_cr8_get(void)
+static u8 tpr_guest_cr8_get(void)
 {
-	uint64_t cr8;
+	u64 cr8;
 
 	asm volatile ("mov %%cr8, %[cr8]\n\t" : [cr8] "=r"(cr8));
 
@@ -104,7 +104,7 @@ static uint8_t tpr_guest_cr8_get(void)
 
 static void tpr_guest_check_tpr_ppr_cr8_equal(void)
 {
-	uint8_t tpr;
+	u8 tpr;
 
 	tpr = tpr_guest_tpr_get();
 
@@ -157,19 +157,19 @@ static void tpr_guest_code(void)
 	GUEST_DONE();
 }
 
-static uint8_t lapic_tpr_get(struct kvm_lapic_state *xapic)
+static u8 lapic_tpr_get(struct kvm_lapic_state *xapic)
 {
 	return GET_APIC_PRI(*((u32 *)&xapic->regs[APIC_TASKPRI]));
 }
 
-static void lapic_tpr_set(struct kvm_lapic_state *xapic, uint8_t val)
+static void lapic_tpr_set(struct kvm_lapic_state *xapic, u8 val)
 {
 	u32 *taskpri = (u32 *)&xapic->regs[APIC_TASKPRI];
 
 	*taskpri = SET_APIC_PRI(*taskpri, val);
 }
 
-static uint8_t sregs_tpr(struct kvm_sregs *sregs)
+static u8 sregs_tpr(struct kvm_sregs *sregs)
 {
 	return sregs->cr8 & GENMASK(3, 0);
 }
@@ -197,7 +197,7 @@ static void test_tpr_check_tpr_cr8_equal(struct kvm_vcpu *vcpu)
 static void test_tpr_set_tpr_for_irq(struct kvm_vcpu *vcpu, bool mask)
 {
 	struct kvm_lapic_state xapic;
-	uint8_t tpr;
+	u8 tpr;
 
 	static_assert(IRQ_VECTOR >= 16, "invalid IRQ vector number");
 	tpr = IRQ_VECTOR / 16;
diff --git a/tools/testing/selftests/kvm/x86/xcr0_cpuid_test.c b/tools/testing/selftests/kvm/x86/xcr0_cpuid_test.c
index d038c1571729..40dc9e6b3fad 100644
--- a/tools/testing/selftests/kvm/x86/xcr0_cpuid_test.c
+++ b/tools/testing/selftests/kvm/x86/xcr0_cpuid_test.c
@@ -21,7 +21,7 @@
  */
 #define ASSERT_XFEATURE_DEPENDENCIES(supported_xcr0, xfeatures, dependencies)		\
 do {											\
-	uint64_t __supported = (supported_xcr0) & ((xfeatures) | (dependencies));	\
+	u64 __supported = (supported_xcr0) & ((xfeatures) | (dependencies));	\
 											\
 	__GUEST_ASSERT((__supported & (xfeatures)) != (xfeatures) ||			\
 		       __supported == ((xfeatures) | (dependencies)),			\
@@ -39,7 +39,7 @@ do {											\
  */
 #define ASSERT_ALL_OR_NONE_XFEATURE(supported_xcr0, xfeatures)		\
 do {									\
-	uint64_t __supported = (supported_xcr0) & (xfeatures);		\
+	u64 __supported = (supported_xcr0) & (xfeatures);		\
 									\
 	__GUEST_ASSERT(!__supported || __supported == (xfeatures),	\
 		       "supported = 0x%lx, xfeatures = 0x%llx",		\
@@ -48,8 +48,8 @@ do {									\
 
 static void guest_code(void)
 {
-	uint64_t initial_xcr0;
-	uint64_t supported_xcr0;
+	u64 initial_xcr0;
+	u64 supported_xcr0;
 	int i, vector;
 
 	set_cr4(get_cr4() | X86_CR4_OSXSAVE);
diff --git a/tools/testing/selftests/kvm/x86/xen_shinfo_test.c b/tools/testing/selftests/kvm/x86/xen_shinfo_test.c
index 23909b501ac2..5076f6a75455 100644
--- a/tools/testing/selftests/kvm/x86/xen_shinfo_test.c
+++ b/tools/testing/selftests/kvm/x86/xen_shinfo_test.c
@@ -116,15 +116,15 @@ struct pvclock_wall_clock {
 } __attribute__((__packed__));
 
 struct vcpu_runstate_info {
-	uint32_t state;
-	uint64_t state_entry_time;
-	uint64_t time[5]; /* Extra field for overrun check */
+	u32 state;
+	u64 state_entry_time;
+	u64 time[5]; /* Extra field for overrun check */
 };
 
 struct compat_vcpu_runstate_info {
-	uint32_t state;
-	uint64_t state_entry_time;
-	uint64_t time[5];
+	u32 state;
+	u64 state_entry_time;
+	u64 time[5];
 } __attribute__((__packed__));
 
 struct arch_vcpu_info {
@@ -133,8 +133,8 @@ struct arch_vcpu_info {
 };
 
 struct vcpu_info {
-	uint8_t evtchn_upcall_pending;
-	uint8_t evtchn_upcall_mask;
+	u8 evtchn_upcall_pending;
+	u8 evtchn_upcall_mask;
 	unsigned long evtchn_pending_sel;
 	struct arch_vcpu_info arch;
 	struct pvclock_vcpu_time_info time;
@@ -145,7 +145,7 @@ struct shared_info {
 	unsigned long evtchn_pending[64];
 	unsigned long evtchn_mask[64];
 	struct pvclock_wall_clock wc;
-	uint32_t wc_sec_hi;
+	u32 wc_sec_hi;
 	/* arch_shared_info here */
 };
 
@@ -658,7 +658,7 @@ int main(int argc, char *argv[])
 					printf("Testing RUNSTATE_ADJUST\n");
 				rst.type = KVM_XEN_VCPU_ATTR_TYPE_RUNSTATE_ADJUST;
 				memset(&rst.u, 0, sizeof(rst.u));
-				rst.u.runstate.state = (uint64_t)-1;
+				rst.u.runstate.state = (u64)-1;
 				rst.u.runstate.time_blocked =
 					0x5a - rs->time[RUNSTATE_blocked];
 				rst.u.runstate.time_offline =
@@ -1113,7 +1113,7 @@ int main(int argc, char *argv[])
 			/* Don't change the address, just trigger a write */
 			struct kvm_xen_vcpu_attr adj = {
 				.type = KVM_XEN_VCPU_ATTR_TYPE_RUNSTATE_ADJUST,
-				.u.runstate.state = (uint64_t)-1
+				.u.runstate.state = (u64)-1
 			};
 			vcpu_ioctl(vcpu, KVM_XEN_VCPU_SET_ATTR, &adj);
 
diff --git a/tools/testing/selftests/kvm/x86/xss_msr_test.c b/tools/testing/selftests/kvm/x86/xss_msr_test.c
index f331a4e9bae3..12c63df6bbce 100644
--- a/tools/testing/selftests/kvm/x86/xss_msr_test.c
+++ b/tools/testing/selftests/kvm/x86/xss_msr_test.c
@@ -17,7 +17,7 @@ int main(int argc, char *argv[])
 	bool xss_in_msr_list;
 	struct kvm_vm *vm;
 	struct kvm_vcpu *vcpu;
-	uint64_t xss_val;
+	u64 xss_val;
 	int i, r;
 
 	/* Create VM */
diff --git a/tools/testing/selftests/mm/config b/tools/testing/selftests/mm/config
index 1dbe2b4558ab..06f78bd232e2 100644
--- a/tools/testing/selftests/mm/config
+++ b/tools/testing/selftests/mm/config
@@ -13,3 +13,4 @@ CONFIG_PROFILING=y
 CONFIG_UPROBES=y
 CONFIG_MEMORY_FAILURE=y
 CONFIG_HWPOISON_INJECT=m
+CONFIG_PROC_MEM_ALWAYS_FORCE=y
diff --git a/tools/testing/selftests/sched_ext/Makefile b/tools/testing/selftests/sched_ext/Makefile
index 789037be44c7..5d2dffca0e91 100644
--- a/tools/testing/selftests/sched_ext/Makefile
+++ b/tools/testing/selftests/sched_ext/Makefile
@@ -175,6 +175,7 @@ auto-test-targets :=			\
 	maximal				\
 	maybe_null			\
 	minimal				\
+	non_scx_kfunc_deny		\
 	numa				\
 	allowed_cpus			\
 	peek_dsq			\
diff --git a/tools/testing/selftests/sched_ext/non_scx_kfunc_deny.bpf.c b/tools/testing/selftests/sched_ext/non_scx_kfunc_deny.bpf.c
new file mode 100644
index 000000000000..0d6fcc8e5eb6
--- /dev/null
+++ b/tools/testing/selftests/sched_ext/non_scx_kfunc_deny.bpf.c
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Verify that context-sensitive SCX kfuncs (even "unlocked" ones) are
+ * restricted to only SCX struct_ops programs. Non-SCX struct_ops programs,
+ * such as TCP congestion control programs, should be rejected by the BPF
+ * verifier when attempting to call these kfuncs.
+ *
+ * Copyright (C) 2026 Ching-Chun (Jim) Huang <jserv@ccns.ncku.edu.tw>
+ * Copyright (C) 2026 Cheng-Yang Chou <yphbchou0911@gmail.com>
+ */
+
+#include <scx/common.bpf.h>
+
+SEC("struct_ops/ssthresh")
+__u32 BPF_PROG(tcp_ca_ssthresh, struct sock *sk)
+{
+	/*
+	 * This call should be rejected by the verifier because this is a
+	 * TCP congestion control program (non-SCX struct_ops).
+	 */
+	scx_bpf_kick_cpu(0, 0);
+	return 2;
+}
+
+SEC("struct_ops/cong_avoid")
+void BPF_PROG(tcp_ca_cong_avoid, struct sock *sk, __u32 ack, __u32 acked) {}
+
+SEC("struct_ops/undo_cwnd")
+__u32 BPF_PROG(tcp_ca_undo_cwnd, struct sock *sk) { return 2; }
+
+SEC(".struct_ops")
+struct tcp_congestion_ops tcp_non_scx_ca = {
+	.ssthresh   = (void *)tcp_ca_ssthresh,
+	.cong_avoid = (void *)tcp_ca_cong_avoid,
+	.undo_cwnd  = (void *)tcp_ca_undo_cwnd,
+	.name       = "tcp_kfunc_deny",
+};
+
+char _license[] SEC("license") = "GPL";
diff --git a/tools/testing/selftests/sched_ext/non_scx_kfunc_deny.c b/tools/testing/selftests/sched_ext/non_scx_kfunc_deny.c
new file mode 100644
index 000000000000..1c031575fb87
--- /dev/null
+++ b/tools/testing/selftests/sched_ext/non_scx_kfunc_deny.c
@@ -0,0 +1,47 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Verify that context-sensitive SCX kfuncs (even "unlocked" ones) are
+ * restricted to only SCX struct_ops programs. Non-SCX struct_ops programs,
+ * such as TCP congestion control programs, should be rejected by the BPF
+ * verifier when attempting to call these kfuncs.
+ *
+ * Copyright (C) 2026 Ching-Chun (Jim) Huang <jserv@ccns.ncku.edu.tw>
+ * Copyright (C) 2026 Cheng-Yang Chou <yphbchou0911@gmail.com>
+ */
+
+#include <bpf/bpf.h>
+#include <scx/common.h>
+#include <unistd.h>
+#include <errno.h>
+#include <stdio.h>
+#include "non_scx_kfunc_deny.bpf.skel.h"
+#include "scx_test.h"
+
+static enum scx_test_status run(void *ctx)
+{
+	struct non_scx_kfunc_deny *skel;
+	int err;
+
+	skel = non_scx_kfunc_deny__open();
+	if (!skel) {
+		SCX_ERR("Failed to open skel");
+		return SCX_TEST_FAIL;
+	}
+
+	err = non_scx_kfunc_deny__load(skel);
+	non_scx_kfunc_deny__destroy(skel);
+
+	if (err == 0) {
+		SCX_ERR("non-SCX BPF program loaded when it should have been rejected");
+		return SCX_TEST_FAIL;
+	}
+
+	return SCX_TEST_PASS;
+}
+
+struct scx_test non_scx_kfunc_deny = {
+	.name = "non_scx_kfunc_deny",
+	.description = "Verify that non-SCX struct_ops programs cannot call SCX kfuncs",
+	.run = run,
+};
+REGISTER_SCX_TEST(&non_scx_kfunc_deny)
diff --git a/tools/testing/vma/include/dup.h b/tools/testing/vma/include/dup.h
index b4864aad2db0..9e0dfd3a85b0 100644
--- a/tools/testing/vma/include/dup.h
+++ b/tools/testing/vma/include/dup.h
@@ -1330,7 +1330,7 @@ static inline int __compat_vma_mmap(struct vm_area_desc *desc,
 	/* Update the VMA from the descriptor. */
 	compat_set_vma_from_desc(vma, desc);
 	/* Complete any specified mmap actions. */
-	return mmap_action_complete(vma, &desc->action);
+	return mmap_action_complete(vma, &desc->action, /*is_compat=*/true);
 }
 
 static inline int compat_vma_mmap(struct file *file, struct vm_area_struct *vma)
diff --git a/tools/testing/vma/include/stubs.h b/tools/testing/vma/include/stubs.h
index a30b8bc84955..64164e25658f 100644
--- a/tools/testing/vma/include/stubs.h
+++ b/tools/testing/vma/include/stubs.h
@@ -87,7 +87,8 @@ static inline int mmap_action_prepare(struct vm_area_desc *desc)
 }
 
 static inline int mmap_action_complete(struct vm_area_struct *vma,
-				       struct mmap_action *action)
+				       struct mmap_action *action,
+				       bool is_compat)
 {
 	return 0;
 }
